Release Notes For ModelSim Altera 10.4

• How to Get Support

  ModelSim Altera is supported by Altera Corporation

  • World-Wide-Web Support

    http://www.altera.com/mySupport
    
    

  
  

Index to Release Notes

• Key Information
• Release Announcements in 10.4
• Base Product Specifications in 10.4
• Compatibility Issues with Release 10.4
• General Defects Repaired in 10.4
• User Interface Defects Repaired in 10.4
• SystemVerilog Defects Repaired in 10.4
• VHDL Defects Repaired in 10.4
• SystemC Defects Repaired in 10.4
• Mixed Language Defects Repaired in 10.4
• WLF and VCD logging Defects Repaired in 10.4
• General Enhancements in 10.4
• User Interface Enhancements in 10.4
• SystemVerilog Enhancements in 10.4
• VHDL Enhancements in 10.4
• SystemC Enhancements in 10.4
• Mixed Language Enhancements in 10.4
• Coverage Enhancements in 10.4

Key Information

• The following lists the supported platforms:
  • win32aloem - Windows 7, Windows 8
  • linuxaloem - RedHat Enterprise Linux 5 and 6, SUSE Linux Enterprise Server 10 and 11

Release Announcements in 10.4

• [nodvtid] -
  [10.4] Support for Windows XP and Windows Vista has been discontinued.
  [10.4] Licensing Information

  There is no licensing change between release 10.3 and 10.4.

  However if you are migrating to 10.4 from a release like 10.2 and older, please note the following:

  • Starting 10.3, it uses FLEXnet v11.11.1.1. The vendor daemons and lmgrd that are shipped with this release will be FLEXnet version 11.11.1.1.
  • For floating licenses it will be necessary to verify that the vendor daemon (i.e., mgcld) and the license server (i.e., lmgrd) have FLEXnet versions equal to or greater than 11.11.1.1. If the current FLEXnet version of your vendor daemon and lmgrd are less than 11.11.1.1 then it will be necessary to stop your license server and restart it using the vendor daemon and lmgrd contained in this release.
  • If you use node locked licenses you don't need to do anything.
  
  [10.3b] OVL is upgraded to v2.8.1.
  [10.3b] The VHDL OSVVM (Open Source VHDL Verification Methodology) library, sources and documentation have been updated to version 2014.01. Dependency checks in vopt and vsim will force recompilation of designs that use the osvvm library. If optimization is performed using vopt, the optimizer will automatically generate new optimized design units. Without the optimization step, vsim will detect dependency errors.
  [10.3] Support for RedHat Enterprise Linux (RHEL) 4.0 has been discontinued.
  [10.2] Support for Solaris SPARC and Solaris x86 has been discontinued. All Solaris OS platforms are not supported.
  [10.2] Support for RedHat Enterprise Linux (RHEL) 3.0 and Novell SUSE Linux Enterprise (SLES) 9 has been discontinued.
  [10.1] Support for GCC versions gcc-4.1.2-sunos510/gcc-4.1.2-sunos510x86 has been discontinued.
  [10.0] Support for Solaris 8 and Solaris 9 has been discontinued.
  
  

Base Product Specifications in 10.4

• [nodvtid] -
  [Supported Platforms]
  Linux RHEL 5 x86/x86-64
  Linux RHEL 6 x86/x86-64
  Linux SLES 10 x86/x86-64
  Linux SLES 11 x86/x86-64
  Windows 7 x86/x64
  Windows 8 x86/x64
  
  [Supported GCC Compilers (for SystemC)]
  gcc-4.7.4-linux/gcc-4.7.4-linux_x86_64
  gcc-4.5.0-linux/gcc-4.5.0-linux_x86_64
  gcc-4.3.3-linux/gcc-4.3.3-linux_x86_64
  gcc-4.2.1-mingw32vc9
  
  [OVL (shipped with product)]
  v2.8.1
  
  [VHDL OSVVM (shipped with product)]
  v2014.07
  
  [Licensing]
  FLEXnet v11.11.1.1
  MSL v2013_3
  MGLS v9.10_7.2
  PCLS v9.10.7.2
  
  

Compatibility Issues with Release 10.4

• dvt69696 - (results) One bit Verilog nets displayed in binary radix would incorrectly show the strength prefix (e.g. St1). This has been fixed and the strength prefix is only displayed when the radix is set to "Symbolic."
• [nodvtid] - (results) SystemC integer types (e.g. short, int, long) did not show the radix prefix when the showbase radix qualifier was enabled.
• dvt71982 - (results) Individual 2-state SV struct field values could be shown incorrectly in the Objects window. This has been corrected.
• dvt30276 - (results) When there is no [onbreak] setting in effect, the default [onbreak] behavior is defined by a new variable: $OnBreakDefaultAction. If $OnBreakDefaultAction is not defined, then the effective default will be [resume]. This is a change in prior behavior where the default action was [pause].

• dvt67278 - (source, results) As per LRM requirement now an error will be given to user if the variables written in always_ff process are written by any other process as well.
• dvt64937 - (results) Under the following condition, X transition delay on an input port with SDF INTERCONNECT delays, was incorrect. The SDF file had RETAIN delay values (associated with some IOPATH) that resolved to the same as that of an INTERCONNECT delay and the RETAIN delay was annotated before the INTERCONNECT delay.
• dvt65850 - (results) Fixed a bug where incorrect result was given while reading part of mult-dimensional packed array containing structures. eg arr[i].b[1] for 3 dimensional array.
• dvt65714 - (results) When "+vlog_retain_same2same_on" was specified, conditional specify paths with SDF RETAIN delays did not evaluate correctly.
• dvt68217 - (results) Vsim's "-errorfile" switch facilitated redirection of all non-assert messages (errors, warnings & notes). Therefore, the name "-errorfile" was deemed confusing and has been changed to "-msgfile". The old switch is still recognized for backward compatibility.
• dvt68824 - (results) Calling vpi_get_time function with a VPI handle of wrong type (for example to a package) would cause vsim to crash.
• dvt68554 - (results) The following two issues caused by "-warning error" switch have been fixed. In vsim, Note messages got turned into errors. In vlog and vopt, warnings that were not reported without the switch got reported as Errors.
• dvt68876 - (results) Relative pathnames to bits of VHDL vector signals in $init_signal_spy, are now correctly resolved. Also improved the error handling/reporting of objects that are not found.
• dvt69536 - (results) In the -novopt flow, if the SDF source file associated with a compiled SDF file was changed but the modification time of the source remained older than that of the compiled SDF, then the simulator didn't automatically recompile the SDF.
• dvt70293 - (results) SystemVerilog force statement is simulated incorrectly when calling from DPI.
• dvt35213 - (results) The simulator command line option +notifier_ondetect causes timing check notifier toggle generated X output values to be scheduled with zero delay.
• [nodvtid] - (results) Added vpi_get_str() support for vpiArrayType.

• dvt64565 - (results) Now instances under VHDL generates can be specified as the SDF back-annotation point with -sdfmin/typ/max switches. For example, "-sdfmax /test/gen_buf1_inst(1)/wrap_buf1_inst=test.sdf", where instance "wrap_buf1_inst" is under the VHDL generate "gen_buf1_inst", now annotates successfully. Now VHDL and Verilog generate scopes (e.g. /test/gen_buf1_inst(1) above) are also accepted.
• dvt71619 - (results) On 64 bits, array shift and rotate operations whose second operand ( shift/rotate amount) is INTEGER'LEFT would generate a stack overflow error. This has been fixed and the result when the shift/rotate amount is INTEGER'LEFT on both 64 and 32 bit has been changed to generate the correct value.
• dvt141 - (results) VHDL access variables (variables of an access type) and their related access objects (designated objects of such variables) can now be logged and displayed in various GUI windows. Use the vsim switch -accessobjdebug to enable this feature. See the manuals for more details.

• dvt38061 - (results) HTML report bydu coverage items under function scopes were incorrect.
• dvt69511 - (results) Added -verbose switch in coverage save to show the work in progress by printing the number of written bins in regular interval
• dvt71441 - (results) Alias toggle nodes are now stored in UCDB by default during coverage save from simulation. The -notogglealias option is added in vsim to stop storing the alias toggle nodes in UCDB during the coverage save from simulation

• [nodvtid] - (results) A new vsim option, -mlopt, has been added. When this option is specified, mixed language nets that cross Verilog-VHDL language boundaries are optimized better. The maximum impact will be seen when a large number of highly active nets like clocks cross Verilog-VHDL language boundaries multiple times. In a few corner case scenerios, there may be differences in simulation results. The differences are mainly about initial values on mixed language nets. The most common difference will be VHDL nets that may have an initial value of 'X' instead of 'U'. There are limitations to what is currently supported with -mlopt. Specifically: - The -mlopt option will be ignored when doing power aware simulation. - The -mlopt option will be ignored when doing multi-core (mc2) simulation. - SDF annotation of interconnect and port delays onto mixed-language nets is not supported. Attempting to annotate delays when -mlopt is specified will result in errors. - This option is only supported for VHDL std_logic and std_ulogic based types (including arrays where the elements are of these types), and Verilog logic types. - VHDL type conversions and conversion functions are not allowed on a mixed language net when -mlopt is specified. - This option is ignored if the design has analog components.

• [nodvtid] - (results) By default, vsim will now print command line with original and unexpanded options, i.e. vsim -f args.f. Previous behavior to print command line with expanded option can be obtained using -stats=cmd+verbose option.

• dvt34970 - (source) Questa 10.4 now supports SystemC-2.3 (IEEE 1666-2011 standard) as default SystemC version. Questa 10.4 will also support SystemC-2.2 (IEEE 1666-2005 standard) as optional SystemC version.
  For SystemC-2.3 (IEEE 1666-2011)
  • Platforms supported: linux, linux_x86_64 and win32
  • Compilers supported: gcc-4.7.4, gcc-4.5.0 for linux and linux_x86_64, and gcc-4.2.1 for win32.
  • Header files location: <path to questa install tree>/include/systemc/sc
  • TLM version supported: 2.0.2
  For SystemC-2.2 (IEEE 1666-2005)
  • Platforms supported: linux, linux_x86_64 and win32
  • Compilers supported: gcc-4.5.0, gcc-4.3.3 for linux and linux_x86_64 and gcc-4.2.1 for win32.
  • Header files location: <path to questa install tree>/include/systemc/sc22
  • TLM version supported: 2.0.1
  • Tool options: To enable SystemC-2.2 version, use “-sc22” option with sccom/vopt/vsim, or set “Sc22Mode” modelsim.ini variable. Please see User’s manual for more details.
  Backward compatibility with 10.3x and earlier
  • If design is currently setup with 10.3x and earlier releases and user doesn't want to move to SystemC-2.3 version, then use option “-sc22” with sccom/vopt/vsim or set modelsim.ini variable “Sc22Mode” with 10.4 release to continue to use the existing design setup.
• [nodvtid] - (results) The 6202 warning for using a VPI routine in a SystemC constructor is now a suppressible error.

General Defects Repaired in 10.4

• dvt8015 - An enhancement has been added to detect stack overflow at runtime. The simulator will catch most stack overflow issues by default and report an error message similar to the following:

  # ** Fatal: (vsim-177) A possible stack overflow is detected!! The stack pointer (0xff3fe000) is outside the specified stack limit of 10485760 bytes. The current stack usage is 12587008 bytes starting from stack top at 0xffffd000. The current call stack is the following: 
  # 
  # Function incr1 src/stackoverflow6.sv(9)
  # Function incr3 src/stackoverflow6.sv(31)
  # Function incr2 src/stackoverflow6.sv(21)
  # Function incr1 src/stackoverflow6.sv(11)
  # Function incr3 src/stackoverflow6.sv(31)
  # Function incr2 src/stackoverflow6.sv(21)
  # Function incr1 src/stackoverflow6.sv(11)
  # Function incr3 src/stackoverflow6.sv(31)
  (more stack frames display are omitted)
  # 
  # A total of 100 stack frames are displayed; further frames have been suppressed.
  #    Time: 0 ns  Iteration: 0  Process: /badtop_stackoverflow6/#INITIAL#34 File: src/stackoverflow6.sv
  # Fatal error at src/stackoverflow6.sv line 9
  

  A new vsim switch "-stackcheck" is also available. This provides a more thorough check of stack issues at the cost of performance.
  Root causes of stack overflow issues may include a function/task call with deep recursion, or an automatic function/task using large size formal/local variables, or a combination of the two. It is recommended that the root cause of the issue in the source code be identified and recoded. The error message may already contain the call stack information. If not, please check whether a vsim_stacktrace.vstf is generated, and if available, send it to support for analysis. A quick workaround is to change your shell's stack size limit by setting it to a number bigger than the required size mentioned in the error message. Try using shell command 'limit stacksize ' to increase the stack size.
• dvt68348 - Fixed a simulation crash at quit time triggered by vsim-133 error (Unable to remove directory).
• dvt70157 - Restored vmake's behavior for VHDL design units to better deal with building incrementally and use of vcom's "-f" switch.

User Interface Defects Repaired in 10.4

• dvt65471 - Two preference variables were added to provide control of source window behavior when a source file is modified external to the source window. PrefSource(CheckModifiedFiles) controls if the source window checks for external file modifications. PrefSource(AutoReloadModifiedFiles) will automatically reload a file into a source window if it is modified outside of the source window.
• dvt68030 - When using vsim -batch, setting the Tcl variable SolveArrayResizeMax had no effect. This issue has been resolved.
• dvt68029 - When using vsim -batch, the command line was not printed into the log file as when using -c. This issue has been resolved.
• dvt68028 - The qverilog command does not recognize the simulator option -batch. This issue has been resolved.
• [nodvtid] - Under rare conditions, an attempt to bring up the RMB menu in the source window would cause the GUI to hang. This has been repaired.
• dvt69696 - (results) One bit Verilog nets displayed in binary radix would incorrectly show the strength prefix (e.g. St1). This has been fixed and the strength prefix is only displayed when the radix is set to "Symbolic."
• [nodvtid] - (results) SystemC integer types (e.g. short, int, long) did not show the radix prefix when the showbase radix qualifier was enabled.
• dvt69489 - In the Dataflow Window, pressing the right mouse button on the time bar in the wave area would cause a TCL script error. This has been fixed to correctly bring up the RMB time bar menu.
• dvt38385 - In GUI mode, using the restore command outside of vsim caused uninformative error "can't read "vsimPriv(Server)": no such element in array" and would cause eventual GUI crash.
• dvt69296 - The [find signals -ports] command returns incorrect list of signals in regions with no ports, in some cases. The main issue was SV interfaces without ports would cause the list of signals in the containing region to be returned. The correct list of ports is now returned, or an empty list if no ports are found.
• dvt69259 - In some rare cases the GUI would hang when right-clicking on a signal in the Source Window. Depending on the specific hierarchy of the design an infinite loop would occur when checking conditions to enable/disable the items in the RMB menu.
• dvt70832 - Class object values would display -No Data- and the waveforms would not draw if there were also transactions in the wave window.
• dvt70981 - Questa would run a specified do-file after loading a WLF file if the -view switch was used (e.g. vsim -do file.do -view vsim.wlf), but run the do-file before loading the WLF file if the -view switch was not used (e.g. vsim -do file.do vsim.wlf). This has been resolved to run the do-file following the loading of the WLF file in both cases.
• dvt63858 - Toggling the "Within Cells" mode of the Memory List window while a search filter is in use can cause the display of an incomplete list of memories. This issues has been resolved.
• dvt71982 - (results) Individual 2-state SV struct field values could be shown incorrectly in the Objects window. This has been corrected.
• dvt64155 - Two new radixes have been implemented, sfixed and ufixed (signed fixed and unsigned fixed, respectively.) Values may be displayed using these radixes, for example, [examine -radix ufixed var] might produce the value 1.375. The criteria for displaying an object as sfixed or ufixed is that the type of the object must be an array of std_ulogic elements between 2 and 64 bits long with a descending range. (The set of supported types may increase in the future.) The binary point for the value is implicitly located between the 0th and -1st elements of the array. The index range for the type need not include 0 or -1, for example (-4 downto -8) in which case the value will be extended for conversion, as appropriate. If the type does not meet these criteria the value will be displayed as decimal or unsigned, respectively. The radix command, global radix dialog and wave window radix menus support these radixes.
• dvt71287 - The "Fixed Point Radix" dialog box was missing the radix "decimal" as a possible base type. This has been corrected. Decimal is now the default base selection in the dialog.

SystemVerilog Defects Repaired in 10.4

• dvt36474 - VPI access of bit-selects and part-selects of packed arrays caused a memory leak (that eventually caused 32-bit platforms to run out of memory) and a slow down in vsim.
• dvt64937 - (results) Under the following condition, X transition delay on an input port with SDF INTERCONNECT delays, was incorrect. The SDF file had RETAIN delay values (associated with some IOPATH) that resolved to the same as that of an INTERCONNECT delay and the RETAIN delay was annotated before the INTERCONNECT delay.
• dvt65850 - (results) Fixed a bug where incorrect result was given while reading part of mult-dimensional packed array containing structures. eg arr[i].b[1] for 3 dimensional array.
• dvt66363 - Hierarchical references connected with the System Verilog "alias" construct resulted in an elaboration crash in some cases.
• dvt66935 - A signed index expression narrower than 32 bits wide was treated as unsigned in some unusual cases.
• dvt24183 - In some cases constant functions returned incorrect results (typically a zero) during elaboration if the function return type contained a parameter.
• [nodvtid] - vlog accepts more types of macros which themselves define macros.
• dvt65714 - (results) When "+vlog_retain_same2same_on" was specified, conditional specify paths with SDF RETAIN delays did not evaluate correctly.
• dvt68217 - (results) Vsim's "-errorfile" switch facilitated redirection of all non-assert messages (errors, warnings & notes). Therefore, the name "-errorfile" was deemed confusing and has been changed to "-msgfile". The old switch is still recognized for backward compatibility.
• dvt68824 - (results) Calling vpi_get_time function with a VPI handle of wrong type (for example to a package) would cause vsim to crash.
• dvt68554 - (results) The following two issues caused by "-warning error" switch have been fixed. In vsim, Note messages got turned into errors. In vlog and vopt, warnings that were not reported without the switch got reported as Errors.
• dvt68876 - (results) Relative pathnames to bits of VHDL vector signals in $init_signal_spy, are now correctly resolved. Also improved the error handling/reporting of objects that are not found.
• dvt68919 - vlog should not produce an error when assigning a parameterized virtual with a type parameter actual declared in a package to an equivalent parameterized virtual with a type parameter actual declared in a module.
• dvt63879 - Now a suppressible error will result when a variable is used for inout port inside modport.
• dvt67524 - Vopt would sometimes crash with very large designs containing SystemVerilog packages.
• dvt67278 - (source, results) As per LRM requirement now an error will be given to user if the variables written in always_ff process are written by any other process as well.
• dvt68778 - Vsim would sometimes generate incorrect errors like this for code in SystemVerilog packages:
  # ** Error: (vsim-3043) test.sv(-2): Unresolved reference to 'a'.
• dvt68960 - Fixed an issue in SV bind doesn't work, when bind target lies within an generate scope which can't be elaborated during vopt.
• dvt69630 - Fix a bug in DPI interface svPutUserData() where the previous user data can not be overwritten by the new data for the same scope/key input combination.
• dvt31751 - Some message used to say "(14)", now it says "(sccom-14)".
• dvt67972 - Using an increment or decrement operator when assigning to a character in a SystemVerilog 'string' type would increment or decrement the index by 2 instead of 1.
• dvt22670 - In some cases with inline randomization constraints, vlog incorrectly reported an error like:
  ** Error: pkg.sv(39): Can't use a typedef ('my_enum_t') here.
  with the usage of a valid type name.
• dvt69899 - A unique priority case statement having bitwise infix expression as selection choice may sometimes results in a vopt crash. This is now fixed
• dvt66228 - An associative array with Integer key may not be able to search the elements in some cases, when the key is close to negative limit of integer. This is now fixed.
• dvt34518 - In some cases, where a parameter is defined as a dynamic array and later used for defining other parameters, may result in an Integer Overflow Error. This is now fixed
• dvt69536 - (results) In the -novopt flow, if the SDF source file associated with a compiled SDF file was changed but the modification time of the source remained older than that of the compiled SDF, then the simulator didn't automatically recompile the SDF.
• dvt70293 - (results) SystemVerilog force statement is simulated incorrectly when calling from DPI.
• dvt71152 - Bit-selects and part-selects of 2-state variables in module input port connections produced incorrect results in some cases.
• dvt70882 - A bit-select of a hierarchical reference connected to a module input port produced incorrect results in some cases if the bit-select index also contained a hierarchical reference.
• [nodvtid] - Array manipluation functions like "arr.find_first_index(x) with ...condition..." would incorrectly report the error "No field named 'x'" in some cases.

VHDL Defects Repaired in 10.4

• dvt64721 - A signal external name appearing in a PROCESS statement, and whose subtype indication is not locally static, could result in a simulator crash when the design was loaded.
• dvt64737 - A configuration declaration that has the same name as the ENTITY that it is configuring cannot be compiled into the same library as that ENTITY. Previously this was a compiler warning resulting in an unloadable design, but this has been changed into a compiler error.
• dvt64565 - (results) Now instances under VHDL generates can be specified as the SDF back-annotation point with -sdfmin/typ/max switches. For example, "-sdfmax /test/gen_buf1_inst(1)/wrap_buf1_inst=test.sdf", where instance "wrap_buf1_inst" is under the VHDL generate "gen_buf1_inst", now annotates successfully. Now VHDL and Verilog generate scopes (e.g. /test/gen_buf1_inst(1) above) are also accepted.
• dvt66430 - A defect in the compiler prevented a resolution function name appearing in a subtype indication from being an operator symbol, even though sometimes this is legal. Further, a predefined function used as a resolution function would result in a simulator crash. Both of these bugs have been fixed.
• dvt67632 - Individual subelement association would sometimes not do the check that all subelements were associated when the array subtype was locally static but had an index whose value was not known in the compiler.
• dvt68122 - If generate evaluation takes an excessive amount of time in the optimizer vopt.
• dvt68058 - A signal assignment statement in a PROCEDURE that assigns to a class Signal, mode Out or Inout formal of that procedure, when the subtype of the formal is a partially constrained record or array type, could sometimes cause a simulator crash.
• dvt67530 - Out-of-date messages generated by vcom and vopt have been changed to report dependent design units that need to be recompiled. This also fixes a crash that could occur in vopt if an entity needed for a default binding needed to be recompiled.
• dvt70898 - Use of the function rising_edge and falling_edge could, in some case, trigger an internal error
• dvt67672 - An array aggregate with an OTHERS choice in an O'SUBTYPE or A'ELEMENT context was erroneously being flagged as an Error. This has been fixed.
• dvt71619 - (results) On 64 bits, array shift and rotate operations whose second operand ( shift/rotate amount) is INTEGER'LEFT would generate a stack overflow error. This has been fixed and the result when the shift/rotate amount is INTEGER'LEFT on both 64 and 32 bit has been changed to generate the correct value.
• dvt72143 - If an uninstantiated package contains signal declarations, and an instance of the package is associated with an interface package in an entity, package, or subprogram instantiation, accesses to the signals could lead to simulator error messages of the form:

  # ** INTERNAL ERROR: pkgref: export lookup failed for package #8[7]
  

• [nodvtid] - An object of a composite type that has a subelement of some null-range scalar subtype, when declared with no default expression (class SIGNAL object) or initial value expression (class VARIABLE object), would not cause an error as it should. Such object declarations are illegal because no value (default/initial or otherwise) can be compatible with such a composite (sub)type.
• [nodvtid] - The predefined package ENV was introduced in VHDL 2008, to be in library STD. While this package is available for VHDL versions other than VHDL 2008, using this package will produce a warning message unless the VHDL 2008 language version is in effect. It is possible to suppress or otherwise change the message severity level.

SystemC Defects Repaired in 10.4

• dvt65715 - Fixed issue in Cdebug where in a 'step' command would incorrectly execute auto-lib-step-out feature and causes simulation to continue instead of stepping into the code.
• dvt65959 - Fixed Cdebug to pick the correct gdb when the CppPath modelsim.ini variable is set.
• dvt66013 - Fixed sccom-95 error message to print correct name of the gcc compiler download file as per the product variant.
• dvt65959 - gdb_path and gdb_custom variables will no longer be read from or written into the .modelsim preferences file.
• dvt67500 - Fixed sccom compilation failure when a full path to the source file was specified from a read-only directory

Mixed Language Defects Repaired in 10.4

• [nodvtid] - Hierarchical references from Verilog to fields of a VHDL record signal could cause the tool to fail.

WLF and VCD logging Defects Repaired in 10.4

• dvt67909 - Logging arrays of System Verilog named events could result in error messages such as: WLF ERROR: Illegal array element type in log_vlog_mem_elmt_event: 21
• dvt70390 - WLF files written in a product version prior to 10.3c could sometimes not be read properly in version 10.3c if they contained a VHDL access type object or SystemC pointer type object.

General Enhancements in 10.4

• [nodvtid] - -stats option has been enhanced to have the following syntax:

      -stats[=[+-]< features_and_modes >]
  

  
  Feature options are:
  • time: Display Start, End, and Elapsed times of the executable
  • cmd: Echo the command line
  • msg: Display error/warning summary at end of execution
  • perf: Display performance stats: CPU time, Wall time, and Memory use
  • all: All stats features are enabled
  • none: All stats features/modes are disabled
  
  Mode options are:
  • verbose: Display verbose information when available
  • list: Display the stats in a Tcl list style
  
  Following commands support this option:
  • vlog, vcom, sccom, mc2com, vopt, vcover, vencrypt, vsim
  
  'Stats' modelsim.ini variable is equivalent for this option and has the default value of time,cmd,msg:

      [vlog/vcom/vopt/sccom/vsim]
      Stats = time,cmd,msg
  

  
  Few functionality notes:
  • time,cmd,msg features are default ON for all the above commands.
  • -stats without any argument is equivalent to time,cmd,msg.
  • Command line option further add/remove features to/from the default feature settings.
  • Multiple -stats options are allowed in the command line, but only the last specified option will take effect.
  
  Following options are obsolete and replaced by -stats option:
  • -nostats; replaced by -stats=none
  • -printstats; replaced by -stats=perf
  • -printsimstatslist; replaced by -stats=perf,list
• [nodvtid] - vmake will now produce more meaningful makefiles for flat libraries. Makefile support for flat libraries is necessarily limited, due to the lack of per-target file objects. But the resulting makefile will trigger a build of all design units should any source file for any design unit be newer than the library. Optimized design units in flat libraries are also supported, with somewhat more precise dependency tracking.
• [nodvtid] - simstats and simstatslist commands have updated syntax and output format.
  Syntax:

     simstats[list] [voptmemory | vopttime | voptcpu | elabmemory | elabtime | elabcpu | simmemory | simtime | simcpu | logtime | logcpu | tclcmdtime | tclcmdcpu | totaltime | totalcpu] 
  

  
  Please refer to Command Reference Manual for more details.
• [nodvtid] - Feature-specific mode specification has been added to -stats syntax. Users can now specify modes globally for all features using comma-separated specification, like -stats=time,perf,list,verbose, or for a specific feature using +/- specification associated with the feature, like -stats=cmd+verbose,perf+list. Both global and feature-specific mode specifications cannot be used together.
• [nodvtid] - (results) By default, vsim will now print command line with original and unexpanded options, i.e. vsim -f args.f. Previous behavior to print command line with expanded option can be obtained using -stats=cmd+verbose option.
• dvt69558 - Added a new vsim switch to enable the support of checkpoint and restore of a foreign C++ library.

    -allowcheckpointcpp 1|0  Turn on/off the support for checkpointing foreign C++ libraries.
                             Must be used in the vsim session where a checkpoint is created.
  

• dvt68871 - Added support in vlog, vcom and vopt to automatically create missing work libraries. Vlog/vcom/vopt command-line option '-nocreatelib', or modelsim.ini variable 'CreateLib', may be used to stop automatic creation of missing work libraries and revert back to the old (10.3x and earlier) behavior.
• dvt30212 - The modelsim.ini file now contains a release version number as a comment. There is no behavioral change to the simulator or any other tools.

User Interface Enhancements in 10.4

• dvt30276 - (results) When there is no [onbreak] setting in effect, the default [onbreak] behavior is defined by a new variable: $OnBreakDefaultAction. If $OnBreakDefaultAction is not defined, then the effective default will be [resume]. This is a change in prior behavior where the default action was [pause].
• [nodvtid] - The vsim -do option has been enhanced to allow for multiple occurances of -do on the command line. The commands provided will be joined together in the order specified. For example, the command: vsim -do "force clk 0 0, 1 10 -r 20" top -wlf top.wlf -do "testfile.do" -do "run -all" will turn into a script: "force clk 0 0, 1 10 -r 20; do testfile.do; run -all"

SystemVerilog Enhancements in 10.4

• [nodvtid] - The vlog command's switch -svext now supports an option named "udm0" which directs the vlog compiler to expand any undefined macro with the text " 1'b0 ".
• dvt63875 - $stacktrace([level]) is now taking an optional argument 'level'. When it is not specified or its value is not a positive number, the maximum number of stack frames being displayed is determined by the new modelsim.ini variable, [vsim] StackTraceDepth, which has a default value 100.
• dvt35213 - (results) The simulator command line option +notifier_ondetect causes timing check notifier toggle generated X output values to be scheduled with zero delay.
• [nodvtid] - The -svext option evis supports expansion of environment variables within `include path names. For example, if MYPATH exists in the environment then it will be expanded in the following: `include "$MYPATH/inc.svh"
• [nodvtid] - (results) Added vpi_get_str() support for vpiArrayType.
• [nodvtid] - The reserved keywords 'config' and 'instance' may be used outside of unit and configuration scopes when the -permissive vlog switch is used.
• [nodvtid] - The vlog command switch -svext supports an option named 'vmctor' to allow virtual method calls in class constructor. The default is to treat them as non-virtual during construction.
• [nodvtid] - The vlog command switch -svext supports an option named 'evdactor' to enable early variable declaration assignments during class construction. The default behavior is to perform all superclass initialization before initializing any fields in a subclass.
• dvt68142 - Vopt and vsim now accept package names on the command line and treat them as a top-level design unit.
• [nodvtid] - The vlog option '-printinfilenames' now can write out to a file specified via '-printinfilenames='. vlog will overwrite existing output from this option.

VHDL Enhancements in 10.4

• dvt67518 - An informational warning message has been added for the situation when compiling an array aggregate with language version 2008, when the aggregate appears in a context where an OTHERS choice would not be legal, when the aggregate contains no named element association whose expression is of the aggregate type, and when a range choice has a direction different from the direction of the index subtype of the base array type. This warning is a reminder that the direction of the aggregate is determined by the direction of the index subtype of the array type, not by the direction of any range choice appearing in a named element association (all of which are of the element type).
• dvt68124 - If the simulator is invoked with the "-noappendclose" switch, or if the modelsim.ini file sets variable AppendClose to 0, the simulator will not immediately close files opened in APPEND mode. Subsequent calls to file_open in APPEND mode will therefore not require operating system interaction, resulting in faster performance. If customer designs rely on files to be closed and completely written to disk following calls to file_close because they perform operations on the files outside the simulation, this enhancement could adversely impact those operations; consequently, in these situations, use of the switch or modelsim.ini variable setting is not recommended.
• dvt141 - (results) VHDL access variables (variables of an access type) and their related access objects (designated objects of such variables) can now be logged and displayed in various GUI windows. Use the vsim switch -accessobjdebug to enable this feature. See the manuals for more details.

SystemC Enhancements in 10.4

• [nodvtid] - (results) The 6202 warning for using a VPI routine in a SystemC constructor is now a suppressible error.
• [nodvtid] - When unsupported g++ compiler is used, sccom generates predefined macro file. sccom option "-predefmacrofile <filename>" can be used to specify this file.
• dvt67502 - Added -gblso command option to vopt and the companion modelsim.ini variable 'GlobalSharedObjectList'

  -gblso       Load the specified shared library with global symbol visibility.
  

  This option would be required if the SystemC top is elaborated in vopt and is depending on the symbols from a common library being loaded with vsim -gblso switch.
• dvt34970 - (source) Questa 10.4 now supports SystemC-2.3 (IEEE 1666-2011 standard) as default SystemC version. Questa 10.4 will also support SystemC-2.2 (IEEE 1666-2005 standard) as optional SystemC version.
  For SystemC-2.3 (IEEE 1666-2011)
  • Platforms supported: linux, linux_x86_64 and win32
  • Compilers supported: gcc-4.7.4, gcc-4.5.0 for linux and linux_x86_64, and gcc-4.2.1 for win32.
  • Header files location: <path to questa install tree>/include/systemc/sc
  • TLM version supported: 2.0.2
  For SystemC-2.2 (IEEE 1666-2005)
  • Platforms supported: linux, linux_x86_64 and win32
  • Compilers supported: gcc-4.5.0, gcc-4.3.3 for linux and linux_x86_64 and gcc-4.2.1 for win32.
  • Header files location: <path to questa install tree>/include/systemc/sc22
  • TLM version supported: 2.0.1
  • Tool options: To enable SystemC-2.2 version, use “-sc22” option with sccom/vopt/vsim, or set “Sc22Mode” modelsim.ini variable. Please see User’s manual for more details.
  Backward compatibility with 10.3x and earlier
  • If design is currently setup with 10.3x and earlier releases and user doesn't want to move to SystemC-2.3 version, then use option “-sc22” with sccom/vopt/vsim or set modelsim.ini variable “Sc22Mode” with 10.4 release to continue to use the existing design setup.

Mixed Language Enhancements in 10.4

• [nodvtid] - (results) A new vsim option, -mlopt, has been added. When this option is specified, mixed language nets that cross Verilog-VHDL language boundaries are optimized better. The maximum impact will be seen when a large number of highly active nets like clocks cross Verilog-VHDL language boundaries multiple times. In a few corner case scenerios, there may be differences in simulation results. The differences are mainly about initial values on mixed language nets. The most common difference will be VHDL nets that may have an initial value of 'X' instead of 'U'. There are limitations to what is currently supported with -mlopt. Specifically: - The -mlopt option will be ignored when doing power aware simulation. - The -mlopt option will be ignored when doing multi-core (mc2) simulation. - SDF annotation of interconnect and port delays onto mixed-language nets is not supported. Attempting to annotate delays when -mlopt is specified will result in errors. - This option is only supported for VHDL std_logic and std_ulogic based types (including arrays where the elements are of these types), and Verilog logic types. - VHDL type conversions and conversion functions are not allowed on a mixed language net when -mlopt is specified. - This option is ignored if the design has analog components.

Coverage Enhancements in 10.4

• dvt19109 - The functional coverage excluded items will be shown in text reports, when the -showexcluded option is used.
• dvt70747 - A new coverage use model is added for reduced data storage and better merge performance. The current use model remains unchanged and acts as default. Here is the list of items added for the new use model.
  
  • The user needs to invoke vsim with -coverstore option to specify a directory path where the simulator will dump coverage data at the end of the simulation. The user doesn't need to save the coverage data explicitly. All the simulation runs in a regression should use the same coverstore directory path and their design hierarchy needs to be the same for this new use model.
  • The user needs to invoke vsim with -testname option along with the -coverstore option to specify the name of the running test.
  • After the coverage data is accumulated in the coverstore area from all the simulation runs, the user can merge the coverage data and create a self-contained UCDB file for further analysis. The user simply needs to specify the coverstore directory path as an input to the vcover merge. No other option is required.
  • The user can also dump the ouput of a merge to a coverstore directory instead of creating the output UCDB file by using the -outputstore option to specify the output directory path. This is useful when the user merges the outputs of lower level merges in a hierarchical merge.
  • The coverage data by default is stored using single-bit counters for code coverage items (statements, branches, conditions, expressions, fsms, toggles), and multi-bit counters for functional coverage items (covergroups, cover directives, assertions). That means we store 1 for a code coverage bin whose count is greater than 0. The user can specify which coverage types to be stored using single-bit counters and which coverage types to be stored using multi-bit counters. The -multicount[=-a|b|c|-d|e|f|-g|s|t] option is added for that. The '-' is preceded to functional coverage types whose defaults are multi-bit, so the user can turn those coverage types to single-bit by using it. For example, -multicount=f-gt will turn the fsm and toggle coverage types to multi-bit and covergroup coverage type to single bit, keeping the other coverage types as unchanged.
• dvt69511 - (results) Added -verbose switch in coverage save to show the work in progress by printing the number of written bins in regular interval
• dvt71441 - (results) Alias toggle nodes are now stored in UCDB by default during coverage save from simulation. The -notogglealias option is added in vsim to stop storing the alias toggle nodes in UCDB during the coverage save from simulation