# log 2

The workflow in lab 2 was to :
	* set a process technology
	* elaborate the VHDL design to produce RTL code
	* synthesize the RTL code using the technology library to produce the actual hardware description
	* iteratively define timing constraints, re-synthesize and see how the additional constraints have caused the compiler to change the hardware with respect to worst-case delay, critical path and area, as well as the resulting timing slack.
	* Use a functional synthesized netlist to re-simulate the design and acertain whether the original functional verification still holds.
	* extract/generate timing information from the sythesized netlist using Synopsys PrimeTime.
	* Elaborate the synthesized netlist, the technology file as well as the original VHDL testbench along with the timing information.
	* simulate the resulting design to confirm that the timing of the netlist satisfies the timing constraints used to generate the netlist.
	
   
   
A technology file, a library describing a certain process technology (in this case ST Microelectronics 1.2V 65nm) was linked to the RTL compiler.

This was then used during elaboration to produce RTL code from the original VHDL source code (excluding the testbench, which is non-synthesizable). The resulting RTL code is composed of "virtual" or symbolic gates which can be mapped onto a process technology during the next phase. Several errors occurred during the elaboration, warning of various non-synthesizable elements of the source code, such as signal intialization, which can be safely ignored.

The RTL code was then sythesized, mapping the RTL code to the process technology, using the minimum level of optimization so as to not change the structure of the design. This was confirmed by checking a gate level diagram, which followed the same modular hierarchy as the source code.

For this unconstrained synthesis the worst-case delay was 4880ps with a critical path through the carry-chain and flag generation blocks in the RCA. The area was found to be 4242 a.u. (area units).

A clock signal of period 2092ps was then defined directly in the compiler and the design resynthesized. The result of this is that the compiler attempts to optimize the design in order to reach zero or positive timing slack. The synthesis was not initially successful but after increasing the optimization effort to "medium", it was able to meet this constraint. The critical path did not change substantially, though the associated gates where clearly changed to simple compound structures, often using NAND gates, rather than the more complex gates of the unoptimized synthesis. The area of the design increased marginally to 4484 a.u.

Next, the timing constraint was set to 1000ps, which could not be fulfilled. The critical path did not seem to change but the associated gates were seemingly changed to even simpler structures albeit with higher drive strengths. The area increased substantially, resulting in 5240 a.u.

As a side note: an experiment was performed to determine the highest achievable clock frequency using various optimization settings such as high effort and heirarchy flattening, resulting in a 1.53GHz.

A verilog netlist was then extracted from the fastest synthesis that fulfilled the timing constraints, which was then used in place of the original source code files to re-simulate the design using the original testbench and perform a new functional verification.

The Synopsys PrimeTime tool was then used to extract timing information from the netlist and output an SDF (Standard Delay Format) file. The netlist, technology file and testbench were then re-compiled and elaborated using this SDF file (once converted to an intermediate format that Incisive can read). The re-elaborated file could then be simulated using the same testbench and test vectors as in the previous lab, though now verifiying static and dynamic properties of the circuit. To verify that the process was successful, the design was simulated with the same clock frequency as the one used to generate the netlist, resulting in no errors. Increasing the frequency started to result in timing violations.