* ALU description and testbench design

1. Description of how the TB was constructed. ie, which test vectors were used, asserts, processes for input and output vectors, how the testbench should terminate.
2. How clock and reset are generated.
3. 

* Verification of ALUs

1. Functional correctness.
2. Test against reference case of proven test vectors.
3. NCSIM logic simulation tool -> Incisive Enterprise Simulator (IES) (can also be done in questasim)
4. 2 cycle delay between input and output.
5. Compilation of ALU in hierarchical order using ncvhdl. -> elaboration using ncelab -> simulation using ncsim
6. Verification for RCA and SKL success! (using both sets of test vectors?)
7. Interpretation of test? -> combinational ALU with zero latency (no timing constraints), pipelining must be definined in testbench.
8. Debugging using assert->report->severity to output useful information (current vector, counter etc...)