echo on;
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%                              Example 3.3                                %
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%                                                                         %
%                      R-2R Ladder Voltage-mode                           %
%                                                                         %
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
echo off;

clear all;
n=8;                                    % 8-bit DAC
errandom=0.6/2^n;
errorgradlad=0.5/2^n;
grad=[1:n];
Vref=256;

%-------------------------------------------------------------------------%
%                                                                         %
%                   Resistances with linear gradient                      %
%                                                                         %
%-------------------------------------------------------------------------%

Ra=2*ones(1,n)+errandom*random('normal',0,1,1,n)+(grad-1)*errorgradlad
Rr=ones(1,n)+errandom*random('normal',0,1,1,n)
Rt=2;

%-------------------------------------------------------------------------%
%                                                                         %
%                Resistances at the left side of node i                   %
%                                                                         %
%-------------------------------------------------------------------------%

RL=ones(1,n);
RL(1)=Rt;
for i=2:n,
    rpar=Ra(i-1)*RL(i-1)/(Ra(i-1)+RL(i-1));
    RL(i)=rpar+Rr(i-1);
end
RL
%-------------------------------------------------------------------------%
%                                                                         %
%                Resistances at the right side of node i                  %
%                                                                         %
%-------------------------------------------------------------------------%

RR=ones(1,n);
RR(n-1)=Rr(n-1)+Ra(n);
for i=2:n-1,
    k=n-i;
    rpar=RR(k+1)*Ra(k+1)/(RR(k+1)+Ra(k+1));
    RR(k)=rpar+Rr(k);
end
RR(n)=inf;
RR
%-------------------------------------------------------------------------%
%                                                                         %
%       Voltage on the node i due to just the bit i set equal to 1        %
%       and current flowing in the right direction                        %
%                                                                         %
%-------------------------------------------------------------------------%

for i=1:n,
    Rpar=RR(i)*RL(i)/(RR(i)+RL(i));
    if i==n
        Rpar=RL(n);
    end
    Vnode(i)=Vref*Rpar/(Rpar+Ra(i));
    Iright(i)=Vnode(i)/RR(i);
end

%-------------------------------------------------------------------------%
%                                                                         %
%           Output voltage generated by the i-th bit set equal to 1       %
%                                                                         %
%-------------------------------------------------------------------------%

for k=1:n-1;
    IR=Iright(k);
for i=1:n-1,
    if i<=k
        IR=IR;
    else
        IR=IR*Ra(i)/(Ra(i)+RR(i));
    end
    Vout(k)=IR*Ra(n);
end
end
Vout(n)= Vnode(n)

%-------------------------------------------------------------------------%
%                                                                         %
%             Output voltage for a given decimal input xin                %
%                                                                         %
%-------------------------------------------------------------------------%

for k=1:2^n-1;
    xin=k;                          %ramp at the input
    xbin=dec2bin(xin,n);
VD=0;
for i=1:n,
    VD=VD+bin2dec(xbin(n+1-i))*Vout(i);
end
VDAC(k)=VD;                         %output voltage
Vid(k)=xin/2^n*Vref;                %ideal response
err(k)=(VDAC(k)-Vid(k))/Vref*2^n;   % INL
end

%--------------------------------Graphics---------------------------------%
%                                                                         %
%     figure(1) --> Output Voltage                                        %
%     figure(2) --> Figure 3.19 page 101                                  %
%     figure(3) --> Figure 3.20 page 101                                  %
%                                                                         %
%-------------------------------------------------------------------------%

figure(1);
clf;
plot(VDAC,'r');
grid on;
title('Output signal')
xlabel('bin')
ylabel('Out')
xlim([0 2^n-1]);

figure(2);
clf;
subplot(2,1,1);
plot(grad,Ra,'rs-');
xlabel('Arm Number');
ylabel('value[\Omega]');
title('Arm Resistors Values');
grid on;
subplot(2,1,2);
plot(grad,Rr,'bs-');
xlabel('Riser Number');
ylabel('value[\Omega]');
title('Riser Resistors Values');
grid on;

figure(3);
clf;
plot(err,'r');
grid on;
title('Integral nonlinearity')
b=zeros(1,length(err));
for i=2:1:length(err)
    b(i-1)=abs(err(i)-err(i-1));
end
xlabel('bin')
ylabel('INL')
text(150,max(err)/2,sprintf(...
    '\\bfmaximum INL= %3.3f LSB\nerr-random=%3.5f\nerr-grad-lin=%3.5f',...
    max(b),errandom,errorgradlad),'Fontsize',12);

   
