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\section{Sequencing 1  }
\textbf{a)}\newline
\textit{Sequencing overhead} is delay caused by sequencing elements eg. flip-flops. In this case there are two sources of delay: the setup time t\tss{setup} and clk-to-Q propagation time (ie. worst case delay) t\tss{pcq}. \[ \text{\textit{seq.overhead}} = t\tss{setup}+t\tss{pcq} = 115ps \]

\bigbreak\noindent\textbf{b)}\newline
The \textit{propagation delay} of the combinational logic must be short enough to allow enough time for the sequencing overhead within a single clock cycle \[ t\tss{pd} \leq T_C - \text{\textit{seq.overhead}} = 500ps - 115ps = 385ps \]

\bigbreak\noindent\textbf{c)}\newline

The logic \textit{contamination delay} is the best case delay and hence by definition \(t\tss{cd} \leq t\tss{pd}\). However, in order to avoid a \textit{hold violation} on the receiving flip-flop, $t\tss{cd} \geq t\tss{hold}-t\tss{ccq}$. The range of t\tss{cd} allowed is therefore \[ -5ps = t\tss{hold}-t\tss{ccq} \leq t\tss{cd} \leq t\tss{pd} = 385ps \] 
Clearly, since t\tss{cd} can not be negative, it is impossible for a hold violation to occur!

\bigbreak\noindent\textbf{d)}\newline
With a clock skew \( |t\tss{skew}|\leq50ps\) between any two sequencing elements in the system, the \textit{sequencing overhead} must take this into account
\[ \text{\textit{seq.overhead}} = t\tss{setup}+t\tss{pcq}+t\tss{skew\tss{max}} = 165ps \]
The logic propagation and contamination delays then become even further constrained. Clock skew must also be assumed to go in both directions and so the possibility of a hold violation must now be reconsidered \[ t\tss{cd} \geq t\tss{hold} - t\tss{ccq} + t\tss{skew} = 45ps \] 
The range to which t\tss{cd} is constrained is thus \[45ps = t\tss{hold} - t\tss{ccq} + t\tss{skew} \leq t\tss{cd} \leq t\tss{pd} \leq 335ps \] 

\section{Sequencing 2}
\textbf{a)}\newline
The longest (critical) path through the circuit is through all three XOR gates. The shortest clock period that allows for the worst-case delay is therefore \[ T_C \geq t\tss{setup} + t\tss{pcq} + 3\cdot t\tss{pd} = 430ps \]
which gives a maximum operating frequency of \[ f_C\tss{max} =  \SI{2.326}{\giga\hertz}\]

\bigbreak\noindent\textbf{b)}\newline
If the circuit operates at 2GHz then the clock skew that it can tolerate can be expressed as \[ t\tss{skew} \leq T_C -(t\tss{setup}+t\tss{pcq}+3\cdot t\tss{pd}) = 70ps \]
which is the time remaining per clock cycle after all the signals have propagated and stabilised.

\bigbreak\noindent\textbf{c)}\newline
The maximum clock skew that the circuit can tolerate before it runs the risk of causing a \textit{hold violation} is the delay of the \textit{shortest} path through the circuit offset by the \textit{hold time} of the receiving flip-flop. The shortest path passes through one XOR gate in this case, giving an expression for the clock-skew as follows
\[ t\tss{skew} \leq (t\tss{cd}+t\tss{ccq})-t\tss{hold} = 85ps\]

\clearpage
\bigbreak\noindent\textbf{d)}\newline
Let the original circuit have inputs \textit{a, b, c} and \textit{d} and output \textit{y}. The logical function of the circuit is then \( y=(((a \oplus b) \oplus c) \oplus d)\).
Due to the \textit{associative} property of the XOR function, the inputs may be grouped in any way. Therefore, with three XOR gates, one could arrange them as \( y=((a \oplus b) \oplus (c\oplus d)) \), reducing the critical path by one gate.

The maximum clock frequency without clock skew is now \[ f_C\tss{max} = (t\tss{setup} + t\tss{pcq} + 2\cdot t\tss{pd})^{-1} = \SI{3.030}{\giga\hertz} \]
Since the shortest path has been increased by one gate, increasing the effective contamination delay of the circuit, the circuit should tolerate a larger clock skew before a hold violation occurs
\[ t\tss{skew} \leq (2 \cdot t\tss{cd} +  t\tss{ccq}) - t\tss{hold} = 140ps \]
and indeed the tolerable clock skew has been increased by 55ps!

\section{Metastability}
\bigbreak\noindent\textbf{a)}\newline
From figures 9 to 14 in \cite{6513714}, two extreme values can be found for both (the measured values of) T\tss{W} and $\tau$ at V\tss{DD}=1.25V, each at the extreme ends of the measured temperature range. 

In order to estimate the \textit{mean time between failures} (MTBF) with a \textit{data rate} F\tss{D} = 200MHz, a \textit{system clock} frequency F\tss{C} = 5GHz, and a metastability \textit{resolution time} S = T\tss{C} ie. one clock cycle, the following equation can be used
\[ \ttt{MTBF} = \frac{e^{S/\tau}}{T_w F_C F_D} \]
The resulting MTBF and values used for each temperature extreme is shown in table \ref{tab:MTBF}.

\begin{table}[h]
\centering
\caption{MTBF, T\tss{w},  $\tau$ at V\tss{DD}=1.25 vs. temperature [\si{\celsius}] }
\begin{tabular}{|l|l|l|l|} 
\toprule
Temperature [\si{\celsius}] & T\tss{w} [\si{\pico\second}] & $\tau$ [\si{\pico\second}]  & MTBF [\si{\micro\second}] \\ 
\hline
-20         & 4    & 65       & 5.4                 \\
100         & 25   & 45          & 3.4              \\
\bottomrule
\end{tabular}
\label{tab:MTBF}
\end{table}

It is clear that the MTBF will vary \( \SI{3.4}{\micro\second} \leq MTBF \leq \SI{5.4}{\micro\second} \) depending on the operating temperature.

\bigbreak\noindent\textbf{b)}\newline
It stands to reason that a system with 4000 flip-flops will be 4000 times as likely to fail due to metastability. If we then have 20 sets of flip-flops, the worst-case MTBF can be estimated at
\[ \ttt{MTBF} = \frac{1}{20 \cdot 4000}\cdot \frac{e^{S/\tau}}{T_w F_C F_D} = 52.5ps \]

\bigbreak\noindent\textbf{c)}\newline
In order to compute the \textit{resolution time} S for a certain minimum MTBF, the previous equations can be rewritten as follows 
\begin{equation*}
    S \geq  \tau \cdot  \ln(\text{MTBF} \cdot T_W F_C F_D)
\end{equation*}
For a failure rate of at most once per 10 years, assuming constant worst-case conditions, as well as f\tss{C} = 100MHz and F\tss{D} = 10MHz \[ S \geq 1.34 ns \] yields the results in table \ref{tab:resolution}.
\begin{table}[h]
\centering
\caption{Resolution time S, T\tss{w} and $\tau$ at V\tss{DD}=1.25 vs. temperature [\si{\celsius}] }
\begin{tabular}{|l|l|l|l|} 
\toprule
Temperature [\si{\celsius}] & T\tss{w} [\si{\pico\second}] & $\tau$ [\si{\pico\second}]  & S [\si{\nano\second}] \\ 
\hline
-20         & 4    & 65       & 1.81                 \\
100         & 25   & 45          & 1.33             \\
\bottomrule
\end{tabular}
\label{tab:resolution}
\end{table}
Both of these values are a small fraction of a single clock cycle (\( 1.34ns/T_C = 0.134\)) and therefore one clock cycle will more than suffice (MTBF grows exponentially with S!).

\bigbreak\noindent\textbf{d)}\newline
Over the temperature range, $\tau$ rises exponentially with falling supply voltage, while $T_W$ tends to be more stable with a linear positive relationship with both temperature and supply voltage. When estimating the required resolution time S for a MTBF of 10 years when V\tss{DD} can reach as low as 1V, a clear maximum can be observed in the data. At $\SI{-20}{\celsius}$, $\tau \approx 600ps$ while $T_W \approx 3ps$. 

Using the previous equation \[ S \geq 13.93ns \] and order of magnitude greater! 

Since every clock cycle $T_C= 10ns$, the resolution time will require two clock  cycles.


\clearpage
\section{}
\textbf{a)}\newline
The spans for the various black and grey PG cells are shown below.

\begin{figure}[h]
    \centering
    \includegraphics[width=0.5\linewidth]{figures/handin3_4a.png}
    \caption{\textit{Spans of various PG cells in PG-tree diagram.}}
    \label{fig:spans}
\end{figure}

\bigbreak\noindent\textbf{b)}\newline
The difference between the black and grey PG-cells are is that the black cells compute both the \textit{group propagate} P\tss{i:j} and the \textit{group generate}  G\tss{i:j}, whereas the grey cells only compute the \textit{group generate}. Furthermore, the grey cells are placed above  black cells in any given bit position, since only the \textit{group generate} is needed when calculating the sum.

\bigbreak\noindent\textbf{c)}\newline
A sum function for a bit i in the PG-tree is (using Weste \& Harris' nomenclature) the \textit{propagate} for i exclusive OR'ed with the previous bit's \textit{group propagate} \[ S_i = P_i\oplus G\tss{i-1:0} \]

\bigbreak\noindent\textbf{d)}\newline
Since the \textit{group generate} of the preceeding bit i-1 is needed to compute the sum, it is clear that very few sums can be formed in this implementation. Only sum bits 1, 2, 4, 8, 12, 16, 20, 24 and 28 can be formed.

\clearpage
\bigbreak\noindent\textbf{e)}\newline
\begin{figure}[h]
    \centering
    \includegraphics[width=\linewidth]{figures/4e.png}
    \caption{\textit{PG-tree with grey PG-cells added in order to make every sum bit computable.}}
    \label{fig:my_label}
\end{figure}

\bigbreak\noindent\textbf{f)}\newline
The longest (critical) path through the PG-tree is through three grey cells and four black ones. Bits 30, 26, and 22 have this propagation delay of seven PG cells. 


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