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\section{Getting to know Cadence}
\section{CMOS inverter cell schematics}
A CMOS inverter uses a pMOS pullup transistor and an nMOS pulldown transistor. The substrates of the pMOS and nMOS must be tied to \( V_{DD} \) and \( V_{SS} \) respectively in order to reverse-bias the internal p-n junctions.

The following schematic has been drawn in LTSpice using 4-terminal MOSFET components that allow the substrate (or \textit{bulk}) to be connected freely. The substrate is represented by the middle port with an arrow indicating the internal p-n junctions.

\begin{figure}[h]
    \centering
    \includegraphics{figures/CMOS_inverter_ltspice-crop.pdf}
    \caption{\textit{CMOS Inverter drawn in LTSpice. \( V_{SS} \) is to be regarded as GND in this case.}}
    \label{fig:CMOS_inverter}
\end{figure}

\clearpage

\section{FO4 inverter delay for the standard-cell X4 drive-strength inverter}
Task parameters:
\begin{itemize}
    \item 65nm process
    \item \( I_{DS,N_\text{sat}}/\mu m  = \SI{600}{\micro\ampere\per\micro\metre} \)
    \item \( I_{DS,P_\text{sat}}/ \mu m = \SI{300}{\micro\ampere\per\micro\metre} \)
    \item \( C_{ox} = \SI{20}{\femto\farad\per\micro\metre\squared} \)
    \item \( V_{\text{DD}} = \SI{1.2}{\volt} \)
    \item \( L = \SI{.06}{\micro\metre} \)
    \item \( W_{N_\text{min}} = \SI{0.2}{\micro\metre} \)
    \item \( W_{P_\text{min}} = \SI{0.4}{\micro\metre} = 2 \cdot  W_{N_\text{min}} \)
    \item X2 drive strength
\end{itemize}
\rule{\textwidth}{0.5pt}
Since the inverter is to have a drive strength of X4, the widths of both the nMOS and the pMOS should be doubled, giving \( W_N = \SI{0.4}{\micro\metre} \) and \( W_P = \SI{0.8}{\micro\metre} \).

The gate capacitance \(C_G\) can now be calculated 
\[ C_G = C_{GN} + C_{GP} = (W_N + W_P)LC_{ox} = 3W_NLC_{ox} = \SI{1.44}{\femto\farad}\]
, where \(W_P = 2\cdot W_N \).

Assuming that the drain capacitance \( C_D \) for each transistor type is \( 0.8C_G \)
\[ C_D = 0.8 \cdot \SI{1.44}{\femto\farad} =  \SI{1.15}{\femto\farad} \]

% \[ R_\text{eff,N} = \frac{V_{DD}}{I_{DS,N_\text{max}}} = \frac{\SI{1.2}{\volt}}{\SI{600}{\micro\ampere\per\micro\metre}} \]

% \[ R_\text{eff,P} = \frac{V_{DD}}{I_{DS,P_\text{max}}} = \frac{\SI{1.2}{\volt}}{\SI{300}{\micro\ampere\per\micro\metre}} \]

% The effective resistance \(R_\text{eff} \) of each transistor device will help us later in calculating the delay
% \begin{align*}
%     R_\text{eff,N} =& \frac{V_\text{DD}}{I_{DS,N_\text{sat}}} = \SI{2}{\kilo\ohm\micro\metre}\\
%     R_\text{eff,P} =& \frac{V_\text{DD}}{I_{DS,P_\text{sat}}} = \SI{4}{\kilo\ohm\micro\metre}
% \end{align*}

In order to begin calculating the delay, we must now determine the saturation current for the transistors of drive-strength X4, set by their respective channel widths. 
\begin{align*}
    I_{DS,N_\text{sat}} =& I_{DS,N_\text{sat}}/\mu m \cdot W_N = \SI{240}{\micro\ampere} \\
    I_{DS,P_\text{sat}} =& I_{DS,P_\text{sat}}/\mu m \cdot W_P = \SI{240}{\micro\ampere}
\end{align*}

We can now see that the scaling of the pMOS wrt. the nMOS has given them equivalent current driving capabilities.  


The RC products can now be calculated for the rising and falling edge
\begin{align*}
    t_\text{pdr} &= 0.7 \frac{C_G \cdot V_\text{DD}}{I_{DS,P_\text{sat}}} = \SI{5.04}{\pico\second} \\
    t_\text{pdf} &= 0.7 \frac{C_G \cdot V_\text{DD}}{I_{DS,N_\text{sat}}} = \SI{5.04}{\pico\second} \\
    t_\text{pdr} &= t_\text{pdf} = \tau
\end{align*}
, where the constant 0.7 is an empirically determined value that closely approximates the behaviour of a ramped signal edge (rather than an ideal step).
Even here, the scaling of the pMOS has yielded identical values that can be consolidated as a single \textit{time constant} \( \tau \).

The actual FO4 delay is thus
\begin{align*}
    t_\text{pdrFO4} =& t_\text{pdfFO4} = t_\text{pd} \cdot (p + h) = 5 \cdot \SI{5.04}{\pico\second} = \SI{25.2}{\pico\second} \\
\end{align*}
, where \textit{p} is a parasitic factor that can be assumed to be 1 if unknown and \textit{h} is the \textit{electrical effort}, a value that quantifies load in terms of driver strength. In this case \textit{h} is equivalent to the fanout ie. 4.

\clearpage

\section{Static characterization of the CMOS inverter - expected values}
Task parameters:
\begin{itemize}
    \item 65nm process
    \item \( V_{\text{TN}} = \SI{0.29}{\volt} \)
    \item \( V_{\text{TP}} = \SI{-0.27}{\volt} \)
    \item \( V_{\text{DD}} = \SI{1.2}{\volt} \)
    \item Assume \(k_n = k_p \)
\end{itemize}
 \rule{\textwidth}{0.5pt}
Let \( x = k_n / k_p = 1\) and \( \Delta V = V_{\text{DD}} + V_{\text{TP}} - V_{\text{TN}} \). The switching voltage can then be calculated with the following equation:
\[ V_{\text{sw}} = V_{\text{TN}} + \frac{\Delta V}{1 + \sqrt{x}} = \SI{0.61}{\volt} \]
To calculate the noise margins we first have to compute the points on the VTC (and its inverse) at which \( A_v = -1 \) using the expressions provided in the assignment that are valid for \(k_n = k_p \). These points lie on the boundaries between \textit{valid} and \textit{indeterminate} symbols.

\begin{align*}
    V_{OH\text{,min}} =& V_{\text{DD}} - \frac{\Delta V}{8} = \SI{1.12}{\volt} \\
    V_{IL\text{,max}} =& V_{\text{sw}} - \frac{\Delta V}{8} = \SI{0.53}{\volt} \\
    V_{OL\text{,max}} =& \frac{\Delta V}{8}                 = \SI{0.08}{\volt} \\
    V_{IH\text{,min}} =& V_{\text{sw}} + \frac{\Delta V}{8} = \SI{0.69}{\volt}
\end{align*}
We can now compute the noise margins (in terms of \(V_\text{out}\) ) using the following expressions
\begin{align*}
    NM_H =& V_{OH\text{,min}} - V_{IH\text{,min}} = \SI{0.43}{\volt}\\
    NM_L =& V_{IL\text{,max}} - V_{OL\text{,max}} = \SI{0.45}{\volt}
\end{align*}

\clearpage

\section{Static characterization of the CMOS inverter - finding the values from the VTC}

The value for \(S_\text{sw} \) is clearly the input value with the greatest negative slope (seen highlighted in red in fig. \ref{fig:VTC}). If the currents \(I_{DS} \) through each transistor are measured, \(V_{sw} \) can also be identified by the point at which they are equivalent. Likewise, the values for \( V_{OH\text{,min}} \) and \( V_{OL\text{,max}} \) can be directly obtained by taking the derivative of the VTC and finding the output values at which the derivative is -1. The corresponding input values at the same points give \( V_{IL\text{,max}} \) and \(  V_{IH\text{,min}} \). 

\( V_{IL\text{,max}} \) and \( V_{IH\text{,min}} \) can also be found by first taking the inverse of the VTC curve, plotting the derivative and finding the output values at which it is -1, the same method used to plot a "butterfly" diagram.

\begin{figure}[h]
    \centering
    \includegraphics[width=\linewidth]{figures/VTC.png}
    \caption{\textit{CMOS inverter VTC. Switching voltage \( S_{sw} \) marked in red, \( V_{OH}, V_{IL}, V_{OL} \) and \( V_{IH} \) regions labeled.}}
    \label{fig:VTC}
\end{figure}

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