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\section{Introduction}
In this lab preparation a ripple-carry cell will be designed at the transistor level as a CMOS compound gate using the 65 nm process. The design will then be analyzed in order to estimate the logical effort for the input of the gate, the worst-case propagation delay through an 8-bit ripple-carry circuit and the total transistor count, which is proportional to gate area.

\section{Boolean Expression}
The truth table for a ripple-carry cell is shown in figure \ref{fig:truth_table}. A carry cell computes the carry-out value resulting from the addition of three input bits (a, b and \(C_\text{in}\)) and outputs true when two or three inputs are true. This can be abstracted as a 3-input \textit{majority function}, \(f\textsubscript{maj}\), a \textit{monotonically increasing} function (ie. transitions in one direction on input causes transition in the same direction on the output) that can therefore not be implemented in a single CMOS-stage as CMOS gates always result in \textit{monotonically decreasing/inverting} logic \cite{dally_harting_aamodt_2016}. By this reasoning, however, \(\overline{f\textsubscript{maj}}\) is possible to implement.   

The expression for this inverse function can be derived using a Karnaugh map that groups '0's and gives an expression in \textit{conjunctive} form\footnote{Also known as product-of-sums. Its counterpart is \textit{disjunctive} form, or sum-of-products.}, that can then be converted to complemented \textit{disjunctive} form using deMorgan's theorem 
\begin{equation}
    \begin{split}
        f(A, B, C\textsubscript{in}) = \overline{f\textsubscript{maj}}  &= \overline{C\textsubscript{in}A + C\textsubscript{in}B + AB}\\
                                                                        &= \overline{C\textsubscript{in}(A+B) + AB} 
    \end{split}
\end{equation}

The nMOS pull-down network is thus given by the inverse function (as it pulls the output low when the function is true)
\begin{equation}
    f_n = C\textsubscript{in}(A+B) + AB 
\end{equation} 
The derivation of the pMOS pull-up network is greatly facilitated by the \textit{principle of duality}\footnote{The \textit{dual} form of a function amounts to converting all ORs to ANDs and vice-versa. In transistor terms, this corresponds to replacing series connections with parallel connections and vice-versa. This also gives rise to a generalised form of deMorgan's theorem, stating \[ f^D(\bar{a}, \bar{b},...) = \overline{f(a,b,...)}\] } using the following reasoning: if the pull-down network realizes a function \(f\textsubscript{n}\) then we know that the CMOS gate will realize the inverse function \( f_p = \overline{f_n(x_1,x_2,...)} \). Duality then gives \( f_p = \overline{f_n(x_1,x_2,...)} = f_n^D(\bar{x_1},\bar{x_2},...) \). Since pMOS transistors inherently invert their inputs, this becomes \( f_p = f_n^D(x_1, x_2,...) \). Thus, for the \textit{majority} function
\begin{equation}
    \begin{split}
        f_p = f_n^D &= (C\textsubscript{in}+AB)(A+B)\\ 
                    &\Rightarrow C\textsubscript{in}A + C\textsubscript{in}B + AAB + ABB\\ 
                    &= C\textsubscript{in}(A+B)+AB 
    \end{split}
\end{equation}
The result is that the \textit{majority} function and its \textit{dual} are equivalent! Due to this fact, we are now free to choose either of the \textit{dual} functions for the networks. Another property of self-duality is that the function inverter (to finally reach the non-inverted carry-cell behaviour) may be placed either on the output or on the inputs.


\begin{figure}[h]
    \centering
    \includegraphics[width=0.4\linewidth]{figures/truth_table.png}
    \caption{\textit{Truth table for 1-bit ripple-carry cell.}}
    \label{fig:truth_table}
\end{figure}

\clearpage

\section{Transistor-Level Schematic}
The previous task gave a few different options for how the schematic could be drawn. One thing to consider is that it is beneficial to reduce length of any series path through the circuit, as each device has its own effective resistance and the width of every device in the path will need to be scaled up to compensate, resulting in a bigger area. The scaling of each device (normalized to the unit size for the process) is shown in schematic below.

An inspection of \( f\textsubscript{maj} \) and \( f\textsubscript{maj}^D \) (eq.2 and 3 resp.) shows that although the same number of terms and gates are used, \( f\textsubscript{maj}^D \) has a maximum series path (terms ANDed together) of 3, whereas \( f\textsubscript{maj} \) has a maximum of only 2. The network given by \( f\textsubscript{maj} \) will therefore be used for both the pull-up and the pull-down networks, resulting in a symmetrical design.

Having the parallel devices connect to the rails rather than the output of the gate also results in a lower output drain-capacitance. The final schematic can be seen in figure \ref{fig:schema}. 

\begin{figure}[h]
    \centering
    \includegraphics[width=0.8\linewidth]{figures/majority_function.pdf}
    \caption{\textit{Transistor-level schematic for a 1-bit ripple carry cell. Gate networks to the left, output inverter to the right. Relative scaling of transistors in red. }}
    \label{fig:schema}
\end{figure}

% \begin{figure}[h]
%     \centering
%     \includegraphics[width=\linewidth]{figures/schema_w_scaling.png}
%     \caption{\textit{Transistor-level schematic for a 1-bit ripple carry cell. Relative scaling of transistors in red. Drawn in LTSpice.}}
%     \label{fig:schema}
% \end{figure}

\clearpage
\section{Logical Effort and Parasitic Delay}
Logical effort and parasitic delay are quantified relative to normalized input capacitance of a single CMOS inverter ie. 3C.
The logical effort for the \( C_{\text{in}}\) input to the ripple-carry cell is \[ g_{\text{C\textsubscript{in}}} = \frac{C\textsubscript{in}}{C\textsubscript{inv}} = \frac{4C+2C}{3C} = 2 \]
and the parasitic delay of the gate output is
\[ P_\text{C\textsubscript{out}} = \frac{4C+4C+2C+2C}{3C} \cdot p_\text{inv} =  4p\textsubscript{inv}\]
The inverter, of course, has \( g\textsubscript{inv}=1\) and \(p = p\textsubscript{inv}\) since it is normalized relative to itself.

\section{Worst-Case Propagation Delay}
The schematic in fig \ref{fig:schema} can be drawn as a block diagram below. 
\begin{figure}[h]
    \centering
    \includegraphics[width=0.5\linewidth]{figures/majority_function_blockschema.pdf}
    \caption{Block diagram showing a single link of a ripple carry adder. Input capacitances at each stage are labeled.}
    \label{fig:blockschema}
\end{figure}

Due to the relative scaling of the stages \( C_L = 2C\textsubscript{in} \). 
Therefore the electrical effort h for the first stage is
\[ h_1 = \frac{C_\textsubscript{L}}{C_\textsubscript{in}} = \frac{2C\textsubscript{in}}{C\textsubscript{in}} = 2 \]
Due to the repeating nature of the ripple-carry adder the next load will be the input to the next carry-cell. The electrical effort for the second stage is therefore
\[ h_2 = \frac{C_\textsubscript{L}}{C_\textsubscript{in}} = \frac{C\textsubscript{in}}{2C\textsubscript{in}} = \frac{1}{2} \]
The normalized delay for a single ripple-carry cell is thus 
\begin{equation*}
    \begin{split}
        d   &= g_1\cdot h_1+ p_1 + g_2\cdot h_2+ p_2 \\
            &= 2\cdot2 + 4p\textsubscript{inv} + 1\cdot\frac{1}{2} + 1 \\
            &= 4.5 + 5p\textsubscript{inv}
    \end{split}
\end{equation*}

The time constant \( \tau\) was determined in \textit{lab prep 1} to be 5ps for this particular process. The worst case time-delay for a single carry cell is thus \[ t_d = d\cdot\tau = 5\cdot (4.5 + 5p\textsubscript{inv}) \approx 47.5ps \]
and for an 8-bit ripple-carry adder
\[ 8*47.5ps = 380ps \]
, where \(p\textsubscript{inv} \) is assumed to be \(\approx\) 1.


\section{Summary}
The ripple-carry cell (or \textit{majority function} gate) can be designed using symmetrical pullup and pulldown networks. Alternatives where considered and shown to result in more area usage and higher output-drain capacitance. The fully realized carry logic uses 12 transistors: 10 for the inverting ripple-carry cell and 2 for output inverter. An 8-bit ripple carry circuit therefore uses 96 transistors.


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