\documentclass{article}
\input{settings.tex}

%\renewcommand{\thesection}{\Roman{section}}
\usepackage{titlesec}
\titleformat{\section}
{\normalfont\Large\bfseries}{Task \texttt{\#}\thesection:}{0.25em}{}
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
\begin{document}
\section{The tools}
\textbf{a)} A transient simulation is a simulation in the time-domain.
\newline
\textbf{b)} The transistor parameters use the SPICE naming conventions and are as follows\cite{m_mosfet}: 
\begin{itemize}
    \item vt0 : zero-bias threshold voltage [V]
    \item kp : transconductance [\(\frac{A}{V^2}\)]
    \item gamma : Bulk threshold parameter [\(V^\frac{1}{2}\)]
    \item lambda : Channel-length modulation [\(V^{-1}\)]
    \item phi : Surface inversion potential [V]
\end{itemize}
\textbf{c)} Node 0 is GND (or 0V).
\newline
\textbf{d)} 
\begin{figure}[h]
    \centering
    \includegraphics[width=0.5\linewidth]{figures/1d.pdf}
    \caption{Inverter schematic specified by Spectre netlist file. Instantiated components and nets labeled.}
    \label{fig:1d}
\end{figure}

\section{The lab}
\section{The Spectre netlist file}
\clearpage
\section{The capacitances of the H-tree}
Ignoring (shorting) the resistances of the H-tree directly connects all the capacitances to the output node of the tapered buffer. The total capacitance is then simply the sum of the indivudual wire and leaf-inverter input capacitances. 

Since none of the wire widths exceed \(\SI{2}{\micro\meter}\), the wire capacitance can be assumed to be \(\SI{0.2}{\femto\farad\per\micro\meter}\).
\begin{align*}
    C_{W1} =& \SI{10}{\milli\meter} \cdot \SI{0.2}{\femto\farad\per\micro\meter} = \SI{2}{\pico\farad} \\
    C_{W2} =&  \SI{7.07}{\milli\meter} \cdot \SI{0.2}{\femto\farad\per\micro\meter} = \SI{1.414}{\pico\farad} \\   
    C_{W2} =&  \SI{5}{\milli\meter} \cdot \SI{0.2}{\femto\farad\per\micro\meter} = \SI{1}{\pico\farad} 
\end{align*}
The input capacitance of an X1 inverter was found in \textit{lab 1} to be \( \SI{0.36}{\femto\farad}\), therefore the input capacitance of the scaled up inverter on the leaves is \( 1000 \cdot \SI{0.36}{\femto\farad} = \SI{0.36}{\pico\farad} \).

The total capacitance of the (zero-resistance) H-tree is \[ C\textsubscript{H-tree} = 2C_{W1} + 4C_{W2} + 8C_{W3} + 8000\cdot C\textsubscript{in,X1} =  \SI{20.536}{\pico\farad} \]

\section{Design of the tapered buffer}
If we let \( C = C\textsubscript{in,X1} = \SI{0.36}{\pico\farad} \) (ie. the input capacitance of an X1 inverter), and use it as a reference value, then the capacitive load of the H-tree can be \textit{normalized} as \( \frac{\SI{20.536}{\pico\farad}}{\SI{0.36}{\pico\farad}} = 57044C \). 

Next, the various \textit{path efforts} can be determined 
\begin{itemize}
    \item G = 1
    \item B = 1
    \item H = \(\frac{57044C}{4C} = 14261\)
\end{itemize}
This gives a \textit{path effort} of \( F = GBH = 14261 \). 

It can be shown that the \textit{path delay} is at a minimum when all the \textit{stage efforts} are equal and approximately 4. Thus the optimum number of stages is chosen to achieve this result as closely as possible. \[ \hat{N} = \log_4 (F) = 6.9 \] 
At this point a value of either 6 or 7 could be chosen. Both will be evaluated here to determine which is more appropriate. 

For \( \hat{N} = 7 \) the minimum \textit{path delay} \( D = \hat{N}\cdot \sqrt[\hat{N}]{F} + P = 7\cdot \sqrt[7]{14261}+7 = 34.5 \) and the \textit{stage effort} \( \hat{f} = \sqrt[7]{14261} = 3.92 \).

For \( \hat{N} = 6 \), however, the minimum \textit{path delay} \( D =  35.5 \) and the \textit{stage effort} \( \hat{f} = 4.92 \). The fact that the delay is insensitive to the number of stages means that accepting a marginal increases in delay (1ps, or 2.8\%) allows an area reduction of 14\% along with the associated power consumption! 

Since this is arguably the superior implementation, it will be used going forward. Finally the absolute \textit{path delay} is \( t\textsubscript{pd} = 35.5 \tau = 177ps \), where \(\tau=5ps\). As a consequence of all the individual \textit{path efforts} being equal, the delays between each stage are also equal ie. \( d_i = g_i h_i + p_i = 5.92 \) or 29.6ps in absolute terms.

\clearpage
\section{The Resistances (and capacitances) of the H-tree}
The resistance of a wire segment can be calculated from its \textit{sheet resistance} and its physical dimensions \[ R_W =R\textsubscript{sh}\frac{L}{W} \], note height (or thickness) is disregarded in this model.

The dimensions of the wires are known and \( R\textsubscript{sh} \) is assumed to be \( 0.01\frac{\Omega}{\square} \). Thus, the resistance of the wires at each level can be calculated as
\begin{itemize}
    \item R\textsubscript{W1} = \SI{50}{\ohm}
    \item R\textsubscript{W2} = \SI{50.1}{\ohm}
    \item R\textsubscript{W3} = \SI{50}{\ohm}
\end{itemize}

\begin{figure}[h]
    \centering
    \includegraphics[width=0.9\linewidth]{figures/H-tree.pdf}
    \caption{H-tree with calculated resistances and capacitances.}
    \label{fig:H-tree}
\end{figure}

\clearpage
\section{Delay of the H-tree with capacitance and resistance when driven by the tapered buffer}
The H-tree is fully symmetrical and when modeled as lumped components, parallellism becomes evident, allowing the tree to be "collapsed" into a single path with no branches. This results in the following schematic

\begin{figure}[h]
    \centering
    \includegraphics[width=\linewidth]{figures/prelab4_elmore.pdf}
    \caption{The "collapsed" H-tree, as a non-branching RC-chain.}
    \label{fig:elmore}
\end{figure}
The Elmore delay of this reduced H-tree is calculated in the following formula

\begin{align*}
    T_E = &R\textsubscript{rep}(C_D+8000C+2C\textsubscript{w1}+4C\textsubscript{w2}+8C\textsubscript{w3})+\\ &R\textsubscript{w1}/2(C\textsubscript{w1} + 4C\textsubscript{w2}+8C\textsubscript{w3} + 8000C) +\\ &R\textsubscript{w2}/4(2C\textsubscript{w2} +  8C\textsubscript{w3} + 8000C) + \\
    &R\textsubscript{w3}/8(4C\textsubscript{w3} + 8000C \\
    = &692.6ps
\end{align*}

After compensating for the behaviour of ramped signal inputs (scaling the delay by 0.7) the Elmore delay is 484.8ps.

\clearpage
\section{Delay	with	inverters	in	the	H	tree	driven	by	tapered	buffer}
The buffers inserted into the H-tree can be modeled as an effective resistance with an input and output capacitance.  The output (diffusion) capacitance \( C_D \) is assumed to be equal to the input capacitance C\textsubscript{in}. The effective resistance of an X1 inverter was determined in \textit{lab 1} to be \(\SI{20}{\kilo\ohm}\).  Since the tree is still symmetrical it can again be collapsed into a single path. Since the inverters do not provide a direct electrical path between the input and the output, the path must be divided into segments with the Elmore delay calculated for each segment individually.

\begin{figure}[h]
    \centering
    \includegraphics[width=\linewidth]{figures/prelab4_elmore2.pdf}
    \caption{Collapsed H-tree with inserted buffers.}
    \label{fig:elmore2}
\end{figure}
The uncompensated Elmore delay for each segment is thus (segments numbered left to right in fig \ref{fig:elmore2})
\begin{align*}
    T_{E_{1}} = &R_{taper}(C_D + C_{w1} +C_{w1} + 2000C) + \frac{R_{w1}}{2}(C_{w1} + 2000C) = 76,8ps \\
    T_{E_{2}} = &R_{inv}(2000C + 2C_{w2} + 2C_{w2} + 2000C) + \frac{ R_{w2}}{4}(2C_{w2} + 2000C) = 115,4ps \\
    T_{E_{3}} = &R_{inv}(2000C +  4C_{w3} + 4C_{w3} + 8000C) + \frac{R_{w3}}{8} (4C_{w3} + 8000C) = 159,0ps
\end{align*}
, resulting in a total delay of 351.3ps. 
Once the results are compensated to take into account ramped input signals, the results are as follows
\begin{align*}
    T_{E_{1}} = 53,8ps \\
    T_{E_{2}} = 80,8ps \\
    T_{E_{3}} = 111,3ps
\end{align*}
, with a total of delay of 245,9ps.


\clearpage
\printbibliography

\end{document}
