# 
# Synthesis run script generated by Vivado
# 

create_project -in_memory -part xc7a100tcsg324-1

set_param project.singleFileAddWarning.threshold 0
set_param project.compositeFile.enableAutoGeneration 0
set_param synth.vivado.isSynthRun true
set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
set_property webtalk.parent_dir Z:/ILA_labs/debug_ila/debug_ila.cache/wt [current_project]
set_property parent.project_path Z:/ILA_labs/debug_ila/debug_ila.xpr [current_project]
set_property XPM_LIBRARIES XPM_MEMORY [current_project]
set_property default_lib xil_defaultlib [current_project]
set_property target_language VHDL [current_project]
set_property ip_output_repo z:/ILA_labs/debug_ila/debug_ila.cache/ip [current_project]
set_property ip_cache_permissions {read write} [current_project]
read_vhdl -library xil_defaultlib {
  Z:/ILA_labs/debug_ila/debug_ila.srcs/sources_1/new/clk_enable.vhd
  Z:/ILA_labs/debug_ila/debug_ila.srcs/sources_1/new/top.vhd
}
read_ip -quiet Z:/ILA_labs/debug_ila/debug_ila.srcs/sources_1/ip/dds_compiler_0/dds_compiler_0.xci
set_property used_in_implementation false [get_files -all z:/ILA_labs/debug_ila/debug_ila.srcs/sources_1/ip/dds_compiler_0/dds_compiler_0_ooc.xdc]
set_property is_locked true [get_files Z:/ILA_labs/debug_ila/debug_ila.srcs/sources_1/ip/dds_compiler_0/dds_compiler_0.xci]

read_ip -quiet Z:/ILA_labs/debug_ila/debug_ila.srcs/sources_1/ip/dds_compiler_1/dds_compiler_1.xci
set_property used_in_implementation false [get_files -all z:/ILA_labs/debug_ila/debug_ila.srcs/sources_1/ip/dds_compiler_1/dds_compiler_1_ooc.xdc]
set_property is_locked true [get_files Z:/ILA_labs/debug_ila/debug_ila.srcs/sources_1/ip/dds_compiler_1/dds_compiler_1.xci]

read_ip -quiet Z:/ILA_labs/debug_ila/debug_ila.srcs/sources_1/ip/ila_0_1/ila_0.xci
set_property used_in_implementation false [get_files -all z:/ILA_labs/debug_ila/debug_ila.srcs/sources_1/ip/ila_0_1/ila_v6_2/constraints/ila.xdc]
set_property used_in_implementation false [get_files -all z:/ILA_labs/debug_ila/debug_ila.srcs/sources_1/ip/ila_0_1/ila_0_ooc.xdc]
set_property is_locked true [get_files Z:/ILA_labs/debug_ila/debug_ila.srcs/sources_1/ip/ila_0_1/ila_0.xci]

# Mark all dcp files as not used in implementation to prevent them from being
# stitched into the results of this synthesis run. Any black boxes in the
# design are intentionally left as such for best results. Dcp files will be
# stitched into the design at a later time, either when this synthesis run is
# opened, or when it is stitched into a dependent implementation run.
foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
  set_property used_in_implementation false $dcp
}
read_xdc Z:/ILA_labs/debug_ila/Nexys-4-DDR-Master.xdc
set_property used_in_implementation false [get_files Z:/ILA_labs/debug_ila/Nexys-4-DDR-Master.xdc]


synth_design -top top -part xc7a100tcsg324-1


write_checkpoint -force -noxdef top.dcp

catch { report_utilization -file top_utilization_synth.rpt -pb top_utilization_synth.pb }
