# 
# Synthesis run script generated by Vivado
# 

set_param tcl.collectionResultDisplayLimit 0
set_param xicom.use_bs_reader 1
create_project -in_memory -part xc7a100tcsg324-1

set_param project.singleFileAddWarning.threshold 0
set_param project.compositeFile.enableAutoGeneration 0
set_param synth.vivado.isSynthRun true
set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
set_property webtalk.parent_dir C:/Users/vikramj/Downloads/dat096-ila-labs/lab1/lab1.cache/wt [current_project]
set_property parent.project_path C:/Users/vikramj/Downloads/dat096-ila-labs/lab1/lab1.xpr [current_project]
set_property XPM_LIBRARIES XPM_MEMORY [current_project]
set_property default_lib xil_defaultlib [current_project]
set_property target_language VHDL [current_project]
set_property ip_cache_permissions disable [current_project]
read_vhdl -library xil_defaultlib {
  C:/Users/vikramj/Downloads/dat096-ila-labs/lab1/lab1.srcs/sources_1/new/top.vhd
  C:/Users/vikramj/Downloads/dat096-ila-labs/lab1/lab1.srcs/sources_1/new/filter.vhd
}
read_ip -quiet C:/Users/vikramj/Downloads/dat096-ila-labs/lab1/lab1.srcs/sources_1/ip/ila_0/ila_0.xci
set_property used_in_implementation false [get_files -all c:/Users/vikramj/Downloads/dat096-ila-labs/lab1/lab1.srcs/sources_1/ip/ila_0/ila_v6_2/constraints/ila.xdc]
set_property used_in_implementation false [get_files -all c:/Users/vikramj/Downloads/dat096-ila-labs/lab1/lab1.srcs/sources_1/ip/ila_0/ila_0_ooc.xdc]
set_property is_locked true [get_files C:/Users/vikramj/Downloads/dat096-ila-labs/lab1/lab1.srcs/sources_1/ip/ila_0/ila_0.xci]

read_ip -quiet C:/Users/vikramj/Downloads/dat096-ila-labs/lab1/lab1.srcs/sources_1/ip/ila_1/ila_1.xci
set_property used_in_implementation false [get_files -all c:/Users/vikramj/Downloads/dat096-ila-labs/lab1/lab1.srcs/sources_1/ip/ila_1/ila_v6_2/constraints/ila.xdc]
set_property used_in_implementation false [get_files -all c:/Users/vikramj/Downloads/dat096-ila-labs/lab1/lab1.srcs/sources_1/ip/ila_1/ila_1_ooc.xdc]
set_property is_locked true [get_files C:/Users/vikramj/Downloads/dat096-ila-labs/lab1/lab1.srcs/sources_1/ip/ila_1/ila_1.xci]

# Mark all dcp files as not used in implementation to prevent them from being
# stitched into the results of this synthesis run. Any black boxes in the
# design are intentionally left as such for best results. Dcp files will be
# stitched into the design at a later time, either when this synthesis run is
# opened, or when it is stitched into a dependent implementation run.
foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
  set_property used_in_implementation false $dcp
}
read_xdc C:/Users/vikramj/Downloads/dat096-ila-labs/lab1/lab1.srcs/constrs_1/new/Nexys-4-DDR-Master.xdc
set_property used_in_implementation false [get_files C:/Users/vikramj/Downloads/dat096-ila-labs/lab1/lab1.srcs/constrs_1/new/Nexys-4-DDR-Master.xdc]


synth_design -top TOP -part xc7a100tcsg324-1


write_checkpoint -force -noxdef TOP.dcp

catch { report_utilization -file TOP_utilization_synth.rpt -pb TOP_utilization_synth.pb }
