<?xml version="1.0" encoding="UTF-8"?>
<probeData version="2" minor="1">
  <probeset name="EDA_PROBESET" active="true">
    <probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
      <probeOptions Id="DebugProbeParams">
        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
        <Option Id="CORE_LOCATION" value="1:0"/>
        <Option Id="HW_ILA" value="debug0"/>
        <Option Id="PROBE_PORT" value="0"/>
        <Option Id="PROBE_PORT_BITS" value="0"/>
        <Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
      </probeOptions>
      <nets>
        <net name="clk_div2"/>
      </nets>
    </probe>
    <probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
      <probeOptions Id="DebugProbeParams">
        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
        <Option Id="CORE_LOCATION" value="1:0"/>
        <Option Id="HW_ILA" value="debug0"/>
        <Option Id="PROBE_PORT" value="1"/>
        <Option Id="PROBE_PORT_BITS" value="0"/>
        <Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
      </probeOptions>
      <nets>
        <net name="inc"/>
      </nets>
    </probe>
    <probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
      <probeOptions Id="DebugProbeParams">
        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
        <Option Id="CORE_LOCATION" value="1:0"/>
        <Option Id="HW_ILA" value="debug0"/>
        <Option Id="PROBE_PORT" value="2"/>
        <Option Id="PROBE_PORT_BITS" value="0"/>
        <Option Id="PROBE_PORT_BIT_COUNT" value="4"/>
      </probeOptions>
      <nets>
        <net name="counter[3]"/>
        <net name="counter[2]"/>
        <net name="counter[1]"/>
        <net name="counter[0]"/>
      </nets>
    </probe>
    <probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
      <probeOptions Id="DebugProbeParams">
        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
        <Option Id="CORE_LOCATION" value="1:0"/>
        <Option Id="HW_ILA" value="debug0"/>
        <Option Id="PROBE_PORT" value="3"/>
        <Option Id="PROBE_PORT_BITS" value="0"/>
        <Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
      </probeOptions>
      <nets>
        <net name="en_sine1"/>
      </nets>
    </probe>
    <probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
      <probeOptions Id="DebugProbeParams">
        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
        <Option Id="CORE_LOCATION" value="1:0"/>
        <Option Id="HW_ILA" value="debug0"/>
        <Option Id="PROBE_PORT" value="4"/>
        <Option Id="PROBE_PORT_BITS" value="0"/>
        <Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
      </probeOptions>
      <nets>
        <net name="en_sine2"/>
      </nets>
    </probe>
    <probe type="ila" busType="net" source="netlist" spec="ILA_V2_RT">
      <probeOptions Id="DebugProbeParams">
        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
        <Option Id="CORE_LOCATION" value="1:0"/>
        <Option Id="HW_ILA" value="debug0"/>
        <Option Id="PROBE_PORT" value="5"/>
        <Option Id="PROBE_PORT_BITS" value="0"/>
        <Option Id="PROBE_PORT_BIT_COUNT" value="1"/>
      </probeOptions>
      <nets>
        <net name="sine1_le"/>
      </nets>
    </probe>
    <probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
      <probeOptions Id="DebugProbeParams">
        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
        <Option Id="CORE_LOCATION" value="1:0"/>
        <Option Id="HW_ILA" value="debug0"/>
        <Option Id="PROBE_PORT" value="6"/>
        <Option Id="PROBE_PORT_BITS" value="0"/>
        <Option Id="PROBE_PORT_BIT_COUNT" value="26"/>
      </probeOptions>
      <nets>
        <net name="probe6[25]"/>
        <net name="probe6[24]"/>
        <net name="probe6[23]"/>
        <net name="probe6[22]"/>
        <net name="probe6[21]"/>
        <net name="probe6[20]"/>
        <net name="probe6[19]"/>
        <net name="probe6[18]"/>
        <net name="probe6[17]"/>
        <net name="probe6[16]"/>
        <net name="probe6[15]"/>
        <net name="probe6[14]"/>
        <net name="probe6[13]"/>
        <net name="probe6[12]"/>
        <net name="probe6[11]"/>
        <net name="probe6[10]"/>
        <net name="probe6[9]"/>
        <net name="probe6[8]"/>
        <net name="probe6[7]"/>
        <net name="probe6[6]"/>
        <net name="probe6[5]"/>
        <net name="probe6[4]"/>
        <net name="probe6[3]"/>
        <net name="probe6[2]"/>
        <net name="probe6[1]"/>
        <net name="probe6[0]"/>
      </nets>
    </probe>
    <probe type="ila" busType="bus" source="netlist" spec="ILA_V2_RT">
      <probeOptions Id="DebugProbeParams">
        <Option Id="BSCAN_SWITCH_INDEX" value="0"/>
        <Option Id="CORE_LOCATION" value="1:0"/>
        <Option Id="HW_ILA" value="debug0"/>
        <Option Id="PROBE_PORT" value="7"/>
        <Option Id="PROBE_PORT_BITS" value="0"/>
        <Option Id="PROBE_PORT_BIT_COUNT" value="26"/>
      </probeOptions>
      <nets>
        <net name="sinegen_out_reg_n_1_[25]"/>
        <net name="sinegen_out_reg_n_1_[24]"/>
        <net name="sinegen_out_reg_n_1_[23]"/>
        <net name="sinegen_out_reg_n_1_[22]"/>
        <net name="sinegen_out_reg_n_1_[21]"/>
        <net name="sinegen_out_reg_n_1_[20]"/>
        <net name="sinegen_out_reg_n_1_[19]"/>
        <net name="sinegen_out_reg_n_1_[18]"/>
        <net name="sinegen_out_reg_n_1_[17]"/>
        <net name="sinegen_out_reg_n_1_[16]"/>
        <net name="sinegen_out_reg_n_1_[15]"/>
        <net name="sinegen_out_reg_n_1_[14]"/>
        <net name="sinegen_out_reg_n_1_[13]"/>
        <net name="sinegen_out_reg_n_1_[12]"/>
        <net name="sinegen_out_reg_n_1_[11]"/>
        <net name="sinegen_out_reg_n_1_[10]"/>
        <net name="sinegen_out_reg_n_1_[9]"/>
        <net name="sinegen_out_reg_n_1_[8]"/>
        <net name="sinegen_out_reg_n_1_[7]"/>
        <net name="sinegen_out_reg_n_1_[6]"/>
        <net name="sinegen_out_reg_n_1_[5]"/>
        <net name="sinegen_out_reg_n_1_[4]"/>
        <net name="sinegen_out_reg_n_1_[3]"/>
        <net name="sinegen_out_reg_n_1_[2]"/>
        <net name="sinegen_out_reg_n_1_[1]"/>
        <net name="sinegen_out_reg_n_1_[0]"/>
      </nets>
    </probe>
  </probeset>
</probeData>
