xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../Xilinx/Vivado/2017.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../../debug_ila.srcs/sources_1/ip/ila_0_1/hdl/verilog"
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../Xilinx/Vivado/2017.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../../debug_ila.srcs/sources_1/ip/ila_0_1/hdl/verilog"
ila_0.vhd,vhdl,xil_defaultlib,../../../../debug_ila.srcs/sources_1/ip/ila_0_1/sim/ila_0.vhd,incdir="../../../../debug_ila.srcs/sources_1/ip/ila_0_1/hdl/verilog"
glbl.v,Verilog,xil_defaultlib,glbl.v
