2017.2:
 * Version 6.2 (Rev. 3)
 * Added new AZYNQUPLUS device support

2017.1:
 * Version 6.2 (Rev. 2)
 * Updated ILA and Debug Hub IPs to handle CDC warnings
 * Revision change in one or more subcores

2016.4:
 * Version 6.2 (Rev. 1)
 * Updated ILA and Debug Hub IPs to handle CDC warnings
 * Revision change in one or more subcores

2016.3:
 * Version 6.2
 * Updated DRC to set individual probe MU count value based on all_probe_same_mu_cnt parameter
 * Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user
 * Revision change in one or more subcores

2016.2:
 * Version 6.1
 * No changes

2016.1:
 * Version 6.1
 * Updated the IP to support 2 Windows & 1 Sample count configuration
 * Number of comparator increased from 1 to 16 in basic mode and 4 to 16 in advanced mode
 * Updated probe data width register

2015.4.2:
 * Version 6.0 (Rev. 1)
 * No changes

2015.4.1:
 * Version 6.0 (Rev. 1)
 * No changes

2015.4:
 * Version 6.0 (Rev. 1)
 * No change

2015.3:
 * Version 6.0
 * Fixed Timing10 DRC violations in ILA IP.
 * IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances

2015.2.1:
 * Version 5.1 (Rev. 1)
 * No changes

2015.2:
 * Version 5.1 (Rev. 1)
 * Updated IP XDC constraints to fix Partial False path scenario in ILA when operated in mulit clock domain
 * Updated IP XDC constraints to fix critical warnings in High Speed Design Debugging mode

2015.1:
 * Version 5.1
 * Fixed example design placer issue with pin location constraints for SVD packages

2014.4.1:
 * Version 5.0 (Rev. 2)
 * Updated example XDC pin location constraints for new devices

2014.4:
 * Version 5.0 (Rev. 1)
 * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time

2014.3:
 * Version 5.0
 * Added AXI4 Stream monitor support. New parameter option AXI4S added to C_SLOT_0_AXI_PROTOCOL
 * Four new user parameters added to support AXI4 Stream. These are C_SLOT_0_AXIS_TDATA_WIDTH, C_SLOT_0_AXIS_TID_WIDTH, C_SLOT_0_AXIS_TUSER_WIDTH, C_SLOT_0_AXIS_TID_WIDTH
 * Updated ILA IP to use new helper libraries (ltlib_v1_0 & xsdbs_v1_0)
 * Changed C_NNUM_MONITOR_SLOTS field to read only as ILA supported only interface in AXI mode

2014.2:
 * Version 4.0 (Rev. 1)
 * Fixed TIMING DRC violations, added ASYNC_REG property on the register which has double synchronizer for CDC paths
 * Fixed re-execution of First state when ila is used in advanced trigger mode
 * Reduced number of unused ports visible to users for AXI mode when AXI4LITE protocol is selected

2014.1:
 * Version 4.0
 * Updated the IP to support new DBG_HUB stitcher algorithm
 * Updated ILA AXI monitor feature to the IP
 * Internal device family name change, no functional changes

2013.4:
 * Version 3.0 (Rev. 1)
 * Kintex UltraScale Pre-Production support

2013.3:
 * Version 3.0
 * All ports changed to lower case
 * Added ILA Advanced Trigger Features

2013.2:
 * Version 2.1
 * Improved support for multiple instances
 * Added C_TRIGOUT_EN  parameter to support cross trigring
 * Added C_TRIGIN_EN  parameter to support cross trigring

2013.1:
 * Version 2.0
 * Native Vivado Release

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