xpm_memory.sv,systemverilog,xil_defaultlib,../../../../../../../../Xilinx/Vivado/2017.2/data/ip/xpm/xpm_memory/hdl/xpm_memory.sv,incdir="../../../../lab1.srcs/sources_1/ip/ila_0/hdl/verilog"
xpm_VCOMP.vhd,vhdl,xpm,../../../../../../../../Xilinx/Vivado/2017.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../../lab1.srcs/sources_1/ip/ila_0/hdl/verilog"
ila_0.vhd,vhdl,xil_defaultlib,../../../../lab1.srcs/sources_1/ip/ila_0/sim/ila_0.vhd,incdir="../../../../lab1.srcs/sources_1/ip/ila_0/hdl/verilog"
glbl.v,Verilog,xil_defaultlib,glbl.v
