------------------------------------------------------------------------------ 2020-02-06 Technical info DAT096 2020, by Christian Križan ------------------------------------------------------------------------------ This text file comprises annotations to the 2020-02-06 technical info lecture, mainly meant for those who cannot open and view annotations in .ppts. Also, I was somewhat unsatisfied with the .pdf container export. ------------------------------------------------------------------------------ SLIDE 1 Opening slide. SLIDE 2 General welcome slide. This lecture will, along with other content, cover the current company contract status (this part will be discussed further on in the lecture by Lena), what documentation has been added since last time, topics regarding up/downconversion - similar to what was discussed last time regarding the Ethernet communications module, questions and their answers, and finally introductory concepts to IQ mixing strategies for those who have never heard of the concept. SLIDE 3 The contract has been finished, the plan is that you sign it on the 7th of February. This is a modified Chalmers product development contract. I have taken the liberty to cut out sections of the contract that I believe is not relevant to this course, and many IMO excessive rights signed over to the company regarding what rights you have - and more inportantly, do not have. In the end, what you'll be signing in short is: - Mats is added as owner to the code. - Mats gets to take said code and use it for commercial purposes. - You are not to smack an OpenSource license onto the code and distribute it freely online, where competitors to Intermodulation Products may simply download your code and synthesise it for their own FPGA without buying the real deal. The detailed terms and conditions are handed out on this lecture for you to see until tomorrow. SLIDE 4 Since last time, there have been updates to the Canvas specification content. This includes, although is not limited to: - A document outlining a set of suggested development procedures, as well as hints on testing during the development of this device. This document also outlines what would be the minimal viable system as well as what your priorities would be during development. - What has been said during lectures / questioned about etc. has been added to the Module specification document. Yet again, if there is content missing - feel free to contact me so that I may forward it to the other groups. (- A student contract has been made.) - I have distributed the datasheets to the PHY chip on the Nexys 4, as well as the ADC/DAC on the Xilinx Ultrascale+ RFSoC. The latter is in fact a good read for anyone who wishes to get into data conversion. - The lecture slides have been annotated and uploaded onto Canvas. SLIDE 5 When designing, you will have to take a lot of decisions regarding for instance what frequencies to design for and the lot. It is highly relevant for this project that you are given a frequency set ansatz. The main goal is to aim for a constant frequency ratio when comparing stages in the target platform and the development one. SLIDE 6 Earlier, Mats and co. have noticed that clocking the central stream controller (or its previous equivalent) at 100 MHz have been insufficient for a sufficiently adequate datastream output. Meaning that the target platform must go much higher. Preferably, you should design for the fastest possible system you can get working on the development platform. SLIDE 7 If we look in the datasheet of the particular Artix 7 present on your development board, we can see that one of the most limiting factors when designing the central stream controller are the FIFOs at its periphery. These have a maximum operational frequency of 200 MHz. This in turn will serve as a benchmark for the target ratio on slide 9. SLIDE 8 In the earlier stages of your design, you could definitely design with a fixed clock frequency in mind. Although such designs tend to cut corners. When synthesising for the target platform, you will make it easier for everybody if you keep your design as generic as possible (considering operating frequencies) without making it too hard for your development. SLIDE 9 Comparing now the FIFOs of the central stream controller, we see that the target FPGA platform has a maximum FIFO clock frequency of 516 MHz. Let's keep it simple and say that this number is 500 MHz. Meaning, that your scale-up reference is 2.5 - frequencies and similar in the development design will end up 2.5 times larger in the final platform. IF this development platform, the Nexys 4, had a representative ADC/DAC, it would achieve an output sample rate of 1.6 GSa/s. In short, your IF stream rate will be 100 MHz. Your IQ mixers will upconvert with a factor of 2. Processing eight parallel samples will mean an effective sample throughput of the sought 1.6 GSa/s, as would be expected from scaling. SLIDE 10 So how do you achieve a 200 MHz clock when the main system clock is 100 MHz? Well, you will have to use one (or several) of the six included MMCM + PLL modules. These include some clever tricks to convert a clock rate to another. I strongly object to you designing your own MMCM + PLL loop, since this is available as an IP core configuration onboard. Also, unless I'm mistaken, the synthesis tool will know what to include from the hard-silicon circuitry - which might not be inferred from your design. Also, for reference, this IF stream rate will also be scaled with a factor of 2.5 on the target FPGA platform. Meaning that the target platform will have a central stream controller clocked at 250 MHz. But, it also has support for GMII (XGMII even?) - so don't think just yet that your data management will be easier because of this upscaling. SLIDE 11 Your teachers this far might have been rather adamant that the maximum clock frequency attainable on the Nexys 4 is 100 MHz. To this, I will quote two people from industry that "They may set the clock rate however they want" ... of course, there are upper bounds, ideating that you may not specify a 500 THz clock rate and get away with it. As you even se here, the internal clock rate is advertised far beyond the 100 MHz main system clock. SLIDE 12 We'll now head into filter territory. SLIDE 13 At seemingly random occasions, you will have to include filters in your design for a broad range of reasons. This is common in DSP work, and will certainly be required in your up-/downconversion stages. Be wary though of the risk that you may quickly run out of available space. Simple impulse response filters tend to be very large. The standard academic approach of interpolator -> FIR -> upconversion may be a consuming design choice. You will have to see yourselves what appears to be a good/bad design. To quote Mats, “A design based on interpolation + FIR + mixer is not normal in the business. You should look into CIC.” Do note that you may have to eventually move out of your comfort zone and start implementing new filter types. Slight hints for a CIC filter: these droop in the passband, commercial implementations tend to have additional compensating FIR filters attached to the FIR filter in order to compensate for its behaviour at various bands. One could imagine that IRL, an operator could compensate for this droop already at the host PC level. The operator could potentially apply some initial digital amplifier passband-effect in code. To be frank, I am myself unsure how I would implement this when writing a potential plug-in for the software we use to generate qubit control waveforms. So don't count on it. See rest of text in the slide. SLIDE 14 If I was a student in this project, I would want to know: what are the basic metrics I can use in order to get going? Well, that's a bit hard to say since we don't know what will be the limiting factors ourselves. But, to at least give some numbers: if you're starting out at a simple implementation with FIR filters and the lot that you have learned in previous courses, I would say go for a 0.1 dB ripple passband and an attenuation of -30 dB. SLIDE 15 Reading this paragraph took more time than reading the slide itself. SLIDE 16 To answer the question of IP blocks: *yes* - IP blocks, if included in Vivado, is perfectly fine in this project. Self-bought IP blocks, are not. SLIDE 17 See text in slide. SLIDE 18 In many applications you find online, you typically see that the IQ streams are combined back again to form some real signal. But, do keep in mind, that every data stream sample contains an I and Q component. This in turn will form what you need for the upconversion. And, on the way back, you'll acquire another I and Q stream. To iterate: the QPU is a passive device. See text in slide. SLIDE 19 The rest of these slides will introduce the IQ mixing field to those of you who have never experienced mixers, and the fact that we may move frequency content in the spectrum more-or-less freely. SLIDE 20 See text in slide. SLIDE 21 Let's imagine some signal at 100 kHz. The order of magnitude is not important. The Y-axis represents the amplitude of the signal. This signal is "real" - which means that the content to the right of the Y-axis must be mirrored (even) about the Y-axis. I like to think of it personally as cos(f) = cos(-f). (Commonly in literature, cos is used to describe real parts in signals.) SLIDE 22 These combined signals yield two new spikes in the spectrum after mixing. These new spurs will appear at the distance |0-IF| from the LO spike. Do note that their amplitudes have been halved. SLIDE 23 The normal real mixer is rather easy to explain using this picture. Do note that this mixer is for upconversion, ie. IF and LO are used as an input while RF outputs our mixed waveform. You'll see RF and IF switching roles in literature online, the reason being up/downconversion respectively. Please observe the multiplication cos*cos SLIDE 24 This slide is more important than you first may think. In the digital domain, mixing is just a multiplication. Unless you do something really interesting, this multiplication will be commutative across your entire signal path. Meaning that this multiplication does not have to happen were you'd typically expect it to (at "the end" of a typical upconversion). If you consider your signal, and draw it on paper, you see that you end up with the same result if you multiply the signal already at the beginning of said typical upconversion. And this is the whole point of so-called translation filters. SLIDE 25 See text in slide. SLIDE 26 A is in this image the "I + Q", it is a signal detailed by using the amplitude of the I component as the X-axis composant, and by using the Q component amplitude as the Y-axis composant. [Phi] is in turn the phase of "I + Q". Meaning also, that at no point can you probe your circuit with a dumb multimeter and read out the amplitude of A. A is a resulting vector from having the complete information in I and Q, without any of these components - you no longer have a complex representation. SLIDE 27 ... which allows for an incredible toolbox in signal processing. SLIDE 28 See text in slide. SLIDE 29 These ideas were meant to introduce you to the concept, and not to explain a deeply algebraic meaning. There is an incredible amount of content available that does a great job of introducing every detail that goes into the IQ concept. SLIDE 30 These slides represent a typical academic way of explaining frequency upconversion. Let's say that you start out with some frequency content as shown in (1). The sample rate is f_s. After a typical interpolator block at some higher sample rate, you'll end up duplicating the band content as shown in (2). At this stage, you typically have to filter out the additional content introduced in (2). A simple LP FIR would give us something like (3). Now, you are free to move this frequency content to some other frequency using a mixer. We do so, and now end up with (4). NOTE THAT THE AMPLITUDES DON'T CORRESPOND TO ACTUAL MIXING, this slide shows the standard academic approach to upconversion of interpolator + FIR + mixer. Should stage (3) be missing, do then note that all duplicated content will be moved to the new sample frequency. Do also note that the f_s still refers to the old sample frequency. f_new > 2*f_s in slide (4) - to satiate the Nyquist-Shannon theorem. SLIDE 31 Time for open-class questions, if you got any. Or send these to me at any time, krizan@chalmers.se SLIDE 32 Final slide.