// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
// Date        : Wed Apr  8 23:04:41 2020
// Host        : LAPTOP-RJQ3H7G3 running 64-bit major release  (build 9200)
// Command     : write_verilog -force -mode funcsim
//               D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/ip/mig/mig_sim_netlist.v
// Design      : mig
// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
//               or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device      : xc7a200tfbg676-2
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

(* NotValidForBitStream *)
module mig
   (ddr3_dq,
    ddr3_dqs_p,
    ddr3_dqs_n,
    ddr3_addr,
    ddr3_ba,
    ddr3_ras_n,
    ddr3_cas_n,
    ddr3_we_n,
    ddr3_reset_n,
    ddr3_ck_p,
    ddr3_ck_n,
    ddr3_cke,
    ddr3_cs_n,
    ddr3_dm,
    ddr3_odt,
    app_addr,
    app_cmd,
    app_en,
    app_wdf_data,
    app_wdf_end,
    app_wdf_mask,
    app_wdf_wren,
    app_rd_data,
    app_rd_data_end,
    app_rd_data_valid,
    app_rdy,
    app_wdf_rdy,
    app_sr_req,
    app_ref_req,
    app_zq_req,
    app_sr_active,
    app_ref_ack,
    app_zq_ack,
    ui_clk,
    ui_clk_sync_rst,
    init_calib_complete,
    sys_clk_p,
    sys_clk_n,
    clk_ref_i,
    device_temp,
    sys_rst);
  inout [63:0]ddr3_dq;
  inout [7:0]ddr3_dqs_p;
  inout [7:0]ddr3_dqs_n;
  output [13:0]ddr3_addr;
  output [2:0]ddr3_ba;
  output ddr3_ras_n;
  output ddr3_cas_n;
  output ddr3_we_n;
  output ddr3_reset_n;
  output [0:0]ddr3_ck_p;
  output [0:0]ddr3_ck_n;
  output [0:0]ddr3_cke;
  output [0:0]ddr3_cs_n;
  output [7:0]ddr3_dm;
  output [0:0]ddr3_odt;
  input [27:0]app_addr;
  input [2:0]app_cmd;
  input app_en;
  input [511:0]app_wdf_data;
  input app_wdf_end;
  input [63:0]app_wdf_mask;
  input app_wdf_wren;
  output [511:0]app_rd_data;
  output app_rd_data_end;
  output app_rd_data_valid;
  output app_rdy;
  output app_wdf_rdy;
  input app_sr_req;
  input app_ref_req;
  input app_zq_req;
  output app_sr_active;
  output app_ref_ack;
  output app_zq_ack;
  output ui_clk;
  output ui_clk_sync_rst;
  output init_calib_complete;
  input sys_clk_p;
  input sys_clk_n;
  input clk_ref_i;
  output [11:0]device_temp;
  input sys_rst;

  wire [27:0]app_addr;
  wire [2:0]app_cmd;
  wire app_en;
  wire [511:0]app_rd_data;
  wire app_rd_data_end;
  wire app_rd_data_valid;
  wire app_rdy;
  wire app_ref_ack;
  wire app_ref_req;
  wire app_sr_active;
  wire app_sr_req;
  wire [511:0]app_wdf_data;
  wire app_wdf_end;
  wire [63:0]app_wdf_mask;
  wire app_wdf_rdy;
  wire app_wdf_wren;
  wire app_zq_ack;
  wire app_zq_req;
  wire clk_ref_i;
  (* DRIVE = "12" *) (* SLEW = "SLOW" *) wire [13:0]ddr3_addr;
  (* DRIVE = "12" *) (* SLEW = "SLOW" *) wire [2:0]ddr3_ba;
  (* DRIVE = "12" *) (* SLEW = "SLOW" *) wire ddr3_cas_n;
  (* SLEW = "SLOW" *) wire [0:0]ddr3_ck_n;
  (* SLEW = "SLOW" *) wire [0:0]ddr3_ck_p;
  (* DRIVE = "12" *) (* SLEW = "SLOW" *) wire [0:0]ddr3_cke;
  (* DRIVE = "12" *) (* SLEW = "SLOW" *) wire [0:0]ddr3_cs_n;
  (* DRIVE = "12" *) (* SLEW = "SLOW" *) wire [7:0]ddr3_dm;
  (* DRIVE = "12" *) (* IBUF_LOW_PWR = 0 *) (* SLEW = "SLOW" *) wire [63:0]ddr3_dq;
  (* DIFF_TERM = 0 *) (* IBUF_LOW_PWR = 0 *) wire [7:0]ddr3_dqs_n;
  (* DIFF_TERM = 0 *) (* IBUF_LOW_PWR = 0 *) wire [7:0]ddr3_dqs_p;
  (* DRIVE = "12" *) (* SLEW = "SLOW" *) wire [0:0]ddr3_odt;
  (* DRIVE = "12" *) (* SLEW = "SLOW" *) wire ddr3_ras_n;
  (* DRIVE = "12" *) (* SLEW = "SLOW" *) wire ddr3_reset_n;
  (* DRIVE = "12" *) (* SLEW = "SLOW" *) wire ddr3_we_n;
  wire [11:0]device_temp;
  (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire init_calib_complete;
  (* DIFF_TERM = 0 *) (* IBUF_LOW_PWR = 0 *) wire sys_clk_n;
  (* DIFF_TERM = 0 *) (* IBUF_LOW_PWR = 0 *) wire sys_clk_p;
  wire sys_rst;
  wire \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/iserdes_clk ;
  wire \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/iserdes_clk ;
  wire \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk ;
  wire \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk ;
  wire \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/iserdes_clk ;
  wire \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/iserdes_clk ;
  wire \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk ;
  wire \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk ;
  wire ui_clk;
  wire ui_clk_sync_rst;

  mig_mig_mig u_mig_mig
       (.CLKB0(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/iserdes_clk ),
        .CLKB0_10(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/iserdes_clk ),
        .CLKB0_11(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/iserdes_clk ),
        .CLKB0_12(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk ),
        .CLKB0_13(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk ),
        .CLKB0_7(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/iserdes_clk ),
        .CLKB0_8(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk ),
        .CLKB0_9(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk ),
        .app_addr(app_addr[26:0]),
        .app_cmd(app_cmd[1:0]),
        .app_en(app_en),
        .app_rd_data_end(app_rd_data_end),
        .app_rd_data_valid(app_rd_data_valid),
        .app_rdy_r_reg(app_rdy),
        .app_ref_ack(app_ref_ack),
        .app_ref_req(app_ref_req),
        .app_sr_active(app_sr_active),
        .app_sr_req(app_sr_req),
        .app_wdf_data(app_wdf_data),
        .app_wdf_end(app_wdf_end),
        .app_wdf_mask(app_wdf_mask),
        .app_wdf_rdy(app_wdf_rdy),
        .app_wdf_wren(app_wdf_wren),
        .app_zq_ack(app_zq_ack),
        .app_zq_req(app_zq_req),
        .clk_ref_i(clk_ref_i),
        .ddr3_addr(ddr3_addr),
        .ddr3_ba(ddr3_ba),
        .ddr3_cas_n(ddr3_cas_n),
        .ddr3_cke(ddr3_cke),
        .ddr3_cs_n(ddr3_cs_n),
        .ddr3_dm(ddr3_dm),
        .ddr3_dq(ddr3_dq),
        .ddr3_dqs_n(ddr3_dqs_n),
        .ddr3_dqs_p(ddr3_dqs_p),
        .ddr3_odt(ddr3_odt),
        .ddr3_ras_n(ddr3_ras_n),
        .ddr3_reset_n(ddr3_reset_n),
        .ddr3_we_n(ddr3_we_n),
        .ddr_ck_out({ddr3_ck_n,ddr3_ck_p}),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] (app_rd_data[128]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 (app_rd_data[160]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] (app_rd_data[224]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 (app_rd_data[192]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] (app_rd_data[256]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 (app_rd_data[288]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] (app_rd_data[352]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 (app_rd_data[320]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] (app_rd_data[416]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 (app_rd_data[384]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] (app_rd_data[448]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 (app_rd_data[480]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] (app_rd_data[40]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 (app_rd_data[48]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 (app_rd_data[24]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 (app_rd_data[8]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_3 (app_rd_data[16]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_4 (app_rd_data[56]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_5 (app_rd_data[1]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_6 (app_rd_data[33]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] (app_rd_data[104]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 (app_rd_data[112]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 (app_rd_data[88]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2 (app_rd_data[72]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_3 (app_rd_data[80]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_4 (app_rd_data[120]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_5 (app_rd_data[65]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_6 (app_rd_data[97]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] (app_rd_data[136]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 (app_rd_data[144]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 (app_rd_data[184]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2 (app_rd_data[168]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_3 (app_rd_data[176]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_4 (app_rd_data[152]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_5 (app_rd_data[129]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_6 (app_rd_data[161]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] (app_rd_data[232]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 (app_rd_data[240]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 (app_rd_data[216]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2 (app_rd_data[200]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_3 (app_rd_data[208]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_4 (app_rd_data[248]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_5 (app_rd_data[193]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_6 (app_rd_data[225]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] (app_rd_data[264]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 (app_rd_data[272]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 (app_rd_data[312]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2 (app_rd_data[296]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_3 (app_rd_data[304]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_4 (app_rd_data[280]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_5 (app_rd_data[257]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_6 (app_rd_data[289]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] (app_rd_data[360]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 (app_rd_data[368]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 (app_rd_data[344]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2 (app_rd_data[328]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_3 (app_rd_data[336]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_4 (app_rd_data[376]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_5 (app_rd_data[321]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_6 (app_rd_data[353]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] (app_rd_data[424]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 (app_rd_data[432]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 (app_rd_data[408]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2 (app_rd_data[392]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_3 (app_rd_data[400]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_4 (app_rd_data[440]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_5 (app_rd_data[385]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_6 (app_rd_data[417]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] (app_rd_data[456]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 (app_rd_data[464]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 (app_rd_data[504]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2 (app_rd_data[488]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_3 (app_rd_data[496]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_4 (app_rd_data[472]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_5 (app_rd_data[449]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_6 (app_rd_data[481]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] (app_rd_data[9]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 (app_rd_data[17]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 (app_rd_data[57]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 (app_rd_data[41]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_3 (app_rd_data[49]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_4 (app_rd_data[25]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_5 (app_rd_data[2]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_6 (app_rd_data[34]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] (app_rd_data[73]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 (app_rd_data[81]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 (app_rd_data[121]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2 (app_rd_data[105]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_3 (app_rd_data[113]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_4 (app_rd_data[89]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_5 (app_rd_data[98]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_6 (app_rd_data[66]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] (app_rd_data[137]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 (app_rd_data[145]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 (app_rd_data[185]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2 (app_rd_data[169]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_3 (app_rd_data[177]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_4 (app_rd_data[153]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_5 (app_rd_data[162]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_6 (app_rd_data[130]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] (app_rd_data[201]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 (app_rd_data[209]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 (app_rd_data[249]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2 (app_rd_data[233]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_3 (app_rd_data[241]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_4 (app_rd_data[217]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_5 (app_rd_data[226]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_6 (app_rd_data[194]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] (app_rd_data[265]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 (app_rd_data[273]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 (app_rd_data[313]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2 (app_rd_data[297]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_3 (app_rd_data[305]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_4 (app_rd_data[281]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_5 (app_rd_data[258]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_6 (app_rd_data[290]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] (app_rd_data[329]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 (app_rd_data[337]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 (app_rd_data[377]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2 (app_rd_data[361]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_3 (app_rd_data[369]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_4 (app_rd_data[345]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_5 (app_rd_data[322]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_6 (app_rd_data[354]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] (app_rd_data[393]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 (app_rd_data[401]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 (app_rd_data[441]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2 (app_rd_data[425]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_3 (app_rd_data[433]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_4 (app_rd_data[409]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_5 (app_rd_data[386]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_6 (app_rd_data[418]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] (app_rd_data[457]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 (app_rd_data[465]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 (app_rd_data[505]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2 (app_rd_data[489]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_3 (app_rd_data[497]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_4 (app_rd_data[473]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_5 (app_rd_data[450]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_6 (app_rd_data[482]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] (app_rd_data[10]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 (app_rd_data[18]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 (app_rd_data[58]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 (app_rd_data[42]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_3 (app_rd_data[50]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_4 (app_rd_data[26]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_5 (app_rd_data[3]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_6 (app_rd_data[35]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] (app_rd_data[106]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 (app_rd_data[114]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 (app_rd_data[90]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2 (app_rd_data[74]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_3 (app_rd_data[82]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_4 (app_rd_data[122]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_5 (app_rd_data[67]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_6 (app_rd_data[99]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] (app_rd_data[170]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 (app_rd_data[178]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 (app_rd_data[154]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2 (app_rd_data[138]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_3 (app_rd_data[146]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_4 (app_rd_data[186]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_5 (app_rd_data[131]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_6 (app_rd_data[163]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] (app_rd_data[234]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 (app_rd_data[242]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 (app_rd_data[218]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2 (app_rd_data[202]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_3 (app_rd_data[210]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_4 (app_rd_data[250]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_5 (app_rd_data[195]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_6 (app_rd_data[227]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] (app_rd_data[266]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 (app_rd_data[274]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 (app_rd_data[314]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2 (app_rd_data[298]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_3 (app_rd_data[306]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_4 (app_rd_data[282]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_5 (app_rd_data[259]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_6 (app_rd_data[291]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] (app_rd_data[330]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 (app_rd_data[338]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 (app_rd_data[378]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2 (app_rd_data[362]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_3 (app_rd_data[370]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_4 (app_rd_data[346]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_5 (app_rd_data[323]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_6 (app_rd_data[355]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] (app_rd_data[394]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 (app_rd_data[402]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 (app_rd_data[442]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2 (app_rd_data[426]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_3 (app_rd_data[434]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_4 (app_rd_data[410]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_5 (app_rd_data[387]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_6 (app_rd_data[419]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] (app_rd_data[458]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 (app_rd_data[466]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 (app_rd_data[506]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2 (app_rd_data[490]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_3 (app_rd_data[498]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_4 (app_rd_data[474]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_5 (app_rd_data[451]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_6 (app_rd_data[483]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] (app_rd_data[11]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 (app_rd_data[19]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 (app_rd_data[59]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 (app_rd_data[43]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_3 (app_rd_data[51]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_4 (app_rd_data[27]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_5 (app_rd_data[36]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_6 (app_rd_data[4]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] (app_rd_data[75]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 (app_rd_data[83]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 (app_rd_data[123]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2 (app_rd_data[107]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_3 (app_rd_data[115]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_4 (app_rd_data[91]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_5 (app_rd_data[100]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_6 (app_rd_data[68]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] (app_rd_data[139]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 (app_rd_data[147]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 (app_rd_data[187]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2 (app_rd_data[171]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_3 (app_rd_data[179]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_4 (app_rd_data[155]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_5 (app_rd_data[164]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_6 (app_rd_data[132]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] (app_rd_data[203]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 (app_rd_data[211]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 (app_rd_data[251]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2 (app_rd_data[235]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_3 (app_rd_data[243]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_4 (app_rd_data[219]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_5 (app_rd_data[228]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_6 (app_rd_data[196]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] (app_rd_data[267]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 (app_rd_data[275]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 (app_rd_data[315]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2 (app_rd_data[299]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_3 (app_rd_data[307]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_4 (app_rd_data[283]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_5 (app_rd_data[292]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_6 (app_rd_data[260]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] (app_rd_data[331]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 (app_rd_data[339]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 (app_rd_data[379]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2 (app_rd_data[363]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_3 (app_rd_data[371]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_4 (app_rd_data[347]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_5 (app_rd_data[356]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_6 (app_rd_data[324]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] (app_rd_data[395]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 (app_rd_data[403]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 (app_rd_data[443]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2 (app_rd_data[427]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_3 (app_rd_data[435]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_4 (app_rd_data[411]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_5 (app_rd_data[420]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_6 (app_rd_data[388]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] (app_rd_data[459]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 (app_rd_data[467]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 (app_rd_data[507]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2 (app_rd_data[491]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_3 (app_rd_data[499]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_4 (app_rd_data[475]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_5 (app_rd_data[452]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_6 (app_rd_data[484]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] (app_rd_data[44]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 (app_rd_data[52]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 (app_rd_data[28]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 (app_rd_data[12]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3 (app_rd_data[20]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_4 (app_rd_data[60]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_5 (app_rd_data[5]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_6 (app_rd_data[37]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] (app_rd_data[108]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 (app_rd_data[116]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 (app_rd_data[92]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2 (app_rd_data[76]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_3 (app_rd_data[84]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_4 (app_rd_data[124]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_5 (app_rd_data[69]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_6 (app_rd_data[101]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] (app_rd_data[172]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 (app_rd_data[180]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 (app_rd_data[156]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2 (app_rd_data[140]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_3 (app_rd_data[148]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_4 (app_rd_data[188]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_5 (app_rd_data[133]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_6 (app_rd_data[165]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] (app_rd_data[236]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 (app_rd_data[244]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 (app_rd_data[220]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2 (app_rd_data[204]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_3 (app_rd_data[212]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_4 (app_rd_data[252]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_5 (app_rd_data[197]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_6 (app_rd_data[229]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] (app_rd_data[300]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 (app_rd_data[308]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 (app_rd_data[284]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2 (app_rd_data[268]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_3 (app_rd_data[276]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_4 (app_rd_data[316]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_5 (app_rd_data[261]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_6 (app_rd_data[293]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] (app_rd_data[364]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 (app_rd_data[372]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 (app_rd_data[348]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2 (app_rd_data[332]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_3 (app_rd_data[340]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_4 (app_rd_data[380]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_5 (app_rd_data[325]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_6 (app_rd_data[357]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] (app_rd_data[428]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 (app_rd_data[436]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 (app_rd_data[412]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2 (app_rd_data[396]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_3 (app_rd_data[404]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_4 (app_rd_data[444]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_5 (app_rd_data[389]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_6 (app_rd_data[421]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] (app_rd_data[460]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 (app_rd_data[468]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 (app_rd_data[508]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2 (app_rd_data[492]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_3 (app_rd_data[500]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_4 (app_rd_data[476]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_5 (app_rd_data[453]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_6 (app_rd_data[485]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] (app_rd_data[13]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 (app_rd_data[21]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 (app_rd_data[61]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 (app_rd_data[45]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_3 (app_rd_data[53]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_4 (app_rd_data[29]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_5 (app_rd_data[6]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_6 (app_rd_data[38]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] (app_rd_data[77]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 (app_rd_data[85]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 (app_rd_data[125]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2 (app_rd_data[109]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_3 (app_rd_data[117]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_4 (app_rd_data[93]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_5 (app_rd_data[70]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_6 (app_rd_data[102]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] (app_rd_data[141]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 (app_rd_data[149]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 (app_rd_data[189]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2 (app_rd_data[173]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_3 (app_rd_data[181]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_4 (app_rd_data[157]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_5 (app_rd_data[134]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_6 (app_rd_data[166]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] (app_rd_data[205]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 (app_rd_data[213]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 (app_rd_data[253]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2 (app_rd_data[237]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_3 (app_rd_data[245]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_4 (app_rd_data[221]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_5 (app_rd_data[198]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_6 (app_rd_data[230]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] (app_rd_data[269]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 (app_rd_data[277]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 (app_rd_data[317]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2 (app_rd_data[301]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_3 (app_rd_data[309]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_4 (app_rd_data[285]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_5 (app_rd_data[262]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_6 (app_rd_data[294]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] (app_rd_data[333]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 (app_rd_data[341]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 (app_rd_data[381]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2 (app_rd_data[365]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_3 (app_rd_data[373]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_4 (app_rd_data[349]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_5 (app_rd_data[326]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_6 (app_rd_data[358]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] (app_rd_data[397]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 (app_rd_data[405]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 (app_rd_data[445]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2 (app_rd_data[429]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_3 (app_rd_data[437]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_4 (app_rd_data[413]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_5 (app_rd_data[390]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_6 (app_rd_data[422]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] (app_rd_data[461]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 (app_rd_data[469]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 (app_rd_data[509]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2 (app_rd_data[493]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_3 (app_rd_data[501]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_4 (app_rd_data[477]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_5 (app_rd_data[454]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_6 (app_rd_data[486]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] (app_rd_data[14]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 (app_rd_data[22]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 (app_rd_data[62]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2 (app_rd_data[46]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_3 (app_rd_data[54]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_4 (app_rd_data[30]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] (app_rd_data[78]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 (app_rd_data[86]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 (app_rd_data[126]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2 (app_rd_data[110]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_3 (app_rd_data[118]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_4 (app_rd_data[94]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] (app_rd_data[142]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 (app_rd_data[150]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 (app_rd_data[190]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_2 (app_rd_data[174]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_3 (app_rd_data[182]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_4 (app_rd_data[158]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] (app_rd_data[206]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 (app_rd_data[214]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 (app_rd_data[254]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_2 (app_rd_data[238]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_3 (app_rd_data[246]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_4 (app_rd_data[222]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] (app_rd_data[270]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 (app_rd_data[278]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 (app_rd_data[318]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_2 (app_rd_data[302]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_3 (app_rd_data[310]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_4 (app_rd_data[286]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] (app_rd_data[334]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 (app_rd_data[342]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 (app_rd_data[382]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_2 (app_rd_data[366]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_3 (app_rd_data[374]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_4 (app_rd_data[350]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] (app_rd_data[398]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 (app_rd_data[406]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 (app_rd_data[446]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_2 (app_rd_data[430]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_3 (app_rd_data[438]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_4 (app_rd_data[414]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] (app_rd_data[462]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 (app_rd_data[470]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 (app_rd_data[510]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_2 (app_rd_data[494]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_3 (app_rd_data[502]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_4 (app_rd_data[478]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] (app_rd_data[15]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 (app_rd_data[23]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1 (app_rd_data[63]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_2 (app_rd_data[7]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_3 (app_rd_data[47]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_4 (app_rd_data[55]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_5 (app_rd_data[31]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_6 (app_rd_data[39]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] (app_rd_data[79]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 (app_rd_data[87]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1 (app_rd_data[127]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_2 (app_rd_data[71]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_3 (app_rd_data[111]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_4 (app_rd_data[119]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_5 (app_rd_data[95]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_6 (app_rd_data[103]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] (app_rd_data[143]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 (app_rd_data[151]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1 (app_rd_data[191]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_2 (app_rd_data[135]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_3 (app_rd_data[175]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_4 (app_rd_data[183]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_5 (app_rd_data[159]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_6 (app_rd_data[167]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] (app_rd_data[207]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 (app_rd_data[215]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1 (app_rd_data[255]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_2 (app_rd_data[199]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_3 (app_rd_data[239]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_4 (app_rd_data[247]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_5 (app_rd_data[223]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_6 (app_rd_data[231]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] (app_rd_data[271]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 (app_rd_data[279]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1 (app_rd_data[319]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_2 (app_rd_data[263]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_3 (app_rd_data[303]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_4 (app_rd_data[311]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_5 (app_rd_data[287]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_6 (app_rd_data[295]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] (app_rd_data[335]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 (app_rd_data[343]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1 (app_rd_data[383]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_2 (app_rd_data[327]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_3 (app_rd_data[367]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_4 (app_rd_data[375]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_5 (app_rd_data[351]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_6 (app_rd_data[359]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] (app_rd_data[399]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 (app_rd_data[407]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1 (app_rd_data[447]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_2 (app_rd_data[391]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_3 (app_rd_data[431]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_4 (app_rd_data[439]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_5 (app_rd_data[415]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_6 (app_rd_data[423]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] (app_rd_data[463]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 (app_rd_data[471]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1 (app_rd_data[511]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2 (app_rd_data[455]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_3 (app_rd_data[495]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_4 (app_rd_data[503]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_5 (app_rd_data[479]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_6 (app_rd_data[487]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] (app_rd_data[32]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 (app_rd_data[0]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] (app_rd_data[96]),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 (app_rd_data[64]),
        .\gen_mmcm.mmcm_i (ui_clk),
        .init_calib_complete(init_calib_complete),
        .iserdes_clk(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/iserdes_clk ),
        .iserdes_clk_0(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/iserdes_clk ),
        .iserdes_clk_1(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk ),
        .iserdes_clk_2(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk ),
        .iserdes_clk_3(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/iserdes_clk ),
        .iserdes_clk_4(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/iserdes_clk ),
        .iserdes_clk_5(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/iserdes_clk ),
        .iserdes_clk_6(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/iserdes_clk ),
        .out(device_temp),
        .rstdiv0_sync_r1_reg_rep(ui_clk_sync_rst),
        .sys_clk_n(sys_clk_n),
        .sys_clk_p(sys_clk_p),
        .sys_rst(sys_rst));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_arb_mux" *) 
module mig_mig_7series_v4_2_arb_mux
   (granted_row_r_reg,
    granted_col_r_reg,
    insert_maint_r1_lcl_reg,
    \pre_4_1_1T_arb.granted_pre_r_reg ,
    DIC,
    col_rd_wr,
    cke_r,
    rnk_config_valid_r_lcl_reg,
    \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] ,
    \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] ,
    \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17] ,
    granted_col_r_reg_0,
    \grant_r_reg[2] ,
    \periodic_rd_generation.read_this_rank_r_reg ,
    Q,
    \periodic_rd_generation.read_this_rank ,
    mc_odt_ns,
    D,
    granted_col_r_reg_1,
    granted_col_r_reg_2,
    E,
    \rtw_timer.rtw_cnt_r_reg[1] ,
    \grant_r_reg[0] ,
    \wr_this_rank_r_reg[0] ,
    \wr_this_rank_r_reg[0]_0 ,
    \grant_r_reg[3] ,
    mc_we_n_ns,
    \grant_r_reg[3]_0 ,
    mc_cas_n_ns,
    mc_ras_n_ns,
    \pre_4_1_1T_arb.granted_pre_r_reg_0 ,
    \pre_4_1_1T_arb.granted_pre_r_reg_1 ,
    mc_cs_n_ns,
    \grant_r_reg[1] ,
    \rnk_config_strobe_r_reg[0] ,
    rnk_config_valid_r_lcl_reg_0,
    rnk_config_valid_r_lcl_reg_1,
    rnk_config_valid_r_lcl_reg_2,
    rnk_config_valid_r_lcl_reg_3,
    override_demand_ns,
    \grant_r_reg[0]_0 ,
    \grant_r_reg[3]_1 ,
    \last_master_r_reg[3] ,
    col_wr_data_buf_addr,
    act_this_rank,
    \grant_r_reg[0]_1 ,
    req_bank_rdy_r_reg,
    \rtw_timer.rtw_cnt_r_reg[1]_0 ,
    \wtr_timer.wtr_cnt_r_reg[1] ,
    \grant_r_reg[0]_2 ,
    cke_r_reg,
    rnk_config_strobe_ns,
    granted_col_ns,
    insert_maint_r1_lcl_reg_0,
    \pre_4_1_1T_arb.granted_pre_ns ,
    cke_r_reg_0,
    mc_cke_ns,
    SR,
    rnk_config_valid_r_lcl_reg_4,
    \cmd_pipe_plus.mc_data_offset_reg[5] ,
    \cmd_pipe_plus.mc_data_offset_1_reg[5] ,
    \cmd_pipe_plus.mc_data_offset_2_reg[5] ,
    \grant_r_reg[0]_3 ,
    \grant_r_reg[0]_4 ,
    \grant_r_reg[2]_0 ,
    \grant_r_reg[0]_5 ,
    \grant_r_reg[3]_2 ,
    granted_row_r_reg_0,
    \grant_r_reg[3]_3 ,
    \periodic_rd_generation.read_this_rank_r ,
    rd_this_rank_r,
    req_periodic_rd_r,
    \rtw_timer.rtw_cnt_r_reg[0] ,
    \cmd_pipe_plus.mc_odt_reg[0] ,
    \rtw_timer.rtw_cnt_r_reg[1]_1 ,
    \cmd_pipe_plus.mc_data_offset_2_reg[0] ,
    \cmd_pipe_plus.mc_data_offset_2_reg[0]_0 ,
    i___22_i_1,
    rd_wr_r,
    wr_this_rank_r,
    \grant_r[3]_i_8 ,
    \grant_r[3]_i_8_0 ,
    \cmd_pipe_plus.mc_we_n_reg[0] ,
    \cmd_pipe_plus.mc_we_n_reg[0]_0 ,
    \cmd_pipe_plus.mc_address_reg[0] ,
    \cmd_pipe_plus.mc_cas_n_reg[0] ,
    maint_zq_r,
    maint_srx_r,
    \cmd_pipe_plus.mc_bank_reg[2] ,
    \cmd_pipe_plus.mc_address_reg[3] ,
    \cmd_pipe_plus.mc_bank_reg[2]_0 ,
    \cmd_pipe_plus.mc_address_reg[0]_0 ,
    \cmd_pipe_plus.mc_bank_reg[2]_1 ,
    \cmd_pipe_plus.mc_bank_reg[8] ,
    \cmd_pipe_plus.mc_address_reg[41] ,
    req_row_r,
    \cmd_pipe_plus.mc_address_reg[10] ,
    \cmd_pipe_plus.mc_address_reg[10]_0 ,
    \cmd_pipe_plus.mc_we_n_reg[0]_1 ,
    \cmd_pipe_plus.mc_we_n_reg[2] ,
    \grant_r_reg[0]_6 ,
    \grant_r_reg[0]_7 ,
    \grant_r_reg[0]_8 ,
    \grant_r_reg[1]_0 ,
    \grant_r_reg[3]_4 ,
    \grant_r_reg[3]_5 ,
    ofs_rdy_r,
    ofs_rdy_r_0,
    ofs_rdy_r_1,
    ofs_rdy_r_2,
    inhbt_act_faw_r,
    req_data_buf_addr_r,
    \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ,
    act_this_rank_r,
    \cmd_pipe_plus.mc_address_reg[23] ,
    \cmd_pipe_plus.mc_address_reg[23]_0 ,
    \cmd_pipe_plus.mc_address_reg[23]_1 ,
    \cmd_pipe_plus.mc_address_reg[23]_2 ,
    \cmd_pipe_plus.mc_address_reg[24] ,
    \cmd_pipe_plus.mc_address_reg[24]_0 ,
    \cmd_pipe_plus.mc_address_reg[24]_1 ,
    \cmd_pipe_plus.mc_address_reg[24]_2 ,
    \cmd_pipe_plus.mc_address_reg[38] ,
    req_bank_rdy_r,
    \grant_r[2]_i_3 ,
    \grant_r[2]_i_3_0 );
  output granted_row_r_reg;
  output granted_col_r_reg;
  output insert_maint_r1_lcl_reg;
  output \pre_4_1_1T_arb.granted_pre_r_reg ;
  output [0:0]DIC;
  output col_rd_wr;
  output cke_r;
  output rnk_config_valid_r_lcl_reg;
  output [3:0]\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] ;
  output [3:0]\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] ;
  output [3:0]\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17] ;
  output granted_col_r_reg_0;
  output \grant_r_reg[2] ;
  output \periodic_rd_generation.read_this_rank_r_reg ;
  output [3:0]Q;
  output \periodic_rd_generation.read_this_rank ;
  output [0:0]mc_odt_ns;
  output [0:0]D;
  output [0:0]granted_col_r_reg_1;
  output [0:0]granted_col_r_reg_2;
  output [0:0]E;
  output [1:0]\rtw_timer.rtw_cnt_r_reg[1] ;
  output \grant_r_reg[0] ;
  output \wr_this_rank_r_reg[0] ;
  output \wr_this_rank_r_reg[0]_0 ;
  output \grant_r_reg[3] ;
  output [1:0]mc_we_n_ns;
  output [3:0]\grant_r_reg[3]_0 ;
  output [2:0]mc_cas_n_ns;
  output [1:0]mc_ras_n_ns;
  output [8:0]\pre_4_1_1T_arb.granted_pre_r_reg_0 ;
  output [38:0]\pre_4_1_1T_arb.granted_pre_r_reg_1 ;
  output [0:0]mc_cs_n_ns;
  output \grant_r_reg[1] ;
  output \rnk_config_strobe_r_reg[0] ;
  output rnk_config_valid_r_lcl_reg_0;
  output rnk_config_valid_r_lcl_reg_1;
  output rnk_config_valid_r_lcl_reg_2;
  output rnk_config_valid_r_lcl_reg_3;
  output override_demand_ns;
  output \grant_r_reg[0]_0 ;
  output [3:0]\grant_r_reg[3]_1 ;
  output [0:0]\last_master_r_reg[3] ;
  output [3:0]col_wr_data_buf_addr;
  output act_this_rank;
  output \grant_r_reg[0]_1 ;
  output req_bank_rdy_r_reg;
  output \rtw_timer.rtw_cnt_r_reg[1]_0 ;
  output \wtr_timer.wtr_cnt_r_reg[1] ;
  output \grant_r_reg[0]_2 ;
  input cke_r_reg;
  input rnk_config_strobe_ns;
  input granted_col_ns;
  input insert_maint_r1_lcl_reg_0;
  input \pre_4_1_1T_arb.granted_pre_ns ;
  input cke_r_reg_0;
  input [0:0]mc_cke_ns;
  input [0:0]SR;
  input rnk_config_valid_r_lcl_reg_4;
  input [5:0]\cmd_pipe_plus.mc_data_offset_reg[5] ;
  input [5:0]\cmd_pipe_plus.mc_data_offset_1_reg[5] ;
  input [5:0]\cmd_pipe_plus.mc_data_offset_2_reg[5] ;
  input \grant_r_reg[0]_3 ;
  input \grant_r_reg[0]_4 ;
  input \grant_r_reg[2]_0 ;
  input \grant_r_reg[0]_5 ;
  input \grant_r_reg[3]_2 ;
  input granted_row_r_reg_0;
  input \grant_r_reg[3]_3 ;
  input \periodic_rd_generation.read_this_rank_r ;
  input [3:0]rd_this_rank_r;
  input [3:0]req_periodic_rd_r;
  input \rtw_timer.rtw_cnt_r_reg[0] ;
  input \cmd_pipe_plus.mc_odt_reg[0] ;
  input [1:0]\rtw_timer.rtw_cnt_r_reg[1]_1 ;
  input \cmd_pipe_plus.mc_data_offset_2_reg[0] ;
  input \cmd_pipe_plus.mc_data_offset_2_reg[0]_0 ;
  input i___22_i_1;
  input [0:0]rd_wr_r;
  input [3:0]wr_this_rank_r;
  input \grant_r[3]_i_8 ;
  input \grant_r[3]_i_8_0 ;
  input \cmd_pipe_plus.mc_we_n_reg[0] ;
  input \cmd_pipe_plus.mc_we_n_reg[0]_0 ;
  input \cmd_pipe_plus.mc_address_reg[0] ;
  input \cmd_pipe_plus.mc_cas_n_reg[0] ;
  input maint_zq_r;
  input maint_srx_r;
  input [2:0]\cmd_pipe_plus.mc_bank_reg[2] ;
  input \cmd_pipe_plus.mc_address_reg[3] ;
  input [2:0]\cmd_pipe_plus.mc_bank_reg[2]_0 ;
  input \cmd_pipe_plus.mc_address_reg[0]_0 ;
  input [2:0]\cmd_pipe_plus.mc_bank_reg[2]_1 ;
  input [2:0]\cmd_pipe_plus.mc_bank_reg[8] ;
  input [19:0]\cmd_pipe_plus.mc_address_reg[41] ;
  input [34:0]req_row_r;
  input \cmd_pipe_plus.mc_address_reg[10] ;
  input \cmd_pipe_plus.mc_address_reg[10]_0 ;
  input \cmd_pipe_plus.mc_we_n_reg[0]_1 ;
  input \cmd_pipe_plus.mc_we_n_reg[2] ;
  input \grant_r_reg[0]_6 ;
  input \grant_r_reg[0]_7 ;
  input \grant_r_reg[0]_8 ;
  input \grant_r_reg[1]_0 ;
  input \grant_r_reg[3]_4 ;
  input \grant_r_reg[3]_5 ;
  input ofs_rdy_r;
  input ofs_rdy_r_0;
  input ofs_rdy_r_1;
  input ofs_rdy_r_2;
  input inhbt_act_faw_r;
  input [15:0]req_data_buf_addr_r;
  input [3:0]\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ;
  input [3:0]act_this_rank_r;
  input [9:0]\cmd_pipe_plus.mc_address_reg[23] ;
  input [9:0]\cmd_pipe_plus.mc_address_reg[23]_0 ;
  input [9:0]\cmd_pipe_plus.mc_address_reg[23]_1 ;
  input [9:0]\cmd_pipe_plus.mc_address_reg[23]_2 ;
  input \cmd_pipe_plus.mc_address_reg[24] ;
  input \cmd_pipe_plus.mc_address_reg[24]_0 ;
  input \cmd_pipe_plus.mc_address_reg[24]_1 ;
  input \cmd_pipe_plus.mc_address_reg[24]_2 ;
  input \cmd_pipe_plus.mc_address_reg[38] ;
  input req_bank_rdy_r;
  input \grant_r[2]_i_3 ;
  input [0:0]\grant_r[2]_i_3_0 ;

  wire [0:0]D;
  wire [0:0]DIC;
  wire [0:0]E;
  wire [3:0]Q;
  wire [0:0]SR;
  wire act_this_rank;
  wire [3:0]act_this_rank_r;
  wire cke_r;
  wire cke_r_reg;
  wire cke_r_reg_0;
  wire \cmd_pipe_plus.mc_address_reg[0] ;
  wire \cmd_pipe_plus.mc_address_reg[0]_0 ;
  wire \cmd_pipe_plus.mc_address_reg[10] ;
  wire \cmd_pipe_plus.mc_address_reg[10]_0 ;
  wire [9:0]\cmd_pipe_plus.mc_address_reg[23] ;
  wire [9:0]\cmd_pipe_plus.mc_address_reg[23]_0 ;
  wire [9:0]\cmd_pipe_plus.mc_address_reg[23]_1 ;
  wire [9:0]\cmd_pipe_plus.mc_address_reg[23]_2 ;
  wire \cmd_pipe_plus.mc_address_reg[24] ;
  wire \cmd_pipe_plus.mc_address_reg[24]_0 ;
  wire \cmd_pipe_plus.mc_address_reg[24]_1 ;
  wire \cmd_pipe_plus.mc_address_reg[24]_2 ;
  wire \cmd_pipe_plus.mc_address_reg[38] ;
  wire \cmd_pipe_plus.mc_address_reg[3] ;
  wire [19:0]\cmd_pipe_plus.mc_address_reg[41] ;
  wire [2:0]\cmd_pipe_plus.mc_bank_reg[2] ;
  wire [2:0]\cmd_pipe_plus.mc_bank_reg[2]_0 ;
  wire [2:0]\cmd_pipe_plus.mc_bank_reg[2]_1 ;
  wire [2:0]\cmd_pipe_plus.mc_bank_reg[8] ;
  wire \cmd_pipe_plus.mc_cas_n_reg[0] ;
  wire [5:0]\cmd_pipe_plus.mc_data_offset_1_reg[5] ;
  wire \cmd_pipe_plus.mc_data_offset_2_reg[0] ;
  wire \cmd_pipe_plus.mc_data_offset_2_reg[0]_0 ;
  wire [5:0]\cmd_pipe_plus.mc_data_offset_2_reg[5] ;
  wire [5:0]\cmd_pipe_plus.mc_data_offset_reg[5] ;
  wire \cmd_pipe_plus.mc_odt_reg[0] ;
  wire \cmd_pipe_plus.mc_we_n_reg[0] ;
  wire \cmd_pipe_plus.mc_we_n_reg[0]_0 ;
  wire \cmd_pipe_plus.mc_we_n_reg[0]_1 ;
  wire \cmd_pipe_plus.mc_we_n_reg[2] ;
  wire \col_mux.col_periodic_rd_r ;
  wire col_rd_wr;
  wire col_rd_wr_r;
  wire [3:0]col_wr_data_buf_addr;
  wire [3:0]\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ;
  wire \grant_r[2]_i_3 ;
  wire [0:0]\grant_r[2]_i_3_0 ;
  wire \grant_r[3]_i_8 ;
  wire \grant_r[3]_i_8_0 ;
  wire \grant_r_reg[0] ;
  wire \grant_r_reg[0]_0 ;
  wire \grant_r_reg[0]_1 ;
  wire \grant_r_reg[0]_2 ;
  wire \grant_r_reg[0]_3 ;
  wire \grant_r_reg[0]_4 ;
  wire \grant_r_reg[0]_5 ;
  wire \grant_r_reg[0]_6 ;
  wire \grant_r_reg[0]_7 ;
  wire \grant_r_reg[0]_8 ;
  wire \grant_r_reg[1] ;
  wire \grant_r_reg[1]_0 ;
  wire \grant_r_reg[2] ;
  wire \grant_r_reg[2]_0 ;
  wire \grant_r_reg[3] ;
  wire [3:0]\grant_r_reg[3]_0 ;
  wire [3:0]\grant_r_reg[3]_1 ;
  wire \grant_r_reg[3]_2 ;
  wire \grant_r_reg[3]_3 ;
  wire \grant_r_reg[3]_4 ;
  wire \grant_r_reg[3]_5 ;
  wire granted_col_ns;
  wire granted_col_r_reg;
  wire granted_col_r_reg_0;
  wire [0:0]granted_col_r_reg_1;
  wire [0:0]granted_col_r_reg_2;
  wire granted_row_r_reg;
  wire granted_row_r_reg_0;
  wire i___22_i_1;
  wire inhbt_act_faw_r;
  wire insert_maint_r1_lcl_reg;
  wire insert_maint_r1_lcl_reg_0;
  wire [0:0]\last_master_r_reg[3] ;
  wire maint_srx_r;
  wire maint_zq_r;
  wire [2:0]mc_cas_n_ns;
  wire [0:0]mc_cke_ns;
  wire [0:0]mc_cs_n_ns;
  wire [3:3]mc_data_offset1;
  wire [3:3]mc_data_offset_11;
  wire [3:3]mc_data_offset_21;
  wire [0:0]mc_odt_ns;
  wire [1:0]mc_ras_n_ns;
  wire [1:0]mc_we_n_ns;
  wire ofs_rdy_r;
  wire ofs_rdy_r_0;
  wire ofs_rdy_r_1;
  wire ofs_rdy_r_2;
  wire override_demand_ns;
  wire \periodic_rd_generation.read_this_rank ;
  wire \periodic_rd_generation.read_this_rank_r ;
  wire \periodic_rd_generation.read_this_rank_r_reg ;
  wire \pre_4_1_1T_arb.granted_pre_ns ;
  wire \pre_4_1_1T_arb.granted_pre_r_reg ;
  wire [8:0]\pre_4_1_1T_arb.granted_pre_r_reg_0 ;
  wire [38:0]\pre_4_1_1T_arb.granted_pre_r_reg_1 ;
  wire [3:0]\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] ;
  wire [3:0]\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] ;
  wire [3:0]\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17] ;
  wire [3:0]rd_this_rank_r;
  wire [0:0]rd_wr_r;
  wire req_bank_rdy_r;
  wire req_bank_rdy_r_reg;
  wire [15:0]req_data_buf_addr_r;
  wire [3:0]req_periodic_rd_r;
  wire [34:0]req_row_r;
  wire rnk_config_strobe_ns;
  wire \rnk_config_strobe_r_reg[0] ;
  wire rnk_config_valid_r_lcl_reg;
  wire rnk_config_valid_r_lcl_reg_0;
  wire rnk_config_valid_r_lcl_reg_1;
  wire rnk_config_valid_r_lcl_reg_2;
  wire rnk_config_valid_r_lcl_reg_3;
  wire rnk_config_valid_r_lcl_reg_4;
  wire \rtw_timer.rtw_cnt_r_reg[0] ;
  wire [1:0]\rtw_timer.rtw_cnt_r_reg[1] ;
  wire \rtw_timer.rtw_cnt_r_reg[1]_0 ;
  wire [1:0]\rtw_timer.rtw_cnt_r_reg[1]_1 ;
  wire [3:0]wr_this_rank_r;
  wire \wr_this_rank_r_reg[0] ;
  wire \wr_this_rank_r_reg[0]_0 ;
  wire \wtr_timer.wtr_cnt_r_reg[1] ;

  mig_mig_7series_v4_2_arb_row_col arb_row_col0
       (.D(D),
        .DIC(DIC),
        .E(E),
        .O(mc_data_offset_21),
        .Q(Q),
        .SR(SR),
        .act_this_rank(act_this_rank),
        .act_this_rank_r(act_this_rank_r),
        .\cmd_pipe_plus.mc_address_reg[0] (\cmd_pipe_plus.mc_address_reg[0] ),
        .\cmd_pipe_plus.mc_address_reg[0]_0 (\cmd_pipe_plus.mc_address_reg[0]_0 ),
        .\cmd_pipe_plus.mc_address_reg[10] (\cmd_pipe_plus.mc_address_reg[10] ),
        .\cmd_pipe_plus.mc_address_reg[10]_0 (\cmd_pipe_plus.mc_address_reg[10]_0 ),
        .\cmd_pipe_plus.mc_address_reg[23] (\cmd_pipe_plus.mc_address_reg[23] ),
        .\cmd_pipe_plus.mc_address_reg[23]_0 (\cmd_pipe_plus.mc_address_reg[23]_0 ),
        .\cmd_pipe_plus.mc_address_reg[23]_1 (\cmd_pipe_plus.mc_address_reg[23]_1 ),
        .\cmd_pipe_plus.mc_address_reg[23]_2 (\cmd_pipe_plus.mc_address_reg[23]_2 ),
        .\cmd_pipe_plus.mc_address_reg[24] (\cmd_pipe_plus.mc_address_reg[24] ),
        .\cmd_pipe_plus.mc_address_reg[24]_0 (\cmd_pipe_plus.mc_address_reg[24]_0 ),
        .\cmd_pipe_plus.mc_address_reg[24]_1 (\cmd_pipe_plus.mc_address_reg[24]_1 ),
        .\cmd_pipe_plus.mc_address_reg[24]_2 (\cmd_pipe_plus.mc_address_reg[24]_2 ),
        .\cmd_pipe_plus.mc_address_reg[38] (\cmd_pipe_plus.mc_address_reg[38] ),
        .\cmd_pipe_plus.mc_address_reg[3] (\cmd_pipe_plus.mc_address_reg[3] ),
        .\cmd_pipe_plus.mc_address_reg[41] (\cmd_pipe_plus.mc_address_reg[41] ),
        .\cmd_pipe_plus.mc_bank_reg[2] (\cmd_pipe_plus.mc_bank_reg[2] ),
        .\cmd_pipe_plus.mc_bank_reg[2]_0 (\cmd_pipe_plus.mc_bank_reg[2]_0 ),
        .\cmd_pipe_plus.mc_bank_reg[2]_1 (\cmd_pipe_plus.mc_bank_reg[2]_1 ),
        .\cmd_pipe_plus.mc_bank_reg[8] (\cmd_pipe_plus.mc_bank_reg[8] ),
        .\cmd_pipe_plus.mc_cas_n_reg[0] (\cmd_pipe_plus.mc_cas_n_reg[0] ),
        .\cmd_pipe_plus.mc_data_offset_1_reg[3] (mc_data_offset_11),
        .\cmd_pipe_plus.mc_data_offset_2_reg[0] (\cmd_pipe_plus.mc_data_offset_2_reg[0] ),
        .\cmd_pipe_plus.mc_data_offset_2_reg[0]_0 (\cmd_pipe_plus.mc_data_offset_2_reg[0]_0 ),
        .\cmd_pipe_plus.mc_data_offset_reg[3] (mc_data_offset1),
        .\cmd_pipe_plus.mc_odt_reg[0] (\cmd_pipe_plus.mc_odt_reg[0] ),
        .\cmd_pipe_plus.mc_we_n_reg[0] (\cmd_pipe_plus.mc_we_n_reg[0] ),
        .\cmd_pipe_plus.mc_we_n_reg[0]_0 (\cmd_pipe_plus.mc_we_n_reg[0]_0 ),
        .\cmd_pipe_plus.mc_we_n_reg[0]_1 (\cmd_pipe_plus.mc_we_n_reg[0]_1 ),
        .\cmd_pipe_plus.mc_we_n_reg[2] (\cmd_pipe_plus.mc_we_n_reg[2] ),
        .\col_mux.col_periodic_rd_r (\col_mux.col_periodic_rd_r ),
        .col_rd_wr(col_rd_wr),
        .col_rd_wr_r(col_rd_wr_r),
        .col_wr_data_buf_addr(col_wr_data_buf_addr),
        .\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] (\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ),
        .\grant_r[2]_i_3 (\grant_r[2]_i_3 ),
        .\grant_r[2]_i_3_0 (\grant_r[2]_i_3_0 ),
        .\grant_r[3]_i_8 (\grant_r[3]_i_8 ),
        .\grant_r[3]_i_8_0 (\grant_r[3]_i_8_0 ),
        .\grant_r_reg[0] (\grant_r_reg[0] ),
        .\grant_r_reg[0]_0 (\grant_r_reg[0]_0 ),
        .\grant_r_reg[0]_1 (\grant_r_reg[0]_1 ),
        .\grant_r_reg[0]_2 (\grant_r_reg[0]_2 ),
        .\grant_r_reg[0]_3 (\grant_r_reg[0]_3 ),
        .\grant_r_reg[0]_4 (\grant_r_reg[0]_4 ),
        .\grant_r_reg[0]_5 (\grant_r_reg[0]_5 ),
        .\grant_r_reg[0]_6 (\grant_r_reg[0]_6 ),
        .\grant_r_reg[0]_7 (\grant_r_reg[0]_7 ),
        .\grant_r_reg[0]_8 (\grant_r_reg[0]_8 ),
        .\grant_r_reg[1] (\grant_r_reg[1] ),
        .\grant_r_reg[1]_0 (\grant_r_reg[1]_0 ),
        .\grant_r_reg[2] (\grant_r_reg[2] ),
        .\grant_r_reg[2]_0 (\grant_r_reg[2]_0 ),
        .\grant_r_reg[3] (\grant_r_reg[3] ),
        .\grant_r_reg[3]_0 (\grant_r_reg[3]_0 ),
        .\grant_r_reg[3]_1 (\grant_r_reg[3]_1 ),
        .\grant_r_reg[3]_2 (\grant_r_reg[3]_2 ),
        .\grant_r_reg[3]_3 (\grant_r_reg[3]_3 ),
        .\grant_r_reg[3]_4 (\grant_r_reg[3]_4 ),
        .\grant_r_reg[3]_5 (\grant_r_reg[3]_5 ),
        .granted_col_ns(granted_col_ns),
        .granted_col_r_reg_0(granted_col_r_reg),
        .granted_col_r_reg_1(granted_col_r_reg_0),
        .granted_col_r_reg_2(granted_col_r_reg_1),
        .granted_col_r_reg_3(granted_col_r_reg_2),
        .granted_row_r_reg_0(granted_row_r_reg),
        .granted_row_r_reg_1(granted_row_r_reg_0),
        .i___22_i_1(i___22_i_1),
        .inhbt_act_faw_r(inhbt_act_faw_r),
        .insert_maint_r1_lcl_reg_0(insert_maint_r1_lcl_reg),
        .insert_maint_r1_lcl_reg_1(insert_maint_r1_lcl_reg_0),
        .\last_master_r_reg[3] (\last_master_r_reg[3] ),
        .\last_master_r_reg[3]_0 (cke_r_reg),
        .maint_srx_r(maint_srx_r),
        .maint_zq_r(maint_zq_r),
        .mc_cas_n_ns(mc_cas_n_ns),
        .mc_cs_n_ns(mc_cs_n_ns),
        .mc_odt_ns(mc_odt_ns),
        .mc_ras_n_ns(mc_ras_n_ns),
        .mc_we_n_ns(mc_we_n_ns),
        .ofs_rdy_r(ofs_rdy_r),
        .ofs_rdy_r_0(ofs_rdy_r_0),
        .ofs_rdy_r_1(ofs_rdy_r_1),
        .ofs_rdy_r_2(ofs_rdy_r_2),
        .override_demand_ns(override_demand_ns),
        .\periodic_rd_generation.read_this_rank (\periodic_rd_generation.read_this_rank ),
        .\periodic_rd_generation.read_this_rank_r (\periodic_rd_generation.read_this_rank_r ),
        .\periodic_rd_generation.read_this_rank_r_reg (\periodic_rd_generation.read_this_rank_r_reg ),
        .\pre_4_1_1T_arb.granted_pre_ns (\pre_4_1_1T_arb.granted_pre_ns ),
        .\pre_4_1_1T_arb.granted_pre_r_reg_0 (\pre_4_1_1T_arb.granted_pre_r_reg ),
        .\pre_4_1_1T_arb.granted_pre_r_reg_1 (\pre_4_1_1T_arb.granted_pre_r_reg_0 ),
        .\pre_4_1_1T_arb.granted_pre_r_reg_2 (\pre_4_1_1T_arb.granted_pre_r_reg_1 ),
        .rd_this_rank_r(rd_this_rank_r),
        .rd_wr_r(rd_wr_r),
        .req_bank_rdy_r(req_bank_rdy_r),
        .req_bank_rdy_r_reg(req_bank_rdy_r_reg),
        .req_data_buf_addr_r(req_data_buf_addr_r),
        .req_periodic_rd_r(req_periodic_rd_r),
        .req_row_r(req_row_r),
        .rnk_config_strobe_ns(rnk_config_strobe_ns),
        .\rnk_config_strobe_r_reg[0]_0 (\rnk_config_strobe_r_reg[0] ),
        .rnk_config_valid_r_lcl_reg_0(rnk_config_valid_r_lcl_reg),
        .rnk_config_valid_r_lcl_reg_1(rnk_config_valid_r_lcl_reg_0),
        .rnk_config_valid_r_lcl_reg_2(rnk_config_valid_r_lcl_reg_1),
        .rnk_config_valid_r_lcl_reg_3(rnk_config_valid_r_lcl_reg_2),
        .rnk_config_valid_r_lcl_reg_4(rnk_config_valid_r_lcl_reg_3),
        .rnk_config_valid_r_lcl_reg_5(rnk_config_valid_r_lcl_reg_4),
        .\rtw_timer.rtw_cnt_r_reg[0] (\rtw_timer.rtw_cnt_r_reg[0] ),
        .\rtw_timer.rtw_cnt_r_reg[1] (\rtw_timer.rtw_cnt_r_reg[1] ),
        .\rtw_timer.rtw_cnt_r_reg[1]_0 (\rtw_timer.rtw_cnt_r_reg[1]_0 ),
        .\rtw_timer.rtw_cnt_r_reg[1]_1 (\rtw_timer.rtw_cnt_r_reg[1]_1 ),
        .wr_this_rank_r(wr_this_rank_r),
        .\wr_this_rank_r_reg[0] (\wr_this_rank_r_reg[0] ),
        .\wr_this_rank_r_reg[0]_0 (\wr_this_rank_r_reg[0]_0 ),
        .\wtr_timer.wtr_cnt_r_reg[1] (\wtr_timer.wtr_cnt_r_reg[1] ));
  mig_mig_7series_v4_2_arb_select arb_select0
       (.DIC(DIC),
        .O(mc_data_offset_21),
        .cke_r(cke_r),
        .cke_r_reg_0(cke_r_reg),
        .cke_r_reg_1(cke_r_reg_0),
        .\cmd_pipe_plus.mc_data_offset_1_reg[5] (\cmd_pipe_plus.mc_data_offset_1_reg[5] ),
        .\cmd_pipe_plus.mc_data_offset_2_reg[5] (\cmd_pipe_plus.mc_data_offset_2_reg[5] ),
        .\cmd_pipe_plus.mc_data_offset_reg[5] (\cmd_pipe_plus.mc_data_offset_reg[5] ),
        .\col_mux.col_periodic_rd_r (\col_mux.col_periodic_rd_r ),
        .col_rd_wr(col_rd_wr),
        .col_rd_wr_r(col_rd_wr_r),
        .mc_cke_ns(mc_cke_ns),
        .\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0] (mc_data_offset1),
        .\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] (\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] ),
        .\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] (\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] ),
        .\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6] (mc_data_offset_11),
        .\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17] (\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17] ));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_arb_row_col" *) 
module mig_mig_7series_v4_2_arb_row_col
   (granted_row_r_reg_0,
    granted_col_r_reg_0,
    insert_maint_r1_lcl_reg_0,
    \pre_4_1_1T_arb.granted_pre_r_reg_0 ,
    rnk_config_valid_r_lcl_reg_0,
    granted_col_r_reg_1,
    \grant_r_reg[2] ,
    \periodic_rd_generation.read_this_rank_r_reg ,
    Q,
    \periodic_rd_generation.read_this_rank ,
    DIC,
    mc_odt_ns,
    D,
    granted_col_r_reg_2,
    granted_col_r_reg_3,
    E,
    \rtw_timer.rtw_cnt_r_reg[1] ,
    col_rd_wr,
    \grant_r_reg[0] ,
    \wr_this_rank_r_reg[0] ,
    \wr_this_rank_r_reg[0]_0 ,
    \grant_r_reg[3] ,
    mc_we_n_ns,
    \grant_r_reg[3]_0 ,
    mc_cas_n_ns,
    mc_ras_n_ns,
    \pre_4_1_1T_arb.granted_pre_r_reg_1 ,
    \pre_4_1_1T_arb.granted_pre_r_reg_2 ,
    mc_cs_n_ns,
    \grant_r_reg[1] ,
    \rnk_config_strobe_r_reg[0]_0 ,
    rnk_config_valid_r_lcl_reg_1,
    rnk_config_valid_r_lcl_reg_2,
    rnk_config_valid_r_lcl_reg_3,
    rnk_config_valid_r_lcl_reg_4,
    override_demand_ns,
    \grant_r_reg[0]_0 ,
    \grant_r_reg[3]_1 ,
    \last_master_r_reg[3] ,
    col_wr_data_buf_addr,
    act_this_rank,
    \grant_r_reg[0]_1 ,
    req_bank_rdy_r_reg,
    \rtw_timer.rtw_cnt_r_reg[1]_0 ,
    \wtr_timer.wtr_cnt_r_reg[1] ,
    \grant_r_reg[0]_2 ,
    \last_master_r_reg[3]_0 ,
    rnk_config_strobe_ns,
    granted_col_ns,
    insert_maint_r1_lcl_reg_1,
    \pre_4_1_1T_arb.granted_pre_ns ,
    SR,
    rnk_config_valid_r_lcl_reg_5,
    \grant_r_reg[0]_3 ,
    \grant_r_reg[0]_4 ,
    \grant_r_reg[2]_0 ,
    \grant_r_reg[0]_5 ,
    \grant_r_reg[3]_2 ,
    granted_row_r_reg_1,
    \grant_r_reg[3]_3 ,
    \periodic_rd_generation.read_this_rank_r ,
    rd_this_rank_r,
    req_periodic_rd_r,
    \rtw_timer.rtw_cnt_r_reg[0] ,
    \col_mux.col_periodic_rd_r ,
    \cmd_pipe_plus.mc_odt_reg[0] ,
    O,
    \cmd_pipe_plus.mc_data_offset_1_reg[3] ,
    \cmd_pipe_plus.mc_data_offset_reg[3] ,
    \rtw_timer.rtw_cnt_r_reg[1]_1 ,
    \cmd_pipe_plus.mc_data_offset_2_reg[0] ,
    \cmd_pipe_plus.mc_data_offset_2_reg[0]_0 ,
    i___22_i_1,
    rd_wr_r,
    col_rd_wr_r,
    wr_this_rank_r,
    \grant_r[3]_i_8 ,
    \grant_r[3]_i_8_0 ,
    \cmd_pipe_plus.mc_we_n_reg[0] ,
    \cmd_pipe_plus.mc_we_n_reg[0]_0 ,
    \cmd_pipe_plus.mc_address_reg[0] ,
    \cmd_pipe_plus.mc_cas_n_reg[0] ,
    maint_zq_r,
    maint_srx_r,
    \cmd_pipe_plus.mc_bank_reg[2] ,
    \cmd_pipe_plus.mc_address_reg[3] ,
    \cmd_pipe_plus.mc_bank_reg[2]_0 ,
    \cmd_pipe_plus.mc_address_reg[0]_0 ,
    \cmd_pipe_plus.mc_bank_reg[2]_1 ,
    \cmd_pipe_plus.mc_bank_reg[8] ,
    \cmd_pipe_plus.mc_address_reg[41] ,
    req_row_r,
    \cmd_pipe_plus.mc_address_reg[10] ,
    \cmd_pipe_plus.mc_address_reg[10]_0 ,
    \cmd_pipe_plus.mc_we_n_reg[0]_1 ,
    \cmd_pipe_plus.mc_we_n_reg[2] ,
    \grant_r_reg[0]_6 ,
    \grant_r_reg[0]_7 ,
    \grant_r_reg[0]_8 ,
    \grant_r_reg[1]_0 ,
    \grant_r_reg[3]_4 ,
    \grant_r_reg[3]_5 ,
    ofs_rdy_r,
    ofs_rdy_r_0,
    ofs_rdy_r_1,
    ofs_rdy_r_2,
    inhbt_act_faw_r,
    req_data_buf_addr_r,
    \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ,
    act_this_rank_r,
    \cmd_pipe_plus.mc_address_reg[23] ,
    \cmd_pipe_plus.mc_address_reg[23]_0 ,
    \cmd_pipe_plus.mc_address_reg[23]_1 ,
    \cmd_pipe_plus.mc_address_reg[23]_2 ,
    \cmd_pipe_plus.mc_address_reg[24] ,
    \cmd_pipe_plus.mc_address_reg[24]_0 ,
    \cmd_pipe_plus.mc_address_reg[24]_1 ,
    \cmd_pipe_plus.mc_address_reg[24]_2 ,
    \cmd_pipe_plus.mc_address_reg[38] ,
    req_bank_rdy_r,
    \grant_r[2]_i_3 ,
    \grant_r[2]_i_3_0 );
  output granted_row_r_reg_0;
  output granted_col_r_reg_0;
  output insert_maint_r1_lcl_reg_0;
  output \pre_4_1_1T_arb.granted_pre_r_reg_0 ;
  output rnk_config_valid_r_lcl_reg_0;
  output granted_col_r_reg_1;
  output \grant_r_reg[2] ;
  output \periodic_rd_generation.read_this_rank_r_reg ;
  output [3:0]Q;
  output \periodic_rd_generation.read_this_rank ;
  output [0:0]DIC;
  output [0:0]mc_odt_ns;
  output [0:0]D;
  output [0:0]granted_col_r_reg_2;
  output [0:0]granted_col_r_reg_3;
  output [0:0]E;
  output [1:0]\rtw_timer.rtw_cnt_r_reg[1] ;
  output col_rd_wr;
  output \grant_r_reg[0] ;
  output \wr_this_rank_r_reg[0] ;
  output \wr_this_rank_r_reg[0]_0 ;
  output \grant_r_reg[3] ;
  output [1:0]mc_we_n_ns;
  output [3:0]\grant_r_reg[3]_0 ;
  output [2:0]mc_cas_n_ns;
  output [1:0]mc_ras_n_ns;
  output [8:0]\pre_4_1_1T_arb.granted_pre_r_reg_1 ;
  output [38:0]\pre_4_1_1T_arb.granted_pre_r_reg_2 ;
  output [0:0]mc_cs_n_ns;
  output \grant_r_reg[1] ;
  output \rnk_config_strobe_r_reg[0]_0 ;
  output rnk_config_valid_r_lcl_reg_1;
  output rnk_config_valid_r_lcl_reg_2;
  output rnk_config_valid_r_lcl_reg_3;
  output rnk_config_valid_r_lcl_reg_4;
  output override_demand_ns;
  output \grant_r_reg[0]_0 ;
  output [3:0]\grant_r_reg[3]_1 ;
  output [0:0]\last_master_r_reg[3] ;
  output [3:0]col_wr_data_buf_addr;
  output act_this_rank;
  output \grant_r_reg[0]_1 ;
  output req_bank_rdy_r_reg;
  output \rtw_timer.rtw_cnt_r_reg[1]_0 ;
  output \wtr_timer.wtr_cnt_r_reg[1] ;
  output \grant_r_reg[0]_2 ;
  input \last_master_r_reg[3]_0 ;
  input rnk_config_strobe_ns;
  input granted_col_ns;
  input insert_maint_r1_lcl_reg_1;
  input \pre_4_1_1T_arb.granted_pre_ns ;
  input [0:0]SR;
  input rnk_config_valid_r_lcl_reg_5;
  input \grant_r_reg[0]_3 ;
  input \grant_r_reg[0]_4 ;
  input \grant_r_reg[2]_0 ;
  input \grant_r_reg[0]_5 ;
  input \grant_r_reg[3]_2 ;
  input granted_row_r_reg_1;
  input \grant_r_reg[3]_3 ;
  input \periodic_rd_generation.read_this_rank_r ;
  input [3:0]rd_this_rank_r;
  input [3:0]req_periodic_rd_r;
  input \rtw_timer.rtw_cnt_r_reg[0] ;
  input \col_mux.col_periodic_rd_r ;
  input \cmd_pipe_plus.mc_odt_reg[0] ;
  input [0:0]O;
  input [0:0]\cmd_pipe_plus.mc_data_offset_1_reg[3] ;
  input [0:0]\cmd_pipe_plus.mc_data_offset_reg[3] ;
  input [1:0]\rtw_timer.rtw_cnt_r_reg[1]_1 ;
  input \cmd_pipe_plus.mc_data_offset_2_reg[0] ;
  input \cmd_pipe_plus.mc_data_offset_2_reg[0]_0 ;
  input i___22_i_1;
  input [0:0]rd_wr_r;
  input col_rd_wr_r;
  input [3:0]wr_this_rank_r;
  input \grant_r[3]_i_8 ;
  input \grant_r[3]_i_8_0 ;
  input \cmd_pipe_plus.mc_we_n_reg[0] ;
  input \cmd_pipe_plus.mc_we_n_reg[0]_0 ;
  input \cmd_pipe_plus.mc_address_reg[0] ;
  input \cmd_pipe_plus.mc_cas_n_reg[0] ;
  input maint_zq_r;
  input maint_srx_r;
  input [2:0]\cmd_pipe_plus.mc_bank_reg[2] ;
  input \cmd_pipe_plus.mc_address_reg[3] ;
  input [2:0]\cmd_pipe_plus.mc_bank_reg[2]_0 ;
  input \cmd_pipe_plus.mc_address_reg[0]_0 ;
  input [2:0]\cmd_pipe_plus.mc_bank_reg[2]_1 ;
  input [2:0]\cmd_pipe_plus.mc_bank_reg[8] ;
  input [19:0]\cmd_pipe_plus.mc_address_reg[41] ;
  input [34:0]req_row_r;
  input \cmd_pipe_plus.mc_address_reg[10] ;
  input \cmd_pipe_plus.mc_address_reg[10]_0 ;
  input \cmd_pipe_plus.mc_we_n_reg[0]_1 ;
  input \cmd_pipe_plus.mc_we_n_reg[2] ;
  input \grant_r_reg[0]_6 ;
  input \grant_r_reg[0]_7 ;
  input \grant_r_reg[0]_8 ;
  input \grant_r_reg[1]_0 ;
  input \grant_r_reg[3]_4 ;
  input \grant_r_reg[3]_5 ;
  input ofs_rdy_r;
  input ofs_rdy_r_0;
  input ofs_rdy_r_1;
  input ofs_rdy_r_2;
  input inhbt_act_faw_r;
  input [15:0]req_data_buf_addr_r;
  input [3:0]\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ;
  input [3:0]act_this_rank_r;
  input [9:0]\cmd_pipe_plus.mc_address_reg[23] ;
  input [9:0]\cmd_pipe_plus.mc_address_reg[23]_0 ;
  input [9:0]\cmd_pipe_plus.mc_address_reg[23]_1 ;
  input [9:0]\cmd_pipe_plus.mc_address_reg[23]_2 ;
  input \cmd_pipe_plus.mc_address_reg[24] ;
  input \cmd_pipe_plus.mc_address_reg[24]_0 ;
  input \cmd_pipe_plus.mc_address_reg[24]_1 ;
  input \cmd_pipe_plus.mc_address_reg[24]_2 ;
  input \cmd_pipe_plus.mc_address_reg[38] ;
  input req_bank_rdy_r;
  input \grant_r[2]_i_3 ;
  input [0:0]\grant_r[2]_i_3_0 ;

  wire [0:0]D;
  wire [0:0]DIC;
  wire [0:0]E;
  wire [0:0]O;
  wire [3:0]Q;
  wire [0:0]SR;
  wire act_this_rank;
  wire [3:0]act_this_rank_r;
  wire \cmd_pipe_plus.mc_address_reg[0] ;
  wire \cmd_pipe_plus.mc_address_reg[0]_0 ;
  wire \cmd_pipe_plus.mc_address_reg[10] ;
  wire \cmd_pipe_plus.mc_address_reg[10]_0 ;
  wire [9:0]\cmd_pipe_plus.mc_address_reg[23] ;
  wire [9:0]\cmd_pipe_plus.mc_address_reg[23]_0 ;
  wire [9:0]\cmd_pipe_plus.mc_address_reg[23]_1 ;
  wire [9:0]\cmd_pipe_plus.mc_address_reg[23]_2 ;
  wire \cmd_pipe_plus.mc_address_reg[24] ;
  wire \cmd_pipe_plus.mc_address_reg[24]_0 ;
  wire \cmd_pipe_plus.mc_address_reg[24]_1 ;
  wire \cmd_pipe_plus.mc_address_reg[24]_2 ;
  wire \cmd_pipe_plus.mc_address_reg[38] ;
  wire \cmd_pipe_plus.mc_address_reg[3] ;
  wire [19:0]\cmd_pipe_plus.mc_address_reg[41] ;
  wire [2:0]\cmd_pipe_plus.mc_bank_reg[2] ;
  wire [2:0]\cmd_pipe_plus.mc_bank_reg[2]_0 ;
  wire [2:0]\cmd_pipe_plus.mc_bank_reg[2]_1 ;
  wire [2:0]\cmd_pipe_plus.mc_bank_reg[8] ;
  wire \cmd_pipe_plus.mc_cas_n_reg[0] ;
  wire [0:0]\cmd_pipe_plus.mc_data_offset_1_reg[3] ;
  wire \cmd_pipe_plus.mc_data_offset_2_reg[0] ;
  wire \cmd_pipe_plus.mc_data_offset_2_reg[0]_0 ;
  wire [0:0]\cmd_pipe_plus.mc_data_offset_reg[3] ;
  wire \cmd_pipe_plus.mc_odt_reg[0] ;
  wire \cmd_pipe_plus.mc_we_n_reg[0] ;
  wire \cmd_pipe_plus.mc_we_n_reg[0]_0 ;
  wire \cmd_pipe_plus.mc_we_n_reg[0]_1 ;
  wire \cmd_pipe_plus.mc_we_n_reg[2] ;
  wire \col_mux.col_periodic_rd_r ;
  wire col_rd_wr;
  wire col_rd_wr_r;
  wire [3:0]col_wr_data_buf_addr;
  wire [3:0]\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ;
  wire \genblk3[1].rnk_config_strobe_r_reg ;
  wire \genblk3[2].rnk_config_strobe_r_reg ;
  wire \grant_r[2]_i_3 ;
  wire [0:0]\grant_r[2]_i_3_0 ;
  wire \grant_r[3]_i_8 ;
  wire \grant_r[3]_i_8_0 ;
  wire \grant_r_reg[0] ;
  wire \grant_r_reg[0]_0 ;
  wire \grant_r_reg[0]_1 ;
  wire \grant_r_reg[0]_2 ;
  wire \grant_r_reg[0]_3 ;
  wire \grant_r_reg[0]_4 ;
  wire \grant_r_reg[0]_5 ;
  wire \grant_r_reg[0]_6 ;
  wire \grant_r_reg[0]_7 ;
  wire \grant_r_reg[0]_8 ;
  wire \grant_r_reg[1] ;
  wire \grant_r_reg[1]_0 ;
  wire \grant_r_reg[2] ;
  wire \grant_r_reg[2]_0 ;
  wire \grant_r_reg[3] ;
  wire [3:0]\grant_r_reg[3]_0 ;
  wire [3:0]\grant_r_reg[3]_1 ;
  wire \grant_r_reg[3]_2 ;
  wire \grant_r_reg[3]_3 ;
  wire \grant_r_reg[3]_4 ;
  wire \grant_r_reg[3]_5 ;
  wire granted_col_ns;
  wire granted_col_r_reg_0;
  wire granted_col_r_reg_1;
  wire [0:0]granted_col_r_reg_2;
  wire [0:0]granted_col_r_reg_3;
  wire granted_row_ns;
  wire granted_row_r_reg_0;
  wire granted_row_r_reg_1;
  wire i___22_i_1;
  wire inhbt_act_faw_r;
  wire insert_maint_r1_lcl_reg_0;
  wire insert_maint_r1_lcl_reg_1;
  wire [0:0]\last_master_r_reg[3] ;
  wire \last_master_r_reg[3]_0 ;
  wire maint_srx_r;
  wire maint_zq_r;
  wire [2:0]mc_cas_n_ns;
  wire [0:0]mc_cs_n_ns;
  wire [0:0]mc_odt_ns;
  wire [1:0]mc_ras_n_ns;
  wire [1:0]mc_we_n_ns;
  wire ofs_rdy_r;
  wire ofs_rdy_r_0;
  wire ofs_rdy_r_1;
  wire ofs_rdy_r_2;
  wire override_demand_ns;
  wire \periodic_rd_generation.read_this_rank ;
  wire \periodic_rd_generation.read_this_rank_r ;
  wire \periodic_rd_generation.read_this_rank_r_reg ;
  wire \pre_4_1_1T_arb.granted_pre_ns ;
  wire \pre_4_1_1T_arb.granted_pre_r_reg_0 ;
  wire [8:0]\pre_4_1_1T_arb.granted_pre_r_reg_1 ;
  wire [38:0]\pre_4_1_1T_arb.granted_pre_r_reg_2 ;
  wire [3:0]rd_this_rank_r;
  wire [0:0]rd_wr_r;
  wire req_bank_rdy_r;
  wire req_bank_rdy_r_reg;
  wire [15:0]req_data_buf_addr_r;
  wire [3:0]req_periodic_rd_r;
  wire [34:0]req_row_r;
  wire rnk_config_strobe;
  wire rnk_config_strobe_ns;
  wire \rnk_config_strobe_r_reg[0]_0 ;
  wire rnk_config_valid_r_lcl_reg_0;
  wire rnk_config_valid_r_lcl_reg_1;
  wire rnk_config_valid_r_lcl_reg_2;
  wire rnk_config_valid_r_lcl_reg_3;
  wire rnk_config_valid_r_lcl_reg_4;
  wire rnk_config_valid_r_lcl_reg_5;
  wire \rtw_timer.rtw_cnt_r_reg[0] ;
  wire [1:0]\rtw_timer.rtw_cnt_r_reg[1] ;
  wire \rtw_timer.rtw_cnt_r_reg[1]_0 ;
  wire [1:0]\rtw_timer.rtw_cnt_r_reg[1]_1 ;
  wire [3:0]wr_this_rank_r;
  wire \wr_this_rank_r_reg[0] ;
  wire \wr_this_rank_r_reg[0]_0 ;
  wire \wtr_timer.wtr_cnt_r_reg[1] ;

  LUT1 #(
    .INIT(2'h1)) 
    \cmd_pipe_plus.mc_cas_n[1]_i_1 
       (.I0(granted_col_r_reg_0),
        .O(mc_cas_n_ns[1]));
  LUT2 #(
    .INIT(4'h1)) 
    \cmd_pipe_plus.mc_cs_n[0]_i_1 
       (.I0(insert_maint_r1_lcl_reg_0),
        .I1(granted_row_r_reg_0),
        .O(mc_cs_n_ns));
  LUT1 #(
    .INIT(2'h1)) 
    \cmd_pipe_plus.mc_ras_n[2]_i_1 
       (.I0(\pre_4_1_1T_arb.granted_pre_r_reg_0 ),
        .O(mc_ras_n_ns[1]));
  mig_mig_7series_v4_2_round_robin_arb__parameterized1 col_arb0
       (.D(D),
        .DIC(DIC),
        .E(E),
        .O(O),
        .Q(Q),
        .\cmd_pipe_plus.mc_address_reg[23] (\cmd_pipe_plus.mc_address_reg[23] ),
        .\cmd_pipe_plus.mc_address_reg[23]_0 (\cmd_pipe_plus.mc_address_reg[23]_0 ),
        .\cmd_pipe_plus.mc_address_reg[23]_1 (\cmd_pipe_plus.mc_address_reg[23]_1 ),
        .\cmd_pipe_plus.mc_address_reg[23]_2 (\cmd_pipe_plus.mc_address_reg[23]_2 ),
        .\cmd_pipe_plus.mc_address_reg[24] (\cmd_pipe_plus.mc_address_reg[24] ),
        .\cmd_pipe_plus.mc_address_reg[24]_0 (\cmd_pipe_plus.mc_address_reg[24]_0 ),
        .\cmd_pipe_plus.mc_address_reg[24]_1 (\cmd_pipe_plus.mc_address_reg[24]_1 ),
        .\cmd_pipe_plus.mc_address_reg[24]_2 (\cmd_pipe_plus.mc_address_reg[24]_2 ),
        .\cmd_pipe_plus.mc_bank_reg[5] (\cmd_pipe_plus.mc_bank_reg[8] ),
        .\cmd_pipe_plus.mc_bank_reg[5]_0 (\cmd_pipe_plus.mc_bank_reg[2] ),
        .\cmd_pipe_plus.mc_bank_reg[5]_1 (\cmd_pipe_plus.mc_bank_reg[2]_0 ),
        .\cmd_pipe_plus.mc_bank_reg[5]_2 (\cmd_pipe_plus.mc_bank_reg[2]_1 ),
        .\cmd_pipe_plus.mc_data_offset_1_reg[3] (\cmd_pipe_plus.mc_data_offset_1_reg[3] ),
        .\cmd_pipe_plus.mc_data_offset_2_reg[0] (granted_col_r_reg_0),
        .\cmd_pipe_plus.mc_data_offset_2_reg[0]_0 (\cmd_pipe_plus.mc_data_offset_2_reg[0] ),
        .\cmd_pipe_plus.mc_data_offset_2_reg[0]_1 (\cmd_pipe_plus.mc_data_offset_2_reg[0]_0 ),
        .\cmd_pipe_plus.mc_data_offset_reg[3] (\cmd_pipe_plus.mc_data_offset_reg[3] ),
        .\cmd_pipe_plus.mc_odt_reg[0] (\cmd_pipe_plus.mc_odt_reg[0] ),
        .\col_mux.col_periodic_rd_r (\col_mux.col_periodic_rd_r ),
        .col_rd_wr(col_rd_wr),
        .col_rd_wr_r(col_rd_wr_r),
        .col_wr_data_buf_addr(col_wr_data_buf_addr),
        .\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] (\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ),
        .\genblk3[1].rnk_config_strobe_r_reg (\genblk3[1].rnk_config_strobe_r_reg ),
        .\genblk3[2].rnk_config_strobe_r_reg (\genblk3[2].rnk_config_strobe_r_reg ),
        .\grant_r[2]_i_3 (\grant_r[2]_i_3 ),
        .\grant_r[2]_i_3_0 (\grant_r[2]_i_3_0 ),
        .\grant_r[3]_i_10 (rnk_config_valid_r_lcl_reg_0),
        .\grant_r[3]_i_8 (\grant_r[3]_i_8 ),
        .\grant_r[3]_i_8_0 (\grant_r[3]_i_8_0 ),
        .\grant_r_reg[0]_0 (\grant_r_reg[0] ),
        .\grant_r_reg[0]_1 (\grant_r_reg[0]_2 ),
        .\grant_r_reg[0]_2 (\grant_r_reg[0]_3 ),
        .\grant_r_reg[0]_3 (\grant_r_reg[0]_4 ),
        .\grant_r_reg[0]_4 (\grant_r_reg[0]_5 ),
        .\grant_r_reg[2]_0 (\grant_r_reg[2] ),
        .\grant_r_reg[2]_1 (\grant_r_reg[2]_0 ),
        .\grant_r_reg[3]_0 (\grant_r_reg[3] ),
        .granted_col_r_reg(granted_col_r_reg_1),
        .granted_col_r_reg_0(granted_col_r_reg_2),
        .granted_col_r_reg_1(granted_col_r_reg_3),
        .granted_col_r_reg_2(\pre_4_1_1T_arb.granted_pre_r_reg_1 [5:3]),
        .granted_col_r_reg_3(\pre_4_1_1T_arb.granted_pre_r_reg_2 [24:14]),
        .i___22_i_1_0(i___22_i_1),
        .\last_master_r_reg[1]_0 (\cmd_pipe_plus.mc_cas_n_reg[0] ),
        .\last_master_r_reg[3]_0 (\last_master_r_reg[3]_0 ),
        .mc_odt_ns(mc_odt_ns),
        .ofs_rdy_r(ofs_rdy_r),
        .ofs_rdy_r_0(ofs_rdy_r_0),
        .ofs_rdy_r_1(ofs_rdy_r_1),
        .ofs_rdy_r_2(ofs_rdy_r_2),
        .\periodic_rd_generation.read_this_rank (\periodic_rd_generation.read_this_rank ),
        .\periodic_rd_generation.read_this_rank_r (\periodic_rd_generation.read_this_rank_r ),
        .\periodic_rd_generation.read_this_rank_r_reg (\periodic_rd_generation.read_this_rank_r_reg ),
        .rd_this_rank_r(rd_this_rank_r),
        .rd_wr_r(rd_wr_r),
        .req_bank_rdy_r(req_bank_rdy_r),
        .req_bank_rdy_r_reg(req_bank_rdy_r_reg),
        .req_data_buf_addr_r(req_data_buf_addr_r),
        .req_periodic_rd_r(req_periodic_rd_r),
        .rnk_config_strobe(rnk_config_strobe),
        .rnk_config_valid_r_lcl_reg(rnk_config_valid_r_lcl_reg_1),
        .rnk_config_valid_r_lcl_reg_0(rnk_config_valid_r_lcl_reg_2),
        .rnk_config_valid_r_lcl_reg_1(rnk_config_valid_r_lcl_reg_3),
        .rnk_config_valid_r_lcl_reg_2(rnk_config_valid_r_lcl_reg_4),
        .\rtw_timer.rtw_cnt_r_reg[0] (\rtw_timer.rtw_cnt_r_reg[0] ),
        .\rtw_timer.rtw_cnt_r_reg[1] (\rtw_timer.rtw_cnt_r_reg[1] ),
        .\rtw_timer.rtw_cnt_r_reg[1]_0 (\rtw_timer.rtw_cnt_r_reg[1]_0 ),
        .\rtw_timer.rtw_cnt_r_reg[1]_1 (\rtw_timer.rtw_cnt_r_reg[1]_1 ),
        .wr_this_rank_r(wr_this_rank_r),
        .\wr_this_rank_r_reg[0] (\wr_this_rank_r_reg[0] ),
        .\wr_this_rank_r_reg[0]_0 (\wr_this_rank_r_reg[0]_0 ),
        .\wtr_timer.wtr_cnt_r_reg[1] (\wtr_timer.wtr_cnt_r_reg[1] ));
  FDRE \genblk3[1].rnk_config_strobe_r_reg[1] 
       (.C(\last_master_r_reg[3]_0 ),
        .CE(1'b1),
        .D(rnk_config_strobe),
        .Q(\genblk3[1].rnk_config_strobe_r_reg ),
        .R(1'b0));
  FDRE \genblk3[2].rnk_config_strobe_r_reg[2] 
       (.C(\last_master_r_reg[3]_0 ),
        .CE(1'b1),
        .D(\genblk3[1].rnk_config_strobe_r_reg ),
        .Q(\genblk3[2].rnk_config_strobe_r_reg ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    granted_col_r_reg
       (.C(\last_master_r_reg[3]_0 ),
        .CE(1'b1),
        .D(granted_col_ns),
        .Q(granted_col_r_reg_0),
        .R(1'b0));
  FDRE granted_row_r_reg
       (.C(\last_master_r_reg[3]_0 ),
        .CE(1'b1),
        .D(granted_row_ns),
        .Q(granted_row_r_reg_0),
        .R(1'b0));
  FDRE insert_maint_r1_lcl_reg
       (.C(\last_master_r_reg[3]_0 ),
        .CE(1'b1),
        .D(insert_maint_r1_lcl_reg_1),
        .Q(insert_maint_r1_lcl_reg_0),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair1149" *) 
  LUT3 #(
    .INIT(8'hFE)) 
    override_demand_r_i_1
       (.I0(\genblk3[1].rnk_config_strobe_r_reg ),
        .I1(\genblk3[2].rnk_config_strobe_r_reg ),
        .I2(rnk_config_strobe),
        .O(override_demand_ns));
  FDRE #(
    .INIT(1'b0)) 
    \pre_4_1_1T_arb.granted_pre_r_reg 
       (.C(\last_master_r_reg[3]_0 ),
        .CE(1'b1),
        .D(\pre_4_1_1T_arb.granted_pre_ns ),
        .Q(\pre_4_1_1T_arb.granted_pre_r_reg_0 ),
        .R(1'b0));
  mig_mig_7series_v4_2_round_robin_arb__parameterized1_3 \pre_4_1_1T_arb.pre_arb0 
       (.Q(\grant_r_reg[3]_1 ),
        .\cmd_pipe_plus.mc_address_reg[38] (\cmd_pipe_plus.mc_address_reg[38] ),
        .\cmd_pipe_plus.mc_address_reg[41] (\pre_4_1_1T_arb.granted_pre_r_reg_0 ),
        .\cmd_pipe_plus.mc_address_reg[41]_0 ({\cmd_pipe_plus.mc_address_reg[41] [19:13],\cmd_pipe_plus.mc_address_reg[41] [11:0]}),
        .\cmd_pipe_plus.mc_bank_reg[8] (\cmd_pipe_plus.mc_bank_reg[8] ),
        .\cmd_pipe_plus.mc_bank_reg[8]_0 (\cmd_pipe_plus.mc_bank_reg[2] ),
        .\cmd_pipe_plus.mc_bank_reg[8]_1 (\cmd_pipe_plus.mc_bank_reg[2]_0 ),
        .\cmd_pipe_plus.mc_bank_reg[8]_2 (\cmd_pipe_plus.mc_bank_reg[2]_1 ),
        .\cmd_pipe_plus.mc_we_n_reg[2] (\cmd_pipe_plus.mc_we_n_reg[2] ),
        .\cmd_pipe_plus.mc_we_n_reg[2]_0 (\cmd_pipe_plus.mc_address_reg[10] ),
        .\cmd_pipe_plus.mc_we_n_reg[2]_1 (\cmd_pipe_plus.mc_we_n_reg[0]_0 ),
        .\cmd_pipe_plus.mc_we_n_reg[2]_2 (\cmd_pipe_plus.mc_we_n_reg[0]_1 ),
        .\grant_r_reg[0]_0 (\grant_r_reg[0]_6 ),
        .\grant_r_reg[0]_1 (\grant_r_reg[0]_7 ),
        .\grant_r_reg[0]_2 (\grant_r_reg[0]_8 ),
        .\grant_r_reg[1]_0 (\grant_r_reg[1]_0 ),
        .\grant_r_reg[3]_0 (\grant_r_reg[3]_4 ),
        .\last_master_r_reg[1]_0 (\cmd_pipe_plus.mc_cas_n_reg[0] ),
        .\last_master_r_reg[3]_0 (\last_master_r_reg[3] ),
        .\last_master_r_reg[3]_1 (\last_master_r_reg[3]_0 ),
        .mc_cas_n_ns(mc_cas_n_ns[2]),
        .mc_we_n_ns(mc_we_n_ns[1]),
        .\pre_4_1_1T_arb.granted_pre_r_reg (\pre_4_1_1T_arb.granted_pre_r_reg_2 [38:25]),
        .\pre_4_1_1T_arb.granted_pre_r_reg_0 (\pre_4_1_1T_arb.granted_pre_r_reg_1 [8:6]),
        .req_row_r(req_row_r));
  (* SOFT_HLUTNM = "soft_lutpair1149" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    \rnk_config_strobe_r[0]_i_3 
       (.I0(rnk_config_strobe),
        .I1(\genblk3[2].rnk_config_strobe_r_reg ),
        .I2(\genblk3[1].rnk_config_strobe_r_reg ),
        .I3(rnk_config_valid_r_lcl_reg_0),
        .O(\rnk_config_strobe_r_reg[0]_0 ));
  FDRE \rnk_config_strobe_r_reg[0] 
       (.C(\last_master_r_reg[3]_0 ),
        .CE(1'b1),
        .D(rnk_config_strobe_ns),
        .Q(rnk_config_strobe),
        .R(1'b0));
  FDRE rnk_config_valid_r_lcl_reg
       (.C(\last_master_r_reg[3]_0 ),
        .CE(1'b1),
        .D(rnk_config_valid_r_lcl_reg_5),
        .Q(rnk_config_valid_r_lcl_reg_0),
        .R(SR));
  mig_mig_7series_v4_2_round_robin_arb__parameterized1_4 row_arb0
       (.Q(\grant_r_reg[3]_0 ),
        .act_this_rank(act_this_rank),
        .act_this_rank_r(act_this_rank_r),
        .\cmd_pipe_plus.mc_address_reg[0] (\cmd_pipe_plus.mc_address_reg[0] ),
        .\cmd_pipe_plus.mc_address_reg[0]_0 (\cmd_pipe_plus.mc_address_reg[0]_0 ),
        .\cmd_pipe_plus.mc_address_reg[10] (\cmd_pipe_plus.mc_address_reg[10] ),
        .\cmd_pipe_plus.mc_address_reg[10]_0 (\cmd_pipe_plus.mc_address_reg[10]_0 ),
        .\cmd_pipe_plus.mc_address_reg[13] (\cmd_pipe_plus.mc_address_reg[41] ),
        .\cmd_pipe_plus.mc_address_reg[3] (\cmd_pipe_plus.mc_address_reg[3] ),
        .\cmd_pipe_plus.mc_bank_reg[2] (\cmd_pipe_plus.mc_bank_reg[2] ),
        .\cmd_pipe_plus.mc_bank_reg[2]_0 (\cmd_pipe_plus.mc_bank_reg[2]_0 ),
        .\cmd_pipe_plus.mc_bank_reg[2]_1 (\cmd_pipe_plus.mc_bank_reg[2]_1 ),
        .\cmd_pipe_plus.mc_bank_reg[2]_2 (\cmd_pipe_plus.mc_bank_reg[8] ),
        .\cmd_pipe_plus.mc_cas_n_reg[0] (\cmd_pipe_plus.mc_cas_n_reg[0] ),
        .\cmd_pipe_plus.mc_ras_n_reg[0] (insert_maint_r1_lcl_reg_0),
        .\cmd_pipe_plus.mc_we_n_reg[0] (\cmd_pipe_plus.mc_we_n_reg[0] ),
        .\cmd_pipe_plus.mc_we_n_reg[0]_0 (\cmd_pipe_plus.mc_we_n_reg[0]_0 ),
        .\cmd_pipe_plus.mc_we_n_reg[0]_1 (\cmd_pipe_plus.mc_we_n_reg[0]_1 ),
        .\cmd_pipe_plus.mc_we_n_reg[0]_2 (\cmd_pipe_plus.mc_we_n_reg[2] ),
        .\grant_r_reg[0]_0 (\pre_4_1_1T_arb.granted_pre_r_reg_1 [2:0]),
        .\grant_r_reg[0]_1 (\grant_r_reg[0]_0 ),
        .\grant_r_reg[0]_2 (\grant_r_reg[0]_1 ),
        .\grant_r_reg[1]_0 (\grant_r_reg[1] ),
        .\grant_r_reg[3]_0 (\grant_r_reg[3]_2 ),
        .\grant_r_reg[3]_1 (\grant_r_reg[3]_3 ),
        .\grant_r_reg[3]_2 (\grant_r_reg[3]_5 ),
        .granted_row_ns(granted_row_ns),
        .granted_row_r_reg(granted_row_r_reg_1),
        .i___70(insert_maint_r1_lcl_reg_1),
        .inhbt_act_faw_r(inhbt_act_faw_r),
        .\last_master_r_reg[2]_0 (granted_row_r_reg_0),
        .\last_master_r_reg[3]_0 (\last_master_r_reg[3]_0 ),
        .maint_srx_r(maint_srx_r),
        .maint_zq_r(maint_zq_r),
        .mc_cas_n_ns(mc_cas_n_ns[0]),
        .mc_ras_n_ns(mc_ras_n_ns[0]),
        .mc_we_n_ns(mc_we_n_ns[0]),
        .req_row_r({req_row_r[34],req_row_r[32:0]}),
        .\req_row_r_lcl_reg[13] (\pre_4_1_1T_arb.granted_pre_r_reg_2 [13:0]));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_arb_select" *) 
module mig_mig_7series_v4_2_arb_select
   (\col_mux.col_periodic_rd_r ,
    col_rd_wr_r,
    cke_r,
    \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] ,
    \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0] ,
    \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] ,
    \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6] ,
    \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17] ,
    O,
    DIC,
    cke_r_reg_0,
    col_rd_wr,
    cke_r_reg_1,
    mc_cke_ns,
    \cmd_pipe_plus.mc_data_offset_reg[5] ,
    \cmd_pipe_plus.mc_data_offset_1_reg[5] ,
    \cmd_pipe_plus.mc_data_offset_2_reg[5] );
  output \col_mux.col_periodic_rd_r ;
  output col_rd_wr_r;
  output cke_r;
  output [3:0]\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] ;
  output [0:0]\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0] ;
  output [3:0]\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] ;
  output [0:0]\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6] ;
  output [3:0]\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17] ;
  output [0:0]O;
  input [0:0]DIC;
  input cke_r_reg_0;
  input col_rd_wr;
  input cke_r_reg_1;
  input [0:0]mc_cke_ns;
  input [5:0]\cmd_pipe_plus.mc_data_offset_reg[5] ;
  input [5:0]\cmd_pipe_plus.mc_data_offset_1_reg[5] ;
  input [5:0]\cmd_pipe_plus.mc_data_offset_2_reg[5] ;

  wire [0:0]DIC;
  wire [0:0]O;
  wire cke_r;
  wire cke_r_reg_0;
  wire cke_r_reg_1;
  wire [5:0]\cmd_pipe_plus.mc_data_offset_1_reg[5] ;
  wire [5:0]\cmd_pipe_plus.mc_data_offset_2_reg[5] ;
  wire [5:0]\cmd_pipe_plus.mc_data_offset_reg[5] ;
  wire \col_mux.col_periodic_rd_r ;
  wire col_rd_wr;
  wire col_rd_wr_r;
  wire [0:0]mc_cke_ns;
  wire \mc_data_offset1_inferred__0/i__carry_n_0 ;
  wire \mc_data_offset1_inferred__0/i__carry_n_1 ;
  wire \mc_data_offset1_inferred__0/i__carry_n_2 ;
  wire \mc_data_offset1_inferred__0/i__carry_n_3 ;
  wire mc_data_offset_11_carry_n_0;
  wire mc_data_offset_11_carry_n_1;
  wire mc_data_offset_11_carry_n_2;
  wire mc_data_offset_11_carry_n_3;
  wire mc_data_offset_21_carry_n_0;
  wire mc_data_offset_21_carry_n_1;
  wire mc_data_offset_21_carry_n_2;
  wire mc_data_offset_21_carry_n_3;
  wire [0:0]\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0] ;
  wire [3:0]\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] ;
  wire [3:0]\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] ;
  wire [0:0]\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6] ;
  wire [3:0]\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17] ;
  wire [3:0]\NLW_mc_data_offset1_inferred__0/i__carry__0_CO_UNCONNECTED ;
  wire [3:1]\NLW_mc_data_offset1_inferred__0/i__carry__0_O_UNCONNECTED ;
  wire [3:0]NLW_mc_data_offset_11_carry__0_CO_UNCONNECTED;
  wire [3:1]NLW_mc_data_offset_11_carry__0_O_UNCONNECTED;
  wire [3:0]NLW_mc_data_offset_21_carry__0_CO_UNCONNECTED;
  wire [3:1]NLW_mc_data_offset_21_carry__0_O_UNCONNECTED;

  FDSE cke_r_reg
       (.C(cke_r_reg_0),
        .CE(1'b1),
        .D(mc_cke_ns),
        .Q(cke_r),
        .S(cke_r_reg_1));
  FDRE \col_mux.col_periodic_rd_r_reg 
       (.C(cke_r_reg_0),
        .CE(1'b1),
        .D(DIC),
        .Q(\col_mux.col_periodic_rd_r ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \col_mux.col_rd_wr_r_reg 
       (.C(cke_r_reg_0),
        .CE(1'b1),
        .D(col_rd_wr),
        .Q(col_rd_wr_r),
        .R(1'b0));
  CARRY4 \mc_data_offset1_inferred__0/i__carry 
       (.CI(1'b0),
        .CO({\mc_data_offset1_inferred__0/i__carry_n_0 ,\mc_data_offset1_inferred__0/i__carry_n_1 ,\mc_data_offset1_inferred__0/i__carry_n_2 ,\mc_data_offset1_inferred__0/i__carry_n_3 }),
        .CYINIT(\cmd_pipe_plus.mc_data_offset_reg[5] [0]),
        .DI(\cmd_pipe_plus.mc_data_offset_reg[5] [4:1]),
        .O({\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] [2],\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0] ,\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] [1:0]}),
        .S(\cmd_pipe_plus.mc_data_offset_reg[5] [4:1]));
  CARRY4 \mc_data_offset1_inferred__0/i__carry__0 
       (.CI(\mc_data_offset1_inferred__0/i__carry_n_0 ),
        .CO(\NLW_mc_data_offset1_inferred__0/i__carry__0_CO_UNCONNECTED [3:0]),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\NLW_mc_data_offset1_inferred__0/i__carry__0_O_UNCONNECTED [3:1],\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] [3]}),
        .S({1'b0,1'b0,1'b0,\cmd_pipe_plus.mc_data_offset_reg[5] [5]}));
  CARRY4 mc_data_offset_11_carry
       (.CI(1'b0),
        .CO({mc_data_offset_11_carry_n_0,mc_data_offset_11_carry_n_1,mc_data_offset_11_carry_n_2,mc_data_offset_11_carry_n_3}),
        .CYINIT(\cmd_pipe_plus.mc_data_offset_1_reg[5] [0]),
        .DI(\cmd_pipe_plus.mc_data_offset_1_reg[5] [4:1]),
        .O({\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] [2],\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6] ,\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] [1:0]}),
        .S(\cmd_pipe_plus.mc_data_offset_1_reg[5] [4:1]));
  CARRY4 mc_data_offset_11_carry__0
       (.CI(mc_data_offset_11_carry_n_0),
        .CO(NLW_mc_data_offset_11_carry__0_CO_UNCONNECTED[3:0]),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({NLW_mc_data_offset_11_carry__0_O_UNCONNECTED[3:1],\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] [3]}),
        .S({1'b0,1'b0,1'b0,\cmd_pipe_plus.mc_data_offset_1_reg[5] [5]}));
  CARRY4 mc_data_offset_21_carry
       (.CI(1'b0),
        .CO({mc_data_offset_21_carry_n_0,mc_data_offset_21_carry_n_1,mc_data_offset_21_carry_n_2,mc_data_offset_21_carry_n_3}),
        .CYINIT(\cmd_pipe_plus.mc_data_offset_2_reg[5] [0]),
        .DI(\cmd_pipe_plus.mc_data_offset_2_reg[5] [4:1]),
        .O({\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17] [2],O,\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17] [1:0]}),
        .S(\cmd_pipe_plus.mc_data_offset_2_reg[5] [4:1]));
  CARRY4 mc_data_offset_21_carry__0
       (.CI(mc_data_offset_21_carry_n_0),
        .CO(NLW_mc_data_offset_21_carry__0_CO_UNCONNECTED[3:0]),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({NLW_mc_data_offset_21_carry__0_O_UNCONNECTED[3:1],\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17] [3]}),
        .S({1'b0,1'b0,1'b0,\cmd_pipe_plus.mc_data_offset_2_reg[5] [5]}));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_bank_cntrl" *) 
module mig_mig_7series_v4_2_bank_cntrl
   (rb_hit_busy_r_reg,
    E,
    req_periodic_rd_r,
    rd_wr_r,
    pre_bm_end_r_reg,
    act_wait_r_lcl_reg,
    col_wait_r_reg,
    act_this_rank_r,
    demand_priority_r_reg,
    demanded_prior_r_reg,
    ofs_rdy_r,
    wr_this_rank_r,
    rd_this_rank_r,
    q_has_rd,
    q_has_priority,
    pass_open_bank_r_lcl_reg,
    wait_for_maint_r,
    tail_r,
    head_r_lcl_reg,
    auto_pre_r_lcl_reg,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[1] ,
    idle_r_lcl_reg,
    rb_hit_busies_r,
    rd_wr_r_lcl_reg,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ,
    bm_end_r1_reg,
    bm_end_r1_reg_0,
    idle_r_lcl_reg_0,
    idle_r_lcl_reg_1,
    idle_r_lcl_reg_2,
    q_entry_ns,
    p_9_in,
    idle_r_lcl_reg_3,
    idle_r_lcl_reg_4,
    \q_entry_r_reg[0] ,
    \q_entry_r_reg[0]_0 ,
    \q_entry_r_reg[1] ,
    rb_hit_busy_r_reg_0,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ,
    rb_hit_busy_r_reg_1,
    idle_r_lcl_reg_5,
    ordered_r_lcl_reg,
    rd_wr_r_lcl_reg_0,
    ordered_r_lcl_reg_0,
    rnk_config_valid_r_lcl_reg,
    rd_wr_r_lcl_reg_1,
    pre_passing_open_bank_r_reg,
    row_hit_r_reg,
    idle_r_lcl_reg_6,
    act_wait_r_lcl_reg_0,
    \compute_tail.tail_r_lcl_reg ,
    idle_r_lcl_reg_7,
    auto_pre_r_lcl_reg_0,
    \req_row_r_lcl_reg[13] ,
    demanded_prior_r_reg_0,
    ofs_rdy_r0,
    ofs_rdy_r0_0,
    ofs_rdy_r0_1,
    \req_data_buf_addr_r_reg[3] ,
    \req_bank_r_lcl_reg[2] ,
    \req_col_r_reg[9] ,
    ofs_rdy_r_reg,
    periodic_rd_insert,
    req_wr_r_lcl0,
    hi_priority,
    col_wait_r_reg_0,
    phy_mc_ctl_full_r_reg,
    phy_mc_ctl_full,
    phy_mc_cmd_full_r_reg,
    of_ctl_full_v,
    q_has_rd_r_reg,
    q_has_priority_r_reg,
    wait_for_maint_r_lcl_reg,
    wait_for_maint_r_lcl_reg_0,
    \compute_tail.tail_r_lcl_reg_0 ,
    head_r_lcl_reg_0,
    auto_pre_r_lcl_reg_1,
    S,
    row_hit_r_reg_0,
    accept_internal_r_reg,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0 ,
    accept_internal_r_reg_0,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ,
    accept_internal_r_reg_1,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ,
    Q,
    \rtp_timer_r_reg[1] ,
    granted_col_r_reg,
    granted_col_r_reg_0,
    granted_col_r_reg_1,
    act_wait_r_lcl_reg_1,
    pre_wait_r_reg,
    \ras_timer_r_reg[0] ,
    \ras_timer_r_reg[0]_0 ,
    \ras_timer_r_reg[0]_1 ,
    \ras_timer_r_reg[0]_2 ,
    \q_entry_r_reg[1]_0 ,
    \q_entry_r_reg[1]_1 ,
    \q_entry_r_reg[1]_2 ,
    \q_entry_r_reg[1]_3 ,
    \q_entry_r_reg[1]_4 ,
    \q_entry_r_reg[1]_5 ,
    \q_entry_r_reg[1]_6 ,
    \q_entry_r_reg[1]_7 ,
    accept_internal_r_reg_2,
    head_r_lcl_reg_1,
    \q_entry_r_reg[0]_1 ,
    \q_entry_r_reg[0]_2 ,
    \q_entry_r_reg[0]_3 ,
    \q_entry_r_reg[0]_4 ,
    i___3_i_4,
    \order_q_r_reg[0] ,
    \order_q_r_reg[0]_0 ,
    \order_q_r_reg[0]_1 ,
    req_bank_rdy_ns,
    rnk_config_valid_r,
    override_demand_ns,
    \rnk_config_strobe_r_reg[0] ,
    req_bank_rdy_r_reg,
    req_bank_rdy_r_reg_0,
    req_bank_rdy_r_reg_1,
    rb_hit_busy_r_reg_2,
    rd_wr_r_lcl_reg_2,
    use_addr,
    accept_internal_r_reg_3,
    accept_internal_r_reg_4,
    pre_bm_end_r_reg_0,
    pass_open_bank_r_lcl_reg_0,
    maint_req_r,
    pass_open_bank_r_lcl_reg_1,
    pass_open_bank_r_lcl_reg_2,
    auto_pre_r_lcl_reg_2,
    pre_wait_r_reg_0,
    demanded_prior_r_reg_1,
    \grant_r[2]_i_3 ,
    override_demand_r,
    \grant_r[2]_i_3_0 ,
    \req_row_r_lcl_reg[13]_0 ,
    \ras_timer_r[1]_i_3 ,
    \ras_timer_r_reg[0]_3 ,
    \ras_timer_r_reg[0]_4 ,
    \ras_timer_r_reg[0]_5 ,
    \ras_timer_r_reg[1] ,
    \ras_timer_r_reg[1]_0 ,
    \ras_timer_r_reg[1]_1 ,
    demanded_prior_r_reg_2,
    demanded_prior_r,
    demand_priority_r_reg_0,
    phy_mc_data_full,
    ofs_rdy_r_reg_0,
    ofs_rdy_r_reg_1,
    ofs_rdy_r_reg_2,
    \rtp_timer_r_reg[0] ,
    \req_data_buf_addr_r_reg[3]_0 ,
    \req_bank_r_lcl_reg[2]_0 ,
    \req_col_r_reg[9]_0 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_1 ,
    \q_entry_r_reg[0]_5 );
  output rb_hit_busy_r_reg;
  output [0:0]E;
  output [0:0]req_periodic_rd_r;
  output [0:0]rd_wr_r;
  output pre_bm_end_r_reg;
  output act_wait_r_lcl_reg;
  output col_wait_r_reg;
  output [0:0]act_this_rank_r;
  output demand_priority_r_reg;
  output demanded_prior_r_reg;
  output ofs_rdy_r;
  output [0:0]wr_this_rank_r;
  output [0:0]rd_this_rank_r;
  output q_has_rd;
  output q_has_priority;
  output pass_open_bank_r_lcl_reg;
  output wait_for_maint_r;
  output tail_r;
  output head_r_lcl_reg;
  output auto_pre_r_lcl_reg;
  output \rb_hit_busies.rb_hit_busies_r_lcl_reg[1] ;
  output idle_r_lcl_reg;
  output [1:0]rb_hit_busies_r;
  output rd_wr_r_lcl_reg;
  output \rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ;
  output bm_end_r1_reg;
  output bm_end_r1_reg_0;
  output idle_r_lcl_reg_0;
  output idle_r_lcl_reg_1;
  output idle_r_lcl_reg_2;
  output [0:0]q_entry_ns;
  output p_9_in;
  output idle_r_lcl_reg_3;
  output idle_r_lcl_reg_4;
  output \q_entry_r_reg[0] ;
  output \q_entry_r_reg[0]_0 ;
  output \q_entry_r_reg[1] ;
  output rb_hit_busy_r_reg_0;
  output \rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ;
  output rb_hit_busy_r_reg_1;
  output idle_r_lcl_reg_5;
  output ordered_r_lcl_reg;
  output rd_wr_r_lcl_reg_0;
  output ordered_r_lcl_reg_0;
  output rnk_config_valid_r_lcl_reg;
  output rd_wr_r_lcl_reg_1;
  output pre_passing_open_bank_r_reg;
  output row_hit_r_reg;
  output idle_r_lcl_reg_6;
  output act_wait_r_lcl_reg_0;
  output \compute_tail.tail_r_lcl_reg ;
  output idle_r_lcl_reg_7;
  output auto_pre_r_lcl_reg_0;
  output [13:0]\req_row_r_lcl_reg[13] ;
  output demanded_prior_r_reg_0;
  output ofs_rdy_r0;
  output ofs_rdy_r0_0;
  output ofs_rdy_r0_1;
  output [3:0]\req_data_buf_addr_r_reg[3] ;
  output [2:0]\req_bank_r_lcl_reg[2] ;
  output [9:0]\req_col_r_reg[9] ;
  input ofs_rdy_r_reg;
  input periodic_rd_insert;
  input req_wr_r_lcl0;
  input hi_priority;
  input col_wait_r_reg_0;
  input phy_mc_ctl_full_r_reg;
  input phy_mc_ctl_full;
  input phy_mc_cmd_full_r_reg;
  input [0:0]of_ctl_full_v;
  input q_has_rd_r_reg;
  input q_has_priority_r_reg;
  input wait_for_maint_r_lcl_reg;
  input wait_for_maint_r_lcl_reg_0;
  input \compute_tail.tail_r_lcl_reg_0 ;
  input head_r_lcl_reg_0;
  input auto_pre_r_lcl_reg_1;
  input [2:0]S;
  input [0:0]row_hit_r_reg_0;
  input accept_internal_r_reg;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0 ;
  input accept_internal_r_reg_0;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ;
  input accept_internal_r_reg_1;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ;
  input [1:0]Q;
  input \rtp_timer_r_reg[1] ;
  input granted_col_r_reg;
  input granted_col_r_reg_0;
  input granted_col_r_reg_1;
  input act_wait_r_lcl_reg_1;
  input pre_wait_r_reg;
  input \ras_timer_r_reg[0] ;
  input \ras_timer_r_reg[0]_0 ;
  input \ras_timer_r_reg[0]_1 ;
  input \ras_timer_r_reg[0]_2 ;
  input \q_entry_r_reg[1]_0 ;
  input \q_entry_r_reg[1]_1 ;
  input [0:0]\q_entry_r_reg[1]_2 ;
  input [0:0]\q_entry_r_reg[1]_3 ;
  input [0:0]\q_entry_r_reg[1]_4 ;
  input \q_entry_r_reg[1]_5 ;
  input \q_entry_r_reg[1]_6 ;
  input \q_entry_r_reg[1]_7 ;
  input accept_internal_r_reg_2;
  input head_r_lcl_reg_1;
  input \q_entry_r_reg[0]_1 ;
  input \q_entry_r_reg[0]_2 ;
  input \q_entry_r_reg[0]_3 ;
  input \q_entry_r_reg[0]_4 ;
  input i___3_i_4;
  input \order_q_r_reg[0] ;
  input \order_q_r_reg[0]_0 ;
  input \order_q_r_reg[0]_1 ;
  input req_bank_rdy_ns;
  input rnk_config_valid_r;
  input override_demand_ns;
  input \rnk_config_strobe_r_reg[0] ;
  input req_bank_rdy_r_reg;
  input req_bank_rdy_r_reg_0;
  input req_bank_rdy_r_reg_1;
  input rb_hit_busy_r_reg_2;
  input rd_wr_r_lcl_reg_2;
  input use_addr;
  input accept_internal_r_reg_3;
  input accept_internal_r_reg_4;
  input [0:0]pre_bm_end_r_reg_0;
  input pass_open_bank_r_lcl_reg_0;
  input maint_req_r;
  input pass_open_bank_r_lcl_reg_1;
  input pass_open_bank_r_lcl_reg_2;
  input auto_pre_r_lcl_reg_2;
  input pre_wait_r_reg_0;
  input demanded_prior_r_reg_1;
  input \grant_r[2]_i_3 ;
  input override_demand_r;
  input \grant_r[2]_i_3_0 ;
  input [13:0]\req_row_r_lcl_reg[13]_0 ;
  input [0:0]\ras_timer_r[1]_i_3 ;
  input \ras_timer_r_reg[0]_3 ;
  input \ras_timer_r_reg[0]_4 ;
  input \ras_timer_r_reg[0]_5 ;
  input \ras_timer_r_reg[1] ;
  input \ras_timer_r_reg[1]_0 ;
  input \ras_timer_r_reg[1]_1 ;
  input demanded_prior_r_reg_2;
  input demanded_prior_r;
  input demand_priority_r_reg_0;
  input phy_mc_data_full;
  input ofs_rdy_r_reg_0;
  input ofs_rdy_r_reg_1;
  input ofs_rdy_r_reg_2;
  input \rtp_timer_r_reg[0] ;
  input [3:0]\req_data_buf_addr_r_reg[3]_0 ;
  input [2:0]\req_bank_r_lcl_reg[2]_0 ;
  input [9:0]\req_col_r_reg[9]_0 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_1 ;
  input \q_entry_r_reg[0]_5 ;

  wire [0:0]E;
  wire [1:0]Q;
  wire [2:0]S;
  wire accept_internal_r_reg;
  wire accept_internal_r_reg_0;
  wire accept_internal_r_reg_1;
  wire accept_internal_r_reg_2;
  wire accept_internal_r_reg_3;
  wire accept_internal_r_reg_4;
  wire [0:0]act_this_rank_r;
  wire act_wait_r_lcl_reg;
  wire act_wait_r_lcl_reg_0;
  wire act_wait_r_lcl_reg_1;
  wire auto_pre_r_lcl_reg;
  wire auto_pre_r_lcl_reg_0;
  wire auto_pre_r_lcl_reg_1;
  wire auto_pre_r_lcl_reg_2;
  wire bank_compare0_n_7;
  wire bank_compare0_n_9;
  wire bank_queue0_n_34;
  wire bank_state0_n_16;
  wire bm_end_r1_reg;
  wire bm_end_r1_reg_0;
  wire col_wait_r_reg;
  wire col_wait_r_reg_0;
  wire \compute_tail.tail_r_lcl_reg ;
  wire \compute_tail.tail_r_lcl_reg_0 ;
  wire demand_priority_r_reg;
  wire demand_priority_r_reg_0;
  wire demanded_prior_r;
  wire demanded_prior_r_reg;
  wire demanded_prior_r_reg_0;
  wire demanded_prior_r_reg_1;
  wire demanded_prior_r_reg_2;
  wire \grant_r[2]_i_3 ;
  wire \grant_r[2]_i_3_0 ;
  wire granted_col_r_reg;
  wire granted_col_r_reg_0;
  wire granted_col_r_reg_1;
  wire head_r_lcl_reg;
  wire head_r_lcl_reg_0;
  wire head_r_lcl_reg_1;
  wire hi_priority;
  wire i___3_i_4;
  wire [0:0]idle_ns;
  wire idle_r_lcl_reg;
  wire idle_r_lcl_reg_0;
  wire idle_r_lcl_reg_1;
  wire idle_r_lcl_reg_2;
  wire idle_r_lcl_reg_3;
  wire idle_r_lcl_reg_4;
  wire idle_r_lcl_reg_5;
  wire idle_r_lcl_reg_6;
  wire idle_r_lcl_reg_7;
  wire maint_req_r;
  wire [0:0]of_ctl_full_v;
  wire ofs_rdy_r;
  wire ofs_rdy_r0;
  wire ofs_rdy_r0_0;
  wire ofs_rdy_r0_1;
  wire ofs_rdy_r_reg;
  wire ofs_rdy_r_reg_0;
  wire ofs_rdy_r_reg_1;
  wire ofs_rdy_r_reg_2;
  wire \order_q_r_reg[0] ;
  wire \order_q_r_reg[0]_0 ;
  wire \order_q_r_reg[0]_1 ;
  wire ordered_r_lcl;
  wire ordered_r_lcl_reg;
  wire ordered_r_lcl_reg_0;
  wire override_demand_ns;
  wire override_demand_r;
  wire p_145_out;
  wire p_9_in;
  wire pass_open_bank_ns;
  wire pass_open_bank_r;
  wire pass_open_bank_r_lcl_reg;
  wire pass_open_bank_r_lcl_reg_0;
  wire pass_open_bank_r_lcl_reg_1;
  wire pass_open_bank_r_lcl_reg_2;
  wire periodic_rd_insert;
  wire phy_mc_cmd_full_r_reg;
  wire phy_mc_ctl_full;
  wire phy_mc_ctl_full_r_reg;
  wire phy_mc_data_full;
  wire pre_bm_end_ns;
  wire pre_bm_end_r_reg;
  wire [0:0]pre_bm_end_r_reg_0;
  wire pre_passing_open_bank_ns;
  wire pre_passing_open_bank_r_reg;
  wire pre_wait_r;
  wire pre_wait_r_reg;
  wire pre_wait_r_reg_0;
  wire [0:0]q_entry_ns;
  wire \q_entry_r_reg[0] ;
  wire \q_entry_r_reg[0]_0 ;
  wire \q_entry_r_reg[0]_1 ;
  wire \q_entry_r_reg[0]_2 ;
  wire \q_entry_r_reg[0]_3 ;
  wire \q_entry_r_reg[0]_4 ;
  wire \q_entry_r_reg[0]_5 ;
  wire \q_entry_r_reg[1] ;
  wire \q_entry_r_reg[1]_0 ;
  wire \q_entry_r_reg[1]_1 ;
  wire [0:0]\q_entry_r_reg[1]_2 ;
  wire [0:0]\q_entry_r_reg[1]_3 ;
  wire [0:0]\q_entry_r_reg[1]_4 ;
  wire \q_entry_r_reg[1]_5 ;
  wire \q_entry_r_reg[1]_6 ;
  wire \q_entry_r_reg[1]_7 ;
  wire q_has_priority;
  wire q_has_priority_r_reg;
  wire q_has_rd;
  wire q_has_rd_r_reg;
  wire [1:0]ras_timer_passed_ns;
  wire [0:0]\ras_timer_r[1]_i_3 ;
  wire \ras_timer_r_reg[0] ;
  wire \ras_timer_r_reg[0]_0 ;
  wire \ras_timer_r_reg[0]_1 ;
  wire \ras_timer_r_reg[0]_2 ;
  wire \ras_timer_r_reg[0]_3 ;
  wire \ras_timer_r_reg[0]_4 ;
  wire \ras_timer_r_reg[0]_5 ;
  wire \ras_timer_r_reg[1] ;
  wire \ras_timer_r_reg[1]_0 ;
  wire \ras_timer_r_reg[1]_1 ;
  wire ras_timer_zero_r;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[1] ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_1 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 ;
  wire [1:0]rb_hit_busies_r;
  wire rb_hit_busy_r_reg;
  wire rb_hit_busy_r_reg_0;
  wire rb_hit_busy_r_reg_1;
  wire rb_hit_busy_r_reg_2;
  wire [0:0]rd_this_rank_r;
  wire [0:0]rd_wr_r;
  wire rd_wr_r_lcl_reg;
  wire rd_wr_r_lcl_reg_0;
  wire rd_wr_r_lcl_reg_1;
  wire rd_wr_r_lcl_reg_2;
  wire [2:0]\req_bank_r_lcl_reg[2] ;
  wire [2:0]\req_bank_r_lcl_reg[2]_0 ;
  wire req_bank_rdy_ns;
  wire req_bank_rdy_ns_0;
  wire req_bank_rdy_r_reg;
  wire req_bank_rdy_r_reg_0;
  wire req_bank_rdy_r_reg_1;
  wire [9:0]\req_col_r_reg[9] ;
  wire [9:0]\req_col_r_reg[9]_0 ;
  wire [3:0]\req_data_buf_addr_r_reg[3] ;
  wire [3:0]\req_data_buf_addr_r_reg[3]_0 ;
  wire [0:0]req_periodic_rd_r;
  wire req_priority_r;
  wire [13:0]\req_row_r_lcl_reg[13] ;
  wire [13:0]\req_row_r_lcl_reg[13]_0 ;
  wire [0:0]req_wr_r;
  wire req_wr_r_lcl0;
  wire \rnk_config_strobe_r_reg[0] ;
  wire rnk_config_valid_r;
  wire rnk_config_valid_r_lcl_reg;
  wire row_hit_r_reg;
  wire [0:0]row_hit_r_reg_0;
  wire \rtp_timer_r_reg[0] ;
  wire \rtp_timer_r_reg[1] ;
  wire start_wtp_timer0;
  wire tail_r;
  wire use_addr;
  wire wait_for_maint_r;
  wire wait_for_maint_r_lcl_reg;
  wire wait_for_maint_r_lcl_reg_0;
  wire [0:0]wr_this_rank_r;

  mig_mig_7series_v4_2_bank_compare_2 bank_compare0
       (.E(idle_ns),
        .Q(Q[0]),
        .S(S),
        .\grant_r_reg[0] (bank_compare0_n_7),
        .hi_priority(hi_priority),
        .maint_req_r(maint_req_r),
        .\order_q_r_reg[1] (\order_q_r_reg[0] ),
        .\order_q_r_reg[1]_0 (\order_q_r_reg[0]_0 ),
        .\order_q_r_reg[1]_1 (\order_q_r_reg[0]_1 ),
        .ordered_r_lcl(ordered_r_lcl),
        .ordered_r_lcl_reg(ordered_r_lcl_reg_0),
        .ordered_r_lcl_reg_0(\q_entry_r_reg[0]_1 ),
        .ordered_r_lcl_reg_1(pre_wait_r_reg),
        .p_145_out(p_145_out),
        .pass_open_bank_r_lcl_reg(pass_open_bank_r_lcl_reg_1),
        .pass_open_bank_r_lcl_reg_0(pass_open_bank_r_lcl_reg_2),
        .periodic_rd_insert(periodic_rd_insert),
        .\q_entry_r[0]_i_2__1 (\q_entry_r_reg[0]_2 ),
        .\q_entry_r[0]_i_2__1_0 (\q_entry_r_reg[0]_3 ),
        .\q_entry_r[0]_i_2__1_1 (\q_entry_r_reg[0]_4 ),
        .rb_hit_busy_r_reg_0(rb_hit_busy_r_reg),
        .rb_hit_busy_r_reg_1(rb_hit_busy_r_reg_1),
        .rb_hit_busy_r_reg_2(rb_hit_busy_r_reg_0),
        .rd_wr_r_lcl_reg_0(rd_wr_r),
        .rd_wr_r_lcl_reg_1(rd_wr_r_lcl_reg_0),
        .rd_wr_r_lcl_reg_2(rd_wr_r_lcl_reg_1),
        .rd_wr_r_lcl_reg_3(bank_compare0_n_9),
        .rd_wr_r_lcl_reg_4(idle_r_lcl_reg),
        .rd_wr_r_lcl_reg_5(rd_wr_r_lcl_reg_2),
        .\req_bank_r_lcl_reg[2]_0 (\req_bank_r_lcl_reg[2] ),
        .\req_bank_r_lcl_reg[2]_1 (\req_bank_r_lcl_reg[2]_0 ),
        .req_bank_rdy_r_reg(req_bank_rdy_r_reg),
        .req_bank_rdy_r_reg_0(req_bank_rdy_r_reg_0),
        .req_bank_rdy_r_reg_1(req_bank_rdy_r_reg_1),
        .\req_col_r_reg[9]_0 (\req_col_r_reg[9] ),
        .\req_col_r_reg[9]_1 (ofs_rdy_r_reg),
        .\req_col_r_reg[9]_2 (\req_col_r_reg[9]_0 ),
        .\req_data_buf_addr_r_reg[3]_0 (\req_data_buf_addr_r_reg[3] ),
        .\req_data_buf_addr_r_reg[3]_1 (E),
        .\req_data_buf_addr_r_reg[3]_2 (\req_data_buf_addr_r_reg[3]_0 ),
        .req_periodic_rd_r(req_periodic_rd_r),
        .req_priority_r(req_priority_r),
        .\req_row_r_lcl_reg[13]_0 (\req_row_r_lcl_reg[13] ),
        .\req_row_r_lcl_reg[13]_1 (\req_row_r_lcl_reg[13]_0 ),
        .req_wr_r(req_wr_r),
        .req_wr_r_lcl0(req_wr_r_lcl0),
        .row_hit_r_reg_0(row_hit_r_reg),
        .row_hit_r_reg_1(row_hit_r_reg_0),
        .start_wtp_timer0(start_wtp_timer0),
        .wait_for_maint_r(wait_for_maint_r));
  mig_mig_7series_v4_2_bank_queue bank_queue0
       (.D(ras_timer_passed_ns),
        .E(idle_ns),
        .Q(Q[0]),
        .accept_internal_r_reg(accept_internal_r_reg),
        .accept_internal_r_reg_0(accept_internal_r_reg_0),
        .accept_internal_r_reg_1(accept_internal_r_reg_1),
        .accept_internal_r_reg_2(accept_internal_r_reg_2),
        .accept_internal_r_reg_3(accept_internal_r_reg_3),
        .accept_internal_r_reg_4(accept_internal_r_reg_4),
        .act_wait_r_lcl_reg(act_wait_r_lcl_reg_0),
        .auto_pre_r_lcl_reg_0(auto_pre_r_lcl_reg),
        .auto_pre_r_lcl_reg_1(auto_pre_r_lcl_reg_1),
        .auto_pre_r_lcl_reg_2(auto_pre_r_lcl_reg_2),
        .bm_end_r1_reg(rd_wr_r),
        .\compute_tail.tail_r_lcl_reg_0 (\compute_tail.tail_r_lcl_reg ),
        .\compute_tail.tail_r_lcl_reg_1 (\compute_tail.tail_r_lcl_reg_0 ),
        .\grant_r[2]_i_3_0 (req_bank_rdy_r_reg),
        .\grant_r[2]_i_3_1 (rd_wr_r_lcl_reg_1),
        .\grant_r[2]_i_3_2 (req_bank_rdy_r_reg_0),
        .\grant_r[2]_i_3_3 (req_bank_rdy_r_reg_1),
        .granted_col_r_reg(granted_col_r_reg),
        .granted_col_r_reg_0(granted_col_r_reg_0),
        .granted_col_r_reg_1(bank_state0_n_16),
        .granted_col_r_reg_2(granted_col_r_reg_1),
        .head_r_lcl_reg_0(head_r_lcl_reg),
        .head_r_lcl_reg_1(phy_mc_cmd_full_r_reg),
        .head_r_lcl_reg_2(head_r_lcl_reg_0),
        .head_r_lcl_reg_3(head_r_lcl_reg_1),
        .i___3_i_4(i___3_i_4),
        .i___70(act_wait_r_lcl_reg),
        .idle_r_lcl_reg_0(E),
        .idle_r_lcl_reg_1(idle_r_lcl_reg),
        .idle_r_lcl_reg_2(idle_r_lcl_reg_0),
        .idle_r_lcl_reg_3(idle_r_lcl_reg_1),
        .idle_r_lcl_reg_4(idle_r_lcl_reg_2),
        .idle_r_lcl_reg_5(idle_r_lcl_reg_3),
        .idle_r_lcl_reg_6(idle_r_lcl_reg_4),
        .idle_r_lcl_reg_7(idle_r_lcl_reg_5),
        .idle_r_lcl_reg_8(idle_r_lcl_reg_6),
        .idle_r_lcl_reg_9(idle_r_lcl_reg_7),
        .\order_q_r_reg[0]_0 (bank_queue0_n_34),
        .\order_q_r_reg[0]_1 (\order_q_r_reg[0] ),
        .\order_q_r_reg[0]_2 (\order_q_r_reg[0]_0 ),
        .\order_q_r_reg[0]_3 (\order_q_r_reg[0]_1 ),
        .\order_q_r_reg[0]_4 (\rtp_timer_r_reg[1] ),
        .\order_q_r_reg[1]_0 (ordered_r_lcl_reg_0),
        .ordered_r_lcl(ordered_r_lcl),
        .ordered_r_lcl_reg_0(ordered_r_lcl_reg),
        .ordered_r_lcl_reg_1(bank_compare0_n_7),
        .p_145_out(p_145_out),
        .p_9_in(p_9_in),
        .pass_open_bank_ns(pass_open_bank_ns),
        .pass_open_bank_r(pass_open_bank_r),
        .pass_open_bank_r_lcl_reg_0(pass_open_bank_r_lcl_reg),
        .pass_open_bank_r_lcl_reg_1(pass_open_bank_r_lcl_reg_0),
        .pass_open_bank_r_lcl_reg_2(row_hit_r_reg),
        .pre_bm_end_ns(pre_bm_end_ns),
        .pre_bm_end_r_reg_0(pre_bm_end_r_reg),
        .pre_passing_open_bank_ns(pre_passing_open_bank_ns),
        .pre_passing_open_bank_r_reg_0(pre_passing_open_bank_r_reg),
        .pre_wait_r(pre_wait_r),
        .q_entry_ns(q_entry_ns),
        .\q_entry_r_reg[0]_0 (\q_entry_r_reg[0] ),
        .\q_entry_r_reg[0]_1 (\q_entry_r_reg[0]_0 ),
        .\q_entry_r_reg[0]_2 (\q_entry_r_reg[0]_1 ),
        .\q_entry_r_reg[0]_3 (\q_entry_r_reg[0]_2 ),
        .\q_entry_r_reg[0]_4 (\q_entry_r_reg[0]_3 ),
        .\q_entry_r_reg[0]_5 (\q_entry_r_reg[0]_4 ),
        .\q_entry_r_reg[0]_6 (rb_hit_busy_r_reg),
        .\q_entry_r_reg[0]_7 (\q_entry_r_reg[0]_5 ),
        .\q_entry_r_reg[1]_0 (\q_entry_r_reg[1] ),
        .\q_entry_r_reg[1]_1 (\q_entry_r_reg[1]_0 ),
        .\q_entry_r_reg[1]_10 (rb_hit_busy_r_reg_1),
        .\q_entry_r_reg[1]_2 (\q_entry_r_reg[1]_1 ),
        .\q_entry_r_reg[1]_3 (\q_entry_r_reg[1]_2 ),
        .\q_entry_r_reg[1]_4 (\q_entry_r_reg[1]_3 ),
        .\q_entry_r_reg[1]_5 (\q_entry_r_reg[1]_4 ),
        .\q_entry_r_reg[1]_6 (\q_entry_r_reg[1]_5 ),
        .\q_entry_r_reg[1]_7 (\q_entry_r_reg[1]_6 ),
        .\q_entry_r_reg[1]_8 (\q_entry_r_reg[1]_7 ),
        .\q_entry_r_reg[1]_9 (rb_hit_busy_r_reg_0),
        .q_has_priority(q_has_priority),
        .q_has_priority_r_reg_0(q_has_priority_r_reg),
        .q_has_priority_r_reg_1(pre_wait_r_reg),
        .q_has_rd(q_has_rd),
        .q_has_rd_r_reg_0(ofs_rdy_r_reg),
        .q_has_rd_r_reg_1(q_has_rd_r_reg),
        .\ras_timer_r_reg[0] (bm_end_r1_reg),
        .\ras_timer_r_reg[0]_0 (\ras_timer_r_reg[0] ),
        .\ras_timer_r_reg[0]_1 (\ras_timer_r_reg[0]_0 ),
        .\ras_timer_r_reg[0]_2 (\ras_timer_r_reg[0]_1 ),
        .\ras_timer_r_reg[0]_3 (\ras_timer_r_reg[0]_2 ),
        .\ras_timer_r_reg[0]_4 (\ras_timer_r_reg[0]_3 ),
        .\ras_timer_r_reg[0]_5 (\ras_timer_r_reg[0]_4 ),
        .\ras_timer_r_reg[0]_6 (\ras_timer_r_reg[0]_5 ),
        .\ras_timer_r_reg[1] (bm_end_r1_reg_0),
        .\ras_timer_r_reg[1]_0 (\ras_timer_r_reg[1] ),
        .\ras_timer_r_reg[1]_1 (\ras_timer_r_reg[1]_0 ),
        .\ras_timer_r_reg[1]_2 (\ras_timer_r_reg[1]_1 ),
        .ras_timer_zero_r(ras_timer_zero_r),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[1] ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_1 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_2 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_1 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 (rb_hit_busies_r[0]),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_2 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_3 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 (rb_hit_busies_r[1]),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_3 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 ),
        .rb_hit_busy_r_reg(rb_hit_busy_r_reg_2),
        .rd_wr_r_lcl_reg(rd_wr_r_lcl_reg),
        .req_bank_rdy_ns(req_bank_rdy_ns_0),
        .req_bank_rdy_r_reg(rd_wr_r_lcl_reg_0),
        .req_bank_rdy_r_reg_0(col_wait_r_reg),
        .req_priority_r(req_priority_r),
        .req_wr_r(req_wr_r),
        .tail_r(tail_r),
        .use_addr(use_addr),
        .wait_for_maint_r(wait_for_maint_r),
        .wait_for_maint_r_lcl_reg_0(wait_for_maint_r_lcl_reg),
        .wait_for_maint_r_lcl_reg_1(wait_for_maint_r_lcl_reg_0));
  mig_mig_7series_v4_2_bank_state bank_state0
       (.D(ras_timer_passed_ns),
        .Q(Q),
        .act_this_rank_r(act_this_rank_r),
        .act_wait_r_lcl_reg_0(act_wait_r_lcl_reg),
        .act_wait_r_lcl_reg_1(act_wait_r_lcl_reg_1),
        .auto_pre_r_lcl_reg(auto_pre_r_lcl_reg_0),
        .bm_end_r1_reg_0(bm_end_r1_reg_0),
        .bm_end_r1_reg_1(bm_end_r1_reg),
        .bm_end_r1_reg_2(pre_bm_end_r_reg),
        .col_wait_r_reg_0(col_wait_r_reg),
        .col_wait_r_reg_1(col_wait_r_reg_0),
        .demand_priority_r_reg_0(demand_priority_r_reg),
        .demand_priority_r_reg_1(bank_state0_n_16),
        .demand_priority_r_reg_2(idle_r_lcl_reg),
        .demand_priority_r_reg_3(bank_queue0_n_34),
        .demand_priority_r_reg_4(demand_priority_r_reg_0),
        .demanded_prior_r(demanded_prior_r),
        .demanded_prior_r_reg_0(demanded_prior_r_reg),
        .demanded_prior_r_reg_1(demanded_prior_r_reg_0),
        .demanded_prior_r_reg_2(demanded_prior_r_reg_1),
        .demanded_prior_r_reg_3(demanded_prior_r_reg_2),
        .\grant_r[2]_i_3 (\grant_r[2]_i_3 ),
        .\grant_r[2]_i_3_0 (\grant_r[2]_i_3_0 ),
        .of_ctl_full_v(of_ctl_full_v),
        .ofs_rdy_r(ofs_rdy_r),
        .ofs_rdy_r0(ofs_rdy_r0),
        .ofs_rdy_r0_0(ofs_rdy_r0_0),
        .ofs_rdy_r0_1(ofs_rdy_r0_1),
        .ofs_rdy_r_reg_0(ofs_rdy_r_reg),
        .ofs_rdy_r_reg_1(ofs_rdy_r_reg_0),
        .ofs_rdy_r_reg_2(ofs_rdy_r_reg_1),
        .ofs_rdy_r_reg_3(ofs_rdy_r_reg_2),
        .override_demand_ns(override_demand_ns),
        .override_demand_r(override_demand_r),
        .pass_open_bank_ns(pass_open_bank_ns),
        .pass_open_bank_r(pass_open_bank_r),
        .phy_mc_cmd_full_r_reg_0(phy_mc_cmd_full_r_reg),
        .phy_mc_ctl_full(phy_mc_ctl_full),
        .phy_mc_ctl_full_r_reg_0(phy_mc_ctl_full_r_reg),
        .phy_mc_data_full(phy_mc_data_full),
        .pre_bm_end_ns(pre_bm_end_ns),
        .pre_bm_end_r_reg(pre_bm_end_r_reg_0),
        .pre_bm_end_r_reg_0(auto_pre_r_lcl_reg),
        .pre_passing_open_bank_ns(pre_passing_open_bank_ns),
        .pre_wait_r(pre_wait_r),
        .pre_wait_r_reg_0(pre_wait_r_reg),
        .pre_wait_r_reg_1(pre_wait_r_reg_0),
        .q_has_rd(q_has_rd),
        .\ras_timer_r[1]_i_3_0 (\ras_timer_r[1]_i_3 ),
        .ras_timer_zero_r(ras_timer_zero_r),
        .ras_timer_zero_r_reg_0(bank_compare0_n_9),
        .rd_this_rank_r(rd_this_rank_r),
        .\rd_this_rank_r_reg[0]_0 (rd_wr_r),
        .req_bank_rdy_ns(req_bank_rdy_ns),
        .req_bank_rdy_ns_0(req_bank_rdy_ns_0),
        .req_wr_r(req_wr_r),
        .\rnk_config_strobe_r_reg[0] (\rnk_config_strobe_r_reg[0] ),
        .rnk_config_valid_r(rnk_config_valid_r),
        .rnk_config_valid_r_lcl_reg(rnk_config_valid_r_lcl_reg),
        .\rtp_timer_r_reg[0]_0 (\rtp_timer_r_reg[0] ),
        .\rtp_timer_r_reg[1]_0 (\rtp_timer_r_reg[1] ),
        .start_wtp_timer0(start_wtp_timer0),
        .wr_this_rank_r(wr_this_rank_r));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_bank_cntrl" *) 
module mig_mig_7series_v4_2_bank_cntrl__parameterized0
   (rb_hit_busy_r_reg,
    E,
    req_periodic_rd_r,
    rd_wr_r_lcl_reg,
    req_wr_r_lcl_reg,
    act_wait_r_lcl_reg,
    act_this_rank_r,
    wr_this_rank_r,
    rd_this_rank_r,
    bm_end_r1,
    col_wait_r_reg,
    req_bank_rdy_r,
    req_bank_rdy_ns,
    demand_priority_r_reg,
    demanded_prior_r_reg,
    ofs_rdy_r,
    pass_open_bank_r_lcl_reg,
    pre_bm_end_r,
    q_has_rd_3,
    q_has_priority,
    wait_for_maint_r_13,
    head_r_lcl_reg,
    ordered_r_lcl_reg,
    tail_r_16,
    auto_pre_r_lcl_reg,
    granted_col_ns,
    rd_wr_r_lcl_reg_0,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ,
    idle_r_lcl_reg,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ,
    pre_passing_open_bank_r_reg,
    row_hit_r_reg,
    pre_bm_end_r_reg,
    rnk_config_strobe_ns,
    demand_priority_r_reg_0,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ,
    \q_entry_r_reg[0] ,
    \q_entry_r_reg[0]_0 ,
    \q_entry_r_reg[1] ,
    \q_entry_r_reg[1]_0 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ,
    bm_end_r1_reg,
    \ras_timer_r_reg[1] ,
    \compute_tail.tail_r_lcl_reg ,
    act_wait_r_lcl_reg_0,
    auto_pre_r_lcl_reg_0,
    \req_row_r_lcl_reg[13] ,
    demanded_prior_r_reg_0,
    \req_data_buf_addr_r_reg[3] ,
    \req_bank_r_lcl_reg[2] ,
    \req_col_r_reg[9] ,
    demand_priority_r_reg_1,
    periodic_rd_insert,
    req_wr_r_lcl0,
    hi_priority,
    col_wait_r_reg_0,
    ofs_rdy_r_reg,
    ofs_rdy_r0,
    q_has_rd_r_reg,
    auto_pre_r_lcl_reg_1,
    q_has_priority_r_reg,
    wait_for_maint_r_lcl_reg,
    wait_for_maint_r_lcl_reg_0,
    head_r_lcl_reg_0,
    \compute_tail.tail_r_lcl_reg_0 ,
    auto_pre_r_lcl_reg_2,
    row_hit_r_reg_0,
    row_hit_r_reg_1,
    granted_col_r_reg,
    granted_col_r_reg_0,
    granted_col_r_reg_1,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_2 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ,
    Q,
    \rtp_timer_r_reg[1] ,
    granted_col_r_reg_2,
    granted_col_r_reg_3,
    granted_col_r_reg_4,
    rb_hit_busies_r,
    rb_hit_busies_r_0,
    rb_hit_busy_r_reg_0,
    rd_wr_r_lcl_reg_1,
    use_addr,
    rb_hit_busy_r_reg_1,
    rb_hit_busy_r_reg_2,
    pre_bm_end_r_reg_0,
    act_wait_r_lcl_reg_1,
    pass_open_bank_r_lcl_reg_0,
    \rnk_config_strobe_r_reg[0] ,
    req_bank_rdy_ns_1,
    \rnk_config_strobe_r_reg[0]_0 ,
    \rnk_config_strobe_r_reg[0]_1 ,
    req_bank_rdy_r_reg,
    \grant_r[3]_i_2 ,
    \grant_r[3]_i_2_0 ,
    \grant_r[3]_i_2_1 ,
    \grant_r[3]_i_2_2 ,
    \order_q_r_reg[1] ,
    head_r_lcl_reg_1,
    head_r_lcl_reg_2,
    head_r_lcl_reg_3,
    act_wait_r_lcl_reg_2,
    \ras_timer_r_reg[0] ,
    \ras_timer_r_reg[0]_0 ,
    \ras_timer_r_reg[0]_1 ,
    \grant_r[3]_i_2_3 ,
    \ras_timer_r_reg[0]_2 ,
    i___34,
    i___34_0,
    i___34_1,
    \ras_timer_r_reg[1]_0 ,
    \ras_timer_r_reg[1]_1 ,
    \ras_timer_r_reg[1]_2 ,
    \ras_timer_r_reg[0]_3 ,
    \ras_timer_r_reg[0]_4 ,
    \ras_timer_r_reg[0]_5 ,
    maint_req_r,
    pass_open_bank_r_lcl_reg_1,
    pass_open_bank_r_lcl_reg_2,
    auto_pre_r_lcl_reg_3,
    ras_timer_zero_r_reg,
    \req_row_r_lcl_reg[13]_0 ,
    ras_timer_zero_r_reg_0,
    demanded_prior_r_reg_1,
    demanded_prior_r_reg_2,
    demanded_prior_r_reg_3,
    demand_priority_r_reg_2,
    \starve_limit_cntr_r_reg[0] ,
    \rtp_timer_r_reg[0] ,
    \req_data_buf_addr_r_reg[3]_0 ,
    \req_bank_r_lcl_reg[2]_0 ,
    \req_col_r_reg[9]_0 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_3 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ,
    q_entry_ns,
    \q_entry_r_reg[1]_1 ,
    \q_entry_r_reg[0]_1 ,
    \q_entry_r_reg[0]_2 ,
    \order_q_r_reg[1]_0 ,
    \order_q_r_reg[0] );
  output rb_hit_busy_r_reg;
  output [0:0]E;
  output [0:0]req_periodic_rd_r;
  output rd_wr_r_lcl_reg;
  output req_wr_r_lcl_reg;
  output act_wait_r_lcl_reg;
  output [0:0]act_this_rank_r;
  output [0:0]wr_this_rank_r;
  output [0:0]rd_this_rank_r;
  output bm_end_r1;
  output col_wait_r_reg;
  output req_bank_rdy_r;
  output req_bank_rdy_ns;
  output demand_priority_r_reg;
  output demanded_prior_r_reg;
  output ofs_rdy_r;
  output pass_open_bank_r_lcl_reg;
  output pre_bm_end_r;
  output q_has_rd_3;
  output q_has_priority;
  output wait_for_maint_r_13;
  output head_r_lcl_reg;
  output ordered_r_lcl_reg;
  output tail_r_16;
  output auto_pre_r_lcl_reg;
  output granted_col_ns;
  output rd_wr_r_lcl_reg_0;
  output [1:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ;
  output idle_r_lcl_reg;
  output \rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ;
  output \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ;
  output pre_passing_open_bank_r_reg;
  output row_hit_r_reg;
  output pre_bm_end_r_reg;
  output rnk_config_strobe_ns;
  output demand_priority_r_reg_0;
  output \rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ;
  output \q_entry_r_reg[0] ;
  output \q_entry_r_reg[0]_0 ;
  output \q_entry_r_reg[1] ;
  output \q_entry_r_reg[1]_0 ;
  output \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ;
  output bm_end_r1_reg;
  output \ras_timer_r_reg[1] ;
  output \compute_tail.tail_r_lcl_reg ;
  output act_wait_r_lcl_reg_0;
  output auto_pre_r_lcl_reg_0;
  output [13:0]\req_row_r_lcl_reg[13] ;
  output demanded_prior_r_reg_0;
  output [3:0]\req_data_buf_addr_r_reg[3] ;
  output [2:0]\req_bank_r_lcl_reg[2] ;
  output [9:0]\req_col_r_reg[9] ;
  input demand_priority_r_reg_1;
  input periodic_rd_insert;
  input req_wr_r_lcl0;
  input hi_priority;
  input col_wait_r_reg_0;
  input ofs_rdy_r_reg;
  input ofs_rdy_r0;
  input q_has_rd_r_reg;
  input auto_pre_r_lcl_reg_1;
  input q_has_priority_r_reg;
  input wait_for_maint_r_lcl_reg;
  input wait_for_maint_r_lcl_reg_0;
  input head_r_lcl_reg_0;
  input \compute_tail.tail_r_lcl_reg_0 ;
  input auto_pre_r_lcl_reg_2;
  input [0:0]row_hit_r_reg_0;
  input [0:0]row_hit_r_reg_1;
  input granted_col_r_reg;
  input granted_col_r_reg_0;
  input granted_col_r_reg_1;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_2 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ;
  input [1:0]Q;
  input \rtp_timer_r_reg[1] ;
  input granted_col_r_reg_2;
  input granted_col_r_reg_3;
  input granted_col_r_reg_4;
  input [0:0]rb_hit_busies_r;
  input [0:0]rb_hit_busies_r_0;
  input rb_hit_busy_r_reg_0;
  input rd_wr_r_lcl_reg_1;
  input use_addr;
  input rb_hit_busy_r_reg_1;
  input rb_hit_busy_r_reg_2;
  input [0:0]pre_bm_end_r_reg_0;
  input act_wait_r_lcl_reg_1;
  input pass_open_bank_r_lcl_reg_0;
  input \rnk_config_strobe_r_reg[0] ;
  input req_bank_rdy_ns_1;
  input \rnk_config_strobe_r_reg[0]_0 ;
  input \rnk_config_strobe_r_reg[0]_1 ;
  input req_bank_rdy_r_reg;
  input \grant_r[3]_i_2 ;
  input \grant_r[3]_i_2_0 ;
  input \grant_r[3]_i_2_1 ;
  input \grant_r[3]_i_2_2 ;
  input \order_q_r_reg[1] ;
  input head_r_lcl_reg_1;
  input head_r_lcl_reg_2;
  input head_r_lcl_reg_3;
  input [0:0]act_wait_r_lcl_reg_2;
  input \ras_timer_r_reg[0] ;
  input \ras_timer_r_reg[0]_0 ;
  input \ras_timer_r_reg[0]_1 ;
  input \grant_r[3]_i_2_3 ;
  input \ras_timer_r_reg[0]_2 ;
  input i___34;
  input i___34_0;
  input i___34_1;
  input \ras_timer_r_reg[1]_0 ;
  input \ras_timer_r_reg[1]_1 ;
  input \ras_timer_r_reg[1]_2 ;
  input \ras_timer_r_reg[0]_3 ;
  input \ras_timer_r_reg[0]_4 ;
  input \ras_timer_r_reg[0]_5 ;
  input maint_req_r;
  input pass_open_bank_r_lcl_reg_1;
  input pass_open_bank_r_lcl_reg_2;
  input auto_pre_r_lcl_reg_3;
  input ras_timer_zero_r_reg;
  input [13:0]\req_row_r_lcl_reg[13]_0 ;
  input ras_timer_zero_r_reg_0;
  input demanded_prior_r_reg_1;
  input demanded_prior_r_reg_2;
  input demanded_prior_r_reg_3;
  input demand_priority_r_reg_2;
  input \starve_limit_cntr_r_reg[0] ;
  input \rtp_timer_r_reg[0] ;
  input [3:0]\req_data_buf_addr_r_reg[3]_0 ;
  input [2:0]\req_bank_r_lcl_reg[2]_0 ;
  input [9:0]\req_col_r_reg[9]_0 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_3 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ;
  input [0:0]q_entry_ns;
  input \q_entry_r_reg[1]_1 ;
  input \q_entry_r_reg[0]_1 ;
  input \q_entry_r_reg[0]_2 ;
  input \order_q_r_reg[1]_0 ;
  input \order_q_r_reg[0] ;

  wire [0:0]E;
  wire [1:0]Q;
  wire [0:0]act_this_rank_r;
  wire act_wait_r_lcl_reg;
  wire act_wait_r_lcl_reg_0;
  wire act_wait_r_lcl_reg_1;
  wire [0:0]act_wait_r_lcl_reg_2;
  wire auto_pre_r_lcl_reg;
  wire auto_pre_r_lcl_reg_0;
  wire auto_pre_r_lcl_reg_1;
  wire auto_pre_r_lcl_reg_2;
  wire auto_pre_r_lcl_reg_3;
  wire bank_compare0_n_5;
  wire bank_queue0_n_23;
  wire bm_end_r1;
  wire bm_end_r1_reg;
  wire col_wait_r_reg;
  wire col_wait_r_reg_0;
  wire \compute_tail.tail_r_lcl_reg ;
  wire \compute_tail.tail_r_lcl_reg_0 ;
  wire demand_priority_r_reg;
  wire demand_priority_r_reg_0;
  wire demand_priority_r_reg_1;
  wire demand_priority_r_reg_2;
  wire demanded_prior_r_reg;
  wire demanded_prior_r_reg_0;
  wire demanded_prior_r_reg_1;
  wire demanded_prior_r_reg_2;
  wire demanded_prior_r_reg_3;
  wire \grant_r[3]_i_2 ;
  wire \grant_r[3]_i_2_0 ;
  wire \grant_r[3]_i_2_1 ;
  wire \grant_r[3]_i_2_2 ;
  wire \grant_r[3]_i_2_3 ;
  wire granted_col_ns;
  wire granted_col_r_reg;
  wire granted_col_r_reg_0;
  wire granted_col_r_reg_1;
  wire granted_col_r_reg_2;
  wire granted_col_r_reg_3;
  wire granted_col_r_reg_4;
  wire head_r_lcl_reg;
  wire head_r_lcl_reg_0;
  wire head_r_lcl_reg_1;
  wire head_r_lcl_reg_2;
  wire head_r_lcl_reg_3;
  wire hi_priority;
  wire i___34;
  wire i___34_0;
  wire i___34_1;
  wire [1:1]idle_ns;
  wire idle_r_lcl_reg;
  wire maint_req_r;
  wire ofs_rdy_r;
  wire ofs_rdy_r0;
  wire ofs_rdy_r_reg;
  wire \order_q_r_reg[0] ;
  wire \order_q_r_reg[1] ;
  wire \order_q_r_reg[1]_0 ;
  wire ordered_r_lcl_reg;
  wire p_106_out;
  wire p_91_out;
  wire pass_open_bank_ns;
  wire pass_open_bank_r_lcl_reg;
  wire pass_open_bank_r_lcl_reg_0;
  wire pass_open_bank_r_lcl_reg_1;
  wire pass_open_bank_r_lcl_reg_2;
  wire periodic_rd_insert;
  wire pre_bm_end_ns;
  wire pre_bm_end_r;
  wire pre_bm_end_r_reg;
  wire [0:0]pre_bm_end_r_reg_0;
  wire pre_passing_open_bank_ns;
  wire pre_passing_open_bank_r_reg;
  wire pre_wait_r;
  wire [0:0]q_entry_ns;
  wire \q_entry_r_reg[0] ;
  wire \q_entry_r_reg[0]_0 ;
  wire \q_entry_r_reg[0]_1 ;
  wire \q_entry_r_reg[0]_2 ;
  wire \q_entry_r_reg[1] ;
  wire \q_entry_r_reg[1]_0 ;
  wire \q_entry_r_reg[1]_1 ;
  wire q_has_priority;
  wire q_has_priority_r_reg;
  wire q_has_rd_3;
  wire q_has_rd_r_reg;
  wire [1:0]ras_timer_passed_ns;
  wire \ras_timer_r_reg[0] ;
  wire \ras_timer_r_reg[0]_0 ;
  wire \ras_timer_r_reg[0]_1 ;
  wire \ras_timer_r_reg[0]_2 ;
  wire \ras_timer_r_reg[0]_3 ;
  wire \ras_timer_r_reg[0]_4 ;
  wire \ras_timer_r_reg[0]_5 ;
  wire \ras_timer_r_reg[1] ;
  wire \ras_timer_r_reg[1]_0 ;
  wire \ras_timer_r_reg[1]_1 ;
  wire \ras_timer_r_reg[1]_2 ;
  wire ras_timer_zero_r;
  wire ras_timer_zero_r_reg;
  wire ras_timer_zero_r_reg_0;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_2 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_3 ;
  wire [1:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ;
  wire [0:0]rb_hit_busies_r;
  wire [0:0]rb_hit_busies_r_0;
  wire rb_hit_busy_r_reg;
  wire rb_hit_busy_r_reg_0;
  wire rb_hit_busy_r_reg_1;
  wire rb_hit_busy_r_reg_2;
  wire [0:0]rd_this_rank_r;
  wire rd_wr_r_lcl_reg;
  wire rd_wr_r_lcl_reg_0;
  wire rd_wr_r_lcl_reg_1;
  wire [2:0]\req_bank_r_lcl_reg[2] ;
  wire [2:0]\req_bank_r_lcl_reg[2]_0 ;
  wire req_bank_rdy_ns;
  wire req_bank_rdy_ns_1;
  wire req_bank_rdy_r;
  wire req_bank_rdy_r_reg;
  wire [9:0]\req_col_r_reg[9] ;
  wire [9:0]\req_col_r_reg[9]_0 ;
  wire [3:0]\req_data_buf_addr_r_reg[3] ;
  wire [3:0]\req_data_buf_addr_r_reg[3]_0 ;
  wire [0:0]req_periodic_rd_r;
  wire req_priority_r;
  wire [13:0]\req_row_r_lcl_reg[13] ;
  wire [13:0]\req_row_r_lcl_reg[13]_0 ;
  wire req_wr_r_lcl0;
  wire req_wr_r_lcl_reg;
  wire rnk_config_strobe_ns;
  wire \rnk_config_strobe_r_reg[0] ;
  wire \rnk_config_strobe_r_reg[0]_0 ;
  wire \rnk_config_strobe_r_reg[0]_1 ;
  wire row_hit_r_reg;
  wire [0:0]row_hit_r_reg_0;
  wire [0:0]row_hit_r_reg_1;
  wire \rtp_timer_r_reg[0] ;
  wire \rtp_timer_r_reg[1] ;
  wire start_wtp_timer0;
  wire \starve_limit_cntr_r_reg[0] ;
  wire tail_r_16;
  wire use_addr;
  wire wait_for_maint_r_13;
  wire wait_for_maint_r_lcl_reg;
  wire wait_for_maint_r_lcl_reg_0;
  wire [0:0]wr_this_rank_r;

  mig_mig_7series_v4_2_bank_compare_1 bank_compare0
       (.E(idle_ns),
        .Q(Q[0]),
        .\grant_r_reg[1] (bank_compare0_n_5),
        .hi_priority(hi_priority),
        .maint_req_r(maint_req_r),
        .ordered_r_lcl_reg(\order_q_r_reg[1] ),
        .ordered_r_lcl_reg_0(ordered_r_lcl_reg),
        .ordered_r_lcl_reg_1(act_wait_r_lcl_reg_1),
        .p_106_out(p_106_out),
        .pass_open_bank_r_lcl_reg(pass_open_bank_r_lcl_reg_1),
        .pass_open_bank_r_lcl_reg_0(pass_open_bank_r_lcl_reg_2),
        .periodic_rd_insert(periodic_rd_insert),
        .rb_hit_busy_r_reg_0(rb_hit_busy_r_reg),
        .rd_wr_r_lcl_reg_0(rd_wr_r_lcl_reg),
        .rd_wr_r_lcl_reg_1(idle_r_lcl_reg),
        .rd_wr_r_lcl_reg_2(rd_wr_r_lcl_reg_1),
        .\req_bank_r_lcl_reg[2]_0 (\req_bank_r_lcl_reg[2] ),
        .\req_bank_r_lcl_reg[2]_1 (\req_bank_r_lcl_reg[2]_0 ),
        .\req_col_r_reg[9]_0 (\req_col_r_reg[9] ),
        .\req_col_r_reg[9]_1 (\req_col_r_reg[9]_0 ),
        .\req_data_buf_addr_r_reg[3]_0 (\req_data_buf_addr_r_reg[3] ),
        .\req_data_buf_addr_r_reg[3]_1 (E),
        .\req_data_buf_addr_r_reg[3]_2 (\req_data_buf_addr_r_reg[3]_0 ),
        .req_periodic_rd_r(req_periodic_rd_r),
        .req_priority_r(req_priority_r),
        .\req_row_r_lcl_reg[13]_0 (\req_row_r_lcl_reg[13] ),
        .\req_row_r_lcl_reg[13]_1 (\req_row_r_lcl_reg[13]_0 ),
        .req_wr_r_lcl0(req_wr_r_lcl0),
        .req_wr_r_lcl_reg_0(req_wr_r_lcl_reg),
        .row_hit_r_reg_0(row_hit_r_reg),
        .row_hit_r_reg_1(demand_priority_r_reg_1),
        .row_hit_r_reg_2(row_hit_r_reg_0),
        .row_hit_r_reg_3(row_hit_r_reg_1),
        .start_wtp_timer0(start_wtp_timer0),
        .wait_for_maint_r_13(wait_for_maint_r_13));
  mig_mig_7series_v4_2_bank_queue__parameterized0 bank_queue0
       (.D(ras_timer_passed_ns),
        .E(idle_ns),
        .Q(Q[0]),
        .act_wait_r_lcl_reg(act_wait_r_lcl_reg_0),
        .auto_pre_r_lcl_reg_0(auto_pre_r_lcl_reg),
        .auto_pre_r_lcl_reg_1(auto_pre_r_lcl_reg_1),
        .auto_pre_r_lcl_reg_2(auto_pre_r_lcl_reg_2),
        .auto_pre_r_lcl_reg_3(auto_pre_r_lcl_reg_3),
        .auto_pre_r_lcl_reg_4(rb_hit_busy_r_reg),
        .bm_end_r1_reg(rd_wr_r_lcl_reg),
        .bm_end_r1_reg_0(req_wr_r_lcl_reg),
        .\compute_tail.tail_r_lcl_reg_0 (\compute_tail.tail_r_lcl_reg ),
        .\compute_tail.tail_r_lcl_reg_1 (\compute_tail.tail_r_lcl_reg_0 ),
        .\grant_r[3]_i_2_0 (\grant_r[3]_i_2 ),
        .\grant_r[3]_i_2_1 (\grant_r[3]_i_2_0 ),
        .\grant_r[3]_i_2_2 (\grant_r[3]_i_2_1 ),
        .\grant_r[3]_i_2_3 (\grant_r[3]_i_2_2 ),
        .\grant_r[3]_i_2_4 (\grant_r[3]_i_2_3 ),
        .granted_col_ns(granted_col_ns),
        .granted_col_r_reg(granted_col_r_reg),
        .granted_col_r_reg_0(granted_col_r_reg_0),
        .granted_col_r_reg_1(granted_col_r_reg_1),
        .granted_col_r_reg_2(granted_col_r_reg_2),
        .granted_col_r_reg_3(granted_col_r_reg_3),
        .granted_col_r_reg_4(granted_col_r_reg_4),
        .head_r_lcl_reg_0(head_r_lcl_reg),
        .head_r_lcl_reg_1(ofs_rdy_r_reg),
        .head_r_lcl_reg_2(head_r_lcl_reg_0),
        .head_r_lcl_reg_3(head_r_lcl_reg_1),
        .head_r_lcl_reg_4(head_r_lcl_reg_2),
        .head_r_lcl_reg_5(head_r_lcl_reg_3),
        .i___34(i___34),
        .i___34_0(i___34_0),
        .i___34_1(i___34_1),
        .i___73(act_wait_r_lcl_reg),
        .idle_r_lcl_reg_0(E),
        .idle_r_lcl_reg_1(idle_r_lcl_reg),
        .\order_q_r_reg[0]_0 (bank_queue0_n_23),
        .\order_q_r_reg[0]_1 (\order_q_r_reg[0] ),
        .\order_q_r_reg[0]_2 (act_wait_r_lcl_reg_1),
        .\order_q_r_reg[1]_0 (demand_priority_r_reg_1),
        .\order_q_r_reg[1]_1 (\order_q_r_reg[1] ),
        .\order_q_r_reg[1]_2 (\order_q_r_reg[1]_0 ),
        .\order_q_r_reg[1]_3 (\rtp_timer_r_reg[1] ),
        .ordered_r_lcl_reg_0(ordered_r_lcl_reg),
        .ordered_r_lcl_reg_1(bank_compare0_n_5),
        .p_106_out(p_106_out),
        .p_91_out(p_91_out),
        .pass_open_bank_ns(pass_open_bank_ns),
        .pass_open_bank_r_lcl_reg_0(pass_open_bank_r_lcl_reg),
        .pass_open_bank_r_lcl_reg_1(pass_open_bank_r_lcl_reg_0),
        .pass_open_bank_r_lcl_reg_2(row_hit_r_reg),
        .pre_bm_end_ns(pre_bm_end_ns),
        .pre_bm_end_r(pre_bm_end_r),
        .pre_bm_end_r_reg_0(pre_bm_end_r_reg),
        .pre_passing_open_bank_ns(pre_passing_open_bank_ns),
        .pre_passing_open_bank_r_reg_0(pre_passing_open_bank_r_reg),
        .pre_wait_r(pre_wait_r),
        .q_entry_ns(q_entry_ns),
        .\q_entry_r_reg[0]_0 (\q_entry_r_reg[0] ),
        .\q_entry_r_reg[0]_1 (\q_entry_r_reg[0]_0 ),
        .\q_entry_r_reg[0]_2 (\q_entry_r_reg[0]_1 ),
        .\q_entry_r_reg[0]_3 (\q_entry_r_reg[0]_2 ),
        .\q_entry_r_reg[1]_0 (\q_entry_r_reg[1] ),
        .\q_entry_r_reg[1]_1 (\q_entry_r_reg[1]_0 ),
        .\q_entry_r_reg[1]_2 (\q_entry_r_reg[1]_1 ),
        .q_has_priority(q_has_priority),
        .q_has_priority_r_reg_0(q_has_priority_r_reg),
        .q_has_rd_3(q_has_rd_3),
        .q_has_rd_r_reg_0(q_has_rd_r_reg),
        .\ras_timer_r_reg[0] (bm_end_r1_reg),
        .\ras_timer_r_reg[0]_0 (\ras_timer_r_reg[0] ),
        .\ras_timer_r_reg[0]_1 (\ras_timer_r_reg[0]_0 ),
        .\ras_timer_r_reg[0]_2 (\ras_timer_r_reg[0]_1 ),
        .\ras_timer_r_reg[0]_3 (\ras_timer_r_reg[0]_2 ),
        .\ras_timer_r_reg[0]_4 (\ras_timer_r_reg[0]_3 ),
        .\ras_timer_r_reg[0]_5 (\ras_timer_r_reg[0]_4 ),
        .\ras_timer_r_reg[0]_6 (\ras_timer_r_reg[0]_5 ),
        .\ras_timer_r_reg[1] (\ras_timer_r_reg[1] ),
        .\ras_timer_r_reg[1]_0 (\ras_timer_r_reg[1]_0 ),
        .\ras_timer_r_reg[1]_1 (\ras_timer_r_reg[1]_1 ),
        .\ras_timer_r_reg[1]_2 (\ras_timer_r_reg[1]_2 ),
        .ras_timer_zero_r(ras_timer_zero_r),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] [0]),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_2 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_3 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_4 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_2 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_5 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_3 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] [1]),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_3 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] (\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ),
        .rb_hit_busies_r(rb_hit_busies_r),
        .rb_hit_busies_r_0(rb_hit_busies_r_0),
        .rb_hit_busy_r_reg(rb_hit_busy_r_reg_0),
        .rb_hit_busy_r_reg_0(rb_hit_busy_r_reg_1),
        .rb_hit_busy_r_reg_1(rb_hit_busy_r_reg_2),
        .rd_wr_r_lcl_reg(rd_wr_r_lcl_reg_0),
        .req_bank_rdy_ns(req_bank_rdy_ns),
        .req_bank_rdy_r_reg(req_bank_rdy_r_reg),
        .req_bank_rdy_r_reg_0(col_wait_r_reg),
        .req_priority_r(req_priority_r),
        .tail_r_16(tail_r_16),
        .use_addr(use_addr),
        .wait_for_maint_r_13(wait_for_maint_r_13),
        .wait_for_maint_r_lcl_reg_0(wait_for_maint_r_lcl_reg),
        .wait_for_maint_r_lcl_reg_1(wait_for_maint_r_lcl_reg_0));
  mig_mig_7series_v4_2_bank_state__parameterized0 bank_state0
       (.D(ras_timer_passed_ns),
        .Q(Q),
        .act_this_rank_r(act_this_rank_r),
        .act_wait_r_lcl_reg_0(act_wait_r_lcl_reg),
        .act_wait_r_lcl_reg_1(act_wait_r_lcl_reg_1),
        .act_wait_r_lcl_reg_2(pre_bm_end_r_reg),
        .act_wait_r_lcl_reg_3(act_wait_r_lcl_reg_2),
        .act_wait_r_lcl_reg_4(\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ),
        .auto_pre_r_lcl_reg(auto_pre_r_lcl_reg_0),
        .bm_end_r1(bm_end_r1),
        .bm_end_r1_reg_0(bm_end_r1_reg),
        .col_wait_r_reg_0(col_wait_r_reg),
        .col_wait_r_reg_1(col_wait_r_reg_0),
        .demand_priority_r_reg_0(demand_priority_r_reg),
        .demand_priority_r_reg_1(demand_priority_r_reg_0),
        .demand_priority_r_reg_2(demand_priority_r_reg_1),
        .demand_priority_r_reg_3(idle_r_lcl_reg),
        .demand_priority_r_reg_4(bank_queue0_n_23),
        .demand_priority_r_reg_5(req_wr_r_lcl_reg),
        .demand_priority_r_reg_6(demand_priority_r_reg_2),
        .demanded_prior_r_reg_0(demanded_prior_r_reg),
        .demanded_prior_r_reg_1(demanded_prior_r_reg_0),
        .demanded_prior_r_reg_2(demanded_prior_r_reg_1),
        .demanded_prior_r_reg_3(demanded_prior_r_reg_2),
        .demanded_prior_r_reg_4(demanded_prior_r_reg_3),
        .ofs_rdy_r(ofs_rdy_r),
        .ofs_rdy_r0(ofs_rdy_r0),
        .ofs_rdy_r_reg_0(ofs_rdy_r_reg),
        .p_91_out(p_91_out),
        .pass_open_bank_ns(pass_open_bank_ns),
        .pre_bm_end_ns(pre_bm_end_ns),
        .pre_bm_end_r_reg(pre_bm_end_r_reg_0),
        .pre_bm_end_r_reg_0(auto_pre_r_lcl_reg),
        .pre_passing_open_bank_ns(pre_passing_open_bank_ns),
        .pre_wait_r(pre_wait_r),
        .q_has_rd_3(q_has_rd_3),
        .\ras_timer_r_reg[1]_0 (\ras_timer_r_reg[1] ),
        .ras_timer_zero_r(ras_timer_zero_r),
        .ras_timer_zero_r_reg_0(ras_timer_zero_r_reg),
        .ras_timer_zero_r_reg_1(ras_timer_zero_r_reg_0),
        .rd_this_rank_r(rd_this_rank_r),
        .\rd_this_rank_r_reg[0]_0 (rd_wr_r_lcl_reg),
        .req_bank_rdy_ns(req_bank_rdy_ns),
        .req_bank_rdy_ns_1(req_bank_rdy_ns_1),
        .req_bank_rdy_r(req_bank_rdy_r),
        .rnk_config_strobe_ns(rnk_config_strobe_ns),
        .\rnk_config_strobe_r_reg[0] (\rnk_config_strobe_r_reg[0] ),
        .\rnk_config_strobe_r_reg[0]_0 (\rnk_config_strobe_r_reg[0]_0 ),
        .\rnk_config_strobe_r_reg[0]_1 (\rnk_config_strobe_r_reg[0]_1 ),
        .\rtp_timer_r_reg[0]_0 (\rtp_timer_r_reg[0] ),
        .\rtp_timer_r_reg[1]_0 (pass_open_bank_r_lcl_reg),
        .\rtp_timer_r_reg[1]_1 (\rtp_timer_r_reg[1] ),
        .start_wtp_timer0(start_wtp_timer0),
        .\starve_limit_cntr_r_reg[0]_0 (\starve_limit_cntr_r_reg[0] ),
        .wr_this_rank_r(wr_this_rank_r));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_bank_cntrl" *) 
module mig_mig_7series_v4_2_bank_cntrl__parameterized1
   (rb_hit_busy_r_reg,
    E,
    req_periodic_rd_r,
    rd_wr_r_lcl_reg,
    req_wr_r_lcl_reg,
    act_wait_r_lcl_reg,
    act_this_rank_r,
    wr_this_rank_r,
    rd_this_rank_r,
    bm_end_r1_0,
    pre_bm_end_r_reg,
    col_wait_r_reg,
    req_bank_rdy_ns,
    demand_priority_r_reg,
    demanded_prior_r_reg,
    override_demand_r,
    ofs_rdy_r,
    q_has_rd_7,
    q_has_priority,
    pass_open_bank_r_lcl_reg,
    wait_for_maint_r_14,
    head_r_lcl_reg,
    ordered_r_lcl_reg,
    tail_r_17,
    auto_pre_r_lcl_reg,
    rb_hit_busies_r,
    idle_r_lcl_reg,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ,
    rd_wr_r_lcl_reg_0,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ,
    bm_end_r1_reg,
    \ras_timer_r_reg[1] ,
    \q_entry_r_reg[1] ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ,
    \q_entry_r_reg[1]_0 ,
    \q_entry_r_reg[0] ,
    \q_entry_r_reg[0]_0 ,
    idle_r_lcl_reg_0,
    \order_q_r_reg[1] ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[6] ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ,
    pre_passing_open_bank_r_reg,
    row_hit_r_reg,
    \compute_tail.tail_r_lcl_reg ,
    ras_timer_zero_r_reg,
    act_wait_r_lcl_reg_0,
    auto_pre_r_lcl_reg_0,
    \req_row_r_lcl_reg[13] ,
    demand_priority_r_reg_0,
    act_wait_r_lcl_reg_1,
    \req_data_buf_addr_r_reg[3] ,
    \req_bank_r_lcl_reg[2] ,
    \req_col_r_reg[9] ,
    ofs_rdy_r_reg,
    periodic_rd_insert,
    req_wr_r_lcl0,
    hi_priority,
    col_wait_r_reg_0,
    override_demand_ns,
    ofs_rdy_r_reg_0,
    ofs_rdy_r0,
    q_has_rd_r_reg,
    q_has_priority_r_reg,
    wait_for_maint_r_lcl_reg,
    wait_for_maint_r_lcl_reg_0,
    head_r_lcl_reg_0,
    \compute_tail.tail_r_lcl_reg_0 ,
    auto_pre_r_lcl_reg_1,
    row_hit_r_reg_0,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ,
    Q,
    pre_wait_r_reg,
    granted_col_r_reg,
    granted_col_r_reg_0,
    granted_col_r_reg_1,
    granted_col_r_reg_2,
    act_wait_r_lcl_reg_2,
    \ras_timer_r_reg[0] ,
    \ras_timer_r_reg[0]_0 ,
    \ras_timer_r_reg[0]_1 ,
    \ras_timer_r_reg[0]_2 ,
    head_r_lcl_reg_1,
    head_r_lcl_reg_2,
    \order_q_r_reg[1]_0 ,
    head_r_lcl_reg_3,
    \q_entry_r_reg[1]_1 ,
    i___5_i_4,
    i___5_i_4_0,
    i___5_i_4_1,
    req_bank_rdy_r_reg,
    \grant_r[3]_i_3 ,
    \grant_r[3]_i_3_0 ,
    \grant_r[3]_i_3_1 ,
    \grant_r[3]_i_3_2 ,
    rnk_config_valid_r_lcl_reg,
    rnk_config_valid_r_lcl_reg_0,
    rb_hit_busy_r_reg_0,
    rd_wr_r_lcl_reg_1,
    use_addr,
    rb_hit_busy_r_reg_1,
    rb_hit_busy_r_reg_2,
    \ras_timer_r_reg[1]_0 ,
    \ras_timer_r_reg[1]_1 ,
    \ras_timer_r_reg[1]_2 ,
    \ras_timer_r_reg[0]_3 ,
    \ras_timer_r_reg[0]_4 ,
    \ras_timer_r_reg[0]_5 ,
    \grant_r[3]_i_6 ,
    rb_hit_busies_r_0,
    rb_hit_busies_r_1,
    pre_bm_end_r_reg_0,
    pass_open_bank_r_lcl_reg_0,
    maint_req_r,
    pass_open_bank_r_lcl_reg_1,
    pass_open_bank_r_lcl_reg_2,
    auto_pre_r_lcl_reg_2,
    \pre_4_1_1T_arb.granted_pre_r_reg ,
    ras_timer_zero_r_reg_0,
    \req_row_r_lcl_reg[13]_0 ,
    ras_timer_zero_r_reg_1,
    demand_priority_r_1,
    demanded_prior_r_reg_0,
    demanded_prior_r_2,
    \cmd_pipe_plus.mc_address_reg[38] ,
    row_cmd_wr,
    demand_priority_r_reg_1,
    \rtp_timer_r_reg[0] ,
    \req_data_buf_addr_r_reg[3]_0 ,
    \req_bank_r_lcl_reg[2]_0 ,
    \req_col_r_reg[9]_0 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_2 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 ,
    \q_entry_r_reg[1]_2 ,
    \q_entry_r_reg[1]_3 ,
    \q_entry_r_reg[0]_1 ,
    \order_q_r_reg[1]_1 ,
    \order_q_r_reg[0] );
  output rb_hit_busy_r_reg;
  output [0:0]E;
  output [0:0]req_periodic_rd_r;
  output rd_wr_r_lcl_reg;
  output req_wr_r_lcl_reg;
  output act_wait_r_lcl_reg;
  output [0:0]act_this_rank_r;
  output [0:0]wr_this_rank_r;
  output [0:0]rd_this_rank_r;
  output bm_end_r1_0;
  output pre_bm_end_r_reg;
  output col_wait_r_reg;
  output req_bank_rdy_ns;
  output demand_priority_r_reg;
  output demanded_prior_r_reg;
  output override_demand_r;
  output ofs_rdy_r;
  output q_has_rd_7;
  output q_has_priority;
  output pass_open_bank_r_lcl_reg;
  output wait_for_maint_r_14;
  output head_r_lcl_reg;
  output ordered_r_lcl_reg;
  output tail_r_17;
  output auto_pre_r_lcl_reg;
  output [1:0]rb_hit_busies_r;
  output idle_r_lcl_reg;
  output \rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ;
  output rd_wr_r_lcl_reg_0;
  output \rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ;
  output bm_end_r1_reg;
  output \ras_timer_r_reg[1] ;
  output \q_entry_r_reg[1] ;
  output \rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ;
  output \q_entry_r_reg[1]_0 ;
  output \q_entry_r_reg[0] ;
  output \q_entry_r_reg[0]_0 ;
  output idle_r_lcl_reg_0;
  output \order_q_r_reg[1] ;
  output \rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ;
  output \rb_hit_busies.rb_hit_busies_r_lcl_reg[6] ;
  output \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ;
  output pre_passing_open_bank_r_reg;
  output row_hit_r_reg;
  output \compute_tail.tail_r_lcl_reg ;
  output ras_timer_zero_r_reg;
  output act_wait_r_lcl_reg_0;
  output auto_pre_r_lcl_reg_0;
  output [13:0]\req_row_r_lcl_reg[13] ;
  output demand_priority_r_reg_0;
  output act_wait_r_lcl_reg_1;
  output [3:0]\req_data_buf_addr_r_reg[3] ;
  output [2:0]\req_bank_r_lcl_reg[2] ;
  output [9:0]\req_col_r_reg[9] ;
  input ofs_rdy_r_reg;
  input periodic_rd_insert;
  input req_wr_r_lcl0;
  input hi_priority;
  input col_wait_r_reg_0;
  input override_demand_ns;
  input ofs_rdy_r_reg_0;
  input ofs_rdy_r0;
  input q_has_rd_r_reg;
  input q_has_priority_r_reg;
  input wait_for_maint_r_lcl_reg;
  input wait_for_maint_r_lcl_reg_0;
  input head_r_lcl_reg_0;
  input \compute_tail.tail_r_lcl_reg_0 ;
  input auto_pre_r_lcl_reg_1;
  input [0:0]row_hit_r_reg_0;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ;
  input [1:0]Q;
  input pre_wait_r_reg;
  input granted_col_r_reg;
  input granted_col_r_reg_0;
  input granted_col_r_reg_1;
  input granted_col_r_reg_2;
  input [0:0]act_wait_r_lcl_reg_2;
  input \ras_timer_r_reg[0] ;
  input \ras_timer_r_reg[0]_0 ;
  input \ras_timer_r_reg[0]_1 ;
  input \ras_timer_r_reg[0]_2 ;
  input head_r_lcl_reg_1;
  input head_r_lcl_reg_2;
  input \order_q_r_reg[1]_0 ;
  input head_r_lcl_reg_3;
  input \q_entry_r_reg[1]_1 ;
  input i___5_i_4;
  input i___5_i_4_0;
  input i___5_i_4_1;
  input req_bank_rdy_r_reg;
  input \grant_r[3]_i_3 ;
  input \grant_r[3]_i_3_0 ;
  input \grant_r[3]_i_3_1 ;
  input \grant_r[3]_i_3_2 ;
  input rnk_config_valid_r_lcl_reg;
  input rnk_config_valid_r_lcl_reg_0;
  input rb_hit_busy_r_reg_0;
  input rd_wr_r_lcl_reg_1;
  input use_addr;
  input rb_hit_busy_r_reg_1;
  input rb_hit_busy_r_reg_2;
  input \ras_timer_r_reg[1]_0 ;
  input \ras_timer_r_reg[1]_1 ;
  input \ras_timer_r_reg[1]_2 ;
  input \ras_timer_r_reg[0]_3 ;
  input \ras_timer_r_reg[0]_4 ;
  input \ras_timer_r_reg[0]_5 ;
  input [0:0]\grant_r[3]_i_6 ;
  input [0:0]rb_hit_busies_r_0;
  input [0:0]rb_hit_busies_r_1;
  input [1:0]pre_bm_end_r_reg_0;
  input pass_open_bank_r_lcl_reg_0;
  input maint_req_r;
  input pass_open_bank_r_lcl_reg_1;
  input pass_open_bank_r_lcl_reg_2;
  input auto_pre_r_lcl_reg_2;
  input \pre_4_1_1T_arb.granted_pre_r_reg ;
  input ras_timer_zero_r_reg_0;
  input [13:0]\req_row_r_lcl_reg[13]_0 ;
  input ras_timer_zero_r_reg_1;
  input demand_priority_r_1;
  input demanded_prior_r_reg_0;
  input demanded_prior_r_2;
  input [0:0]\cmd_pipe_plus.mc_address_reg[38] ;
  input [0:0]row_cmd_wr;
  input demand_priority_r_reg_1;
  input \rtp_timer_r_reg[0] ;
  input [3:0]\req_data_buf_addr_r_reg[3]_0 ;
  input [2:0]\req_bank_r_lcl_reg[2]_0 ;
  input [9:0]\req_col_r_reg[9]_0 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_2 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 ;
  input \q_entry_r_reg[1]_2 ;
  input \q_entry_r_reg[1]_3 ;
  input \q_entry_r_reg[0]_1 ;
  input \order_q_r_reg[1]_1 ;
  input \order_q_r_reg[0] ;

  wire [0:0]E;
  wire [1:0]Q;
  wire [0:0]act_this_rank_r;
  wire act_wait_r_lcl_reg;
  wire act_wait_r_lcl_reg_0;
  wire act_wait_r_lcl_reg_1;
  wire [0:0]act_wait_r_lcl_reg_2;
  wire auto_pre_r_lcl_reg;
  wire auto_pre_r_lcl_reg_0;
  wire auto_pre_r_lcl_reg_1;
  wire auto_pre_r_lcl_reg_2;
  wire bank_compare0_n_5;
  wire bank_queue0_n_27;
  wire bm_end_r1_0;
  wire bm_end_r1_reg;
  wire [0:0]\cmd_pipe_plus.mc_address_reg[38] ;
  wire col_wait_r_reg;
  wire col_wait_r_reg_0;
  wire \compute_tail.tail_r_lcl_reg ;
  wire \compute_tail.tail_r_lcl_reg_0 ;
  wire demand_priority_r_1;
  wire demand_priority_r_reg;
  wire demand_priority_r_reg_0;
  wire demand_priority_r_reg_1;
  wire demanded_prior_r_2;
  wire demanded_prior_r_reg;
  wire demanded_prior_r_reg_0;
  wire \grant_r[3]_i_3 ;
  wire \grant_r[3]_i_3_0 ;
  wire \grant_r[3]_i_3_1 ;
  wire \grant_r[3]_i_3_2 ;
  wire [0:0]\grant_r[3]_i_6 ;
  wire granted_col_r_reg;
  wire granted_col_r_reg_0;
  wire granted_col_r_reg_1;
  wire granted_col_r_reg_2;
  wire head_r_lcl_reg;
  wire head_r_lcl_reg_0;
  wire head_r_lcl_reg_1;
  wire head_r_lcl_reg_2;
  wire head_r_lcl_reg_3;
  wire hi_priority;
  wire i___5_i_4;
  wire i___5_i_4_0;
  wire i___5_i_4_1;
  wire [2:2]idle_ns;
  wire idle_r_lcl_reg;
  wire idle_r_lcl_reg_0;
  wire maint_req_r;
  wire ofs_rdy_r;
  wire ofs_rdy_r0;
  wire ofs_rdy_r_reg;
  wire ofs_rdy_r_reg_0;
  wire \order_q_r_reg[0] ;
  wire \order_q_r_reg[1] ;
  wire \order_q_r_reg[1]_0 ;
  wire \order_q_r_reg[1]_1 ;
  wire ordered_r_lcl_reg;
  wire override_demand_ns;
  wire override_demand_r;
  wire p_67_out;
  wire pass_open_bank_ns;
  wire pass_open_bank_r;
  wire pass_open_bank_r_lcl_reg;
  wire pass_open_bank_r_lcl_reg_0;
  wire pass_open_bank_r_lcl_reg_1;
  wire pass_open_bank_r_lcl_reg_2;
  wire periodic_rd_insert;
  wire \pre_4_1_1T_arb.granted_pre_r_reg ;
  wire pre_bm_end_ns;
  wire pre_bm_end_r_reg;
  wire [1:0]pre_bm_end_r_reg_0;
  wire pre_passing_open_bank_ns;
  wire pre_passing_open_bank_r_reg;
  wire pre_wait_r;
  wire pre_wait_r_reg;
  wire \q_entry_r_reg[0] ;
  wire \q_entry_r_reg[0]_0 ;
  wire \q_entry_r_reg[0]_1 ;
  wire \q_entry_r_reg[1] ;
  wire \q_entry_r_reg[1]_0 ;
  wire \q_entry_r_reg[1]_1 ;
  wire \q_entry_r_reg[1]_2 ;
  wire \q_entry_r_reg[1]_3 ;
  wire q_has_priority;
  wire q_has_priority_r_reg;
  wire q_has_rd_7;
  wire q_has_rd_r_reg;
  wire [1:0]ras_timer_passed_ns;
  wire \ras_timer_r_reg[0] ;
  wire \ras_timer_r_reg[0]_0 ;
  wire \ras_timer_r_reg[0]_1 ;
  wire \ras_timer_r_reg[0]_2 ;
  wire \ras_timer_r_reg[0]_3 ;
  wire \ras_timer_r_reg[0]_4 ;
  wire \ras_timer_r_reg[0]_5 ;
  wire \ras_timer_r_reg[1] ;
  wire \ras_timer_r_reg[1]_0 ;
  wire \ras_timer_r_reg[1]_1 ;
  wire \ras_timer_r_reg[1]_2 ;
  wire ras_timer_zero_r;
  wire ras_timer_zero_r_reg;
  wire ras_timer_zero_r_reg_0;
  wire ras_timer_zero_r_reg_1;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_2 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[6] ;
  wire [1:0]rb_hit_busies_r;
  wire [0:0]rb_hit_busies_r_0;
  wire [0:0]rb_hit_busies_r_1;
  wire rb_hit_busy_r_reg;
  wire rb_hit_busy_r_reg_0;
  wire rb_hit_busy_r_reg_1;
  wire rb_hit_busy_r_reg_2;
  wire [0:0]rd_this_rank_r;
  wire rd_wr_r_lcl_reg;
  wire rd_wr_r_lcl_reg_0;
  wire rd_wr_r_lcl_reg_1;
  wire [2:0]\req_bank_r_lcl_reg[2] ;
  wire [2:0]\req_bank_r_lcl_reg[2]_0 ;
  wire req_bank_rdy_ns;
  wire req_bank_rdy_r_reg;
  wire [9:0]\req_col_r_reg[9] ;
  wire [9:0]\req_col_r_reg[9]_0 ;
  wire [3:0]\req_data_buf_addr_r_reg[3] ;
  wire [3:0]\req_data_buf_addr_r_reg[3]_0 ;
  wire [0:0]req_periodic_rd_r;
  wire req_priority_r;
  wire [13:0]\req_row_r_lcl_reg[13] ;
  wire [13:0]\req_row_r_lcl_reg[13]_0 ;
  wire req_wr_r_lcl0;
  wire req_wr_r_lcl_reg;
  wire rnk_config_valid_r_lcl_reg;
  wire rnk_config_valid_r_lcl_reg_0;
  wire [0:0]row_cmd_wr;
  wire row_hit_r_reg;
  wire [0:0]row_hit_r_reg_0;
  wire \rtp_timer_r_reg[0] ;
  wire start_wtp_timer0;
  wire tail_r_17;
  wire use_addr;
  wire wait_for_maint_r_14;
  wire wait_for_maint_r_lcl_reg;
  wire wait_for_maint_r_lcl_reg_0;
  wire [0:0]wr_this_rank_r;

  mig_mig_7series_v4_2_bank_compare_0 bank_compare0
       (.E(idle_ns),
        .Q(Q[1]),
        .\grant_r_reg[2] (bank_compare0_n_5),
        .hi_priority(hi_priority),
        .maint_req_r(maint_req_r),
        .ordered_r_lcl_reg(\order_q_r_reg[1]_0 ),
        .ordered_r_lcl_reg_0(ordered_r_lcl_reg),
        .ordered_r_lcl_reg_1(pre_wait_r_reg),
        .p_67_out(p_67_out),
        .pass_open_bank_r_lcl_reg(pass_open_bank_r_lcl_reg_1),
        .pass_open_bank_r_lcl_reg_0(pass_open_bank_r_lcl_reg_2),
        .periodic_rd_insert(periodic_rd_insert),
        .rb_hit_busy_r_reg_0(rb_hit_busy_r_reg),
        .rd_wr_r_lcl_reg_0(rd_wr_r_lcl_reg),
        .rd_wr_r_lcl_reg_1(idle_r_lcl_reg),
        .rd_wr_r_lcl_reg_2(rd_wr_r_lcl_reg_1),
        .\req_bank_r_lcl_reg[2]_0 (\req_bank_r_lcl_reg[2] ),
        .\req_bank_r_lcl_reg[2]_1 (\req_bank_r_lcl_reg[2]_0 ),
        .\req_col_r_reg[9]_0 (\req_col_r_reg[9] ),
        .\req_col_r_reg[9]_1 (ofs_rdy_r_reg),
        .\req_col_r_reg[9]_2 (\req_col_r_reg[9]_0 ),
        .\req_data_buf_addr_r_reg[3]_0 (\req_data_buf_addr_r_reg[3] ),
        .\req_data_buf_addr_r_reg[3]_1 (E),
        .\req_data_buf_addr_r_reg[3]_2 (\req_data_buf_addr_r_reg[3]_0 ),
        .req_periodic_rd_r(req_periodic_rd_r),
        .req_priority_r(req_priority_r),
        .\req_row_r_lcl_reg[13]_0 (\req_row_r_lcl_reg[13] ),
        .\req_row_r_lcl_reg[13]_1 (\req_row_r_lcl_reg[13]_0 ),
        .req_wr_r_lcl0(req_wr_r_lcl0),
        .req_wr_r_lcl_reg_0(req_wr_r_lcl_reg),
        .row_hit_r_reg_0(row_hit_r_reg),
        .row_hit_r_reg_1(row_hit_r_reg_0),
        .start_wtp_timer0(start_wtp_timer0),
        .wait_for_maint_r_14(wait_for_maint_r_14));
  mig_mig_7series_v4_2_bank_queue__parameterized1 bank_queue0
       (.D(ras_timer_passed_ns),
        .E(idle_ns),
        .Q(Q[1]),
        .act_wait_r_lcl_reg(act_wait_r_lcl_reg_0),
        .auto_pre_r_lcl_reg_0(auto_pre_r_lcl_reg),
        .auto_pre_r_lcl_reg_1(auto_pre_r_lcl_reg_1),
        .auto_pre_r_lcl_reg_2(auto_pre_r_lcl_reg_2),
        .auto_pre_r_lcl_reg_3(rb_hit_busy_r_reg),
        .\compute_tail.tail_r_lcl_reg_0 (\compute_tail.tail_r_lcl_reg ),
        .\compute_tail.tail_r_lcl_reg_1 (\compute_tail.tail_r_lcl_reg_0 ),
        .\grant_r[3]_i_2__0 (act_wait_r_lcl_reg),
        .\grant_r[3]_i_3_0 (\grant_r[3]_i_3 ),
        .\grant_r[3]_i_3_1 (\grant_r[3]_i_3_0 ),
        .\grant_r[3]_i_3_2 (\grant_r[3]_i_3_1 ),
        .\grant_r[3]_i_3_3 (\grant_r[3]_i_3_2 ),
        .\grant_r[3]_i_6 (\grant_r[3]_i_6 ),
        .granted_col_r_reg(granted_col_r_reg),
        .granted_col_r_reg_0(granted_col_r_reg_0),
        .granted_col_r_reg_1(granted_col_r_reg_1),
        .granted_col_r_reg_2(granted_col_r_reg_2),
        .head_r_lcl_reg_0(head_r_lcl_reg),
        .head_r_lcl_reg_1(ofs_rdy_r_reg_0),
        .head_r_lcl_reg_2(head_r_lcl_reg_0),
        .head_r_lcl_reg_3(head_r_lcl_reg_1),
        .head_r_lcl_reg_4(head_r_lcl_reg_2),
        .head_r_lcl_reg_5(head_r_lcl_reg_3),
        .i___5_i_4(i___5_i_4),
        .i___5_i_4_0(i___5_i_4_0),
        .i___5_i_4_1(i___5_i_4_1),
        .idle_r_lcl_reg_0(E),
        .idle_r_lcl_reg_1(idle_r_lcl_reg),
        .idle_r_lcl_reg_2(idle_r_lcl_reg_0),
        .\order_q_r_reg[0]_0 (bank_queue0_n_27),
        .\order_q_r_reg[0]_1 (\order_q_r_reg[0] ),
        .\order_q_r_reg[1]_0 (\order_q_r_reg[1] ),
        .\order_q_r_reg[1]_1 (\order_q_r_reg[1]_0 ),
        .\order_q_r_reg[1]_2 (\order_q_r_reg[1]_1 ),
        .ordered_r_lcl_reg_0(ordered_r_lcl_reg),
        .ordered_r_lcl_reg_1(bank_compare0_n_5),
        .p_67_out(p_67_out),
        .pass_open_bank_ns(pass_open_bank_ns),
        .pass_open_bank_r(pass_open_bank_r),
        .pass_open_bank_r_lcl_reg_0(pass_open_bank_r_lcl_reg),
        .pass_open_bank_r_lcl_reg_1(pass_open_bank_r_lcl_reg_0),
        .pass_open_bank_r_lcl_reg_2(row_hit_r_reg),
        .pre_bm_end_ns(pre_bm_end_ns),
        .pre_bm_end_r_reg_0(pre_bm_end_r_reg),
        .pre_passing_open_bank_ns(pre_passing_open_bank_ns),
        .pre_passing_open_bank_r_reg_0(pre_passing_open_bank_r_reg),
        .pre_wait_r(pre_wait_r),
        .\q_entry_r_reg[0]_0 (\q_entry_r_reg[0] ),
        .\q_entry_r_reg[0]_1 (\q_entry_r_reg[0]_0 ),
        .\q_entry_r_reg[0]_2 (\q_entry_r_reg[0]_1 ),
        .\q_entry_r_reg[1]_0 (\q_entry_r_reg[1] ),
        .\q_entry_r_reg[1]_1 (\q_entry_r_reg[1]_0 ),
        .\q_entry_r_reg[1]_2 (\q_entry_r_reg[1]_1 ),
        .\q_entry_r_reg[1]_3 (\q_entry_r_reg[1]_2 ),
        .\q_entry_r_reg[1]_4 (\q_entry_r_reg[1]_3 ),
        .q_has_priority(q_has_priority),
        .q_has_priority_r_reg_0(q_has_priority_r_reg),
        .q_has_priority_r_reg_1(rd_wr_r_lcl_reg),
        .q_has_priority_r_reg_2(req_wr_r_lcl_reg),
        .q_has_priority_r_reg_3(pre_wait_r_reg),
        .q_has_rd_7(q_has_rd_7),
        .q_has_rd_r_reg_0(ofs_rdy_r_reg),
        .q_has_rd_r_reg_1(q_has_rd_r_reg),
        .\ras_timer_r_reg[0] (bm_end_r1_reg),
        .\ras_timer_r_reg[0]_0 (\ras_timer_r_reg[0] ),
        .\ras_timer_r_reg[0]_1 (\ras_timer_r_reg[0]_0 ),
        .\ras_timer_r_reg[0]_2 (\ras_timer_r_reg[0]_1 ),
        .\ras_timer_r_reg[0]_3 (\ras_timer_r_reg[0]_2 ),
        .\ras_timer_r_reg[0]_4 (\ras_timer_r_reg[0]_3 ),
        .\ras_timer_r_reg[0]_5 (\ras_timer_r_reg[0]_4 ),
        .\ras_timer_r_reg[0]_6 (\ras_timer_r_reg[0]_5 ),
        .\ras_timer_r_reg[1] (\ras_timer_r_reg[1] ),
        .\ras_timer_r_reg[1]_0 (\ras_timer_r_reg[1]_0 ),
        .\ras_timer_r_reg[1]_1 (\ras_timer_r_reg[1]_1 ),
        .\ras_timer_r_reg[1]_2 (\ras_timer_r_reg[1]_2 ),
        .ras_timer_zero_r(ras_timer_zero_r),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] (\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 (rb_hit_busies_r[0]),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_3 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_4 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_3 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 (rb_hit_busies_r[1]),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_2 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_3 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_4 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_2 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[6] (\rb_hit_busies.rb_hit_busies_r_lcl_reg[6] ),
        .rb_hit_busies_r_0(rb_hit_busies_r_0),
        .rb_hit_busies_r_1(rb_hit_busies_r_1),
        .rb_hit_busy_r_reg(rb_hit_busy_r_reg_0),
        .rb_hit_busy_r_reg_0(rb_hit_busy_r_reg_1),
        .rb_hit_busy_r_reg_1(rb_hit_busy_r_reg_2),
        .rd_wr_r_lcl_reg(rd_wr_r_lcl_reg_0),
        .req_bank_rdy_ns(req_bank_rdy_ns),
        .req_bank_rdy_r_reg(req_bank_rdy_r_reg),
        .req_bank_rdy_r_reg_0(col_wait_r_reg),
        .req_priority_r(req_priority_r),
        .rnk_config_valid_r_lcl_reg(rnk_config_valid_r_lcl_reg),
        .rnk_config_valid_r_lcl_reg_0(rnk_config_valid_r_lcl_reg_0),
        .tail_r_17(tail_r_17),
        .use_addr(use_addr),
        .wait_for_maint_r_14(wait_for_maint_r_14),
        .wait_for_maint_r_lcl_reg_0(wait_for_maint_r_lcl_reg),
        .wait_for_maint_r_lcl_reg_1(wait_for_maint_r_lcl_reg_0));
  mig_mig_7series_v4_2_bank_state__parameterized1 bank_state0
       (.D(ras_timer_passed_ns),
        .Q(Q),
        .act_this_rank_r(act_this_rank_r),
        .act_wait_r_lcl_reg_0(act_wait_r_lcl_reg),
        .act_wait_r_lcl_reg_1(act_wait_r_lcl_reg_1),
        .act_wait_r_lcl_reg_2(act_wait_r_lcl_reg_2),
        .act_wait_r_lcl_reg_3(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ),
        .auto_pre_r_lcl_reg(auto_pre_r_lcl_reg_0),
        .bm_end_r1_0(bm_end_r1_0),
        .bm_end_r1_reg_0(bm_end_r1_reg),
        .bm_end_r1_reg_1(pre_bm_end_r_reg),
        .\cmd_pipe_plus.mc_address_reg[38] (\req_row_r_lcl_reg[13] [10]),
        .\cmd_pipe_plus.mc_address_reg[38]_0 (\cmd_pipe_plus.mc_address_reg[38] ),
        .col_wait_r_reg_0(col_wait_r_reg),
        .col_wait_r_reg_1(col_wait_r_reg_0),
        .demand_priority_r_1(demand_priority_r_1),
        .demand_priority_r_reg_0(demand_priority_r_reg),
        .demand_priority_r_reg_1(demand_priority_r_reg_0),
        .demand_priority_r_reg_2(idle_r_lcl_reg),
        .demand_priority_r_reg_3(bank_queue0_n_27),
        .demand_priority_r_reg_4(demand_priority_r_reg_1),
        .demand_priority_r_reg_5(req_wr_r_lcl_reg),
        .demanded_prior_r_2(demanded_prior_r_2),
        .demanded_prior_r_reg_0(demanded_prior_r_reg),
        .demanded_prior_r_reg_1(demanded_prior_r_reg_0),
        .ofs_rdy_r(ofs_rdy_r),
        .ofs_rdy_r0(ofs_rdy_r0),
        .ofs_rdy_r_reg_0(ofs_rdy_r_reg),
        .ofs_rdy_r_reg_1(ofs_rdy_r_reg_0),
        .override_demand_ns(override_demand_ns),
        .override_demand_r(override_demand_r),
        .pass_open_bank_ns(pass_open_bank_ns),
        .pass_open_bank_r(pass_open_bank_r),
        .\pre_4_1_1T_arb.granted_pre_r_reg (\pre_4_1_1T_arb.granted_pre_r_reg ),
        .pre_bm_end_ns(pre_bm_end_ns),
        .pre_bm_end_r_reg(pre_bm_end_r_reg_0),
        .pre_bm_end_r_reg_0(auto_pre_r_lcl_reg),
        .pre_passing_open_bank_ns(pre_passing_open_bank_ns),
        .pre_wait_r(pre_wait_r),
        .pre_wait_r_reg_0(pre_wait_r_reg),
        .q_has_rd_7(q_has_rd_7),
        .\ras_timer_r_reg[1]_0 (\ras_timer_r_reg[1] ),
        .ras_timer_zero_r(ras_timer_zero_r),
        .ras_timer_zero_r_reg_0(ras_timer_zero_r_reg),
        .ras_timer_zero_r_reg_1(ras_timer_zero_r_reg_0),
        .ras_timer_zero_r_reg_2(ras_timer_zero_r_reg_1),
        .rd_this_rank_r(rd_this_rank_r),
        .\rd_this_rank_r_reg[0]_0 (rd_wr_r_lcl_reg),
        .req_bank_rdy_ns(req_bank_rdy_ns),
        .row_cmd_wr(row_cmd_wr),
        .\rtp_timer_r_reg[0]_0 (\rtp_timer_r_reg[0] ),
        .start_wtp_timer0(start_wtp_timer0),
        .wr_this_rank_r(wr_this_rank_r));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_bank_cntrl" *) 
module mig_mig_7series_v4_2_bank_cntrl__parameterized2
   (rb_hit_busy_r_reg,
    E,
    req_periodic_rd_r,
    rd_wr_r_lcl_reg,
    req_wr_r_lcl_reg,
    act_wait_r_lcl_reg,
    act_this_rank_r,
    wr_this_rank_r,
    rd_this_rank_r,
    bm_end_r1_1,
    col_wait_r_reg,
    req_bank_rdy_ns,
    demand_priority_r_reg,
    demanded_prior_r_0,
    ofs_rdy_r,
    pass_open_bank_r_lcl_reg,
    pre_bm_end_r_11,
    q_has_rd_12,
    q_has_priority,
    wait_for_maint_r_15,
    head_r_lcl_reg,
    ordered_r_lcl_reg,
    tail_r_18,
    auto_pre_r_lcl_reg,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[6] ,
    idle_r_lcl_reg,
    rd_wr_r_lcl_reg_0,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0 ,
    bm_end_r1_reg,
    \ras_timer_r_reg[1] ,
    pre_bm_end_r_reg,
    pre_bm_end_r_reg_0,
    \q_entry_r_reg[1] ,
    \q_entry_r_reg[0] ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ,
    \q_entry_r_reg[0]_0 ,
    pre_bm_end_r_reg_1,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 ,
    pre_passing_open_bank_r_reg,
    row_hit_r_reg,
    \compute_tail.tail_r_lcl_reg ,
    \pre_4_1_1T_arb.granted_pre_ns ,
    act_wait_r_lcl_reg_0,
    auto_pre_r_lcl_reg_0,
    \req_row_r_lcl_reg[13] ,
    act_wait_r_lcl_reg_1,
    demand_priority_r_reg_0,
    \grant_r_reg[3] ,
    \req_data_buf_addr_r_reg[3] ,
    \req_bank_r_lcl_reg[2] ,
    \req_col_r_reg[9] ,
    demand_priority_r_reg_1,
    periodic_rd_insert,
    req_wr_r_lcl0,
    hi_priority,
    col_wait_r_reg_0,
    ofs_rdy_r_reg,
    ofs_rdy_r0,
    q_has_rd_r_reg,
    auto_pre_r_lcl_reg_1,
    q_has_priority_r_reg,
    wait_for_maint_r_lcl_reg,
    wait_for_maint_r_lcl_reg_0,
    head_r_lcl_reg_0,
    \compute_tail.tail_r_lcl_reg_0 ,
    auto_pre_r_lcl_reg_2,
    row_hit_r_reg_0,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_1 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_2 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ,
    Q,
    pre_wait_r_reg,
    granted_col_r_reg,
    granted_col_r_reg_0,
    granted_col_r_reg_1,
    act_wait_r_lcl_reg_2,
    \ras_timer_r_reg[0] ,
    \ras_timer_r_reg[0]_0 ,
    \ras_timer_r_reg[0]_1 ,
    \grant_r[3]_i_5 ,
    \ras_timer_r_reg[0]_2 ,
    \compute_tail.tail_r_lcl_reg_1 ,
    \compute_tail.tail_r_lcl_reg_2 ,
    \q_entry_r_reg[1]_0 ,
    \q_entry_r_reg[1]_1 ,
    \order_q_r_reg[1] ,
    head_r_lcl_reg_1,
    head_r_lcl_reg_2,
    head_r_lcl_reg_3,
    \compute_tail.tail_r_lcl_reg_3 ,
    req_bank_rdy_r_reg,
    \grant_r[3]_i_5_0 ,
    \grant_r[3]_i_5_1 ,
    \grant_r[3]_i_5_2 ,
    \grant_r[3]_i_5_3 ,
    rb_hit_busy_r_reg_0,
    rd_wr_r_lcl_reg_1,
    use_addr,
    rb_hit_busy_r_reg_1,
    rb_hit_busy_r_reg_2,
    \ras_timer_r_reg[1]_0 ,
    \ras_timer_r_reg[1]_1 ,
    \ras_timer_r_reg[1]_2 ,
    \ras_timer_r_reg[0]_3 ,
    \ras_timer_r_reg[0]_4 ,
    \ras_timer_r_reg[0]_5 ,
    \grant_r[3]_i_6 ,
    rb_hit_busies_r,
    rb_hit_busies_r_1,
    pre_bm_end_r_reg_2,
    pass_open_bank_r_lcl_reg_0,
    maint_req_r,
    pass_open_bank_r_lcl_reg_1,
    pass_open_bank_r_lcl_reg_2,
    auto_pre_r_lcl_reg_3,
    \pre_4_1_1T_arb.granted_pre_r_reg ,
    \pre_4_1_1T_arb.granted_pre_r_reg_0 ,
    \ras_timer_r_reg[0]_6 ,
    \req_row_r_lcl_reg[13]_0 ,
    row_cmd_wr,
    \cmd_pipe_plus.mc_address[10]_i_2 ,
    ras_timer_zero_r_reg,
    demanded_prior_r_reg,
    demand_priority_r,
    demanded_prior_r,
    demand_priority_r_reg_2,
    \rtp_timer_r_reg[0] ,
    \req_data_buf_addr_r_reg[3]_0 ,
    \req_bank_r_lcl_reg[2]_0 ,
    \req_col_r_reg[9]_0 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_3 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 ,
    \q_entry_r_reg[1]_2 ,
    \q_entry_r_reg[1]_3 ,
    \q_entry_r_reg[1]_4 ,
    \q_entry_r_reg[0]_1 ,
    \order_q_r_reg[1]_0 ,
    \order_q_r_reg[0] );
  output rb_hit_busy_r_reg;
  output [0:0]E;
  output [0:0]req_periodic_rd_r;
  output rd_wr_r_lcl_reg;
  output req_wr_r_lcl_reg;
  output act_wait_r_lcl_reg;
  output [0:0]act_this_rank_r;
  output [0:0]wr_this_rank_r;
  output [0:0]rd_this_rank_r;
  output bm_end_r1_1;
  output col_wait_r_reg;
  output req_bank_rdy_ns;
  output demand_priority_r_reg;
  output demanded_prior_r_0;
  output ofs_rdy_r;
  output pass_open_bank_r_lcl_reg;
  output pre_bm_end_r_11;
  output q_has_rd_12;
  output q_has_priority;
  output wait_for_maint_r_15;
  output head_r_lcl_reg;
  output ordered_r_lcl_reg;
  output tail_r_18;
  output auto_pre_r_lcl_reg;
  output [1:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[6] ;
  output idle_r_lcl_reg;
  output rd_wr_r_lcl_reg_0;
  output \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0 ;
  output bm_end_r1_reg;
  output \ras_timer_r_reg[1] ;
  output pre_bm_end_r_reg;
  output pre_bm_end_r_reg_0;
  output \q_entry_r_reg[1] ;
  output \q_entry_r_reg[0] ;
  output \rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ;
  output \q_entry_r_reg[0]_0 ;
  output pre_bm_end_r_reg_1;
  output \rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ;
  output \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ;
  output \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 ;
  output pre_passing_open_bank_r_reg;
  output row_hit_r_reg;
  output \compute_tail.tail_r_lcl_reg ;
  output \pre_4_1_1T_arb.granted_pre_ns ;
  output act_wait_r_lcl_reg_0;
  output auto_pre_r_lcl_reg_0;
  output [13:0]\req_row_r_lcl_reg[13] ;
  output act_wait_r_lcl_reg_1;
  output demand_priority_r_reg_0;
  output \grant_r_reg[3] ;
  output [3:0]\req_data_buf_addr_r_reg[3] ;
  output [2:0]\req_bank_r_lcl_reg[2] ;
  output [9:0]\req_col_r_reg[9] ;
  input demand_priority_r_reg_1;
  input periodic_rd_insert;
  input req_wr_r_lcl0;
  input hi_priority;
  input col_wait_r_reg_0;
  input ofs_rdy_r_reg;
  input ofs_rdy_r0;
  input q_has_rd_r_reg;
  input auto_pre_r_lcl_reg_1;
  input q_has_priority_r_reg;
  input wait_for_maint_r_lcl_reg;
  input wait_for_maint_r_lcl_reg_0;
  input head_r_lcl_reg_0;
  input \compute_tail.tail_r_lcl_reg_0 ;
  input auto_pre_r_lcl_reg_2;
  input [0:0]row_hit_r_reg_0;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_1 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_2 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ;
  input [1:0]Q;
  input pre_wait_r_reg;
  input granted_col_r_reg;
  input granted_col_r_reg_0;
  input granted_col_r_reg_1;
  input [1:0]act_wait_r_lcl_reg_2;
  input \ras_timer_r_reg[0] ;
  input \ras_timer_r_reg[0]_0 ;
  input \ras_timer_r_reg[0]_1 ;
  input \grant_r[3]_i_5 ;
  input \ras_timer_r_reg[0]_2 ;
  input \compute_tail.tail_r_lcl_reg_1 ;
  input \compute_tail.tail_r_lcl_reg_2 ;
  input \q_entry_r_reg[1]_0 ;
  input \q_entry_r_reg[1]_1 ;
  input \order_q_r_reg[1] ;
  input head_r_lcl_reg_1;
  input head_r_lcl_reg_2;
  input head_r_lcl_reg_3;
  input \compute_tail.tail_r_lcl_reg_3 ;
  input req_bank_rdy_r_reg;
  input \grant_r[3]_i_5_0 ;
  input \grant_r[3]_i_5_1 ;
  input \grant_r[3]_i_5_2 ;
  input \grant_r[3]_i_5_3 ;
  input rb_hit_busy_r_reg_0;
  input rd_wr_r_lcl_reg_1;
  input use_addr;
  input rb_hit_busy_r_reg_1;
  input rb_hit_busy_r_reg_2;
  input \ras_timer_r_reg[1]_0 ;
  input \ras_timer_r_reg[1]_1 ;
  input \ras_timer_r_reg[1]_2 ;
  input \ras_timer_r_reg[0]_3 ;
  input \ras_timer_r_reg[0]_4 ;
  input \ras_timer_r_reg[0]_5 ;
  input [0:0]\grant_r[3]_i_6 ;
  input [0:0]rb_hit_busies_r;
  input [0:0]rb_hit_busies_r_1;
  input [0:0]pre_bm_end_r_reg_2;
  input pass_open_bank_r_lcl_reg_0;
  input maint_req_r;
  input pass_open_bank_r_lcl_reg_1;
  input pass_open_bank_r_lcl_reg_2;
  input auto_pre_r_lcl_reg_3;
  input \pre_4_1_1T_arb.granted_pre_r_reg ;
  input \pre_4_1_1T_arb.granted_pre_r_reg_0 ;
  input \ras_timer_r_reg[0]_6 ;
  input [13:0]\req_row_r_lcl_reg[13]_0 ;
  input [0:0]row_cmd_wr;
  input [0:0]\cmd_pipe_plus.mc_address[10]_i_2 ;
  input ras_timer_zero_r_reg;
  input demanded_prior_r_reg;
  input demand_priority_r;
  input demanded_prior_r;
  input demand_priority_r_reg_2;
  input \rtp_timer_r_reg[0] ;
  input [3:0]\req_data_buf_addr_r_reg[3]_0 ;
  input [2:0]\req_bank_r_lcl_reg[2]_0 ;
  input [9:0]\req_col_r_reg[9]_0 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_3 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 ;
  input \q_entry_r_reg[1]_2 ;
  input \q_entry_r_reg[1]_3 ;
  input \q_entry_r_reg[1]_4 ;
  input \q_entry_r_reg[0]_1 ;
  input \order_q_r_reg[1]_0 ;
  input \order_q_r_reg[0] ;

  wire [0:0]E;
  wire [1:0]Q;
  wire [0:0]act_this_rank_r;
  wire act_wait_r_lcl_reg;
  wire act_wait_r_lcl_reg_0;
  wire act_wait_r_lcl_reg_1;
  wire [1:0]act_wait_r_lcl_reg_2;
  wire auto_pre_r_lcl_reg;
  wire auto_pre_r_lcl_reg_0;
  wire auto_pre_r_lcl_reg_1;
  wire auto_pre_r_lcl_reg_2;
  wire auto_pre_r_lcl_reg_3;
  wire bank_compare0_n_5;
  wire bank_queue0_n_26;
  wire bm_end_r1_1;
  wire bm_end_r1_reg;
  wire [0:0]\cmd_pipe_plus.mc_address[10]_i_2 ;
  wire col_wait_r_reg;
  wire col_wait_r_reg_0;
  wire \compute_tail.tail_r_lcl_reg ;
  wire \compute_tail.tail_r_lcl_reg_0 ;
  wire \compute_tail.tail_r_lcl_reg_1 ;
  wire \compute_tail.tail_r_lcl_reg_2 ;
  wire \compute_tail.tail_r_lcl_reg_3 ;
  wire demand_priority_r;
  wire demand_priority_r_reg;
  wire demand_priority_r_reg_0;
  wire demand_priority_r_reg_1;
  wire demand_priority_r_reg_2;
  wire demanded_prior_r;
  wire demanded_prior_r_0;
  wire demanded_prior_r_reg;
  wire \grant_r[3]_i_5 ;
  wire \grant_r[3]_i_5_0 ;
  wire \grant_r[3]_i_5_1 ;
  wire \grant_r[3]_i_5_2 ;
  wire \grant_r[3]_i_5_3 ;
  wire [0:0]\grant_r[3]_i_6 ;
  wire \grant_r_reg[3] ;
  wire granted_col_r_reg;
  wire granted_col_r_reg_0;
  wire granted_col_r_reg_1;
  wire head_r_lcl_reg;
  wire head_r_lcl_reg_0;
  wire head_r_lcl_reg_1;
  wire head_r_lcl_reg_2;
  wire head_r_lcl_reg_3;
  wire hi_priority;
  wire [3:3]idle_ns;
  wire idle_r_lcl_reg;
  wire maint_req_r;
  wire ofs_rdy_r;
  wire ofs_rdy_r0;
  wire ofs_rdy_r_reg;
  wire \order_q_r_reg[0] ;
  wire \order_q_r_reg[1] ;
  wire \order_q_r_reg[1]_0 ;
  wire ordered_r_lcl_reg;
  wire p_13_out;
  wire p_28_out;
  wire pass_open_bank_ns;
  wire pass_open_bank_r_lcl_reg;
  wire pass_open_bank_r_lcl_reg_0;
  wire pass_open_bank_r_lcl_reg_1;
  wire pass_open_bank_r_lcl_reg_2;
  wire periodic_rd_insert;
  wire \pre_4_1_1T_arb.granted_pre_ns ;
  wire \pre_4_1_1T_arb.granted_pre_r_reg ;
  wire \pre_4_1_1T_arb.granted_pre_r_reg_0 ;
  wire pre_bm_end_ns;
  wire pre_bm_end_r_11;
  wire pre_bm_end_r_reg;
  wire pre_bm_end_r_reg_0;
  wire pre_bm_end_r_reg_1;
  wire [0:0]pre_bm_end_r_reg_2;
  wire pre_passing_open_bank_ns;
  wire pre_passing_open_bank_r_reg;
  wire pre_wait_r;
  wire pre_wait_r_reg;
  wire \q_entry_r_reg[0] ;
  wire \q_entry_r_reg[0]_0 ;
  wire \q_entry_r_reg[0]_1 ;
  wire \q_entry_r_reg[1] ;
  wire \q_entry_r_reg[1]_0 ;
  wire \q_entry_r_reg[1]_1 ;
  wire \q_entry_r_reg[1]_2 ;
  wire \q_entry_r_reg[1]_3 ;
  wire \q_entry_r_reg[1]_4 ;
  wire q_has_priority;
  wire q_has_priority_r_reg;
  wire q_has_rd_12;
  wire q_has_rd_r_reg;
  wire [1:0]ras_timer_passed_ns;
  wire \ras_timer_r_reg[0] ;
  wire \ras_timer_r_reg[0]_0 ;
  wire \ras_timer_r_reg[0]_1 ;
  wire \ras_timer_r_reg[0]_2 ;
  wire \ras_timer_r_reg[0]_3 ;
  wire \ras_timer_r_reg[0]_4 ;
  wire \ras_timer_r_reg[0]_5 ;
  wire \ras_timer_r_reg[0]_6 ;
  wire \ras_timer_r_reg[1] ;
  wire \ras_timer_r_reg[1]_0 ;
  wire \ras_timer_r_reg[1]_1 ;
  wire \ras_timer_r_reg[1]_2 ;
  wire ras_timer_zero_r;
  wire ras_timer_zero_r_reg;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1 ;
  wire [1:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[6] ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_1 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_2 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_3 ;
  wire [0:0]rb_hit_busies_r;
  wire [0:0]rb_hit_busies_r_1;
  wire rb_hit_busy_r_reg;
  wire rb_hit_busy_r_reg_0;
  wire rb_hit_busy_r_reg_1;
  wire rb_hit_busy_r_reg_2;
  wire [0:0]rd_this_rank_r;
  wire rd_wr_r_lcl_reg;
  wire rd_wr_r_lcl_reg_0;
  wire rd_wr_r_lcl_reg_1;
  wire [2:0]\req_bank_r_lcl_reg[2] ;
  wire [2:0]\req_bank_r_lcl_reg[2]_0 ;
  wire req_bank_rdy_ns;
  wire req_bank_rdy_r_reg;
  wire [9:0]\req_col_r_reg[9] ;
  wire [9:0]\req_col_r_reg[9]_0 ;
  wire [3:0]\req_data_buf_addr_r_reg[3] ;
  wire [3:0]\req_data_buf_addr_r_reg[3]_0 ;
  wire [0:0]req_periodic_rd_r;
  wire req_priority_r;
  wire [13:0]\req_row_r_lcl_reg[13] ;
  wire [13:0]\req_row_r_lcl_reg[13]_0 ;
  wire req_wr_r_lcl0;
  wire req_wr_r_lcl_reg;
  wire [0:0]row_cmd_wr;
  wire row_hit_r_reg;
  wire [0:0]row_hit_r_reg_0;
  wire \rtp_timer_r_reg[0] ;
  wire start_wtp_timer0;
  wire tail_r_18;
  wire use_addr;
  wire wait_for_maint_r_15;
  wire wait_for_maint_r_lcl_reg;
  wire wait_for_maint_r_lcl_reg_0;
  wire [0:0]wr_this_rank_r;

  mig_mig_7series_v4_2_bank_compare bank_compare0
       (.E(idle_ns),
        .Q(Q[1]),
        .\grant_r_reg[3] (bank_compare0_n_5),
        .hi_priority(hi_priority),
        .maint_req_r(maint_req_r),
        .ordered_r_lcl_reg(\order_q_r_reg[1] ),
        .ordered_r_lcl_reg_0(ordered_r_lcl_reg),
        .ordered_r_lcl_reg_1(pre_wait_r_reg),
        .p_28_out(p_28_out),
        .pass_open_bank_r_lcl_reg(pass_open_bank_r_lcl_reg_1),
        .pass_open_bank_r_lcl_reg_0(pass_open_bank_r_lcl_reg_2),
        .periodic_rd_insert(periodic_rd_insert),
        .rb_hit_busy_r_reg_0(rb_hit_busy_r_reg),
        .rd_wr_r_lcl_reg_0(rd_wr_r_lcl_reg),
        .rd_wr_r_lcl_reg_1(idle_r_lcl_reg),
        .rd_wr_r_lcl_reg_2(rd_wr_r_lcl_reg_1),
        .\req_bank_r_lcl_reg[2]_0 (\req_bank_r_lcl_reg[2] ),
        .\req_bank_r_lcl_reg[2]_1 (\req_bank_r_lcl_reg[2]_0 ),
        .\req_col_r_reg[9]_0 (\req_col_r_reg[9] ),
        .\req_col_r_reg[9]_1 (\req_col_r_reg[9]_0 ),
        .\req_data_buf_addr_r_reg[3]_0 (\req_data_buf_addr_r_reg[3] ),
        .\req_data_buf_addr_r_reg[3]_1 (E),
        .\req_data_buf_addr_r_reg[3]_2 (\req_data_buf_addr_r_reg[3]_0 ),
        .req_periodic_rd_r(req_periodic_rd_r),
        .req_priority_r(req_priority_r),
        .\req_row_r_lcl_reg[13]_0 (\req_row_r_lcl_reg[13] ),
        .\req_row_r_lcl_reg[13]_1 (\req_row_r_lcl_reg[13]_0 ),
        .req_wr_r_lcl0(req_wr_r_lcl0),
        .req_wr_r_lcl_reg_0(req_wr_r_lcl_reg),
        .row_hit_r_reg_0(row_hit_r_reg),
        .row_hit_r_reg_1(demand_priority_r_reg_1),
        .row_hit_r_reg_2(row_hit_r_reg_0),
        .start_wtp_timer0(start_wtp_timer0),
        .wait_for_maint_r_15(wait_for_maint_r_15));
  mig_mig_7series_v4_2_bank_queue__parameterized2 bank_queue0
       (.D(ras_timer_passed_ns),
        .E(idle_ns),
        .Q(Q[1]),
        .act_wait_r_lcl_reg(act_wait_r_lcl_reg_0),
        .auto_pre_r_lcl_reg_0(auto_pre_r_lcl_reg),
        .auto_pre_r_lcl_reg_1(auto_pre_r_lcl_reg_1),
        .auto_pre_r_lcl_reg_2(auto_pre_r_lcl_reg_2),
        .auto_pre_r_lcl_reg_3(rb_hit_busy_r_reg),
        .auto_pre_r_lcl_reg_4(auto_pre_r_lcl_reg_3),
        .bm_end_r1_reg(rd_wr_r_lcl_reg),
        .bm_end_r1_reg_0(req_wr_r_lcl_reg),
        .\compute_tail.tail_r_lcl_reg_0 (\compute_tail.tail_r_lcl_reg ),
        .\compute_tail.tail_r_lcl_reg_1 (\compute_tail.tail_r_lcl_reg_0 ),
        .\compute_tail.tail_r_lcl_reg_2 (\compute_tail.tail_r_lcl_reg_1 ),
        .\compute_tail.tail_r_lcl_reg_3 (\compute_tail.tail_r_lcl_reg_2 ),
        .\compute_tail.tail_r_lcl_reg_4 (\compute_tail.tail_r_lcl_reg_3 ),
        .\grant_r[3]_i_5_0 (\grant_r[3]_i_5 ),
        .\grant_r[3]_i_5_1 (\grant_r[3]_i_5_0 ),
        .\grant_r[3]_i_5_2 (\grant_r[3]_i_5_1 ),
        .\grant_r[3]_i_5_3 (\grant_r[3]_i_5_2 ),
        .\grant_r[3]_i_5_4 (\grant_r[3]_i_5_3 ),
        .\grant_r[3]_i_6 (\grant_r[3]_i_6 ),
        .granted_col_r_reg(granted_col_r_reg),
        .granted_col_r_reg_0(granted_col_r_reg_0),
        .granted_col_r_reg_1(granted_col_r_reg_1),
        .head_r_lcl_reg_0(head_r_lcl_reg),
        .head_r_lcl_reg_1(ofs_rdy_r_reg),
        .head_r_lcl_reg_2(head_r_lcl_reg_0),
        .head_r_lcl_reg_3(head_r_lcl_reg_1),
        .head_r_lcl_reg_4(head_r_lcl_reg_2),
        .head_r_lcl_reg_5(head_r_lcl_reg_3),
        .i___74(act_wait_r_lcl_reg),
        .idle_r_lcl_reg_0(E),
        .idle_r_lcl_reg_1(idle_r_lcl_reg),
        .\order_q_r_reg[0]_0 (bank_queue0_n_26),
        .\order_q_r_reg[0]_1 (pre_wait_r_reg),
        .\order_q_r_reg[0]_2 (\order_q_r_reg[0] ),
        .\order_q_r_reg[1]_0 (demand_priority_r_reg_1),
        .\order_q_r_reg[1]_1 (\order_q_r_reg[1] ),
        .\order_q_r_reg[1]_2 (\order_q_r_reg[1]_0 ),
        .ordered_r_lcl_reg_0(ordered_r_lcl_reg),
        .ordered_r_lcl_reg_1(bank_compare0_n_5),
        .p_13_out(p_13_out),
        .p_28_out(p_28_out),
        .pass_open_bank_ns(pass_open_bank_ns),
        .pass_open_bank_r_lcl_reg_0(pass_open_bank_r_lcl_reg),
        .pass_open_bank_r_lcl_reg_1(pass_open_bank_r_lcl_reg_0),
        .pass_open_bank_r_lcl_reg_2(row_hit_r_reg),
        .pre_bm_end_ns(pre_bm_end_ns),
        .pre_bm_end_r_11(pre_bm_end_r_11),
        .pre_bm_end_r_reg_0(pre_bm_end_r_reg_0),
        .pre_bm_end_r_reg_1(pre_bm_end_r_reg),
        .pre_bm_end_r_reg_2(pre_bm_end_r_reg_1),
        .pre_passing_open_bank_ns(pre_passing_open_bank_ns),
        .pre_passing_open_bank_r_reg_0(pre_passing_open_bank_r_reg),
        .pre_wait_r(pre_wait_r),
        .\q_entry_r_reg[0]_0 (\q_entry_r_reg[0] ),
        .\q_entry_r_reg[0]_1 (\q_entry_r_reg[0]_0 ),
        .\q_entry_r_reg[0]_2 (\q_entry_r_reg[0]_1 ),
        .\q_entry_r_reg[1]_0 (\q_entry_r_reg[1] ),
        .\q_entry_r_reg[1]_1 (\q_entry_r_reg[1]_0 ),
        .\q_entry_r_reg[1]_2 (\q_entry_r_reg[1]_1 ),
        .\q_entry_r_reg[1]_3 (\q_entry_r_reg[1]_2 ),
        .\q_entry_r_reg[1]_4 (\q_entry_r_reg[1]_3 ),
        .\q_entry_r_reg[1]_5 (\q_entry_r_reg[1]_4 ),
        .q_has_priority(q_has_priority),
        .q_has_priority_r_reg_0(q_has_priority_r_reg),
        .q_has_rd_12(q_has_rd_12),
        .q_has_rd_r_reg_0(q_has_rd_r_reg),
        .\ras_timer_r_reg[0] (bm_end_r1_reg),
        .\ras_timer_r_reg[0]_0 (\ras_timer_r_reg[0] ),
        .\ras_timer_r_reg[0]_1 (\ras_timer_r_reg[0]_0 ),
        .\ras_timer_r_reg[0]_2 (\ras_timer_r_reg[0]_1 ),
        .\ras_timer_r_reg[0]_3 (\ras_timer_r_reg[0]_2 ),
        .\ras_timer_r_reg[0]_4 (\ras_timer_r_reg[0]_3 ),
        .\ras_timer_r_reg[0]_5 (\ras_timer_r_reg[0]_4 ),
        .\ras_timer_r_reg[0]_6 (\ras_timer_r_reg[0]_5 ),
        .\ras_timer_r_reg[1] (\ras_timer_r_reg[1] ),
        .\ras_timer_r_reg[1]_0 (\ras_timer_r_reg[1]_0 ),
        .\ras_timer_r_reg[1]_1 (\ras_timer_r_reg[1]_1 ),
        .\ras_timer_r_reg[1]_2 (\ras_timer_r_reg[1]_2 ),
        .ras_timer_zero_r(ras_timer_zero_r),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] (\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_3 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[6] [0]),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_2 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_3 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[6] [1]),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_1 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_2 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_1 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_3 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_2 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_4 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_3 ),
        .rb_hit_busies_r(rb_hit_busies_r),
        .rb_hit_busies_r_1(rb_hit_busies_r_1),
        .rb_hit_busy_r_reg(rb_hit_busy_r_reg_0),
        .rb_hit_busy_r_reg_0(rb_hit_busy_r_reg_1),
        .rb_hit_busy_r_reg_1(rb_hit_busy_r_reg_2),
        .rd_wr_r_lcl_reg(rd_wr_r_lcl_reg_0),
        .req_bank_rdy_ns(req_bank_rdy_ns),
        .req_bank_rdy_r_reg(col_wait_r_reg),
        .req_bank_rdy_r_reg_0(req_bank_rdy_r_reg),
        .req_priority_r(req_priority_r),
        .tail_r_18(tail_r_18),
        .use_addr(use_addr),
        .wait_for_maint_r_15(wait_for_maint_r_15),
        .wait_for_maint_r_lcl_reg_0(wait_for_maint_r_lcl_reg),
        .wait_for_maint_r_lcl_reg_1(wait_for_maint_r_lcl_reg_0));
  mig_mig_7series_v4_2_bank_state__parameterized2 bank_state0
       (.D(ras_timer_passed_ns),
        .Q(Q),
        .act_this_rank_r(act_this_rank_r),
        .act_wait_r_lcl_reg_0(act_wait_r_lcl_reg),
        .act_wait_r_lcl_reg_1(act_wait_r_lcl_reg_1),
        .act_wait_r_lcl_reg_2(pre_bm_end_r_reg),
        .act_wait_r_lcl_reg_3(act_wait_r_lcl_reg_2),
        .act_wait_r_lcl_reg_4(\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0 ),
        .auto_pre_r_lcl_reg(auto_pre_r_lcl_reg_0),
        .bm_end_r1_1(bm_end_r1_1),
        .bm_end_r1_reg_0(bm_end_r1_reg),
        .\cmd_pipe_plus.mc_address[10]_i_2 (\req_row_r_lcl_reg[13] [10]),
        .\cmd_pipe_plus.mc_address[10]_i_2_0 (\cmd_pipe_plus.mc_address[10]_i_2 ),
        .col_wait_r_reg_0(col_wait_r_reg),
        .col_wait_r_reg_1(col_wait_r_reg_0),
        .demand_priority_r(demand_priority_r),
        .demand_priority_r_reg_0(demand_priority_r_reg),
        .demand_priority_r_reg_1(demand_priority_r_reg_0),
        .demand_priority_r_reg_2(demand_priority_r_reg_1),
        .demand_priority_r_reg_3(idle_r_lcl_reg),
        .demand_priority_r_reg_4(bank_queue0_n_26),
        .demand_priority_r_reg_5(demand_priority_r_reg_2),
        .demand_priority_r_reg_6(req_wr_r_lcl_reg),
        .demanded_prior_r(demanded_prior_r),
        .demanded_prior_r_reg_0(demanded_prior_r_0),
        .demanded_prior_r_reg_1(demanded_prior_r_reg),
        .\grant_r_reg[3] (\grant_r_reg[3] ),
        .ofs_rdy_r(ofs_rdy_r),
        .ofs_rdy_r0(ofs_rdy_r0),
        .ofs_rdy_r_reg_0(ofs_rdy_r_reg),
        .p_13_out(p_13_out),
        .pass_open_bank_ns(pass_open_bank_ns),
        .\pre_4_1_1T_arb.granted_pre_ns (\pre_4_1_1T_arb.granted_pre_ns ),
        .\pre_4_1_1T_arb.granted_pre_r_reg (\pre_4_1_1T_arb.granted_pre_r_reg ),
        .\pre_4_1_1T_arb.granted_pre_r_reg_0 (\pre_4_1_1T_arb.granted_pre_r_reg_0 ),
        .pre_bm_end_ns(pre_bm_end_ns),
        .pre_bm_end_r_reg(pre_bm_end_r_reg_2),
        .pre_bm_end_r_reg_0(auto_pre_r_lcl_reg),
        .pre_passing_open_bank_ns(pre_passing_open_bank_ns),
        .pre_wait_r(pre_wait_r),
        .pre_wait_r_reg_0(pre_wait_r_reg),
        .q_has_rd_12(q_has_rd_12),
        .\ras_timer_r_reg[0]_0 (\ras_timer_r_reg[0]_6 ),
        .\ras_timer_r_reg[1]_0 (\ras_timer_r_reg[1] ),
        .ras_timer_zero_r(ras_timer_zero_r),
        .ras_timer_zero_r_reg_0(ras_timer_zero_r_reg),
        .rd_this_rank_r(rd_this_rank_r),
        .\rd_this_rank_r_reg[0]_0 (rd_wr_r_lcl_reg),
        .req_bank_rdy_ns(req_bank_rdy_ns),
        .row_cmd_wr(row_cmd_wr),
        .\rtp_timer_r_reg[0]_0 (\rtp_timer_r_reg[0] ),
        .\rtp_timer_r_reg[1]_0 (pass_open_bank_r_lcl_reg),
        .start_wtp_timer0(start_wtp_timer0),
        .wr_this_rank_r(wr_this_rank_r));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_bank_common" *) 
module mig_mig_7series_v4_2_bank_common
   (accept_internal_r_reg_0,
    periodic_rd_ack_r_lcl_reg_0,
    accept_r_reg_0,
    accept_ns,
    was_wr,
    hi_priority,
    \generate_maint_cmds.insert_maint_r_lcl_reg_0 ,
    \maint_controller.maint_wip_r_lcl_reg_0 ,
    periodic_rd_cntr_r_reg_0,
    req_wr_r_lcl0,
    clear_periodic_rd_request,
    accept_r_reg_1,
    set_order_q,
    accept_r_reg_2,
    set_order_q_22,
    accept_r_reg_3,
    set_order_q_23,
    accept_r_reg_4,
    set_order_q_24,
    periodic_rd_insert,
    Q,
    q_has_priority_r_reg,
    q_has_priority_r_reg_0,
    idle_r_lcl_reg,
    periodic_rd_ack_r_lcl_reg_1,
    q_has_priority_r_reg_1,
    rb_hit_busy_r_reg,
    q_has_priority_r_reg_2,
    rb_hit_busy_r_reg_0,
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]_0 ,
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_0 ,
    \maint_controller.maint_hit_busies_r_reg[3]_0 ,
    p_9_in,
    \maint_controller.maint_wip_r_lcl_reg_1 ,
    maint_srx_r,
    \maint_controller.maint_wip_r_lcl_reg_2 ,
    \maint_controller.maint_wip_r_lcl_reg_3 ,
    periodic_rd_cntr_r_reg_1,
    periodic_rd_cntr_r_reg_2,
    periodic_rd_r,
    cmd,
    \periodic_read_request.periodic_rd_grant_r ,
    \maint_controller.maint_hit_busies_r_reg[3]_1 ,
    i___6_i_1,
    use_addr,
    E,
    i___5_i_1,
    \q_entry_r_reg[0] ,
    i___3_i_2,
    \q_entry_r_reg[0]_0 ,
    i___4_i_1,
    \q_entry_r_reg[0]_1 ,
    head_r,
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_0 ,
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1]_0 ,
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_1 ,
    maint_req_r,
    q_has_priority,
    rb_hit_busy_r,
    q_has_priority_0,
    q_has_priority_1,
    q_has_priority_2,
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ,
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]_1 ,
    maint_zq_r,
    was_priority_reg_0,
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_1 );
  output accept_internal_r_reg_0;
  output periodic_rd_ack_r_lcl_reg_0;
  output accept_r_reg_0;
  output accept_ns;
  output was_wr;
  output hi_priority;
  output \generate_maint_cmds.insert_maint_r_lcl_reg_0 ;
  output \maint_controller.maint_wip_r_lcl_reg_0 ;
  output periodic_rd_cntr_r_reg_0;
  output req_wr_r_lcl0;
  output clear_periodic_rd_request;
  output accept_r_reg_1;
  output set_order_q;
  output accept_r_reg_2;
  output set_order_q_22;
  output accept_r_reg_3;
  output set_order_q_23;
  output accept_r_reg_4;
  output set_order_q_24;
  output periodic_rd_insert;
  output [3:0]Q;
  output q_has_priority_r_reg;
  output q_has_priority_r_reg_0;
  output idle_r_lcl_reg;
  output periodic_rd_ack_r_lcl_reg_1;
  output q_has_priority_r_reg_1;
  output rb_hit_busy_r_reg;
  output q_has_priority_r_reg_2;
  output rb_hit_busy_r_reg_0;
  output \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]_0 ;
  output \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_0 ;
  output [3:0]\maint_controller.maint_hit_busies_r_reg[3]_0 ;
  input p_9_in;
  input \maint_controller.maint_wip_r_lcl_reg_1 ;
  input maint_srx_r;
  input \maint_controller.maint_wip_r_lcl_reg_2 ;
  input \maint_controller.maint_wip_r_lcl_reg_3 ;
  input periodic_rd_cntr_r_reg_1;
  input periodic_rd_cntr_r_reg_2;
  input periodic_rd_r;
  input [1:0]cmd;
  input \periodic_read_request.periodic_rd_grant_r ;
  input [3:0]\maint_controller.maint_hit_busies_r_reg[3]_1 ;
  input i___6_i_1;
  input use_addr;
  input [0:0]E;
  input i___5_i_1;
  input [0:0]\q_entry_r_reg[0] ;
  input i___3_i_2;
  input [0:0]\q_entry_r_reg[0]_0 ;
  input i___4_i_1;
  input [0:0]\q_entry_r_reg[0]_1 ;
  input [3:0]head_r;
  input \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_0 ;
  input \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1]_0 ;
  input \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_1 ;
  input maint_req_r;
  input q_has_priority;
  input [3:0]rb_hit_busy_r;
  input q_has_priority_0;
  input q_has_priority_1;
  input q_has_priority_2;
  input \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ;
  input \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]_1 ;
  input maint_zq_r;
  input was_priority_reg_0;
  input [1:0]\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_1 ;

  wire [0:0]E;
  wire [3:0]Q;
  wire accept_internal_r_reg_0;
  wire accept_ns;
  wire accept_r_reg_0;
  wire accept_r_reg_1;
  wire accept_r_reg_2;
  wire accept_r_reg_3;
  wire accept_r_reg_4;
  wire clear_periodic_rd_request;
  wire [1:0]cmd;
  wire \generate_maint_cmds.insert_maint_ns ;
  wire \generate_maint_cmds.insert_maint_r_lcl_reg_0 ;
  wire [3:0]head_r;
  wire hi_priority;
  wire i___3_i_2;
  wire i___4_i_1;
  wire i___5_i_1;
  wire i___6_i_1;
  wire idle_r_lcl_reg;
  wire [3:0]\maint_controller.maint_hit_busies_r_reg[3]_0 ;
  wire [3:0]\maint_controller.maint_hit_busies_r_reg[3]_1 ;
  wire \maint_controller.maint_rdy ;
  wire \maint_controller.maint_rdy_r1 ;
  wire \maint_controller.maint_rdy_r1_i_2_n_0 ;
  wire \maint_controller.maint_srx_r1 ;
  wire \maint_controller.maint_wip_r_lcl_reg_0 ;
  wire \maint_controller.maint_wip_r_lcl_reg_1 ;
  wire \maint_controller.maint_wip_r_lcl_reg_2 ;
  wire \maint_controller.maint_wip_r_lcl_reg_3 ;
  wire maint_req_r;
  wire maint_srx_r;
  wire maint_zq_r;
  wire p_9_in;
  wire periodic_rd_ack_ns;
  wire periodic_rd_ack_r_lcl_reg_0;
  wire periodic_rd_ack_r_lcl_reg_1;
  wire periodic_rd_cntr_r_reg_0;
  wire periodic_rd_cntr_r_reg_1;
  wire periodic_rd_cntr_r_reg_2;
  wire periodic_rd_insert;
  wire periodic_rd_r;
  wire \periodic_read_request.periodic_rd_grant_r ;
  wire [0:0]\q_entry_r_reg[0] ;
  wire [0:0]\q_entry_r_reg[0]_0 ;
  wire [0:0]\q_entry_r_reg[0]_1 ;
  wire q_has_priority;
  wire q_has_priority_0;
  wire q_has_priority_1;
  wire q_has_priority_2;
  wire q_has_priority_r_reg;
  wire q_has_priority_r_reg_0;
  wire q_has_priority_r_reg_1;
  wire q_has_priority_r_reg_2;
  wire [3:0]rb_hit_busy_r;
  wire rb_hit_busy_r_reg;
  wire rb_hit_busy_r_reg_0;
  wire req_wr_r_lcl0;
  wire [6:1]\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_ns ;
  wire [7:4]\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r ;
  wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_1_n_0 ;
  wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ;
  wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1]_0 ;
  wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_0 ;
  wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_1 ;
  wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]_0 ;
  wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]_1 ;
  wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_0 ;
  wire [1:0]\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_1 ;
  wire set_order_q;
  wire set_order_q_22;
  wire set_order_q_23;
  wire set_order_q_24;
  wire use_addr;
  wire was_priority;
  wire was_priority_reg_0;
  wire was_wr;
  wire was_wr0;

  FDRE accept_internal_r_reg
       (.C(\maint_controller.maint_wip_r_lcl_reg_1 ),
        .CE(1'b1),
        .D(p_9_in),
        .Q(accept_internal_r_reg_0),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair1192" *) 
  LUT4 #(
    .INIT(16'h80AA)) 
    accept_r_i_1
       (.I0(p_9_in),
        .I1(periodic_rd_ack_r_lcl_reg_0),
        .I2(periodic_rd_cntr_r_reg_0),
        .I3(periodic_rd_r),
        .O(accept_ns));
  FDRE accept_r_reg
       (.C(\maint_controller.maint_wip_r_lcl_reg_1 ),
        .CE(1'b1),
        .D(accept_ns),
        .Q(accept_r_reg_0),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h4F44)) 
    \generate_maint_cmds.insert_maint_r_lcl_i_1 
       (.I0(\maint_controller.maint_srx_r1 ),
        .I1(maint_srx_r),
        .I2(\maint_controller.maint_rdy_r1 ),
        .I3(\maint_controller.maint_rdy ),
        .O(\generate_maint_cmds.insert_maint_ns ));
  FDRE \generate_maint_cmds.insert_maint_r_lcl_reg 
       (.C(\maint_controller.maint_wip_r_lcl_reg_1 ),
        .CE(1'b1),
        .D(\generate_maint_cmds.insert_maint_ns ),
        .Q(\generate_maint_cmds.insert_maint_r_lcl_reg_0 ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair1194" *) 
  LUT2 #(
    .INIT(4'h8)) 
    i___20_i_3
       (.I0(periodic_rd_ack_r_lcl_reg_0),
        .I1(\periodic_read_request.periodic_rd_grant_r ),
        .O(clear_periodic_rd_request));
  LUT5 #(
    .INIT(32'hE0000000)) 
    i___2_i_1
       (.I0(use_addr),
        .I1(periodic_rd_ack_r_lcl_reg_0),
        .I2(head_r[0]),
        .I3(\q_entry_r_reg[0]_0 ),
        .I4(accept_internal_r_reg_0),
        .O(set_order_q_23));
  (* SOFT_HLUTNM = "soft_lutpair1193" *) 
  LUT3 #(
    .INIT(8'hEA)) 
    i___34_i_2
       (.I0(periodic_rd_ack_r_lcl_reg_0),
        .I1(accept_r_reg_0),
        .I2(use_addr),
        .O(periodic_rd_ack_r_lcl_reg_1));
  LUT6 #(
    .INIT(64'h3333300055555555)) 
    i___3_i_4
       (.I0(i___3_i_2),
        .I1(set_order_q_23),
        .I2(use_addr),
        .I3(accept_r_reg_0),
        .I4(periodic_rd_ack_r_lcl_reg_0),
        .I5(\q_entry_r_reg[0]_0 ),
        .O(accept_r_reg_3));
  LUT6 #(
    .INIT(64'hCCCCCFFFAAAAAAAA)) 
    i___4_i_3
       (.I0(i___4_i_1),
        .I1(set_order_q_24),
        .I2(use_addr),
        .I3(accept_r_reg_0),
        .I4(periodic_rd_ack_r_lcl_reg_0),
        .I5(\q_entry_r_reg[0]_1 ),
        .O(accept_r_reg_4));
  LUT6 #(
    .INIT(64'hCCCCCFFFAAAAAAAA)) 
    i___5_i_4
       (.I0(i___5_i_1),
        .I1(set_order_q_22),
        .I2(use_addr),
        .I3(accept_r_reg_0),
        .I4(periodic_rd_ack_r_lcl_reg_0),
        .I5(\q_entry_r_reg[0] ),
        .O(accept_r_reg_2));
  LUT5 #(
    .INIT(32'h55555556)) 
    i___60_i_1
       (.I0(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r [7]),
        .I1(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r [4]),
        .I2(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r [5]),
        .I3(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]_1 ),
        .I4(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r [6]),
        .O(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_0 ));
  LUT6 #(
    .INIT(64'h3333300055555555)) 
    i___6_i_3
       (.I0(i___6_i_1),
        .I1(set_order_q),
        .I2(use_addr),
        .I3(accept_r_reg_0),
        .I4(periodic_rd_ack_r_lcl_reg_0),
        .I5(E),
        .O(accept_r_reg_1));
  LUT5 #(
    .INIT(32'hE0000000)) 
    i___7_i_1
       (.I0(use_addr),
        .I1(periodic_rd_ack_r_lcl_reg_0),
        .I2(head_r[1]),
        .I3(\q_entry_r_reg[0]_1 ),
        .I4(accept_internal_r_reg_0),
        .O(set_order_q_24));
  (* SOFT_HLUTNM = "soft_lutpair1194" *) 
  LUT4 #(
    .INIT(16'hAA80)) 
    i___7_i_2
       (.I0(rb_hit_busy_r[1]),
        .I1(use_addr),
        .I2(accept_r_reg_0),
        .I3(periodic_rd_ack_r_lcl_reg_0),
        .O(rb_hit_busy_r_reg_0));
  LUT5 #(
    .INIT(32'h00000001)) 
    i___82_i_1
       (.I0(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r [4]),
        .I1(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r [5]),
        .I2(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r [7]),
        .I3(Q[3]),
        .I4(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r [6]),
        .O(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]_0 ));
  LUT5 #(
    .INIT(32'hE0000000)) 
    i___8_i_1
       (.I0(use_addr),
        .I1(periodic_rd_ack_r_lcl_reg_0),
        .I2(head_r[2]),
        .I3(\q_entry_r_reg[0] ),
        .I4(accept_internal_r_reg_0),
        .O(set_order_q_22));
  (* SOFT_HLUTNM = "soft_lutpair1193" *) 
  LUT4 #(
    .INIT(16'hAA80)) 
    i___8_i_2
       (.I0(rb_hit_busy_r[2]),
        .I1(use_addr),
        .I2(accept_r_reg_0),
        .I3(periodic_rd_ack_r_lcl_reg_0),
        .O(rb_hit_busy_r_reg));
  LUT5 #(
    .INIT(32'hE0000000)) 
    i___9_i_1
       (.I0(use_addr),
        .I1(periodic_rd_ack_r_lcl_reg_0),
        .I2(head_r[3]),
        .I3(E),
        .I4(accept_internal_r_reg_0),
        .O(set_order_q));
  FDRE \maint_controller.maint_hit_busies_r_reg[0] 
       (.C(\maint_controller.maint_wip_r_lcl_reg_1 ),
        .CE(1'b1),
        .D(\maint_controller.maint_hit_busies_r_reg[3]_1 [0]),
        .Q(\maint_controller.maint_hit_busies_r_reg[3]_0 [0]),
        .R(1'b0));
  FDRE \maint_controller.maint_hit_busies_r_reg[1] 
       (.C(\maint_controller.maint_wip_r_lcl_reg_1 ),
        .CE(1'b1),
        .D(\maint_controller.maint_hit_busies_r_reg[3]_1 [1]),
        .Q(\maint_controller.maint_hit_busies_r_reg[3]_0 [1]),
        .R(1'b0));
  FDRE \maint_controller.maint_hit_busies_r_reg[2] 
       (.C(\maint_controller.maint_wip_r_lcl_reg_1 ),
        .CE(1'b1),
        .D(\maint_controller.maint_hit_busies_r_reg[3]_1 [2]),
        .Q(\maint_controller.maint_hit_busies_r_reg[3]_0 [2]),
        .R(1'b0));
  FDRE \maint_controller.maint_hit_busies_r_reg[3] 
       (.C(\maint_controller.maint_wip_r_lcl_reg_1 ),
        .CE(1'b1),
        .D(\maint_controller.maint_hit_busies_r_reg[3]_1 [3]),
        .Q(\maint_controller.maint_hit_busies_r_reg[3]_0 [3]),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h00000004)) 
    \maint_controller.maint_rdy_r1_i_1 
       (.I0(\maint_controller.maint_hit_busies_r_reg[3]_1 [1]),
        .I1(\maint_controller.maint_rdy_r1_i_2_n_0 ),
        .I2(\maint_controller.maint_hit_busies_r_reg[3]_1 [0]),
        .I3(\maint_controller.maint_hit_busies_r_reg[3]_1 [2]),
        .I4(\maint_controller.maint_hit_busies_r_reg[3]_1 [3]),
        .O(\maint_controller.maint_rdy ));
  LUT3 #(
    .INIT(8'hBA)) 
    \maint_controller.maint_rdy_r1_i_2 
       (.I0(\maint_controller.maint_wip_r_lcl_reg_0 ),
        .I1(periodic_rd_cntr_r_reg_0),
        .I2(maint_req_r),
        .O(\maint_controller.maint_rdy_r1_i_2_n_0 ));
  FDRE \maint_controller.maint_rdy_r1_reg 
       (.C(\maint_controller.maint_wip_r_lcl_reg_1 ),
        .CE(1'b1),
        .D(\maint_controller.maint_rdy ),
        .Q(\maint_controller.maint_rdy_r1 ),
        .R(1'b0));
  FDRE \maint_controller.maint_srx_r1_reg 
       (.C(\maint_controller.maint_wip_r_lcl_reg_1 ),
        .CE(1'b1),
        .D(maint_srx_r),
        .Q(\maint_controller.maint_srx_r1 ),
        .R(1'b0));
  FDRE \maint_controller.maint_wip_r_lcl_reg 
       (.C(\maint_controller.maint_wip_r_lcl_reg_1 ),
        .CE(1'b1),
        .D(\maint_controller.maint_wip_r_lcl_reg_3 ),
        .Q(\maint_controller.maint_wip_r_lcl_reg_0 ),
        .R(\maint_controller.maint_wip_r_lcl_reg_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1192" *) 
  LUT4 #(
    .INIT(16'h2A00)) 
    periodic_rd_ack_r_lcl_i_1
       (.I0(p_9_in),
        .I1(periodic_rd_ack_r_lcl_reg_0),
        .I2(periodic_rd_cntr_r_reg_0),
        .I3(periodic_rd_r),
        .O(periodic_rd_ack_ns));
  FDRE periodic_rd_ack_r_lcl_reg
       (.C(\maint_controller.maint_wip_r_lcl_reg_1 ),
        .CE(1'b1),
        .D(periodic_rd_ack_ns),
        .Q(periodic_rd_ack_r_lcl_reg_0),
        .R(1'b0));
  FDRE periodic_rd_cntr_r_reg
       (.C(\maint_controller.maint_wip_r_lcl_reg_1 ),
        .CE(1'b1),
        .D(periodic_rd_cntr_r_reg_2),
        .Q(periodic_rd_cntr_r_reg_0),
        .R(periodic_rd_cntr_r_reg_1));
  LUT5 #(
    .INIT(32'h96696996)) 
    \q_entry_r[0]_i_2__2 
       (.I0(periodic_rd_ack_r_lcl_reg_1),
        .I1(E),
        .I2(\q_entry_r_reg[0] ),
        .I3(\q_entry_r_reg[0]_1 ),
        .I4(\q_entry_r_reg[0]_0 ),
        .O(idle_r_lcl_reg));
  LUT6 #(
    .INIT(64'hFFEAAAAAAAAAAAAA)) 
    q_has_priority_r_i_1
       (.I0(q_has_priority),
        .I1(use_addr),
        .I2(accept_r_reg_0),
        .I3(periodic_rd_ack_r_lcl_reg_0),
        .I4(rb_hit_busy_r[3]),
        .I5(was_priority),
        .O(q_has_priority_r_reg));
  LUT6 #(
    .INIT(64'hFFEAAAAAAAAAAAAA)) 
    q_has_priority_r_i_1__0
       (.I0(q_has_priority_0),
        .I1(use_addr),
        .I2(accept_r_reg_0),
        .I3(periodic_rd_ack_r_lcl_reg_0),
        .I4(rb_hit_busy_r[0]),
        .I5(was_priority),
        .O(q_has_priority_r_reg_0));
  LUT6 #(
    .INIT(64'hEEEEEAAAAAAAAAAA)) 
    q_has_priority_r_i_1__1
       (.I0(q_has_priority_1),
        .I1(rb_hit_busy_r[2]),
        .I2(use_addr),
        .I3(accept_r_reg_0),
        .I4(periodic_rd_ack_r_lcl_reg_0),
        .I5(was_priority),
        .O(q_has_priority_r_reg_1));
  LUT6 #(
    .INIT(64'hEEEEEAAAAAAAAAAA)) 
    q_has_priority_r_i_1__2
       (.I0(q_has_priority_2),
        .I1(rb_hit_busy_r[1]),
        .I2(use_addr),
        .I3(accept_r_reg_0),
        .I4(periodic_rd_ack_r_lcl_reg_0),
        .I5(was_priority),
        .O(q_has_priority_r_reg_2));
  (* SOFT_HLUTNM = "soft_lutpair1191" *) 
  LUT3 #(
    .INIT(8'h2A)) 
    req_periodic_rd_r_lcl_i_1
       (.I0(periodic_rd_r),
        .I1(periodic_rd_cntr_r_reg_0),
        .I2(periodic_rd_ack_r_lcl_reg_0),
        .O(periodic_rd_insert));
  (* SOFT_HLUTNM = "soft_lutpair1191" *) 
  LUT5 #(
    .INIT(32'hD500D5D5)) 
    req_wr_r_lcl_i_1
       (.I0(periodic_rd_r),
        .I1(periodic_rd_cntr_r_reg_0),
        .I2(periodic_rd_ack_r_lcl_reg_0),
        .I3(cmd[1]),
        .I4(cmd[0]),
        .O(req_wr_r_lcl0));
  LUT5 #(
    .INIT(32'hAAAAAAEB)) 
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[1]_i_1 
       (.I0(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_0 ),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1]_0 ),
        .I4(\generate_maint_cmds.insert_maint_r_lcl_reg_0 ),
        .O(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_ns [1]));
  LUT5 #(
    .INIT(32'h11100001)) 
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[2]_i_1 
       (.I0(\generate_maint_cmds.insert_maint_r_lcl_reg_0 ),
        .I1(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(Q[2]),
        .O(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_ns [2]));
  LUT6 #(
    .INIT(64'hEEEEEEEBAAAAAAAA)) 
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[3]_i_1 
       (.I0(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_0 ),
        .I1(Q[3]),
        .I2(Q[2]),
        .I3(Q[1]),
        .I4(Q[0]),
        .I5(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_1 ),
        .O(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_ns [3]));
  LUT5 #(
    .INIT(32'h0000F909)) 
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[4]_i_1 
       (.I0(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r [4]),
        .I1(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]_1 ),
        .I2(\generate_maint_cmds.insert_maint_r_lcl_reg_0 ),
        .I3(maint_zq_r),
        .I4(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ),
        .O(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_ns [4]));
  LUT5 #(
    .INIT(32'h11100001)) 
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[5]_i_1 
       (.I0(\generate_maint_cmds.insert_maint_r_lcl_reg_0 ),
        .I1(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ),
        .I2(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r [4]),
        .I3(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]_1 ),
        .I4(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r [5]),
        .O(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_ns [5]));
  LUT6 #(
    .INIT(64'h1111111000000001)) 
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[6]_i_1 
       (.I0(\generate_maint_cmds.insert_maint_r_lcl_reg_0 ),
        .I1(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ),
        .I2(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r [4]),
        .I3(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r [5]),
        .I4(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]_1 ),
        .I5(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r [6]),
        .O(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_ns [6]));
  LUT6 #(
    .INIT(64'hFFFFFFFEFFFFFFFF)) 
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_1 
       (.I0(Q[0]),
        .I1(Q[1]),
        .I2(Q[2]),
        .I3(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ),
        .I4(\generate_maint_cmds.insert_maint_r_lcl_reg_0 ),
        .I5(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]_0 ),
        .O(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_1_n_0 ));
  FDRE \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] 
       (.C(\maint_controller.maint_wip_r_lcl_reg_1 ),
        .CE(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_1_n_0 ),
        .D(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_1 [0]),
        .Q(Q[0]),
        .R(1'b0));
  FDRE \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1] 
       (.C(\maint_controller.maint_wip_r_lcl_reg_1 ),
        .CE(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_1_n_0 ),
        .D(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_ns [1]),
        .Q(Q[1]),
        .R(1'b0));
  FDRE \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[2] 
       (.C(\maint_controller.maint_wip_r_lcl_reg_1 ),
        .CE(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_1_n_0 ),
        .D(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_ns [2]),
        .Q(Q[2]),
        .R(1'b0));
  FDRE \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] 
       (.C(\maint_controller.maint_wip_r_lcl_reg_1 ),
        .CE(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_1_n_0 ),
        .D(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_ns [3]),
        .Q(Q[3]),
        .R(1'b0));
  FDRE \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4] 
       (.C(\maint_controller.maint_wip_r_lcl_reg_1 ),
        .CE(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_1_n_0 ),
        .D(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_ns [4]),
        .Q(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r [4]),
        .R(1'b0));
  FDRE \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[5] 
       (.C(\maint_controller.maint_wip_r_lcl_reg_1 ),
        .CE(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_1_n_0 ),
        .D(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_ns [5]),
        .Q(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r [5]),
        .R(1'b0));
  FDRE \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[6] 
       (.C(\maint_controller.maint_wip_r_lcl_reg_1 ),
        .CE(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_1_n_0 ),
        .D(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_ns [6]),
        .Q(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r [6]),
        .R(1'b0));
  FDRE \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] 
       (.C(\maint_controller.maint_wip_r_lcl_reg_1 ),
        .CE(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[7]_i_1_n_0 ),
        .D(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_1 [1]),
        .Q(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r [7]),
        .R(1'b0));
  LUT2 #(
    .INIT(4'h2)) 
    was_priority_i_1
       (.I0(was_priority),
        .I1(was_priority_reg_0),
        .O(hi_priority));
  FDRE was_priority_reg
       (.C(\maint_controller.maint_wip_r_lcl_reg_1 ),
        .CE(1'b1),
        .D(hi_priority),
        .Q(was_priority),
        .R(1'b0));
  LUT3 #(
    .INIT(8'h8A)) 
    was_wr_i_1
       (.I0(cmd[0]),
        .I1(periodic_rd_ack_r_lcl_reg_0),
        .I2(periodic_rd_r),
        .O(was_wr0));
  FDRE was_wr_reg
       (.C(\maint_controller.maint_wip_r_lcl_reg_1 ),
        .CE(1'b1),
        .D(was_wr0),
        .Q(was_wr),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_bank_compare" *) 
module mig_mig_7series_v4_2_bank_compare
   (rb_hit_busy_r_reg_0,
    req_periodic_rd_r,
    rd_wr_r_lcl_reg_0,
    req_wr_r_lcl_reg_0,
    req_priority_r,
    \grant_r_reg[3] ,
    row_hit_r_reg_0,
    start_wtp_timer0,
    \req_row_r_lcl_reg[13]_0 ,
    \req_data_buf_addr_r_reg[3]_0 ,
    \req_bank_r_lcl_reg[2]_0 ,
    \req_col_r_reg[9]_0 ,
    p_28_out,
    row_hit_r_reg_1,
    E,
    periodic_rd_insert,
    req_wr_r_lcl0,
    hi_priority,
    row_hit_r_reg_2,
    Q,
    rd_wr_r_lcl_reg_1,
    rd_wr_r_lcl_reg_2,
    ordered_r_lcl_reg,
    ordered_r_lcl_reg_0,
    ordered_r_lcl_reg_1,
    maint_req_r,
    pass_open_bank_r_lcl_reg,
    pass_open_bank_r_lcl_reg_0,
    wait_for_maint_r_15,
    \req_row_r_lcl_reg[13]_1 ,
    \req_data_buf_addr_r_reg[3]_1 ,
    \req_data_buf_addr_r_reg[3]_2 ,
    \req_bank_r_lcl_reg[2]_1 ,
    \req_col_r_reg[9]_1 );
  output rb_hit_busy_r_reg_0;
  output [0:0]req_periodic_rd_r;
  output rd_wr_r_lcl_reg_0;
  output req_wr_r_lcl_reg_0;
  output req_priority_r;
  output \grant_r_reg[3] ;
  output row_hit_r_reg_0;
  output start_wtp_timer0;
  output [13:0]\req_row_r_lcl_reg[13]_0 ;
  output [3:0]\req_data_buf_addr_r_reg[3]_0 ;
  output [2:0]\req_bank_r_lcl_reg[2]_0 ;
  output [9:0]\req_col_r_reg[9]_0 ;
  input p_28_out;
  input row_hit_r_reg_1;
  input [0:0]E;
  input periodic_rd_insert;
  input req_wr_r_lcl0;
  input hi_priority;
  input [0:0]row_hit_r_reg_2;
  input [0:0]Q;
  input rd_wr_r_lcl_reg_1;
  input rd_wr_r_lcl_reg_2;
  input ordered_r_lcl_reg;
  input ordered_r_lcl_reg_0;
  input ordered_r_lcl_reg_1;
  input maint_req_r;
  input pass_open_bank_r_lcl_reg;
  input pass_open_bank_r_lcl_reg_0;
  input wait_for_maint_r_15;
  input [13:0]\req_row_r_lcl_reg[13]_1 ;
  input [0:0]\req_data_buf_addr_r_reg[3]_1 ;
  input [3:0]\req_data_buf_addr_r_reg[3]_2 ;
  input [2:0]\req_bank_r_lcl_reg[2]_1 ;
  input [9:0]\req_col_r_reg[9]_1 ;

  wire [0:0]E;
  wire [0:0]Q;
  wire \grant_r_reg[3] ;
  wire hi_priority;
  wire maint_req_r;
  wire ordered_r_lcl_reg;
  wire ordered_r_lcl_reg_0;
  wire ordered_r_lcl_reg_1;
  wire p_28_out;
  wire pass_open_bank_r_lcl_reg;
  wire pass_open_bank_r_lcl_reg_0;
  wire periodic_rd_insert;
  wire rb_hit_busy_r_reg_0;
  wire rd_wr_ns;
  wire rd_wr_r_lcl_reg_0;
  wire rd_wr_r_lcl_reg_1;
  wire rd_wr_r_lcl_reg_2;
  wire [2:0]\req_bank_r_lcl_reg[2]_0 ;
  wire [2:0]\req_bank_r_lcl_reg[2]_1 ;
  wire [9:0]\req_col_r_reg[9]_0 ;
  wire [9:0]\req_col_r_reg[9]_1 ;
  wire [3:0]\req_data_buf_addr_r_reg[3]_0 ;
  wire [0:0]\req_data_buf_addr_r_reg[3]_1 ;
  wire [3:0]\req_data_buf_addr_r_reg[3]_2 ;
  wire [0:0]req_periodic_rd_r;
  wire req_priority_r;
  wire [13:0]\req_row_r_lcl_reg[13]_0 ;
  wire [13:0]\req_row_r_lcl_reg[13]_1 ;
  wire req_wr_r_lcl0;
  wire req_wr_r_lcl_reg_0;
  wire row_hit_ns_carry__0_n_3;
  wire row_hit_ns_carry_i_1__2_n_0;
  wire row_hit_ns_carry_i_2__2_n_0;
  wire row_hit_ns_carry_i_3__2_n_0;
  wire row_hit_ns_carry_i_4__2_n_0;
  wire row_hit_ns_carry_n_0;
  wire row_hit_ns_carry_n_1;
  wire row_hit_ns_carry_n_2;
  wire row_hit_ns_carry_n_3;
  wire row_hit_r;
  wire row_hit_r_reg_0;
  wire row_hit_r_reg_1;
  wire [0:0]row_hit_r_reg_2;
  wire start_wtp_timer0;
  wire wait_for_maint_r_15;
  wire [3:0]NLW_row_hit_ns_carry_O_UNCONNECTED;
  wire [3:1]NLW_row_hit_ns_carry__0_CO_UNCONNECTED;
  wire [3:0]NLW_row_hit_ns_carry__0_O_UNCONNECTED;

  LUT5 #(
    .INIT(32'hAAAA00A2)) 
    i___64_i_1
       (.I0(row_hit_r),
        .I1(maint_req_r),
        .I2(pass_open_bank_r_lcl_reg),
        .I3(pass_open_bank_r_lcl_reg_0),
        .I4(wait_for_maint_r_15),
        .O(row_hit_r_reg_0));
  LUT6 #(
    .INIT(64'h00000000D5D5D500)) 
    ordered_r_lcl_i_1__0
       (.I0(Q),
        .I1(rd_wr_r_lcl_reg_0),
        .I2(req_wr_r_lcl_reg_0),
        .I3(ordered_r_lcl_reg),
        .I4(ordered_r_lcl_reg_0),
        .I5(ordered_r_lcl_reg_1),
        .O(\grant_r_reg[3] ));
  FDRE rb_hit_busy_r_reg
       (.C(row_hit_r_reg_1),
        .CE(1'b1),
        .D(p_28_out),
        .Q(rb_hit_busy_r_reg_0),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair1180" *) 
  LUT4 #(
    .INIT(16'h2F20)) 
    rd_wr_r_lcl_i_1__0
       (.I0(rd_wr_r_lcl_reg_0),
        .I1(Q),
        .I2(rd_wr_r_lcl_reg_1),
        .I3(rd_wr_r_lcl_reg_2),
        .O(rd_wr_ns));
  FDRE rd_wr_r_lcl_reg
       (.C(row_hit_r_reg_1),
        .CE(1'b1),
        .D(rd_wr_ns),
        .Q(rd_wr_r_lcl_reg_0),
        .R(1'b0));
  FDRE \req_bank_r_lcl_reg[0] 
       (.C(row_hit_r_reg_1),
        .CE(E),
        .D(\req_bank_r_lcl_reg[2]_1 [0]),
        .Q(\req_bank_r_lcl_reg[2]_0 [0]),
        .R(1'b0));
  FDRE \req_bank_r_lcl_reg[1] 
       (.C(row_hit_r_reg_1),
        .CE(E),
        .D(\req_bank_r_lcl_reg[2]_1 [1]),
        .Q(\req_bank_r_lcl_reg[2]_0 [1]),
        .R(1'b0));
  FDRE \req_bank_r_lcl_reg[2] 
       (.C(row_hit_r_reg_1),
        .CE(E),
        .D(\req_bank_r_lcl_reg[2]_1 [2]),
        .Q(\req_bank_r_lcl_reg[2]_0 [2]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[0] 
       (.C(row_hit_r_reg_1),
        .CE(E),
        .D(\req_col_r_reg[9]_1 [0]),
        .Q(\req_col_r_reg[9]_0 [0]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[1] 
       (.C(row_hit_r_reg_1),
        .CE(E),
        .D(\req_col_r_reg[9]_1 [1]),
        .Q(\req_col_r_reg[9]_0 [1]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[2] 
       (.C(row_hit_r_reg_1),
        .CE(E),
        .D(\req_col_r_reg[9]_1 [2]),
        .Q(\req_col_r_reg[9]_0 [2]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[3] 
       (.C(row_hit_r_reg_1),
        .CE(E),
        .D(\req_col_r_reg[9]_1 [3]),
        .Q(\req_col_r_reg[9]_0 [3]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[4] 
       (.C(row_hit_r_reg_1),
        .CE(E),
        .D(\req_col_r_reg[9]_1 [4]),
        .Q(\req_col_r_reg[9]_0 [4]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[5] 
       (.C(row_hit_r_reg_1),
        .CE(E),
        .D(\req_col_r_reg[9]_1 [5]),
        .Q(\req_col_r_reg[9]_0 [5]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[6] 
       (.C(row_hit_r_reg_1),
        .CE(E),
        .D(\req_col_r_reg[9]_1 [6]),
        .Q(\req_col_r_reg[9]_0 [6]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[7] 
       (.C(row_hit_r_reg_1),
        .CE(E),
        .D(\req_col_r_reg[9]_1 [7]),
        .Q(\req_col_r_reg[9]_0 [7]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[8] 
       (.C(row_hit_r_reg_1),
        .CE(E),
        .D(\req_col_r_reg[9]_1 [8]),
        .Q(\req_col_r_reg[9]_0 [8]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[9] 
       (.C(row_hit_r_reg_1),
        .CE(E),
        .D(\req_col_r_reg[9]_1 [9]),
        .Q(\req_col_r_reg[9]_0 [9]),
        .R(1'b0));
  FDRE \req_data_buf_addr_r_reg[0] 
       (.C(row_hit_r_reg_1),
        .CE(\req_data_buf_addr_r_reg[3]_1 ),
        .D(\req_data_buf_addr_r_reg[3]_2 [0]),
        .Q(\req_data_buf_addr_r_reg[3]_0 [0]),
        .R(1'b0));
  FDRE \req_data_buf_addr_r_reg[1] 
       (.C(row_hit_r_reg_1),
        .CE(\req_data_buf_addr_r_reg[3]_1 ),
        .D(\req_data_buf_addr_r_reg[3]_2 [1]),
        .Q(\req_data_buf_addr_r_reg[3]_0 [1]),
        .R(1'b0));
  FDRE \req_data_buf_addr_r_reg[2] 
       (.C(row_hit_r_reg_1),
        .CE(\req_data_buf_addr_r_reg[3]_1 ),
        .D(\req_data_buf_addr_r_reg[3]_2 [2]),
        .Q(\req_data_buf_addr_r_reg[3]_0 [2]),
        .R(1'b0));
  FDRE \req_data_buf_addr_r_reg[3] 
       (.C(row_hit_r_reg_1),
        .CE(\req_data_buf_addr_r_reg[3]_1 ),
        .D(\req_data_buf_addr_r_reg[3]_2 [3]),
        .Q(\req_data_buf_addr_r_reg[3]_0 [3]),
        .R(1'b0));
  FDRE req_periodic_rd_r_lcl_reg
       (.C(row_hit_r_reg_1),
        .CE(E),
        .D(periodic_rd_insert),
        .Q(req_periodic_rd_r),
        .R(1'b0));
  FDRE req_priority_r_reg
       (.C(row_hit_r_reg_1),
        .CE(E),
        .D(hi_priority),
        .Q(req_priority_r),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[0] 
       (.C(row_hit_r_reg_1),
        .CE(E),
        .D(\req_row_r_lcl_reg[13]_1 [0]),
        .Q(\req_row_r_lcl_reg[13]_0 [0]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[10] 
       (.C(row_hit_r_reg_1),
        .CE(E),
        .D(\req_row_r_lcl_reg[13]_1 [10]),
        .Q(\req_row_r_lcl_reg[13]_0 [10]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[11] 
       (.C(row_hit_r_reg_1),
        .CE(E),
        .D(\req_row_r_lcl_reg[13]_1 [11]),
        .Q(\req_row_r_lcl_reg[13]_0 [11]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[12] 
       (.C(row_hit_r_reg_1),
        .CE(E),
        .D(\req_row_r_lcl_reg[13]_1 [12]),
        .Q(\req_row_r_lcl_reg[13]_0 [12]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[13] 
       (.C(row_hit_r_reg_1),
        .CE(E),
        .D(\req_row_r_lcl_reg[13]_1 [13]),
        .Q(\req_row_r_lcl_reg[13]_0 [13]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[1] 
       (.C(row_hit_r_reg_1),
        .CE(E),
        .D(\req_row_r_lcl_reg[13]_1 [1]),
        .Q(\req_row_r_lcl_reg[13]_0 [1]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[2] 
       (.C(row_hit_r_reg_1),
        .CE(E),
        .D(\req_row_r_lcl_reg[13]_1 [2]),
        .Q(\req_row_r_lcl_reg[13]_0 [2]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[3] 
       (.C(row_hit_r_reg_1),
        .CE(E),
        .D(\req_row_r_lcl_reg[13]_1 [3]),
        .Q(\req_row_r_lcl_reg[13]_0 [3]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[4] 
       (.C(row_hit_r_reg_1),
        .CE(E),
        .D(\req_row_r_lcl_reg[13]_1 [4]),
        .Q(\req_row_r_lcl_reg[13]_0 [4]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[5] 
       (.C(row_hit_r_reg_1),
        .CE(E),
        .D(\req_row_r_lcl_reg[13]_1 [5]),
        .Q(\req_row_r_lcl_reg[13]_0 [5]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[6] 
       (.C(row_hit_r_reg_1),
        .CE(E),
        .D(\req_row_r_lcl_reg[13]_1 [6]),
        .Q(\req_row_r_lcl_reg[13]_0 [6]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[7] 
       (.C(row_hit_r_reg_1),
        .CE(E),
        .D(\req_row_r_lcl_reg[13]_1 [7]),
        .Q(\req_row_r_lcl_reg[13]_0 [7]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[8] 
       (.C(row_hit_r_reg_1),
        .CE(E),
        .D(\req_row_r_lcl_reg[13]_1 [8]),
        .Q(\req_row_r_lcl_reg[13]_0 [8]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[9] 
       (.C(row_hit_r_reg_1),
        .CE(E),
        .D(\req_row_r_lcl_reg[13]_1 [9]),
        .Q(\req_row_r_lcl_reg[13]_0 [9]),
        .R(1'b0));
  FDRE req_wr_r_lcl_reg
       (.C(row_hit_r_reg_1),
        .CE(E),
        .D(req_wr_r_lcl0),
        .Q(req_wr_r_lcl_reg_0),
        .R(1'b0));
  CARRY4 row_hit_ns_carry
       (.CI(1'b0),
        .CO({row_hit_ns_carry_n_0,row_hit_ns_carry_n_1,row_hit_ns_carry_n_2,row_hit_ns_carry_n_3}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_row_hit_ns_carry_O_UNCONNECTED[3:0]),
        .S({row_hit_ns_carry_i_1__2_n_0,row_hit_ns_carry_i_2__2_n_0,row_hit_ns_carry_i_3__2_n_0,row_hit_ns_carry_i_4__2_n_0}));
  CARRY4 row_hit_ns_carry__0
       (.CI(row_hit_ns_carry_n_0),
        .CO({NLW_row_hit_ns_carry__0_CO_UNCONNECTED[3:1],row_hit_ns_carry__0_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_row_hit_ns_carry__0_O_UNCONNECTED[3:0]),
        .S({1'b0,1'b0,1'b0,row_hit_r_reg_2}));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    row_hit_ns_carry_i_1__2
       (.I0(\req_row_r_lcl_reg[13]_0 [11]),
        .I1(\req_row_r_lcl_reg[13]_1 [11]),
        .I2(\req_row_r_lcl_reg[13]_0 [9]),
        .I3(\req_row_r_lcl_reg[13]_1 [9]),
        .I4(\req_row_r_lcl_reg[13]_1 [10]),
        .I5(\req_row_r_lcl_reg[13]_0 [10]),
        .O(row_hit_ns_carry_i_1__2_n_0));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    row_hit_ns_carry_i_2__2
       (.I0(\req_row_r_lcl_reg[13]_0 [8]),
        .I1(\req_row_r_lcl_reg[13]_1 [8]),
        .I2(\req_row_r_lcl_reg[13]_0 [7]),
        .I3(\req_row_r_lcl_reg[13]_1 [7]),
        .I4(\req_row_r_lcl_reg[13]_1 [6]),
        .I5(\req_row_r_lcl_reg[13]_0 [6]),
        .O(row_hit_ns_carry_i_2__2_n_0));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    row_hit_ns_carry_i_3__2
       (.I0(\req_row_r_lcl_reg[13]_0 [5]),
        .I1(\req_row_r_lcl_reg[13]_1 [5]),
        .I2(\req_row_r_lcl_reg[13]_0 [3]),
        .I3(\req_row_r_lcl_reg[13]_1 [3]),
        .I4(\req_row_r_lcl_reg[13]_1 [4]),
        .I5(\req_row_r_lcl_reg[13]_0 [4]),
        .O(row_hit_ns_carry_i_3__2_n_0));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    row_hit_ns_carry_i_4__2
       (.I0(\req_row_r_lcl_reg[13]_0 [2]),
        .I1(\req_row_r_lcl_reg[13]_1 [2]),
        .I2(\req_row_r_lcl_reg[13]_0 [1]),
        .I3(\req_row_r_lcl_reg[13]_1 [1]),
        .I4(\req_row_r_lcl_reg[13]_1 [0]),
        .I5(\req_row_r_lcl_reg[13]_0 [0]),
        .O(row_hit_ns_carry_i_4__2_n_0));
  FDRE row_hit_r_reg
       (.C(row_hit_r_reg_1),
        .CE(1'b1),
        .D(row_hit_ns_carry__0_n_3),
        .Q(row_hit_r),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair1180" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \wr_this_rank_r[0]_i_1__2 
       (.I0(rd_wr_r_lcl_reg_0),
        .O(start_wtp_timer0));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_bank_compare" *) 
module mig_mig_7series_v4_2_bank_compare_0
   (rb_hit_busy_r_reg_0,
    req_periodic_rd_r,
    rd_wr_r_lcl_reg_0,
    req_wr_r_lcl_reg_0,
    req_priority_r,
    \grant_r_reg[2] ,
    row_hit_r_reg_0,
    start_wtp_timer0,
    \req_row_r_lcl_reg[13]_0 ,
    \req_data_buf_addr_r_reg[3]_0 ,
    \req_bank_r_lcl_reg[2]_0 ,
    \req_col_r_reg[9]_0 ,
    p_67_out,
    \req_col_r_reg[9]_1 ,
    E,
    periodic_rd_insert,
    req_wr_r_lcl0,
    hi_priority,
    row_hit_r_reg_1,
    Q,
    rd_wr_r_lcl_reg_1,
    rd_wr_r_lcl_reg_2,
    ordered_r_lcl_reg,
    ordered_r_lcl_reg_0,
    ordered_r_lcl_reg_1,
    maint_req_r,
    pass_open_bank_r_lcl_reg,
    pass_open_bank_r_lcl_reg_0,
    wait_for_maint_r_14,
    \req_row_r_lcl_reg[13]_1 ,
    \req_data_buf_addr_r_reg[3]_1 ,
    \req_data_buf_addr_r_reg[3]_2 ,
    \req_bank_r_lcl_reg[2]_1 ,
    \req_col_r_reg[9]_2 );
  output rb_hit_busy_r_reg_0;
  output [0:0]req_periodic_rd_r;
  output rd_wr_r_lcl_reg_0;
  output req_wr_r_lcl_reg_0;
  output req_priority_r;
  output \grant_r_reg[2] ;
  output row_hit_r_reg_0;
  output start_wtp_timer0;
  output [13:0]\req_row_r_lcl_reg[13]_0 ;
  output [3:0]\req_data_buf_addr_r_reg[3]_0 ;
  output [2:0]\req_bank_r_lcl_reg[2]_0 ;
  output [9:0]\req_col_r_reg[9]_0 ;
  input p_67_out;
  input \req_col_r_reg[9]_1 ;
  input [0:0]E;
  input periodic_rd_insert;
  input req_wr_r_lcl0;
  input hi_priority;
  input [0:0]row_hit_r_reg_1;
  input [0:0]Q;
  input rd_wr_r_lcl_reg_1;
  input rd_wr_r_lcl_reg_2;
  input ordered_r_lcl_reg;
  input ordered_r_lcl_reg_0;
  input ordered_r_lcl_reg_1;
  input maint_req_r;
  input pass_open_bank_r_lcl_reg;
  input pass_open_bank_r_lcl_reg_0;
  input wait_for_maint_r_14;
  input [13:0]\req_row_r_lcl_reg[13]_1 ;
  input \req_data_buf_addr_r_reg[3]_1 ;
  input [3:0]\req_data_buf_addr_r_reg[3]_2 ;
  input [2:0]\req_bank_r_lcl_reg[2]_1 ;
  input [9:0]\req_col_r_reg[9]_2 ;

  wire [0:0]E;
  wire [0:0]Q;
  wire \grant_r_reg[2] ;
  wire hi_priority;
  wire maint_req_r;
  wire ordered_r_lcl_reg;
  wire ordered_r_lcl_reg_0;
  wire ordered_r_lcl_reg_1;
  wire p_67_out;
  wire pass_open_bank_r_lcl_reg;
  wire pass_open_bank_r_lcl_reg_0;
  wire periodic_rd_insert;
  wire rb_hit_busy_r_reg_0;
  wire rd_wr_ns;
  wire rd_wr_r_lcl_reg_0;
  wire rd_wr_r_lcl_reg_1;
  wire rd_wr_r_lcl_reg_2;
  wire [2:0]\req_bank_r_lcl_reg[2]_0 ;
  wire [2:0]\req_bank_r_lcl_reg[2]_1 ;
  wire [9:0]\req_col_r_reg[9]_0 ;
  wire \req_col_r_reg[9]_1 ;
  wire [9:0]\req_col_r_reg[9]_2 ;
  wire [3:0]\req_data_buf_addr_r_reg[3]_0 ;
  wire \req_data_buf_addr_r_reg[3]_1 ;
  wire [3:0]\req_data_buf_addr_r_reg[3]_2 ;
  wire [0:0]req_periodic_rd_r;
  wire req_priority_r;
  wire [13:0]\req_row_r_lcl_reg[13]_0 ;
  wire [13:0]\req_row_r_lcl_reg[13]_1 ;
  wire req_wr_r_lcl0;
  wire req_wr_r_lcl_reg_0;
  wire row_hit_ns_carry__0_n_3;
  wire row_hit_ns_carry_i_1__1_n_0;
  wire row_hit_ns_carry_i_2__1_n_0;
  wire row_hit_ns_carry_i_3__1_n_0;
  wire row_hit_ns_carry_i_4__1_n_0;
  wire row_hit_ns_carry_n_0;
  wire row_hit_ns_carry_n_1;
  wire row_hit_ns_carry_n_2;
  wire row_hit_ns_carry_n_3;
  wire row_hit_r;
  wire row_hit_r_reg_0;
  wire [0:0]row_hit_r_reg_1;
  wire start_wtp_timer0;
  wire wait_for_maint_r_14;
  wire [3:0]NLW_row_hit_ns_carry_O_UNCONNECTED;
  wire [3:1]NLW_row_hit_ns_carry__0_CO_UNCONNECTED;
  wire [3:0]NLW_row_hit_ns_carry__0_O_UNCONNECTED;

  LUT5 #(
    .INIT(32'hAAAA00A2)) 
    i___63_i_1
       (.I0(row_hit_r),
        .I1(maint_req_r),
        .I2(pass_open_bank_r_lcl_reg),
        .I3(pass_open_bank_r_lcl_reg_0),
        .I4(wait_for_maint_r_14),
        .O(row_hit_r_reg_0));
  LUT6 #(
    .INIT(64'h00000000D5D5D500)) 
    ordered_r_lcl_i_1__1
       (.I0(Q),
        .I1(rd_wr_r_lcl_reg_0),
        .I2(req_wr_r_lcl_reg_0),
        .I3(ordered_r_lcl_reg),
        .I4(ordered_r_lcl_reg_0),
        .I5(ordered_r_lcl_reg_1),
        .O(\grant_r_reg[2] ));
  FDRE rb_hit_busy_r_reg
       (.C(\req_col_r_reg[9]_1 ),
        .CE(1'b1),
        .D(p_67_out),
        .Q(rb_hit_busy_r_reg_0),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair1172" *) 
  LUT4 #(
    .INIT(16'h2F20)) 
    rd_wr_r_lcl_i_1__1
       (.I0(rd_wr_r_lcl_reg_0),
        .I1(Q),
        .I2(rd_wr_r_lcl_reg_1),
        .I3(rd_wr_r_lcl_reg_2),
        .O(rd_wr_ns));
  FDRE rd_wr_r_lcl_reg
       (.C(\req_col_r_reg[9]_1 ),
        .CE(1'b1),
        .D(rd_wr_ns),
        .Q(rd_wr_r_lcl_reg_0),
        .R(1'b0));
  FDRE \req_bank_r_lcl_reg[0] 
       (.C(\req_col_r_reg[9]_1 ),
        .CE(E),
        .D(\req_bank_r_lcl_reg[2]_1 [0]),
        .Q(\req_bank_r_lcl_reg[2]_0 [0]),
        .R(1'b0));
  FDRE \req_bank_r_lcl_reg[1] 
       (.C(\req_col_r_reg[9]_1 ),
        .CE(E),
        .D(\req_bank_r_lcl_reg[2]_1 [1]),
        .Q(\req_bank_r_lcl_reg[2]_0 [1]),
        .R(1'b0));
  FDRE \req_bank_r_lcl_reg[2] 
       (.C(\req_col_r_reg[9]_1 ),
        .CE(E),
        .D(\req_bank_r_lcl_reg[2]_1 [2]),
        .Q(\req_bank_r_lcl_reg[2]_0 [2]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[0] 
       (.C(\req_col_r_reg[9]_1 ),
        .CE(E),
        .D(\req_col_r_reg[9]_2 [0]),
        .Q(\req_col_r_reg[9]_0 [0]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[1] 
       (.C(\req_col_r_reg[9]_1 ),
        .CE(E),
        .D(\req_col_r_reg[9]_2 [1]),
        .Q(\req_col_r_reg[9]_0 [1]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[2] 
       (.C(\req_col_r_reg[9]_1 ),
        .CE(E),
        .D(\req_col_r_reg[9]_2 [2]),
        .Q(\req_col_r_reg[9]_0 [2]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[3] 
       (.C(\req_col_r_reg[9]_1 ),
        .CE(E),
        .D(\req_col_r_reg[9]_2 [3]),
        .Q(\req_col_r_reg[9]_0 [3]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[4] 
       (.C(\req_col_r_reg[9]_1 ),
        .CE(E),
        .D(\req_col_r_reg[9]_2 [4]),
        .Q(\req_col_r_reg[9]_0 [4]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[5] 
       (.C(\req_col_r_reg[9]_1 ),
        .CE(E),
        .D(\req_col_r_reg[9]_2 [5]),
        .Q(\req_col_r_reg[9]_0 [5]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[6] 
       (.C(\req_col_r_reg[9]_1 ),
        .CE(E),
        .D(\req_col_r_reg[9]_2 [6]),
        .Q(\req_col_r_reg[9]_0 [6]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[7] 
       (.C(\req_col_r_reg[9]_1 ),
        .CE(E),
        .D(\req_col_r_reg[9]_2 [7]),
        .Q(\req_col_r_reg[9]_0 [7]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[8] 
       (.C(\req_col_r_reg[9]_1 ),
        .CE(E),
        .D(\req_col_r_reg[9]_2 [8]),
        .Q(\req_col_r_reg[9]_0 [8]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[9] 
       (.C(\req_col_r_reg[9]_1 ),
        .CE(E),
        .D(\req_col_r_reg[9]_2 [9]),
        .Q(\req_col_r_reg[9]_0 [9]),
        .R(1'b0));
  FDRE \req_data_buf_addr_r_reg[0] 
       (.C(\req_col_r_reg[9]_1 ),
        .CE(\req_data_buf_addr_r_reg[3]_1 ),
        .D(\req_data_buf_addr_r_reg[3]_2 [0]),
        .Q(\req_data_buf_addr_r_reg[3]_0 [0]),
        .R(1'b0));
  FDRE \req_data_buf_addr_r_reg[1] 
       (.C(\req_col_r_reg[9]_1 ),
        .CE(\req_data_buf_addr_r_reg[3]_1 ),
        .D(\req_data_buf_addr_r_reg[3]_2 [1]),
        .Q(\req_data_buf_addr_r_reg[3]_0 [1]),
        .R(1'b0));
  FDRE \req_data_buf_addr_r_reg[2] 
       (.C(\req_col_r_reg[9]_1 ),
        .CE(\req_data_buf_addr_r_reg[3]_1 ),
        .D(\req_data_buf_addr_r_reg[3]_2 [2]),
        .Q(\req_data_buf_addr_r_reg[3]_0 [2]),
        .R(1'b0));
  FDRE \req_data_buf_addr_r_reg[3] 
       (.C(\req_col_r_reg[9]_1 ),
        .CE(\req_data_buf_addr_r_reg[3]_1 ),
        .D(\req_data_buf_addr_r_reg[3]_2 [3]),
        .Q(\req_data_buf_addr_r_reg[3]_0 [3]),
        .R(1'b0));
  FDRE req_periodic_rd_r_lcl_reg
       (.C(\req_col_r_reg[9]_1 ),
        .CE(E),
        .D(periodic_rd_insert),
        .Q(req_periodic_rd_r),
        .R(1'b0));
  FDRE req_priority_r_reg
       (.C(\req_col_r_reg[9]_1 ),
        .CE(E),
        .D(hi_priority),
        .Q(req_priority_r),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[0] 
       (.C(\req_col_r_reg[9]_1 ),
        .CE(E),
        .D(\req_row_r_lcl_reg[13]_1 [0]),
        .Q(\req_row_r_lcl_reg[13]_0 [0]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[10] 
       (.C(\req_col_r_reg[9]_1 ),
        .CE(E),
        .D(\req_row_r_lcl_reg[13]_1 [10]),
        .Q(\req_row_r_lcl_reg[13]_0 [10]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[11] 
       (.C(\req_col_r_reg[9]_1 ),
        .CE(E),
        .D(\req_row_r_lcl_reg[13]_1 [11]),
        .Q(\req_row_r_lcl_reg[13]_0 [11]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[12] 
       (.C(\req_col_r_reg[9]_1 ),
        .CE(E),
        .D(\req_row_r_lcl_reg[13]_1 [12]),
        .Q(\req_row_r_lcl_reg[13]_0 [12]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[13] 
       (.C(\req_col_r_reg[9]_1 ),
        .CE(E),
        .D(\req_row_r_lcl_reg[13]_1 [13]),
        .Q(\req_row_r_lcl_reg[13]_0 [13]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[1] 
       (.C(\req_col_r_reg[9]_1 ),
        .CE(E),
        .D(\req_row_r_lcl_reg[13]_1 [1]),
        .Q(\req_row_r_lcl_reg[13]_0 [1]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[2] 
       (.C(\req_col_r_reg[9]_1 ),
        .CE(E),
        .D(\req_row_r_lcl_reg[13]_1 [2]),
        .Q(\req_row_r_lcl_reg[13]_0 [2]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[3] 
       (.C(\req_col_r_reg[9]_1 ),
        .CE(E),
        .D(\req_row_r_lcl_reg[13]_1 [3]),
        .Q(\req_row_r_lcl_reg[13]_0 [3]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[4] 
       (.C(\req_col_r_reg[9]_1 ),
        .CE(E),
        .D(\req_row_r_lcl_reg[13]_1 [4]),
        .Q(\req_row_r_lcl_reg[13]_0 [4]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[5] 
       (.C(\req_col_r_reg[9]_1 ),
        .CE(E),
        .D(\req_row_r_lcl_reg[13]_1 [5]),
        .Q(\req_row_r_lcl_reg[13]_0 [5]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[6] 
       (.C(\req_col_r_reg[9]_1 ),
        .CE(E),
        .D(\req_row_r_lcl_reg[13]_1 [6]),
        .Q(\req_row_r_lcl_reg[13]_0 [6]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[7] 
       (.C(\req_col_r_reg[9]_1 ),
        .CE(E),
        .D(\req_row_r_lcl_reg[13]_1 [7]),
        .Q(\req_row_r_lcl_reg[13]_0 [7]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[8] 
       (.C(\req_col_r_reg[9]_1 ),
        .CE(E),
        .D(\req_row_r_lcl_reg[13]_1 [8]),
        .Q(\req_row_r_lcl_reg[13]_0 [8]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[9] 
       (.C(\req_col_r_reg[9]_1 ),
        .CE(E),
        .D(\req_row_r_lcl_reg[13]_1 [9]),
        .Q(\req_row_r_lcl_reg[13]_0 [9]),
        .R(1'b0));
  FDRE req_wr_r_lcl_reg
       (.C(\req_col_r_reg[9]_1 ),
        .CE(E),
        .D(req_wr_r_lcl0),
        .Q(req_wr_r_lcl_reg_0),
        .R(1'b0));
  CARRY4 row_hit_ns_carry
       (.CI(1'b0),
        .CO({row_hit_ns_carry_n_0,row_hit_ns_carry_n_1,row_hit_ns_carry_n_2,row_hit_ns_carry_n_3}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_row_hit_ns_carry_O_UNCONNECTED[3:0]),
        .S({row_hit_ns_carry_i_1__1_n_0,row_hit_ns_carry_i_2__1_n_0,row_hit_ns_carry_i_3__1_n_0,row_hit_ns_carry_i_4__1_n_0}));
  CARRY4 row_hit_ns_carry__0
       (.CI(row_hit_ns_carry_n_0),
        .CO({NLW_row_hit_ns_carry__0_CO_UNCONNECTED[3:1],row_hit_ns_carry__0_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_row_hit_ns_carry__0_O_UNCONNECTED[3:0]),
        .S({1'b0,1'b0,1'b0,row_hit_r_reg_1}));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    row_hit_ns_carry_i_1__1
       (.I0(\req_row_r_lcl_reg[13]_0 [11]),
        .I1(\req_row_r_lcl_reg[13]_1 [11]),
        .I2(\req_row_r_lcl_reg[13]_0 [9]),
        .I3(\req_row_r_lcl_reg[13]_1 [9]),
        .I4(\req_row_r_lcl_reg[13]_1 [10]),
        .I5(\req_row_r_lcl_reg[13]_0 [10]),
        .O(row_hit_ns_carry_i_1__1_n_0));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    row_hit_ns_carry_i_2__1
       (.I0(\req_row_r_lcl_reg[13]_0 [8]),
        .I1(\req_row_r_lcl_reg[13]_1 [8]),
        .I2(\req_row_r_lcl_reg[13]_0 [6]),
        .I3(\req_row_r_lcl_reg[13]_1 [6]),
        .I4(\req_row_r_lcl_reg[13]_1 [7]),
        .I5(\req_row_r_lcl_reg[13]_0 [7]),
        .O(row_hit_ns_carry_i_2__1_n_0));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    row_hit_ns_carry_i_3__1
       (.I0(\req_row_r_lcl_reg[13]_0 [5]),
        .I1(\req_row_r_lcl_reg[13]_1 [5]),
        .I2(\req_row_r_lcl_reg[13]_0 [4]),
        .I3(\req_row_r_lcl_reg[13]_1 [4]),
        .I4(\req_row_r_lcl_reg[13]_1 [3]),
        .I5(\req_row_r_lcl_reg[13]_0 [3]),
        .O(row_hit_ns_carry_i_3__1_n_0));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    row_hit_ns_carry_i_4__1
       (.I0(\req_row_r_lcl_reg[13]_0 [2]),
        .I1(\req_row_r_lcl_reg[13]_1 [2]),
        .I2(\req_row_r_lcl_reg[13]_0 [1]),
        .I3(\req_row_r_lcl_reg[13]_1 [1]),
        .I4(\req_row_r_lcl_reg[13]_1 [0]),
        .I5(\req_row_r_lcl_reg[13]_0 [0]),
        .O(row_hit_ns_carry_i_4__1_n_0));
  FDRE row_hit_r_reg
       (.C(\req_col_r_reg[9]_1 ),
        .CE(1'b1),
        .D(row_hit_ns_carry__0_n_3),
        .Q(row_hit_r),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair1172" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \wr_this_rank_r[0]_i_1__1 
       (.I0(rd_wr_r_lcl_reg_0),
        .O(start_wtp_timer0));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_bank_compare" *) 
module mig_mig_7series_v4_2_bank_compare_1
   (rb_hit_busy_r_reg_0,
    req_periodic_rd_r,
    rd_wr_r_lcl_reg_0,
    req_wr_r_lcl_reg_0,
    req_priority_r,
    \grant_r_reg[1] ,
    row_hit_r_reg_0,
    start_wtp_timer0,
    \req_row_r_lcl_reg[13]_0 ,
    \req_data_buf_addr_r_reg[3]_0 ,
    \req_bank_r_lcl_reg[2]_0 ,
    \req_col_r_reg[9]_0 ,
    p_106_out,
    row_hit_r_reg_1,
    E,
    periodic_rd_insert,
    req_wr_r_lcl0,
    hi_priority,
    row_hit_r_reg_2,
    row_hit_r_reg_3,
    Q,
    rd_wr_r_lcl_reg_1,
    rd_wr_r_lcl_reg_2,
    ordered_r_lcl_reg,
    ordered_r_lcl_reg_0,
    ordered_r_lcl_reg_1,
    maint_req_r,
    pass_open_bank_r_lcl_reg,
    pass_open_bank_r_lcl_reg_0,
    wait_for_maint_r_13,
    \req_row_r_lcl_reg[13]_1 ,
    \req_data_buf_addr_r_reg[3]_1 ,
    \req_data_buf_addr_r_reg[3]_2 ,
    \req_bank_r_lcl_reg[2]_1 ,
    \req_col_r_reg[9]_1 );
  output rb_hit_busy_r_reg_0;
  output [0:0]req_periodic_rd_r;
  output rd_wr_r_lcl_reg_0;
  output req_wr_r_lcl_reg_0;
  output req_priority_r;
  output \grant_r_reg[1] ;
  output row_hit_r_reg_0;
  output start_wtp_timer0;
  output [13:0]\req_row_r_lcl_reg[13]_0 ;
  output [3:0]\req_data_buf_addr_r_reg[3]_0 ;
  output [2:0]\req_bank_r_lcl_reg[2]_0 ;
  output [9:0]\req_col_r_reg[9]_0 ;
  input p_106_out;
  input row_hit_r_reg_1;
  input [0:0]E;
  input periodic_rd_insert;
  input req_wr_r_lcl0;
  input hi_priority;
  input [0:0]row_hit_r_reg_2;
  input [0:0]row_hit_r_reg_3;
  input [0:0]Q;
  input rd_wr_r_lcl_reg_1;
  input rd_wr_r_lcl_reg_2;
  input ordered_r_lcl_reg;
  input ordered_r_lcl_reg_0;
  input ordered_r_lcl_reg_1;
  input maint_req_r;
  input pass_open_bank_r_lcl_reg;
  input pass_open_bank_r_lcl_reg_0;
  input wait_for_maint_r_13;
  input [13:0]\req_row_r_lcl_reg[13]_1 ;
  input [0:0]\req_data_buf_addr_r_reg[3]_1 ;
  input [3:0]\req_data_buf_addr_r_reg[3]_2 ;
  input [2:0]\req_bank_r_lcl_reg[2]_1 ;
  input [9:0]\req_col_r_reg[9]_1 ;

  wire [0:0]E;
  wire [0:0]Q;
  wire \grant_r_reg[1] ;
  wire hi_priority;
  wire maint_req_r;
  wire ordered_r_lcl_reg;
  wire ordered_r_lcl_reg_0;
  wire ordered_r_lcl_reg_1;
  wire p_106_out;
  wire pass_open_bank_r_lcl_reg;
  wire pass_open_bank_r_lcl_reg_0;
  wire periodic_rd_insert;
  wire rb_hit_busy_r_reg_0;
  wire rd_wr_ns;
  wire rd_wr_r_lcl_reg_0;
  wire rd_wr_r_lcl_reg_1;
  wire rd_wr_r_lcl_reg_2;
  wire [2:0]\req_bank_r_lcl_reg[2]_0 ;
  wire [2:0]\req_bank_r_lcl_reg[2]_1 ;
  wire [9:0]\req_col_r_reg[9]_0 ;
  wire [9:0]\req_col_r_reg[9]_1 ;
  wire [3:0]\req_data_buf_addr_r_reg[3]_0 ;
  wire [0:0]\req_data_buf_addr_r_reg[3]_1 ;
  wire [3:0]\req_data_buf_addr_r_reg[3]_2 ;
  wire [0:0]req_periodic_rd_r;
  wire req_priority_r;
  wire [13:0]\req_row_r_lcl_reg[13]_0 ;
  wire [13:0]\req_row_r_lcl_reg[13]_1 ;
  wire req_wr_r_lcl0;
  wire req_wr_r_lcl_reg_0;
  wire row_hit_ns_carry__0_n_3;
  wire row_hit_ns_carry_i_2__0_n_0;
  wire row_hit_ns_carry_i_3__0_n_0;
  wire row_hit_ns_carry_i_4__0_n_0;
  wire row_hit_ns_carry_n_0;
  wire row_hit_ns_carry_n_1;
  wire row_hit_ns_carry_n_2;
  wire row_hit_ns_carry_n_3;
  wire row_hit_r;
  wire row_hit_r_reg_0;
  wire row_hit_r_reg_1;
  wire [0:0]row_hit_r_reg_2;
  wire [0:0]row_hit_r_reg_3;
  wire start_wtp_timer0;
  wire wait_for_maint_r_13;
  wire [3:0]NLW_row_hit_ns_carry_O_UNCONNECTED;
  wire [3:1]NLW_row_hit_ns_carry__0_CO_UNCONNECTED;
  wire [3:0]NLW_row_hit_ns_carry__0_O_UNCONNECTED;

  LUT5 #(
    .INIT(32'hAAAA00A2)) 
    i___62_i_1
       (.I0(row_hit_r),
        .I1(maint_req_r),
        .I2(pass_open_bank_r_lcl_reg),
        .I3(pass_open_bank_r_lcl_reg_0),
        .I4(wait_for_maint_r_13),
        .O(row_hit_r_reg_0));
  LUT6 #(
    .INIT(64'h00000000D5D5D500)) 
    ordered_r_lcl_i_1
       (.I0(Q),
        .I1(rd_wr_r_lcl_reg_0),
        .I2(req_wr_r_lcl_reg_0),
        .I3(ordered_r_lcl_reg),
        .I4(ordered_r_lcl_reg_0),
        .I5(ordered_r_lcl_reg_1),
        .O(\grant_r_reg[1] ));
  FDRE rb_hit_busy_r_reg
       (.C(row_hit_r_reg_1),
        .CE(1'b1),
        .D(p_106_out),
        .Q(rb_hit_busy_r_reg_0),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair1164" *) 
  LUT4 #(
    .INIT(16'h2F20)) 
    rd_wr_r_lcl_i_1
       (.I0(rd_wr_r_lcl_reg_0),
        .I1(Q),
        .I2(rd_wr_r_lcl_reg_1),
        .I3(rd_wr_r_lcl_reg_2),
        .O(rd_wr_ns));
  FDRE rd_wr_r_lcl_reg
       (.C(row_hit_r_reg_1),
        .CE(1'b1),
        .D(rd_wr_ns),
        .Q(rd_wr_r_lcl_reg_0),
        .R(1'b0));
  FDRE \req_bank_r_lcl_reg[0] 
       (.C(row_hit_r_reg_1),
        .CE(E),
        .D(\req_bank_r_lcl_reg[2]_1 [0]),
        .Q(\req_bank_r_lcl_reg[2]_0 [0]),
        .R(1'b0));
  FDRE \req_bank_r_lcl_reg[1] 
       (.C(row_hit_r_reg_1),
        .CE(E),
        .D(\req_bank_r_lcl_reg[2]_1 [1]),
        .Q(\req_bank_r_lcl_reg[2]_0 [1]),
        .R(1'b0));
  FDRE \req_bank_r_lcl_reg[2] 
       (.C(row_hit_r_reg_1),
        .CE(E),
        .D(\req_bank_r_lcl_reg[2]_1 [2]),
        .Q(\req_bank_r_lcl_reg[2]_0 [2]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[0] 
       (.C(row_hit_r_reg_1),
        .CE(E),
        .D(\req_col_r_reg[9]_1 [0]),
        .Q(\req_col_r_reg[9]_0 [0]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[1] 
       (.C(row_hit_r_reg_1),
        .CE(E),
        .D(\req_col_r_reg[9]_1 [1]),
        .Q(\req_col_r_reg[9]_0 [1]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[2] 
       (.C(row_hit_r_reg_1),
        .CE(E),
        .D(\req_col_r_reg[9]_1 [2]),
        .Q(\req_col_r_reg[9]_0 [2]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[3] 
       (.C(row_hit_r_reg_1),
        .CE(E),
        .D(\req_col_r_reg[9]_1 [3]),
        .Q(\req_col_r_reg[9]_0 [3]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[4] 
       (.C(row_hit_r_reg_1),
        .CE(E),
        .D(\req_col_r_reg[9]_1 [4]),
        .Q(\req_col_r_reg[9]_0 [4]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[5] 
       (.C(row_hit_r_reg_1),
        .CE(E),
        .D(\req_col_r_reg[9]_1 [5]),
        .Q(\req_col_r_reg[9]_0 [5]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[6] 
       (.C(row_hit_r_reg_1),
        .CE(E),
        .D(\req_col_r_reg[9]_1 [6]),
        .Q(\req_col_r_reg[9]_0 [6]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[7] 
       (.C(row_hit_r_reg_1),
        .CE(E),
        .D(\req_col_r_reg[9]_1 [7]),
        .Q(\req_col_r_reg[9]_0 [7]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[8] 
       (.C(row_hit_r_reg_1),
        .CE(E),
        .D(\req_col_r_reg[9]_1 [8]),
        .Q(\req_col_r_reg[9]_0 [8]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[9] 
       (.C(row_hit_r_reg_1),
        .CE(E),
        .D(\req_col_r_reg[9]_1 [9]),
        .Q(\req_col_r_reg[9]_0 [9]),
        .R(1'b0));
  FDRE \req_data_buf_addr_r_reg[0] 
       (.C(row_hit_r_reg_1),
        .CE(\req_data_buf_addr_r_reg[3]_1 ),
        .D(\req_data_buf_addr_r_reg[3]_2 [0]),
        .Q(\req_data_buf_addr_r_reg[3]_0 [0]),
        .R(1'b0));
  FDRE \req_data_buf_addr_r_reg[1] 
       (.C(row_hit_r_reg_1),
        .CE(\req_data_buf_addr_r_reg[3]_1 ),
        .D(\req_data_buf_addr_r_reg[3]_2 [1]),
        .Q(\req_data_buf_addr_r_reg[3]_0 [1]),
        .R(1'b0));
  FDRE \req_data_buf_addr_r_reg[2] 
       (.C(row_hit_r_reg_1),
        .CE(\req_data_buf_addr_r_reg[3]_1 ),
        .D(\req_data_buf_addr_r_reg[3]_2 [2]),
        .Q(\req_data_buf_addr_r_reg[3]_0 [2]),
        .R(1'b0));
  FDRE \req_data_buf_addr_r_reg[3] 
       (.C(row_hit_r_reg_1),
        .CE(\req_data_buf_addr_r_reg[3]_1 ),
        .D(\req_data_buf_addr_r_reg[3]_2 [3]),
        .Q(\req_data_buf_addr_r_reg[3]_0 [3]),
        .R(1'b0));
  FDRE req_periodic_rd_r_lcl_reg
       (.C(row_hit_r_reg_1),
        .CE(E),
        .D(periodic_rd_insert),
        .Q(req_periodic_rd_r),
        .R(1'b0));
  FDRE req_priority_r_reg
       (.C(row_hit_r_reg_1),
        .CE(E),
        .D(hi_priority),
        .Q(req_priority_r),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[0] 
       (.C(row_hit_r_reg_1),
        .CE(E),
        .D(\req_row_r_lcl_reg[13]_1 [0]),
        .Q(\req_row_r_lcl_reg[13]_0 [0]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[10] 
       (.C(row_hit_r_reg_1),
        .CE(E),
        .D(\req_row_r_lcl_reg[13]_1 [10]),
        .Q(\req_row_r_lcl_reg[13]_0 [10]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[11] 
       (.C(row_hit_r_reg_1),
        .CE(E),
        .D(\req_row_r_lcl_reg[13]_1 [11]),
        .Q(\req_row_r_lcl_reg[13]_0 [11]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[12] 
       (.C(row_hit_r_reg_1),
        .CE(E),
        .D(\req_row_r_lcl_reg[13]_1 [12]),
        .Q(\req_row_r_lcl_reg[13]_0 [12]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[13] 
       (.C(row_hit_r_reg_1),
        .CE(E),
        .D(\req_row_r_lcl_reg[13]_1 [13]),
        .Q(\req_row_r_lcl_reg[13]_0 [13]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[1] 
       (.C(row_hit_r_reg_1),
        .CE(E),
        .D(\req_row_r_lcl_reg[13]_1 [1]),
        .Q(\req_row_r_lcl_reg[13]_0 [1]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[2] 
       (.C(row_hit_r_reg_1),
        .CE(E),
        .D(\req_row_r_lcl_reg[13]_1 [2]),
        .Q(\req_row_r_lcl_reg[13]_0 [2]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[3] 
       (.C(row_hit_r_reg_1),
        .CE(E),
        .D(\req_row_r_lcl_reg[13]_1 [3]),
        .Q(\req_row_r_lcl_reg[13]_0 [3]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[4] 
       (.C(row_hit_r_reg_1),
        .CE(E),
        .D(\req_row_r_lcl_reg[13]_1 [4]),
        .Q(\req_row_r_lcl_reg[13]_0 [4]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[5] 
       (.C(row_hit_r_reg_1),
        .CE(E),
        .D(\req_row_r_lcl_reg[13]_1 [5]),
        .Q(\req_row_r_lcl_reg[13]_0 [5]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[6] 
       (.C(row_hit_r_reg_1),
        .CE(E),
        .D(\req_row_r_lcl_reg[13]_1 [6]),
        .Q(\req_row_r_lcl_reg[13]_0 [6]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[7] 
       (.C(row_hit_r_reg_1),
        .CE(E),
        .D(\req_row_r_lcl_reg[13]_1 [7]),
        .Q(\req_row_r_lcl_reg[13]_0 [7]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[8] 
       (.C(row_hit_r_reg_1),
        .CE(E),
        .D(\req_row_r_lcl_reg[13]_1 [8]),
        .Q(\req_row_r_lcl_reg[13]_0 [8]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[9] 
       (.C(row_hit_r_reg_1),
        .CE(E),
        .D(\req_row_r_lcl_reg[13]_1 [9]),
        .Q(\req_row_r_lcl_reg[13]_0 [9]),
        .R(1'b0));
  FDRE req_wr_r_lcl_reg
       (.C(row_hit_r_reg_1),
        .CE(E),
        .D(req_wr_r_lcl0),
        .Q(req_wr_r_lcl_reg_0),
        .R(1'b0));
  CARRY4 row_hit_ns_carry
       (.CI(1'b0),
        .CO({row_hit_ns_carry_n_0,row_hit_ns_carry_n_1,row_hit_ns_carry_n_2,row_hit_ns_carry_n_3}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_row_hit_ns_carry_O_UNCONNECTED[3:0]),
        .S({row_hit_r_reg_2,row_hit_ns_carry_i_2__0_n_0,row_hit_ns_carry_i_3__0_n_0,row_hit_ns_carry_i_4__0_n_0}));
  CARRY4 row_hit_ns_carry__0
       (.CI(row_hit_ns_carry_n_0),
        .CO({NLW_row_hit_ns_carry__0_CO_UNCONNECTED[3:1],row_hit_ns_carry__0_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_row_hit_ns_carry__0_O_UNCONNECTED[3:0]),
        .S({1'b0,1'b0,1'b0,row_hit_r_reg_3}));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    row_hit_ns_carry_i_2__0
       (.I0(\req_row_r_lcl_reg[13]_0 [8]),
        .I1(\req_row_r_lcl_reg[13]_1 [8]),
        .I2(\req_row_r_lcl_reg[13]_0 [7]),
        .I3(\req_row_r_lcl_reg[13]_1 [7]),
        .I4(\req_row_r_lcl_reg[13]_1 [6]),
        .I5(\req_row_r_lcl_reg[13]_0 [6]),
        .O(row_hit_ns_carry_i_2__0_n_0));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    row_hit_ns_carry_i_3__0
       (.I0(\req_row_r_lcl_reg[13]_0 [5]),
        .I1(\req_row_r_lcl_reg[13]_1 [5]),
        .I2(\req_row_r_lcl_reg[13]_0 [4]),
        .I3(\req_row_r_lcl_reg[13]_1 [4]),
        .I4(\req_row_r_lcl_reg[13]_1 [3]),
        .I5(\req_row_r_lcl_reg[13]_0 [3]),
        .O(row_hit_ns_carry_i_3__0_n_0));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    row_hit_ns_carry_i_4__0
       (.I0(\req_row_r_lcl_reg[13]_0 [2]),
        .I1(\req_row_r_lcl_reg[13]_1 [2]),
        .I2(\req_row_r_lcl_reg[13]_0 [1]),
        .I3(\req_row_r_lcl_reg[13]_1 [1]),
        .I4(\req_row_r_lcl_reg[13]_1 [0]),
        .I5(\req_row_r_lcl_reg[13]_0 [0]),
        .O(row_hit_ns_carry_i_4__0_n_0));
  FDRE row_hit_r_reg
       (.C(row_hit_r_reg_1),
        .CE(1'b1),
        .D(row_hit_ns_carry__0_n_3),
        .Q(row_hit_r),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair1164" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \wr_this_rank_r[0]_i_1__0 
       (.I0(rd_wr_r_lcl_reg_0),
        .O(start_wtp_timer0));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_bank_compare" *) 
module mig_mig_7series_v4_2_bank_compare_2
   (rb_hit_busy_r_reg_0,
    req_periodic_rd_r,
    rd_wr_r_lcl_reg_0,
    req_wr_r,
    req_priority_r,
    ordered_r_lcl_reg,
    rd_wr_r_lcl_reg_1,
    \grant_r_reg[0] ,
    rd_wr_r_lcl_reg_2,
    rd_wr_r_lcl_reg_3,
    row_hit_r_reg_0,
    start_wtp_timer0,
    \req_row_r_lcl_reg[13]_0 ,
    rb_hit_busy_r_reg_1,
    rb_hit_busy_r_reg_2,
    \req_data_buf_addr_r_reg[3]_0 ,
    \req_bank_r_lcl_reg[2]_0 ,
    \req_col_r_reg[9]_0 ,
    p_145_out,
    \req_col_r_reg[9]_1 ,
    E,
    periodic_rd_insert,
    req_wr_r_lcl0,
    hi_priority,
    S,
    row_hit_r_reg_1,
    ordered_r_lcl,
    \order_q_r_reg[1] ,
    \order_q_r_reg[1]_0 ,
    \order_q_r_reg[1]_1 ,
    req_bank_rdy_r_reg,
    Q,
    req_bank_rdy_r_reg_0,
    req_bank_rdy_r_reg_1,
    rd_wr_r_lcl_reg_4,
    rd_wr_r_lcl_reg_5,
    ordered_r_lcl_reg_0,
    ordered_r_lcl_reg_1,
    maint_req_r,
    pass_open_bank_r_lcl_reg,
    pass_open_bank_r_lcl_reg_0,
    wait_for_maint_r,
    \req_row_r_lcl_reg[13]_1 ,
    \q_entry_r[0]_i_2__1 ,
    \q_entry_r[0]_i_2__1_0 ,
    \q_entry_r[0]_i_2__1_1 ,
    \req_data_buf_addr_r_reg[3]_1 ,
    \req_data_buf_addr_r_reg[3]_2 ,
    \req_bank_r_lcl_reg[2]_1 ,
    \req_col_r_reg[9]_2 );
  output rb_hit_busy_r_reg_0;
  output [0:0]req_periodic_rd_r;
  output rd_wr_r_lcl_reg_0;
  output [0:0]req_wr_r;
  output req_priority_r;
  output ordered_r_lcl_reg;
  output rd_wr_r_lcl_reg_1;
  output \grant_r_reg[0] ;
  output rd_wr_r_lcl_reg_2;
  output rd_wr_r_lcl_reg_3;
  output row_hit_r_reg_0;
  output start_wtp_timer0;
  output [13:0]\req_row_r_lcl_reg[13]_0 ;
  output rb_hit_busy_r_reg_1;
  output rb_hit_busy_r_reg_2;
  output [3:0]\req_data_buf_addr_r_reg[3]_0 ;
  output [2:0]\req_bank_r_lcl_reg[2]_0 ;
  output [9:0]\req_col_r_reg[9]_0 ;
  input p_145_out;
  input \req_col_r_reg[9]_1 ;
  input [0:0]E;
  input periodic_rd_insert;
  input req_wr_r_lcl0;
  input hi_priority;
  input [2:0]S;
  input [0:0]row_hit_r_reg_1;
  input ordered_r_lcl;
  input \order_q_r_reg[1] ;
  input \order_q_r_reg[1]_0 ;
  input \order_q_r_reg[1]_1 ;
  input req_bank_rdy_r_reg;
  input [0:0]Q;
  input req_bank_rdy_r_reg_0;
  input req_bank_rdy_r_reg_1;
  input rd_wr_r_lcl_reg_4;
  input rd_wr_r_lcl_reg_5;
  input ordered_r_lcl_reg_0;
  input ordered_r_lcl_reg_1;
  input maint_req_r;
  input pass_open_bank_r_lcl_reg;
  input pass_open_bank_r_lcl_reg_0;
  input wait_for_maint_r;
  input [13:0]\req_row_r_lcl_reg[13]_1 ;
  input \q_entry_r[0]_i_2__1 ;
  input \q_entry_r[0]_i_2__1_0 ;
  input \q_entry_r[0]_i_2__1_1 ;
  input \req_data_buf_addr_r_reg[3]_1 ;
  input [3:0]\req_data_buf_addr_r_reg[3]_2 ;
  input [2:0]\req_bank_r_lcl_reg[2]_1 ;
  input [9:0]\req_col_r_reg[9]_2 ;

  wire [0:0]E;
  wire [0:0]Q;
  wire [2:0]S;
  wire \grant_r_reg[0] ;
  wire hi_priority;
  wire maint_req_r;
  wire \order_q_r_reg[1] ;
  wire \order_q_r_reg[1]_0 ;
  wire \order_q_r_reg[1]_1 ;
  wire ordered_r_lcl;
  wire ordered_r_lcl_reg;
  wire ordered_r_lcl_reg_0;
  wire ordered_r_lcl_reg_1;
  wire p_145_out;
  wire pass_open_bank_r_lcl_reg;
  wire pass_open_bank_r_lcl_reg_0;
  wire periodic_rd_insert;
  wire \q_entry_r[0]_i_2__1 ;
  wire \q_entry_r[0]_i_2__1_0 ;
  wire \q_entry_r[0]_i_2__1_1 ;
  wire rb_hit_busy_r_reg_0;
  wire rb_hit_busy_r_reg_1;
  wire rb_hit_busy_r_reg_2;
  wire rd_wr_ns;
  wire rd_wr_r_lcl_reg_0;
  wire rd_wr_r_lcl_reg_1;
  wire rd_wr_r_lcl_reg_2;
  wire rd_wr_r_lcl_reg_3;
  wire rd_wr_r_lcl_reg_4;
  wire rd_wr_r_lcl_reg_5;
  wire [2:0]\req_bank_r_lcl_reg[2]_0 ;
  wire [2:0]\req_bank_r_lcl_reg[2]_1 ;
  wire req_bank_rdy_r_reg;
  wire req_bank_rdy_r_reg_0;
  wire req_bank_rdy_r_reg_1;
  wire [9:0]\req_col_r_reg[9]_0 ;
  wire \req_col_r_reg[9]_1 ;
  wire [9:0]\req_col_r_reg[9]_2 ;
  wire [3:0]\req_data_buf_addr_r_reg[3]_0 ;
  wire \req_data_buf_addr_r_reg[3]_1 ;
  wire [3:0]\req_data_buf_addr_r_reg[3]_2 ;
  wire [0:0]req_periodic_rd_r;
  wire req_priority_r;
  wire [13:0]\req_row_r_lcl_reg[13]_0 ;
  wire [13:0]\req_row_r_lcl_reg[13]_1 ;
  wire [0:0]req_wr_r;
  wire req_wr_r_lcl0;
  wire row_hit_ns;
  wire row_hit_ns_carry_i_1_n_0;
  wire row_hit_ns_carry_n_0;
  wire row_hit_ns_carry_n_1;
  wire row_hit_ns_carry_n_2;
  wire row_hit_ns_carry_n_3;
  wire row_hit_r;
  wire row_hit_r_reg_0;
  wire [0:0]row_hit_r_reg_1;
  wire start_wtp_timer0;
  wire wait_for_maint_r;
  wire [3:0]NLW_row_hit_ns_carry_O_UNCONNECTED;
  wire [3:1]NLW_row_hit_ns_carry__0_CO_UNCONNECTED;
  wire [3:0]NLW_row_hit_ns_carry__0_O_UNCONNECTED;

  (* SOFT_HLUTNM = "soft_lutpair1150" *) 
  LUT3 #(
    .INIT(8'h8F)) 
    \grant_r[3]_i_15 
       (.I0(rd_wr_r_lcl_reg_0),
        .I1(req_wr_r),
        .I2(Q),
        .O(rd_wr_r_lcl_reg_2));
  (* SOFT_HLUTNM = "soft_lutpair1151" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    i___3_i_5
       (.I0(rb_hit_busy_r_reg_0),
        .I1(\q_entry_r[0]_i_2__1_1 ),
        .I2(\q_entry_r[0]_i_2__1_0 ),
        .I3(\q_entry_r[0]_i_2__1 ),
        .O(rb_hit_busy_r_reg_2));
  (* SOFT_HLUTNM = "soft_lutpair1151" *) 
  LUT4 #(
    .INIT(16'h7EE8)) 
    i___3_i_7
       (.I0(rb_hit_busy_r_reg_0),
        .I1(\q_entry_r[0]_i_2__1 ),
        .I2(\q_entry_r[0]_i_2__1_0 ),
        .I3(\q_entry_r[0]_i_2__1_1 ),
        .O(rb_hit_busy_r_reg_1));
  LUT5 #(
    .INIT(32'hAAAA00A2)) 
    i___61_i_1
       (.I0(row_hit_r),
        .I1(maint_req_r),
        .I2(pass_open_bank_r_lcl_reg),
        .I3(pass_open_bank_r_lcl_reg_0),
        .I4(wait_for_maint_r),
        .O(row_hit_r_reg_0));
  LUT5 #(
    .INIT(32'hBDD4D442)) 
    \order_q_r[1]_i_2 
       (.I0(rd_wr_r_lcl_reg_1),
        .I1(ordered_r_lcl),
        .I2(\order_q_r_reg[1] ),
        .I3(\order_q_r_reg[1]_0 ),
        .I4(\order_q_r_reg[1]_1 ),
        .O(ordered_r_lcl_reg));
  LUT6 #(
    .INIT(64'h00000000D5D5D500)) 
    ordered_r_lcl_i_1__2
       (.I0(Q),
        .I1(req_wr_r),
        .I2(rd_wr_r_lcl_reg_0),
        .I3(ordered_r_lcl_reg_0),
        .I4(ordered_r_lcl),
        .I5(ordered_r_lcl_reg_1),
        .O(\grant_r_reg[0] ));
  (* SOFT_HLUTNM = "soft_lutpair1152" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \ras_timer_r[1]_i_5 
       (.I0(rd_wr_r_lcl_reg_0),
        .I1(Q),
        .O(rd_wr_r_lcl_reg_3));
  FDRE rb_hit_busy_r_reg
       (.C(\req_col_r_reg[9]_1 ),
        .CE(1'b1),
        .D(p_145_out),
        .Q(rb_hit_busy_r_reg_0),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair1150" *) 
  LUT4 #(
    .INIT(16'h2F20)) 
    rd_wr_r_lcl_i_1__2
       (.I0(rd_wr_r_lcl_reg_0),
        .I1(Q),
        .I2(rd_wr_r_lcl_reg_4),
        .I3(rd_wr_r_lcl_reg_5),
        .O(rd_wr_ns));
  FDRE rd_wr_r_lcl_reg
       (.C(\req_col_r_reg[9]_1 ),
        .CE(1'b1),
        .D(rd_wr_ns),
        .Q(rd_wr_r_lcl_reg_0),
        .R(1'b0));
  FDRE \req_bank_r_lcl_reg[0] 
       (.C(\req_col_r_reg[9]_1 ),
        .CE(E),
        .D(\req_bank_r_lcl_reg[2]_1 [0]),
        .Q(\req_bank_r_lcl_reg[2]_0 [0]),
        .R(1'b0));
  FDRE \req_bank_r_lcl_reg[1] 
       (.C(\req_col_r_reg[9]_1 ),
        .CE(E),
        .D(\req_bank_r_lcl_reg[2]_1 [1]),
        .Q(\req_bank_r_lcl_reg[2]_0 [1]),
        .R(1'b0));
  FDRE \req_bank_r_lcl_reg[2] 
       (.C(\req_col_r_reg[9]_1 ),
        .CE(E),
        .D(\req_bank_r_lcl_reg[2]_1 [2]),
        .Q(\req_bank_r_lcl_reg[2]_0 [2]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h7F55FFFFFFFFFFFF)) 
    req_bank_rdy_r_i_2
       (.I0(req_bank_rdy_r_reg),
        .I1(rd_wr_r_lcl_reg_0),
        .I2(req_wr_r),
        .I3(Q),
        .I4(req_bank_rdy_r_reg_0),
        .I5(req_bank_rdy_r_reg_1),
        .O(rd_wr_r_lcl_reg_1));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[0] 
       (.C(\req_col_r_reg[9]_1 ),
        .CE(E),
        .D(\req_col_r_reg[9]_2 [0]),
        .Q(\req_col_r_reg[9]_0 [0]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[1] 
       (.C(\req_col_r_reg[9]_1 ),
        .CE(E),
        .D(\req_col_r_reg[9]_2 [1]),
        .Q(\req_col_r_reg[9]_0 [1]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[2] 
       (.C(\req_col_r_reg[9]_1 ),
        .CE(E),
        .D(\req_col_r_reg[9]_2 [2]),
        .Q(\req_col_r_reg[9]_0 [2]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[3] 
       (.C(\req_col_r_reg[9]_1 ),
        .CE(E),
        .D(\req_col_r_reg[9]_2 [3]),
        .Q(\req_col_r_reg[9]_0 [3]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[4] 
       (.C(\req_col_r_reg[9]_1 ),
        .CE(E),
        .D(\req_col_r_reg[9]_2 [4]),
        .Q(\req_col_r_reg[9]_0 [4]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[5] 
       (.C(\req_col_r_reg[9]_1 ),
        .CE(E),
        .D(\req_col_r_reg[9]_2 [5]),
        .Q(\req_col_r_reg[9]_0 [5]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[6] 
       (.C(\req_col_r_reg[9]_1 ),
        .CE(E),
        .D(\req_col_r_reg[9]_2 [6]),
        .Q(\req_col_r_reg[9]_0 [6]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[7] 
       (.C(\req_col_r_reg[9]_1 ),
        .CE(E),
        .D(\req_col_r_reg[9]_2 [7]),
        .Q(\req_col_r_reg[9]_0 [7]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[8] 
       (.C(\req_col_r_reg[9]_1 ),
        .CE(E),
        .D(\req_col_r_reg[9]_2 [8]),
        .Q(\req_col_r_reg[9]_0 [8]),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \req_col_r_reg[9] 
       (.C(\req_col_r_reg[9]_1 ),
        .CE(E),
        .D(\req_col_r_reg[9]_2 [9]),
        .Q(\req_col_r_reg[9]_0 [9]),
        .R(1'b0));
  FDRE \req_data_buf_addr_r_reg[0] 
       (.C(\req_col_r_reg[9]_1 ),
        .CE(\req_data_buf_addr_r_reg[3]_1 ),
        .D(\req_data_buf_addr_r_reg[3]_2 [0]),
        .Q(\req_data_buf_addr_r_reg[3]_0 [0]),
        .R(1'b0));
  FDRE \req_data_buf_addr_r_reg[1] 
       (.C(\req_col_r_reg[9]_1 ),
        .CE(\req_data_buf_addr_r_reg[3]_1 ),
        .D(\req_data_buf_addr_r_reg[3]_2 [1]),
        .Q(\req_data_buf_addr_r_reg[3]_0 [1]),
        .R(1'b0));
  FDRE \req_data_buf_addr_r_reg[2] 
       (.C(\req_col_r_reg[9]_1 ),
        .CE(\req_data_buf_addr_r_reg[3]_1 ),
        .D(\req_data_buf_addr_r_reg[3]_2 [2]),
        .Q(\req_data_buf_addr_r_reg[3]_0 [2]),
        .R(1'b0));
  FDRE \req_data_buf_addr_r_reg[3] 
       (.C(\req_col_r_reg[9]_1 ),
        .CE(\req_data_buf_addr_r_reg[3]_1 ),
        .D(\req_data_buf_addr_r_reg[3]_2 [3]),
        .Q(\req_data_buf_addr_r_reg[3]_0 [3]),
        .R(1'b0));
  FDRE req_periodic_rd_r_lcl_reg
       (.C(\req_col_r_reg[9]_1 ),
        .CE(E),
        .D(periodic_rd_insert),
        .Q(req_periodic_rd_r),
        .R(1'b0));
  FDRE req_priority_r_reg
       (.C(\req_col_r_reg[9]_1 ),
        .CE(E),
        .D(hi_priority),
        .Q(req_priority_r),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[0] 
       (.C(\req_col_r_reg[9]_1 ),
        .CE(E),
        .D(\req_row_r_lcl_reg[13]_1 [0]),
        .Q(\req_row_r_lcl_reg[13]_0 [0]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[10] 
       (.C(\req_col_r_reg[9]_1 ),
        .CE(E),
        .D(\req_row_r_lcl_reg[13]_1 [10]),
        .Q(\req_row_r_lcl_reg[13]_0 [10]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[11] 
       (.C(\req_col_r_reg[9]_1 ),
        .CE(E),
        .D(\req_row_r_lcl_reg[13]_1 [11]),
        .Q(\req_row_r_lcl_reg[13]_0 [11]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[12] 
       (.C(\req_col_r_reg[9]_1 ),
        .CE(E),
        .D(\req_row_r_lcl_reg[13]_1 [12]),
        .Q(\req_row_r_lcl_reg[13]_0 [12]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[13] 
       (.C(\req_col_r_reg[9]_1 ),
        .CE(E),
        .D(\req_row_r_lcl_reg[13]_1 [13]),
        .Q(\req_row_r_lcl_reg[13]_0 [13]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[1] 
       (.C(\req_col_r_reg[9]_1 ),
        .CE(E),
        .D(\req_row_r_lcl_reg[13]_1 [1]),
        .Q(\req_row_r_lcl_reg[13]_0 [1]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[2] 
       (.C(\req_col_r_reg[9]_1 ),
        .CE(E),
        .D(\req_row_r_lcl_reg[13]_1 [2]),
        .Q(\req_row_r_lcl_reg[13]_0 [2]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[3] 
       (.C(\req_col_r_reg[9]_1 ),
        .CE(E),
        .D(\req_row_r_lcl_reg[13]_1 [3]),
        .Q(\req_row_r_lcl_reg[13]_0 [3]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[4] 
       (.C(\req_col_r_reg[9]_1 ),
        .CE(E),
        .D(\req_row_r_lcl_reg[13]_1 [4]),
        .Q(\req_row_r_lcl_reg[13]_0 [4]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[5] 
       (.C(\req_col_r_reg[9]_1 ),
        .CE(E),
        .D(\req_row_r_lcl_reg[13]_1 [5]),
        .Q(\req_row_r_lcl_reg[13]_0 [5]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[6] 
       (.C(\req_col_r_reg[9]_1 ),
        .CE(E),
        .D(\req_row_r_lcl_reg[13]_1 [6]),
        .Q(\req_row_r_lcl_reg[13]_0 [6]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[7] 
       (.C(\req_col_r_reg[9]_1 ),
        .CE(E),
        .D(\req_row_r_lcl_reg[13]_1 [7]),
        .Q(\req_row_r_lcl_reg[13]_0 [7]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[8] 
       (.C(\req_col_r_reg[9]_1 ),
        .CE(E),
        .D(\req_row_r_lcl_reg[13]_1 [8]),
        .Q(\req_row_r_lcl_reg[13]_0 [8]),
        .R(1'b0));
  FDRE \req_row_r_lcl_reg[9] 
       (.C(\req_col_r_reg[9]_1 ),
        .CE(E),
        .D(\req_row_r_lcl_reg[13]_1 [9]),
        .Q(\req_row_r_lcl_reg[13]_0 [9]),
        .R(1'b0));
  FDRE req_wr_r_lcl_reg
       (.C(\req_col_r_reg[9]_1 ),
        .CE(E),
        .D(req_wr_r_lcl0),
        .Q(req_wr_r),
        .R(1'b0));
  CARRY4 row_hit_ns_carry
       (.CI(1'b0),
        .CO({row_hit_ns_carry_n_0,row_hit_ns_carry_n_1,row_hit_ns_carry_n_2,row_hit_ns_carry_n_3}),
        .CYINIT(1'b1),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_row_hit_ns_carry_O_UNCONNECTED[3:0]),
        .S({row_hit_ns_carry_i_1_n_0,S}));
  CARRY4 row_hit_ns_carry__0
       (.CI(row_hit_ns_carry_n_0),
        .CO({NLW_row_hit_ns_carry__0_CO_UNCONNECTED[3:1],row_hit_ns}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(NLW_row_hit_ns_carry__0_O_UNCONNECTED[3:0]),
        .S({1'b0,1'b0,1'b0,row_hit_r_reg_1}));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    row_hit_ns_carry_i_1
       (.I0(\req_row_r_lcl_reg[13]_0 [11]),
        .I1(\req_row_r_lcl_reg[13]_1 [11]),
        .I2(\req_row_r_lcl_reg[13]_0 [9]),
        .I3(\req_row_r_lcl_reg[13]_1 [9]),
        .I4(\req_row_r_lcl_reg[13]_1 [10]),
        .I5(\req_row_r_lcl_reg[13]_0 [10]),
        .O(row_hit_ns_carry_i_1_n_0));
  FDRE row_hit_r_reg
       (.C(\req_col_r_reg[9]_1 ),
        .CE(1'b1),
        .D(row_hit_ns),
        .Q(row_hit_r),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair1152" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \wr_this_rank_r[0]_i_1 
       (.I0(rd_wr_r_lcl_reg_0),
        .O(start_wtp_timer0));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_bank_mach" *) 
module mig_mig_7series_v4_2_bank_mach
   (sent_row,
    sent_col,
    insert_maint_r1,
    \generate_maint_cmds.insert_maint_r_lcl_reg ,
    cs_en2,
    DIC,
    col_rd_wr,
    cke_r,
    accept_internal_r,
    periodic_rd_ack_r,
    accept_r_reg,
    accept_ns,
    rb_hit_busy_r,
    idle_r,
    was_wr,
    rd_wr_r_lcl_reg,
    req_wr_r_lcl_reg,
    p_130_out,
    row_cmd_wr,
    col_wait_r,
    demand_priority_r,
    demanded_prior_r,
    q_has_rd,
    bm_end_r1,
    col_wait_r_0,
    req_bank_rdy_ns,
    demand_priority_r_1,
    demanded_prior_r_2,
    pass_open_bank_r,
    pre_bm_end_r,
    q_has_rd_3,
    bm_end_r1_0,
    p_52_out,
    col_wait_r_4,
    demand_priority_r_5,
    demanded_prior_r_6,
    override_demand_r,
    override_demand_ns,
    q_has_rd_7,
    bm_end_r1_1,
    col_wait_r_8,
    demand_priority_r_9,
    pass_open_bank_r_10,
    pre_bm_end_r_11,
    q_has_rd_12,
    pass_open_bank_r_lcl_reg,
    pass_open_bank_r_lcl_reg_0,
    rnk_config_valid_r,
    maint_wip_r,
    wait_for_maint_r,
    wait_for_maint_r_13,
    wait_for_maint_r_14,
    wait_for_maint_r_15,
    periodic_rd_cntr_r,
    tail_r,
    head_r,
    tail_r_16,
    tail_r_17,
    tail_r_18,
    auto_pre_r,
    auto_pre_r_19,
    auto_pre_r_20,
    auto_pre_r_21,
    \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] ,
    \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] ,
    \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17] ,
    granted_col_r_reg,
    \grant_r_reg[2] ,
    idle_r_lcl_reg,
    idle_r_lcl_reg_0,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ,
    idle_r_lcl_reg_1,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[1] ,
    idle_r_lcl_reg_2,
    Q,
    clear_periodic_rd_request,
    \periodic_rd_generation.read_this_rank_r_reg ,
    \periodic_rd_generation.read_this_rank ,
    mc_odt_ns,
    D,
    granted_col_r_reg_0,
    granted_col_r_reg_1,
    E,
    \rtw_timer.rtw_cnt_r_reg[1] ,
    \grant_r_reg[0] ,
    \wr_this_rank_r_reg[0] ,
    \wr_this_rank_r_reg[0]_0 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[6] ,
    pre_bm_end_r_reg,
    \grant_r_reg[3] ,
    pre_passing_open_bank_r_reg,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ,
    pre_passing_open_bank_r_reg_0,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ,
    pre_bm_end_r_reg_0,
    pre_bm_end_r_reg_1,
    set_order_q,
    \q_entry_r_reg[1] ,
    \q_entry_r_reg[0] ,
    periodic_rd_ack_r_lcl_reg,
    \grant_r_reg[3]_0 ,
    rb_hit_busy_r_reg,
    row_hit_r_reg,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ,
    \q_entry_r_reg[0]_0 ,
    set_order_q_22,
    \q_entry_r_reg[1]_0 ,
    \q_entry_r_reg[0]_1 ,
    \q_entry_r_reg[0]_2 ,
    idle_r_lcl_reg_3,
    \q_entry_r_reg[0]_3 ,
    q_entry_r,
    idle_r_lcl_reg_4,
    set_order_q_23,
    pre_bm_end_r_reg_2,
    demand_priority_r_reg,
    rnk_config_valid_r_lcl_reg,
    \order_q_r_reg[1] ,
    set_order_q_24,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ,
    \q_entry_r_reg[0]_4 ,
    \q_entry_r_reg[0]_5 ,
    \q_entry_r_reg[1]_1 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1 ,
    row_hit_r_reg_0,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_2 ,
    rb_hit_busy_r_reg_0,
    row_hit_r_reg_1,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 ,
    row_hit_r_reg_2,
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] ,
    mc_we_n_ns,
    mc_cas_n_ns,
    mc_ras_n_ns,
    \pre_4_1_1T_arb.granted_pre_r_reg ,
    \req_bank_r_lcl_reg[2] ,
    \req_bank_r_lcl_reg[2]_0 ,
    \req_bank_r_lcl_reg[2]_1 ,
    \req_bank_r_lcl_reg[2]_2 ,
    \pre_4_1_1T_arb.granted_pre_r_reg_0 ,
    \req_row_r_lcl_reg[13] ,
    mc_cs_n_ns,
    act_wait_r_lcl_reg,
    \compute_tail.tail_r_lcl_reg ,
    \compute_tail.tail_r_lcl_reg_0 ,
    idle_r_lcl_reg_5,
    \compute_tail.tail_r_lcl_reg_1 ,
    \compute_tail.tail_r_lcl_reg_2 ,
    act_wait_r_lcl_reg_0,
    \grant_r_reg[1] ,
    demanded_prior_r_reg,
    act_wait_r_lcl_reg_1,
    \grant_r_reg[0]_0 ,
    \last_master_r_reg[3] ,
    col_wr_data_buf_addr,
    act_this_rank,
    \grant_r_reg[0]_1 ,
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4] ,
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] ,
    demanded_prior_r_reg_0,
    \grant_r_reg[0]_2 ,
    \maint_controller.maint_hit_busies_r_reg[3] ,
    \maint_controller.maint_wip_r_lcl_reg ,
    cke_r_reg,
    mc_cke_ns,
    maint_srx_r,
    col_wait_r_reg,
    periodic_rd_cntr_r_reg,
    phy_mc_ctl_full,
    ofs_rdy_r_reg,
    of_ctl_full_v,
    q_has_rd_r_reg,
    col_wait_r_reg_0,
    q_has_rd_r_reg_0,
    col_wait_r_reg_1,
    q_has_rd_r_reg_1,
    col_wait_r_reg_2,
    q_has_rd_r_reg_2,
    auto_pre_r_lcl_reg,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ,
    SR,
    rnk_config_valid_r_lcl_reg_0,
    \maint_controller.maint_wip_r_lcl_reg_0 ,
    \maint_controller.maint_wip_r_lcl_reg_1 ,
    wait_for_maint_r_lcl_reg,
    wait_for_maint_r_lcl_reg_0,
    wait_for_maint_r_lcl_reg_1,
    wait_for_maint_r_lcl_reg_2,
    periodic_rd_cntr_r_reg_0,
    \compute_tail.tail_r_lcl_reg_3 ,
    head_r_lcl_reg,
    head_r_lcl_reg_0,
    head_r_lcl_reg_1,
    head_r_lcl_reg_2,
    \compute_tail.tail_r_lcl_reg_4 ,
    \compute_tail.tail_r_lcl_reg_5 ,
    \compute_tail.tail_r_lcl_reg_6 ,
    auto_pre_r_lcl_reg_0,
    auto_pre_r_lcl_reg_1,
    auto_pre_r_lcl_reg_2,
    auto_pre_r_lcl_reg_3,
    \cmd_pipe_plus.mc_data_offset_reg[5] ,
    \cmd_pipe_plus.mc_data_offset_1_reg[5] ,
    \cmd_pipe_plus.mc_data_offset_2_reg[5] ,
    S,
    row_hit_r_reg_3,
    row_hit_r_reg_4,
    row_hit_r_reg_5,
    row_hit_r_reg_6,
    row_hit_r_reg_7,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1 ,
    rb_hit_busy_r_reg_1,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ,
    periodic_rd_r,
    cmd,
    \grant_r_reg[3]_1 ,
    granted_row_r_reg,
    \grant_r_reg[3]_2 ,
    \rtp_timer_r_reg[1] ,
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1] ,
    \periodic_read_request.periodic_rd_grant_r ,
    \periodic_rd_generation.read_this_rank_r ,
    \cmd_pipe_plus.mc_odt_reg[0] ,
    \rtw_timer.rtw_cnt_r_reg[1]_0 ,
    granted_col_r_reg_2,
    granted_col_r_reg_3,
    granted_col_r_reg_4,
    granted_col_r_reg_5,
    granted_col_r_reg_6,
    \ras_timer_r_reg[0] ,
    act_wait_r_lcl_reg_2,
    \ras_timer_r_reg[0]_0 ,
    \ras_timer_r_reg[0]_1 ,
    \q_entry_r_reg[1]_2 ,
    \maint_controller.maint_hit_busies_r_reg[3]_0 ,
    rd_wr_r_lcl_reg_0,
    accept_internal_r_reg,
    use_addr,
    req_bank_rdy_r_reg,
    req_bank_rdy_r_reg_0,
    req_bank_rdy_r_reg_1,
    \ras_timer_r_reg[0]_2 ,
    pass_open_bank_r_lcl_reg_1,
    pass_open_bank_r_lcl_reg_2,
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_0 ,
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_0 ,
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_1 ,
    maint_req_r,
    \cmd_pipe_plus.mc_we_n_reg[0] ,
    \cmd_pipe_plus.mc_address_reg[0] ,
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ,
    maint_zq_r,
    \cmd_pipe_plus.mc_address_reg[3] ,
    \cmd_pipe_plus.mc_address_reg[0]_0 ,
    \grant_r_reg[3]_3 ,
    \req_row_r_lcl_reg[13]_0 ,
    inhbt_act_faw_r,
    ras_timer_zero_r_reg,
    ras_timer_zero_r_reg_0,
    ras_timer_zero_r_reg_1,
    \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ,
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]_0 ,
    phy_mc_data_full,
    \rtp_timer_r_reg[0] ,
    \grant_r[2]_i_3 ,
    was_priority_reg,
    \req_data_buf_addr_r_reg[3] ,
    \req_bank_r_lcl_reg[2]_3 ,
    \req_col_r_reg[9] ,
    \q_entry_r_reg[1]_3 ,
    \q_entry_r_reg[0]_6 ,
    \q_entry_r_reg[1]_4 );
  output sent_row;
  output sent_col;
  output insert_maint_r1;
  output \generate_maint_cmds.insert_maint_r_lcl_reg ;
  output cs_en2;
  output [0:0]DIC;
  output col_rd_wr;
  output cke_r;
  output accept_internal_r;
  output periodic_rd_ack_r;
  output accept_r_reg;
  output accept_ns;
  output [3:0]rb_hit_busy_r;
  output [3:0]idle_r;
  output was_wr;
  output [2:0]rd_wr_r_lcl_reg;
  output [2:0]req_wr_r_lcl_reg;
  output p_130_out;
  output [3:0]row_cmd_wr;
  output col_wait_r;
  output demand_priority_r;
  output demanded_prior_r;
  output q_has_rd;
  output bm_end_r1;
  output col_wait_r_0;
  output req_bank_rdy_ns;
  output demand_priority_r_1;
  output demanded_prior_r_2;
  output pass_open_bank_r;
  output pre_bm_end_r;
  output q_has_rd_3;
  output bm_end_r1_0;
  output p_52_out;
  output col_wait_r_4;
  output demand_priority_r_5;
  output demanded_prior_r_6;
  output override_demand_r;
  output override_demand_ns;
  output q_has_rd_7;
  output bm_end_r1_1;
  output col_wait_r_8;
  output demand_priority_r_9;
  output pass_open_bank_r_10;
  output pre_bm_end_r_11;
  output q_has_rd_12;
  output pass_open_bank_r_lcl_reg;
  output pass_open_bank_r_lcl_reg_0;
  output rnk_config_valid_r;
  output maint_wip_r;
  output wait_for_maint_r;
  output wait_for_maint_r_13;
  output wait_for_maint_r_14;
  output wait_for_maint_r_15;
  output periodic_rd_cntr_r;
  output tail_r;
  output [3:0]head_r;
  output tail_r_16;
  output tail_r_17;
  output tail_r_18;
  output auto_pre_r;
  output auto_pre_r_19;
  output auto_pre_r_20;
  output auto_pre_r_21;
  output [3:0]\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] ;
  output [3:0]\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] ;
  output [3:0]\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17] ;
  output granted_col_r_reg;
  output \grant_r_reg[2] ;
  output idle_r_lcl_reg;
  output idle_r_lcl_reg_0;
  output [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ;
  output idle_r_lcl_reg_1;
  output [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[1] ;
  output idle_r_lcl_reg_2;
  output [3:0]Q;
  output clear_periodic_rd_request;
  output \periodic_rd_generation.read_this_rank_r_reg ;
  output \periodic_rd_generation.read_this_rank ;
  output [0:0]mc_odt_ns;
  output [0:0]D;
  output [0:0]granted_col_r_reg_0;
  output [0:0]granted_col_r_reg_1;
  output [0:0]E;
  output [1:0]\rtw_timer.rtw_cnt_r_reg[1] ;
  output \grant_r_reg[0] ;
  output \wr_this_rank_r_reg[0] ;
  output \wr_this_rank_r_reg[0]_0 ;
  output \rb_hit_busies.rb_hit_busies_r_lcl_reg[6] ;
  output pre_bm_end_r_reg;
  output [3:0]\grant_r_reg[3] ;
  output pre_passing_open_bank_r_reg;
  output \rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ;
  output \rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ;
  output pre_passing_open_bank_r_reg_0;
  output \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ;
  output \rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ;
  output pre_bm_end_r_reg_0;
  output pre_bm_end_r_reg_1;
  output set_order_q;
  output \q_entry_r_reg[1] ;
  output \q_entry_r_reg[0] ;
  output periodic_rd_ack_r_lcl_reg;
  output [0:0]\grant_r_reg[3]_0 ;
  output rb_hit_busy_r_reg;
  output row_hit_r_reg;
  output \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ;
  output \q_entry_r_reg[0]_0 ;
  output set_order_q_22;
  output \q_entry_r_reg[1]_0 ;
  output \q_entry_r_reg[0]_1 ;
  output \q_entry_r_reg[0]_2 ;
  output idle_r_lcl_reg_3;
  output \q_entry_r_reg[0]_3 ;
  output [1:0]q_entry_r;
  output idle_r_lcl_reg_4;
  output set_order_q_23;
  output pre_bm_end_r_reg_2;
  output demand_priority_r_reg;
  output rnk_config_valid_r_lcl_reg;
  output \order_q_r_reg[1] ;
  output set_order_q_24;
  output \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ;
  output \q_entry_r_reg[0]_4 ;
  output \q_entry_r_reg[0]_5 ;
  output \q_entry_r_reg[1]_1 ;
  output \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1 ;
  output row_hit_r_reg_0;
  output \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_2 ;
  output rb_hit_busy_r_reg_0;
  output row_hit_r_reg_1;
  output \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 ;
  output row_hit_r_reg_2;
  output [3:0]\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] ;
  output [1:0]mc_we_n_ns;
  output [2:0]mc_cas_n_ns;
  output [1:0]mc_ras_n_ns;
  output [8:0]\pre_4_1_1T_arb.granted_pre_r_reg ;
  output [2:0]\req_bank_r_lcl_reg[2] ;
  output [2:0]\req_bank_r_lcl_reg[2]_0 ;
  output [2:0]\req_bank_r_lcl_reg[2]_1 ;
  output [2:0]\req_bank_r_lcl_reg[2]_2 ;
  output [38:0]\pre_4_1_1T_arb.granted_pre_r_reg_0 ;
  output [19:0]\req_row_r_lcl_reg[13] ;
  output [0:0]mc_cs_n_ns;
  output act_wait_r_lcl_reg;
  output \compute_tail.tail_r_lcl_reg ;
  output \compute_tail.tail_r_lcl_reg_0 ;
  output idle_r_lcl_reg_5;
  output \compute_tail.tail_r_lcl_reg_1 ;
  output \compute_tail.tail_r_lcl_reg_2 ;
  output act_wait_r_lcl_reg_0;
  output \grant_r_reg[1] ;
  output demanded_prior_r_reg;
  output act_wait_r_lcl_reg_1;
  output \grant_r_reg[0]_0 ;
  output [0:0]\last_master_r_reg[3] ;
  output [3:0]col_wr_data_buf_addr;
  output act_this_rank;
  output \grant_r_reg[0]_1 ;
  output \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4] ;
  output \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] ;
  output demanded_prior_r_reg_0;
  output \grant_r_reg[0]_2 ;
  output [3:0]\maint_controller.maint_hit_busies_r_reg[3] ;
  input \maint_controller.maint_wip_r_lcl_reg ;
  input cke_r_reg;
  input [0:0]mc_cke_ns;
  input maint_srx_r;
  input col_wait_r_reg;
  input periodic_rd_cntr_r_reg;
  input phy_mc_ctl_full;
  input ofs_rdy_r_reg;
  input [0:0]of_ctl_full_v;
  input q_has_rd_r_reg;
  input col_wait_r_reg_0;
  input q_has_rd_r_reg_0;
  input col_wait_r_reg_1;
  input q_has_rd_r_reg_1;
  input col_wait_r_reg_2;
  input q_has_rd_r_reg_2;
  input auto_pre_r_lcl_reg;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ;
  input [0:0]SR;
  input rnk_config_valid_r_lcl_reg_0;
  input \maint_controller.maint_wip_r_lcl_reg_0 ;
  input \maint_controller.maint_wip_r_lcl_reg_1 ;
  input wait_for_maint_r_lcl_reg;
  input wait_for_maint_r_lcl_reg_0;
  input wait_for_maint_r_lcl_reg_1;
  input wait_for_maint_r_lcl_reg_2;
  input periodic_rd_cntr_r_reg_0;
  input \compute_tail.tail_r_lcl_reg_3 ;
  input head_r_lcl_reg;
  input head_r_lcl_reg_0;
  input head_r_lcl_reg_1;
  input head_r_lcl_reg_2;
  input \compute_tail.tail_r_lcl_reg_4 ;
  input \compute_tail.tail_r_lcl_reg_5 ;
  input \compute_tail.tail_r_lcl_reg_6 ;
  input auto_pre_r_lcl_reg_0;
  input auto_pre_r_lcl_reg_1;
  input auto_pre_r_lcl_reg_2;
  input auto_pre_r_lcl_reg_3;
  input [5:0]\cmd_pipe_plus.mc_data_offset_reg[5] ;
  input [5:0]\cmd_pipe_plus.mc_data_offset_1_reg[5] ;
  input [5:0]\cmd_pipe_plus.mc_data_offset_2_reg[5] ;
  input [2:0]S;
  input [0:0]row_hit_r_reg_3;
  input [0:0]row_hit_r_reg_4;
  input [0:0]row_hit_r_reg_5;
  input [0:0]row_hit_r_reg_6;
  input [0:0]row_hit_r_reg_7;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1 ;
  input rb_hit_busy_r_reg_1;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ;
  input periodic_rd_r;
  input [1:0]cmd;
  input \grant_r_reg[3]_1 ;
  input granted_row_r_reg;
  input \grant_r_reg[3]_2 ;
  input \rtp_timer_r_reg[1] ;
  input \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1] ;
  input \periodic_read_request.periodic_rd_grant_r ;
  input \periodic_rd_generation.read_this_rank_r ;
  input \cmd_pipe_plus.mc_odt_reg[0] ;
  input [1:0]\rtw_timer.rtw_cnt_r_reg[1]_0 ;
  input granted_col_r_reg_2;
  input granted_col_r_reg_3;
  input granted_col_r_reg_4;
  input granted_col_r_reg_5;
  input granted_col_r_reg_6;
  input \ras_timer_r_reg[0] ;
  input act_wait_r_lcl_reg_2;
  input \ras_timer_r_reg[0]_0 ;
  input \ras_timer_r_reg[0]_1 ;
  input \q_entry_r_reg[1]_2 ;
  input [3:0]\maint_controller.maint_hit_busies_r_reg[3]_0 ;
  input rd_wr_r_lcl_reg_0;
  input accept_internal_r_reg;
  input use_addr;
  input req_bank_rdy_r_reg;
  input req_bank_rdy_r_reg_0;
  input req_bank_rdy_r_reg_1;
  input \ras_timer_r_reg[0]_2 ;
  input pass_open_bank_r_lcl_reg_1;
  input pass_open_bank_r_lcl_reg_2;
  input [1:0]\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_0 ;
  input \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_0 ;
  input \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_1 ;
  input maint_req_r;
  input \cmd_pipe_plus.mc_we_n_reg[0] ;
  input \cmd_pipe_plus.mc_address_reg[0] ;
  input \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ;
  input maint_zq_r;
  input \cmd_pipe_plus.mc_address_reg[3] ;
  input \cmd_pipe_plus.mc_address_reg[0]_0 ;
  input \grant_r_reg[3]_3 ;
  input [13:0]\req_row_r_lcl_reg[13]_0 ;
  input inhbt_act_faw_r;
  input ras_timer_zero_r_reg;
  input ras_timer_zero_r_reg_0;
  input ras_timer_zero_r_reg_1;
  input [3:0]\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ;
  input \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]_0 ;
  input phy_mc_data_full;
  input \rtp_timer_r_reg[0] ;
  input [0:0]\grant_r[2]_i_3 ;
  input was_priority_reg;
  input [3:0]\req_data_buf_addr_r_reg[3] ;
  input [2:0]\req_bank_r_lcl_reg[2]_3 ;
  input [9:0]\req_col_r_reg[9] ;
  input \q_entry_r_reg[1]_3 ;
  input \q_entry_r_reg[0]_6 ;
  input \q_entry_r_reg[1]_4 ;

  wire [0:0]D;
  wire [0:0]DIC;
  wire [0:0]E;
  wire [3:0]Q;
  wire [2:0]S;
  wire [0:0]SR;
  wire accept_internal_r;
  wire accept_internal_r_reg;
  wire accept_ns;
  wire accept_r_reg;
  wire act_this_rank;
  wire [3:0]act_this_rank_r;
  wire act_wait_r_lcl_reg;
  wire act_wait_r_lcl_reg_0;
  wire act_wait_r_lcl_reg_1;
  wire act_wait_r_lcl_reg_2;
  wire arb_mux0_n_100;
  wire arb_mux0_n_101;
  wire arb_mux0_n_102;
  wire arb_mux0_n_103;
  wire arb_mux0_n_104;
  wire arb_mux0_n_118;
  wire arb_mux0_n_119;
  wire arb_mux0_n_120;
  wire arb_mux0_n_38;
  wire \arb_row_col0/granted_col_ns ;
  wire \arb_row_col0/pre_4_1_1T_arb.granted_pre_ns ;
  wire \arb_row_col0/rnk_config_strobe_ns ;
  wire auto_pre_r;
  wire auto_pre_r_19;
  wire auto_pre_r_20;
  wire auto_pre_r_21;
  wire auto_pre_r_lcl_reg;
  wire auto_pre_r_lcl_reg_0;
  wire auto_pre_r_lcl_reg_1;
  wire auto_pre_r_lcl_reg_2;
  wire auto_pre_r_lcl_reg_3;
  wire \bank_cntrl[0].bank0_n_24 ;
  wire \bank_cntrl[0].bank0_n_26 ;
  wire \bank_cntrl[0].bank0_n_27 ;
  wire \bank_cntrl[0].bank0_n_28 ;
  wire \bank_cntrl[0].bank0_n_29 ;
  wire \bank_cntrl[0].bank0_n_30 ;
  wire \bank_cntrl[0].bank0_n_33 ;
  wire \bank_cntrl[0].bank0_n_34 ;
  wire \bank_cntrl[0].bank0_n_38 ;
  wire \bank_cntrl[0].bank0_n_39 ;
  wire \bank_cntrl[0].bank0_n_40 ;
  wire \bank_cntrl[0].bank0_n_42 ;
  wire \bank_cntrl[0].bank0_n_43 ;
  wire \bank_cntrl[0].bank0_n_44 ;
  wire \bank_cntrl[0].bank0_n_46 ;
  wire \bank_cntrl[0].bank0_n_49 ;
  wire \bank_cntrl[0].bank0_n_53 ;
  wire \bank_cntrl[1].bank0_n_22 ;
  wire \bank_cntrl[1].bank0_n_26 ;
  wire \bank_cntrl[1].bank0_n_30 ;
  wire \bank_cntrl[1].bank0_n_36 ;
  wire \bank_cntrl[1].bank0_n_41 ;
  wire \bank_cntrl[1].bank0_n_43 ;
  wire \bank_cntrl[1].bank0_n_44 ;
  wire \bank_cntrl[1].bank0_n_47 ;
  wire \bank_cntrl[2].bank0_n_22 ;
  wire \bank_cntrl[2].bank0_n_29 ;
  wire \bank_cntrl[2].bank0_n_31 ;
  wire \bank_cntrl[2].bank0_n_32 ;
  wire \bank_cntrl[2].bank0_n_33 ;
  wire \bank_cntrl[2].bank0_n_34 ;
  wire \bank_cntrl[2].bank0_n_40 ;
  wire \bank_cntrl[2].bank0_n_41 ;
  wire \bank_cntrl[2].bank0_n_43 ;
  wire \bank_cntrl[2].bank0_n_46 ;
  wire \bank_cntrl[2].bank0_n_47 ;
  wire \bank_cntrl[2].bank0_n_48 ;
  wire \bank_cntrl[2].bank0_n_64 ;
  wire \bank_cntrl[3].bank0_n_21 ;
  wire \bank_cntrl[3].bank0_n_27 ;
  wire \bank_cntrl[3].bank0_n_29 ;
  wire \bank_cntrl[3].bank0_n_30 ;
  wire \bank_cntrl[3].bank0_n_38 ;
  wire \bank_cntrl[3].bank0_n_41 ;
  wire \bank_cntrl[3].bank0_n_46 ;
  wire \bank_cntrl[3].bank0_n_61 ;
  wire \bank_cntrl[3].bank0_n_62 ;
  wire \bank_cntrl[3].bank0_n_63 ;
  wire bank_common0_n_11;
  wire bank_common0_n_13;
  wire bank_common0_n_15;
  wire bank_common0_n_17;
  wire bank_common0_n_24;
  wire bank_common0_n_25;
  wire bank_common0_n_26;
  wire bank_common0_n_28;
  wire bank_common0_n_30;
  wire [9:0]\bank_compare0/req_col_r ;
  wire [9:0]\bank_compare0/req_col_r_10 ;
  wire [9:0]\bank_compare0/req_col_r_2 ;
  wire [9:0]\bank_compare0/req_col_r_6 ;
  wire \bank_compare0/req_wr_r_lcl0 ;
  wire [1:1]\bank_queue0/q_entry_ns ;
  wire \bank_state0/demanded_prior_r ;
  wire \bank_state0/ofs_rdy_r ;
  wire \bank_state0/ofs_rdy_r0 ;
  wire \bank_state0/ofs_rdy_r0_0 ;
  wire \bank_state0/ofs_rdy_r0_1 ;
  wire \bank_state0/ofs_rdy_r_13 ;
  wire \bank_state0/ofs_rdy_r_5 ;
  wire \bank_state0/ofs_rdy_r_9 ;
  wire \bank_state0/req_bank_rdy_ns ;
  wire \bank_state0/req_bank_rdy_ns_14 ;
  wire \bank_state0/req_bank_rdy_r ;
  wire bm_end_r1;
  wire bm_end_r1_0;
  wire bm_end_r1_1;
  wire cke_r;
  wire cke_r_reg;
  wire clear_periodic_rd_request;
  wire [1:0]cmd;
  wire \cmd_pipe_plus.mc_address_reg[0] ;
  wire \cmd_pipe_plus.mc_address_reg[0]_0 ;
  wire \cmd_pipe_plus.mc_address_reg[3] ;
  wire [5:0]\cmd_pipe_plus.mc_data_offset_1_reg[5] ;
  wire [5:0]\cmd_pipe_plus.mc_data_offset_2_reg[5] ;
  wire [5:0]\cmd_pipe_plus.mc_data_offset_reg[5] ;
  wire \cmd_pipe_plus.mc_odt_reg[0] ;
  wire \cmd_pipe_plus.mc_we_n_reg[0] ;
  wire col_rd_wr;
  wire col_wait_r;
  wire col_wait_r_0;
  wire col_wait_r_4;
  wire col_wait_r_8;
  wire col_wait_r_reg;
  wire col_wait_r_reg_0;
  wire col_wait_r_reg_1;
  wire col_wait_r_reg_2;
  wire [3:0]col_wr_data_buf_addr;
  wire \compute_tail.tail_r_lcl_reg ;
  wire \compute_tail.tail_r_lcl_reg_0 ;
  wire \compute_tail.tail_r_lcl_reg_1 ;
  wire \compute_tail.tail_r_lcl_reg_2 ;
  wire \compute_tail.tail_r_lcl_reg_3 ;
  wire \compute_tail.tail_r_lcl_reg_4 ;
  wire \compute_tail.tail_r_lcl_reg_5 ;
  wire \compute_tail.tail_r_lcl_reg_6 ;
  wire cs_en2;
  wire [3:0]\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ;
  wire demand_priority_r;
  wire demand_priority_r_1;
  wire demand_priority_r_5;
  wire demand_priority_r_9;
  wire demand_priority_r_reg;
  wire demanded_prior_r;
  wire demanded_prior_r_2;
  wire demanded_prior_r_6;
  wire demanded_prior_r_reg;
  wire demanded_prior_r_reg_0;
  wire \generate_maint_cmds.insert_maint_r_lcl_reg ;
  wire [0:0]\grant_r[2]_i_3 ;
  wire \grant_r_reg[0] ;
  wire \grant_r_reg[0]_0 ;
  wire \grant_r_reg[0]_1 ;
  wire \grant_r_reg[0]_2 ;
  wire \grant_r_reg[1] ;
  wire \grant_r_reg[2] ;
  wire [3:0]\grant_r_reg[3] ;
  wire [0:0]\grant_r_reg[3]_0 ;
  wire \grant_r_reg[3]_1 ;
  wire \grant_r_reg[3]_2 ;
  wire \grant_r_reg[3]_3 ;
  wire granted_col_r_reg;
  wire [0:0]granted_col_r_reg_0;
  wire [0:0]granted_col_r_reg_1;
  wire granted_col_r_reg_2;
  wire granted_col_r_reg_3;
  wire granted_col_r_reg_4;
  wire granted_col_r_reg_5;
  wire granted_col_r_reg_6;
  wire granted_row_r_reg;
  wire [3:0]head_r;
  wire head_r_lcl_reg;
  wire head_r_lcl_reg_0;
  wire head_r_lcl_reg_1;
  wire head_r_lcl_reg_2;
  wire hi_priority;
  wire [3:0]idle_r;
  wire idle_r_lcl_reg;
  wire idle_r_lcl_reg_0;
  wire idle_r_lcl_reg_1;
  wire idle_r_lcl_reg_2;
  wire idle_r_lcl_reg_3;
  wire idle_r_lcl_reg_4;
  wire idle_r_lcl_reg_5;
  wire inhbt_act_faw_r;
  wire insert_maint_r1;
  wire [0:0]\last_master_r_reg[3] ;
  wire [3:0]\maint_controller.maint_hit_busies_r_reg[3] ;
  wire [3:0]\maint_controller.maint_hit_busies_r_reg[3]_0 ;
  wire \maint_controller.maint_wip_r_lcl_reg ;
  wire \maint_controller.maint_wip_r_lcl_reg_0 ;
  wire \maint_controller.maint_wip_r_lcl_reg_1 ;
  wire maint_req_r;
  wire maint_srx_r;
  wire maint_wip_r;
  wire maint_zq_r;
  wire [2:0]mc_cas_n_ns;
  wire [0:0]mc_cke_ns;
  wire [0:0]mc_cs_n_ns;
  wire [0:0]mc_odt_ns;
  wire [1:0]mc_ras_n_ns;
  wire [1:0]mc_we_n_ns;
  wire [0:0]of_ctl_full_v;
  wire ofs_rdy_r_reg;
  wire \order_q_r_reg[1] ;
  wire override_demand_ns;
  wire override_demand_r;
  wire p_130_out;
  wire p_52_out;
  wire p_9_in;
  wire pass_open_bank_r;
  wire pass_open_bank_r_10;
  wire pass_open_bank_r_lcl_reg;
  wire pass_open_bank_r_lcl_reg_0;
  wire pass_open_bank_r_lcl_reg_1;
  wire pass_open_bank_r_lcl_reg_2;
  wire periodic_rd_ack_r;
  wire periodic_rd_ack_r_lcl_reg;
  wire periodic_rd_cntr_r;
  wire periodic_rd_cntr_r_reg;
  wire periodic_rd_cntr_r_reg_0;
  wire \periodic_rd_generation.read_this_rank ;
  wire \periodic_rd_generation.read_this_rank_r ;
  wire \periodic_rd_generation.read_this_rank_r_reg ;
  wire periodic_rd_insert;
  wire periodic_rd_r;
  wire \periodic_read_request.periodic_rd_grant_r ;
  wire phy_mc_ctl_full;
  wire phy_mc_data_full;
  wire [8:0]\pre_4_1_1T_arb.granted_pre_r_reg ;
  wire [38:0]\pre_4_1_1T_arb.granted_pre_r_reg_0 ;
  wire pre_bm_end_r;
  wire pre_bm_end_r_11;
  wire pre_bm_end_r_reg;
  wire pre_bm_end_r_reg_0;
  wire pre_bm_end_r_reg_1;
  wire pre_bm_end_r_reg_2;
  wire pre_passing_open_bank_r_reg;
  wire pre_passing_open_bank_r_reg_0;
  wire [1:0]q_entry_r;
  wire \q_entry_r_reg[0] ;
  wire \q_entry_r_reg[0]_0 ;
  wire \q_entry_r_reg[0]_1 ;
  wire \q_entry_r_reg[0]_2 ;
  wire \q_entry_r_reg[0]_3 ;
  wire \q_entry_r_reg[0]_4 ;
  wire \q_entry_r_reg[0]_5 ;
  wire \q_entry_r_reg[0]_6 ;
  wire \q_entry_r_reg[1] ;
  wire \q_entry_r_reg[1]_0 ;
  wire \q_entry_r_reg[1]_1 ;
  wire \q_entry_r_reg[1]_2 ;
  wire \q_entry_r_reg[1]_3 ;
  wire \q_entry_r_reg[1]_4 ;
  wire q_has_priority;
  wire q_has_priority_12;
  wire q_has_priority_4;
  wire q_has_priority_8;
  wire q_has_rd;
  wire q_has_rd_12;
  wire q_has_rd_3;
  wire q_has_rd_7;
  wire q_has_rd_r_reg;
  wire q_has_rd_r_reg_0;
  wire q_has_rd_r_reg_1;
  wire q_has_rd_r_reg_2;
  wire [3:0]\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] ;
  wire [3:0]\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] ;
  wire [3:0]\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17] ;
  wire \ras_timer_r_reg[0] ;
  wire \ras_timer_r_reg[0]_0 ;
  wire \ras_timer_r_reg[0]_1 ;
  wire \ras_timer_r_reg[0]_2 ;
  wire ras_timer_zero_r_reg;
  wire ras_timer_zero_r_reg_0;
  wire ras_timer_zero_r_reg_1;
  wire [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[1] ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_2 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 ;
  wire [0:0]\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[6] ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0 ;
  wire [3:2]rb_hit_busies_r;
  wire [6:5]rb_hit_busies_r_11;
  wire [3:2]rb_hit_busies_r_3;
  wire [5:3]rb_hit_busies_r_7;
  wire [3:0]rb_hit_busy_r;
  wire rb_hit_busy_r_reg;
  wire rb_hit_busy_r_reg_0;
  wire rb_hit_busy_r_reg_1;
  wire [3:0]rd_this_rank_r;
  wire [0:0]rd_wr_r;
  wire [2:0]rd_wr_r_lcl_reg;
  wire rd_wr_r_lcl_reg_0;
  wire [2:0]\req_bank_r_lcl_reg[2] ;
  wire [2:0]\req_bank_r_lcl_reg[2]_0 ;
  wire [2:0]\req_bank_r_lcl_reg[2]_1 ;
  wire [2:0]\req_bank_r_lcl_reg[2]_2 ;
  wire [2:0]\req_bank_r_lcl_reg[2]_3 ;
  wire req_bank_rdy_ns;
  wire req_bank_rdy_r_reg;
  wire req_bank_rdy_r_reg_0;
  wire req_bank_rdy_r_reg_1;
  wire [9:0]\req_col_r_reg[9] ;
  wire [18:0]req_data_buf_addr_r;
  wire [3:0]\req_data_buf_addr_r_reg[3] ;
  wire [3:0]req_periodic_rd_r;
  wire [53:9]req_row_r;
  wire [19:0]\req_row_r_lcl_reg[13] ;
  wire [13:0]\req_row_r_lcl_reg[13]_0 ;
  wire [2:0]req_wr_r_lcl_reg;
  wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ;
  wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1] ;
  wire [3:0]\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] ;
  wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_0 ;
  wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_1 ;
  wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4] ;
  wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]_0 ;
  wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] ;
  wire [1:0]\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_0 ;
  wire rnk_config_valid_r;
  wire rnk_config_valid_r_lcl_reg;
  wire rnk_config_valid_r_lcl_reg_0;
  wire [3:0]row_cmd_wr;
  wire row_hit_r_reg;
  wire row_hit_r_reg_0;
  wire row_hit_r_reg_1;
  wire row_hit_r_reg_2;
  wire [0:0]row_hit_r_reg_3;
  wire [0:0]row_hit_r_reg_4;
  wire [0:0]row_hit_r_reg_5;
  wire [0:0]row_hit_r_reg_6;
  wire [0:0]row_hit_r_reg_7;
  wire \rtp_timer_r_reg[0] ;
  wire \rtp_timer_r_reg[1] ;
  wire [1:0]\rtw_timer.rtw_cnt_r_reg[1] ;
  wire [1:0]\rtw_timer.rtw_cnt_r_reg[1]_0 ;
  wire [2:0]sending_pre;
  wire sent_col;
  wire sent_row;
  wire set_order_q;
  wire set_order_q_22;
  wire set_order_q_23;
  wire set_order_q_24;
  wire tail_r;
  wire tail_r_16;
  wire tail_r_17;
  wire tail_r_18;
  wire use_addr;
  wire wait_for_maint_r;
  wire wait_for_maint_r_13;
  wire wait_for_maint_r_14;
  wire wait_for_maint_r_15;
  wire wait_for_maint_r_lcl_reg;
  wire wait_for_maint_r_lcl_reg_0;
  wire wait_for_maint_r_lcl_reg_1;
  wire wait_for_maint_r_lcl_reg_2;
  wire was_priority_reg;
  wire was_wr;
  wire [3:0]wr_this_rank_r;
  wire \wr_this_rank_r_reg[0] ;
  wire \wr_this_rank_r_reg[0]_0 ;

  mig_mig_7series_v4_2_arb_mux arb_mux0
       (.D(D),
        .DIC(DIC),
        .E(E),
        .Q(Q),
        .SR(SR),
        .act_this_rank(act_this_rank),
        .act_this_rank_r(act_this_rank_r),
        .cke_r(cke_r),
        .cke_r_reg(\maint_controller.maint_wip_r_lcl_reg ),
        .cke_r_reg_0(cke_r_reg),
        .\cmd_pipe_plus.mc_address_reg[0] (\cmd_pipe_plus.mc_address_reg[0] ),
        .\cmd_pipe_plus.mc_address_reg[0]_0 (\cmd_pipe_plus.mc_address_reg[0]_0 ),
        .\cmd_pipe_plus.mc_address_reg[10] (row_cmd_wr[0]),
        .\cmd_pipe_plus.mc_address_reg[10]_0 (\bank_cntrl[3].bank0_n_61 ),
        .\cmd_pipe_plus.mc_address_reg[23] (\bank_compare0/req_col_r_10 ),
        .\cmd_pipe_plus.mc_address_reg[23]_0 (\bank_compare0/req_col_r ),
        .\cmd_pipe_plus.mc_address_reg[23]_1 (\bank_compare0/req_col_r_2 ),
        .\cmd_pipe_plus.mc_address_reg[23]_2 (\bank_compare0/req_col_r_6 ),
        .\cmd_pipe_plus.mc_address_reg[24] (auto_pre_r_21),
        .\cmd_pipe_plus.mc_address_reg[24]_0 (auto_pre_r),
        .\cmd_pipe_plus.mc_address_reg[24]_1 (auto_pre_r_19),
        .\cmd_pipe_plus.mc_address_reg[24]_2 (auto_pre_r_20),
        .\cmd_pipe_plus.mc_address_reg[38] (\bank_cntrl[2].bank0_n_64 ),
        .\cmd_pipe_plus.mc_address_reg[3] (\cmd_pipe_plus.mc_address_reg[3] ),
        .\cmd_pipe_plus.mc_address_reg[41] (\req_row_r_lcl_reg[13] ),
        .\cmd_pipe_plus.mc_bank_reg[2] (\req_bank_r_lcl_reg[2] ),
        .\cmd_pipe_plus.mc_bank_reg[2]_0 (\req_bank_r_lcl_reg[2]_0 ),
        .\cmd_pipe_plus.mc_bank_reg[2]_1 (\req_bank_r_lcl_reg[2]_1 ),
        .\cmd_pipe_plus.mc_bank_reg[8] (\req_bank_r_lcl_reg[2]_2 ),
        .\cmd_pipe_plus.mc_cas_n_reg[0] (\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ),
        .\cmd_pipe_plus.mc_data_offset_1_reg[5] (\cmd_pipe_plus.mc_data_offset_1_reg[5] ),
        .\cmd_pipe_plus.mc_data_offset_2_reg[0] (rd_wr_r_lcl_reg[1]),
        .\cmd_pipe_plus.mc_data_offset_2_reg[0]_0 (rd_wr_r_lcl_reg[2]),
        .\cmd_pipe_plus.mc_data_offset_2_reg[5] (\cmd_pipe_plus.mc_data_offset_2_reg[5] ),
        .\cmd_pipe_plus.mc_data_offset_reg[5] (\cmd_pipe_plus.mc_data_offset_reg[5] ),
        .\cmd_pipe_plus.mc_odt_reg[0] (\cmd_pipe_plus.mc_odt_reg[0] ),
        .\cmd_pipe_plus.mc_we_n_reg[0] (\cmd_pipe_plus.mc_we_n_reg[0] ),
        .\cmd_pipe_plus.mc_we_n_reg[0]_0 (row_cmd_wr[1]),
        .\cmd_pipe_plus.mc_we_n_reg[0]_1 (row_cmd_wr[2]),
        .\cmd_pipe_plus.mc_we_n_reg[2] (row_cmd_wr[3]),
        .col_rd_wr(col_rd_wr),
        .col_wr_data_buf_addr(col_wr_data_buf_addr),
        .\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] (\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ),
        .\grant_r[2]_i_3 (\rtp_timer_r_reg[0] ),
        .\grant_r[2]_i_3_0 (\grant_r[2]_i_3 ),
        .\grant_r[3]_i_8 (req_wr_r_lcl_reg[2]),
        .\grant_r[3]_i_8_0 (req_wr_r_lcl_reg[1]),
        .\grant_r_reg[0] (\grant_r_reg[0] ),
        .\grant_r_reg[0]_0 (\grant_r_reg[0]_0 ),
        .\grant_r_reg[0]_1 (\grant_r_reg[0]_1 ),
        .\grant_r_reg[0]_2 (\grant_r_reg[0]_2 ),
        .\grant_r_reg[0]_3 (\bank_cntrl[3].bank0_n_27 ),
        .\grant_r_reg[0]_4 (\bank_cntrl[0].bank0_n_24 ),
        .\grant_r_reg[0]_5 (\bank_cntrl[2].bank0_n_29 ),
        .\grant_r_reg[0]_6 (\bank_cntrl[3].bank0_n_46 ),
        .\grant_r_reg[0]_7 (\bank_cntrl[2].bank0_n_48 ),
        .\grant_r_reg[0]_8 (\bank_cntrl[0].bank0_n_53 ),
        .\grant_r_reg[1] (\grant_r_reg[1] ),
        .\grant_r_reg[1]_0 (\bank_cntrl[1].bank0_n_47 ),
        .\grant_r_reg[2] (\grant_r_reg[2] ),
        .\grant_r_reg[2]_0 (\bank_cntrl[1].bank0_n_26 ),
        .\grant_r_reg[3] (arb_mux0_n_38),
        .\grant_r_reg[3]_0 (\grant_r_reg[3] ),
        .\grant_r_reg[3]_1 ({\grant_r_reg[3]_0 ,sending_pre}),
        .\grant_r_reg[3]_2 (\grant_r_reg[3]_1 ),
        .\grant_r_reg[3]_3 (\grant_r_reg[3]_2 ),
        .\grant_r_reg[3]_4 (\grant_r_reg[3]_3 ),
        .\grant_r_reg[3]_5 (\bank_cntrl[2].bank0_n_47 ),
        .granted_col_ns(\arb_row_col0/granted_col_ns ),
        .granted_col_r_reg(sent_col),
        .granted_col_r_reg_0(granted_col_r_reg),
        .granted_col_r_reg_1(granted_col_r_reg_0),
        .granted_col_r_reg_2(granted_col_r_reg_1),
        .granted_row_r_reg(sent_row),
        .granted_row_r_reg_0(granted_row_r_reg),
        .i___22_i_1(rd_wr_r_lcl_reg[0]),
        .inhbt_act_faw_r(inhbt_act_faw_r),
        .insert_maint_r1_lcl_reg(insert_maint_r1),
        .insert_maint_r1_lcl_reg_0(\generate_maint_cmds.insert_maint_r_lcl_reg ),
        .\last_master_r_reg[3] (\last_master_r_reg[3] ),
        .maint_srx_r(maint_srx_r),
        .maint_zq_r(maint_zq_r),
        .mc_cas_n_ns(mc_cas_n_ns),
        .mc_cke_ns(mc_cke_ns),
        .mc_cs_n_ns(mc_cs_n_ns),
        .mc_odt_ns(mc_odt_ns),
        .mc_ras_n_ns(mc_ras_n_ns),
        .mc_we_n_ns(mc_we_n_ns),
        .ofs_rdy_r(\bank_state0/ofs_rdy_r_9 ),
        .ofs_rdy_r_0(\bank_state0/ofs_rdy_r ),
        .ofs_rdy_r_1(\bank_state0/ofs_rdy_r_13 ),
        .ofs_rdy_r_2(\bank_state0/ofs_rdy_r_5 ),
        .override_demand_ns(override_demand_ns),
        .\periodic_rd_generation.read_this_rank (\periodic_rd_generation.read_this_rank ),
        .\periodic_rd_generation.read_this_rank_r (\periodic_rd_generation.read_this_rank_r ),
        .\periodic_rd_generation.read_this_rank_r_reg (\periodic_rd_generation.read_this_rank_r_reg ),
        .\pre_4_1_1T_arb.granted_pre_ns (\arb_row_col0/pre_4_1_1T_arb.granted_pre_ns ),
        .\pre_4_1_1T_arb.granted_pre_r_reg (cs_en2),
        .\pre_4_1_1T_arb.granted_pre_r_reg_0 (\pre_4_1_1T_arb.granted_pre_r_reg ),
        .\pre_4_1_1T_arb.granted_pre_r_reg_1 (\pre_4_1_1T_arb.granted_pre_r_reg_0 ),
        .\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] (\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] ),
        .\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] (\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] ),
        .\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17] (\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17] ),
        .rd_this_rank_r(rd_this_rank_r),
        .rd_wr_r(rd_wr_r),
        .req_bank_rdy_r(\bank_state0/req_bank_rdy_r ),
        .req_bank_rdy_r_reg(arb_mux0_n_118),
        .req_data_buf_addr_r({req_data_buf_addr_r[18:15],req_data_buf_addr_r[13:10],req_data_buf_addr_r[8:5],req_data_buf_addr_r[3:0]}),
        .req_periodic_rd_r(req_periodic_rd_r),
        .req_row_r({req_row_r[53:42],req_row_r[39],req_row_r[37:28],req_row_r[22:14],req_row_r[11:9]}),
        .rnk_config_strobe_ns(\arb_row_col0/rnk_config_strobe_ns ),
        .\rnk_config_strobe_r_reg[0] (arb_mux0_n_100),
        .rnk_config_valid_r_lcl_reg(rnk_config_valid_r),
        .rnk_config_valid_r_lcl_reg_0(arb_mux0_n_101),
        .rnk_config_valid_r_lcl_reg_1(arb_mux0_n_102),
        .rnk_config_valid_r_lcl_reg_2(arb_mux0_n_103),
        .rnk_config_valid_r_lcl_reg_3(arb_mux0_n_104),
        .rnk_config_valid_r_lcl_reg_4(rnk_config_valid_r_lcl_reg_0),
        .\rtw_timer.rtw_cnt_r_reg[0] (\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1] ),
        .\rtw_timer.rtw_cnt_r_reg[1] (\rtw_timer.rtw_cnt_r_reg[1] ),
        .\rtw_timer.rtw_cnt_r_reg[1]_0 (arb_mux0_n_119),
        .\rtw_timer.rtw_cnt_r_reg[1]_1 (\rtw_timer.rtw_cnt_r_reg[1]_0 ),
        .wr_this_rank_r(wr_this_rank_r),
        .\wr_this_rank_r_reg[0] (\wr_this_rank_r_reg[0] ),
        .\wr_this_rank_r_reg[0]_0 (\wr_this_rank_r_reg[0]_0 ),
        .\wtr_timer.wtr_cnt_r_reg[1] (arb_mux0_n_120));
  mig_mig_7series_v4_2_bank_cntrl \bank_cntrl[0].bank0 
       (.E(idle_r[0]),
        .Q({Q[3],Q[0]}),
        .S(S),
        .accept_internal_r_reg(idle_r_lcl_reg),
        .accept_internal_r_reg_0(idle_r_lcl_reg_0),
        .accept_internal_r_reg_1(idle_r_lcl_reg_1),
        .accept_internal_r_reg_2(accept_internal_r_reg),
        .accept_internal_r_reg_3(periodic_rd_ack_r),
        .accept_internal_r_reg_4(accept_internal_r),
        .act_this_rank_r(act_this_rank_r[0]),
        .act_wait_r_lcl_reg(row_cmd_wr[0]),
        .act_wait_r_lcl_reg_0(act_wait_r_lcl_reg),
        .act_wait_r_lcl_reg_1(act_wait_r_lcl_reg_2),
        .auto_pre_r_lcl_reg(auto_pre_r),
        .auto_pre_r_lcl_reg_0(\bank_cntrl[0].bank0_n_53 ),
        .auto_pre_r_lcl_reg_1(auto_pre_r_lcl_reg_0),
        .auto_pre_r_lcl_reg_2(accept_r_reg),
        .bm_end_r1_reg(\bank_cntrl[0].bank0_n_26 ),
        .bm_end_r1_reg_0(\bank_cntrl[0].bank0_n_27 ),
        .col_wait_r_reg(col_wait_r),
        .col_wait_r_reg_0(col_wait_r_reg),
        .\compute_tail.tail_r_lcl_reg (\compute_tail.tail_r_lcl_reg_0 ),
        .\compute_tail.tail_r_lcl_reg_0 (\compute_tail.tail_r_lcl_reg_3 ),
        .demand_priority_r_reg(demand_priority_r),
        .demand_priority_r_reg_0(sent_col),
        .demanded_prior_r(\bank_state0/demanded_prior_r ),
        .demanded_prior_r_reg(demanded_prior_r),
        .demanded_prior_r_reg_0(demanded_prior_r_reg_0),
        .demanded_prior_r_reg_1(demanded_prior_r_reg),
        .demanded_prior_r_reg_2(demand_priority_r_9),
        .\grant_r[2]_i_3 (\bank_cntrl[3].bank0_n_63 ),
        .\grant_r[2]_i_3_0 (arb_mux0_n_102),
        .granted_col_r_reg(granted_col_r_reg_6),
        .granted_col_r_reg_0(arb_mux0_n_120),
        .granted_col_r_reg_1(arb_mux0_n_119),
        .head_r_lcl_reg(head_r[0]),
        .head_r_lcl_reg_0(head_r_lcl_reg),
        .head_r_lcl_reg_1(bank_common0_n_15),
        .hi_priority(hi_priority),
        .i___3_i_4(pre_bm_end_r_reg),
        .idle_r_lcl_reg(idle_r_lcl_reg_2),
        .idle_r_lcl_reg_0(\bank_cntrl[0].bank0_n_28 ),
        .idle_r_lcl_reg_1(\bank_cntrl[0].bank0_n_29 ),
        .idle_r_lcl_reg_2(\bank_cntrl[0].bank0_n_30 ),
        .idle_r_lcl_reg_3(\bank_cntrl[0].bank0_n_33 ),
        .idle_r_lcl_reg_4(\bank_cntrl[0].bank0_n_34 ),
        .idle_r_lcl_reg_5(idle_r_lcl_reg_4),
        .idle_r_lcl_reg_6(\bank_cntrl[0].bank0_n_49 ),
        .idle_r_lcl_reg_7(idle_r_lcl_reg_5),
        .maint_req_r(maint_req_r),
        .of_ctl_full_v(of_ctl_full_v),
        .ofs_rdy_r(\bank_state0/ofs_rdy_r ),
        .ofs_rdy_r0(\bank_state0/ofs_rdy_r0_1 ),
        .ofs_rdy_r0_0(\bank_state0/ofs_rdy_r0_0 ),
        .ofs_rdy_r0_1(\bank_state0/ofs_rdy_r0 ),
        .ofs_rdy_r_reg(\maint_controller.maint_wip_r_lcl_reg ),
        .ofs_rdy_r_reg_0(rd_wr_r_lcl_reg[2]),
        .ofs_rdy_r_reg_1(rd_wr_r_lcl_reg[1]),
        .ofs_rdy_r_reg_2(rd_wr_r_lcl_reg[0]),
        .\order_q_r_reg[0] (\bank_cntrl[1].bank0_n_22 ),
        .\order_q_r_reg[0]_0 (\bank_cntrl[2].bank0_n_22 ),
        .\order_q_r_reg[0]_1 (\bank_cntrl[3].bank0_n_21 ),
        .ordered_r_lcl_reg(\bank_cntrl[0].bank0_n_42 ),
        .ordered_r_lcl_reg_0(\bank_cntrl[0].bank0_n_44 ),
        .override_demand_ns(override_demand_ns),
        .override_demand_r(override_demand_r),
        .p_9_in(p_9_in),
        .pass_open_bank_r_lcl_reg(pass_open_bank_r_lcl_reg_0),
        .pass_open_bank_r_lcl_reg_0(pass_open_bank_r_lcl_reg_1),
        .pass_open_bank_r_lcl_reg_1(periodic_rd_cntr_r),
        .pass_open_bank_r_lcl_reg_2(maint_wip_r),
        .periodic_rd_insert(periodic_rd_insert),
        .phy_mc_cmd_full_r_reg(ofs_rdy_r_reg),
        .phy_mc_ctl_full(phy_mc_ctl_full),
        .phy_mc_ctl_full_r_reg(periodic_rd_cntr_r_reg),
        .phy_mc_data_full(phy_mc_data_full),
        .pre_bm_end_r_reg(p_130_out),
        .pre_bm_end_r_reg_0(sending_pre[0]),
        .pre_passing_open_bank_r_reg(pre_passing_open_bank_r_reg),
        .pre_wait_r_reg(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1] ),
        .pre_wait_r_reg_0(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ),
        .q_entry_ns(\bank_queue0/q_entry_ns ),
        .\q_entry_r_reg[0] (\q_entry_r_reg[0]_3 ),
        .\q_entry_r_reg[0]_0 (q_entry_r[0]),
        .\q_entry_r_reg[0]_1 (set_order_q_23),
        .\q_entry_r_reg[0]_2 (rb_hit_busy_r[3]),
        .\q_entry_r_reg[0]_3 (rb_hit_busy_r[1]),
        .\q_entry_r_reg[0]_4 (rb_hit_busy_r[2]),
        .\q_entry_r_reg[0]_5 (bank_common0_n_26),
        .\q_entry_r_reg[1] (q_entry_r[1]),
        .\q_entry_r_reg[1]_0 (pre_bm_end_r_reg_1),
        .\q_entry_r_reg[1]_1 (p_52_out),
        .\q_entry_r_reg[1]_2 (idle_r[1]),
        .\q_entry_r_reg[1]_3 (idle_r[2]),
        .\q_entry_r_reg[1]_4 (idle_r[3]),
        .\q_entry_r_reg[1]_5 (\bank_cntrl[2].bank0_n_33 ),
        .\q_entry_r_reg[1]_6 (periodic_rd_ack_r_lcl_reg),
        .\q_entry_r_reg[1]_7 (\bank_cntrl[1].bank0_n_41 ),
        .q_has_priority(q_has_priority),
        .q_has_priority_r_reg(bank_common0_n_25),
        .q_has_rd(q_has_rd),
        .q_has_rd_r_reg(q_has_rd_r_reg),
        .\ras_timer_r[1]_i_3 (\grant_r_reg[3] [0]),
        .\ras_timer_r_reg[0] (\bank_cntrl[2].bank0_n_43 ),
        .\ras_timer_r_reg[0]_0 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ),
        .\ras_timer_r_reg[0]_1 (pre_passing_open_bank_r_reg_0),
        .\ras_timer_r_reg[0]_2 (\ras_timer_r_reg[0]_0 ),
        .\ras_timer_r_reg[0]_3 (\bank_cntrl[3].bank0_n_29 ),
        .\ras_timer_r_reg[0]_4 (\bank_cntrl[2].bank0_n_31 ),
        .\ras_timer_r_reg[0]_5 (\bank_cntrl[1].bank0_n_43 ),
        .\ras_timer_r_reg[1] (\bank_cntrl[3].bank0_n_30 ),
        .\ras_timer_r_reg[1]_0 (\bank_cntrl[2].bank0_n_32 ),
        .\ras_timer_r_reg[1]_1 (\bank_cntrl[1].bank0_n_44 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[1] (\rb_hit_busies.rb_hit_busies_r_lcl_reg[1] ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_1 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] (\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1 (pass_open_bank_r_lcl_reg),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] (\bank_cntrl[0].bank0_n_39 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 (rb_hit_busy_r_reg_1),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 (auto_pre_r_lcl_reg),
        .rb_hit_busies_r(rb_hit_busies_r),
        .rb_hit_busy_r_reg(rb_hit_busy_r[0]),
        .rb_hit_busy_r_reg_0(\bank_cntrl[0].bank0_n_38 ),
        .rb_hit_busy_r_reg_1(\bank_cntrl[0].bank0_n_40 ),
        .rb_hit_busy_r_reg_2(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ),
        .rd_this_rank_r(rd_this_rank_r[0]),
        .rd_wr_r(rd_wr_r),
        .rd_wr_r_lcl_reg(\bank_cntrl[0].bank0_n_24 ),
        .rd_wr_r_lcl_reg_0(\bank_cntrl[0].bank0_n_43 ),
        .rd_wr_r_lcl_reg_1(\bank_cntrl[0].bank0_n_46 ),
        .rd_wr_r_lcl_reg_2(rd_wr_r_lcl_reg_0),
        .\req_bank_r_lcl_reg[2] (\req_bank_r_lcl_reg[2] ),
        .\req_bank_r_lcl_reg[2]_0 (\req_bank_r_lcl_reg[2]_3 ),
        .req_bank_rdy_ns(\bank_state0/req_bank_rdy_ns_14 ),
        .req_bank_rdy_r_reg(req_bank_rdy_r_reg),
        .req_bank_rdy_r_reg_0(req_bank_rdy_r_reg_0),
        .req_bank_rdy_r_reg_1(req_bank_rdy_r_reg_1),
        .\req_col_r_reg[9] (\bank_compare0/req_col_r ),
        .\req_col_r_reg[9]_0 (\req_col_r_reg[9] ),
        .\req_data_buf_addr_r_reg[3] (req_data_buf_addr_r[3:0]),
        .\req_data_buf_addr_r_reg[3]_0 (\req_data_buf_addr_r_reg[3] ),
        .req_periodic_rd_r(req_periodic_rd_r[0]),
        .\req_row_r_lcl_reg[13] ({\req_row_r_lcl_reg[13] [10:9],req_row_r[11:9],\req_row_r_lcl_reg[13] [8:0]}),
        .\req_row_r_lcl_reg[13]_0 (\req_row_r_lcl_reg[13]_0 ),
        .req_wr_r_lcl0(\bank_compare0/req_wr_r_lcl0 ),
        .\rnk_config_strobe_r_reg[0] (\bank_cntrl[3].bank0_n_62 ),
        .rnk_config_valid_r(rnk_config_valid_r),
        .rnk_config_valid_r_lcl_reg(rnk_config_valid_r_lcl_reg),
        .row_hit_r_reg(row_hit_r_reg_0),
        .row_hit_r_reg_0(row_hit_r_reg_3),
        .\rtp_timer_r_reg[0] (\rtp_timer_r_reg[0] ),
        .\rtp_timer_r_reg[1] (\rtp_timer_r_reg[1] ),
        .tail_r(tail_r),
        .use_addr(use_addr),
        .wait_for_maint_r(wait_for_maint_r),
        .wait_for_maint_r_lcl_reg(\maint_controller.maint_wip_r_lcl_reg_0 ),
        .wait_for_maint_r_lcl_reg_0(wait_for_maint_r_lcl_reg),
        .wr_this_rank_r(wr_this_rank_r[0]));
  mig_mig_7series_v4_2_bank_cntrl__parameterized0 \bank_cntrl[1].bank0 
       (.E(idle_r[1]),
        .Q(Q[2:1]),
        .act_this_rank_r(act_this_rank_r[1]),
        .act_wait_r_lcl_reg(row_cmd_wr[1]),
        .act_wait_r_lcl_reg_0(act_wait_r_lcl_reg_0),
        .act_wait_r_lcl_reg_1(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1] ),
        .act_wait_r_lcl_reg_2(\grant_r_reg[3] [1]),
        .auto_pre_r_lcl_reg(auto_pre_r_19),
        .auto_pre_r_lcl_reg_0(\bank_cntrl[1].bank0_n_47 ),
        .auto_pre_r_lcl_reg_1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ),
        .auto_pre_r_lcl_reg_2(auto_pre_r_lcl_reg_1),
        .auto_pre_r_lcl_reg_3(accept_r_reg),
        .bm_end_r1(bm_end_r1),
        .bm_end_r1_reg(\bank_cntrl[1].bank0_n_43 ),
        .col_wait_r_reg(col_wait_r_0),
        .col_wait_r_reg_0(col_wait_r_reg_0),
        .\compute_tail.tail_r_lcl_reg (\compute_tail.tail_r_lcl_reg_2 ),
        .\compute_tail.tail_r_lcl_reg_0 (\compute_tail.tail_r_lcl_reg_4 ),
        .demand_priority_r_reg(demand_priority_r_1),
        .demand_priority_r_reg_0(\bank_cntrl[1].bank0_n_36 ),
        .demand_priority_r_reg_1(\maint_controller.maint_wip_r_lcl_reg ),
        .demand_priority_r_reg_2(arb_mux0_n_118),
        .demanded_prior_r_reg(demanded_prior_r_2),
        .demanded_prior_r_reg_0(demanded_prior_r_reg),
        .demanded_prior_r_reg_1(demanded_prior_r_6),
        .demanded_prior_r_reg_2(demand_priority_r_5),
        .demanded_prior_r_reg_3(demanded_prior_r_reg_0),
        .\grant_r[3]_i_2 (arb_mux0_n_38),
        .\grant_r[3]_i_2_0 (\bank_cntrl[0].bank0_n_46 ),
        .\grant_r[3]_i_2_1 (req_bank_rdy_r_reg),
        .\grant_r[3]_i_2_2 (arb_mux0_n_104),
        .\grant_r[3]_i_2_3 (\bank_cntrl[2].bank0_n_40 ),
        .granted_col_ns(\arb_row_col0/granted_col_ns ),
        .granted_col_r_reg(\bank_cntrl[2].bank0_n_29 ),
        .granted_col_r_reg_0(\bank_cntrl[3].bank0_n_27 ),
        .granted_col_r_reg_1(\bank_cntrl[0].bank0_n_24 ),
        .granted_col_r_reg_2(arb_mux0_n_120),
        .granted_col_r_reg_3(granted_col_r_reg_5),
        .granted_col_r_reg_4(arb_mux0_n_119),
        .head_r_lcl_reg(head_r[1]),
        .head_r_lcl_reg_0(head_r_lcl_reg_0),
        .head_r_lcl_reg_1(\bank_cntrl[0].bank0_n_38 ),
        .head_r_lcl_reg_2(\bank_cntrl[0].bank0_n_40 ),
        .head_r_lcl_reg_3(bank_common0_n_17),
        .hi_priority(hi_priority),
        .i___34(p_52_out),
        .i___34_0(p_130_out),
        .i___34_1(pre_bm_end_r_reg),
        .idle_r_lcl_reg(idle_r_lcl_reg),
        .maint_req_r(maint_req_r),
        .ofs_rdy_r(\bank_state0/ofs_rdy_r_5 ),
        .ofs_rdy_r0(\bank_state0/ofs_rdy_r0 ),
        .ofs_rdy_r_reg(ofs_rdy_r_reg),
        .\order_q_r_reg[0] (\bank_cntrl[0].bank0_n_42 ),
        .\order_q_r_reg[1] (set_order_q_24),
        .\order_q_r_reg[1]_0 (\bank_cntrl[0].bank0_n_44 ),
        .ordered_r_lcl_reg(\bank_cntrl[1].bank0_n_22 ),
        .pass_open_bank_r_lcl_reg(pass_open_bank_r),
        .pass_open_bank_r_lcl_reg_0(rb_hit_busy_r_reg),
        .pass_open_bank_r_lcl_reg_1(periodic_rd_cntr_r),
        .pass_open_bank_r_lcl_reg_2(maint_wip_r),
        .periodic_rd_insert(periodic_rd_insert),
        .pre_bm_end_r(pre_bm_end_r),
        .pre_bm_end_r_reg(pre_bm_end_r_reg_1),
        .pre_bm_end_r_reg_0(sending_pre[1]),
        .pre_passing_open_bank_r_reg(pre_passing_open_bank_r_reg_0),
        .q_entry_ns(\bank_queue0/q_entry_ns ),
        .\q_entry_r_reg[0] (\q_entry_r_reg[0]_4 ),
        .\q_entry_r_reg[0]_0 (\q_entry_r_reg[0]_5 ),
        .\q_entry_r_reg[0]_1 (\bank_cntrl[0].bank0_n_49 ),
        .\q_entry_r_reg[0]_2 (periodic_rd_ack_r_lcl_reg),
        .\q_entry_r_reg[1] (\q_entry_r_reg[1]_1 ),
        .\q_entry_r_reg[1]_0 (\bank_cntrl[1].bank0_n_41 ),
        .\q_entry_r_reg[1]_1 (\q_entry_r_reg[1]_3 ),
        .q_has_priority(q_has_priority_4),
        .q_has_priority_r_reg(bank_common0_n_30),
        .q_has_rd_3(q_has_rd_3),
        .q_has_rd_r_reg(q_has_rd_r_reg_0),
        .\ras_timer_r_reg[0] (\ras_timer_r_reg[0]_2 ),
        .\ras_timer_r_reg[0]_0 (pre_passing_open_bank_r_reg),
        .\ras_timer_r_reg[0]_1 (\bank_cntrl[3].bank0_n_38 ),
        .\ras_timer_r_reg[0]_2 (\bank_cntrl[2].bank0_n_43 ),
        .\ras_timer_r_reg[0]_3 (\bank_cntrl[0].bank0_n_26 ),
        .\ras_timer_r_reg[0]_4 (\bank_cntrl[2].bank0_n_31 ),
        .\ras_timer_r_reg[0]_5 (\bank_cntrl[3].bank0_n_29 ),
        .\ras_timer_r_reg[1] (\bank_cntrl[1].bank0_n_44 ),
        .\ras_timer_r_reg[1]_0 (\bank_cntrl[0].bank0_n_27 ),
        .\ras_timer_r_reg[1]_1 (\bank_cntrl[3].bank0_n_30 ),
        .\ras_timer_r_reg[1]_2 (\bank_cntrl[2].bank0_n_32 ),
        .ras_timer_zero_r_reg(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ),
        .ras_timer_zero_r_reg_0(ras_timer_zero_r_reg),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] (\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1 (idle_r_lcl_reg_1),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_2 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_3 (pass_open_bank_r_lcl_reg),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] (rb_hit_busies_r_3),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 (idle_r_lcl_reg_0),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 (rb_hit_busy_r_reg_1),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2 (auto_pre_r_lcl_reg),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] (idle_r_lcl_reg_2),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 (pass_open_bank_r_lcl_reg_0),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] (\bank_cntrl[1].bank0_n_30 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ),
        .rb_hit_busies_r(rb_hit_busies_r_11[5]),
        .rb_hit_busies_r_0(rb_hit_busies_r_7[5]),
        .rb_hit_busy_r_reg(rb_hit_busy_r[1]),
        .rb_hit_busy_r_reg_0(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1 ),
        .rb_hit_busy_r_reg_1(periodic_rd_ack_r),
        .rb_hit_busy_r_reg_2(accept_internal_r),
        .rd_this_rank_r(rd_this_rank_r[1]),
        .rd_wr_r_lcl_reg(rd_wr_r_lcl_reg[0]),
        .rd_wr_r_lcl_reg_0(\bank_cntrl[1].bank0_n_26 ),
        .rd_wr_r_lcl_reg_1(rd_wr_r_lcl_reg_0),
        .\req_bank_r_lcl_reg[2] (\req_bank_r_lcl_reg[2]_0 ),
        .\req_bank_r_lcl_reg[2]_0 (\req_bank_r_lcl_reg[2]_3 ),
        .req_bank_rdy_ns(req_bank_rdy_ns),
        .req_bank_rdy_ns_1(\bank_state0/req_bank_rdy_ns ),
        .req_bank_rdy_r(\bank_state0/req_bank_rdy_r ),
        .req_bank_rdy_r_reg(\bank_cntrl[0].bank0_n_43 ),
        .\req_col_r_reg[9] (\bank_compare0/req_col_r_2 ),
        .\req_col_r_reg[9]_0 (\req_col_r_reg[9] ),
        .\req_data_buf_addr_r_reg[3] (req_data_buf_addr_r[8:5]),
        .\req_data_buf_addr_r_reg[3]_0 (\req_data_buf_addr_r_reg[3] ),
        .req_periodic_rd_r(req_periodic_rd_r[1]),
        .\req_row_r_lcl_reg[13] ({\req_row_r_lcl_reg[13] [15:11],req_row_r[22:14]}),
        .\req_row_r_lcl_reg[13]_0 (\req_row_r_lcl_reg[13]_0 ),
        .req_wr_r_lcl0(\bank_compare0/req_wr_r_lcl0 ),
        .req_wr_r_lcl_reg(req_wr_r_lcl_reg[0]),
        .rnk_config_strobe_ns(\arb_row_col0/rnk_config_strobe_ns ),
        .\rnk_config_strobe_r_reg[0] (arb_mux0_n_100),
        .\rnk_config_strobe_r_reg[0]_0 (demand_priority_r_reg),
        .\rnk_config_strobe_r_reg[0]_1 (rnk_config_valid_r_lcl_reg),
        .row_hit_r_reg(row_hit_r_reg),
        .row_hit_r_reg_0(row_hit_r_reg_4),
        .row_hit_r_reg_1(row_hit_r_reg_5),
        .\rtp_timer_r_reg[0] (\rtp_timer_r_reg[0] ),
        .\rtp_timer_r_reg[1] (\rtp_timer_r_reg[1] ),
        .\starve_limit_cntr_r_reg[0] (sent_col),
        .tail_r_16(tail_r_16),
        .use_addr(use_addr),
        .wait_for_maint_r_13(wait_for_maint_r_13),
        .wait_for_maint_r_lcl_reg(\maint_controller.maint_wip_r_lcl_reg_0 ),
        .wait_for_maint_r_lcl_reg_0(wait_for_maint_r_lcl_reg_0),
        .wr_this_rank_r(wr_this_rank_r[1]));
  mig_mig_7series_v4_2_bank_cntrl__parameterized1 \bank_cntrl[2].bank0 
       (.E(idle_r[2]),
        .Q(Q[2:1]),
        .act_this_rank_r(act_this_rank_r[2]),
        .act_wait_r_lcl_reg(row_cmd_wr[2]),
        .act_wait_r_lcl_reg_0(\bank_cntrl[2].bank0_n_47 ),
        .act_wait_r_lcl_reg_1(\bank_cntrl[2].bank0_n_64 ),
        .act_wait_r_lcl_reg_2(\grant_r_reg[3] [2]),
        .auto_pre_r_lcl_reg(auto_pre_r_20),
        .auto_pre_r_lcl_reg_0(\bank_cntrl[2].bank0_n_48 ),
        .auto_pre_r_lcl_reg_1(auto_pre_r_lcl_reg_2),
        .auto_pre_r_lcl_reg_2(accept_r_reg),
        .bm_end_r1_0(bm_end_r1_0),
        .bm_end_r1_reg(\bank_cntrl[2].bank0_n_31 ),
        .\cmd_pipe_plus.mc_address_reg[38] (\req_row_r_lcl_reg[13] [12]),
        .col_wait_r_reg(col_wait_r_4),
        .col_wait_r_reg_0(col_wait_r_reg_1),
        .\compute_tail.tail_r_lcl_reg (\compute_tail.tail_r_lcl_reg_1 ),
        .\compute_tail.tail_r_lcl_reg_0 (\compute_tail.tail_r_lcl_reg_5 ),
        .demand_priority_r_1(demand_priority_r_1),
        .demand_priority_r_reg(demand_priority_r_5),
        .demand_priority_r_reg_0(demand_priority_r_reg),
        .demand_priority_r_reg_1(sent_col),
        .demanded_prior_r_2(demanded_prior_r_2),
        .demanded_prior_r_reg(demanded_prior_r_6),
        .demanded_prior_r_reg_0(demanded_prior_r_reg_0),
        .\grant_r[3]_i_3 (arb_mux0_n_38),
        .\grant_r[3]_i_3_0 (\bank_cntrl[0].bank0_n_46 ),
        .\grant_r[3]_i_3_1 (req_bank_rdy_r_reg),
        .\grant_r[3]_i_3_2 (arb_mux0_n_101),
        .\grant_r[3]_i_6 (rb_hit_busies_r_3[2]),
        .granted_col_r_reg(granted_col_r_reg_3),
        .granted_col_r_reg_0(arb_mux0_n_120),
        .granted_col_r_reg_1(granted_col_r_reg_4),
        .granted_col_r_reg_2(arb_mux0_n_119),
        .head_r_lcl_reg(head_r[2]),
        .head_r_lcl_reg_0(head_r_lcl_reg_1),
        .head_r_lcl_reg_1(\bank_cntrl[0].bank0_n_40 ),
        .head_r_lcl_reg_2(\bank_cntrl[0].bank0_n_38 ),
        .head_r_lcl_reg_3(bank_common0_n_13),
        .hi_priority(hi_priority),
        .i___5_i_4(pre_bm_end_r_reg_1),
        .i___5_i_4_0(p_130_out),
        .i___5_i_4_1(pre_bm_end_r_reg),
        .idle_r_lcl_reg(idle_r_lcl_reg_1),
        .idle_r_lcl_reg_0(idle_r_lcl_reg_3),
        .maint_req_r(maint_req_r),
        .ofs_rdy_r(\bank_state0/ofs_rdy_r_9 ),
        .ofs_rdy_r0(\bank_state0/ofs_rdy_r0_0 ),
        .ofs_rdy_r_reg(\maint_controller.maint_wip_r_lcl_reg ),
        .ofs_rdy_r_reg_0(ofs_rdy_r_reg),
        .\order_q_r_reg[0] (\bank_cntrl[0].bank0_n_42 ),
        .\order_q_r_reg[1] (\order_q_r_reg[1] ),
        .\order_q_r_reg[1]_0 (set_order_q_22),
        .\order_q_r_reg[1]_1 (\bank_cntrl[0].bank0_n_44 ),
        .ordered_r_lcl_reg(\bank_cntrl[2].bank0_n_22 ),
        .override_demand_ns(override_demand_ns),
        .override_demand_r(override_demand_r),
        .pass_open_bank_r_lcl_reg(pass_open_bank_r_lcl_reg),
        .pass_open_bank_r_lcl_reg_0(rb_hit_busy_r_reg_0),
        .pass_open_bank_r_lcl_reg_1(periodic_rd_cntr_r),
        .pass_open_bank_r_lcl_reg_2(maint_wip_r),
        .periodic_rd_insert(periodic_rd_insert),
        .\pre_4_1_1T_arb.granted_pre_r_reg (\bank_cntrl[1].bank0_n_47 ),
        .pre_bm_end_r_reg(p_52_out),
        .pre_bm_end_r_reg_0(sending_pre[2:1]),
        .pre_passing_open_bank_r_reg(\bank_cntrl[2].bank0_n_43 ),
        .pre_wait_r_reg(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1] ),
        .\q_entry_r_reg[0] (\q_entry_r_reg[0]_1 ),
        .\q_entry_r_reg[0]_0 (\q_entry_r_reg[0]_2 ),
        .\q_entry_r_reg[0]_1 (\q_entry_r_reg[0]_6 ),
        .\q_entry_r_reg[1] (\bank_cntrl[2].bank0_n_33 ),
        .\q_entry_r_reg[1]_0 (\q_entry_r_reg[1]_0 ),
        .\q_entry_r_reg[1]_1 (periodic_rd_ack_r_lcl_reg),
        .\q_entry_r_reg[1]_2 (\bank_cntrl[0].bank0_n_29 ),
        .\q_entry_r_reg[1]_3 (\bank_cntrl[0].bank0_n_30 ),
        .q_has_priority(q_has_priority_8),
        .q_has_priority_r_reg(bank_common0_n_28),
        .q_has_rd_7(q_has_rd_7),
        .q_has_rd_r_reg(q_has_rd_r_reg_1),
        .\ras_timer_r_reg[0] (\bank_cntrl[3].bank0_n_41 ),
        .\ras_timer_r_reg[0]_0 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ),
        .\ras_timer_r_reg[0]_1 (pre_passing_open_bank_r_reg),
        .\ras_timer_r_reg[0]_2 (\ras_timer_r_reg[0]_1 ),
        .\ras_timer_r_reg[0]_3 (\bank_cntrl[1].bank0_n_43 ),
        .\ras_timer_r_reg[0]_4 (\bank_cntrl[0].bank0_n_26 ),
        .\ras_timer_r_reg[0]_5 (\bank_cntrl[3].bank0_n_29 ),
        .\ras_timer_r_reg[1] (\bank_cntrl[2].bank0_n_32 ),
        .\ras_timer_r_reg[1]_0 (\bank_cntrl[1].bank0_n_44 ),
        .\ras_timer_r_reg[1]_1 (\bank_cntrl[0].bank0_n_27 ),
        .\ras_timer_r_reg[1]_2 (\bank_cntrl[3].bank0_n_30 ),
        .ras_timer_zero_r_reg(\bank_cntrl[2].bank0_n_46 ),
        .ras_timer_zero_r_reg_0(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ),
        .ras_timer_zero_r_reg_1(ras_timer_zero_r_reg_0),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] (\bank_cntrl[2].bank0_n_40 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_2 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] (\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 (idle_r_lcl_reg_0),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 (rb_hit_busy_r_reg_1),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2 (auto_pre_r_lcl_reg),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] (\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 (idle_r_lcl_reg_2),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 (pass_open_bank_r_lcl_reg_0),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] (\bank_cntrl[2].bank0_n_34 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 (idle_r_lcl_reg),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_2 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[6] (\bank_cntrl[2].bank0_n_41 ),
        .rb_hit_busies_r({rb_hit_busies_r_7[5],rb_hit_busies_r_7[3]}),
        .rb_hit_busies_r_0(rb_hit_busies_r_11[6]),
        .rb_hit_busies_r_1(rb_hit_busies_r[2]),
        .rb_hit_busy_r_reg(rb_hit_busy_r[2]),
        .rb_hit_busy_r_reg_0(\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0 ),
        .rb_hit_busy_r_reg_1(periodic_rd_ack_r),
        .rb_hit_busy_r_reg_2(accept_internal_r),
        .rd_this_rank_r(rd_this_rank_r[2]),
        .rd_wr_r_lcl_reg(rd_wr_r_lcl_reg[1]),
        .rd_wr_r_lcl_reg_0(\bank_cntrl[2].bank0_n_29 ),
        .rd_wr_r_lcl_reg_1(rd_wr_r_lcl_reg_0),
        .\req_bank_r_lcl_reg[2] (\req_bank_r_lcl_reg[2]_1 ),
        .\req_bank_r_lcl_reg[2]_0 (\req_bank_r_lcl_reg[2]_3 ),
        .req_bank_rdy_ns(\bank_state0/req_bank_rdy_ns ),
        .req_bank_rdy_r_reg(\bank_cntrl[0].bank0_n_43 ),
        .\req_col_r_reg[9] (\bank_compare0/req_col_r_6 ),
        .\req_col_r_reg[9]_0 (\req_col_r_reg[9] ),
        .\req_data_buf_addr_r_reg[3] (req_data_buf_addr_r[13:10]),
        .\req_data_buf_addr_r_reg[3]_0 (\req_data_buf_addr_r_reg[3] ),
        .req_periodic_rd_r(req_periodic_rd_r[2]),
        .\req_row_r_lcl_reg[13] ({\req_row_r_lcl_reg[13] [17:16],req_row_r[39:28]}),
        .\req_row_r_lcl_reg[13]_0 (\req_row_r_lcl_reg[13]_0 ),
        .req_wr_r_lcl0(\bank_compare0/req_wr_r_lcl0 ),
        .req_wr_r_lcl_reg(req_wr_r_lcl_reg[1]),
        .rnk_config_valid_r_lcl_reg(\bank_cntrl[1].bank0_n_36 ),
        .rnk_config_valid_r_lcl_reg_0(arb_mux0_n_100),
        .row_cmd_wr(row_cmd_wr[1]),
        .row_hit_r_reg(row_hit_r_reg_1),
        .row_hit_r_reg_0(row_hit_r_reg_6),
        .\rtp_timer_r_reg[0] (\rtp_timer_r_reg[0] ),
        .tail_r_17(tail_r_17),
        .use_addr(use_addr),
        .wait_for_maint_r_14(wait_for_maint_r_14),
        .wait_for_maint_r_lcl_reg(\maint_controller.maint_wip_r_lcl_reg_0 ),
        .wait_for_maint_r_lcl_reg_0(wait_for_maint_r_lcl_reg_1),
        .wr_this_rank_r(wr_this_rank_r[2]));
  mig_mig_7series_v4_2_bank_cntrl__parameterized2 \bank_cntrl[3].bank0 
       (.E(idle_r[3]),
        .Q({Q[3],Q[0]}),
        .act_this_rank_r(act_this_rank_r[3]),
        .act_wait_r_lcl_reg(row_cmd_wr[3]),
        .act_wait_r_lcl_reg_0(act_wait_r_lcl_reg_1),
        .act_wait_r_lcl_reg_1(\bank_cntrl[3].bank0_n_61 ),
        .act_wait_r_lcl_reg_2(\grant_r_reg[3] [3:2]),
        .auto_pre_r_lcl_reg(auto_pre_r_21),
        .auto_pre_r_lcl_reg_0(\bank_cntrl[3].bank0_n_46 ),
        .auto_pre_r_lcl_reg_1(auto_pre_r_lcl_reg),
        .auto_pre_r_lcl_reg_2(auto_pre_r_lcl_reg_3),
        .auto_pre_r_lcl_reg_3(accept_r_reg),
        .bm_end_r1_1(bm_end_r1_1),
        .bm_end_r1_reg(\bank_cntrl[3].bank0_n_29 ),
        .\cmd_pipe_plus.mc_address[10]_i_2 (req_row_r[38]),
        .col_wait_r_reg(col_wait_r_8),
        .col_wait_r_reg_0(col_wait_r_reg_2),
        .\compute_tail.tail_r_lcl_reg (\compute_tail.tail_r_lcl_reg ),
        .\compute_tail.tail_r_lcl_reg_0 (\compute_tail.tail_r_lcl_reg_6 ),
        .\compute_tail.tail_r_lcl_reg_1 (pre_bm_end_r_reg_1),
        .\compute_tail.tail_r_lcl_reg_2 (p_130_out),
        .\compute_tail.tail_r_lcl_reg_3 (p_52_out),
        .demand_priority_r(demand_priority_r),
        .demand_priority_r_reg(demand_priority_r_9),
        .demand_priority_r_reg_0(\bank_cntrl[3].bank0_n_62 ),
        .demand_priority_r_reg_1(\maint_controller.maint_wip_r_lcl_reg ),
        .demand_priority_r_reg_2(sent_col),
        .demanded_prior_r(demanded_prior_r),
        .demanded_prior_r_0(\bank_state0/demanded_prior_r ),
        .demanded_prior_r_reg(demanded_prior_r_reg),
        .\grant_r[3]_i_5 (\bank_cntrl[2].bank0_n_41 ),
        .\grant_r[3]_i_5_0 (arb_mux0_n_38),
        .\grant_r[3]_i_5_1 (\bank_cntrl[0].bank0_n_46 ),
        .\grant_r[3]_i_5_2 (req_bank_rdy_r_reg),
        .\grant_r[3]_i_5_3 (arb_mux0_n_103),
        .\grant_r[3]_i_6 (rb_hit_busies_r_3[3]),
        .\grant_r_reg[3] (\bank_cntrl[3].bank0_n_63 ),
        .granted_col_r_reg(arb_mux0_n_120),
        .granted_col_r_reg_0(granted_col_r_reg_2),
        .granted_col_r_reg_1(arb_mux0_n_119),
        .head_r_lcl_reg(head_r[3]),
        .head_r_lcl_reg_0(head_r_lcl_reg_2),
        .head_r_lcl_reg_1(\bank_cntrl[0].bank0_n_38 ),
        .head_r_lcl_reg_2(bank_common0_n_11),
        .head_r_lcl_reg_3(\bank_cntrl[0].bank0_n_40 ),
        .hi_priority(hi_priority),
        .idle_r_lcl_reg(idle_r_lcl_reg_0),
        .maint_req_r(maint_req_r),
        .ofs_rdy_r(\bank_state0/ofs_rdy_r_13 ),
        .ofs_rdy_r0(\bank_state0/ofs_rdy_r0_1 ),
        .ofs_rdy_r_reg(ofs_rdy_r_reg),
        .\order_q_r_reg[0] (\bank_cntrl[0].bank0_n_42 ),
        .\order_q_r_reg[1] (set_order_q),
        .\order_q_r_reg[1]_0 (\bank_cntrl[0].bank0_n_44 ),
        .ordered_r_lcl_reg(\bank_cntrl[3].bank0_n_21 ),
        .pass_open_bank_r_lcl_reg(pass_open_bank_r_10),
        .pass_open_bank_r_lcl_reg_0(pass_open_bank_r_lcl_reg_2),
        .pass_open_bank_r_lcl_reg_1(periodic_rd_cntr_r),
        .pass_open_bank_r_lcl_reg_2(maint_wip_r),
        .periodic_rd_insert(periodic_rd_insert),
        .\pre_4_1_1T_arb.granted_pre_ns (\arb_row_col0/pre_4_1_1T_arb.granted_pre_ns ),
        .\pre_4_1_1T_arb.granted_pre_r_reg (\bank_cntrl[0].bank0_n_53 ),
        .\pre_4_1_1T_arb.granted_pre_r_reg_0 (\bank_cntrl[2].bank0_n_46 ),
        .pre_bm_end_r_11(pre_bm_end_r_11),
        .pre_bm_end_r_reg(pre_bm_end_r_reg),
        .pre_bm_end_r_reg_0(pre_bm_end_r_reg_0),
        .pre_bm_end_r_reg_1(pre_bm_end_r_reg_2),
        .pre_bm_end_r_reg_2(\grant_r_reg[3]_0 ),
        .pre_passing_open_bank_r_reg(\bank_cntrl[3].bank0_n_41 ),
        .pre_wait_r_reg(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1] ),
        .\q_entry_r_reg[0] (\q_entry_r_reg[0] ),
        .\q_entry_r_reg[0]_0 (\q_entry_r_reg[0]_0 ),
        .\q_entry_r_reg[0]_1 (\bank_cntrl[0].bank0_n_33 ),
        .\q_entry_r_reg[1] (\q_entry_r_reg[1] ),
        .\q_entry_r_reg[1]_0 (\bank_cntrl[0].bank0_n_28 ),
        .\q_entry_r_reg[1]_1 (\q_entry_r_reg[1]_2 ),
        .\q_entry_r_reg[1]_2 (\bank_cntrl[0].bank0_n_34 ),
        .\q_entry_r_reg[1]_3 (periodic_rd_ack_r_lcl_reg),
        .\q_entry_r_reg[1]_4 (\q_entry_r_reg[1]_4 ),
        .q_has_priority(q_has_priority_12),
        .q_has_priority_r_reg(bank_common0_n_24),
        .q_has_rd_12(q_has_rd_12),
        .q_has_rd_r_reg(q_has_rd_r_reg_2),
        .\ras_timer_r_reg[0] (\ras_timer_r_reg[0] ),
        .\ras_timer_r_reg[0]_0 (pre_passing_open_bank_r_reg),
        .\ras_timer_r_reg[0]_1 (\bank_cntrl[1].bank0_n_30 ),
        .\ras_timer_r_reg[0]_2 (\bank_cntrl[2].bank0_n_43 ),
        .\ras_timer_r_reg[0]_3 (\bank_cntrl[2].bank0_n_31 ),
        .\ras_timer_r_reg[0]_4 (\bank_cntrl[1].bank0_n_43 ),
        .\ras_timer_r_reg[0]_5 (\bank_cntrl[0].bank0_n_26 ),
        .\ras_timer_r_reg[0]_6 (\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ),
        .\ras_timer_r_reg[1] (\bank_cntrl[3].bank0_n_30 ),
        .\ras_timer_r_reg[1]_0 (\bank_cntrl[2].bank0_n_32 ),
        .\ras_timer_r_reg[1]_1 (\bank_cntrl[1].bank0_n_44 ),
        .\ras_timer_r_reg[1]_2 (\bank_cntrl[0].bank0_n_27 ),
        .ras_timer_zero_r_reg(ras_timer_zero_r_reg_1),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] (\bank_cntrl[3].bank0_n_38 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] (\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 (idle_r_lcl_reg_2),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 (pass_open_bank_r_lcl_reg_0),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] (idle_r_lcl_reg),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[6] (rb_hit_busies_r_11),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[6] ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_1 (idle_r_lcl_reg_1),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_2 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0 ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_3 (pass_open_bank_r_lcl_reg),
        .rb_hit_busies_r(rb_hit_busies_r[3]),
        .rb_hit_busies_r_1(rb_hit_busies_r_7[3]),
        .rb_hit_busy_r_reg(rb_hit_busy_r[3]),
        .rb_hit_busy_r_reg_0(rb_hit_busy_r_reg_1),
        .rb_hit_busy_r_reg_1(periodic_rd_ack_r),
        .rb_hit_busy_r_reg_2(accept_internal_r),
        .rd_this_rank_r(rd_this_rank_r[3]),
        .rd_wr_r_lcl_reg(rd_wr_r_lcl_reg[2]),
        .rd_wr_r_lcl_reg_0(\bank_cntrl[3].bank0_n_27 ),
        .rd_wr_r_lcl_reg_1(rd_wr_r_lcl_reg_0),
        .\req_bank_r_lcl_reg[2] (\req_bank_r_lcl_reg[2]_2 ),
        .\req_bank_r_lcl_reg[2]_0 (\req_bank_r_lcl_reg[2]_3 ),
        .req_bank_rdy_ns(\bank_state0/req_bank_rdy_ns_14 ),
        .req_bank_rdy_r_reg(\bank_cntrl[0].bank0_n_43 ),
        .\req_col_r_reg[9] (\bank_compare0/req_col_r_10 ),
        .\req_col_r_reg[9]_0 (\req_col_r_reg[9] ),
        .\req_data_buf_addr_r_reg[3] (req_data_buf_addr_r[18:15]),
        .\req_data_buf_addr_r_reg[3]_0 (\req_data_buf_addr_r_reg[3] ),
        .req_periodic_rd_r(req_periodic_rd_r[3]),
        .\req_row_r_lcl_reg[13] ({\req_row_r_lcl_reg[13] [19:18],req_row_r[53:42]}),
        .\req_row_r_lcl_reg[13]_0 (\req_row_r_lcl_reg[13]_0 ),
        .req_wr_r_lcl0(\bank_compare0/req_wr_r_lcl0 ),
        .req_wr_r_lcl_reg(req_wr_r_lcl_reg[2]),
        .row_cmd_wr(row_cmd_wr[2]),
        .row_hit_r_reg(row_hit_r_reg_2),
        .row_hit_r_reg_0(row_hit_r_reg_7),
        .\rtp_timer_r_reg[0] (\rtp_timer_r_reg[0] ),
        .tail_r_18(tail_r_18),
        .use_addr(use_addr),
        .wait_for_maint_r_15(wait_for_maint_r_15),
        .wait_for_maint_r_lcl_reg(\maint_controller.maint_wip_r_lcl_reg_0 ),
        .wait_for_maint_r_lcl_reg_0(wait_for_maint_r_lcl_reg_2),
        .wr_this_rank_r(wr_this_rank_r[3]));
  mig_mig_7series_v4_2_bank_common bank_common0
       (.E(idle_r[3]),
        .Q(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] ),
        .accept_internal_r_reg_0(accept_internal_r),
        .accept_ns(accept_ns),
        .accept_r_reg_0(accept_r_reg),
        .accept_r_reg_1(bank_common0_n_11),
        .accept_r_reg_2(bank_common0_n_13),
        .accept_r_reg_3(bank_common0_n_15),
        .accept_r_reg_4(bank_common0_n_17),
        .clear_periodic_rd_request(clear_periodic_rd_request),
        .cmd(cmd),
        .\generate_maint_cmds.insert_maint_r_lcl_reg_0 (\generate_maint_cmds.insert_maint_r_lcl_reg ),
        .head_r(head_r),
        .hi_priority(hi_priority),
        .i___3_i_2(\bank_cntrl[0].bank0_n_39 ),
        .i___4_i_1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ),
        .i___5_i_1(\bank_cntrl[2].bank0_n_34 ),
        .i___6_i_1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ),
        .idle_r_lcl_reg(bank_common0_n_26),
        .\maint_controller.maint_hit_busies_r_reg[3]_0 (\maint_controller.maint_hit_busies_r_reg[3] ),
        .\maint_controller.maint_hit_busies_r_reg[3]_1 (\maint_controller.maint_hit_busies_r_reg[3]_0 ),
        .\maint_controller.maint_wip_r_lcl_reg_0 (maint_wip_r),
        .\maint_controller.maint_wip_r_lcl_reg_1 (\maint_controller.maint_wip_r_lcl_reg ),
        .\maint_controller.maint_wip_r_lcl_reg_2 (\maint_controller.maint_wip_r_lcl_reg_0 ),
        .\maint_controller.maint_wip_r_lcl_reg_3 (\maint_controller.maint_wip_r_lcl_reg_1 ),
        .maint_req_r(maint_req_r),
        .maint_srx_r(maint_srx_r),
        .maint_zq_r(maint_zq_r),
        .p_9_in(p_9_in),
        .periodic_rd_ack_r_lcl_reg_0(periodic_rd_ack_r),
        .periodic_rd_ack_r_lcl_reg_1(periodic_rd_ack_r_lcl_reg),
        .periodic_rd_cntr_r_reg_0(periodic_rd_cntr_r),
        .periodic_rd_cntr_r_reg_1(periodic_rd_cntr_r_reg),
        .periodic_rd_cntr_r_reg_2(periodic_rd_cntr_r_reg_0),
        .periodic_rd_insert(periodic_rd_insert),
        .periodic_rd_r(periodic_rd_r),
        .\periodic_read_request.periodic_rd_grant_r (\periodic_read_request.periodic_rd_grant_r ),
        .\q_entry_r_reg[0] (idle_r[2]),
        .\q_entry_r_reg[0]_0 (idle_r[0]),
        .\q_entry_r_reg[0]_1 (idle_r[1]),
        .q_has_priority(q_has_priority_12),
        .q_has_priority_0(q_has_priority),
        .q_has_priority_1(q_has_priority_8),
        .q_has_priority_2(q_has_priority_4),
        .q_has_priority_r_reg(bank_common0_n_24),
        .q_has_priority_r_reg_0(bank_common0_n_25),
        .q_has_priority_r_reg_1(bank_common0_n_28),
        .q_has_priority_r_reg_2(bank_common0_n_30),
        .rb_hit_busy_r(rb_hit_busy_r),
        .rb_hit_busy_r_reg(rb_hit_busy_r_reg_0),
        .rb_hit_busy_r_reg_0(rb_hit_busy_r_reg),
        .req_wr_r_lcl0(\bank_compare0/req_wr_r_lcl0 ),
        .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 (\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ),
        .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1]_0 (\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1] ),
        .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_0 (\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_0 ),
        .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_1 (\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_1 ),
        .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]_0 (\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4] ),
        .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]_1 (\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]_0 ),
        .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_0 (\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] ),
        .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_1 (\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_0 ),
        .set_order_q(set_order_q),
        .set_order_q_22(set_order_q_22),
        .set_order_q_23(set_order_q_23),
        .set_order_q_24(set_order_q_24),
        .use_addr(use_addr),
        .was_priority_reg_0(was_priority_reg),
        .was_wr(was_wr));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_bank_queue" *) 
module mig_mig_7series_v4_2_bank_queue
   (idle_r_lcl_reg_0,
    E,
    pass_open_bank_r,
    pass_open_bank_ns,
    q_has_rd,
    q_has_priority,
    pass_open_bank_r_lcl_reg_0,
    wait_for_maint_r,
    tail_r,
    head_r_lcl_reg_0,
    ordered_r_lcl,
    auto_pre_r_lcl_reg_0,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0 ,
    idle_r_lcl_reg_1,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ,
    rd_wr_r_lcl_reg,
    D,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1 ,
    idle_r_lcl_reg_2,
    pre_bm_end_r_reg_0,
    idle_r_lcl_reg_3,
    idle_r_lcl_reg_4,
    q_entry_ns,
    p_9_in,
    idle_r_lcl_reg_5,
    idle_r_lcl_reg_6,
    \q_entry_r_reg[0]_0 ,
    \q_entry_r_reg[0]_1 ,
    \q_entry_r_reg[1]_0 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 ,
    idle_r_lcl_reg_7,
    ordered_r_lcl_reg_0,
    \order_q_r_reg[0]_0 ,
    req_bank_rdy_ns,
    p_145_out,
    pre_passing_open_bank_r_reg_0,
    idle_r_lcl_reg_8,
    act_wait_r_lcl_reg,
    \compute_tail.tail_r_lcl_reg_0 ,
    idle_r_lcl_reg_9,
    q_has_rd_r_reg_0,
    pre_bm_end_ns,
    pre_passing_open_bank_ns,
    q_has_rd_r_reg_1,
    q_has_priority_r_reg_0,
    wait_for_maint_r_lcl_reg_0,
    wait_for_maint_r_lcl_reg_1,
    head_r_lcl_reg_1,
    \compute_tail.tail_r_lcl_reg_1 ,
    head_r_lcl_reg_2,
    ordered_r_lcl_reg_1,
    auto_pre_r_lcl_reg_1,
    accept_internal_r_reg,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_1 ,
    accept_internal_r_reg_0,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2 ,
    accept_internal_r_reg_1,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_2 ,
    granted_col_r_reg,
    granted_col_r_reg_0,
    bm_end_r1_reg,
    granted_col_r_reg_1,
    granted_col_r_reg_2,
    \ras_timer_r_reg[0] ,
    \ras_timer_r_reg[1] ,
    \ras_timer_r_reg[0]_0 ,
    \ras_timer_r_reg[0]_1 ,
    \ras_timer_r_reg[0]_2 ,
    \ras_timer_r_reg[0]_3 ,
    \q_entry_r_reg[1]_1 ,
    \q_entry_r_reg[1]_2 ,
    \q_entry_r_reg[1]_3 ,
    \q_entry_r_reg[1]_4 ,
    \q_entry_r_reg[1]_5 ,
    \q_entry_r_reg[1]_6 ,
    \q_entry_r_reg[1]_7 ,
    \q_entry_r_reg[1]_8 ,
    accept_internal_r_reg_2,
    head_r_lcl_reg_3,
    \q_entry_r_reg[1]_9 ,
    \q_entry_r_reg[1]_10 ,
    \q_entry_r_reg[0]_2 ,
    \q_entry_r_reg[0]_3 ,
    \q_entry_r_reg[0]_4 ,
    \q_entry_r_reg[0]_5 ,
    \q_entry_r_reg[0]_6 ,
    i___3_i_4,
    \order_q_r_reg[0]_1 ,
    \order_q_r_reg[0]_2 ,
    \order_q_r_reg[0]_3 ,
    req_bank_rdy_r_reg,
    req_priority_r,
    req_bank_rdy_r_reg_0,
    \grant_r[2]_i_3_0 ,
    \grant_r[2]_i_3_1 ,
    \grant_r[2]_i_3_2 ,
    \grant_r[2]_i_3_3 ,
    rb_hit_busy_r_reg,
    use_addr,
    accept_internal_r_reg_3,
    accept_internal_r_reg_4,
    req_wr_r,
    Q,
    pass_open_bank_r_lcl_reg_1,
    pre_wait_r,
    pass_open_bank_r_lcl_reg_2,
    q_has_priority_r_reg_1,
    i___70,
    ras_timer_zero_r,
    auto_pre_r_lcl_reg_2,
    \ras_timer_r_reg[0]_4 ,
    \ras_timer_r_reg[0]_5 ,
    \ras_timer_r_reg[0]_6 ,
    \ras_timer_r_reg[1]_0 ,
    \ras_timer_r_reg[1]_1 ,
    \ras_timer_r_reg[1]_2 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_3 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_3 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_2 ,
    \q_entry_r_reg[0]_7 ,
    \order_q_r_reg[1]_0 ,
    \order_q_r_reg[0]_4 );
  output idle_r_lcl_reg_0;
  output [0:0]E;
  output pass_open_bank_r;
  output pass_open_bank_ns;
  output q_has_rd;
  output q_has_priority;
  output pass_open_bank_r_lcl_reg_0;
  output wait_for_maint_r;
  output tail_r;
  output head_r_lcl_reg_0;
  output ordered_r_lcl;
  output auto_pre_r_lcl_reg_0;
  output \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0 ;
  output idle_r_lcl_reg_1;
  output \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ;
  output \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ;
  output rd_wr_r_lcl_reg;
  output [1:0]D;
  output \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1 ;
  output idle_r_lcl_reg_2;
  output pre_bm_end_r_reg_0;
  output idle_r_lcl_reg_3;
  output idle_r_lcl_reg_4;
  output [0:0]q_entry_ns;
  output p_9_in;
  output idle_r_lcl_reg_5;
  output idle_r_lcl_reg_6;
  output \q_entry_r_reg[0]_0 ;
  output \q_entry_r_reg[0]_1 ;
  output \q_entry_r_reg[1]_0 ;
  output \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 ;
  output idle_r_lcl_reg_7;
  output ordered_r_lcl_reg_0;
  output \order_q_r_reg[0]_0 ;
  output req_bank_rdy_ns;
  output p_145_out;
  output pre_passing_open_bank_r_reg_0;
  output idle_r_lcl_reg_8;
  output act_wait_r_lcl_reg;
  output \compute_tail.tail_r_lcl_reg_0 ;
  output idle_r_lcl_reg_9;
  input q_has_rd_r_reg_0;
  input pre_bm_end_ns;
  input pre_passing_open_bank_ns;
  input q_has_rd_r_reg_1;
  input q_has_priority_r_reg_0;
  input wait_for_maint_r_lcl_reg_0;
  input wait_for_maint_r_lcl_reg_1;
  input head_r_lcl_reg_1;
  input \compute_tail.tail_r_lcl_reg_1 ;
  input head_r_lcl_reg_2;
  input ordered_r_lcl_reg_1;
  input auto_pre_r_lcl_reg_1;
  input accept_internal_r_reg;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_1 ;
  input accept_internal_r_reg_0;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2 ;
  input accept_internal_r_reg_1;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_2 ;
  input granted_col_r_reg;
  input granted_col_r_reg_0;
  input bm_end_r1_reg;
  input granted_col_r_reg_1;
  input granted_col_r_reg_2;
  input \ras_timer_r_reg[0] ;
  input \ras_timer_r_reg[1] ;
  input \ras_timer_r_reg[0]_0 ;
  input \ras_timer_r_reg[0]_1 ;
  input \ras_timer_r_reg[0]_2 ;
  input \ras_timer_r_reg[0]_3 ;
  input \q_entry_r_reg[1]_1 ;
  input \q_entry_r_reg[1]_2 ;
  input [0:0]\q_entry_r_reg[1]_3 ;
  input [0:0]\q_entry_r_reg[1]_4 ;
  input [0:0]\q_entry_r_reg[1]_5 ;
  input \q_entry_r_reg[1]_6 ;
  input \q_entry_r_reg[1]_7 ;
  input \q_entry_r_reg[1]_8 ;
  input accept_internal_r_reg_2;
  input head_r_lcl_reg_3;
  input \q_entry_r_reg[1]_9 ;
  input \q_entry_r_reg[1]_10 ;
  input \q_entry_r_reg[0]_2 ;
  input \q_entry_r_reg[0]_3 ;
  input \q_entry_r_reg[0]_4 ;
  input \q_entry_r_reg[0]_5 ;
  input \q_entry_r_reg[0]_6 ;
  input i___3_i_4;
  input \order_q_r_reg[0]_1 ;
  input \order_q_r_reg[0]_2 ;
  input \order_q_r_reg[0]_3 ;
  input req_bank_rdy_r_reg;
  input req_priority_r;
  input req_bank_rdy_r_reg_0;
  input \grant_r[2]_i_3_0 ;
  input \grant_r[2]_i_3_1 ;
  input \grant_r[2]_i_3_2 ;
  input \grant_r[2]_i_3_3 ;
  input rb_hit_busy_r_reg;
  input use_addr;
  input accept_internal_r_reg_3;
  input accept_internal_r_reg_4;
  input [0:0]req_wr_r;
  input [0:0]Q;
  input pass_open_bank_r_lcl_reg_1;
  input pre_wait_r;
  input pass_open_bank_r_lcl_reg_2;
  input q_has_priority_r_reg_1;
  input i___70;
  input ras_timer_zero_r;
  input auto_pre_r_lcl_reg_2;
  input \ras_timer_r_reg[0]_4 ;
  input \ras_timer_r_reg[0]_5 ;
  input \ras_timer_r_reg[0]_6 ;
  input \ras_timer_r_reg[1]_0 ;
  input \ras_timer_r_reg[1]_1 ;
  input \ras_timer_r_reg[1]_2 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_3 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_3 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_2 ;
  input \q_entry_r_reg[0]_7 ;
  input \order_q_r_reg[1]_0 ;
  input \order_q_r_reg[0]_4 ;

  wire [1:0]D;
  wire [0:0]E;
  wire [0:0]Q;
  wire accept_internal_r_reg;
  wire accept_internal_r_reg_0;
  wire accept_internal_r_reg_1;
  wire accept_internal_r_reg_2;
  wire accept_internal_r_reg_3;
  wire accept_internal_r_reg_4;
  wire act_wait_r_lcl_reg;
  wire auto_pre_r_lcl_reg_0;
  wire auto_pre_r_lcl_reg_1;
  wire auto_pre_r_lcl_reg_2;
  wire bm_end_r1_reg;
  wire \compute_tail.tail_r_lcl_reg_0 ;
  wire \compute_tail.tail_r_lcl_reg_1 ;
  wire \grant_r[2]_i_3_0 ;
  wire \grant_r[2]_i_3_1 ;
  wire \grant_r[2]_i_3_2 ;
  wire \grant_r[2]_i_3_3 ;
  wire \grant_r[2]_i_5_n_0 ;
  wire granted_col_r_reg;
  wire granted_col_r_reg_0;
  wire granted_col_r_reg_1;
  wire granted_col_r_reg_2;
  wire head_r_lcl_reg_0;
  wire head_r_lcl_reg_1;
  wire head_r_lcl_reg_2;
  wire head_r_lcl_reg_3;
  wire i___3_i_4;
  wire i___70;
  wire idle_r_lcl_reg_0;
  wire idle_r_lcl_reg_1;
  wire idle_r_lcl_reg_2;
  wire idle_r_lcl_reg_3;
  wire idle_r_lcl_reg_4;
  wire idle_r_lcl_reg_5;
  wire idle_r_lcl_reg_6;
  wire idle_r_lcl_reg_7;
  wire idle_r_lcl_reg_8;
  wire idle_r_lcl_reg_9;
  wire [1:0]order_q_r;
  wire \order_q_r[0]_i_1_n_0 ;
  wire \order_q_r[1]_i_1_n_0 ;
  wire \order_q_r_reg[0]_0 ;
  wire \order_q_r_reg[0]_1 ;
  wire \order_q_r_reg[0]_2 ;
  wire \order_q_r_reg[0]_3 ;
  wire \order_q_r_reg[0]_4 ;
  wire \order_q_r_reg[1]_0 ;
  wire ordered_r_lcl;
  wire ordered_r_lcl_reg_0;
  wire ordered_r_lcl_reg_1;
  wire p_145_out;
  wire p_9_in;
  wire pass_open_bank_ns;
  wire pass_open_bank_r;
  wire pass_open_bank_r_lcl_reg_0;
  wire pass_open_bank_r_lcl_reg_1;
  wire pass_open_bank_r_lcl_reg_2;
  wire pre_bm_end_ns;
  wire pre_bm_end_r;
  wire pre_bm_end_r_reg_0;
  wire pre_passing_open_bank_ns;
  wire pre_passing_open_bank_r;
  wire pre_passing_open_bank_r_reg_0;
  wire pre_wait_r;
  wire [0:0]q_entry_ns;
  wire \q_entry_r[0]_i_1_n_0 ;
  wire \q_entry_r[0]_i_3__0_n_0 ;
  wire \q_entry_r[1]_i_1_n_0 ;
  wire \q_entry_r[1]_i_2__2_n_0 ;
  wire \q_entry_r[1]_i_3__2_n_0 ;
  wire \q_entry_r[1]_i_4__1_n_0 ;
  wire \q_entry_r[1]_i_5_n_0 ;
  wire \q_entry_r_reg[0]_0 ;
  wire \q_entry_r_reg[0]_1 ;
  wire \q_entry_r_reg[0]_2 ;
  wire \q_entry_r_reg[0]_3 ;
  wire \q_entry_r_reg[0]_4 ;
  wire \q_entry_r_reg[0]_5 ;
  wire \q_entry_r_reg[0]_6 ;
  wire \q_entry_r_reg[0]_7 ;
  wire \q_entry_r_reg[1]_0 ;
  wire \q_entry_r_reg[1]_1 ;
  wire \q_entry_r_reg[1]_10 ;
  wire \q_entry_r_reg[1]_2 ;
  wire [0:0]\q_entry_r_reg[1]_3 ;
  wire [0:0]\q_entry_r_reg[1]_4 ;
  wire [0:0]\q_entry_r_reg[1]_5 ;
  wire \q_entry_r_reg[1]_6 ;
  wire \q_entry_r_reg[1]_7 ;
  wire \q_entry_r_reg[1]_8 ;
  wire \q_entry_r_reg[1]_9 ;
  wire q_has_priority;
  wire q_has_priority_r_reg_0;
  wire q_has_priority_r_reg_1;
  wire q_has_rd;
  wire q_has_rd_r_reg_0;
  wire q_has_rd_r_reg_1;
  wire \ras_timer_r[0]_i_2__2_n_0 ;
  wire \ras_timer_r[1]_i_2__2_n_0 ;
  wire \ras_timer_r_reg[0] ;
  wire \ras_timer_r_reg[0]_0 ;
  wire \ras_timer_r_reg[0]_1 ;
  wire \ras_timer_r_reg[0]_2 ;
  wire \ras_timer_r_reg[0]_3 ;
  wire \ras_timer_r_reg[0]_4 ;
  wire \ras_timer_r_reg[0]_5 ;
  wire \ras_timer_r_reg[0]_6 ;
  wire \ras_timer_r_reg[1] ;
  wire \ras_timer_r_reg[1]_0 ;
  wire \ras_timer_r_reg[1]_1 ;
  wire \ras_timer_r_reg[1]_2 ;
  wire ras_timer_zero_r;
  wire \rb_hit_busies.rb_hit_busies_r_lcl[1]_i_1_n_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl[2]_i_2_n_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl[3]_i_1__0_n_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_1 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_2 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_2 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_3 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_3 ;
  wire rb_hit_busy_r_reg;
  wire rd_wr_r_lcl_reg;
  wire req_bank_rdy_ns;
  wire req_bank_rdy_r_reg;
  wire req_bank_rdy_r_reg_0;
  wire req_priority_r;
  wire [0:0]req_wr_r;
  wire tail_r;
  wire use_addr;
  wire wait_for_maint_r;
  wire wait_for_maint_r_lcl_reg_0;
  wire wait_for_maint_r_lcl_reg_1;

  (* SOFT_HLUTNM = "soft_lutpair1153" *) 
  LUT5 #(
    .INIT(32'h2AAAAAAA)) 
    accept_internal_r_i_1
       (.I0(accept_internal_r_reg_2),
        .I1(idle_r_lcl_reg_1),
        .I2(accept_internal_r_reg),
        .I3(accept_internal_r_reg_0),
        .I4(accept_internal_r_reg_1),
        .O(p_9_in));
  FDRE auto_pre_r_lcl_reg
       (.C(q_has_rd_r_reg_0),
        .CE(1'b1),
        .D(auto_pre_r_lcl_reg_1),
        .Q(auto_pre_r_lcl_reg_0),
        .R(pass_open_bank_r_lcl_reg_0));
  LUT5 #(
    .INIT(32'hBFAAAAAA)) 
    bm_end_r1_i_1__0
       (.I0(pre_bm_end_r),
        .I1(bm_end_r1_reg),
        .I2(req_wr_r),
        .I3(Q),
        .I4(pass_open_bank_r),
        .O(pre_bm_end_r_reg_0));
  FDRE #(
    .INIT(1'b1)) 
    \compute_tail.tail_r_lcl_reg 
       (.C(q_has_rd_r_reg_0),
        .CE(1'b1),
        .D(\compute_tail.tail_r_lcl_reg_1 ),
        .Q(tail_r),
        .R(head_r_lcl_reg_1));
  LUT5 #(
    .INIT(32'hF2F2F2FF)) 
    demand_priority_r_i_2__2
       (.I0(order_q_r[0]),
        .I1(req_bank_rdy_r_reg),
        .I2(order_q_r[1]),
        .I3(q_has_priority),
        .I4(req_priority_r),
        .O(\order_q_r_reg[0]_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFBAFFFFFFBF)) 
    \grant_r[2]_i_3 
       (.I0(granted_col_r_reg),
        .I1(granted_col_r_reg_0),
        .I2(bm_end_r1_reg),
        .I3(granted_col_r_reg_1),
        .I4(\grant_r[2]_i_5_n_0 ),
        .I5(granted_col_r_reg_2),
        .O(rd_wr_r_lcl_reg));
  LUT6 #(
    .INIT(64'hEAAAAAAAAAAAAAAA)) 
    \grant_r[2]_i_5 
       (.I0(order_q_r[1]),
        .I1(\grant_r[2]_i_3_0 ),
        .I2(\grant_r[2]_i_3_1 ),
        .I3(\grant_r[2]_i_3_2 ),
        .I4(\grant_r[2]_i_3_3 ),
        .I5(order_q_r[0]),
        .O(\grant_r[2]_i_5_n_0 ));
  FDSE head_r_lcl_reg
       (.C(q_has_rd_r_reg_0),
        .CE(1'b1),
        .D(head_r_lcl_reg_2),
        .Q(head_r_lcl_reg_0),
        .S(head_r_lcl_reg_1));
  LUT6 #(
    .INIT(64'h00000000F4F4FFF4)) 
    i___26_i_1
       (.I0(\ras_timer_r_reg[0]_0 ),
        .I1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ),
        .I2(\ras_timer_r_reg[0]_1 ),
        .I3(\rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0 ),
        .I4(\ras_timer_r_reg[0]_2 ),
        .I5(\ras_timer_r_reg[0]_3 ),
        .O(\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1 ));
  LUT5 #(
    .INIT(32'h40555555)) 
    i___29_i_1
       (.I0(pre_passing_open_bank_r),
        .I1(bm_end_r1_reg),
        .I2(req_wr_r),
        .I3(Q),
        .I4(pass_open_bank_r),
        .O(pre_passing_open_bank_r_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair1154" *) 
  LUT5 #(
    .INIT(32'h01168001)) 
    i___3_i_1
       (.I0(idle_r_lcl_reg_0),
        .I1(\q_entry_r_reg[1]_3 ),
        .I2(\q_entry_r_reg[1]_4 ),
        .I3(\q_entry_r_reg[1]_5 ),
        .I4(\q_entry_r_reg[1]_7 ),
        .O(idle_r_lcl_reg_9));
  LUT6 #(
    .INIT(64'h20202020202F2F20)) 
    i___3_i_2
       (.I0(\q_entry_r_reg[0]_1 ),
        .I1(\q_entry_r_reg[1]_0 ),
        .I2(head_r_lcl_reg_3),
        .I3(\q_entry_r_reg[1]_9 ),
        .I4(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 ),
        .I5(\q_entry_r_reg[1]_10 ),
        .O(\q_entry_r_reg[0]_0 ));
  LUT5 #(
    .INIT(32'hFFFAFBFB)) 
    i___3_i_3
       (.I0(pre_bm_end_r_reg_0),
        .I1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 ),
        .I2(\q_entry_r_reg[0]_2 ),
        .I3(\q_entry_r_reg[1]_7 ),
        .I4(idle_r_lcl_reg_0),
        .O(idle_r_lcl_reg_7));
  LUT6 #(
    .INIT(64'h0DDD0DDD00000DDD)) 
    i___3_i_6
       (.I0(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ),
        .I1(i___3_i_4),
        .I2(\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ),
        .I3(\q_entry_r_reg[1]_2 ),
        .I4(\rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0 ),
        .I5(\q_entry_r_reg[1]_1 ),
        .O(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 ));
  LUT6 #(
    .INIT(64'h00000000FD555555)) 
    i___48_i_1
       (.I0(idle_r_lcl_reg_0),
        .I1(use_addr),
        .I2(accept_internal_r_reg_3),
        .I3(head_r_lcl_reg_0),
        .I4(accept_internal_r_reg_4),
        .I5(pass_open_bank_r_lcl_reg_0),
        .O(idle_r_lcl_reg_1));
  LUT5 #(
    .INIT(32'h777F7F7F)) 
    i___61_i_2
       (.I0(tail_r),
        .I1(\q_entry_r_reg[0]_6 ),
        .I2(accept_internal_r_reg_3),
        .I3(auto_pre_r_lcl_reg_2),
        .I4(use_addr),
        .O(\compute_tail.tail_r_lcl_reg_0 ));
  LUT5 #(
    .INIT(32'hFFDFFFFF)) 
    i___70_i_2
       (.I0(i___70),
        .I1(idle_r_lcl_reg_0),
        .I2(head_r_lcl_reg_0),
        .I3(wait_for_maint_r),
        .I4(ras_timer_zero_r),
        .O(act_wait_r_lcl_reg));
  (* SOFT_HLUTNM = "soft_lutpair1153" *) 
  LUT1 #(
    .INIT(2'h1)) 
    idle_r_lcl_i_1__2
       (.I0(idle_r_lcl_reg_1),
        .O(E));
  FDRE idle_r_lcl_reg
       (.C(q_has_rd_r_reg_0),
        .CE(1'b1),
        .D(E),
        .Q(idle_r_lcl_reg_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0D550C000D550CF0)) 
    \order_q_r[0]_i_1 
       (.I0(ordered_r_lcl_reg_0),
        .I1(order_q_r[1]),
        .I2(order_q_r[0]),
        .I3(req_bank_rdy_r_reg),
        .I4(\q_entry_r_reg[0]_2 ),
        .I5(\order_q_r_reg[0]_4 ),
        .O(\order_q_r[0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h69969669)) 
    \order_q_r[0]_i_2 
       (.I0(ordered_r_lcl),
        .I1(\order_q_r_reg[0]_1 ),
        .I2(\order_q_r_reg[0]_2 ),
        .I3(\order_q_r_reg[0]_3 ),
        .I4(req_bank_rdy_r_reg),
        .O(ordered_r_lcl_reg_0));
  LUT6 #(
    .INIT(64'hC2AAC000C2AAC0CC)) 
    \order_q_r[1]_i_1 
       (.I0(\order_q_r_reg[1]_0 ),
        .I1(order_q_r[1]),
        .I2(order_q_r[0]),
        .I3(req_bank_rdy_r_reg),
        .I4(\q_entry_r_reg[0]_2 ),
        .I5(\order_q_r_reg[0]_4 ),
        .O(\order_q_r[1]_i_1_n_0 ));
  FDRE \order_q_r_reg[0] 
       (.C(q_has_rd_r_reg_0),
        .CE(1'b1),
        .D(\order_q_r[0]_i_1_n_0 ),
        .Q(order_q_r[0]),
        .R(1'b0));
  FDRE \order_q_r_reg[1] 
       (.C(q_has_rd_r_reg_0),
        .CE(1'b1),
        .D(\order_q_r[1]_i_1_n_0 ),
        .Q(order_q_r[1]),
        .R(1'b0));
  FDRE ordered_r_lcl_reg
       (.C(q_has_rd_r_reg_0),
        .CE(1'b1),
        .D(ordered_r_lcl_reg_1),
        .Q(ordered_r_lcl),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h4444544444444444)) 
    pass_open_bank_r_lcl_i_1__0
       (.I0(pass_open_bank_r_lcl_reg_0),
        .I1(pass_open_bank_r),
        .I2(tail_r),
        .I3(pass_open_bank_r_lcl_reg_1),
        .I4(pre_wait_r),
        .I5(pass_open_bank_r_lcl_reg_2),
        .O(pass_open_bank_ns));
  FDRE pass_open_bank_r_lcl_reg
       (.C(q_has_rd_r_reg_0),
        .CE(1'b1),
        .D(pass_open_bank_ns),
        .Q(pass_open_bank_r),
        .R(1'b0));
  FDRE pre_bm_end_r_reg
       (.C(q_has_rd_r_reg_0),
        .CE(1'b1),
        .D(pre_bm_end_ns),
        .Q(pre_bm_end_r),
        .R(1'b0));
  FDRE pre_passing_open_bank_r_reg
       (.C(q_has_rd_r_reg_0),
        .CE(1'b1),
        .D(pre_passing_open_bank_ns),
        .Q(pre_passing_open_bank_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h88B8FFFF8BBB0000)) 
    \q_entry_r[0]_i_1 
       (.I0(\q_entry_r_reg[0]_7 ),
        .I1(pre_bm_end_r_reg_0),
        .I2(\q_entry_r_reg[0]_2 ),
        .I3(\q_entry_r[0]_i_3__0_n_0 ),
        .I4(idle_r_lcl_reg_7),
        .I5(\q_entry_r_reg[0]_1 ),
        .O(\q_entry_r[0]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h6996)) 
    \q_entry_r[0]_i_2 
       (.I0(\q_entry_r[1]_i_5_n_0 ),
        .I1(pre_bm_end_r_reg_0),
        .I2(\q_entry_r_reg[1]_1 ),
        .I3(\q_entry_r_reg[1]_2 ),
        .O(idle_r_lcl_reg_5));
  LUT5 #(
    .INIT(32'h96696996)) 
    \q_entry_r[0]_i_3__0 
       (.I0(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 ),
        .I1(\q_entry_r_reg[0]_3 ),
        .I2(\q_entry_r_reg[0]_4 ),
        .I3(\q_entry_r_reg[0]_5 ),
        .I4(\q_entry_r_reg[0]_6 ),
        .O(\q_entry_r[0]_i_3__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1155" *) 
  LUT5 #(
    .INIT(32'h96696996)) 
    \q_entry_r[0]_i_3__1 
       (.I0(pre_bm_end_r_reg_0),
        .I1(\q_entry_r_reg[1]_5 ),
        .I2(\q_entry_r_reg[1]_4 ),
        .I3(\q_entry_r_reg[1]_3 ),
        .I4(idle_r_lcl_reg_0),
        .O(idle_r_lcl_reg_8));
  LUT5 #(
    .INIT(32'hF1FFF100)) 
    \q_entry_r[1]_i_1 
       (.I0(\q_entry_r[1]_i_2__2_n_0 ),
        .I1(pre_bm_end_r_reg_0),
        .I2(\q_entry_r[1]_i_3__2_n_0 ),
        .I3(idle_r_lcl_reg_7),
        .I4(\q_entry_r_reg[1]_0 ),
        .O(\q_entry_r[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h7EE8E881177E7EE8)) 
    \q_entry_r[1]_i_2 
       (.I0(idle_r_lcl_reg_0),
        .I1(\q_entry_r_reg[1]_3 ),
        .I2(\q_entry_r_reg[1]_4 ),
        .I3(\q_entry_r_reg[1]_5 ),
        .I4(pre_bm_end_r_reg_0),
        .I5(\q_entry_r_reg[1]_1 ),
        .O(idle_r_lcl_reg_3));
  LUT6 #(
    .INIT(64'hE2D1F3C0F3C0D1E2)) 
    \q_entry_r[1]_i_2__0 
       (.I0(\q_entry_r_reg[1]_7 ),
        .I1(\q_entry_r_reg[1]_1 ),
        .I2(\q_entry_r_reg[1]_8 ),
        .I3(\q_entry_r[1]_i_4__1_n_0 ),
        .I4(\q_entry_r[1]_i_5_n_0 ),
        .I5(pre_bm_end_r_reg_0),
        .O(q_entry_ns));
  (* SOFT_HLUTNM = "soft_lutpair1156" *) 
  LUT5 #(
    .INIT(32'h65A6A69A)) 
    \q_entry_r[1]_i_2__1 
       (.I0(\q_entry_r[1]_i_4__1_n_0 ),
        .I1(\q_entry_r_reg[1]_2 ),
        .I2(\q_entry_r_reg[1]_1 ),
        .I3(pre_bm_end_r_reg_0),
        .I4(\q_entry_r[1]_i_5_n_0 ),
        .O(idle_r_lcl_reg_6));
  LUT6 #(
    .INIT(64'h560056FF56FF5600)) 
    \q_entry_r[1]_i_2__2 
       (.I0(\q_entry_r_reg[1]_10 ),
        .I1(\q_entry_r_reg[1]_9 ),
        .I2(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 ),
        .I3(\q_entry_r_reg[0]_2 ),
        .I4(\q_entry_r_reg[1]_0 ),
        .I5(\q_entry_r_reg[0]_1 ),
        .O(\q_entry_r[1]_i_2__2_n_0 ));
  LUT6 #(
    .INIT(64'h599A599A0000FFFF)) 
    \q_entry_r[1]_i_3__0 
       (.I0(\q_entry_r[1]_i_4__1_n_0 ),
        .I1(\q_entry_r_reg[1]_1 ),
        .I2(\q_entry_r[1]_i_5_n_0 ),
        .I3(pre_bm_end_r_reg_0),
        .I4(\q_entry_r_reg[1]_6 ),
        .I5(\q_entry_r_reg[1]_2 ),
        .O(idle_r_lcl_reg_4));
  LUT6 #(
    .INIT(64'hBDD4D44200000000)) 
    \q_entry_r[1]_i_3__2 
       (.I0(\q_entry_r_reg[1]_7 ),
        .I1(\q_entry_r_reg[1]_3 ),
        .I2(\q_entry_r_reg[1]_4 ),
        .I3(\q_entry_r_reg[1]_5 ),
        .I4(idle_r_lcl_reg_0),
        .I5(pre_bm_end_r_reg_0),
        .O(\q_entry_r[1]_i_3__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1156" *) 
  LUT5 #(
    .INIT(32'hE78E1871)) 
    \q_entry_r[1]_i_4 
       (.I0(\q_entry_r[1]_i_5_n_0 ),
        .I1(pre_bm_end_r_reg_0),
        .I2(\q_entry_r_reg[1]_1 ),
        .I3(\q_entry_r_reg[1]_2 ),
        .I4(\q_entry_r[1]_i_4__1_n_0 ),
        .O(idle_r_lcl_reg_2));
  (* SOFT_HLUTNM = "soft_lutpair1154" *) 
  LUT4 #(
    .INIT(16'h7EE8)) 
    \q_entry_r[1]_i_4__1 
       (.I0(idle_r_lcl_reg_0),
        .I1(\q_entry_r_reg[1]_5 ),
        .I2(\q_entry_r_reg[1]_4 ),
        .I3(\q_entry_r_reg[1]_3 ),
        .O(\q_entry_r[1]_i_4__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1155" *) 
  LUT4 #(
    .INIT(16'h6996)) 
    \q_entry_r[1]_i_5 
       (.I0(idle_r_lcl_reg_0),
        .I1(\q_entry_r_reg[1]_3 ),
        .I2(\q_entry_r_reg[1]_4 ),
        .I3(\q_entry_r_reg[1]_5 ),
        .O(\q_entry_r[1]_i_5_n_0 ));
  FDRE \q_entry_r_reg[0] 
       (.C(q_has_rd_r_reg_0),
        .CE(1'b1),
        .D(\q_entry_r[0]_i_1_n_0 ),
        .Q(\q_entry_r_reg[0]_1 ),
        .R(head_r_lcl_reg_1));
  FDRE \q_entry_r_reg[1] 
       (.C(q_has_rd_r_reg_0),
        .CE(1'b1),
        .D(\q_entry_r[1]_i_1_n_0 ),
        .Q(\q_entry_r_reg[1]_0 ),
        .R(head_r_lcl_reg_1));
  FDRE q_has_priority_r_reg
       (.C(q_has_rd_r_reg_0),
        .CE(1'b1),
        .D(q_has_priority_r_reg_0),
        .Q(q_has_priority),
        .R(pass_open_bank_r_lcl_reg_0));
  FDRE q_has_rd_r_reg
       (.C(q_has_rd_r_reg_0),
        .CE(1'b1),
        .D(q_has_rd_r_reg_1),
        .Q(q_has_rd),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair1158" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ras_timer_r[0]_i_1__0 
       (.I0(\ras_timer_r[0]_i_2__2_n_0 ),
        .I1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1 ),
        .I2(\ras_timer_r_reg[0] ),
        .O(D[0]));
  LUT6 #(
    .INIT(64'hB8BBB888B888B888)) 
    \ras_timer_r[0]_i_2__2 
       (.I0(\ras_timer_r_reg[0]_4 ),
        .I1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ),
        .I2(\ras_timer_r_reg[0]_5 ),
        .I3(\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ),
        .I4(\rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0 ),
        .I5(\ras_timer_r_reg[0]_6 ),
        .O(\ras_timer_r[0]_i_2__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1158" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ras_timer_r[1]_i_1__0 
       (.I0(\ras_timer_r[1]_i_2__2_n_0 ),
        .I1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1 ),
        .I2(\ras_timer_r_reg[1] ),
        .O(D[1]));
  LUT6 #(
    .INIT(64'hB8BBB888B888B888)) 
    \ras_timer_r[1]_i_2__2 
       (.I0(\ras_timer_r_reg[1]_0 ),
        .I1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ),
        .I2(\ras_timer_r_reg[1]_1 ),
        .I3(\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ),
        .I4(\rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0 ),
        .I5(\ras_timer_r_reg[1]_2 ),
        .O(\ras_timer_r[1]_i_2__2_n_0 ));
  LUT4 #(
    .INIT(16'hF022)) 
    \rb_hit_busies.rb_hit_busies_r_lcl[1]_i_1 
       (.I0(accept_internal_r_reg),
        .I1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_1 ),
        .I2(\rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0 ),
        .I3(idle_r_lcl_reg_1),
        .O(\rb_hit_busies.rb_hit_busies_r_lcl[1]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hF022)) 
    \rb_hit_busies.rb_hit_busies_r_lcl[2]_i_2 
       (.I0(accept_internal_r_reg_1),
        .I1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_2 ),
        .I2(\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ),
        .I3(idle_r_lcl_reg_1),
        .O(\rb_hit_busies.rb_hit_busies_r_lcl[2]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1157" *) 
  LUT4 #(
    .INIT(16'hF022)) 
    \rb_hit_busies.rb_hit_busies_r_lcl[3]_i_1__0 
       (.I0(accept_internal_r_reg_0),
        .I1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2 ),
        .I2(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ),
        .I3(idle_r_lcl_reg_1),
        .O(\rb_hit_busies.rb_hit_busies_r_lcl[3]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFAAEAEAEA)) 
    \rb_hit_busies.rb_hit_busies_r_lcl[4]_i_1 
       (.I0(q_has_priority_r_reg_1),
        .I1(pass_open_bank_r),
        .I2(Q),
        .I3(req_wr_r),
        .I4(bm_end_r1_reg),
        .I5(pre_bm_end_r),
        .O(pass_open_bank_r_lcl_reg_0));
  FDRE #(
    .INIT(1'b0)) 
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[1] 
       (.C(q_has_rd_r_reg_0),
        .CE(1'b1),
        .D(\rb_hit_busies.rb_hit_busies_r_lcl[1]_i_1_n_0 ),
        .Q(\rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_0 ),
        .R(\rb_hit_busies.rb_hit_busies_r_lcl_reg[1]_2 ));
  FDRE #(
    .INIT(1'b0)) 
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2] 
       (.C(q_has_rd_r_reg_0),
        .CE(1'b1),
        .D(\rb_hit_busies.rb_hit_busies_r_lcl[2]_i_2_n_0 ),
        .Q(\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ),
        .R(\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_3 ));
  FDRE #(
    .INIT(1'b0)) 
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3] 
       (.C(q_has_rd_r_reg_0),
        .CE(1'b1),
        .D(\rb_hit_busies.rb_hit_busies_r_lcl[3]_i_1__0_n_0 ),
        .Q(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ),
        .R(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_3 ));
  (* SOFT_HLUTNM = "soft_lutpair1157" *) 
  LUT2 #(
    .INIT(4'h2)) 
    rb_hit_busy_r_i_1__2
       (.I0(idle_r_lcl_reg_1),
        .I1(rb_hit_busy_r_reg),
        .O(p_145_out));
  LUT4 #(
    .INIT(16'h00A2)) 
    req_bank_rdy_r_i_1__2
       (.I0(req_bank_rdy_r_reg_0),
        .I1(order_q_r[0]),
        .I2(req_bank_rdy_r_reg),
        .I3(order_q_r[1]),
        .O(req_bank_rdy_ns));
  FDRE wait_for_maint_r_lcl_reg
       (.C(q_has_rd_r_reg_0),
        .CE(1'b1),
        .D(wait_for_maint_r_lcl_reg_1),
        .Q(wait_for_maint_r),
        .R(wait_for_maint_r_lcl_reg_0));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_bank_queue" *) 
module mig_mig_7series_v4_2_bank_queue__parameterized0
   (idle_r_lcl_reg_0,
    E,
    pass_open_bank_r_lcl_reg_0,
    pass_open_bank_ns,
    pre_bm_end_r,
    q_has_rd_3,
    q_has_priority,
    wait_for_maint_r_13,
    head_r_lcl_reg_0,
    ordered_r_lcl_reg_0,
    tail_r_16,
    auto_pre_r_lcl_reg_0,
    granted_col_ns,
    rd_wr_r_lcl_reg,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ,
    idle_r_lcl_reg_1,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ,
    pre_passing_open_bank_r_reg_0,
    p_106_out,
    p_91_out,
    pre_bm_end_r_reg_0,
    \order_q_r_reg[0]_0 ,
    req_bank_rdy_ns,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1 ,
    \q_entry_r_reg[0]_0 ,
    \q_entry_r_reg[0]_1 ,
    \q_entry_r_reg[1]_0 ,
    \q_entry_r_reg[1]_1 ,
    D,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_2 ,
    \compute_tail.tail_r_lcl_reg_0 ,
    act_wait_r_lcl_reg,
    \order_q_r_reg[1]_0 ,
    pre_bm_end_ns,
    pre_passing_open_bank_ns,
    q_has_rd_r_reg_0,
    auto_pre_r_lcl_reg_1,
    q_has_priority_r_reg_0,
    wait_for_maint_r_lcl_reg_0,
    wait_for_maint_r_lcl_reg_1,
    head_r_lcl_reg_1,
    head_r_lcl_reg_2,
    ordered_r_lcl_reg_1,
    \compute_tail.tail_r_lcl_reg_1 ,
    auto_pre_r_lcl_reg_2,
    granted_col_r_reg,
    granted_col_r_reg_0,
    granted_col_r_reg_1,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_3 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_4 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ,
    granted_col_r_reg_2,
    bm_end_r1_reg,
    granted_col_r_reg_3,
    granted_col_r_reg_4,
    rb_hit_busies_r,
    Q,
    bm_end_r1_reg_0,
    rb_hit_busies_r_0,
    rb_hit_busy_r_reg,
    use_addr,
    rb_hit_busy_r_reg_0,
    rb_hit_busy_r_reg_1,
    pass_open_bank_r_lcl_reg_1,
    pre_wait_r,
    pass_open_bank_r_lcl_reg_2,
    req_bank_rdy_r_reg,
    req_priority_r,
    \grant_r[3]_i_2_0 ,
    \grant_r[3]_i_2_1 ,
    \grant_r[3]_i_2_2 ,
    \grant_r[3]_i_2_3 ,
    req_bank_rdy_r_reg_0,
    head_r_lcl_reg_3,
    \order_q_r_reg[1]_1 ,
    head_r_lcl_reg_4,
    head_r_lcl_reg_5,
    \ras_timer_r_reg[0] ,
    \ras_timer_r_reg[1] ,
    \ras_timer_r_reg[0]_0 ,
    \ras_timer_r_reg[0]_1 ,
    \ras_timer_r_reg[0]_2 ,
    \grant_r[3]_i_2_4 ,
    \ras_timer_r_reg[0]_3 ,
    i___34,
    i___34_0,
    i___34_1,
    \ras_timer_r_reg[1]_0 ,
    \ras_timer_r_reg[1]_1 ,
    \ras_timer_r_reg[1]_2 ,
    \ras_timer_r_reg[0]_4 ,
    \ras_timer_r_reg[0]_5 ,
    \ras_timer_r_reg[0]_6 ,
    auto_pre_r_lcl_reg_3,
    auto_pre_r_lcl_reg_4,
    i___73,
    ras_timer_zero_r,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_3 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_5 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 ,
    q_entry_ns,
    \q_entry_r_reg[1]_2 ,
    \q_entry_r_reg[0]_2 ,
    \q_entry_r_reg[0]_3 ,
    \order_q_r_reg[1]_2 ,
    \order_q_r_reg[1]_3 ,
    \order_q_r_reg[0]_1 ,
    \order_q_r_reg[0]_2 );
  output [0:0]idle_r_lcl_reg_0;
  output [0:0]E;
  output pass_open_bank_r_lcl_reg_0;
  output pass_open_bank_ns;
  output pre_bm_end_r;
  output q_has_rd_3;
  output q_has_priority;
  output wait_for_maint_r_13;
  output head_r_lcl_reg_0;
  output ordered_r_lcl_reg_0;
  output tail_r_16;
  output auto_pre_r_lcl_reg_0;
  output granted_col_ns;
  output rd_wr_r_lcl_reg;
  output \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ;
  output idle_r_lcl_reg_1;
  output \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ;
  output \rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ;
  output \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ;
  output pre_passing_open_bank_r_reg_0;
  output p_106_out;
  output p_91_out;
  output pre_bm_end_r_reg_0;
  output \order_q_r_reg[0]_0 ;
  output req_bank_rdy_ns;
  output \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1 ;
  output \q_entry_r_reg[0]_0 ;
  output \q_entry_r_reg[0]_1 ;
  output \q_entry_r_reg[1]_0 ;
  output \q_entry_r_reg[1]_1 ;
  output [1:0]D;
  output \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_2 ;
  output \compute_tail.tail_r_lcl_reg_0 ;
  output act_wait_r_lcl_reg;
  input \order_q_r_reg[1]_0 ;
  input pre_bm_end_ns;
  input pre_passing_open_bank_ns;
  input q_has_rd_r_reg_0;
  input auto_pre_r_lcl_reg_1;
  input q_has_priority_r_reg_0;
  input wait_for_maint_r_lcl_reg_0;
  input wait_for_maint_r_lcl_reg_1;
  input head_r_lcl_reg_1;
  input head_r_lcl_reg_2;
  input ordered_r_lcl_reg_1;
  input \compute_tail.tail_r_lcl_reg_1 ;
  input auto_pre_r_lcl_reg_2;
  input granted_col_r_reg;
  input granted_col_r_reg_0;
  input granted_col_r_reg_1;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_3 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_4 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ;
  input granted_col_r_reg_2;
  input bm_end_r1_reg;
  input granted_col_r_reg_3;
  input granted_col_r_reg_4;
  input [0:0]rb_hit_busies_r;
  input [0:0]Q;
  input bm_end_r1_reg_0;
  input [0:0]rb_hit_busies_r_0;
  input rb_hit_busy_r_reg;
  input use_addr;
  input rb_hit_busy_r_reg_0;
  input rb_hit_busy_r_reg_1;
  input pass_open_bank_r_lcl_reg_1;
  input pre_wait_r;
  input pass_open_bank_r_lcl_reg_2;
  input req_bank_rdy_r_reg;
  input req_priority_r;
  input \grant_r[3]_i_2_0 ;
  input \grant_r[3]_i_2_1 ;
  input \grant_r[3]_i_2_2 ;
  input \grant_r[3]_i_2_3 ;
  input req_bank_rdy_r_reg_0;
  input head_r_lcl_reg_3;
  input \order_q_r_reg[1]_1 ;
  input head_r_lcl_reg_4;
  input head_r_lcl_reg_5;
  input \ras_timer_r_reg[0] ;
  input \ras_timer_r_reg[1] ;
  input \ras_timer_r_reg[0]_0 ;
  input \ras_timer_r_reg[0]_1 ;
  input \ras_timer_r_reg[0]_2 ;
  input \grant_r[3]_i_2_4 ;
  input \ras_timer_r_reg[0]_3 ;
  input i___34;
  input i___34_0;
  input i___34_1;
  input \ras_timer_r_reg[1]_0 ;
  input \ras_timer_r_reg[1]_1 ;
  input \ras_timer_r_reg[1]_2 ;
  input \ras_timer_r_reg[0]_4 ;
  input \ras_timer_r_reg[0]_5 ;
  input \ras_timer_r_reg[0]_6 ;
  input auto_pre_r_lcl_reg_3;
  input auto_pre_r_lcl_reg_4;
  input i___73;
  input ras_timer_zero_r;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_3 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_5 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 ;
  input [0:0]q_entry_ns;
  input \q_entry_r_reg[1]_2 ;
  input \q_entry_r_reg[0]_2 ;
  input \q_entry_r_reg[0]_3 ;
  input \order_q_r_reg[1]_2 ;
  input \order_q_r_reg[1]_3 ;
  input \order_q_r_reg[0]_1 ;
  input \order_q_r_reg[0]_2 ;

  wire [1:0]D;
  wire [0:0]E;
  wire [0:0]Q;
  wire act_wait_r_lcl_reg;
  wire auto_pre_r_lcl_reg_0;
  wire auto_pre_r_lcl_reg_1;
  wire auto_pre_r_lcl_reg_2;
  wire auto_pre_r_lcl_reg_3;
  wire auto_pre_r_lcl_reg_4;
  wire bm_end_r1_reg;
  wire bm_end_r1_reg_0;
  wire \compute_tail.tail_r_lcl_reg_0 ;
  wire \compute_tail.tail_r_lcl_reg_1 ;
  wire \grant_r[3]_i_2_0 ;
  wire \grant_r[3]_i_2_1 ;
  wire \grant_r[3]_i_2_2 ;
  wire \grant_r[3]_i_2_3 ;
  wire \grant_r[3]_i_2_4 ;
  wire \grant_r[3]_i_6_n_0 ;
  wire \grant_r[3]_i_8_n_0 ;
  wire granted_col_ns;
  wire granted_col_r_reg;
  wire granted_col_r_reg_0;
  wire granted_col_r_reg_1;
  wire granted_col_r_reg_2;
  wire granted_col_r_reg_3;
  wire granted_col_r_reg_4;
  wire head_r_lcl_reg_0;
  wire head_r_lcl_reg_1;
  wire head_r_lcl_reg_2;
  wire head_r_lcl_reg_3;
  wire head_r_lcl_reg_4;
  wire head_r_lcl_reg_5;
  wire i___34;
  wire i___34_0;
  wire i___34_1;
  wire i___73;
  wire [0:0]idle_r_lcl_reg_0;
  wire idle_r_lcl_reg_1;
  wire [1:0]order_q_r;
  wire \order_q_r[0]_i_1_n_0 ;
  wire \order_q_r[1]_i_1_n_0 ;
  wire \order_q_r_reg[0]_0 ;
  wire \order_q_r_reg[0]_1 ;
  wire \order_q_r_reg[0]_2 ;
  wire \order_q_r_reg[1]_0 ;
  wire \order_q_r_reg[1]_1 ;
  wire \order_q_r_reg[1]_2 ;
  wire \order_q_r_reg[1]_3 ;
  wire ordered_r_lcl_reg_0;
  wire ordered_r_lcl_reg_1;
  wire p_106_out;
  wire p_91_out;
  wire pass_open_bank_ns;
  wire pass_open_bank_r_lcl_reg_0;
  wire pass_open_bank_r_lcl_reg_1;
  wire pass_open_bank_r_lcl_reg_2;
  wire pre_bm_end_ns;
  wire pre_bm_end_r;
  wire pre_bm_end_r_reg_0;
  wire pre_passing_open_bank_ns;
  wire pre_passing_open_bank_r;
  wire pre_passing_open_bank_r_reg_0;
  wire pre_wait_r;
  wire [0:0]q_entry_ns;
  wire \q_entry_r[0]_i_1_n_0 ;
  wire \q_entry_r[0]_i_2__1_n_0 ;
  wire \q_entry_r[1]_i_1_n_0 ;
  wire \q_entry_r_reg[0]_0 ;
  wire \q_entry_r_reg[0]_1 ;
  wire \q_entry_r_reg[0]_2 ;
  wire \q_entry_r_reg[0]_3 ;
  wire \q_entry_r_reg[1]_0 ;
  wire \q_entry_r_reg[1]_1 ;
  wire \q_entry_r_reg[1]_2 ;
  wire q_has_priority;
  wire q_has_priority_r_reg_0;
  wire q_has_rd_3;
  wire q_has_rd_r_reg_0;
  wire \ras_timer_r[0]_i_2__1_n_0 ;
  wire \ras_timer_r[1]_i_2__1_n_0 ;
  wire \ras_timer_r_reg[0] ;
  wire \ras_timer_r_reg[0]_0 ;
  wire \ras_timer_r_reg[0]_1 ;
  wire \ras_timer_r_reg[0]_2 ;
  wire \ras_timer_r_reg[0]_3 ;
  wire \ras_timer_r_reg[0]_4 ;
  wire \ras_timer_r_reg[0]_5 ;
  wire \ras_timer_r_reg[0]_6 ;
  wire \ras_timer_r_reg[1] ;
  wire \ras_timer_r_reg[1]_0 ;
  wire \ras_timer_r_reg[1]_1 ;
  wire \ras_timer_r_reg[1]_2 ;
  wire ras_timer_zero_r;
  wire \rb_hit_busies.rb_hit_busies_r_lcl[2]_i_1__0_n_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl[3]_i_1__1_n_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl[4]_i_2_n_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_2 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_3 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_4 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_5 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_3 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ;
  wire [0:0]rb_hit_busies_r;
  wire [0:0]rb_hit_busies_r_0;
  wire [4:4]rb_hit_busies_r_1;
  wire rb_hit_busy_r_reg;
  wire rb_hit_busy_r_reg_0;
  wire rb_hit_busy_r_reg_1;
  wire rd_wr_r_lcl_reg;
  wire req_bank_rdy_ns;
  wire req_bank_rdy_r_reg;
  wire req_bank_rdy_r_reg_0;
  wire req_priority_r;
  wire tail_r_16;
  wire use_addr;
  wire wait_for_maint_r_13;
  wire wait_for_maint_r_lcl_reg_0;
  wire wait_for_maint_r_lcl_reg_1;

  FDRE auto_pre_r_lcl_reg
       (.C(\order_q_r_reg[1]_0 ),
        .CE(1'b1),
        .D(auto_pre_r_lcl_reg_2),
        .Q(auto_pre_r_lcl_reg_0),
        .R(auto_pre_r_lcl_reg_1));
  (* SOFT_HLUTNM = "soft_lutpair1165" *) 
  LUT5 #(
    .INIT(32'hFFFF0888)) 
    bm_end_r1_i_1
       (.I0(pass_open_bank_r_lcl_reg_0),
        .I1(Q),
        .I2(bm_end_r1_reg),
        .I3(bm_end_r1_reg_0),
        .I4(pre_bm_end_r),
        .O(p_91_out));
  FDRE #(
    .INIT(1'b1)) 
    \compute_tail.tail_r_lcl_reg 
       (.C(\order_q_r_reg[1]_0 ),
        .CE(1'b1),
        .D(\compute_tail.tail_r_lcl_reg_1 ),
        .Q(tail_r_16),
        .R(head_r_lcl_reg_1));
  LUT5 #(
    .INIT(32'hF2F2F2FF)) 
    demand_priority_r_i_2__1
       (.I0(order_q_r[0]),
        .I1(req_bank_rdy_r_reg),
        .I2(order_q_r[1]),
        .I3(q_has_priority),
        .I4(req_priority_r),
        .O(\order_q_r_reg[0]_0 ));
  LUT6 #(
    .INIT(64'h0000008A00000080)) 
    \grant_r[3]_i_2 
       (.I0(\grant_r[3]_i_6_n_0 ),
        .I1(granted_col_r_reg_2),
        .I2(bm_end_r1_reg),
        .I3(\grant_r[3]_i_8_n_0 ),
        .I4(granted_col_r_reg_3),
        .I5(granted_col_r_reg_4),
        .O(rd_wr_r_lcl_reg));
  LUT6 #(
    .INIT(64'hBBBBBBBBBBBBABAA)) 
    \grant_r[3]_i_6 
       (.I0(req_bank_rdy_r_reg_0),
        .I1(\ras_timer_r_reg[0]_0 ),
        .I2(\ras_timer_r_reg[0]_1 ),
        .I3(rb_hit_busies_r_1),
        .I4(\ras_timer_r_reg[0]_2 ),
        .I5(\grant_r[3]_i_2_4 ),
        .O(\grant_r[3]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF2000)) 
    \grant_r[3]_i_8 
       (.I0(order_q_r[0]),
        .I1(\grant_r[3]_i_2_0 ),
        .I2(\grant_r[3]_i_2_1 ),
        .I3(\grant_r[3]_i_2_2 ),
        .I4(order_q_r[1]),
        .I5(\grant_r[3]_i_2_3 ),
        .O(\grant_r[3]_i_8_n_0 ));
  LUT4 #(
    .INIT(16'hBFFF)) 
    granted_col_r_i_1
       (.I0(rd_wr_r_lcl_reg),
        .I1(granted_col_r_reg),
        .I2(granted_col_r_reg_0),
        .I3(granted_col_r_reg_1),
        .O(granted_col_ns));
  FDRE head_r_lcl_reg
       (.C(\order_q_r_reg[1]_0 ),
        .CE(1'b1),
        .D(head_r_lcl_reg_2),
        .Q(head_r_lcl_reg_0),
        .R(head_r_lcl_reg_1));
  LUT6 #(
    .INIT(64'hAAAAAAAA00808080)) 
    i___25_i_3
       (.I0(rb_hit_busies_r),
        .I1(pass_open_bank_r_lcl_reg_0),
        .I2(Q),
        .I3(bm_end_r1_reg),
        .I4(bm_end_r1_reg_0),
        .I5(pre_passing_open_bank_r),
        .O(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ));
  LUT5 #(
    .INIT(32'h40555555)) 
    i___28_i_1
       (.I0(pre_passing_open_bank_r),
        .I1(bm_end_r1_reg_0),
        .I2(bm_end_r1_reg),
        .I3(Q),
        .I4(pass_open_bank_r_lcl_reg_0),
        .O(pre_passing_open_bank_r_reg_0));
  LUT6 #(
    .INIT(64'hAAAAAAAA00808080)) 
    i___29_i_2
       (.I0(rb_hit_busies_r_0),
        .I1(pass_open_bank_r_lcl_reg_0),
        .I2(Q),
        .I3(bm_end_r1_reg),
        .I4(bm_end_r1_reg_0),
        .I5(pre_passing_open_bank_r),
        .O(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ));
  LUT6 #(
    .INIT(64'h0777077700000777)) 
    i___34_i_1
       (.I0(i___34),
        .I1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ),
        .I2(rb_hit_busies_r_1),
        .I3(i___34_0),
        .I4(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ),
        .I5(i___34_1),
        .O(\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1 ));
  LUT6 #(
    .INIT(64'h00000000FD555555)) 
    i___35_i_1
       (.I0(idle_r_lcl_reg_0),
        .I1(use_addr),
        .I2(rb_hit_busy_r_reg_0),
        .I3(head_r_lcl_reg_0),
        .I4(rb_hit_busy_r_reg_1),
        .I5(auto_pre_r_lcl_reg_1),
        .O(idle_r_lcl_reg_1));
  LUT6 #(
    .INIT(64'h00000000F4F4FFF4)) 
    i___49_i_1
       (.I0(\ras_timer_r_reg[0]_3 ),
        .I1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ),
        .I2(\ras_timer_r_reg[0]_2 ),
        .I3(rb_hit_busies_r_1),
        .I4(\ras_timer_r_reg[0]_1 ),
        .I5(\ras_timer_r_reg[0]_0 ),
        .O(\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_2 ));
  LUT6 #(
    .INIT(64'h1400140014FF1400)) 
    i___4_i_1
       (.I0(head_r_lcl_reg_4),
        .I1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1 ),
        .I2(head_r_lcl_reg_3),
        .I3(head_r_lcl_reg_5),
        .I4(\q_entry_r_reg[0]_0 ),
        .I5(\q_entry_r_reg[1]_0 ),
        .O(\q_entry_r_reg[0]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1165" *) 
  LUT5 #(
    .INIT(32'h40555555)) 
    i___4_i_2
       (.I0(pre_bm_end_r),
        .I1(bm_end_r1_reg_0),
        .I2(bm_end_r1_reg),
        .I3(Q),
        .I4(pass_open_bank_r_lcl_reg_0),
        .O(pre_bm_end_r_reg_0));
  LUT5 #(
    .INIT(32'h5777FFFF)) 
    i___62_i_2
       (.I0(tail_r_16),
        .I1(rb_hit_busy_r_reg_0),
        .I2(auto_pre_r_lcl_reg_3),
        .I3(use_addr),
        .I4(auto_pre_r_lcl_reg_4),
        .O(\compute_tail.tail_r_lcl_reg_0 ));
  LUT5 #(
    .INIT(32'hFFDFFFFF)) 
    i___73_i_1
       (.I0(i___73),
        .I1(idle_r_lcl_reg_0),
        .I2(head_r_lcl_reg_0),
        .I3(wait_for_maint_r_13),
        .I4(ras_timer_zero_r),
        .O(act_wait_r_lcl_reg));
  (* SOFT_HLUTNM = "soft_lutpair1166" *) 
  LUT1 #(
    .INIT(2'h1)) 
    idle_r_lcl_i_1
       (.I0(idle_r_lcl_reg_1),
        .O(E));
  FDRE idle_r_lcl_reg
       (.C(\order_q_r_reg[1]_0 ),
        .CE(1'b1),
        .D(E),
        .Q(idle_r_lcl_reg_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0D550C000D550CF0)) 
    \order_q_r[0]_i_1 
       (.I0(\order_q_r_reg[0]_1 ),
        .I1(order_q_r[1]),
        .I2(order_q_r[0]),
        .I3(req_bank_rdy_r_reg),
        .I4(\order_q_r_reg[1]_1 ),
        .I5(\order_q_r_reg[0]_2 ),
        .O(\order_q_r[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hC2AAC000C2AAC0CC)) 
    \order_q_r[1]_i_1 
       (.I0(\order_q_r_reg[1]_2 ),
        .I1(order_q_r[1]),
        .I2(order_q_r[0]),
        .I3(req_bank_rdy_r_reg),
        .I4(\order_q_r_reg[1]_1 ),
        .I5(\order_q_r_reg[1]_3 ),
        .O(\order_q_r[1]_i_1_n_0 ));
  FDRE \order_q_r_reg[0] 
       (.C(\order_q_r_reg[1]_0 ),
        .CE(1'b1),
        .D(\order_q_r[0]_i_1_n_0 ),
        .Q(order_q_r[0]),
        .R(1'b0));
  FDRE \order_q_r_reg[1] 
       (.C(\order_q_r_reg[1]_0 ),
        .CE(1'b1),
        .D(\order_q_r[1]_i_1_n_0 ),
        .Q(order_q_r[1]),
        .R(1'b0));
  FDRE ordered_r_lcl_reg
       (.C(\order_q_r_reg[1]_0 ),
        .CE(1'b1),
        .D(ordered_r_lcl_reg_1),
        .Q(ordered_r_lcl_reg_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h4444544444444444)) 
    pass_open_bank_r_lcl_i_1
       (.I0(auto_pre_r_lcl_reg_1),
        .I1(pass_open_bank_r_lcl_reg_0),
        .I2(tail_r_16),
        .I3(pass_open_bank_r_lcl_reg_1),
        .I4(pre_wait_r),
        .I5(pass_open_bank_r_lcl_reg_2),
        .O(pass_open_bank_ns));
  FDRE pass_open_bank_r_lcl_reg
       (.C(\order_q_r_reg[1]_0 ),
        .CE(1'b1),
        .D(pass_open_bank_ns),
        .Q(pass_open_bank_r_lcl_reg_0),
        .R(1'b0));
  FDRE pre_bm_end_r_reg
       (.C(\order_q_r_reg[1]_0 ),
        .CE(1'b1),
        .D(pre_bm_end_ns),
        .Q(pre_bm_end_r),
        .R(1'b0));
  FDRE pre_passing_open_bank_r_reg
       (.C(\order_q_r_reg[1]_0 ),
        .CE(1'b1),
        .D(pre_passing_open_bank_ns),
        .Q(pre_passing_open_bank_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hAA3CFFFFAA3C0000)) 
    \q_entry_r[0]_i_1 
       (.I0(\q_entry_r[0]_i_2__1_n_0 ),
        .I1(\q_entry_r_reg[0]_2 ),
        .I2(\q_entry_r_reg[0]_3 ),
        .I3(pre_bm_end_r_reg_0),
        .I4(\q_entry_r_reg[1]_2 ),
        .I5(\q_entry_r_reg[0]_0 ),
        .O(\q_entry_r[0]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h909F)) 
    \q_entry_r[0]_i_2__1 
       (.I0(head_r_lcl_reg_3),
        .I1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1 ),
        .I2(\order_q_r_reg[1]_1 ),
        .I3(\q_entry_r_reg[0]_0 ),
        .O(\q_entry_r[0]_i_2__1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \q_entry_r[1]_i_1 
       (.I0(q_entry_ns),
        .I1(\q_entry_r_reg[1]_2 ),
        .I2(\q_entry_r_reg[1]_0 ),
        .O(\q_entry_r[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hA9A9A9A9FF0000FF)) 
    \q_entry_r[1]_i_3__1 
       (.I0(head_r_lcl_reg_4),
        .I1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1 ),
        .I2(head_r_lcl_reg_3),
        .I3(\q_entry_r_reg[1]_0 ),
        .I4(\q_entry_r_reg[0]_0 ),
        .I5(\order_q_r_reg[1]_1 ),
        .O(\q_entry_r_reg[1]_1 ));
  FDSE \q_entry_r_reg[0] 
       (.C(\order_q_r_reg[1]_0 ),
        .CE(1'b1),
        .D(\q_entry_r[0]_i_1_n_0 ),
        .Q(\q_entry_r_reg[0]_0 ),
        .S(head_r_lcl_reg_1));
  FDRE \q_entry_r_reg[1] 
       (.C(\order_q_r_reg[1]_0 ),
        .CE(1'b1),
        .D(\q_entry_r[1]_i_1_n_0 ),
        .Q(\q_entry_r_reg[1]_0 ),
        .R(head_r_lcl_reg_1));
  FDRE q_has_priority_r_reg
       (.C(\order_q_r_reg[1]_0 ),
        .CE(1'b1),
        .D(q_has_priority_r_reg_0),
        .Q(q_has_priority),
        .R(auto_pre_r_lcl_reg_1));
  FDRE q_has_rd_r_reg
       (.C(\order_q_r_reg[1]_0 ),
        .CE(1'b1),
        .D(q_has_rd_r_reg_0),
        .Q(q_has_rd_3),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair1168" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ras_timer_r[0]_i_1__2 
       (.I0(\ras_timer_r[0]_i_2__1_n_0 ),
        .I1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_2 ),
        .I2(\ras_timer_r_reg[0] ),
        .O(D[0]));
  LUT6 #(
    .INIT(64'hBBBB8888B888B888)) 
    \ras_timer_r[0]_i_2__1 
       (.I0(\ras_timer_r_reg[0]_4 ),
        .I1(rb_hit_busies_r_1),
        .I2(\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ),
        .I3(\ras_timer_r_reg[0]_5 ),
        .I4(\ras_timer_r_reg[0]_6 ),
        .I5(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ),
        .O(\ras_timer_r[0]_i_2__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1168" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ras_timer_r[1]_i_1__2 
       (.I0(\ras_timer_r[1]_i_2__1_n_0 ),
        .I1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_2 ),
        .I2(\ras_timer_r_reg[1] ),
        .O(D[1]));
  LUT6 #(
    .INIT(64'hB8BBB888B888B888)) 
    \ras_timer_r[1]_i_2__1 
       (.I0(\ras_timer_r_reg[1]_0 ),
        .I1(rb_hit_busies_r_1),
        .I2(\ras_timer_r_reg[1]_1 ),
        .I3(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ),
        .I4(\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ),
        .I5(\ras_timer_r_reg[1]_2 ),
        .O(\ras_timer_r[1]_i_2__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1167" *) 
  LUT4 #(
    .INIT(16'hF022)) 
    \rb_hit_busies.rb_hit_busies_r_lcl[2]_i_1__0 
       (.I0(\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_3 ),
        .I1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_4 ),
        .I2(\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ),
        .I3(idle_r_lcl_reg_1),
        .O(\rb_hit_busies.rb_hit_busies_r_lcl[2]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'hF022)) 
    \rb_hit_busies.rb_hit_busies_r_lcl[3]_i_1__1 
       (.I0(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 ),
        .I1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2 ),
        .I2(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ),
        .I3(idle_r_lcl_reg_1),
        .O(\rb_hit_busies.rb_hit_busies_r_lcl[3]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1166" *) 
  LUT4 #(
    .INIT(16'hF022)) 
    \rb_hit_busies.rb_hit_busies_r_lcl[4]_i_2 
       (.I0(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ),
        .I1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ),
        .I2(rb_hit_busies_r_1),
        .I3(idle_r_lcl_reg_1),
        .O(\rb_hit_busies.rb_hit_busies_r_lcl[4]_i_2_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2] 
       (.C(\order_q_r_reg[1]_0 ),
        .CE(1'b1),
        .D(\rb_hit_busies.rb_hit_busies_r_lcl[2]_i_1__0_n_0 ),
        .Q(\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ),
        .R(\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_5 ));
  FDRE #(
    .INIT(1'b0)) 
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3] 
       (.C(\order_q_r_reg[1]_0 ),
        .CE(1'b1),
        .D(\rb_hit_busies.rb_hit_busies_r_lcl[3]_i_1__1_n_0 ),
        .Q(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ),
        .R(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_3 ));
  FDRE #(
    .INIT(1'b0)) 
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4] 
       (.C(\order_q_r_reg[1]_0 ),
        .CE(1'b1),
        .D(\rb_hit_busies.rb_hit_busies_r_lcl[4]_i_2_n_0 ),
        .Q(rb_hit_busies_r_1),
        .R(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1167" *) 
  LUT2 #(
    .INIT(4'h2)) 
    rb_hit_busy_r_i_1
       (.I0(idle_r_lcl_reg_1),
        .I1(rb_hit_busy_r_reg),
        .O(p_106_out));
  LUT4 #(
    .INIT(16'h00A2)) 
    req_bank_rdy_r_i_1__1
       (.I0(req_bank_rdy_r_reg_0),
        .I1(order_q_r[0]),
        .I2(req_bank_rdy_r_reg),
        .I3(order_q_r[1]),
        .O(req_bank_rdy_ns));
  FDRE wait_for_maint_r_lcl_reg
       (.C(\order_q_r_reg[1]_0 ),
        .CE(1'b1),
        .D(wait_for_maint_r_lcl_reg_1),
        .Q(wait_for_maint_r_13),
        .R(wait_for_maint_r_lcl_reg_0));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_bank_queue" *) 
module mig_mig_7series_v4_2_bank_queue__parameterized1
   (idle_r_lcl_reg_0,
    E,
    pass_open_bank_r,
    pass_open_bank_ns,
    q_has_rd_7,
    q_has_priority,
    pass_open_bank_r_lcl_reg_0,
    wait_for_maint_r_14,
    head_r_lcl_reg_0,
    ordered_r_lcl_reg_0,
    tail_r_17,
    auto_pre_r_lcl_reg_0,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ,
    idle_r_lcl_reg_1,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ,
    rd_wr_r_lcl_reg,
    D,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 ,
    \q_entry_r_reg[1]_0 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1 ,
    \q_entry_r_reg[1]_1 ,
    \q_entry_r_reg[0]_0 ,
    pre_bm_end_r_reg_0,
    \q_entry_r_reg[0]_1 ,
    idle_r_lcl_reg_2,
    \order_q_r_reg[0]_0 ,
    \order_q_r_reg[1]_0 ,
    req_bank_rdy_ns,
    p_67_out,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[6] ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ,
    pre_passing_open_bank_r_reg_0,
    \compute_tail.tail_r_lcl_reg_0 ,
    act_wait_r_lcl_reg,
    q_has_rd_r_reg_0,
    pre_bm_end_ns,
    pre_passing_open_bank_ns,
    q_has_rd_r_reg_1,
    q_has_priority_r_reg_0,
    wait_for_maint_r_lcl_reg_0,
    wait_for_maint_r_lcl_reg_1,
    head_r_lcl_reg_1,
    head_r_lcl_reg_2,
    ordered_r_lcl_reg_1,
    \compute_tail.tail_r_lcl_reg_1 ,
    auto_pre_r_lcl_reg_1,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_2 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_3 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_3 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 ,
    granted_col_r_reg,
    granted_col_r_reg_0,
    q_has_priority_r_reg_1,
    granted_col_r_reg_1,
    granted_col_r_reg_2,
    \ras_timer_r_reg[0] ,
    \ras_timer_r_reg[1] ,
    \ras_timer_r_reg[0]_0 ,
    \ras_timer_r_reg[0]_1 ,
    \ras_timer_r_reg[0]_2 ,
    \ras_timer_r_reg[0]_3 ,
    head_r_lcl_reg_3,
    head_r_lcl_reg_4,
    \order_q_r_reg[1]_1 ,
    head_r_lcl_reg_5,
    \q_entry_r_reg[1]_2 ,
    i___5_i_4,
    i___5_i_4_0,
    i___5_i_4_1,
    req_bank_rdy_r_reg,
    req_priority_r,
    \grant_r[3]_i_3_0 ,
    \grant_r[3]_i_3_1 ,
    \grant_r[3]_i_3_2 ,
    \grant_r[3]_i_3_3 ,
    rnk_config_valid_r_lcl_reg,
    rnk_config_valid_r_lcl_reg_0,
    req_bank_rdy_r_reg_0,
    rb_hit_busy_r_reg,
    use_addr,
    rb_hit_busy_r_reg_0,
    rb_hit_busy_r_reg_1,
    \ras_timer_r_reg[1]_0 ,
    \ras_timer_r_reg[1]_1 ,
    \ras_timer_r_reg[1]_2 ,
    \ras_timer_r_reg[0]_4 ,
    \ras_timer_r_reg[0]_5 ,
    \ras_timer_r_reg[0]_6 ,
    \grant_r[3]_i_6 ,
    Q,
    q_has_priority_r_reg_2,
    rb_hit_busies_r_0,
    rb_hit_busies_r_1,
    pass_open_bank_r_lcl_reg_1,
    pre_wait_r,
    pass_open_bank_r_lcl_reg_2,
    q_has_priority_r_reg_3,
    auto_pre_r_lcl_reg_2,
    auto_pre_r_lcl_reg_3,
    \grant_r[3]_i_2__0 ,
    ras_timer_zero_r,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_4 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_4 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_3 ,
    \q_entry_r_reg[1]_3 ,
    \q_entry_r_reg[1]_4 ,
    \q_entry_r_reg[0]_2 ,
    \order_q_r_reg[1]_2 ,
    \order_q_r_reg[0]_1 );
  output idle_r_lcl_reg_0;
  output [0:0]E;
  output pass_open_bank_r;
  output pass_open_bank_ns;
  output q_has_rd_7;
  output q_has_priority;
  output pass_open_bank_r_lcl_reg_0;
  output wait_for_maint_r_14;
  output head_r_lcl_reg_0;
  output ordered_r_lcl_reg_0;
  output tail_r_17;
  output auto_pre_r_lcl_reg_0;
  output \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ;
  output idle_r_lcl_reg_1;
  output \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ;
  output \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ;
  output rd_wr_r_lcl_reg;
  output [1:0]D;
  output \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 ;
  output \q_entry_r_reg[1]_0 ;
  output \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1 ;
  output \q_entry_r_reg[1]_1 ;
  output \q_entry_r_reg[0]_0 ;
  output pre_bm_end_r_reg_0;
  output \q_entry_r_reg[0]_1 ;
  output idle_r_lcl_reg_2;
  output \order_q_r_reg[0]_0 ;
  output \order_q_r_reg[1]_0 ;
  output req_bank_rdy_ns;
  output p_67_out;
  output \rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ;
  output \rb_hit_busies.rb_hit_busies_r_lcl_reg[6] ;
  output \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ;
  output pre_passing_open_bank_r_reg_0;
  output \compute_tail.tail_r_lcl_reg_0 ;
  output act_wait_r_lcl_reg;
  input q_has_rd_r_reg_0;
  input pre_bm_end_ns;
  input pre_passing_open_bank_ns;
  input q_has_rd_r_reg_1;
  input q_has_priority_r_reg_0;
  input wait_for_maint_r_lcl_reg_0;
  input wait_for_maint_r_lcl_reg_1;
  input head_r_lcl_reg_1;
  input head_r_lcl_reg_2;
  input ordered_r_lcl_reg_1;
  input \compute_tail.tail_r_lcl_reg_1 ;
  input auto_pre_r_lcl_reg_1;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_2 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_3 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_3 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 ;
  input granted_col_r_reg;
  input granted_col_r_reg_0;
  input q_has_priority_r_reg_1;
  input granted_col_r_reg_1;
  input granted_col_r_reg_2;
  input \ras_timer_r_reg[0] ;
  input \ras_timer_r_reg[1] ;
  input \ras_timer_r_reg[0]_0 ;
  input \ras_timer_r_reg[0]_1 ;
  input \ras_timer_r_reg[0]_2 ;
  input \ras_timer_r_reg[0]_3 ;
  input head_r_lcl_reg_3;
  input head_r_lcl_reg_4;
  input \order_q_r_reg[1]_1 ;
  input head_r_lcl_reg_5;
  input \q_entry_r_reg[1]_2 ;
  input i___5_i_4;
  input i___5_i_4_0;
  input i___5_i_4_1;
  input req_bank_rdy_r_reg;
  input req_priority_r;
  input \grant_r[3]_i_3_0 ;
  input \grant_r[3]_i_3_1 ;
  input \grant_r[3]_i_3_2 ;
  input \grant_r[3]_i_3_3 ;
  input rnk_config_valid_r_lcl_reg;
  input rnk_config_valid_r_lcl_reg_0;
  input req_bank_rdy_r_reg_0;
  input rb_hit_busy_r_reg;
  input use_addr;
  input rb_hit_busy_r_reg_0;
  input rb_hit_busy_r_reg_1;
  input \ras_timer_r_reg[1]_0 ;
  input \ras_timer_r_reg[1]_1 ;
  input \ras_timer_r_reg[1]_2 ;
  input \ras_timer_r_reg[0]_4 ;
  input \ras_timer_r_reg[0]_5 ;
  input \ras_timer_r_reg[0]_6 ;
  input [0:0]\grant_r[3]_i_6 ;
  input [0:0]Q;
  input q_has_priority_r_reg_2;
  input [0:0]rb_hit_busies_r_0;
  input [0:0]rb_hit_busies_r_1;
  input pass_open_bank_r_lcl_reg_1;
  input pre_wait_r;
  input pass_open_bank_r_lcl_reg_2;
  input q_has_priority_r_reg_3;
  input auto_pre_r_lcl_reg_2;
  input auto_pre_r_lcl_reg_3;
  input \grant_r[3]_i_2__0 ;
  input ras_timer_zero_r;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_4 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_4 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_3 ;
  input \q_entry_r_reg[1]_3 ;
  input \q_entry_r_reg[1]_4 ;
  input \q_entry_r_reg[0]_2 ;
  input \order_q_r_reg[1]_2 ;
  input \order_q_r_reg[0]_1 ;

  wire [1:0]D;
  wire [0:0]E;
  wire [0:0]Q;
  wire act_wait_r_lcl_reg;
  wire auto_pre_r_lcl_reg_0;
  wire auto_pre_r_lcl_reg_1;
  wire auto_pre_r_lcl_reg_2;
  wire auto_pre_r_lcl_reg_3;
  wire \compute_tail.tail_r_lcl_reg_0 ;
  wire \compute_tail.tail_r_lcl_reg_1 ;
  wire \grant_r[3]_i_10_n_0 ;
  wire \grant_r[3]_i_2__0 ;
  wire \grant_r[3]_i_3_0 ;
  wire \grant_r[3]_i_3_1 ;
  wire \grant_r[3]_i_3_2 ;
  wire \grant_r[3]_i_3_3 ;
  wire [0:0]\grant_r[3]_i_6 ;
  wire granted_col_r_reg;
  wire granted_col_r_reg_0;
  wire granted_col_r_reg_1;
  wire granted_col_r_reg_2;
  wire head_r_lcl_reg_0;
  wire head_r_lcl_reg_1;
  wire head_r_lcl_reg_2;
  wire head_r_lcl_reg_3;
  wire head_r_lcl_reg_4;
  wire head_r_lcl_reg_5;
  wire i___5_i_4;
  wire i___5_i_4_0;
  wire i___5_i_4_1;
  wire idle_r_lcl_reg_0;
  wire idle_r_lcl_reg_1;
  wire idle_r_lcl_reg_2;
  wire [1:0]order_q_r;
  wire \order_q_r[0]_i_1_n_0 ;
  wire \order_q_r[1]_i_1_n_0 ;
  wire \order_q_r_reg[0]_0 ;
  wire \order_q_r_reg[0]_1 ;
  wire \order_q_r_reg[1]_0 ;
  wire \order_q_r_reg[1]_1 ;
  wire \order_q_r_reg[1]_2 ;
  wire ordered_r_lcl_reg_0;
  wire ordered_r_lcl_reg_1;
  wire p_67_out;
  wire pass_open_bank_ns;
  wire pass_open_bank_r;
  wire pass_open_bank_r_lcl_reg_0;
  wire pass_open_bank_r_lcl_reg_1;
  wire pass_open_bank_r_lcl_reg_2;
  wire pre_bm_end_ns;
  wire pre_bm_end_r;
  wire pre_bm_end_r_reg_0;
  wire pre_passing_open_bank_ns;
  wire pre_passing_open_bank_r;
  wire pre_passing_open_bank_r_reg_0;
  wire pre_wait_r;
  wire \q_entry_r[0]_i_1_n_0 ;
  wire \q_entry_r[0]_i_2__0_n_0 ;
  wire \q_entry_r[1]_i_1_n_0 ;
  wire \q_entry_r_reg[0]_0 ;
  wire \q_entry_r_reg[0]_1 ;
  wire \q_entry_r_reg[0]_2 ;
  wire \q_entry_r_reg[1]_0 ;
  wire \q_entry_r_reg[1]_1 ;
  wire \q_entry_r_reg[1]_2 ;
  wire \q_entry_r_reg[1]_3 ;
  wire \q_entry_r_reg[1]_4 ;
  wire q_has_priority;
  wire q_has_priority_r_reg_0;
  wire q_has_priority_r_reg_1;
  wire q_has_priority_r_reg_2;
  wire q_has_priority_r_reg_3;
  wire q_has_rd_7;
  wire q_has_rd_r_reg_0;
  wire q_has_rd_r_reg_1;
  wire \ras_timer_r[0]_i_2__0_n_0 ;
  wire \ras_timer_r[1]_i_2__0_n_0 ;
  wire \ras_timer_r_reg[0] ;
  wire \ras_timer_r_reg[0]_0 ;
  wire \ras_timer_r_reg[0]_1 ;
  wire \ras_timer_r_reg[0]_2 ;
  wire \ras_timer_r_reg[0]_3 ;
  wire \ras_timer_r_reg[0]_4 ;
  wire \ras_timer_r_reg[0]_5 ;
  wire \ras_timer_r_reg[0]_6 ;
  wire \ras_timer_r_reg[1] ;
  wire \ras_timer_r_reg[1]_0 ;
  wire \ras_timer_r_reg[1]_1 ;
  wire \ras_timer_r_reg[1]_2 ;
  wire ras_timer_zero_r;
  wire \rb_hit_busies.rb_hit_busies_r_lcl[3]_i_1_n_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl[4]_i_1__0_n_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl[5]_i_1__0_n_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_3 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_4 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_3 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_2 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_3 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_4 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[6] ;
  wire [0:0]rb_hit_busies_r_0;
  wire [0:0]rb_hit_busies_r_1;
  wire rb_hit_busy_r_reg;
  wire rb_hit_busy_r_reg_0;
  wire rb_hit_busy_r_reg_1;
  wire rd_wr_r_lcl_reg;
  wire req_bank_rdy_ns;
  wire req_bank_rdy_r_reg;
  wire req_bank_rdy_r_reg_0;
  wire req_priority_r;
  wire rnk_config_valid_r_lcl_reg;
  wire rnk_config_valid_r_lcl_reg_0;
  wire tail_r_17;
  wire use_addr;
  wire wait_for_maint_r_14;
  wire wait_for_maint_r_lcl_reg_0;
  wire wait_for_maint_r_lcl_reg_1;

  FDRE auto_pre_r_lcl_reg
       (.C(q_has_rd_r_reg_0),
        .CE(1'b1),
        .D(auto_pre_r_lcl_reg_1),
        .Q(auto_pre_r_lcl_reg_0),
        .R(pass_open_bank_r_lcl_reg_0));
  LUT5 #(
    .INIT(32'hBFAAAAAA)) 
    bm_end_r1_i_1__1
       (.I0(pre_bm_end_r),
        .I1(q_has_priority_r_reg_2),
        .I2(q_has_priority_r_reg_1),
        .I3(Q),
        .I4(pass_open_bank_r),
        .O(pre_bm_end_r_reg_0));
  FDRE #(
    .INIT(1'b1)) 
    \compute_tail.tail_r_lcl_reg 
       (.C(q_has_rd_r_reg_0),
        .CE(1'b1),
        .D(\compute_tail.tail_r_lcl_reg_1 ),
        .Q(tail_r_17),
        .R(head_r_lcl_reg_1));
  LUT5 #(
    .INIT(32'hF2F2F2FF)) 
    demand_priority_r_i_2__0
       (.I0(order_q_r[0]),
        .I1(req_bank_rdy_r_reg),
        .I2(order_q_r[1]),
        .I3(q_has_priority),
        .I4(req_priority_r),
        .O(\order_q_r_reg[0]_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF2000)) 
    \grant_r[3]_i_10 
       (.I0(order_q_r[0]),
        .I1(\grant_r[3]_i_3_0 ),
        .I2(\grant_r[3]_i_3_1 ),
        .I3(\grant_r[3]_i_3_2 ),
        .I4(order_q_r[1]),
        .I5(\grant_r[3]_i_3_3 ),
        .O(\grant_r[3]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAA00808080)) 
    \grant_r[3]_i_13 
       (.I0(\grant_r[3]_i_6 ),
        .I1(pass_open_bank_r),
        .I2(Q),
        .I3(q_has_priority_r_reg_1),
        .I4(q_has_priority_r_reg_2),
        .I5(pre_passing_open_bank_r),
        .O(\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] ));
  LUT6 #(
    .INIT(64'hAAAAAAAA00808080)) 
    \grant_r[3]_i_20 
       (.I0(rb_hit_busies_r_0),
        .I1(pass_open_bank_r),
        .I2(Q),
        .I3(q_has_priority_r_reg_1),
        .I4(q_has_priority_r_reg_2),
        .I5(pre_passing_open_bank_r),
        .O(\rb_hit_busies.rb_hit_busies_r_lcl_reg[6] ));
  LUT6 #(
    .INIT(64'hFFFFFFBAFFFFFFBF)) 
    \grant_r[3]_i_3 
       (.I0(granted_col_r_reg),
        .I1(granted_col_r_reg_0),
        .I2(q_has_priority_r_reg_1),
        .I3(\grant_r[3]_i_10_n_0 ),
        .I4(granted_col_r_reg_1),
        .I5(granted_col_r_reg_2),
        .O(rd_wr_r_lcl_reg));
  LUT5 #(
    .INIT(32'hFFDFFFFF)) 
    \grant_r[3]_i_4__1 
       (.I0(\grant_r[3]_i_2__0 ),
        .I1(idle_r_lcl_reg_0),
        .I2(head_r_lcl_reg_0),
        .I3(wait_for_maint_r_14),
        .I4(ras_timer_zero_r),
        .O(act_wait_r_lcl_reg));
  FDRE head_r_lcl_reg
       (.C(q_has_rd_r_reg_0),
        .CE(1'b1),
        .D(head_r_lcl_reg_2),
        .Q(head_r_lcl_reg_0),
        .R(head_r_lcl_reg_1));
  LUT5 #(
    .INIT(32'h40555555)) 
    i___25_i_2
       (.I0(pre_passing_open_bank_r),
        .I1(q_has_priority_r_reg_2),
        .I2(q_has_priority_r_reg_1),
        .I3(Q),
        .I4(pass_open_bank_r),
        .O(pre_passing_open_bank_r_reg_0));
  LUT6 #(
    .INIT(64'hAAAAAAAA00808080)) 
    i___28_i_3
       (.I0(rb_hit_busies_r_1),
        .I1(pass_open_bank_r),
        .I2(Q),
        .I3(q_has_priority_r_reg_1),
        .I4(q_has_priority_r_reg_2),
        .I5(pre_passing_open_bank_r),
        .O(\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 ));
  LUT6 #(
    .INIT(64'h00000000F4F4FFF4)) 
    i___30_i_1
       (.I0(\ras_timer_r_reg[0]_0 ),
        .I1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ),
        .I2(\ras_timer_r_reg[0]_1 ),
        .I3(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ),
        .I4(\ras_timer_r_reg[0]_2 ),
        .I5(\ras_timer_r_reg[0]_3 ),
        .O(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 ));
  LUT6 #(
    .INIT(64'hFDFFFDFDFFFFFFFF)) 
    i___40_i_3
       (.I0(rnk_config_valid_r_lcl_reg),
        .I1(rnk_config_valid_r_lcl_reg_0),
        .I2(order_q_r[1]),
        .I3(req_bank_rdy_r_reg),
        .I4(order_q_r[0]),
        .I5(req_bank_rdy_r_reg_0),
        .O(\order_q_r_reg[1]_0 ));
  LUT6 #(
    .INIT(64'h00000000FD555555)) 
    i___46_i_1
       (.I0(idle_r_lcl_reg_0),
        .I1(use_addr),
        .I2(rb_hit_busy_r_reg_0),
        .I3(head_r_lcl_reg_0),
        .I4(rb_hit_busy_r_reg_1),
        .I5(pass_open_bank_r_lcl_reg_0),
        .O(idle_r_lcl_reg_1));
  LUT6 #(
    .INIT(64'h1400140014FF1400)) 
    i___5_i_1
       (.I0(head_r_lcl_reg_3),
        .I1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1 ),
        .I2(head_r_lcl_reg_4),
        .I3(head_r_lcl_reg_5),
        .I4(\q_entry_r_reg[0]_0 ),
        .I5(\q_entry_r_reg[1]_1 ),
        .O(\q_entry_r_reg[0]_1 ));
  LUT5 #(
    .INIT(32'hFFFAFBFB)) 
    i___5_i_2
       (.I0(pre_bm_end_r_reg_0),
        .I1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1 ),
        .I2(\order_q_r_reg[1]_1 ),
        .I3(\q_entry_r_reg[1]_2 ),
        .I4(idle_r_lcl_reg_0),
        .O(idle_r_lcl_reg_2));
  LUT6 #(
    .INIT(64'h0DDD0DDD00000DDD)) 
    i___5_i_3
       (.I0(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ),
        .I1(i___5_i_4),
        .I2(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ),
        .I3(i___5_i_4_0),
        .I4(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ),
        .I5(i___5_i_4_1),
        .O(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1 ));
  LUT5 #(
    .INIT(32'h5777FFFF)) 
    i___63_i_2
       (.I0(tail_r_17),
        .I1(rb_hit_busy_r_reg_0),
        .I2(auto_pre_r_lcl_reg_2),
        .I3(use_addr),
        .I4(auto_pre_r_lcl_reg_3),
        .O(\compute_tail.tail_r_lcl_reg_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1173" *) 
  LUT1 #(
    .INIT(2'h1)) 
    idle_r_lcl_i_1__1
       (.I0(idle_r_lcl_reg_1),
        .O(E));
  FDRE idle_r_lcl_reg
       (.C(q_has_rd_r_reg_0),
        .CE(1'b1),
        .D(E),
        .Q(idle_r_lcl_reg_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0D550C000D550CF0)) 
    \order_q_r[0]_i_1 
       (.I0(\order_q_r_reg[0]_1 ),
        .I1(order_q_r[1]),
        .I2(order_q_r[0]),
        .I3(req_bank_rdy_r_reg),
        .I4(\order_q_r_reg[1]_1 ),
        .I5(q_has_priority_r_reg_3),
        .O(\order_q_r[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hC2AAC000C2AAC0CC)) 
    \order_q_r[1]_i_1 
       (.I0(\order_q_r_reg[1]_2 ),
        .I1(order_q_r[1]),
        .I2(order_q_r[0]),
        .I3(req_bank_rdy_r_reg),
        .I4(\order_q_r_reg[1]_1 ),
        .I5(q_has_priority_r_reg_3),
        .O(\order_q_r[1]_i_1_n_0 ));
  FDRE \order_q_r_reg[0] 
       (.C(q_has_rd_r_reg_0),
        .CE(1'b1),
        .D(\order_q_r[0]_i_1_n_0 ),
        .Q(order_q_r[0]),
        .R(1'b0));
  FDRE \order_q_r_reg[1] 
       (.C(q_has_rd_r_reg_0),
        .CE(1'b1),
        .D(\order_q_r[1]_i_1_n_0 ),
        .Q(order_q_r[1]),
        .R(1'b0));
  FDRE ordered_r_lcl_reg
       (.C(q_has_rd_r_reg_0),
        .CE(1'b1),
        .D(ordered_r_lcl_reg_1),
        .Q(ordered_r_lcl_reg_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h4444544444444444)) 
    pass_open_bank_r_lcl_i_1__1
       (.I0(pass_open_bank_r_lcl_reg_0),
        .I1(pass_open_bank_r),
        .I2(tail_r_17),
        .I3(pass_open_bank_r_lcl_reg_1),
        .I4(pre_wait_r),
        .I5(pass_open_bank_r_lcl_reg_2),
        .O(pass_open_bank_ns));
  FDRE pass_open_bank_r_lcl_reg
       (.C(q_has_rd_r_reg_0),
        .CE(1'b1),
        .D(pass_open_bank_ns),
        .Q(pass_open_bank_r),
        .R(1'b0));
  FDRE pre_bm_end_r_reg
       (.C(q_has_rd_r_reg_0),
        .CE(1'b1),
        .D(pre_bm_end_ns),
        .Q(pre_bm_end_r),
        .R(1'b0));
  FDRE pre_passing_open_bank_r_reg
       (.C(q_has_rd_r_reg_0),
        .CE(1'b1),
        .D(pre_passing_open_bank_ns),
        .Q(pre_passing_open_bank_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFF48FFFFFF480000)) 
    \q_entry_r[0]_i_1 
       (.I0(\q_entry_r_reg[1]_2 ),
        .I1(pre_bm_end_r_reg_0),
        .I2(\q_entry_r_reg[0]_2 ),
        .I3(\q_entry_r[0]_i_2__0_n_0 ),
        .I4(idle_r_lcl_reg_2),
        .I5(\q_entry_r_reg[0]_0 ),
        .O(\q_entry_r[0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h0000990F)) 
    \q_entry_r[0]_i_2__0 
       (.I0(head_r_lcl_reg_4),
        .I1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1 ),
        .I2(\q_entry_r_reg[0]_0 ),
        .I3(\order_q_r_reg[1]_1 ),
        .I4(pre_bm_end_r_reg_0),
        .O(\q_entry_r[0]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'hBF80FFFFBF800000)) 
    \q_entry_r[1]_i_1 
       (.I0(\q_entry_r_reg[1]_3 ),
        .I1(pre_bm_end_r_reg_0),
        .I2(\q_entry_r_reg[1]_2 ),
        .I3(\q_entry_r_reg[1]_4 ),
        .I4(idle_r_lcl_reg_2),
        .I5(\q_entry_r_reg[1]_1 ),
        .O(\q_entry_r[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h560056FF56FF5600)) 
    \q_entry_r[1]_i_4__0 
       (.I0(head_r_lcl_reg_3),
        .I1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1 ),
        .I2(head_r_lcl_reg_4),
        .I3(\order_q_r_reg[1]_1 ),
        .I4(\q_entry_r_reg[1]_1 ),
        .I5(\q_entry_r_reg[0]_0 ),
        .O(\q_entry_r_reg[1]_0 ));
  FDRE \q_entry_r_reg[0] 
       (.C(q_has_rd_r_reg_0),
        .CE(1'b1),
        .D(\q_entry_r[0]_i_1_n_0 ),
        .Q(\q_entry_r_reg[0]_0 ),
        .R(head_r_lcl_reg_1));
  FDSE \q_entry_r_reg[1] 
       (.C(q_has_rd_r_reg_0),
        .CE(1'b1),
        .D(\q_entry_r[1]_i_1_n_0 ),
        .Q(\q_entry_r_reg[1]_1 ),
        .S(head_r_lcl_reg_1));
  FDRE q_has_priority_r_reg
       (.C(q_has_rd_r_reg_0),
        .CE(1'b1),
        .D(q_has_priority_r_reg_0),
        .Q(q_has_priority),
        .R(pass_open_bank_r_lcl_reg_0));
  FDRE q_has_rd_r_reg
       (.C(q_has_rd_r_reg_0),
        .CE(1'b1),
        .D(q_has_rd_r_reg_1),
        .Q(q_has_rd_7),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair1175" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ras_timer_r[0]_i_1__1 
       (.I0(\ras_timer_r[0]_i_2__0_n_0 ),
        .I1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 ),
        .I2(\ras_timer_r_reg[0] ),
        .O(D[0]));
  LUT6 #(
    .INIT(64'hB8BBB888B888B888)) 
    \ras_timer_r[0]_i_2__0 
       (.I0(\ras_timer_r_reg[0]_4 ),
        .I1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ),
        .I2(\ras_timer_r_reg[0]_5 ),
        .I3(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ),
        .I4(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ),
        .I5(\ras_timer_r_reg[0]_6 ),
        .O(\ras_timer_r[0]_i_2__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1175" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ras_timer_r[1]_i_1__1 
       (.I0(\ras_timer_r[1]_i_2__0_n_0 ),
        .I1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 ),
        .I2(\ras_timer_r_reg[1] ),
        .O(D[1]));
  LUT6 #(
    .INIT(64'hB8BBB888B888B888)) 
    \ras_timer_r[1]_i_2__0 
       (.I0(\ras_timer_r_reg[1]_0 ),
        .I1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ),
        .I2(\ras_timer_r_reg[1]_1 ),
        .I3(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ),
        .I4(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ),
        .I5(\ras_timer_r_reg[1]_2 ),
        .O(\ras_timer_r[1]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFAAEAEAEA)) 
    \rb_hit_busies.rb_hit_busies_r_lcl[2]_i_1 
       (.I0(q_has_priority_r_reg_3),
        .I1(pass_open_bank_r),
        .I2(Q),
        .I3(q_has_priority_r_reg_1),
        .I4(q_has_priority_r_reg_2),
        .I5(pre_bm_end_r),
        .O(pass_open_bank_r_lcl_reg_0));
  LUT4 #(
    .INIT(16'hF022)) 
    \rb_hit_busies.rb_hit_busies_r_lcl[3]_i_1 
       (.I0(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_2 ),
        .I1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_3 ),
        .I2(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ),
        .I3(idle_r_lcl_reg_1),
        .O(\rb_hit_busies.rb_hit_busies_r_lcl[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1173" *) 
  LUT4 #(
    .INIT(16'hF022)) 
    \rb_hit_busies.rb_hit_busies_r_lcl[4]_i_1__0 
       (.I0(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ),
        .I1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 ),
        .I2(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ),
        .I3(idle_r_lcl_reg_1),
        .O(\rb_hit_busies.rb_hit_busies_r_lcl[4]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1174" *) 
  LUT4 #(
    .INIT(16'hF022)) 
    \rb_hit_busies.rb_hit_busies_r_lcl[5]_i_1__0 
       (.I0(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_2 ),
        .I1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_3 ),
        .I2(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ),
        .I3(idle_r_lcl_reg_1),
        .O(\rb_hit_busies.rb_hit_busies_r_lcl[5]_i_1__0_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3] 
       (.C(q_has_rd_r_reg_0),
        .CE(1'b1),
        .D(\rb_hit_busies.rb_hit_busies_r_lcl[3]_i_1_n_0 ),
        .Q(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ),
        .R(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_4 ));
  FDRE #(
    .INIT(1'b0)) 
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4] 
       (.C(q_has_rd_r_reg_0),
        .CE(1'b1),
        .D(\rb_hit_busies.rb_hit_busies_r_lcl[4]_i_1__0_n_0 ),
        .Q(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ),
        .R(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_3 ));
  FDRE #(
    .INIT(1'b0)) 
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5] 
       (.C(q_has_rd_r_reg_0),
        .CE(1'b1),
        .D(\rb_hit_busies.rb_hit_busies_r_lcl[5]_i_1__0_n_0 ),
        .Q(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ),
        .R(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1174" *) 
  LUT2 #(
    .INIT(4'h2)) 
    rb_hit_busy_r_i_1__1
       (.I0(idle_r_lcl_reg_1),
        .I1(rb_hit_busy_r_reg),
        .O(p_67_out));
  LUT4 #(
    .INIT(16'h00A2)) 
    req_bank_rdy_r_i_1__0
       (.I0(req_bank_rdy_r_reg_0),
        .I1(order_q_r[0]),
        .I2(req_bank_rdy_r_reg),
        .I3(order_q_r[1]),
        .O(req_bank_rdy_ns));
  FDRE wait_for_maint_r_lcl_reg
       (.C(q_has_rd_r_reg_0),
        .CE(1'b1),
        .D(wait_for_maint_r_lcl_reg_1),
        .Q(wait_for_maint_r_14),
        .R(wait_for_maint_r_lcl_reg_0));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_bank_queue" *) 
module mig_mig_7series_v4_2_bank_queue__parameterized2
   (idle_r_lcl_reg_0,
    E,
    pass_open_bank_r_lcl_reg_0,
    pass_open_bank_ns,
    pre_bm_end_r_11,
    q_has_rd_12,
    q_has_priority,
    wait_for_maint_r_15,
    head_r_lcl_reg_0,
    ordered_r_lcl_reg_0,
    tail_r_18,
    auto_pre_r_lcl_reg_0,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ,
    idle_r_lcl_reg_1,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0 ,
    rd_wr_r_lcl_reg,
    D,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_1 ,
    pre_bm_end_r_reg_0,
    pre_bm_end_r_reg_1,
    \q_entry_r_reg[1]_0 ,
    \q_entry_r_reg[0]_0 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ,
    \q_entry_r_reg[0]_1 ,
    pre_bm_end_r_reg_2,
    \order_q_r_reg[0]_0 ,
    req_bank_rdy_ns,
    p_28_out,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 ,
    pre_passing_open_bank_r_reg_0,
    p_13_out,
    \compute_tail.tail_r_lcl_reg_0 ,
    act_wait_r_lcl_reg,
    \order_q_r_reg[1]_0 ,
    pre_bm_end_ns,
    pre_passing_open_bank_ns,
    q_has_rd_r_reg_0,
    auto_pre_r_lcl_reg_1,
    q_has_priority_r_reg_0,
    wait_for_maint_r_lcl_reg_0,
    wait_for_maint_r_lcl_reg_1,
    head_r_lcl_reg_1,
    head_r_lcl_reg_2,
    ordered_r_lcl_reg_1,
    \compute_tail.tail_r_lcl_reg_1 ,
    auto_pre_r_lcl_reg_2,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_2 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_2 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_3 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 ,
    granted_col_r_reg,
    bm_end_r1_reg,
    granted_col_r_reg_0,
    granted_col_r_reg_1,
    \ras_timer_r_reg[0] ,
    \ras_timer_r_reg[1] ,
    req_bank_rdy_r_reg,
    \ras_timer_r_reg[0]_0 ,
    \ras_timer_r_reg[0]_1 ,
    \ras_timer_r_reg[0]_2 ,
    \grant_r[3]_i_5_0 ,
    \ras_timer_r_reg[0]_3 ,
    \compute_tail.tail_r_lcl_reg_2 ,
    \compute_tail.tail_r_lcl_reg_3 ,
    \q_entry_r_reg[1]_1 ,
    \q_entry_r_reg[1]_2 ,
    \order_q_r_reg[1]_1 ,
    head_r_lcl_reg_3,
    head_r_lcl_reg_4,
    head_r_lcl_reg_5,
    \compute_tail.tail_r_lcl_reg_4 ,
    req_bank_rdy_r_reg_0,
    req_priority_r,
    \grant_r[3]_i_5_1 ,
    \grant_r[3]_i_5_2 ,
    \grant_r[3]_i_5_3 ,
    \grant_r[3]_i_5_4 ,
    rb_hit_busy_r_reg,
    use_addr,
    rb_hit_busy_r_reg_0,
    rb_hit_busy_r_reg_1,
    \ras_timer_r_reg[1]_0 ,
    \ras_timer_r_reg[1]_1 ,
    \ras_timer_r_reg[1]_2 ,
    \ras_timer_r_reg[0]_4 ,
    \ras_timer_r_reg[0]_5 ,
    \ras_timer_r_reg[0]_6 ,
    \grant_r[3]_i_6 ,
    Q,
    bm_end_r1_reg_0,
    rb_hit_busies_r,
    rb_hit_busies_r_1,
    pass_open_bank_r_lcl_reg_1,
    pre_wait_r,
    pass_open_bank_r_lcl_reg_2,
    auto_pre_r_lcl_reg_3,
    auto_pre_r_lcl_reg_4,
    i___74,
    ras_timer_zero_r,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_4 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_3 ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_3 ,
    \q_entry_r_reg[1]_3 ,
    \q_entry_r_reg[1]_4 ,
    \q_entry_r_reg[1]_5 ,
    \q_entry_r_reg[0]_2 ,
    \order_q_r_reg[1]_2 ,
    \order_q_r_reg[0]_1 ,
    \order_q_r_reg[0]_2 );
  output [0:0]idle_r_lcl_reg_0;
  output [0:0]E;
  output pass_open_bank_r_lcl_reg_0;
  output pass_open_bank_ns;
  output pre_bm_end_r_11;
  output q_has_rd_12;
  output q_has_priority;
  output wait_for_maint_r_15;
  output head_r_lcl_reg_0;
  output ordered_r_lcl_reg_0;
  output tail_r_18;
  output auto_pre_r_lcl_reg_0;
  output \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ;
  output idle_r_lcl_reg_1;
  output \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0 ;
  output rd_wr_r_lcl_reg;
  output [1:0]D;
  output \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_1 ;
  output pre_bm_end_r_reg_0;
  output pre_bm_end_r_reg_1;
  output \q_entry_r_reg[1]_0 ;
  output \q_entry_r_reg[0]_0 ;
  output \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ;
  output \q_entry_r_reg[0]_1 ;
  output pre_bm_end_r_reg_2;
  output \order_q_r_reg[0]_0 ;
  output req_bank_rdy_ns;
  output p_28_out;
  output \rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ;
  output \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ;
  output \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 ;
  output pre_passing_open_bank_r_reg_0;
  output p_13_out;
  output \compute_tail.tail_r_lcl_reg_0 ;
  output act_wait_r_lcl_reg;
  input \order_q_r_reg[1]_0 ;
  input pre_bm_end_ns;
  input pre_passing_open_bank_ns;
  input q_has_rd_r_reg_0;
  input auto_pre_r_lcl_reg_1;
  input q_has_priority_r_reg_0;
  input wait_for_maint_r_lcl_reg_0;
  input wait_for_maint_r_lcl_reg_1;
  input head_r_lcl_reg_1;
  input head_r_lcl_reg_2;
  input ordered_r_lcl_reg_1;
  input \compute_tail.tail_r_lcl_reg_1 ;
  input auto_pre_r_lcl_reg_2;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_2 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_2 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_3 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 ;
  input granted_col_r_reg;
  input bm_end_r1_reg;
  input granted_col_r_reg_0;
  input granted_col_r_reg_1;
  input \ras_timer_r_reg[0] ;
  input \ras_timer_r_reg[1] ;
  input req_bank_rdy_r_reg;
  input \ras_timer_r_reg[0]_0 ;
  input \ras_timer_r_reg[0]_1 ;
  input \ras_timer_r_reg[0]_2 ;
  input \grant_r[3]_i_5_0 ;
  input \ras_timer_r_reg[0]_3 ;
  input \compute_tail.tail_r_lcl_reg_2 ;
  input \compute_tail.tail_r_lcl_reg_3 ;
  input \q_entry_r_reg[1]_1 ;
  input \q_entry_r_reg[1]_2 ;
  input \order_q_r_reg[1]_1 ;
  input head_r_lcl_reg_3;
  input head_r_lcl_reg_4;
  input head_r_lcl_reg_5;
  input \compute_tail.tail_r_lcl_reg_4 ;
  input req_bank_rdy_r_reg_0;
  input req_priority_r;
  input \grant_r[3]_i_5_1 ;
  input \grant_r[3]_i_5_2 ;
  input \grant_r[3]_i_5_3 ;
  input \grant_r[3]_i_5_4 ;
  input rb_hit_busy_r_reg;
  input use_addr;
  input rb_hit_busy_r_reg_0;
  input rb_hit_busy_r_reg_1;
  input \ras_timer_r_reg[1]_0 ;
  input \ras_timer_r_reg[1]_1 ;
  input \ras_timer_r_reg[1]_2 ;
  input \ras_timer_r_reg[0]_4 ;
  input \ras_timer_r_reg[0]_5 ;
  input \ras_timer_r_reg[0]_6 ;
  input [0:0]\grant_r[3]_i_6 ;
  input [0:0]Q;
  input bm_end_r1_reg_0;
  input [0:0]rb_hit_busies_r;
  input [0:0]rb_hit_busies_r_1;
  input pass_open_bank_r_lcl_reg_1;
  input pre_wait_r;
  input pass_open_bank_r_lcl_reg_2;
  input auto_pre_r_lcl_reg_3;
  input auto_pre_r_lcl_reg_4;
  input i___74;
  input ras_timer_zero_r;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_4 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_3 ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_3 ;
  input \q_entry_r_reg[1]_3 ;
  input \q_entry_r_reg[1]_4 ;
  input \q_entry_r_reg[1]_5 ;
  input \q_entry_r_reg[0]_2 ;
  input \order_q_r_reg[1]_2 ;
  input \order_q_r_reg[0]_1 ;
  input \order_q_r_reg[0]_2 ;

  wire [1:0]D;
  wire [0:0]E;
  wire [0:0]Q;
  wire act_wait_r_lcl_reg;
  wire auto_pre_r_lcl_reg_0;
  wire auto_pre_r_lcl_reg_1;
  wire auto_pre_r_lcl_reg_2;
  wire auto_pre_r_lcl_reg_3;
  wire auto_pre_r_lcl_reg_4;
  wire bm_end_r1_reg;
  wire bm_end_r1_reg_0;
  wire \compute_tail.tail_r_lcl_reg_0 ;
  wire \compute_tail.tail_r_lcl_reg_1 ;
  wire \compute_tail.tail_r_lcl_reg_2 ;
  wire \compute_tail.tail_r_lcl_reg_3 ;
  wire \compute_tail.tail_r_lcl_reg_4 ;
  wire \grant_r[3]_i_11_n_0 ;
  wire \grant_r[3]_i_12_n_0 ;
  wire \grant_r[3]_i_5_0 ;
  wire \grant_r[3]_i_5_1 ;
  wire \grant_r[3]_i_5_2 ;
  wire \grant_r[3]_i_5_3 ;
  wire \grant_r[3]_i_5_4 ;
  wire [0:0]\grant_r[3]_i_6 ;
  wire granted_col_r_reg;
  wire granted_col_r_reg_0;
  wire granted_col_r_reg_1;
  wire head_r_lcl_reg_0;
  wire head_r_lcl_reg_1;
  wire head_r_lcl_reg_2;
  wire head_r_lcl_reg_3;
  wire head_r_lcl_reg_4;
  wire head_r_lcl_reg_5;
  wire i___74;
  wire [0:0]idle_r_lcl_reg_0;
  wire idle_r_lcl_reg_1;
  wire [1:0]order_q_r;
  wire \order_q_r[0]_i_1_n_0 ;
  wire \order_q_r[1]_i_1_n_0 ;
  wire \order_q_r_reg[0]_0 ;
  wire \order_q_r_reg[0]_1 ;
  wire \order_q_r_reg[0]_2 ;
  wire \order_q_r_reg[1]_0 ;
  wire \order_q_r_reg[1]_1 ;
  wire \order_q_r_reg[1]_2 ;
  wire ordered_r_lcl_reg_0;
  wire ordered_r_lcl_reg_1;
  wire p_13_out;
  wire p_28_out;
  wire pass_open_bank_ns;
  wire pass_open_bank_r_lcl_reg_0;
  wire pass_open_bank_r_lcl_reg_1;
  wire pass_open_bank_r_lcl_reg_2;
  wire pre_bm_end_ns;
  wire pre_bm_end_r_11;
  wire pre_bm_end_r_reg_0;
  wire pre_bm_end_r_reg_1;
  wire pre_bm_end_r_reg_2;
  wire pre_passing_open_bank_ns;
  wire pre_passing_open_bank_r;
  wire pre_passing_open_bank_r_reg_0;
  wire pre_wait_r;
  wire \q_entry_r[0]_i_1_n_0 ;
  wire \q_entry_r[0]_i_3_n_0 ;
  wire \q_entry_r[1]_i_1_n_0 ;
  wire \q_entry_r[1]_i_3_n_0 ;
  wire \q_entry_r_reg[0]_0 ;
  wire \q_entry_r_reg[0]_1 ;
  wire \q_entry_r_reg[0]_2 ;
  wire \q_entry_r_reg[1]_0 ;
  wire \q_entry_r_reg[1]_1 ;
  wire \q_entry_r_reg[1]_2 ;
  wire \q_entry_r_reg[1]_3 ;
  wire \q_entry_r_reg[1]_4 ;
  wire \q_entry_r_reg[1]_5 ;
  wire q_has_priority;
  wire q_has_priority_r_reg_0;
  wire q_has_rd_12;
  wire q_has_rd_r_reg_0;
  wire \ras_timer_r[0]_i_2_n_0 ;
  wire \ras_timer_r[1]_i_2_n_0 ;
  wire \ras_timer_r_reg[0] ;
  wire \ras_timer_r_reg[0]_0 ;
  wire \ras_timer_r_reg[0]_1 ;
  wire \ras_timer_r_reg[0]_2 ;
  wire \ras_timer_r_reg[0]_3 ;
  wire \ras_timer_r_reg[0]_4 ;
  wire \ras_timer_r_reg[0]_5 ;
  wire \ras_timer_r_reg[0]_6 ;
  wire \ras_timer_r_reg[1] ;
  wire \ras_timer_r_reg[1]_0 ;
  wire \ras_timer_r_reg[1]_1 ;
  wire \ras_timer_r_reg[1]_2 ;
  wire ras_timer_zero_r;
  wire \rb_hit_busies.rb_hit_busies_r_lcl[4]_i_1__1_n_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl[5]_i_1_n_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl[6]_i_1_n_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_3 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_2 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_3 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_1 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_2 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_3 ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_4 ;
  wire [0:0]rb_hit_busies_r;
  wire [4:4]rb_hit_busies_r_0;
  wire [0:0]rb_hit_busies_r_1;
  wire rb_hit_busy_r_reg;
  wire rb_hit_busy_r_reg_0;
  wire rb_hit_busy_r_reg_1;
  wire rd_wr_r_lcl_reg;
  wire req_bank_rdy_ns;
  wire req_bank_rdy_r_reg;
  wire req_bank_rdy_r_reg_0;
  wire req_priority_r;
  wire tail_r_18;
  wire use_addr;
  wire wait_for_maint_r_15;
  wire wait_for_maint_r_lcl_reg_0;
  wire wait_for_maint_r_lcl_reg_1;

  FDRE auto_pre_r_lcl_reg
       (.C(\order_q_r_reg[1]_0 ),
        .CE(1'b1),
        .D(auto_pre_r_lcl_reg_2),
        .Q(auto_pre_r_lcl_reg_0),
        .R(auto_pre_r_lcl_reg_1));
  (* SOFT_HLUTNM = "soft_lutpair1181" *) 
  LUT5 #(
    .INIT(32'hFFFF0888)) 
    bm_end_r1_i_1__2
       (.I0(pass_open_bank_r_lcl_reg_0),
        .I1(Q),
        .I2(bm_end_r1_reg),
        .I3(bm_end_r1_reg_0),
        .I4(pre_bm_end_r_11),
        .O(p_13_out));
  FDRE #(
    .INIT(1'b1)) 
    \compute_tail.tail_r_lcl_reg 
       (.C(\order_q_r_reg[1]_0 ),
        .CE(1'b1),
        .D(\compute_tail.tail_r_lcl_reg_1 ),
        .Q(tail_r_18),
        .R(head_r_lcl_reg_1));
  LUT5 #(
    .INIT(32'hF2F2F2FF)) 
    demand_priority_r_i_2
       (.I0(order_q_r[0]),
        .I1(req_bank_rdy_r_reg_0),
        .I2(order_q_r[1]),
        .I3(q_has_priority),
        .I4(req_priority_r),
        .O(\order_q_r_reg[0]_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF2000)) 
    \grant_r[3]_i_11 
       (.I0(order_q_r[0]),
        .I1(\grant_r[3]_i_5_1 ),
        .I2(\grant_r[3]_i_5_2 ),
        .I3(\grant_r[3]_i_5_3 ),
        .I4(order_q_r[1]),
        .I5(\grant_r[3]_i_5_4 ),
        .O(\grant_r[3]_i_11_n_0 ));
  LUT6 #(
    .INIT(64'hBBBBBBBBBBBBABAA)) 
    \grant_r[3]_i_12 
       (.I0(req_bank_rdy_r_reg),
        .I1(\ras_timer_r_reg[0]_0 ),
        .I2(\ras_timer_r_reg[0]_1 ),
        .I3(rb_hit_busies_r_0),
        .I4(\ras_timer_r_reg[0]_2 ),
        .I5(\grant_r[3]_i_5_0 ),
        .O(\grant_r[3]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF7FFFFFFFF)) 
    \grant_r[3]_i_5 
       (.I0(granted_col_r_reg),
        .I1(bm_end_r1_reg),
        .I2(\grant_r[3]_i_11_n_0 ),
        .I3(granted_col_r_reg_0),
        .I4(granted_col_r_reg_1),
        .I5(\grant_r[3]_i_12_n_0 ),
        .O(rd_wr_r_lcl_reg));
  FDRE head_r_lcl_reg
       (.C(\order_q_r_reg[1]_0 ),
        .CE(1'b1),
        .D(head_r_lcl_reg_2),
        .Q(head_r_lcl_reg_0),
        .R(head_r_lcl_reg_1));
  LUT6 #(
    .INIT(64'h00000000F4F4FFF4)) 
    i___25_i_1
       (.I0(\ras_timer_r_reg[0]_3 ),
        .I1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0 ),
        .I2(\ras_timer_r_reg[0]_2 ),
        .I3(rb_hit_busies_r_0),
        .I4(\ras_timer_r_reg[0]_1 ),
        .I5(\ras_timer_r_reg[0]_0 ),
        .O(\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_1 ));
  LUT6 #(
    .INIT(64'hAAAAAAAA00808080)) 
    i___28_i_2
       (.I0(rb_hit_busies_r),
        .I1(pass_open_bank_r_lcl_reg_0),
        .I2(Q),
        .I3(bm_end_r1_reg),
        .I4(bm_end_r1_reg_0),
        .I5(pre_passing_open_bank_r),
        .O(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAA00808080)) 
    i___29_i_3
       (.I0(rb_hit_busies_r_1),
        .I1(pass_open_bank_r_lcl_reg_0),
        .I2(Q),
        .I3(bm_end_r1_reg),
        .I4(bm_end_r1_reg_0),
        .I5(pre_passing_open_bank_r),
        .O(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1184" *) 
  LUT3 #(
    .INIT(8'h08)) 
    i___2_i_2
       (.I0(pre_bm_end_r_reg_1),
        .I1(\compute_tail.tail_r_lcl_reg_2 ),
        .I2(\compute_tail.tail_r_lcl_reg_4 ),
        .O(pre_bm_end_r_reg_2));
  LUT5 #(
    .INIT(32'h40555555)) 
    i___30_i_2
       (.I0(pre_passing_open_bank_r),
        .I1(bm_end_r1_reg_0),
        .I2(bm_end_r1_reg),
        .I3(Q),
        .I4(pass_open_bank_r_lcl_reg_0),
        .O(pre_passing_open_bank_r_reg_0));
  LUT6 #(
    .INIT(64'h0777077700000777)) 
    i___38_i_1
       (.I0(\compute_tail.tail_r_lcl_reg_3 ),
        .I1(rb_hit_busies_r_0),
        .I2(\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0 ),
        .I3(\compute_tail.tail_r_lcl_reg_4 ),
        .I4(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ),
        .I5(\compute_tail.tail_r_lcl_reg_2 ),
        .O(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ));
  LUT6 #(
    .INIT(64'h00000000FD555555)) 
    i___44_i_1
       (.I0(idle_r_lcl_reg_0),
        .I1(use_addr),
        .I2(rb_hit_busy_r_reg_0),
        .I3(head_r_lcl_reg_0),
        .I4(rb_hit_busy_r_reg_1),
        .I5(auto_pre_r_lcl_reg_1),
        .O(idle_r_lcl_reg_1));
  LUT6 #(
    .INIT(64'hAAAAAAAA00808080)) 
    i___49_i_2
       (.I0(\grant_r[3]_i_6 ),
        .I1(pass_open_bank_r_lcl_reg_0),
        .I2(Q),
        .I3(bm_end_r1_reg),
        .I4(bm_end_r1_reg_0),
        .I5(pre_passing_open_bank_r),
        .O(\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] ));
  LUT5 #(
    .INIT(32'h777F7F7F)) 
    i___64_i_2
       (.I0(tail_r_18),
        .I1(auto_pre_r_lcl_reg_3),
        .I2(rb_hit_busy_r_reg_0),
        .I3(auto_pre_r_lcl_reg_4),
        .I4(use_addr),
        .O(\compute_tail.tail_r_lcl_reg_0 ));
  LUT6 #(
    .INIT(64'h2020202F202F2020)) 
    i___6_i_1
       (.I0(\q_entry_r_reg[0]_0 ),
        .I1(\q_entry_r_reg[1]_0 ),
        .I2(head_r_lcl_reg_4),
        .I3(head_r_lcl_reg_5),
        .I4(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ),
        .I5(head_r_lcl_reg_3),
        .O(\q_entry_r_reg[0]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1181" *) 
  LUT5 #(
    .INIT(32'h40555555)) 
    i___6_i_2
       (.I0(pre_bm_end_r_11),
        .I1(bm_end_r1_reg_0),
        .I2(bm_end_r1_reg),
        .I3(Q),
        .I4(pass_open_bank_r_lcl_reg_0),
        .O(pre_bm_end_r_reg_1));
  LUT5 #(
    .INIT(32'hFFDFFFFF)) 
    i___74_i_1
       (.I0(i___74),
        .I1(idle_r_lcl_reg_0),
        .I2(head_r_lcl_reg_0),
        .I3(wait_for_maint_r_15),
        .I4(ras_timer_zero_r),
        .O(act_wait_r_lcl_reg));
  (* SOFT_HLUTNM = "soft_lutpair1184" *) 
  LUT3 #(
    .INIT(8'h08)) 
    i___8_i_3
       (.I0(pre_bm_end_r_reg_1),
        .I1(\compute_tail.tail_r_lcl_reg_2 ),
        .I2(\compute_tail.tail_r_lcl_reg_3 ),
        .O(pre_bm_end_r_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair1182" *) 
  LUT1 #(
    .INIT(2'h1)) 
    idle_r_lcl_i_1__0
       (.I0(idle_r_lcl_reg_1),
        .O(E));
  FDRE idle_r_lcl_reg
       (.C(\order_q_r_reg[1]_0 ),
        .CE(1'b1),
        .D(E),
        .Q(idle_r_lcl_reg_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0D550C000D550CF0)) 
    \order_q_r[0]_i_1 
       (.I0(\order_q_r_reg[0]_2 ),
        .I1(order_q_r[1]),
        .I2(order_q_r[0]),
        .I3(req_bank_rdy_r_reg_0),
        .I4(\order_q_r_reg[1]_1 ),
        .I5(\order_q_r_reg[0]_1 ),
        .O(\order_q_r[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hC2AAC000C2AAC0CC)) 
    \order_q_r[1]_i_1 
       (.I0(\order_q_r_reg[1]_2 ),
        .I1(order_q_r[1]),
        .I2(order_q_r[0]),
        .I3(req_bank_rdy_r_reg_0),
        .I4(\order_q_r_reg[1]_1 ),
        .I5(\order_q_r_reg[0]_1 ),
        .O(\order_q_r[1]_i_1_n_0 ));
  FDRE \order_q_r_reg[0] 
       (.C(\order_q_r_reg[1]_0 ),
        .CE(1'b1),
        .D(\order_q_r[0]_i_1_n_0 ),
        .Q(order_q_r[0]),
        .R(1'b0));
  FDRE \order_q_r_reg[1] 
       (.C(\order_q_r_reg[1]_0 ),
        .CE(1'b1),
        .D(\order_q_r[1]_i_1_n_0 ),
        .Q(order_q_r[1]),
        .R(1'b0));
  FDRE ordered_r_lcl_reg
       (.C(\order_q_r_reg[1]_0 ),
        .CE(1'b1),
        .D(ordered_r_lcl_reg_1),
        .Q(ordered_r_lcl_reg_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h4444544444444444)) 
    pass_open_bank_r_lcl_i_1__2
       (.I0(auto_pre_r_lcl_reg_1),
        .I1(pass_open_bank_r_lcl_reg_0),
        .I2(tail_r_18),
        .I3(pass_open_bank_r_lcl_reg_1),
        .I4(pre_wait_r),
        .I5(pass_open_bank_r_lcl_reg_2),
        .O(pass_open_bank_ns));
  FDRE pass_open_bank_r_lcl_reg
       (.C(\order_q_r_reg[1]_0 ),
        .CE(1'b1),
        .D(pass_open_bank_ns),
        .Q(pass_open_bank_r_lcl_reg_0),
        .R(1'b0));
  FDRE pre_bm_end_r_reg
       (.C(\order_q_r_reg[1]_0 ),
        .CE(1'b1),
        .D(pre_bm_end_ns),
        .Q(pre_bm_end_r_11),
        .R(1'b0));
  FDRE pre_passing_open_bank_r_reg
       (.C(\order_q_r_reg[1]_0 ),
        .CE(1'b1),
        .D(pre_passing_open_bank_ns),
        .Q(pre_passing_open_bank_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFD21FFFFFD210000)) 
    \q_entry_r[0]_i_1 
       (.I0(\q_entry_r_reg[1]_4 ),
        .I1(pre_bm_end_r_reg_1),
        .I2(\q_entry_r_reg[0]_2 ),
        .I3(\q_entry_r[0]_i_3_n_0 ),
        .I4(\q_entry_r_reg[1]_5 ),
        .I5(\q_entry_r_reg[0]_0 ),
        .O(\q_entry_r[0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h909F0000)) 
    \q_entry_r[0]_i_3 
       (.I0(head_r_lcl_reg_3),
        .I1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 ),
        .I2(\order_q_r_reg[1]_1 ),
        .I3(\q_entry_r_reg[0]_0 ),
        .I4(pre_bm_end_r_reg_1),
        .O(\q_entry_r[0]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFB08FFFFFB080000)) 
    \q_entry_r[1]_i_1 
       (.I0(\q_entry_r_reg[1]_3 ),
        .I1(\q_entry_r_reg[1]_4 ),
        .I2(pre_bm_end_r_reg_1),
        .I3(\q_entry_r[1]_i_3_n_0 ),
        .I4(\q_entry_r_reg[1]_5 ),
        .I5(\q_entry_r_reg[1]_0 ),
        .O(\q_entry_r[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h1DDD1D111D111DDD)) 
    \q_entry_r[1]_i_3 
       (.I0(\q_entry_r_reg[1]_1 ),
        .I1(pre_bm_end_r_reg_1),
        .I2(\q_entry_r_reg[1]_2 ),
        .I3(\order_q_r_reg[1]_1 ),
        .I4(\q_entry_r_reg[1]_0 ),
        .I5(\q_entry_r_reg[0]_0 ),
        .O(\q_entry_r[1]_i_3_n_0 ));
  FDSE \q_entry_r_reg[0] 
       (.C(\order_q_r_reg[1]_0 ),
        .CE(1'b1),
        .D(\q_entry_r[0]_i_1_n_0 ),
        .Q(\q_entry_r_reg[0]_0 ),
        .S(head_r_lcl_reg_1));
  FDSE \q_entry_r_reg[1] 
       (.C(\order_q_r_reg[1]_0 ),
        .CE(1'b1),
        .D(\q_entry_r[1]_i_1_n_0 ),
        .Q(\q_entry_r_reg[1]_0 ),
        .S(head_r_lcl_reg_1));
  FDRE q_has_priority_r_reg
       (.C(\order_q_r_reg[1]_0 ),
        .CE(1'b1),
        .D(q_has_priority_r_reg_0),
        .Q(q_has_priority),
        .R(auto_pre_r_lcl_reg_1));
  FDRE q_has_rd_r_reg
       (.C(\order_q_r_reg[1]_0 ),
        .CE(1'b1),
        .D(q_has_rd_r_reg_0),
        .Q(q_has_rd_12),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair1185" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ras_timer_r[0]_i_1 
       (.I0(\ras_timer_r[0]_i_2_n_0 ),
        .I1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_1 ),
        .I2(\ras_timer_r_reg[0] ),
        .O(D[0]));
  LUT6 #(
    .INIT(64'hB8BBB888B888B888)) 
    \ras_timer_r[0]_i_2 
       (.I0(\ras_timer_r_reg[0]_4 ),
        .I1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0 ),
        .I2(\ras_timer_r_reg[0]_5 ),
        .I3(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ),
        .I4(\ras_timer_r_reg[0]_6 ),
        .I5(rb_hit_busies_r_0),
        .O(\ras_timer_r[0]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1185" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \ras_timer_r[1]_i_1 
       (.I0(\ras_timer_r[1]_i_2_n_0 ),
        .I1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_1 ),
        .I2(\ras_timer_r_reg[1] ),
        .O(D[1]));
  LUT6 #(
    .INIT(64'hB8BBB888B888B888)) 
    \ras_timer_r[1]_i_2 
       (.I0(\ras_timer_r_reg[1]_0 ),
        .I1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0 ),
        .I2(\ras_timer_r_reg[1]_1 ),
        .I3(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ),
        .I4(\ras_timer_r_reg[1]_2 ),
        .I5(rb_hit_busies_r_0),
        .O(\ras_timer_r[1]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1183" *) 
  LUT4 #(
    .INIT(16'hF022)) 
    \rb_hit_busies.rb_hit_busies_r_lcl[4]_i_1__1 
       (.I0(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 ),
        .I1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_2 ),
        .I2(rb_hit_busies_r_0),
        .I3(idle_r_lcl_reg_1),
        .O(\rb_hit_busies.rb_hit_busies_r_lcl[4]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'hF022)) 
    \rb_hit_busies.rb_hit_busies_r_lcl[5]_i_1 
       (.I0(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1 ),
        .I1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_2 ),
        .I2(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ),
        .I3(idle_r_lcl_reg_1),
        .O(\rb_hit_busies.rb_hit_busies_r_lcl[5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1182" *) 
  LUT4 #(
    .INIT(16'hF022)) 
    \rb_hit_busies.rb_hit_busies_r_lcl[6]_i_1 
       (.I0(\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_2 ),
        .I1(\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_3 ),
        .I2(\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0 ),
        .I3(idle_r_lcl_reg_1),
        .O(\rb_hit_busies.rb_hit_busies_r_lcl[6]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4] 
       (.C(\order_q_r_reg[1]_0 ),
        .CE(1'b1),
        .D(\rb_hit_busies.rb_hit_busies_r_lcl[4]_i_1__1_n_0 ),
        .Q(rb_hit_busies_r_0),
        .R(\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_3 ));
  FDRE #(
    .INIT(1'b0)) 
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5] 
       (.C(\order_q_r_reg[1]_0 ),
        .CE(1'b1),
        .D(\rb_hit_busies.rb_hit_busies_r_lcl[5]_i_1_n_0 ),
        .Q(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 ),
        .R(\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_3 ));
  FDRE #(
    .INIT(1'b0)) 
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[6] 
       (.C(\order_q_r_reg[1]_0 ),
        .CE(1'b1),
        .D(\rb_hit_busies.rb_hit_busies_r_lcl[6]_i_1_n_0 ),
        .Q(\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0 ),
        .R(\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair1183" *) 
  LUT2 #(
    .INIT(4'h2)) 
    rb_hit_busy_r_i_1__0
       (.I0(idle_r_lcl_reg_1),
        .I1(rb_hit_busy_r_reg),
        .O(p_28_out));
  LUT4 #(
    .INIT(16'h00A2)) 
    req_bank_rdy_r_i_1
       (.I0(req_bank_rdy_r_reg),
        .I1(order_q_r[0]),
        .I2(req_bank_rdy_r_reg_0),
        .I3(order_q_r[1]),
        .O(req_bank_rdy_ns));
  FDRE wait_for_maint_r_lcl_reg
       (.C(\order_q_r_reg[1]_0 ),
        .CE(1'b1),
        .D(wait_for_maint_r_lcl_reg_1),
        .Q(wait_for_maint_r_15),
        .R(wait_for_maint_r_lcl_reg_0));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_bank_state" *) 
module mig_mig_7series_v4_2_bank_state
   (act_wait_r_lcl_reg_0,
    ras_timer_zero_r,
    pre_wait_r,
    col_wait_r_reg_0,
    act_this_rank_r,
    demand_priority_r_reg_0,
    demanded_prior_r_reg_0,
    ofs_rdy_r,
    wr_this_rank_r,
    rd_this_rank_r,
    rnk_config_valid_r_lcl_reg,
    pre_bm_end_ns,
    pre_passing_open_bank_ns,
    bm_end_r1_reg_0,
    bm_end_r1_reg_1,
    auto_pre_r_lcl_reg,
    demand_priority_r_reg_1,
    demanded_prior_r_reg_1,
    ofs_rdy_r0,
    ofs_rdy_r0_0,
    ofs_rdy_r0_1,
    bm_end_r1_reg_2,
    ofs_rdy_r_reg_0,
    col_wait_r_reg_1,
    req_bank_rdy_ns_0,
    phy_mc_ctl_full_r_reg_0,
    phy_mc_ctl_full,
    phy_mc_cmd_full_r_reg_0,
    of_ctl_full_v,
    start_wtp_timer0,
    \rd_this_rank_r_reg[0]_0 ,
    Q,
    pass_open_bank_r,
    \rtp_timer_r_reg[1]_0 ,
    act_wait_r_lcl_reg_1,
    pre_wait_r_reg_0,
    demand_priority_r_reg_2,
    demand_priority_r_reg_3,
    req_bank_rdy_ns,
    rnk_config_valid_r,
    override_demand_ns,
    \rnk_config_strobe_r_reg[0] ,
    pre_bm_end_r_reg,
    pre_bm_end_r_reg_0,
    pass_open_bank_ns,
    ras_timer_zero_r_reg_0,
    pre_wait_r_reg_1,
    demanded_prior_r_reg_2,
    \grant_r[2]_i_3 ,
    override_demand_r,
    \grant_r[2]_i_3_0 ,
    \ras_timer_r[1]_i_3_0 ,
    demanded_prior_r_reg_3,
    demanded_prior_r,
    demand_priority_r_reg_4,
    req_wr_r,
    q_has_rd,
    phy_mc_data_full,
    ofs_rdy_r_reg_1,
    ofs_rdy_r_reg_2,
    ofs_rdy_r_reg_3,
    \rtp_timer_r_reg[0]_0 ,
    D);
  output act_wait_r_lcl_reg_0;
  output ras_timer_zero_r;
  output pre_wait_r;
  output col_wait_r_reg_0;
  output [0:0]act_this_rank_r;
  output demand_priority_r_reg_0;
  output demanded_prior_r_reg_0;
  output ofs_rdy_r;
  output [0:0]wr_this_rank_r;
  output [0:0]rd_this_rank_r;
  output rnk_config_valid_r_lcl_reg;
  output pre_bm_end_ns;
  output pre_passing_open_bank_ns;
  output bm_end_r1_reg_0;
  output bm_end_r1_reg_1;
  output auto_pre_r_lcl_reg;
  output demand_priority_r_reg_1;
  output demanded_prior_r_reg_1;
  output ofs_rdy_r0;
  output ofs_rdy_r0_0;
  output ofs_rdy_r0_1;
  input bm_end_r1_reg_2;
  input ofs_rdy_r_reg_0;
  input col_wait_r_reg_1;
  input req_bank_rdy_ns_0;
  input phy_mc_ctl_full_r_reg_0;
  input phy_mc_ctl_full;
  input phy_mc_cmd_full_r_reg_0;
  input [0:0]of_ctl_full_v;
  input start_wtp_timer0;
  input \rd_this_rank_r_reg[0]_0 ;
  input [1:0]Q;
  input pass_open_bank_r;
  input \rtp_timer_r_reg[1]_0 ;
  input act_wait_r_lcl_reg_1;
  input pre_wait_r_reg_0;
  input demand_priority_r_reg_2;
  input demand_priority_r_reg_3;
  input req_bank_rdy_ns;
  input rnk_config_valid_r;
  input override_demand_ns;
  input \rnk_config_strobe_r_reg[0] ;
  input [0:0]pre_bm_end_r_reg;
  input pre_bm_end_r_reg_0;
  input pass_open_bank_ns;
  input ras_timer_zero_r_reg_0;
  input pre_wait_r_reg_1;
  input demanded_prior_r_reg_2;
  input \grant_r[2]_i_3 ;
  input override_demand_r;
  input \grant_r[2]_i_3_0 ;
  input [0:0]\ras_timer_r[1]_i_3_0 ;
  input demanded_prior_r_reg_3;
  input demanded_prior_r;
  input demand_priority_r_reg_4;
  input [0:0]req_wr_r;
  input q_has_rd;
  input phy_mc_data_full;
  input ofs_rdy_r_reg_1;
  input ofs_rdy_r_reg_2;
  input ofs_rdy_r_reg_3;
  input \rtp_timer_r_reg[0]_0 ;
  input [1:0]D;

  wire [1:0]D;
  wire [1:0]Q;
  wire [0:0]act_this_rank_r;
  wire act_wait_ns;
  wire act_wait_r_lcl_reg_0;
  wire act_wait_r_lcl_reg_1;
  wire auto_pre_r_lcl_reg;
  wire \bank_cntrl[3].bank0/bank_state0/phy_mc_cmd_full_r ;
  wire \bank_cntrl[3].bank0/bank_state0/phy_mc_ctl_full_r ;
  wire bm_end_r1;
  wire bm_end_r1_reg_0;
  wire bm_end_r1_reg_1;
  wire bm_end_r1_reg_2;
  wire col_wait_r_reg_0;
  wire col_wait_r_reg_1;
  wire demand_priority_ns;
  wire demand_priority_r_i_3_n_0;
  wire demand_priority_r_i_4_n_0;
  wire demand_priority_r_reg_0;
  wire demand_priority_r_reg_1;
  wire demand_priority_r_reg_2;
  wire demand_priority_r_reg_3;
  wire demand_priority_r_reg_4;
  wire demanded_prior_ns;
  wire demanded_prior_r;
  wire demanded_prior_r_reg_0;
  wire demanded_prior_r_reg_1;
  wire demanded_prior_r_reg_2;
  wire demanded_prior_r_reg_3;
  wire \grant_r[2]_i_3 ;
  wire \grant_r[2]_i_3_0 ;
  wire i___40_i_4_n_0;
  wire [0:0]of_ctl_full_v;
  wire ofs_rdy_r;
  wire ofs_rdy_r0;
  wire ofs_rdy_r0_0;
  wire ofs_rdy_r0_1;
  wire ofs_rdy_r0_2;
  wire ofs_rdy_r_reg_0;
  wire ofs_rdy_r_reg_1;
  wire ofs_rdy_r_reg_2;
  wire ofs_rdy_r_reg_3;
  wire override_demand_ns;
  wire override_demand_r;
  wire pass_open_bank_ns;
  wire pass_open_bank_r;
  wire phy_mc_cmd_full_r_reg_0;
  wire phy_mc_ctl_full;
  wire phy_mc_ctl_full_r_reg_0;
  wire phy_mc_data_full;
  wire pre_bm_end_ns;
  wire [0:0]pre_bm_end_r_reg;
  wire pre_bm_end_r_reg_0;
  wire pre_passing_open_bank_ns;
  wire pre_wait_ns;
  wire pre_wait_r;
  wire pre_wait_r_i_2_n_0;
  wire pre_wait_r_reg_0;
  wire pre_wait_r_reg_1;
  wire q_has_rd;
  wire [1:0]ras_timer_r;
  wire [0:0]\ras_timer_r[1]_i_3_0 ;
  wire \ras_timer_r[1]_i_4_n_0 ;
  wire ras_timer_zero_ns;
  wire ras_timer_zero_r;
  wire ras_timer_zero_r_reg_0;
  wire [0:0]rd_this_rank_r;
  wire \rd_this_rank_r_reg[0]_0 ;
  wire req_bank_rdy_ns;
  wire req_bank_rdy_ns_0;
  wire req_bank_rdy_r;
  wire [0:0]req_wr_r;
  wire \rnk_config_strobe_r_reg[0] ;
  wire rnk_config_valid_r;
  wire rnk_config_valid_r_lcl_reg;
  wire [1:0]rtp_timer_r;
  wire \rtp_timer_r[0]_i_1_n_0 ;
  wire \rtp_timer_r[1]_i_1_n_0 ;
  wire \rtp_timer_r_reg[0]_0 ;
  wire \rtp_timer_r_reg[1]_0 ;
  wire start_wtp_timer0;
  wire [2:0]starve_limit_cntr_r;
  wire starve_limit_cntr_r0;
  wire \starve_limit_cntr_r[0]_i_1_n_0 ;
  wire \starve_limit_cntr_r[1]_i_1_n_0 ;
  wire \starve_limit_cntr_r[2]_i_1_n_0 ;
  wire [0:0]wr_this_rank_r;

  FDRE \act_this_rank_r_reg[0] 
       (.C(ofs_rdy_r_reg_0),
        .CE(1'b1),
        .D(act_wait_r_lcl_reg_0),
        .Q(act_this_rank_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFF888)) 
    act_wait_r_lcl_i_1__0
       (.I0(act_wait_r_lcl_reg_0),
        .I1(act_wait_r_lcl_reg_1),
        .I2(pass_open_bank_r),
        .I3(bm_end_r1_reg_2),
        .I4(pre_wait_r_reg_0),
        .I5(bm_end_r1),
        .O(act_wait_ns));
  FDRE act_wait_r_lcl_reg
       (.C(ofs_rdy_r_reg_0),
        .CE(1'b1),
        .D(act_wait_ns),
        .Q(act_wait_r_lcl_reg_0),
        .R(1'b0));
  FDRE bm_end_r1_reg
       (.C(ofs_rdy_r_reg_0),
        .CE(1'b1),
        .D(bm_end_r1_reg_2),
        .Q(bm_end_r1),
        .R(1'b0));
  FDRE col_wait_r_reg
       (.C(ofs_rdy_r_reg_0),
        .CE(1'b1),
        .D(col_wait_r_reg_1),
        .Q(col_wait_r_reg_0),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h88888808)) 
    demand_priority_r_i_1__0
       (.I0(col_wait_r_reg_1),
        .I1(demand_priority_r_reg_2),
        .I2(demand_priority_r_reg_3),
        .I3(demand_priority_r_i_3_n_0),
        .I4(demand_priority_r_reg_0),
        .O(demand_priority_ns));
  LUT6 #(
    .INIT(64'h0000000040400040)) 
    demand_priority_r_i_3
       (.I0(Q[0]),
        .I1(demand_priority_r_reg_4),
        .I2(req_bank_rdy_r),
        .I3(req_wr_r),
        .I4(q_has_rd),
        .I5(demand_priority_r_i_4_n_0),
        .O(demand_priority_r_i_3_n_0));
  (* SOFT_HLUTNM = "soft_lutpair1163" *) 
  LUT3 #(
    .INIT(8'h7F)) 
    demand_priority_r_i_4
       (.I0(starve_limit_cntr_r[2]),
        .I1(starve_limit_cntr_r[1]),
        .I2(starve_limit_cntr_r[0]),
        .O(demand_priority_r_i_4_n_0));
  FDRE demand_priority_r_reg
       (.C(ofs_rdy_r_reg_0),
        .CE(1'b1),
        .D(demand_priority_ns),
        .Q(demand_priority_r_reg_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hD0D0D0D0D0DDD0D0)) 
    demanded_prior_r_i_1__0
       (.I0(demand_priority_r_reg_0),
        .I1(demanded_prior_r_reg_0),
        .I2(demanded_prior_r_reg_2),
        .I3(Q[1]),
        .I4(demanded_prior_r_reg_3),
        .I5(demanded_prior_r),
        .O(demanded_prior_ns));
  FDRE demanded_prior_r_reg
       (.C(ofs_rdy_r_reg_0),
        .CE(1'b1),
        .D(demanded_prior_ns),
        .Q(demanded_prior_r_reg_0),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair1159" *) 
  LUT4 #(
    .INIT(16'h1000)) 
    \grant_r[2]_i_3__0 
       (.I0(pre_bm_end_r_reg_0),
        .I1(pre_bm_end_r_reg),
        .I2(pre_wait_r),
        .I3(ras_timer_zero_r),
        .O(auto_pre_r_lcl_reg));
  LUT5 #(
    .INIT(32'hFFFF0045)) 
    \grant_r[2]_i_4 
       (.I0(demand_priority_r_reg_0),
        .I1(demanded_prior_r_reg_2),
        .I2(\grant_r[2]_i_3 ),
        .I3(override_demand_r),
        .I4(\grant_r[2]_i_3_0 ),
        .O(demand_priority_r_reg_1));
  LUT6 #(
    .INIT(64'h000F000800080008)) 
    i___40_i_1
       (.I0(i___40_i_4_n_0),
        .I1(req_bank_rdy_ns),
        .I2(rnk_config_valid_r),
        .I3(override_demand_ns),
        .I4(\rnk_config_strobe_r_reg[0] ),
        .I5(req_bank_rdy_ns_0),
        .O(rnk_config_valid_r_lcl_reg));
  LUT5 #(
    .INIT(32'hBBBBBABB)) 
    i___40_i_4
       (.I0(demanded_prior_r_reg_3),
        .I1(demanded_prior_r_reg_2),
        .I2(Q[0]),
        .I3(demand_priority_r_reg_0),
        .I4(demanded_prior_r_reg_0),
        .O(i___40_i_4_n_0));
  LUT6 #(
    .INIT(64'hFBFBFBFBFB00FBFB)) 
    i___85_i_1
       (.I0(demanded_prior_r_reg_0),
        .I1(demand_priority_r_reg_0),
        .I2(Q[0]),
        .I3(demanded_prior_r),
        .I4(demanded_prior_r_reg_3),
        .I5(Q[1]),
        .O(demanded_prior_r_reg_1));
  (* SOFT_HLUTNM = "soft_lutpair1161" *) 
  LUT4 #(
    .INIT(16'h1011)) 
    ofs_rdy_r_i_1
       (.I0(\bank_cntrl[3].bank0/bank_state0/phy_mc_cmd_full_r ),
        .I1(\bank_cntrl[3].bank0/bank_state0/phy_mc_ctl_full_r ),
        .I2(\rd_this_rank_r_reg[0]_0 ),
        .I3(phy_mc_data_full),
        .O(ofs_rdy_r0_2));
  (* SOFT_HLUTNM = "soft_lutpair1161" *) 
  LUT4 #(
    .INIT(16'h1011)) 
    ofs_rdy_r_i_1__0
       (.I0(\bank_cntrl[3].bank0/bank_state0/phy_mc_cmd_full_r ),
        .I1(\bank_cntrl[3].bank0/bank_state0/phy_mc_ctl_full_r ),
        .I2(ofs_rdy_r_reg_1),
        .I3(phy_mc_data_full),
        .O(ofs_rdy_r0));
  (* SOFT_HLUTNM = "soft_lutpair1162" *) 
  LUT4 #(
    .INIT(16'h1011)) 
    ofs_rdy_r_i_1__1
       (.I0(\bank_cntrl[3].bank0/bank_state0/phy_mc_cmd_full_r ),
        .I1(\bank_cntrl[3].bank0/bank_state0/phy_mc_ctl_full_r ),
        .I2(ofs_rdy_r_reg_2),
        .I3(phy_mc_data_full),
        .O(ofs_rdy_r0_0));
  (* SOFT_HLUTNM = "soft_lutpair1162" *) 
  LUT4 #(
    .INIT(16'h1011)) 
    ofs_rdy_r_i_1__2
       (.I0(\bank_cntrl[3].bank0/bank_state0/phy_mc_cmd_full_r ),
        .I1(\bank_cntrl[3].bank0/bank_state0/phy_mc_ctl_full_r ),
        .I2(ofs_rdy_r_reg_3),
        .I3(phy_mc_data_full),
        .O(ofs_rdy_r0_1));
  FDRE #(
    .INIT(1'b0)) 
    ofs_rdy_r_reg
       (.C(ofs_rdy_r_reg_0),
        .CE(1'b1),
        .D(ofs_rdy_r0_2),
        .Q(ofs_rdy_r),
        .R(phy_mc_cmd_full_r_reg_0));
  FDRE #(
    .INIT(1'b0)) 
    phy_mc_cmd_full_r_reg
       (.C(ofs_rdy_r_reg_0),
        .CE(1'b1),
        .D(of_ctl_full_v),
        .Q(\bank_cntrl[3].bank0/bank_state0/phy_mc_cmd_full_r ),
        .R(phy_mc_cmd_full_r_reg_0));
  FDRE #(
    .INIT(1'b0)) 
    phy_mc_ctl_full_r_reg
       (.C(ofs_rdy_r_reg_0),
        .CE(1'b1),
        .D(phy_mc_ctl_full),
        .Q(\bank_cntrl[3].bank0/bank_state0/phy_mc_ctl_full_r ),
        .R(phy_mc_ctl_full_r_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair1159" *) 
  LUT5 #(
    .INIT(32'hEAEAEAAA)) 
    pre_bm_end_r_i_1__0
       (.I0(pre_passing_open_bank_ns),
        .I1(ras_timer_zero_r),
        .I2(pre_wait_r),
        .I3(pre_bm_end_r_reg),
        .I4(pre_bm_end_r_reg_0),
        .O(pre_bm_end_ns));
  LUT6 #(
    .INIT(64'hAAA8AAAAAAA8AAA8)) 
    pre_passing_open_bank_r_i_1__0
       (.I0(pass_open_bank_ns),
        .I1(Q[0]),
        .I2(rtp_timer_r[0]),
        .I3(rtp_timer_r[1]),
        .I4(ras_timer_zero_r),
        .I5(pre_wait_r),
        .O(pre_passing_open_bank_ns));
  LUT6 #(
    .INIT(64'h4444444444454444)) 
    pre_wait_r_i_1__0
       (.I0(pass_open_bank_ns),
        .I1(pre_wait_r_i_2_n_0),
        .I2(pass_open_bank_r),
        .I3(pre_wait_r_reg_0),
        .I4(rtp_timer_r[0]),
        .I5(rtp_timer_r[1]),
        .O(pre_wait_ns));
  LUT5 #(
    .INIT(32'h10101050)) 
    pre_wait_r_i_2
       (.I0(pre_wait_r_reg_1),
        .I1(ras_timer_zero_r),
        .I2(pre_wait_r),
        .I3(pre_bm_end_r_reg),
        .I4(pre_bm_end_r_reg_0),
        .O(pre_wait_r_i_2_n_0));
  FDRE pre_wait_r_reg
       (.C(ofs_rdy_r_reg_0),
        .CE(1'b1),
        .D(pre_wait_ns),
        .Q(pre_wait_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0010111100100010)) 
    \ras_timer_r[0]_i_3 
       (.I0(bm_end_r1),
        .I1(pre_wait_r_reg_0),
        .I2(ras_timer_r[1]),
        .I3(ras_timer_r[0]),
        .I4(\rd_this_rank_r_reg[0]_0 ),
        .I5(Q[0]),
        .O(bm_end_r1_reg_1));
  LUT6 #(
    .INIT(64'h1010010011111111)) 
    \ras_timer_r[1]_i_3 
       (.I0(bm_end_r1),
        .I1(pre_wait_r_reg_0),
        .I2(ras_timer_r[1]),
        .I3(\ras_timer_r[1]_i_4_n_0 ),
        .I4(ras_timer_r[0]),
        .I5(ras_timer_zero_r_reg_0),
        .O(bm_end_r1_reg_0));
  LUT2 #(
    .INIT(4'h8)) 
    \ras_timer_r[1]_i_4 
       (.I0(act_wait_r_lcl_reg_0),
        .I1(\ras_timer_r[1]_i_3_0 ),
        .O(\ras_timer_r[1]_i_4_n_0 ));
  FDRE \ras_timer_r_reg[0] 
       (.C(ofs_rdy_r_reg_0),
        .CE(1'b1),
        .D(D[0]),
        .Q(ras_timer_r[0]),
        .R(1'b0));
  FDRE \ras_timer_r_reg[1] 
       (.C(ofs_rdy_r_reg_0),
        .CE(1'b1),
        .D(D[1]),
        .Q(ras_timer_r[1]),
        .R(1'b0));
  LUT2 #(
    .INIT(4'h1)) 
    ras_timer_zero_r_i_1
       (.I0(bm_end_r1_reg_0),
        .I1(bm_end_r1_reg_1),
        .O(ras_timer_zero_ns));
  FDRE ras_timer_zero_r_reg
       (.C(ofs_rdy_r_reg_0),
        .CE(1'b1),
        .D(ras_timer_zero_ns),
        .Q(ras_timer_zero_r),
        .R(1'b0));
  FDRE \rd_this_rank_r_reg[0] 
       (.C(ofs_rdy_r_reg_0),
        .CE(1'b1),
        .D(\rd_this_rank_r_reg[0]_0 ),
        .Q(rd_this_rank_r),
        .R(1'b0));
  FDRE req_bank_rdy_r_reg
       (.C(ofs_rdy_r_reg_0),
        .CE(1'b1),
        .D(req_bank_rdy_ns_0),
        .Q(req_bank_rdy_r),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0010)) 
    \rtp_timer_r[0]_i_1 
       (.I0(\rtp_timer_r_reg[0]_0 ),
        .I1(pass_open_bank_r),
        .I2(rtp_timer_r[1]),
        .I3(rtp_timer_r[0]),
        .O(\rtp_timer_r[0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h000000C2)) 
    \rtp_timer_r[1]_i_1 
       (.I0(Q[0]),
        .I1(rtp_timer_r[0]),
        .I2(rtp_timer_r[1]),
        .I3(pass_open_bank_r),
        .I4(\rtp_timer_r_reg[1]_0 ),
        .O(\rtp_timer_r[1]_i_1_n_0 ));
  FDRE \rtp_timer_r_reg[0] 
       (.C(ofs_rdy_r_reg_0),
        .CE(1'b1),
        .D(\rtp_timer_r[0]_i_1_n_0 ),
        .Q(rtp_timer_r[0]),
        .R(1'b0));
  FDRE \rtp_timer_r_reg[1] 
       (.C(ofs_rdy_r_reg_0),
        .CE(1'b1),
        .D(\rtp_timer_r[1]_i_1_n_0 ),
        .Q(rtp_timer_r[1]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair1163" *) 
  LUT3 #(
    .INIT(8'h60)) 
    \starve_limit_cntr_r[0]_i_1 
       (.I0(starve_limit_cntr_r[0]),
        .I1(starve_limit_cntr_r0),
        .I2(col_wait_r_reg_0),
        .O(\starve_limit_cntr_r[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1160" *) 
  LUT4 #(
    .INIT(16'h6A00)) 
    \starve_limit_cntr_r[1]_i_1 
       (.I0(starve_limit_cntr_r[1]),
        .I1(starve_limit_cntr_r0),
        .I2(starve_limit_cntr_r[0]),
        .I3(col_wait_r_reg_0),
        .O(\starve_limit_cntr_r[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1160" *) 
  LUT5 #(
    .INIT(32'h6AAA0000)) 
    \starve_limit_cntr_r[2]_i_1 
       (.I0(starve_limit_cntr_r[2]),
        .I1(starve_limit_cntr_r0),
        .I2(starve_limit_cntr_r[0]),
        .I3(starve_limit_cntr_r[1]),
        .I4(col_wait_r_reg_0),
        .O(\starve_limit_cntr_r[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h007F000000000000)) 
    \starve_limit_cntr_r[2]_i_2 
       (.I0(starve_limit_cntr_r[0]),
        .I1(starve_limit_cntr_r[1]),
        .I2(starve_limit_cntr_r[2]),
        .I3(Q[0]),
        .I4(demand_priority_r_reg_4),
        .I5(req_bank_rdy_r),
        .O(starve_limit_cntr_r0));
  FDRE \starve_limit_cntr_r_reg[0] 
       (.C(ofs_rdy_r_reg_0),
        .CE(1'b1),
        .D(\starve_limit_cntr_r[0]_i_1_n_0 ),
        .Q(starve_limit_cntr_r[0]),
        .R(1'b0));
  FDRE \starve_limit_cntr_r_reg[1] 
       (.C(ofs_rdy_r_reg_0),
        .CE(1'b1),
        .D(\starve_limit_cntr_r[1]_i_1_n_0 ),
        .Q(starve_limit_cntr_r[1]),
        .R(1'b0));
  FDRE \starve_limit_cntr_r_reg[2] 
       (.C(ofs_rdy_r_reg_0),
        .CE(1'b1),
        .D(\starve_limit_cntr_r[2]_i_1_n_0 ),
        .Q(starve_limit_cntr_r[2]),
        .R(1'b0));
  FDRE \wr_this_rank_r_reg[0] 
       (.C(ofs_rdy_r_reg_0),
        .CE(1'b1),
        .D(start_wtp_timer0),
        .Q(wr_this_rank_r),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_bank_state" *) 
module mig_mig_7series_v4_2_bank_state__parameterized0
   (act_wait_r_lcl_reg_0,
    act_this_rank_r,
    wr_this_rank_r,
    rd_this_rank_r,
    bm_end_r1,
    ras_timer_zero_r,
    pre_wait_r,
    col_wait_r_reg_0,
    req_bank_rdy_r,
    demand_priority_r_reg_0,
    demanded_prior_r_reg_0,
    ofs_rdy_r,
    pre_bm_end_ns,
    pre_passing_open_bank_ns,
    rnk_config_strobe_ns,
    demand_priority_r_reg_1,
    auto_pre_r_lcl_reg,
    \ras_timer_r_reg[1]_0 ,
    bm_end_r1_reg_0,
    demanded_prior_r_reg_1,
    demand_priority_r_reg_2,
    start_wtp_timer0,
    \rd_this_rank_r_reg[0]_0 ,
    p_91_out,
    col_wait_r_reg_1,
    req_bank_rdy_ns,
    ofs_rdy_r_reg_0,
    ofs_rdy_r0,
    Q,
    \rtp_timer_r_reg[1]_0 ,
    \rtp_timer_r_reg[1]_1 ,
    demand_priority_r_reg_3,
    demand_priority_r_reg_4,
    pre_bm_end_r_reg,
    pre_bm_end_r_reg_0,
    pass_open_bank_ns,
    act_wait_r_lcl_reg_1,
    act_wait_r_lcl_reg_2,
    \rnk_config_strobe_r_reg[0] ,
    req_bank_rdy_ns_1,
    \rnk_config_strobe_r_reg[0]_0 ,
    \rnk_config_strobe_r_reg[0]_1 ,
    act_wait_r_lcl_reg_3,
    act_wait_r_lcl_reg_4,
    ras_timer_zero_r_reg_0,
    ras_timer_zero_r_reg_1,
    demanded_prior_r_reg_2,
    demanded_prior_r_reg_3,
    demanded_prior_r_reg_4,
    demand_priority_r_reg_5,
    q_has_rd_3,
    demand_priority_r_reg_6,
    \starve_limit_cntr_r_reg[0]_0 ,
    \rtp_timer_r_reg[0]_0 ,
    D);
  output act_wait_r_lcl_reg_0;
  output [0:0]act_this_rank_r;
  output [0:0]wr_this_rank_r;
  output [0:0]rd_this_rank_r;
  output bm_end_r1;
  output ras_timer_zero_r;
  output pre_wait_r;
  output col_wait_r_reg_0;
  output req_bank_rdy_r;
  output demand_priority_r_reg_0;
  output demanded_prior_r_reg_0;
  output ofs_rdy_r;
  output pre_bm_end_ns;
  output pre_passing_open_bank_ns;
  output rnk_config_strobe_ns;
  output demand_priority_r_reg_1;
  output auto_pre_r_lcl_reg;
  output \ras_timer_r_reg[1]_0 ;
  output bm_end_r1_reg_0;
  output demanded_prior_r_reg_1;
  input demand_priority_r_reg_2;
  input start_wtp_timer0;
  input \rd_this_rank_r_reg[0]_0 ;
  input p_91_out;
  input col_wait_r_reg_1;
  input req_bank_rdy_ns;
  input ofs_rdy_r_reg_0;
  input ofs_rdy_r0;
  input [1:0]Q;
  input \rtp_timer_r_reg[1]_0 ;
  input \rtp_timer_r_reg[1]_1 ;
  input demand_priority_r_reg_3;
  input demand_priority_r_reg_4;
  input [0:0]pre_bm_end_r_reg;
  input pre_bm_end_r_reg_0;
  input pass_open_bank_ns;
  input act_wait_r_lcl_reg_1;
  input act_wait_r_lcl_reg_2;
  input \rnk_config_strobe_r_reg[0] ;
  input req_bank_rdy_ns_1;
  input \rnk_config_strobe_r_reg[0]_0 ;
  input \rnk_config_strobe_r_reg[0]_1 ;
  input [0:0]act_wait_r_lcl_reg_3;
  input act_wait_r_lcl_reg_4;
  input ras_timer_zero_r_reg_0;
  input ras_timer_zero_r_reg_1;
  input demanded_prior_r_reg_2;
  input demanded_prior_r_reg_3;
  input demanded_prior_r_reg_4;
  input demand_priority_r_reg_5;
  input q_has_rd_3;
  input demand_priority_r_reg_6;
  input \starve_limit_cntr_r_reg[0]_0 ;
  input \rtp_timer_r_reg[0]_0 ;
  input [1:0]D;

  wire [1:0]D;
  wire [1:0]Q;
  wire [0:0]act_this_rank_r;
  wire act_wait_ns;
  wire act_wait_r_lcl_i_2__1_n_0;
  wire act_wait_r_lcl_reg_0;
  wire act_wait_r_lcl_reg_1;
  wire act_wait_r_lcl_reg_2;
  wire [0:0]act_wait_r_lcl_reg_3;
  wire act_wait_r_lcl_reg_4;
  wire auto_pre_r_lcl_reg;
  wire bm_end_r1;
  wire bm_end_r1_reg_0;
  wire col_wait_r_reg_0;
  wire col_wait_r_reg_1;
  wire demand_priority_ns;
  wire demand_priority_r_i_3__0_n_0;
  wire demand_priority_r_reg_0;
  wire demand_priority_r_reg_1;
  wire demand_priority_r_reg_2;
  wire demand_priority_r_reg_3;
  wire demand_priority_r_reg_4;
  wire demand_priority_r_reg_5;
  wire demand_priority_r_reg_6;
  wire demanded_prior_ns;
  wire demanded_prior_r_reg_0;
  wire demanded_prior_r_reg_1;
  wire demanded_prior_r_reg_2;
  wire demanded_prior_r_reg_3;
  wire demanded_prior_r_reg_4;
  wire ofs_rdy_r;
  wire ofs_rdy_r0;
  wire ofs_rdy_r_reg_0;
  wire p_91_out;
  wire pass_open_bank_ns;
  wire pre_bm_end_ns;
  wire [0:0]pre_bm_end_r_reg;
  wire pre_bm_end_r_reg_0;
  wire pre_passing_open_bank_ns;
  wire pre_wait_ns;
  wire pre_wait_r;
  wire pre_wait_r_i_2__0_n_0;
  wire q_has_rd_3;
  wire \ras_timer_r[1]_i_5__0_n_0 ;
  wire \ras_timer_r_reg[1]_0 ;
  wire \ras_timer_r_reg_n_0_[0] ;
  wire \ras_timer_r_reg_n_0_[1] ;
  wire ras_timer_zero_r;
  wire ras_timer_zero_r_i_1__0_n_0;
  wire ras_timer_zero_r_reg_0;
  wire ras_timer_zero_r_reg_1;
  wire [0:0]rd_this_rank_r;
  wire \rd_this_rank_r_reg[0]_0 ;
  wire req_bank_rdy_ns;
  wire req_bank_rdy_ns_1;
  wire req_bank_rdy_r;
  wire rnk_config_strobe_ns;
  wire \rnk_config_strobe_r_reg[0] ;
  wire \rnk_config_strobe_r_reg[0]_0 ;
  wire \rnk_config_strobe_r_reg[0]_1 ;
  wire [1:0]rtp_timer_r;
  wire \rtp_timer_r[0]_i_1__0_n_0 ;
  wire \rtp_timer_r[1]_i_1__0_n_0 ;
  wire \rtp_timer_r_reg[0]_0 ;
  wire \rtp_timer_r_reg[1]_0 ;
  wire \rtp_timer_r_reg[1]_1 ;
  wire start_wtp_timer0;
  wire [2:0]starve_limit_cntr_r;
  wire starve_limit_cntr_r0;
  wire \starve_limit_cntr_r[0]_i_1_n_0 ;
  wire \starve_limit_cntr_r[1]_i_1_n_0 ;
  wire \starve_limit_cntr_r[2]_i_1_n_0 ;
  wire \starve_limit_cntr_r_reg[0]_0 ;
  wire [0:0]wr_this_rank_r;

  FDRE \act_this_rank_r_reg[0] 
       (.C(demand_priority_r_reg_2),
        .CE(1'b1),
        .D(act_wait_r_lcl_reg_0),
        .Q(act_this_rank_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF88F8)) 
    act_wait_r_lcl_i_1__2
       (.I0(act_wait_r_lcl_reg_0),
        .I1(act_wait_r_lcl_i_2__1_n_0),
        .I2(\rtp_timer_r_reg[1]_0 ),
        .I3(act_wait_r_lcl_reg_2),
        .I4(act_wait_r_lcl_reg_1),
        .I5(bm_end_r1),
        .O(act_wait_ns));
  (* SOFT_HLUTNM = "soft_lutpair1171" *) 
  LUT3 #(
    .INIT(8'h07)) 
    act_wait_r_lcl_i_2__1
       (.I0(act_wait_r_lcl_reg_3),
        .I1(act_wait_r_lcl_reg_0),
        .I2(act_wait_r_lcl_reg_4),
        .O(act_wait_r_lcl_i_2__1_n_0));
  FDRE act_wait_r_lcl_reg
       (.C(demand_priority_r_reg_2),
        .CE(1'b1),
        .D(act_wait_ns),
        .Q(act_wait_r_lcl_reg_0),
        .R(1'b0));
  FDRE bm_end_r1_reg
       (.C(demand_priority_r_reg_2),
        .CE(1'b1),
        .D(p_91_out),
        .Q(bm_end_r1),
        .R(1'b0));
  FDRE col_wait_r_reg
       (.C(demand_priority_r_reg_2),
        .CE(1'b1),
        .D(col_wait_r_reg_1),
        .Q(col_wait_r_reg_0),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h88888808)) 
    demand_priority_r_i_1__2
       (.I0(col_wait_r_reg_1),
        .I1(demand_priority_r_reg_3),
        .I2(demand_priority_r_reg_4),
        .I3(demand_priority_r_i_3__0_n_0),
        .I4(demand_priority_r_reg_0),
        .O(demand_priority_ns));
  LUT6 #(
    .INIT(64'h0000000080800080)) 
    demand_priority_r_i_3__0
       (.I0(starve_limit_cntr_r[0]),
        .I1(starve_limit_cntr_r[1]),
        .I2(starve_limit_cntr_r[2]),
        .I3(demand_priority_r_reg_5),
        .I4(q_has_rd_3),
        .I5(demand_priority_r_reg_6),
        .O(demand_priority_r_i_3__0_n_0));
  FDRE demand_priority_r_reg
       (.C(demand_priority_r_reg_2),
        .CE(1'b1),
        .D(demand_priority_ns),
        .Q(demand_priority_r_reg_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h00000D00DDDDDDDD)) 
    demanded_prior_r_i_1__1
       (.I0(demand_priority_r_reg_0),
        .I1(demanded_prior_r_reg_0),
        .I2(Q[1]),
        .I3(demanded_prior_r_reg_3),
        .I4(demanded_prior_r_reg_2),
        .I5(demanded_prior_r_reg_4),
        .O(demanded_prior_ns));
  FDRE demanded_prior_r_reg
       (.C(demand_priority_r_reg_2),
        .CE(1'b1),
        .D(demanded_prior_ns),
        .Q(demanded_prior_r_reg_0),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair1169" *) 
  LUT4 #(
    .INIT(16'h1000)) 
    \grant_r[3]_i_3__1 
       (.I0(pre_bm_end_r_reg_0),
        .I1(pre_bm_end_r_reg),
        .I2(pre_wait_r),
        .I3(ras_timer_zero_r),
        .O(auto_pre_r_lcl_reg));
  LUT6 #(
    .INIT(64'h0404040404FF0404)) 
    i___84_i_1
       (.I0(demanded_prior_r_reg_0),
        .I1(demand_priority_r_reg_0),
        .I2(Q[0]),
        .I3(demanded_prior_r_reg_2),
        .I4(demanded_prior_r_reg_3),
        .I5(Q[1]),
        .O(demanded_prior_r_reg_1));
  FDRE #(
    .INIT(1'b0)) 
    ofs_rdy_r_reg
       (.C(demand_priority_r_reg_2),
        .CE(1'b1),
        .D(ofs_rdy_r0),
        .Q(ofs_rdy_r),
        .R(ofs_rdy_r_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair1169" *) 
  LUT5 #(
    .INIT(32'hEAEAEAAA)) 
    pre_bm_end_r_i_1
       (.I0(pre_passing_open_bank_ns),
        .I1(ras_timer_zero_r),
        .I2(pre_wait_r),
        .I3(pre_bm_end_r_reg),
        .I4(pre_bm_end_r_reg_0),
        .O(pre_bm_end_ns));
  LUT6 #(
    .INIT(64'hAAA8AAAAAAA8AAA8)) 
    pre_passing_open_bank_r_i_1
       (.I0(pass_open_bank_ns),
        .I1(Q[0]),
        .I2(rtp_timer_r[0]),
        .I3(rtp_timer_r[1]),
        .I4(ras_timer_zero_r),
        .I5(pre_wait_r),
        .O(pre_passing_open_bank_ns));
  LUT6 #(
    .INIT(64'h4444444444454444)) 
    pre_wait_r_i_1
       (.I0(pass_open_bank_ns),
        .I1(pre_wait_r_i_2__0_n_0),
        .I2(\rtp_timer_r_reg[1]_0 ),
        .I3(act_wait_r_lcl_reg_1),
        .I4(rtp_timer_r[0]),
        .I5(rtp_timer_r[1]),
        .O(pre_wait_ns));
  LUT5 #(
    .INIT(32'h10101050)) 
    pre_wait_r_i_2__0
       (.I0(ras_timer_zero_r_reg_0),
        .I1(ras_timer_zero_r),
        .I2(pre_wait_r),
        .I3(pre_bm_end_r_reg),
        .I4(pre_bm_end_r_reg_0),
        .O(pre_wait_r_i_2__0_n_0));
  FDRE pre_wait_r_reg
       (.C(demand_priority_r_reg_2),
        .CE(1'b1),
        .D(pre_wait_ns),
        .Q(pre_wait_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0010111100100010)) 
    \ras_timer_r[0]_i_3__0 
       (.I0(bm_end_r1),
        .I1(ras_timer_zero_r_reg_0),
        .I2(\ras_timer_r_reg_n_0_[1] ),
        .I3(\ras_timer_r_reg_n_0_[0] ),
        .I4(\rd_this_rank_r_reg[0]_0 ),
        .I5(Q[0]),
        .O(bm_end_r1_reg_0));
  LUT6 #(
    .INIT(64'h4410555544104410)) 
    \ras_timer_r[1]_i_3__0 
       (.I0(ras_timer_zero_r_reg_1),
        .I1(\ras_timer_r_reg_n_0_[1] ),
        .I2(\ras_timer_r[1]_i_5__0_n_0 ),
        .I3(\ras_timer_r_reg_n_0_[0] ),
        .I4(\rd_this_rank_r_reg[0]_0 ),
        .I5(Q[0]),
        .O(\ras_timer_r_reg[1]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1171" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ras_timer_r[1]_i_5__0 
       (.I0(act_wait_r_lcl_reg_0),
        .I1(act_wait_r_lcl_reg_3),
        .O(\ras_timer_r[1]_i_5__0_n_0 ));
  FDRE \ras_timer_r_reg[0] 
       (.C(demand_priority_r_reg_2),
        .CE(1'b1),
        .D(D[0]),
        .Q(\ras_timer_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \ras_timer_r_reg[1] 
       (.C(demand_priority_r_reg_2),
        .CE(1'b1),
        .D(D[1]),
        .Q(\ras_timer_r_reg_n_0_[1] ),
        .R(1'b0));
  LUT2 #(
    .INIT(4'h1)) 
    ras_timer_zero_r_i_1__0
       (.I0(\ras_timer_r_reg[1]_0 ),
        .I1(bm_end_r1_reg_0),
        .O(ras_timer_zero_r_i_1__0_n_0));
  FDRE ras_timer_zero_r_reg
       (.C(demand_priority_r_reg_2),
        .CE(1'b1),
        .D(ras_timer_zero_r_i_1__0_n_0),
        .Q(ras_timer_zero_r),
        .R(1'b0));
  FDRE \rd_this_rank_r_reg[0] 
       (.C(demand_priority_r_reg_2),
        .CE(1'b1),
        .D(\rd_this_rank_r_reg[0]_0 ),
        .Q(rd_this_rank_r),
        .R(1'b0));
  FDRE req_bank_rdy_r_reg
       (.C(demand_priority_r_reg_2),
        .CE(1'b1),
        .D(req_bank_rdy_ns),
        .Q(req_bank_rdy_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF33202020)) 
    \rnk_config_strobe_r[0]_i_1 
       (.I0(demand_priority_r_reg_1),
        .I1(\rnk_config_strobe_r_reg[0] ),
        .I2(req_bank_rdy_ns_1),
        .I3(req_bank_rdy_ns),
        .I4(\rnk_config_strobe_r_reg[0]_0 ),
        .I5(\rnk_config_strobe_r_reg[0]_1 ),
        .O(rnk_config_strobe_ns));
  LUT5 #(
    .INIT(32'hFFEFAAAA)) 
    \rnk_config_strobe_r[0]_i_2 
       (.I0(demanded_prior_r_reg_3),
        .I1(Q[0]),
        .I2(demand_priority_r_reg_0),
        .I3(demanded_prior_r_reg_0),
        .I4(demanded_prior_r_reg_4),
        .O(demand_priority_r_reg_1));
  LUT4 #(
    .INIT(16'h0010)) 
    \rtp_timer_r[0]_i_1__0 
       (.I0(\rtp_timer_r_reg[0]_0 ),
        .I1(\rtp_timer_r_reg[1]_0 ),
        .I2(rtp_timer_r[1]),
        .I3(rtp_timer_r[0]),
        .O(\rtp_timer_r[0]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'h000000C2)) 
    \rtp_timer_r[1]_i_1__0 
       (.I0(Q[0]),
        .I1(rtp_timer_r[0]),
        .I2(rtp_timer_r[1]),
        .I3(\rtp_timer_r_reg[1]_0 ),
        .I4(\rtp_timer_r_reg[1]_1 ),
        .O(\rtp_timer_r[1]_i_1__0_n_0 ));
  FDRE \rtp_timer_r_reg[0] 
       (.C(demand_priority_r_reg_2),
        .CE(1'b1),
        .D(\rtp_timer_r[0]_i_1__0_n_0 ),
        .Q(rtp_timer_r[0]),
        .R(1'b0));
  FDRE \rtp_timer_r_reg[1] 
       (.C(demand_priority_r_reg_2),
        .CE(1'b1),
        .D(\rtp_timer_r[1]_i_1__0_n_0 ),
        .Q(rtp_timer_r[1]),
        .R(1'b0));
  LUT3 #(
    .INIT(8'h60)) 
    \starve_limit_cntr_r[0]_i_1 
       (.I0(starve_limit_cntr_r[0]),
        .I1(starve_limit_cntr_r0),
        .I2(col_wait_r_reg_0),
        .O(\starve_limit_cntr_r[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1170" *) 
  LUT4 #(
    .INIT(16'h6A00)) 
    \starve_limit_cntr_r[1]_i_1 
       (.I0(starve_limit_cntr_r[1]),
        .I1(starve_limit_cntr_r0),
        .I2(starve_limit_cntr_r[0]),
        .I3(col_wait_r_reg_0),
        .O(\starve_limit_cntr_r[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1170" *) 
  LUT5 #(
    .INIT(32'h6AAA0000)) 
    \starve_limit_cntr_r[2]_i_1 
       (.I0(starve_limit_cntr_r[2]),
        .I1(starve_limit_cntr_r0),
        .I2(starve_limit_cntr_r[0]),
        .I3(starve_limit_cntr_r[1]),
        .I4(col_wait_r_reg_0),
        .O(\starve_limit_cntr_r[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00007F0000000000)) 
    \starve_limit_cntr_r[2]_i_2__0 
       (.I0(starve_limit_cntr_r[0]),
        .I1(starve_limit_cntr_r[1]),
        .I2(starve_limit_cntr_r[2]),
        .I3(\starve_limit_cntr_r_reg[0]_0 ),
        .I4(Q[0]),
        .I5(req_bank_rdy_r),
        .O(starve_limit_cntr_r0));
  FDRE \starve_limit_cntr_r_reg[0] 
       (.C(demand_priority_r_reg_2),
        .CE(1'b1),
        .D(\starve_limit_cntr_r[0]_i_1_n_0 ),
        .Q(starve_limit_cntr_r[0]),
        .R(1'b0));
  FDRE \starve_limit_cntr_r_reg[1] 
       (.C(demand_priority_r_reg_2),
        .CE(1'b1),
        .D(\starve_limit_cntr_r[1]_i_1_n_0 ),
        .Q(starve_limit_cntr_r[1]),
        .R(1'b0));
  FDRE \starve_limit_cntr_r_reg[2] 
       (.C(demand_priority_r_reg_2),
        .CE(1'b1),
        .D(\starve_limit_cntr_r[2]_i_1_n_0 ),
        .Q(starve_limit_cntr_r[2]),
        .R(1'b0));
  FDRE \wr_this_rank_r_reg[0] 
       (.C(demand_priority_r_reg_2),
        .CE(1'b1),
        .D(start_wtp_timer0),
        .Q(wr_this_rank_r),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_bank_state" *) 
module mig_mig_7series_v4_2_bank_state__parameterized1
   (act_wait_r_lcl_reg_0,
    act_this_rank_r,
    wr_this_rank_r,
    rd_this_rank_r,
    bm_end_r1_0,
    ras_timer_zero_r,
    pre_wait_r,
    col_wait_r_reg_0,
    demand_priority_r_reg_0,
    demanded_prior_r_reg_0,
    override_demand_r,
    ofs_rdy_r,
    pre_bm_end_ns,
    pre_passing_open_bank_ns,
    ras_timer_zero_r_reg_0,
    auto_pre_r_lcl_reg,
    \ras_timer_r_reg[1]_0 ,
    bm_end_r1_reg_0,
    demand_priority_r_reg_1,
    act_wait_r_lcl_reg_1,
    ofs_rdy_r_reg_0,
    start_wtp_timer0,
    \rd_this_rank_r_reg[0]_0 ,
    bm_end_r1_reg_1,
    col_wait_r_reg_1,
    req_bank_rdy_ns,
    override_demand_ns,
    ofs_rdy_r_reg_1,
    ofs_rdy_r0,
    Q,
    pass_open_bank_r,
    pre_wait_r_reg_0,
    demand_priority_r_reg_2,
    demand_priority_r_reg_3,
    act_wait_r_lcl_reg_2,
    act_wait_r_lcl_reg_3,
    pre_bm_end_r_reg,
    pre_bm_end_r_reg_0,
    pass_open_bank_ns,
    \pre_4_1_1T_arb.granted_pre_r_reg ,
    ras_timer_zero_r_reg_1,
    ras_timer_zero_r_reg_2,
    demand_priority_r_1,
    demanded_prior_r_reg_1,
    demanded_prior_r_2,
    \cmd_pipe_plus.mc_address_reg[38] ,
    \cmd_pipe_plus.mc_address_reg[38]_0 ,
    row_cmd_wr,
    demand_priority_r_reg_4,
    demand_priority_r_reg_5,
    q_has_rd_7,
    \rtp_timer_r_reg[0]_0 ,
    D);
  output act_wait_r_lcl_reg_0;
  output [0:0]act_this_rank_r;
  output [0:0]wr_this_rank_r;
  output [0:0]rd_this_rank_r;
  output bm_end_r1_0;
  output ras_timer_zero_r;
  output pre_wait_r;
  output col_wait_r_reg_0;
  output demand_priority_r_reg_0;
  output demanded_prior_r_reg_0;
  output override_demand_r;
  output ofs_rdy_r;
  output pre_bm_end_ns;
  output pre_passing_open_bank_ns;
  output ras_timer_zero_r_reg_0;
  output auto_pre_r_lcl_reg;
  output \ras_timer_r_reg[1]_0 ;
  output bm_end_r1_reg_0;
  output demand_priority_r_reg_1;
  output act_wait_r_lcl_reg_1;
  input ofs_rdy_r_reg_0;
  input start_wtp_timer0;
  input \rd_this_rank_r_reg[0]_0 ;
  input bm_end_r1_reg_1;
  input col_wait_r_reg_1;
  input req_bank_rdy_ns;
  input override_demand_ns;
  input ofs_rdy_r_reg_1;
  input ofs_rdy_r0;
  input [1:0]Q;
  input pass_open_bank_r;
  input pre_wait_r_reg_0;
  input demand_priority_r_reg_2;
  input demand_priority_r_reg_3;
  input [0:0]act_wait_r_lcl_reg_2;
  input act_wait_r_lcl_reg_3;
  input [1:0]pre_bm_end_r_reg;
  input pre_bm_end_r_reg_0;
  input pass_open_bank_ns;
  input \pre_4_1_1T_arb.granted_pre_r_reg ;
  input ras_timer_zero_r_reg_1;
  input ras_timer_zero_r_reg_2;
  input demand_priority_r_1;
  input demanded_prior_r_reg_1;
  input demanded_prior_r_2;
  input [0:0]\cmd_pipe_plus.mc_address_reg[38] ;
  input [0:0]\cmd_pipe_plus.mc_address_reg[38]_0 ;
  input [0:0]row_cmd_wr;
  input demand_priority_r_reg_4;
  input demand_priority_r_reg_5;
  input q_has_rd_7;
  input \rtp_timer_r_reg[0]_0 ;
  input [1:0]D;

  wire [1:0]D;
  wire [1:0]Q;
  wire [0:0]act_this_rank_r;
  wire act_wait_ns;
  wire act_wait_r_lcl_i_2__0_n_0;
  wire act_wait_r_lcl_reg_0;
  wire act_wait_r_lcl_reg_1;
  wire [0:0]act_wait_r_lcl_reg_2;
  wire act_wait_r_lcl_reg_3;
  wire auto_pre_r_lcl_reg;
  wire bm_end_r1_0;
  wire bm_end_r1_reg_0;
  wire bm_end_r1_reg_1;
  wire [0:0]\cmd_pipe_plus.mc_address_reg[38] ;
  wire [0:0]\cmd_pipe_plus.mc_address_reg[38]_0 ;
  wire col_wait_r_reg_0;
  wire col_wait_r_reg_1;
  wire demand_priority_ns;
  wire demand_priority_r_1;
  wire demand_priority_r_i_3__1_n_0;
  wire demand_priority_r_i_4__1_n_0;
  wire demand_priority_r_reg_0;
  wire demand_priority_r_reg_1;
  wire demand_priority_r_reg_2;
  wire demand_priority_r_reg_3;
  wire demand_priority_r_reg_4;
  wire demand_priority_r_reg_5;
  wire demanded_prior_ns;
  wire demanded_prior_r_2;
  wire demanded_prior_r_reg_0;
  wire demanded_prior_r_reg_1;
  wire ofs_rdy_r;
  wire ofs_rdy_r0;
  wire ofs_rdy_r_reg_0;
  wire ofs_rdy_r_reg_1;
  wire override_demand_ns;
  wire override_demand_r;
  wire pass_open_bank_ns;
  wire pass_open_bank_r;
  wire \pre_4_1_1T_arb.granted_pre_r_reg ;
  wire pre_bm_end_ns;
  wire [1:0]pre_bm_end_r_reg;
  wire pre_bm_end_r_reg_0;
  wire pre_passing_open_bank_ns;
  wire pre_wait_ns;
  wire pre_wait_r;
  wire pre_wait_r_i_2__1_n_0;
  wire pre_wait_r_reg_0;
  wire q_has_rd_7;
  wire \ras_timer_r[1]_i_5__1_n_0 ;
  wire \ras_timer_r_reg[1]_0 ;
  wire \ras_timer_r_reg_n_0_[0] ;
  wire \ras_timer_r_reg_n_0_[1] ;
  wire ras_timer_zero_r;
  wire ras_timer_zero_r_i_1__1_n_0;
  wire ras_timer_zero_r_reg_0;
  wire ras_timer_zero_r_reg_1;
  wire ras_timer_zero_r_reg_2;
  wire [0:0]rd_this_rank_r;
  wire \rd_this_rank_r_reg[0]_0 ;
  wire req_bank_rdy_ns;
  wire req_bank_rdy_r;
  wire [0:0]row_cmd_wr;
  wire [1:0]rtp_timer_r;
  wire \rtp_timer_r[0]_i_1__1_n_0 ;
  wire \rtp_timer_r[1]_i_1__1_n_0 ;
  wire \rtp_timer_r_reg[0]_0 ;
  wire start_wtp_timer0;
  wire [2:0]starve_limit_cntr_r;
  wire starve_limit_cntr_r0;
  wire \starve_limit_cntr_r[0]_i_1_n_0 ;
  wire \starve_limit_cntr_r[1]_i_1_n_0 ;
  wire \starve_limit_cntr_r[2]_i_1_n_0 ;
  wire [0:0]wr_this_rank_r;

  FDRE \act_this_rank_r_reg[0] 
       (.C(ofs_rdy_r_reg_0),
        .CE(1'b1),
        .D(act_wait_r_lcl_reg_0),
        .Q(act_this_rank_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFF888)) 
    act_wait_r_lcl_i_1__1
       (.I0(act_wait_r_lcl_reg_0),
        .I1(act_wait_r_lcl_i_2__0_n_0),
        .I2(pass_open_bank_r),
        .I3(bm_end_r1_reg_1),
        .I4(pre_wait_r_reg_0),
        .I5(bm_end_r1_0),
        .O(act_wait_ns));
  (* SOFT_HLUTNM = "soft_lutpair1179" *) 
  LUT3 #(
    .INIT(8'h07)) 
    act_wait_r_lcl_i_2__0
       (.I0(act_wait_r_lcl_reg_2),
        .I1(act_wait_r_lcl_reg_0),
        .I2(act_wait_r_lcl_reg_3),
        .O(act_wait_r_lcl_i_2__0_n_0));
  FDRE act_wait_r_lcl_reg
       (.C(ofs_rdy_r_reg_0),
        .CE(1'b1),
        .D(act_wait_ns),
        .Q(act_wait_r_lcl_reg_0),
        .R(1'b0));
  FDRE bm_end_r1_reg
       (.C(ofs_rdy_r_reg_0),
        .CE(1'b1),
        .D(bm_end_r1_reg_1),
        .Q(bm_end_r1_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h88888888F0000000)) 
    \cmd_pipe_plus.mc_address[38]_i_3 
       (.I0(act_wait_r_lcl_reg_0),
        .I1(\cmd_pipe_plus.mc_address_reg[38] ),
        .I2(\cmd_pipe_plus.mc_address_reg[38]_0 ),
        .I3(row_cmd_wr),
        .I4(pre_bm_end_r_reg[0]),
        .I5(pre_bm_end_r_reg[1]),
        .O(act_wait_r_lcl_reg_1));
  FDRE col_wait_r_reg
       (.C(ofs_rdy_r_reg_0),
        .CE(1'b1),
        .D(col_wait_r_reg_1),
        .Q(col_wait_r_reg_0),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h88888808)) 
    demand_priority_r_i_1__1
       (.I0(col_wait_r_reg_1),
        .I1(demand_priority_r_reg_2),
        .I2(demand_priority_r_reg_3),
        .I3(demand_priority_r_i_3__1_n_0),
        .I4(demand_priority_r_reg_0),
        .O(demand_priority_ns));
  LUT6 #(
    .INIT(64'h0000000040400040)) 
    demand_priority_r_i_3__1
       (.I0(Q[1]),
        .I1(demand_priority_r_reg_4),
        .I2(req_bank_rdy_r),
        .I3(demand_priority_r_reg_5),
        .I4(q_has_rd_7),
        .I5(demand_priority_r_i_4__1_n_0),
        .O(demand_priority_r_i_3__1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair1178" *) 
  LUT3 #(
    .INIT(8'h7F)) 
    demand_priority_r_i_4__1
       (.I0(starve_limit_cntr_r[2]),
        .I1(starve_limit_cntr_r[1]),
        .I2(starve_limit_cntr_r[0]),
        .O(demand_priority_r_i_4__1_n_0));
  FDRE demand_priority_r_reg
       (.C(ofs_rdy_r_reg_0),
        .CE(1'b1),
        .D(demand_priority_ns),
        .Q(demand_priority_r_reg_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h00000D00DDDDDDDD)) 
    demanded_prior_r_i_1__2
       (.I0(demand_priority_r_reg_0),
        .I1(demanded_prior_r_reg_0),
        .I2(Q[0]),
        .I3(demand_priority_r_1),
        .I4(demanded_prior_r_2),
        .I5(demanded_prior_r_reg_1),
        .O(demanded_prior_ns));
  FDRE demanded_prior_r_reg
       (.C(ofs_rdy_r_reg_0),
        .CE(1'b1),
        .D(demanded_prior_ns),
        .Q(demanded_prior_r_reg_0),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair1176" *) 
  LUT4 #(
    .INIT(16'h1000)) 
    \grant_r[3]_i_2__1 
       (.I0(pre_bm_end_r_reg_0),
        .I1(pre_bm_end_r_reg[1]),
        .I2(pre_wait_r),
        .I3(ras_timer_zero_r),
        .O(auto_pre_r_lcl_reg));
  LUT5 #(
    .INIT(32'hFFEFAAAA)) 
    i___40_i_2
       (.I0(demand_priority_r_1),
        .I1(Q[1]),
        .I2(demand_priority_r_reg_0),
        .I3(demanded_prior_r_reg_0),
        .I4(demanded_prior_r_reg_1),
        .O(demand_priority_r_reg_1));
  FDRE #(
    .INIT(1'b0)) 
    ofs_rdy_r_reg
       (.C(ofs_rdy_r_reg_0),
        .CE(1'b1),
        .D(ofs_rdy_r0),
        .Q(ofs_rdy_r),
        .R(ofs_rdy_r_reg_1));
  FDRE override_demand_r_reg
       (.C(ofs_rdy_r_reg_0),
        .CE(1'b1),
        .D(override_demand_ns),
        .Q(override_demand_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h0000FFF7)) 
    \pre_4_1_1T_arb.granted_pre_r_i_2 
       (.I0(ras_timer_zero_r),
        .I1(pre_wait_r),
        .I2(pre_bm_end_r_reg[1]),
        .I3(pre_bm_end_r_reg_0),
        .I4(\pre_4_1_1T_arb.granted_pre_r_reg ),
        .O(ras_timer_zero_r_reg_0));
  LUT5 #(
    .INIT(32'hEAEAEAAA)) 
    pre_bm_end_r_i_1__1
       (.I0(pre_passing_open_bank_ns),
        .I1(ras_timer_zero_r),
        .I2(pre_wait_r),
        .I3(pre_bm_end_r_reg[1]),
        .I4(pre_bm_end_r_reg_0),
        .O(pre_bm_end_ns));
  LUT6 #(
    .INIT(64'hAAA8AAAAAAA8AAA8)) 
    pre_passing_open_bank_r_i_1__1
       (.I0(pass_open_bank_ns),
        .I1(Q[1]),
        .I2(rtp_timer_r[0]),
        .I3(rtp_timer_r[1]),
        .I4(ras_timer_zero_r),
        .I5(pre_wait_r),
        .O(pre_passing_open_bank_ns));
  LUT6 #(
    .INIT(64'h4444444444454444)) 
    pre_wait_r_i_1__1
       (.I0(pass_open_bank_ns),
        .I1(pre_wait_r_i_2__1_n_0),
        .I2(pass_open_bank_r),
        .I3(pre_wait_r_reg_0),
        .I4(rtp_timer_r[0]),
        .I5(rtp_timer_r[1]),
        .O(pre_wait_ns));
  (* SOFT_HLUTNM = "soft_lutpair1176" *) 
  LUT5 #(
    .INIT(32'h10101050)) 
    pre_wait_r_i_2__1
       (.I0(ras_timer_zero_r_reg_1),
        .I1(ras_timer_zero_r),
        .I2(pre_wait_r),
        .I3(pre_bm_end_r_reg[1]),
        .I4(pre_bm_end_r_reg_0),
        .O(pre_wait_r_i_2__1_n_0));
  FDRE pre_wait_r_reg
       (.C(ofs_rdy_r_reg_0),
        .CE(1'b1),
        .D(pre_wait_ns),
        .Q(pre_wait_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0010111100100010)) 
    \ras_timer_r[0]_i_3__1 
       (.I0(bm_end_r1_0),
        .I1(ras_timer_zero_r_reg_1),
        .I2(\ras_timer_r_reg_n_0_[1] ),
        .I3(\ras_timer_r_reg_n_0_[0] ),
        .I4(\rd_this_rank_r_reg[0]_0 ),
        .I5(Q[1]),
        .O(bm_end_r1_reg_0));
  LUT6 #(
    .INIT(64'h4041555540414041)) 
    \ras_timer_r[1]_i_3__1 
       (.I0(ras_timer_zero_r_reg_2),
        .I1(\ras_timer_r_reg_n_0_[1] ),
        .I2(\ras_timer_r_reg_n_0_[0] ),
        .I3(\ras_timer_r[1]_i_5__1_n_0 ),
        .I4(\rd_this_rank_r_reg[0]_0 ),
        .I5(Q[1]),
        .O(\ras_timer_r_reg[1]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1179" *) 
  LUT2 #(
    .INIT(4'h7)) 
    \ras_timer_r[1]_i_5__1 
       (.I0(act_wait_r_lcl_reg_0),
        .I1(act_wait_r_lcl_reg_2),
        .O(\ras_timer_r[1]_i_5__1_n_0 ));
  FDRE \ras_timer_r_reg[0] 
       (.C(ofs_rdy_r_reg_0),
        .CE(1'b1),
        .D(D[0]),
        .Q(\ras_timer_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \ras_timer_r_reg[1] 
       (.C(ofs_rdy_r_reg_0),
        .CE(1'b1),
        .D(D[1]),
        .Q(\ras_timer_r_reg_n_0_[1] ),
        .R(1'b0));
  LUT2 #(
    .INIT(4'h1)) 
    ras_timer_zero_r_i_1__1
       (.I0(\ras_timer_r_reg[1]_0 ),
        .I1(bm_end_r1_reg_0),
        .O(ras_timer_zero_r_i_1__1_n_0));
  FDRE ras_timer_zero_r_reg
       (.C(ofs_rdy_r_reg_0),
        .CE(1'b1),
        .D(ras_timer_zero_r_i_1__1_n_0),
        .Q(ras_timer_zero_r),
        .R(1'b0));
  FDRE \rd_this_rank_r_reg[0] 
       (.C(ofs_rdy_r_reg_0),
        .CE(1'b1),
        .D(\rd_this_rank_r_reg[0]_0 ),
        .Q(rd_this_rank_r),
        .R(1'b0));
  FDRE req_bank_rdy_r_reg
       (.C(ofs_rdy_r_reg_0),
        .CE(1'b1),
        .D(req_bank_rdy_ns),
        .Q(req_bank_rdy_r),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0010)) 
    \rtp_timer_r[0]_i_1__1 
       (.I0(\rtp_timer_r_reg[0]_0 ),
        .I1(pass_open_bank_r),
        .I2(rtp_timer_r[1]),
        .I3(rtp_timer_r[0]),
        .O(\rtp_timer_r[0]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'h000000C2)) 
    \rtp_timer_r[1]_i_1__1 
       (.I0(Q[1]),
        .I1(rtp_timer_r[0]),
        .I2(rtp_timer_r[1]),
        .I3(pass_open_bank_r),
        .I4(pre_wait_r_reg_0),
        .O(\rtp_timer_r[1]_i_1__1_n_0 ));
  FDRE \rtp_timer_r_reg[0] 
       (.C(ofs_rdy_r_reg_0),
        .CE(1'b1),
        .D(\rtp_timer_r[0]_i_1__1_n_0 ),
        .Q(rtp_timer_r[0]),
        .R(1'b0));
  FDRE \rtp_timer_r_reg[1] 
       (.C(ofs_rdy_r_reg_0),
        .CE(1'b1),
        .D(\rtp_timer_r[1]_i_1__1_n_0 ),
        .Q(rtp_timer_r[1]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair1178" *) 
  LUT3 #(
    .INIT(8'h60)) 
    \starve_limit_cntr_r[0]_i_1 
       (.I0(starve_limit_cntr_r[0]),
        .I1(starve_limit_cntr_r0),
        .I2(col_wait_r_reg_0),
        .O(\starve_limit_cntr_r[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1177" *) 
  LUT4 #(
    .INIT(16'h6A00)) 
    \starve_limit_cntr_r[1]_i_1 
       (.I0(starve_limit_cntr_r[1]),
        .I1(starve_limit_cntr_r0),
        .I2(starve_limit_cntr_r[0]),
        .I3(col_wait_r_reg_0),
        .O(\starve_limit_cntr_r[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1177" *) 
  LUT5 #(
    .INIT(32'h6AAA0000)) 
    \starve_limit_cntr_r[2]_i_1 
       (.I0(starve_limit_cntr_r[2]),
        .I1(starve_limit_cntr_r0),
        .I2(starve_limit_cntr_r[0]),
        .I3(starve_limit_cntr_r[1]),
        .I4(col_wait_r_reg_0),
        .O(\starve_limit_cntr_r[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h007F000000000000)) 
    \starve_limit_cntr_r[2]_i_2__1 
       (.I0(starve_limit_cntr_r[0]),
        .I1(starve_limit_cntr_r[1]),
        .I2(starve_limit_cntr_r[2]),
        .I3(Q[1]),
        .I4(demand_priority_r_reg_4),
        .I5(req_bank_rdy_r),
        .O(starve_limit_cntr_r0));
  FDRE \starve_limit_cntr_r_reg[0] 
       (.C(ofs_rdy_r_reg_0),
        .CE(1'b1),
        .D(\starve_limit_cntr_r[0]_i_1_n_0 ),
        .Q(starve_limit_cntr_r[0]),
        .R(1'b0));
  FDRE \starve_limit_cntr_r_reg[1] 
       (.C(ofs_rdy_r_reg_0),
        .CE(1'b1),
        .D(\starve_limit_cntr_r[1]_i_1_n_0 ),
        .Q(starve_limit_cntr_r[1]),
        .R(1'b0));
  FDRE \starve_limit_cntr_r_reg[2] 
       (.C(ofs_rdy_r_reg_0),
        .CE(1'b1),
        .D(\starve_limit_cntr_r[2]_i_1_n_0 ),
        .Q(starve_limit_cntr_r[2]),
        .R(1'b0));
  FDRE \wr_this_rank_r_reg[0] 
       (.C(ofs_rdy_r_reg_0),
        .CE(1'b1),
        .D(start_wtp_timer0),
        .Q(wr_this_rank_r),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_bank_state" *) 
module mig_mig_7series_v4_2_bank_state__parameterized2
   (act_wait_r_lcl_reg_0,
    act_this_rank_r,
    wr_this_rank_r,
    rd_this_rank_r,
    bm_end_r1_1,
    ras_timer_zero_r,
    pre_wait_r,
    col_wait_r_reg_0,
    demand_priority_r_reg_0,
    demanded_prior_r_reg_0,
    ofs_rdy_r,
    pre_bm_end_ns,
    pre_passing_open_bank_ns,
    \pre_4_1_1T_arb.granted_pre_ns ,
    auto_pre_r_lcl_reg,
    act_wait_r_lcl_reg_1,
    \ras_timer_r_reg[1]_0 ,
    bm_end_r1_reg_0,
    demand_priority_r_reg_1,
    \grant_r_reg[3] ,
    demand_priority_r_reg_2,
    start_wtp_timer0,
    \rd_this_rank_r_reg[0]_0 ,
    p_13_out,
    col_wait_r_reg_1,
    req_bank_rdy_ns,
    ofs_rdy_r_reg_0,
    ofs_rdy_r0,
    Q,
    \rtp_timer_r_reg[1]_0 ,
    pre_wait_r_reg_0,
    act_wait_r_lcl_reg_2,
    demand_priority_r_reg_3,
    demand_priority_r_reg_4,
    act_wait_r_lcl_reg_3,
    act_wait_r_lcl_reg_4,
    pre_bm_end_r_reg,
    pre_bm_end_r_reg_0,
    pass_open_bank_ns,
    \pre_4_1_1T_arb.granted_pre_r_reg ,
    \pre_4_1_1T_arb.granted_pre_r_reg_0 ,
    \ras_timer_r_reg[0]_0 ,
    \cmd_pipe_plus.mc_address[10]_i_2 ,
    row_cmd_wr,
    \cmd_pipe_plus.mc_address[10]_i_2_0 ,
    ras_timer_zero_r_reg_0,
    demanded_prior_r_reg_1,
    demand_priority_r,
    demanded_prior_r,
    demand_priority_r_reg_5,
    demand_priority_r_reg_6,
    q_has_rd_12,
    \rtp_timer_r_reg[0]_0 ,
    D);
  output act_wait_r_lcl_reg_0;
  output [0:0]act_this_rank_r;
  output [0:0]wr_this_rank_r;
  output [0:0]rd_this_rank_r;
  output bm_end_r1_1;
  output ras_timer_zero_r;
  output pre_wait_r;
  output col_wait_r_reg_0;
  output demand_priority_r_reg_0;
  output demanded_prior_r_reg_0;
  output ofs_rdy_r;
  output pre_bm_end_ns;
  output pre_passing_open_bank_ns;
  output \pre_4_1_1T_arb.granted_pre_ns ;
  output auto_pre_r_lcl_reg;
  output act_wait_r_lcl_reg_1;
  output \ras_timer_r_reg[1]_0 ;
  output bm_end_r1_reg_0;
  output demand_priority_r_reg_1;
  output \grant_r_reg[3] ;
  input demand_priority_r_reg_2;
  input start_wtp_timer0;
  input \rd_this_rank_r_reg[0]_0 ;
  input p_13_out;
  input col_wait_r_reg_1;
  input req_bank_rdy_ns;
  input ofs_rdy_r_reg_0;
  input ofs_rdy_r0;
  input [1:0]Q;
  input \rtp_timer_r_reg[1]_0 ;
  input pre_wait_r_reg_0;
  input act_wait_r_lcl_reg_2;
  input demand_priority_r_reg_3;
  input demand_priority_r_reg_4;
  input [1:0]act_wait_r_lcl_reg_3;
  input act_wait_r_lcl_reg_4;
  input [0:0]pre_bm_end_r_reg;
  input pre_bm_end_r_reg_0;
  input pass_open_bank_ns;
  input \pre_4_1_1T_arb.granted_pre_r_reg ;
  input \pre_4_1_1T_arb.granted_pre_r_reg_0 ;
  input \ras_timer_r_reg[0]_0 ;
  input [0:0]\cmd_pipe_plus.mc_address[10]_i_2 ;
  input [0:0]row_cmd_wr;
  input [0:0]\cmd_pipe_plus.mc_address[10]_i_2_0 ;
  input ras_timer_zero_r_reg_0;
  input demanded_prior_r_reg_1;
  input demand_priority_r;
  input demanded_prior_r;
  input demand_priority_r_reg_5;
  input demand_priority_r_reg_6;
  input q_has_rd_12;
  input \rtp_timer_r_reg[0]_0 ;
  input [1:0]D;

  wire [1:0]D;
  wire [1:0]Q;
  wire [0:0]act_this_rank_r;
  wire act_wait_ns;
  wire act_wait_r_lcl_i_2_n_0;
  wire act_wait_r_lcl_reg_0;
  wire act_wait_r_lcl_reg_1;
  wire act_wait_r_lcl_reg_2;
  wire [1:0]act_wait_r_lcl_reg_3;
  wire act_wait_r_lcl_reg_4;
  wire auto_pre_r_lcl_reg;
  wire bm_end_r1_1;
  wire bm_end_r1_reg_0;
  wire [0:0]\cmd_pipe_plus.mc_address[10]_i_2 ;
  wire [0:0]\cmd_pipe_plus.mc_address[10]_i_2_0 ;
  wire col_wait_r_reg_0;
  wire col_wait_r_reg_1;
  wire demand_priority_ns;
  wire demand_priority_r;
  wire demand_priority_r_i_3__2_n_0;
  wire demand_priority_r_i_4__2_n_0;
  wire demand_priority_r_reg_0;
  wire demand_priority_r_reg_1;
  wire demand_priority_r_reg_2;
  wire demand_priority_r_reg_3;
  wire demand_priority_r_reg_4;
  wire demand_priority_r_reg_5;
  wire demand_priority_r_reg_6;
  wire demanded_prior_ns;
  wire demanded_prior_r;
  wire demanded_prior_r_reg_0;
  wire demanded_prior_r_reg_1;
  wire \grant_r_reg[3] ;
  wire ofs_rdy_r;
  wire ofs_rdy_r0;
  wire ofs_rdy_r_reg_0;
  wire p_13_out;
  wire pass_open_bank_ns;
  wire \pre_4_1_1T_arb.granted_pre_ns ;
  wire \pre_4_1_1T_arb.granted_pre_r_reg ;
  wire \pre_4_1_1T_arb.granted_pre_r_reg_0 ;
  wire pre_bm_end_ns;
  wire [0:0]pre_bm_end_r_reg;
  wire pre_bm_end_r_reg_0;
  wire pre_passing_open_bank_ns;
  wire pre_wait_ns;
  wire pre_wait_r;
  wire pre_wait_r_i_2__2_n_0;
  wire pre_wait_r_reg_0;
  wire q_has_rd_12;
  wire \ras_timer_r_reg[0]_0 ;
  wire \ras_timer_r_reg[1]_0 ;
  wire \ras_timer_r_reg_n_0_[0] ;
  wire \ras_timer_r_reg_n_0_[1] ;
  wire ras_timer_zero_r;
  wire ras_timer_zero_r_i_1__2_n_0;
  wire ras_timer_zero_r_i_2_n_0;
  wire ras_timer_zero_r_reg_0;
  wire [0:0]rd_this_rank_r;
  wire \rd_this_rank_r_reg[0]_0 ;
  wire req_bank_rdy_ns;
  wire req_bank_rdy_r;
  wire [0:0]row_cmd_wr;
  wire [1:0]rtp_timer_r;
  wire \rtp_timer_r[0]_i_1__2_n_0 ;
  wire \rtp_timer_r[1]_i_1__2_n_0 ;
  wire \rtp_timer_r_reg[0]_0 ;
  wire \rtp_timer_r_reg[1]_0 ;
  wire start_wtp_timer0;
  wire [2:0]starve_limit_cntr_r;
  wire starve_limit_cntr_r0;
  wire \starve_limit_cntr_r[0]_i_1_n_0 ;
  wire \starve_limit_cntr_r[1]_i_1_n_0 ;
  wire \starve_limit_cntr_r[2]_i_1_n_0 ;
  wire [0:0]wr_this_rank_r;

  FDRE \act_this_rank_r_reg[0] 
       (.C(demand_priority_r_reg_2),
        .CE(1'b1),
        .D(act_wait_r_lcl_reg_0),
        .Q(act_this_rank_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF88F8)) 
    act_wait_r_lcl_i_1
       (.I0(act_wait_r_lcl_reg_0),
        .I1(act_wait_r_lcl_i_2_n_0),
        .I2(\rtp_timer_r_reg[1]_0 ),
        .I3(act_wait_r_lcl_reg_2),
        .I4(pre_wait_r_reg_0),
        .I5(bm_end_r1_1),
        .O(act_wait_ns));
  (* SOFT_HLUTNM = "soft_lutpair1190" *) 
  LUT3 #(
    .INIT(8'h07)) 
    act_wait_r_lcl_i_2
       (.I0(act_wait_r_lcl_reg_3[1]),
        .I1(act_wait_r_lcl_reg_0),
        .I2(act_wait_r_lcl_reg_4),
        .O(act_wait_r_lcl_i_2_n_0));
  FDRE act_wait_r_lcl_reg
       (.C(demand_priority_r_reg_2),
        .CE(1'b1),
        .D(act_wait_ns),
        .Q(act_wait_r_lcl_reg_0),
        .R(1'b0));
  FDRE bm_end_r1_reg
       (.C(demand_priority_r_reg_2),
        .CE(1'b1),
        .D(p_13_out),
        .Q(bm_end_r1_1),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h8888F00088880000)) 
    \cmd_pipe_plus.mc_address[10]_i_3 
       (.I0(act_wait_r_lcl_reg_0),
        .I1(\cmd_pipe_plus.mc_address[10]_i_2 ),
        .I2(row_cmd_wr),
        .I3(act_wait_r_lcl_reg_3[0]),
        .I4(act_wait_r_lcl_reg_3[1]),
        .I5(\cmd_pipe_plus.mc_address[10]_i_2_0 ),
        .O(act_wait_r_lcl_reg_1));
  FDRE col_wait_r_reg
       (.C(demand_priority_r_reg_2),
        .CE(1'b1),
        .D(col_wait_r_reg_1),
        .Q(col_wait_r_reg_0),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h88888808)) 
    demand_priority_r_i_1
       (.I0(col_wait_r_reg_1),
        .I1(demand_priority_r_reg_3),
        .I2(demand_priority_r_reg_4),
        .I3(demand_priority_r_i_3__2_n_0),
        .I4(demand_priority_r_reg_0),
        .O(demand_priority_ns));
  LUT6 #(
    .INIT(64'h0000000040400040)) 
    demand_priority_r_i_3__2
       (.I0(Q[1]),
        .I1(demand_priority_r_reg_5),
        .I2(req_bank_rdy_r),
        .I3(demand_priority_r_reg_6),
        .I4(q_has_rd_12),
        .I5(demand_priority_r_i_4__2_n_0),
        .O(demand_priority_r_i_3__2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair1189" *) 
  LUT3 #(
    .INIT(8'h7F)) 
    demand_priority_r_i_4__2
       (.I0(starve_limit_cntr_r[2]),
        .I1(starve_limit_cntr_r[1]),
        .I2(starve_limit_cntr_r[0]),
        .O(demand_priority_r_i_4__2_n_0));
  FDRE demand_priority_r_reg
       (.C(demand_priority_r_reg_2),
        .CE(1'b1),
        .D(demand_priority_ns),
        .Q(demand_priority_r_reg_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hD0D0D0D0D0DDD0D0)) 
    demanded_prior_r_i_1
       (.I0(demand_priority_r_reg_0),
        .I1(demanded_prior_r_reg_0),
        .I2(demanded_prior_r_reg_1),
        .I3(Q[0]),
        .I4(demand_priority_r),
        .I5(demanded_prior_r),
        .O(demanded_prior_ns));
  FDRE demanded_prior_r_reg
       (.C(demand_priority_r_reg_2),
        .CE(1'b1),
        .D(demanded_prior_ns),
        .Q(demanded_prior_r_reg_0),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair1187" *) 
  LUT3 #(
    .INIT(8'hFB)) 
    \grant_r[2]_i_6 
       (.I0(Q[1]),
        .I1(demand_priority_r_reg_0),
        .I2(demanded_prior_r_reg_0),
        .O(\grant_r_reg[3] ));
  (* SOFT_HLUTNM = "soft_lutpair1186" *) 
  LUT4 #(
    .INIT(16'h1000)) 
    \grant_r[3]_i_5__0 
       (.I0(pre_bm_end_r_reg_0),
        .I1(pre_bm_end_r_reg),
        .I2(pre_wait_r),
        .I3(ras_timer_zero_r),
        .O(auto_pre_r_lcl_reg));
  (* SOFT_HLUTNM = "soft_lutpair1187" *) 
  LUT5 #(
    .INIT(32'hBBBBBABB)) 
    i___40_i_5
       (.I0(demand_priority_r),
        .I1(demanded_prior_r_reg_1),
        .I2(Q[1]),
        .I3(demand_priority_r_reg_0),
        .I4(demanded_prior_r_reg_0),
        .O(demand_priority_r_reg_1));
  FDRE #(
    .INIT(1'b0)) 
    ofs_rdy_r_reg
       (.C(demand_priority_r_reg_2),
        .CE(1'b1),
        .D(ofs_rdy_r0),
        .Q(ofs_rdy_r),
        .R(ofs_rdy_r_reg_0));
  LUT6 #(
    .INIT(64'hABAAAAAAFFFFFFFF)) 
    \pre_4_1_1T_arb.granted_pre_r_i_1 
       (.I0(\pre_4_1_1T_arb.granted_pre_r_reg ),
        .I1(pre_bm_end_r_reg_0),
        .I2(pre_bm_end_r_reg),
        .I3(pre_wait_r),
        .I4(ras_timer_zero_r),
        .I5(\pre_4_1_1T_arb.granted_pre_r_reg_0 ),
        .O(\pre_4_1_1T_arb.granted_pre_ns ));
  (* SOFT_HLUTNM = "soft_lutpair1186" *) 
  LUT5 #(
    .INIT(32'hEAEAEAAA)) 
    pre_bm_end_r_i_1__2
       (.I0(pre_passing_open_bank_ns),
        .I1(ras_timer_zero_r),
        .I2(pre_wait_r),
        .I3(pre_bm_end_r_reg),
        .I4(pre_bm_end_r_reg_0),
        .O(pre_bm_end_ns));
  LUT6 #(
    .INIT(64'hAAA8AAAAAAA8AAA8)) 
    pre_passing_open_bank_r_i_1__2
       (.I0(pass_open_bank_ns),
        .I1(Q[1]),
        .I2(rtp_timer_r[0]),
        .I3(rtp_timer_r[1]),
        .I4(ras_timer_zero_r),
        .I5(pre_wait_r),
        .O(pre_passing_open_bank_ns));
  LUT6 #(
    .INIT(64'h4444444444454444)) 
    pre_wait_r_i_1__2
       (.I0(pass_open_bank_ns),
        .I1(pre_wait_r_i_2__2_n_0),
        .I2(\rtp_timer_r_reg[1]_0 ),
        .I3(pre_wait_r_reg_0),
        .I4(rtp_timer_r[0]),
        .I5(rtp_timer_r[1]),
        .O(pre_wait_ns));
  LUT5 #(
    .INIT(32'h10101050)) 
    pre_wait_r_i_2__2
       (.I0(\ras_timer_r_reg[0]_0 ),
        .I1(ras_timer_zero_r),
        .I2(pre_wait_r),
        .I3(pre_bm_end_r_reg),
        .I4(pre_bm_end_r_reg_0),
        .O(pre_wait_r_i_2__2_n_0));
  FDRE pre_wait_r_reg
       (.C(demand_priority_r_reg_2),
        .CE(1'b1),
        .D(pre_wait_ns),
        .Q(pre_wait_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0010111100100010)) 
    \ras_timer_r[0]_i_3__2 
       (.I0(bm_end_r1_1),
        .I1(\ras_timer_r_reg[0]_0 ),
        .I2(\ras_timer_r_reg_n_0_[1] ),
        .I3(\ras_timer_r_reg_n_0_[0] ),
        .I4(\rd_this_rank_r_reg[0]_0 ),
        .I5(Q[1]),
        .O(bm_end_r1_reg_0));
  LUT6 #(
    .INIT(64'h4041555540414041)) 
    \ras_timer_r[1]_i_3__2 
       (.I0(ras_timer_zero_r_reg_0),
        .I1(\ras_timer_r_reg_n_0_[1] ),
        .I2(\ras_timer_r_reg_n_0_[0] ),
        .I3(ras_timer_zero_r_i_2_n_0),
        .I4(\rd_this_rank_r_reg[0]_0 ),
        .I5(Q[1]),
        .O(\ras_timer_r_reg[1]_0 ));
  FDRE \ras_timer_r_reg[0] 
       (.C(demand_priority_r_reg_2),
        .CE(1'b1),
        .D(D[0]),
        .Q(\ras_timer_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \ras_timer_r_reg[1] 
       (.C(demand_priority_r_reg_2),
        .CE(1'b1),
        .D(D[1]),
        .Q(\ras_timer_r_reg_n_0_[1] ),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF0000DDD0)) 
    ras_timer_zero_r_i_1__2
       (.I0(Q[1]),
        .I1(\rd_this_rank_r_reg[0]_0 ),
        .I2(ras_timer_zero_r_i_2_n_0),
        .I3(\ras_timer_r_reg_n_0_[0] ),
        .I4(\ras_timer_r_reg_n_0_[1] ),
        .I5(ras_timer_zero_r_reg_0),
        .O(ras_timer_zero_r_i_1__2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair1190" *) 
  LUT2 #(
    .INIT(4'h7)) 
    ras_timer_zero_r_i_2
       (.I0(act_wait_r_lcl_reg_0),
        .I1(act_wait_r_lcl_reg_3[1]),
        .O(ras_timer_zero_r_i_2_n_0));
  FDRE ras_timer_zero_r_reg
       (.C(demand_priority_r_reg_2),
        .CE(1'b1),
        .D(ras_timer_zero_r_i_1__2_n_0),
        .Q(ras_timer_zero_r),
        .R(1'b0));
  FDRE \rd_this_rank_r_reg[0] 
       (.C(demand_priority_r_reg_2),
        .CE(1'b1),
        .D(\rd_this_rank_r_reg[0]_0 ),
        .Q(rd_this_rank_r),
        .R(1'b0));
  FDRE req_bank_rdy_r_reg
       (.C(demand_priority_r_reg_2),
        .CE(1'b1),
        .D(req_bank_rdy_ns),
        .Q(req_bank_rdy_r),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0010)) 
    \rtp_timer_r[0]_i_1__2 
       (.I0(\rtp_timer_r_reg[0]_0 ),
        .I1(\rtp_timer_r_reg[1]_0 ),
        .I2(rtp_timer_r[1]),
        .I3(rtp_timer_r[0]),
        .O(\rtp_timer_r[0]_i_1__2_n_0 ));
  LUT5 #(
    .INIT(32'h000000C2)) 
    \rtp_timer_r[1]_i_1__2 
       (.I0(Q[1]),
        .I1(rtp_timer_r[0]),
        .I2(rtp_timer_r[1]),
        .I3(\rtp_timer_r_reg[1]_0 ),
        .I4(pre_wait_r_reg_0),
        .O(\rtp_timer_r[1]_i_1__2_n_0 ));
  FDRE \rtp_timer_r_reg[0] 
       (.C(demand_priority_r_reg_2),
        .CE(1'b1),
        .D(\rtp_timer_r[0]_i_1__2_n_0 ),
        .Q(rtp_timer_r[0]),
        .R(1'b0));
  FDRE \rtp_timer_r_reg[1] 
       (.C(demand_priority_r_reg_2),
        .CE(1'b1),
        .D(\rtp_timer_r[1]_i_1__2_n_0 ),
        .Q(rtp_timer_r[1]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair1189" *) 
  LUT3 #(
    .INIT(8'h60)) 
    \starve_limit_cntr_r[0]_i_1 
       (.I0(starve_limit_cntr_r[0]),
        .I1(starve_limit_cntr_r0),
        .I2(col_wait_r_reg_0),
        .O(\starve_limit_cntr_r[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1188" *) 
  LUT4 #(
    .INIT(16'h6A00)) 
    \starve_limit_cntr_r[1]_i_1 
       (.I0(starve_limit_cntr_r[1]),
        .I1(starve_limit_cntr_r0),
        .I2(starve_limit_cntr_r[0]),
        .I3(col_wait_r_reg_0),
        .O(\starve_limit_cntr_r[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1188" *) 
  LUT5 #(
    .INIT(32'h6AAA0000)) 
    \starve_limit_cntr_r[2]_i_1 
       (.I0(starve_limit_cntr_r[2]),
        .I1(starve_limit_cntr_r0),
        .I2(starve_limit_cntr_r[0]),
        .I3(starve_limit_cntr_r[1]),
        .I4(col_wait_r_reg_0),
        .O(\starve_limit_cntr_r[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h007F000000000000)) 
    \starve_limit_cntr_r[2]_i_2__2 
       (.I0(starve_limit_cntr_r[0]),
        .I1(starve_limit_cntr_r[1]),
        .I2(starve_limit_cntr_r[2]),
        .I3(Q[1]),
        .I4(demand_priority_r_reg_5),
        .I5(req_bank_rdy_r),
        .O(starve_limit_cntr_r0));
  FDRE \starve_limit_cntr_r_reg[0] 
       (.C(demand_priority_r_reg_2),
        .CE(1'b1),
        .D(\starve_limit_cntr_r[0]_i_1_n_0 ),
        .Q(starve_limit_cntr_r[0]),
        .R(1'b0));
  FDRE \starve_limit_cntr_r_reg[1] 
       (.C(demand_priority_r_reg_2),
        .CE(1'b1),
        .D(\starve_limit_cntr_r[1]_i_1_n_0 ),
        .Q(starve_limit_cntr_r[1]),
        .R(1'b0));
  FDRE \starve_limit_cntr_r_reg[2] 
       (.C(demand_priority_r_reg_2),
        .CE(1'b1),
        .D(\starve_limit_cntr_r[2]_i_1_n_0 ),
        .Q(starve_limit_cntr_r[2]),
        .R(1'b0));
  FDRE \wr_this_rank_r_reg[0] 
       (.C(demand_priority_r_reg_2),
        .CE(1'b1),
        .D(start_wtp_timer0),
        .Q(wr_this_rank_r),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_clk_ibuf" *) 
module mig_mig_7series_v4_2_clk_ibuf
   (out,
    sys_clk_p,
    sys_clk_n);
  output out;
  input sys_clk_p;
  input sys_clk_n;

  (* RTL_KEEP = "true" *) (* syn_keep = "true" *) wire sys_clk_ibufg;
  wire sys_clk_n;
  wire sys_clk_p;

  assign out = sys_clk_ibufg;
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  (* IBUF_DELAY_VALUE = "0" *) 
  (* XILINX_LEGACY_PRIM = "IBUFGDS" *) 
  IBUFDS #(
    .IOSTANDARD("DEFAULT")) 
    \diff_input_clk.u_ibufg_sys_clk 
       (.I(sys_clk_p),
        .IB(sys_clk_n),
        .O(sys_clk_ibufg));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_col_mach" *) 
module mig_mig_7series_v4_2_col_mach
   (col_rd_wr_r1,
    col_rd_wr_r2,
    sent_col_r2,
    D,
    \read_fifo.tail_r_reg[4]_0 ,
    \read_fifo.tail_r_reg[2]_0 ,
    mc_ref_zq_wip_ns,
    \read_fifo.tail_r_reg[0]_0 ,
    \read_fifo.tail_r_reg[4]_1 ,
    \read_fifo.fifo_out_data_r_reg[7]_0 ,
    \read_fifo.head_r_reg[4]_0 ,
    DIC,
    ADDRA,
    col_rd_wr,
    mc_cmd,
    col_wr_data_buf_addr,
    maint_ref_zq_wip,
    \read_fifo.tail_r_reg[2]_1 ,
    \read_fifo.fifo_out_data_r_reg[7]_1 ,
    \read_fifo.tail_r_reg[1]_0 ,
    \read_fifo.tail_r_reg[0]_1 ,
    \read_fifo.head_r_reg[0]_0 ,
    E);
  output col_rd_wr_r1;
  output col_rd_wr_r2;
  output sent_col_r2;
  output [3:0]D;
  output \read_fifo.tail_r_reg[4]_0 ;
  output [1:0]\read_fifo.tail_r_reg[2]_0 ;
  output mc_ref_zq_wip_ns;
  output \read_fifo.tail_r_reg[0]_0 ;
  output \read_fifo.tail_r_reg[4]_1 ;
  output [1:0]\read_fifo.fifo_out_data_r_reg[7]_0 ;
  input \read_fifo.head_r_reg[4]_0 ;
  input [0:0]DIC;
  input [2:0]ADDRA;
  input col_rd_wr;
  input [0:0]mc_cmd;
  input [3:0]col_wr_data_buf_addr;
  input maint_ref_zq_wip;
  input \read_fifo.tail_r_reg[2]_1 ;
  input \read_fifo.fifo_out_data_r_reg[7]_1 ;
  input \read_fifo.tail_r_reg[1]_0 ;
  input \read_fifo.tail_r_reg[0]_1 ;
  input \read_fifo.head_r_reg[0]_0 ;
  input [0:0]E;

  wire [2:0]ADDRA;
  wire [3:0]D;
  wire [0:0]DIC;
  wire [0:0]E;
  wire col_rd_wr;
  wire col_rd_wr_r1;
  wire col_rd_wr_r2;
  wire [3:0]col_wr_data_buf_addr;
  wire maint_ref_zq_wip;
  wire [0:0]mc_cmd;
  wire mc_ref_zq_wip_ns;
  wire mc_ref_zq_wip_r_i_2_n_0;
  wire [4:0]p_0_in;
  wire [7:6]\read_fifo.fifo_out_data_ns ;
  wire [1:0]\read_fifo.fifo_out_data_r_reg[7]_0 ;
  wire \read_fifo.fifo_out_data_r_reg[7]_1 ;
  wire [4:0]\read_fifo.head_r ;
  wire \read_fifo.head_r_reg[0]_0 ;
  wire \read_fifo.head_r_reg[4]_0 ;
  wire [3:0]\read_fifo.tail_ns ;
  wire [4:3]\read_fifo.tail_r ;
  wire \read_fifo.tail_r[1]_i_1_n_0 ;
  wire \read_fifo.tail_r[2]_i_1_n_0 ;
  wire \read_fifo.tail_r[3]_i_1_n_0 ;
  wire \read_fifo.tail_r[4]_i_1_n_0 ;
  wire \read_fifo.tail_r_reg[0]_0 ;
  wire \read_fifo.tail_r_reg[0]_1 ;
  wire \read_fifo.tail_r_reg[1]_0 ;
  wire [1:0]\read_fifo.tail_r_reg[2]_0 ;
  wire \read_fifo.tail_r_reg[2]_1 ;
  wire \read_fifo.tail_r_reg[4]_0 ;
  wire \read_fifo.tail_r_reg[4]_1 ;
  wire sent_col_r2;
  wire [1:0]\NLW_read_fifo.fifo_ram[1].RAM32M0_DOA_UNCONNECTED ;
  wire [1:0]\NLW_read_fifo.fifo_ram[1].RAM32M0_DOB_UNCONNECTED ;
  wire [1:0]\NLW_read_fifo.fifo_ram[1].RAM32M0_DOD_UNCONNECTED ;

  FDRE \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[0] 
       (.C(\read_fifo.head_r_reg[4]_0 ),
        .CE(1'b1),
        .D(col_wr_data_buf_addr[0]),
        .Q(D[0]),
        .R(1'b0));
  FDRE \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[1] 
       (.C(\read_fifo.head_r_reg[4]_0 ),
        .CE(1'b1),
        .D(col_wr_data_buf_addr[1]),
        .Q(D[1]),
        .R(1'b0));
  FDRE \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[2] 
       (.C(\read_fifo.head_r_reg[4]_0 ),
        .CE(1'b1),
        .D(col_wr_data_buf_addr[2]),
        .Q(D[2]),
        .R(1'b0));
  FDRE \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] 
       (.C(\read_fifo.head_r_reg[4]_0 ),
        .CE(1'b1),
        .D(col_wr_data_buf_addr[3]),
        .Q(D[3]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h9555555555555555)) 
    i___92_i_1
       (.I0(\read_fifo.tail_r [4]),
        .I1(\read_fifo.tail_r_reg[2]_0 [0]),
        .I2(\read_fifo.tail_r_reg[2]_1 ),
        .I3(\read_fifo.tail_r_reg[0]_0 ),
        .I4(\read_fifo.tail_r_reg[2]_0 [1]),
        .I5(\read_fifo.tail_r [3]),
        .O(\read_fifo.tail_r_reg[4]_1 ));
  LUT5 #(
    .INIT(32'h09000009)) 
    mc_read_idle_r_i_2
       (.I0(\read_fifo.tail_r [4]),
        .I1(\read_fifo.head_r [4]),
        .I2(mc_ref_zq_wip_r_i_2_n_0),
        .I3(\read_fifo.head_r [3]),
        .I4(\read_fifo.tail_r [3]),
        .O(\read_fifo.tail_r_reg[4]_0 ));
  LUT6 #(
    .INIT(64'h0082000000000082)) 
    mc_ref_zq_wip_r_i_1
       (.I0(maint_ref_zq_wip),
        .I1(\read_fifo.tail_r [4]),
        .I2(\read_fifo.head_r [4]),
        .I3(mc_ref_zq_wip_r_i_2_n_0),
        .I4(\read_fifo.head_r [3]),
        .I5(\read_fifo.tail_r [3]),
        .O(mc_ref_zq_wip_ns));
  LUT6 #(
    .INIT(64'h6FF6FFFFFFFF6FF6)) 
    mc_ref_zq_wip_r_i_2
       (.I0(\read_fifo.head_r [1]),
        .I1(\read_fifo.tail_r_reg[2]_0 [0]),
        .I2(\read_fifo.head_r [2]),
        .I3(\read_fifo.tail_r_reg[2]_0 [1]),
        .I4(\read_fifo.tail_r_reg[0]_0 ),
        .I5(\read_fifo.head_r [0]),
        .O(mc_ref_zq_wip_r_i_2_n_0));
  FDRE \offset_pipe_0.col_rd_wr_r1_reg 
       (.C(\read_fifo.head_r_reg[4]_0 ),
        .CE(1'b1),
        .D(col_rd_wr),
        .Q(col_rd_wr_r1),
        .R(1'b0));
  FDRE \offset_pipe_1.col_rd_wr_r2_reg 
       (.C(\read_fifo.head_r_reg[4]_0 ),
        .CE(1'b1),
        .D(col_rd_wr_r1),
        .Q(col_rd_wr_r2),
        .R(1'b0));
  FDRE \read_fifo.fifo_out_data_r_reg[6] 
       (.C(\read_fifo.head_r_reg[4]_0 ),
        .CE(1'b1),
        .D(\read_fifo.fifo_out_data_ns [6]),
        .Q(\read_fifo.fifo_out_data_r_reg[7]_0 [0]),
        .R(1'b0));
  FDRE \read_fifo.fifo_out_data_r_reg[7] 
       (.C(\read_fifo.head_r_reg[4]_0 ),
        .CE(1'b1),
        .D(\read_fifo.fifo_out_data_ns [7]),
        .Q(\read_fifo.fifo_out_data_r_reg[7]_0 [1]),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \read_fifo.fifo_ram[1].RAM32M0 
       (.ADDRA({ADDRA[2],\read_fifo.tail_ns [3],ADDRA[1:0],\read_fifo.tail_ns [0]}),
        .ADDRB({ADDRA[2],\read_fifo.tail_ns [3],ADDRA[1:0],\read_fifo.tail_ns [0]}),
        .ADDRC({ADDRA[2],\read_fifo.tail_ns [3],ADDRA[1:0],\read_fifo.tail_ns [0]}),
        .ADDRD(\read_fifo.head_r ),
        .DIA({1'b0,1'b0}),
        .DIB({1'b0,1'b0}),
        .DIC({1'b1,DIC}),
        .DID({1'b0,1'b0}),
        .DOA(\NLW_read_fifo.fifo_ram[1].RAM32M0_DOA_UNCONNECTED [1:0]),
        .DOB(\NLW_read_fifo.fifo_ram[1].RAM32M0_DOB_UNCONNECTED [1:0]),
        .DOC(\read_fifo.fifo_out_data_ns ),
        .DOD(\NLW_read_fifo.fifo_ram[1].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\read_fifo.head_r_reg[4]_0 ),
        .WE(1'b1));
  LUT6 #(
    .INIT(64'h000000007FFF8000)) 
    \read_fifo.fifo_ram[1].RAM32M0_i_1 
       (.I0(\read_fifo.tail_r_reg[2]_0 [0]),
        .I1(\read_fifo.tail_r_reg[2]_1 ),
        .I2(\read_fifo.tail_r_reg[0]_0 ),
        .I3(\read_fifo.tail_r_reg[2]_0 [1]),
        .I4(\read_fifo.tail_r [3]),
        .I5(\read_fifo.fifo_out_data_r_reg[7]_1 ),
        .O(\read_fifo.tail_ns [3]));
  LUT3 #(
    .INIT(8'h06)) 
    \read_fifo.fifo_ram[1].RAM32M0_i_2 
       (.I0(\read_fifo.tail_r_reg[0]_0 ),
        .I1(\read_fifo.tail_r_reg[2]_1 ),
        .I2(\read_fifo.fifo_out_data_r_reg[7]_1 ),
        .O(\read_fifo.tail_ns [0]));
  LUT1 #(
    .INIT(2'h1)) 
    \read_fifo.head_r[0]_i_1 
       (.I0(\read_fifo.head_r [0]),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair1197" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \read_fifo.head_r[1]_i_1 
       (.I0(\read_fifo.head_r [0]),
        .I1(\read_fifo.head_r [1]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair1197" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \read_fifo.head_r[2]_i_1 
       (.I0(\read_fifo.head_r [2]),
        .I1(\read_fifo.head_r [1]),
        .I2(\read_fifo.head_r [0]),
        .O(p_0_in[2]));
  (* SOFT_HLUTNM = "soft_lutpair1196" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \read_fifo.head_r[3]_i_1 
       (.I0(\read_fifo.head_r [3]),
        .I1(\read_fifo.head_r [0]),
        .I2(\read_fifo.head_r [1]),
        .I3(\read_fifo.head_r [2]),
        .O(p_0_in[3]));
  (* SOFT_HLUTNM = "soft_lutpair1196" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \read_fifo.head_r[4]_i_1 
       (.I0(\read_fifo.head_r [4]),
        .I1(\read_fifo.head_r [2]),
        .I2(\read_fifo.head_r [1]),
        .I3(\read_fifo.head_r [0]),
        .I4(\read_fifo.head_r [3]),
        .O(p_0_in[4]));
  FDRE \read_fifo.head_r_reg[0] 
       (.C(\read_fifo.head_r_reg[4]_0 ),
        .CE(E),
        .D(p_0_in[0]),
        .Q(\read_fifo.head_r [0]),
        .R(\read_fifo.head_r_reg[0]_0 ));
  FDRE \read_fifo.head_r_reg[1] 
       (.C(\read_fifo.head_r_reg[4]_0 ),
        .CE(E),
        .D(p_0_in[1]),
        .Q(\read_fifo.head_r [1]),
        .R(\read_fifo.head_r_reg[0]_0 ));
  FDRE \read_fifo.head_r_reg[2] 
       (.C(\read_fifo.head_r_reg[4]_0 ),
        .CE(E),
        .D(p_0_in[2]),
        .Q(\read_fifo.head_r [2]),
        .R(\read_fifo.head_r_reg[0]_0 ));
  FDRE \read_fifo.head_r_reg[3] 
       (.C(\read_fifo.head_r_reg[4]_0 ),
        .CE(E),
        .D(p_0_in[3]),
        .Q(\read_fifo.head_r [3]),
        .R(\read_fifo.head_r_reg[0]_0 ));
  FDRE \read_fifo.head_r_reg[4] 
       (.C(\read_fifo.head_r_reg[4]_0 ),
        .CE(E),
        .D(p_0_in[4]),
        .Q(\read_fifo.head_r [4]),
        .R(\read_fifo.head_r_reg[0]_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \read_fifo.tail_r[1]_i_1 
       (.I0(\read_fifo.tail_r_reg[2]_1 ),
        .I1(\read_fifo.tail_r_reg[0]_0 ),
        .I2(\read_fifo.tail_r_reg[2]_0 [0]),
        .O(\read_fifo.tail_r[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1195" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \read_fifo.tail_r[2]_i_1 
       (.I0(\read_fifo.tail_r_reg[0]_0 ),
        .I1(\read_fifo.tail_r_reg[2]_1 ),
        .I2(\read_fifo.tail_r_reg[2]_0 [0]),
        .I3(\read_fifo.tail_r_reg[2]_0 [1]),
        .O(\read_fifo.tail_r[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1195" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \read_fifo.tail_r[3]_i_1 
       (.I0(\read_fifo.tail_r [3]),
        .I1(\read_fifo.tail_r_reg[2]_0 [1]),
        .I2(\read_fifo.tail_r_reg[0]_0 ),
        .I3(\read_fifo.tail_r_reg[2]_1 ),
        .I4(\read_fifo.tail_r_reg[2]_0 [0]),
        .O(\read_fifo.tail_r[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \read_fifo.tail_r[4]_i_1 
       (.I0(\read_fifo.tail_r [3]),
        .I1(\read_fifo.tail_r_reg[2]_0 [1]),
        .I2(\read_fifo.tail_r_reg[0]_0 ),
        .I3(\read_fifo.tail_r_reg[2]_1 ),
        .I4(\read_fifo.tail_r_reg[2]_0 [0]),
        .I5(\read_fifo.tail_r [4]),
        .O(\read_fifo.tail_r[4]_i_1_n_0 ));
  FDRE \read_fifo.tail_r_reg[0] 
       (.C(\read_fifo.head_r_reg[4]_0 ),
        .CE(1'b1),
        .D(\read_fifo.tail_r_reg[0]_1 ),
        .Q(\read_fifo.tail_r_reg[0]_0 ),
        .R(\read_fifo.tail_r_reg[1]_0 ));
  FDRE \read_fifo.tail_r_reg[1] 
       (.C(\read_fifo.head_r_reg[4]_0 ),
        .CE(1'b1),
        .D(\read_fifo.tail_r[1]_i_1_n_0 ),
        .Q(\read_fifo.tail_r_reg[2]_0 [0]),
        .R(\read_fifo.tail_r_reg[1]_0 ));
  FDRE \read_fifo.tail_r_reg[2] 
       (.C(\read_fifo.head_r_reg[4]_0 ),
        .CE(1'b1),
        .D(\read_fifo.tail_r[2]_i_1_n_0 ),
        .Q(\read_fifo.tail_r_reg[2]_0 [1]),
        .R(\read_fifo.tail_r_reg[1]_0 ));
  FDRE \read_fifo.tail_r_reg[3] 
       (.C(\read_fifo.head_r_reg[4]_0 ),
        .CE(1'b1),
        .D(\read_fifo.tail_r[3]_i_1_n_0 ),
        .Q(\read_fifo.tail_r [3]),
        .R(\read_fifo.tail_r_reg[1]_0 ));
  FDRE \read_fifo.tail_r_reg[4] 
       (.C(\read_fifo.head_r_reg[4]_0 ),
        .CE(1'b1),
        .D(\read_fifo.tail_r[4]_i_1_n_0 ),
        .Q(\read_fifo.tail_r [4]),
        .R(\read_fifo.tail_r_reg[1]_0 ));
  FDRE sent_col_r2_reg
       (.C(\read_fifo.head_r_reg[4]_0 ),
        .CE(1'b1),
        .D(mc_cmd),
        .Q(sent_col_r2),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_byte_group_io" *) 
module mig_mig_7series_v4_2_ddr_byte_group_io
   (out_dqs_0,
    ts_dqs_0,
    D1,
    D2,
    D3,
    D4,
    D5,
    D6,
    D7,
    D9,
    mem_dq_out,
    mem_dq_ts,
    idelay_ld_rst_3,
    oserdes_clk,
    oserdes_clkdiv,
    po_oserdes_rst,
    DTSBUS,
    oserdes_clk_delayed,
    DQSBUS,
    CTSBUS,
    idelay_ld_rst_reg_0,
    \input_[9].iserdes_dq_.iserdesdq_0 ,
    mem_dq_in,
    idelay_inc,
    LD0_10,
    A_rst_primitives,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,
    CLKB0_10,
    iserdes_clkdiv,
    of_dqbus,
    rst_r4);
  output out_dqs_0;
  output ts_dqs_0;
  output [3:0]D1;
  output [3:0]D2;
  output [3:0]D3;
  output [3:0]D4;
  output [3:0]D5;
  output [3:0]D6;
  output [3:0]D7;
  output [3:0]D9;
  output [8:0]mem_dq_out;
  output [8:0]mem_dq_ts;
  output idelay_ld_rst_3;
  input oserdes_clk;
  input oserdes_clkdiv;
  input po_oserdes_rst;
  input [1:0]DTSBUS;
  input oserdes_clk_delayed;
  input [1:0]DQSBUS;
  input [0:0]CTSBUS;
  input idelay_ld_rst_reg_0;
  input \input_[9].iserdes_dq_.iserdesdq_0 ;
  input [7:0]mem_dq_in;
  input idelay_inc;
  input LD0_10;
  input A_rst_primitives;
  input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  input CLKB0_10;
  input iserdes_clkdiv;
  input [35:0]of_dqbus;
  input rst_r4;

  wire A_rst_primitives;
  wire CLKB0_10;
  wire [0:0]CTSBUS;
  wire [3:0]D1;
  wire [3:0]D2;
  wire [3:0]D3;
  wire [3:0]D4;
  wire [3:0]D5;
  wire [3:0]D6;
  wire [3:0]D7;
  wire [3:0]D9;
  wire [1:0]DQSBUS;
  wire [1:0]DTSBUS;
  wire LD0_10;
  wire data_in_dly_1;
  wire data_in_dly_2;
  wire data_in_dly_3;
  wire data_in_dly_4;
  wire data_in_dly_5;
  wire data_in_dly_6;
  wire data_in_dly_7;
  wire data_in_dly_9;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  wire idelay_inc;
  wire idelay_ld_rst_3;
  wire idelay_ld_rst_i_1__3_n_0;
  wire idelay_ld_rst_reg_0;
  wire \input_[9].iserdes_dq_.iserdesdq_0 ;
  wire iserdes_clkdiv;
  wire [7:0]mem_dq_in;
  wire [8:0]mem_dq_out;
  wire [8:0]mem_dq_ts;
  wire [35:0]of_dqbus;
  wire oserdes_clk;
  wire oserdes_clk_delayed;
  wire oserdes_clkdiv;
  wire out_dqs_0;
  wire po_oserdes_rst;
  wire rst_r4;
  wire tbyte_out;
  wire ts_dqs_0;
  wire \NLW_dqs_gen.oddr_dqs_S_UNCONNECTED ;
  wire \NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED ;
  wire [4:0]\NLW_input_[1].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[3].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[5].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[9].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED ;

  (* BOX_TYPE = "PRIMITIVE" *) 
  (* __SRVAL = "FALSE" *) 
  ODDR #(
    .DDR_CLK_EDGE("SAME_EDGE"),
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .SRTYPE("SYNC")) 
    \dqs_gen.oddr_dqs 
       (.C(oserdes_clk_delayed),
        .CE(1'b1),
        .D1(DQSBUS[0]),
        .D2(DQSBUS[1]),
        .Q(out_dqs_0),
        .R(1'b0),
        .S(\NLW_dqs_gen.oddr_dqs_S_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* __SRVAL = "TRUE" *) 
  ODDR #(
    .DDR_CLK_EDGE("SAME_EDGE"),
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .SRTYPE("SYNC")) 
    \dqs_gen.oddr_dqsts 
       (.C(oserdes_clk_delayed),
        .CE(1'b1),
        .D1(CTSBUS),
        .D2(CTSBUS),
        .Q(ts_dqs_0),
        .R(\NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED ),
        .S(1'b0));
  LUT2 #(
    .INIT(4'h2)) 
    idelay_ld_rst_i_1__3
       (.I0(idelay_ld_rst_3),
        .I1(rst_r4),
        .O(idelay_ld_rst_i_1__3_n_0));
  FDSE idelay_ld_rst_reg
       (.C(idelay_ld_rst_reg_0),
        .CE(1'b1),
        .D(idelay_ld_rst_i_1__3_n_0),
        .Q(idelay_ld_rst_3),
        .S(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[1].iserdes_dq_.idelay_dq.idelaye2 
       (.C(idelay_ld_rst_reg_0),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[1].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_1),
        .IDATAIN(mem_dq_in[0]),
        .INC(idelay_inc),
        .LD(LD0_10),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[1].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0_10),
        .CLKDIV(\NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[0]),
        .DDLY(data_in_dly_1),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D1[3]),
        .Q2(D1[2]),
        .Q3(D1[1]),
        .Q4(D1[0]),
        .Q5(\NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[2].iserdes_dq_.idelay_dq.idelaye2 
       (.C(idelay_ld_rst_reg_0),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_2),
        .IDATAIN(mem_dq_in[1]),
        .INC(idelay_inc),
        .LD(LD0_10),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[2].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0_10),
        .CLKDIV(\NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[1]),
        .DDLY(data_in_dly_2),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D2[3]),
        .Q2(D2[2]),
        .Q3(D2[1]),
        .Q4(D2[0]),
        .Q5(\NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[3].iserdes_dq_.idelay_dq.idelaye2 
       (.C(idelay_ld_rst_reg_0),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[3].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_3),
        .IDATAIN(mem_dq_in[2]),
        .INC(idelay_inc),
        .LD(LD0_10),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[3].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0_10),
        .CLKDIV(\NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[2]),
        .DDLY(data_in_dly_3),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D3[3]),
        .Q2(D3[2]),
        .Q3(D3[1]),
        .Q4(D3[0]),
        .Q5(\NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[4].iserdes_dq_.idelay_dq.idelaye2 
       (.C(idelay_ld_rst_reg_0),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_4),
        .IDATAIN(mem_dq_in[3]),
        .INC(idelay_inc),
        .LD(LD0_10),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[4].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0_10),
        .CLKDIV(\NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[3]),
        .DDLY(data_in_dly_4),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D4[3]),
        .Q2(D4[2]),
        .Q3(D4[1]),
        .Q4(D4[0]),
        .Q5(\NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[5].iserdes_dq_.idelay_dq.idelaye2 
       (.C(idelay_ld_rst_reg_0),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[5].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_5),
        .IDATAIN(mem_dq_in[4]),
        .INC(idelay_inc),
        .LD(LD0_10),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[5].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0_10),
        .CLKDIV(\NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[4]),
        .DDLY(data_in_dly_5),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D5[3]),
        .Q2(D5[2]),
        .Q3(D5[1]),
        .Q4(D5[0]),
        .Q5(\NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[6].iserdes_dq_.idelay_dq.idelaye2 
       (.C(idelay_ld_rst_reg_0),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_6),
        .IDATAIN(mem_dq_in[5]),
        .INC(idelay_inc),
        .LD(LD0_10),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[6].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0_10),
        .CLKDIV(\NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[5]),
        .DDLY(data_in_dly_6),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D6[3]),
        .Q2(D6[2]),
        .Q3(D6[1]),
        .Q4(D6[0]),
        .Q5(\NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[7].iserdes_dq_.idelay_dq.idelaye2 
       (.C(idelay_ld_rst_reg_0),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_7),
        .IDATAIN(mem_dq_in[6]),
        .INC(idelay_inc),
        .LD(LD0_10),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[7].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0_10),
        .CLKDIV(\NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[6]),
        .DDLY(data_in_dly_7),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D7[3]),
        .Q2(D7[2]),
        .Q3(D7[1]),
        .Q4(D7[0]),
        .Q5(\NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[9].iserdes_dq_.idelay_dq.idelaye2 
       (.C(idelay_ld_rst_reg_0),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[9].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_9),
        .IDATAIN(mem_dq_in[7]),
        .INC(idelay_inc),
        .LD(LD0_10),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[9].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0_10),
        .CLKDIV(\NLW_input_[9].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[7]),
        .DDLY(data_in_dly_9),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[9].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[9].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[9].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D9[3]),
        .Q2(D9[2]),
        .Q3(D9[1]),
        .Q4(D9[0]),
        .Q5(\NLW_input_[9].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[9].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[9].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[9].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[0].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[0]),
        .D2(of_dqbus[1]),
        .D3(of_dqbus[2]),
        .D4(of_dqbus[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[0]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[0]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[1].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[4]),
        .D2(of_dqbus[5]),
        .D3(of_dqbus[6]),
        .D4(of_dqbus[7]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[1]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[1]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[2].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[8]),
        .D2(of_dqbus[9]),
        .D3(of_dqbus[10]),
        .D4(of_dqbus[11]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[2]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[2]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[3].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[12]),
        .D2(of_dqbus[13]),
        .D3(of_dqbus[14]),
        .D4(of_dqbus[15]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[3]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[3]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[4].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[16]),
        .D2(of_dqbus[17]),
        .D3(of_dqbus[18]),
        .D4(of_dqbus[19]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[4]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[4]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[5].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[20]),
        .D2(of_dqbus[21]),
        .D3(of_dqbus[22]),
        .D4(of_dqbus[23]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[5]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[5]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[6].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[24]),
        .D2(of_dqbus[25]),
        .D3(of_dqbus[26]),
        .D4(of_dqbus[27]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[6]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[6]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[7].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[28]),
        .D2(of_dqbus[29]),
        .D3(of_dqbus[30]),
        .D4(of_dqbus[31]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[7]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[7]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[9].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[32]),
        .D2(of_dqbus[33]),
        .D3(of_dqbus[34]),
        .D4(of_dqbus[35]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[8]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[8]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("TRUE"),
    .TRISTATE_WIDTH(4)) 
    \slave_ts.oserdes_slave_ts 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(1'b0),
        .D2(1'b0),
        .D3(1'b0),
        .D4(1'b0),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED ),
        .OQ(\NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED ),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED ),
        .T1(DTSBUS[0]),
        .T2(DTSBUS[0]),
        .T3(DTSBUS[1]),
        .T4(DTSBUS[1]),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(tbyte_out),
        .TCE(1'b1),
        .TFB(\NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED ),
        .TQ(\NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED ));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_byte_group_io" *) 
module mig_mig_7series_v4_2_ddr_byte_group_io_38
   (out_dqs_4,
    ts_dqs_4,
    D1,
    D2,
    D3,
    D4,
    D5,
    D6,
    D7,
    D9,
    mem_dq_out,
    mem_dq_ts,
    idelay_ld_rst,
    oserdes_clk,
    oserdes_clkdiv,
    po_oserdes_rst,
    DTSBUS,
    oserdes_clk_delayed,
    DQSBUS,
    CTSBUS,
    idelay_ld_rst_reg_0,
    \input_[9].iserdes_dq_.iserdesdq_0 ,
    mem_dq_in,
    idelay_inc,
    LD0,
    A_rst_primitives,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,
    CLKB0,
    iserdes_clkdiv,
    of_dqbus,
    rst_r4);
  output out_dqs_4;
  output ts_dqs_4;
  output [3:0]D1;
  output [3:0]D2;
  output [3:0]D3;
  output [3:0]D4;
  output [3:0]D5;
  output [3:0]D6;
  output [3:0]D7;
  output [3:0]D9;
  output [8:0]mem_dq_out;
  output [8:0]mem_dq_ts;
  output idelay_ld_rst;
  input oserdes_clk;
  input oserdes_clkdiv;
  input po_oserdes_rst;
  input [1:0]DTSBUS;
  input oserdes_clk_delayed;
  input [1:0]DQSBUS;
  input [0:0]CTSBUS;
  input idelay_ld_rst_reg_0;
  input \input_[9].iserdes_dq_.iserdesdq_0 ;
  input [7:0]mem_dq_in;
  input idelay_inc;
  input LD0;
  input A_rst_primitives;
  input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  input CLKB0;
  input iserdes_clkdiv;
  input [35:0]of_dqbus;
  input rst_r4;

  wire A_rst_primitives;
  wire CLKB0;
  wire [0:0]CTSBUS;
  wire [3:0]D1;
  wire [3:0]D2;
  wire [3:0]D3;
  wire [3:0]D4;
  wire [3:0]D5;
  wire [3:0]D6;
  wire [3:0]D7;
  wire [3:0]D9;
  wire [1:0]DQSBUS;
  wire [1:0]DTSBUS;
  wire LD0;
  wire data_in_dly_1;
  wire data_in_dly_2;
  wire data_in_dly_3;
  wire data_in_dly_4;
  wire data_in_dly_5;
  wire data_in_dly_6;
  wire data_in_dly_7;
  wire data_in_dly_9;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  wire idelay_inc;
  wire idelay_ld_rst;
  wire idelay_ld_rst_i_1_n_0;
  wire idelay_ld_rst_reg_0;
  wire \input_[9].iserdes_dq_.iserdesdq_0 ;
  wire iserdes_clkdiv;
  wire [7:0]mem_dq_in;
  wire [8:0]mem_dq_out;
  wire [8:0]mem_dq_ts;
  wire [35:0]of_dqbus;
  wire oserdes_clk;
  wire oserdes_clk_delayed;
  wire oserdes_clkdiv;
  wire out_dqs_4;
  wire po_oserdes_rst;
  wire rst_r4;
  wire tbyte_out;
  wire ts_dqs_4;
  wire \NLW_dqs_gen.oddr_dqs_S_UNCONNECTED ;
  wire \NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED ;
  wire [4:0]\NLW_input_[1].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[3].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[5].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[9].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED ;

  (* BOX_TYPE = "PRIMITIVE" *) 
  (* __SRVAL = "FALSE" *) 
  ODDR #(
    .DDR_CLK_EDGE("SAME_EDGE"),
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .SRTYPE("SYNC")) 
    \dqs_gen.oddr_dqs 
       (.C(oserdes_clk_delayed),
        .CE(1'b1),
        .D1(DQSBUS[0]),
        .D2(DQSBUS[1]),
        .Q(out_dqs_4),
        .R(1'b0),
        .S(\NLW_dqs_gen.oddr_dqs_S_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* __SRVAL = "TRUE" *) 
  ODDR #(
    .DDR_CLK_EDGE("SAME_EDGE"),
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .SRTYPE("SYNC")) 
    \dqs_gen.oddr_dqsts 
       (.C(oserdes_clk_delayed),
        .CE(1'b1),
        .D1(CTSBUS),
        .D2(CTSBUS),
        .Q(ts_dqs_4),
        .R(\NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED ),
        .S(1'b0));
  LUT2 #(
    .INIT(4'h2)) 
    idelay_ld_rst_i_1
       (.I0(idelay_ld_rst),
        .I1(rst_r4),
        .O(idelay_ld_rst_i_1_n_0));
  FDSE idelay_ld_rst_reg
       (.C(idelay_ld_rst_reg_0),
        .CE(1'b1),
        .D(idelay_ld_rst_i_1_n_0),
        .Q(idelay_ld_rst),
        .S(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[1].iserdes_dq_.idelay_dq.idelaye2 
       (.C(idelay_ld_rst_reg_0),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[1].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_1),
        .IDATAIN(mem_dq_in[0]),
        .INC(idelay_inc),
        .LD(LD0),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[1].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0),
        .CLKDIV(\NLW_input_[1].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[0]),
        .DDLY(data_in_dly_1),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[1].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[1].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[1].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D1[3]),
        .Q2(D1[2]),
        .Q3(D1[1]),
        .Q4(D1[0]),
        .Q5(\NLW_input_[1].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[1].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[1].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[1].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[1].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[2].iserdes_dq_.idelay_dq.idelaye2 
       (.C(idelay_ld_rst_reg_0),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_2),
        .IDATAIN(mem_dq_in[1]),
        .INC(idelay_inc),
        .LD(LD0),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[2].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0),
        .CLKDIV(\NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[1]),
        .DDLY(data_in_dly_2),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D2[3]),
        .Q2(D2[2]),
        .Q3(D2[1]),
        .Q4(D2[0]),
        .Q5(\NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[3].iserdes_dq_.idelay_dq.idelaye2 
       (.C(idelay_ld_rst_reg_0),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[3].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_3),
        .IDATAIN(mem_dq_in[2]),
        .INC(idelay_inc),
        .LD(LD0),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[3].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0),
        .CLKDIV(\NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[2]),
        .DDLY(data_in_dly_3),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D3[3]),
        .Q2(D3[2]),
        .Q3(D3[1]),
        .Q4(D3[0]),
        .Q5(\NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[4].iserdes_dq_.idelay_dq.idelaye2 
       (.C(idelay_ld_rst_reg_0),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_4),
        .IDATAIN(mem_dq_in[3]),
        .INC(idelay_inc),
        .LD(LD0),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[4].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0),
        .CLKDIV(\NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[3]),
        .DDLY(data_in_dly_4),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D4[3]),
        .Q2(D4[2]),
        .Q3(D4[1]),
        .Q4(D4[0]),
        .Q5(\NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[5].iserdes_dq_.idelay_dq.idelaye2 
       (.C(idelay_ld_rst_reg_0),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[5].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_5),
        .IDATAIN(mem_dq_in[4]),
        .INC(idelay_inc),
        .LD(LD0),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[5].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0),
        .CLKDIV(\NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[4]),
        .DDLY(data_in_dly_5),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D5[3]),
        .Q2(D5[2]),
        .Q3(D5[1]),
        .Q4(D5[0]),
        .Q5(\NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[6].iserdes_dq_.idelay_dq.idelaye2 
       (.C(idelay_ld_rst_reg_0),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_6),
        .IDATAIN(mem_dq_in[5]),
        .INC(idelay_inc),
        .LD(LD0),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[6].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0),
        .CLKDIV(\NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[5]),
        .DDLY(data_in_dly_6),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D6[3]),
        .Q2(D6[2]),
        .Q3(D6[1]),
        .Q4(D6[0]),
        .Q5(\NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[7].iserdes_dq_.idelay_dq.idelaye2 
       (.C(idelay_ld_rst_reg_0),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_7),
        .IDATAIN(mem_dq_in[6]),
        .INC(idelay_inc),
        .LD(LD0),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[7].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0),
        .CLKDIV(\NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[6]),
        .DDLY(data_in_dly_7),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D7[3]),
        .Q2(D7[2]),
        .Q3(D7[1]),
        .Q4(D7[0]),
        .Q5(\NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[9].iserdes_dq_.idelay_dq.idelaye2 
       (.C(idelay_ld_rst_reg_0),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[9].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_9),
        .IDATAIN(mem_dq_in[7]),
        .INC(idelay_inc),
        .LD(LD0),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[9].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0),
        .CLKDIV(\NLW_input_[9].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[7]),
        .DDLY(data_in_dly_9),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[9].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[9].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[9].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D9[3]),
        .Q2(D9[2]),
        .Q3(D9[1]),
        .Q4(D9[0]),
        .Q5(\NLW_input_[9].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[9].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[9].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[9].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[0].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[0]),
        .D2(of_dqbus[1]),
        .D3(of_dqbus[2]),
        .D4(of_dqbus[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[0]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[0].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[0]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[1].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[4]),
        .D2(of_dqbus[5]),
        .D3(of_dqbus[6]),
        .D4(of_dqbus[7]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[1]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[1]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[2].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[8]),
        .D2(of_dqbus[9]),
        .D3(of_dqbus[10]),
        .D4(of_dqbus[11]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[2]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[2]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[3].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[12]),
        .D2(of_dqbus[13]),
        .D3(of_dqbus[14]),
        .D4(of_dqbus[15]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[3]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[3]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[4].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[16]),
        .D2(of_dqbus[17]),
        .D3(of_dqbus[18]),
        .D4(of_dqbus[19]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[4]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[4]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[5].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[20]),
        .D2(of_dqbus[21]),
        .D3(of_dqbus[22]),
        .D4(of_dqbus[23]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[5]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[5]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[6].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[24]),
        .D2(of_dqbus[25]),
        .D3(of_dqbus[26]),
        .D4(of_dqbus[27]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[6]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[6]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[7].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[28]),
        .D2(of_dqbus[29]),
        .D3(of_dqbus[30]),
        .D4(of_dqbus[31]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[7]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[7]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[9].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[32]),
        .D2(of_dqbus[33]),
        .D3(of_dqbus[34]),
        .D4(of_dqbus[35]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[8]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[8]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("TRUE"),
    .TRISTATE_WIDTH(4)) 
    \slave_ts.oserdes_slave_ts 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(1'b0),
        .D2(1'b0),
        .D3(1'b0),
        .D4(1'b0),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED ),
        .OQ(\NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED ),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED ),
        .T1(DTSBUS[0]),
        .T2(DTSBUS[0]),
        .T3(DTSBUS[1]),
        .T4(DTSBUS[1]),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(tbyte_out),
        .TCE(1'b1),
        .TFB(\NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED ),
        .TQ(\NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED ));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_byte_group_io" *) 
module mig_mig_7series_v4_2_ddr_byte_group_io__parameterized0
   (out_dqs_3,
    ts_dqs_3,
    D2,
    D3,
    D4,
    D5,
    D6,
    D7,
    D8,
    D9,
    mem_dq_out,
    mem_dq_ts,
    idelay_ld_rst_6,
    rst_r4,
    oserdes_clk,
    oserdes_clkdiv,
    po_oserdes_rst,
    DTSBUS,
    oserdes_clk_delayed,
    DQSBUS,
    CTSBUS,
    idelay_ld_rst_reg_0,
    \input_[9].iserdes_dq_.iserdesdq_0 ,
    mem_dq_in,
    idelay_inc,
    LD0_13,
    A_rst_primitives,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,
    CLKB0_13,
    iserdes_clkdiv,
    of_dqbus);
  output out_dqs_3;
  output ts_dqs_3;
  output [3:0]D2;
  output [3:0]D3;
  output [3:0]D4;
  output [3:0]D5;
  output [3:0]D6;
  output [3:0]D7;
  output [3:0]D8;
  output [3:0]D9;
  output [8:0]mem_dq_out;
  output [8:0]mem_dq_ts;
  output idelay_ld_rst_6;
  output rst_r4;
  input oserdes_clk;
  input oserdes_clkdiv;
  input po_oserdes_rst;
  input [1:0]DTSBUS;
  input oserdes_clk_delayed;
  input [1:0]DQSBUS;
  input [0:0]CTSBUS;
  input idelay_ld_rst_reg_0;
  input \input_[9].iserdes_dq_.iserdesdq_0 ;
  input [7:0]mem_dq_in;
  input idelay_inc;
  input LD0_13;
  input A_rst_primitives;
  input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  input CLKB0_13;
  input iserdes_clkdiv;
  input [35:0]of_dqbus;

  wire A_rst_primitives;
  wire CLKB0_13;
  wire [0:0]CTSBUS;
  wire [3:0]D2;
  wire [3:0]D3;
  wire [3:0]D4;
  wire [3:0]D5;
  wire [3:0]D6;
  wire [3:0]D7;
  wire [3:0]D8;
  wire [3:0]D9;
  wire [1:0]DQSBUS;
  wire [1:0]DTSBUS;
  wire LD0_13;
  wire data_in_dly_2;
  wire data_in_dly_3;
  wire data_in_dly_4;
  wire data_in_dly_5;
  wire data_in_dly_6;
  wire data_in_dly_7;
  wire data_in_dly_8;
  wire data_in_dly_9;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  wire idelay_inc;
  wire idelay_ld_rst_6;
  wire idelay_ld_rst_i_1__6_n_0;
  wire idelay_ld_rst_reg_0;
  wire \input_[9].iserdes_dq_.iserdesdq_0 ;
  wire iserdes_clkdiv;
  wire [7:0]mem_dq_in;
  wire [8:0]mem_dq_out;
  wire [8:0]mem_dq_ts;
  wire [35:0]of_dqbus;
  wire oserdes_clk;
  wire oserdes_clk_delayed;
  wire oserdes_clkdiv;
  wire out_dqs_3;
  wire po_oserdes_rst;
  wire rst_r3_reg_srl3_n_0;
  wire rst_r4;
  wire tbyte_out;
  wire ts_dqs_3;
  wire \NLW_dqs_gen.oddr_dqs_S_UNCONNECTED ;
  wire \NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED ;
  wire [4:0]\NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[3].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[5].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[8].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[9].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED ;

  (* BOX_TYPE = "PRIMITIVE" *) 
  (* __SRVAL = "FALSE" *) 
  ODDR #(
    .DDR_CLK_EDGE("SAME_EDGE"),
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .SRTYPE("SYNC")) 
    \dqs_gen.oddr_dqs 
       (.C(oserdes_clk_delayed),
        .CE(1'b1),
        .D1(DQSBUS[0]),
        .D2(DQSBUS[1]),
        .Q(out_dqs_3),
        .R(1'b0),
        .S(\NLW_dqs_gen.oddr_dqs_S_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* __SRVAL = "TRUE" *) 
  ODDR #(
    .DDR_CLK_EDGE("SAME_EDGE"),
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .SRTYPE("SYNC")) 
    \dqs_gen.oddr_dqsts 
       (.C(oserdes_clk_delayed),
        .CE(1'b1),
        .D1(CTSBUS),
        .D2(CTSBUS),
        .Q(ts_dqs_3),
        .R(\NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED ),
        .S(1'b0));
  LUT2 #(
    .INIT(4'h2)) 
    idelay_ld_rst_i_1__6
       (.I0(idelay_ld_rst_6),
        .I1(rst_r4),
        .O(idelay_ld_rst_i_1__6_n_0));
  FDSE idelay_ld_rst_reg
       (.C(idelay_ld_rst_reg_0),
        .CE(1'b1),
        .D(idelay_ld_rst_i_1__6_n_0),
        .Q(idelay_ld_rst_6),
        .S(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[2].iserdes_dq_.idelay_dq.idelaye2 
       (.C(idelay_ld_rst_reg_0),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_2),
        .IDATAIN(mem_dq_in[0]),
        .INC(idelay_inc),
        .LD(LD0_13),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[2].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0_13),
        .CLKDIV(\NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[0]),
        .DDLY(data_in_dly_2),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D2[3]),
        .Q2(D2[2]),
        .Q3(D2[1]),
        .Q4(D2[0]),
        .Q5(\NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[3].iserdes_dq_.idelay_dq.idelaye2 
       (.C(idelay_ld_rst_reg_0),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[3].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_3),
        .IDATAIN(mem_dq_in[1]),
        .INC(idelay_inc),
        .LD(LD0_13),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[3].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0_13),
        .CLKDIV(\NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[1]),
        .DDLY(data_in_dly_3),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D3[3]),
        .Q2(D3[2]),
        .Q3(D3[1]),
        .Q4(D3[0]),
        .Q5(\NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[4].iserdes_dq_.idelay_dq.idelaye2 
       (.C(idelay_ld_rst_reg_0),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_4),
        .IDATAIN(mem_dq_in[2]),
        .INC(idelay_inc),
        .LD(LD0_13),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[4].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0_13),
        .CLKDIV(\NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[2]),
        .DDLY(data_in_dly_4),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D4[3]),
        .Q2(D4[2]),
        .Q3(D4[1]),
        .Q4(D4[0]),
        .Q5(\NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[5].iserdes_dq_.idelay_dq.idelaye2 
       (.C(idelay_ld_rst_reg_0),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[5].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_5),
        .IDATAIN(mem_dq_in[3]),
        .INC(idelay_inc),
        .LD(LD0_13),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[5].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0_13),
        .CLKDIV(\NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[3]),
        .DDLY(data_in_dly_5),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D5[3]),
        .Q2(D5[2]),
        .Q3(D5[1]),
        .Q4(D5[0]),
        .Q5(\NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[6].iserdes_dq_.idelay_dq.idelaye2 
       (.C(idelay_ld_rst_reg_0),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_6),
        .IDATAIN(mem_dq_in[4]),
        .INC(idelay_inc),
        .LD(LD0_13),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[6].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0_13),
        .CLKDIV(\NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[4]),
        .DDLY(data_in_dly_6),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D6[3]),
        .Q2(D6[2]),
        .Q3(D6[1]),
        .Q4(D6[0]),
        .Q5(\NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[7].iserdes_dq_.idelay_dq.idelaye2 
       (.C(idelay_ld_rst_reg_0),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_7),
        .IDATAIN(mem_dq_in[5]),
        .INC(idelay_inc),
        .LD(LD0_13),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[7].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0_13),
        .CLKDIV(\NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[5]),
        .DDLY(data_in_dly_7),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D7[3]),
        .Q2(D7[2]),
        .Q3(D7[1]),
        .Q4(D7[0]),
        .Q5(\NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[8].iserdes_dq_.idelay_dq.idelaye2 
       (.C(idelay_ld_rst_reg_0),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[8].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_8),
        .IDATAIN(mem_dq_in[6]),
        .INC(idelay_inc),
        .LD(LD0_13),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[8].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0_13),
        .CLKDIV(\NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[6]),
        .DDLY(data_in_dly_8),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D8[3]),
        .Q2(D8[2]),
        .Q3(D8[1]),
        .Q4(D8[0]),
        .Q5(\NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[9].iserdes_dq_.idelay_dq.idelaye2 
       (.C(idelay_ld_rst_reg_0),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[9].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_9),
        .IDATAIN(mem_dq_in[7]),
        .INC(idelay_inc),
        .LD(LD0_13),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[9].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0_13),
        .CLKDIV(\NLW_input_[9].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[7]),
        .DDLY(data_in_dly_9),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[9].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[9].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[9].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D9[3]),
        .Q2(D9[2]),
        .Q3(D9[1]),
        .Q4(D9[0]),
        .Q5(\NLW_input_[9].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[9].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[9].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[9].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[1].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[0]),
        .D2(of_dqbus[1]),
        .D3(of_dqbus[2]),
        .D4(of_dqbus[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[0]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[0]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[2].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[4]),
        .D2(of_dqbus[5]),
        .D3(of_dqbus[6]),
        .D4(of_dqbus[7]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[1]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[1]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[3].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[8]),
        .D2(of_dqbus[9]),
        .D3(of_dqbus[10]),
        .D4(of_dqbus[11]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[2]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[2]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[4].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[12]),
        .D2(of_dqbus[13]),
        .D3(of_dqbus[14]),
        .D4(of_dqbus[15]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[3]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[3]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[5].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[16]),
        .D2(of_dqbus[17]),
        .D3(of_dqbus[18]),
        .D4(of_dqbus[19]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[4]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[4]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[6].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[20]),
        .D2(of_dqbus[21]),
        .D3(of_dqbus[22]),
        .D4(of_dqbus[23]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[5]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[5]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[7].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[24]),
        .D2(of_dqbus[25]),
        .D3(of_dqbus[26]),
        .D4(of_dqbus[27]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[6]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[6]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[8].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[28]),
        .D2(of_dqbus[29]),
        .D3(of_dqbus[30]),
        .D4(of_dqbus[31]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[7]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[7]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[9].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[32]),
        .D2(of_dqbus[33]),
        .D3(of_dqbus[34]),
        .D4(of_dqbus[35]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[8]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[8]));
  (* srl_name = "\u_mig_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/rst_r3_reg_srl3 " *) 
  SRL16E rst_r3_reg_srl3
       (.A0(1'b0),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(idelay_ld_rst_reg_0),
        .D(A_rst_primitives),
        .Q(rst_r3_reg_srl3_n_0));
  FDRE rst_r4_reg
       (.C(idelay_ld_rst_reg_0),
        .CE(1'b1),
        .D(rst_r3_reg_srl3_n_0),
        .Q(rst_r4),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("TRUE"),
    .TRISTATE_WIDTH(4)) 
    \slave_ts.oserdes_slave_ts 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(1'b0),
        .D2(1'b0),
        .D3(1'b0),
        .D4(1'b0),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED ),
        .OQ(\NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED ),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED ),
        .T1(DTSBUS[0]),
        .T2(DTSBUS[0]),
        .T3(DTSBUS[1]),
        .T4(DTSBUS[1]),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(tbyte_out),
        .TCE(1'b1),
        .TFB(\NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED ),
        .TQ(\NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED ));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_byte_group_io" *) 
module mig_mig_7series_v4_2_ddr_byte_group_io__parameterized0_14
   (out_dqs_2,
    ts_dqs_2,
    D2,
    D3,
    D4,
    D5,
    D6,
    D7,
    D8,
    D9,
    mem_dq_out,
    mem_dq_ts,
    idelay_ld_rst_5,
    oserdes_clk,
    oserdes_clkdiv,
    po_oserdes_rst,
    DTSBUS,
    oserdes_clk_delayed,
    DQSBUS,
    CTSBUS,
    idelay_ld_rst_reg_0,
    \input_[9].iserdes_dq_.iserdesdq_0 ,
    mem_dq_in,
    idelay_inc,
    LD0_12,
    A_rst_primitives,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,
    CLKB0_12,
    iserdes_clkdiv,
    of_dqbus,
    rst_r4);
  output out_dqs_2;
  output ts_dqs_2;
  output [3:0]D2;
  output [3:0]D3;
  output [3:0]D4;
  output [3:0]D5;
  output [3:0]D6;
  output [3:0]D7;
  output [3:0]D8;
  output [3:0]D9;
  output [8:0]mem_dq_out;
  output [8:0]mem_dq_ts;
  output idelay_ld_rst_5;
  input oserdes_clk;
  input oserdes_clkdiv;
  input po_oserdes_rst;
  input [1:0]DTSBUS;
  input oserdes_clk_delayed;
  input [1:0]DQSBUS;
  input [0:0]CTSBUS;
  input idelay_ld_rst_reg_0;
  input \input_[9].iserdes_dq_.iserdesdq_0 ;
  input [7:0]mem_dq_in;
  input idelay_inc;
  input LD0_12;
  input A_rst_primitives;
  input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  input CLKB0_12;
  input iserdes_clkdiv;
  input [35:0]of_dqbus;
  input rst_r4;

  wire A_rst_primitives;
  wire CLKB0_12;
  wire [0:0]CTSBUS;
  wire [3:0]D2;
  wire [3:0]D3;
  wire [3:0]D4;
  wire [3:0]D5;
  wire [3:0]D6;
  wire [3:0]D7;
  wire [3:0]D8;
  wire [3:0]D9;
  wire [1:0]DQSBUS;
  wire [1:0]DTSBUS;
  wire LD0_12;
  wire data_in_dly_2;
  wire data_in_dly_3;
  wire data_in_dly_4;
  wire data_in_dly_5;
  wire data_in_dly_6;
  wire data_in_dly_7;
  wire data_in_dly_8;
  wire data_in_dly_9;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  wire idelay_inc;
  wire idelay_ld_rst_5;
  wire idelay_ld_rst_i_1__5_n_0;
  wire idelay_ld_rst_reg_0;
  wire \input_[9].iserdes_dq_.iserdesdq_0 ;
  wire iserdes_clkdiv;
  wire [7:0]mem_dq_in;
  wire [8:0]mem_dq_out;
  wire [8:0]mem_dq_ts;
  wire [35:0]of_dqbus;
  wire oserdes_clk;
  wire oserdes_clk_delayed;
  wire oserdes_clkdiv;
  wire out_dqs_2;
  wire po_oserdes_rst;
  wire rst_r4;
  wire tbyte_out;
  wire ts_dqs_2;
  wire \NLW_dqs_gen.oddr_dqs_S_UNCONNECTED ;
  wire \NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED ;
  wire [4:0]\NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[3].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[5].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[8].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[9].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED ;

  (* BOX_TYPE = "PRIMITIVE" *) 
  (* __SRVAL = "FALSE" *) 
  ODDR #(
    .DDR_CLK_EDGE("SAME_EDGE"),
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .SRTYPE("SYNC")) 
    \dqs_gen.oddr_dqs 
       (.C(oserdes_clk_delayed),
        .CE(1'b1),
        .D1(DQSBUS[0]),
        .D2(DQSBUS[1]),
        .Q(out_dqs_2),
        .R(1'b0),
        .S(\NLW_dqs_gen.oddr_dqs_S_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* __SRVAL = "TRUE" *) 
  ODDR #(
    .DDR_CLK_EDGE("SAME_EDGE"),
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .SRTYPE("SYNC")) 
    \dqs_gen.oddr_dqsts 
       (.C(oserdes_clk_delayed),
        .CE(1'b1),
        .D1(CTSBUS),
        .D2(CTSBUS),
        .Q(ts_dqs_2),
        .R(\NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED ),
        .S(1'b0));
  LUT2 #(
    .INIT(4'h2)) 
    idelay_ld_rst_i_1__5
       (.I0(idelay_ld_rst_5),
        .I1(rst_r4),
        .O(idelay_ld_rst_i_1__5_n_0));
  FDSE idelay_ld_rst_reg
       (.C(idelay_ld_rst_reg_0),
        .CE(1'b1),
        .D(idelay_ld_rst_i_1__5_n_0),
        .Q(idelay_ld_rst_5),
        .S(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[2].iserdes_dq_.idelay_dq.idelaye2 
       (.C(idelay_ld_rst_reg_0),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_2),
        .IDATAIN(mem_dq_in[0]),
        .INC(idelay_inc),
        .LD(LD0_12),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[2].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0_12),
        .CLKDIV(\NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[0]),
        .DDLY(data_in_dly_2),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D2[3]),
        .Q2(D2[2]),
        .Q3(D2[1]),
        .Q4(D2[0]),
        .Q5(\NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[3].iserdes_dq_.idelay_dq.idelaye2 
       (.C(idelay_ld_rst_reg_0),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[3].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_3),
        .IDATAIN(mem_dq_in[1]),
        .INC(idelay_inc),
        .LD(LD0_12),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[3].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0_12),
        .CLKDIV(\NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[1]),
        .DDLY(data_in_dly_3),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D3[3]),
        .Q2(D3[2]),
        .Q3(D3[1]),
        .Q4(D3[0]),
        .Q5(\NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[4].iserdes_dq_.idelay_dq.idelaye2 
       (.C(idelay_ld_rst_reg_0),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_4),
        .IDATAIN(mem_dq_in[2]),
        .INC(idelay_inc),
        .LD(LD0_12),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[4].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0_12),
        .CLKDIV(\NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[2]),
        .DDLY(data_in_dly_4),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D4[3]),
        .Q2(D4[2]),
        .Q3(D4[1]),
        .Q4(D4[0]),
        .Q5(\NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[5].iserdes_dq_.idelay_dq.idelaye2 
       (.C(idelay_ld_rst_reg_0),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[5].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_5),
        .IDATAIN(mem_dq_in[3]),
        .INC(idelay_inc),
        .LD(LD0_12),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[5].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0_12),
        .CLKDIV(\NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[3]),
        .DDLY(data_in_dly_5),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D5[3]),
        .Q2(D5[2]),
        .Q3(D5[1]),
        .Q4(D5[0]),
        .Q5(\NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[6].iserdes_dq_.idelay_dq.idelaye2 
       (.C(idelay_ld_rst_reg_0),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_6),
        .IDATAIN(mem_dq_in[4]),
        .INC(idelay_inc),
        .LD(LD0_12),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[6].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0_12),
        .CLKDIV(\NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[4]),
        .DDLY(data_in_dly_6),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D6[3]),
        .Q2(D6[2]),
        .Q3(D6[1]),
        .Q4(D6[0]),
        .Q5(\NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[7].iserdes_dq_.idelay_dq.idelaye2 
       (.C(idelay_ld_rst_reg_0),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_7),
        .IDATAIN(mem_dq_in[5]),
        .INC(idelay_inc),
        .LD(LD0_12),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[7].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0_12),
        .CLKDIV(\NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[5]),
        .DDLY(data_in_dly_7),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D7[3]),
        .Q2(D7[2]),
        .Q3(D7[1]),
        .Q4(D7[0]),
        .Q5(\NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[8].iserdes_dq_.idelay_dq.idelaye2 
       (.C(idelay_ld_rst_reg_0),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[8].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_8),
        .IDATAIN(mem_dq_in[6]),
        .INC(idelay_inc),
        .LD(LD0_12),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[8].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0_12),
        .CLKDIV(\NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[6]),
        .DDLY(data_in_dly_8),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D8[3]),
        .Q2(D8[2]),
        .Q3(D8[1]),
        .Q4(D8[0]),
        .Q5(\NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[9].iserdes_dq_.idelay_dq.idelaye2 
       (.C(idelay_ld_rst_reg_0),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[9].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_9),
        .IDATAIN(mem_dq_in[7]),
        .INC(idelay_inc),
        .LD(LD0_12),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[9].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0_12),
        .CLKDIV(\NLW_input_[9].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[7]),
        .DDLY(data_in_dly_9),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[9].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[9].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[9].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D9[3]),
        .Q2(D9[2]),
        .Q3(D9[1]),
        .Q4(D9[0]),
        .Q5(\NLW_input_[9].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[9].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[9].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[9].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[1].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[0]),
        .D2(of_dqbus[1]),
        .D3(of_dqbus[2]),
        .D4(of_dqbus[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[0]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[0]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[2].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[4]),
        .D2(of_dqbus[5]),
        .D3(of_dqbus[6]),
        .D4(of_dqbus[7]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[1]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[1]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[3].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[8]),
        .D2(of_dqbus[9]),
        .D3(of_dqbus[10]),
        .D4(of_dqbus[11]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[2]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[2]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[4].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[12]),
        .D2(of_dqbus[13]),
        .D3(of_dqbus[14]),
        .D4(of_dqbus[15]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[3]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[3]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[5].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[16]),
        .D2(of_dqbus[17]),
        .D3(of_dqbus[18]),
        .D4(of_dqbus[19]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[4]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[4]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[6].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[20]),
        .D2(of_dqbus[21]),
        .D3(of_dqbus[22]),
        .D4(of_dqbus[23]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[5]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[5]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[7].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[24]),
        .D2(of_dqbus[25]),
        .D3(of_dqbus[26]),
        .D4(of_dqbus[27]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[6]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[6]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[8].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[28]),
        .D2(of_dqbus[29]),
        .D3(of_dqbus[30]),
        .D4(of_dqbus[31]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[7]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[7]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[9].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[32]),
        .D2(of_dqbus[33]),
        .D3(of_dqbus[34]),
        .D4(of_dqbus[35]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[8]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[8]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("TRUE"),
    .TRISTATE_WIDTH(4)) 
    \slave_ts.oserdes_slave_ts 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(1'b0),
        .D2(1'b0),
        .D3(1'b0),
        .D4(1'b0),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED ),
        .OQ(\NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED ),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED ),
        .T1(DTSBUS[0]),
        .T2(DTSBUS[0]),
        .T3(DTSBUS[1]),
        .T4(DTSBUS[1]),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(tbyte_out),
        .TCE(1'b1),
        .TFB(\NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED ),
        .TQ(\NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED ));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_byte_group_io" *) 
module mig_mig_7series_v4_2_ddr_byte_group_io__parameterized0_17
   (out_dqs_1,
    ts_dqs_1,
    D2,
    D3,
    D4,
    D5,
    D6,
    D7,
    D8,
    D9,
    mem_dq_out,
    mem_dq_ts,
    idelay_ld_rst_4,
    oserdes_clk,
    oserdes_clkdiv,
    po_oserdes_rst,
    DTSBUS,
    oserdes_clk_delayed,
    DQSBUS,
    CTSBUS,
    idelay_ld_rst_reg_0,
    \input_[9].iserdes_dq_.iserdesdq_0 ,
    mem_dq_in,
    idelay_inc,
    LD0_11,
    A_rst_primitives,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,
    CLKB0_11,
    iserdes_clkdiv,
    of_dqbus,
    rst_r4);
  output out_dqs_1;
  output ts_dqs_1;
  output [3:0]D2;
  output [3:0]D3;
  output [3:0]D4;
  output [3:0]D5;
  output [3:0]D6;
  output [3:0]D7;
  output [3:0]D8;
  output [3:0]D9;
  output [8:0]mem_dq_out;
  output [8:0]mem_dq_ts;
  output idelay_ld_rst_4;
  input oserdes_clk;
  input oserdes_clkdiv;
  input po_oserdes_rst;
  input [1:0]DTSBUS;
  input oserdes_clk_delayed;
  input [1:0]DQSBUS;
  input [0:0]CTSBUS;
  input idelay_ld_rst_reg_0;
  input \input_[9].iserdes_dq_.iserdesdq_0 ;
  input [7:0]mem_dq_in;
  input idelay_inc;
  input LD0_11;
  input A_rst_primitives;
  input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  input CLKB0_11;
  input iserdes_clkdiv;
  input [35:0]of_dqbus;
  input rst_r4;

  wire A_rst_primitives;
  wire CLKB0_11;
  wire [0:0]CTSBUS;
  wire [3:0]D2;
  wire [3:0]D3;
  wire [3:0]D4;
  wire [3:0]D5;
  wire [3:0]D6;
  wire [3:0]D7;
  wire [3:0]D8;
  wire [3:0]D9;
  wire [1:0]DQSBUS;
  wire [1:0]DTSBUS;
  wire LD0_11;
  wire data_in_dly_2;
  wire data_in_dly_3;
  wire data_in_dly_4;
  wire data_in_dly_5;
  wire data_in_dly_6;
  wire data_in_dly_7;
  wire data_in_dly_8;
  wire data_in_dly_9;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  wire idelay_inc;
  wire idelay_ld_rst_4;
  wire idelay_ld_rst_i_1__4_n_0;
  wire idelay_ld_rst_reg_0;
  wire \input_[9].iserdes_dq_.iserdesdq_0 ;
  wire iserdes_clkdiv;
  wire [7:0]mem_dq_in;
  wire [8:0]mem_dq_out;
  wire [8:0]mem_dq_ts;
  wire [35:0]of_dqbus;
  wire oserdes_clk;
  wire oserdes_clk_delayed;
  wire oserdes_clkdiv;
  wire out_dqs_1;
  wire po_oserdes_rst;
  wire rst_r4;
  wire tbyte_out;
  wire ts_dqs_1;
  wire \NLW_dqs_gen.oddr_dqs_S_UNCONNECTED ;
  wire \NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED ;
  wire [4:0]\NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[3].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[5].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[8].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[9].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED ;

  (* BOX_TYPE = "PRIMITIVE" *) 
  (* __SRVAL = "FALSE" *) 
  ODDR #(
    .DDR_CLK_EDGE("SAME_EDGE"),
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .SRTYPE("SYNC")) 
    \dqs_gen.oddr_dqs 
       (.C(oserdes_clk_delayed),
        .CE(1'b1),
        .D1(DQSBUS[0]),
        .D2(DQSBUS[1]),
        .Q(out_dqs_1),
        .R(1'b0),
        .S(\NLW_dqs_gen.oddr_dqs_S_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* __SRVAL = "TRUE" *) 
  ODDR #(
    .DDR_CLK_EDGE("SAME_EDGE"),
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .SRTYPE("SYNC")) 
    \dqs_gen.oddr_dqsts 
       (.C(oserdes_clk_delayed),
        .CE(1'b1),
        .D1(CTSBUS),
        .D2(CTSBUS),
        .Q(ts_dqs_1),
        .R(\NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED ),
        .S(1'b0));
  LUT2 #(
    .INIT(4'h2)) 
    idelay_ld_rst_i_1__4
       (.I0(idelay_ld_rst_4),
        .I1(rst_r4),
        .O(idelay_ld_rst_i_1__4_n_0));
  FDSE idelay_ld_rst_reg
       (.C(idelay_ld_rst_reg_0),
        .CE(1'b1),
        .D(idelay_ld_rst_i_1__4_n_0),
        .Q(idelay_ld_rst_4),
        .S(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[2].iserdes_dq_.idelay_dq.idelaye2 
       (.C(idelay_ld_rst_reg_0),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_2),
        .IDATAIN(mem_dq_in[0]),
        .INC(idelay_inc),
        .LD(LD0_11),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[2].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0_11),
        .CLKDIV(\NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[0]),
        .DDLY(data_in_dly_2),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D2[3]),
        .Q2(D2[2]),
        .Q3(D2[1]),
        .Q4(D2[0]),
        .Q5(\NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[3].iserdes_dq_.idelay_dq.idelaye2 
       (.C(idelay_ld_rst_reg_0),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[3].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_3),
        .IDATAIN(mem_dq_in[1]),
        .INC(idelay_inc),
        .LD(LD0_11),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[3].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0_11),
        .CLKDIV(\NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[1]),
        .DDLY(data_in_dly_3),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D3[3]),
        .Q2(D3[2]),
        .Q3(D3[1]),
        .Q4(D3[0]),
        .Q5(\NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[4].iserdes_dq_.idelay_dq.idelaye2 
       (.C(idelay_ld_rst_reg_0),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_4),
        .IDATAIN(mem_dq_in[2]),
        .INC(idelay_inc),
        .LD(LD0_11),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[4].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0_11),
        .CLKDIV(\NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[2]),
        .DDLY(data_in_dly_4),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D4[3]),
        .Q2(D4[2]),
        .Q3(D4[1]),
        .Q4(D4[0]),
        .Q5(\NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[5].iserdes_dq_.idelay_dq.idelaye2 
       (.C(idelay_ld_rst_reg_0),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[5].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_5),
        .IDATAIN(mem_dq_in[3]),
        .INC(idelay_inc),
        .LD(LD0_11),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[5].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0_11),
        .CLKDIV(\NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[3]),
        .DDLY(data_in_dly_5),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D5[3]),
        .Q2(D5[2]),
        .Q3(D5[1]),
        .Q4(D5[0]),
        .Q5(\NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[6].iserdes_dq_.idelay_dq.idelaye2 
       (.C(idelay_ld_rst_reg_0),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_6),
        .IDATAIN(mem_dq_in[4]),
        .INC(idelay_inc),
        .LD(LD0_11),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[6].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0_11),
        .CLKDIV(\NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[4]),
        .DDLY(data_in_dly_6),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D6[3]),
        .Q2(D6[2]),
        .Q3(D6[1]),
        .Q4(D6[0]),
        .Q5(\NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[7].iserdes_dq_.idelay_dq.idelaye2 
       (.C(idelay_ld_rst_reg_0),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_7),
        .IDATAIN(mem_dq_in[5]),
        .INC(idelay_inc),
        .LD(LD0_11),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[7].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0_11),
        .CLKDIV(\NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[5]),
        .DDLY(data_in_dly_7),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D7[3]),
        .Q2(D7[2]),
        .Q3(D7[1]),
        .Q4(D7[0]),
        .Q5(\NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[8].iserdes_dq_.idelay_dq.idelaye2 
       (.C(idelay_ld_rst_reg_0),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[8].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_8),
        .IDATAIN(mem_dq_in[6]),
        .INC(idelay_inc),
        .LD(LD0_11),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[8].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0_11),
        .CLKDIV(\NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[6]),
        .DDLY(data_in_dly_8),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D8[3]),
        .Q2(D8[2]),
        .Q3(D8[1]),
        .Q4(D8[0]),
        .Q5(\NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[9].iserdes_dq_.idelay_dq.idelaye2 
       (.C(idelay_ld_rst_reg_0),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[9].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_9),
        .IDATAIN(mem_dq_in[7]),
        .INC(idelay_inc),
        .LD(LD0_11),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[9].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0_11),
        .CLKDIV(\NLW_input_[9].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[7]),
        .DDLY(data_in_dly_9),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[9].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[9].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[9].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D9[3]),
        .Q2(D9[2]),
        .Q3(D9[1]),
        .Q4(D9[0]),
        .Q5(\NLW_input_[9].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[9].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[9].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[9].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[1].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[0]),
        .D2(of_dqbus[1]),
        .D3(of_dqbus[2]),
        .D4(of_dqbus[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[0]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[0]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[2].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[4]),
        .D2(of_dqbus[5]),
        .D3(of_dqbus[6]),
        .D4(of_dqbus[7]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[1]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[1]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[3].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[8]),
        .D2(of_dqbus[9]),
        .D3(of_dqbus[10]),
        .D4(of_dqbus[11]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[2]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[2]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[4].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[12]),
        .D2(of_dqbus[13]),
        .D3(of_dqbus[14]),
        .D4(of_dqbus[15]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[3]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[3]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[5].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[16]),
        .D2(of_dqbus[17]),
        .D3(of_dqbus[18]),
        .D4(of_dqbus[19]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[4]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[4]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[6].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[20]),
        .D2(of_dqbus[21]),
        .D3(of_dqbus[22]),
        .D4(of_dqbus[23]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[5]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[5]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[7].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[24]),
        .D2(of_dqbus[25]),
        .D3(of_dqbus[26]),
        .D4(of_dqbus[27]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[6]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[6]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[8].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[28]),
        .D2(of_dqbus[29]),
        .D3(of_dqbus[30]),
        .D4(of_dqbus[31]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[7]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[7]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[9].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[32]),
        .D2(of_dqbus[33]),
        .D3(of_dqbus[34]),
        .D4(of_dqbus[35]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[8]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[8]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("TRUE"),
    .TRISTATE_WIDTH(4)) 
    \slave_ts.oserdes_slave_ts 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(1'b0),
        .D2(1'b0),
        .D3(1'b0),
        .D4(1'b0),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED ),
        .OQ(\NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED ),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED ),
        .T1(DTSBUS[0]),
        .T2(DTSBUS[0]),
        .T3(DTSBUS[1]),
        .T4(DTSBUS[1]),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(tbyte_out),
        .TCE(1'b1),
        .TFB(\NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED ),
        .TQ(\NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED ));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_byte_group_io" *) 
module mig_mig_7series_v4_2_ddr_byte_group_io__parameterized0_29
   (out_dqs_7,
    ts_dqs_7,
    D2,
    D3,
    D4,
    D5,
    D6,
    D7,
    D8,
    D9,
    mem_dq_out,
    mem_dq_ts,
    idelay_ld_rst_2,
    rst_r4,
    oserdes_clk,
    oserdes_clkdiv,
    po_oserdes_rst,
    DTSBUS,
    oserdes_clk_delayed,
    DQSBUS,
    CTSBUS,
    idelay_ld_rst_reg_0,
    \input_[9].iserdes_dq_.iserdesdq_0 ,
    mem_dq_in,
    idelay_inc,
    LD0_9,
    A_rst_primitives,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,
    CLKB0_9,
    iserdes_clkdiv,
    of_dqbus);
  output out_dqs_7;
  output ts_dqs_7;
  output [3:0]D2;
  output [3:0]D3;
  output [3:0]D4;
  output [3:0]D5;
  output [3:0]D6;
  output [3:0]D7;
  output [3:0]D8;
  output [3:0]D9;
  output [8:0]mem_dq_out;
  output [8:0]mem_dq_ts;
  output idelay_ld_rst_2;
  output rst_r4;
  input oserdes_clk;
  input oserdes_clkdiv;
  input po_oserdes_rst;
  input [1:0]DTSBUS;
  input oserdes_clk_delayed;
  input [1:0]DQSBUS;
  input [0:0]CTSBUS;
  input idelay_ld_rst_reg_0;
  input \input_[9].iserdes_dq_.iserdesdq_0 ;
  input [7:0]mem_dq_in;
  input idelay_inc;
  input LD0_9;
  input A_rst_primitives;
  input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  input CLKB0_9;
  input iserdes_clkdiv;
  input [35:0]of_dqbus;

  wire A_rst_primitives;
  wire CLKB0_9;
  wire [0:0]CTSBUS;
  wire [3:0]D2;
  wire [3:0]D3;
  wire [3:0]D4;
  wire [3:0]D5;
  wire [3:0]D6;
  wire [3:0]D7;
  wire [3:0]D8;
  wire [3:0]D9;
  wire [1:0]DQSBUS;
  wire [1:0]DTSBUS;
  wire LD0_9;
  wire data_in_dly_2;
  wire data_in_dly_3;
  wire data_in_dly_4;
  wire data_in_dly_5;
  wire data_in_dly_6;
  wire data_in_dly_7;
  wire data_in_dly_8;
  wire data_in_dly_9;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  wire idelay_inc;
  wire idelay_ld_rst_2;
  wire idelay_ld_rst_i_1__2_n_0;
  wire idelay_ld_rst_reg_0;
  wire \input_[9].iserdes_dq_.iserdesdq_0 ;
  wire iserdes_clkdiv;
  wire [7:0]mem_dq_in;
  wire [8:0]mem_dq_out;
  wire [8:0]mem_dq_ts;
  wire [35:0]of_dqbus;
  wire oserdes_clk;
  wire oserdes_clk_delayed;
  wire oserdes_clkdiv;
  wire out_dqs_7;
  wire po_oserdes_rst;
  wire rst_r3_reg_srl3_n_0;
  wire rst_r4;
  wire tbyte_out;
  wire ts_dqs_7;
  wire \NLW_dqs_gen.oddr_dqs_S_UNCONNECTED ;
  wire \NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED ;
  wire [4:0]\NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[3].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[5].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[8].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[9].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED ;

  (* BOX_TYPE = "PRIMITIVE" *) 
  (* __SRVAL = "FALSE" *) 
  ODDR #(
    .DDR_CLK_EDGE("SAME_EDGE"),
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .SRTYPE("SYNC")) 
    \dqs_gen.oddr_dqs 
       (.C(oserdes_clk_delayed),
        .CE(1'b1),
        .D1(DQSBUS[0]),
        .D2(DQSBUS[1]),
        .Q(out_dqs_7),
        .R(1'b0),
        .S(\NLW_dqs_gen.oddr_dqs_S_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* __SRVAL = "TRUE" *) 
  ODDR #(
    .DDR_CLK_EDGE("SAME_EDGE"),
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .SRTYPE("SYNC")) 
    \dqs_gen.oddr_dqsts 
       (.C(oserdes_clk_delayed),
        .CE(1'b1),
        .D1(CTSBUS),
        .D2(CTSBUS),
        .Q(ts_dqs_7),
        .R(\NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED ),
        .S(1'b0));
  LUT2 #(
    .INIT(4'h2)) 
    idelay_ld_rst_i_1__2
       (.I0(idelay_ld_rst_2),
        .I1(rst_r4),
        .O(idelay_ld_rst_i_1__2_n_0));
  FDSE idelay_ld_rst_reg
       (.C(idelay_ld_rst_reg_0),
        .CE(1'b1),
        .D(idelay_ld_rst_i_1__2_n_0),
        .Q(idelay_ld_rst_2),
        .S(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[2].iserdes_dq_.idelay_dq.idelaye2 
       (.C(idelay_ld_rst_reg_0),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_2),
        .IDATAIN(mem_dq_in[0]),
        .INC(idelay_inc),
        .LD(LD0_9),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[2].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0_9),
        .CLKDIV(\NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[0]),
        .DDLY(data_in_dly_2),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D2[3]),
        .Q2(D2[2]),
        .Q3(D2[1]),
        .Q4(D2[0]),
        .Q5(\NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[3].iserdes_dq_.idelay_dq.idelaye2 
       (.C(idelay_ld_rst_reg_0),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[3].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_3),
        .IDATAIN(mem_dq_in[1]),
        .INC(idelay_inc),
        .LD(LD0_9),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[3].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0_9),
        .CLKDIV(\NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[1]),
        .DDLY(data_in_dly_3),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D3[3]),
        .Q2(D3[2]),
        .Q3(D3[1]),
        .Q4(D3[0]),
        .Q5(\NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[4].iserdes_dq_.idelay_dq.idelaye2 
       (.C(idelay_ld_rst_reg_0),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_4),
        .IDATAIN(mem_dq_in[2]),
        .INC(idelay_inc),
        .LD(LD0_9),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[4].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0_9),
        .CLKDIV(\NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[2]),
        .DDLY(data_in_dly_4),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D4[3]),
        .Q2(D4[2]),
        .Q3(D4[1]),
        .Q4(D4[0]),
        .Q5(\NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[5].iserdes_dq_.idelay_dq.idelaye2 
       (.C(idelay_ld_rst_reg_0),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[5].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_5),
        .IDATAIN(mem_dq_in[3]),
        .INC(idelay_inc),
        .LD(LD0_9),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[5].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0_9),
        .CLKDIV(\NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[3]),
        .DDLY(data_in_dly_5),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D5[3]),
        .Q2(D5[2]),
        .Q3(D5[1]),
        .Q4(D5[0]),
        .Q5(\NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[6].iserdes_dq_.idelay_dq.idelaye2 
       (.C(idelay_ld_rst_reg_0),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_6),
        .IDATAIN(mem_dq_in[4]),
        .INC(idelay_inc),
        .LD(LD0_9),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[6].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0_9),
        .CLKDIV(\NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[4]),
        .DDLY(data_in_dly_6),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D6[3]),
        .Q2(D6[2]),
        .Q3(D6[1]),
        .Q4(D6[0]),
        .Q5(\NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[7].iserdes_dq_.idelay_dq.idelaye2 
       (.C(idelay_ld_rst_reg_0),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_7),
        .IDATAIN(mem_dq_in[5]),
        .INC(idelay_inc),
        .LD(LD0_9),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[7].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0_9),
        .CLKDIV(\NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[5]),
        .DDLY(data_in_dly_7),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D7[3]),
        .Q2(D7[2]),
        .Q3(D7[1]),
        .Q4(D7[0]),
        .Q5(\NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[8].iserdes_dq_.idelay_dq.idelaye2 
       (.C(idelay_ld_rst_reg_0),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[8].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_8),
        .IDATAIN(mem_dq_in[6]),
        .INC(idelay_inc),
        .LD(LD0_9),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[8].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0_9),
        .CLKDIV(\NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[6]),
        .DDLY(data_in_dly_8),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D8[3]),
        .Q2(D8[2]),
        .Q3(D8[1]),
        .Q4(D8[0]),
        .Q5(\NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[9].iserdes_dq_.idelay_dq.idelaye2 
       (.C(idelay_ld_rst_reg_0),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[9].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_9),
        .IDATAIN(mem_dq_in[7]),
        .INC(idelay_inc),
        .LD(LD0_9),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[9].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0_9),
        .CLKDIV(\NLW_input_[9].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[7]),
        .DDLY(data_in_dly_9),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[9].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[9].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[9].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D9[3]),
        .Q2(D9[2]),
        .Q3(D9[1]),
        .Q4(D9[0]),
        .Q5(\NLW_input_[9].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[9].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[9].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[9].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[1].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[0]),
        .D2(of_dqbus[1]),
        .D3(of_dqbus[2]),
        .D4(of_dqbus[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[0]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[0]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[2].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[4]),
        .D2(of_dqbus[5]),
        .D3(of_dqbus[6]),
        .D4(of_dqbus[7]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[1]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[1]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[3].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[8]),
        .D2(of_dqbus[9]),
        .D3(of_dqbus[10]),
        .D4(of_dqbus[11]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[2]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[2]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[4].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[12]),
        .D2(of_dqbus[13]),
        .D3(of_dqbus[14]),
        .D4(of_dqbus[15]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[3]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[3]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[5].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[16]),
        .D2(of_dqbus[17]),
        .D3(of_dqbus[18]),
        .D4(of_dqbus[19]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[4]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[4]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[6].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[20]),
        .D2(of_dqbus[21]),
        .D3(of_dqbus[22]),
        .D4(of_dqbus[23]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[5]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[5]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[7].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[24]),
        .D2(of_dqbus[25]),
        .D3(of_dqbus[26]),
        .D4(of_dqbus[27]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[6]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[6]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[8].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[28]),
        .D2(of_dqbus[29]),
        .D3(of_dqbus[30]),
        .D4(of_dqbus[31]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[7]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[7]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[9].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[32]),
        .D2(of_dqbus[33]),
        .D3(of_dqbus[34]),
        .D4(of_dqbus[35]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[8]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[8]));
  (* srl_name = "\u_mig_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/rst_r3_reg_srl3 " *) 
  SRL16E rst_r3_reg_srl3
       (.A0(1'b0),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(idelay_ld_rst_reg_0),
        .D(A_rst_primitives),
        .Q(rst_r3_reg_srl3_n_0));
  FDRE rst_r4_reg
       (.C(idelay_ld_rst_reg_0),
        .CE(1'b1),
        .D(rst_r3_reg_srl3_n_0),
        .Q(rst_r4),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("TRUE"),
    .TRISTATE_WIDTH(4)) 
    \slave_ts.oserdes_slave_ts 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(1'b0),
        .D2(1'b0),
        .D3(1'b0),
        .D4(1'b0),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED ),
        .OQ(\NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED ),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED ),
        .T1(DTSBUS[0]),
        .T2(DTSBUS[0]),
        .T3(DTSBUS[1]),
        .T4(DTSBUS[1]),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(tbyte_out),
        .TCE(1'b1),
        .TFB(\NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED ),
        .TQ(\NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED ));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_byte_group_io" *) 
module mig_mig_7series_v4_2_ddr_byte_group_io__parameterized0_32
   (out_dqs_6,
    ts_dqs_6,
    D2,
    D3,
    D4,
    D5,
    D6,
    D7,
    D8,
    D9,
    mem_dq_out,
    mem_dq_ts,
    idelay_ld_rst_1,
    oserdes_clk,
    oserdes_clkdiv,
    po_oserdes_rst,
    DTSBUS,
    oserdes_clk_delayed,
    DQSBUS,
    CTSBUS,
    idelay_ld_rst_reg_0,
    \input_[9].iserdes_dq_.iserdesdq_0 ,
    mem_dq_in,
    idelay_inc,
    LD0_8,
    A_rst_primitives,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,
    CLKB0_8,
    iserdes_clkdiv,
    of_dqbus,
    rst_r4);
  output out_dqs_6;
  output ts_dqs_6;
  output [3:0]D2;
  output [3:0]D3;
  output [3:0]D4;
  output [3:0]D5;
  output [3:0]D6;
  output [3:0]D7;
  output [3:0]D8;
  output [3:0]D9;
  output [8:0]mem_dq_out;
  output [8:0]mem_dq_ts;
  output idelay_ld_rst_1;
  input oserdes_clk;
  input oserdes_clkdiv;
  input po_oserdes_rst;
  input [1:0]DTSBUS;
  input oserdes_clk_delayed;
  input [1:0]DQSBUS;
  input [0:0]CTSBUS;
  input idelay_ld_rst_reg_0;
  input \input_[9].iserdes_dq_.iserdesdq_0 ;
  input [7:0]mem_dq_in;
  input idelay_inc;
  input LD0_8;
  input A_rst_primitives;
  input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  input CLKB0_8;
  input iserdes_clkdiv;
  input [35:0]of_dqbus;
  input rst_r4;

  wire A_rst_primitives;
  wire CLKB0_8;
  wire [0:0]CTSBUS;
  wire [3:0]D2;
  wire [3:0]D3;
  wire [3:0]D4;
  wire [3:0]D5;
  wire [3:0]D6;
  wire [3:0]D7;
  wire [3:0]D8;
  wire [3:0]D9;
  wire [1:0]DQSBUS;
  wire [1:0]DTSBUS;
  wire LD0_8;
  wire data_in_dly_2;
  wire data_in_dly_3;
  wire data_in_dly_4;
  wire data_in_dly_5;
  wire data_in_dly_6;
  wire data_in_dly_7;
  wire data_in_dly_8;
  wire data_in_dly_9;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  wire idelay_inc;
  wire idelay_ld_rst_1;
  wire idelay_ld_rst_i_1__1_n_0;
  wire idelay_ld_rst_reg_0;
  wire \input_[9].iserdes_dq_.iserdesdq_0 ;
  wire iserdes_clkdiv;
  wire [7:0]mem_dq_in;
  wire [8:0]mem_dq_out;
  wire [8:0]mem_dq_ts;
  wire [35:0]of_dqbus;
  wire oserdes_clk;
  wire oserdes_clk_delayed;
  wire oserdes_clkdiv;
  wire out_dqs_6;
  wire po_oserdes_rst;
  wire rst_r4;
  wire tbyte_out;
  wire ts_dqs_6;
  wire \NLW_dqs_gen.oddr_dqs_S_UNCONNECTED ;
  wire \NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED ;
  wire [4:0]\NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[3].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[5].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[8].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[9].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED ;

  (* BOX_TYPE = "PRIMITIVE" *) 
  (* __SRVAL = "FALSE" *) 
  ODDR #(
    .DDR_CLK_EDGE("SAME_EDGE"),
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .SRTYPE("SYNC")) 
    \dqs_gen.oddr_dqs 
       (.C(oserdes_clk_delayed),
        .CE(1'b1),
        .D1(DQSBUS[0]),
        .D2(DQSBUS[1]),
        .Q(out_dqs_6),
        .R(1'b0),
        .S(\NLW_dqs_gen.oddr_dqs_S_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* __SRVAL = "TRUE" *) 
  ODDR #(
    .DDR_CLK_EDGE("SAME_EDGE"),
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .SRTYPE("SYNC")) 
    \dqs_gen.oddr_dqsts 
       (.C(oserdes_clk_delayed),
        .CE(1'b1),
        .D1(CTSBUS),
        .D2(CTSBUS),
        .Q(ts_dqs_6),
        .R(\NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED ),
        .S(1'b0));
  LUT2 #(
    .INIT(4'h2)) 
    idelay_ld_rst_i_1__1
       (.I0(idelay_ld_rst_1),
        .I1(rst_r4),
        .O(idelay_ld_rst_i_1__1_n_0));
  FDSE idelay_ld_rst_reg
       (.C(idelay_ld_rst_reg_0),
        .CE(1'b1),
        .D(idelay_ld_rst_i_1__1_n_0),
        .Q(idelay_ld_rst_1),
        .S(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[2].iserdes_dq_.idelay_dq.idelaye2 
       (.C(idelay_ld_rst_reg_0),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_2),
        .IDATAIN(mem_dq_in[0]),
        .INC(idelay_inc),
        .LD(LD0_8),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[2].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0_8),
        .CLKDIV(\NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[0]),
        .DDLY(data_in_dly_2),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D2[3]),
        .Q2(D2[2]),
        .Q3(D2[1]),
        .Q4(D2[0]),
        .Q5(\NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[3].iserdes_dq_.idelay_dq.idelaye2 
       (.C(idelay_ld_rst_reg_0),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[3].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_3),
        .IDATAIN(mem_dq_in[1]),
        .INC(idelay_inc),
        .LD(LD0_8),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[3].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0_8),
        .CLKDIV(\NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[1]),
        .DDLY(data_in_dly_3),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D3[3]),
        .Q2(D3[2]),
        .Q3(D3[1]),
        .Q4(D3[0]),
        .Q5(\NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[4].iserdes_dq_.idelay_dq.idelaye2 
       (.C(idelay_ld_rst_reg_0),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_4),
        .IDATAIN(mem_dq_in[2]),
        .INC(idelay_inc),
        .LD(LD0_8),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[4].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0_8),
        .CLKDIV(\NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[2]),
        .DDLY(data_in_dly_4),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D4[3]),
        .Q2(D4[2]),
        .Q3(D4[1]),
        .Q4(D4[0]),
        .Q5(\NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[5].iserdes_dq_.idelay_dq.idelaye2 
       (.C(idelay_ld_rst_reg_0),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[5].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_5),
        .IDATAIN(mem_dq_in[3]),
        .INC(idelay_inc),
        .LD(LD0_8),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[5].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0_8),
        .CLKDIV(\NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[3]),
        .DDLY(data_in_dly_5),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D5[3]),
        .Q2(D5[2]),
        .Q3(D5[1]),
        .Q4(D5[0]),
        .Q5(\NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[6].iserdes_dq_.idelay_dq.idelaye2 
       (.C(idelay_ld_rst_reg_0),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_6),
        .IDATAIN(mem_dq_in[4]),
        .INC(idelay_inc),
        .LD(LD0_8),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[6].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0_8),
        .CLKDIV(\NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[4]),
        .DDLY(data_in_dly_6),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D6[3]),
        .Q2(D6[2]),
        .Q3(D6[1]),
        .Q4(D6[0]),
        .Q5(\NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[7].iserdes_dq_.idelay_dq.idelaye2 
       (.C(idelay_ld_rst_reg_0),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_7),
        .IDATAIN(mem_dq_in[5]),
        .INC(idelay_inc),
        .LD(LD0_8),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[7].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0_8),
        .CLKDIV(\NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[5]),
        .DDLY(data_in_dly_7),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D7[3]),
        .Q2(D7[2]),
        .Q3(D7[1]),
        .Q4(D7[0]),
        .Q5(\NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[8].iserdes_dq_.idelay_dq.idelaye2 
       (.C(idelay_ld_rst_reg_0),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[8].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_8),
        .IDATAIN(mem_dq_in[6]),
        .INC(idelay_inc),
        .LD(LD0_8),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[8].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0_8),
        .CLKDIV(\NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[6]),
        .DDLY(data_in_dly_8),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D8[3]),
        .Q2(D8[2]),
        .Q3(D8[1]),
        .Q4(D8[0]),
        .Q5(\NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[9].iserdes_dq_.idelay_dq.idelaye2 
       (.C(idelay_ld_rst_reg_0),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[9].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_9),
        .IDATAIN(mem_dq_in[7]),
        .INC(idelay_inc),
        .LD(LD0_8),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[9].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0_8),
        .CLKDIV(\NLW_input_[9].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[7]),
        .DDLY(data_in_dly_9),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[9].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[9].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[9].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D9[3]),
        .Q2(D9[2]),
        .Q3(D9[1]),
        .Q4(D9[0]),
        .Q5(\NLW_input_[9].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[9].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[9].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[9].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[1].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[0]),
        .D2(of_dqbus[1]),
        .D3(of_dqbus[2]),
        .D4(of_dqbus[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[0]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[0]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[2].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[4]),
        .D2(of_dqbus[5]),
        .D3(of_dqbus[6]),
        .D4(of_dqbus[7]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[1]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[1]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[3].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[8]),
        .D2(of_dqbus[9]),
        .D3(of_dqbus[10]),
        .D4(of_dqbus[11]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[2]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[2]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[4].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[12]),
        .D2(of_dqbus[13]),
        .D3(of_dqbus[14]),
        .D4(of_dqbus[15]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[3]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[3]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[5].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[16]),
        .D2(of_dqbus[17]),
        .D3(of_dqbus[18]),
        .D4(of_dqbus[19]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[4]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[4]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[6].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[20]),
        .D2(of_dqbus[21]),
        .D3(of_dqbus[22]),
        .D4(of_dqbus[23]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[5]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[5]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[7].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[24]),
        .D2(of_dqbus[25]),
        .D3(of_dqbus[26]),
        .D4(of_dqbus[27]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[6]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[6]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[8].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[28]),
        .D2(of_dqbus[29]),
        .D3(of_dqbus[30]),
        .D4(of_dqbus[31]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[7]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[7]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[9].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[32]),
        .D2(of_dqbus[33]),
        .D3(of_dqbus[34]),
        .D4(of_dqbus[35]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[8]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[8]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("TRUE"),
    .TRISTATE_WIDTH(4)) 
    \slave_ts.oserdes_slave_ts 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(1'b0),
        .D2(1'b0),
        .D3(1'b0),
        .D4(1'b0),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED ),
        .OQ(\NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED ),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED ),
        .T1(DTSBUS[0]),
        .T2(DTSBUS[0]),
        .T3(DTSBUS[1]),
        .T4(DTSBUS[1]),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(tbyte_out),
        .TCE(1'b1),
        .TFB(\NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED ),
        .TQ(\NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED ));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_byte_group_io" *) 
module mig_mig_7series_v4_2_ddr_byte_group_io__parameterized0_35
   (out_dqs_5,
    ts_dqs_5,
    D2,
    D3,
    D4,
    D5,
    D6,
    D7,
    D8,
    D9,
    mem_dq_out,
    mem_dq_ts,
    idelay_ld_rst_0,
    oserdes_clk,
    oserdes_clkdiv,
    po_oserdes_rst,
    DTSBUS,
    oserdes_clk_delayed,
    DQSBUS,
    CTSBUS,
    idelay_ld_rst_reg_0,
    \input_[9].iserdes_dq_.iserdesdq_0 ,
    mem_dq_in,
    idelay_inc,
    LD0_7,
    A_rst_primitives,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,
    CLKB0_7,
    iserdes_clkdiv,
    of_dqbus,
    rst_r4);
  output out_dqs_5;
  output ts_dqs_5;
  output [3:0]D2;
  output [3:0]D3;
  output [3:0]D4;
  output [3:0]D5;
  output [3:0]D6;
  output [3:0]D7;
  output [3:0]D8;
  output [3:0]D9;
  output [8:0]mem_dq_out;
  output [8:0]mem_dq_ts;
  output idelay_ld_rst_0;
  input oserdes_clk;
  input oserdes_clkdiv;
  input po_oserdes_rst;
  input [1:0]DTSBUS;
  input oserdes_clk_delayed;
  input [1:0]DQSBUS;
  input [0:0]CTSBUS;
  input idelay_ld_rst_reg_0;
  input \input_[9].iserdes_dq_.iserdesdq_0 ;
  input [7:0]mem_dq_in;
  input idelay_inc;
  input LD0_7;
  input A_rst_primitives;
  input \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  input CLKB0_7;
  input iserdes_clkdiv;
  input [35:0]of_dqbus;
  input rst_r4;

  wire A_rst_primitives;
  wire CLKB0_7;
  wire [0:0]CTSBUS;
  wire [3:0]D2;
  wire [3:0]D3;
  wire [3:0]D4;
  wire [3:0]D5;
  wire [3:0]D6;
  wire [3:0]D7;
  wire [3:0]D8;
  wire [3:0]D9;
  wire [1:0]DQSBUS;
  wire [1:0]DTSBUS;
  wire LD0_7;
  wire data_in_dly_2;
  wire data_in_dly_3;
  wire data_in_dly_4;
  wire data_in_dly_5;
  wire data_in_dly_6;
  wire data_in_dly_7;
  wire data_in_dly_8;
  wire data_in_dly_9;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  wire idelay_inc;
  wire idelay_ld_rst_0;
  wire idelay_ld_rst_i_1__0_n_0;
  wire idelay_ld_rst_reg_0;
  wire \input_[9].iserdes_dq_.iserdesdq_0 ;
  wire iserdes_clkdiv;
  wire [7:0]mem_dq_in;
  wire [8:0]mem_dq_out;
  wire [8:0]mem_dq_ts;
  wire [35:0]of_dqbus;
  wire oserdes_clk;
  wire oserdes_clk_delayed;
  wire oserdes_clkdiv;
  wire out_dqs_5;
  wire po_oserdes_rst;
  wire rst_r4;
  wire tbyte_out;
  wire ts_dqs_5;
  wire \NLW_dqs_gen.oddr_dqs_S_UNCONNECTED ;
  wire \NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED ;
  wire [4:0]\NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[3].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[5].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[8].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire [4:0]\NLW_input_[9].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_O_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED ;
  wire \NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED ;

  (* BOX_TYPE = "PRIMITIVE" *) 
  (* __SRVAL = "FALSE" *) 
  ODDR #(
    .DDR_CLK_EDGE("SAME_EDGE"),
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .SRTYPE("SYNC")) 
    \dqs_gen.oddr_dqs 
       (.C(oserdes_clk_delayed),
        .CE(1'b1),
        .D1(DQSBUS[0]),
        .D2(DQSBUS[1]),
        .Q(out_dqs_5),
        .R(1'b0),
        .S(\NLW_dqs_gen.oddr_dqs_S_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* __SRVAL = "TRUE" *) 
  ODDR #(
    .DDR_CLK_EDGE("SAME_EDGE"),
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .SRTYPE("SYNC")) 
    \dqs_gen.oddr_dqsts 
       (.C(oserdes_clk_delayed),
        .CE(1'b1),
        .D1(CTSBUS),
        .D2(CTSBUS),
        .Q(ts_dqs_5),
        .R(\NLW_dqs_gen.oddr_dqsts_R_UNCONNECTED ),
        .S(1'b0));
  LUT2 #(
    .INIT(4'h2)) 
    idelay_ld_rst_i_1__0
       (.I0(idelay_ld_rst_0),
        .I1(rst_r4),
        .O(idelay_ld_rst_i_1__0_n_0));
  FDSE idelay_ld_rst_reg
       (.C(idelay_ld_rst_reg_0),
        .CE(1'b1),
        .D(idelay_ld_rst_i_1__0_n_0),
        .Q(idelay_ld_rst_0),
        .S(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[2].iserdes_dq_.idelay_dq.idelaye2 
       (.C(idelay_ld_rst_reg_0),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[2].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_2),
        .IDATAIN(mem_dq_in[0]),
        .INC(idelay_inc),
        .LD(LD0_7),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[2].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0_7),
        .CLKDIV(\NLW_input_[2].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[0]),
        .DDLY(data_in_dly_2),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[2].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[2].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[2].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D2[3]),
        .Q2(D2[2]),
        .Q3(D2[1]),
        .Q4(D2[0]),
        .Q5(\NLW_input_[2].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[2].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[2].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[2].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[2].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[3].iserdes_dq_.idelay_dq.idelaye2 
       (.C(idelay_ld_rst_reg_0),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[3].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_3),
        .IDATAIN(mem_dq_in[1]),
        .INC(idelay_inc),
        .LD(LD0_7),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[3].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0_7),
        .CLKDIV(\NLW_input_[3].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[1]),
        .DDLY(data_in_dly_3),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[3].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[3].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[3].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D3[3]),
        .Q2(D3[2]),
        .Q3(D3[1]),
        .Q4(D3[0]),
        .Q5(\NLW_input_[3].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[3].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[3].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[3].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[3].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[4].iserdes_dq_.idelay_dq.idelaye2 
       (.C(idelay_ld_rst_reg_0),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[4].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_4),
        .IDATAIN(mem_dq_in[2]),
        .INC(idelay_inc),
        .LD(LD0_7),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[4].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0_7),
        .CLKDIV(\NLW_input_[4].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[2]),
        .DDLY(data_in_dly_4),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[4].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[4].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[4].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D4[3]),
        .Q2(D4[2]),
        .Q3(D4[1]),
        .Q4(D4[0]),
        .Q5(\NLW_input_[4].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[4].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[4].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[4].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[4].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[5].iserdes_dq_.idelay_dq.idelaye2 
       (.C(idelay_ld_rst_reg_0),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[5].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_5),
        .IDATAIN(mem_dq_in[3]),
        .INC(idelay_inc),
        .LD(LD0_7),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[5].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0_7),
        .CLKDIV(\NLW_input_[5].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[3]),
        .DDLY(data_in_dly_5),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[5].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[5].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[5].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D5[3]),
        .Q2(D5[2]),
        .Q3(D5[1]),
        .Q4(D5[0]),
        .Q5(\NLW_input_[5].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[5].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[5].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[5].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[5].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[6].iserdes_dq_.idelay_dq.idelaye2 
       (.C(idelay_ld_rst_reg_0),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[6].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_6),
        .IDATAIN(mem_dq_in[4]),
        .INC(idelay_inc),
        .LD(LD0_7),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[6].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0_7),
        .CLKDIV(\NLW_input_[6].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[4]),
        .DDLY(data_in_dly_6),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[6].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[6].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[6].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D6[3]),
        .Q2(D6[2]),
        .Q3(D6[1]),
        .Q4(D6[0]),
        .Q5(\NLW_input_[6].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[6].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[6].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[6].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[6].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[7].iserdes_dq_.idelay_dq.idelaye2 
       (.C(idelay_ld_rst_reg_0),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[7].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_7),
        .IDATAIN(mem_dq_in[5]),
        .INC(idelay_inc),
        .LD(LD0_7),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[7].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0_7),
        .CLKDIV(\NLW_input_[7].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[5]),
        .DDLY(data_in_dly_7),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[7].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[7].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[7].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D7[3]),
        .Q2(D7[2]),
        .Q3(D7[1]),
        .Q4(D7[0]),
        .Q5(\NLW_input_[7].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[7].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[7].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[7].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[7].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[8].iserdes_dq_.idelay_dq.idelaye2 
       (.C(idelay_ld_rst_reg_0),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[8].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_8),
        .IDATAIN(mem_dq_in[6]),
        .INC(idelay_inc),
        .LD(LD0_7),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[8].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0_7),
        .CLKDIV(\NLW_input_[8].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[6]),
        .DDLY(data_in_dly_8),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[8].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[8].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[8].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D8[3]),
        .Q2(D8[2]),
        .Q3(D8[1]),
        .Q4(D8[0]),
        .Q5(\NLW_input_[8].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[8].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[8].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[8].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[8].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_IODELAY_MIG0" *) 
  (* SIM_DELAY_D = "0" *) 
  IDELAYE2 #(
    .CINVCTRL_SEL("FALSE"),
    .DELAY_SRC("IDATAIN"),
    .HIGH_PERFORMANCE_MODE("TRUE"),
    .IDELAY_TYPE("VARIABLE"),
    .IDELAY_VALUE(0),
    .IS_C_INVERTED(1'b0),
    .IS_DATAIN_INVERTED(1'b0),
    .IS_IDATAIN_INVERTED(1'b0),
    .PIPE_SEL("FALSE"),
    .REFCLK_FREQUENCY(200.000000),
    .SIGNAL_PATTERN("DATA")) 
    \input_[9].iserdes_dq_.idelay_dq.idelaye2 
       (.C(idelay_ld_rst_reg_0),
        .CE(\input_[9].iserdes_dq_.iserdesdq_0 ),
        .CINVCTRL(1'b0),
        .CNTVALUEIN({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CNTVALUEOUT(\NLW_input_[9].iserdes_dq_.idelay_dq.idelaye2_CNTVALUEOUT_UNCONNECTED [4:0]),
        .DATAIN(1'b0),
        .DATAOUT(data_in_dly_9),
        .IDATAIN(mem_dq_in[7]),
        .INC(idelay_inc),
        .LD(LD0_7),
        .LDPIPEEN(1'b0),
        .REGRST(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* OPT_MODIFIED = "MLO" *) 
  ISERDESE2 #(
    .DATA_RATE("DDR"),
    .DATA_WIDTH(4),
    .DYN_CLKDIV_INV_EN("FALSE"),
    .DYN_CLK_INV_EN("FALSE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .INIT_Q3(1'b0),
    .INIT_Q4(1'b0),
    .INTERFACE_TYPE("MEMORY_DDR3"),
    .IOBDELAY("IFD"),
    .IS_CLKB_INVERTED(1'b1),
    .IS_CLKDIVP_INVERTED(1'b0),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .IS_OCLKB_INVERTED(1'b0),
    .IS_OCLK_INVERTED(1'b0),
    .NUM_CE(2),
    .OFB_USED("FALSE"),
    .SERDES_MODE("MASTER"),
    .SRVAL_Q1(1'b0),
    .SRVAL_Q2(1'b0),
    .SRVAL_Q3(1'b0),
    .SRVAL_Q4(1'b0)) 
    \input_[9].iserdes_dq_.iserdesdq 
       (.BITSLIP(1'b0),
        .CE1(1'b1),
        .CE2(1'b1),
        .CLK(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .CLKB(CLKB0_7),
        .CLKDIV(\NLW_input_[9].iserdes_dq_.iserdesdq_CLKDIV_UNCONNECTED ),
        .CLKDIVP(iserdes_clkdiv),
        .D(mem_dq_in[7]),
        .DDLY(data_in_dly_9),
        .DYNCLKDIVSEL(1'b0),
        .DYNCLKSEL(1'b0),
        .O(\NLW_input_[9].iserdes_dq_.iserdesdq_O_UNCONNECTED ),
        .OCLK(oserdes_clk),
        .OCLKB(\NLW_input_[9].iserdes_dq_.iserdesdq_OCLKB_UNCONNECTED ),
        .OFB(\NLW_input_[9].iserdes_dq_.iserdesdq_OFB_UNCONNECTED ),
        .Q1(D9[3]),
        .Q2(D9[2]),
        .Q3(D9[1]),
        .Q4(D9[0]),
        .Q5(\NLW_input_[9].iserdes_dq_.iserdesdq_Q5_UNCONNECTED ),
        .Q6(\NLW_input_[9].iserdes_dq_.iserdesdq_Q6_UNCONNECTED ),
        .Q7(\NLW_input_[9].iserdes_dq_.iserdesdq_Q7_UNCONNECTED ),
        .Q8(\NLW_input_[9].iserdes_dq_.iserdesdq_Q8_UNCONNECTED ),
        .RST(1'b0),
        .SHIFTIN1(1'b0),
        .SHIFTIN2(1'b0),
        .SHIFTOUT1(\NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_input_[9].iserdes_dq_.iserdesdq_SHIFTOUT2_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[1].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[0]),
        .D2(of_dqbus[1]),
        .D3(of_dqbus[2]),
        .D4(of_dqbus[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[0]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[1].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[0]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[2].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[4]),
        .D2(of_dqbus[5]),
        .D3(of_dqbus[6]),
        .D4(of_dqbus[7]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[1]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[2].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[1]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[3].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[8]),
        .D2(of_dqbus[9]),
        .D3(of_dqbus[10]),
        .D4(of_dqbus[11]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[2]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[3].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[2]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[4].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[12]),
        .D2(of_dqbus[13]),
        .D3(of_dqbus[14]),
        .D4(of_dqbus[15]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[3]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[4].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[3]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[5].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[16]),
        .D2(of_dqbus[17]),
        .D3(of_dqbus[18]),
        .D4(of_dqbus[19]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[4]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[5].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[4]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[6].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[20]),
        .D2(of_dqbus[21]),
        .D3(of_dqbus[22]),
        .D4(of_dqbus[23]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[5]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[6].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[5]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[7].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[24]),
        .D2(of_dqbus[25]),
        .D3(of_dqbus[26]),
        .D4(of_dqbus[27]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[6]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[7].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[6]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[8].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[28]),
        .D2(of_dqbus[29]),
        .D3(of_dqbus[30]),
        .D4(of_dqbus[31]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[7]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[8].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[7]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(4)) 
    \output_[9].oserdes_dq_.ddr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(of_dqbus[32]),
        .D2(of_dqbus[33]),
        .D3(of_dqbus[34]),
        .D4(of_dqbus[35]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[8]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[9].oserdes_dq_.ddr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(mem_dq_ts[8]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("DDR"),
    .DATA_RATE_TQ("DDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b1),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b1),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("TRUE"),
    .TBYTE_SRC("TRUE"),
    .TRISTATE_WIDTH(4)) 
    \slave_ts.oserdes_slave_ts 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(1'b0),
        .D2(1'b0),
        .D3(1'b0),
        .D4(1'b0),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_slave_ts.oserdes_slave_ts_OFB_UNCONNECTED ),
        .OQ(\NLW_slave_ts.oserdes_slave_ts_OQ_UNCONNECTED ),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_slave_ts.oserdes_slave_ts_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_slave_ts.oserdes_slave_ts_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_slave_ts.oserdes_slave_ts_SHIFTOUT2_UNCONNECTED ),
        .T1(DTSBUS[0]),
        .T2(DTSBUS[0]),
        .T3(DTSBUS[1]),
        .T4(DTSBUS[1]),
        .TBYTEIN(tbyte_out),
        .TBYTEOUT(tbyte_out),
        .TCE(1'b1),
        .TFB(\NLW_slave_ts.oserdes_slave_ts_TFB_UNCONNECTED ),
        .TQ(\NLW_slave_ts.oserdes_slave_ts_TQ_UNCONNECTED ));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_byte_group_io" *) 
module mig_mig_7series_v4_2_ddr_byte_group_io__parameterized1
   (mem_dq_out,
    oserdes_clk,
    oserdes_clkdiv,
    oserdes_dq,
    po_oserdes_rst);
  output [5:0]mem_dq_out;
  input oserdes_clk;
  input oserdes_clkdiv;
  input [23:0]oserdes_dq;
  input po_oserdes_rst;

  wire [5:0]mem_dq_out;
  wire oserdes_clk;
  wire oserdes_clkdiv;
  wire [23:0]oserdes_dq;
  wire po_oserdes_rst;
  wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;
  wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;
  wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;
  wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;

  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("SDR"),
    .DATA_RATE_TQ("SDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b0),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b0),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("FALSE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(1)) 
    \output_[10].oserdes_dq_.sdr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(oserdes_dq[16]),
        .D2(oserdes_dq[17]),
        .D3(oserdes_dq[18]),
        .D4(oserdes_dq[19]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[4]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),
        .TBYTEOUT(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("SDR"),
    .DATA_RATE_TQ("SDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b0),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b0),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("FALSE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(1)) 
    \output_[11].oserdes_dq_.sdr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(oserdes_dq[20]),
        .D2(oserdes_dq[21]),
        .D3(oserdes_dq[22]),
        .D4(oserdes_dq[23]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[5]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),
        .TBYTEOUT(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("SDR"),
    .DATA_RATE_TQ("SDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b0),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b0),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("FALSE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(1)) 
    \output_[2].oserdes_dq_.sdr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(oserdes_dq[0]),
        .D2(oserdes_dq[1]),
        .D3(oserdes_dq[2]),
        .D4(oserdes_dq[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[0]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),
        .TBYTEOUT(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("SDR"),
    .DATA_RATE_TQ("SDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b0),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b0),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("FALSE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(1)) 
    \output_[4].oserdes_dq_.sdr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(oserdes_dq[4]),
        .D2(oserdes_dq[5]),
        .D3(oserdes_dq[6]),
        .D4(oserdes_dq[7]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[1]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),
        .TBYTEOUT(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("SDR"),
    .DATA_RATE_TQ("SDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b0),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b0),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("FALSE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(1)) 
    \output_[5].oserdes_dq_.sdr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(oserdes_dq[8]),
        .D2(oserdes_dq[9]),
        .D3(oserdes_dq[10]),
        .D4(oserdes_dq[11]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[2]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),
        .TBYTEOUT(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("SDR"),
    .DATA_RATE_TQ("SDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b0),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b0),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("FALSE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(1)) 
    \output_[7].oserdes_dq_.sdr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(oserdes_dq[12]),
        .D2(oserdes_dq[13]),
        .D3(oserdes_dq[14]),
        .D4(oserdes_dq[15]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[3]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),
        .TBYTEOUT(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_byte_group_io" *) 
module mig_mig_7series_v4_2_ddr_byte_group_io__parameterized2
   (mem_dq_out,
    oserdes_clk,
    oserdes_clkdiv,
    oserdes_dq,
    po_oserdes_rst);
  output [5:0]mem_dq_out;
  input oserdes_clk;
  input oserdes_clkdiv;
  input [23:0]oserdes_dq;
  input po_oserdes_rst;

  wire [5:0]mem_dq_out;
  wire oserdes_clk;
  wire oserdes_clkdiv;
  wire [23:0]oserdes_dq;
  wire po_oserdes_rst;
  wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;
  wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;
  wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;
  wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;

  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("SDR"),
    .DATA_RATE_TQ("SDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b0),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b0),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("FALSE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(1)) 
    \output_[10].oserdes_dq_.sdr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(oserdes_dq[16]),
        .D2(oserdes_dq[17]),
        .D3(oserdes_dq[18]),
        .D4(oserdes_dq[19]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[4]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),
        .TBYTEOUT(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("SDR"),
    .DATA_RATE_TQ("SDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b0),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b0),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("FALSE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(1)) 
    \output_[11].oserdes_dq_.sdr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(oserdes_dq[20]),
        .D2(oserdes_dq[21]),
        .D3(oserdes_dq[22]),
        .D4(oserdes_dq[23]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[5]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),
        .TBYTEOUT(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("SDR"),
    .DATA_RATE_TQ("SDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b0),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b0),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("FALSE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(1)) 
    \output_[4].oserdes_dq_.sdr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(oserdes_dq[0]),
        .D2(oserdes_dq[1]),
        .D3(oserdes_dq[2]),
        .D4(oserdes_dq[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[0]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),
        .TBYTEOUT(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("SDR"),
    .DATA_RATE_TQ("SDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b0),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b0),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("FALSE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(1)) 
    \output_[5].oserdes_dq_.sdr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(oserdes_dq[4]),
        .D2(oserdes_dq[5]),
        .D3(oserdes_dq[6]),
        .D4(oserdes_dq[7]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[1]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),
        .TBYTEOUT(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("SDR"),
    .DATA_RATE_TQ("SDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b0),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b0),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("FALSE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(1)) 
    \output_[8].oserdes_dq_.sdr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(oserdes_dq[8]),
        .D2(oserdes_dq[9]),
        .D3(oserdes_dq[10]),
        .D4(oserdes_dq[11]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[2]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),
        .TBYTEOUT(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("SDR"),
    .DATA_RATE_TQ("SDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b0),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b0),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("FALSE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(1)) 
    \output_[9].oserdes_dq_.sdr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(oserdes_dq[12]),
        .D2(oserdes_dq[13]),
        .D3(oserdes_dq[14]),
        .D4(oserdes_dq[15]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[3]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),
        .TBYTEOUT(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_byte_group_io" *) 
module mig_mig_7series_v4_2_ddr_byte_group_io__parameterized3
   (mem_dq_out,
    oserdes_clk,
    oserdes_clkdiv,
    oserdes_dq,
    po_oserdes_rst);
  output [10:0]mem_dq_out;
  input oserdes_clk;
  input oserdes_clkdiv;
  input [43:0]oserdes_dq;
  input po_oserdes_rst;

  wire [10:0]mem_dq_out;
  wire oserdes_clk;
  wire oserdes_clkdiv;
  wire [43:0]oserdes_dq;
  wire po_oserdes_rst;
  wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;
  wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;
  wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;
  wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ;
  wire \NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ;

  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("SDR"),
    .DATA_RATE_TQ("SDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b0),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b0),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("FALSE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(1)) 
    \output_[10].oserdes_dq_.sdr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(oserdes_dq[36]),
        .D2(oserdes_dq[37]),
        .D3(oserdes_dq[38]),
        .D4(oserdes_dq[39]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[9]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),
        .TBYTEOUT(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\NLW_output_[10].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("SDR"),
    .DATA_RATE_TQ("SDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b0),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b0),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("FALSE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(1)) 
    \output_[11].oserdes_dq_.sdr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(oserdes_dq[40]),
        .D2(oserdes_dq[41]),
        .D3(oserdes_dq[42]),
        .D4(oserdes_dq[43]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[10]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),
        .TBYTEOUT(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\NLW_output_[11].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("SDR"),
    .DATA_RATE_TQ("SDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b0),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b0),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("FALSE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(1)) 
    \output_[1].oserdes_dq_.sdr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(oserdes_dq[0]),
        .D2(oserdes_dq[1]),
        .D3(oserdes_dq[2]),
        .D4(oserdes_dq[3]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[0]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),
        .TBYTEOUT(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\NLW_output_[1].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("SDR"),
    .DATA_RATE_TQ("SDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b0),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b0),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("FALSE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(1)) 
    \output_[2].oserdes_dq_.sdr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(oserdes_dq[4]),
        .D2(oserdes_dq[5]),
        .D3(oserdes_dq[6]),
        .D4(oserdes_dq[7]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[1]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),
        .TBYTEOUT(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\NLW_output_[2].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("SDR"),
    .DATA_RATE_TQ("SDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b0),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b0),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("FALSE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(1)) 
    \output_[3].oserdes_dq_.sdr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(oserdes_dq[8]),
        .D2(oserdes_dq[9]),
        .D3(oserdes_dq[10]),
        .D4(oserdes_dq[11]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[2]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),
        .TBYTEOUT(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\NLW_output_[3].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("SDR"),
    .DATA_RATE_TQ("SDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b0),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b0),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("FALSE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(1)) 
    \output_[4].oserdes_dq_.sdr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(oserdes_dq[12]),
        .D2(oserdes_dq[13]),
        .D3(oserdes_dq[14]),
        .D4(oserdes_dq[15]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[3]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),
        .TBYTEOUT(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\NLW_output_[4].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("SDR"),
    .DATA_RATE_TQ("SDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b0),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b0),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("FALSE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(1)) 
    \output_[5].oserdes_dq_.sdr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(oserdes_dq[16]),
        .D2(oserdes_dq[17]),
        .D3(oserdes_dq[18]),
        .D4(oserdes_dq[19]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[4]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),
        .TBYTEOUT(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\NLW_output_[5].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("SDR"),
    .DATA_RATE_TQ("SDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b0),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b0),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("FALSE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(1)) 
    \output_[6].oserdes_dq_.sdr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(oserdes_dq[20]),
        .D2(oserdes_dq[21]),
        .D3(oserdes_dq[22]),
        .D4(oserdes_dq[23]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[5]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),
        .TBYTEOUT(\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\NLW_output_[6].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("SDR"),
    .DATA_RATE_TQ("SDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b0),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b0),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("FALSE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(1)) 
    \output_[7].oserdes_dq_.sdr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(oserdes_dq[24]),
        .D2(oserdes_dq[25]),
        .D3(oserdes_dq[26]),
        .D4(oserdes_dq[27]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[6]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),
        .TBYTEOUT(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\NLW_output_[7].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("SDR"),
    .DATA_RATE_TQ("SDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b0),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b0),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("FALSE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(1)) 
    \output_[8].oserdes_dq_.sdr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(oserdes_dq[28]),
        .D2(oserdes_dq[29]),
        .D3(oserdes_dq[30]),
        .D4(oserdes_dq[31]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[7]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),
        .TBYTEOUT(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\NLW_output_[8].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OSERDESE2 #(
    .DATA_RATE_OQ("SDR"),
    .DATA_RATE_TQ("SDR"),
    .DATA_WIDTH(4),
    .INIT_OQ(1'b0),
    .INIT_TQ(1'b1),
    .IS_CLKDIV_INVERTED(1'b0),
    .IS_CLK_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .IS_D3_INVERTED(1'b0),
    .IS_D4_INVERTED(1'b0),
    .IS_D5_INVERTED(1'b0),
    .IS_D6_INVERTED(1'b0),
    .IS_D7_INVERTED(1'b0),
    .IS_D8_INVERTED(1'b0),
    .IS_T1_INVERTED(1'b0),
    .IS_T2_INVERTED(1'b0),
    .IS_T3_INVERTED(1'b0),
    .IS_T4_INVERTED(1'b0),
    .SERDES_MODE("MASTER"),
    .SRVAL_OQ(1'b0),
    .SRVAL_TQ(1'b1),
    .TBYTE_CTL("FALSE"),
    .TBYTE_SRC("FALSE"),
    .TRISTATE_WIDTH(1)) 
    \output_[9].oserdes_dq_.sdr.oserdes_dq_i 
       (.CLK(oserdes_clk),
        .CLKDIV(oserdes_clkdiv),
        .D1(oserdes_dq[32]),
        .D2(oserdes_dq[33]),
        .D3(oserdes_dq[34]),
        .D4(oserdes_dq[35]),
        .D5(1'b0),
        .D6(1'b0),
        .D7(1'b0),
        .D8(1'b0),
        .OCE(1'b1),
        .OFB(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_OFB_UNCONNECTED ),
        .OQ(mem_dq_out[8]),
        .RST(po_oserdes_rst),
        .SHIFTIN1(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN1_UNCONNECTED ),
        .SHIFTIN2(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTIN2_UNCONNECTED ),
        .SHIFTOUT1(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT1_UNCONNECTED ),
        .SHIFTOUT2(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_SHIFTOUT2_UNCONNECTED ),
        .T1(1'b0),
        .T2(1'b0),
        .T3(1'b0),
        .T4(1'b0),
        .TBYTEIN(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEIN_UNCONNECTED ),
        .TBYTEOUT(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TBYTEOUT_UNCONNECTED ),
        .TCE(1'b1),
        .TFB(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TFB_UNCONNECTED ),
        .TQ(\NLW_output_[9].oserdes_dq_.sdr.oserdes_dq_i_TQ_UNCONNECTED ));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_byte_lane" *) 
module mig_mig_7series_v4_2_ddr_byte_lane
   (out_dqs_0,
    ts_dqs_0,
    A_rst_primitives_reg,
    mem_dq_out,
    mem_dq_ts,
    in0,
    A_rst_primitives_reg_0,
    COUNTERREADVAL,
    A_rst_primitives_reg_1,
    if_empty_r,
    \my_empty_reg[4] ,
    idelay_ld_rst_3,
    \my_empty_reg[1] ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ,
    \rd_ptr_reg[3] ,
    Q,
    \wr_ptr_timing_reg[3] ,
    \input_[9].iserdes_dq_.iserdesdq ,
    mem_dq_in,
    idelay_inc,
    LD0_10,
    A_rst_primitives,
    CLKB0_10,
    phaser_ctl_bus,
    \pi_dqs_found_lanes_r1_reg[8] ,
    \pi_dqs_found_lanes_r1_reg[8]_0 ,
    \pi_dqs_found_lanes_r1_reg[8]_1 ,
    \pi_dqs_found_lanes_r1_reg[8]_2 ,
    freq_refclk,
    mem_refclk,
    mem_dqs_in,
    ififo_rst_reg_0,
    sync_pulse,
    PCENABLECALIB,
    \pi_dqs_found_lanes_r1_reg[8]_3 ,
    \po_counter_read_val_reg[8] ,
    \po_counter_read_val_reg[8]_0 ,
    \po_counter_read_val_reg[8]_1 ,
    \my_empty_reg[7] ,
    D2,
    \my_empty_reg[7]_0 ,
    \my_empty_reg[7]_1 ,
    \my_empty_reg[7]_2 ,
    \my_empty_reg[7]_3 ,
    \my_empty_reg[7]_4 ,
    \my_empty_reg[7]_5 ,
    phy_if_reset,
    \my_full_reg[1] ,
    phy_data_wr_en,
    rst_r4,
    out_fifo_0,
    out_fifo_1,
    out_fifo_2,
    out_fifo_i_75__0);
  output out_dqs_0;
  output ts_dqs_0;
  output A_rst_primitives_reg;
  output [8:0]mem_dq_out;
  output [8:0]mem_dq_ts;
  output [0:0]in0;
  output A_rst_primitives_reg_0;
  output [5:0]COUNTERREADVAL;
  output [8:0]A_rst_primitives_reg_1;
  output [0:0]if_empty_r;
  output [0:0]\my_empty_reg[4] ;
  output idelay_ld_rst_3;
  output \my_empty_reg[1] ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ;
  output [63:0]\rd_ptr_reg[3] ;
  output [2:0]Q;
  input \wr_ptr_timing_reg[3] ;
  input \input_[9].iserdes_dq_.iserdesdq ;
  input [7:0]mem_dq_in;
  input idelay_inc;
  input LD0_10;
  input A_rst_primitives;
  input CLKB0_10;
  input [3:0]phaser_ctl_bus;
  input \pi_dqs_found_lanes_r1_reg[8] ;
  input \pi_dqs_found_lanes_r1_reg[8]_0 ;
  input \pi_dqs_found_lanes_r1_reg[8]_1 ;
  input \pi_dqs_found_lanes_r1_reg[8]_2 ;
  input freq_refclk;
  input mem_refclk;
  input [0:0]mem_dqs_in;
  input ififo_rst_reg_0;
  input sync_pulse;
  input [1:0]PCENABLECALIB;
  input [5:0]\pi_dqs_found_lanes_r1_reg[8]_3 ;
  input \po_counter_read_val_reg[8] ;
  input \po_counter_read_val_reg[8]_0 ;
  input \po_counter_read_val_reg[8]_1 ;
  input [7:0]\my_empty_reg[7] ;
  input [7:0]D2;
  input [7:0]\my_empty_reg[7]_0 ;
  input [7:0]\my_empty_reg[7]_1 ;
  input [7:0]\my_empty_reg[7]_2 ;
  input [7:0]\my_empty_reg[7]_3 ;
  input [7:0]\my_empty_reg[7]_4 ;
  input [7:0]\my_empty_reg[7]_5 ;
  input phy_if_reset;
  input \my_full_reg[1] ;
  input phy_data_wr_en;
  input rst_r4;
  input out_fifo_0;
  input [7:0]out_fifo_1;
  input out_fifo_2;
  input [71:0]out_fifo_i_75__0;

  wire A_rst_primitives;
  wire A_rst_primitives_reg;
  wire A_rst_primitives_reg_0;
  wire [8:0]A_rst_primitives_reg_1;
  wire CLKB0_10;
  wire [5:0]COUNTERREADVAL;
  wire [7:0]D2;
  wire LD0_10;
  wire [1:0]PCENABLECALIB;
  wire [2:0]Q;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ;
  wire freq_refclk;
  wire idelay_inc;
  wire idelay_ld_rst_3;
  wire [3:0]if_d1;
  wire [3:0]if_d2;
  wire [3:0]if_d3;
  wire [3:0]if_d4;
  wire [3:0]if_d5;
  wire [3:0]if_d6;
  wire [3:0]if_d7;
  wire [3:0]if_d9;
  wire if_empty_;
  wire [0:0]if_empty_r;
  wire ififo_rst;
  wire ififo_rst_reg_0;
  wire ififo_wr_enable;
  wire [0:0]in0;
  wire \in_fifo_gen.in_fifo_n_0 ;
  wire \in_fifo_gen.in_fifo_n_1 ;
  wire \in_fifo_gen.in_fifo_n_3 ;
  wire \input_[9].iserdes_dq_.iserdesdq ;
  wire iserdes_clkdiv;
  wire [7:0]mem_dq_in;
  wire [8:0]mem_dq_out;
  wire [8:0]mem_dq_ts;
  wire [0:0]mem_dqs_in;
  wire mem_refclk;
  wire \my_empty_reg[1] ;
  wire [0:0]\my_empty_reg[4] ;
  wire [7:0]\my_empty_reg[7] ;
  wire [7:0]\my_empty_reg[7]_0 ;
  wire [7:0]\my_empty_reg[7]_1 ;
  wire [7:0]\my_empty_reg[7]_2 ;
  wire [7:0]\my_empty_reg[7]_3 ;
  wire [7:0]\my_empty_reg[7]_4 ;
  wire [7:0]\my_empty_reg[7]_5 ;
  wire \my_full_reg[1] ;
  wire [7:0]of_d0;
  wire [39:0]of_dqbus;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ;
  wire ofifo_rst;
  wire oserdes_clk;
  wire oserdes_clk_delayed;
  wire oserdes_clkdiv;
  wire [1:0]oserdes_dq_ts;
  wire [1:0]oserdes_dqs;
  wire [1:0]oserdes_dqs_ts;
  wire out_dqs_0;
  wire out_fifo_0;
  wire [7:0]out_fifo_1;
  wire out_fifo_2;
  wire [71:0]out_fifo_i_75__0;
  wire out_fifo_n_0;
  wire out_fifo_n_1;
  wire out_fifo_n_2;
  wire out_fifo_n_3;
  wire [3:0]phaser_ctl_bus;
  wire \phaser_in_gen.phaser_in_n_1 ;
  wire \phaser_in_gen.phaser_in_n_2 ;
  wire \phaser_in_gen.phaser_in_n_5 ;
  wire \phaser_in_gen.phaser_in_n_7 ;
  wire phaser_out_n_0;
  wire phaser_out_n_1;
  wire phy_data_wr_en;
  wire phy_if_reset;
  wire \pi_dqs_found_lanes_r1_reg[8] ;
  wire \pi_dqs_found_lanes_r1_reg[8]_0 ;
  wire \pi_dqs_found_lanes_r1_reg[8]_1 ;
  wire \pi_dqs_found_lanes_r1_reg[8]_2 ;
  wire [5:0]\pi_dqs_found_lanes_r1_reg[8]_3 ;
  wire \po_counter_read_val_reg[8] ;
  wire \po_counter_read_val_reg[8]_0 ;
  wire \po_counter_read_val_reg[8]_1 ;
  wire po_oserdes_rst;
  wire po_rd_enable;
  wire [79:0]rd_data;
  wire [79:6]rd_data_r;
  wire [63:0]\rd_ptr_reg[3] ;
  wire rst_r4;
  wire sync_pulse;
  wire ts_dqs_0;
  wire \wr_ptr_timing_reg[3] ;
  wire [7:4]\NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED ;
  wire [7:4]\NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED ;
  wire [7:4]NLW_out_fifo_Q5_UNCONNECTED;
  wire [7:4]NLW_out_fifo_Q6_UNCONNECTED;
  wire NLW_phaser_out_PHASEREFCLK_UNCONNECTED;

  mig_mig_7series_v4_2_ddr_byte_group_io ddr_byte_group_io
       (.A_rst_primitives(A_rst_primitives),
        .CLKB0_10(CLKB0_10),
        .CTSBUS(oserdes_dqs_ts[0]),
        .D1(if_d1),
        .D2(if_d2),
        .D3(if_d3),
        .D4(if_d4),
        .D5(if_d5),
        .D6(if_d6),
        .D7(if_d7),
        .D9(if_d9),
        .DQSBUS(oserdes_dqs),
        .DTSBUS(oserdes_dq_ts),
        .LD0_10(LD0_10),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (A_rst_primitives_reg),
        .idelay_inc(idelay_inc),
        .idelay_ld_rst_3(idelay_ld_rst_3),
        .idelay_ld_rst_reg_0(\wr_ptr_timing_reg[3] ),
        .\input_[9].iserdes_dq_.iserdesdq_0 (\input_[9].iserdes_dq_.iserdesdq ),
        .iserdes_clkdiv(iserdes_clkdiv),
        .mem_dq_in(mem_dq_in),
        .mem_dq_out(mem_dq_out),
        .mem_dq_ts(mem_dq_ts),
        .of_dqbus({of_dqbus[39:36],of_dqbus[31:0]}),
        .oserdes_clk(oserdes_clk),
        .oserdes_clk_delayed(oserdes_clk_delayed),
        .oserdes_clkdiv(oserdes_clkdiv),
        .out_dqs_0(out_dqs_0),
        .po_oserdes_rst(po_oserdes_rst),
        .rst_r4(rst_r4),
        .ts_dqs_0(ts_dqs_0));
  (* syn_maxfan = "3" *) 
  FDRE \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(if_empty_),
        .Q(if_empty_r),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[10]),
        .Q(rd_data_r[10]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[11]),
        .Q(rd_data_r[11]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[12]),
        .Q(rd_data_r[12]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[13]),
        .Q(rd_data_r[13]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[14]),
        .Q(rd_data_r[14]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[15]),
        .Q(rd_data_r[15]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[16]),
        .Q(rd_data_r[16]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[17]),
        .Q(rd_data_r[17]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[18]),
        .Q(rd_data_r[18]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[19]),
        .Q(rd_data_r[19]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[20]),
        .Q(rd_data_r[20]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[21]),
        .Q(rd_data_r[21]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[22]),
        .Q(rd_data_r[22]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[23]),
        .Q(rd_data_r[23]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[24]),
        .Q(rd_data_r[24]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[25]),
        .Q(rd_data_r[25]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[26]),
        .Q(rd_data_r[26]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[27]),
        .Q(rd_data_r[27]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[28]),
        .Q(rd_data_r[28]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[29]),
        .Q(rd_data_r[29]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[30]),
        .Q(rd_data_r[30]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[31]),
        .Q(rd_data_r[31]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[32]),
        .Q(rd_data_r[32]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[33]),
        .Q(rd_data_r[33]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[34]),
        .Q(rd_data_r[34]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[35]),
        .Q(rd_data_r[35]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[36]),
        .Q(rd_data_r[36]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[37]),
        .Q(rd_data_r[37]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[38]),
        .Q(rd_data_r[38]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[39]),
        .Q(rd_data_r[39]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[40]),
        .Q(rd_data_r[40]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[41]),
        .Q(rd_data_r[41]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[42]),
        .Q(rd_data_r[42]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[43]),
        .Q(rd_data_r[43]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[44]),
        .Q(rd_data_r[44]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[45]),
        .Q(rd_data_r[45]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[46]),
        .Q(rd_data_r[46]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[47]),
        .Q(rd_data_r[47]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[48]),
        .Q(rd_data_r[48]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[49]),
        .Q(rd_data_r[49]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[50]),
        .Q(rd_data_r[50]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[51]),
        .Q(rd_data_r[51]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[52]),
        .Q(rd_data_r[52]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[53]),
        .Q(rd_data_r[53]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[54]),
        .Q(rd_data_r[54]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[55]),
        .Q(rd_data_r[55]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[56]),
        .Q(rd_data_r[56]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[57]),
        .Q(rd_data_r[57]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[58]),
        .Q(rd_data_r[58]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[59]),
        .Q(rd_data_r[59]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[60]),
        .Q(rd_data_r[60]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[61]),
        .Q(rd_data_r[61]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[62]),
        .Q(rd_data_r[62]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[63]),
        .Q(rd_data_r[63]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[64]),
        .Q(rd_data_r[64]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[65]),
        .Q(rd_data_r[65]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[6]),
        .Q(rd_data_r[6]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[72]),
        .Q(rd_data_r[72]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[73]),
        .Q(rd_data_r[73]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[74]),
        .Q(rd_data_r[74]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[75]),
        .Q(rd_data_r[75]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[76]),
        .Q(rd_data_r[76]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[77]),
        .Q(rd_data_r[77]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[78]),
        .Q(rd_data_r[78]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[79]),
        .Q(rd_data_r[79]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[7]),
        .Q(rd_data_r[7]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[8]),
        .Q(rd_data_r[8]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[9]),
        .Q(rd_data_r[9]),
        .R(1'b0));
  mig_mig_7series_v4_2_ddr_if_post_fifo_20 \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo 
       (.Q({rd_data_r[79:72],rd_data_r[65:6]}),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ),
        .ififo_rst(ififo_rst),
        .\my_empty_reg[4]_0 (\my_empty_reg[4] ),
        .\my_full_reg[1]_0 (if_empty_r),
        .\my_full_reg[1]_1 (\my_full_reg[1] ),
        .\rd_ptr_reg[1]_0 (\wr_ptr_timing_reg[3] ));
  FDSE #(
    .INIT(1'b1)) 
    ififo_rst_reg
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(ififo_rst_reg_0),
        .Q(ififo_rst),
        .S(phy_if_reset));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IN_FIFO #(
    .ALMOST_EMPTY_VALUE(1),
    .ALMOST_FULL_VALUE(1),
    .ARRAY_MODE("ARRAY_MODE_4_X_8"),
    .SYNCHRONOUS_MODE("FALSE")) 
    \in_fifo_gen.in_fifo 
       (.ALMOSTEMPTY(\in_fifo_gen.in_fifo_n_0 ),
        .ALMOSTFULL(\in_fifo_gen.in_fifo_n_1 ),
        .D0({1'b0,1'b0,1'b0,1'b0}),
        .D1(if_d1),
        .D2(if_d2),
        .D3(if_d3),
        .D4(if_d4),
        .D5({\NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED [7:4],if_d5}),
        .D6({\NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED [7:4],if_d6}),
        .D7(if_d7),
        .D8({1'b0,1'b0,1'b0,1'b0}),
        .D9(if_d9),
        .EMPTY(if_empty_),
        .FULL(\in_fifo_gen.in_fifo_n_3 ),
        .Q0(rd_data[7:0]),
        .Q1(rd_data[15:8]),
        .Q2(rd_data[23:16]),
        .Q3(rd_data[31:24]),
        .Q4(rd_data[39:32]),
        .Q5(rd_data[47:40]),
        .Q6(rd_data[55:48]),
        .Q7(rd_data[63:56]),
        .Q8(rd_data[71:64]),
        .Q9(rd_data[79:72]),
        .RDCLK(\wr_ptr_timing_reg[3] ),
        .RDEN(1'b1),
        .RESET(ififo_rst),
        .WRCLK(iserdes_clkdiv),
        .WREN(ififo_wr_enable));
  mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_21 \of_pre_fifo_gen.u_ddr_of_pre_fifo 
       (.D0(of_d0),
        .D8({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 }),
        .Q(Q),
        .\my_empty_reg[1]_0 (\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ),
        .\my_empty_reg[1]_1 (\my_empty_reg[1] ),
        .\my_empty_reg[7]_0 (out_fifo_n_3),
        .ofifo_rst(ofifo_rst),
        .out_fifo(out_fifo_0),
        .out_fifo_0(out_fifo_1),
        .out_fifo_1(out_fifo_2),
        .out_fifo_i_75__0(out_fifo_i_75__0),
        .phy_data_wr_en(phy_data_wr_en),
        .\rd_ptr_reg[3]_0 (\rd_ptr_reg[3] ),
        .\wr_ptr_timing_reg[3]_0 (\wr_ptr_timing_reg[3] ));
  FDSE #(
    .INIT(1'b1)) 
    ofifo_rst_reg
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(ififo_rst_reg_0),
        .Q(ofifo_rst),
        .S(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OUT_FIFO #(
    .ALMOST_EMPTY_VALUE(1),
    .ALMOST_FULL_VALUE(1),
    .ARRAY_MODE("ARRAY_MODE_8_X_4"),
    .OUTPUT_DISABLE("FALSE"),
    .SYNCHRONOUS_MODE("FALSE")) 
    out_fifo
       (.ALMOSTEMPTY(out_fifo_n_0),
        .ALMOSTFULL(out_fifo_n_1),
        .D0(of_d0),
        .D1(\my_empty_reg[7] ),
        .D2(D2),
        .D3(\my_empty_reg[7]_0 ),
        .D4(\my_empty_reg[7]_1 ),
        .D5(\my_empty_reg[7]_2 ),
        .D6(\my_empty_reg[7]_3 ),
        .D7(\my_empty_reg[7]_4 ),
        .D8({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 }),
        .D9(\my_empty_reg[7]_5 ),
        .EMPTY(out_fifo_n_2),
        .FULL(out_fifo_n_3),
        .Q0(of_dqbus[3:0]),
        .Q1(of_dqbus[7:4]),
        .Q2(of_dqbus[11:8]),
        .Q3(of_dqbus[15:12]),
        .Q4(of_dqbus[19:16]),
        .Q5({NLW_out_fifo_Q5_UNCONNECTED[7:4],of_dqbus[23:20]}),
        .Q6({NLW_out_fifo_Q6_UNCONNECTED[7:4],of_dqbus[27:24]}),
        .Q7(of_dqbus[31:28]),
        .Q8(of_dqbus[35:32]),
        .Q9(of_dqbus[39:36]),
        .RDCLK(oserdes_clkdiv),
        .RDEN(po_rd_enable),
        .RESET(ofifo_rst),
        .WRCLK(\wr_ptr_timing_reg[3] ),
        .WREN(\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  PHASER_IN_PHY #(
    .BURST_MODE("TRUE"),
    .CLKOUT_DIV(2),
    .DQS_AUTO_RECAL(1'b1),
    .DQS_BIAS_MODE("FALSE"),
    .DQS_FIND_PATTERN(3'b000),
    .FINE_DELAY(33),
    .FREQ_REF_DIV("DIV2"),
    .IS_RST_INVERTED(1'b0),
    .MEMREFCLK_PERIOD(2.500000),
    .OUTPUT_CLK_SRC("DELAYED_REF"),
    .PHASEREFCLK_PERIOD(2.500000),
    .REFCLK_PERIOD(1.250000),
    .SEL_CLK_OFFSET(6),
    .SYNC_IN_DIV_RST("TRUE"),
    .WR_CYCLES("FALSE")) 
    \phaser_in_gen.phaser_in 
       (.BURSTPENDINGPHY(phaser_ctl_bus[1]),
        .COUNTERLOADEN(\pi_dqs_found_lanes_r1_reg[8] ),
        .COUNTERLOADVAL(\pi_dqs_found_lanes_r1_reg[8]_3 ),
        .COUNTERREADEN(\pi_dqs_found_lanes_r1_reg[8]_0 ),
        .COUNTERREADVAL(COUNTERREADVAL),
        .DQSFOUND(in0),
        .DQSOUTOFRANGE(\phaser_in_gen.phaser_in_n_1 ),
        .ENCALIBPHY(PCENABLECALIB),
        .FINEENABLE(\pi_dqs_found_lanes_r1_reg[8]_1 ),
        .FINEINC(\pi_dqs_found_lanes_r1_reg[8]_2 ),
        .FINEOVERFLOW(\phaser_in_gen.phaser_in_n_2 ),
        .FREQREFCLK(freq_refclk),
        .ICLK(A_rst_primitives_reg),
        .ICLKDIV(iserdes_clkdiv),
        .ISERDESRST(\phaser_in_gen.phaser_in_n_5 ),
        .MEMREFCLK(mem_refclk),
        .PHASELOCKED(A_rst_primitives_reg_0),
        .PHASEREFCLK(mem_dqs_in),
        .RANKSELPHY(phaser_ctl_bus[3:2]),
        .RCLK(\phaser_in_gen.phaser_in_n_7 ),
        .RST(A_rst_primitives),
        .RSTDQSFIND(ififo_rst_reg_0),
        .SYNCIN(sync_pulse),
        .SYSCLK(\wr_ptr_timing_reg[3] ),
        .WRENABLE(ififo_wr_enable));
  (* BOX_TYPE = "PRIMITIVE" *) 
  PHASER_OUT_PHY #(
    .CLKOUT_DIV(2),
    .COARSE_BYPASS("FALSE"),
    .COARSE_DELAY(0),
    .DATA_CTL_N("TRUE"),
    .DATA_RD_CYCLES("FALSE"),
    .FINE_DELAY(60),
    .IS_RST_INVERTED(1'b0),
    .MEMREFCLK_PERIOD(2.500000),
    .OCLKDELAY_INV("FALSE"),
    .OCLK_DELAY(0),
    .OUTPUT_CLK_SRC("DELAYED_REF"),
    .PHASEREFCLK_PERIOD(1.000000),
    .PO(3'b111),
    .REFCLK_PERIOD(1.250000),
    .SYNC_IN_DIV_RST("TRUE")) 
    phaser_out
       (.BURSTPENDINGPHY(phaser_ctl_bus[0]),
        .COARSEENABLE(\po_counter_read_val_reg[8] ),
        .COARSEINC(\po_counter_read_val_reg[8] ),
        .COARSEOVERFLOW(phaser_out_n_0),
        .COUNTERLOADEN(1'b0),
        .COUNTERLOADVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .COUNTERREADEN(\pi_dqs_found_lanes_r1_reg[8]_0 ),
        .COUNTERREADVAL(A_rst_primitives_reg_1),
        .CTSBUS(oserdes_dqs_ts),
        .DQSBUS(oserdes_dqs),
        .DTSBUS(oserdes_dq_ts),
        .ENCALIBPHY(PCENABLECALIB),
        .FINEENABLE(\po_counter_read_val_reg[8]_0 ),
        .FINEINC(\po_counter_read_val_reg[8]_1 ),
        .FINEOVERFLOW(phaser_out_n_1),
        .FREQREFCLK(freq_refclk),
        .MEMREFCLK(mem_refclk),
        .OCLK(oserdes_clk),
        .OCLKDELAYED(oserdes_clk_delayed),
        .OCLKDIV(oserdes_clkdiv),
        .OSERDESRST(po_oserdes_rst),
        .PHASEREFCLK(NLW_phaser_out_PHASEREFCLK_UNCONNECTED),
        .RDENABLE(po_rd_enable),
        .RST(A_rst_primitives),
        .SELFINEOCLKDELAY(1'b0),
        .SYNCIN(sync_pulse),
        .SYSCLK(\wr_ptr_timing_reg[3] ));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_byte_lane" *) 
module mig_mig_7series_v4_2_ddr_byte_lane_25
   (out_dqs_4,
    ts_dqs_4,
    A_rst_primitives_reg,
    mem_dq_out,
    mem_dq_ts,
    in0,
    A_rst_primitives_reg_0,
    COUNTERREADVAL,
    A_rst_primitives_reg_1,
    idelay_ld_rst,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ,
    if_empty,
    \my_empty_reg[1] ,
    phy_rddata_en,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ,
    \rd_ptr_reg[3] ,
    Q,
    \my_full_reg[4] ,
    \input_[9].iserdes_dq_.iserdesdq ,
    mem_dq_in,
    idelay_inc,
    LD0,
    A_rst_primitives,
    CLKB0,
    phaser_ctl_bus,
    \pi_dqs_found_lanes_r1_reg[0] ,
    \pi_dqs_found_lanes_r1_reg[0]_0 ,
    \pi_dqs_found_lanes_r1_reg[0]_1 ,
    \pi_dqs_found_lanes_r1_reg[0]_2 ,
    freq_refclk,
    mem_refclk,
    mem_dqs_in,
    ififo_rst_reg_0,
    sync_pulse,
    PCENABLECALIB,
    COUNTERLOADVAL,
    \po_counter_read_val_reg[8] ,
    \po_counter_read_val_reg[8]_0 ,
    \po_counter_read_val_reg[8]_1 ,
    \my_empty_reg[7] ,
    \my_empty_reg[7]_0 ,
    \my_empty_reg[7]_1 ,
    \my_empty_reg[7]_2 ,
    \my_empty_reg[7]_3 ,
    \my_empty_reg[7]_4 ,
    \my_empty_reg[7]_5 ,
    \my_empty_reg[7]_6 ,
    phy_if_reset,
    my_empty,
    if_empty_r,
    \my_full_reg[1] ,
    my_empty_0,
    \wr_ptr[1]_i_2 ,
    phy_if_empty_r_reg,
    if_empty_v,
    phy_data_wr_en,
    rst_r4,
    out_fifo_0,
    out_fifo_1,
    out_fifo_2,
    phy_dout);
  output out_dqs_4;
  output ts_dqs_4;
  output A_rst_primitives_reg;
  output [8:0]mem_dq_out;
  output [8:0]mem_dq_ts;
  output [0:0]in0;
  output A_rst_primitives_reg_0;
  output [5:0]COUNTERREADVAL;
  output [8:0]A_rst_primitives_reg_1;
  output idelay_ld_rst;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;
  output if_empty;
  output \my_empty_reg[1] ;
  output phy_rddata_en;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ;
  output [63:0]\rd_ptr_reg[3] ;
  output [2:0]Q;
  input \my_full_reg[4] ;
  input \input_[9].iserdes_dq_.iserdesdq ;
  input [7:0]mem_dq_in;
  input idelay_inc;
  input LD0;
  input A_rst_primitives;
  input CLKB0;
  input [3:0]phaser_ctl_bus;
  input \pi_dqs_found_lanes_r1_reg[0] ;
  input \pi_dqs_found_lanes_r1_reg[0]_0 ;
  input \pi_dqs_found_lanes_r1_reg[0]_1 ;
  input \pi_dqs_found_lanes_r1_reg[0]_2 ;
  input freq_refclk;
  input mem_refclk;
  input [0:0]mem_dqs_in;
  input ififo_rst_reg_0;
  input sync_pulse;
  input [1:0]PCENABLECALIB;
  input [5:0]COUNTERLOADVAL;
  input \po_counter_read_val_reg[8] ;
  input \po_counter_read_val_reg[8]_0 ;
  input \po_counter_read_val_reg[8]_1 ;
  input [7:0]\my_empty_reg[7] ;
  input [7:0]\my_empty_reg[7]_0 ;
  input [7:0]\my_empty_reg[7]_1 ;
  input [7:0]\my_empty_reg[7]_2 ;
  input [7:0]\my_empty_reg[7]_3 ;
  input [7:0]\my_empty_reg[7]_4 ;
  input [7:0]\my_empty_reg[7]_5 ;
  input [7:0]\my_empty_reg[7]_6 ;
  input phy_if_reset;
  input [1:0]my_empty;
  input [0:0]if_empty_r;
  input \my_full_reg[1] ;
  input [0:0]my_empty_0;
  input \wr_ptr[1]_i_2 ;
  input phy_if_empty_r_reg;
  input [0:0]if_empty_v;
  input phy_data_wr_en;
  input rst_r4;
  input out_fifo_0;
  input [7:0]out_fifo_1;
  input out_fifo_2;
  input [71:0]phy_dout;

  wire A_rst_primitives;
  wire A_rst_primitives_reg;
  wire A_rst_primitives_reg_0;
  wire [8:0]A_rst_primitives_reg_1;
  wire CLKB0;
  wire [5:0]COUNTERLOADVAL;
  wire [5:0]COUNTERREADVAL;
  wire LD0;
  wire [1:0]PCENABLECALIB;
  wire [2:0]Q;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ;
  wire freq_refclk;
  wire idelay_inc;
  wire idelay_ld_rst;
  wire [3:0]if_d1;
  wire [3:0]if_d2;
  wire [3:0]if_d3;
  wire [3:0]if_d4;
  wire [3:0]if_d5;
  wire [3:0]if_d6;
  wire [3:0]if_d7;
  wire [3:0]if_d9;
  wire if_empty;
  wire if_empty_;
  wire [0:0]if_empty_r;
  wire [3:3]if_empty_r_0;
  wire [0:0]if_empty_v;
  wire ififo_rst;
  wire ififo_rst_reg_0;
  wire ififo_wr_enable;
  wire [0:0]in0;
  wire \in_fifo_gen.in_fifo_n_0 ;
  wire \in_fifo_gen.in_fifo_n_1 ;
  wire \in_fifo_gen.in_fifo_n_3 ;
  wire \input_[9].iserdes_dq_.iserdesdq ;
  wire iserdes_clkdiv;
  wire [7:0]mem_dq_in;
  wire [8:0]mem_dq_out;
  wire [8:0]mem_dq_ts;
  wire [0:0]mem_dqs_in;
  wire mem_refclk;
  wire [1:0]my_empty;
  wire [0:0]my_empty_0;
  wire \my_empty_reg[1] ;
  wire [7:0]\my_empty_reg[7] ;
  wire [7:0]\my_empty_reg[7]_0 ;
  wire [7:0]\my_empty_reg[7]_1 ;
  wire [7:0]\my_empty_reg[7]_2 ;
  wire [7:0]\my_empty_reg[7]_3 ;
  wire [7:0]\my_empty_reg[7]_4 ;
  wire [7:0]\my_empty_reg[7]_5 ;
  wire [7:0]\my_empty_reg[7]_6 ;
  wire \my_full_reg[1] ;
  wire \my_full_reg[4] ;
  wire [7:0]of_d0;
  wire [39:0]of_dqbus;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ;
  wire ofifo_rst;
  wire oserdes_clk;
  wire oserdes_clk_delayed;
  wire oserdes_clkdiv;
  wire [1:0]oserdes_dq_ts;
  wire [1:0]oserdes_dqs;
  wire [1:0]oserdes_dqs_ts;
  wire out_dqs_4;
  wire out_fifo_0;
  wire [7:0]out_fifo_1;
  wire out_fifo_2;
  wire out_fifo_n_0;
  wire out_fifo_n_1;
  wire out_fifo_n_2;
  wire out_fifo_n_3;
  wire [3:0]phaser_ctl_bus;
  wire \phaser_in_gen.phaser_in_n_1 ;
  wire \phaser_in_gen.phaser_in_n_2 ;
  wire \phaser_in_gen.phaser_in_n_5 ;
  wire \phaser_in_gen.phaser_in_n_7 ;
  wire phaser_out_n_0;
  wire phaser_out_n_1;
  wire phy_data_wr_en;
  wire [71:0]phy_dout;
  wire phy_if_empty_r_reg;
  wire phy_if_reset;
  wire phy_rddata_en;
  wire \pi_dqs_found_lanes_r1_reg[0] ;
  wire \pi_dqs_found_lanes_r1_reg[0]_0 ;
  wire \pi_dqs_found_lanes_r1_reg[0]_1 ;
  wire \pi_dqs_found_lanes_r1_reg[0]_2 ;
  wire \po_counter_read_val_reg[8] ;
  wire \po_counter_read_val_reg[8]_0 ;
  wire \po_counter_read_val_reg[8]_1 ;
  wire po_oserdes_rst;
  wire po_rd_enable;
  wire [79:0]rd_data;
  wire [79:6]rd_data_r;
  wire [63:0]\rd_ptr_reg[3] ;
  wire rst_r4;
  wire sync_pulse;
  wire ts_dqs_4;
  wire \wr_ptr[1]_i_2 ;
  wire [7:4]\NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED ;
  wire [7:4]\NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED ;
  wire [7:4]NLW_out_fifo_Q5_UNCONNECTED;
  wire [7:4]NLW_out_fifo_Q6_UNCONNECTED;
  wire NLW_phaser_out_PHASEREFCLK_UNCONNECTED;

  mig_mig_7series_v4_2_ddr_byte_group_io_38 ddr_byte_group_io
       (.A_rst_primitives(A_rst_primitives),
        .CLKB0(CLKB0),
        .CTSBUS(oserdes_dqs_ts[0]),
        .D1(if_d1),
        .D2(if_d2),
        .D3(if_d3),
        .D4(if_d4),
        .D5(if_d5),
        .D6(if_d6),
        .D7(if_d7),
        .D9(if_d9),
        .DQSBUS(oserdes_dqs),
        .DTSBUS(oserdes_dq_ts),
        .LD0(LD0),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (A_rst_primitives_reg),
        .idelay_inc(idelay_inc),
        .idelay_ld_rst(idelay_ld_rst),
        .idelay_ld_rst_reg_0(\my_full_reg[4] ),
        .\input_[9].iserdes_dq_.iserdesdq_0 (\input_[9].iserdes_dq_.iserdesdq ),
        .iserdes_clkdiv(iserdes_clkdiv),
        .mem_dq_in(mem_dq_in),
        .mem_dq_out(mem_dq_out),
        .mem_dq_ts(mem_dq_ts),
        .of_dqbus({of_dqbus[39:36],of_dqbus[31:0]}),
        .oserdes_clk(oserdes_clk),
        .oserdes_clk_delayed(oserdes_clk_delayed),
        .oserdes_clkdiv(oserdes_clkdiv),
        .out_dqs_4(out_dqs_4),
        .po_oserdes_rst(po_oserdes_rst),
        .rst_r4(rst_r4),
        .ts_dqs_4(ts_dqs_4));
  (* syn_maxfan = "3" *) 
  FDRE \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(if_empty_),
        .Q(if_empty_r_0),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[10]),
        .Q(rd_data_r[10]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[11]),
        .Q(rd_data_r[11]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[12]),
        .Q(rd_data_r[12]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[13]),
        .Q(rd_data_r[13]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[14]),
        .Q(rd_data_r[14]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[15]),
        .Q(rd_data_r[15]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[16]),
        .Q(rd_data_r[16]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[17]),
        .Q(rd_data_r[17]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[18]),
        .Q(rd_data_r[18]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[19]),
        .Q(rd_data_r[19]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[20]),
        .Q(rd_data_r[20]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[21]),
        .Q(rd_data_r[21]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[22]),
        .Q(rd_data_r[22]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[23]),
        .Q(rd_data_r[23]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[24]),
        .Q(rd_data_r[24]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[25]),
        .Q(rd_data_r[25]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[26]),
        .Q(rd_data_r[26]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[27]),
        .Q(rd_data_r[27]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[28]),
        .Q(rd_data_r[28]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[29]),
        .Q(rd_data_r[29]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[30]),
        .Q(rd_data_r[30]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[31]),
        .Q(rd_data_r[31]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[32]),
        .Q(rd_data_r[32]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[33]),
        .Q(rd_data_r[33]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[34]),
        .Q(rd_data_r[34]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[35]),
        .Q(rd_data_r[35]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[36]),
        .Q(rd_data_r[36]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[37]),
        .Q(rd_data_r[37]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[38]),
        .Q(rd_data_r[38]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[39]),
        .Q(rd_data_r[39]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[40]),
        .Q(rd_data_r[40]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[41]),
        .Q(rd_data_r[41]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[42]),
        .Q(rd_data_r[42]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[43]),
        .Q(rd_data_r[43]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[44]),
        .Q(rd_data_r[44]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[45]),
        .Q(rd_data_r[45]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[46]),
        .Q(rd_data_r[46]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[47]),
        .Q(rd_data_r[47]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[48]),
        .Q(rd_data_r[48]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[49]),
        .Q(rd_data_r[49]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[50]),
        .Q(rd_data_r[50]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[51]),
        .Q(rd_data_r[51]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[52]),
        .Q(rd_data_r[52]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[53]),
        .Q(rd_data_r[53]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[54]),
        .Q(rd_data_r[54]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[55]),
        .Q(rd_data_r[55]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[56]),
        .Q(rd_data_r[56]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[57]),
        .Q(rd_data_r[57]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[58]),
        .Q(rd_data_r[58]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[59]),
        .Q(rd_data_r[59]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[60]),
        .Q(rd_data_r[60]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[61]),
        .Q(rd_data_r[61]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[62]),
        .Q(rd_data_r[62]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[63]),
        .Q(rd_data_r[63]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[64]),
        .Q(rd_data_r[64]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[65]),
        .Q(rd_data_r[65]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[6] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[6]),
        .Q(rd_data_r[6]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[72]),
        .Q(rd_data_r[72]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[73]),
        .Q(rd_data_r[73]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[74]),
        .Q(rd_data_r[74]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[75]),
        .Q(rd_data_r[75]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[76]),
        .Q(rd_data_r[76]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[77]),
        .Q(rd_data_r[77]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[78]),
        .Q(rd_data_r[78]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[79]),
        .Q(rd_data_r[79]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[7] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[7]),
        .Q(rd_data_r[7]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[8]),
        .Q(rd_data_r[8]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[9]),
        .Q(rd_data_r[9]),
        .R(1'b0));
  mig_mig_7series_v4_2_ddr_if_post_fifo_39 \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo 
       (.Q({rd_data_r[79:72],rd_data_r[65:6]}),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ),
        .if_empty(if_empty),
        .if_empty_r(if_empty_r),
        .if_empty_r_0(if_empty_r_0),
        .if_empty_v(if_empty_v),
        .ififo_rst(ififo_rst),
        .my_empty(my_empty),
        .my_empty_0(my_empty_0),
        .\my_full_reg[1]_0 (\my_full_reg[1] ),
        .phy_if_empty_r_reg(phy_if_empty_r_reg),
        .phy_rddata_en(phy_rddata_en),
        .\rd_ptr_timing_reg[1]_0 (\my_full_reg[4] ),
        .\wr_ptr[1]_i_2 (\wr_ptr[1]_i_2 ));
  FDSE #(
    .INIT(1'b1)) 
    ififo_rst_reg
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(ififo_rst_reg_0),
        .Q(ififo_rst),
        .S(phy_if_reset));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IN_FIFO #(
    .ALMOST_EMPTY_VALUE(1),
    .ALMOST_FULL_VALUE(1),
    .ARRAY_MODE("ARRAY_MODE_4_X_8"),
    .SYNCHRONOUS_MODE("FALSE")) 
    \in_fifo_gen.in_fifo 
       (.ALMOSTEMPTY(\in_fifo_gen.in_fifo_n_0 ),
        .ALMOSTFULL(\in_fifo_gen.in_fifo_n_1 ),
        .D0({1'b0,1'b0,1'b0,1'b0}),
        .D1(if_d1),
        .D2(if_d2),
        .D3(if_d3),
        .D4(if_d4),
        .D5({\NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED [7:4],if_d5}),
        .D6({\NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED [7:4],if_d6}),
        .D7(if_d7),
        .D8({1'b0,1'b0,1'b0,1'b0}),
        .D9(if_d9),
        .EMPTY(if_empty_),
        .FULL(\in_fifo_gen.in_fifo_n_3 ),
        .Q0(rd_data[7:0]),
        .Q1(rd_data[15:8]),
        .Q2(rd_data[23:16]),
        .Q3(rd_data[31:24]),
        .Q4(rd_data[39:32]),
        .Q5(rd_data[47:40]),
        .Q6(rd_data[55:48]),
        .Q7(rd_data[63:56]),
        .Q8(rd_data[71:64]),
        .Q9(rd_data[79:72]),
        .RDCLK(\my_full_reg[4] ),
        .RDEN(1'b1),
        .RESET(ififo_rst),
        .WRCLK(iserdes_clkdiv),
        .WREN(ififo_wr_enable));
  mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_40 \of_pre_fifo_gen.u_ddr_of_pre_fifo 
       (.D0(of_d0),
        .D8({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 }),
        .Q(Q),
        .\my_empty_reg[1]_0 (\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ),
        .\my_empty_reg[1]_1 (\my_empty_reg[1] ),
        .\my_empty_reg[7]_0 (out_fifo_n_3),
        .\my_full_reg[4]_0 (\my_full_reg[4] ),
        .ofifo_rst(ofifo_rst),
        .out_fifo(out_fifo_0),
        .out_fifo_0(out_fifo_1),
        .out_fifo_1(out_fifo_2),
        .phy_data_wr_en(phy_data_wr_en),
        .phy_dout(phy_dout),
        .\rd_ptr_reg[3]_0 (\rd_ptr_reg[3] ));
  FDSE #(
    .INIT(1'b1)) 
    ofifo_rst_reg
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(ififo_rst_reg_0),
        .Q(ofifo_rst),
        .S(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OUT_FIFO #(
    .ALMOST_EMPTY_VALUE(1),
    .ALMOST_FULL_VALUE(1),
    .ARRAY_MODE("ARRAY_MODE_8_X_4"),
    .OUTPUT_DISABLE("FALSE"),
    .SYNCHRONOUS_MODE("FALSE")) 
    out_fifo
       (.ALMOSTEMPTY(out_fifo_n_0),
        .ALMOSTFULL(out_fifo_n_1),
        .D0(of_d0),
        .D1(\my_empty_reg[7] ),
        .D2(\my_empty_reg[7]_0 ),
        .D3(\my_empty_reg[7]_1 ),
        .D4(\my_empty_reg[7]_2 ),
        .D5(\my_empty_reg[7]_3 ),
        .D6(\my_empty_reg[7]_4 ),
        .D7(\my_empty_reg[7]_5 ),
        .D8({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 }),
        .D9(\my_empty_reg[7]_6 ),
        .EMPTY(out_fifo_n_2),
        .FULL(out_fifo_n_3),
        .Q0(of_dqbus[3:0]),
        .Q1(of_dqbus[7:4]),
        .Q2(of_dqbus[11:8]),
        .Q3(of_dqbus[15:12]),
        .Q4(of_dqbus[19:16]),
        .Q5({NLW_out_fifo_Q5_UNCONNECTED[7:4],of_dqbus[23:20]}),
        .Q6({NLW_out_fifo_Q6_UNCONNECTED[7:4],of_dqbus[27:24]}),
        .Q7(of_dqbus[31:28]),
        .Q8(of_dqbus[35:32]),
        .Q9(of_dqbus[39:36]),
        .RDCLK(oserdes_clkdiv),
        .RDEN(po_rd_enable),
        .RESET(ofifo_rst),
        .WRCLK(\my_full_reg[4] ),
        .WREN(\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  PHASER_IN_PHY #(
    .BURST_MODE("TRUE"),
    .CLKOUT_DIV(2),
    .DQS_AUTO_RECAL(1'b1),
    .DQS_BIAS_MODE("FALSE"),
    .DQS_FIND_PATTERN(3'b000),
    .FINE_DELAY(33),
    .FREQ_REF_DIV("DIV2"),
    .IS_RST_INVERTED(1'b0),
    .MEMREFCLK_PERIOD(2.500000),
    .OUTPUT_CLK_SRC("DELAYED_REF"),
    .PHASEREFCLK_PERIOD(2.500000),
    .REFCLK_PERIOD(1.250000),
    .SEL_CLK_OFFSET(6),
    .SYNC_IN_DIV_RST("TRUE"),
    .WR_CYCLES("FALSE")) 
    \phaser_in_gen.phaser_in 
       (.BURSTPENDINGPHY(phaser_ctl_bus[1]),
        .COUNTERLOADEN(\pi_dqs_found_lanes_r1_reg[0] ),
        .COUNTERLOADVAL(COUNTERLOADVAL),
        .COUNTERREADEN(\pi_dqs_found_lanes_r1_reg[0]_0 ),
        .COUNTERREADVAL(COUNTERREADVAL),
        .DQSFOUND(in0),
        .DQSOUTOFRANGE(\phaser_in_gen.phaser_in_n_1 ),
        .ENCALIBPHY(PCENABLECALIB),
        .FINEENABLE(\pi_dqs_found_lanes_r1_reg[0]_1 ),
        .FINEINC(\pi_dqs_found_lanes_r1_reg[0]_2 ),
        .FINEOVERFLOW(\phaser_in_gen.phaser_in_n_2 ),
        .FREQREFCLK(freq_refclk),
        .ICLK(A_rst_primitives_reg),
        .ICLKDIV(iserdes_clkdiv),
        .ISERDESRST(\phaser_in_gen.phaser_in_n_5 ),
        .MEMREFCLK(mem_refclk),
        .PHASELOCKED(A_rst_primitives_reg_0),
        .PHASEREFCLK(mem_dqs_in),
        .RANKSELPHY(phaser_ctl_bus[3:2]),
        .RCLK(\phaser_in_gen.phaser_in_n_7 ),
        .RST(A_rst_primitives),
        .RSTDQSFIND(ififo_rst_reg_0),
        .SYNCIN(sync_pulse),
        .SYSCLK(\my_full_reg[4] ),
        .WRENABLE(ififo_wr_enable));
  (* BOX_TYPE = "PRIMITIVE" *) 
  PHASER_OUT_PHY #(
    .CLKOUT_DIV(2),
    .COARSE_BYPASS("FALSE"),
    .COARSE_DELAY(0),
    .DATA_CTL_N("TRUE"),
    .DATA_RD_CYCLES("FALSE"),
    .FINE_DELAY(60),
    .IS_RST_INVERTED(1'b0),
    .MEMREFCLK_PERIOD(2.500000),
    .OCLKDELAY_INV("FALSE"),
    .OCLK_DELAY(0),
    .OUTPUT_CLK_SRC("DELAYED_REF"),
    .PHASEREFCLK_PERIOD(1.000000),
    .PO(3'b111),
    .REFCLK_PERIOD(1.250000),
    .SYNC_IN_DIV_RST("TRUE")) 
    phaser_out
       (.BURSTPENDINGPHY(phaser_ctl_bus[0]),
        .COARSEENABLE(\po_counter_read_val_reg[8] ),
        .COARSEINC(\po_counter_read_val_reg[8] ),
        .COARSEOVERFLOW(phaser_out_n_0),
        .COUNTERLOADEN(1'b0),
        .COUNTERLOADVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .COUNTERREADEN(\pi_dqs_found_lanes_r1_reg[0]_0 ),
        .COUNTERREADVAL(A_rst_primitives_reg_1),
        .CTSBUS(oserdes_dqs_ts),
        .DQSBUS(oserdes_dqs),
        .DTSBUS(oserdes_dq_ts),
        .ENCALIBPHY(PCENABLECALIB),
        .FINEENABLE(\po_counter_read_val_reg[8]_0 ),
        .FINEINC(\po_counter_read_val_reg[8]_1 ),
        .FINEOVERFLOW(phaser_out_n_1),
        .FREQREFCLK(freq_refclk),
        .MEMREFCLK(mem_refclk),
        .OCLK(oserdes_clk),
        .OCLKDELAYED(oserdes_clk_delayed),
        .OCLKDIV(oserdes_clkdiv),
        .OSERDESRST(po_oserdes_rst),
        .PHASEREFCLK(NLW_phaser_out_PHASEREFCLK_UNCONNECTED),
        .RDENABLE(po_rd_enable),
        .RST(A_rst_primitives),
        .SELFINEOCLKDELAY(1'b0),
        .SYNCIN(sync_pulse),
        .SYSCLK(\my_full_reg[4] ));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_byte_lane" *) 
module mig_mig_7series_v4_2_ddr_byte_lane__parameterized0
   (out_dqs_1,
    ts_dqs_1,
    A_rst_primitives_reg,
    mem_dq_out,
    mem_dq_ts,
    in0,
    A_rst_primitives_reg_0,
    B_rclk,
    if_empty_r,
    \my_empty_reg[4] ,
    idelay_ld_rst_4,
    \my_empty_reg[1] ,
    \rd_mux_sel_r_reg[0] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ,
    \rd_mux_sel_r_reg[0]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ,
    \rd_mux_sel_r_reg[0]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ,
    \rd_mux_sel_r_reg[0]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ,
    \rd_mux_sel_r_reg[0]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ,
    \rd_mux_sel_r_reg[0]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ,
    \rd_mux_sel_r_reg[0]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ,
    \rd_mux_sel_r_reg[0]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ,
    \rd_mux_sel_r_reg[0]_7 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ,
    \rd_mux_sel_r_reg[0]_8 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ,
    \rd_mux_sel_r_reg[0]_9 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ,
    \rd_mux_sel_r_reg[0]_10 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ,
    \rd_mux_sel_r_reg[0]_11 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ,
    \rd_mux_sel_r_reg[0]_12 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ,
    \rd_mux_sel_r_reg[0]_13 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ,
    \rd_mux_sel_r_reg[0]_14 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 ,
    \rd_mux_sel_r_reg[0]_15 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ,
    \rd_mux_sel_r_reg[0]_16 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ,
    \rd_mux_sel_r_reg[0]_17 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ,
    \rd_mux_sel_r_reg[0]_18 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ,
    \rd_mux_sel_r_reg[0]_19 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ,
    \rd_mux_sel_r_reg[0]_20 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ,
    \rd_mux_sel_r_reg[0]_21 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ,
    \rd_mux_sel_r_reg[0]_22 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 ,
    \rd_mux_sel_r_reg[0]_23 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ,
    \rd_mux_sel_r_reg[0]_24 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ,
    \rd_mux_sel_r_reg[0]_25 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ,
    \rd_mux_sel_r_reg[0]_26 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ,
    \rd_mux_sel_r_reg[0]_27 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ,
    \rd_mux_sel_r_reg[0]_28 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ,
    \rd_mux_sel_r_reg[0]_29 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ,
    \rd_mux_sel_r_reg[0]_30 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 ,
    \rd_mux_sel_r_reg[0]_31 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ,
    \rd_mux_sel_r_reg[0]_32 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ,
    \rd_mux_sel_r_reg[0]_33 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ,
    \rd_mux_sel_r_reg[0]_34 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ,
    \rd_mux_sel_r_reg[0]_35 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ,
    \rd_mux_sel_r_reg[0]_36 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ,
    \rd_mux_sel_r_reg[0]_37 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ,
    \rd_mux_sel_r_reg[0]_38 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 ,
    \rd_mux_sel_r_reg[0]_39 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ,
    \rd_mux_sel_r_reg[0]_40 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ,
    \rd_mux_sel_r_reg[0]_41 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ,
    \rd_mux_sel_r_reg[0]_42 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ,
    \rd_mux_sel_r_reg[0]_43 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ,
    \rd_mux_sel_r_reg[0]_44 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ,
    \rd_mux_sel_r_reg[0]_45 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ,
    \rd_mux_sel_r_reg[0]_46 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 ,
    \rd_mux_sel_r_reg[0]_47 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ,
    \rd_mux_sel_r_reg[0]_48 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ,
    \rd_mux_sel_r_reg[0]_49 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ,
    \rd_mux_sel_r_reg[0]_50 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ,
    \rd_mux_sel_r_reg[0]_51 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ,
    \rd_mux_sel_r_reg[0]_52 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ,
    \rd_mux_sel_r_reg[0]_53 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ,
    \rd_mux_sel_r_reg[0]_54 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 ,
    \rd_mux_sel_r_reg[0]_55 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ,
    \rd_mux_sel_r_reg[0]_56 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ,
    \rd_mux_sel_r_reg[0]_57 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ,
    \rd_mux_sel_r_reg[0]_58 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ,
    \rd_mux_sel_r_reg[0]_59 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ,
    \rd_mux_sel_r_reg[0]_60 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ,
    \rd_mux_sel_r_reg[0]_61 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ,
    \rd_mux_sel_r_reg[0]_62 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ,
    \rd_ptr_reg[3] ,
    D,
    \calib_sel_reg[1] ,
    Q,
    \entry_cnt_reg[4] ,
    \input_[9].iserdes_dq_.iserdesdq ,
    mem_dq_in,
    idelay_inc,
    LD0_11,
    A_rst_primitives,
    CLKB0_11,
    phaser_ctl_bus,
    \pi_dqs_found_lanes_r1_reg[9] ,
    \pi_dqs_found_lanes_r1_reg[9]_0 ,
    \pi_dqs_found_lanes_r1_reg[9]_1 ,
    \pi_dqs_found_lanes_r1_reg[9]_2 ,
    freq_refclk,
    mem_refclk,
    mem_dqs_in,
    ififo_rst_reg_0,
    sync_pulse,
    PCENABLECALIB,
    \pi_dqs_found_lanes_r1_reg[9]_3 ,
    \po_counter_read_val_reg[8] ,
    \po_counter_read_val_reg[8]_0 ,
    \po_counter_read_val_reg[8]_1 ,
    \my_empty_reg[7] ,
    \my_empty_reg[7]_0 ,
    \my_empty_reg[7]_1 ,
    \my_empty_reg[7]_2 ,
    \my_empty_reg[7]_3 ,
    \my_empty_reg[7]_4 ,
    \my_empty_reg[7]_5 ,
    \my_empty_reg[7]_6 ,
    phy_if_reset,
    \my_full_reg[1] ,
    phy_data_wr_en,
    rst_r4,
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0] ,
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ,
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1 ,
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_2 ,
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1 ,
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2] ,
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ,
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1 ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 ,
    \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ,
    \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0 ,
    \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_1 ,
    \gen_mux_rd[5].mux_rd_rise0_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_1 ,
    \gen_mux_rd[6].mux_rd_rise0_r_reg[6] ,
    \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0 ,
    \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_1 ,
    \gen_mux_rd[7].mux_rd_rise0_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_1 ,
    \gen_mux_rd[0].mux_rd_fall0_r_reg[0] ,
    \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0 ,
    \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_1 ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 ,
    \gen_mux_rd[2].mux_rd_fall0_r_reg[2] ,
    \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0 ,
    \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_1 ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 ,
    \gen_mux_rd[4].mux_rd_fall0_r_reg[4] ,
    \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0 ,
    \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_1 ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 ,
    \gen_mux_rd[6].mux_rd_fall0_r_reg[6] ,
    \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0 ,
    \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_1 ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 ,
    \gen_mux_rd[0].mux_rd_rise1_r_reg[0] ,
    \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0 ,
    \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_1 ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 ,
    \gen_mux_rd[2].mux_rd_rise1_r_reg[2] ,
    \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0 ,
    \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_1 ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 ,
    \gen_mux_rd[4].mux_rd_rise1_r_reg[4] ,
    \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0 ,
    \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_1 ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 ,
    \gen_mux_rd[6].mux_rd_rise1_r_reg[6] ,
    \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0 ,
    \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_1 ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 ,
    \gen_mux_rd[0].mux_rd_fall1_r_reg[0] ,
    \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0 ,
    \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_1 ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 ,
    \gen_mux_rd[2].mux_rd_fall1_r_reg[2] ,
    \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0 ,
    \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_1 ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 ,
    \gen_mux_rd[4].mux_rd_fall1_r_reg[4] ,
    \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0 ,
    \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_1 ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 ,
    \gen_mux_rd[6].mux_rd_fall1_r_reg[6] ,
    \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0 ,
    \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_1 ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 ,
    \gen_mux_rd[0].mux_rd_rise2_r_reg[0] ,
    \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0 ,
    \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_1 ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 ,
    \gen_mux_rd[2].mux_rd_rise2_r_reg[2] ,
    \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0 ,
    \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_1 ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 ,
    \gen_mux_rd[4].mux_rd_rise2_r_reg[4] ,
    \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0 ,
    \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_1 ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 ,
    \gen_mux_rd[6].mux_rd_rise2_r_reg[6] ,
    \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0 ,
    \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_1 ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 ,
    \gen_mux_rd[0].mux_rd_fall2_r_reg[0] ,
    \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0 ,
    \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_1 ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 ,
    \gen_mux_rd[2].mux_rd_fall2_r_reg[2] ,
    \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0 ,
    \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_1 ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 ,
    \gen_mux_rd[4].mux_rd_fall2_r_reg[4] ,
    \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0 ,
    \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_1 ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 ,
    \gen_mux_rd[6].mux_rd_fall2_r_reg[6] ,
    \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0 ,
    \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_1 ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 ,
    \gen_mux_rd[0].mux_rd_rise3_r_reg[0] ,
    \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0 ,
    \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_1 ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 ,
    \gen_mux_rd[2].mux_rd_rise3_r_reg[2] ,
    \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0 ,
    \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_1 ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 ,
    \gen_mux_rd[4].mux_rd_rise3_r_reg[4] ,
    \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0 ,
    \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_1 ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 ,
    \gen_mux_rd[6].mux_rd_rise3_r_reg[6] ,
    \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0 ,
    \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_1 ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 ,
    \gen_mux_rd[0].mux_rd_fall3_r_reg[0] ,
    \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0 ,
    \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_1 ,
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1 ,
    \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ,
    \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 ,
    \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_1 ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 ,
    \gen_mux_rd[4].mux_rd_fall3_r_reg[4] ,
    \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0 ,
    \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_1 ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 ,
    \gen_mux_rd[6].mux_rd_fall3_r_reg[6] ,
    \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0 ,
    \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_1 ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 ,
    out_fifo_0,
    out_fifo_1,
    out_fifo_2,
    out_fifo_i_75__1,
    COUNTERREADVAL,
    \pi_counter_read_val_reg[5] ,
    calib_sel,
    \pi_counter_read_val_reg[5]_0 ,
    \po_counter_read_val_reg[8]_2 ,
    \po_counter_read_val_reg[8]_3 ,
    \po_counter_read_val_reg[8]_4 );
  output out_dqs_1;
  output ts_dqs_1;
  output A_rst_primitives_reg;
  output [8:0]mem_dq_out;
  output [8:0]mem_dq_ts;
  output [0:0]in0;
  output A_rst_primitives_reg_0;
  output B_rclk;
  output [0:0]if_empty_r;
  output [1:0]\my_empty_reg[4] ;
  output idelay_ld_rst_4;
  output \my_empty_reg[1] ;
  output \rd_mux_sel_r_reg[0] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ;
  output \rd_mux_sel_r_reg[0]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;
  output \rd_mux_sel_r_reg[0]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ;
  output \rd_mux_sel_r_reg[0]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ;
  output \rd_mux_sel_r_reg[0]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ;
  output \rd_mux_sel_r_reg[0]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ;
  output \rd_mux_sel_r_reg[0]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ;
  output \rd_mux_sel_r_reg[0]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ;
  output \rd_mux_sel_r_reg[0]_7 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ;
  output \rd_mux_sel_r_reg[0]_8 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ;
  output \rd_mux_sel_r_reg[0]_9 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ;
  output \rd_mux_sel_r_reg[0]_10 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ;
  output \rd_mux_sel_r_reg[0]_11 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ;
  output \rd_mux_sel_r_reg[0]_12 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ;
  output \rd_mux_sel_r_reg[0]_13 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ;
  output \rd_mux_sel_r_reg[0]_14 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 ;
  output \rd_mux_sel_r_reg[0]_15 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ;
  output \rd_mux_sel_r_reg[0]_16 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ;
  output \rd_mux_sel_r_reg[0]_17 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ;
  output \rd_mux_sel_r_reg[0]_18 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ;
  output \rd_mux_sel_r_reg[0]_19 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ;
  output \rd_mux_sel_r_reg[0]_20 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ;
  output \rd_mux_sel_r_reg[0]_21 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ;
  output \rd_mux_sel_r_reg[0]_22 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 ;
  output \rd_mux_sel_r_reg[0]_23 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ;
  output \rd_mux_sel_r_reg[0]_24 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ;
  output \rd_mux_sel_r_reg[0]_25 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ;
  output \rd_mux_sel_r_reg[0]_26 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ;
  output \rd_mux_sel_r_reg[0]_27 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ;
  output \rd_mux_sel_r_reg[0]_28 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ;
  output \rd_mux_sel_r_reg[0]_29 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ;
  output \rd_mux_sel_r_reg[0]_30 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 ;
  output \rd_mux_sel_r_reg[0]_31 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ;
  output \rd_mux_sel_r_reg[0]_32 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ;
  output \rd_mux_sel_r_reg[0]_33 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ;
  output \rd_mux_sel_r_reg[0]_34 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ;
  output \rd_mux_sel_r_reg[0]_35 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ;
  output \rd_mux_sel_r_reg[0]_36 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ;
  output \rd_mux_sel_r_reg[0]_37 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ;
  output \rd_mux_sel_r_reg[0]_38 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 ;
  output \rd_mux_sel_r_reg[0]_39 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ;
  output \rd_mux_sel_r_reg[0]_40 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ;
  output \rd_mux_sel_r_reg[0]_41 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ;
  output \rd_mux_sel_r_reg[0]_42 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ;
  output \rd_mux_sel_r_reg[0]_43 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ;
  output \rd_mux_sel_r_reg[0]_44 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ;
  output \rd_mux_sel_r_reg[0]_45 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ;
  output \rd_mux_sel_r_reg[0]_46 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 ;
  output \rd_mux_sel_r_reg[0]_47 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ;
  output \rd_mux_sel_r_reg[0]_48 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ;
  output \rd_mux_sel_r_reg[0]_49 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ;
  output \rd_mux_sel_r_reg[0]_50 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ;
  output \rd_mux_sel_r_reg[0]_51 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ;
  output \rd_mux_sel_r_reg[0]_52 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ;
  output \rd_mux_sel_r_reg[0]_53 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ;
  output \rd_mux_sel_r_reg[0]_54 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 ;
  output \rd_mux_sel_r_reg[0]_55 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ;
  output \rd_mux_sel_r_reg[0]_56 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ;
  output \rd_mux_sel_r_reg[0]_57 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ;
  output \rd_mux_sel_r_reg[0]_58 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ;
  output \rd_mux_sel_r_reg[0]_59 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ;
  output \rd_mux_sel_r_reg[0]_60 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ;
  output \rd_mux_sel_r_reg[0]_61 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ;
  output \rd_mux_sel_r_reg[0]_62 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  output [63:0]\rd_ptr_reg[3] ;
  output [5:0]D;
  output [8:0]\calib_sel_reg[1] ;
  output [2:0]Q;
  input \entry_cnt_reg[4] ;
  input \input_[9].iserdes_dq_.iserdesdq ;
  input [7:0]mem_dq_in;
  input idelay_inc;
  input LD0_11;
  input A_rst_primitives;
  input CLKB0_11;
  input [3:0]phaser_ctl_bus;
  input \pi_dqs_found_lanes_r1_reg[9] ;
  input \pi_dqs_found_lanes_r1_reg[9]_0 ;
  input \pi_dqs_found_lanes_r1_reg[9]_1 ;
  input \pi_dqs_found_lanes_r1_reg[9]_2 ;
  input freq_refclk;
  input mem_refclk;
  input [0:0]mem_dqs_in;
  input ififo_rst_reg_0;
  input sync_pulse;
  input [1:0]PCENABLECALIB;
  input [5:0]\pi_dqs_found_lanes_r1_reg[9]_3 ;
  input \po_counter_read_val_reg[8] ;
  input \po_counter_read_val_reg[8]_0 ;
  input \po_counter_read_val_reg[8]_1 ;
  input [7:0]\my_empty_reg[7] ;
  input [7:0]\my_empty_reg[7]_0 ;
  input [7:0]\my_empty_reg[7]_1 ;
  input [7:0]\my_empty_reg[7]_2 ;
  input [7:0]\my_empty_reg[7]_3 ;
  input [7:0]\my_empty_reg[7]_4 ;
  input [7:0]\my_empty_reg[7]_5 ;
  input [7:0]\my_empty_reg[7]_6 ;
  input phy_if_reset;
  input \my_full_reg[1] ;
  input phy_data_wr_en;
  input rst_r4;
  input [1:0]\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;
  input \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ;
  input \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1 ;
  input \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_2 ;
  input \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;
  input \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ;
  input \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1 ;
  input \gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;
  input \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ;
  input \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1 ;
  input \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  input \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ;
  input \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 ;
  input \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;
  input \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0 ;
  input \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_1 ;
  input \gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;
  input \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0 ;
  input \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_1 ;
  input \gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;
  input \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0 ;
  input \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_1 ;
  input \gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;
  input \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0 ;
  input \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_1 ;
  input \gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;
  input \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0 ;
  input \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_1 ;
  input \gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  input \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ;
  input \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 ;
  input \gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;
  input \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0 ;
  input \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_1 ;
  input \gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  input \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ;
  input \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 ;
  input \gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;
  input \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0 ;
  input \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_1 ;
  input \gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  input \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ;
  input \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 ;
  input \gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;
  input \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0 ;
  input \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_1 ;
  input \gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  input \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ;
  input \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 ;
  input \gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;
  input \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0 ;
  input \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_1 ;
  input \gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  input \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ;
  input \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 ;
  input \gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;
  input \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0 ;
  input \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_1 ;
  input \gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  input \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ;
  input \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 ;
  input \gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;
  input \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0 ;
  input \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_1 ;
  input \gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  input \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ;
  input \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 ;
  input \gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;
  input \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0 ;
  input \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_1 ;
  input \gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  input \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ;
  input \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 ;
  input \gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;
  input \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0 ;
  input \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_1 ;
  input \gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  input \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ;
  input \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 ;
  input \gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;
  input \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0 ;
  input \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_1 ;
  input \gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  input \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ;
  input \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 ;
  input \gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;
  input \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0 ;
  input \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_1 ;
  input \gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  input \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ;
  input \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 ;
  input \gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;
  input \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0 ;
  input \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_1 ;
  input \gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  input \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ;
  input \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 ;
  input \gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;
  input \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0 ;
  input \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_1 ;
  input \gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  input \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ;
  input \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 ;
  input \gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;
  input \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0 ;
  input \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_1 ;
  input \gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  input \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ;
  input \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 ;
  input \gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;
  input \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0 ;
  input \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_1 ;
  input \gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  input \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ;
  input \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 ;
  input \gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;
  input \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0 ;
  input \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_1 ;
  input \gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  input \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ;
  input \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 ;
  input \gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;
  input \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0 ;
  input \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_1 ;
  input \gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  input \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ;
  input \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 ;
  input \gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;
  input \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0 ;
  input \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_1 ;
  input \gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  input \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ;
  input \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 ;
  input \gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;
  input \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0 ;
  input \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_1 ;
  input \gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  input \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ;
  input \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 ;
  input \gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;
  input \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0 ;
  input \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_1 ;
  input \gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  input \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ;
  input \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 ;
  input \gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;
  input \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0 ;
  input \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_1 ;
  input \gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  input \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ;
  input \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 ;
  input \gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;
  input \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0 ;
  input \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_1 ;
  input \gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  input \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ;
  input \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 ;
  input \gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;
  input \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0 ;
  input \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_1 ;
  input \gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  input \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ;
  input \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 ;
  input \gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;
  input \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0 ;
  input \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_1 ;
  input \gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  input \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ;
  input \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 ;
  input \gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;
  input \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0 ;
  input \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_1 ;
  input \gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  input \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ;
  input \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1 ;
  input \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  input \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 ;
  input \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_1 ;
  input \gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  input \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ;
  input \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 ;
  input \gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;
  input \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0 ;
  input \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_1 ;
  input \gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  input \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ;
  input \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 ;
  input \gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;
  input \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0 ;
  input \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_1 ;
  input \gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  input \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ;
  input \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 ;
  input out_fifo_0;
  input [7:0]out_fifo_1;
  input out_fifo_2;
  input [71:0]out_fifo_i_75__1;
  input [5:0]COUNTERREADVAL;
  input [5:0]\pi_counter_read_val_reg[5] ;
  input [1:0]calib_sel;
  input [5:0]\pi_counter_read_val_reg[5]_0 ;
  input [8:0]\po_counter_read_val_reg[8]_2 ;
  input [8:0]\po_counter_read_val_reg[8]_3 ;
  input [8:0]\po_counter_read_val_reg[8]_4 ;

  wire A_rst_primitives;
  wire A_rst_primitives_reg;
  wire A_rst_primitives_reg_0;
  wire [5:0]B_pi_counter_read_val;
  wire [8:0]B_po_counter_read_val;
  wire B_rclk;
  wire CLKB0_11;
  wire [5:0]COUNTERREADVAL;
  wire [5:0]D;
  wire LD0_11;
  wire [1:0]PCENABLECALIB;
  wire [2:0]Q;
  wire [1:0]calib_sel;
  wire [8:0]\calib_sel_reg[1] ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ;
  wire \entry_cnt_reg[4] ;
  wire freq_refclk;
  wire \gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0 ;
  wire \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_1 ;
  wire \gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0 ;
  wire \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_1 ;
  wire \gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0 ;
  wire \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_1 ;
  wire \gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0 ;
  wire \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_1 ;
  wire [1:0]\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ;
  wire \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1 ;
  wire \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_2 ;
  wire \gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0 ;
  wire \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_1 ;
  wire \gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0 ;
  wire \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_1 ;
  wire \gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0 ;
  wire \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_1 ;
  wire \gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 ;
  wire \gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 ;
  wire \gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 ;
  wire \gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1 ;
  wire \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1 ;
  wire \gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 ;
  wire \gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 ;
  wire \gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 ;
  wire \gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0 ;
  wire \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_1 ;
  wire \gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0 ;
  wire \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_1 ;
  wire \gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0 ;
  wire \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_1 ;
  wire \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 ;
  wire \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_1 ;
  wire \gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ;
  wire \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1 ;
  wire \gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0 ;
  wire \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_1 ;
  wire \gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0 ;
  wire \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_1 ;
  wire \gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0 ;
  wire \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_1 ;
  wire \gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 ;
  wire \gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 ;
  wire \gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 ;
  wire \gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 ;
  wire \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 ;
  wire \gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 ;
  wire \gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 ;
  wire \gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 ;
  wire \gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0 ;
  wire \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_1 ;
  wire \gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0 ;
  wire \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_1 ;
  wire \gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0 ;
  wire \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_1 ;
  wire \gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0 ;
  wire \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_1 ;
  wire \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0 ;
  wire \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_1 ;
  wire \gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0 ;
  wire \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_1 ;
  wire \gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0 ;
  wire \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_1 ;
  wire \gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0 ;
  wire \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_1 ;
  wire \gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 ;
  wire \gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 ;
  wire \gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 ;
  wire \gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 ;
  wire \gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_1 ;
  wire \gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 ;
  wire \gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 ;
  wire \gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 ;
  wire \gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0 ;
  wire \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_1 ;
  wire \gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0 ;
  wire \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_1 ;
  wire \gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0 ;
  wire \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_1 ;
  wire \gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0 ;
  wire \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_1 ;
  wire \gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0 ;
  wire \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_1 ;
  wire \gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0 ;
  wire \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_1 ;
  wire \gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0 ;
  wire \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_1 ;
  wire \gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0 ;
  wire \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_1 ;
  wire \gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 ;
  wire \gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 ;
  wire \gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 ;
  wire \gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 ;
  wire \gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_1 ;
  wire \gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 ;
  wire \gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 ;
  wire \gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 ;
  wire idelay_inc;
  wire idelay_ld_rst_4;
  wire [3:0]if_d2;
  wire [3:0]if_d3;
  wire [3:0]if_d4;
  wire [3:0]if_d5;
  wire [3:0]if_d6;
  wire [3:0]if_d7;
  wire [3:0]if_d8;
  wire [3:0]if_d9;
  wire if_empty_;
  wire [0:0]if_empty_r;
  wire ififo_rst;
  wire ififo_rst_reg_0;
  wire ififo_wr_enable;
  wire [0:0]in0;
  wire \in_fifo_gen.in_fifo_n_0 ;
  wire \in_fifo_gen.in_fifo_n_1 ;
  wire \in_fifo_gen.in_fifo_n_3 ;
  wire \input_[9].iserdes_dq_.iserdesdq ;
  wire iserdes_clkdiv;
  wire [7:0]mem_dq_in;
  wire [8:0]mem_dq_out;
  wire [8:0]mem_dq_ts;
  wire [0:0]mem_dqs_in;
  wire mem_refclk;
  wire \my_empty_reg[1] ;
  wire [1:0]\my_empty_reg[4] ;
  wire [7:0]\my_empty_reg[7] ;
  wire [7:0]\my_empty_reg[7]_0 ;
  wire [7:0]\my_empty_reg[7]_1 ;
  wire [7:0]\my_empty_reg[7]_2 ;
  wire [7:0]\my_empty_reg[7]_3 ;
  wire [7:0]\my_empty_reg[7]_4 ;
  wire [7:0]\my_empty_reg[7]_5 ;
  wire [7:0]\my_empty_reg[7]_6 ;
  wire \my_full_reg[1] ;
  wire [7:0]of_d1;
  wire [39:0]of_dqbus;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ;
  wire ofifo_rst;
  wire oserdes_clk;
  wire oserdes_clk_delayed;
  wire oserdes_clkdiv;
  wire [1:0]oserdes_dq_ts;
  wire [1:0]oserdes_dqs;
  wire [1:0]oserdes_dqs_ts;
  wire out_dqs_1;
  wire out_fifo_0;
  wire [7:0]out_fifo_1;
  wire out_fifo_2;
  wire [71:0]out_fifo_i_75__1;
  wire out_fifo_n_0;
  wire out_fifo_n_1;
  wire out_fifo_n_2;
  wire out_fifo_n_3;
  wire [3:0]phaser_ctl_bus;
  wire \phaser_in_gen.phaser_in_n_1 ;
  wire \phaser_in_gen.phaser_in_n_2 ;
  wire \phaser_in_gen.phaser_in_n_5 ;
  wire phaser_out_n_0;
  wire phaser_out_n_1;
  wire phy_data_wr_en;
  wire phy_if_reset;
  wire [5:0]\pi_counter_read_val_reg[5] ;
  wire [5:0]\pi_counter_read_val_reg[5]_0 ;
  wire \pi_dqs_found_lanes_r1_reg[9] ;
  wire \pi_dqs_found_lanes_r1_reg[9]_0 ;
  wire \pi_dqs_found_lanes_r1_reg[9]_1 ;
  wire \pi_dqs_found_lanes_r1_reg[9]_2 ;
  wire [5:0]\pi_dqs_found_lanes_r1_reg[9]_3 ;
  wire \po_counter_read_val_reg[8] ;
  wire \po_counter_read_val_reg[8]_0 ;
  wire \po_counter_read_val_reg[8]_1 ;
  wire [8:0]\po_counter_read_val_reg[8]_2 ;
  wire [8:0]\po_counter_read_val_reg[8]_3 ;
  wire [8:0]\po_counter_read_val_reg[8]_4 ;
  wire po_oserdes_rst;
  wire po_rd_enable;
  wire [79:0]rd_data;
  wire [79:12]rd_data_r;
  wire \rd_mux_sel_r_reg[0] ;
  wire \rd_mux_sel_r_reg[0]_0 ;
  wire \rd_mux_sel_r_reg[0]_1 ;
  wire \rd_mux_sel_r_reg[0]_10 ;
  wire \rd_mux_sel_r_reg[0]_11 ;
  wire \rd_mux_sel_r_reg[0]_12 ;
  wire \rd_mux_sel_r_reg[0]_13 ;
  wire \rd_mux_sel_r_reg[0]_14 ;
  wire \rd_mux_sel_r_reg[0]_15 ;
  wire \rd_mux_sel_r_reg[0]_16 ;
  wire \rd_mux_sel_r_reg[0]_17 ;
  wire \rd_mux_sel_r_reg[0]_18 ;
  wire \rd_mux_sel_r_reg[0]_19 ;
  wire \rd_mux_sel_r_reg[0]_2 ;
  wire \rd_mux_sel_r_reg[0]_20 ;
  wire \rd_mux_sel_r_reg[0]_21 ;
  wire \rd_mux_sel_r_reg[0]_22 ;
  wire \rd_mux_sel_r_reg[0]_23 ;
  wire \rd_mux_sel_r_reg[0]_24 ;
  wire \rd_mux_sel_r_reg[0]_25 ;
  wire \rd_mux_sel_r_reg[0]_26 ;
  wire \rd_mux_sel_r_reg[0]_27 ;
  wire \rd_mux_sel_r_reg[0]_28 ;
  wire \rd_mux_sel_r_reg[0]_29 ;
  wire \rd_mux_sel_r_reg[0]_3 ;
  wire \rd_mux_sel_r_reg[0]_30 ;
  wire \rd_mux_sel_r_reg[0]_31 ;
  wire \rd_mux_sel_r_reg[0]_32 ;
  wire \rd_mux_sel_r_reg[0]_33 ;
  wire \rd_mux_sel_r_reg[0]_34 ;
  wire \rd_mux_sel_r_reg[0]_35 ;
  wire \rd_mux_sel_r_reg[0]_36 ;
  wire \rd_mux_sel_r_reg[0]_37 ;
  wire \rd_mux_sel_r_reg[0]_38 ;
  wire \rd_mux_sel_r_reg[0]_39 ;
  wire \rd_mux_sel_r_reg[0]_4 ;
  wire \rd_mux_sel_r_reg[0]_40 ;
  wire \rd_mux_sel_r_reg[0]_41 ;
  wire \rd_mux_sel_r_reg[0]_42 ;
  wire \rd_mux_sel_r_reg[0]_43 ;
  wire \rd_mux_sel_r_reg[0]_44 ;
  wire \rd_mux_sel_r_reg[0]_45 ;
  wire \rd_mux_sel_r_reg[0]_46 ;
  wire \rd_mux_sel_r_reg[0]_47 ;
  wire \rd_mux_sel_r_reg[0]_48 ;
  wire \rd_mux_sel_r_reg[0]_49 ;
  wire \rd_mux_sel_r_reg[0]_5 ;
  wire \rd_mux_sel_r_reg[0]_50 ;
  wire \rd_mux_sel_r_reg[0]_51 ;
  wire \rd_mux_sel_r_reg[0]_52 ;
  wire \rd_mux_sel_r_reg[0]_53 ;
  wire \rd_mux_sel_r_reg[0]_54 ;
  wire \rd_mux_sel_r_reg[0]_55 ;
  wire \rd_mux_sel_r_reg[0]_56 ;
  wire \rd_mux_sel_r_reg[0]_57 ;
  wire \rd_mux_sel_r_reg[0]_58 ;
  wire \rd_mux_sel_r_reg[0]_59 ;
  wire \rd_mux_sel_r_reg[0]_6 ;
  wire \rd_mux_sel_r_reg[0]_60 ;
  wire \rd_mux_sel_r_reg[0]_61 ;
  wire \rd_mux_sel_r_reg[0]_62 ;
  wire \rd_mux_sel_r_reg[0]_7 ;
  wire \rd_mux_sel_r_reg[0]_8 ;
  wire \rd_mux_sel_r_reg[0]_9 ;
  wire [63:0]\rd_ptr_reg[3] ;
  wire rst_r4;
  wire sync_pulse;
  wire ts_dqs_1;
  wire [7:4]\NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED ;
  wire [7:4]\NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED ;
  wire [7:4]NLW_out_fifo_Q5_UNCONNECTED;
  wire [7:4]NLW_out_fifo_Q6_UNCONNECTED;
  wire NLW_phaser_out_PHASEREFCLK_UNCONNECTED;

  mig_mig_7series_v4_2_ddr_byte_group_io__parameterized0_17 ddr_byte_group_io
       (.A_rst_primitives(A_rst_primitives),
        .CLKB0_11(CLKB0_11),
        .CTSBUS(oserdes_dqs_ts[0]),
        .D2(if_d2),
        .D3(if_d3),
        .D4(if_d4),
        .D5(if_d5),
        .D6(if_d6),
        .D7(if_d7),
        .D8(if_d8),
        .D9(if_d9),
        .DQSBUS(oserdes_dqs),
        .DTSBUS(oserdes_dq_ts),
        .LD0_11(LD0_11),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (A_rst_primitives_reg),
        .idelay_inc(idelay_inc),
        .idelay_ld_rst_4(idelay_ld_rst_4),
        .idelay_ld_rst_reg_0(\entry_cnt_reg[4] ),
        .\input_[9].iserdes_dq_.iserdesdq_0 (\input_[9].iserdes_dq_.iserdesdq ),
        .iserdes_clkdiv(iserdes_clkdiv),
        .mem_dq_in(mem_dq_in),
        .mem_dq_out(mem_dq_out),
        .mem_dq_ts(mem_dq_ts),
        .of_dqbus(of_dqbus[39:4]),
        .oserdes_clk(oserdes_clk),
        .oserdes_clk_delayed(oserdes_clk_delayed),
        .oserdes_clkdiv(oserdes_clkdiv),
        .out_dqs_1(out_dqs_1),
        .po_oserdes_rst(po_oserdes_rst),
        .rst_r4(rst_r4),
        .ts_dqs_1(ts_dqs_1));
  (* syn_maxfan = "3" *) 
  FDRE \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(if_empty_),
        .Q(if_empty_r),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[12]),
        .Q(rd_data_r[12]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[13]),
        .Q(rd_data_r[13]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[14]),
        .Q(rd_data_r[14]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[15]),
        .Q(rd_data_r[15]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[16]),
        .Q(rd_data_r[16]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[17]),
        .Q(rd_data_r[17]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[18]),
        .Q(rd_data_r[18]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[19]),
        .Q(rd_data_r[19]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[20]),
        .Q(rd_data_r[20]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[21]),
        .Q(rd_data_r[21]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[22]),
        .Q(rd_data_r[22]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[23]),
        .Q(rd_data_r[23]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[24]),
        .Q(rd_data_r[24]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[25]),
        .Q(rd_data_r[25]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[26]),
        .Q(rd_data_r[26]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[27]),
        .Q(rd_data_r[27]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[28]),
        .Q(rd_data_r[28]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[29]),
        .Q(rd_data_r[29]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[30]),
        .Q(rd_data_r[30]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[31]),
        .Q(rd_data_r[31]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[32]),
        .Q(rd_data_r[32]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[33]),
        .Q(rd_data_r[33]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[34]),
        .Q(rd_data_r[34]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[35]),
        .Q(rd_data_r[35]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[36]),
        .Q(rd_data_r[36]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[37]),
        .Q(rd_data_r[37]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[38]),
        .Q(rd_data_r[38]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[39]),
        .Q(rd_data_r[39]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[40]),
        .Q(rd_data_r[40]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[41]),
        .Q(rd_data_r[41]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[42]),
        .Q(rd_data_r[42]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[43]),
        .Q(rd_data_r[43]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[44]),
        .Q(rd_data_r[44]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[45]),
        .Q(rd_data_r[45]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[46]),
        .Q(rd_data_r[46]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[47]),
        .Q(rd_data_r[47]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[48]),
        .Q(rd_data_r[48]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[49]),
        .Q(rd_data_r[49]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[50]),
        .Q(rd_data_r[50]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[51]),
        .Q(rd_data_r[51]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[52]),
        .Q(rd_data_r[52]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[53]),
        .Q(rd_data_r[53]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[54]),
        .Q(rd_data_r[54]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[55]),
        .Q(rd_data_r[55]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[56]),
        .Q(rd_data_r[56]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[57]),
        .Q(rd_data_r[57]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[58]),
        .Q(rd_data_r[58]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[59]),
        .Q(rd_data_r[59]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[60]),
        .Q(rd_data_r[60]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[61]),
        .Q(rd_data_r[61]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[62]),
        .Q(rd_data_r[62]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[63]),
        .Q(rd_data_r[63]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[64]),
        .Q(rd_data_r[64]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[65]),
        .Q(rd_data_r[65]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[66]),
        .Q(rd_data_r[66]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[67]),
        .Q(rd_data_r[67]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[68]),
        .Q(rd_data_r[68]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[69]),
        .Q(rd_data_r[69]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[70]),
        .Q(rd_data_r[70]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[71]),
        .Q(rd_data_r[71]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[72]),
        .Q(rd_data_r[72]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[73]),
        .Q(rd_data_r[73]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[74]),
        .Q(rd_data_r[74]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[75]),
        .Q(rd_data_r[75]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[76]),
        .Q(rd_data_r[76]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[77]),
        .Q(rd_data_r[77]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[78]),
        .Q(rd_data_r[78]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[79]),
        .Q(rd_data_r[79]),
        .R(1'b0));
  mig_mig_7series_v4_2_ddr_if_post_fifo_18 \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo 
       (.Q(rd_data_r),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ),
        .\gen_mux_rd[0].mux_rd_fall0_r_reg[0] (\gen_mux_rd[0].mux_rd_fall0_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0 (\gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0 ),
        .\gen_mux_rd[0].mux_rd_fall0_r_reg[0]_1 (\gen_mux_rd[0].mux_rd_fall0_r_reg[0]_1 ),
        .\gen_mux_rd[0].mux_rd_fall1_r_reg[0] (\gen_mux_rd[0].mux_rd_fall1_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0 (\gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0 ),
        .\gen_mux_rd[0].mux_rd_fall1_r_reg[0]_1 (\gen_mux_rd[0].mux_rd_fall1_r_reg[0]_1 ),
        .\gen_mux_rd[0].mux_rd_fall2_r_reg[0] (\gen_mux_rd[0].mux_rd_fall2_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0 (\gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0 ),
        .\gen_mux_rd[0].mux_rd_fall2_r_reg[0]_1 (\gen_mux_rd[0].mux_rd_fall2_r_reg[0]_1 ),
        .\gen_mux_rd[0].mux_rd_fall3_r_reg[0] (\gen_mux_rd[0].mux_rd_fall3_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0 (\gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0 ),
        .\gen_mux_rd[0].mux_rd_fall3_r_reg[0]_1 (\gen_mux_rd[0].mux_rd_fall3_r_reg[0]_1 ),
        .\gen_mux_rd[0].mux_rd_rise0_r_reg[0] (\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 (\gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ),
        .\gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1 (\gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1 ),
        .\gen_mux_rd[0].mux_rd_rise0_r_reg[0]_2 (\gen_mux_rd[0].mux_rd_rise0_r_reg[0]_2 ),
        .\gen_mux_rd[0].mux_rd_rise1_r_reg[0] (\gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0 (\gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0 ),
        .\gen_mux_rd[0].mux_rd_rise1_r_reg[0]_1 (\gen_mux_rd[0].mux_rd_rise1_r_reg[0]_1 ),
        .\gen_mux_rd[0].mux_rd_rise2_r_reg[0] (\gen_mux_rd[0].mux_rd_rise2_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0 (\gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0 ),
        .\gen_mux_rd[0].mux_rd_rise2_r_reg[0]_1 (\gen_mux_rd[0].mux_rd_rise2_r_reg[0]_1 ),
        .\gen_mux_rd[0].mux_rd_rise3_r_reg[0] (\gen_mux_rd[0].mux_rd_rise3_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0 (\gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0 ),
        .\gen_mux_rd[0].mux_rd_rise3_r_reg[0]_1 (\gen_mux_rd[0].mux_rd_rise3_r_reg[0]_1 ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1] (\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 (\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1] (\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 (\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1] (\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 (\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 ),
        .\gen_mux_rd[1].mux_rd_fall3_r_reg[1] (\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1 (\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1 ),
        .\gen_mux_rd[1].mux_rd_rise0_r_reg[1] (\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1 (\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1 ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1] (\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 (\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1] (\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 (\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1] (\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 (\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 ),
        .\gen_mux_rd[2].mux_rd_fall0_r_reg[2] (\gen_mux_rd[2].mux_rd_fall0_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0 (\gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0 ),
        .\gen_mux_rd[2].mux_rd_fall0_r_reg[2]_1 (\gen_mux_rd[2].mux_rd_fall0_r_reg[2]_1 ),
        .\gen_mux_rd[2].mux_rd_fall1_r_reg[2] (\gen_mux_rd[2].mux_rd_fall1_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0 (\gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0 ),
        .\gen_mux_rd[2].mux_rd_fall1_r_reg[2]_1 (\gen_mux_rd[2].mux_rd_fall1_r_reg[2]_1 ),
        .\gen_mux_rd[2].mux_rd_fall2_r_reg[2] (\gen_mux_rd[2].mux_rd_fall2_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0 (\gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0 ),
        .\gen_mux_rd[2].mux_rd_fall2_r_reg[2]_1 (\gen_mux_rd[2].mux_rd_fall2_r_reg[2]_1 ),
        .\gen_mux_rd[2].mux_rd_fall3_r_reg[2] (\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 (\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 ),
        .\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_1 (\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_1 ),
        .\gen_mux_rd[2].mux_rd_rise0_r_reg[2] (\gen_mux_rd[2].mux_rd_rise0_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 (\gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ),
        .\gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1 (\gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1 ),
        .\gen_mux_rd[2].mux_rd_rise1_r_reg[2] (\gen_mux_rd[2].mux_rd_rise1_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0 (\gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0 ),
        .\gen_mux_rd[2].mux_rd_rise1_r_reg[2]_1 (\gen_mux_rd[2].mux_rd_rise1_r_reg[2]_1 ),
        .\gen_mux_rd[2].mux_rd_rise2_r_reg[2] (\gen_mux_rd[2].mux_rd_rise2_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0 (\gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0 ),
        .\gen_mux_rd[2].mux_rd_rise2_r_reg[2]_1 (\gen_mux_rd[2].mux_rd_rise2_r_reg[2]_1 ),
        .\gen_mux_rd[2].mux_rd_rise3_r_reg[2] (\gen_mux_rd[2].mux_rd_rise3_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0 (\gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0 ),
        .\gen_mux_rd[2].mux_rd_rise3_r_reg[2]_1 (\gen_mux_rd[2].mux_rd_rise3_r_reg[2]_1 ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3] (\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 (\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3] (\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 (\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3] (\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 (\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3] (\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 (\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3] (\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 (\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3] (\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 (\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3] (\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 (\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3] (\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 (\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 ),
        .\gen_mux_rd[4].mux_rd_fall0_r_reg[4] (\gen_mux_rd[4].mux_rd_fall0_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0 (\gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0 ),
        .\gen_mux_rd[4].mux_rd_fall0_r_reg[4]_1 (\gen_mux_rd[4].mux_rd_fall0_r_reg[4]_1 ),
        .\gen_mux_rd[4].mux_rd_fall1_r_reg[4] (\gen_mux_rd[4].mux_rd_fall1_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0 (\gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0 ),
        .\gen_mux_rd[4].mux_rd_fall1_r_reg[4]_1 (\gen_mux_rd[4].mux_rd_fall1_r_reg[4]_1 ),
        .\gen_mux_rd[4].mux_rd_fall2_r_reg[4] (\gen_mux_rd[4].mux_rd_fall2_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0 (\gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0 ),
        .\gen_mux_rd[4].mux_rd_fall2_r_reg[4]_1 (\gen_mux_rd[4].mux_rd_fall2_r_reg[4]_1 ),
        .\gen_mux_rd[4].mux_rd_fall3_r_reg[4] (\gen_mux_rd[4].mux_rd_fall3_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0 (\gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0 ),
        .\gen_mux_rd[4].mux_rd_fall3_r_reg[4]_1 (\gen_mux_rd[4].mux_rd_fall3_r_reg[4]_1 ),
        .\gen_mux_rd[4].mux_rd_rise0_r_reg[4] (\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0 (\gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0 ),
        .\gen_mux_rd[4].mux_rd_rise0_r_reg[4]_1 (\gen_mux_rd[4].mux_rd_rise0_r_reg[4]_1 ),
        .\gen_mux_rd[4].mux_rd_rise1_r_reg[4] (\gen_mux_rd[4].mux_rd_rise1_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0 (\gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0 ),
        .\gen_mux_rd[4].mux_rd_rise1_r_reg[4]_1 (\gen_mux_rd[4].mux_rd_rise1_r_reg[4]_1 ),
        .\gen_mux_rd[4].mux_rd_rise2_r_reg[4] (\gen_mux_rd[4].mux_rd_rise2_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0 (\gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0 ),
        .\gen_mux_rd[4].mux_rd_rise2_r_reg[4]_1 (\gen_mux_rd[4].mux_rd_rise2_r_reg[4]_1 ),
        .\gen_mux_rd[4].mux_rd_rise3_r_reg[4] (\gen_mux_rd[4].mux_rd_rise3_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0 (\gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0 ),
        .\gen_mux_rd[4].mux_rd_rise3_r_reg[4]_1 (\gen_mux_rd[4].mux_rd_rise3_r_reg[4]_1 ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5] (\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 (\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5] (\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 (\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5] (\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 (\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5] (\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 (\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 ),
        .\gen_mux_rd[5].mux_rd_rise0_r_reg[5] (\gen_mux_rd[5].mux_rd_rise0_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_rise0_r_reg[5]_1 (\gen_mux_rd[5].mux_rd_rise0_r_reg[5]_1 ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5] (\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 (\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5] (\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 (\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5] (\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 (\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 ),
        .\gen_mux_rd[6].mux_rd_fall0_r_reg[6] (\gen_mux_rd[6].mux_rd_fall0_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0 (\gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0 ),
        .\gen_mux_rd[6].mux_rd_fall0_r_reg[6]_1 (\gen_mux_rd[6].mux_rd_fall0_r_reg[6]_1 ),
        .\gen_mux_rd[6].mux_rd_fall1_r_reg[6] (\gen_mux_rd[6].mux_rd_fall1_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0 (\gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0 ),
        .\gen_mux_rd[6].mux_rd_fall1_r_reg[6]_1 (\gen_mux_rd[6].mux_rd_fall1_r_reg[6]_1 ),
        .\gen_mux_rd[6].mux_rd_fall2_r_reg[6] (\gen_mux_rd[6].mux_rd_fall2_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0 (\gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0 ),
        .\gen_mux_rd[6].mux_rd_fall2_r_reg[6]_1 (\gen_mux_rd[6].mux_rd_fall2_r_reg[6]_1 ),
        .\gen_mux_rd[6].mux_rd_fall3_r_reg[6] (\gen_mux_rd[6].mux_rd_fall3_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0 (\gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0 ),
        .\gen_mux_rd[6].mux_rd_fall3_r_reg[6]_1 (\gen_mux_rd[6].mux_rd_fall3_r_reg[6]_1 ),
        .\gen_mux_rd[6].mux_rd_rise0_r_reg[6] (\gen_mux_rd[6].mux_rd_rise0_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0 (\gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0 ),
        .\gen_mux_rd[6].mux_rd_rise0_r_reg[6]_1 (\gen_mux_rd[6].mux_rd_rise0_r_reg[6]_1 ),
        .\gen_mux_rd[6].mux_rd_rise1_r_reg[6] (\gen_mux_rd[6].mux_rd_rise1_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0 (\gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0 ),
        .\gen_mux_rd[6].mux_rd_rise1_r_reg[6]_1 (\gen_mux_rd[6].mux_rd_rise1_r_reg[6]_1 ),
        .\gen_mux_rd[6].mux_rd_rise2_r_reg[6] (\gen_mux_rd[6].mux_rd_rise2_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0 (\gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0 ),
        .\gen_mux_rd[6].mux_rd_rise2_r_reg[6]_1 (\gen_mux_rd[6].mux_rd_rise2_r_reg[6]_1 ),
        .\gen_mux_rd[6].mux_rd_rise3_r_reg[6] (\gen_mux_rd[6].mux_rd_rise3_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0 (\gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0 ),
        .\gen_mux_rd[6].mux_rd_rise3_r_reg[6]_1 (\gen_mux_rd[6].mux_rd_rise3_r_reg[6]_1 ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7] (\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 (\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7] (\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 (\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7] (\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 (\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 (\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 ),
        .\gen_mux_rd[7].mux_rd_rise0_r_reg[7] (\gen_mux_rd[7].mux_rd_rise0_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_rise0_r_reg[7]_1 (\gen_mux_rd[7].mux_rd_rise0_r_reg[7]_1 ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7] (\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 (\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7] (\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 (\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7] (\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 (\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 ),
        .ififo_rst(ififo_rst),
        .\my_empty_reg[4]_0 (\my_empty_reg[4] [0]),
        .\my_empty_reg[4]_1 (\my_empty_reg[4] [1]),
        .\my_full_reg[1]_0 (if_empty_r),
        .\my_full_reg[1]_1 (\my_full_reg[1] ),
        .\rd_mux_sel_r_reg[0] (\rd_mux_sel_r_reg[0] ),
        .\rd_mux_sel_r_reg[0]_0 (\rd_mux_sel_r_reg[0]_0 ),
        .\rd_mux_sel_r_reg[0]_1 (\rd_mux_sel_r_reg[0]_1 ),
        .\rd_mux_sel_r_reg[0]_10 (\rd_mux_sel_r_reg[0]_10 ),
        .\rd_mux_sel_r_reg[0]_11 (\rd_mux_sel_r_reg[0]_11 ),
        .\rd_mux_sel_r_reg[0]_12 (\rd_mux_sel_r_reg[0]_12 ),
        .\rd_mux_sel_r_reg[0]_13 (\rd_mux_sel_r_reg[0]_13 ),
        .\rd_mux_sel_r_reg[0]_14 (\rd_mux_sel_r_reg[0]_14 ),
        .\rd_mux_sel_r_reg[0]_15 (\rd_mux_sel_r_reg[0]_15 ),
        .\rd_mux_sel_r_reg[0]_16 (\rd_mux_sel_r_reg[0]_16 ),
        .\rd_mux_sel_r_reg[0]_17 (\rd_mux_sel_r_reg[0]_17 ),
        .\rd_mux_sel_r_reg[0]_18 (\rd_mux_sel_r_reg[0]_18 ),
        .\rd_mux_sel_r_reg[0]_19 (\rd_mux_sel_r_reg[0]_19 ),
        .\rd_mux_sel_r_reg[0]_2 (\rd_mux_sel_r_reg[0]_2 ),
        .\rd_mux_sel_r_reg[0]_20 (\rd_mux_sel_r_reg[0]_20 ),
        .\rd_mux_sel_r_reg[0]_21 (\rd_mux_sel_r_reg[0]_21 ),
        .\rd_mux_sel_r_reg[0]_22 (\rd_mux_sel_r_reg[0]_22 ),
        .\rd_mux_sel_r_reg[0]_23 (\rd_mux_sel_r_reg[0]_23 ),
        .\rd_mux_sel_r_reg[0]_24 (\rd_mux_sel_r_reg[0]_24 ),
        .\rd_mux_sel_r_reg[0]_25 (\rd_mux_sel_r_reg[0]_25 ),
        .\rd_mux_sel_r_reg[0]_26 (\rd_mux_sel_r_reg[0]_26 ),
        .\rd_mux_sel_r_reg[0]_27 (\rd_mux_sel_r_reg[0]_27 ),
        .\rd_mux_sel_r_reg[0]_28 (\rd_mux_sel_r_reg[0]_28 ),
        .\rd_mux_sel_r_reg[0]_29 (\rd_mux_sel_r_reg[0]_29 ),
        .\rd_mux_sel_r_reg[0]_3 (\rd_mux_sel_r_reg[0]_3 ),
        .\rd_mux_sel_r_reg[0]_30 (\rd_mux_sel_r_reg[0]_30 ),
        .\rd_mux_sel_r_reg[0]_31 (\rd_mux_sel_r_reg[0]_31 ),
        .\rd_mux_sel_r_reg[0]_32 (\rd_mux_sel_r_reg[0]_32 ),
        .\rd_mux_sel_r_reg[0]_33 (\rd_mux_sel_r_reg[0]_33 ),
        .\rd_mux_sel_r_reg[0]_34 (\rd_mux_sel_r_reg[0]_34 ),
        .\rd_mux_sel_r_reg[0]_35 (\rd_mux_sel_r_reg[0]_35 ),
        .\rd_mux_sel_r_reg[0]_36 (\rd_mux_sel_r_reg[0]_36 ),
        .\rd_mux_sel_r_reg[0]_37 (\rd_mux_sel_r_reg[0]_37 ),
        .\rd_mux_sel_r_reg[0]_38 (\rd_mux_sel_r_reg[0]_38 ),
        .\rd_mux_sel_r_reg[0]_39 (\rd_mux_sel_r_reg[0]_39 ),
        .\rd_mux_sel_r_reg[0]_4 (\rd_mux_sel_r_reg[0]_4 ),
        .\rd_mux_sel_r_reg[0]_40 (\rd_mux_sel_r_reg[0]_40 ),
        .\rd_mux_sel_r_reg[0]_41 (\rd_mux_sel_r_reg[0]_41 ),
        .\rd_mux_sel_r_reg[0]_42 (\rd_mux_sel_r_reg[0]_42 ),
        .\rd_mux_sel_r_reg[0]_43 (\rd_mux_sel_r_reg[0]_43 ),
        .\rd_mux_sel_r_reg[0]_44 (\rd_mux_sel_r_reg[0]_44 ),
        .\rd_mux_sel_r_reg[0]_45 (\rd_mux_sel_r_reg[0]_45 ),
        .\rd_mux_sel_r_reg[0]_46 (\rd_mux_sel_r_reg[0]_46 ),
        .\rd_mux_sel_r_reg[0]_47 (\rd_mux_sel_r_reg[0]_47 ),
        .\rd_mux_sel_r_reg[0]_48 (\rd_mux_sel_r_reg[0]_48 ),
        .\rd_mux_sel_r_reg[0]_49 (\rd_mux_sel_r_reg[0]_49 ),
        .\rd_mux_sel_r_reg[0]_5 (\rd_mux_sel_r_reg[0]_5 ),
        .\rd_mux_sel_r_reg[0]_50 (\rd_mux_sel_r_reg[0]_50 ),
        .\rd_mux_sel_r_reg[0]_51 (\rd_mux_sel_r_reg[0]_51 ),
        .\rd_mux_sel_r_reg[0]_52 (\rd_mux_sel_r_reg[0]_52 ),
        .\rd_mux_sel_r_reg[0]_53 (\rd_mux_sel_r_reg[0]_53 ),
        .\rd_mux_sel_r_reg[0]_54 (\rd_mux_sel_r_reg[0]_54 ),
        .\rd_mux_sel_r_reg[0]_55 (\rd_mux_sel_r_reg[0]_55 ),
        .\rd_mux_sel_r_reg[0]_56 (\rd_mux_sel_r_reg[0]_56 ),
        .\rd_mux_sel_r_reg[0]_57 (\rd_mux_sel_r_reg[0]_57 ),
        .\rd_mux_sel_r_reg[0]_58 (\rd_mux_sel_r_reg[0]_58 ),
        .\rd_mux_sel_r_reg[0]_59 (\rd_mux_sel_r_reg[0]_59 ),
        .\rd_mux_sel_r_reg[0]_6 (\rd_mux_sel_r_reg[0]_6 ),
        .\rd_mux_sel_r_reg[0]_60 (\rd_mux_sel_r_reg[0]_60 ),
        .\rd_mux_sel_r_reg[0]_61 (\rd_mux_sel_r_reg[0]_61 ),
        .\rd_mux_sel_r_reg[0]_62 (\rd_mux_sel_r_reg[0]_62 ),
        .\rd_mux_sel_r_reg[0]_7 (\rd_mux_sel_r_reg[0]_7 ),
        .\rd_mux_sel_r_reg[0]_8 (\rd_mux_sel_r_reg[0]_8 ),
        .\rd_mux_sel_r_reg[0]_9 (\rd_mux_sel_r_reg[0]_9 ),
        .\rd_ptr_timing_reg[1]_0 (\entry_cnt_reg[4] ));
  FDSE #(
    .INIT(1'b1)) 
    ififo_rst_reg
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(ififo_rst_reg_0),
        .Q(ififo_rst),
        .S(phy_if_reset));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IN_FIFO #(
    .ALMOST_EMPTY_VALUE(1),
    .ALMOST_FULL_VALUE(1),
    .ARRAY_MODE("ARRAY_MODE_4_X_8"),
    .SYNCHRONOUS_MODE("FALSE")) 
    \in_fifo_gen.in_fifo 
       (.ALMOSTEMPTY(\in_fifo_gen.in_fifo_n_0 ),
        .ALMOSTFULL(\in_fifo_gen.in_fifo_n_1 ),
        .D0({1'b0,1'b0,1'b0,1'b0}),
        .D1({1'b0,1'b0,1'b0,1'b0}),
        .D2(if_d2),
        .D3(if_d3),
        .D4(if_d4),
        .D5({\NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED [7:4],if_d5}),
        .D6({\NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED [7:4],if_d6}),
        .D7(if_d7),
        .D8(if_d8),
        .D9(if_d9),
        .EMPTY(if_empty_),
        .FULL(\in_fifo_gen.in_fifo_n_3 ),
        .Q0(rd_data[7:0]),
        .Q1(rd_data[15:8]),
        .Q2(rd_data[23:16]),
        .Q3(rd_data[31:24]),
        .Q4(rd_data[39:32]),
        .Q5(rd_data[47:40]),
        .Q6(rd_data[55:48]),
        .Q7(rd_data[63:56]),
        .Q8(rd_data[71:64]),
        .Q9(rd_data[79:72]),
        .RDCLK(\entry_cnt_reg[4] ),
        .RDEN(1'b1),
        .RESET(ififo_rst),
        .WRCLK(iserdes_clkdiv),
        .WREN(ififo_wr_enable));
  mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_19 \of_pre_fifo_gen.u_ddr_of_pre_fifo 
       (.D0({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 }),
        .D1(of_d1),
        .Q(Q),
        .\entry_cnt_reg[4]_0 (\entry_cnt_reg[4] ),
        .\my_empty_reg[1]_0 (\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ),
        .\my_empty_reg[1]_1 (\my_empty_reg[1] ),
        .\my_empty_reg[7]_0 (out_fifo_n_3),
        .ofifo_rst(ofifo_rst),
        .out_fifo(out_fifo_0),
        .out_fifo_0(out_fifo_1),
        .out_fifo_1(out_fifo_2),
        .out_fifo_i_75__1(out_fifo_i_75__1),
        .phy_data_wr_en(phy_data_wr_en),
        .\rd_ptr_reg[3]_0 (\rd_ptr_reg[3] ));
  FDSE #(
    .INIT(1'b1)) 
    ofifo_rst_reg
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(ififo_rst_reg_0),
        .Q(ofifo_rst),
        .S(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OUT_FIFO #(
    .ALMOST_EMPTY_VALUE(1),
    .ALMOST_FULL_VALUE(1),
    .ARRAY_MODE("ARRAY_MODE_8_X_4"),
    .OUTPUT_DISABLE("FALSE"),
    .SYNCHRONOUS_MODE("FALSE")) 
    out_fifo
       (.ALMOSTEMPTY(out_fifo_n_0),
        .ALMOSTFULL(out_fifo_n_1),
        .D0({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 }),
        .D1(of_d1),
        .D2(\my_empty_reg[7] ),
        .D3(\my_empty_reg[7]_0 ),
        .D4(\my_empty_reg[7]_1 ),
        .D5(\my_empty_reg[7]_2 ),
        .D6(\my_empty_reg[7]_3 ),
        .D7(\my_empty_reg[7]_4 ),
        .D8(\my_empty_reg[7]_5 ),
        .D9(\my_empty_reg[7]_6 ),
        .EMPTY(out_fifo_n_2),
        .FULL(out_fifo_n_3),
        .Q0(of_dqbus[3:0]),
        .Q1(of_dqbus[7:4]),
        .Q2(of_dqbus[11:8]),
        .Q3(of_dqbus[15:12]),
        .Q4(of_dqbus[19:16]),
        .Q5({NLW_out_fifo_Q5_UNCONNECTED[7:4],of_dqbus[23:20]}),
        .Q6({NLW_out_fifo_Q6_UNCONNECTED[7:4],of_dqbus[27:24]}),
        .Q7(of_dqbus[31:28]),
        .Q8(of_dqbus[35:32]),
        .Q9(of_dqbus[39:36]),
        .RDCLK(oserdes_clkdiv),
        .RDEN(po_rd_enable),
        .RESET(ofifo_rst),
        .WRCLK(\entry_cnt_reg[4] ),
        .WREN(\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  PHASER_IN_PHY #(
    .BURST_MODE("TRUE"),
    .CLKOUT_DIV(2),
    .DQS_AUTO_RECAL(1'b1),
    .DQS_BIAS_MODE("FALSE"),
    .DQS_FIND_PATTERN(3'b000),
    .FINE_DELAY(33),
    .FREQ_REF_DIV("DIV2"),
    .IS_RST_INVERTED(1'b0),
    .MEMREFCLK_PERIOD(2.500000),
    .OUTPUT_CLK_SRC("DELAYED_REF"),
    .PHASEREFCLK_PERIOD(2.500000),
    .REFCLK_PERIOD(1.250000),
    .SEL_CLK_OFFSET(6),
    .SYNC_IN_DIV_RST("TRUE"),
    .WR_CYCLES("FALSE")) 
    \phaser_in_gen.phaser_in 
       (.BURSTPENDINGPHY(phaser_ctl_bus[1]),
        .COUNTERLOADEN(\pi_dqs_found_lanes_r1_reg[9] ),
        .COUNTERLOADVAL(\pi_dqs_found_lanes_r1_reg[9]_3 ),
        .COUNTERREADEN(\pi_dqs_found_lanes_r1_reg[9]_0 ),
        .COUNTERREADVAL(B_pi_counter_read_val),
        .DQSFOUND(in0),
        .DQSOUTOFRANGE(\phaser_in_gen.phaser_in_n_1 ),
        .ENCALIBPHY(PCENABLECALIB),
        .FINEENABLE(\pi_dqs_found_lanes_r1_reg[9]_1 ),
        .FINEINC(\pi_dqs_found_lanes_r1_reg[9]_2 ),
        .FINEOVERFLOW(\phaser_in_gen.phaser_in_n_2 ),
        .FREQREFCLK(freq_refclk),
        .ICLK(A_rst_primitives_reg),
        .ICLKDIV(iserdes_clkdiv),
        .ISERDESRST(\phaser_in_gen.phaser_in_n_5 ),
        .MEMREFCLK(mem_refclk),
        .PHASELOCKED(A_rst_primitives_reg_0),
        .PHASEREFCLK(mem_dqs_in),
        .RANKSELPHY(phaser_ctl_bus[3:2]),
        .RCLK(B_rclk),
        .RST(A_rst_primitives),
        .RSTDQSFIND(ififo_rst_reg_0),
        .SYNCIN(sync_pulse),
        .SYSCLK(\entry_cnt_reg[4] ),
        .WRENABLE(ififo_wr_enable));
  (* BOX_TYPE = "PRIMITIVE" *) 
  PHASER_OUT_PHY #(
    .CLKOUT_DIV(2),
    .COARSE_BYPASS("FALSE"),
    .COARSE_DELAY(0),
    .DATA_CTL_N("TRUE"),
    .DATA_RD_CYCLES("FALSE"),
    .FINE_DELAY(60),
    .IS_RST_INVERTED(1'b0),
    .MEMREFCLK_PERIOD(2.500000),
    .OCLKDELAY_INV("FALSE"),
    .OCLK_DELAY(0),
    .OUTPUT_CLK_SRC("DELAYED_REF"),
    .PHASEREFCLK_PERIOD(1.000000),
    .PO(3'b111),
    .REFCLK_PERIOD(1.250000),
    .SYNC_IN_DIV_RST("TRUE")) 
    phaser_out
       (.BURSTPENDINGPHY(phaser_ctl_bus[0]),
        .COARSEENABLE(\po_counter_read_val_reg[8] ),
        .COARSEINC(\po_counter_read_val_reg[8] ),
        .COARSEOVERFLOW(phaser_out_n_0),
        .COUNTERLOADEN(1'b0),
        .COUNTERLOADVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .COUNTERREADEN(\pi_dqs_found_lanes_r1_reg[9]_0 ),
        .COUNTERREADVAL(B_po_counter_read_val),
        .CTSBUS(oserdes_dqs_ts),
        .DQSBUS(oserdes_dqs),
        .DTSBUS(oserdes_dq_ts),
        .ENCALIBPHY(PCENABLECALIB),
        .FINEENABLE(\po_counter_read_val_reg[8]_0 ),
        .FINEINC(\po_counter_read_val_reg[8]_1 ),
        .FINEOVERFLOW(phaser_out_n_1),
        .FREQREFCLK(freq_refclk),
        .MEMREFCLK(mem_refclk),
        .OCLK(oserdes_clk),
        .OCLKDELAYED(oserdes_clk_delayed),
        .OCLKDIV(oserdes_clkdiv),
        .OSERDESRST(po_oserdes_rst),
        .PHASEREFCLK(NLW_phaser_out_PHASEREFCLK_UNCONNECTED),
        .RDENABLE(po_rd_enable),
        .RST(A_rst_primitives),
        .SELFINEOCLKDELAY(1'b0),
        .SYNCIN(sync_pulse),
        .SYSCLK(\entry_cnt_reg[4] ));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \pi_counter_read_val[0]_i_1__0 
       (.I0(B_pi_counter_read_val[0]),
        .I1(COUNTERREADVAL[0]),
        .I2(\pi_counter_read_val_reg[5] [0]),
        .I3(calib_sel[1]),
        .I4(calib_sel[0]),
        .I5(\pi_counter_read_val_reg[5]_0 [0]),
        .O(D[0]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \pi_counter_read_val[1]_i_1__0 
       (.I0(B_pi_counter_read_val[1]),
        .I1(COUNTERREADVAL[1]),
        .I2(\pi_counter_read_val_reg[5] [1]),
        .I3(calib_sel[1]),
        .I4(calib_sel[0]),
        .I5(\pi_counter_read_val_reg[5]_0 [1]),
        .O(D[1]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \pi_counter_read_val[2]_i_1__0 
       (.I0(B_pi_counter_read_val[2]),
        .I1(COUNTERREADVAL[2]),
        .I2(\pi_counter_read_val_reg[5] [2]),
        .I3(calib_sel[1]),
        .I4(calib_sel[0]),
        .I5(\pi_counter_read_val_reg[5]_0 [2]),
        .O(D[2]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \pi_counter_read_val[3]_i_1__0 
       (.I0(B_pi_counter_read_val[3]),
        .I1(COUNTERREADVAL[3]),
        .I2(\pi_counter_read_val_reg[5] [3]),
        .I3(calib_sel[1]),
        .I4(calib_sel[0]),
        .I5(\pi_counter_read_val_reg[5]_0 [3]),
        .O(D[3]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \pi_counter_read_val[4]_i_1__0 
       (.I0(B_pi_counter_read_val[4]),
        .I1(COUNTERREADVAL[4]),
        .I2(\pi_counter_read_val_reg[5] [4]),
        .I3(calib_sel[1]),
        .I4(calib_sel[0]),
        .I5(\pi_counter_read_val_reg[5]_0 [4]),
        .O(D[4]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \pi_counter_read_val[5]_i_1__0 
       (.I0(B_pi_counter_read_val[5]),
        .I1(COUNTERREADVAL[5]),
        .I2(\pi_counter_read_val_reg[5] [5]),
        .I3(calib_sel[1]),
        .I4(calib_sel[0]),
        .I5(\pi_counter_read_val_reg[5]_0 [5]),
        .O(D[5]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \po_counter_read_val[0]_i_1__0 
       (.I0(B_po_counter_read_val[0]),
        .I1(\po_counter_read_val_reg[8]_2 [0]),
        .I2(\po_counter_read_val_reg[8]_3 [0]),
        .I3(calib_sel[1]),
        .I4(calib_sel[0]),
        .I5(\po_counter_read_val_reg[8]_4 [0]),
        .O(\calib_sel_reg[1] [0]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \po_counter_read_val[1]_i_1__0 
       (.I0(B_po_counter_read_val[1]),
        .I1(\po_counter_read_val_reg[8]_2 [1]),
        .I2(\po_counter_read_val_reg[8]_3 [1]),
        .I3(calib_sel[1]),
        .I4(calib_sel[0]),
        .I5(\po_counter_read_val_reg[8]_4 [1]),
        .O(\calib_sel_reg[1] [1]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \po_counter_read_val[2]_i_1__0 
       (.I0(B_po_counter_read_val[2]),
        .I1(\po_counter_read_val_reg[8]_2 [2]),
        .I2(\po_counter_read_val_reg[8]_3 [2]),
        .I3(calib_sel[1]),
        .I4(calib_sel[0]),
        .I5(\po_counter_read_val_reg[8]_4 [2]),
        .O(\calib_sel_reg[1] [2]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \po_counter_read_val[3]_i_1__0 
       (.I0(B_po_counter_read_val[3]),
        .I1(\po_counter_read_val_reg[8]_2 [3]),
        .I2(\po_counter_read_val_reg[8]_3 [3]),
        .I3(calib_sel[1]),
        .I4(calib_sel[0]),
        .I5(\po_counter_read_val_reg[8]_4 [3]),
        .O(\calib_sel_reg[1] [3]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \po_counter_read_val[4]_i_1__0 
       (.I0(B_po_counter_read_val[4]),
        .I1(\po_counter_read_val_reg[8]_2 [4]),
        .I2(\po_counter_read_val_reg[8]_3 [4]),
        .I3(calib_sel[1]),
        .I4(calib_sel[0]),
        .I5(\po_counter_read_val_reg[8]_4 [4]),
        .O(\calib_sel_reg[1] [4]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \po_counter_read_val[5]_i_1__0 
       (.I0(B_po_counter_read_val[5]),
        .I1(\po_counter_read_val_reg[8]_2 [5]),
        .I2(\po_counter_read_val_reg[8]_3 [5]),
        .I3(calib_sel[1]),
        .I4(calib_sel[0]),
        .I5(\po_counter_read_val_reg[8]_4 [5]),
        .O(\calib_sel_reg[1] [5]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \po_counter_read_val[6]_i_1__0 
       (.I0(B_po_counter_read_val[6]),
        .I1(\po_counter_read_val_reg[8]_2 [6]),
        .I2(\po_counter_read_val_reg[8]_3 [6]),
        .I3(calib_sel[1]),
        .I4(calib_sel[0]),
        .I5(\po_counter_read_val_reg[8]_4 [6]),
        .O(\calib_sel_reg[1] [6]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \po_counter_read_val[7]_i_1__0 
       (.I0(B_po_counter_read_val[7]),
        .I1(\po_counter_read_val_reg[8]_2 [7]),
        .I2(\po_counter_read_val_reg[8]_3 [7]),
        .I3(calib_sel[1]),
        .I4(calib_sel[0]),
        .I5(\po_counter_read_val_reg[8]_4 [7]),
        .O(\calib_sel_reg[1] [7]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \po_counter_read_val[8]_i_1__0 
       (.I0(B_po_counter_read_val[8]),
        .I1(\po_counter_read_val_reg[8]_2 [8]),
        .I2(\po_counter_read_val_reg[8]_3 [8]),
        .I3(calib_sel[1]),
        .I4(calib_sel[0]),
        .I5(\po_counter_read_val_reg[8]_4 [8]),
        .O(\calib_sel_reg[1] [8]));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_byte_lane" *) 
module mig_mig_7series_v4_2_ddr_byte_lane__parameterized0_26
   (out_dqs_5,
    ts_dqs_5,
    A_rst_primitives_reg,
    mem_dq_out,
    mem_dq_ts,
    in0,
    A_rst_primitives_reg_0,
    B_rclk,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ,
    \my_empty_reg[4] ,
    idelay_ld_rst_0,
    \my_empty_reg[4]_0 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ,
    \my_empty_reg[1] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ,
    \rd_mux_sel_r_reg[2] ,
    \rd_mux_sel_r_reg[2]_0 ,
    \rd_mux_sel_r_reg[2]_1 ,
    \rd_mux_sel_r_reg[2]_2 ,
    \rd_mux_sel_r_reg[2]_3 ,
    \rd_mux_sel_r_reg[2]_4 ,
    \rd_mux_sel_r_reg[2]_5 ,
    \rd_mux_sel_r_reg[2]_6 ,
    \rd_mux_sel_r_reg[2]_7 ,
    \rd_mux_sel_r_reg[2]_8 ,
    \rd_mux_sel_r_reg[2]_9 ,
    \rd_mux_sel_r_reg[2]_10 ,
    \rd_mux_sel_r_reg[2]_11 ,
    \rd_mux_sel_r_reg[2]_12 ,
    \rd_mux_sel_r_reg[2]_13 ,
    \rd_mux_sel_r_reg[2]_14 ,
    \rd_mux_sel_r_reg[2]_15 ,
    \rd_mux_sel_r_reg[2]_16 ,
    \rd_mux_sel_r_reg[2]_17 ,
    \rd_mux_sel_r_reg[2]_18 ,
    \rd_mux_sel_r_reg[2]_19 ,
    \rd_mux_sel_r_reg[2]_20 ,
    \rd_mux_sel_r_reg[2]_21 ,
    \rd_mux_sel_r_reg[2]_22 ,
    \rd_mux_sel_r_reg[2]_23 ,
    \rd_mux_sel_r_reg[2]_24 ,
    \rd_mux_sel_r_reg[2]_25 ,
    \rd_mux_sel_r_reg[2]_26 ,
    \rd_mux_sel_r_reg[2]_27 ,
    \rd_mux_sel_r_reg[2]_28 ,
    \rd_mux_sel_r_reg[2]_29 ,
    \rd_mux_sel_r_reg[2]_30 ,
    \rd_mux_sel_r_reg[2]_31 ,
    \rd_mux_sel_r_reg[2]_32 ,
    \rd_mux_sel_r_reg[2]_33 ,
    \rd_mux_sel_r_reg[2]_34 ,
    \rd_mux_sel_r_reg[2]_35 ,
    \rd_mux_sel_r_reg[2]_36 ,
    \rd_mux_sel_r_reg[2]_37 ,
    \rd_mux_sel_r_reg[2]_38 ,
    \rd_mux_sel_r_reg[2]_39 ,
    \rd_mux_sel_r_reg[2]_40 ,
    \rd_mux_sel_r_reg[2]_41 ,
    \rd_mux_sel_r_reg[2]_42 ,
    \rd_mux_sel_r_reg[2]_43 ,
    \rd_mux_sel_r_reg[2]_44 ,
    \rd_mux_sel_r_reg[2]_45 ,
    \rd_mux_sel_r_reg[2]_46 ,
    \rd_mux_sel_r_reg[2]_47 ,
    \rd_mux_sel_r_reg[2]_48 ,
    \rd_mux_sel_r_reg[2]_49 ,
    \rd_mux_sel_r_reg[2]_50 ,
    \rd_mux_sel_r_reg[2]_51 ,
    \rd_mux_sel_r_reg[2]_52 ,
    \rd_mux_sel_r_reg[2]_53 ,
    \rd_mux_sel_r_reg[2]_54 ,
    \rd_mux_sel_r_reg[2]_55 ,
    \rd_mux_sel_r_reg[2]_56 ,
    \rd_mux_sel_r_reg[2]_57 ,
    \rd_mux_sel_r_reg[2]_58 ,
    \rd_mux_sel_r_reg[2]_59 ,
    \rd_mux_sel_r_reg[2]_60 ,
    \rd_mux_sel_r_reg[2]_61 ,
    \rd_mux_sel_r_reg[2]_62 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ,
    \rd_ptr_reg[3] ,
    D,
    \calib_sel_reg[1] ,
    Q,
    \entry_cnt_reg[4] ,
    \input_[9].iserdes_dq_.iserdesdq ,
    mem_dq_in,
    idelay_inc,
    LD0_7,
    A_rst_primitives,
    CLKB0_7,
    phaser_ctl_bus,
    \pi_dqs_found_lanes_r1_reg[1] ,
    \pi_dqs_found_lanes_r1_reg[1]_0 ,
    \pi_dqs_found_lanes_r1_reg[1]_1 ,
    \pi_dqs_found_lanes_r1_reg[1]_2 ,
    freq_refclk,
    mem_refclk,
    mem_dqs_in,
    ififo_rst_reg_0,
    sync_pulse,
    PCENABLECALIB,
    \pi_dqs_found_lanes_r1_reg[1]_3 ,
    \po_counter_read_val_reg[8] ,
    \po_counter_read_val_reg[8]_0 ,
    \po_counter_read_val_reg[8]_1 ,
    \my_empty_reg[7] ,
    \my_empty_reg[7]_0 ,
    \my_empty_reg[7]_1 ,
    \my_empty_reg[7]_2 ,
    \my_empty_reg[7]_3 ,
    \my_empty_reg[7]_4 ,
    \my_empty_reg[7]_5 ,
    \my_empty_reg[7]_6 ,
    phy_if_reset,
    \my_full_reg[1] ,
    my_empty,
    \wr_ptr[1]_i_2__0 ,
    phy_data_wr_en,
    rst_r4,
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0] ,
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ,
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1 ,
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_2 ,
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1 ,
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2] ,
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ,
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1 ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 ,
    \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ,
    \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0 ,
    \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_1 ,
    \gen_mux_rd[5].mux_rd_rise0_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_1 ,
    \gen_mux_rd[6].mux_rd_rise0_r_reg[6] ,
    \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0 ,
    \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_1 ,
    \gen_mux_rd[7].mux_rd_rise0_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_1 ,
    \gen_mux_rd[0].mux_rd_fall0_r_reg[0] ,
    \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0 ,
    \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_1 ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 ,
    \gen_mux_rd[2].mux_rd_fall0_r_reg[2] ,
    \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0 ,
    \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_1 ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 ,
    \gen_mux_rd[4].mux_rd_fall0_r_reg[4] ,
    \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0 ,
    \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_1 ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 ,
    \gen_mux_rd[6].mux_rd_fall0_r_reg[6] ,
    \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0 ,
    \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_1 ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 ,
    \gen_mux_rd[0].mux_rd_rise1_r_reg[0] ,
    \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0 ,
    \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_1 ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 ,
    \gen_mux_rd[2].mux_rd_rise1_r_reg[2] ,
    \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0 ,
    \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_1 ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 ,
    \gen_mux_rd[4].mux_rd_rise1_r_reg[4] ,
    \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0 ,
    \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_1 ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 ,
    \gen_mux_rd[6].mux_rd_rise1_r_reg[6] ,
    \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0 ,
    \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_1 ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 ,
    \gen_mux_rd[0].mux_rd_fall1_r_reg[0] ,
    \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0 ,
    \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_1 ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 ,
    \gen_mux_rd[2].mux_rd_fall1_r_reg[2] ,
    \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0 ,
    \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_1 ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 ,
    \gen_mux_rd[4].mux_rd_fall1_r_reg[4] ,
    \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0 ,
    \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_1 ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 ,
    \gen_mux_rd[6].mux_rd_fall1_r_reg[6] ,
    \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0 ,
    \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_1 ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 ,
    \gen_mux_rd[0].mux_rd_rise2_r_reg[0] ,
    \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0 ,
    \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_1 ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 ,
    \gen_mux_rd[2].mux_rd_rise2_r_reg[2] ,
    \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0 ,
    \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_1 ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 ,
    \gen_mux_rd[4].mux_rd_rise2_r_reg[4] ,
    \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0 ,
    \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_1 ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 ,
    \gen_mux_rd[6].mux_rd_rise2_r_reg[6] ,
    \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0 ,
    \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_1 ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 ,
    \gen_mux_rd[0].mux_rd_fall2_r_reg[0] ,
    \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0 ,
    \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_1 ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 ,
    \gen_mux_rd[2].mux_rd_fall2_r_reg[2] ,
    \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0 ,
    \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_1 ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 ,
    \gen_mux_rd[4].mux_rd_fall2_r_reg[4] ,
    \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0 ,
    \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_1 ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 ,
    \gen_mux_rd[6].mux_rd_fall2_r_reg[6] ,
    \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0 ,
    \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_1 ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 ,
    \gen_mux_rd[0].mux_rd_rise3_r_reg[0] ,
    \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0 ,
    \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_1 ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 ,
    \gen_mux_rd[2].mux_rd_rise3_r_reg[2] ,
    \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0 ,
    \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_1 ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 ,
    \gen_mux_rd[4].mux_rd_rise3_r_reg[4] ,
    \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0 ,
    \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_1 ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 ,
    \gen_mux_rd[6].mux_rd_rise3_r_reg[6] ,
    \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0 ,
    \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_1 ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 ,
    \gen_mux_rd[0].mux_rd_fall3_r_reg[0] ,
    \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0 ,
    \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_1 ,
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1 ,
    \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ,
    \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 ,
    \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_1 ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 ,
    \gen_mux_rd[4].mux_rd_fall3_r_reg[4] ,
    \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0 ,
    \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_1 ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 ,
    \gen_mux_rd[6].mux_rd_fall3_r_reg[6] ,
    \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0 ,
    \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_1 ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 ,
    out_fifo_0,
    out_fifo_1,
    out_fifo_2,
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ,
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_3 ,
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_2 ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_2 ,
    \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_2 ,
    \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_2 ,
    \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_2 ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_2 ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_2 ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_2 ,
    \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_2 ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_2 ,
    \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_2 ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_2 ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_2 ,
    \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_2 ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_2 ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_2 ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_2 ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_2 ,
    \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_2 ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_2 ,
    \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_2 ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_2 ,
    \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_2 ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_2 ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_2 ,
    \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_2 ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_2 ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_2 ,
    \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_2 ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_2 ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_2 ,
    \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_2 ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_2 ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_2 ,
    \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_2 ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_2 ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_2 ,
    \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_2 ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_2 ,
    \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_2 ,
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_2 ,
    \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_2 ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_2 ,
    \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_2 ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_2 ,
    \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_2 ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_2 ,
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_3 ,
    \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_2 ,
    \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_2 ,
    \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_2 ,
    \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_2 ,
    \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_2 ,
    \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_2 ,
    \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_2 ,
    \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_2 ,
    \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_2 ,
    \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_2 ,
    \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_2 ,
    \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_2 ,
    \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_2 ,
    \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_2 ,
    out_fifo_i_75__5,
    COUNTERREADVAL,
    \pi_counter_read_val_reg[5] ,
    calib_sel,
    \pi_counter_read_val_reg[5]_0 ,
    \po_counter_read_val_reg[8]_2 ,
    \po_counter_read_val_reg[8]_3 ,
    \po_counter_read_val_reg[8]_4 );
  output out_dqs_5;
  output ts_dqs_5;
  output A_rst_primitives_reg;
  output [8:0]mem_dq_out;
  output [8:0]mem_dq_ts;
  output [0:0]in0;
  output A_rst_primitives_reg_0;
  output B_rclk;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  output \my_empty_reg[4] ;
  output idelay_ld_rst_0;
  output [0:0]\my_empty_reg[4]_0 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;
  output \my_empty_reg[1] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ;
  output \rd_mux_sel_r_reg[2] ;
  output \rd_mux_sel_r_reg[2]_0 ;
  output \rd_mux_sel_r_reg[2]_1 ;
  output \rd_mux_sel_r_reg[2]_2 ;
  output \rd_mux_sel_r_reg[2]_3 ;
  output \rd_mux_sel_r_reg[2]_4 ;
  output \rd_mux_sel_r_reg[2]_5 ;
  output \rd_mux_sel_r_reg[2]_6 ;
  output \rd_mux_sel_r_reg[2]_7 ;
  output \rd_mux_sel_r_reg[2]_8 ;
  output \rd_mux_sel_r_reg[2]_9 ;
  output \rd_mux_sel_r_reg[2]_10 ;
  output \rd_mux_sel_r_reg[2]_11 ;
  output \rd_mux_sel_r_reg[2]_12 ;
  output \rd_mux_sel_r_reg[2]_13 ;
  output \rd_mux_sel_r_reg[2]_14 ;
  output \rd_mux_sel_r_reg[2]_15 ;
  output \rd_mux_sel_r_reg[2]_16 ;
  output \rd_mux_sel_r_reg[2]_17 ;
  output \rd_mux_sel_r_reg[2]_18 ;
  output \rd_mux_sel_r_reg[2]_19 ;
  output \rd_mux_sel_r_reg[2]_20 ;
  output \rd_mux_sel_r_reg[2]_21 ;
  output \rd_mux_sel_r_reg[2]_22 ;
  output \rd_mux_sel_r_reg[2]_23 ;
  output \rd_mux_sel_r_reg[2]_24 ;
  output \rd_mux_sel_r_reg[2]_25 ;
  output \rd_mux_sel_r_reg[2]_26 ;
  output \rd_mux_sel_r_reg[2]_27 ;
  output \rd_mux_sel_r_reg[2]_28 ;
  output \rd_mux_sel_r_reg[2]_29 ;
  output \rd_mux_sel_r_reg[2]_30 ;
  output \rd_mux_sel_r_reg[2]_31 ;
  output \rd_mux_sel_r_reg[2]_32 ;
  output \rd_mux_sel_r_reg[2]_33 ;
  output \rd_mux_sel_r_reg[2]_34 ;
  output \rd_mux_sel_r_reg[2]_35 ;
  output \rd_mux_sel_r_reg[2]_36 ;
  output \rd_mux_sel_r_reg[2]_37 ;
  output \rd_mux_sel_r_reg[2]_38 ;
  output \rd_mux_sel_r_reg[2]_39 ;
  output \rd_mux_sel_r_reg[2]_40 ;
  output \rd_mux_sel_r_reg[2]_41 ;
  output \rd_mux_sel_r_reg[2]_42 ;
  output \rd_mux_sel_r_reg[2]_43 ;
  output \rd_mux_sel_r_reg[2]_44 ;
  output \rd_mux_sel_r_reg[2]_45 ;
  output \rd_mux_sel_r_reg[2]_46 ;
  output \rd_mux_sel_r_reg[2]_47 ;
  output \rd_mux_sel_r_reg[2]_48 ;
  output \rd_mux_sel_r_reg[2]_49 ;
  output \rd_mux_sel_r_reg[2]_50 ;
  output \rd_mux_sel_r_reg[2]_51 ;
  output \rd_mux_sel_r_reg[2]_52 ;
  output \rd_mux_sel_r_reg[2]_53 ;
  output \rd_mux_sel_r_reg[2]_54 ;
  output \rd_mux_sel_r_reg[2]_55 ;
  output \rd_mux_sel_r_reg[2]_56 ;
  output \rd_mux_sel_r_reg[2]_57 ;
  output \rd_mux_sel_r_reg[2]_58 ;
  output \rd_mux_sel_r_reg[2]_59 ;
  output \rd_mux_sel_r_reg[2]_60 ;
  output \rd_mux_sel_r_reg[2]_61 ;
  output \rd_mux_sel_r_reg[2]_62 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;
  output [63:0]\rd_ptr_reg[3] ;
  output [5:0]D;
  output [8:0]\calib_sel_reg[1] ;
  output [2:0]Q;
  input \entry_cnt_reg[4] ;
  input \input_[9].iserdes_dq_.iserdesdq ;
  input [7:0]mem_dq_in;
  input idelay_inc;
  input LD0_7;
  input A_rst_primitives;
  input CLKB0_7;
  input [3:0]phaser_ctl_bus;
  input \pi_dqs_found_lanes_r1_reg[1] ;
  input \pi_dqs_found_lanes_r1_reg[1]_0 ;
  input \pi_dqs_found_lanes_r1_reg[1]_1 ;
  input \pi_dqs_found_lanes_r1_reg[1]_2 ;
  input freq_refclk;
  input mem_refclk;
  input [0:0]mem_dqs_in;
  input ififo_rst_reg_0;
  input sync_pulse;
  input [1:0]PCENABLECALIB;
  input [5:0]\pi_dqs_found_lanes_r1_reg[1]_3 ;
  input \po_counter_read_val_reg[8] ;
  input \po_counter_read_val_reg[8]_0 ;
  input \po_counter_read_val_reg[8]_1 ;
  input [7:0]\my_empty_reg[7] ;
  input [7:0]\my_empty_reg[7]_0 ;
  input [7:0]\my_empty_reg[7]_1 ;
  input [7:0]\my_empty_reg[7]_2 ;
  input [7:0]\my_empty_reg[7]_3 ;
  input [7:0]\my_empty_reg[7]_4 ;
  input [7:0]\my_empty_reg[7]_5 ;
  input [7:0]\my_empty_reg[7]_6 ;
  input phy_if_reset;
  input \my_full_reg[1] ;
  input [0:0]my_empty;
  input \wr_ptr[1]_i_2__0 ;
  input phy_data_wr_en;
  input rst_r4;
  input [1:0]\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;
  input \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ;
  input \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1 ;
  input \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_2 ;
  input \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;
  input \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ;
  input \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1 ;
  input \gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;
  input \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ;
  input \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1 ;
  input \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  input \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ;
  input \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 ;
  input \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;
  input \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0 ;
  input \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_1 ;
  input \gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;
  input \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0 ;
  input \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_1 ;
  input \gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;
  input \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0 ;
  input \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_1 ;
  input \gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;
  input \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0 ;
  input \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_1 ;
  input \gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;
  input \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0 ;
  input \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_1 ;
  input \gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  input \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ;
  input \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 ;
  input \gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;
  input \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0 ;
  input \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_1 ;
  input \gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  input \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ;
  input \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 ;
  input \gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;
  input \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0 ;
  input \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_1 ;
  input \gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  input \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ;
  input \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 ;
  input \gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;
  input \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0 ;
  input \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_1 ;
  input \gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  input \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ;
  input \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 ;
  input \gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;
  input \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0 ;
  input \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_1 ;
  input \gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  input \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ;
  input \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 ;
  input \gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;
  input \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0 ;
  input \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_1 ;
  input \gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  input \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ;
  input \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 ;
  input \gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;
  input \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0 ;
  input \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_1 ;
  input \gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  input \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ;
  input \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 ;
  input \gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;
  input \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0 ;
  input \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_1 ;
  input \gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  input \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ;
  input \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 ;
  input \gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;
  input \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0 ;
  input \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_1 ;
  input \gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  input \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ;
  input \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 ;
  input \gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;
  input \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0 ;
  input \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_1 ;
  input \gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  input \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ;
  input \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 ;
  input \gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;
  input \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0 ;
  input \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_1 ;
  input \gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  input \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ;
  input \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 ;
  input \gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;
  input \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0 ;
  input \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_1 ;
  input \gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  input \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ;
  input \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 ;
  input \gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;
  input \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0 ;
  input \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_1 ;
  input \gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  input \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ;
  input \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 ;
  input \gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;
  input \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0 ;
  input \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_1 ;
  input \gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  input \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ;
  input \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 ;
  input \gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;
  input \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0 ;
  input \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_1 ;
  input \gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  input \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ;
  input \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 ;
  input \gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;
  input \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0 ;
  input \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_1 ;
  input \gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  input \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ;
  input \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 ;
  input \gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;
  input \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0 ;
  input \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_1 ;
  input \gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  input \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ;
  input \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 ;
  input \gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;
  input \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0 ;
  input \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_1 ;
  input \gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  input \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ;
  input \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 ;
  input \gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;
  input \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0 ;
  input \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_1 ;
  input \gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  input \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ;
  input \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 ;
  input \gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;
  input \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0 ;
  input \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_1 ;
  input \gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  input \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ;
  input \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 ;
  input \gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;
  input \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0 ;
  input \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_1 ;
  input \gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  input \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ;
  input \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 ;
  input \gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;
  input \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0 ;
  input \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_1 ;
  input \gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  input \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ;
  input \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 ;
  input \gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;
  input \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0 ;
  input \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_1 ;
  input \gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  input \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ;
  input \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 ;
  input \gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;
  input \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0 ;
  input \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_1 ;
  input \gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  input \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ;
  input \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 ;
  input \gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;
  input \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0 ;
  input \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_1 ;
  input \gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  input \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ;
  input \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1 ;
  input \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  input \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 ;
  input \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_1 ;
  input \gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  input \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ;
  input \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 ;
  input \gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;
  input \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0 ;
  input \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_1 ;
  input \gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  input \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ;
  input \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 ;
  input \gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;
  input \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0 ;
  input \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_1 ;
  input \gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  input \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ;
  input \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 ;
  input out_fifo_0;
  input [7:0]out_fifo_1;
  input out_fifo_2;
  input \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ;
  input \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_3 ;
  input \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_2 ;
  input \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_2 ;
  input \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_2 ;
  input \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_2 ;
  input \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_2 ;
  input \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_2 ;
  input \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_2 ;
  input \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_2 ;
  input \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_2 ;
  input \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_2 ;
  input \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 ;
  input \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_2 ;
  input \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_2 ;
  input \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_2 ;
  input \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_2 ;
  input \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_2 ;
  input \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_2 ;
  input \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_2 ;
  input \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_2 ;
  input \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_2 ;
  input \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_2 ;
  input \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_2 ;
  input \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_2 ;
  input \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_2 ;
  input \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_2 ;
  input \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_2 ;
  input \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_2 ;
  input \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_2 ;
  input \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_2 ;
  input \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_2 ;
  input \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_2 ;
  input \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_2 ;
  input \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_2 ;
  input \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_2 ;
  input \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_2 ;
  input \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_2 ;
  input \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_2 ;
  input \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_2 ;
  input \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_2 ;
  input \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_2 ;
  input \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_2 ;
  input \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_2 ;
  input \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_2 ;
  input \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_2 ;
  input \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_2 ;
  input \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_2 ;
  input \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_2 ;
  input \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_2 ;
  input \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_3 ;
  input \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_2 ;
  input \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_2 ;
  input \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_2 ;
  input \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_2 ;
  input \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_2 ;
  input \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_2 ;
  input \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_2 ;
  input \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_2 ;
  input \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_2 ;
  input \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_2 ;
  input \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_2 ;
  input \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_2 ;
  input \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_2 ;
  input \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_2 ;
  input [71:0]out_fifo_i_75__5;
  input [5:0]COUNTERREADVAL;
  input [5:0]\pi_counter_read_val_reg[5] ;
  input [1:0]calib_sel;
  input [5:0]\pi_counter_read_val_reg[5]_0 ;
  input [8:0]\po_counter_read_val_reg[8]_2 ;
  input [8:0]\po_counter_read_val_reg[8]_3 ;
  input [8:0]\po_counter_read_val_reg[8]_4 ;

  wire A_rst_primitives;
  wire A_rst_primitives_reg;
  wire A_rst_primitives_reg_0;
  wire [5:0]B_pi_counter_read_val;
  wire [8:0]B_po_counter_read_val;
  wire B_rclk;
  wire CLKB0_7;
  wire [5:0]COUNTERREADVAL;
  wire [5:0]D;
  wire LD0_7;
  wire [1:0]PCENABLECALIB;
  wire [2:0]Q;
  wire [1:0]calib_sel;
  wire [8:0]\calib_sel_reg[1] ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ;
  wire \entry_cnt_reg[4] ;
  wire freq_refclk;
  wire \gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0 ;
  wire \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_1 ;
  wire \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_2 ;
  wire \gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0 ;
  wire \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_1 ;
  wire \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_2 ;
  wire \gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0 ;
  wire \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_1 ;
  wire \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_2 ;
  wire \gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0 ;
  wire \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_1 ;
  wire \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_2 ;
  wire [1:0]\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ;
  wire \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1 ;
  wire \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_2 ;
  wire \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_3 ;
  wire \gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0 ;
  wire \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_1 ;
  wire \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 ;
  wire \gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0 ;
  wire \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_1 ;
  wire \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_2 ;
  wire \gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0 ;
  wire \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_1 ;
  wire \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_2 ;
  wire \gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 ;
  wire \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_2 ;
  wire \gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 ;
  wire \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_2 ;
  wire \gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 ;
  wire \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_2 ;
  wire \gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1 ;
  wire \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_2 ;
  wire \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1 ;
  wire \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ;
  wire \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_3 ;
  wire \gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 ;
  wire \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_2 ;
  wire \gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 ;
  wire \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_2 ;
  wire \gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 ;
  wire \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_2 ;
  wire \gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0 ;
  wire \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_1 ;
  wire \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_2 ;
  wire \gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0 ;
  wire \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_1 ;
  wire \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_2 ;
  wire \gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0 ;
  wire \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_1 ;
  wire \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_2 ;
  wire \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 ;
  wire \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_1 ;
  wire \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_2 ;
  wire \gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ;
  wire \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1 ;
  wire \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_2 ;
  wire \gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0 ;
  wire \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_1 ;
  wire \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_2 ;
  wire \gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0 ;
  wire \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_1 ;
  wire \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_2 ;
  wire \gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0 ;
  wire \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_1 ;
  wire \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_2 ;
  wire \gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 ;
  wire \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_2 ;
  wire \gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 ;
  wire \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_2 ;
  wire \gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 ;
  wire \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_2 ;
  wire \gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 ;
  wire \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_2 ;
  wire \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 ;
  wire \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_2 ;
  wire \gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 ;
  wire \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_2 ;
  wire \gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 ;
  wire \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_2 ;
  wire \gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 ;
  wire \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_2 ;
  wire \gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0 ;
  wire \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_1 ;
  wire \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_2 ;
  wire \gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0 ;
  wire \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_1 ;
  wire \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_2 ;
  wire \gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0 ;
  wire \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_1 ;
  wire \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_2 ;
  wire \gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0 ;
  wire \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_1 ;
  wire \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_2 ;
  wire \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0 ;
  wire \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_1 ;
  wire \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_2 ;
  wire \gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0 ;
  wire \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_1 ;
  wire \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_2 ;
  wire \gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0 ;
  wire \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_1 ;
  wire \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_2 ;
  wire \gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0 ;
  wire \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_1 ;
  wire \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_2 ;
  wire \gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 ;
  wire \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_2 ;
  wire \gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 ;
  wire \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_2 ;
  wire \gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 ;
  wire \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_2 ;
  wire \gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 ;
  wire \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_2 ;
  wire \gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_1 ;
  wire \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_2 ;
  wire \gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 ;
  wire \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_2 ;
  wire \gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 ;
  wire \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_2 ;
  wire \gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 ;
  wire \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_2 ;
  wire \gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0 ;
  wire \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_1 ;
  wire \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_2 ;
  wire \gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0 ;
  wire \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_1 ;
  wire \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_2 ;
  wire \gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0 ;
  wire \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_1 ;
  wire \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_2 ;
  wire \gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0 ;
  wire \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_1 ;
  wire \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_2 ;
  wire \gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0 ;
  wire \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_1 ;
  wire \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_2 ;
  wire \gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0 ;
  wire \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_1 ;
  wire \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_2 ;
  wire \gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0 ;
  wire \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_1 ;
  wire \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_2 ;
  wire \gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0 ;
  wire \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_1 ;
  wire \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_2 ;
  wire \gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 ;
  wire \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_2 ;
  wire \gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 ;
  wire \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_2 ;
  wire \gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 ;
  wire \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_2 ;
  wire \gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 ;
  wire \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_2 ;
  wire \gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_1 ;
  wire \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_2 ;
  wire \gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 ;
  wire \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_2 ;
  wire \gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 ;
  wire \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_2 ;
  wire \gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 ;
  wire \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_2 ;
  wire idelay_inc;
  wire idelay_ld_rst_0;
  wire [3:0]if_d2;
  wire [3:0]if_d3;
  wire [3:0]if_d4;
  wire [3:0]if_d5;
  wire [3:0]if_d6;
  wire [3:0]if_d7;
  wire [3:0]if_d8;
  wire [3:0]if_d9;
  wire if_empty_;
  wire ififo_rst;
  wire ififo_rst_reg_0;
  wire ififo_wr_enable;
  wire [0:0]in0;
  wire \in_fifo_gen.in_fifo_n_0 ;
  wire \in_fifo_gen.in_fifo_n_1 ;
  wire \in_fifo_gen.in_fifo_n_3 ;
  wire \input_[9].iserdes_dq_.iserdesdq ;
  wire iserdes_clkdiv;
  wire [7:0]mem_dq_in;
  wire [8:0]mem_dq_out;
  wire [8:0]mem_dq_ts;
  wire [0:0]mem_dqs_in;
  wire mem_refclk;
  wire [0:0]my_empty;
  wire \my_empty_reg[1] ;
  wire \my_empty_reg[4] ;
  wire [0:0]\my_empty_reg[4]_0 ;
  wire [7:0]\my_empty_reg[7] ;
  wire [7:0]\my_empty_reg[7]_0 ;
  wire [7:0]\my_empty_reg[7]_1 ;
  wire [7:0]\my_empty_reg[7]_2 ;
  wire [7:0]\my_empty_reg[7]_3 ;
  wire [7:0]\my_empty_reg[7]_4 ;
  wire [7:0]\my_empty_reg[7]_5 ;
  wire [7:0]\my_empty_reg[7]_6 ;
  wire \my_full_reg[1] ;
  wire [7:0]of_d1;
  wire [39:0]of_dqbus;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ;
  wire ofifo_rst;
  wire oserdes_clk;
  wire oserdes_clk_delayed;
  wire oserdes_clkdiv;
  wire [1:0]oserdes_dq_ts;
  wire [1:0]oserdes_dqs;
  wire [1:0]oserdes_dqs_ts;
  wire out_dqs_5;
  wire out_fifo_0;
  wire [7:0]out_fifo_1;
  wire out_fifo_2;
  wire [71:0]out_fifo_i_75__5;
  wire out_fifo_n_0;
  wire out_fifo_n_1;
  wire out_fifo_n_2;
  wire out_fifo_n_3;
  wire [3:0]phaser_ctl_bus;
  wire \phaser_in_gen.phaser_in_n_1 ;
  wire \phaser_in_gen.phaser_in_n_2 ;
  wire \phaser_in_gen.phaser_in_n_5 ;
  wire phaser_out_n_0;
  wire phaser_out_n_1;
  wire phy_data_wr_en;
  wire phy_if_reset;
  wire [5:0]\pi_counter_read_val_reg[5] ;
  wire [5:0]\pi_counter_read_val_reg[5]_0 ;
  wire \pi_dqs_found_lanes_r1_reg[1] ;
  wire \pi_dqs_found_lanes_r1_reg[1]_0 ;
  wire \pi_dqs_found_lanes_r1_reg[1]_1 ;
  wire \pi_dqs_found_lanes_r1_reg[1]_2 ;
  wire [5:0]\pi_dqs_found_lanes_r1_reg[1]_3 ;
  wire \po_counter_read_val_reg[8] ;
  wire \po_counter_read_val_reg[8]_0 ;
  wire \po_counter_read_val_reg[8]_1 ;
  wire [8:0]\po_counter_read_val_reg[8]_2 ;
  wire [8:0]\po_counter_read_val_reg[8]_3 ;
  wire [8:0]\po_counter_read_val_reg[8]_4 ;
  wire po_oserdes_rst;
  wire po_rd_enable;
  wire [79:0]rd_data;
  wire [79:12]rd_data_r;
  wire \rd_mux_sel_r_reg[2] ;
  wire \rd_mux_sel_r_reg[2]_0 ;
  wire \rd_mux_sel_r_reg[2]_1 ;
  wire \rd_mux_sel_r_reg[2]_10 ;
  wire \rd_mux_sel_r_reg[2]_11 ;
  wire \rd_mux_sel_r_reg[2]_12 ;
  wire \rd_mux_sel_r_reg[2]_13 ;
  wire \rd_mux_sel_r_reg[2]_14 ;
  wire \rd_mux_sel_r_reg[2]_15 ;
  wire \rd_mux_sel_r_reg[2]_16 ;
  wire \rd_mux_sel_r_reg[2]_17 ;
  wire \rd_mux_sel_r_reg[2]_18 ;
  wire \rd_mux_sel_r_reg[2]_19 ;
  wire \rd_mux_sel_r_reg[2]_2 ;
  wire \rd_mux_sel_r_reg[2]_20 ;
  wire \rd_mux_sel_r_reg[2]_21 ;
  wire \rd_mux_sel_r_reg[2]_22 ;
  wire \rd_mux_sel_r_reg[2]_23 ;
  wire \rd_mux_sel_r_reg[2]_24 ;
  wire \rd_mux_sel_r_reg[2]_25 ;
  wire \rd_mux_sel_r_reg[2]_26 ;
  wire \rd_mux_sel_r_reg[2]_27 ;
  wire \rd_mux_sel_r_reg[2]_28 ;
  wire \rd_mux_sel_r_reg[2]_29 ;
  wire \rd_mux_sel_r_reg[2]_3 ;
  wire \rd_mux_sel_r_reg[2]_30 ;
  wire \rd_mux_sel_r_reg[2]_31 ;
  wire \rd_mux_sel_r_reg[2]_32 ;
  wire \rd_mux_sel_r_reg[2]_33 ;
  wire \rd_mux_sel_r_reg[2]_34 ;
  wire \rd_mux_sel_r_reg[2]_35 ;
  wire \rd_mux_sel_r_reg[2]_36 ;
  wire \rd_mux_sel_r_reg[2]_37 ;
  wire \rd_mux_sel_r_reg[2]_38 ;
  wire \rd_mux_sel_r_reg[2]_39 ;
  wire \rd_mux_sel_r_reg[2]_4 ;
  wire \rd_mux_sel_r_reg[2]_40 ;
  wire \rd_mux_sel_r_reg[2]_41 ;
  wire \rd_mux_sel_r_reg[2]_42 ;
  wire \rd_mux_sel_r_reg[2]_43 ;
  wire \rd_mux_sel_r_reg[2]_44 ;
  wire \rd_mux_sel_r_reg[2]_45 ;
  wire \rd_mux_sel_r_reg[2]_46 ;
  wire \rd_mux_sel_r_reg[2]_47 ;
  wire \rd_mux_sel_r_reg[2]_48 ;
  wire \rd_mux_sel_r_reg[2]_49 ;
  wire \rd_mux_sel_r_reg[2]_5 ;
  wire \rd_mux_sel_r_reg[2]_50 ;
  wire \rd_mux_sel_r_reg[2]_51 ;
  wire \rd_mux_sel_r_reg[2]_52 ;
  wire \rd_mux_sel_r_reg[2]_53 ;
  wire \rd_mux_sel_r_reg[2]_54 ;
  wire \rd_mux_sel_r_reg[2]_55 ;
  wire \rd_mux_sel_r_reg[2]_56 ;
  wire \rd_mux_sel_r_reg[2]_57 ;
  wire \rd_mux_sel_r_reg[2]_58 ;
  wire \rd_mux_sel_r_reg[2]_59 ;
  wire \rd_mux_sel_r_reg[2]_6 ;
  wire \rd_mux_sel_r_reg[2]_60 ;
  wire \rd_mux_sel_r_reg[2]_61 ;
  wire \rd_mux_sel_r_reg[2]_62 ;
  wire \rd_mux_sel_r_reg[2]_7 ;
  wire \rd_mux_sel_r_reg[2]_8 ;
  wire \rd_mux_sel_r_reg[2]_9 ;
  wire [63:0]\rd_ptr_reg[3] ;
  wire rst_r4;
  wire sync_pulse;
  wire ts_dqs_5;
  wire \wr_ptr[1]_i_2__0 ;
  wire [7:4]\NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED ;
  wire [7:4]\NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED ;
  wire [7:4]NLW_out_fifo_Q5_UNCONNECTED;
  wire [7:4]NLW_out_fifo_Q6_UNCONNECTED;
  wire NLW_phaser_out_PHASEREFCLK_UNCONNECTED;

  mig_mig_7series_v4_2_ddr_byte_group_io__parameterized0_35 ddr_byte_group_io
       (.A_rst_primitives(A_rst_primitives),
        .CLKB0_7(CLKB0_7),
        .CTSBUS(oserdes_dqs_ts[0]),
        .D2(if_d2),
        .D3(if_d3),
        .D4(if_d4),
        .D5(if_d5),
        .D6(if_d6),
        .D7(if_d7),
        .D8(if_d8),
        .D9(if_d9),
        .DQSBUS(oserdes_dqs),
        .DTSBUS(oserdes_dq_ts),
        .LD0_7(LD0_7),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (A_rst_primitives_reg),
        .idelay_inc(idelay_inc),
        .idelay_ld_rst_0(idelay_ld_rst_0),
        .idelay_ld_rst_reg_0(\entry_cnt_reg[4] ),
        .\input_[9].iserdes_dq_.iserdesdq_0 (\input_[9].iserdes_dq_.iserdesdq ),
        .iserdes_clkdiv(iserdes_clkdiv),
        .mem_dq_in(mem_dq_in),
        .mem_dq_out(mem_dq_out),
        .mem_dq_ts(mem_dq_ts),
        .of_dqbus(of_dqbus[39:4]),
        .oserdes_clk(oserdes_clk),
        .oserdes_clk_delayed(oserdes_clk_delayed),
        .oserdes_clkdiv(oserdes_clkdiv),
        .out_dqs_5(out_dqs_5),
        .po_oserdes_rst(po_oserdes_rst),
        .rst_r4(rst_r4),
        .ts_dqs_5(ts_dqs_5));
  (* syn_maxfan = "3" *) 
  FDRE \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(if_empty_),
        .Q(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[12]),
        .Q(rd_data_r[12]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[13]),
        .Q(rd_data_r[13]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[14]),
        .Q(rd_data_r[14]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[15]),
        .Q(rd_data_r[15]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[16]),
        .Q(rd_data_r[16]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[17]),
        .Q(rd_data_r[17]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[18]),
        .Q(rd_data_r[18]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[19]),
        .Q(rd_data_r[19]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[20]),
        .Q(rd_data_r[20]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[21]),
        .Q(rd_data_r[21]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[22]),
        .Q(rd_data_r[22]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[23]),
        .Q(rd_data_r[23]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[24]),
        .Q(rd_data_r[24]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[25]),
        .Q(rd_data_r[25]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[26]),
        .Q(rd_data_r[26]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[27]),
        .Q(rd_data_r[27]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[28]),
        .Q(rd_data_r[28]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[29]),
        .Q(rd_data_r[29]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[30]),
        .Q(rd_data_r[30]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[31]),
        .Q(rd_data_r[31]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[32]),
        .Q(rd_data_r[32]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[33]),
        .Q(rd_data_r[33]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[34]),
        .Q(rd_data_r[34]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[35]),
        .Q(rd_data_r[35]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[36]),
        .Q(rd_data_r[36]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[37]),
        .Q(rd_data_r[37]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[38]),
        .Q(rd_data_r[38]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[39]),
        .Q(rd_data_r[39]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[40]),
        .Q(rd_data_r[40]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[41]),
        .Q(rd_data_r[41]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[42]),
        .Q(rd_data_r[42]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[43]),
        .Q(rd_data_r[43]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[44]),
        .Q(rd_data_r[44]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[45]),
        .Q(rd_data_r[45]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[46]),
        .Q(rd_data_r[46]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[47]),
        .Q(rd_data_r[47]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[48]),
        .Q(rd_data_r[48]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[49]),
        .Q(rd_data_r[49]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[50]),
        .Q(rd_data_r[50]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[51]),
        .Q(rd_data_r[51]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[52]),
        .Q(rd_data_r[52]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[53]),
        .Q(rd_data_r[53]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[54]),
        .Q(rd_data_r[54]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[55]),
        .Q(rd_data_r[55]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[56]),
        .Q(rd_data_r[56]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[57]),
        .Q(rd_data_r[57]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[58]),
        .Q(rd_data_r[58]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[59]),
        .Q(rd_data_r[59]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[60]),
        .Q(rd_data_r[60]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[61]),
        .Q(rd_data_r[61]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[62]),
        .Q(rd_data_r[62]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[63]),
        .Q(rd_data_r[63]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[64]),
        .Q(rd_data_r[64]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[65]),
        .Q(rd_data_r[65]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[66]),
        .Q(rd_data_r[66]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[67]),
        .Q(rd_data_r[67]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[68]),
        .Q(rd_data_r[68]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[69]),
        .Q(rd_data_r[69]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[70]),
        .Q(rd_data_r[70]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[71]),
        .Q(rd_data_r[71]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[72]),
        .Q(rd_data_r[72]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[73]),
        .Q(rd_data_r[73]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[74]),
        .Q(rd_data_r[74]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[75]),
        .Q(rd_data_r[75]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[76]),
        .Q(rd_data_r[76]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[77]),
        .Q(rd_data_r[77]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[78]),
        .Q(rd_data_r[78]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[79]),
        .Q(rd_data_r[79]),
        .R(1'b0));
  mig_mig_7series_v4_2_ddr_if_post_fifo_36 \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo 
       (.Q(rd_data_r),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ),
        .\gen_mux_rd[0].mux_rd_fall0_r_reg[0] (\gen_mux_rd[0].mux_rd_fall0_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0 (\gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0 ),
        .\gen_mux_rd[0].mux_rd_fall0_r_reg[0]_1 (\gen_mux_rd[0].mux_rd_fall0_r_reg[0]_1 ),
        .\gen_mux_rd[0].mux_rd_fall0_r_reg[0]_2 (\gen_mux_rd[0].mux_rd_fall0_r_reg[0]_2 ),
        .\gen_mux_rd[0].mux_rd_fall1_r_reg[0] (\gen_mux_rd[0].mux_rd_fall1_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0 (\gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0 ),
        .\gen_mux_rd[0].mux_rd_fall1_r_reg[0]_1 (\gen_mux_rd[0].mux_rd_fall1_r_reg[0]_1 ),
        .\gen_mux_rd[0].mux_rd_fall1_r_reg[0]_2 (\gen_mux_rd[0].mux_rd_fall1_r_reg[0]_2 ),
        .\gen_mux_rd[0].mux_rd_fall2_r_reg[0] (\gen_mux_rd[0].mux_rd_fall2_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0 (\gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0 ),
        .\gen_mux_rd[0].mux_rd_fall2_r_reg[0]_1 (\gen_mux_rd[0].mux_rd_fall2_r_reg[0]_1 ),
        .\gen_mux_rd[0].mux_rd_fall2_r_reg[0]_2 (\gen_mux_rd[0].mux_rd_fall2_r_reg[0]_2 ),
        .\gen_mux_rd[0].mux_rd_fall3_r_reg[0] (\gen_mux_rd[0].mux_rd_fall3_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0 (\gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0 ),
        .\gen_mux_rd[0].mux_rd_fall3_r_reg[0]_1 (\gen_mux_rd[0].mux_rd_fall3_r_reg[0]_1 ),
        .\gen_mux_rd[0].mux_rd_fall3_r_reg[0]_2 (\gen_mux_rd[0].mux_rd_fall3_r_reg[0]_2 ),
        .\gen_mux_rd[0].mux_rd_rise0_r_reg[0] (\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 (\gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ),
        .\gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1 (\gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1 ),
        .\gen_mux_rd[0].mux_rd_rise0_r_reg[0]_2 (\gen_mux_rd[0].mux_rd_rise0_r_reg[0]_2 ),
        .\gen_mux_rd[0].mux_rd_rise0_r_reg[0]_3 (\gen_mux_rd[0].mux_rd_rise0_r_reg[0]_3 ),
        .\gen_mux_rd[0].mux_rd_rise1_r_reg[0] (\gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0 (\gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0 ),
        .\gen_mux_rd[0].mux_rd_rise1_r_reg[0]_1 (\gen_mux_rd[0].mux_rd_rise1_r_reg[0]_1 ),
        .\gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 (\gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 ),
        .\gen_mux_rd[0].mux_rd_rise2_r_reg[0] (\gen_mux_rd[0].mux_rd_rise2_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0 (\gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0 ),
        .\gen_mux_rd[0].mux_rd_rise2_r_reg[0]_1 (\gen_mux_rd[0].mux_rd_rise2_r_reg[0]_1 ),
        .\gen_mux_rd[0].mux_rd_rise2_r_reg[0]_2 (\gen_mux_rd[0].mux_rd_rise2_r_reg[0]_2 ),
        .\gen_mux_rd[0].mux_rd_rise3_r_reg[0] (\gen_mux_rd[0].mux_rd_rise3_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0 (\gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0 ),
        .\gen_mux_rd[0].mux_rd_rise3_r_reg[0]_1 (\gen_mux_rd[0].mux_rd_rise3_r_reg[0]_1 ),
        .\gen_mux_rd[0].mux_rd_rise3_r_reg[0]_2 (\gen_mux_rd[0].mux_rd_rise3_r_reg[0]_2 ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1] (\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 (\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_2 (\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_2 ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1] (\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 (\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_2 (\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_2 ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1] (\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 (\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_2 (\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_2 ),
        .\gen_mux_rd[1].mux_rd_fall3_r_reg[1] (\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1 (\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1 ),
        .\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_2 (\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_2 ),
        .\gen_mux_rd[1].mux_rd_rise0_r_reg[1] (\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1 (\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1 ),
        .\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 (\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ),
        .\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_3 (\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_3 ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1] (\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 (\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_2 (\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_2 ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1] (\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 (\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_2 (\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_2 ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1] (\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 (\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_2 (\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_2 ),
        .\gen_mux_rd[2].mux_rd_fall0_r_reg[2] (\gen_mux_rd[2].mux_rd_fall0_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0 (\gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0 ),
        .\gen_mux_rd[2].mux_rd_fall0_r_reg[2]_1 (\gen_mux_rd[2].mux_rd_fall0_r_reg[2]_1 ),
        .\gen_mux_rd[2].mux_rd_fall0_r_reg[2]_2 (\gen_mux_rd[2].mux_rd_fall0_r_reg[2]_2 ),
        .\gen_mux_rd[2].mux_rd_fall1_r_reg[2] (\gen_mux_rd[2].mux_rd_fall1_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0 (\gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0 ),
        .\gen_mux_rd[2].mux_rd_fall1_r_reg[2]_1 (\gen_mux_rd[2].mux_rd_fall1_r_reg[2]_1 ),
        .\gen_mux_rd[2].mux_rd_fall1_r_reg[2]_2 (\gen_mux_rd[2].mux_rd_fall1_r_reg[2]_2 ),
        .\gen_mux_rd[2].mux_rd_fall2_r_reg[2] (\gen_mux_rd[2].mux_rd_fall2_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0 (\gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0 ),
        .\gen_mux_rd[2].mux_rd_fall2_r_reg[2]_1 (\gen_mux_rd[2].mux_rd_fall2_r_reg[2]_1 ),
        .\gen_mux_rd[2].mux_rd_fall2_r_reg[2]_2 (\gen_mux_rd[2].mux_rd_fall2_r_reg[2]_2 ),
        .\gen_mux_rd[2].mux_rd_fall3_r_reg[2] (\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 (\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 ),
        .\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_1 (\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_1 ),
        .\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_2 (\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_2 ),
        .\gen_mux_rd[2].mux_rd_rise0_r_reg[2] (\gen_mux_rd[2].mux_rd_rise0_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 (\gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ),
        .\gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1 (\gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1 ),
        .\gen_mux_rd[2].mux_rd_rise0_r_reg[2]_2 (\gen_mux_rd[2].mux_rd_rise0_r_reg[2]_2 ),
        .\gen_mux_rd[2].mux_rd_rise1_r_reg[2] (\gen_mux_rd[2].mux_rd_rise1_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0 (\gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0 ),
        .\gen_mux_rd[2].mux_rd_rise1_r_reg[2]_1 (\gen_mux_rd[2].mux_rd_rise1_r_reg[2]_1 ),
        .\gen_mux_rd[2].mux_rd_rise1_r_reg[2]_2 (\gen_mux_rd[2].mux_rd_rise1_r_reg[2]_2 ),
        .\gen_mux_rd[2].mux_rd_rise2_r_reg[2] (\gen_mux_rd[2].mux_rd_rise2_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0 (\gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0 ),
        .\gen_mux_rd[2].mux_rd_rise2_r_reg[2]_1 (\gen_mux_rd[2].mux_rd_rise2_r_reg[2]_1 ),
        .\gen_mux_rd[2].mux_rd_rise2_r_reg[2]_2 (\gen_mux_rd[2].mux_rd_rise2_r_reg[2]_2 ),
        .\gen_mux_rd[2].mux_rd_rise3_r_reg[2] (\gen_mux_rd[2].mux_rd_rise3_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0 (\gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0 ),
        .\gen_mux_rd[2].mux_rd_rise3_r_reg[2]_1 (\gen_mux_rd[2].mux_rd_rise3_r_reg[2]_1 ),
        .\gen_mux_rd[2].mux_rd_rise3_r_reg[2]_2 (\gen_mux_rd[2].mux_rd_rise3_r_reg[2]_2 ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3] (\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 (\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_2 (\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_2 ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3] (\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 (\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_2 (\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_2 ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3] (\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 (\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_2 (\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_2 ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3] (\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 (\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_2 (\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_2 ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3] (\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 (\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_2 (\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_2 ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3] (\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 (\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_2 (\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_2 ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3] (\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 (\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_2 (\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_2 ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3] (\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 (\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_2 (\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_2 ),
        .\gen_mux_rd[4].mux_rd_fall0_r_reg[4] (\gen_mux_rd[4].mux_rd_fall0_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0 (\gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0 ),
        .\gen_mux_rd[4].mux_rd_fall0_r_reg[4]_1 (\gen_mux_rd[4].mux_rd_fall0_r_reg[4]_1 ),
        .\gen_mux_rd[4].mux_rd_fall0_r_reg[4]_2 (\gen_mux_rd[4].mux_rd_fall0_r_reg[4]_2 ),
        .\gen_mux_rd[4].mux_rd_fall1_r_reg[4] (\gen_mux_rd[4].mux_rd_fall1_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0 (\gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0 ),
        .\gen_mux_rd[4].mux_rd_fall1_r_reg[4]_1 (\gen_mux_rd[4].mux_rd_fall1_r_reg[4]_1 ),
        .\gen_mux_rd[4].mux_rd_fall1_r_reg[4]_2 (\gen_mux_rd[4].mux_rd_fall1_r_reg[4]_2 ),
        .\gen_mux_rd[4].mux_rd_fall2_r_reg[4] (\gen_mux_rd[4].mux_rd_fall2_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0 (\gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0 ),
        .\gen_mux_rd[4].mux_rd_fall2_r_reg[4]_1 (\gen_mux_rd[4].mux_rd_fall2_r_reg[4]_1 ),
        .\gen_mux_rd[4].mux_rd_fall2_r_reg[4]_2 (\gen_mux_rd[4].mux_rd_fall2_r_reg[4]_2 ),
        .\gen_mux_rd[4].mux_rd_fall3_r_reg[4] (\gen_mux_rd[4].mux_rd_fall3_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0 (\gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0 ),
        .\gen_mux_rd[4].mux_rd_fall3_r_reg[4]_1 (\gen_mux_rd[4].mux_rd_fall3_r_reg[4]_1 ),
        .\gen_mux_rd[4].mux_rd_fall3_r_reg[4]_2 (\gen_mux_rd[4].mux_rd_fall3_r_reg[4]_2 ),
        .\gen_mux_rd[4].mux_rd_rise0_r_reg[4] (\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0 (\gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0 ),
        .\gen_mux_rd[4].mux_rd_rise0_r_reg[4]_1 (\gen_mux_rd[4].mux_rd_rise0_r_reg[4]_1 ),
        .\gen_mux_rd[4].mux_rd_rise0_r_reg[4]_2 (\gen_mux_rd[4].mux_rd_rise0_r_reg[4]_2 ),
        .\gen_mux_rd[4].mux_rd_rise1_r_reg[4] (\gen_mux_rd[4].mux_rd_rise1_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0 (\gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0 ),
        .\gen_mux_rd[4].mux_rd_rise1_r_reg[4]_1 (\gen_mux_rd[4].mux_rd_rise1_r_reg[4]_1 ),
        .\gen_mux_rd[4].mux_rd_rise1_r_reg[4]_2 (\gen_mux_rd[4].mux_rd_rise1_r_reg[4]_2 ),
        .\gen_mux_rd[4].mux_rd_rise2_r_reg[4] (\gen_mux_rd[4].mux_rd_rise2_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0 (\gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0 ),
        .\gen_mux_rd[4].mux_rd_rise2_r_reg[4]_1 (\gen_mux_rd[4].mux_rd_rise2_r_reg[4]_1 ),
        .\gen_mux_rd[4].mux_rd_rise2_r_reg[4]_2 (\gen_mux_rd[4].mux_rd_rise2_r_reg[4]_2 ),
        .\gen_mux_rd[4].mux_rd_rise3_r_reg[4] (\gen_mux_rd[4].mux_rd_rise3_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0 (\gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0 ),
        .\gen_mux_rd[4].mux_rd_rise3_r_reg[4]_1 (\gen_mux_rd[4].mux_rd_rise3_r_reg[4]_1 ),
        .\gen_mux_rd[4].mux_rd_rise3_r_reg[4]_2 (\gen_mux_rd[4].mux_rd_rise3_r_reg[4]_2 ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5] (\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 (\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_2 (\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_2 ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5] (\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 (\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_2 (\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_2 ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5] (\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 (\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_2 (\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_2 ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5] (\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 (\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_2 (\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_2 ),
        .\gen_mux_rd[5].mux_rd_rise0_r_reg[5] (\gen_mux_rd[5].mux_rd_rise0_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_rise0_r_reg[5]_1 (\gen_mux_rd[5].mux_rd_rise0_r_reg[5]_1 ),
        .\gen_mux_rd[5].mux_rd_rise0_r_reg[5]_2 (\gen_mux_rd[5].mux_rd_rise0_r_reg[5]_2 ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5] (\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 (\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_2 (\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_2 ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5] (\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 (\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_2 (\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_2 ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5] (\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 (\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_2 (\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_2 ),
        .\gen_mux_rd[6].mux_rd_fall0_r_reg[6] (\gen_mux_rd[6].mux_rd_fall0_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0 (\gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0 ),
        .\gen_mux_rd[6].mux_rd_fall0_r_reg[6]_1 (\gen_mux_rd[6].mux_rd_fall0_r_reg[6]_1 ),
        .\gen_mux_rd[6].mux_rd_fall0_r_reg[6]_2 (\gen_mux_rd[6].mux_rd_fall0_r_reg[6]_2 ),
        .\gen_mux_rd[6].mux_rd_fall1_r_reg[6] (\gen_mux_rd[6].mux_rd_fall1_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0 (\gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0 ),
        .\gen_mux_rd[6].mux_rd_fall1_r_reg[6]_1 (\gen_mux_rd[6].mux_rd_fall1_r_reg[6]_1 ),
        .\gen_mux_rd[6].mux_rd_fall1_r_reg[6]_2 (\gen_mux_rd[6].mux_rd_fall1_r_reg[6]_2 ),
        .\gen_mux_rd[6].mux_rd_fall2_r_reg[6] (\gen_mux_rd[6].mux_rd_fall2_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0 (\gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0 ),
        .\gen_mux_rd[6].mux_rd_fall2_r_reg[6]_1 (\gen_mux_rd[6].mux_rd_fall2_r_reg[6]_1 ),
        .\gen_mux_rd[6].mux_rd_fall2_r_reg[6]_2 (\gen_mux_rd[6].mux_rd_fall2_r_reg[6]_2 ),
        .\gen_mux_rd[6].mux_rd_fall3_r_reg[6] (\gen_mux_rd[6].mux_rd_fall3_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0 (\gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0 ),
        .\gen_mux_rd[6].mux_rd_fall3_r_reg[6]_1 (\gen_mux_rd[6].mux_rd_fall3_r_reg[6]_1 ),
        .\gen_mux_rd[6].mux_rd_fall3_r_reg[6]_2 (\gen_mux_rd[6].mux_rd_fall3_r_reg[6]_2 ),
        .\gen_mux_rd[6].mux_rd_rise0_r_reg[6] (\gen_mux_rd[6].mux_rd_rise0_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0 (\gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0 ),
        .\gen_mux_rd[6].mux_rd_rise0_r_reg[6]_1 (\gen_mux_rd[6].mux_rd_rise0_r_reg[6]_1 ),
        .\gen_mux_rd[6].mux_rd_rise0_r_reg[6]_2 (\gen_mux_rd[6].mux_rd_rise0_r_reg[6]_2 ),
        .\gen_mux_rd[6].mux_rd_rise1_r_reg[6] (\gen_mux_rd[6].mux_rd_rise1_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0 (\gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0 ),
        .\gen_mux_rd[6].mux_rd_rise1_r_reg[6]_1 (\gen_mux_rd[6].mux_rd_rise1_r_reg[6]_1 ),
        .\gen_mux_rd[6].mux_rd_rise1_r_reg[6]_2 (\gen_mux_rd[6].mux_rd_rise1_r_reg[6]_2 ),
        .\gen_mux_rd[6].mux_rd_rise2_r_reg[6] (\gen_mux_rd[6].mux_rd_rise2_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0 (\gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0 ),
        .\gen_mux_rd[6].mux_rd_rise2_r_reg[6]_1 (\gen_mux_rd[6].mux_rd_rise2_r_reg[6]_1 ),
        .\gen_mux_rd[6].mux_rd_rise2_r_reg[6]_2 (\gen_mux_rd[6].mux_rd_rise2_r_reg[6]_2 ),
        .\gen_mux_rd[6].mux_rd_rise3_r_reg[6] (\gen_mux_rd[6].mux_rd_rise3_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0 (\gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0 ),
        .\gen_mux_rd[6].mux_rd_rise3_r_reg[6]_1 (\gen_mux_rd[6].mux_rd_rise3_r_reg[6]_1 ),
        .\gen_mux_rd[6].mux_rd_rise3_r_reg[6]_2 (\gen_mux_rd[6].mux_rd_rise3_r_reg[6]_2 ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7] (\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 (\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_2 (\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_2 ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7] (\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 (\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_2 (\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_2 ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7] (\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 (\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_2 (\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_2 ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 (\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_2 (\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_2 ),
        .\gen_mux_rd[7].mux_rd_rise0_r_reg[7] (\gen_mux_rd[7].mux_rd_rise0_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_rise0_r_reg[7]_1 (\gen_mux_rd[7].mux_rd_rise0_r_reg[7]_1 ),
        .\gen_mux_rd[7].mux_rd_rise0_r_reg[7]_2 (\gen_mux_rd[7].mux_rd_rise0_r_reg[7]_2 ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7] (\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 (\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_2 (\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_2 ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7] (\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 (\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_2 (\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_2 ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7] (\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 (\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_2 (\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_2 ),
        .ififo_rst(ififo_rst),
        .my_empty(my_empty),
        .\my_empty_reg[4]_0 (\my_empty_reg[4] ),
        .\my_empty_reg[4]_1 (\my_empty_reg[4]_0 ),
        .\my_full_reg[1]_0 (\my_full_reg[1] ),
        .\rd_mux_sel_r_reg[2] (\rd_mux_sel_r_reg[2] ),
        .\rd_mux_sel_r_reg[2]_0 (\rd_mux_sel_r_reg[2]_0 ),
        .\rd_mux_sel_r_reg[2]_1 (\rd_mux_sel_r_reg[2]_1 ),
        .\rd_mux_sel_r_reg[2]_10 (\rd_mux_sel_r_reg[2]_10 ),
        .\rd_mux_sel_r_reg[2]_11 (\rd_mux_sel_r_reg[2]_11 ),
        .\rd_mux_sel_r_reg[2]_12 (\rd_mux_sel_r_reg[2]_12 ),
        .\rd_mux_sel_r_reg[2]_13 (\rd_mux_sel_r_reg[2]_13 ),
        .\rd_mux_sel_r_reg[2]_14 (\rd_mux_sel_r_reg[2]_14 ),
        .\rd_mux_sel_r_reg[2]_15 (\rd_mux_sel_r_reg[2]_15 ),
        .\rd_mux_sel_r_reg[2]_16 (\rd_mux_sel_r_reg[2]_16 ),
        .\rd_mux_sel_r_reg[2]_17 (\rd_mux_sel_r_reg[2]_17 ),
        .\rd_mux_sel_r_reg[2]_18 (\rd_mux_sel_r_reg[2]_18 ),
        .\rd_mux_sel_r_reg[2]_19 (\rd_mux_sel_r_reg[2]_19 ),
        .\rd_mux_sel_r_reg[2]_2 (\rd_mux_sel_r_reg[2]_2 ),
        .\rd_mux_sel_r_reg[2]_20 (\rd_mux_sel_r_reg[2]_20 ),
        .\rd_mux_sel_r_reg[2]_21 (\rd_mux_sel_r_reg[2]_21 ),
        .\rd_mux_sel_r_reg[2]_22 (\rd_mux_sel_r_reg[2]_22 ),
        .\rd_mux_sel_r_reg[2]_23 (\rd_mux_sel_r_reg[2]_23 ),
        .\rd_mux_sel_r_reg[2]_24 (\rd_mux_sel_r_reg[2]_24 ),
        .\rd_mux_sel_r_reg[2]_25 (\rd_mux_sel_r_reg[2]_25 ),
        .\rd_mux_sel_r_reg[2]_26 (\rd_mux_sel_r_reg[2]_26 ),
        .\rd_mux_sel_r_reg[2]_27 (\rd_mux_sel_r_reg[2]_27 ),
        .\rd_mux_sel_r_reg[2]_28 (\rd_mux_sel_r_reg[2]_28 ),
        .\rd_mux_sel_r_reg[2]_29 (\rd_mux_sel_r_reg[2]_29 ),
        .\rd_mux_sel_r_reg[2]_3 (\rd_mux_sel_r_reg[2]_3 ),
        .\rd_mux_sel_r_reg[2]_30 (\rd_mux_sel_r_reg[2]_30 ),
        .\rd_mux_sel_r_reg[2]_31 (\rd_mux_sel_r_reg[2]_31 ),
        .\rd_mux_sel_r_reg[2]_32 (\rd_mux_sel_r_reg[2]_32 ),
        .\rd_mux_sel_r_reg[2]_33 (\rd_mux_sel_r_reg[2]_33 ),
        .\rd_mux_sel_r_reg[2]_34 (\rd_mux_sel_r_reg[2]_34 ),
        .\rd_mux_sel_r_reg[2]_35 (\rd_mux_sel_r_reg[2]_35 ),
        .\rd_mux_sel_r_reg[2]_36 (\rd_mux_sel_r_reg[2]_36 ),
        .\rd_mux_sel_r_reg[2]_37 (\rd_mux_sel_r_reg[2]_37 ),
        .\rd_mux_sel_r_reg[2]_38 (\rd_mux_sel_r_reg[2]_38 ),
        .\rd_mux_sel_r_reg[2]_39 (\rd_mux_sel_r_reg[2]_39 ),
        .\rd_mux_sel_r_reg[2]_4 (\rd_mux_sel_r_reg[2]_4 ),
        .\rd_mux_sel_r_reg[2]_40 (\rd_mux_sel_r_reg[2]_40 ),
        .\rd_mux_sel_r_reg[2]_41 (\rd_mux_sel_r_reg[2]_41 ),
        .\rd_mux_sel_r_reg[2]_42 (\rd_mux_sel_r_reg[2]_42 ),
        .\rd_mux_sel_r_reg[2]_43 (\rd_mux_sel_r_reg[2]_43 ),
        .\rd_mux_sel_r_reg[2]_44 (\rd_mux_sel_r_reg[2]_44 ),
        .\rd_mux_sel_r_reg[2]_45 (\rd_mux_sel_r_reg[2]_45 ),
        .\rd_mux_sel_r_reg[2]_46 (\rd_mux_sel_r_reg[2]_46 ),
        .\rd_mux_sel_r_reg[2]_47 (\rd_mux_sel_r_reg[2]_47 ),
        .\rd_mux_sel_r_reg[2]_48 (\rd_mux_sel_r_reg[2]_48 ),
        .\rd_mux_sel_r_reg[2]_49 (\rd_mux_sel_r_reg[2]_49 ),
        .\rd_mux_sel_r_reg[2]_5 (\rd_mux_sel_r_reg[2]_5 ),
        .\rd_mux_sel_r_reg[2]_50 (\rd_mux_sel_r_reg[2]_50 ),
        .\rd_mux_sel_r_reg[2]_51 (\rd_mux_sel_r_reg[2]_51 ),
        .\rd_mux_sel_r_reg[2]_52 (\rd_mux_sel_r_reg[2]_52 ),
        .\rd_mux_sel_r_reg[2]_53 (\rd_mux_sel_r_reg[2]_53 ),
        .\rd_mux_sel_r_reg[2]_54 (\rd_mux_sel_r_reg[2]_54 ),
        .\rd_mux_sel_r_reg[2]_55 (\rd_mux_sel_r_reg[2]_55 ),
        .\rd_mux_sel_r_reg[2]_56 (\rd_mux_sel_r_reg[2]_56 ),
        .\rd_mux_sel_r_reg[2]_57 (\rd_mux_sel_r_reg[2]_57 ),
        .\rd_mux_sel_r_reg[2]_58 (\rd_mux_sel_r_reg[2]_58 ),
        .\rd_mux_sel_r_reg[2]_59 (\rd_mux_sel_r_reg[2]_59 ),
        .\rd_mux_sel_r_reg[2]_6 (\rd_mux_sel_r_reg[2]_6 ),
        .\rd_mux_sel_r_reg[2]_60 (\rd_mux_sel_r_reg[2]_60 ),
        .\rd_mux_sel_r_reg[2]_61 (\rd_mux_sel_r_reg[2]_61 ),
        .\rd_mux_sel_r_reg[2]_62 (\rd_mux_sel_r_reg[2]_62 ),
        .\rd_mux_sel_r_reg[2]_7 (\rd_mux_sel_r_reg[2]_7 ),
        .\rd_mux_sel_r_reg[2]_8 (\rd_mux_sel_r_reg[2]_8 ),
        .\rd_mux_sel_r_reg[2]_9 (\rd_mux_sel_r_reg[2]_9 ),
        .\rd_ptr_reg[1]_0 (\entry_cnt_reg[4] ),
        .\wr_ptr[1]_i_2__0 (\wr_ptr[1]_i_2__0 ),
        .\wr_ptr_reg[0]_0 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ));
  FDSE #(
    .INIT(1'b1)) 
    ififo_rst_reg
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(ififo_rst_reg_0),
        .Q(ififo_rst),
        .S(phy_if_reset));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IN_FIFO #(
    .ALMOST_EMPTY_VALUE(1),
    .ALMOST_FULL_VALUE(1),
    .ARRAY_MODE("ARRAY_MODE_4_X_8"),
    .SYNCHRONOUS_MODE("FALSE")) 
    \in_fifo_gen.in_fifo 
       (.ALMOSTEMPTY(\in_fifo_gen.in_fifo_n_0 ),
        .ALMOSTFULL(\in_fifo_gen.in_fifo_n_1 ),
        .D0({1'b0,1'b0,1'b0,1'b0}),
        .D1({1'b0,1'b0,1'b0,1'b0}),
        .D2(if_d2),
        .D3(if_d3),
        .D4(if_d4),
        .D5({\NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED [7:4],if_d5}),
        .D6({\NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED [7:4],if_d6}),
        .D7(if_d7),
        .D8(if_d8),
        .D9(if_d9),
        .EMPTY(if_empty_),
        .FULL(\in_fifo_gen.in_fifo_n_3 ),
        .Q0(rd_data[7:0]),
        .Q1(rd_data[15:8]),
        .Q2(rd_data[23:16]),
        .Q3(rd_data[31:24]),
        .Q4(rd_data[39:32]),
        .Q5(rd_data[47:40]),
        .Q6(rd_data[55:48]),
        .Q7(rd_data[63:56]),
        .Q8(rd_data[71:64]),
        .Q9(rd_data[79:72]),
        .RDCLK(\entry_cnt_reg[4] ),
        .RDEN(1'b1),
        .RESET(ififo_rst),
        .WRCLK(iserdes_clkdiv),
        .WREN(ififo_wr_enable));
  mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_37 \of_pre_fifo_gen.u_ddr_of_pre_fifo 
       (.D0({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 }),
        .D1(of_d1),
        .Q(Q),
        .\entry_cnt_reg[4]_0 (\entry_cnt_reg[4] ),
        .\my_empty_reg[1]_0 (\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ),
        .\my_empty_reg[1]_1 (\my_empty_reg[1] ),
        .\my_empty_reg[7]_0 (out_fifo_n_3),
        .ofifo_rst(ofifo_rst),
        .out_fifo(out_fifo_0),
        .out_fifo_0(out_fifo_1),
        .out_fifo_1(out_fifo_2),
        .out_fifo_i_75__5(out_fifo_i_75__5),
        .phy_data_wr_en(phy_data_wr_en),
        .\rd_ptr_reg[3]_0 (\rd_ptr_reg[3] ));
  FDSE #(
    .INIT(1'b1)) 
    ofifo_rst_reg
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(ififo_rst_reg_0),
        .Q(ofifo_rst),
        .S(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OUT_FIFO #(
    .ALMOST_EMPTY_VALUE(1),
    .ALMOST_FULL_VALUE(1),
    .ARRAY_MODE("ARRAY_MODE_8_X_4"),
    .OUTPUT_DISABLE("FALSE"),
    .SYNCHRONOUS_MODE("FALSE")) 
    out_fifo
       (.ALMOSTEMPTY(out_fifo_n_0),
        .ALMOSTFULL(out_fifo_n_1),
        .D0({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 }),
        .D1(of_d1),
        .D2(\my_empty_reg[7] ),
        .D3(\my_empty_reg[7]_0 ),
        .D4(\my_empty_reg[7]_1 ),
        .D5(\my_empty_reg[7]_2 ),
        .D6(\my_empty_reg[7]_3 ),
        .D7(\my_empty_reg[7]_4 ),
        .D8(\my_empty_reg[7]_5 ),
        .D9(\my_empty_reg[7]_6 ),
        .EMPTY(out_fifo_n_2),
        .FULL(out_fifo_n_3),
        .Q0(of_dqbus[3:0]),
        .Q1(of_dqbus[7:4]),
        .Q2(of_dqbus[11:8]),
        .Q3(of_dqbus[15:12]),
        .Q4(of_dqbus[19:16]),
        .Q5({NLW_out_fifo_Q5_UNCONNECTED[7:4],of_dqbus[23:20]}),
        .Q6({NLW_out_fifo_Q6_UNCONNECTED[7:4],of_dqbus[27:24]}),
        .Q7(of_dqbus[31:28]),
        .Q8(of_dqbus[35:32]),
        .Q9(of_dqbus[39:36]),
        .RDCLK(oserdes_clkdiv),
        .RDEN(po_rd_enable),
        .RESET(ofifo_rst),
        .WRCLK(\entry_cnt_reg[4] ),
        .WREN(\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  PHASER_IN_PHY #(
    .BURST_MODE("TRUE"),
    .CLKOUT_DIV(2),
    .DQS_AUTO_RECAL(1'b1),
    .DQS_BIAS_MODE("FALSE"),
    .DQS_FIND_PATTERN(3'b000),
    .FINE_DELAY(33),
    .FREQ_REF_DIV("DIV2"),
    .IS_RST_INVERTED(1'b0),
    .MEMREFCLK_PERIOD(2.500000),
    .OUTPUT_CLK_SRC("DELAYED_REF"),
    .PHASEREFCLK_PERIOD(2.500000),
    .REFCLK_PERIOD(1.250000),
    .SEL_CLK_OFFSET(6),
    .SYNC_IN_DIV_RST("TRUE"),
    .WR_CYCLES("FALSE")) 
    \phaser_in_gen.phaser_in 
       (.BURSTPENDINGPHY(phaser_ctl_bus[1]),
        .COUNTERLOADEN(\pi_dqs_found_lanes_r1_reg[1] ),
        .COUNTERLOADVAL(\pi_dqs_found_lanes_r1_reg[1]_3 ),
        .COUNTERREADEN(\pi_dqs_found_lanes_r1_reg[1]_0 ),
        .COUNTERREADVAL(B_pi_counter_read_val),
        .DQSFOUND(in0),
        .DQSOUTOFRANGE(\phaser_in_gen.phaser_in_n_1 ),
        .ENCALIBPHY(PCENABLECALIB),
        .FINEENABLE(\pi_dqs_found_lanes_r1_reg[1]_1 ),
        .FINEINC(\pi_dqs_found_lanes_r1_reg[1]_2 ),
        .FINEOVERFLOW(\phaser_in_gen.phaser_in_n_2 ),
        .FREQREFCLK(freq_refclk),
        .ICLK(A_rst_primitives_reg),
        .ICLKDIV(iserdes_clkdiv),
        .ISERDESRST(\phaser_in_gen.phaser_in_n_5 ),
        .MEMREFCLK(mem_refclk),
        .PHASELOCKED(A_rst_primitives_reg_0),
        .PHASEREFCLK(mem_dqs_in),
        .RANKSELPHY(phaser_ctl_bus[3:2]),
        .RCLK(B_rclk),
        .RST(A_rst_primitives),
        .RSTDQSFIND(ififo_rst_reg_0),
        .SYNCIN(sync_pulse),
        .SYSCLK(\entry_cnt_reg[4] ),
        .WRENABLE(ififo_wr_enable));
  (* BOX_TYPE = "PRIMITIVE" *) 
  PHASER_OUT_PHY #(
    .CLKOUT_DIV(2),
    .COARSE_BYPASS("FALSE"),
    .COARSE_DELAY(0),
    .DATA_CTL_N("TRUE"),
    .DATA_RD_CYCLES("FALSE"),
    .FINE_DELAY(60),
    .IS_RST_INVERTED(1'b0),
    .MEMREFCLK_PERIOD(2.500000),
    .OCLKDELAY_INV("FALSE"),
    .OCLK_DELAY(0),
    .OUTPUT_CLK_SRC("DELAYED_REF"),
    .PHASEREFCLK_PERIOD(1.000000),
    .PO(3'b111),
    .REFCLK_PERIOD(1.250000),
    .SYNC_IN_DIV_RST("TRUE")) 
    phaser_out
       (.BURSTPENDINGPHY(phaser_ctl_bus[0]),
        .COARSEENABLE(\po_counter_read_val_reg[8] ),
        .COARSEINC(\po_counter_read_val_reg[8] ),
        .COARSEOVERFLOW(phaser_out_n_0),
        .COUNTERLOADEN(1'b0),
        .COUNTERLOADVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .COUNTERREADEN(\pi_dqs_found_lanes_r1_reg[1]_0 ),
        .COUNTERREADVAL(B_po_counter_read_val),
        .CTSBUS(oserdes_dqs_ts),
        .DQSBUS(oserdes_dqs),
        .DTSBUS(oserdes_dq_ts),
        .ENCALIBPHY(PCENABLECALIB),
        .FINEENABLE(\po_counter_read_val_reg[8]_0 ),
        .FINEINC(\po_counter_read_val_reg[8]_1 ),
        .FINEOVERFLOW(phaser_out_n_1),
        .FREQREFCLK(freq_refclk),
        .MEMREFCLK(mem_refclk),
        .OCLK(oserdes_clk),
        .OCLKDELAYED(oserdes_clk_delayed),
        .OCLKDIV(oserdes_clkdiv),
        .OSERDESRST(po_oserdes_rst),
        .PHASEREFCLK(NLW_phaser_out_PHASEREFCLK_UNCONNECTED),
        .RDENABLE(po_rd_enable),
        .RST(A_rst_primitives),
        .SELFINEOCLKDELAY(1'b0),
        .SYNCIN(sync_pulse),
        .SYSCLK(\entry_cnt_reg[4] ));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \pi_counter_read_val[0]_i_1 
       (.I0(B_pi_counter_read_val[0]),
        .I1(COUNTERREADVAL[0]),
        .I2(\pi_counter_read_val_reg[5] [0]),
        .I3(calib_sel[1]),
        .I4(calib_sel[0]),
        .I5(\pi_counter_read_val_reg[5]_0 [0]),
        .O(D[0]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \pi_counter_read_val[1]_i_1 
       (.I0(B_pi_counter_read_val[1]),
        .I1(COUNTERREADVAL[1]),
        .I2(\pi_counter_read_val_reg[5] [1]),
        .I3(calib_sel[1]),
        .I4(calib_sel[0]),
        .I5(\pi_counter_read_val_reg[5]_0 [1]),
        .O(D[1]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \pi_counter_read_val[2]_i_1 
       (.I0(B_pi_counter_read_val[2]),
        .I1(COUNTERREADVAL[2]),
        .I2(\pi_counter_read_val_reg[5] [2]),
        .I3(calib_sel[1]),
        .I4(calib_sel[0]),
        .I5(\pi_counter_read_val_reg[5]_0 [2]),
        .O(D[2]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \pi_counter_read_val[3]_i_1 
       (.I0(B_pi_counter_read_val[3]),
        .I1(COUNTERREADVAL[3]),
        .I2(\pi_counter_read_val_reg[5] [3]),
        .I3(calib_sel[1]),
        .I4(calib_sel[0]),
        .I5(\pi_counter_read_val_reg[5]_0 [3]),
        .O(D[3]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \pi_counter_read_val[4]_i_1 
       (.I0(B_pi_counter_read_val[4]),
        .I1(COUNTERREADVAL[4]),
        .I2(\pi_counter_read_val_reg[5] [4]),
        .I3(calib_sel[1]),
        .I4(calib_sel[0]),
        .I5(\pi_counter_read_val_reg[5]_0 [4]),
        .O(D[4]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \pi_counter_read_val[5]_i_1 
       (.I0(B_pi_counter_read_val[5]),
        .I1(COUNTERREADVAL[5]),
        .I2(\pi_counter_read_val_reg[5] [5]),
        .I3(calib_sel[1]),
        .I4(calib_sel[0]),
        .I5(\pi_counter_read_val_reg[5]_0 [5]),
        .O(D[5]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \po_counter_read_val[0]_i_1 
       (.I0(B_po_counter_read_val[0]),
        .I1(\po_counter_read_val_reg[8]_2 [0]),
        .I2(\po_counter_read_val_reg[8]_3 [0]),
        .I3(calib_sel[1]),
        .I4(calib_sel[0]),
        .I5(\po_counter_read_val_reg[8]_4 [0]),
        .O(\calib_sel_reg[1] [0]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \po_counter_read_val[1]_i_1 
       (.I0(B_po_counter_read_val[1]),
        .I1(\po_counter_read_val_reg[8]_2 [1]),
        .I2(\po_counter_read_val_reg[8]_3 [1]),
        .I3(calib_sel[1]),
        .I4(calib_sel[0]),
        .I5(\po_counter_read_val_reg[8]_4 [1]),
        .O(\calib_sel_reg[1] [1]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \po_counter_read_val[2]_i_1 
       (.I0(B_po_counter_read_val[2]),
        .I1(\po_counter_read_val_reg[8]_2 [2]),
        .I2(\po_counter_read_val_reg[8]_3 [2]),
        .I3(calib_sel[1]),
        .I4(calib_sel[0]),
        .I5(\po_counter_read_val_reg[8]_4 [2]),
        .O(\calib_sel_reg[1] [2]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \po_counter_read_val[3]_i_1 
       (.I0(B_po_counter_read_val[3]),
        .I1(\po_counter_read_val_reg[8]_2 [3]),
        .I2(\po_counter_read_val_reg[8]_3 [3]),
        .I3(calib_sel[1]),
        .I4(calib_sel[0]),
        .I5(\po_counter_read_val_reg[8]_4 [3]),
        .O(\calib_sel_reg[1] [3]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \po_counter_read_val[4]_i_1 
       (.I0(B_po_counter_read_val[4]),
        .I1(\po_counter_read_val_reg[8]_2 [4]),
        .I2(\po_counter_read_val_reg[8]_3 [4]),
        .I3(calib_sel[1]),
        .I4(calib_sel[0]),
        .I5(\po_counter_read_val_reg[8]_4 [4]),
        .O(\calib_sel_reg[1] [4]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \po_counter_read_val[5]_i_1 
       (.I0(B_po_counter_read_val[5]),
        .I1(\po_counter_read_val_reg[8]_2 [5]),
        .I2(\po_counter_read_val_reg[8]_3 [5]),
        .I3(calib_sel[1]),
        .I4(calib_sel[0]),
        .I5(\po_counter_read_val_reg[8]_4 [5]),
        .O(\calib_sel_reg[1] [5]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \po_counter_read_val[6]_i_1 
       (.I0(B_po_counter_read_val[6]),
        .I1(\po_counter_read_val_reg[8]_2 [6]),
        .I2(\po_counter_read_val_reg[8]_3 [6]),
        .I3(calib_sel[1]),
        .I4(calib_sel[0]),
        .I5(\po_counter_read_val_reg[8]_4 [6]),
        .O(\calib_sel_reg[1] [6]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \po_counter_read_val[7]_i_1 
       (.I0(B_po_counter_read_val[7]),
        .I1(\po_counter_read_val_reg[8]_2 [7]),
        .I2(\po_counter_read_val_reg[8]_3 [7]),
        .I3(calib_sel[1]),
        .I4(calib_sel[0]),
        .I5(\po_counter_read_val_reg[8]_4 [7]),
        .O(\calib_sel_reg[1] [7]));
  LUT6 #(
    .INIT(64'hF0AAFFCCF0AA00CC)) 
    \po_counter_read_val[8]_i_1 
       (.I0(B_po_counter_read_val[8]),
        .I1(\po_counter_read_val_reg[8]_2 [8]),
        .I2(\po_counter_read_val_reg[8]_3 [8]),
        .I3(calib_sel[1]),
        .I4(calib_sel[0]),
        .I5(\po_counter_read_val_reg[8]_4 [8]),
        .O(\calib_sel_reg[1] [8]));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_byte_lane" *) 
module mig_mig_7series_v4_2_ddr_byte_lane__parameterized1
   (out_dqs_2,
    ts_dqs_2,
    A_rst_primitives_reg,
    mem_dq_out,
    mem_dq_ts,
    in0,
    A_rst_primitives_reg_0,
    A_rst_primitives_reg_1,
    A_rst_primitives_reg_2,
    idelay_ld_rst_5,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ,
    \my_empty_reg[1] ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ,
    \rd_ptr_reg[3] ,
    Q,
    \wr_ptr_timing_reg[3] ,
    \input_[9].iserdes_dq_.iserdesdq ,
    mem_dq_in,
    idelay_inc,
    LD0_12,
    A_rst_primitives,
    CLKB0_12,
    phaser_ctl_bus,
    \pi_dqs_found_lanes_r1_reg[10] ,
    \pi_dqs_found_lanes_r1_reg[10]_0 ,
    \pi_dqs_found_lanes_r1_reg[10]_1 ,
    \pi_dqs_found_lanes_r1_reg[10]_2 ,
    freq_refclk,
    mem_refclk,
    mem_dqs_in,
    ififo_rst_reg_0,
    sync_pulse,
    PCENABLECALIB,
    \pi_dqs_found_lanes_r1_reg[10]_3 ,
    \po_counter_read_val_reg[8] ,
    \po_counter_read_val_reg[8]_0 ,
    \po_counter_read_val_reg[8]_1 ,
    \my_empty_reg[7] ,
    \my_empty_reg[7]_0 ,
    \my_empty_reg[7]_1 ,
    \my_empty_reg[7]_2 ,
    \my_empty_reg[7]_3 ,
    \my_empty_reg[7]_4 ,
    \my_empty_reg[7]_5 ,
    \my_empty_reg[7]_6 ,
    phy_if_reset,
    \my_full_reg[1] ,
    \wr_ptr[1]_i_2__2 ,
    if_empty_r,
    phy_data_wr_en,
    rst_r4,
    out_fifo_0,
    out_fifo_1,
    out_fifo_2,
    \my_full_reg[1]_0 ,
    \my_full_reg[1]_1 ,
    \my_full_reg[1]_2 ,
    \my_full_reg[1]_3 ,
    \my_full_reg[1]_4 ,
    out_fifo_i_75__2);
  output out_dqs_2;
  output ts_dqs_2;
  output A_rst_primitives_reg;
  output [8:0]mem_dq_out;
  output [8:0]mem_dq_ts;
  output [0:0]in0;
  output A_rst_primitives_reg_0;
  output [5:0]A_rst_primitives_reg_1;
  output [8:0]A_rst_primitives_reg_2;
  output idelay_ld_rst_5;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  output \my_empty_reg[1] ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ;
  output [63:0]\rd_ptr_reg[3] ;
  output [2:0]Q;
  input \wr_ptr_timing_reg[3] ;
  input \input_[9].iserdes_dq_.iserdesdq ;
  input [7:0]mem_dq_in;
  input idelay_inc;
  input LD0_12;
  input A_rst_primitives;
  input CLKB0_12;
  input [3:0]phaser_ctl_bus;
  input \pi_dqs_found_lanes_r1_reg[10] ;
  input \pi_dqs_found_lanes_r1_reg[10]_0 ;
  input \pi_dqs_found_lanes_r1_reg[10]_1 ;
  input \pi_dqs_found_lanes_r1_reg[10]_2 ;
  input freq_refclk;
  input mem_refclk;
  input [0:0]mem_dqs_in;
  input ififo_rst_reg_0;
  input sync_pulse;
  input [1:0]PCENABLECALIB;
  input [5:0]\pi_dqs_found_lanes_r1_reg[10]_3 ;
  input \po_counter_read_val_reg[8] ;
  input \po_counter_read_val_reg[8]_0 ;
  input \po_counter_read_val_reg[8]_1 ;
  input [7:0]\my_empty_reg[7] ;
  input [7:0]\my_empty_reg[7]_0 ;
  input [7:0]\my_empty_reg[7]_1 ;
  input [7:0]\my_empty_reg[7]_2 ;
  input [7:0]\my_empty_reg[7]_3 ;
  input [7:0]\my_empty_reg[7]_4 ;
  input [7:0]\my_empty_reg[7]_5 ;
  input [7:0]\my_empty_reg[7]_6 ;
  input phy_if_reset;
  input \my_full_reg[1] ;
  input [1:0]\wr_ptr[1]_i_2__2 ;
  input [0:0]if_empty_r;
  input phy_data_wr_en;
  input rst_r4;
  input out_fifo_0;
  input [7:0]out_fifo_1;
  input out_fifo_2;
  input \my_full_reg[1]_0 ;
  input \my_full_reg[1]_1 ;
  input \my_full_reg[1]_2 ;
  input \my_full_reg[1]_3 ;
  input \my_full_reg[1]_4 ;
  input [71:0]out_fifo_i_75__2;

  wire A_rst_primitives;
  wire A_rst_primitives_reg;
  wire A_rst_primitives_reg_0;
  wire [5:0]A_rst_primitives_reg_1;
  wire [8:0]A_rst_primitives_reg_2;
  wire CLKB0_12;
  wire LD0_12;
  wire [1:0]PCENABLECALIB;
  wire [2:0]Q;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ;
  wire freq_refclk;
  wire idelay_inc;
  wire idelay_ld_rst_5;
  wire [3:0]if_d2;
  wire [3:0]if_d3;
  wire [3:0]if_d4;
  wire [3:0]if_d5;
  wire [3:0]if_d6;
  wire [3:0]if_d7;
  wire [3:0]if_d8;
  wire [3:0]if_d9;
  wire if_empty_;
  wire [0:0]if_empty_r;
  wire [3:3]if_empty_r_0;
  wire ififo_rst;
  wire ififo_rst_reg_0;
  wire ififo_wr_enable;
  wire [0:0]in0;
  wire \in_fifo_gen.in_fifo_n_0 ;
  wire \in_fifo_gen.in_fifo_n_1 ;
  wire \in_fifo_gen.in_fifo_n_3 ;
  wire \input_[9].iserdes_dq_.iserdesdq ;
  wire iserdes_clkdiv;
  wire [7:0]mem_dq_in;
  wire [8:0]mem_dq_out;
  wire [8:0]mem_dq_ts;
  wire [0:0]mem_dqs_in;
  wire mem_refclk;
  wire \my_empty_reg[1] ;
  wire [7:0]\my_empty_reg[7] ;
  wire [7:0]\my_empty_reg[7]_0 ;
  wire [7:0]\my_empty_reg[7]_1 ;
  wire [7:0]\my_empty_reg[7]_2 ;
  wire [7:0]\my_empty_reg[7]_3 ;
  wire [7:0]\my_empty_reg[7]_4 ;
  wire [7:0]\my_empty_reg[7]_5 ;
  wire [7:0]\my_empty_reg[7]_6 ;
  wire \my_full_reg[1] ;
  wire \my_full_reg[1]_0 ;
  wire \my_full_reg[1]_1 ;
  wire \my_full_reg[1]_2 ;
  wire \my_full_reg[1]_3 ;
  wire \my_full_reg[1]_4 ;
  wire [7:0]of_d1;
  wire [39:0]of_dqbus;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ;
  wire ofifo_rst;
  wire oserdes_clk;
  wire oserdes_clk_delayed;
  wire oserdes_clkdiv;
  wire [1:0]oserdes_dq_ts;
  wire [1:0]oserdes_dqs;
  wire [1:0]oserdes_dqs_ts;
  wire out_dqs_2;
  wire out_fifo_0;
  wire [7:0]out_fifo_1;
  wire out_fifo_2;
  wire [71:0]out_fifo_i_75__2;
  wire out_fifo_n_0;
  wire out_fifo_n_1;
  wire out_fifo_n_2;
  wire out_fifo_n_3;
  wire [3:0]phaser_ctl_bus;
  wire \phaser_in_gen.phaser_in_n_1 ;
  wire \phaser_in_gen.phaser_in_n_2 ;
  wire \phaser_in_gen.phaser_in_n_5 ;
  wire \phaser_in_gen.phaser_in_n_7 ;
  wire phaser_out_n_0;
  wire phaser_out_n_1;
  wire phy_data_wr_en;
  wire phy_if_reset;
  wire \pi_dqs_found_lanes_r1_reg[10] ;
  wire \pi_dqs_found_lanes_r1_reg[10]_0 ;
  wire \pi_dqs_found_lanes_r1_reg[10]_1 ;
  wire \pi_dqs_found_lanes_r1_reg[10]_2 ;
  wire [5:0]\pi_dqs_found_lanes_r1_reg[10]_3 ;
  wire \po_counter_read_val_reg[8] ;
  wire \po_counter_read_val_reg[8]_0 ;
  wire \po_counter_read_val_reg[8]_1 ;
  wire po_oserdes_rst;
  wire po_rd_enable;
  wire [79:0]rd_data;
  wire [79:12]rd_data_r;
  wire [63:0]\rd_ptr_reg[3] ;
  wire rst_r4;
  wire sync_pulse;
  wire ts_dqs_2;
  wire [1:0]\wr_ptr[1]_i_2__2 ;
  wire \wr_ptr_timing_reg[3] ;
  wire [7:4]\NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED ;
  wire [7:4]\NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED ;
  wire [7:4]NLW_out_fifo_Q5_UNCONNECTED;
  wire [7:4]NLW_out_fifo_Q6_UNCONNECTED;
  wire NLW_phaser_out_PHASEREFCLK_UNCONNECTED;

  mig_mig_7series_v4_2_ddr_byte_group_io__parameterized0_14 ddr_byte_group_io
       (.A_rst_primitives(A_rst_primitives),
        .CLKB0_12(CLKB0_12),
        .CTSBUS(oserdes_dqs_ts[0]),
        .D2(if_d2),
        .D3(if_d3),
        .D4(if_d4),
        .D5(if_d5),
        .D6(if_d6),
        .D7(if_d7),
        .D8(if_d8),
        .D9(if_d9),
        .DQSBUS(oserdes_dqs),
        .DTSBUS(oserdes_dq_ts),
        .LD0_12(LD0_12),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (A_rst_primitives_reg),
        .idelay_inc(idelay_inc),
        .idelay_ld_rst_5(idelay_ld_rst_5),
        .idelay_ld_rst_reg_0(\wr_ptr_timing_reg[3] ),
        .\input_[9].iserdes_dq_.iserdesdq_0 (\input_[9].iserdes_dq_.iserdesdq ),
        .iserdes_clkdiv(iserdes_clkdiv),
        .mem_dq_in(mem_dq_in),
        .mem_dq_out(mem_dq_out),
        .mem_dq_ts(mem_dq_ts),
        .of_dqbus(of_dqbus[39:4]),
        .oserdes_clk(oserdes_clk),
        .oserdes_clk_delayed(oserdes_clk_delayed),
        .oserdes_clkdiv(oserdes_clkdiv),
        .out_dqs_2(out_dqs_2),
        .po_oserdes_rst(po_oserdes_rst),
        .rst_r4(rst_r4),
        .ts_dqs_2(ts_dqs_2));
  (* syn_maxfan = "3" *) 
  FDRE \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(if_empty_),
        .Q(if_empty_r_0),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[12]),
        .Q(rd_data_r[12]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[13]),
        .Q(rd_data_r[13]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[14]),
        .Q(rd_data_r[14]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[15]),
        .Q(rd_data_r[15]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[16]),
        .Q(rd_data_r[16]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[17]),
        .Q(rd_data_r[17]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[18]),
        .Q(rd_data_r[18]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[19]),
        .Q(rd_data_r[19]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[20]),
        .Q(rd_data_r[20]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[21]),
        .Q(rd_data_r[21]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[22]),
        .Q(rd_data_r[22]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[23]),
        .Q(rd_data_r[23]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[24]),
        .Q(rd_data_r[24]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[25]),
        .Q(rd_data_r[25]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[26]),
        .Q(rd_data_r[26]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[27]),
        .Q(rd_data_r[27]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[28]),
        .Q(rd_data_r[28]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[29]),
        .Q(rd_data_r[29]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[30]),
        .Q(rd_data_r[30]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[31]),
        .Q(rd_data_r[31]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[32]),
        .Q(rd_data_r[32]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[33]),
        .Q(rd_data_r[33]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[34]),
        .Q(rd_data_r[34]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[35]),
        .Q(rd_data_r[35]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[36]),
        .Q(rd_data_r[36]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[37]),
        .Q(rd_data_r[37]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[38]),
        .Q(rd_data_r[38]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[39]),
        .Q(rd_data_r[39]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[40]),
        .Q(rd_data_r[40]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[41]),
        .Q(rd_data_r[41]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[42]),
        .Q(rd_data_r[42]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[43]),
        .Q(rd_data_r[43]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[44]),
        .Q(rd_data_r[44]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[45]),
        .Q(rd_data_r[45]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[46]),
        .Q(rd_data_r[46]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[47]),
        .Q(rd_data_r[47]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[48]),
        .Q(rd_data_r[48]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[49]),
        .Q(rd_data_r[49]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[50]),
        .Q(rd_data_r[50]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[51]),
        .Q(rd_data_r[51]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[52]),
        .Q(rd_data_r[52]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[53]),
        .Q(rd_data_r[53]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[54]),
        .Q(rd_data_r[54]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[55]),
        .Q(rd_data_r[55]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[56]),
        .Q(rd_data_r[56]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[57]),
        .Q(rd_data_r[57]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[58]),
        .Q(rd_data_r[58]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[59]),
        .Q(rd_data_r[59]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[60]),
        .Q(rd_data_r[60]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[61]),
        .Q(rd_data_r[61]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[62]),
        .Q(rd_data_r[62]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[63]),
        .Q(rd_data_r[63]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[64]),
        .Q(rd_data_r[64]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[65]),
        .Q(rd_data_r[65]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[66]),
        .Q(rd_data_r[66]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[67]),
        .Q(rd_data_r[67]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[68]),
        .Q(rd_data_r[68]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[69]),
        .Q(rd_data_r[69]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[70]),
        .Q(rd_data_r[70]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[71]),
        .Q(rd_data_r[71]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[72]),
        .Q(rd_data_r[72]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[73]),
        .Q(rd_data_r[73]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[74]),
        .Q(rd_data_r[74]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[75]),
        .Q(rd_data_r[75]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[76]),
        .Q(rd_data_r[76]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[77]),
        .Q(rd_data_r[77]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[78]),
        .Q(rd_data_r[78]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rd_data[79]),
        .Q(rd_data_r[79]),
        .R(1'b0));
  mig_mig_7series_v4_2_ddr_if_post_fifo_15 \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo 
       (.Q(rd_data_r),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ),
        .if_empty_r(if_empty_r),
        .if_empty_r_0(if_empty_r_0),
        .ififo_rst(ififo_rst),
        .\my_full_reg[1]_0 (\my_full_reg[1] ),
        .\my_full_reg[1]_1 (\my_full_reg[1]_0 ),
        .\my_full_reg[1]_2 (\my_full_reg[1]_1 ),
        .\my_full_reg[1]_3 (\my_full_reg[1]_2 ),
        .\my_full_reg[1]_4 (\my_full_reg[1]_3 ),
        .\my_full_reg[1]_5 (\my_full_reg[1]_4 ),
        .\rd_ptr_reg[1]_0 (\wr_ptr_timing_reg[3] ),
        .\wr_ptr[1]_i_2__2 (\wr_ptr[1]_i_2__2 ));
  FDSE #(
    .INIT(1'b1)) 
    ififo_rst_reg
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(ififo_rst_reg_0),
        .Q(ififo_rst),
        .S(phy_if_reset));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IN_FIFO #(
    .ALMOST_EMPTY_VALUE(1),
    .ALMOST_FULL_VALUE(1),
    .ARRAY_MODE("ARRAY_MODE_4_X_8"),
    .SYNCHRONOUS_MODE("FALSE")) 
    \in_fifo_gen.in_fifo 
       (.ALMOSTEMPTY(\in_fifo_gen.in_fifo_n_0 ),
        .ALMOSTFULL(\in_fifo_gen.in_fifo_n_1 ),
        .D0({1'b0,1'b0,1'b0,1'b0}),
        .D1({1'b0,1'b0,1'b0,1'b0}),
        .D2(if_d2),
        .D3(if_d3),
        .D4(if_d4),
        .D5({\NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED [7:4],if_d5}),
        .D6({\NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED [7:4],if_d6}),
        .D7(if_d7),
        .D8(if_d8),
        .D9(if_d9),
        .EMPTY(if_empty_),
        .FULL(\in_fifo_gen.in_fifo_n_3 ),
        .Q0(rd_data[7:0]),
        .Q1(rd_data[15:8]),
        .Q2(rd_data[23:16]),
        .Q3(rd_data[31:24]),
        .Q4(rd_data[39:32]),
        .Q5(rd_data[47:40]),
        .Q6(rd_data[55:48]),
        .Q7(rd_data[63:56]),
        .Q8(rd_data[71:64]),
        .Q9(rd_data[79:72]),
        .RDCLK(\wr_ptr_timing_reg[3] ),
        .RDEN(1'b1),
        .RESET(ififo_rst),
        .WRCLK(iserdes_clkdiv),
        .WREN(ififo_wr_enable));
  mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_16 \of_pre_fifo_gen.u_ddr_of_pre_fifo 
       (.D0({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 }),
        .D1(of_d1),
        .Q(Q),
        .\my_empty_reg[1]_0 (\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ),
        .\my_empty_reg[1]_1 (\my_empty_reg[1] ),
        .\my_empty_reg[7]_0 (out_fifo_n_3),
        .ofifo_rst(ofifo_rst),
        .out_fifo(out_fifo_0),
        .out_fifo_0(out_fifo_1),
        .out_fifo_1(out_fifo_2),
        .out_fifo_i_75__2(out_fifo_i_75__2),
        .phy_data_wr_en(phy_data_wr_en),
        .\rd_ptr_reg[3]_0 (\rd_ptr_reg[3] ),
        .\wr_ptr_timing_reg[3]_0 (\wr_ptr_timing_reg[3] ));
  FDSE #(
    .INIT(1'b1)) 
    ofifo_rst_reg
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(ififo_rst_reg_0),
        .Q(ofifo_rst),
        .S(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OUT_FIFO #(
    .ALMOST_EMPTY_VALUE(1),
    .ALMOST_FULL_VALUE(1),
    .ARRAY_MODE("ARRAY_MODE_8_X_4"),
    .OUTPUT_DISABLE("FALSE"),
    .SYNCHRONOUS_MODE("FALSE")) 
    out_fifo
       (.ALMOSTEMPTY(out_fifo_n_0),
        .ALMOSTFULL(out_fifo_n_1),
        .D0({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 }),
        .D1(of_d1),
        .D2(\my_empty_reg[7] ),
        .D3(\my_empty_reg[7]_0 ),
        .D4(\my_empty_reg[7]_1 ),
        .D5(\my_empty_reg[7]_2 ),
        .D6(\my_empty_reg[7]_3 ),
        .D7(\my_empty_reg[7]_4 ),
        .D8(\my_empty_reg[7]_5 ),
        .D9(\my_empty_reg[7]_6 ),
        .EMPTY(out_fifo_n_2),
        .FULL(out_fifo_n_3),
        .Q0(of_dqbus[3:0]),
        .Q1(of_dqbus[7:4]),
        .Q2(of_dqbus[11:8]),
        .Q3(of_dqbus[15:12]),
        .Q4(of_dqbus[19:16]),
        .Q5({NLW_out_fifo_Q5_UNCONNECTED[7:4],of_dqbus[23:20]}),
        .Q6({NLW_out_fifo_Q6_UNCONNECTED[7:4],of_dqbus[27:24]}),
        .Q7(of_dqbus[31:28]),
        .Q8(of_dqbus[35:32]),
        .Q9(of_dqbus[39:36]),
        .RDCLK(oserdes_clkdiv),
        .RDEN(po_rd_enable),
        .RESET(ofifo_rst),
        .WRCLK(\wr_ptr_timing_reg[3] ),
        .WREN(\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  PHASER_IN_PHY #(
    .BURST_MODE("TRUE"),
    .CLKOUT_DIV(2),
    .DQS_AUTO_RECAL(1'b1),
    .DQS_BIAS_MODE("FALSE"),
    .DQS_FIND_PATTERN(3'b000),
    .FINE_DELAY(33),
    .FREQ_REF_DIV("DIV2"),
    .IS_RST_INVERTED(1'b0),
    .MEMREFCLK_PERIOD(2.500000),
    .OUTPUT_CLK_SRC("DELAYED_REF"),
    .PHASEREFCLK_PERIOD(2.500000),
    .REFCLK_PERIOD(1.250000),
    .SEL_CLK_OFFSET(6),
    .SYNC_IN_DIV_RST("TRUE"),
    .WR_CYCLES("FALSE")) 
    \phaser_in_gen.phaser_in 
       (.BURSTPENDINGPHY(phaser_ctl_bus[1]),
        .COUNTERLOADEN(\pi_dqs_found_lanes_r1_reg[10] ),
        .COUNTERLOADVAL(\pi_dqs_found_lanes_r1_reg[10]_3 ),
        .COUNTERREADEN(\pi_dqs_found_lanes_r1_reg[10]_0 ),
        .COUNTERREADVAL(A_rst_primitives_reg_1),
        .DQSFOUND(in0),
        .DQSOUTOFRANGE(\phaser_in_gen.phaser_in_n_1 ),
        .ENCALIBPHY(PCENABLECALIB),
        .FINEENABLE(\pi_dqs_found_lanes_r1_reg[10]_1 ),
        .FINEINC(\pi_dqs_found_lanes_r1_reg[10]_2 ),
        .FINEOVERFLOW(\phaser_in_gen.phaser_in_n_2 ),
        .FREQREFCLK(freq_refclk),
        .ICLK(A_rst_primitives_reg),
        .ICLKDIV(iserdes_clkdiv),
        .ISERDESRST(\phaser_in_gen.phaser_in_n_5 ),
        .MEMREFCLK(mem_refclk),
        .PHASELOCKED(A_rst_primitives_reg_0),
        .PHASEREFCLK(mem_dqs_in),
        .RANKSELPHY(phaser_ctl_bus[3:2]),
        .RCLK(\phaser_in_gen.phaser_in_n_7 ),
        .RST(A_rst_primitives),
        .RSTDQSFIND(ififo_rst_reg_0),
        .SYNCIN(sync_pulse),
        .SYSCLK(\wr_ptr_timing_reg[3] ),
        .WRENABLE(ififo_wr_enable));
  (* BOX_TYPE = "PRIMITIVE" *) 
  PHASER_OUT_PHY #(
    .CLKOUT_DIV(2),
    .COARSE_BYPASS("FALSE"),
    .COARSE_DELAY(0),
    .DATA_CTL_N("TRUE"),
    .DATA_RD_CYCLES("FALSE"),
    .FINE_DELAY(60),
    .IS_RST_INVERTED(1'b0),
    .MEMREFCLK_PERIOD(2.500000),
    .OCLKDELAY_INV("FALSE"),
    .OCLK_DELAY(0),
    .OUTPUT_CLK_SRC("DELAYED_REF"),
    .PHASEREFCLK_PERIOD(1.000000),
    .PO(3'b111),
    .REFCLK_PERIOD(1.250000),
    .SYNC_IN_DIV_RST("TRUE")) 
    phaser_out
       (.BURSTPENDINGPHY(phaser_ctl_bus[0]),
        .COARSEENABLE(\po_counter_read_val_reg[8] ),
        .COARSEINC(\po_counter_read_val_reg[8] ),
        .COARSEOVERFLOW(phaser_out_n_0),
        .COUNTERLOADEN(1'b0),
        .COUNTERLOADVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .COUNTERREADEN(\pi_dqs_found_lanes_r1_reg[10]_0 ),
        .COUNTERREADVAL(A_rst_primitives_reg_2),
        .CTSBUS(oserdes_dqs_ts),
        .DQSBUS(oserdes_dqs),
        .DTSBUS(oserdes_dq_ts),
        .ENCALIBPHY(PCENABLECALIB),
        .FINEENABLE(\po_counter_read_val_reg[8]_0 ),
        .FINEINC(\po_counter_read_val_reg[8]_1 ),
        .FINEOVERFLOW(phaser_out_n_1),
        .FREQREFCLK(freq_refclk),
        .MEMREFCLK(mem_refclk),
        .OCLK(oserdes_clk),
        .OCLKDELAYED(oserdes_clk_delayed),
        .OCLKDIV(oserdes_clkdiv),
        .OSERDESRST(po_oserdes_rst),
        .PHASEREFCLK(NLW_phaser_out_PHASEREFCLK_UNCONNECTED),
        .RDENABLE(po_rd_enable),
        .RST(A_rst_primitives),
        .SELFINEOCLKDELAY(1'b0),
        .SYNCIN(sync_pulse),
        .SYSCLK(\wr_ptr_timing_reg[3] ));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_byte_lane" *) 
module mig_mig_7series_v4_2_ddr_byte_lane__parameterized1_27
   (out_dqs_6,
    ts_dqs_6,
    A_rst_primitives_reg,
    mem_dq_out,
    mem_dq_ts,
    in0,
    A_rst_primitives_reg_0,
    A_rst_primitives_reg_1,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ,
    \my_empty_reg[4] ,
    idelay_ld_rst_1,
    \my_empty_reg[4]_0 ,
    phy_mc_data_full,
    \my_empty_reg[1] ,
    A_rst_primitives_reg_2,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ,
    \rd_ptr_reg[3] ,
    Q,
    \my_full_reg[4] ,
    \input_[9].iserdes_dq_.iserdesdq ,
    mem_dq_in,
    idelay_inc,
    LD0_8,
    A_rst_primitives,
    CLKB0_8,
    phaser_ctl_bus,
    \pi_dqs_found_lanes_r1_reg[2] ,
    \pi_dqs_found_lanes_r1_reg[2]_0 ,
    \pi_dqs_found_lanes_r1_reg[2]_1 ,
    \pi_dqs_found_lanes_r1_reg[2]_2 ,
    freq_refclk,
    mem_refclk,
    mem_dqs_in,
    ififo_rst_reg_0,
    sync_pulse,
    PCENABLECALIB,
    \pi_dqs_found_lanes_r1_reg[2]_3 ,
    \po_counter_read_val_reg[8] ,
    \po_counter_read_val_reg[8]_0 ,
    \po_counter_read_val_reg[8]_1 ,
    \my_empty_reg[7] ,
    \my_empty_reg[7]_0 ,
    \my_empty_reg[7]_1 ,
    \my_empty_reg[7]_2 ,
    \my_empty_reg[7]_3 ,
    \my_empty_reg[7]_4 ,
    \my_empty_reg[7]_5 ,
    \my_empty_reg[7]_6 ,
    phy_if_reset,
    \my_full_reg[1] ,
    ofs_rdy_r_reg,
    ofs_rdy_r_reg_0,
    ofs_rdy_r_reg_1,
    ofs_rdy_r_reg_2,
    phy_data_wr_en,
    pi_phase_locked_all_r1_reg,
    pi_phase_locked_all_r1_reg_0,
    pi_phase_locked_all_r1_reg_1,
    pi_phase_locked_all_r1_reg_2,
    rst_r4,
    \wr_ptr[1]_i_2__6 ,
    if_empty_r,
    out_fifo_0,
    out_fifo_1,
    out_fifo_2,
    \my_full_reg[1]_0 ,
    \my_full_reg[1]_1 ,
    \my_full_reg[1]_2 ,
    \my_full_reg[1]_3 ,
    \my_full_reg[1]_4 ,
    out_fifo_i_75__6);
  output out_dqs_6;
  output ts_dqs_6;
  output A_rst_primitives_reg;
  output [8:0]mem_dq_out;
  output [8:0]mem_dq_ts;
  output [0:0]in0;
  output [5:0]A_rst_primitives_reg_0;
  output [8:0]A_rst_primitives_reg_1;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  output \my_empty_reg[4] ;
  output idelay_ld_rst_1;
  output [0:0]\my_empty_reg[4]_0 ;
  output phy_mc_data_full;
  output \my_empty_reg[1] ;
  output A_rst_primitives_reg_2;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;
  output [63:0]\rd_ptr_reg[3] ;
  output [2:0]Q;
  input \my_full_reg[4] ;
  input \input_[9].iserdes_dq_.iserdesdq ;
  input [7:0]mem_dq_in;
  input idelay_inc;
  input LD0_8;
  input A_rst_primitives;
  input CLKB0_8;
  input [3:0]phaser_ctl_bus;
  input \pi_dqs_found_lanes_r1_reg[2] ;
  input \pi_dqs_found_lanes_r1_reg[2]_0 ;
  input \pi_dqs_found_lanes_r1_reg[2]_1 ;
  input \pi_dqs_found_lanes_r1_reg[2]_2 ;
  input freq_refclk;
  input mem_refclk;
  input [0:0]mem_dqs_in;
  input ififo_rst_reg_0;
  input sync_pulse;
  input [1:0]PCENABLECALIB;
  input [5:0]\pi_dqs_found_lanes_r1_reg[2]_3 ;
  input \po_counter_read_val_reg[8] ;
  input \po_counter_read_val_reg[8]_0 ;
  input \po_counter_read_val_reg[8]_1 ;
  input [7:0]\my_empty_reg[7] ;
  input [7:0]\my_empty_reg[7]_0 ;
  input [7:0]\my_empty_reg[7]_1 ;
  input [7:0]\my_empty_reg[7]_2 ;
  input [7:0]\my_empty_reg[7]_3 ;
  input [7:0]\my_empty_reg[7]_4 ;
  input [7:0]\my_empty_reg[7]_5 ;
  input [7:0]\my_empty_reg[7]_6 ;
  input phy_if_reset;
  input \my_full_reg[1] ;
  input ofs_rdy_r_reg;
  input ofs_rdy_r_reg_0;
  input ofs_rdy_r_reg_1;
  input ofs_rdy_r_reg_2;
  input phy_data_wr_en;
  input pi_phase_locked_all_r1_reg;
  input pi_phase_locked_all_r1_reg_0;
  input pi_phase_locked_all_r1_reg_1;
  input pi_phase_locked_all_r1_reg_2;
  input rst_r4;
  input [0:0]\wr_ptr[1]_i_2__6 ;
  input [0:0]if_empty_r;
  input out_fifo_0;
  input [7:0]out_fifo_1;
  input out_fifo_2;
  input \my_full_reg[1]_0 ;
  input \my_full_reg[1]_1 ;
  input \my_full_reg[1]_2 ;
  input \my_full_reg[1]_3 ;
  input \my_full_reg[1]_4 ;
  input [71:0]out_fifo_i_75__6;

  wire A_rst_primitives;
  wire A_rst_primitives_reg;
  wire [5:0]A_rst_primitives_reg_0;
  wire [8:0]A_rst_primitives_reg_1;
  wire A_rst_primitives_reg_2;
  wire CLKB0_8;
  wire LD0_8;
  wire [1:0]PCENABLECALIB;
  wire [2:0]Q;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ;
  wire freq_refclk;
  wire idelay_inc;
  wire idelay_ld_rst_1;
  wire [3:0]if_d2;
  wire [3:0]if_d3;
  wire [3:0]if_d4;
  wire [3:0]if_d5;
  wire [3:0]if_d6;
  wire [3:0]if_d7;
  wire [3:0]if_d8;
  wire [3:0]if_d9;
  wire if_empty_;
  wire [0:0]if_empty_r;
  wire ififo_rst;
  wire ififo_rst_reg_0;
  wire ififo_wr_enable;
  wire [0:0]in0;
  wire \in_fifo_gen.in_fifo_n_0 ;
  wire \in_fifo_gen.in_fifo_n_1 ;
  wire \in_fifo_gen.in_fifo_n_3 ;
  wire \input_[9].iserdes_dq_.iserdesdq ;
  wire iserdes_clkdiv;
  wire [7:0]mem_dq_in;
  wire [8:0]mem_dq_out;
  wire [8:0]mem_dq_ts;
  wire [0:0]mem_dqs_in;
  wire mem_refclk;
  wire \my_empty_reg[1] ;
  wire \my_empty_reg[4] ;
  wire [0:0]\my_empty_reg[4]_0 ;
  wire [7:0]\my_empty_reg[7] ;
  wire [7:0]\my_empty_reg[7]_0 ;
  wire [7:0]\my_empty_reg[7]_1 ;
  wire [7:0]\my_empty_reg[7]_2 ;
  wire [7:0]\my_empty_reg[7]_3 ;
  wire [7:0]\my_empty_reg[7]_4 ;
  wire [7:0]\my_empty_reg[7]_5 ;
  wire [7:0]\my_empty_reg[7]_6 ;
  wire \my_full_reg[1] ;
  wire \my_full_reg[1]_0 ;
  wire \my_full_reg[1]_1 ;
  wire \my_full_reg[1]_2 ;
  wire \my_full_reg[1]_3 ;
  wire \my_full_reg[1]_4 ;
  wire \my_full_reg[4] ;
  wire [7:0]of_d1;
  wire [39:0]of_dqbus;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_1 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ;
  wire ofifo_rst;
  wire ofs_rdy_r_reg;
  wire ofs_rdy_r_reg_0;
  wire ofs_rdy_r_reg_1;
  wire ofs_rdy_r_reg_2;
  wire oserdes_clk;
  wire oserdes_clk_delayed;
  wire oserdes_clkdiv;
  wire [1:0]oserdes_dq_ts;
  wire [1:0]oserdes_dqs;
  wire [1:0]oserdes_dqs_ts;
  wire out_dqs_6;
  wire out_fifo_0;
  wire [7:0]out_fifo_1;
  wire out_fifo_2;
  wire [71:0]out_fifo_i_75__6;
  wire out_fifo_n_0;
  wire out_fifo_n_1;
  wire out_fifo_n_2;
  wire out_fifo_n_3;
  wire [3:0]phaser_ctl_bus;
  wire \phaser_in_gen.phaser_in_n_1 ;
  wire \phaser_in_gen.phaser_in_n_2 ;
  wire \phaser_in_gen.phaser_in_n_5 ;
  wire \phaser_in_gen.phaser_in_n_6 ;
  wire \phaser_in_gen.phaser_in_n_7 ;
  wire phaser_out_n_0;
  wire phaser_out_n_1;
  wire phy_data_wr_en;
  wire phy_if_reset;
  wire phy_mc_data_full;
  wire \pi_dqs_found_lanes_r1_reg[2] ;
  wire \pi_dqs_found_lanes_r1_reg[2]_0 ;
  wire \pi_dqs_found_lanes_r1_reg[2]_1 ;
  wire \pi_dqs_found_lanes_r1_reg[2]_2 ;
  wire [5:0]\pi_dqs_found_lanes_r1_reg[2]_3 ;
  wire pi_phase_locked_all_r1_reg;
  wire pi_phase_locked_all_r1_reg_0;
  wire pi_phase_locked_all_r1_reg_1;
  wire pi_phase_locked_all_r1_reg_2;
  wire \po_counter_read_val_reg[8] ;
  wire \po_counter_read_val_reg[8]_0 ;
  wire \po_counter_read_val_reg[8]_1 ;
  wire po_oserdes_rst;
  wire po_rd_enable;
  wire [79:0]rd_data;
  wire [79:12]rd_data_r;
  wire [63:0]\rd_ptr_reg[3] ;
  wire rst_r4;
  wire sync_pulse;
  wire ts_dqs_6;
  wire [0:0]\wr_ptr[1]_i_2__6 ;
  wire [7:4]\NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED ;
  wire [7:4]\NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED ;
  wire [7:4]NLW_out_fifo_Q5_UNCONNECTED;
  wire [7:4]NLW_out_fifo_Q6_UNCONNECTED;
  wire NLW_phaser_out_PHASEREFCLK_UNCONNECTED;

  mig_mig_7series_v4_2_ddr_byte_group_io__parameterized0_32 ddr_byte_group_io
       (.A_rst_primitives(A_rst_primitives),
        .CLKB0_8(CLKB0_8),
        .CTSBUS(oserdes_dqs_ts[0]),
        .D2(if_d2),
        .D3(if_d3),
        .D4(if_d4),
        .D5(if_d5),
        .D6(if_d6),
        .D7(if_d7),
        .D8(if_d8),
        .D9(if_d9),
        .DQSBUS(oserdes_dqs),
        .DTSBUS(oserdes_dq_ts),
        .LD0_8(LD0_8),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (A_rst_primitives_reg),
        .idelay_inc(idelay_inc),
        .idelay_ld_rst_1(idelay_ld_rst_1),
        .idelay_ld_rst_reg_0(\my_full_reg[4] ),
        .\input_[9].iserdes_dq_.iserdesdq_0 (\input_[9].iserdes_dq_.iserdesdq ),
        .iserdes_clkdiv(iserdes_clkdiv),
        .mem_dq_in(mem_dq_in),
        .mem_dq_out(mem_dq_out),
        .mem_dq_ts(mem_dq_ts),
        .of_dqbus(of_dqbus[39:4]),
        .oserdes_clk(oserdes_clk),
        .oserdes_clk_delayed(oserdes_clk_delayed),
        .oserdes_clkdiv(oserdes_clkdiv),
        .out_dqs_6(out_dqs_6),
        .po_oserdes_rst(po_oserdes_rst),
        .rst_r4(rst_r4),
        .ts_dqs_6(ts_dqs_6));
  (* syn_maxfan = "3" *) 
  FDRE \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(if_empty_),
        .Q(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[12]),
        .Q(rd_data_r[12]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[13]),
        .Q(rd_data_r[13]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[14]),
        .Q(rd_data_r[14]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[15]),
        .Q(rd_data_r[15]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[16]),
        .Q(rd_data_r[16]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[17]),
        .Q(rd_data_r[17]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[18]),
        .Q(rd_data_r[18]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[19]),
        .Q(rd_data_r[19]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[20]),
        .Q(rd_data_r[20]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[21]),
        .Q(rd_data_r[21]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[22]),
        .Q(rd_data_r[22]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[23]),
        .Q(rd_data_r[23]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[24]),
        .Q(rd_data_r[24]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[25]),
        .Q(rd_data_r[25]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[26]),
        .Q(rd_data_r[26]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[27]),
        .Q(rd_data_r[27]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[28]),
        .Q(rd_data_r[28]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[29]),
        .Q(rd_data_r[29]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[30]),
        .Q(rd_data_r[30]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[31]),
        .Q(rd_data_r[31]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[32]),
        .Q(rd_data_r[32]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[33]),
        .Q(rd_data_r[33]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[34]),
        .Q(rd_data_r[34]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[35]),
        .Q(rd_data_r[35]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[36]),
        .Q(rd_data_r[36]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[37]),
        .Q(rd_data_r[37]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[38]),
        .Q(rd_data_r[38]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[39]),
        .Q(rd_data_r[39]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[40]),
        .Q(rd_data_r[40]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[41]),
        .Q(rd_data_r[41]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[42]),
        .Q(rd_data_r[42]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[43]),
        .Q(rd_data_r[43]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[44]),
        .Q(rd_data_r[44]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[45]),
        .Q(rd_data_r[45]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[46]),
        .Q(rd_data_r[46]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[47]),
        .Q(rd_data_r[47]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[48]),
        .Q(rd_data_r[48]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[49]),
        .Q(rd_data_r[49]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[50]),
        .Q(rd_data_r[50]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[51]),
        .Q(rd_data_r[51]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[52]),
        .Q(rd_data_r[52]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[53]),
        .Q(rd_data_r[53]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[54]),
        .Q(rd_data_r[54]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[55]),
        .Q(rd_data_r[55]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[56]),
        .Q(rd_data_r[56]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[57]),
        .Q(rd_data_r[57]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[58]),
        .Q(rd_data_r[58]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[59]),
        .Q(rd_data_r[59]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[60]),
        .Q(rd_data_r[60]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[61]),
        .Q(rd_data_r[61]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[62]),
        .Q(rd_data_r[62]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[63]),
        .Q(rd_data_r[63]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[64]),
        .Q(rd_data_r[64]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[65]),
        .Q(rd_data_r[65]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[66]),
        .Q(rd_data_r[66]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[67]),
        .Q(rd_data_r[67]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[68]),
        .Q(rd_data_r[68]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[69]),
        .Q(rd_data_r[69]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[70]),
        .Q(rd_data_r[70]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[71]),
        .Q(rd_data_r[71]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[72]),
        .Q(rd_data_r[72]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[73]),
        .Q(rd_data_r[73]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[74]),
        .Q(rd_data_r[74]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[75]),
        .Q(rd_data_r[75]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[76]),
        .Q(rd_data_r[76]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[77]),
        .Q(rd_data_r[77]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[78]),
        .Q(rd_data_r[78]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] 
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(rd_data[79]),
        .Q(rd_data_r[79]),
        .R(1'b0));
  mig_mig_7series_v4_2_ddr_if_post_fifo_33 \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo 
       (.Q(rd_data_r),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ),
        .if_empty_r(if_empty_r),
        .ififo_rst(ififo_rst),
        .\my_empty_reg[4]_0 (\my_empty_reg[4] ),
        .\my_empty_reg[4]_1 (\my_empty_reg[4]_0 ),
        .\my_full_reg[1]_0 (\my_full_reg[1] ),
        .\my_full_reg[1]_1 (\my_full_reg[1]_0 ),
        .\my_full_reg[1]_2 (\my_full_reg[1]_1 ),
        .\my_full_reg[1]_3 (\my_full_reg[1]_2 ),
        .\my_full_reg[1]_4 (\my_full_reg[1]_3 ),
        .\my_full_reg[1]_5 (\my_full_reg[1]_4 ),
        .\rd_ptr_timing_reg[1]_0 (\my_full_reg[4] ),
        .\wr_ptr[1]_i_2__6 (\wr_ptr[1]_i_2__6 ),
        .\wr_ptr_reg[0]_0 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ));
  FDSE #(
    .INIT(1'b1)) 
    ififo_rst_reg
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(ififo_rst_reg_0),
        .Q(ififo_rst),
        .S(phy_if_reset));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IN_FIFO #(
    .ALMOST_EMPTY_VALUE(1),
    .ALMOST_FULL_VALUE(1),
    .ARRAY_MODE("ARRAY_MODE_4_X_8"),
    .SYNCHRONOUS_MODE("FALSE")) 
    \in_fifo_gen.in_fifo 
       (.ALMOSTEMPTY(\in_fifo_gen.in_fifo_n_0 ),
        .ALMOSTFULL(\in_fifo_gen.in_fifo_n_1 ),
        .D0({1'b0,1'b0,1'b0,1'b0}),
        .D1({1'b0,1'b0,1'b0,1'b0}),
        .D2(if_d2),
        .D3(if_d3),
        .D4(if_d4),
        .D5({\NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED [7:4],if_d5}),
        .D6({\NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED [7:4],if_d6}),
        .D7(if_d7),
        .D8(if_d8),
        .D9(if_d9),
        .EMPTY(if_empty_),
        .FULL(\in_fifo_gen.in_fifo_n_3 ),
        .Q0(rd_data[7:0]),
        .Q1(rd_data[15:8]),
        .Q2(rd_data[23:16]),
        .Q3(rd_data[31:24]),
        .Q4(rd_data[39:32]),
        .Q5(rd_data[47:40]),
        .Q6(rd_data[55:48]),
        .Q7(rd_data[63:56]),
        .Q8(rd_data[71:64]),
        .Q9(rd_data[79:72]),
        .RDCLK(\my_full_reg[4] ),
        .RDEN(1'b1),
        .RESET(ififo_rst),
        .WRCLK(iserdes_clkdiv),
        .WREN(ififo_wr_enable));
  mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_34 \of_pre_fifo_gen.u_ddr_of_pre_fifo 
       (.D0({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 }),
        .D1(of_d1),
        .Q(Q),
        .\my_empty_reg[1]_0 (\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_1 ),
        .\my_empty_reg[1]_1 (\my_empty_reg[1] ),
        .\my_empty_reg[7]_0 (out_fifo_n_3),
        .\my_full_reg[4]_0 (\my_full_reg[4] ),
        .ofifo_rst(ofifo_rst),
        .ofs_rdy_r_reg(ofs_rdy_r_reg),
        .ofs_rdy_r_reg_0(ofs_rdy_r_reg_0),
        .ofs_rdy_r_reg_1(ofs_rdy_r_reg_1),
        .ofs_rdy_r_reg_2(ofs_rdy_r_reg_2),
        .out_fifo(out_fifo_0),
        .out_fifo_0(out_fifo_1),
        .out_fifo_1(out_fifo_2),
        .out_fifo_i_75__6(out_fifo_i_75__6),
        .phy_data_wr_en(phy_data_wr_en),
        .phy_mc_data_full(phy_mc_data_full),
        .\rd_ptr_reg[3]_0 (\rd_ptr_reg[3] ));
  FDSE #(
    .INIT(1'b1)) 
    ofifo_rst_reg
       (.C(\my_full_reg[4] ),
        .CE(1'b1),
        .D(ififo_rst_reg_0),
        .Q(ofifo_rst),
        .S(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OUT_FIFO #(
    .ALMOST_EMPTY_VALUE(1),
    .ALMOST_FULL_VALUE(1),
    .ARRAY_MODE("ARRAY_MODE_8_X_4"),
    .OUTPUT_DISABLE("FALSE"),
    .SYNCHRONOUS_MODE("FALSE")) 
    out_fifo
       (.ALMOSTEMPTY(out_fifo_n_0),
        .ALMOSTFULL(out_fifo_n_1),
        .D0({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 }),
        .D1(of_d1),
        .D2(\my_empty_reg[7] ),
        .D3(\my_empty_reg[7]_0 ),
        .D4(\my_empty_reg[7]_1 ),
        .D5(\my_empty_reg[7]_2 ),
        .D6(\my_empty_reg[7]_3 ),
        .D7(\my_empty_reg[7]_4 ),
        .D8(\my_empty_reg[7]_5 ),
        .D9(\my_empty_reg[7]_6 ),
        .EMPTY(out_fifo_n_2),
        .FULL(out_fifo_n_3),
        .Q0(of_dqbus[3:0]),
        .Q1(of_dqbus[7:4]),
        .Q2(of_dqbus[11:8]),
        .Q3(of_dqbus[15:12]),
        .Q4(of_dqbus[19:16]),
        .Q5({NLW_out_fifo_Q5_UNCONNECTED[7:4],of_dqbus[23:20]}),
        .Q6({NLW_out_fifo_Q6_UNCONNECTED[7:4],of_dqbus[27:24]}),
        .Q7(of_dqbus[31:28]),
        .Q8(of_dqbus[35:32]),
        .Q9(of_dqbus[39:36]),
        .RDCLK(oserdes_clkdiv),
        .RDEN(po_rd_enable),
        .RESET(ofifo_rst),
        .WRCLK(\my_full_reg[4] ),
        .WREN(\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_1 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  PHASER_IN_PHY #(
    .BURST_MODE("TRUE"),
    .CLKOUT_DIV(2),
    .DQS_AUTO_RECAL(1'b1),
    .DQS_BIAS_MODE("FALSE"),
    .DQS_FIND_PATTERN(3'b000),
    .FINE_DELAY(33),
    .FREQ_REF_DIV("DIV2"),
    .IS_RST_INVERTED(1'b0),
    .MEMREFCLK_PERIOD(2.500000),
    .OUTPUT_CLK_SRC("DELAYED_REF"),
    .PHASEREFCLK_PERIOD(2.500000),
    .REFCLK_PERIOD(1.250000),
    .SEL_CLK_OFFSET(6),
    .SYNC_IN_DIV_RST("TRUE"),
    .WR_CYCLES("FALSE")) 
    \phaser_in_gen.phaser_in 
       (.BURSTPENDINGPHY(phaser_ctl_bus[1]),
        .COUNTERLOADEN(\pi_dqs_found_lanes_r1_reg[2] ),
        .COUNTERLOADVAL(\pi_dqs_found_lanes_r1_reg[2]_3 ),
        .COUNTERREADEN(\pi_dqs_found_lanes_r1_reg[2]_0 ),
        .COUNTERREADVAL(A_rst_primitives_reg_0),
        .DQSFOUND(in0),
        .DQSOUTOFRANGE(\phaser_in_gen.phaser_in_n_1 ),
        .ENCALIBPHY(PCENABLECALIB),
        .FINEENABLE(\pi_dqs_found_lanes_r1_reg[2]_1 ),
        .FINEINC(\pi_dqs_found_lanes_r1_reg[2]_2 ),
        .FINEOVERFLOW(\phaser_in_gen.phaser_in_n_2 ),
        .FREQREFCLK(freq_refclk),
        .ICLK(A_rst_primitives_reg),
        .ICLKDIV(iserdes_clkdiv),
        .ISERDESRST(\phaser_in_gen.phaser_in_n_5 ),
        .MEMREFCLK(mem_refclk),
        .PHASELOCKED(\phaser_in_gen.phaser_in_n_6 ),
        .PHASEREFCLK(mem_dqs_in),
        .RANKSELPHY(phaser_ctl_bus[3:2]),
        .RCLK(\phaser_in_gen.phaser_in_n_7 ),
        .RST(A_rst_primitives),
        .RSTDQSFIND(ififo_rst_reg_0),
        .SYNCIN(sync_pulse),
        .SYSCLK(\my_full_reg[4] ),
        .WRENABLE(ififo_wr_enable));
  (* BOX_TYPE = "PRIMITIVE" *) 
  PHASER_OUT_PHY #(
    .CLKOUT_DIV(2),
    .COARSE_BYPASS("FALSE"),
    .COARSE_DELAY(0),
    .DATA_CTL_N("TRUE"),
    .DATA_RD_CYCLES("FALSE"),
    .FINE_DELAY(60),
    .IS_RST_INVERTED(1'b0),
    .MEMREFCLK_PERIOD(2.500000),
    .OCLKDELAY_INV("FALSE"),
    .OCLK_DELAY(0),
    .OUTPUT_CLK_SRC("DELAYED_REF"),
    .PHASEREFCLK_PERIOD(1.000000),
    .PO(3'b111),
    .REFCLK_PERIOD(1.250000),
    .SYNC_IN_DIV_RST("TRUE")) 
    phaser_out
       (.BURSTPENDINGPHY(phaser_ctl_bus[0]),
        .COARSEENABLE(\po_counter_read_val_reg[8] ),
        .COARSEINC(\po_counter_read_val_reg[8] ),
        .COARSEOVERFLOW(phaser_out_n_0),
        .COUNTERLOADEN(1'b0),
        .COUNTERLOADVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .COUNTERREADEN(\pi_dqs_found_lanes_r1_reg[2]_0 ),
        .COUNTERREADVAL(A_rst_primitives_reg_1),
        .CTSBUS(oserdes_dqs_ts),
        .DQSBUS(oserdes_dqs),
        .DTSBUS(oserdes_dq_ts),
        .ENCALIBPHY(PCENABLECALIB),
        .FINEENABLE(\po_counter_read_val_reg[8]_0 ),
        .FINEINC(\po_counter_read_val_reg[8]_1 ),
        .FINEOVERFLOW(phaser_out_n_1),
        .FREQREFCLK(freq_refclk),
        .MEMREFCLK(mem_refclk),
        .OCLK(oserdes_clk),
        .OCLKDELAYED(oserdes_clk_delayed),
        .OCLKDIV(oserdes_clkdiv),
        .OSERDESRST(po_oserdes_rst),
        .PHASEREFCLK(NLW_phaser_out_PHASEREFCLK_UNCONNECTED),
        .RDENABLE(po_rd_enable),
        .RST(A_rst_primitives),
        .SELFINEOCLKDELAY(1'b0),
        .SYNCIN(sync_pulse),
        .SYSCLK(\my_full_reg[4] ));
  LUT5 #(
    .INIT(32'h80000000)) 
    pi_phase_locked_all_inferred_i_1
       (.I0(\phaser_in_gen.phaser_in_n_6 ),
        .I1(pi_phase_locked_all_r1_reg),
        .I2(pi_phase_locked_all_r1_reg_0),
        .I3(pi_phase_locked_all_r1_reg_1),
        .I4(pi_phase_locked_all_r1_reg_2),
        .O(A_rst_primitives_reg_2));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_byte_lane" *) 
module mig_mig_7series_v4_2_ddr_byte_lane__parameterized2
   (out_dqs_3,
    ts_dqs_3,
    A_rst_primitives_reg,
    mem_dq_out,
    mem_dq_ts,
    in0,
    A_rst_primitives_reg_0,
    A_rst_primitives_reg_1,
    idelay_ld_rst_6,
    rst_r4,
    \my_empty_reg[1] ,
    A_rst_primitives_reg_2,
    \rd_mux_sel_r_reg[2] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ,
    \rd_mux_sel_r_reg[2]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ,
    \rd_mux_sel_r_reg[2]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ,
    \rd_mux_sel_r_reg[2]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ,
    \rd_mux_sel_r_reg[2]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ,
    \rd_mux_sel_r_reg[2]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ,
    \rd_mux_sel_r_reg[2]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ,
    \rd_mux_sel_r_reg[2]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ,
    \rd_mux_sel_r_reg[2]_7 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ,
    \rd_mux_sel_r_reg[2]_8 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ,
    \rd_mux_sel_r_reg[2]_9 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ,
    \rd_mux_sel_r_reg[2]_10 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ,
    \rd_mux_sel_r_reg[2]_11 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ,
    \rd_mux_sel_r_reg[2]_12 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ,
    \rd_mux_sel_r_reg[2]_13 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ,
    \rd_mux_sel_r_reg[2]_14 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 ,
    \rd_mux_sel_r_reg[2]_15 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ,
    \rd_mux_sel_r_reg[2]_16 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ,
    \rd_mux_sel_r_reg[2]_17 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ,
    \rd_mux_sel_r_reg[2]_18 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ,
    \rd_mux_sel_r_reg[2]_19 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ,
    \rd_mux_sel_r_reg[2]_20 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ,
    \rd_mux_sel_r_reg[2]_21 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ,
    \rd_mux_sel_r_reg[2]_22 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 ,
    \rd_mux_sel_r_reg[2]_23 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ,
    \rd_mux_sel_r_reg[2]_24 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ,
    \rd_mux_sel_r_reg[2]_25 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ,
    \rd_mux_sel_r_reg[2]_26 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ,
    \rd_mux_sel_r_reg[2]_27 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ,
    \rd_mux_sel_r_reg[2]_28 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ,
    \rd_mux_sel_r_reg[2]_29 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ,
    \rd_mux_sel_r_reg[2]_30 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 ,
    \rd_mux_sel_r_reg[2]_31 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ,
    \rd_mux_sel_r_reg[2]_32 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ,
    \rd_mux_sel_r_reg[2]_33 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ,
    \rd_mux_sel_r_reg[2]_34 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ,
    \rd_mux_sel_r_reg[2]_35 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ,
    \rd_mux_sel_r_reg[2]_36 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ,
    \rd_mux_sel_r_reg[2]_37 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ,
    \rd_mux_sel_r_reg[2]_38 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 ,
    \rd_mux_sel_r_reg[2]_39 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ,
    \rd_mux_sel_r_reg[2]_40 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ,
    \rd_mux_sel_r_reg[2]_41 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ,
    \rd_mux_sel_r_reg[2]_42 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ,
    \rd_mux_sel_r_reg[2]_43 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ,
    \rd_mux_sel_r_reg[2]_44 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ,
    \rd_mux_sel_r_reg[2]_45 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ,
    \rd_mux_sel_r_reg[2]_46 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 ,
    \rd_mux_sel_r_reg[2]_47 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ,
    \rd_mux_sel_r_reg[2]_48 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ,
    \rd_mux_sel_r_reg[2]_49 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ,
    \rd_mux_sel_r_reg[2]_50 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ,
    \rd_mux_sel_r_reg[2]_51 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ,
    \rd_mux_sel_r_reg[2]_52 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ,
    \rd_mux_sel_r_reg[2]_53 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ,
    \rd_mux_sel_r_reg[2]_54 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 ,
    \rd_mux_sel_r_reg[2]_55 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ,
    \rd_mux_sel_r_reg[2]_56 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ,
    \rd_mux_sel_r_reg[2]_57 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ,
    \rd_mux_sel_r_reg[2]_58 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ,
    \rd_mux_sel_r_reg[2]_59 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ,
    \rd_mux_sel_r_reg[2]_60 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ,
    \rd_mux_sel_r_reg[2]_61 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ,
    \rd_mux_sel_r_reg[2]_62 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ,
    p_0_out,
    \po_stg2_wrcal_cnt_reg[2] ,
    \po_stg2_wrcal_cnt_reg[2]_0 ,
    \po_stg2_wrcal_cnt_reg[2]_1 ,
    \po_stg2_wrcal_cnt_reg[2]_2 ,
    \po_stg2_wrcal_cnt_reg[2]_3 ,
    \po_stg2_wrcal_cnt_reg[2]_4 ,
    \po_stg2_wrcal_cnt_reg[2]_5 ,
    \po_stg2_wrcal_cnt_reg[2]_6 ,
    \po_stg2_wrcal_cnt_reg[2]_7 ,
    \po_stg2_wrcal_cnt_reg[2]_8 ,
    \po_stg2_wrcal_cnt_reg[2]_9 ,
    \po_stg2_wrcal_cnt_reg[2]_10 ,
    \po_stg2_wrcal_cnt_reg[2]_11 ,
    \po_stg2_wrcal_cnt_reg[2]_12 ,
    \po_stg2_wrcal_cnt_reg[2]_13 ,
    \po_stg2_wrcal_cnt_reg[2]_14 ,
    \po_stg2_wrcal_cnt_reg[2]_15 ,
    \po_stg2_wrcal_cnt_reg[2]_16 ,
    \po_stg2_wrcal_cnt_reg[2]_17 ,
    \po_stg2_wrcal_cnt_reg[2]_18 ,
    \po_stg2_wrcal_cnt_reg[2]_19 ,
    \po_stg2_wrcal_cnt_reg[2]_20 ,
    \po_stg2_wrcal_cnt_reg[2]_21 ,
    \po_stg2_wrcal_cnt_reg[2]_22 ,
    \po_stg2_wrcal_cnt_reg[2]_23 ,
    \po_stg2_wrcal_cnt_reg[2]_24 ,
    \po_stg2_wrcal_cnt_reg[2]_25 ,
    \po_stg2_wrcal_cnt_reg[2]_26 ,
    \po_stg2_wrcal_cnt_reg[2]_27 ,
    \po_stg2_wrcal_cnt_reg[2]_28 ,
    \po_stg2_wrcal_cnt_reg[2]_29 ,
    \po_stg2_wrcal_cnt_reg[2]_30 ,
    \po_stg2_wrcal_cnt_reg[2]_31 ,
    \po_stg2_wrcal_cnt_reg[2]_32 ,
    \po_stg2_wrcal_cnt_reg[2]_33 ,
    \po_stg2_wrcal_cnt_reg[2]_34 ,
    \po_stg2_wrcal_cnt_reg[2]_35 ,
    \po_stg2_wrcal_cnt_reg[2]_36 ,
    \po_stg2_wrcal_cnt_reg[2]_37 ,
    \po_stg2_wrcal_cnt_reg[2]_38 ,
    \po_stg2_wrcal_cnt_reg[2]_39 ,
    \po_stg2_wrcal_cnt_reg[2]_40 ,
    \po_stg2_wrcal_cnt_reg[2]_41 ,
    \po_stg2_wrcal_cnt_reg[2]_42 ,
    \po_stg2_wrcal_cnt_reg[2]_43 ,
    \po_stg2_wrcal_cnt_reg[2]_44 ,
    \po_stg2_wrcal_cnt_reg[2]_45 ,
    \po_stg2_wrcal_cnt_reg[2]_46 ,
    \po_stg2_wrcal_cnt_reg[2]_47 ,
    \po_stg2_wrcal_cnt_reg[2]_48 ,
    \po_stg2_wrcal_cnt_reg[2]_49 ,
    \po_stg2_wrcal_cnt_reg[2]_50 ,
    \po_stg2_wrcal_cnt_reg[2]_51 ,
    \po_stg2_wrcal_cnt_reg[2]_52 ,
    \po_stg2_wrcal_cnt_reg[2]_53 ,
    \po_stg2_wrcal_cnt_reg[2]_54 ,
    \po_stg2_wrcal_cnt_reg[2]_55 ,
    \po_stg2_wrcal_cnt_reg[2]_56 ,
    \po_stg2_wrcal_cnt_reg[2]_57 ,
    \po_stg2_wrcal_cnt_reg[2]_58 ,
    \po_stg2_wrcal_cnt_reg[2]_59 ,
    \po_stg2_wrcal_cnt_reg[2]_60 ,
    \po_stg2_wrcal_cnt_reg[2]_61 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ,
    if_empty_v,
    \rd_ptr_reg[3] ,
    Q,
    \entry_cnt_reg[4] ,
    \input_[9].iserdes_dq_.iserdesdq ,
    mem_dq_in,
    idelay_inc,
    LD0_13,
    A_rst_primitives,
    CLKB0_13,
    phaser_ctl_bus,
    \pi_dqs_found_lanes_r1_reg[11] ,
    \pi_dqs_found_lanes_r1_reg[11]_0 ,
    \pi_dqs_found_lanes_r1_reg[11]_1 ,
    \pi_dqs_found_lanes_r1_reg[11]_2 ,
    freq_refclk,
    mem_refclk,
    mem_dqs_in,
    ififo_rst_reg_0,
    sync_pulse,
    PCENABLECALIB,
    \pi_dqs_found_lanes_r1_reg[11]_3 ,
    \po_counter_read_val_reg[8] ,
    \po_counter_read_val_reg[8]_0 ,
    \po_counter_read_val_reg[8]_1 ,
    \my_empty_reg[7] ,
    \my_empty_reg[7]_0 ,
    \my_empty_reg[7]_1 ,
    \my_empty_reg[7]_2 ,
    \my_empty_reg[7]_3 ,
    \my_empty_reg[7]_4 ,
    \my_empty_reg[7]_5 ,
    \my_empty_reg[7]_6 ,
    phy_if_reset,
    \my_full_reg[1] ,
    phy_data_wr_en,
    out_fifo_0,
    out_fifo_1,
    out_fifo_2,
    pi_phase_locked_all_r1_reg,
    pi_phase_locked_all_r1_reg_0,
    pi_phase_locked_all_r1_reg_1,
    \gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ,
    \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1 ,
    \gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1 ,
    \gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1 ,
    \gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 ,
    \gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_1 ,
    \gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_1 ,
    \gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_1 ,
    \gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_1 ,
    \gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_1 ,
    \gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 ,
    \gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_1 ,
    \gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 ,
    \gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_1 ,
    \gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 ,
    \gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_1 ,
    \gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 ,
    \gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_1 ,
    \gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 ,
    \gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_1 ,
    \gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 ,
    \gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_1 ,
    \gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 ,
    \gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_1 ,
    \gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 ,
    \gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_1 ,
    \gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 ,
    \gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_1 ,
    \gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 ,
    \gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_1 ,
    \gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 ,
    \gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_1 ,
    \gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 ,
    \gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_1 ,
    \gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 ,
    \gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_1 ,
    \gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 ,
    \gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_1 ,
    \gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 ,
    \gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_1 ,
    \gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 ,
    \gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_1 ,
    \gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 ,
    \gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_1 ,
    \gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 ,
    \gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_1 ,
    \gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 ,
    \gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_1 ,
    \gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 ,
    \gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_1 ,
    \gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 ,
    \gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_1 ,
    \gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 ,
    \gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_1 ,
    \gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 ,
    \gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_1 ,
    \gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 ,
    \gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_1 ,
    \gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1 ,
    \gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_1 ,
    \gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 ,
    \gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_1 ,
    \gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 ,
    \gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_1 ,
    \gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_3 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_2 ,
    \my_full_reg[1]_0 ,
    \my_full_reg[1]_1 ,
    \my_full_reg[1]_2 ,
    \my_full_reg[1]_3 ,
    \my_full_reg[1]_4 ,
    phy_if_empty_r_reg,
    if_empty_r,
    phy_if_empty_r_reg_0,
    out_fifo_i_75__3);
  output out_dqs_3;
  output ts_dqs_3;
  output A_rst_primitives_reg;
  output [8:0]mem_dq_out;
  output [8:0]mem_dq_ts;
  output [0:0]in0;
  output [5:0]A_rst_primitives_reg_0;
  output [8:0]A_rst_primitives_reg_1;
  output idelay_ld_rst_6;
  output rst_r4;
  output \my_empty_reg[1] ;
  output A_rst_primitives_reg_2;
  output \rd_mux_sel_r_reg[2] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ;
  output \rd_mux_sel_r_reg[2]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;
  output \rd_mux_sel_r_reg[2]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ;
  output \rd_mux_sel_r_reg[2]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ;
  output \rd_mux_sel_r_reg[2]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ;
  output \rd_mux_sel_r_reg[2]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ;
  output \rd_mux_sel_r_reg[2]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ;
  output \rd_mux_sel_r_reg[2]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ;
  output \rd_mux_sel_r_reg[2]_7 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ;
  output \rd_mux_sel_r_reg[2]_8 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ;
  output \rd_mux_sel_r_reg[2]_9 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ;
  output \rd_mux_sel_r_reg[2]_10 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ;
  output \rd_mux_sel_r_reg[2]_11 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ;
  output \rd_mux_sel_r_reg[2]_12 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ;
  output \rd_mux_sel_r_reg[2]_13 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ;
  output \rd_mux_sel_r_reg[2]_14 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 ;
  output \rd_mux_sel_r_reg[2]_15 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ;
  output \rd_mux_sel_r_reg[2]_16 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ;
  output \rd_mux_sel_r_reg[2]_17 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ;
  output \rd_mux_sel_r_reg[2]_18 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ;
  output \rd_mux_sel_r_reg[2]_19 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ;
  output \rd_mux_sel_r_reg[2]_20 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ;
  output \rd_mux_sel_r_reg[2]_21 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ;
  output \rd_mux_sel_r_reg[2]_22 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 ;
  output \rd_mux_sel_r_reg[2]_23 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ;
  output \rd_mux_sel_r_reg[2]_24 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ;
  output \rd_mux_sel_r_reg[2]_25 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ;
  output \rd_mux_sel_r_reg[2]_26 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ;
  output \rd_mux_sel_r_reg[2]_27 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ;
  output \rd_mux_sel_r_reg[2]_28 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ;
  output \rd_mux_sel_r_reg[2]_29 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ;
  output \rd_mux_sel_r_reg[2]_30 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 ;
  output \rd_mux_sel_r_reg[2]_31 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ;
  output \rd_mux_sel_r_reg[2]_32 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ;
  output \rd_mux_sel_r_reg[2]_33 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ;
  output \rd_mux_sel_r_reg[2]_34 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ;
  output \rd_mux_sel_r_reg[2]_35 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ;
  output \rd_mux_sel_r_reg[2]_36 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ;
  output \rd_mux_sel_r_reg[2]_37 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ;
  output \rd_mux_sel_r_reg[2]_38 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 ;
  output \rd_mux_sel_r_reg[2]_39 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ;
  output \rd_mux_sel_r_reg[2]_40 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ;
  output \rd_mux_sel_r_reg[2]_41 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ;
  output \rd_mux_sel_r_reg[2]_42 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ;
  output \rd_mux_sel_r_reg[2]_43 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ;
  output \rd_mux_sel_r_reg[2]_44 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ;
  output \rd_mux_sel_r_reg[2]_45 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ;
  output \rd_mux_sel_r_reg[2]_46 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 ;
  output \rd_mux_sel_r_reg[2]_47 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ;
  output \rd_mux_sel_r_reg[2]_48 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ;
  output \rd_mux_sel_r_reg[2]_49 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ;
  output \rd_mux_sel_r_reg[2]_50 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ;
  output \rd_mux_sel_r_reg[2]_51 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ;
  output \rd_mux_sel_r_reg[2]_52 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ;
  output \rd_mux_sel_r_reg[2]_53 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ;
  output \rd_mux_sel_r_reg[2]_54 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 ;
  output \rd_mux_sel_r_reg[2]_55 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ;
  output \rd_mux_sel_r_reg[2]_56 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ;
  output \rd_mux_sel_r_reg[2]_57 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ;
  output \rd_mux_sel_r_reg[2]_58 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ;
  output \rd_mux_sel_r_reg[2]_59 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ;
  output \rd_mux_sel_r_reg[2]_60 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ;
  output \rd_mux_sel_r_reg[2]_61 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ;
  output \rd_mux_sel_r_reg[2]_62 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ;
  output p_0_out;
  output \po_stg2_wrcal_cnt_reg[2] ;
  output \po_stg2_wrcal_cnt_reg[2]_0 ;
  output \po_stg2_wrcal_cnt_reg[2]_1 ;
  output \po_stg2_wrcal_cnt_reg[2]_2 ;
  output \po_stg2_wrcal_cnt_reg[2]_3 ;
  output \po_stg2_wrcal_cnt_reg[2]_4 ;
  output \po_stg2_wrcal_cnt_reg[2]_5 ;
  output \po_stg2_wrcal_cnt_reg[2]_6 ;
  output \po_stg2_wrcal_cnt_reg[2]_7 ;
  output \po_stg2_wrcal_cnt_reg[2]_8 ;
  output \po_stg2_wrcal_cnt_reg[2]_9 ;
  output \po_stg2_wrcal_cnt_reg[2]_10 ;
  output \po_stg2_wrcal_cnt_reg[2]_11 ;
  output \po_stg2_wrcal_cnt_reg[2]_12 ;
  output \po_stg2_wrcal_cnt_reg[2]_13 ;
  output \po_stg2_wrcal_cnt_reg[2]_14 ;
  output \po_stg2_wrcal_cnt_reg[2]_15 ;
  output \po_stg2_wrcal_cnt_reg[2]_16 ;
  output \po_stg2_wrcal_cnt_reg[2]_17 ;
  output \po_stg2_wrcal_cnt_reg[2]_18 ;
  output \po_stg2_wrcal_cnt_reg[2]_19 ;
  output \po_stg2_wrcal_cnt_reg[2]_20 ;
  output \po_stg2_wrcal_cnt_reg[2]_21 ;
  output \po_stg2_wrcal_cnt_reg[2]_22 ;
  output \po_stg2_wrcal_cnt_reg[2]_23 ;
  output \po_stg2_wrcal_cnt_reg[2]_24 ;
  output \po_stg2_wrcal_cnt_reg[2]_25 ;
  output \po_stg2_wrcal_cnt_reg[2]_26 ;
  output \po_stg2_wrcal_cnt_reg[2]_27 ;
  output \po_stg2_wrcal_cnt_reg[2]_28 ;
  output \po_stg2_wrcal_cnt_reg[2]_29 ;
  output \po_stg2_wrcal_cnt_reg[2]_30 ;
  output \po_stg2_wrcal_cnt_reg[2]_31 ;
  output \po_stg2_wrcal_cnt_reg[2]_32 ;
  output \po_stg2_wrcal_cnt_reg[2]_33 ;
  output \po_stg2_wrcal_cnt_reg[2]_34 ;
  output \po_stg2_wrcal_cnt_reg[2]_35 ;
  output \po_stg2_wrcal_cnt_reg[2]_36 ;
  output \po_stg2_wrcal_cnt_reg[2]_37 ;
  output \po_stg2_wrcal_cnt_reg[2]_38 ;
  output \po_stg2_wrcal_cnt_reg[2]_39 ;
  output \po_stg2_wrcal_cnt_reg[2]_40 ;
  output \po_stg2_wrcal_cnt_reg[2]_41 ;
  output \po_stg2_wrcal_cnt_reg[2]_42 ;
  output \po_stg2_wrcal_cnt_reg[2]_43 ;
  output \po_stg2_wrcal_cnt_reg[2]_44 ;
  output \po_stg2_wrcal_cnt_reg[2]_45 ;
  output \po_stg2_wrcal_cnt_reg[2]_46 ;
  output \po_stg2_wrcal_cnt_reg[2]_47 ;
  output \po_stg2_wrcal_cnt_reg[2]_48 ;
  output \po_stg2_wrcal_cnt_reg[2]_49 ;
  output \po_stg2_wrcal_cnt_reg[2]_50 ;
  output \po_stg2_wrcal_cnt_reg[2]_51 ;
  output \po_stg2_wrcal_cnt_reg[2]_52 ;
  output \po_stg2_wrcal_cnt_reg[2]_53 ;
  output \po_stg2_wrcal_cnt_reg[2]_54 ;
  output \po_stg2_wrcal_cnt_reg[2]_55 ;
  output \po_stg2_wrcal_cnt_reg[2]_56 ;
  output \po_stg2_wrcal_cnt_reg[2]_57 ;
  output \po_stg2_wrcal_cnt_reg[2]_58 ;
  output \po_stg2_wrcal_cnt_reg[2]_59 ;
  output \po_stg2_wrcal_cnt_reg[2]_60 ;
  output \po_stg2_wrcal_cnt_reg[2]_61 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ;
  output [0:0]if_empty_v;
  output [63:0]\rd_ptr_reg[3] ;
  output [2:0]Q;
  input \entry_cnt_reg[4] ;
  input \input_[9].iserdes_dq_.iserdesdq ;
  input [7:0]mem_dq_in;
  input idelay_inc;
  input LD0_13;
  input A_rst_primitives;
  input CLKB0_13;
  input [3:0]phaser_ctl_bus;
  input \pi_dqs_found_lanes_r1_reg[11] ;
  input \pi_dqs_found_lanes_r1_reg[11]_0 ;
  input \pi_dqs_found_lanes_r1_reg[11]_1 ;
  input \pi_dqs_found_lanes_r1_reg[11]_2 ;
  input freq_refclk;
  input mem_refclk;
  input [0:0]mem_dqs_in;
  input ififo_rst_reg_0;
  input sync_pulse;
  input [1:0]PCENABLECALIB;
  input [5:0]\pi_dqs_found_lanes_r1_reg[11]_3 ;
  input \po_counter_read_val_reg[8] ;
  input \po_counter_read_val_reg[8]_0 ;
  input \po_counter_read_val_reg[8]_1 ;
  input [7:0]\my_empty_reg[7] ;
  input [7:0]\my_empty_reg[7]_0 ;
  input [7:0]\my_empty_reg[7]_1 ;
  input [7:0]\my_empty_reg[7]_2 ;
  input [7:0]\my_empty_reg[7]_3 ;
  input [7:0]\my_empty_reg[7]_4 ;
  input [7:0]\my_empty_reg[7]_5 ;
  input [7:0]\my_empty_reg[7]_6 ;
  input phy_if_reset;
  input \my_full_reg[1] ;
  input phy_data_wr_en;
  input out_fifo_0;
  input [7:0]out_fifo_1;
  input out_fifo_2;
  input pi_phase_locked_all_r1_reg;
  input pi_phase_locked_all_r1_reg_0;
  input pi_phase_locked_all_r1_reg_1;
  input [2:0]\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ;
  input \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1 ;
  input \gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1 ;
  input \gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1 ;
  input \gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 ;
  input \gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_1 ;
  input \gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_1 ;
  input \gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_1 ;
  input \gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_1 ;
  input \gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_1 ;
  input \gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 ;
  input \gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_1 ;
  input \gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 ;
  input \gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_1 ;
  input \gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 ;
  input \gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_1 ;
  input \gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 ;
  input \gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_1 ;
  input \gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 ;
  input \gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_1 ;
  input \gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 ;
  input \gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_1 ;
  input \gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 ;
  input \gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_1 ;
  input \gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 ;
  input \gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_1 ;
  input \gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 ;
  input \gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_1 ;
  input \gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 ;
  input \gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_1 ;
  input \gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 ;
  input \gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_1 ;
  input \gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 ;
  input \gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_1 ;
  input \gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 ;
  input \gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_1 ;
  input \gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 ;
  input \gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_1 ;
  input \gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 ;
  input \gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_1 ;
  input \gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 ;
  input \gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_1 ;
  input \gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 ;
  input \gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_1 ;
  input \gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 ;
  input \gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_1 ;
  input \gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 ;
  input \gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_1 ;
  input \gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 ;
  input \gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_1 ;
  input \gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 ;
  input \gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_1 ;
  input \gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 ;
  input \gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_1 ;
  input \gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 ;
  input \gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_1 ;
  input \gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 ;
  input \gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_1 ;
  input \gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1 ;
  input \gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_1 ;
  input \gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 ;
  input \gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_1 ;
  input \gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 ;
  input \gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_1 ;
  input \gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 ;
  input [2:0]\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_3 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_2 ;
  input \my_full_reg[1]_0 ;
  input \my_full_reg[1]_1 ;
  input \my_full_reg[1]_2 ;
  input \my_full_reg[1]_3 ;
  input \my_full_reg[1]_4 ;
  input [0:0]phy_if_empty_r_reg;
  input [0:0]if_empty_r;
  input phy_if_empty_r_reg_0;
  input [71:0]out_fifo_i_75__3;

  wire A_rst_primitives;
  wire A_rst_primitives_reg;
  wire [5:0]A_rst_primitives_reg_0;
  wire [8:0]A_rst_primitives_reg_1;
  wire A_rst_primitives_reg_2;
  wire CLKB0_13;
  wire LD0_13;
  wire [1:0]PCENABLECALIB;
  wire [2:0]Q;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ;
  wire \entry_cnt_reg[4] ;
  wire freq_refclk;
  wire \gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ;
  wire [2:0]\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]_0 ;
  wire \gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ;
  wire \gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ;
  wire \gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ;
  wire \gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ;
  wire \gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ;
  wire \gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ;
  wire \gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ;
  wire \gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_1 ;
  wire [2:0]\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_3 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_2 ;
  wire idelay_inc;
  wire idelay_ld_rst_6;
  wire [3:0]if_d2;
  wire [3:0]if_d3;
  wire [3:0]if_d4;
  wire [3:0]if_d5;
  wire [3:0]if_d6;
  wire [3:0]if_d7;
  wire [3:0]if_d8;
  wire [3:0]if_d9;
  wire if_empty_;
  wire [0:0]if_empty_r;
  wire [3:3]if_empty_r_0;
  wire [0:0]if_empty_v;
  wire ififo_rst;
  wire ififo_rst_reg_0;
  wire ififo_wr_enable;
  wire [0:0]in0;
  wire \in_fifo_gen.in_fifo_n_0 ;
  wire \in_fifo_gen.in_fifo_n_1 ;
  wire \in_fifo_gen.in_fifo_n_3 ;
  wire \input_[9].iserdes_dq_.iserdesdq ;
  wire iserdes_clkdiv;
  wire [7:0]mem_dq_in;
  wire [8:0]mem_dq_out;
  wire [8:0]mem_dq_ts;
  wire [0:0]mem_dqs_in;
  wire mem_refclk;
  wire \my_empty_reg[1] ;
  wire [7:0]\my_empty_reg[7] ;
  wire [7:0]\my_empty_reg[7]_0 ;
  wire [7:0]\my_empty_reg[7]_1 ;
  wire [7:0]\my_empty_reg[7]_2 ;
  wire [7:0]\my_empty_reg[7]_3 ;
  wire [7:0]\my_empty_reg[7]_4 ;
  wire [7:0]\my_empty_reg[7]_5 ;
  wire [7:0]\my_empty_reg[7]_6 ;
  wire \my_full_reg[1] ;
  wire \my_full_reg[1]_0 ;
  wire \my_full_reg[1]_1 ;
  wire \my_full_reg[1]_2 ;
  wire \my_full_reg[1]_3 ;
  wire \my_full_reg[1]_4 ;
  wire [7:0]of_d1;
  wire [39:0]of_dqbus;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ;
  wire ofifo_rst;
  wire oserdes_clk;
  wire oserdes_clk_delayed;
  wire oserdes_clkdiv;
  wire [1:0]oserdes_dq_ts;
  wire [1:0]oserdes_dqs;
  wire [1:0]oserdes_dqs_ts;
  wire out_dqs_3;
  wire out_fifo_0;
  wire [7:0]out_fifo_1;
  wire out_fifo_2;
  wire [71:0]out_fifo_i_75__3;
  wire out_fifo_n_0;
  wire out_fifo_n_1;
  wire out_fifo_n_2;
  wire out_fifo_n_3;
  wire p_0_out;
  wire [3:0]phaser_ctl_bus;
  wire \phaser_in_gen.phaser_in_n_1 ;
  wire \phaser_in_gen.phaser_in_n_2 ;
  wire \phaser_in_gen.phaser_in_n_5 ;
  wire \phaser_in_gen.phaser_in_n_6 ;
  wire \phaser_in_gen.phaser_in_n_7 ;
  wire phaser_out_n_0;
  wire phaser_out_n_1;
  wire phy_data_wr_en;
  wire [0:0]phy_if_empty_r_reg;
  wire phy_if_empty_r_reg_0;
  wire phy_if_reset;
  wire \pi_dqs_found_lanes_r1_reg[11] ;
  wire \pi_dqs_found_lanes_r1_reg[11]_0 ;
  wire \pi_dqs_found_lanes_r1_reg[11]_1 ;
  wire \pi_dqs_found_lanes_r1_reg[11]_2 ;
  wire [5:0]\pi_dqs_found_lanes_r1_reg[11]_3 ;
  wire pi_phase_locked_all_r1_reg;
  wire pi_phase_locked_all_r1_reg_0;
  wire pi_phase_locked_all_r1_reg_1;
  wire \po_counter_read_val_reg[8] ;
  wire \po_counter_read_val_reg[8]_0 ;
  wire \po_counter_read_val_reg[8]_1 ;
  wire po_oserdes_rst;
  wire po_rd_enable;
  wire \po_stg2_wrcal_cnt_reg[2] ;
  wire \po_stg2_wrcal_cnt_reg[2]_0 ;
  wire \po_stg2_wrcal_cnt_reg[2]_1 ;
  wire \po_stg2_wrcal_cnt_reg[2]_10 ;
  wire \po_stg2_wrcal_cnt_reg[2]_11 ;
  wire \po_stg2_wrcal_cnt_reg[2]_12 ;
  wire \po_stg2_wrcal_cnt_reg[2]_13 ;
  wire \po_stg2_wrcal_cnt_reg[2]_14 ;
  wire \po_stg2_wrcal_cnt_reg[2]_15 ;
  wire \po_stg2_wrcal_cnt_reg[2]_16 ;
  wire \po_stg2_wrcal_cnt_reg[2]_17 ;
  wire \po_stg2_wrcal_cnt_reg[2]_18 ;
  wire \po_stg2_wrcal_cnt_reg[2]_19 ;
  wire \po_stg2_wrcal_cnt_reg[2]_2 ;
  wire \po_stg2_wrcal_cnt_reg[2]_20 ;
  wire \po_stg2_wrcal_cnt_reg[2]_21 ;
  wire \po_stg2_wrcal_cnt_reg[2]_22 ;
  wire \po_stg2_wrcal_cnt_reg[2]_23 ;
  wire \po_stg2_wrcal_cnt_reg[2]_24 ;
  wire \po_stg2_wrcal_cnt_reg[2]_25 ;
  wire \po_stg2_wrcal_cnt_reg[2]_26 ;
  wire \po_stg2_wrcal_cnt_reg[2]_27 ;
  wire \po_stg2_wrcal_cnt_reg[2]_28 ;
  wire \po_stg2_wrcal_cnt_reg[2]_29 ;
  wire \po_stg2_wrcal_cnt_reg[2]_3 ;
  wire \po_stg2_wrcal_cnt_reg[2]_30 ;
  wire \po_stg2_wrcal_cnt_reg[2]_31 ;
  wire \po_stg2_wrcal_cnt_reg[2]_32 ;
  wire \po_stg2_wrcal_cnt_reg[2]_33 ;
  wire \po_stg2_wrcal_cnt_reg[2]_34 ;
  wire \po_stg2_wrcal_cnt_reg[2]_35 ;
  wire \po_stg2_wrcal_cnt_reg[2]_36 ;
  wire \po_stg2_wrcal_cnt_reg[2]_37 ;
  wire \po_stg2_wrcal_cnt_reg[2]_38 ;
  wire \po_stg2_wrcal_cnt_reg[2]_39 ;
  wire \po_stg2_wrcal_cnt_reg[2]_4 ;
  wire \po_stg2_wrcal_cnt_reg[2]_40 ;
  wire \po_stg2_wrcal_cnt_reg[2]_41 ;
  wire \po_stg2_wrcal_cnt_reg[2]_42 ;
  wire \po_stg2_wrcal_cnt_reg[2]_43 ;
  wire \po_stg2_wrcal_cnt_reg[2]_44 ;
  wire \po_stg2_wrcal_cnt_reg[2]_45 ;
  wire \po_stg2_wrcal_cnt_reg[2]_46 ;
  wire \po_stg2_wrcal_cnt_reg[2]_47 ;
  wire \po_stg2_wrcal_cnt_reg[2]_48 ;
  wire \po_stg2_wrcal_cnt_reg[2]_49 ;
  wire \po_stg2_wrcal_cnt_reg[2]_5 ;
  wire \po_stg2_wrcal_cnt_reg[2]_50 ;
  wire \po_stg2_wrcal_cnt_reg[2]_51 ;
  wire \po_stg2_wrcal_cnt_reg[2]_52 ;
  wire \po_stg2_wrcal_cnt_reg[2]_53 ;
  wire \po_stg2_wrcal_cnt_reg[2]_54 ;
  wire \po_stg2_wrcal_cnt_reg[2]_55 ;
  wire \po_stg2_wrcal_cnt_reg[2]_56 ;
  wire \po_stg2_wrcal_cnt_reg[2]_57 ;
  wire \po_stg2_wrcal_cnt_reg[2]_58 ;
  wire \po_stg2_wrcal_cnt_reg[2]_59 ;
  wire \po_stg2_wrcal_cnt_reg[2]_6 ;
  wire \po_stg2_wrcal_cnt_reg[2]_60 ;
  wire \po_stg2_wrcal_cnt_reg[2]_61 ;
  wire \po_stg2_wrcal_cnt_reg[2]_7 ;
  wire \po_stg2_wrcal_cnt_reg[2]_8 ;
  wire \po_stg2_wrcal_cnt_reg[2]_9 ;
  wire [79:0]rd_data;
  wire [79:12]rd_data_r;
  wire \rd_mux_sel_r_reg[2] ;
  wire \rd_mux_sel_r_reg[2]_0 ;
  wire \rd_mux_sel_r_reg[2]_1 ;
  wire \rd_mux_sel_r_reg[2]_10 ;
  wire \rd_mux_sel_r_reg[2]_11 ;
  wire \rd_mux_sel_r_reg[2]_12 ;
  wire \rd_mux_sel_r_reg[2]_13 ;
  wire \rd_mux_sel_r_reg[2]_14 ;
  wire \rd_mux_sel_r_reg[2]_15 ;
  wire \rd_mux_sel_r_reg[2]_16 ;
  wire \rd_mux_sel_r_reg[2]_17 ;
  wire \rd_mux_sel_r_reg[2]_18 ;
  wire \rd_mux_sel_r_reg[2]_19 ;
  wire \rd_mux_sel_r_reg[2]_2 ;
  wire \rd_mux_sel_r_reg[2]_20 ;
  wire \rd_mux_sel_r_reg[2]_21 ;
  wire \rd_mux_sel_r_reg[2]_22 ;
  wire \rd_mux_sel_r_reg[2]_23 ;
  wire \rd_mux_sel_r_reg[2]_24 ;
  wire \rd_mux_sel_r_reg[2]_25 ;
  wire \rd_mux_sel_r_reg[2]_26 ;
  wire \rd_mux_sel_r_reg[2]_27 ;
  wire \rd_mux_sel_r_reg[2]_28 ;
  wire \rd_mux_sel_r_reg[2]_29 ;
  wire \rd_mux_sel_r_reg[2]_3 ;
  wire \rd_mux_sel_r_reg[2]_30 ;
  wire \rd_mux_sel_r_reg[2]_31 ;
  wire \rd_mux_sel_r_reg[2]_32 ;
  wire \rd_mux_sel_r_reg[2]_33 ;
  wire \rd_mux_sel_r_reg[2]_34 ;
  wire \rd_mux_sel_r_reg[2]_35 ;
  wire \rd_mux_sel_r_reg[2]_36 ;
  wire \rd_mux_sel_r_reg[2]_37 ;
  wire \rd_mux_sel_r_reg[2]_38 ;
  wire \rd_mux_sel_r_reg[2]_39 ;
  wire \rd_mux_sel_r_reg[2]_4 ;
  wire \rd_mux_sel_r_reg[2]_40 ;
  wire \rd_mux_sel_r_reg[2]_41 ;
  wire \rd_mux_sel_r_reg[2]_42 ;
  wire \rd_mux_sel_r_reg[2]_43 ;
  wire \rd_mux_sel_r_reg[2]_44 ;
  wire \rd_mux_sel_r_reg[2]_45 ;
  wire \rd_mux_sel_r_reg[2]_46 ;
  wire \rd_mux_sel_r_reg[2]_47 ;
  wire \rd_mux_sel_r_reg[2]_48 ;
  wire \rd_mux_sel_r_reg[2]_49 ;
  wire \rd_mux_sel_r_reg[2]_5 ;
  wire \rd_mux_sel_r_reg[2]_50 ;
  wire \rd_mux_sel_r_reg[2]_51 ;
  wire \rd_mux_sel_r_reg[2]_52 ;
  wire \rd_mux_sel_r_reg[2]_53 ;
  wire \rd_mux_sel_r_reg[2]_54 ;
  wire \rd_mux_sel_r_reg[2]_55 ;
  wire \rd_mux_sel_r_reg[2]_56 ;
  wire \rd_mux_sel_r_reg[2]_57 ;
  wire \rd_mux_sel_r_reg[2]_58 ;
  wire \rd_mux_sel_r_reg[2]_59 ;
  wire \rd_mux_sel_r_reg[2]_6 ;
  wire \rd_mux_sel_r_reg[2]_60 ;
  wire \rd_mux_sel_r_reg[2]_61 ;
  wire \rd_mux_sel_r_reg[2]_62 ;
  wire \rd_mux_sel_r_reg[2]_7 ;
  wire \rd_mux_sel_r_reg[2]_8 ;
  wire \rd_mux_sel_r_reg[2]_9 ;
  wire [63:0]\rd_ptr_reg[3] ;
  wire rst_r4;
  wire sync_pulse;
  wire ts_dqs_3;
  wire [7:4]\NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED ;
  wire [7:4]\NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED ;
  wire [7:4]NLW_out_fifo_Q5_UNCONNECTED;
  wire [7:4]NLW_out_fifo_Q6_UNCONNECTED;
  wire NLW_phaser_out_PHASEREFCLK_UNCONNECTED;

  mig_mig_7series_v4_2_ddr_byte_group_io__parameterized0 ddr_byte_group_io
       (.A_rst_primitives(A_rst_primitives),
        .CLKB0_13(CLKB0_13),
        .CTSBUS(oserdes_dqs_ts[0]),
        .D2(if_d2),
        .D3(if_d3),
        .D4(if_d4),
        .D5(if_d5),
        .D6(if_d6),
        .D7(if_d7),
        .D8(if_d8),
        .D9(if_d9),
        .DQSBUS(oserdes_dqs),
        .DTSBUS(oserdes_dq_ts),
        .LD0_13(LD0_13),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (A_rst_primitives_reg),
        .idelay_inc(idelay_inc),
        .idelay_ld_rst_6(idelay_ld_rst_6),
        .idelay_ld_rst_reg_0(\entry_cnt_reg[4] ),
        .\input_[9].iserdes_dq_.iserdesdq_0 (\input_[9].iserdes_dq_.iserdesdq ),
        .iserdes_clkdiv(iserdes_clkdiv),
        .mem_dq_in(mem_dq_in),
        .mem_dq_out(mem_dq_out),
        .mem_dq_ts(mem_dq_ts),
        .of_dqbus(of_dqbus[39:4]),
        .oserdes_clk(oserdes_clk),
        .oserdes_clk_delayed(oserdes_clk_delayed),
        .oserdes_clkdiv(oserdes_clkdiv),
        .out_dqs_3(out_dqs_3),
        .po_oserdes_rst(po_oserdes_rst),
        .rst_r4(rst_r4),
        .ts_dqs_3(ts_dqs_3));
  (* syn_maxfan = "3" *) 
  FDRE \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(if_empty_),
        .Q(if_empty_r_0),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[12]),
        .Q(rd_data_r[12]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[13]),
        .Q(rd_data_r[13]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[14]),
        .Q(rd_data_r[14]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[15]),
        .Q(rd_data_r[15]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[16]),
        .Q(rd_data_r[16]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[17]),
        .Q(rd_data_r[17]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[18]),
        .Q(rd_data_r[18]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[19]),
        .Q(rd_data_r[19]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[20]),
        .Q(rd_data_r[20]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[21]),
        .Q(rd_data_r[21]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[22]),
        .Q(rd_data_r[22]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[23]),
        .Q(rd_data_r[23]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[24]),
        .Q(rd_data_r[24]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[25]),
        .Q(rd_data_r[25]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[26]),
        .Q(rd_data_r[26]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[27]),
        .Q(rd_data_r[27]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[28]),
        .Q(rd_data_r[28]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[29]),
        .Q(rd_data_r[29]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[30]),
        .Q(rd_data_r[30]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[31]),
        .Q(rd_data_r[31]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[32]),
        .Q(rd_data_r[32]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[33]),
        .Q(rd_data_r[33]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[34]),
        .Q(rd_data_r[34]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[35]),
        .Q(rd_data_r[35]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[36]),
        .Q(rd_data_r[36]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[37]),
        .Q(rd_data_r[37]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[38]),
        .Q(rd_data_r[38]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[39]),
        .Q(rd_data_r[39]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[40]),
        .Q(rd_data_r[40]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[41]),
        .Q(rd_data_r[41]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[42]),
        .Q(rd_data_r[42]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[43]),
        .Q(rd_data_r[43]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[44]),
        .Q(rd_data_r[44]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[45]),
        .Q(rd_data_r[45]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[46]),
        .Q(rd_data_r[46]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[47]),
        .Q(rd_data_r[47]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[48]),
        .Q(rd_data_r[48]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[49]),
        .Q(rd_data_r[49]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[50]),
        .Q(rd_data_r[50]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[51]),
        .Q(rd_data_r[51]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[52]),
        .Q(rd_data_r[52]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[53]),
        .Q(rd_data_r[53]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[54]),
        .Q(rd_data_r[54]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[55]),
        .Q(rd_data_r[55]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[56]),
        .Q(rd_data_r[56]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[57]),
        .Q(rd_data_r[57]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[58]),
        .Q(rd_data_r[58]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[59]),
        .Q(rd_data_r[59]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[60]),
        .Q(rd_data_r[60]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[61]),
        .Q(rd_data_r[61]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[62]),
        .Q(rd_data_r[62]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[63]),
        .Q(rd_data_r[63]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[64]),
        .Q(rd_data_r[64]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[65]),
        .Q(rd_data_r[65]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[66]),
        .Q(rd_data_r[66]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[67]),
        .Q(rd_data_r[67]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[68]),
        .Q(rd_data_r[68]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[69]),
        .Q(rd_data_r[69]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[70]),
        .Q(rd_data_r[70]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[71]),
        .Q(rd_data_r[71]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[72]),
        .Q(rd_data_r[72]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[73]),
        .Q(rd_data_r[73]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[74]),
        .Q(rd_data_r[74]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[75]),
        .Q(rd_data_r[75]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[76]),
        .Q(rd_data_r[76]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[77]),
        .Q(rd_data_r[77]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[78]),
        .Q(rd_data_r[78]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[79]),
        .Q(rd_data_r[79]),
        .R(1'b0));
  mig_mig_7series_v4_2_ddr_if_post_fifo \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo 
       (.Q(rd_data_r),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ),
        .\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] (\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ),
        .\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] (\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ),
        .\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] (\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ),
        .\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] (\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ),
        .\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] (\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ),
        .\gen_mux_rd[0].mux_rd_rise0_r1_reg[0]_0 (\gen_mux_rd[0].mux_rd_rise0_r1_reg[0]_0 ),
        .\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] (\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ),
        .\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] (\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ),
        .\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] (\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ),
        .\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] (\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] (\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] (\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] (\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] (\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] (\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] (\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] (\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ),
        .\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] (\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ),
        .\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] (\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ),
        .\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] (\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ),
        .\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] (\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ),
        .\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] (\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ),
        .\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] (\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ),
        .\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] (\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ),
        .\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] (\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ),
        .\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] (\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] (\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] (\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] (\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] (\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] (\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] (\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] (\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ),
        .\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] (\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ),
        .\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] (\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ),
        .\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] (\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ),
        .\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] (\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ),
        .\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] (\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ),
        .\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] (\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ),
        .\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] (\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ),
        .\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] (\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ),
        .\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] (\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] (\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] (\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] (\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] (\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] (\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] (\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] (\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ),
        .\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] (\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ),
        .\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] (\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ),
        .\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] (\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ),
        .\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] (\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ),
        .\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] (\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ),
        .\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] (\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ),
        .\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] (\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ),
        .\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] (\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ),
        .\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] (\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] (\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] (\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] (\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] (\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] (\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] (\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] (\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_1 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_2 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_2 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_1 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_2 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_2 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_1 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_2 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_2 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_1 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_2 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_2 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_2 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_2 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_1 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_3 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_3 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_1 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_2 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_2 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_1 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_2 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_2 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_2 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_2 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_2 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_2 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_2 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_2 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_2 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_2 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_2 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_2 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_2 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_2 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_2 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_2 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_1 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_2 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_2 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_1 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_2 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_2 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_1 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_2 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_2 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_1 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_2 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_2 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_2 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_2 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_1 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_2 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_2 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_1 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_2 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_2 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_1 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_2 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_2 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_2 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_2 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_2 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_2 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_2 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_2 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_2 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_2 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_2 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_2 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_2 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_2 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_2 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_2 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_2 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_2 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_1 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_2 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_2 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_1 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_2 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_2 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_1 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_2 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_2 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_1 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_2 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_2 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_1 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_2 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_2 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_1 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_2 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_2 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_1 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_2 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_2 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_1 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_2 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_2 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_2 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_2 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_2 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_2 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_2 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_2 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_2 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_2 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_1 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_2 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_2 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_2 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_2 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_2 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_2 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_2 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_2 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_1 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_2 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_2 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_1 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_2 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_2 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_1 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_2 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_2 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_1 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_2 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_2 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_1 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_2 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_2 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_1 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_2 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_2 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_1 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_2 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_2 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_1 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_2 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_2 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_2 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_2 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_2 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_2 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_2 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_2 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_2 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_2 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_1 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_2 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_2 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_2 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_2 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_2 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_2 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_2 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_2 ),
        .if_empty_r(if_empty_r),
        .if_empty_r_0(if_empty_r_0),
        .if_empty_v(if_empty_v),
        .ififo_rst(ififo_rst),
        .\my_full_reg[1]_0 (\my_full_reg[1] ),
        .\my_full_reg[1]_1 (\my_full_reg[1]_0 ),
        .\my_full_reg[1]_2 (\my_full_reg[1]_1 ),
        .\my_full_reg[1]_3 (\my_full_reg[1]_2 ),
        .\my_full_reg[1]_4 (\my_full_reg[1]_3 ),
        .\my_full_reg[1]_5 (\my_full_reg[1]_4 ),
        .p_0_out(p_0_out),
        .phy_if_empty_r_reg(phy_if_empty_r_reg),
        .phy_if_empty_r_reg_0(phy_if_empty_r_reg_0),
        .\po_stg2_wrcal_cnt_reg[2] (\po_stg2_wrcal_cnt_reg[2] ),
        .\po_stg2_wrcal_cnt_reg[2]_0 (\po_stg2_wrcal_cnt_reg[2]_0 ),
        .\po_stg2_wrcal_cnt_reg[2]_1 (\po_stg2_wrcal_cnt_reg[2]_1 ),
        .\po_stg2_wrcal_cnt_reg[2]_10 (\po_stg2_wrcal_cnt_reg[2]_10 ),
        .\po_stg2_wrcal_cnt_reg[2]_11 (\po_stg2_wrcal_cnt_reg[2]_11 ),
        .\po_stg2_wrcal_cnt_reg[2]_12 (\po_stg2_wrcal_cnt_reg[2]_12 ),
        .\po_stg2_wrcal_cnt_reg[2]_13 (\po_stg2_wrcal_cnt_reg[2]_13 ),
        .\po_stg2_wrcal_cnt_reg[2]_14 (\po_stg2_wrcal_cnt_reg[2]_14 ),
        .\po_stg2_wrcal_cnt_reg[2]_15 (\po_stg2_wrcal_cnt_reg[2]_15 ),
        .\po_stg2_wrcal_cnt_reg[2]_16 (\po_stg2_wrcal_cnt_reg[2]_16 ),
        .\po_stg2_wrcal_cnt_reg[2]_17 (\po_stg2_wrcal_cnt_reg[2]_17 ),
        .\po_stg2_wrcal_cnt_reg[2]_18 (\po_stg2_wrcal_cnt_reg[2]_18 ),
        .\po_stg2_wrcal_cnt_reg[2]_19 (\po_stg2_wrcal_cnt_reg[2]_19 ),
        .\po_stg2_wrcal_cnt_reg[2]_2 (\po_stg2_wrcal_cnt_reg[2]_2 ),
        .\po_stg2_wrcal_cnt_reg[2]_20 (\po_stg2_wrcal_cnt_reg[2]_20 ),
        .\po_stg2_wrcal_cnt_reg[2]_21 (\po_stg2_wrcal_cnt_reg[2]_21 ),
        .\po_stg2_wrcal_cnt_reg[2]_22 (\po_stg2_wrcal_cnt_reg[2]_22 ),
        .\po_stg2_wrcal_cnt_reg[2]_23 (\po_stg2_wrcal_cnt_reg[2]_23 ),
        .\po_stg2_wrcal_cnt_reg[2]_24 (\po_stg2_wrcal_cnt_reg[2]_24 ),
        .\po_stg2_wrcal_cnt_reg[2]_25 (\po_stg2_wrcal_cnt_reg[2]_25 ),
        .\po_stg2_wrcal_cnt_reg[2]_26 (\po_stg2_wrcal_cnt_reg[2]_26 ),
        .\po_stg2_wrcal_cnt_reg[2]_27 (\po_stg2_wrcal_cnt_reg[2]_27 ),
        .\po_stg2_wrcal_cnt_reg[2]_28 (\po_stg2_wrcal_cnt_reg[2]_28 ),
        .\po_stg2_wrcal_cnt_reg[2]_29 (\po_stg2_wrcal_cnt_reg[2]_29 ),
        .\po_stg2_wrcal_cnt_reg[2]_3 (\po_stg2_wrcal_cnt_reg[2]_3 ),
        .\po_stg2_wrcal_cnt_reg[2]_30 (\po_stg2_wrcal_cnt_reg[2]_30 ),
        .\po_stg2_wrcal_cnt_reg[2]_31 (\po_stg2_wrcal_cnt_reg[2]_31 ),
        .\po_stg2_wrcal_cnt_reg[2]_32 (\po_stg2_wrcal_cnt_reg[2]_32 ),
        .\po_stg2_wrcal_cnt_reg[2]_33 (\po_stg2_wrcal_cnt_reg[2]_33 ),
        .\po_stg2_wrcal_cnt_reg[2]_34 (\po_stg2_wrcal_cnt_reg[2]_34 ),
        .\po_stg2_wrcal_cnt_reg[2]_35 (\po_stg2_wrcal_cnt_reg[2]_35 ),
        .\po_stg2_wrcal_cnt_reg[2]_36 (\po_stg2_wrcal_cnt_reg[2]_36 ),
        .\po_stg2_wrcal_cnt_reg[2]_37 (\po_stg2_wrcal_cnt_reg[2]_37 ),
        .\po_stg2_wrcal_cnt_reg[2]_38 (\po_stg2_wrcal_cnt_reg[2]_38 ),
        .\po_stg2_wrcal_cnt_reg[2]_39 (\po_stg2_wrcal_cnt_reg[2]_39 ),
        .\po_stg2_wrcal_cnt_reg[2]_4 (\po_stg2_wrcal_cnt_reg[2]_4 ),
        .\po_stg2_wrcal_cnt_reg[2]_40 (\po_stg2_wrcal_cnt_reg[2]_40 ),
        .\po_stg2_wrcal_cnt_reg[2]_41 (\po_stg2_wrcal_cnt_reg[2]_41 ),
        .\po_stg2_wrcal_cnt_reg[2]_42 (\po_stg2_wrcal_cnt_reg[2]_42 ),
        .\po_stg2_wrcal_cnt_reg[2]_43 (\po_stg2_wrcal_cnt_reg[2]_43 ),
        .\po_stg2_wrcal_cnt_reg[2]_44 (\po_stg2_wrcal_cnt_reg[2]_44 ),
        .\po_stg2_wrcal_cnt_reg[2]_45 (\po_stg2_wrcal_cnt_reg[2]_45 ),
        .\po_stg2_wrcal_cnt_reg[2]_46 (\po_stg2_wrcal_cnt_reg[2]_46 ),
        .\po_stg2_wrcal_cnt_reg[2]_47 (\po_stg2_wrcal_cnt_reg[2]_47 ),
        .\po_stg2_wrcal_cnt_reg[2]_48 (\po_stg2_wrcal_cnt_reg[2]_48 ),
        .\po_stg2_wrcal_cnt_reg[2]_49 (\po_stg2_wrcal_cnt_reg[2]_49 ),
        .\po_stg2_wrcal_cnt_reg[2]_5 (\po_stg2_wrcal_cnt_reg[2]_5 ),
        .\po_stg2_wrcal_cnt_reg[2]_50 (\po_stg2_wrcal_cnt_reg[2]_50 ),
        .\po_stg2_wrcal_cnt_reg[2]_51 (\po_stg2_wrcal_cnt_reg[2]_51 ),
        .\po_stg2_wrcal_cnt_reg[2]_52 (\po_stg2_wrcal_cnt_reg[2]_52 ),
        .\po_stg2_wrcal_cnt_reg[2]_53 (\po_stg2_wrcal_cnt_reg[2]_53 ),
        .\po_stg2_wrcal_cnt_reg[2]_54 (\po_stg2_wrcal_cnt_reg[2]_54 ),
        .\po_stg2_wrcal_cnt_reg[2]_55 (\po_stg2_wrcal_cnt_reg[2]_55 ),
        .\po_stg2_wrcal_cnt_reg[2]_56 (\po_stg2_wrcal_cnt_reg[2]_56 ),
        .\po_stg2_wrcal_cnt_reg[2]_57 (\po_stg2_wrcal_cnt_reg[2]_57 ),
        .\po_stg2_wrcal_cnt_reg[2]_58 (\po_stg2_wrcal_cnt_reg[2]_58 ),
        .\po_stg2_wrcal_cnt_reg[2]_59 (\po_stg2_wrcal_cnt_reg[2]_59 ),
        .\po_stg2_wrcal_cnt_reg[2]_6 (\po_stg2_wrcal_cnt_reg[2]_6 ),
        .\po_stg2_wrcal_cnt_reg[2]_60 (\po_stg2_wrcal_cnt_reg[2]_60 ),
        .\po_stg2_wrcal_cnt_reg[2]_61 (\po_stg2_wrcal_cnt_reg[2]_61 ),
        .\po_stg2_wrcal_cnt_reg[2]_7 (\po_stg2_wrcal_cnt_reg[2]_7 ),
        .\po_stg2_wrcal_cnt_reg[2]_8 (\po_stg2_wrcal_cnt_reg[2]_8 ),
        .\po_stg2_wrcal_cnt_reg[2]_9 (\po_stg2_wrcal_cnt_reg[2]_9 ),
        .\rd_mux_sel_r_reg[2] (\rd_mux_sel_r_reg[2] ),
        .\rd_mux_sel_r_reg[2]_0 (\rd_mux_sel_r_reg[2]_0 ),
        .\rd_mux_sel_r_reg[2]_1 (\rd_mux_sel_r_reg[2]_1 ),
        .\rd_mux_sel_r_reg[2]_10 (\rd_mux_sel_r_reg[2]_10 ),
        .\rd_mux_sel_r_reg[2]_11 (\rd_mux_sel_r_reg[2]_11 ),
        .\rd_mux_sel_r_reg[2]_12 (\rd_mux_sel_r_reg[2]_12 ),
        .\rd_mux_sel_r_reg[2]_13 (\rd_mux_sel_r_reg[2]_13 ),
        .\rd_mux_sel_r_reg[2]_14 (\rd_mux_sel_r_reg[2]_14 ),
        .\rd_mux_sel_r_reg[2]_15 (\rd_mux_sel_r_reg[2]_15 ),
        .\rd_mux_sel_r_reg[2]_16 (\rd_mux_sel_r_reg[2]_16 ),
        .\rd_mux_sel_r_reg[2]_17 (\rd_mux_sel_r_reg[2]_17 ),
        .\rd_mux_sel_r_reg[2]_18 (\rd_mux_sel_r_reg[2]_18 ),
        .\rd_mux_sel_r_reg[2]_19 (\rd_mux_sel_r_reg[2]_19 ),
        .\rd_mux_sel_r_reg[2]_2 (\rd_mux_sel_r_reg[2]_2 ),
        .\rd_mux_sel_r_reg[2]_20 (\rd_mux_sel_r_reg[2]_20 ),
        .\rd_mux_sel_r_reg[2]_21 (\rd_mux_sel_r_reg[2]_21 ),
        .\rd_mux_sel_r_reg[2]_22 (\rd_mux_sel_r_reg[2]_22 ),
        .\rd_mux_sel_r_reg[2]_23 (\rd_mux_sel_r_reg[2]_23 ),
        .\rd_mux_sel_r_reg[2]_24 (\rd_mux_sel_r_reg[2]_24 ),
        .\rd_mux_sel_r_reg[2]_25 (\rd_mux_sel_r_reg[2]_25 ),
        .\rd_mux_sel_r_reg[2]_26 (\rd_mux_sel_r_reg[2]_26 ),
        .\rd_mux_sel_r_reg[2]_27 (\rd_mux_sel_r_reg[2]_27 ),
        .\rd_mux_sel_r_reg[2]_28 (\rd_mux_sel_r_reg[2]_28 ),
        .\rd_mux_sel_r_reg[2]_29 (\rd_mux_sel_r_reg[2]_29 ),
        .\rd_mux_sel_r_reg[2]_3 (\rd_mux_sel_r_reg[2]_3 ),
        .\rd_mux_sel_r_reg[2]_30 (\rd_mux_sel_r_reg[2]_30 ),
        .\rd_mux_sel_r_reg[2]_31 (\rd_mux_sel_r_reg[2]_31 ),
        .\rd_mux_sel_r_reg[2]_32 (\rd_mux_sel_r_reg[2]_32 ),
        .\rd_mux_sel_r_reg[2]_33 (\rd_mux_sel_r_reg[2]_33 ),
        .\rd_mux_sel_r_reg[2]_34 (\rd_mux_sel_r_reg[2]_34 ),
        .\rd_mux_sel_r_reg[2]_35 (\rd_mux_sel_r_reg[2]_35 ),
        .\rd_mux_sel_r_reg[2]_36 (\rd_mux_sel_r_reg[2]_36 ),
        .\rd_mux_sel_r_reg[2]_37 (\rd_mux_sel_r_reg[2]_37 ),
        .\rd_mux_sel_r_reg[2]_38 (\rd_mux_sel_r_reg[2]_38 ),
        .\rd_mux_sel_r_reg[2]_39 (\rd_mux_sel_r_reg[2]_39 ),
        .\rd_mux_sel_r_reg[2]_4 (\rd_mux_sel_r_reg[2]_4 ),
        .\rd_mux_sel_r_reg[2]_40 (\rd_mux_sel_r_reg[2]_40 ),
        .\rd_mux_sel_r_reg[2]_41 (\rd_mux_sel_r_reg[2]_41 ),
        .\rd_mux_sel_r_reg[2]_42 (\rd_mux_sel_r_reg[2]_42 ),
        .\rd_mux_sel_r_reg[2]_43 (\rd_mux_sel_r_reg[2]_43 ),
        .\rd_mux_sel_r_reg[2]_44 (\rd_mux_sel_r_reg[2]_44 ),
        .\rd_mux_sel_r_reg[2]_45 (\rd_mux_sel_r_reg[2]_45 ),
        .\rd_mux_sel_r_reg[2]_46 (\rd_mux_sel_r_reg[2]_46 ),
        .\rd_mux_sel_r_reg[2]_47 (\rd_mux_sel_r_reg[2]_47 ),
        .\rd_mux_sel_r_reg[2]_48 (\rd_mux_sel_r_reg[2]_48 ),
        .\rd_mux_sel_r_reg[2]_49 (\rd_mux_sel_r_reg[2]_49 ),
        .\rd_mux_sel_r_reg[2]_5 (\rd_mux_sel_r_reg[2]_5 ),
        .\rd_mux_sel_r_reg[2]_50 (\rd_mux_sel_r_reg[2]_50 ),
        .\rd_mux_sel_r_reg[2]_51 (\rd_mux_sel_r_reg[2]_51 ),
        .\rd_mux_sel_r_reg[2]_52 (\rd_mux_sel_r_reg[2]_52 ),
        .\rd_mux_sel_r_reg[2]_53 (\rd_mux_sel_r_reg[2]_53 ),
        .\rd_mux_sel_r_reg[2]_54 (\rd_mux_sel_r_reg[2]_54 ),
        .\rd_mux_sel_r_reg[2]_55 (\rd_mux_sel_r_reg[2]_55 ),
        .\rd_mux_sel_r_reg[2]_56 (\rd_mux_sel_r_reg[2]_56 ),
        .\rd_mux_sel_r_reg[2]_57 (\rd_mux_sel_r_reg[2]_57 ),
        .\rd_mux_sel_r_reg[2]_58 (\rd_mux_sel_r_reg[2]_58 ),
        .\rd_mux_sel_r_reg[2]_59 (\rd_mux_sel_r_reg[2]_59 ),
        .\rd_mux_sel_r_reg[2]_6 (\rd_mux_sel_r_reg[2]_6 ),
        .\rd_mux_sel_r_reg[2]_60 (\rd_mux_sel_r_reg[2]_60 ),
        .\rd_mux_sel_r_reg[2]_61 (\rd_mux_sel_r_reg[2]_61 ),
        .\rd_mux_sel_r_reg[2]_62 (\rd_mux_sel_r_reg[2]_62 ),
        .\rd_mux_sel_r_reg[2]_7 (\rd_mux_sel_r_reg[2]_7 ),
        .\rd_mux_sel_r_reg[2]_8 (\rd_mux_sel_r_reg[2]_8 ),
        .\rd_mux_sel_r_reg[2]_9 (\rd_mux_sel_r_reg[2]_9 ),
        .\rd_ptr_timing_reg[1]_0 (\entry_cnt_reg[4] ));
  FDSE #(
    .INIT(1'b1)) 
    ififo_rst_reg
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(ififo_rst_reg_0),
        .Q(ififo_rst),
        .S(phy_if_reset));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IN_FIFO #(
    .ALMOST_EMPTY_VALUE(1),
    .ALMOST_FULL_VALUE(1),
    .ARRAY_MODE("ARRAY_MODE_4_X_8"),
    .SYNCHRONOUS_MODE("FALSE")) 
    \in_fifo_gen.in_fifo 
       (.ALMOSTEMPTY(\in_fifo_gen.in_fifo_n_0 ),
        .ALMOSTFULL(\in_fifo_gen.in_fifo_n_1 ),
        .D0({1'b0,1'b0,1'b0,1'b0}),
        .D1({1'b0,1'b0,1'b0,1'b0}),
        .D2(if_d2),
        .D3(if_d3),
        .D4(if_d4),
        .D5({\NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED [7:4],if_d5}),
        .D6({\NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED [7:4],if_d6}),
        .D7(if_d7),
        .D8(if_d8),
        .D9(if_d9),
        .EMPTY(if_empty_),
        .FULL(\in_fifo_gen.in_fifo_n_3 ),
        .Q0(rd_data[7:0]),
        .Q1(rd_data[15:8]),
        .Q2(rd_data[23:16]),
        .Q3(rd_data[31:24]),
        .Q4(rd_data[39:32]),
        .Q5(rd_data[47:40]),
        .Q6(rd_data[55:48]),
        .Q7(rd_data[63:56]),
        .Q8(rd_data[71:64]),
        .Q9(rd_data[79:72]),
        .RDCLK(\entry_cnt_reg[4] ),
        .RDEN(1'b1),
        .RESET(ififo_rst),
        .WRCLK(iserdes_clkdiv),
        .WREN(ififo_wr_enable));
  mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1 \of_pre_fifo_gen.u_ddr_of_pre_fifo 
       (.D0({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 }),
        .D1(of_d1),
        .Q(Q),
        .\entry_cnt_reg[4]_0 (\entry_cnt_reg[4] ),
        .\my_empty_reg[1]_0 (\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ),
        .\my_empty_reg[1]_1 (\my_empty_reg[1] ),
        .\my_empty_reg[7]_0 (out_fifo_n_3),
        .ofifo_rst(ofifo_rst),
        .out_fifo(out_fifo_0),
        .out_fifo_0(out_fifo_1),
        .out_fifo_1(out_fifo_2),
        .out_fifo_i_75__3(out_fifo_i_75__3),
        .phy_data_wr_en(phy_data_wr_en),
        .\rd_ptr_reg[3]_0 (\rd_ptr_reg[3] ));
  FDSE #(
    .INIT(1'b1)) 
    ofifo_rst_reg
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(ififo_rst_reg_0),
        .Q(ofifo_rst),
        .S(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OUT_FIFO #(
    .ALMOST_EMPTY_VALUE(1),
    .ALMOST_FULL_VALUE(1),
    .ARRAY_MODE("ARRAY_MODE_8_X_4"),
    .OUTPUT_DISABLE("FALSE"),
    .SYNCHRONOUS_MODE("FALSE")) 
    out_fifo
       (.ALMOSTEMPTY(out_fifo_n_0),
        .ALMOSTFULL(out_fifo_n_1),
        .D0({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 }),
        .D1(of_d1),
        .D2(\my_empty_reg[7] ),
        .D3(\my_empty_reg[7]_0 ),
        .D4(\my_empty_reg[7]_1 ),
        .D5(\my_empty_reg[7]_2 ),
        .D6(\my_empty_reg[7]_3 ),
        .D7(\my_empty_reg[7]_4 ),
        .D8(\my_empty_reg[7]_5 ),
        .D9(\my_empty_reg[7]_6 ),
        .EMPTY(out_fifo_n_2),
        .FULL(out_fifo_n_3),
        .Q0(of_dqbus[3:0]),
        .Q1(of_dqbus[7:4]),
        .Q2(of_dqbus[11:8]),
        .Q3(of_dqbus[15:12]),
        .Q4(of_dqbus[19:16]),
        .Q5({NLW_out_fifo_Q5_UNCONNECTED[7:4],of_dqbus[23:20]}),
        .Q6({NLW_out_fifo_Q6_UNCONNECTED[7:4],of_dqbus[27:24]}),
        .Q7(of_dqbus[31:28]),
        .Q8(of_dqbus[35:32]),
        .Q9(of_dqbus[39:36]),
        .RDCLK(oserdes_clkdiv),
        .RDEN(po_rd_enable),
        .RESET(ofifo_rst),
        .WRCLK(\entry_cnt_reg[4] ),
        .WREN(\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  PHASER_IN_PHY #(
    .BURST_MODE("TRUE"),
    .CLKOUT_DIV(2),
    .DQS_AUTO_RECAL(1'b1),
    .DQS_BIAS_MODE("FALSE"),
    .DQS_FIND_PATTERN(3'b000),
    .FINE_DELAY(33),
    .FREQ_REF_DIV("DIV2"),
    .IS_RST_INVERTED(1'b0),
    .MEMREFCLK_PERIOD(2.500000),
    .OUTPUT_CLK_SRC("DELAYED_REF"),
    .PHASEREFCLK_PERIOD(2.500000),
    .REFCLK_PERIOD(1.250000),
    .SEL_CLK_OFFSET(6),
    .SYNC_IN_DIV_RST("TRUE"),
    .WR_CYCLES("FALSE")) 
    \phaser_in_gen.phaser_in 
       (.BURSTPENDINGPHY(phaser_ctl_bus[1]),
        .COUNTERLOADEN(\pi_dqs_found_lanes_r1_reg[11] ),
        .COUNTERLOADVAL(\pi_dqs_found_lanes_r1_reg[11]_3 ),
        .COUNTERREADEN(\pi_dqs_found_lanes_r1_reg[11]_0 ),
        .COUNTERREADVAL(A_rst_primitives_reg_0),
        .DQSFOUND(in0),
        .DQSOUTOFRANGE(\phaser_in_gen.phaser_in_n_1 ),
        .ENCALIBPHY(PCENABLECALIB),
        .FINEENABLE(\pi_dqs_found_lanes_r1_reg[11]_1 ),
        .FINEINC(\pi_dqs_found_lanes_r1_reg[11]_2 ),
        .FINEOVERFLOW(\phaser_in_gen.phaser_in_n_2 ),
        .FREQREFCLK(freq_refclk),
        .ICLK(A_rst_primitives_reg),
        .ICLKDIV(iserdes_clkdiv),
        .ISERDESRST(\phaser_in_gen.phaser_in_n_5 ),
        .MEMREFCLK(mem_refclk),
        .PHASELOCKED(\phaser_in_gen.phaser_in_n_6 ),
        .PHASEREFCLK(mem_dqs_in),
        .RANKSELPHY(phaser_ctl_bus[3:2]),
        .RCLK(\phaser_in_gen.phaser_in_n_7 ),
        .RST(A_rst_primitives),
        .RSTDQSFIND(ififo_rst_reg_0),
        .SYNCIN(sync_pulse),
        .SYSCLK(\entry_cnt_reg[4] ),
        .WRENABLE(ififo_wr_enable));
  (* BOX_TYPE = "PRIMITIVE" *) 
  PHASER_OUT_PHY #(
    .CLKOUT_DIV(2),
    .COARSE_BYPASS("FALSE"),
    .COARSE_DELAY(0),
    .DATA_CTL_N("TRUE"),
    .DATA_RD_CYCLES("FALSE"),
    .FINE_DELAY(60),
    .IS_RST_INVERTED(1'b0),
    .MEMREFCLK_PERIOD(2.500000),
    .OCLKDELAY_INV("FALSE"),
    .OCLK_DELAY(0),
    .OUTPUT_CLK_SRC("DELAYED_REF"),
    .PHASEREFCLK_PERIOD(1.000000),
    .PO(3'b111),
    .REFCLK_PERIOD(1.250000),
    .SYNC_IN_DIV_RST("TRUE")) 
    phaser_out
       (.BURSTPENDINGPHY(phaser_ctl_bus[0]),
        .COARSEENABLE(\po_counter_read_val_reg[8] ),
        .COARSEINC(\po_counter_read_val_reg[8] ),
        .COARSEOVERFLOW(phaser_out_n_0),
        .COUNTERLOADEN(1'b0),
        .COUNTERLOADVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .COUNTERREADEN(\pi_dqs_found_lanes_r1_reg[11]_0 ),
        .COUNTERREADVAL(A_rst_primitives_reg_1),
        .CTSBUS(oserdes_dqs_ts),
        .DQSBUS(oserdes_dqs),
        .DTSBUS(oserdes_dq_ts),
        .ENCALIBPHY(PCENABLECALIB),
        .FINEENABLE(\po_counter_read_val_reg[8]_0 ),
        .FINEINC(\po_counter_read_val_reg[8]_1 ),
        .FINEOVERFLOW(phaser_out_n_1),
        .FREQREFCLK(freq_refclk),
        .MEMREFCLK(mem_refclk),
        .OCLK(oserdes_clk),
        .OCLKDELAYED(oserdes_clk_delayed),
        .OCLKDIV(oserdes_clkdiv),
        .OSERDESRST(po_oserdes_rst),
        .PHASEREFCLK(NLW_phaser_out_PHASEREFCLK_UNCONNECTED),
        .RDENABLE(po_rd_enable),
        .RST(A_rst_primitives),
        .SELFINEOCLKDELAY(1'b0),
        .SYNCIN(sync_pulse),
        .SYSCLK(\entry_cnt_reg[4] ));
  LUT4 #(
    .INIT(16'h8000)) 
    pi_phase_locked_all_inferred_i_2
       (.I0(\phaser_in_gen.phaser_in_n_6 ),
        .I1(pi_phase_locked_all_r1_reg),
        .I2(pi_phase_locked_all_r1_reg_0),
        .I3(pi_phase_locked_all_r1_reg_1),
        .O(A_rst_primitives_reg_2));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_byte_lane" *) 
module mig_mig_7series_v4_2_ddr_byte_lane__parameterized2_28
   (out_dqs_7,
    ts_dqs_7,
    A_rst_primitives_reg,
    mem_dq_out,
    mem_dq_ts,
    in0,
    A_rst_primitives_reg_0,
    A_rst_primitives_reg_1,
    A_rst_primitives_reg_2,
    if_empty_r_0,
    \my_empty_reg[4] ,
    idelay_ld_rst_2,
    rst_r4,
    \my_empty_reg[1] ,
    \rd_mux_sel_r_reg[1] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ,
    \rd_mux_sel_r_reg[1]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ,
    \rd_mux_sel_r_reg[1]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ,
    \rd_mux_sel_r_reg[1]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ,
    \rd_mux_sel_r_reg[1]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ,
    \rd_mux_sel_r_reg[1]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ,
    \rd_mux_sel_r_reg[1]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ,
    \rd_mux_sel_r_reg[1]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ,
    \rd_mux_sel_r_reg[1]_7 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ,
    \rd_mux_sel_r_reg[1]_8 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ,
    \rd_mux_sel_r_reg[1]_9 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ,
    \rd_mux_sel_r_reg[1]_10 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ,
    \rd_mux_sel_r_reg[1]_11 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ,
    \rd_mux_sel_r_reg[1]_12 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ,
    \rd_mux_sel_r_reg[1]_13 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ,
    \rd_mux_sel_r_reg[1]_14 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 ,
    \rd_mux_sel_r_reg[1]_15 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ,
    \rd_mux_sel_r_reg[1]_16 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ,
    \rd_mux_sel_r_reg[1]_17 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ,
    \rd_mux_sel_r_reg[1]_18 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ,
    \rd_mux_sel_r_reg[1]_19 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ,
    \rd_mux_sel_r_reg[1]_20 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ,
    \rd_mux_sel_r_reg[1]_21 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ,
    \rd_mux_sel_r_reg[1]_22 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 ,
    \rd_mux_sel_r_reg[1]_23 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ,
    \rd_mux_sel_r_reg[1]_24 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ,
    \rd_mux_sel_r_reg[1]_25 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ,
    \rd_mux_sel_r_reg[1]_26 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ,
    \rd_mux_sel_r_reg[1]_27 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ,
    \rd_mux_sel_r_reg[1]_28 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ,
    \rd_mux_sel_r_reg[1]_29 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ,
    \rd_mux_sel_r_reg[1]_30 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 ,
    \rd_mux_sel_r_reg[1]_31 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ,
    \rd_mux_sel_r_reg[1]_32 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ,
    \rd_mux_sel_r_reg[1]_33 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ,
    \rd_mux_sel_r_reg[1]_34 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ,
    \rd_mux_sel_r_reg[1]_35 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ,
    \rd_mux_sel_r_reg[1]_36 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ,
    \rd_mux_sel_r_reg[1]_37 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ,
    \rd_mux_sel_r_reg[1]_38 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 ,
    \rd_mux_sel_r_reg[1]_39 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ,
    \rd_mux_sel_r_reg[1]_40 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ,
    \rd_mux_sel_r_reg[1]_41 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ,
    \rd_mux_sel_r_reg[1]_42 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ,
    \rd_mux_sel_r_reg[1]_43 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ,
    \rd_mux_sel_r_reg[1]_44 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ,
    \rd_mux_sel_r_reg[1]_45 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ,
    \rd_mux_sel_r_reg[1]_46 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 ,
    \rd_mux_sel_r_reg[1]_47 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ,
    \rd_mux_sel_r_reg[1]_48 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ,
    \rd_mux_sel_r_reg[1]_49 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ,
    \rd_mux_sel_r_reg[1]_50 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ,
    \rd_mux_sel_r_reg[1]_51 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ,
    \rd_mux_sel_r_reg[1]_52 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ,
    \rd_mux_sel_r_reg[1]_53 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ,
    \rd_mux_sel_r_reg[1]_54 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 ,
    \rd_mux_sel_r_reg[1]_55 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ,
    \rd_mux_sel_r_reg[1]_56 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ,
    \rd_mux_sel_r_reg[1]_57 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ,
    \rd_mux_sel_r_reg[1]_58 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ,
    \rd_mux_sel_r_reg[1]_59 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ,
    \rd_mux_sel_r_reg[1]_60 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ,
    \rd_mux_sel_r_reg[1]_61 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ,
    \rd_mux_sel_r_reg[1]_62 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ,
    \po_stg2_wrcal_cnt_reg[1] ,
    \po_stg2_wrcal_cnt_reg[1]_0 ,
    \po_stg2_wrcal_cnt_reg[1]_1 ,
    \po_stg2_wrcal_cnt_reg[1]_2 ,
    \po_stg2_wrcal_cnt_reg[1]_3 ,
    \po_stg2_wrcal_cnt_reg[1]_4 ,
    \po_stg2_wrcal_cnt_reg[1]_5 ,
    \po_stg2_wrcal_cnt_reg[1]_6 ,
    \po_stg2_wrcal_cnt_reg[1]_7 ,
    \po_stg2_wrcal_cnt_reg[1]_8 ,
    \po_stg2_wrcal_cnt_reg[1]_9 ,
    \po_stg2_wrcal_cnt_reg[1]_10 ,
    \po_stg2_wrcal_cnt_reg[1]_11 ,
    \po_stg2_wrcal_cnt_reg[1]_12 ,
    \po_stg2_wrcal_cnt_reg[1]_13 ,
    \po_stg2_wrcal_cnt_reg[1]_14 ,
    \po_stg2_wrcal_cnt_reg[1]_15 ,
    \po_stg2_wrcal_cnt_reg[1]_16 ,
    \po_stg2_wrcal_cnt_reg[1]_17 ,
    \po_stg2_wrcal_cnt_reg[1]_18 ,
    \po_stg2_wrcal_cnt_reg[1]_19 ,
    \po_stg2_wrcal_cnt_reg[1]_20 ,
    \po_stg2_wrcal_cnt_reg[1]_21 ,
    \po_stg2_wrcal_cnt_reg[1]_22 ,
    \po_stg2_wrcal_cnt_reg[1]_23 ,
    \po_stg2_wrcal_cnt_reg[1]_24 ,
    \po_stg2_wrcal_cnt_reg[1]_25 ,
    \po_stg2_wrcal_cnt_reg[1]_26 ,
    \po_stg2_wrcal_cnt_reg[1]_27 ,
    \po_stg2_wrcal_cnt_reg[1]_28 ,
    \po_stg2_wrcal_cnt_reg[1]_29 ,
    \po_stg2_wrcal_cnt_reg[1]_30 ,
    \po_stg2_wrcal_cnt_reg[1]_31 ,
    \po_stg2_wrcal_cnt_reg[1]_32 ,
    \po_stg2_wrcal_cnt_reg[1]_33 ,
    \po_stg2_wrcal_cnt_reg[1]_34 ,
    \po_stg2_wrcal_cnt_reg[1]_35 ,
    \po_stg2_wrcal_cnt_reg[1]_36 ,
    \po_stg2_wrcal_cnt_reg[1]_37 ,
    \po_stg2_wrcal_cnt_reg[1]_38 ,
    \po_stg2_wrcal_cnt_reg[1]_39 ,
    \po_stg2_wrcal_cnt_reg[1]_40 ,
    \po_stg2_wrcal_cnt_reg[1]_41 ,
    \po_stg2_wrcal_cnt_reg[1]_42 ,
    \po_stg2_wrcal_cnt_reg[1]_43 ,
    \po_stg2_wrcal_cnt_reg[1]_44 ,
    \po_stg2_wrcal_cnt_reg[1]_45 ,
    \po_stg2_wrcal_cnt_reg[1]_46 ,
    \po_stg2_wrcal_cnt_reg[1]_47 ,
    \po_stg2_wrcal_cnt_reg[1]_48 ,
    \po_stg2_wrcal_cnt_reg[1]_49 ,
    \po_stg2_wrcal_cnt_reg[1]_50 ,
    \po_stg2_wrcal_cnt_reg[1]_51 ,
    \po_stg2_wrcal_cnt_reg[1]_52 ,
    \po_stg2_wrcal_cnt_reg[1]_53 ,
    \po_stg2_wrcal_cnt_reg[1]_54 ,
    \po_stg2_wrcal_cnt_reg[1]_55 ,
    \po_stg2_wrcal_cnt_reg[1]_56 ,
    \po_stg2_wrcal_cnt_reg[1]_57 ,
    \po_stg2_wrcal_cnt_reg[1]_58 ,
    \po_stg2_wrcal_cnt_reg[1]_59 ,
    \po_stg2_wrcal_cnt_reg[1]_60 ,
    \po_stg2_wrcal_cnt_reg[1]_61 ,
    \po_stg2_wrcal_cnt_reg[1]_62 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ,
    \rd_ptr_reg[3] ,
    Q,
    \entry_cnt_reg[4] ,
    \input_[9].iserdes_dq_.iserdesdq ,
    mem_dq_in,
    idelay_inc,
    LD0_9,
    A_rst_primitives,
    CLKB0_9,
    phaser_ctl_bus,
    \pi_dqs_found_lanes_r1_reg[3] ,
    \pi_dqs_found_lanes_r1_reg[3]_0 ,
    \pi_dqs_found_lanes_r1_reg[3]_1 ,
    \pi_dqs_found_lanes_r1_reg[3]_2 ,
    freq_refclk,
    mem_refclk,
    mem_dqs_in,
    ififo_rst_reg_0,
    sync_pulse,
    PCENABLECALIB,
    \pi_dqs_found_lanes_r1_reg[3]_3 ,
    \po_counter_read_val_reg[8] ,
    \po_counter_read_val_reg[8]_0 ,
    \po_counter_read_val_reg[8]_1 ,
    \my_empty_reg[7] ,
    \my_empty_reg[7]_0 ,
    \my_empty_reg[7]_1 ,
    \my_empty_reg[7]_2 ,
    \my_empty_reg[7]_3 ,
    \my_empty_reg[7]_4 ,
    \my_empty_reg[7]_5 ,
    \my_empty_reg[7]_6 ,
    phy_if_reset,
    \my_full_reg[1] ,
    phy_data_wr_en,
    out_fifo_0,
    out_fifo_1,
    out_fifo_2,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ,
    \gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 ,
    \my_full_reg[1]_0 ,
    \my_full_reg[1]_1 ,
    \my_full_reg[1]_2 ,
    \my_full_reg[1]_3 ,
    \my_full_reg[1]_4 ,
    \my_full_reg[1]_5 ,
    \my_full_reg[1]_6 ,
    \my_full_reg[1]_7 ,
    \wr_ptr[1]_i_2__2 ,
    if_empty_r,
    out_fifo_i_75__7);
  output out_dqs_7;
  output ts_dqs_7;
  output A_rst_primitives_reg;
  output [8:0]mem_dq_out;
  output [8:0]mem_dq_ts;
  output [0:0]in0;
  output A_rst_primitives_reg_0;
  output [5:0]A_rst_primitives_reg_1;
  output [8:0]A_rst_primitives_reg_2;
  output [0:0]if_empty_r_0;
  output [1:0]\my_empty_reg[4] ;
  output idelay_ld_rst_2;
  output rst_r4;
  output \my_empty_reg[1] ;
  output \rd_mux_sel_r_reg[1] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ;
  output \rd_mux_sel_r_reg[1]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;
  output \rd_mux_sel_r_reg[1]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ;
  output \rd_mux_sel_r_reg[1]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ;
  output \rd_mux_sel_r_reg[1]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ;
  output \rd_mux_sel_r_reg[1]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ;
  output \rd_mux_sel_r_reg[1]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ;
  output \rd_mux_sel_r_reg[1]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ;
  output \rd_mux_sel_r_reg[1]_7 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ;
  output \rd_mux_sel_r_reg[1]_8 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ;
  output \rd_mux_sel_r_reg[1]_9 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ;
  output \rd_mux_sel_r_reg[1]_10 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ;
  output \rd_mux_sel_r_reg[1]_11 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ;
  output \rd_mux_sel_r_reg[1]_12 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ;
  output \rd_mux_sel_r_reg[1]_13 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ;
  output \rd_mux_sel_r_reg[1]_14 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 ;
  output \rd_mux_sel_r_reg[1]_15 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ;
  output \rd_mux_sel_r_reg[1]_16 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ;
  output \rd_mux_sel_r_reg[1]_17 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ;
  output \rd_mux_sel_r_reg[1]_18 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ;
  output \rd_mux_sel_r_reg[1]_19 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ;
  output \rd_mux_sel_r_reg[1]_20 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ;
  output \rd_mux_sel_r_reg[1]_21 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ;
  output \rd_mux_sel_r_reg[1]_22 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 ;
  output \rd_mux_sel_r_reg[1]_23 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ;
  output \rd_mux_sel_r_reg[1]_24 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ;
  output \rd_mux_sel_r_reg[1]_25 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ;
  output \rd_mux_sel_r_reg[1]_26 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ;
  output \rd_mux_sel_r_reg[1]_27 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ;
  output \rd_mux_sel_r_reg[1]_28 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ;
  output \rd_mux_sel_r_reg[1]_29 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ;
  output \rd_mux_sel_r_reg[1]_30 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 ;
  output \rd_mux_sel_r_reg[1]_31 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ;
  output \rd_mux_sel_r_reg[1]_32 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ;
  output \rd_mux_sel_r_reg[1]_33 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ;
  output \rd_mux_sel_r_reg[1]_34 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ;
  output \rd_mux_sel_r_reg[1]_35 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ;
  output \rd_mux_sel_r_reg[1]_36 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ;
  output \rd_mux_sel_r_reg[1]_37 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ;
  output \rd_mux_sel_r_reg[1]_38 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 ;
  output \rd_mux_sel_r_reg[1]_39 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ;
  output \rd_mux_sel_r_reg[1]_40 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ;
  output \rd_mux_sel_r_reg[1]_41 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ;
  output \rd_mux_sel_r_reg[1]_42 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ;
  output \rd_mux_sel_r_reg[1]_43 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ;
  output \rd_mux_sel_r_reg[1]_44 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ;
  output \rd_mux_sel_r_reg[1]_45 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ;
  output \rd_mux_sel_r_reg[1]_46 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 ;
  output \rd_mux_sel_r_reg[1]_47 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ;
  output \rd_mux_sel_r_reg[1]_48 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ;
  output \rd_mux_sel_r_reg[1]_49 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ;
  output \rd_mux_sel_r_reg[1]_50 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ;
  output \rd_mux_sel_r_reg[1]_51 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ;
  output \rd_mux_sel_r_reg[1]_52 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ;
  output \rd_mux_sel_r_reg[1]_53 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ;
  output \rd_mux_sel_r_reg[1]_54 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 ;
  output \rd_mux_sel_r_reg[1]_55 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ;
  output \rd_mux_sel_r_reg[1]_56 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ;
  output \rd_mux_sel_r_reg[1]_57 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ;
  output \rd_mux_sel_r_reg[1]_58 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ;
  output \rd_mux_sel_r_reg[1]_59 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ;
  output \rd_mux_sel_r_reg[1]_60 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ;
  output \rd_mux_sel_r_reg[1]_61 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ;
  output \rd_mux_sel_r_reg[1]_62 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ;
  output \po_stg2_wrcal_cnt_reg[1] ;
  output \po_stg2_wrcal_cnt_reg[1]_0 ;
  output \po_stg2_wrcal_cnt_reg[1]_1 ;
  output \po_stg2_wrcal_cnt_reg[1]_2 ;
  output \po_stg2_wrcal_cnt_reg[1]_3 ;
  output \po_stg2_wrcal_cnt_reg[1]_4 ;
  output \po_stg2_wrcal_cnt_reg[1]_5 ;
  output \po_stg2_wrcal_cnt_reg[1]_6 ;
  output \po_stg2_wrcal_cnt_reg[1]_7 ;
  output \po_stg2_wrcal_cnt_reg[1]_8 ;
  output \po_stg2_wrcal_cnt_reg[1]_9 ;
  output \po_stg2_wrcal_cnt_reg[1]_10 ;
  output \po_stg2_wrcal_cnt_reg[1]_11 ;
  output \po_stg2_wrcal_cnt_reg[1]_12 ;
  output \po_stg2_wrcal_cnt_reg[1]_13 ;
  output \po_stg2_wrcal_cnt_reg[1]_14 ;
  output \po_stg2_wrcal_cnt_reg[1]_15 ;
  output \po_stg2_wrcal_cnt_reg[1]_16 ;
  output \po_stg2_wrcal_cnt_reg[1]_17 ;
  output \po_stg2_wrcal_cnt_reg[1]_18 ;
  output \po_stg2_wrcal_cnt_reg[1]_19 ;
  output \po_stg2_wrcal_cnt_reg[1]_20 ;
  output \po_stg2_wrcal_cnt_reg[1]_21 ;
  output \po_stg2_wrcal_cnt_reg[1]_22 ;
  output \po_stg2_wrcal_cnt_reg[1]_23 ;
  output \po_stg2_wrcal_cnt_reg[1]_24 ;
  output \po_stg2_wrcal_cnt_reg[1]_25 ;
  output \po_stg2_wrcal_cnt_reg[1]_26 ;
  output \po_stg2_wrcal_cnt_reg[1]_27 ;
  output \po_stg2_wrcal_cnt_reg[1]_28 ;
  output \po_stg2_wrcal_cnt_reg[1]_29 ;
  output \po_stg2_wrcal_cnt_reg[1]_30 ;
  output \po_stg2_wrcal_cnt_reg[1]_31 ;
  output \po_stg2_wrcal_cnt_reg[1]_32 ;
  output \po_stg2_wrcal_cnt_reg[1]_33 ;
  output \po_stg2_wrcal_cnt_reg[1]_34 ;
  output \po_stg2_wrcal_cnt_reg[1]_35 ;
  output \po_stg2_wrcal_cnt_reg[1]_36 ;
  output \po_stg2_wrcal_cnt_reg[1]_37 ;
  output \po_stg2_wrcal_cnt_reg[1]_38 ;
  output \po_stg2_wrcal_cnt_reg[1]_39 ;
  output \po_stg2_wrcal_cnt_reg[1]_40 ;
  output \po_stg2_wrcal_cnt_reg[1]_41 ;
  output \po_stg2_wrcal_cnt_reg[1]_42 ;
  output \po_stg2_wrcal_cnt_reg[1]_43 ;
  output \po_stg2_wrcal_cnt_reg[1]_44 ;
  output \po_stg2_wrcal_cnt_reg[1]_45 ;
  output \po_stg2_wrcal_cnt_reg[1]_46 ;
  output \po_stg2_wrcal_cnt_reg[1]_47 ;
  output \po_stg2_wrcal_cnt_reg[1]_48 ;
  output \po_stg2_wrcal_cnt_reg[1]_49 ;
  output \po_stg2_wrcal_cnt_reg[1]_50 ;
  output \po_stg2_wrcal_cnt_reg[1]_51 ;
  output \po_stg2_wrcal_cnt_reg[1]_52 ;
  output \po_stg2_wrcal_cnt_reg[1]_53 ;
  output \po_stg2_wrcal_cnt_reg[1]_54 ;
  output \po_stg2_wrcal_cnt_reg[1]_55 ;
  output \po_stg2_wrcal_cnt_reg[1]_56 ;
  output \po_stg2_wrcal_cnt_reg[1]_57 ;
  output \po_stg2_wrcal_cnt_reg[1]_58 ;
  output \po_stg2_wrcal_cnt_reg[1]_59 ;
  output \po_stg2_wrcal_cnt_reg[1]_60 ;
  output \po_stg2_wrcal_cnt_reg[1]_61 ;
  output \po_stg2_wrcal_cnt_reg[1]_62 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ;
  output [63:0]\rd_ptr_reg[3] ;
  output [2:0]Q;
  input \entry_cnt_reg[4] ;
  input \input_[9].iserdes_dq_.iserdesdq ;
  input [7:0]mem_dq_in;
  input idelay_inc;
  input LD0_9;
  input A_rst_primitives;
  input CLKB0_9;
  input [3:0]phaser_ctl_bus;
  input \pi_dqs_found_lanes_r1_reg[3] ;
  input \pi_dqs_found_lanes_r1_reg[3]_0 ;
  input \pi_dqs_found_lanes_r1_reg[3]_1 ;
  input \pi_dqs_found_lanes_r1_reg[3]_2 ;
  input freq_refclk;
  input mem_refclk;
  input [0:0]mem_dqs_in;
  input ififo_rst_reg_0;
  input sync_pulse;
  input [1:0]PCENABLECALIB;
  input [5:0]\pi_dqs_found_lanes_r1_reg[3]_3 ;
  input \po_counter_read_val_reg[8] ;
  input \po_counter_read_val_reg[8]_0 ;
  input \po_counter_read_val_reg[8]_1 ;
  input [7:0]\my_empty_reg[7] ;
  input [7:0]\my_empty_reg[7]_0 ;
  input [7:0]\my_empty_reg[7]_1 ;
  input [7:0]\my_empty_reg[7]_2 ;
  input [7:0]\my_empty_reg[7]_3 ;
  input [7:0]\my_empty_reg[7]_4 ;
  input [7:0]\my_empty_reg[7]_5 ;
  input [7:0]\my_empty_reg[7]_6 ;
  input phy_if_reset;
  input \my_full_reg[1] ;
  input phy_data_wr_en;
  input out_fifo_0;
  input [7:0]out_fifo_1;
  input out_fifo_2;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;
  input [1:0]\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 ;
  input [1:0]\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 ;
  input \my_full_reg[1]_0 ;
  input \my_full_reg[1]_1 ;
  input \my_full_reg[1]_2 ;
  input \my_full_reg[1]_3 ;
  input \my_full_reg[1]_4 ;
  input \my_full_reg[1]_5 ;
  input \my_full_reg[1]_6 ;
  input \my_full_reg[1]_7 ;
  input [0:0]\wr_ptr[1]_i_2__2 ;
  input [0:0]if_empty_r;
  input [71:0]out_fifo_i_75__7;

  wire A_rst_primitives;
  wire A_rst_primitives_reg;
  wire A_rst_primitives_reg_0;
  wire [5:0]A_rst_primitives_reg_1;
  wire [8:0]A_rst_primitives_reg_2;
  wire CLKB0_9;
  wire LD0_9;
  wire [1:0]PCENABLECALIB;
  wire [2:0]Q;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ;
  wire \entry_cnt_reg[4] ;
  wire freq_refclk;
  wire [1:0]\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_1 ;
  wire [1:0]\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 ;
  wire idelay_inc;
  wire idelay_ld_rst_2;
  wire [3:0]if_d2;
  wire [3:0]if_d3;
  wire [3:0]if_d4;
  wire [3:0]if_d5;
  wire [3:0]if_d6;
  wire [3:0]if_d7;
  wire [3:0]if_d8;
  wire [3:0]if_d9;
  wire if_empty_;
  wire [0:0]if_empty_r;
  wire [0:0]if_empty_r_0;
  wire ififo_rst;
  wire ififo_rst_reg_0;
  wire ififo_wr_enable;
  wire [0:0]in0;
  wire \in_fifo_gen.in_fifo_n_0 ;
  wire \in_fifo_gen.in_fifo_n_1 ;
  wire \in_fifo_gen.in_fifo_n_3 ;
  wire \input_[9].iserdes_dq_.iserdesdq ;
  wire iserdes_clkdiv;
  wire [7:0]mem_dq_in;
  wire [8:0]mem_dq_out;
  wire [8:0]mem_dq_ts;
  wire [0:0]mem_dqs_in;
  wire mem_refclk;
  wire \my_empty_reg[1] ;
  wire [1:0]\my_empty_reg[4] ;
  wire [7:0]\my_empty_reg[7] ;
  wire [7:0]\my_empty_reg[7]_0 ;
  wire [7:0]\my_empty_reg[7]_1 ;
  wire [7:0]\my_empty_reg[7]_2 ;
  wire [7:0]\my_empty_reg[7]_3 ;
  wire [7:0]\my_empty_reg[7]_4 ;
  wire [7:0]\my_empty_reg[7]_5 ;
  wire [7:0]\my_empty_reg[7]_6 ;
  wire \my_full_reg[1] ;
  wire \my_full_reg[1]_0 ;
  wire \my_full_reg[1]_1 ;
  wire \my_full_reg[1]_2 ;
  wire \my_full_reg[1]_3 ;
  wire \my_full_reg[1]_4 ;
  wire \my_full_reg[1]_5 ;
  wire \my_full_reg[1]_6 ;
  wire \my_full_reg[1]_7 ;
  wire [7:0]of_d1;
  wire [39:0]of_dqbus;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ;
  wire ofifo_rst;
  wire oserdes_clk;
  wire oserdes_clk_delayed;
  wire oserdes_clkdiv;
  wire [1:0]oserdes_dq_ts;
  wire [1:0]oserdes_dqs;
  wire [1:0]oserdes_dqs_ts;
  wire out_dqs_7;
  wire out_fifo_0;
  wire [7:0]out_fifo_1;
  wire out_fifo_2;
  wire [71:0]out_fifo_i_75__7;
  wire out_fifo_n_0;
  wire out_fifo_n_1;
  wire out_fifo_n_2;
  wire out_fifo_n_3;
  wire [3:0]phaser_ctl_bus;
  wire \phaser_in_gen.phaser_in_n_1 ;
  wire \phaser_in_gen.phaser_in_n_2 ;
  wire \phaser_in_gen.phaser_in_n_5 ;
  wire \phaser_in_gen.phaser_in_n_7 ;
  wire phaser_out_n_0;
  wire phaser_out_n_1;
  wire phy_data_wr_en;
  wire phy_if_reset;
  wire \pi_dqs_found_lanes_r1_reg[3] ;
  wire \pi_dqs_found_lanes_r1_reg[3]_0 ;
  wire \pi_dqs_found_lanes_r1_reg[3]_1 ;
  wire \pi_dqs_found_lanes_r1_reg[3]_2 ;
  wire [5:0]\pi_dqs_found_lanes_r1_reg[3]_3 ;
  wire \po_counter_read_val_reg[8] ;
  wire \po_counter_read_val_reg[8]_0 ;
  wire \po_counter_read_val_reg[8]_1 ;
  wire po_oserdes_rst;
  wire po_rd_enable;
  wire \po_stg2_wrcal_cnt_reg[1] ;
  wire \po_stg2_wrcal_cnt_reg[1]_0 ;
  wire \po_stg2_wrcal_cnt_reg[1]_1 ;
  wire \po_stg2_wrcal_cnt_reg[1]_10 ;
  wire \po_stg2_wrcal_cnt_reg[1]_11 ;
  wire \po_stg2_wrcal_cnt_reg[1]_12 ;
  wire \po_stg2_wrcal_cnt_reg[1]_13 ;
  wire \po_stg2_wrcal_cnt_reg[1]_14 ;
  wire \po_stg2_wrcal_cnt_reg[1]_15 ;
  wire \po_stg2_wrcal_cnt_reg[1]_16 ;
  wire \po_stg2_wrcal_cnt_reg[1]_17 ;
  wire \po_stg2_wrcal_cnt_reg[1]_18 ;
  wire \po_stg2_wrcal_cnt_reg[1]_19 ;
  wire \po_stg2_wrcal_cnt_reg[1]_2 ;
  wire \po_stg2_wrcal_cnt_reg[1]_20 ;
  wire \po_stg2_wrcal_cnt_reg[1]_21 ;
  wire \po_stg2_wrcal_cnt_reg[1]_22 ;
  wire \po_stg2_wrcal_cnt_reg[1]_23 ;
  wire \po_stg2_wrcal_cnt_reg[1]_24 ;
  wire \po_stg2_wrcal_cnt_reg[1]_25 ;
  wire \po_stg2_wrcal_cnt_reg[1]_26 ;
  wire \po_stg2_wrcal_cnt_reg[1]_27 ;
  wire \po_stg2_wrcal_cnt_reg[1]_28 ;
  wire \po_stg2_wrcal_cnt_reg[1]_29 ;
  wire \po_stg2_wrcal_cnt_reg[1]_3 ;
  wire \po_stg2_wrcal_cnt_reg[1]_30 ;
  wire \po_stg2_wrcal_cnt_reg[1]_31 ;
  wire \po_stg2_wrcal_cnt_reg[1]_32 ;
  wire \po_stg2_wrcal_cnt_reg[1]_33 ;
  wire \po_stg2_wrcal_cnt_reg[1]_34 ;
  wire \po_stg2_wrcal_cnt_reg[1]_35 ;
  wire \po_stg2_wrcal_cnt_reg[1]_36 ;
  wire \po_stg2_wrcal_cnt_reg[1]_37 ;
  wire \po_stg2_wrcal_cnt_reg[1]_38 ;
  wire \po_stg2_wrcal_cnt_reg[1]_39 ;
  wire \po_stg2_wrcal_cnt_reg[1]_4 ;
  wire \po_stg2_wrcal_cnt_reg[1]_40 ;
  wire \po_stg2_wrcal_cnt_reg[1]_41 ;
  wire \po_stg2_wrcal_cnt_reg[1]_42 ;
  wire \po_stg2_wrcal_cnt_reg[1]_43 ;
  wire \po_stg2_wrcal_cnt_reg[1]_44 ;
  wire \po_stg2_wrcal_cnt_reg[1]_45 ;
  wire \po_stg2_wrcal_cnt_reg[1]_46 ;
  wire \po_stg2_wrcal_cnt_reg[1]_47 ;
  wire \po_stg2_wrcal_cnt_reg[1]_48 ;
  wire \po_stg2_wrcal_cnt_reg[1]_49 ;
  wire \po_stg2_wrcal_cnt_reg[1]_5 ;
  wire \po_stg2_wrcal_cnt_reg[1]_50 ;
  wire \po_stg2_wrcal_cnt_reg[1]_51 ;
  wire \po_stg2_wrcal_cnt_reg[1]_52 ;
  wire \po_stg2_wrcal_cnt_reg[1]_53 ;
  wire \po_stg2_wrcal_cnt_reg[1]_54 ;
  wire \po_stg2_wrcal_cnt_reg[1]_55 ;
  wire \po_stg2_wrcal_cnt_reg[1]_56 ;
  wire \po_stg2_wrcal_cnt_reg[1]_57 ;
  wire \po_stg2_wrcal_cnt_reg[1]_58 ;
  wire \po_stg2_wrcal_cnt_reg[1]_59 ;
  wire \po_stg2_wrcal_cnt_reg[1]_6 ;
  wire \po_stg2_wrcal_cnt_reg[1]_60 ;
  wire \po_stg2_wrcal_cnt_reg[1]_61 ;
  wire \po_stg2_wrcal_cnt_reg[1]_62 ;
  wire \po_stg2_wrcal_cnt_reg[1]_7 ;
  wire \po_stg2_wrcal_cnt_reg[1]_8 ;
  wire \po_stg2_wrcal_cnt_reg[1]_9 ;
  wire [79:0]rd_data;
  wire [79:12]rd_data_r;
  wire \rd_mux_sel_r_reg[1] ;
  wire \rd_mux_sel_r_reg[1]_0 ;
  wire \rd_mux_sel_r_reg[1]_1 ;
  wire \rd_mux_sel_r_reg[1]_10 ;
  wire \rd_mux_sel_r_reg[1]_11 ;
  wire \rd_mux_sel_r_reg[1]_12 ;
  wire \rd_mux_sel_r_reg[1]_13 ;
  wire \rd_mux_sel_r_reg[1]_14 ;
  wire \rd_mux_sel_r_reg[1]_15 ;
  wire \rd_mux_sel_r_reg[1]_16 ;
  wire \rd_mux_sel_r_reg[1]_17 ;
  wire \rd_mux_sel_r_reg[1]_18 ;
  wire \rd_mux_sel_r_reg[1]_19 ;
  wire \rd_mux_sel_r_reg[1]_2 ;
  wire \rd_mux_sel_r_reg[1]_20 ;
  wire \rd_mux_sel_r_reg[1]_21 ;
  wire \rd_mux_sel_r_reg[1]_22 ;
  wire \rd_mux_sel_r_reg[1]_23 ;
  wire \rd_mux_sel_r_reg[1]_24 ;
  wire \rd_mux_sel_r_reg[1]_25 ;
  wire \rd_mux_sel_r_reg[1]_26 ;
  wire \rd_mux_sel_r_reg[1]_27 ;
  wire \rd_mux_sel_r_reg[1]_28 ;
  wire \rd_mux_sel_r_reg[1]_29 ;
  wire \rd_mux_sel_r_reg[1]_3 ;
  wire \rd_mux_sel_r_reg[1]_30 ;
  wire \rd_mux_sel_r_reg[1]_31 ;
  wire \rd_mux_sel_r_reg[1]_32 ;
  wire \rd_mux_sel_r_reg[1]_33 ;
  wire \rd_mux_sel_r_reg[1]_34 ;
  wire \rd_mux_sel_r_reg[1]_35 ;
  wire \rd_mux_sel_r_reg[1]_36 ;
  wire \rd_mux_sel_r_reg[1]_37 ;
  wire \rd_mux_sel_r_reg[1]_38 ;
  wire \rd_mux_sel_r_reg[1]_39 ;
  wire \rd_mux_sel_r_reg[1]_4 ;
  wire \rd_mux_sel_r_reg[1]_40 ;
  wire \rd_mux_sel_r_reg[1]_41 ;
  wire \rd_mux_sel_r_reg[1]_42 ;
  wire \rd_mux_sel_r_reg[1]_43 ;
  wire \rd_mux_sel_r_reg[1]_44 ;
  wire \rd_mux_sel_r_reg[1]_45 ;
  wire \rd_mux_sel_r_reg[1]_46 ;
  wire \rd_mux_sel_r_reg[1]_47 ;
  wire \rd_mux_sel_r_reg[1]_48 ;
  wire \rd_mux_sel_r_reg[1]_49 ;
  wire \rd_mux_sel_r_reg[1]_5 ;
  wire \rd_mux_sel_r_reg[1]_50 ;
  wire \rd_mux_sel_r_reg[1]_51 ;
  wire \rd_mux_sel_r_reg[1]_52 ;
  wire \rd_mux_sel_r_reg[1]_53 ;
  wire \rd_mux_sel_r_reg[1]_54 ;
  wire \rd_mux_sel_r_reg[1]_55 ;
  wire \rd_mux_sel_r_reg[1]_56 ;
  wire \rd_mux_sel_r_reg[1]_57 ;
  wire \rd_mux_sel_r_reg[1]_58 ;
  wire \rd_mux_sel_r_reg[1]_59 ;
  wire \rd_mux_sel_r_reg[1]_6 ;
  wire \rd_mux_sel_r_reg[1]_60 ;
  wire \rd_mux_sel_r_reg[1]_61 ;
  wire \rd_mux_sel_r_reg[1]_62 ;
  wire \rd_mux_sel_r_reg[1]_7 ;
  wire \rd_mux_sel_r_reg[1]_8 ;
  wire \rd_mux_sel_r_reg[1]_9 ;
  wire [63:0]\rd_ptr_reg[3] ;
  wire rst_r4;
  wire sync_pulse;
  wire ts_dqs_7;
  wire [0:0]\wr_ptr[1]_i_2__2 ;
  wire [7:4]\NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED ;
  wire [7:4]\NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED ;
  wire [7:4]NLW_out_fifo_Q5_UNCONNECTED;
  wire [7:4]NLW_out_fifo_Q6_UNCONNECTED;
  wire NLW_phaser_out_PHASEREFCLK_UNCONNECTED;

  mig_mig_7series_v4_2_ddr_byte_group_io__parameterized0_29 ddr_byte_group_io
       (.A_rst_primitives(A_rst_primitives),
        .CLKB0_9(CLKB0_9),
        .CTSBUS(oserdes_dqs_ts[0]),
        .D2(if_d2),
        .D3(if_d3),
        .D4(if_d4),
        .D5(if_d5),
        .D6(if_d6),
        .D7(if_d7),
        .D8(if_d8),
        .D9(if_d9),
        .DQSBUS(oserdes_dqs),
        .DTSBUS(oserdes_dq_ts),
        .LD0_9(LD0_9),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (A_rst_primitives_reg),
        .idelay_inc(idelay_inc),
        .idelay_ld_rst_2(idelay_ld_rst_2),
        .idelay_ld_rst_reg_0(\entry_cnt_reg[4] ),
        .\input_[9].iserdes_dq_.iserdesdq_0 (\input_[9].iserdes_dq_.iserdesdq ),
        .iserdes_clkdiv(iserdes_clkdiv),
        .mem_dq_in(mem_dq_in),
        .mem_dq_out(mem_dq_out),
        .mem_dq_ts(mem_dq_ts),
        .of_dqbus(of_dqbus[39:4]),
        .oserdes_clk(oserdes_clk),
        .oserdes_clk_delayed(oserdes_clk_delayed),
        .oserdes_clkdiv(oserdes_clkdiv),
        .out_dqs_7(out_dqs_7),
        .po_oserdes_rst(po_oserdes_rst),
        .rst_r4(rst_r4),
        .ts_dqs_7(ts_dqs_7));
  (* syn_maxfan = "3" *) 
  FDRE \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(if_empty_),
        .Q(if_empty_r_0),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[12]),
        .Q(rd_data_r[12]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[13]),
        .Q(rd_data_r[13]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[14]),
        .Q(rd_data_r[14]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[15]),
        .Q(rd_data_r[15]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[16]),
        .Q(rd_data_r[16]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[17]),
        .Q(rd_data_r[17]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[18]),
        .Q(rd_data_r[18]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[19]),
        .Q(rd_data_r[19]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[20]),
        .Q(rd_data_r[20]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[21]),
        .Q(rd_data_r[21]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[22]),
        .Q(rd_data_r[22]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[23]),
        .Q(rd_data_r[23]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[24]),
        .Q(rd_data_r[24]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[25]),
        .Q(rd_data_r[25]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[26]),
        .Q(rd_data_r[26]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[27]),
        .Q(rd_data_r[27]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[28]),
        .Q(rd_data_r[28]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[29]),
        .Q(rd_data_r[29]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[30]),
        .Q(rd_data_r[30]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[31]),
        .Q(rd_data_r[31]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[32]),
        .Q(rd_data_r[32]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[33]),
        .Q(rd_data_r[33]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[34]),
        .Q(rd_data_r[34]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[35]),
        .Q(rd_data_r[35]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[36]),
        .Q(rd_data_r[36]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[37]),
        .Q(rd_data_r[37]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[38]),
        .Q(rd_data_r[38]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[39]),
        .Q(rd_data_r[39]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[40]),
        .Q(rd_data_r[40]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[41]),
        .Q(rd_data_r[41]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[42]),
        .Q(rd_data_r[42]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[43]),
        .Q(rd_data_r[43]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[44]),
        .Q(rd_data_r[44]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[45]),
        .Q(rd_data_r[45]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[46]),
        .Q(rd_data_r[46]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[47]),
        .Q(rd_data_r[47]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[48]),
        .Q(rd_data_r[48]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[49]),
        .Q(rd_data_r[49]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[50]),
        .Q(rd_data_r[50]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[51]),
        .Q(rd_data_r[51]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[52]),
        .Q(rd_data_r[52]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[53]),
        .Q(rd_data_r[53]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[54]),
        .Q(rd_data_r[54]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[55]),
        .Q(rd_data_r[55]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[56]),
        .Q(rd_data_r[56]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[57]),
        .Q(rd_data_r[57]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[58]),
        .Q(rd_data_r[58]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[59]),
        .Q(rd_data_r[59]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[60]),
        .Q(rd_data_r[60]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[61]),
        .Q(rd_data_r[61]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[62]),
        .Q(rd_data_r[62]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[63]),
        .Q(rd_data_r[63]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[64]),
        .Q(rd_data_r[64]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[65]),
        .Q(rd_data_r[65]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[66]),
        .Q(rd_data_r[66]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[67]),
        .Q(rd_data_r[67]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[68]),
        .Q(rd_data_r[68]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[69]),
        .Q(rd_data_r[69]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[70]),
        .Q(rd_data_r[70]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[71]),
        .Q(rd_data_r[71]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[72]),
        .Q(rd_data_r[72]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[73]),
        .Q(rd_data_r[73]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[74]),
        .Q(rd_data_r[74]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[75]),
        .Q(rd_data_r[75]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[76]),
        .Q(rd_data_r[76]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[77]),
        .Q(rd_data_r[77]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[78]),
        .Q(rd_data_r[78]),
        .R(1'b0));
  FDRE \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rd_data[79]),
        .Q(rd_data_r[79]),
        .R(1'b0));
  mig_mig_7series_v4_2_ddr_if_post_fifo_30 \dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo 
       (.Q(rd_data_r),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ),
        .\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] (\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_1 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_1 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_1 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_1 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_1 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_1 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_1 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_1 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_1 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_1 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_1 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_1 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_1 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_1 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_1 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_1 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_1 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_1 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_1 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_1 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_1 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_1 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_1 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_1 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_1 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_1 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_1 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_1 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_1 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_1 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_1 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_1 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 ),
        .if_empty_r(if_empty_r),
        .ififo_rst(ififo_rst),
        .\my_empty_reg[4]_0 (\my_empty_reg[4] [0]),
        .\my_empty_reg[4]_1 (\my_empty_reg[4] [1]),
        .\my_full_reg[1]_0 (if_empty_r_0),
        .\my_full_reg[1]_1 (\my_full_reg[1] ),
        .\my_full_reg[1]_2 (\my_full_reg[1]_0 ),
        .\my_full_reg[1]_3 (\my_full_reg[1]_1 ),
        .\my_full_reg[1]_4 (\my_full_reg[1]_2 ),
        .\my_full_reg[1]_5 (\my_full_reg[1]_3 ),
        .\my_full_reg[1]_6 (\my_full_reg[1]_4 ),
        .\my_full_reg[1]_7 (\my_full_reg[1]_5 ),
        .\my_full_reg[1]_8 (\my_full_reg[1]_6 ),
        .\my_full_reg[1]_9 (\my_full_reg[1]_7 ),
        .\po_stg2_wrcal_cnt_reg[1] (\po_stg2_wrcal_cnt_reg[1] ),
        .\po_stg2_wrcal_cnt_reg[1]_0 (\po_stg2_wrcal_cnt_reg[1]_0 ),
        .\po_stg2_wrcal_cnt_reg[1]_1 (\po_stg2_wrcal_cnt_reg[1]_1 ),
        .\po_stg2_wrcal_cnt_reg[1]_10 (\po_stg2_wrcal_cnt_reg[1]_10 ),
        .\po_stg2_wrcal_cnt_reg[1]_11 (\po_stg2_wrcal_cnt_reg[1]_11 ),
        .\po_stg2_wrcal_cnt_reg[1]_12 (\po_stg2_wrcal_cnt_reg[1]_12 ),
        .\po_stg2_wrcal_cnt_reg[1]_13 (\po_stg2_wrcal_cnt_reg[1]_13 ),
        .\po_stg2_wrcal_cnt_reg[1]_14 (\po_stg2_wrcal_cnt_reg[1]_14 ),
        .\po_stg2_wrcal_cnt_reg[1]_15 (\po_stg2_wrcal_cnt_reg[1]_15 ),
        .\po_stg2_wrcal_cnt_reg[1]_16 (\po_stg2_wrcal_cnt_reg[1]_16 ),
        .\po_stg2_wrcal_cnt_reg[1]_17 (\po_stg2_wrcal_cnt_reg[1]_17 ),
        .\po_stg2_wrcal_cnt_reg[1]_18 (\po_stg2_wrcal_cnt_reg[1]_18 ),
        .\po_stg2_wrcal_cnt_reg[1]_19 (\po_stg2_wrcal_cnt_reg[1]_19 ),
        .\po_stg2_wrcal_cnt_reg[1]_2 (\po_stg2_wrcal_cnt_reg[1]_2 ),
        .\po_stg2_wrcal_cnt_reg[1]_20 (\po_stg2_wrcal_cnt_reg[1]_20 ),
        .\po_stg2_wrcal_cnt_reg[1]_21 (\po_stg2_wrcal_cnt_reg[1]_21 ),
        .\po_stg2_wrcal_cnt_reg[1]_22 (\po_stg2_wrcal_cnt_reg[1]_22 ),
        .\po_stg2_wrcal_cnt_reg[1]_23 (\po_stg2_wrcal_cnt_reg[1]_23 ),
        .\po_stg2_wrcal_cnt_reg[1]_24 (\po_stg2_wrcal_cnt_reg[1]_24 ),
        .\po_stg2_wrcal_cnt_reg[1]_25 (\po_stg2_wrcal_cnt_reg[1]_25 ),
        .\po_stg2_wrcal_cnt_reg[1]_26 (\po_stg2_wrcal_cnt_reg[1]_26 ),
        .\po_stg2_wrcal_cnt_reg[1]_27 (\po_stg2_wrcal_cnt_reg[1]_27 ),
        .\po_stg2_wrcal_cnt_reg[1]_28 (\po_stg2_wrcal_cnt_reg[1]_28 ),
        .\po_stg2_wrcal_cnt_reg[1]_29 (\po_stg2_wrcal_cnt_reg[1]_29 ),
        .\po_stg2_wrcal_cnt_reg[1]_3 (\po_stg2_wrcal_cnt_reg[1]_3 ),
        .\po_stg2_wrcal_cnt_reg[1]_30 (\po_stg2_wrcal_cnt_reg[1]_30 ),
        .\po_stg2_wrcal_cnt_reg[1]_31 (\po_stg2_wrcal_cnt_reg[1]_31 ),
        .\po_stg2_wrcal_cnt_reg[1]_32 (\po_stg2_wrcal_cnt_reg[1]_32 ),
        .\po_stg2_wrcal_cnt_reg[1]_33 (\po_stg2_wrcal_cnt_reg[1]_33 ),
        .\po_stg2_wrcal_cnt_reg[1]_34 (\po_stg2_wrcal_cnt_reg[1]_34 ),
        .\po_stg2_wrcal_cnt_reg[1]_35 (\po_stg2_wrcal_cnt_reg[1]_35 ),
        .\po_stg2_wrcal_cnt_reg[1]_36 (\po_stg2_wrcal_cnt_reg[1]_36 ),
        .\po_stg2_wrcal_cnt_reg[1]_37 (\po_stg2_wrcal_cnt_reg[1]_37 ),
        .\po_stg2_wrcal_cnt_reg[1]_38 (\po_stg2_wrcal_cnt_reg[1]_38 ),
        .\po_stg2_wrcal_cnt_reg[1]_39 (\po_stg2_wrcal_cnt_reg[1]_39 ),
        .\po_stg2_wrcal_cnt_reg[1]_4 (\po_stg2_wrcal_cnt_reg[1]_4 ),
        .\po_stg2_wrcal_cnt_reg[1]_40 (\po_stg2_wrcal_cnt_reg[1]_40 ),
        .\po_stg2_wrcal_cnt_reg[1]_41 (\po_stg2_wrcal_cnt_reg[1]_41 ),
        .\po_stg2_wrcal_cnt_reg[1]_42 (\po_stg2_wrcal_cnt_reg[1]_42 ),
        .\po_stg2_wrcal_cnt_reg[1]_43 (\po_stg2_wrcal_cnt_reg[1]_43 ),
        .\po_stg2_wrcal_cnt_reg[1]_44 (\po_stg2_wrcal_cnt_reg[1]_44 ),
        .\po_stg2_wrcal_cnt_reg[1]_45 (\po_stg2_wrcal_cnt_reg[1]_45 ),
        .\po_stg2_wrcal_cnt_reg[1]_46 (\po_stg2_wrcal_cnt_reg[1]_46 ),
        .\po_stg2_wrcal_cnt_reg[1]_47 (\po_stg2_wrcal_cnt_reg[1]_47 ),
        .\po_stg2_wrcal_cnt_reg[1]_48 (\po_stg2_wrcal_cnt_reg[1]_48 ),
        .\po_stg2_wrcal_cnt_reg[1]_49 (\po_stg2_wrcal_cnt_reg[1]_49 ),
        .\po_stg2_wrcal_cnt_reg[1]_5 (\po_stg2_wrcal_cnt_reg[1]_5 ),
        .\po_stg2_wrcal_cnt_reg[1]_50 (\po_stg2_wrcal_cnt_reg[1]_50 ),
        .\po_stg2_wrcal_cnt_reg[1]_51 (\po_stg2_wrcal_cnt_reg[1]_51 ),
        .\po_stg2_wrcal_cnt_reg[1]_52 (\po_stg2_wrcal_cnt_reg[1]_52 ),
        .\po_stg2_wrcal_cnt_reg[1]_53 (\po_stg2_wrcal_cnt_reg[1]_53 ),
        .\po_stg2_wrcal_cnt_reg[1]_54 (\po_stg2_wrcal_cnt_reg[1]_54 ),
        .\po_stg2_wrcal_cnt_reg[1]_55 (\po_stg2_wrcal_cnt_reg[1]_55 ),
        .\po_stg2_wrcal_cnt_reg[1]_56 (\po_stg2_wrcal_cnt_reg[1]_56 ),
        .\po_stg2_wrcal_cnt_reg[1]_57 (\po_stg2_wrcal_cnt_reg[1]_57 ),
        .\po_stg2_wrcal_cnt_reg[1]_58 (\po_stg2_wrcal_cnt_reg[1]_58 ),
        .\po_stg2_wrcal_cnt_reg[1]_59 (\po_stg2_wrcal_cnt_reg[1]_59 ),
        .\po_stg2_wrcal_cnt_reg[1]_6 (\po_stg2_wrcal_cnt_reg[1]_6 ),
        .\po_stg2_wrcal_cnt_reg[1]_60 (\po_stg2_wrcal_cnt_reg[1]_60 ),
        .\po_stg2_wrcal_cnt_reg[1]_61 (\po_stg2_wrcal_cnt_reg[1]_61 ),
        .\po_stg2_wrcal_cnt_reg[1]_62 (\po_stg2_wrcal_cnt_reg[1]_62 ),
        .\po_stg2_wrcal_cnt_reg[1]_7 (\po_stg2_wrcal_cnt_reg[1]_7 ),
        .\po_stg2_wrcal_cnt_reg[1]_8 (\po_stg2_wrcal_cnt_reg[1]_8 ),
        .\po_stg2_wrcal_cnt_reg[1]_9 (\po_stg2_wrcal_cnt_reg[1]_9 ),
        .\rd_mux_sel_r_reg[1] (\rd_mux_sel_r_reg[1] ),
        .\rd_mux_sel_r_reg[1]_0 (\rd_mux_sel_r_reg[1]_0 ),
        .\rd_mux_sel_r_reg[1]_1 (\rd_mux_sel_r_reg[1]_1 ),
        .\rd_mux_sel_r_reg[1]_10 (\rd_mux_sel_r_reg[1]_10 ),
        .\rd_mux_sel_r_reg[1]_11 (\rd_mux_sel_r_reg[1]_11 ),
        .\rd_mux_sel_r_reg[1]_12 (\rd_mux_sel_r_reg[1]_12 ),
        .\rd_mux_sel_r_reg[1]_13 (\rd_mux_sel_r_reg[1]_13 ),
        .\rd_mux_sel_r_reg[1]_14 (\rd_mux_sel_r_reg[1]_14 ),
        .\rd_mux_sel_r_reg[1]_15 (\rd_mux_sel_r_reg[1]_15 ),
        .\rd_mux_sel_r_reg[1]_16 (\rd_mux_sel_r_reg[1]_16 ),
        .\rd_mux_sel_r_reg[1]_17 (\rd_mux_sel_r_reg[1]_17 ),
        .\rd_mux_sel_r_reg[1]_18 (\rd_mux_sel_r_reg[1]_18 ),
        .\rd_mux_sel_r_reg[1]_19 (\rd_mux_sel_r_reg[1]_19 ),
        .\rd_mux_sel_r_reg[1]_2 (\rd_mux_sel_r_reg[1]_2 ),
        .\rd_mux_sel_r_reg[1]_20 (\rd_mux_sel_r_reg[1]_20 ),
        .\rd_mux_sel_r_reg[1]_21 (\rd_mux_sel_r_reg[1]_21 ),
        .\rd_mux_sel_r_reg[1]_22 (\rd_mux_sel_r_reg[1]_22 ),
        .\rd_mux_sel_r_reg[1]_23 (\rd_mux_sel_r_reg[1]_23 ),
        .\rd_mux_sel_r_reg[1]_24 (\rd_mux_sel_r_reg[1]_24 ),
        .\rd_mux_sel_r_reg[1]_25 (\rd_mux_sel_r_reg[1]_25 ),
        .\rd_mux_sel_r_reg[1]_26 (\rd_mux_sel_r_reg[1]_26 ),
        .\rd_mux_sel_r_reg[1]_27 (\rd_mux_sel_r_reg[1]_27 ),
        .\rd_mux_sel_r_reg[1]_28 (\rd_mux_sel_r_reg[1]_28 ),
        .\rd_mux_sel_r_reg[1]_29 (\rd_mux_sel_r_reg[1]_29 ),
        .\rd_mux_sel_r_reg[1]_3 (\rd_mux_sel_r_reg[1]_3 ),
        .\rd_mux_sel_r_reg[1]_30 (\rd_mux_sel_r_reg[1]_30 ),
        .\rd_mux_sel_r_reg[1]_31 (\rd_mux_sel_r_reg[1]_31 ),
        .\rd_mux_sel_r_reg[1]_32 (\rd_mux_sel_r_reg[1]_32 ),
        .\rd_mux_sel_r_reg[1]_33 (\rd_mux_sel_r_reg[1]_33 ),
        .\rd_mux_sel_r_reg[1]_34 (\rd_mux_sel_r_reg[1]_34 ),
        .\rd_mux_sel_r_reg[1]_35 (\rd_mux_sel_r_reg[1]_35 ),
        .\rd_mux_sel_r_reg[1]_36 (\rd_mux_sel_r_reg[1]_36 ),
        .\rd_mux_sel_r_reg[1]_37 (\rd_mux_sel_r_reg[1]_37 ),
        .\rd_mux_sel_r_reg[1]_38 (\rd_mux_sel_r_reg[1]_38 ),
        .\rd_mux_sel_r_reg[1]_39 (\rd_mux_sel_r_reg[1]_39 ),
        .\rd_mux_sel_r_reg[1]_4 (\rd_mux_sel_r_reg[1]_4 ),
        .\rd_mux_sel_r_reg[1]_40 (\rd_mux_sel_r_reg[1]_40 ),
        .\rd_mux_sel_r_reg[1]_41 (\rd_mux_sel_r_reg[1]_41 ),
        .\rd_mux_sel_r_reg[1]_42 (\rd_mux_sel_r_reg[1]_42 ),
        .\rd_mux_sel_r_reg[1]_43 (\rd_mux_sel_r_reg[1]_43 ),
        .\rd_mux_sel_r_reg[1]_44 (\rd_mux_sel_r_reg[1]_44 ),
        .\rd_mux_sel_r_reg[1]_45 (\rd_mux_sel_r_reg[1]_45 ),
        .\rd_mux_sel_r_reg[1]_46 (\rd_mux_sel_r_reg[1]_46 ),
        .\rd_mux_sel_r_reg[1]_47 (\rd_mux_sel_r_reg[1]_47 ),
        .\rd_mux_sel_r_reg[1]_48 (\rd_mux_sel_r_reg[1]_48 ),
        .\rd_mux_sel_r_reg[1]_49 (\rd_mux_sel_r_reg[1]_49 ),
        .\rd_mux_sel_r_reg[1]_5 (\rd_mux_sel_r_reg[1]_5 ),
        .\rd_mux_sel_r_reg[1]_50 (\rd_mux_sel_r_reg[1]_50 ),
        .\rd_mux_sel_r_reg[1]_51 (\rd_mux_sel_r_reg[1]_51 ),
        .\rd_mux_sel_r_reg[1]_52 (\rd_mux_sel_r_reg[1]_52 ),
        .\rd_mux_sel_r_reg[1]_53 (\rd_mux_sel_r_reg[1]_53 ),
        .\rd_mux_sel_r_reg[1]_54 (\rd_mux_sel_r_reg[1]_54 ),
        .\rd_mux_sel_r_reg[1]_55 (\rd_mux_sel_r_reg[1]_55 ),
        .\rd_mux_sel_r_reg[1]_56 (\rd_mux_sel_r_reg[1]_56 ),
        .\rd_mux_sel_r_reg[1]_57 (\rd_mux_sel_r_reg[1]_57 ),
        .\rd_mux_sel_r_reg[1]_58 (\rd_mux_sel_r_reg[1]_58 ),
        .\rd_mux_sel_r_reg[1]_59 (\rd_mux_sel_r_reg[1]_59 ),
        .\rd_mux_sel_r_reg[1]_6 (\rd_mux_sel_r_reg[1]_6 ),
        .\rd_mux_sel_r_reg[1]_60 (\rd_mux_sel_r_reg[1]_60 ),
        .\rd_mux_sel_r_reg[1]_61 (\rd_mux_sel_r_reg[1]_61 ),
        .\rd_mux_sel_r_reg[1]_62 (\rd_mux_sel_r_reg[1]_62 ),
        .\rd_mux_sel_r_reg[1]_7 (\rd_mux_sel_r_reg[1]_7 ),
        .\rd_mux_sel_r_reg[1]_8 (\rd_mux_sel_r_reg[1]_8 ),
        .\rd_mux_sel_r_reg[1]_9 (\rd_mux_sel_r_reg[1]_9 ),
        .\rd_ptr_reg[1]_0 (\entry_cnt_reg[4] ),
        .\wr_ptr[1]_i_2__2 (\wr_ptr[1]_i_2__2 ));
  FDSE #(
    .INIT(1'b1)) 
    ififo_rst_reg
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(ififo_rst_reg_0),
        .Q(ififo_rst),
        .S(phy_if_reset));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IN_FIFO #(
    .ALMOST_EMPTY_VALUE(1),
    .ALMOST_FULL_VALUE(1),
    .ARRAY_MODE("ARRAY_MODE_4_X_8"),
    .SYNCHRONOUS_MODE("FALSE")) 
    \in_fifo_gen.in_fifo 
       (.ALMOSTEMPTY(\in_fifo_gen.in_fifo_n_0 ),
        .ALMOSTFULL(\in_fifo_gen.in_fifo_n_1 ),
        .D0({1'b0,1'b0,1'b0,1'b0}),
        .D1({1'b0,1'b0,1'b0,1'b0}),
        .D2(if_d2),
        .D3(if_d3),
        .D4(if_d4),
        .D5({\NLW_in_fifo_gen.in_fifo_D5_UNCONNECTED [7:4],if_d5}),
        .D6({\NLW_in_fifo_gen.in_fifo_D6_UNCONNECTED [7:4],if_d6}),
        .D7(if_d7),
        .D8(if_d8),
        .D9(if_d9),
        .EMPTY(if_empty_),
        .FULL(\in_fifo_gen.in_fifo_n_3 ),
        .Q0(rd_data[7:0]),
        .Q1(rd_data[15:8]),
        .Q2(rd_data[23:16]),
        .Q3(rd_data[31:24]),
        .Q4(rd_data[39:32]),
        .Q5(rd_data[47:40]),
        .Q6(rd_data[55:48]),
        .Q7(rd_data[63:56]),
        .Q8(rd_data[71:64]),
        .Q9(rd_data[79:72]),
        .RDCLK(\entry_cnt_reg[4] ),
        .RDEN(1'b1),
        .RESET(ififo_rst),
        .WRCLK(iserdes_clkdiv),
        .WREN(ififo_wr_enable));
  mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_31 \of_pre_fifo_gen.u_ddr_of_pre_fifo 
       (.D0({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 }),
        .D1(of_d1),
        .Q(Q),
        .\entry_cnt_reg[4]_0 (\entry_cnt_reg[4] ),
        .\my_empty_reg[1]_0 (\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ),
        .\my_empty_reg[1]_1 (\my_empty_reg[1] ),
        .\my_empty_reg[7]_0 (out_fifo_n_3),
        .ofifo_rst(ofifo_rst),
        .out_fifo(out_fifo_0),
        .out_fifo_0(out_fifo_1),
        .out_fifo_1(out_fifo_2),
        .out_fifo_i_75__7(out_fifo_i_75__7),
        .phy_data_wr_en(phy_data_wr_en),
        .\rd_ptr_reg[3]_0 (\rd_ptr_reg[3] ));
  FDSE #(
    .INIT(1'b1)) 
    ofifo_rst_reg
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(ififo_rst_reg_0),
        .Q(ofifo_rst),
        .S(A_rst_primitives));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OUT_FIFO #(
    .ALMOST_EMPTY_VALUE(1),
    .ALMOST_FULL_VALUE(1),
    .ARRAY_MODE("ARRAY_MODE_8_X_4"),
    .OUTPUT_DISABLE("FALSE"),
    .SYNCHRONOUS_MODE("FALSE")) 
    out_fifo
       (.ALMOSTEMPTY(out_fifo_n_0),
        .ALMOSTFULL(out_fifo_n_1),
        .D0({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 }),
        .D1(of_d1),
        .D2(\my_empty_reg[7] ),
        .D3(\my_empty_reg[7]_0 ),
        .D4(\my_empty_reg[7]_1 ),
        .D5(\my_empty_reg[7]_2 ),
        .D6(\my_empty_reg[7]_3 ),
        .D7(\my_empty_reg[7]_4 ),
        .D8(\my_empty_reg[7]_5 ),
        .D9(\my_empty_reg[7]_6 ),
        .EMPTY(out_fifo_n_2),
        .FULL(out_fifo_n_3),
        .Q0(of_dqbus[3:0]),
        .Q1(of_dqbus[7:4]),
        .Q2(of_dqbus[11:8]),
        .Q3(of_dqbus[15:12]),
        .Q4(of_dqbus[19:16]),
        .Q5({NLW_out_fifo_Q5_UNCONNECTED[7:4],of_dqbus[23:20]}),
        .Q6({NLW_out_fifo_Q6_UNCONNECTED[7:4],of_dqbus[27:24]}),
        .Q7(of_dqbus[31:28]),
        .Q8(of_dqbus[35:32]),
        .Q9(of_dqbus[39:36]),
        .RDCLK(oserdes_clkdiv),
        .RDEN(po_rd_enable),
        .RESET(ofifo_rst),
        .WRCLK(\entry_cnt_reg[4] ),
        .WREN(\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  PHASER_IN_PHY #(
    .BURST_MODE("TRUE"),
    .CLKOUT_DIV(2),
    .DQS_AUTO_RECAL(1'b1),
    .DQS_BIAS_MODE("FALSE"),
    .DQS_FIND_PATTERN(3'b000),
    .FINE_DELAY(33),
    .FREQ_REF_DIV("DIV2"),
    .IS_RST_INVERTED(1'b0),
    .MEMREFCLK_PERIOD(2.500000),
    .OUTPUT_CLK_SRC("DELAYED_REF"),
    .PHASEREFCLK_PERIOD(2.500000),
    .REFCLK_PERIOD(1.250000),
    .SEL_CLK_OFFSET(6),
    .SYNC_IN_DIV_RST("TRUE"),
    .WR_CYCLES("FALSE")) 
    \phaser_in_gen.phaser_in 
       (.BURSTPENDINGPHY(phaser_ctl_bus[1]),
        .COUNTERLOADEN(\pi_dqs_found_lanes_r1_reg[3] ),
        .COUNTERLOADVAL(\pi_dqs_found_lanes_r1_reg[3]_3 ),
        .COUNTERREADEN(\pi_dqs_found_lanes_r1_reg[3]_0 ),
        .COUNTERREADVAL(A_rst_primitives_reg_1),
        .DQSFOUND(in0),
        .DQSOUTOFRANGE(\phaser_in_gen.phaser_in_n_1 ),
        .ENCALIBPHY(PCENABLECALIB),
        .FINEENABLE(\pi_dqs_found_lanes_r1_reg[3]_1 ),
        .FINEINC(\pi_dqs_found_lanes_r1_reg[3]_2 ),
        .FINEOVERFLOW(\phaser_in_gen.phaser_in_n_2 ),
        .FREQREFCLK(freq_refclk),
        .ICLK(A_rst_primitives_reg),
        .ICLKDIV(iserdes_clkdiv),
        .ISERDESRST(\phaser_in_gen.phaser_in_n_5 ),
        .MEMREFCLK(mem_refclk),
        .PHASELOCKED(A_rst_primitives_reg_0),
        .PHASEREFCLK(mem_dqs_in),
        .RANKSELPHY(phaser_ctl_bus[3:2]),
        .RCLK(\phaser_in_gen.phaser_in_n_7 ),
        .RST(A_rst_primitives),
        .RSTDQSFIND(ififo_rst_reg_0),
        .SYNCIN(sync_pulse),
        .SYSCLK(\entry_cnt_reg[4] ),
        .WRENABLE(ififo_wr_enable));
  (* BOX_TYPE = "PRIMITIVE" *) 
  PHASER_OUT_PHY #(
    .CLKOUT_DIV(2),
    .COARSE_BYPASS("FALSE"),
    .COARSE_DELAY(0),
    .DATA_CTL_N("TRUE"),
    .DATA_RD_CYCLES("FALSE"),
    .FINE_DELAY(60),
    .IS_RST_INVERTED(1'b0),
    .MEMREFCLK_PERIOD(2.500000),
    .OCLKDELAY_INV("FALSE"),
    .OCLK_DELAY(0),
    .OUTPUT_CLK_SRC("DELAYED_REF"),
    .PHASEREFCLK_PERIOD(1.000000),
    .PO(3'b111),
    .REFCLK_PERIOD(1.250000),
    .SYNC_IN_DIV_RST("TRUE")) 
    phaser_out
       (.BURSTPENDINGPHY(phaser_ctl_bus[0]),
        .COARSEENABLE(\po_counter_read_val_reg[8] ),
        .COARSEINC(\po_counter_read_val_reg[8] ),
        .COARSEOVERFLOW(phaser_out_n_0),
        .COUNTERLOADEN(1'b0),
        .COUNTERLOADVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .COUNTERREADEN(\pi_dqs_found_lanes_r1_reg[3]_0 ),
        .COUNTERREADVAL(A_rst_primitives_reg_2),
        .CTSBUS(oserdes_dqs_ts),
        .DQSBUS(oserdes_dqs),
        .DTSBUS(oserdes_dq_ts),
        .ENCALIBPHY(PCENABLECALIB),
        .FINEENABLE(\po_counter_read_val_reg[8]_0 ),
        .FINEINC(\po_counter_read_val_reg[8]_1 ),
        .FINEOVERFLOW(phaser_out_n_1),
        .FREQREFCLK(freq_refclk),
        .MEMREFCLK(mem_refclk),
        .OCLK(oserdes_clk),
        .OCLKDELAYED(oserdes_clk_delayed),
        .OCLKDIV(oserdes_clkdiv),
        .OSERDESRST(po_oserdes_rst),
        .PHASEREFCLK(NLW_phaser_out_PHASEREFCLK_UNCONNECTED),
        .RDENABLE(po_rd_enable),
        .RST(A_rst_primitives),
        .SELFINEOCLKDELAY(1'b0),
        .SYNCIN(sync_pulse),
        .SYSCLK(\entry_cnt_reg[4] ));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_byte_lane" *) 
module mig_mig_7series_v4_2_ddr_byte_lane__parameterized3
   (SR,
    \my_empty_reg[1] ,
    of_ctl_full_v,
    mem_out,
    mem_dq_out,
    D,
    OUTBURSTPENDING,
    \po_counter_read_val_reg[8] ,
    \po_counter_read_val_reg[8]_0 ,
    \po_counter_read_val_reg[8]_1 ,
    \po_counter_read_val_reg[8]_2 ,
    freq_refclk,
    mem_refclk,
    B_rst_primitives,
    sync_pulse,
    \my_full_reg[3] ,
    PCENABLECALIB,
    \my_full_reg[3]_0 ,
    \my_full_reg[3]_1 ,
    \my_full_reg[3]_2 ,
    \my_full_reg[3]_3 ,
    \my_full_reg[3]_4 ,
    phy_cmd_wr_en,
    mc_we_n,
    out_fifo_0,
    mc_ras_n,
    mc_cs_n,
    mc_cas_n,
    C_of_full,
    D_of_full,
    out_fifo_i_47__8,
    COUNTERREADVAL,
    calib_sel,
    \po_counter_read_val_reg[8]_3 );
  output [0:0]SR;
  output \my_empty_reg[1] ;
  output [0:0]of_ctl_full_v;
  output [11:0]mem_out;
  output [5:0]mem_dq_out;
  output [8:0]D;
  input [0:0]OUTBURSTPENDING;
  input \po_counter_read_val_reg[8] ;
  input \po_counter_read_val_reg[8]_0 ;
  input \po_counter_read_val_reg[8]_1 ;
  input \po_counter_read_val_reg[8]_2 ;
  input freq_refclk;
  input mem_refclk;
  input B_rst_primitives;
  input sync_pulse;
  input \my_full_reg[3] ;
  input [1:0]PCENABLECALIB;
  input [3:0]\my_full_reg[3]_0 ;
  input [0:0]\my_full_reg[3]_1 ;
  input [1:0]\my_full_reg[3]_2 ;
  input [0:0]\my_full_reg[3]_3 ;
  input [3:0]\my_full_reg[3]_4 ;
  input phy_cmd_wr_en;
  input [1:0]mc_we_n;
  input out_fifo_0;
  input [1:0]mc_ras_n;
  input [0:0]mc_cs_n;
  input [1:0]mc_cas_n;
  input C_of_full;
  input D_of_full;
  input [12:0]out_fifo_i_47__8;
  input [8:0]COUNTERREADVAL;
  input [1:0]calib_sel;
  input [8:0]\po_counter_read_val_reg[8]_3 ;

  wire B_of_a_full;
  wire B_of_full;
  wire B_po_coarse_overflow;
  wire [8:0]B_po_counter_read_val;
  wire B_po_fine_overflow;
  wire B_rst_primitives;
  wire [8:0]COUNTERREADVAL;
  wire C_of_full;
  wire [8:0]D;
  wire D_of_full;
  wire [0:0]OUTBURSTPENDING;
  wire [1:0]PCENABLECALIB;
  wire [0:0]SR;
  wire [1:0]calib_sel;
  wire freq_refclk;
  wire [1:0]mc_cas_n;
  wire [0:0]mc_cs_n;
  wire [1:0]mc_ras_n;
  wire [1:0]mc_we_n;
  wire [5:0]mem_dq_out;
  wire [11:0]mem_out;
  wire mem_refclk;
  wire \my_empty_reg[1] ;
  wire \my_full_reg[3] ;
  wire [3:0]\my_full_reg[3]_0 ;
  wire [0:0]\my_full_reg[3]_1 ;
  wire [1:0]\my_full_reg[3]_2 ;
  wire [0:0]\my_full_reg[3]_3 ;
  wire [3:0]\my_full_reg[3]_4 ;
  wire [0:0]of_ctl_full_v;
  wire [2:0]of_d4;
  wire [6:0]of_d5;
  wire [6:4]of_d6;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_1 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_26 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_27 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_28 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_29 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_30 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_31 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_32 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_33 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_34 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_35 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_36 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_37 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ;
  wire [3:0]of_q0;
  wire [3:0]of_q1;
  wire [3:0]of_q2;
  wire [3:0]of_q3;
  wire [3:0]of_q4;
  wire [7:0]of_q5;
  wire [7:0]of_q6;
  wire [3:0]of_q7;
  wire [3:0]of_q8;
  wire [3:0]of_q9;
  wire oserdes_clk;
  wire oserdes_clk_delayed;
  wire oserdes_clkdiv;
  wire [1:0]oserdes_dq_ts;
  wire [1:0]oserdes_dqs;
  wire [1:0]oserdes_dqs_ts;
  wire out_fifo_0;
  wire [12:0]out_fifo_i_47__8;
  wire out_fifo_n_0;
  wire out_fifo_n_2;
  wire phy_cmd_wr_en;
  wire \po_counter_read_val_reg[8] ;
  wire \po_counter_read_val_reg[8]_0 ;
  wire \po_counter_read_val_reg[8]_1 ;
  wire \po_counter_read_val_reg[8]_2 ;
  wire [8:0]\po_counter_read_val_reg[8]_3 ;
  wire po_oserdes_rst;
  wire po_rd_enable;
  wire sync_pulse;
  wire NLW_phaser_out_PHASEREFCLK_UNCONNECTED;

  mig_mig_7series_v4_2_ddr_byte_group_io__parameterized1 ddr_byte_group_io
       (.mem_dq_out(mem_dq_out),
        .oserdes_clk(oserdes_clk),
        .oserdes_clkdiv(oserdes_clkdiv),
        .oserdes_dq({of_q6[7:4],of_q5[7:4],of_q7,of_q5[3:0],of_q4,of_q2}),
        .po_oserdes_rst(po_oserdes_rst));
  mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_24 \of_pre_fifo_gen.u_ddr_of_pre_fifo 
       (.B_of_full(B_of_full),
        .D1({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_30 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_31 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_32 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_33 }),
        .D2({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_34 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_35 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_36 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_37 }),
        .D3({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_26 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_27 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_28 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_29 }),
        .D4({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,of_d4[2],of_d4[0]}),
        .D5({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ,of_d5[6],of_d5[4],\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,of_d5[2],of_d5[0]}),
        .D6({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15 ,of_d6[6],of_d6[4],\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21 }),
        .SR(SR),
        .mc_cas_n(mc_cas_n),
        .mc_cs_n(mc_cs_n),
        .mc_ras_n(mc_ras_n),
        .mc_we_n(mc_we_n),
        .mem_out(mem_out),
        .\my_empty_reg[1]_0 (\my_empty_reg[1] ),
        .\my_empty_reg[1]_1 (\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_1 ),
        .\my_full_reg[3]_0 (\my_full_reg[3] ),
        .out_fifo(out_fifo_0),
        .out_fifo_i_47__8(out_fifo_i_47__8),
        .phy_cmd_wr_en(phy_cmd_wr_en));
  FDRE #(
    .INIT(1'b1)) 
    ofifo_rst_reg
       (.C(\my_full_reg[3] ),
        .CE(1'b1),
        .D(B_rst_primitives),
        .Q(SR),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OUT_FIFO #(
    .ALMOST_EMPTY_VALUE(1),
    .ALMOST_FULL_VALUE(1),
    .ARRAY_MODE("ARRAY_MODE_4_X_4"),
    .OUTPUT_DISABLE("FALSE"),
    .SYNCHRONOUS_MODE("FALSE")) 
    out_fifo
       (.ALMOSTEMPTY(out_fifo_n_0),
        .ALMOSTFULL(B_of_a_full),
        .D0({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_28 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_29 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_26 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_27 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_28 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_29 }),
        .D1({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_30 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_31 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_32 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_33 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_26 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_27 }),
        .D2({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_34 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_35 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_36 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_37 ,\my_full_reg[3]_0 }),
        .D3({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_26 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_27 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_28 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_29 }),
        .D4({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,of_d4[2],\my_full_reg[3]_1 ,of_d4[0]}),
        .D5({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ,of_d5[6],\my_full_reg[3]_2 [1],of_d5[4],\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,of_d5[2],\my_full_reg[3]_2 [0],of_d5[0]}),
        .D6({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15 ,of_d6[6],\my_full_reg[3]_3 ,of_d6[4],\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21 }),
        .D7({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_26 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_27 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_28 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_29 ,\my_full_reg[3]_4 }),
        .D8({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_26 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_27 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_28 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_29 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25 }),
        .D9({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_28 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_29 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_26 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_27 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_28 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_29 }),
        .EMPTY(out_fifo_n_2),
        .FULL(B_of_full),
        .Q0(of_q0),
        .Q1(of_q1),
        .Q2(of_q2),
        .Q3(of_q3),
        .Q4(of_q4),
        .Q5(of_q5),
        .Q6(of_q6),
        .Q7(of_q7),
        .Q8(of_q8),
        .Q9(of_q9),
        .RDCLK(oserdes_clkdiv),
        .RDEN(po_rd_enable),
        .RESET(SR),
        .WRCLK(\my_full_reg[3] ),
        .WREN(\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_1 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  PHASER_OUT_PHY #(
    .CLKOUT_DIV(4),
    .COARSE_BYPASS("FALSE"),
    .COARSE_DELAY(0),
    .DATA_CTL_N("FALSE"),
    .DATA_RD_CYCLES("FALSE"),
    .FINE_DELAY(60),
    .IS_RST_INVERTED(1'b0),
    .MEMREFCLK_PERIOD(2.500000),
    .OCLKDELAY_INV("FALSE"),
    .OCLK_DELAY(0),
    .OUTPUT_CLK_SRC("DELAYED_REF"),
    .PHASEREFCLK_PERIOD(1.000000),
    .PO(3'b111),
    .REFCLK_PERIOD(1.250000),
    .SYNC_IN_DIV_RST("TRUE")) 
    phaser_out
       (.BURSTPENDINGPHY(OUTBURSTPENDING),
        .COARSEENABLE(\po_counter_read_val_reg[8] ),
        .COARSEINC(\po_counter_read_val_reg[8] ),
        .COARSEOVERFLOW(B_po_coarse_overflow),
        .COUNTERLOADEN(1'b0),
        .COUNTERLOADVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .COUNTERREADEN(\po_counter_read_val_reg[8]_0 ),
        .COUNTERREADVAL(B_po_counter_read_val),
        .CTSBUS(oserdes_dqs_ts),
        .DQSBUS(oserdes_dqs),
        .DTSBUS(oserdes_dq_ts),
        .ENCALIBPHY(PCENABLECALIB),
        .FINEENABLE(\po_counter_read_val_reg[8]_1 ),
        .FINEINC(\po_counter_read_val_reg[8]_2 ),
        .FINEOVERFLOW(B_po_fine_overflow),
        .FREQREFCLK(freq_refclk),
        .MEMREFCLK(mem_refclk),
        .OCLK(oserdes_clk),
        .OCLKDELAYED(oserdes_clk_delayed),
        .OCLKDIV(oserdes_clkdiv),
        .OSERDESRST(po_oserdes_rst),
        .PHASEREFCLK(NLW_phaser_out_PHASEREFCLK_UNCONNECTED),
        .RDENABLE(po_rd_enable),
        .RST(B_rst_primitives),
        .SELFINEOCLKDELAY(1'b0),
        .SYNCIN(sync_pulse),
        .SYSCLK(\my_full_reg[3] ));
  LUT3 #(
    .INIT(8'hFE)) 
    phy_mc_cmd_full_r_i_1
       (.I0(B_of_full),
        .I1(C_of_full),
        .I2(D_of_full),
        .O(of_ctl_full_v));
  LUT5 #(
    .INIT(32'hCAF0CA00)) 
    \po_counter_read_val[0]_i_1__1 
       (.I0(B_po_counter_read_val[0]),
        .I1(COUNTERREADVAL[0]),
        .I2(calib_sel[1]),
        .I3(calib_sel[0]),
        .I4(\po_counter_read_val_reg[8]_3 [0]),
        .O(D[0]));
  LUT5 #(
    .INIT(32'hCAF0CA00)) 
    \po_counter_read_val[1]_i_1__1 
       (.I0(B_po_counter_read_val[1]),
        .I1(COUNTERREADVAL[1]),
        .I2(calib_sel[1]),
        .I3(calib_sel[0]),
        .I4(\po_counter_read_val_reg[8]_3 [1]),
        .O(D[1]));
  LUT5 #(
    .INIT(32'hCAF0CA00)) 
    \po_counter_read_val[2]_i_1__1 
       (.I0(B_po_counter_read_val[2]),
        .I1(COUNTERREADVAL[2]),
        .I2(calib_sel[1]),
        .I3(calib_sel[0]),
        .I4(\po_counter_read_val_reg[8]_3 [2]),
        .O(D[2]));
  LUT5 #(
    .INIT(32'hCAF0CA00)) 
    \po_counter_read_val[3]_i_1__1 
       (.I0(B_po_counter_read_val[3]),
        .I1(COUNTERREADVAL[3]),
        .I2(calib_sel[1]),
        .I3(calib_sel[0]),
        .I4(\po_counter_read_val_reg[8]_3 [3]),
        .O(D[3]));
  LUT5 #(
    .INIT(32'hCAF0CA00)) 
    \po_counter_read_val[4]_i_1__1 
       (.I0(B_po_counter_read_val[4]),
        .I1(COUNTERREADVAL[4]),
        .I2(calib_sel[1]),
        .I3(calib_sel[0]),
        .I4(\po_counter_read_val_reg[8]_3 [4]),
        .O(D[4]));
  LUT5 #(
    .INIT(32'hCAF0CA00)) 
    \po_counter_read_val[5]_i_1__1 
       (.I0(B_po_counter_read_val[5]),
        .I1(COUNTERREADVAL[5]),
        .I2(calib_sel[1]),
        .I3(calib_sel[0]),
        .I4(\po_counter_read_val_reg[8]_3 [5]),
        .O(D[5]));
  LUT5 #(
    .INIT(32'hCAF0CA00)) 
    \po_counter_read_val[6]_i_1__1 
       (.I0(B_po_counter_read_val[6]),
        .I1(COUNTERREADVAL[6]),
        .I2(calib_sel[1]),
        .I3(calib_sel[0]),
        .I4(\po_counter_read_val_reg[8]_3 [6]),
        .O(D[6]));
  LUT5 #(
    .INIT(32'hCAF0CA00)) 
    \po_counter_read_val[7]_i_1__1 
       (.I0(B_po_counter_read_val[7]),
        .I1(COUNTERREADVAL[7]),
        .I2(calib_sel[1]),
        .I3(calib_sel[0]),
        .I4(\po_counter_read_val_reg[8]_3 [7]),
        .O(D[7]));
  LUT5 #(
    .INIT(32'hCAF0CA00)) 
    \po_counter_read_val[8]_i_2 
       (.I0(B_po_counter_read_val[8]),
        .I1(COUNTERREADVAL[8]),
        .I2(calib_sel[1]),
        .I3(calib_sel[0]),
        .I4(\po_counter_read_val_reg[8]_3 [8]),
        .O(D[8]));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_byte_lane" *) 
module mig_mig_7series_v4_2_ddr_byte_lane__parameterized4
   (ddr_ck_out,
    mem_dq_out,
    B_rst_primitives_reg,
    C_of_full,
    \my_empty_reg[1] ,
    \rd_ptr_reg[3] ,
    SR,
    \wr_ptr_timing_reg[3] ,
    OUTBURSTPENDING,
    C_po_coarse_enable26_out,
    C_po_counter_read_en38_out,
    C_po_fine_enable23_out,
    C_po_fine_inc29_out,
    freq_refclk,
    mem_refclk,
    B_rst_primitives,
    sync_pulse,
    PCENABLECALIB,
    \my_empty_reg[7] ,
    \my_empty_reg[7]_0 ,
    \my_empty_reg[7]_1 ,
    \my_empty_reg[7]_2 ,
    D9,
    phy_cmd_wr_en,
    phy_dout);
  output [1:0]ddr_ck_out;
  output [5:0]mem_dq_out;
  output [8:0]B_rst_primitives_reg;
  output C_of_full;
  output \my_empty_reg[1] ;
  output [23:0]\rd_ptr_reg[3] ;
  input [0:0]SR;
  input \wr_ptr_timing_reg[3] ;
  input [0:0]OUTBURSTPENDING;
  input C_po_coarse_enable26_out;
  input C_po_counter_read_en38_out;
  input C_po_fine_enable23_out;
  input C_po_fine_inc29_out;
  input freq_refclk;
  input mem_refclk;
  input B_rst_primitives;
  input sync_pulse;
  input [1:0]PCENABLECALIB;
  input [3:0]\my_empty_reg[7] ;
  input [7:0]\my_empty_reg[7]_0 ;
  input [3:0]\my_empty_reg[7]_1 ;
  input [3:0]\my_empty_reg[7]_2 ;
  input [3:0]D9;
  input phy_cmd_wr_en;
  input [23:0]phy_dout;

  wire B_rst_primitives;
  wire [8:0]B_rst_primitives_reg;
  wire C_of_full;
  wire C_po_coarse_enable26_out;
  wire C_po_counter_read_en38_out;
  wire C_po_fine_enable23_out;
  wire C_po_fine_inc29_out;
  wire [3:0]D9;
  wire [0:0]OUTBURSTPENDING;
  wire [1:0]PCENABLECALIB;
  wire [0:0]SR;
  wire [1:0]ddr_ck_out;
  wire [0:0]ddr_ck_out_q;
  wire freq_refclk;
  wire [5:0]mem_dq_out;
  wire mem_refclk;
  wire \my_empty_reg[1] ;
  wire [3:0]\my_empty_reg[7] ;
  wire [7:0]\my_empty_reg[7]_0 ;
  wire [3:0]\my_empty_reg[7]_1 ;
  wire [3:0]\my_empty_reg[7]_2 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_26 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_27 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_28 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_29 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_30 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_31 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ;
  wire [3:0]of_q0;
  wire [3:0]of_q1;
  wire [3:0]of_q2;
  wire [3:0]of_q3;
  wire [3:0]of_q4;
  wire [7:0]of_q5;
  wire [7:0]of_q6;
  wire [3:0]of_q7;
  wire [3:0]of_q8;
  wire [3:0]of_q9;
  wire oserdes_clk;
  wire oserdes_clk_delayed;
  wire oserdes_clkdiv;
  wire [1:0]oserdes_dq_ts;
  wire [1:0]oserdes_dqs;
  wire [1:0]oserdes_dqs_ts;
  wire out_fifo_n_0;
  wire out_fifo_n_1;
  wire out_fifo_n_2;
  wire phaser_out_n_0;
  wire phaser_out_n_1;
  wire phy_cmd_wr_en;
  wire [23:0]phy_dout;
  wire po_oserdes_rst;
  wire po_rd_enable;
  wire [23:0]\rd_ptr_reg[3] ;
  wire sync_pulse;
  wire \wr_ptr_timing_reg[3] ;
  wire \NLW_ddr_ck_gen_loop[0].ddr_ck_gen.ddr_ck_S_UNCONNECTED ;
  wire NLW_phaser_out_PHASEREFCLK_UNCONNECTED;

  mig_mig_7series_v4_2_ddr_byte_group_io__parameterized2 ddr_byte_group_io
       (.mem_dq_out(mem_dq_out),
        .oserdes_clk(oserdes_clk),
        .oserdes_clkdiv(oserdes_clkdiv),
        .oserdes_dq({of_q6[7:4],of_q5[7:4],of_q9,of_q8,of_q5[3:0],of_q4}),
        .po_oserdes_rst(po_oserdes_rst));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* __SRVAL = "FALSE" *) 
  ODDR #(
    .DDR_CLK_EDGE("SAME_EDGE"),
    .INIT(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D1_INVERTED(1'b0),
    .IS_D2_INVERTED(1'b0),
    .SRTYPE("SYNC")) 
    \ddr_ck_gen_loop[0].ddr_ck_gen.ddr_ck 
       (.C(oserdes_clk),
        .CE(1'b1),
        .D1(1'b0),
        .D2(1'b1),
        .Q(ddr_ck_out_q),
        .R(1'b0),
        .S(\NLW_ddr_ck_gen_loop[0].ddr_ck_gen.ddr_ck_S_UNCONNECTED ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  (* XILINX_LEGACY_PRIM = "OBUFDS" *) 
  OBUFDS #(
    .IOSTANDARD("DEFAULT")) 
    \ddr_ck_gen_loop[0].ddr_ck_gen.ddr_ck_obuf 
       (.I(ddr_ck_out_q),
        .O(ddr_ck_out[0]),
        .OB(ddr_ck_out[1]));
  mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_23 \of_pre_fifo_gen.u_ddr_of_pre_fifo 
       (.D0({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 }),
        .D3({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 }),
        .D4({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 }),
        .D6({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 }),
        .D7({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25 }),
        .D8({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_26 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_27 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_28 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_29 }),
        .D9({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_30 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_31 }),
        .SR(SR),
        .\my_empty_reg[1]_0 (\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ),
        .\my_empty_reg[1]_1 (\my_empty_reg[1] ),
        .\my_empty_reg[7]_0 (C_of_full),
        .phy_cmd_wr_en(phy_cmd_wr_en),
        .phy_dout(phy_dout),
        .\rd_ptr_reg[3]_0 (\rd_ptr_reg[3] ),
        .\wr_ptr_timing_reg[3]_0 (\wr_ptr_timing_reg[3] ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OUT_FIFO #(
    .ALMOST_EMPTY_VALUE(1),
    .ALMOST_FULL_VALUE(1),
    .ARRAY_MODE("ARRAY_MODE_4_X_4"),
    .OUTPUT_DISABLE("FALSE"),
    .SYNCHRONOUS_MODE("FALSE")) 
    out_fifo
       (.ALMOSTEMPTY(out_fifo_n_0),
        .ALMOSTFULL(out_fifo_n_1),
        .D0({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 }),
        .D1({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 }),
        .D2({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 }),
        .D3({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 }),
        .D4({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,\my_empty_reg[7] }),
        .D5(\my_empty_reg[7]_0 ),
        .D6({\my_empty_reg[7]_1 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 }),
        .D7({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_18 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_19 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_20 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_21 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25 }),
        .D8({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_26 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_27 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_28 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_29 ,\my_empty_reg[7]_2 }),
        .D9({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_30 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_31 ,D9}),
        .EMPTY(out_fifo_n_2),
        .FULL(C_of_full),
        .Q0(of_q0),
        .Q1(of_q1),
        .Q2(of_q2),
        .Q3(of_q3),
        .Q4(of_q4),
        .Q5(of_q5),
        .Q6(of_q6),
        .Q7(of_q7),
        .Q8(of_q8),
        .Q9(of_q9),
        .RDCLK(oserdes_clkdiv),
        .RDEN(po_rd_enable),
        .RESET(SR),
        .WRCLK(\wr_ptr_timing_reg[3] ),
        .WREN(\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  PHASER_OUT_PHY #(
    .CLKOUT_DIV(4),
    .COARSE_BYPASS("FALSE"),
    .COARSE_DELAY(0),
    .DATA_CTL_N("FALSE"),
    .DATA_RD_CYCLES("FALSE"),
    .FINE_DELAY(60),
    .IS_RST_INVERTED(1'b0),
    .MEMREFCLK_PERIOD(2.500000),
    .OCLKDELAY_INV("FALSE"),
    .OCLK_DELAY(0),
    .OUTPUT_CLK_SRC("DELAYED_REF"),
    .PHASEREFCLK_PERIOD(1.000000),
    .PO(3'b111),
    .REFCLK_PERIOD(1.250000),
    .SYNC_IN_DIV_RST("TRUE")) 
    phaser_out
       (.BURSTPENDINGPHY(OUTBURSTPENDING),
        .COARSEENABLE(C_po_coarse_enable26_out),
        .COARSEINC(C_po_coarse_enable26_out),
        .COARSEOVERFLOW(phaser_out_n_0),
        .COUNTERLOADEN(1'b0),
        .COUNTERLOADVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .COUNTERREADEN(C_po_counter_read_en38_out),
        .COUNTERREADVAL(B_rst_primitives_reg),
        .CTSBUS(oserdes_dqs_ts),
        .DQSBUS(oserdes_dqs),
        .DTSBUS(oserdes_dq_ts),
        .ENCALIBPHY(PCENABLECALIB),
        .FINEENABLE(C_po_fine_enable23_out),
        .FINEINC(C_po_fine_inc29_out),
        .FINEOVERFLOW(phaser_out_n_1),
        .FREQREFCLK(freq_refclk),
        .MEMREFCLK(mem_refclk),
        .OCLK(oserdes_clk),
        .OCLKDELAYED(oserdes_clk_delayed),
        .OCLKDIV(oserdes_clkdiv),
        .OSERDESRST(po_oserdes_rst),
        .PHASEREFCLK(NLW_phaser_out_PHASEREFCLK_UNCONNECTED),
        .RDENABLE(po_rd_enable),
        .RST(B_rst_primitives),
        .SELFINEOCLKDELAY(1'b0),
        .SYNCIN(sync_pulse),
        .SYSCLK(\wr_ptr_timing_reg[3] ));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_byte_lane" *) 
module mig_mig_7series_v4_2_ddr_byte_lane__parameterized5
   (COUNTERREADVAL,
    D_of_full,
    \my_empty_reg[1] ,
    \rd_ptr_reg[3] ,
    mem_dq_out,
    OUTBURSTPENDING,
    \po_counter_read_val_reg[8] ,
    \po_counter_read_val_reg[8]_0 ,
    \po_counter_read_val_reg[8]_1 ,
    \po_counter_read_val_reg[8]_2 ,
    freq_refclk,
    mem_refclk,
    B_rst_primitives,
    sync_pulse,
    \wr_ptr_timing_reg[3] ,
    PCENABLECALIB,
    SR,
    D1,
    D3,
    D4,
    D5,
    D6,
    D7,
    D8,
    \rd_ptr_reg[3]_0 ,
    phy_cmd_wr_en,
    out_fifo_0,
    mc_cas_n,
    mc_address,
    out_fifo_1,
    d_in,
    out_fifo_2);
  output [8:0]COUNTERREADVAL;
  output D_of_full;
  output \my_empty_reg[1] ;
  output [35:0]\rd_ptr_reg[3] ;
  output [10:0]mem_dq_out;
  input [0:0]OUTBURSTPENDING;
  input \po_counter_read_val_reg[8] ;
  input \po_counter_read_val_reg[8]_0 ;
  input \po_counter_read_val_reg[8]_1 ;
  input \po_counter_read_val_reg[8]_2 ;
  input freq_refclk;
  input mem_refclk;
  input B_rst_primitives;
  input sync_pulse;
  input \wr_ptr_timing_reg[3] ;
  input [1:0]PCENABLECALIB;
  input [0:0]SR;
  input [3:0]D1;
  input [3:0]D3;
  input [3:0]D4;
  input [3:0]D5;
  input [7:0]D6;
  input [3:0]D7;
  input [3:0]D8;
  input [3:0]\rd_ptr_reg[3]_0 ;
  input phy_cmd_wr_en;
  input out_fifo_0;
  input [0:0]mc_cas_n;
  input [3:0]mc_address;
  input out_fifo_1;
  input [41:0]d_in;
  input out_fifo_2;

  wire B_rst_primitives;
  wire [8:0]COUNTERREADVAL;
  wire [3:0]D1;
  wire [3:0]D3;
  wire [3:0]D4;
  wire [3:0]D5;
  wire [7:0]D6;
  wire [3:0]D7;
  wire [3:0]D8;
  wire D_of_a_full;
  wire D_of_full;
  wire D_po_coarse_overflow;
  wire D_po_fine_overflow;
  wire [0:0]OUTBURSTPENDING;
  wire [1:0]PCENABLECALIB;
  wire [0:0]SR;
  wire [41:0]d_in;
  wire freq_refclk;
  wire [3:0]mc_address;
  wire [0:0]mc_cas_n;
  wire [10:0]mem_dq_out;
  wire mem_refclk;
  wire \my_empty_reg[1] ;
  wire [3:0]of_d2;
  wire [3:0]of_d5;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_1 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_26 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_27 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_28 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_29 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_30 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_31 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_32 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_33 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_34 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_35 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_36 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_37 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_38 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_39 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ;
  wire \of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ;
  wire [3:0]of_q0;
  wire [3:0]of_q1;
  wire [3:0]of_q2;
  wire [3:0]of_q3;
  wire [3:0]of_q4;
  wire [7:0]of_q5;
  wire [7:0]of_q6;
  wire [3:0]of_q7;
  wire [3:0]of_q8;
  wire [3:0]of_q9;
  wire oserdes_clk;
  wire oserdes_clk_delayed;
  wire oserdes_clkdiv;
  wire [1:0]oserdes_dq_ts;
  wire [1:0]oserdes_dqs;
  wire [1:0]oserdes_dqs_ts;
  wire out_fifo_0;
  wire out_fifo_1;
  wire out_fifo_2;
  wire out_fifo_n_0;
  wire out_fifo_n_2;
  wire phy_cmd_wr_en;
  wire \po_counter_read_val_reg[8] ;
  wire \po_counter_read_val_reg[8]_0 ;
  wire \po_counter_read_val_reg[8]_1 ;
  wire \po_counter_read_val_reg[8]_2 ;
  wire po_oserdes_rst;
  wire po_rd_enable;
  wire [35:0]\rd_ptr_reg[3] ;
  wire [3:0]\rd_ptr_reg[3]_0 ;
  wire sync_pulse;
  wire \wr_ptr_timing_reg[3] ;
  wire NLW_phaser_out_PHASEREFCLK_UNCONNECTED;

  mig_mig_7series_v4_2_ddr_byte_group_io__parameterized3 ddr_byte_group_io
       (.mem_dq_out(mem_dq_out),
        .oserdes_clk(oserdes_clk),
        .oserdes_clkdiv(oserdes_clkdiv),
        .oserdes_dq({of_q6[7:4],of_q5[7:4],of_q9,of_q8,of_q7,of_q6[3:0],of_q5[3:0],of_q4,of_q3,of_q2,of_q1}),
        .po_oserdes_rst(po_oserdes_rst));
  mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_22 \of_pre_fifo_gen.u_ddr_of_pre_fifo 
       (.D0({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 }),
        .D1({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 }),
        .D2({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,of_d2}),
        .D3({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25 }),
        .D4({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_26 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_27 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_28 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_29 }),
        .D5(of_d5),
        .D7({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_30 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_31 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_32 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_33 }),
        .D8({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_34 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_35 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_36 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_37 }),
        .D9({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_38 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_39 }),
        .SR(SR),
        .d_in(d_in),
        .mc_address(mc_address),
        .mc_cas_n(mc_cas_n),
        .\my_empty_reg[1]_0 (\my_empty_reg[1] ),
        .\my_empty_reg[1]_1 (\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_1 ),
        .out_fifo(out_fifo_0),
        .out_fifo_0(out_fifo_1),
        .out_fifo_1(out_fifo_2),
        .phy_cmd_wr_en(phy_cmd_wr_en),
        .\rd_ptr_reg[3]_0 (\rd_ptr_reg[3] ),
        .\rd_ptr_reg[3]_1 (D_of_full),
        .\wr_ptr_timing_reg[3]_0 (\wr_ptr_timing_reg[3] ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  OUT_FIFO #(
    .ALMOST_EMPTY_VALUE(1),
    .ALMOST_FULL_VALUE(1),
    .ARRAY_MODE("ARRAY_MODE_4_X_4"),
    .OUTPUT_DISABLE("FALSE"),
    .SYNCHRONOUS_MODE("FALSE")) 
    out_fifo
       (.ALMOSTEMPTY(out_fifo_n_0),
        .ALMOSTFULL(D_of_a_full),
        .D0({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_2 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_3 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_4 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_5 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_6 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_7 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 }),
        .D1({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_10 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_11 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_12 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_13 ,D1}),
        .D2({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_14 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_15 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_16 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_17 ,of_d2}),
        .D3({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_22 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_23 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_24 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_25 ,D3}),
        .D4({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_26 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_27 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_28 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_29 ,D4}),
        .D5({D5,of_d5}),
        .D6(D6),
        .D7({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_30 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_31 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_32 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_33 ,D7}),
        .D8({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_34 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_35 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_36 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_37 ,D8}),
        .D9({\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_8 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_9 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_38 ,\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_39 ,\rd_ptr_reg[3]_0 }),
        .EMPTY(out_fifo_n_2),
        .FULL(D_of_full),
        .Q0(of_q0),
        .Q1(of_q1),
        .Q2(of_q2),
        .Q3(of_q3),
        .Q4(of_q4),
        .Q5(of_q5),
        .Q6(of_q6),
        .Q7(of_q7),
        .Q8(of_q8),
        .Q9(of_q9),
        .RDCLK(oserdes_clkdiv),
        .RDEN(po_rd_enable),
        .RESET(SR),
        .WRCLK(\wr_ptr_timing_reg[3] ),
        .WREN(\of_pre_fifo_gen.u_ddr_of_pre_fifo_n_1 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  PHASER_OUT_PHY #(
    .CLKOUT_DIV(4),
    .COARSE_BYPASS("FALSE"),
    .COARSE_DELAY(0),
    .DATA_CTL_N("FALSE"),
    .DATA_RD_CYCLES("FALSE"),
    .FINE_DELAY(60),
    .IS_RST_INVERTED(1'b0),
    .MEMREFCLK_PERIOD(2.500000),
    .OCLKDELAY_INV("FALSE"),
    .OCLK_DELAY(0),
    .OUTPUT_CLK_SRC("DELAYED_REF"),
    .PHASEREFCLK_PERIOD(1.000000),
    .PO(3'b111),
    .REFCLK_PERIOD(1.250000),
    .SYNC_IN_DIV_RST("TRUE")) 
    phaser_out
       (.BURSTPENDINGPHY(OUTBURSTPENDING),
        .COARSEENABLE(\po_counter_read_val_reg[8] ),
        .COARSEINC(\po_counter_read_val_reg[8] ),
        .COARSEOVERFLOW(D_po_coarse_overflow),
        .COUNTERLOADEN(1'b0),
        .COUNTERLOADVAL({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .COUNTERREADEN(\po_counter_read_val_reg[8]_0 ),
        .COUNTERREADVAL(COUNTERREADVAL),
        .CTSBUS(oserdes_dqs_ts),
        .DQSBUS(oserdes_dqs),
        .DTSBUS(oserdes_dq_ts),
        .ENCALIBPHY(PCENABLECALIB),
        .FINEENABLE(\po_counter_read_val_reg[8]_1 ),
        .FINEINC(\po_counter_read_val_reg[8]_2 ),
        .FINEOVERFLOW(D_po_fine_overflow),
        .FREQREFCLK(freq_refclk),
        .MEMREFCLK(mem_refclk),
        .OCLK(oserdes_clk),
        .OCLKDELAYED(oserdes_clk_delayed),
        .OCLKDIV(oserdes_clkdiv),
        .OSERDESRST(po_oserdes_rst),
        .PHASEREFCLK(NLW_phaser_out_PHASEREFCLK_UNCONNECTED),
        .RDENABLE(po_rd_enable),
        .RST(B_rst_primitives),
        .SELFINEOCLKDELAY(1'b0),
        .SYNCIN(sync_pulse),
        .SYSCLK(\wr_ptr_timing_reg[3] ));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_calib_top" *) 
module mig_mig_7series_v4_2_ddr_calib_top
   (po_cnt_dec_reg,
    po_cnt_dec_2,
    fine_adjust_reg,
    new_cnt_cpt_r_reg,
    rdlvl_stg1_start_reg,
    samp_edge_cnt0_en_r,
    pi_counter_load_en,
    pi_cnt_dec_reg,
    E,
    prbs_rdlvl_done_pulse_reg,
    phy_write_calib,
    phy_read_calib,
    phy_if_reset,
    idelay_inc,
    d_in,
    init_calib_complete_reg_rep_0,
    init_calib_complete_reg_rep__0_0,
    init_calib_complete_reg_rep__11_0,
    init_calib_complete_reg_rep__12_0,
    init_calib_complete_reg_rep__24_0,
    init_calib_complete_reg_rep__25_0,
    init_calib_complete_reg_rep__26_0,
    pi_fine_enable,
    pi_fine_inc,
    \po_stg2_wrcal_cnt_reg[2] ,
    \rd_mux_sel_r_reg[2] ,
    \rd_mux_sel_r_reg[1] ,
    phy_dout,
    init_complete_r1_timing_reg,
    \write_buffer.wr_buf_out_data_reg[455] ,
    \write_buffer.wr_buf_out_data_reg[463] ,
    \write_buffer.wr_buf_out_data_reg[471] ,
    \write_buffer.wr_buf_out_data_reg[479] ,
    \write_buffer.wr_buf_out_data_reg[487] ,
    \write_buffer.wr_buf_out_data_reg[495] ,
    \write_buffer.wr_buf_out_data_reg[503] ,
    \write_buffer.wr_buf_out_data_reg[511] ,
    LD0,
    calib_sel,
    LD0_0,
    LD0_1,
    LD0_2,
    LD0_3,
    LD0_4,
    LD0_5,
    LD0_6,
    \calib_sel_reg[1]_0 ,
    \calib_sel_reg[1]_1 ,
    \calib_sel_reg[1]_2 ,
    \calib_sel_reg[1]_3 ,
    \calib_sel_reg[1]_4 ,
    \calib_sel_reg[1]_5 ,
    \calib_sel_reg[1]_6 ,
    \calib_sel_reg[1]_7 ,
    \calib_sel_reg[1]_8 ,
    dqs_wl_po_stg2_c_incdec_reg,
    \calib_sel_reg[1]_9 ,
    \calib_sel_reg[1]_10 ,
    \calib_sel_reg[1]_11 ,
    \calib_sel_reg[0]_0 ,
    \calib_sel_reg[1]_12 ,
    \calib_sel_reg[1]_13 ,
    \calib_sel_reg[1]_14 ,
    \calib_sel_reg[1]_15 ,
    \calib_sel_reg[1]_16 ,
    \calib_sel_reg[1]_17 ,
    \calib_sel_reg[1]_18 ,
    \calib_sel_reg[1]_19 ,
    \calib_sel_reg[1]_20 ,
    \calib_sel_reg[1]_21 ,
    \calib_sel_reg[1]_22 ,
    \calib_sel_reg[1]_23 ,
    idelay_ce_r2_reg_0,
    \calib_sel_reg[0]_1 ,
    \pi_rst_stg1_cal_reg[0] ,
    \calib_sel_reg[0]_2 ,
    \calib_sel_reg[0]_3 ,
    pi_stg2_load_reg,
    \calib_sel_reg[1]_24 ,
    \calib_sel_reg[1]_25 ,
    \calib_sel_reg[1]_26 ,
    \calib_sel_reg[1]_27 ,
    \calib_sel_reg[1]_28 ,
    \calib_sel_reg[1]_29 ,
    \calib_sel_reg[1]_30 ,
    \calib_sel_reg[1]_31 ,
    \calib_sel_reg[1]_32 ,
    dqs_wl_po_stg2_c_incdec_reg_0,
    \calib_sel_reg[1]_33 ,
    \calib_sel_reg[1]_34 ,
    \calib_sel_reg[1]_35 ,
    \calib_sel_reg[0]_4 ,
    \calib_sel_reg[1]_36 ,
    \calib_sel_reg[1]_37 ,
    \calib_sel_reg[1]_38 ,
    \calib_sel_reg[1]_39 ,
    \calib_sel_reg[1]_40 ,
    \calib_sel_reg[1]_41 ,
    \calib_sel_reg[1]_42 ,
    \calib_sel_reg[1]_43 ,
    \calib_sel_reg[1]_44 ,
    \calib_sel_reg[1]_45 ,
    \calib_sel_reg[1]_46 ,
    \calib_sel_reg[1]_47 ,
    idelay_ce_r2_reg_1,
    \calib_sel_reg[0]_5 ,
    \pi_rst_stg1_cal_reg[2] ,
    \calib_sel_reg[0]_6 ,
    \calib_sel_reg[0]_7 ,
    pi_stg2_load_reg_0,
    C_po_coarse_enable26_out,
    \gen_byte_sel_div2.calib_in_common_reg_0 ,
    \gen_byte_sel_div2.calib_in_common_reg_1 ,
    C_po_fine_enable23_out,
    \gen_byte_sel_div2.calib_in_common_reg_2 ,
    \gen_byte_sel_div2.calib_in_common_reg_3 ,
    \gen_byte_sel_div2.calib_in_common_reg_4 ,
    \gen_byte_sel_div2.calib_in_common_reg_5 ,
    C_po_counter_read_en38_out,
    dqs_po_stg2_f_incdec_reg,
    dqs_po_stg2_f_incdec_reg_0,
    dqs_po_stg2_f_incdec_reg_1,
    dqs_po_stg2_f_incdec_reg_2,
    dqs_po_stg2_f_incdec_reg_3,
    dqs_po_stg2_f_incdec_reg_4,
    dqs_po_stg2_f_incdec_reg_5,
    dqs_po_stg2_f_incdec_reg_6,
    C_po_fine_inc29_out,
    dqs_po_stg2_f_incdec_reg_7,
    dqs_po_stg2_f_incdec_reg_8,
    D6,
    D8,
    \gen_no_mirror.div_clk_loop[0].phy_address_reg[2] ,
    D5,
    D4,
    D7,
    D9,
    D1,
    \gen_no_mirror.div_clk_loop[0].phy_address_reg[8] ,
    \gen_no_mirror.div_clk_loop[0].phy_address_reg[9] ,
    D3,
    \gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] ,
    \gen_no_mirror.div_clk_loop[0].phy_bank_reg[1] ,
    \write_buffer.wr_buf_out_data_reg[448] ,
    D2,
    \write_buffer.wr_buf_out_data_reg[450] ,
    \write_buffer.wr_buf_out_data_reg[451] ,
    \write_buffer.wr_buf_out_data_reg[452] ,
    \write_buffer.wr_buf_out_data_reg[453] ,
    \write_buffer.wr_buf_out_data_reg[454] ,
    \write_buffer.wr_buf_out_data_reg[455]_0 ,
    \write_buffer.wr_buf_out_data_reg[456] ,
    \write_buffer.wr_buf_out_data_reg[457] ,
    \write_buffer.wr_buf_out_data_reg[458] ,
    \write_buffer.wr_buf_out_data_reg[459] ,
    \write_buffer.wr_buf_out_data_reg[460] ,
    \write_buffer.wr_buf_out_data_reg[461] ,
    \write_buffer.wr_buf_out_data_reg[462] ,
    \write_buffer.wr_buf_out_data_reg[463]_0 ,
    \write_buffer.wr_buf_out_data_reg[464] ,
    \write_buffer.wr_buf_out_data_reg[465] ,
    \write_buffer.wr_buf_out_data_reg[466] ,
    \write_buffer.wr_buf_out_data_reg[467] ,
    \write_buffer.wr_buf_out_data_reg[468] ,
    \write_buffer.wr_buf_out_data_reg[469] ,
    \write_buffer.wr_buf_out_data_reg[470] ,
    \write_buffer.wr_buf_out_data_reg[471]_0 ,
    \write_buffer.wr_buf_out_data_reg[472] ,
    \write_buffer.wr_buf_out_data_reg[473] ,
    \write_buffer.wr_buf_out_data_reg[474] ,
    \write_buffer.wr_buf_out_data_reg[475] ,
    \write_buffer.wr_buf_out_data_reg[476] ,
    \write_buffer.wr_buf_out_data_reg[477] ,
    \write_buffer.wr_buf_out_data_reg[478] ,
    \write_buffer.wr_buf_out_data_reg[479]_0 ,
    \write_buffer.wr_buf_out_data_reg[480] ,
    \write_buffer.wr_buf_out_data_reg[481] ,
    \write_buffer.wr_buf_out_data_reg[482] ,
    \write_buffer.wr_buf_out_data_reg[483] ,
    \write_buffer.wr_buf_out_data_reg[484] ,
    \write_buffer.wr_buf_out_data_reg[485] ,
    \write_buffer.wr_buf_out_data_reg[486] ,
    \write_buffer.wr_buf_out_data_reg[487]_0 ,
    \write_buffer.wr_buf_out_data_reg[488] ,
    \write_buffer.wr_buf_out_data_reg[489] ,
    \write_buffer.wr_buf_out_data_reg[490] ,
    \write_buffer.wr_buf_out_data_reg[491] ,
    \write_buffer.wr_buf_out_data_reg[492] ,
    \write_buffer.wr_buf_out_data_reg[493] ,
    \write_buffer.wr_buf_out_data_reg[494] ,
    \write_buffer.wr_buf_out_data_reg[495]_0 ,
    \write_buffer.wr_buf_out_data_reg[496] ,
    \write_buffer.wr_buf_out_data_reg[497] ,
    \write_buffer.wr_buf_out_data_reg[498] ,
    \write_buffer.wr_buf_out_data_reg[499] ,
    \write_buffer.wr_buf_out_data_reg[500] ,
    \write_buffer.wr_buf_out_data_reg[501] ,
    \write_buffer.wr_buf_out_data_reg[502] ,
    \write_buffer.wr_buf_out_data_reg[503]_0 ,
    \write_buffer.wr_buf_out_data_reg[504] ,
    \write_buffer.wr_buf_out_data_reg[505] ,
    \write_buffer.wr_buf_out_data_reg[506] ,
    \write_buffer.wr_buf_out_data_reg[507] ,
    \write_buffer.wr_buf_out_data_reg[508] ,
    \write_buffer.wr_buf_out_data_reg[509] ,
    \write_buffer.wr_buf_out_data_reg[510] ,
    \write_buffer.wr_buf_out_data_reg[511]_0 ,
    \cmd_pipe_plus.mc_ras_n_reg[1] ,
    \cmd_pipe_plus.mc_cas_n_reg[1] ,
    \cmd_pipe_plus.mc_odt_reg[0] ,
    \cmd_pipe_plus.mc_cke_reg[3] ,
    \cmd_pipe_plus.mc_we_n_reg[1] ,
    init_calib_complete_reg_rep__26_1,
    app_rd_data_valid,
    \read_fifo.tail_r_reg[0] ,
    \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0] ,
    \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] ,
    \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6] ,
    \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] ,
    \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][12] ,
    \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17] ,
    \init_state_r_reg[4] ,
    SR,
    pi_rst_dqs_find,
    pi_counter_load_val,
    \rd_mux_sel_r_reg[2]_0 ,
    D,
    COUNTERLOADVAL,
    \calib_sel_reg[1]_48 ,
    \calib_sel_reg[1]_49 ,
    \pi_stg2_reg_l_reg[5] ,
    \calib_sel_reg[1]_50 ,
    \calib_sel_reg[1]_51 ,
    \calib_sel_reg[1]_52 ,
    \pi_stg2_reg_l_reg[5]_0 ,
    \cmd_pipe_plus.mc_data_offset_1_reg[5] ,
    \cmd_pipe_plus.mc_data_offset_2_reg[5] ,
    phy_data_wr_en,
    phy_cmd_wr_en,
    mux_reset_n,
    \cmd_pipe_plus.mc_cke_reg[3]_0 ,
    Q,
    \dout_o_reg[15] ,
    \fine_dec_cnt_reg[5] ,
    \corse_inc_reg[6][2] ,
    \wl_dqs_tap_count_r_reg[0][5][5] ,
    po_en_stg2_f_reg,
    in0,
    first_fail_detect_reg,
    \rdlvl_dqs_tap_cnt_r_reg[0][0][2] ,
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ,
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ,
    \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_rise0_r_reg[5] ,
    \gen_mux_rd[6].mux_rd_rise0_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_rise0_r_reg[7] ,
    \gen_mux_rd[0].mux_rd_fall0_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1] ,
    \gen_mux_rd[2].mux_rd_fall0_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3] ,
    \gen_mux_rd[4].mux_rd_fall0_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5] ,
    \gen_mux_rd[6].mux_rd_fall0_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7] ,
    \gen_mux_rd[0].mux_rd_rise1_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1] ,
    \gen_mux_rd[2].mux_rd_rise1_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3] ,
    \gen_mux_rd[4].mux_rd_rise1_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5] ,
    \gen_mux_rd[6].mux_rd_rise1_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7] ,
    \gen_mux_rd[0].mux_rd_fall1_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1] ,
    \gen_mux_rd[2].mux_rd_fall1_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3] ,
    \gen_mux_rd[4].mux_rd_fall1_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5] ,
    \gen_mux_rd[6].mux_rd_fall1_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7] ,
    \gen_mux_rd[0].mux_rd_rise2_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1] ,
    \gen_mux_rd[2].mux_rd_rise2_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3] ,
    \gen_mux_rd[4].mux_rd_rise2_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5] ,
    \gen_mux_rd[6].mux_rd_rise2_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7] ,
    \gen_mux_rd[0].mux_rd_fall2_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1] ,
    \gen_mux_rd[2].mux_rd_fall2_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3] ,
    \gen_mux_rd[4].mux_rd_fall2_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5] ,
    \gen_mux_rd[6].mux_rd_fall2_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7] ,
    \gen_mux_rd[0].mux_rd_rise3_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1] ,
    \gen_mux_rd[2].mux_rd_rise3_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3] ,
    \gen_mux_rd[4].mux_rd_rise3_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5] ,
    \gen_mux_rd[6].mux_rd_rise3_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7] ,
    \gen_mux_rd[0].mux_rd_fall3_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1] ,
    \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3] ,
    \gen_mux_rd[4].mux_rd_fall3_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5] ,
    \gen_mux_rd[6].mux_rd_fall3_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7] ,
    \samp_edge_cnt1_r_reg[0] ,
    \FSM_onehot_cal1_state_r_reg[7] ,
    \samples_cnt_r_reg[0] ,
    \gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ,
    \gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ,
    \gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ,
    \gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ,
    \gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ,
    \gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ,
    \gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ,
    \gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ,
    \gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ,
    \gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ,
    \gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ,
    \gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ,
    \gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ,
    \gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ,
    \gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ,
    \gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ,
    \gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ,
    \gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ,
    \gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ,
    \gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ,
    \gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ,
    \gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ,
    \gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ,
    \gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ,
    \gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ,
    \gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ,
    \gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ,
    \gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ,
    \gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ,
    \gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ,
    \gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ,
    \gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ,
    \gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ,
    \gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ,
    \gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ,
    \gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ,
    \gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ,
    \gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ,
    \gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ,
    \gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ,
    \gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ,
    \gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ,
    \gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ,
    \gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ,
    \gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ,
    \gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ,
    \gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ,
    \gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ,
    \gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ,
    \gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ,
    \gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ,
    \gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ,
    \gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ,
    \gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ,
    \gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ,
    \gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ,
    \gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ,
    \gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ,
    \gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ,
    \gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ,
    \gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ,
    \gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ,
    \gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ,
    \gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ,
    \en_cnt_div4.enable_wrlvl_cnt_reg[2] ,
    pi_phase_locked_all_r1_reg,
    \victim_sel_reg[0] ,
    \four_dec_min_limit_reg[0] ,
    mc_ref_zq_wip,
    \one_dec_min_limit_reg[11] ,
    \one_dec_max_limit_reg[2] ,
    phy_rddata_en,
    if_empty,
    p_0_out,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ,
    cal2_if_reset_reg,
    \idelay_tap_cnt_r_reg[0][0][4] ,
    \not_empty_wait_cnt_reg[4] ,
    \complex_num_writes_reg[1] ,
    mem_reg_0_15_12_17,
    idelay_ld_rst,
    idelay_ld_rst_7,
    idelay_ld_rst_8,
    idelay_ld_rst_9,
    idelay_ld_rst_10,
    idelay_ld_rst_11,
    idelay_ld_rst_12,
    idelay_ld_rst_13,
    out,
    ififo_rst_reg,
    \pi_dqs_found_lanes_r1_reg[0] ,
    \pi_dqs_found_lanes_r1_reg[0]_0 ,
    mc_address,
    mem_out,
    out_fifo,
    out_fifo_0,
    out_fifo_1,
    mc_ras_n,
    mc_bank,
    out_fifo_2,
    out_fifo_3,
    out_fifo_4,
    out_fifo_5,
    out_fifo_6,
    out_fifo_7,
    out_fifo_8,
    out_fifo_9,
    out_fifo_10,
    out_fifo_11,
    out_fifo_12,
    out_fifo_13,
    out_fifo_14,
    out_fifo_15,
    out_fifo_16,
    out_fifo_17,
    mc_cas_n,
    out_fifo_18,
    out_fifo_19,
    mc_odt,
    mc_cke,
    mc_we_n,
    app_rd_data_valid_0,
    \read_fifo.tail_r ,
    \idelay_tap_cnt_r_reg[0][4][4] ,
    \po_rdval_cnt_reg[7] ,
    \po_rdval_cnt_reg[8] ,
    \po_rdval_cnt_reg[0] ,
    \po_rdval_cnt_reg[1] ,
    \po_rdval_cnt_reg[2] ,
    \po_rdval_cnt_reg[3] ,
    \po_rdval_cnt_reg[4] ,
    \po_rdval_cnt_reg[5] ,
    \po_rdval_cnt_reg[6] ,
    \pi_rst_stg1_cal_r_reg[1] ,
    \cmp_err_4to1.compare_err_f3_reg ,
    \fine_inc_reg[6][3] ,
    \corse_dec_reg[7][0] ,
    SS,
    \wait_cnt_r_reg[0] ,
    \tap_cnt_cpt_r_reg[5] ,
    \cnt_shift_r_reg[0] ,
    \wait_cnt_r_reg[0]_0 ,
    \en_cnt_div4.enable_wrlvl_cnt_reg[4] ,
    \device_temp_101_reg[11] ,
    \gen_rd[0].rd_data_rise_wl_r_reg[0] ,
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_0 ,
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_1 ,
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_2 ,
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_3 ,
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_4 ,
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_5 ,
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_6 ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1] ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_0 ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_1 ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_2 ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_3 ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_4 ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_5 ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_6 ,
    \gen_rd[2].rd_data_rise_wl_r_reg[2] ,
    \gen_rd[2].rd_data_rise_wl_r_reg[2]_0 ,
    \gen_rd[2].rd_data_rise_wl_r_reg[2]_1 ,
    \gen_rd[2].rd_data_rise_wl_r_reg[2]_2 ,
    \gen_rd[2].rd_data_rise_wl_r_reg[2]_3 ,
    \gen_rd[2].rd_data_rise_wl_r_reg[2]_4 ,
    \gen_rd[2].rd_data_rise_wl_r_reg[2]_5 ,
    \gen_rd[2].rd_data_rise_wl_r_reg[2]_6 ,
    \gen_rd[3].rd_data_rise_wl_r_reg[3] ,
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_0 ,
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_1 ,
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_2 ,
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_3 ,
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_4 ,
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_5 ,
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_6 ,
    \gen_rd[4].rd_data_rise_wl_r_reg[4] ,
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_0 ,
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_1 ,
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_2 ,
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_3 ,
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_4 ,
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_5 ,
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_6 ,
    \gen_rd[5].rd_data_rise_wl_r_reg[5] ,
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_0 ,
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_1 ,
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_2 ,
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_3 ,
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_4 ,
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_5 ,
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_6 ,
    \gen_rd[6].rd_data_rise_wl_r_reg[6] ,
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_0 ,
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_1 ,
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_2 ,
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_3 ,
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_4 ,
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_5 ,
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_6 ,
    \gen_rd[7].rd_data_rise_wl_r_reg[7] ,
    \gen_rd[7].rd_data_rise_wl_r_reg[7]_0 ,
    \gen_rd[7].rd_data_rise_wl_r_reg[7]_1 ,
    \gen_rd[7].rd_data_rise_wl_r_reg[7]_2 ,
    \gen_rd[7].rd_data_rise_wl_r_reg[7]_3 ,
    \gen_rd[7].rd_data_rise_wl_r_reg[7]_4 ,
    \gen_rd[7].rd_data_rise_wl_r_reg[7]_5 ,
    \gen_rd[7].rd_data_rise_wl_r_reg[7]_6 ,
    \pi_dqs_found_lanes_r1_reg[0]_1 ,
    \rdlvl_cpt_tap_cnt_reg[5] ,
    \rdlvl_cpt_tap_cnt_reg[5]_0 ,
    \data_offset_1_i1_reg[0] ,
    \data_offset_1_i1_reg[1] ,
    \data_offset_1_i1_reg[2] ,
    mc_data_offset_1,
    \data_offset_1_i1_reg[4] ,
    \data_offset_1_i1_reg[5] ,
    \data_offset_2_i1_reg[0] ,
    \data_offset_2_i1_reg[1] ,
    \data_offset_2_i1_reg[2] ,
    mc_data_offset_2,
    \data_offset_2_i1_reg[4] ,
    \data_offset_2_i1_reg[5] ,
    mc_cmd,
    \phy_ctl_wd_i1_reg[17] ,
    \phy_ctl_wd_i1_reg[18] ,
    \phy_ctl_wd_i1_reg[19] ,
    mc_data_offset,
    \phy_ctl_wd_i1_reg[21] ,
    \phy_ctl_wd_i1_reg[22] ,
    mc_wrdata_en);
  output po_cnt_dec_reg;
  output po_cnt_dec_2;
  output fine_adjust_reg;
  output new_cnt_cpt_r_reg;
  output rdlvl_stg1_start_reg;
  output samp_edge_cnt0_en_r;
  output pi_counter_load_en;
  output pi_cnt_dec_reg;
  output [0:0]E;
  output prbs_rdlvl_done_pulse_reg;
  output phy_write_calib;
  output phy_read_calib;
  output phy_if_reset;
  output idelay_inc;
  output [37:0]d_in;
  output init_calib_complete_reg_rep_0;
  output init_calib_complete_reg_rep__0_0;
  output init_calib_complete_reg_rep__11_0;
  output init_calib_complete_reg_rep__12_0;
  output init_calib_complete_reg_rep__24_0;
  output init_calib_complete_reg_rep__25_0;
  output init_calib_complete_reg_rep__26_0;
  output pi_fine_enable;
  output pi_fine_inc;
  output [2:0]\po_stg2_wrcal_cnt_reg[2] ;
  output \rd_mux_sel_r_reg[2] ;
  output [1:0]\rd_mux_sel_r_reg[1] ;
  output [23:0]phy_dout;
  output init_complete_r1_timing_reg;
  output [71:0]\write_buffer.wr_buf_out_data_reg[455] ;
  output [71:0]\write_buffer.wr_buf_out_data_reg[463] ;
  output [71:0]\write_buffer.wr_buf_out_data_reg[471] ;
  output [71:0]\write_buffer.wr_buf_out_data_reg[479] ;
  output [71:0]\write_buffer.wr_buf_out_data_reg[487] ;
  output [71:0]\write_buffer.wr_buf_out_data_reg[495] ;
  output [71:0]\write_buffer.wr_buf_out_data_reg[503] ;
  output [71:0]\write_buffer.wr_buf_out_data_reg[511] ;
  output LD0;
  output [3:0]calib_sel;
  output LD0_0;
  output LD0_1;
  output LD0_2;
  output LD0_3;
  output LD0_4;
  output LD0_5;
  output LD0_6;
  output \calib_sel_reg[1]_0 ;
  output \calib_sel_reg[1]_1 ;
  output \calib_sel_reg[1]_2 ;
  output \calib_sel_reg[1]_3 ;
  output \calib_sel_reg[1]_4 ;
  output \calib_sel_reg[1]_5 ;
  output \calib_sel_reg[1]_6 ;
  output \calib_sel_reg[1]_7 ;
  output \calib_sel_reg[1]_8 ;
  output dqs_wl_po_stg2_c_incdec_reg;
  output \calib_sel_reg[1]_9 ;
  output \calib_sel_reg[1]_10 ;
  output \calib_sel_reg[1]_11 ;
  output \calib_sel_reg[0]_0 ;
  output \calib_sel_reg[1]_12 ;
  output \calib_sel_reg[1]_13 ;
  output \calib_sel_reg[1]_14 ;
  output \calib_sel_reg[1]_15 ;
  output \calib_sel_reg[1]_16 ;
  output \calib_sel_reg[1]_17 ;
  output \calib_sel_reg[1]_18 ;
  output \calib_sel_reg[1]_19 ;
  output \calib_sel_reg[1]_20 ;
  output \calib_sel_reg[1]_21 ;
  output \calib_sel_reg[1]_22 ;
  output \calib_sel_reg[1]_23 ;
  output idelay_ce_r2_reg_0;
  output \calib_sel_reg[0]_1 ;
  output \pi_rst_stg1_cal_reg[0] ;
  output \calib_sel_reg[0]_2 ;
  output \calib_sel_reg[0]_3 ;
  output pi_stg2_load_reg;
  output \calib_sel_reg[1]_24 ;
  output \calib_sel_reg[1]_25 ;
  output \calib_sel_reg[1]_26 ;
  output \calib_sel_reg[1]_27 ;
  output \calib_sel_reg[1]_28 ;
  output \calib_sel_reg[1]_29 ;
  output \calib_sel_reg[1]_30 ;
  output \calib_sel_reg[1]_31 ;
  output \calib_sel_reg[1]_32 ;
  output dqs_wl_po_stg2_c_incdec_reg_0;
  output \calib_sel_reg[1]_33 ;
  output \calib_sel_reg[1]_34 ;
  output \calib_sel_reg[1]_35 ;
  output \calib_sel_reg[0]_4 ;
  output \calib_sel_reg[1]_36 ;
  output \calib_sel_reg[1]_37 ;
  output \calib_sel_reg[1]_38 ;
  output \calib_sel_reg[1]_39 ;
  output \calib_sel_reg[1]_40 ;
  output \calib_sel_reg[1]_41 ;
  output \calib_sel_reg[1]_42 ;
  output \calib_sel_reg[1]_43 ;
  output \calib_sel_reg[1]_44 ;
  output \calib_sel_reg[1]_45 ;
  output \calib_sel_reg[1]_46 ;
  output \calib_sel_reg[1]_47 ;
  output idelay_ce_r2_reg_1;
  output \calib_sel_reg[0]_5 ;
  output \pi_rst_stg1_cal_reg[2] ;
  output \calib_sel_reg[0]_6 ;
  output \calib_sel_reg[0]_7 ;
  output pi_stg2_load_reg_0;
  output C_po_coarse_enable26_out;
  output \gen_byte_sel_div2.calib_in_common_reg_0 ;
  output \gen_byte_sel_div2.calib_in_common_reg_1 ;
  output C_po_fine_enable23_out;
  output \gen_byte_sel_div2.calib_in_common_reg_2 ;
  output \gen_byte_sel_div2.calib_in_common_reg_3 ;
  output \gen_byte_sel_div2.calib_in_common_reg_4 ;
  output \gen_byte_sel_div2.calib_in_common_reg_5 ;
  output C_po_counter_read_en38_out;
  output dqs_po_stg2_f_incdec_reg;
  output dqs_po_stg2_f_incdec_reg_0;
  output dqs_po_stg2_f_incdec_reg_1;
  output dqs_po_stg2_f_incdec_reg_2;
  output dqs_po_stg2_f_incdec_reg_3;
  output dqs_po_stg2_f_incdec_reg_4;
  output dqs_po_stg2_f_incdec_reg_5;
  output dqs_po_stg2_f_incdec_reg_6;
  output C_po_fine_inc29_out;
  output dqs_po_stg2_f_incdec_reg_7;
  output dqs_po_stg2_f_incdec_reg_8;
  output [7:0]D6;
  output [3:0]D8;
  output [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[2] ;
  output [3:0]D5;
  output [3:0]D4;
  output [3:0]D7;
  output [3:0]D9;
  output [3:0]D1;
  output [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[8] ;
  output [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] ;
  output [3:0]D3;
  output [3:0]\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] ;
  output [7:0]\gen_no_mirror.div_clk_loop[0].phy_bank_reg[1] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[448] ;
  output [7:0]D2;
  output [7:0]\write_buffer.wr_buf_out_data_reg[450] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[451] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[452] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[453] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[454] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[455]_0 ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[456] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[457] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[458] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[459] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[460] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[461] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[462] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[463]_0 ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[464] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[465] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[466] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[467] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[468] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[469] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[470] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[471]_0 ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[472] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[473] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[474] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[475] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[476] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[477] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[478] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[479]_0 ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[480] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[481] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[482] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[483] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[484] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[485] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[486] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[487]_0 ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[488] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[489] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[490] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[491] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[492] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[493] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[494] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[495]_0 ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[496] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[497] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[498] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[499] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[500] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[501] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[502] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[503]_0 ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[504] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[505] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[506] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[507] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[508] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[509] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[510] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[511]_0 ;
  output [1:0]\cmd_pipe_plus.mc_ras_n_reg[1] ;
  output [0:0]\cmd_pipe_plus.mc_cas_n_reg[1] ;
  output [3:0]\cmd_pipe_plus.mc_odt_reg[0] ;
  output [3:0]\cmd_pipe_plus.mc_cke_reg[3] ;
  output [0:0]\cmd_pipe_plus.mc_we_n_reg[1] ;
  output init_calib_complete_reg_rep__26_1;
  output app_rd_data_valid;
  output \read_fifo.tail_r_reg[0] ;
  output \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0] ;
  output [5:0]\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] ;
  output \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6] ;
  output [5:0]\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] ;
  output \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][12] ;
  output [5:0]\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17] ;
  output \init_state_r_reg[4] ;
  output [0:0]SR;
  output [2:0]pi_rst_dqs_find;
  output [5:0]pi_counter_load_val;
  output [2:0]\rd_mux_sel_r_reg[2]_0 ;
  output [10:0]D;
  output [5:0]COUNTERLOADVAL;
  output [5:0]\calib_sel_reg[1]_48 ;
  output [5:0]\calib_sel_reg[1]_49 ;
  output [5:0]\pi_stg2_reg_l_reg[5] ;
  output [5:0]\calib_sel_reg[1]_50 ;
  output [5:0]\calib_sel_reg[1]_51 ;
  output [5:0]\calib_sel_reg[1]_52 ;
  output [5:0]\pi_stg2_reg_l_reg[5]_0 ;
  output [5:0]\cmd_pipe_plus.mc_data_offset_1_reg[5] ;
  output [5:0]\cmd_pipe_plus.mc_data_offset_2_reg[5] ;
  output phy_data_wr_en;
  output phy_cmd_wr_en;
  output mux_reset_n;
  output [5:0]\cmd_pipe_plus.mc_cke_reg[3]_0 ;
  input [0:0]Q;
  input \dout_o_reg[15] ;
  input [1:0]\fine_dec_cnt_reg[5] ;
  input [1:0]\corse_inc_reg[6][2] ;
  input \wl_dqs_tap_count_r_reg[0][5][5] ;
  input po_en_stg2_f_reg;
  input [7:0]in0;
  input first_fail_detect_reg;
  input [1:0]\rdlvl_dqs_tap_cnt_r_reg[0][0][2] ;
  input \gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;
  input \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;
  input \gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;
  input \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  input \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;
  input \gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;
  input \gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;
  input \gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;
  input \gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;
  input \gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  input \gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;
  input \gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  input \gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;
  input \gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  input \gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;
  input \gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  input \gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;
  input \gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  input \gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;
  input \gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  input \gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;
  input \gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  input \gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;
  input \gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  input \gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;
  input \gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  input \gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;
  input \gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  input \gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;
  input \gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  input \gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;
  input \gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  input \gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;
  input \gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  input \gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;
  input \gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  input \gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;
  input \gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  input \gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;
  input \gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  input \gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;
  input \gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  input \gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;
  input \gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  input \gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;
  input \gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  input \gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;
  input \gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  input \gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;
  input \gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  input \gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;
  input \gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  input \gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;
  input \gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  input \gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;
  input \gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  input \gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;
  input \gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  input \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  input \gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  input \gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;
  input \gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  input \gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;
  input \gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  input \samp_edge_cnt1_r_reg[0] ;
  input [0:0]\FSM_onehot_cal1_state_r_reg[7] ;
  input \samples_cnt_r_reg[0] ;
  input \gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ;
  input \gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ;
  input \gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ;
  input \gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ;
  input \gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ;
  input \gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ;
  input \gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ;
  input \gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ;
  input \gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ;
  input \gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ;
  input \gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ;
  input \gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ;
  input \gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ;
  input \gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ;
  input \gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ;
  input \gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ;
  input \gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ;
  input \gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ;
  input \gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ;
  input \gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ;
  input \gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ;
  input \gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ;
  input \gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ;
  input \gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ;
  input \gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ;
  input \gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ;
  input \gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ;
  input \gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ;
  input \gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ;
  input \gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ;
  input \gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ;
  input \gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ;
  input \gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ;
  input \gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ;
  input \gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ;
  input \gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ;
  input \gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ;
  input \gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ;
  input \gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ;
  input \gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ;
  input \gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ;
  input \gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ;
  input \gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ;
  input \gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ;
  input \gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ;
  input \gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ;
  input \gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ;
  input \gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ;
  input \gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ;
  input \gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ;
  input \gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ;
  input \gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ;
  input \gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ;
  input \gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ;
  input \gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ;
  input \gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ;
  input \gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ;
  input \gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ;
  input \gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ;
  input \gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ;
  input \gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ;
  input \gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ;
  input \gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ;
  input \gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ;
  input \en_cnt_div4.enable_wrlvl_cnt_reg[2] ;
  input pi_phase_locked_all_r1_reg;
  input [0:0]\victim_sel_reg[0] ;
  input \four_dec_min_limit_reg[0] ;
  input mc_ref_zq_wip;
  input \one_dec_min_limit_reg[11] ;
  input \one_dec_max_limit_reg[2] ;
  input phy_rddata_en;
  input if_empty;
  input p_0_out;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  input cal2_if_reset_reg;
  input \idelay_tap_cnt_r_reg[0][0][4] ;
  input \not_empty_wait_cnt_reg[4] ;
  input \complex_num_writes_reg[1] ;
  input [575:0]mem_reg_0_15_12_17;
  input idelay_ld_rst;
  input idelay_ld_rst_7;
  input idelay_ld_rst_8;
  input idelay_ld_rst_9;
  input idelay_ld_rst_10;
  input idelay_ld_rst_11;
  input idelay_ld_rst_12;
  input idelay_ld_rst_13;
  input out;
  input [1:0]ififo_rst_reg;
  input \pi_dqs_found_lanes_r1_reg[0] ;
  input \pi_dqs_found_lanes_r1_reg[0]_0 ;
  input [34:0]mc_address;
  input [35:0]mem_out;
  input out_fifo;
  input [23:0]out_fifo_0;
  input out_fifo_1;
  input [0:0]mc_ras_n;
  input [8:0]mc_bank;
  input [63:0]out_fifo_2;
  input out_fifo_3;
  input [63:0]out_fifo_4;
  input out_fifo_5;
  input [63:0]out_fifo_6;
  input out_fifo_7;
  input [63:0]out_fifo_8;
  input out_fifo_9;
  input [63:0]out_fifo_10;
  input out_fifo_11;
  input [63:0]out_fifo_12;
  input out_fifo_13;
  input [63:0]out_fifo_14;
  input out_fifo_15;
  input [63:0]out_fifo_16;
  input out_fifo_17;
  input [0:0]mc_cas_n;
  input [11:0]out_fifo_18;
  input out_fifo_19;
  input [0:0]mc_odt;
  input [0:0]mc_cke;
  input [0:0]mc_we_n;
  input [0:0]app_rd_data_valid_0;
  input [0:0]\read_fifo.tail_r ;
  input \idelay_tap_cnt_r_reg[0][4][4] ;
  input \po_rdval_cnt_reg[7] ;
  input \po_rdval_cnt_reg[8] ;
  input \po_rdval_cnt_reg[0] ;
  input \po_rdval_cnt_reg[1] ;
  input \po_rdval_cnt_reg[2] ;
  input \po_rdval_cnt_reg[3] ;
  input \po_rdval_cnt_reg[4] ;
  input \po_rdval_cnt_reg[5] ;
  input \po_rdval_cnt_reg[6] ;
  input \pi_rst_stg1_cal_r_reg[1] ;
  input \cmp_err_4to1.compare_err_f3_reg ;
  input [1:0]\fine_inc_reg[6][3] ;
  input [1:0]\corse_dec_reg[7][0] ;
  input [0:0]SS;
  input [0:0]\wait_cnt_r_reg[0] ;
  input [0:0]\tap_cnt_cpt_r_reg[5] ;
  input [0:0]\cnt_shift_r_reg[0] ;
  input [0:0]\wait_cnt_r_reg[0]_0 ;
  input \en_cnt_div4.enable_wrlvl_cnt_reg[4] ;
  input [11:0]\device_temp_101_reg[11] ;
  input \gen_rd[0].rd_data_rise_wl_r_reg[0] ;
  input \gen_rd[0].rd_data_rise_wl_r_reg[0]_0 ;
  input \gen_rd[0].rd_data_rise_wl_r_reg[0]_1 ;
  input \gen_rd[0].rd_data_rise_wl_r_reg[0]_2 ;
  input \gen_rd[0].rd_data_rise_wl_r_reg[0]_3 ;
  input \gen_rd[0].rd_data_rise_wl_r_reg[0]_4 ;
  input \gen_rd[0].rd_data_rise_wl_r_reg[0]_5 ;
  input \gen_rd[0].rd_data_rise_wl_r_reg[0]_6 ;
  input \gen_rd[1].rd_data_rise_wl_r_reg[1] ;
  input \gen_rd[1].rd_data_rise_wl_r_reg[1]_0 ;
  input \gen_rd[1].rd_data_rise_wl_r_reg[1]_1 ;
  input \gen_rd[1].rd_data_rise_wl_r_reg[1]_2 ;
  input \gen_rd[1].rd_data_rise_wl_r_reg[1]_3 ;
  input \gen_rd[1].rd_data_rise_wl_r_reg[1]_4 ;
  input \gen_rd[1].rd_data_rise_wl_r_reg[1]_5 ;
  input \gen_rd[1].rd_data_rise_wl_r_reg[1]_6 ;
  input \gen_rd[2].rd_data_rise_wl_r_reg[2] ;
  input \gen_rd[2].rd_data_rise_wl_r_reg[2]_0 ;
  input \gen_rd[2].rd_data_rise_wl_r_reg[2]_1 ;
  input \gen_rd[2].rd_data_rise_wl_r_reg[2]_2 ;
  input \gen_rd[2].rd_data_rise_wl_r_reg[2]_3 ;
  input \gen_rd[2].rd_data_rise_wl_r_reg[2]_4 ;
  input \gen_rd[2].rd_data_rise_wl_r_reg[2]_5 ;
  input \gen_rd[2].rd_data_rise_wl_r_reg[2]_6 ;
  input \gen_rd[3].rd_data_rise_wl_r_reg[3] ;
  input \gen_rd[3].rd_data_rise_wl_r_reg[3]_0 ;
  input \gen_rd[3].rd_data_rise_wl_r_reg[3]_1 ;
  input \gen_rd[3].rd_data_rise_wl_r_reg[3]_2 ;
  input \gen_rd[3].rd_data_rise_wl_r_reg[3]_3 ;
  input \gen_rd[3].rd_data_rise_wl_r_reg[3]_4 ;
  input \gen_rd[3].rd_data_rise_wl_r_reg[3]_5 ;
  input \gen_rd[3].rd_data_rise_wl_r_reg[3]_6 ;
  input \gen_rd[4].rd_data_rise_wl_r_reg[4] ;
  input \gen_rd[4].rd_data_rise_wl_r_reg[4]_0 ;
  input \gen_rd[4].rd_data_rise_wl_r_reg[4]_1 ;
  input \gen_rd[4].rd_data_rise_wl_r_reg[4]_2 ;
  input \gen_rd[4].rd_data_rise_wl_r_reg[4]_3 ;
  input \gen_rd[4].rd_data_rise_wl_r_reg[4]_4 ;
  input \gen_rd[4].rd_data_rise_wl_r_reg[4]_5 ;
  input \gen_rd[4].rd_data_rise_wl_r_reg[4]_6 ;
  input \gen_rd[5].rd_data_rise_wl_r_reg[5] ;
  input \gen_rd[5].rd_data_rise_wl_r_reg[5]_0 ;
  input \gen_rd[5].rd_data_rise_wl_r_reg[5]_1 ;
  input \gen_rd[5].rd_data_rise_wl_r_reg[5]_2 ;
  input \gen_rd[5].rd_data_rise_wl_r_reg[5]_3 ;
  input \gen_rd[5].rd_data_rise_wl_r_reg[5]_4 ;
  input \gen_rd[5].rd_data_rise_wl_r_reg[5]_5 ;
  input \gen_rd[5].rd_data_rise_wl_r_reg[5]_6 ;
  input \gen_rd[6].rd_data_rise_wl_r_reg[6] ;
  input \gen_rd[6].rd_data_rise_wl_r_reg[6]_0 ;
  input \gen_rd[6].rd_data_rise_wl_r_reg[6]_1 ;
  input \gen_rd[6].rd_data_rise_wl_r_reg[6]_2 ;
  input \gen_rd[6].rd_data_rise_wl_r_reg[6]_3 ;
  input \gen_rd[6].rd_data_rise_wl_r_reg[6]_4 ;
  input \gen_rd[6].rd_data_rise_wl_r_reg[6]_5 ;
  input \gen_rd[6].rd_data_rise_wl_r_reg[6]_6 ;
  input \gen_rd[7].rd_data_rise_wl_r_reg[7] ;
  input \gen_rd[7].rd_data_rise_wl_r_reg[7]_0 ;
  input \gen_rd[7].rd_data_rise_wl_r_reg[7]_1 ;
  input \gen_rd[7].rd_data_rise_wl_r_reg[7]_2 ;
  input \gen_rd[7].rd_data_rise_wl_r_reg[7]_3 ;
  input \gen_rd[7].rd_data_rise_wl_r_reg[7]_4 ;
  input \gen_rd[7].rd_data_rise_wl_r_reg[7]_5 ;
  input \gen_rd[7].rd_data_rise_wl_r_reg[7]_6 ;
  input [5:0]\pi_dqs_found_lanes_r1_reg[0]_1 ;
  input [5:0]\rdlvl_cpt_tap_cnt_reg[5] ;
  input [5:0]\rdlvl_cpt_tap_cnt_reg[5]_0 ;
  input \data_offset_1_i1_reg[0] ;
  input \data_offset_1_i1_reg[1] ;
  input \data_offset_1_i1_reg[2] ;
  input [0:0]mc_data_offset_1;
  input \data_offset_1_i1_reg[4] ;
  input \data_offset_1_i1_reg[5] ;
  input \data_offset_2_i1_reg[0] ;
  input \data_offset_2_i1_reg[1] ;
  input \data_offset_2_i1_reg[2] ;
  input [0:0]mc_data_offset_2;
  input \data_offset_2_i1_reg[4] ;
  input \data_offset_2_i1_reg[5] ;
  input [1:0]mc_cmd;
  input \phy_ctl_wd_i1_reg[17] ;
  input \phy_ctl_wd_i1_reg[18] ;
  input \phy_ctl_wd_i1_reg[19] ;
  input [0:0]mc_data_offset;
  input \phy_ctl_wd_i1_reg[21] ;
  input \phy_ctl_wd_i1_reg[22] ;
  input mc_wrdata_en;

  wire [5:0]COUNTERLOADVAL;
  wire C_po_coarse_enable26_out;
  wire C_po_counter_read_en38_out;
  wire C_po_fine_enable23_out;
  wire C_po_fine_inc29_out;
  wire [10:0]D;
  wire [3:0]D1;
  wire [7:0]D2;
  wire [3:0]D3;
  wire [3:0]D4;
  wire [3:0]D5;
  wire [7:0]D6;
  wire [3:0]D7;
  wire [3:0]D8;
  wire [3:0]D9;
  wire [0:0]E;
  wire [0:0]\FSM_onehot_cal1_state_r_reg[7] ;
  wire LD0;
  wire LD0_0;
  wire LD0_1;
  wire LD0_2;
  wire LD0_3;
  wire LD0_4;
  wire LD0_5;
  wire LD0_6;
  wire [0:0]Q;
  wire [0:0]SR;
  wire [0:0]SS;
  wire app_rd_data_valid;
  wire [0:0]app_rd_data_valid_0;
  wire cal2_if_reset_reg;
  wire calib_complete;
  wire calib_in_common;
  wire calib_in_common4_out;
  wire [3:0]calib_sel;
  wire calib_sel1__1;
  wire \calib_sel[1]_i_3_n_0 ;
  wire \calib_sel_reg[0]_0 ;
  wire \calib_sel_reg[0]_1 ;
  wire \calib_sel_reg[0]_2 ;
  wire \calib_sel_reg[0]_3 ;
  wire \calib_sel_reg[0]_4 ;
  wire \calib_sel_reg[0]_5 ;
  wire \calib_sel_reg[0]_6 ;
  wire \calib_sel_reg[0]_7 ;
  wire \calib_sel_reg[1]_0 ;
  wire \calib_sel_reg[1]_1 ;
  wire \calib_sel_reg[1]_10 ;
  wire \calib_sel_reg[1]_11 ;
  wire \calib_sel_reg[1]_12 ;
  wire \calib_sel_reg[1]_13 ;
  wire \calib_sel_reg[1]_14 ;
  wire \calib_sel_reg[1]_15 ;
  wire \calib_sel_reg[1]_16 ;
  wire \calib_sel_reg[1]_17 ;
  wire \calib_sel_reg[1]_18 ;
  wire \calib_sel_reg[1]_19 ;
  wire \calib_sel_reg[1]_2 ;
  wire \calib_sel_reg[1]_20 ;
  wire \calib_sel_reg[1]_21 ;
  wire \calib_sel_reg[1]_22 ;
  wire \calib_sel_reg[1]_23 ;
  wire \calib_sel_reg[1]_24 ;
  wire \calib_sel_reg[1]_25 ;
  wire \calib_sel_reg[1]_26 ;
  wire \calib_sel_reg[1]_27 ;
  wire \calib_sel_reg[1]_28 ;
  wire \calib_sel_reg[1]_29 ;
  wire \calib_sel_reg[1]_3 ;
  wire \calib_sel_reg[1]_30 ;
  wire \calib_sel_reg[1]_31 ;
  wire \calib_sel_reg[1]_32 ;
  wire \calib_sel_reg[1]_33 ;
  wire \calib_sel_reg[1]_34 ;
  wire \calib_sel_reg[1]_35 ;
  wire \calib_sel_reg[1]_36 ;
  wire \calib_sel_reg[1]_37 ;
  wire \calib_sel_reg[1]_38 ;
  wire \calib_sel_reg[1]_39 ;
  wire \calib_sel_reg[1]_4 ;
  wire \calib_sel_reg[1]_40 ;
  wire \calib_sel_reg[1]_41 ;
  wire \calib_sel_reg[1]_42 ;
  wire \calib_sel_reg[1]_43 ;
  wire \calib_sel_reg[1]_44 ;
  wire \calib_sel_reg[1]_45 ;
  wire \calib_sel_reg[1]_46 ;
  wire \calib_sel_reg[1]_47 ;
  wire [5:0]\calib_sel_reg[1]_48 ;
  wire [5:0]\calib_sel_reg[1]_49 ;
  wire \calib_sel_reg[1]_5 ;
  wire [5:0]\calib_sel_reg[1]_50 ;
  wire [5:0]\calib_sel_reg[1]_51 ;
  wire [5:0]\calib_sel_reg[1]_52 ;
  wire \calib_sel_reg[1]_6 ;
  wire \calib_sel_reg[1]_7 ;
  wire \calib_sel_reg[1]_8 ;
  wire \calib_sel_reg[1]_9 ;
  wire [2:0]calib_zero_inputs;
  wire ck_addr_cmd_delay_done;
  wire ck_po_stg2_f_en;
  wire ck_po_stg2_f_indec;
  wire cmd_delay_start0;
  wire [0:0]\cmd_pipe_plus.mc_cas_n_reg[1] ;
  wire [3:0]\cmd_pipe_plus.mc_cke_reg[3] ;
  wire [5:0]\cmd_pipe_plus.mc_cke_reg[3]_0 ;
  wire [5:0]\cmd_pipe_plus.mc_data_offset_1_reg[5] ;
  wire [5:0]\cmd_pipe_plus.mc_data_offset_2_reg[5] ;
  wire [3:0]\cmd_pipe_plus.mc_odt_reg[0] ;
  wire [1:0]\cmd_pipe_plus.mc_ras_n_reg[1] ;
  wire [0:0]\cmd_pipe_plus.mc_we_n_reg[1] ;
  wire cmd_po_en_stg2_f;
  wire \cmp_err_4to1.compare_err_f3_reg ;
  wire [0:0]\cnt_shift_r_reg[0] ;
  wire complex_act_start;
  wire \complex_num_writes_reg[1] ;
  wire complex_ocal_reset_rd_addr;
  wire complex_pi_incdec_done;
  wire [1:0]\corse_dec_reg[7][0] ;
  wire [1:0]\corse_inc_reg[6][2] ;
  wire [2:0]ctl_lane_cnt;
  wire ctl_lane_sel;
  wire [37:0]d_in;
  wire \data_offset_1_i1_reg[0] ;
  wire \data_offset_1_i1_reg[1] ;
  wire \data_offset_1_i1_reg[2] ;
  wire \data_offset_1_i1_reg[4] ;
  wire \data_offset_1_i1_reg[5] ;
  wire \data_offset_2_i1_reg[0] ;
  wire \data_offset_2_i1_reg[1] ;
  wire \data_offset_2_i1_reg[2] ;
  wire \data_offset_2_i1_reg[4] ;
  wire \data_offset_2_i1_reg[5] ;
  wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_1 ;
  wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_11 ;
  wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_12 ;
  wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_13 ;
  wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_14 ;
  wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_15 ;
  wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_16 ;
  wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_17 ;
  wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_18 ;
  wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_19 ;
  wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_2 ;
  wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_20 ;
  wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_22 ;
  wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_23 ;
  wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_25 ;
  wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_26 ;
  wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_27 ;
  wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_28 ;
  wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_29 ;
  (* MAX_FANOUT = "100" *) (* RTL_MAX_FANOUT = "found" *) wire \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_7 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_10 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_14 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_15 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_19 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_20 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_22 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_23 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_24 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_25 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_26 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_27 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_28 ;
  wire \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_30 ;
  wire ddr_phy_tempmon_0_n_2;
  wire ddr_phy_tempmon_0_n_3;
  wire ddr_phy_tempmon_0_n_4;
  wire ddr_phy_tempmon_0_n_5;
  wire ddr_phy_tempmon_0_n_6;
  wire delaydec_cnt_r10_in;
  wire detect_pi_found_dqs;
  wire [11:0]\device_temp_101_reg[11] ;
  wire done_dqs_dec238_out;
  wire done_dqs_tap_inc;
  wire \dout_o_reg[15] ;
  wire [3:3]dqs_count_r;
  wire dqs_found_prech_req;
  wire dqs_po_dec_done;
  wire dqs_po_en_stg2_f;
  wire dqs_po_stg2_f_incdec_reg;
  wire dqs_po_stg2_f_incdec_reg_0;
  wire dqs_po_stg2_f_incdec_reg_1;
  wire dqs_po_stg2_f_incdec_reg_2;
  wire dqs_po_stg2_f_incdec_reg_3;
  wire dqs_po_stg2_f_incdec_reg_4;
  wire dqs_po_stg2_f_incdec_reg_5;
  wire dqs_po_stg2_f_incdec_reg_6;
  wire dqs_po_stg2_f_incdec_reg_7;
  wire dqs_po_stg2_f_incdec_reg_8;
  wire dqs_wl_po_stg2_c_incdec_reg;
  wire dqs_wl_po_stg2_c_incdec_reg_0;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_2 ;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_28 ;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_29 ;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_30 ;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_34 ;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_35 ;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_36 ;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_37 ;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_38 ;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_39 ;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_40 ;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_41 ;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_42 ;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_43 ;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_44 ;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_45 ;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_46 ;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_47 ;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_48 ;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_49 ;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_50 ;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_51 ;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_52 ;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_53 ;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_54 ;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_56 ;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_57 ;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_58 ;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_59 ;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_61 ;
  wire \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_62 ;
  wire \en_cnt_div4.enable_wrlvl_cnt_reg[2] ;
  wire \en_cnt_div4.enable_wrlvl_cnt_reg[4] ;
  wire fine_adjust_reg;
  wire [1:0]\fine_dec_cnt_reg[5] ;
  wire [1:0]\fine_inc_reg[6][3] ;
  wire first_fail_detect_reg;
  wire first_rdlvl_pat_r;
  wire first_wrcal_pat_r;
  wire \four_dec_min_limit_reg[0] ;
  wire \gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[0] ;
  wire \gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[1] ;
  wire \gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[2] ;
  wire \gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[3] ;
  wire \gen_byte_sel_div2.calib_in_common_reg_0 ;
  wire \gen_byte_sel_div2.calib_in_common_reg_1 ;
  wire \gen_byte_sel_div2.calib_in_common_reg_2 ;
  wire \gen_byte_sel_div2.calib_in_common_reg_3 ;
  wire \gen_byte_sel_div2.calib_in_common_reg_4 ;
  wire \gen_byte_sel_div2.calib_in_common_reg_5 ;
  wire \gen_byte_sel_div2.ctl_lane_sel_reg_n_0_[0] ;
  wire \gen_byte_sel_div2.ctl_lane_sel_reg_n_0_[1] ;
  wire \gen_byte_sel_div2.ctl_lane_sel_reg_n_0_[2] ;
  wire \gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;
  wire \gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  wire \gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;
  wire \gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  wire \gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;
  wire \gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  wire \gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;
  wire \gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[2] ;
  wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[8] ;
  wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] ;
  wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] ;
  wire [7:0]\gen_no_mirror.div_clk_loop[0].phy_bank_reg[1] ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg[0] ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg[0]_0 ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg[0]_1 ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg[0]_2 ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg[0]_3 ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg[0]_4 ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg[0]_5 ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg[0]_6 ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg[1] ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg[1]_0 ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg[1]_1 ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg[1]_2 ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg[1]_3 ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg[1]_4 ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg[1]_5 ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg[1]_6 ;
  wire \gen_rd[2].rd_data_rise_wl_r_reg[2] ;
  wire \gen_rd[2].rd_data_rise_wl_r_reg[2]_0 ;
  wire \gen_rd[2].rd_data_rise_wl_r_reg[2]_1 ;
  wire \gen_rd[2].rd_data_rise_wl_r_reg[2]_2 ;
  wire \gen_rd[2].rd_data_rise_wl_r_reg[2]_3 ;
  wire \gen_rd[2].rd_data_rise_wl_r_reg[2]_4 ;
  wire \gen_rd[2].rd_data_rise_wl_r_reg[2]_5 ;
  wire \gen_rd[2].rd_data_rise_wl_r_reg[2]_6 ;
  wire \gen_rd[3].rd_data_rise_wl_r_reg[3] ;
  wire \gen_rd[3].rd_data_rise_wl_r_reg[3]_0 ;
  wire \gen_rd[3].rd_data_rise_wl_r_reg[3]_1 ;
  wire \gen_rd[3].rd_data_rise_wl_r_reg[3]_2 ;
  wire \gen_rd[3].rd_data_rise_wl_r_reg[3]_3 ;
  wire \gen_rd[3].rd_data_rise_wl_r_reg[3]_4 ;
  wire \gen_rd[3].rd_data_rise_wl_r_reg[3]_5 ;
  wire \gen_rd[3].rd_data_rise_wl_r_reg[3]_6 ;
  wire \gen_rd[4].rd_data_rise_wl_r_reg[4] ;
  wire \gen_rd[4].rd_data_rise_wl_r_reg[4]_0 ;
  wire \gen_rd[4].rd_data_rise_wl_r_reg[4]_1 ;
  wire \gen_rd[4].rd_data_rise_wl_r_reg[4]_2 ;
  wire \gen_rd[4].rd_data_rise_wl_r_reg[4]_3 ;
  wire \gen_rd[4].rd_data_rise_wl_r_reg[4]_4 ;
  wire \gen_rd[4].rd_data_rise_wl_r_reg[4]_5 ;
  wire \gen_rd[4].rd_data_rise_wl_r_reg[4]_6 ;
  wire \gen_rd[5].rd_data_rise_wl_r_reg[5] ;
  wire \gen_rd[5].rd_data_rise_wl_r_reg[5]_0 ;
  wire \gen_rd[5].rd_data_rise_wl_r_reg[5]_1 ;
  wire \gen_rd[5].rd_data_rise_wl_r_reg[5]_2 ;
  wire \gen_rd[5].rd_data_rise_wl_r_reg[5]_3 ;
  wire \gen_rd[5].rd_data_rise_wl_r_reg[5]_4 ;
  wire \gen_rd[5].rd_data_rise_wl_r_reg[5]_5 ;
  wire \gen_rd[5].rd_data_rise_wl_r_reg[5]_6 ;
  wire \gen_rd[6].rd_data_rise_wl_r_reg[6] ;
  wire \gen_rd[6].rd_data_rise_wl_r_reg[6]_0 ;
  wire \gen_rd[6].rd_data_rise_wl_r_reg[6]_1 ;
  wire \gen_rd[6].rd_data_rise_wl_r_reg[6]_2 ;
  wire \gen_rd[6].rd_data_rise_wl_r_reg[6]_3 ;
  wire \gen_rd[6].rd_data_rise_wl_r_reg[6]_4 ;
  wire \gen_rd[6].rd_data_rise_wl_r_reg[6]_5 ;
  wire \gen_rd[6].rd_data_rise_wl_r_reg[6]_6 ;
  wire \gen_rd[7].rd_data_rise_wl_r_reg[7] ;
  wire \gen_rd[7].rd_data_rise_wl_r_reg[7]_0 ;
  wire \gen_rd[7].rd_data_rise_wl_r_reg[7]_1 ;
  wire \gen_rd[7].rd_data_rise_wl_r_reg[7]_2 ;
  wire \gen_rd[7].rd_data_rise_wl_r_reg[7]_3 ;
  wire \gen_rd[7].rd_data_rise_wl_r_reg[7]_4 ;
  wire \gen_rd[7].rd_data_rise_wl_r_reg[7]_5 ;
  wire \gen_rd[7].rd_data_rise_wl_r_reg[7]_6 ;
  wire idelay_ce;
  wire idelay_ce_int;
  wire idelay_ce_r1;
  wire idelay_ce_r2_reg_0;
  wire idelay_ce_r2_reg_1;
  wire idelay_inc;
  wire idelay_inc_int;
  wire idelay_inc_r1;
  wire idelay_ld_rst;
  wire idelay_ld_rst_10;
  wire idelay_ld_rst_11;
  wire idelay_ld_rst_12;
  wire idelay_ld_rst_13;
  wire idelay_ld_rst_7;
  wire idelay_ld_rst_8;
  wire idelay_ld_rst_9;
  wire \idelay_tap_cnt_r_reg[0][0][4] ;
  wire \idelay_tap_cnt_r_reg[0][4][4] ;
  wire if_empty;
  wire [1:0]ififo_rst_reg;
  wire [7:0]in0;
  wire init_calib_complete_reg_rep_0;
  wire init_calib_complete_reg_rep__0_0;
  (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire init_calib_complete_reg_rep__10_n_0;
  wire init_calib_complete_reg_rep__11_0;
  wire init_calib_complete_reg_rep__12_0;
  (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire init_calib_complete_reg_rep__13_n_0;
  (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire init_calib_complete_reg_rep__14_n_0;
  (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire init_calib_complete_reg_rep__15_n_0;
  (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire init_calib_complete_reg_rep__16_n_0;
  (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire init_calib_complete_reg_rep__17_n_0;
  (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire init_calib_complete_reg_rep__18_n_0;
  (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire init_calib_complete_reg_rep__19_n_0;
  (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire init_calib_complete_reg_rep__1_n_0;
  (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire init_calib_complete_reg_rep__20_n_0;
  (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire init_calib_complete_reg_rep__21_n_0;
  (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire init_calib_complete_reg_rep__22_n_0;
  (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire init_calib_complete_reg_rep__23_n_0;
  wire init_calib_complete_reg_rep__24_0;
  wire init_calib_complete_reg_rep__25_0;
  wire init_calib_complete_reg_rep__26_0;
  wire init_calib_complete_reg_rep__26_1;
  (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire init_calib_complete_reg_rep__2_n_0;
  (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire init_calib_complete_reg_rep__3_n_0;
  (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire init_calib_complete_reg_rep__4_n_0;
  (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire init_calib_complete_reg_rep__5_n_0;
  (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire init_calib_complete_reg_rep__6_n_0;
  (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire init_calib_complete_reg_rep__7_n_0;
  (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire init_calib_complete_reg_rep__8_n_0;
  (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire init_calib_complete_reg_rep__9_n_0;
  wire init_complete_r1_timing_reg;
  wire init_dqsfound_done_r2;
  wire \init_state_r_reg[4] ;
  wire \mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_7 ;
  wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_10 ;
  wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_44 ;
  wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_45 ;
  wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_46 ;
  wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_47 ;
  wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_48 ;
  wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_5 ;
  wire \mb_wrlvl_inst.u_ddr_phy_wrlvl_n_50 ;
  wire [34:0]mc_address;
  wire [8:0]mc_bank;
  wire [0:0]mc_cas_n;
  wire [0:0]mc_cke;
  wire [1:0]mc_cmd;
  wire [0:0]mc_data_offset;
  wire [0:0]mc_data_offset_1;
  wire [0:0]mc_data_offset_2;
  wire [0:0]mc_odt;
  wire [0:0]mc_ras_n;
  wire mc_ref_zq_wip;
  wire [0:0]mc_we_n;
  wire mc_wrdata_en;
  wire [35:0]mem_out;
  wire [575:0]mem_reg_0_15_12_17;
  wire mux_rd_valid_r0;
  wire mux_reset_n;
  wire new_cnt_cpt_r_reg;
  wire \not_empty_wait_cnt_reg[4] ;
  wire num_samples_done_r;
  wire \one_dec_max_limit_reg[2] ;
  wire \one_dec_min_limit_reg[11] ;
  wire out;
  wire out_fifo;
  wire [23:0]out_fifo_0;
  wire out_fifo_1;
  wire [63:0]out_fifo_10;
  wire out_fifo_11;
  wire [63:0]out_fifo_12;
  wire out_fifo_13;
  wire [63:0]out_fifo_14;
  wire out_fifo_15;
  wire [63:0]out_fifo_16;
  wire out_fifo_17;
  wire [11:0]out_fifo_18;
  wire out_fifo_19;
  wire [63:0]out_fifo_2;
  wire out_fifo_3;
  wire [63:0]out_fifo_4;
  wire out_fifo_5;
  wire [63:0]out_fifo_6;
  wire out_fifo_7;
  wire [63:0]out_fifo_8;
  wire out_fifo_9;
  wire p_0_out;
  wire [3:0]p_1_in;
  wire p_1_in_0;
  wire phy_cmd_wr_en;
  wire \phy_ctl_wd_i1_reg[17] ;
  wire \phy_ctl_wd_i1_reg[18] ;
  wire \phy_ctl_wd_i1_reg[19] ;
  wire \phy_ctl_wd_i1_reg[21] ;
  wire \phy_ctl_wd_i1_reg[22] ;
  wire phy_data_wr_en;
  wire [23:0]phy_dout;
  wire phy_if_reset;
  wire phy_if_reset0__0;
  wire phy_if_reset_w;
  wire phy_rddata_en;
  wire phy_read_calib;
  wire phy_write_calib;
  wire pi_calib_done;
  wire pi_cnt_dec_reg;
  wire pi_counter_load_en;
  wire [5:0]pi_counter_load_val;
  wire pi_dqs_found_done_r1;
  wire \pi_dqs_found_lanes_r1_reg[0] ;
  wire \pi_dqs_found_lanes_r1_reg[0]_0 ;
  wire [5:0]\pi_dqs_found_lanes_r1_reg[0]_1 ;
  wire pi_dqs_found_rank_done;
  wire pi_fine_dly_dec_done;
  wire pi_fine_enable;
  wire pi_fine_inc;
  wire pi_phase_locked_all_r1_reg;
  wire [2:0]pi_rst_dqs_find;
  wire \pi_rst_stg1_cal_r_reg[1] ;
  wire \pi_rst_stg1_cal_reg[0] ;
  wire \pi_rst_stg1_cal_reg[2] ;
  wire pi_stg2_load_reg;
  wire pi_stg2_load_reg_0;
  wire [5:0]\pi_stg2_reg_l_reg[5] ;
  wire [5:0]\pi_stg2_reg_l_reg[5]_0 ;
  wire po_cnt_dec_2;
  wire po_cnt_dec_reg;
  wire po_en_stg2_f_reg;
  wire [2:2]po_enstg2_f;
  wire \po_rdval_cnt_reg[0] ;
  wire \po_rdval_cnt_reg[1] ;
  wire \po_rdval_cnt_reg[2] ;
  wire \po_rdval_cnt_reg[3] ;
  wire \po_rdval_cnt_reg[4] ;
  wire \po_rdval_cnt_reg[5] ;
  wire \po_rdval_cnt_reg[6] ;
  wire \po_rdval_cnt_reg[7] ;
  wire \po_rdval_cnt_reg[8] ;
  wire [3:3]po_stg2_wrcal_cnt;
  wire [2:0]\po_stg2_wrcal_cnt_reg[2] ;
  wire prbs_last_byte_done;
  wire [511:56]prbs_out;
  wire prbs_pi_stg2_f_en;
  wire prbs_pi_stg2_f_incdec;
  wire prbs_rdlvl_done_pulse0;
  wire prbs_rdlvl_done_pulse_reg;
  wire prbs_rdlvl_done_r1;
  wire prbs_rdlvl_start_r;
  wire prech_done;
  wire prech_req;
  wire \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0] ;
  wire [5:0]\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] ;
  wire [5:0]\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] ;
  wire \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6] ;
  wire \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][12] ;
  wire [5:0]\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17] ;
  wire rd_active_r;
  wire [3:3]rd_data_offset_ranks_0;
  wire [3:3]rd_data_offset_ranks_1;
  wire [3:3]rd_data_offset_ranks_2;
  wire [1:0]\rd_mux_sel_r_reg[1] ;
  wire \rd_mux_sel_r_reg[2] ;
  wire [2:0]\rd_mux_sel_r_reg[2]_0 ;
  wire [5:0]\rdlvl_cpt_tap_cnt_reg[5] ;
  wire [5:0]\rdlvl_cpt_tap_cnt_reg[5]_0 ;
  wire [1:0]\rdlvl_dqs_tap_cnt_r_reg[0][0][2] ;
  wire rdlvl_last_byte_done;
  wire rdlvl_pi_incdec;
  wire rdlvl_pi_stg2_f_en;
  wire rdlvl_pi_stg2_f_incdec;
  wire rdlvl_prech_req;
  wire rdlvl_stg1_done_r1;
  wire rdlvl_stg1_rank_done;
  wire rdlvl_stg1_start_reg;
  wire [0:0]\read_fifo.tail_r ;
  wire \read_fifo.tail_r_reg[0] ;
  wire reset_if;
  wire reset_if_r8_reg_srl8_n_0;
  wire reset_if_r9;
  wire reset_rd_addr;
  wire reset_rd_addr0;
  wire samp_edge_cnt0_en_r;
  wire \samp_edge_cnt1_r_reg[0] ;
  wire samples_cnt_r;
  wire \samples_cnt_r_reg[0] ;
  wire sel;
  wire stg1_wr_done;
  wire [0:0]\tap_cnt_cpt_r_reg[5] ;
  wire tempmon_pi_f_en_r;
  wire tempmon_pi_f_inc;
  wire tempmon_pi_f_inc_r;
  wire tempmon_sel_pi_incdec;
  wire u_ddr_phy_init_n_13;
  wire u_ddr_phy_init_n_15;
  wire u_ddr_phy_init_n_22;
  wire u_ddr_phy_init_n_23;
  wire u_ddr_phy_init_n_24;
  wire u_ddr_phy_init_n_25;
  wire u_ddr_phy_init_n_26;
  wire u_ddr_phy_init_n_27;
  wire u_ddr_phy_init_n_28;
  wire u_ddr_phy_init_n_29;
  wire u_ddr_phy_init_n_3;
  wire u_ddr_phy_init_n_677;
  wire u_ddr_phy_init_n_679;
  wire u_ddr_phy_init_n_680;
  wire u_ddr_phy_init_n_683;
  wire u_ddr_phy_init_n_684;
  wire u_ddr_phy_init_n_686;
  wire u_ddr_phy_init_n_687;
  wire u_ddr_phy_init_n_688;
  wire u_ddr_phy_init_n_689;
  wire u_ddr_phy_init_n_699;
  wire u_ddr_phy_init_n_700;
  wire u_ddr_phy_init_n_701;
  wire u_ddr_phy_wrcal_n_22;
  wire u_ddr_phy_wrcal_n_23;
  wire u_ddr_phy_wrcal_n_24;
  wire u_ddr_phy_wrcal_n_25;
  wire u_ddr_phy_wrcal_n_26;
  wire u_ddr_phy_wrcal_n_27;
  wire u_ddr_phy_wrcal_n_28;
  wire u_ddr_phy_wrcal_n_29;
  wire u_ddr_phy_wrcal_n_3;
  wire u_ddr_phy_wrcal_n_30;
  wire u_ddr_phy_wrcal_n_31;
  wire u_ddr_phy_wrcal_n_32;
  wire u_ddr_phy_wrcal_n_33;
  wire u_ddr_phy_wrcal_n_34;
  wire u_ddr_phy_wrcal_n_35;
  wire u_ddr_phy_wrcal_n_36;
  wire u_ddr_phy_wrcal_n_37;
  wire u_ddr_phy_wrcal_n_38;
  wire u_ddr_phy_wrcal_n_39;
  wire u_ddr_phy_wrcal_n_4;
  wire u_ddr_phy_wrcal_n_40;
  wire u_ddr_phy_wrcal_n_6;
  wire u_ddr_phy_wrcal_n_8;
  wire u_ddr_prbs_gen_n_0;
  wire u_ddr_prbs_gen_n_1;
  wire u_ddr_prbs_gen_n_10;
  wire u_ddr_prbs_gen_n_11;
  wire u_ddr_prbs_gen_n_12;
  wire u_ddr_prbs_gen_n_13;
  wire u_ddr_prbs_gen_n_14;
  wire u_ddr_prbs_gen_n_15;
  wire u_ddr_prbs_gen_n_16;
  wire u_ddr_prbs_gen_n_17;
  wire u_ddr_prbs_gen_n_18;
  wire u_ddr_prbs_gen_n_19;
  wire u_ddr_prbs_gen_n_2;
  wire u_ddr_prbs_gen_n_20;
  wire u_ddr_prbs_gen_n_21;
  wire u_ddr_prbs_gen_n_22;
  wire u_ddr_prbs_gen_n_23;
  wire u_ddr_prbs_gen_n_24;
  wire u_ddr_prbs_gen_n_25;
  wire u_ddr_prbs_gen_n_26;
  wire u_ddr_prbs_gen_n_27;
  wire u_ddr_prbs_gen_n_28;
  wire u_ddr_prbs_gen_n_29;
  wire u_ddr_prbs_gen_n_3;
  wire u_ddr_prbs_gen_n_30;
  wire u_ddr_prbs_gen_n_31;
  wire u_ddr_prbs_gen_n_32;
  wire u_ddr_prbs_gen_n_33;
  wire u_ddr_prbs_gen_n_34;
  wire u_ddr_prbs_gen_n_35;
  wire u_ddr_prbs_gen_n_36;
  wire u_ddr_prbs_gen_n_37;
  wire u_ddr_prbs_gen_n_38;
  wire u_ddr_prbs_gen_n_39;
  wire u_ddr_prbs_gen_n_4;
  wire u_ddr_prbs_gen_n_40;
  wire u_ddr_prbs_gen_n_41;
  wire u_ddr_prbs_gen_n_42;
  wire u_ddr_prbs_gen_n_43;
  wire u_ddr_prbs_gen_n_44;
  wire u_ddr_prbs_gen_n_45;
  wire u_ddr_prbs_gen_n_5;
  wire u_ddr_prbs_gen_n_6;
  wire u_ddr_prbs_gen_n_7;
  wire u_ddr_prbs_gen_n_8;
  wire u_ddr_prbs_gen_n_9;
  wire [0:0]\victim_sel_reg[0] ;
  wire [0:0]\wait_cnt_r_reg[0] ;
  wire [0:0]\wait_cnt_r_reg[0]_0 ;
  wire \wl_dqs_tap_count_r_reg[0][5][5] ;
  wire wl_sm_start;
  wire [4:3]wl_state_r__0;
  wire wr_level_done_r5;
  wire wrcal_prech_req;
  wire wrcal_rd_wait;
  wire wrcal_resume_w;
  wire wrcal_sanity_chk;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[448] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[450] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[451] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[452] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[453] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[454] ;
  wire [71:0]\write_buffer.wr_buf_out_data_reg[455] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[455]_0 ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[456] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[457] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[458] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[459] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[460] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[461] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[462] ;
  wire [71:0]\write_buffer.wr_buf_out_data_reg[463] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[463]_0 ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[464] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[465] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[466] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[467] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[468] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[469] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[470] ;
  wire [71:0]\write_buffer.wr_buf_out_data_reg[471] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[471]_0 ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[472] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[473] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[474] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[475] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[476] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[477] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[478] ;
  wire [71:0]\write_buffer.wr_buf_out_data_reg[479] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[479]_0 ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[480] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[481] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[482] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[483] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[484] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[485] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[486] ;
  wire [71:0]\write_buffer.wr_buf_out_data_reg[487] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[487]_0 ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[488] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[489] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[490] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[491] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[492] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[493] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[494] ;
  wire [71:0]\write_buffer.wr_buf_out_data_reg[495] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[495]_0 ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[496] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[497] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[498] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[499] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[500] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[501] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[502] ;
  wire [71:0]\write_buffer.wr_buf_out_data_reg[503] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[503]_0 ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[504] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[505] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[506] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[507] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[508] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[509] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[510] ;
  wire [71:0]\write_buffer.wr_buf_out_data_reg[511] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[511]_0 ;
  wire wrlvl_byte_done;
  wire wrlvl_byte_redo;
  wire wrlvl_byte_redo_r;
  wire wrlvl_done_r1;
  wire wrlvl_final_if_rst;
  wire wrlvl_rank_done;

  LUT2 #(
    .INIT(4'h2)) 
    \calib_sel[1]_i_3 
       (.I0(\gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[1] ),
        .I1(\gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[3] ),
        .O(\calib_sel[1]_i_3_n_0 ));
  (* syn_maxfan = "10" *) 
  FDRE \calib_sel_reg[0] 
       (.C(\dout_o_reg[15] ),
        .CE(1'b1),
        .D(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_59 ),
        .Q(calib_sel[0]),
        .R(ddr_phy_tempmon_0_n_5));
  (* syn_maxfan = "10" *) 
  FDRE \calib_sel_reg[1] 
       (.C(\dout_o_reg[15] ),
        .CE(1'b1),
        .D(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_61 ),
        .Q(calib_sel[1]),
        .R(ddr_phy_tempmon_0_n_5));
  (* syn_maxfan = "10" *) 
  FDRE \calib_sel_reg[3] 
       (.C(\dout_o_reg[15] ),
        .CE(1'b1),
        .D(ctl_lane_sel),
        .Q(calib_sel[2]),
        .R(ddr_phy_tempmon_0_n_5));
  (* syn_maxfan = "10" *) 
  FDRE \calib_sel_reg[4] 
       (.C(\dout_o_reg[15] ),
        .CE(1'b1),
        .D(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_62 ),
        .Q(calib_sel[3]),
        .R(ddr_phy_tempmon_0_n_5));
  (* syn_maxfan = "10" *) 
  FDRE \calib_zero_inputs_reg[0] 
       (.C(\dout_o_reg[15] ),
        .CE(1'b1),
        .D(ddr_phy_tempmon_0_n_4),
        .Q(calib_zero_inputs[0]),
        .R(1'b0));
  (* syn_maxfan = "10" *) 
  FDRE \calib_zero_inputs_reg[1] 
       (.C(\dout_o_reg[15] ),
        .CE(1'b1),
        .D(ddr_phy_tempmon_0_n_3),
        .Q(calib_zero_inputs[1]),
        .R(1'b0));
  (* syn_maxfan = "10" *) 
  FDRE \calib_zero_inputs_reg[2] 
       (.C(\dout_o_reg[15] ),
        .CE(1'b1),
        .D(ddr_phy_tempmon_0_n_2),
        .Q(calib_zero_inputs[2]),
        .R(1'b0));
  mig_mig_7series_v4_2_ddr_phy_prbs_rdlvl \ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl 
       (.D({\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_12 ,\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_13 ,\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_14 ,\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_15 ,\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_16 ,\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_17 }),
        .E(samples_cnt_r),
        .Q({po_stg2_wrcal_cnt,\po_stg2_wrcal_cnt_reg[2] }),
        .\bit_cnt_reg[7]_0 (\dout_o_reg[15] ),
        .\cmp_err_4to1.compare_err_f3_reg_0 (\cmp_err_4to1.compare_err_f3_reg ),
        .complex_act_start(complex_act_start),
        .complex_ocal_reset_rd_addr(complex_ocal_reset_rd_addr),
        .complex_pi_incdec_done(complex_pi_incdec_done),
        .complex_victim_inc_reg_0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_1 ),
        .dqs_found_done_r_reg(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_23 ),
        .\gen_byte_sel_div2.byte_sel_cnt_reg[0] (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_10 ),
        .\gen_byte_sel_div2.byte_sel_cnt_reg[0]_0 (u_ddr_phy_wrcal_n_3),
        .\gen_mux_rd[0].mux_rd_fall0_r1_reg[0]_0 (\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ),
        .\gen_mux_rd[0].mux_rd_fall1_r1_reg[0]_0 (\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ),
        .\gen_mux_rd[0].mux_rd_fall2_r1_reg[0]_0 (\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ),
        .\gen_mux_rd[0].mux_rd_fall3_r1_reg[0]_0 (\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ),
        .\gen_mux_rd[0].mux_rd_rise0_r1_reg[0]_0 (\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ),
        .\gen_mux_rd[0].mux_rd_rise1_r1_reg[0]_0 (\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ),
        .\gen_mux_rd[0].mux_rd_rise2_r1_reg[0]_0 (\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ),
        .\gen_mux_rd[0].mux_rd_rise3_r1_reg[0]_0 (\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ),
        .\gen_mux_rd[1].mux_rd_fall0_r1_reg[1]_0 (\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall1_r1_reg[1]_0 (\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall2_r1_reg[1]_0 (\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall3_r1_reg[1]_0 (\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise0_r1_reg[1]_0 (\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise1_r1_reg[1]_0 (\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise2_r1_reg[1]_0 (\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise3_r1_reg[1]_0 (\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ),
        .\gen_mux_rd[2].mux_rd_fall0_r1_reg[2]_0 (\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ),
        .\gen_mux_rd[2].mux_rd_fall1_r1_reg[2]_0 (\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ),
        .\gen_mux_rd[2].mux_rd_fall2_r1_reg[2]_0 (\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ),
        .\gen_mux_rd[2].mux_rd_fall3_r1_reg[2]_0 (\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ),
        .\gen_mux_rd[2].mux_rd_rise0_r1_reg[2]_0 (\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ),
        .\gen_mux_rd[2].mux_rd_rise1_r1_reg[2]_0 (\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ),
        .\gen_mux_rd[2].mux_rd_rise2_r1_reg[2]_0 (\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ),
        .\gen_mux_rd[2].mux_rd_rise3_r1_reg[2]_0 (\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ),
        .\gen_mux_rd[3].mux_rd_fall0_r1_reg[3]_0 (\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall1_r1_reg[3]_0 (\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall2_r1_reg[3]_0 (\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall3_r1_reg[3]_0 (\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise0_r1_reg[3]_0 (\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise1_r1_reg[3]_0 (\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise2_r1_reg[3]_0 (\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise3_r1_reg[3]_0 (\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ),
        .\gen_mux_rd[4].mux_rd_fall0_r1_reg[4]_0 (\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ),
        .\gen_mux_rd[4].mux_rd_fall1_r1_reg[4]_0 (\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ),
        .\gen_mux_rd[4].mux_rd_fall2_r1_reg[4]_0 (\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ),
        .\gen_mux_rd[4].mux_rd_fall3_r1_reg[4]_0 (\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ),
        .\gen_mux_rd[4].mux_rd_rise0_r1_reg[4]_0 (\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ),
        .\gen_mux_rd[4].mux_rd_rise1_r1_reg[4]_0 (\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ),
        .\gen_mux_rd[4].mux_rd_rise2_r1_reg[4]_0 (\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ),
        .\gen_mux_rd[4].mux_rd_rise3_r1_reg[4]_0 (\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ),
        .\gen_mux_rd[5].mux_rd_fall0_r1_reg[5]_0 (\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall1_r1_reg[5]_0 (\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall2_r1_reg[5]_0 (\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall3_r1_reg[5]_0 (\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise0_r1_reg[5]_0 (\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise1_r1_reg[5]_0 (\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise2_r1_reg[5]_0 (\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise3_r1_reg[5]_0 (\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ),
        .\gen_mux_rd[6].mux_rd_fall0_r1_reg[6]_0 (\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ),
        .\gen_mux_rd[6].mux_rd_fall1_r1_reg[6]_0 (\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ),
        .\gen_mux_rd[6].mux_rd_fall2_r1_reg[6]_0 (\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ),
        .\gen_mux_rd[6].mux_rd_fall3_r1_reg[6]_0 (\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ),
        .\gen_mux_rd[6].mux_rd_rise0_r1_reg[6]_0 (\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ),
        .\gen_mux_rd[6].mux_rd_rise1_r1_reg[6]_0 (\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ),
        .\gen_mux_rd[6].mux_rd_rise2_r1_reg[6]_0 (\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ),
        .\gen_mux_rd[6].mux_rd_rise3_r1_reg[6]_0 (\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ),
        .\gen_mux_rd[7].mux_rd_fall0_r1_reg[7]_0 (\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall1_r1_reg[7]_0 (\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall2_r1_reg[7]_0 (\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall3_r1_reg[7]_0 (\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise0_r1_reg[7]_0 (\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise1_r1_reg[7]_0 (\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise2_r1_reg[7]_0 (\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise3_r1_reg[7]_0 (\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ),
        .\init_state_r[0]_i_27 (\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_2 ),
        .\init_state_r[0]_i_27_0 (u_ddr_phy_init_n_13),
        .\match_flag_and_reg[7]_0 (\en_cnt_div4.enable_wrlvl_cnt_reg[2] ),
        .mux_rd_valid_r0(mux_rd_valid_r0),
        .new_cnt_dqs_r_reg_0(E),
        .new_cnt_dqs_r_reg_1(u_ddr_phy_init_n_680),
        .no_err_win_detected_reg_0(po_en_stg2_f_reg),
        .num_samples_done_r(num_samples_done_r),
        .\prbs_dec_tap_cnt_reg[0]_0 (\fine_dec_cnt_reg[5] [0]),
        .\prbs_dqs_cnt_r_reg[0]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_25 ),
        .\prbs_dqs_cnt_r_reg[0]_1 (cal2_if_reset_reg),
        .\prbs_dqs_cnt_r_reg[1]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_26 ),
        .\prbs_dqs_cnt_r_reg[2]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_27 ),
        .\prbs_dqs_cnt_r_reg[3]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_28 ),
        .prbs_found_2nd_edge_r_reg_0(first_fail_detect_reg),
        .prbs_last_byte_done(prbs_last_byte_done),
        .prbs_out({prbs_out[511:504],prbs_out[447:440],prbs_out[383:376],prbs_out[319:312],prbs_out[255:248],prbs_out[191:184],prbs_out[127:120],prbs_out[63:56]}),
        .prbs_pi_stg2_f_en(prbs_pi_stg2_f_en),
        .prbs_pi_stg2_f_incdec(prbs_pi_stg2_f_incdec),
        .prbs_rdlvl_done_pulse0(prbs_rdlvl_done_pulse0),
        .prbs_rdlvl_done_r1(prbs_rdlvl_done_r1),
        .prbs_rdlvl_done_reg_0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_7 ),
        .prbs_rdlvl_done_reg_1(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_22 ),
        .prbs_rdlvl_prech_req_reg_0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_2 ),
        .prbs_rdlvl_start_r(prbs_rdlvl_start_r),
        .prbs_rdlvl_start_r_reg_0(u_ddr_phy_init_n_679),
        .prech_done(prech_done),
        .\rd_mux_sel_r_reg[2]_0 (\rd_mux_sel_r_reg[2]_0 ),
        .\rd_victim_sel_reg[0]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_19 ),
        .\rd_victim_sel_reg[1]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_20 ),
        .\rd_victim_sel_reg[2]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_18 ),
        .\rd_victim_sel_reg[2]_1 (\idelay_tap_cnt_r_reg[0][0][4] ),
        .\rdlvl_cpt_tap_cnt_reg[5]_0 (calib_sel[2]),
        .\rdlvl_cpt_tap_cnt_reg[5]_1 (\rdlvl_cpt_tap_cnt_reg[5] ),
        .\rdlvl_cpt_tap_cnt_reg[5]_2 (calib_sel[3]),
        .\rdlvl_cpt_tap_cnt_reg[5]_3 (\rdlvl_cpt_tap_cnt_reg[5]_0 ),
        .rdlvl_last_byte_done(rdlvl_last_byte_done),
        .rdlvl_stg1_done_r1(rdlvl_stg1_done_r1),
        .reset_if(reset_if),
        .reset_if_r9(reset_if_r9),
        .reset_if_r9_reg(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_29 ),
        .reset_if_reg(\not_empty_wait_cnt_reg[4] ),
        .reset_rd_addr(reset_rd_addr),
        .reset_rd_addr0(reset_rd_addr0),
        .\samples_cnt_r_reg[0]_0 (\samples_cnt_r_reg[0] ),
        .\samples_cnt_r_reg[11]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_11 ));
  mig_mig_7series_v4_2_ddr_phy_rdlvl \ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl 
       (.D({\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_12 ,\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_13 ,\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_14 ,\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_15 ,\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_16 ,\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_17 }),
        .E(rd_active_r),
        .Q(\rd_mux_sel_r_reg[1] ),
        .SR({\FSM_onehot_cal1_state_r_reg[7] ,\corse_inc_reg[6][2] [0]}),
        .\cal1_cnt_cpt_r_reg[0]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_23 ),
        .\cal1_cnt_cpt_r_reg[0]_1 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_24 ),
        .\cal1_cnt_cpt_r_reg[2]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_15 ),
        .\cal1_cnt_cpt_r_reg[2]_1 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_22 ),
        .cal1_dq_idel_ce_reg_0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_25 ),
        .cal1_dq_idel_ce_reg_1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_27 ),
        .cal1_dq_idel_ce_reg_2(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_28 ),
        .\cnt_shift_r_reg[0]_0 (\cnt_shift_r_reg[0] ),
        .\done_cnt_reg[2]_0 (\idelay_tap_cnt_r_reg[0][4][4] ),
        .dqs_found_prech_req(dqs_found_prech_req),
        .dqs_po_dec_done(dqs_po_dec_done),
        .found_second_edge_r_reg_0(first_fail_detect_reg),
        .\gen_byte_sel_div2.byte_sel_cnt_reg[0] (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_25 ),
        .\gen_byte_sel_div2.byte_sel_cnt_reg[0]_0 (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_47 ),
        .\gen_byte_sel_div2.byte_sel_cnt_reg[1] (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_26 ),
        .\gen_byte_sel_div2.byte_sel_cnt_reg[1]_0 (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_48 ),
        .\gen_byte_sel_div2.byte_sel_cnt_reg[2] (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_27 ),
        .\gen_byte_sel_div2.byte_sel_cnt_reg[2]_0 (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_10 ),
        .\gen_byte_sel_div2.byte_sel_cnt_reg[3] (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_28 ),
        .\gen_byte_sel_div2.byte_sel_cnt_reg[3]_0 (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_5 ),
        .\gen_byte_sel_div2.byte_sel_cnt_reg[3]_1 (dqs_count_r),
        .\gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0 (\gen_mux_rd[0].mux_rd_fall0_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0 (\gen_mux_rd[0].mux_rd_fall1_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0 (\gen_mux_rd[0].mux_rd_fall2_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0 (\gen_mux_rd[0].mux_rd_fall3_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 (\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0 (\gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0 (\gen_mux_rd[0].mux_rd_rise2_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0 (\gen_mux_rd[0].mux_rd_rise3_r_reg[0] ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ),
        .\gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0 (\gen_mux_rd[2].mux_rd_fall0_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0 (\gen_mux_rd[2].mux_rd_fall1_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0 (\gen_mux_rd[2].mux_rd_fall2_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 (\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 (\gen_mux_rd[2].mux_rd_rise0_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0 (\gen_mux_rd[2].mux_rd_rise1_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0 (\gen_mux_rd[2].mux_rd_rise2_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0 (\gen_mux_rd[2].mux_rd_rise3_r_reg[2] ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ),
        .\gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0 (\gen_mux_rd[4].mux_rd_fall0_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0 (\gen_mux_rd[4].mux_rd_fall1_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0 (\gen_mux_rd[4].mux_rd_fall2_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0 (\gen_mux_rd[4].mux_rd_fall3_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0 (\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0 (\gen_mux_rd[4].mux_rd_rise1_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0 (\gen_mux_rd[4].mux_rd_rise2_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0 (\gen_mux_rd[4].mux_rd_rise3_r_reg[4] ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_rise0_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ),
        .\gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0 (\gen_mux_rd[6].mux_rd_fall0_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0 (\gen_mux_rd[6].mux_rd_fall1_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0 (\gen_mux_rd[6].mux_rd_fall2_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0 (\gen_mux_rd[6].mux_rd_fall3_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0 (\gen_mux_rd[6].mux_rd_rise0_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0 (\gen_mux_rd[6].mux_rd_rise1_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0 (\gen_mux_rd[6].mux_rd_rise2_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0 (\gen_mux_rd[6].mux_rd_rise3_r_reg[6] ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_rise0_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ),
        .idelay_ce_int(idelay_ce_int),
        .idelay_inc_int(idelay_inc_int),
        .\idelay_tap_cnt_r_reg[0][0][4]_0 (u_ddr_phy_wrcal_n_30),
        .\idelay_tap_cnt_r_reg[0][1][4]_0 (u_ddr_phy_wrcal_n_34),
        .\idelay_tap_cnt_r_reg[0][2][4]_0 (u_ddr_phy_wrcal_n_35),
        .\idelay_tap_cnt_r_reg[0][3][4]_0 (u_ddr_phy_wrcal_n_36),
        .\idelay_tap_cnt_r_reg[0][4][4]_0 (u_ddr_phy_wrcal_n_29),
        .\idelay_tap_cnt_r_reg[0][5][4]_0 (u_ddr_phy_wrcal_n_31),
        .\idelay_tap_cnt_r_reg[0][6][4]_0 (u_ddr_phy_wrcal_n_32),
        .\idelay_tap_cnt_r_reg[0][7][4]_0 (u_ddr_phy_wrcal_n_33),
        .\init_state_r[1]_i_16 (u_ddr_phy_init_n_29),
        .mpr_rdlvl_start_r_reg_0(u_ddr_phy_init_n_701),
        .new_cnt_cpt_r_reg_0(new_cnt_cpt_r_reg),
        .p_1_in(p_1_in_0),
        .pi_cnt_dec_reg_0(pi_cnt_dec_reg),
        .pi_fine_dly_dec_done(pi_fine_dly_dec_done),
        .pi_stg2_f_incdec_timing_reg_0(\idelay_tap_cnt_r_reg[0][0][4] ),
        .pi_stg2_load_reg_0(pi_counter_load_en),
        .\pi_stg2_reg_l_reg[5]_0 (pi_counter_load_val),
        .prech_done(prech_done),
        .prech_req(prech_req),
        .prech_req_r_reg(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_2 ),
        .prech_req_r_reg_0(u_ddr_phy_init_n_683),
        .\rd_mux_sel_r_reg[2]_0 (\rd_mux_sel_r_reg[2] ),
        .\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 (\rdlvl_dqs_tap_cnt_r_reg[0][0][2] ),
        .rdlvl_last_byte_done(rdlvl_last_byte_done),
        .rdlvl_pi_incdec(rdlvl_pi_incdec),
        .rdlvl_pi_incdec_reg_0(\dout_o_reg[15] ),
        .rdlvl_pi_stg2_f_en(rdlvl_pi_stg2_f_en),
        .rdlvl_pi_stg2_f_incdec(rdlvl_pi_stg2_f_incdec),
        .rdlvl_prech_req(rdlvl_prech_req),
        .rdlvl_stg1_done_int_reg_0(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_10 ),
        .rdlvl_stg1_done_int_reg_1(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_19 ),
        .rdlvl_stg1_done_int_reg_2(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_20 ),
        .rdlvl_stg1_done_int_reg_3(p_1_in),
        .rdlvl_stg1_done_r1(rdlvl_stg1_done_r1),
        .rdlvl_stg1_done_r1_reg(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_30 ),
        .rdlvl_stg1_rank_done(rdlvl_stg1_rank_done),
        .rdlvl_stg1_start_r_reg_0(rdlvl_stg1_start_reg),
        .\rnk_cnt_r_reg[0]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_26 ),
        .\rnk_cnt_r_reg[1]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_14 ),
        .samp_edge_cnt0_en_r(samp_edge_cnt0_en_r),
        .\samp_edge_cnt1_r_reg[0]_0 (\samp_edge_cnt1_r_reg[0] ),
        .sr_valid_r_reg_0(po_en_stg2_f_reg),
        .stg1_wr_done(stg1_wr_done),
        .\stg1_wr_rd_cnt_reg[3] (\not_empty_wait_cnt_reg[4] ),
        .\tap_cnt_cpt_r_reg[5]_0 (\tap_cnt_cpt_r_reg[5] ),
        .\wait_cnt_r_reg[0]_0 (\wait_cnt_r_reg[0]_0 ),
        .wrcal_prech_req(wrcal_prech_req),
        .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56] (u_ddr_phy_wrcal_n_3),
        .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_7 ));
  mig_mig_7series_v4_2_ddr_phy_tempmon ddr_phy_tempmon_0
       (.D({ddr_phy_tempmon_0_n_2,ddr_phy_tempmon_0_n_3,ddr_phy_tempmon_0_n_4}),
        .Q({\gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[3] ,\gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[2] }),
        .calib_complete(calib_complete),
        .calib_in_common(calib_in_common),
        .calib_in_common4_out(calib_in_common4_out),
        .calib_sel1__1(calib_sel1__1),
        .\calib_sel_reg[0] (\not_empty_wait_cnt_reg[4] ),
        .\calib_zero_inputs_reg[2] (\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_54 ),
        .cmd_delay_start0(cmd_delay_start0),
        .\device_temp_101_reg[0]_0 (first_fail_detect_reg),
        .\device_temp_101_reg[11]_0 (\device_temp_101_reg[11] ),
        .dqs_po_dec_done(dqs_po_dec_done),
        .\four_dec_min_limit_reg[0]_0 (\four_dec_min_limit_reg[0] ),
        .\gen_byte_sel_div2.calib_in_common_i_2 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_10 ),
        .\gen_byte_sel_div2.calib_in_common_i_2_0 (u_ddr_phy_wrcal_n_3),
        .\gen_byte_sel_div2.calib_in_common_i_2_1 (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_5 ),
        .\gen_byte_sel_div2.calib_in_common_i_3 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_7 ),
        .mc_ref_zq_wip(mc_ref_zq_wip),
        .\neutral_max_limit_reg[11]_0 (po_en_stg2_f_reg),
        .\one_dec_max_limit_reg[2]_0 (\one_dec_max_limit_reg[2] ),
        .\one_dec_min_limit_reg[11]_0 (\one_dec_min_limit_reg[11] ),
        .pi_f_dec_reg_0(\dout_o_reg[15] ),
        .pi_f_dec_reg_1(\victim_sel_reg[0] ),
        .pi_f_inc_reg_0(ddr_phy_tempmon_0_n_5),
        .pi_fine_dly_dec_done(pi_fine_dly_dec_done),
        .rdlvl_stg1_done_int_reg(ddr_phy_tempmon_0_n_6),
        .tempmon_pi_f_inc(tempmon_pi_f_inc),
        .tempmon_sel_pi_incdec(tempmon_sel_pi_incdec));
  mig_mig_7series_v4_2_ddr_phy_dqs_found_cal_hr \dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr 
       (.Q(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_28 ),
        .SR(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_58 ),
        .calib_in_common(calib_in_common),
        .calib_in_common4_out(calib_in_common4_out),
        .calib_sel1__1(calib_sel1__1),
        .\calib_sel_reg[0] ({\gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[3] ,\gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[2] ,\gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[0] }),
        .\calib_sel_reg[1] (\calib_sel[1]_i_3_n_0 ),
        .ck_addr_cmd_delay_done(ck_addr_cmd_delay_done),
        .ck_po_stg2_f_en(ck_po_stg2_f_en),
        .ck_po_stg2_f_indec(ck_po_stg2_f_indec),
        .cmd_delay_start0(cmd_delay_start0),
        .ctl_lane_cnt(ctl_lane_cnt),
        .\ctl_lane_cnt_reg[0]_0 (\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_57 ),
        .\ctl_lane_cnt_reg[1]_0 (\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_56 ),
        .\ctl_lane_cnt_reg[2]_0 (\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_53 ),
        .ctl_lane_sel(ctl_lane_sel),
        .delay_done_r4_reg(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_52 ),
        .delay_done_r4_reg_0(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_62 ),
        .detect_pi_found_dqs(detect_pi_found_dqs),
        .dqs_found_done_r_reg_0(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_2 ),
        .dqs_found_done_r_reg_1(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_49 ),
        .dqs_found_done_r_reg_2(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_50 ),
        .dqs_found_prech_req(dqs_found_prech_req),
        .dqs_found_start_r_reg_0(u_ddr_phy_init_n_700),
        .dqs_po_dec_done(dqs_po_dec_done),
        .fine_adjust_reg_0(fine_adjust_reg),
        .first_fail_detect_reg_0(first_fail_detect_reg),
        .\gen_byte_sel_div2.byte_sel_cnt_reg[0] (\not_empty_wait_cnt_reg[4] ),
        .\gen_byte_sel_div2.calib_in_common_reg (ddr_phy_tempmon_0_n_6),
        .\gen_byte_sel_div2.ctl_lane_sel_reg[0] (\gen_byte_sel_div2.ctl_lane_sel_reg_n_0_[0] ),
        .\gen_byte_sel_div2.ctl_lane_sel_reg[1] (\gen_byte_sel_div2.ctl_lane_sel_reg_n_0_[1] ),
        .\gen_byte_sel_div2.ctl_lane_sel_reg[2] (\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_59 ),
        .\gen_byte_sel_div2.ctl_lane_sel_reg[2]_0 (\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_61 ),
        .\gen_byte_sel_div2.ctl_lane_sel_reg[2]_1 (\gen_byte_sel_div2.ctl_lane_sel_reg_n_0_[2] ),
        .\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_10 ),
        .\gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_7 ),
        .in0(in0),
        .\init_dec_cnt_reg[4]_0 (\rdlvl_dqs_tap_cnt_r_reg[0][0][2] [0]),
        .init_dqsfound_done_r2(init_dqsfound_done_r2),
        .init_dqsfound_done_r5_reg_0(\dout_o_reg[15] ),
        .init_dqsfound_done_r_reg_0(\idelay_tap_cnt_r_reg[0][4][4] ),
        .\init_state_r[0]_i_10 (u_ddr_phy_init_n_3),
        .\init_state_r[2]_i_10 (u_ddr_phy_wrcal_n_3),
        .pi_calib_done(pi_calib_done),
        .\pi_dqs_found_any_bank_reg[0]_0 (\fine_dec_cnt_reg[5] ),
        .pi_dqs_found_done_r1(pi_dqs_found_done_r1),
        .pi_dqs_found_done_r1_reg(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_34 ),
        .pi_dqs_found_done_r1_reg_0(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_35 ),
        .pi_dqs_found_done_r1_reg_1(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_36 ),
        .pi_dqs_found_done_r1_reg_10(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_45 ),
        .pi_dqs_found_done_r1_reg_11(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_46 ),
        .pi_dqs_found_done_r1_reg_12(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_47 ),
        .pi_dqs_found_done_r1_reg_13(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_48 ),
        .pi_dqs_found_done_r1_reg_2(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_37 ),
        .pi_dqs_found_done_r1_reg_3(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_38 ),
        .pi_dqs_found_done_r1_reg_4(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_39 ),
        .pi_dqs_found_done_r1_reg_5(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_40 ),
        .pi_dqs_found_done_r1_reg_6(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_41 ),
        .pi_dqs_found_done_r1_reg_7(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_42 ),
        .pi_dqs_found_done_r1_reg_8(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_43 ),
        .pi_dqs_found_done_r1_reg_9(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_44 ),
        .pi_dqs_found_rank_done(pi_dqs_found_rank_done),
        .pi_fine_dly_dec_done(pi_fine_dly_dec_done),
        .\pi_rst_stg1_cal_r_reg[1]_0 (\pi_rst_stg1_cal_r_reg[1] ),
        .\pi_rst_stg1_cal_reg[0]_0 (\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_54 ),
        .\pi_rst_stg1_cal_reg[2]_0 (pi_rst_dqs_find),
        .prech_done(prech_done),
        .rank_done_r_reg_0(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_51 ),
        .\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0]_0 (\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0] ),
        .\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]_0 (\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] ),
        .\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 (rd_data_offset_ranks_0),
        .\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11]_0 (\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] ),
        .\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6]_0 (\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6] ),
        .\rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9]_0 (rd_data_offset_ranks_1),
        .\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][12]_0 (\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][12] ),
        .\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17]_0 (\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17] ),
        .\rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][15]_0 (rd_data_offset_ranks_2),
        .\rd_byte_data_offset_reg[0][15]_0 (\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_30 ),
        .\rd_byte_data_offset_reg[0][9]_0 (\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_29 ),
        .\stable_pass_cnt_reg[0]_0 (cal2_if_reset_reg));
  FDRE \gen_byte_sel_div2.byte_sel_cnt_reg[0] 
       (.C(\dout_o_reg[15] ),
        .CE(\mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_7 ),
        .D(p_1_in[0]),
        .Q(\gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[0] ),
        .R(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_58 ));
  FDRE \gen_byte_sel_div2.byte_sel_cnt_reg[1] 
       (.C(\dout_o_reg[15] ),
        .CE(\mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_7 ),
        .D(p_1_in[1]),
        .Q(\gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[1] ),
        .R(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_58 ));
  FDRE \gen_byte_sel_div2.byte_sel_cnt_reg[2] 
       (.C(\dout_o_reg[15] ),
        .CE(\mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_7 ),
        .D(p_1_in[2]),
        .Q(\gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[2] ),
        .R(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_58 ));
  FDRE \gen_byte_sel_div2.byte_sel_cnt_reg[3] 
       (.C(\dout_o_reg[15] ),
        .CE(\mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_7 ),
        .D(p_1_in[3]),
        .Q(\gen_byte_sel_div2.byte_sel_cnt_reg_n_0_[3] ),
        .R(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_58 ));
  (* syn_maxfan = "10" *) 
  FDRE \gen_byte_sel_div2.calib_in_common_reg 
       (.C(\dout_o_reg[15] ),
        .CE(1'b1),
        .D(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_52 ),
        .Q(calib_in_common),
        .R(\corse_inc_reg[6][2] [0]));
  FDRE \gen_byte_sel_div2.ctl_lane_sel_reg[0] 
       (.C(\dout_o_reg[15] ),
        .CE(1'b1),
        .D(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_57 ),
        .Q(\gen_byte_sel_div2.ctl_lane_sel_reg_n_0_[0] ),
        .R(\corse_inc_reg[6][2] [0]));
  FDRE \gen_byte_sel_div2.ctl_lane_sel_reg[1] 
       (.C(\dout_o_reg[15] ),
        .CE(1'b1),
        .D(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_56 ),
        .Q(\gen_byte_sel_div2.ctl_lane_sel_reg_n_0_[1] ),
        .R(\corse_inc_reg[6][2] [0]));
  FDRE \gen_byte_sel_div2.ctl_lane_sel_reg[2] 
       (.C(\dout_o_reg[15] ),
        .CE(1'b1),
        .D(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_53 ),
        .Q(\gen_byte_sel_div2.ctl_lane_sel_reg_n_0_[2] ),
        .R(\corse_inc_reg[6][2] [0]));
  FDRE idelay_ce_r1_reg
       (.C(\dout_o_reg[15] ),
        .CE(1'b1),
        .D(idelay_ce_int),
        .Q(idelay_ce_r1),
        .R(\corse_inc_reg[6][2] [0]));
  FDRE idelay_ce_r2_reg
       (.C(\dout_o_reg[15] ),
        .CE(1'b1),
        .D(idelay_ce_r1),
        .Q(idelay_ce),
        .R(\corse_inc_reg[6][2] [0]));
  FDRE idelay_inc_r1_reg
       (.C(\dout_o_reg[15] ),
        .CE(1'b1),
        .D(idelay_inc_int),
        .Q(idelay_inc_r1),
        .R(\corse_inc_reg[6][2] [0]));
  (* syn_maxfan = "30" *) 
  FDRE idelay_inc_r2_reg
       (.C(\dout_o_reg[15] ),
        .CE(1'b1),
        .D(idelay_inc_r1),
        .Q(idelay_inc),
        .R(\corse_inc_reg[6][2] [0]));
  (* ORIG_CELL_NAME = "init_calib_complete_reg" *) 
  FDRE init_calib_complete_reg
       (.C(\dout_o_reg[15] ),
        .CE(1'b1),
        .D(calib_complete),
        .Q(d_in[13]),
        .R(1'b0));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  (* ORIG_CELL_NAME = "init_calib_complete_reg" *) 
  FDRE init_calib_complete_reg_rep
       (.C(\dout_o_reg[15] ),
        .CE(1'b1),
        .D(calib_complete),
        .Q(init_calib_complete_reg_rep_0),
        .R(1'b0));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  (* ORIG_CELL_NAME = "init_calib_complete_reg" *) 
  FDRE init_calib_complete_reg_rep__0
       (.C(\dout_o_reg[15] ),
        .CE(1'b1),
        .D(calib_complete),
        .Q(init_calib_complete_reg_rep__0_0),
        .R(1'b0));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  (* ORIG_CELL_NAME = "init_calib_complete_reg" *) 
  (* RTL_MAX_FANOUT = "found" *) 
  (* syn_maxfan = "10" *) 
  FDRE init_calib_complete_reg_rep__1
       (.C(\dout_o_reg[15] ),
        .CE(1'b1),
        .D(calib_complete),
        .Q(init_calib_complete_reg_rep__1_n_0),
        .R(1'b0));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  (* ORIG_CELL_NAME = "init_calib_complete_reg" *) 
  (* RTL_MAX_FANOUT = "found" *) 
  (* syn_maxfan = "10" *) 
  FDRE init_calib_complete_reg_rep__10
       (.C(\dout_o_reg[15] ),
        .CE(1'b1),
        .D(calib_complete),
        .Q(init_calib_complete_reg_rep__10_n_0),
        .R(1'b0));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  (* ORIG_CELL_NAME = "init_calib_complete_reg" *) 
  FDRE init_calib_complete_reg_rep__11
       (.C(\dout_o_reg[15] ),
        .CE(1'b1),
        .D(calib_complete),
        .Q(init_calib_complete_reg_rep__11_0),
        .R(1'b0));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  (* ORIG_CELL_NAME = "init_calib_complete_reg" *) 
  FDRE init_calib_complete_reg_rep__12
       (.C(\dout_o_reg[15] ),
        .CE(1'b1),
        .D(calib_complete),
        .Q(init_calib_complete_reg_rep__12_0),
        .R(1'b0));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  (* ORIG_CELL_NAME = "init_calib_complete_reg" *) 
  (* RTL_MAX_FANOUT = "found" *) 
  (* syn_maxfan = "10" *) 
  FDRE init_calib_complete_reg_rep__13
       (.C(\dout_o_reg[15] ),
        .CE(1'b1),
        .D(calib_complete),
        .Q(init_calib_complete_reg_rep__13_n_0),
        .R(1'b0));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  (* ORIG_CELL_NAME = "init_calib_complete_reg" *) 
  (* RTL_MAX_FANOUT = "found" *) 
  (* syn_maxfan = "10" *) 
  FDRE init_calib_complete_reg_rep__14
       (.C(\dout_o_reg[15] ),
        .CE(1'b1),
        .D(calib_complete),
        .Q(init_calib_complete_reg_rep__14_n_0),
        .R(1'b0));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  (* ORIG_CELL_NAME = "init_calib_complete_reg" *) 
  (* RTL_MAX_FANOUT = "found" *) 
  (* syn_maxfan = "10" *) 
  FDRE init_calib_complete_reg_rep__15
       (.C(\dout_o_reg[15] ),
        .CE(1'b1),
        .D(calib_complete),
        .Q(init_calib_complete_reg_rep__15_n_0),
        .R(1'b0));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  (* ORIG_CELL_NAME = "init_calib_complete_reg" *) 
  (* RTL_MAX_FANOUT = "found" *) 
  (* syn_maxfan = "10" *) 
  FDRE init_calib_complete_reg_rep__16
       (.C(\dout_o_reg[15] ),
        .CE(1'b1),
        .D(calib_complete),
        .Q(init_calib_complete_reg_rep__16_n_0),
        .R(1'b0));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  (* ORIG_CELL_NAME = "init_calib_complete_reg" *) 
  (* RTL_MAX_FANOUT = "found" *) 
  (* syn_maxfan = "10" *) 
  FDRE init_calib_complete_reg_rep__17
       (.C(\dout_o_reg[15] ),
        .CE(1'b1),
        .D(calib_complete),
        .Q(init_calib_complete_reg_rep__17_n_0),
        .R(1'b0));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  (* ORIG_CELL_NAME = "init_calib_complete_reg" *) 
  (* RTL_MAX_FANOUT = "found" *) 
  (* syn_maxfan = "10" *) 
  FDRE init_calib_complete_reg_rep__18
       (.C(\dout_o_reg[15] ),
        .CE(1'b1),
        .D(calib_complete),
        .Q(init_calib_complete_reg_rep__18_n_0),
        .R(1'b0));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  (* ORIG_CELL_NAME = "init_calib_complete_reg" *) 
  (* RTL_MAX_FANOUT = "found" *) 
  (* syn_maxfan = "10" *) 
  FDRE init_calib_complete_reg_rep__19
       (.C(\dout_o_reg[15] ),
        .CE(1'b1),
        .D(calib_complete),
        .Q(init_calib_complete_reg_rep__19_n_0),
        .R(1'b0));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  (* ORIG_CELL_NAME = "init_calib_complete_reg" *) 
  (* RTL_MAX_FANOUT = "found" *) 
  (* syn_maxfan = "10" *) 
  FDRE init_calib_complete_reg_rep__2
       (.C(\dout_o_reg[15] ),
        .CE(1'b1),
        .D(calib_complete),
        .Q(init_calib_complete_reg_rep__2_n_0),
        .R(1'b0));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  (* ORIG_CELL_NAME = "init_calib_complete_reg" *) 
  (* RTL_MAX_FANOUT = "found" *) 
  (* syn_maxfan = "10" *) 
  FDRE init_calib_complete_reg_rep__20
       (.C(\dout_o_reg[15] ),
        .CE(1'b1),
        .D(calib_complete),
        .Q(init_calib_complete_reg_rep__20_n_0),
        .R(1'b0));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  (* ORIG_CELL_NAME = "init_calib_complete_reg" *) 
  (* RTL_MAX_FANOUT = "found" *) 
  (* syn_maxfan = "10" *) 
  FDRE init_calib_complete_reg_rep__21
       (.C(\dout_o_reg[15] ),
        .CE(1'b1),
        .D(calib_complete),
        .Q(init_calib_complete_reg_rep__21_n_0),
        .R(1'b0));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  (* ORIG_CELL_NAME = "init_calib_complete_reg" *) 
  (* RTL_MAX_FANOUT = "found" *) 
  (* syn_maxfan = "10" *) 
  FDRE init_calib_complete_reg_rep__22
       (.C(\dout_o_reg[15] ),
        .CE(1'b1),
        .D(calib_complete),
        .Q(init_calib_complete_reg_rep__22_n_0),
        .R(1'b0));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  (* ORIG_CELL_NAME = "init_calib_complete_reg" *) 
  (* RTL_MAX_FANOUT = "found" *) 
  (* syn_maxfan = "10" *) 
  FDRE init_calib_complete_reg_rep__23
       (.C(\dout_o_reg[15] ),
        .CE(1'b1),
        .D(calib_complete),
        .Q(init_calib_complete_reg_rep__23_n_0),
        .R(1'b0));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  (* ORIG_CELL_NAME = "init_calib_complete_reg" *) 
  FDRE init_calib_complete_reg_rep__24
       (.C(\dout_o_reg[15] ),
        .CE(1'b1),
        .D(calib_complete),
        .Q(init_calib_complete_reg_rep__24_0),
        .R(1'b0));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  (* ORIG_CELL_NAME = "init_calib_complete_reg" *) 
  FDRE init_calib_complete_reg_rep__25
       (.C(\dout_o_reg[15] ),
        .CE(1'b1),
        .D(calib_complete),
        .Q(init_calib_complete_reg_rep__25_0),
        .R(1'b0));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  (* ORIG_CELL_NAME = "init_calib_complete_reg" *) 
  FDRE init_calib_complete_reg_rep__26
       (.C(\dout_o_reg[15] ),
        .CE(1'b1),
        .D(calib_complete),
        .Q(init_calib_complete_reg_rep__26_0),
        .R(1'b0));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  (* ORIG_CELL_NAME = "init_calib_complete_reg" *) 
  (* RTL_MAX_FANOUT = "found" *) 
  (* syn_maxfan = "10" *) 
  FDRE init_calib_complete_reg_rep__3
       (.C(\dout_o_reg[15] ),
        .CE(1'b1),
        .D(calib_complete),
        .Q(init_calib_complete_reg_rep__3_n_0),
        .R(1'b0));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  (* ORIG_CELL_NAME = "init_calib_complete_reg" *) 
  (* RTL_MAX_FANOUT = "found" *) 
  (* syn_maxfan = "10" *) 
  FDRE init_calib_complete_reg_rep__4
       (.C(\dout_o_reg[15] ),
        .CE(1'b1),
        .D(calib_complete),
        .Q(init_calib_complete_reg_rep__4_n_0),
        .R(1'b0));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  (* ORIG_CELL_NAME = "init_calib_complete_reg" *) 
  (* RTL_MAX_FANOUT = "found" *) 
  (* syn_maxfan = "10" *) 
  FDRE init_calib_complete_reg_rep__5
       (.C(\dout_o_reg[15] ),
        .CE(1'b1),
        .D(calib_complete),
        .Q(init_calib_complete_reg_rep__5_n_0),
        .R(1'b0));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  (* ORIG_CELL_NAME = "init_calib_complete_reg" *) 
  (* RTL_MAX_FANOUT = "found" *) 
  (* syn_maxfan = "10" *) 
  FDRE init_calib_complete_reg_rep__6
       (.C(\dout_o_reg[15] ),
        .CE(1'b1),
        .D(calib_complete),
        .Q(init_calib_complete_reg_rep__6_n_0),
        .R(1'b0));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  (* ORIG_CELL_NAME = "init_calib_complete_reg" *) 
  (* RTL_MAX_FANOUT = "found" *) 
  (* syn_maxfan = "10" *) 
  FDRE init_calib_complete_reg_rep__7
       (.C(\dout_o_reg[15] ),
        .CE(1'b1),
        .D(calib_complete),
        .Q(init_calib_complete_reg_rep__7_n_0),
        .R(1'b0));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  (* ORIG_CELL_NAME = "init_calib_complete_reg" *) 
  (* RTL_MAX_FANOUT = "found" *) 
  (* syn_maxfan = "10" *) 
  FDRE init_calib_complete_reg_rep__8
       (.C(\dout_o_reg[15] ),
        .CE(1'b1),
        .D(calib_complete),
        .Q(init_calib_complete_reg_rep__8_n_0),
        .R(1'b0));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  (* ORIG_CELL_NAME = "init_calib_complete_reg" *) 
  (* RTL_MAX_FANOUT = "found" *) 
  (* syn_maxfan = "10" *) 
  FDRE init_calib_complete_reg_rep__9
       (.C(\dout_o_reg[15] ),
        .CE(1'b1),
        .D(calib_complete),
        .Q(init_calib_complete_reg_rep__9_n_0),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair621" *) 
  LUT5 #(
    .INIT(32'h0000F010)) 
    \input_[1].iserdes_dq_.idelay_dq.idelaye2_i_1 
       (.I0(calib_sel[1]),
        .I1(calib_sel[0]),
        .I2(idelay_ce),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[0]),
        .O(\calib_sel_reg[1]_3 ));
  (* SOFT_HLUTNM = "soft_lutpair623" *) 
  LUT5 #(
    .INIT(32'h0000F010)) 
    \input_[1].iserdes_dq_.idelay_dq.idelaye2_i_1__0 
       (.I0(calib_sel[1]),
        .I1(calib_sel[0]),
        .I2(idelay_ce),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[2]),
        .O(\calib_sel_reg[1]_27 ));
  (* SOFT_HLUTNM = "soft_lutpair621" *) 
  LUT5 #(
    .INIT(32'h0000CC40)) 
    \input_[2].iserdes_dq_.idelay_dq.idelaye2_i_1 
       (.I0(calib_sel[1]),
        .I1(idelay_ce),
        .I2(calib_sel[0]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[0]),
        .O(\calib_sel_reg[1]_12 ));
  (* SOFT_HLUTNM = "soft_lutpair622" *) 
  LUT5 #(
    .INIT(32'h0000CC08)) 
    \input_[2].iserdes_dq_.idelay_dq.idelaye2_i_1__0 
       (.I0(calib_sel[1]),
        .I1(idelay_ce),
        .I2(calib_sel[0]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[0]),
        .O(\calib_sel_reg[1]_18 ));
  (* SOFT_HLUTNM = "soft_lutpair622" *) 
  LUT5 #(
    .INIT(32'h0000AA80)) 
    \input_[2].iserdes_dq_.idelay_dq.idelaye2_i_1__1 
       (.I0(idelay_ce),
        .I1(calib_sel[0]),
        .I2(calib_sel[1]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[0]),
        .O(idelay_ce_r2_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair623" *) 
  LUT5 #(
    .INIT(32'h0000CC40)) 
    \input_[2].iserdes_dq_.idelay_dq.idelaye2_i_1__2 
       (.I0(calib_sel[1]),
        .I1(idelay_ce),
        .I2(calib_sel[0]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[2]),
        .O(\calib_sel_reg[1]_36 ));
  (* SOFT_HLUTNM = "soft_lutpair624" *) 
  LUT5 #(
    .INIT(32'h0000CC08)) 
    \input_[2].iserdes_dq_.idelay_dq.idelaye2_i_1__3 
       (.I0(calib_sel[1]),
        .I1(idelay_ce),
        .I2(calib_sel[0]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[2]),
        .O(\calib_sel_reg[1]_42 ));
  (* SOFT_HLUTNM = "soft_lutpair624" *) 
  LUT5 #(
    .INIT(32'h0000AA80)) 
    \input_[2].iserdes_dq_.idelay_dq.idelaye2_i_1__4 
       (.I0(idelay_ce),
        .I1(calib_sel[0]),
        .I2(calib_sel[1]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[2]),
        .O(idelay_ce_r2_reg_1));
  mig_mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay \mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay 
       (.E(\mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay_n_7 ),
        .SS(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_50 ),
        .ck_addr_cmd_delay_done(ck_addr_cmd_delay_done),
        .cmd_delay_start0(cmd_delay_start0),
        .cmd_po_en_stg2_f(cmd_po_en_stg2_f),
        .ctl_lane_cnt(ctl_lane_cnt),
        .\ctl_lane_cnt_reg[1]_0 (\idelay_tap_cnt_r_reg[0][4][4] ),
        .delay_done_r4_reg_0(\dout_o_reg[15] ),
        .delaydec_cnt_r10_in(delaydec_cnt_r10_in),
        .dqs_po_dec_done(dqs_po_dec_done),
        .\gen_byte_sel_div2.byte_sel_cnt_reg[0] (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_5 ),
        .\gen_byte_sel_div2.byte_sel_cnt_reg[0]_0 (u_ddr_phy_wrcal_n_3),
        .\gen_byte_sel_div2.byte_sel_cnt_reg[0]_1 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_7 ),
        .\gen_byte_sel_div2.byte_sel_cnt_reg[0]_2 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_10 ),
        .p_1_in(p_1_in_0),
        .pi_fine_dly_dec_done(pi_fine_dly_dec_done),
        .po_cnt_dec_2(po_cnt_dec_2),
        .po_en_stg2_f_reg_0(po_en_stg2_f_reg),
        .tempmon_sel_pi_incdec(tempmon_sel_pi_incdec),
        .\wait_cnt_r_reg[0]_0 (\wait_cnt_r_reg[0] ));
  mig_mig_7series_v4_2_ddr_phy_wrlvl \mb_wrlvl_inst.u_ddr_phy_wrlvl 
       (.C_po_coarse_enable26_out(C_po_coarse_enable26_out),
        .C_po_fine_enable23_out(C_po_fine_enable23_out),
        .C_po_fine_inc29_out(C_po_fine_inc29_out),
        .\FSM_sequential_wl_state_r_reg[0]_0 (u_ddr_phy_init_n_677),
        .\FSM_sequential_wl_state_r_reg[2]_0 (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_46 ),
        .\FSM_sequential_wl_state_r_reg[4]_0 (wl_state_r__0),
        .Q(Q),
        .SS(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_50 ),
        .calib_in_common(calib_in_common),
        .\calib_sel_reg[0] (\calib_sel_reg[0]_1 ),
        .\calib_sel_reg[0]_0 (\calib_sel_reg[0]_5 ),
        .\calib_sel_reg[1] (\calib_sel_reg[1]_2 ),
        .\calib_sel_reg[1]_0 (\calib_sel_reg[1]_4 ),
        .\calib_sel_reg[1]_1 (\calib_sel_reg[1]_8 ),
        .\calib_sel_reg[1]_10 (\calib_sel_reg[1]_43 ),
        .\calib_sel_reg[1]_2 (\calib_sel_reg[1]_10 ),
        .\calib_sel_reg[1]_3 (\calib_sel_reg[1]_13 ),
        .\calib_sel_reg[1]_4 (\calib_sel_reg[1]_19 ),
        .\calib_sel_reg[1]_5 (\calib_sel_reg[1]_26 ),
        .\calib_sel_reg[1]_6 (\calib_sel_reg[1]_28 ),
        .\calib_sel_reg[1]_7 (\calib_sel_reg[1]_32 ),
        .\calib_sel_reg[1]_8 (\calib_sel_reg[1]_34 ),
        .\calib_sel_reg[1]_9 (\calib_sel_reg[1]_37 ),
        .ck_po_stg2_f_indec(ck_po_stg2_f_indec),
        .cmd_delay_start0(cmd_delay_start0),
        .\corse_cnt_reg[3][0]_0 (u_ddr_phy_wrcal_n_23),
        .\corse_cnt_reg[4][0]_0 (u_ddr_phy_wrcal_n_25),
        .\corse_cnt_reg[5][0]_0 (u_ddr_phy_wrcal_n_26),
        .\corse_cnt_reg[6][0]_0 (u_ddr_phy_wrcal_n_27),
        .\corse_cnt_reg[7][0]_0 (u_ddr_phy_wrcal_n_8),
        .\corse_cnt_reg[7][0]_1 (u_ddr_phy_wrcal_n_28),
        .\corse_dec_reg[7][0]_0 (\corse_dec_reg[7][0] ),
        .\corse_inc_reg[6][2]_0 (\corse_inc_reg[6][2] ),
        .delaydec_cnt_r10_in(delaydec_cnt_r10_in),
        .done_dqs_dec238_out(done_dqs_dec238_out),
        .done_dqs_tap_inc(done_dqs_tap_inc),
        .\dqs_count_r_reg[0]_rep_0 (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_47 ),
        .\dqs_count_r_reg[1]_rep_0 (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_48 ),
        .\dqs_count_r_reg[2]_rep__0_0 (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_10 ),
        .\dqs_count_r_reg[2]_rep__0_1 (\dout_o_reg[15] ),
        .\dqs_count_r_reg[2]_rep__0_2 (cal2_if_reset_reg),
        .\dqs_count_r_reg[3]_0 (dqs_count_r),
        .\dqs_count_r_reg[3]_1 ({po_stg2_wrcal_cnt,\po_stg2_wrcal_cnt_reg[2] }),
        .dqs_po_dec_done(dqs_po_dec_done),
        .dqs_po_en_stg2_f(dqs_po_en_stg2_f),
        .dqs_po_stg2_f_incdec_reg_0(dqs_po_stg2_f_incdec_reg),
        .dqs_po_stg2_f_incdec_reg_1(dqs_po_stg2_f_incdec_reg_0),
        .dqs_po_stg2_f_incdec_reg_2(dqs_po_stg2_f_incdec_reg_1),
        .dqs_po_stg2_f_incdec_reg_3(dqs_po_stg2_f_incdec_reg_2),
        .dqs_po_stg2_f_incdec_reg_4(dqs_po_stg2_f_incdec_reg_3),
        .dqs_po_stg2_f_incdec_reg_5(dqs_po_stg2_f_incdec_reg_4),
        .dqs_po_stg2_f_incdec_reg_6(dqs_po_stg2_f_incdec_reg_5),
        .dqs_po_stg2_f_incdec_reg_7(dqs_po_stg2_f_incdec_reg_6),
        .dqs_po_stg2_f_incdec_reg_8(dqs_po_stg2_f_incdec_reg_7),
        .dqs_po_stg2_f_incdec_reg_9(dqs_po_stg2_f_incdec_reg_8),
        .dqs_wl_po_stg2_c_incdec_reg_0(dqs_wl_po_stg2_c_incdec_reg),
        .dqs_wl_po_stg2_c_incdec_reg_1(dqs_wl_po_stg2_c_incdec_reg_0),
        .\fine_dec_cnt_reg[5]_0 (\fine_dec_cnt_reg[5] [1]),
        .\fine_inc_reg[6][3]_0 (\fine_inc_reg[6][3] ),
        .\gen_byte_sel_div2.calib_in_common_reg (\gen_byte_sel_div2.calib_in_common_reg_0 ),
        .\gen_byte_sel_div2.calib_in_common_reg_0 (\gen_byte_sel_div2.calib_in_common_reg_1 ),
        .\gen_byte_sel_div2.calib_in_common_reg_1 (\gen_byte_sel_div2.calib_in_common_reg_2 ),
        .\gen_byte_sel_div2.calib_in_common_reg_2 (\gen_byte_sel_div2.calib_in_common_reg_3 ),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0]_0 (\gen_rd[0].rd_data_rise_wl_r_reg[0] ),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0]_1 (\gen_rd[0].rd_data_rise_wl_r_reg[0]_0 ),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0]_2 (\gen_rd[0].rd_data_rise_wl_r_reg[0]_1 ),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0]_3 (\gen_rd[0].rd_data_rise_wl_r_reg[0]_2 ),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0]_4 (\gen_rd[0].rd_data_rise_wl_r_reg[0]_3 ),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0]_5 (\gen_rd[0].rd_data_rise_wl_r_reg[0]_4 ),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0]_6 (\gen_rd[0].rd_data_rise_wl_r_reg[0]_5 ),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0]_7 (\gen_rd[0].rd_data_rise_wl_r_reg[0]_6 ),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1]_0 (\gen_rd[1].rd_data_rise_wl_r_reg[1] ),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1]_1 (\gen_rd[1].rd_data_rise_wl_r_reg[1]_0 ),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1]_2 (\gen_rd[1].rd_data_rise_wl_r_reg[1]_1 ),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1]_3 (\gen_rd[1].rd_data_rise_wl_r_reg[1]_2 ),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1]_4 (\gen_rd[1].rd_data_rise_wl_r_reg[1]_3 ),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1]_5 (\gen_rd[1].rd_data_rise_wl_r_reg[1]_4 ),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1]_6 (\gen_rd[1].rd_data_rise_wl_r_reg[1]_5 ),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1]_7 (\gen_rd[1].rd_data_rise_wl_r_reg[1]_6 ),
        .\gen_rd[2].rd_data_rise_wl_r_reg[2]_0 (\gen_rd[2].rd_data_rise_wl_r_reg[2] ),
        .\gen_rd[2].rd_data_rise_wl_r_reg[2]_1 (\gen_rd[2].rd_data_rise_wl_r_reg[2]_0 ),
        .\gen_rd[2].rd_data_rise_wl_r_reg[2]_2 (\gen_rd[2].rd_data_rise_wl_r_reg[2]_1 ),
        .\gen_rd[2].rd_data_rise_wl_r_reg[2]_3 (\gen_rd[2].rd_data_rise_wl_r_reg[2]_2 ),
        .\gen_rd[2].rd_data_rise_wl_r_reg[2]_4 (\gen_rd[2].rd_data_rise_wl_r_reg[2]_3 ),
        .\gen_rd[2].rd_data_rise_wl_r_reg[2]_5 (\gen_rd[2].rd_data_rise_wl_r_reg[2]_4 ),
        .\gen_rd[2].rd_data_rise_wl_r_reg[2]_6 (\gen_rd[2].rd_data_rise_wl_r_reg[2]_5 ),
        .\gen_rd[2].rd_data_rise_wl_r_reg[2]_7 (\gen_rd[2].rd_data_rise_wl_r_reg[2]_6 ),
        .\gen_rd[3].rd_data_rise_wl_r_reg[3]_0 (\gen_rd[3].rd_data_rise_wl_r_reg[3] ),
        .\gen_rd[3].rd_data_rise_wl_r_reg[3]_1 (\gen_rd[3].rd_data_rise_wl_r_reg[3]_0 ),
        .\gen_rd[3].rd_data_rise_wl_r_reg[3]_2 (\gen_rd[3].rd_data_rise_wl_r_reg[3]_1 ),
        .\gen_rd[3].rd_data_rise_wl_r_reg[3]_3 (\gen_rd[3].rd_data_rise_wl_r_reg[3]_2 ),
        .\gen_rd[3].rd_data_rise_wl_r_reg[3]_4 (\gen_rd[3].rd_data_rise_wl_r_reg[3]_3 ),
        .\gen_rd[3].rd_data_rise_wl_r_reg[3]_5 (\gen_rd[3].rd_data_rise_wl_r_reg[3]_4 ),
        .\gen_rd[3].rd_data_rise_wl_r_reg[3]_6 (\gen_rd[3].rd_data_rise_wl_r_reg[3]_5 ),
        .\gen_rd[3].rd_data_rise_wl_r_reg[3]_7 (\gen_rd[3].rd_data_rise_wl_r_reg[3]_6 ),
        .\gen_rd[4].rd_data_rise_wl_r_reg[4]_0 (\gen_rd[4].rd_data_rise_wl_r_reg[4] ),
        .\gen_rd[4].rd_data_rise_wl_r_reg[4]_1 (\gen_rd[4].rd_data_rise_wl_r_reg[4]_0 ),
        .\gen_rd[4].rd_data_rise_wl_r_reg[4]_2 (\gen_rd[4].rd_data_rise_wl_r_reg[4]_1 ),
        .\gen_rd[4].rd_data_rise_wl_r_reg[4]_3 (\gen_rd[4].rd_data_rise_wl_r_reg[4]_2 ),
        .\gen_rd[4].rd_data_rise_wl_r_reg[4]_4 (\gen_rd[4].rd_data_rise_wl_r_reg[4]_3 ),
        .\gen_rd[4].rd_data_rise_wl_r_reg[4]_5 (\gen_rd[4].rd_data_rise_wl_r_reg[4]_4 ),
        .\gen_rd[4].rd_data_rise_wl_r_reg[4]_6 (\gen_rd[4].rd_data_rise_wl_r_reg[4]_5 ),
        .\gen_rd[4].rd_data_rise_wl_r_reg[4]_7 (\gen_rd[4].rd_data_rise_wl_r_reg[4]_6 ),
        .\gen_rd[5].rd_data_rise_wl_r_reg[5]_0 (\gen_rd[5].rd_data_rise_wl_r_reg[5] ),
        .\gen_rd[5].rd_data_rise_wl_r_reg[5]_1 (\gen_rd[5].rd_data_rise_wl_r_reg[5]_0 ),
        .\gen_rd[5].rd_data_rise_wl_r_reg[5]_2 (\gen_rd[5].rd_data_rise_wl_r_reg[5]_1 ),
        .\gen_rd[5].rd_data_rise_wl_r_reg[5]_3 (\gen_rd[5].rd_data_rise_wl_r_reg[5]_2 ),
        .\gen_rd[5].rd_data_rise_wl_r_reg[5]_4 (\gen_rd[5].rd_data_rise_wl_r_reg[5]_3 ),
        .\gen_rd[5].rd_data_rise_wl_r_reg[5]_5 (\gen_rd[5].rd_data_rise_wl_r_reg[5]_4 ),
        .\gen_rd[5].rd_data_rise_wl_r_reg[5]_6 (\gen_rd[5].rd_data_rise_wl_r_reg[5]_5 ),
        .\gen_rd[5].rd_data_rise_wl_r_reg[5]_7 (\gen_rd[5].rd_data_rise_wl_r_reg[5]_6 ),
        .\gen_rd[6].rd_data_rise_wl_r_reg[6]_0 (\gen_rd[6].rd_data_rise_wl_r_reg[6] ),
        .\gen_rd[6].rd_data_rise_wl_r_reg[6]_1 (\gen_rd[6].rd_data_rise_wl_r_reg[6]_0 ),
        .\gen_rd[6].rd_data_rise_wl_r_reg[6]_2 (\gen_rd[6].rd_data_rise_wl_r_reg[6]_1 ),
        .\gen_rd[6].rd_data_rise_wl_r_reg[6]_3 (\gen_rd[6].rd_data_rise_wl_r_reg[6]_2 ),
        .\gen_rd[6].rd_data_rise_wl_r_reg[6]_4 (\gen_rd[6].rd_data_rise_wl_r_reg[6]_3 ),
        .\gen_rd[6].rd_data_rise_wl_r_reg[6]_5 (\gen_rd[6].rd_data_rise_wl_r_reg[6]_4 ),
        .\gen_rd[6].rd_data_rise_wl_r_reg[6]_6 (\gen_rd[6].rd_data_rise_wl_r_reg[6]_5 ),
        .\gen_rd[6].rd_data_rise_wl_r_reg[6]_7 (\gen_rd[6].rd_data_rise_wl_r_reg[6]_6 ),
        .\gen_rd[7].rd_data_rise_wl_r_reg[7]_0 (\gen_rd[7].rd_data_rise_wl_r_reg[7] ),
        .\gen_rd[7].rd_data_rise_wl_r_reg[7]_1 (\gen_rd[7].rd_data_rise_wl_r_reg[7]_0 ),
        .\gen_rd[7].rd_data_rise_wl_r_reg[7]_2 (\gen_rd[7].rd_data_rise_wl_r_reg[7]_1 ),
        .\gen_rd[7].rd_data_rise_wl_r_reg[7]_3 (\gen_rd[7].rd_data_rise_wl_r_reg[7]_2 ),
        .\gen_rd[7].rd_data_rise_wl_r_reg[7]_4 (\gen_rd[7].rd_data_rise_wl_r_reg[7]_3 ),
        .\gen_rd[7].rd_data_rise_wl_r_reg[7]_5 (\gen_rd[7].rd_data_rise_wl_r_reg[7]_4 ),
        .\gen_rd[7].rd_data_rise_wl_r_reg[7]_6 (\gen_rd[7].rd_data_rise_wl_r_reg[7]_5 ),
        .\gen_rd[7].rd_data_rise_wl_r_reg[7]_7 (\gen_rd[7].rd_data_rise_wl_r_reg[7]_6 ),
        .phaser_out(calib_sel[1]),
        .phaser_out_0(calib_sel[0]),
        .phaser_out_1(calib_zero_inputs),
        .pi_fine_dly_dec_done(pi_fine_dly_dec_done),
        .po_cnt_dec_reg_0(po_cnt_dec_reg),
        .po_enstg2_f(po_enstg2_f),
        .\po_rdval_cnt_reg[0]_0 (\po_rdval_cnt_reg[0] ),
        .\po_rdval_cnt_reg[1]_0 (\po_rdval_cnt_reg[1] ),
        .\po_rdval_cnt_reg[2]_0 (\po_rdval_cnt_reg[2] ),
        .\po_rdval_cnt_reg[3]_0 (\po_rdval_cnt_reg[3] ),
        .\po_rdval_cnt_reg[4]_0 (\po_rdval_cnt_reg[4] ),
        .\po_rdval_cnt_reg[5]_0 (\po_rdval_cnt_reg[5] ),
        .\po_rdval_cnt_reg[6]_0 (\po_rdval_cnt_reg[6] ),
        .\po_rdval_cnt_reg[7]_0 (\po_rdval_cnt_reg[7] ),
        .\po_rdval_cnt_reg[8]_0 (\po_rdval_cnt_reg[8] ),
        .\po_stg2_wrcal_cnt_reg[2] (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_44 ),
        .\po_stg2_wrcal_cnt_reg[2]_0 (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_45 ),
        .\single_rank.done_dqs_dec_reg_0 (\idelay_tap_cnt_r_reg[0][4][4] ),
        .\wait_cnt_reg[0]_0 (SS),
        .\wl_dqs_tap_count_r_reg[0][5][5]_0 (\wl_dqs_tap_count_r_reg[0][5][5] ),
        .wl_sm_start(wl_sm_start),
        .wr_level_done_r5(wr_level_done_r5),
        .wr_level_done_reg_0(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_5 ),
        .wr_level_start_r_reg_0(u_ddr_phy_init_n_15),
        .wrlvl_byte_done(wrlvl_byte_done),
        .wrlvl_byte_redo(wrlvl_byte_redo),
        .wrlvl_byte_redo_r(wrlvl_byte_redo_r),
        .wrlvl_rank_done(wrlvl_rank_done),
        .\wrlvl_redo_corse_inc[2]_i_4_0 (u_ddr_phy_wrcal_n_24),
        .\wrlvl_redo_corse_inc_reg[2]_0 (u_ddr_phy_wrcal_n_6));
  LUT1 #(
    .INIT(2'h1)) 
    mc_read_idle_r_i_1
       (.I0(init_calib_complete_reg_rep__26_0),
        .O(init_calib_complete_reg_rep__26_1));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_0_5_i_2
       (.I0(init_calib_complete_reg_rep__25_0),
        .I1(mem_reg_0_15_12_17[520]),
        .O(\write_buffer.wr_buf_out_data_reg[455] [1]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_0_5_i_2__0
       (.I0(init_calib_complete_reg_rep__25_0),
        .I1(mem_reg_0_15_12_17[524]),
        .O(\write_buffer.wr_buf_out_data_reg[487] [1]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_0_5_i_3
       (.I0(init_calib_complete_reg_rep__25_0),
        .I1(mem_reg_0_15_12_17[512]),
        .O(\write_buffer.wr_buf_out_data_reg[455] [0]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_0_5_i_3__0
       (.I0(init_calib_complete_reg_rep__25_0),
        .I1(mem_reg_0_15_12_17[516]),
        .O(\write_buffer.wr_buf_out_data_reg[487] [0]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_0_5_i_4
       (.I0(init_calib_complete_reg_rep__25_0),
        .I1(mem_reg_0_15_12_17[536]),
        .O(\write_buffer.wr_buf_out_data_reg[455] [3]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_0_5_i_4__0
       (.I0(init_calib_complete_reg_rep__25_0),
        .I1(mem_reg_0_15_12_17[540]),
        .O(\write_buffer.wr_buf_out_data_reg[487] [3]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_0_5_i_5
       (.I0(init_calib_complete_reg_rep__25_0),
        .I1(mem_reg_0_15_12_17[528]),
        .O(\write_buffer.wr_buf_out_data_reg[455] [2]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_0_5_i_5__0
       (.I0(init_calib_complete_reg_rep__25_0),
        .I1(mem_reg_0_15_12_17[532]),
        .O(\write_buffer.wr_buf_out_data_reg[487] [2]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_0_5_i_6
       (.I0(init_calib_complete_reg_rep__25_0),
        .I1(mem_reg_0_15_12_17[552]),
        .O(\write_buffer.wr_buf_out_data_reg[455] [5]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_0_5_i_6__0
       (.I0(init_calib_complete_reg_rep__26_0),
        .I1(mem_reg_0_15_12_17[556]),
        .O(\write_buffer.wr_buf_out_data_reg[487] [5]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_0_5_i_7
       (.I0(init_calib_complete_reg_rep__25_0),
        .I1(mem_reg_0_15_12_17[544]),
        .O(\write_buffer.wr_buf_out_data_reg[455] [4]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_0_5_i_7__0
       (.I0(init_calib_complete_reg_rep__25_0),
        .I1(mem_reg_0_15_12_17[548]),
        .O(\write_buffer.wr_buf_out_data_reg[487] [4]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_12_17_i_1
       (.I0(init_calib_complete_reg_rep__14_n_0),
        .I1(mc_cas_n),
        .O(d_in[12]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_12_17_i_1__3
       (.I0(init_calib_complete_reg_rep__25_0),
        .I1(mem_reg_0_15_12_17[553]),
        .O(\write_buffer.wr_buf_out_data_reg[463] [5]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_12_17_i_1__4
       (.I0(init_calib_complete_reg_rep__25_0),
        .I1(mem_reg_0_15_12_17[554]),
        .O(\write_buffer.wr_buf_out_data_reg[471] [5]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_12_17_i_1__5
       (.I0(init_calib_complete_reg_rep__25_0),
        .I1(mem_reg_0_15_12_17[555]),
        .O(\write_buffer.wr_buf_out_data_reg[479] [5]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_12_17_i_1__6
       (.I0(init_calib_complete_reg_rep__26_0),
        .I1(mem_reg_0_15_12_17[557]),
        .O(\write_buffer.wr_buf_out_data_reg[495] [5]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_12_17_i_1__7
       (.I0(init_calib_complete_reg_rep__26_0),
        .I1(mem_reg_0_15_12_17[558]),
        .O(\write_buffer.wr_buf_out_data_reg[503] [5]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_12_17_i_1__8
       (.I0(init_calib_complete_reg_rep__26_0),
        .I1(mem_reg_0_15_12_17[559]),
        .O(\write_buffer.wr_buf_out_data_reg[511] [5]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_12_17_i_2__2
       (.I0(init_calib_complete_reg_rep__25_0),
        .I1(mem_reg_0_15_12_17[545]),
        .O(\write_buffer.wr_buf_out_data_reg[463] [4]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_12_17_i_2__3
       (.I0(init_calib_complete_reg_rep__25_0),
        .I1(mem_reg_0_15_12_17[546]),
        .O(\write_buffer.wr_buf_out_data_reg[471] [4]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_12_17_i_2__4
       (.I0(init_calib_complete_reg_rep__25_0),
        .I1(mem_reg_0_15_12_17[547]),
        .O(\write_buffer.wr_buf_out_data_reg[479] [4]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_12_17_i_2__5
       (.I0(init_calib_complete_reg_rep__25_0),
        .I1(mem_reg_0_15_12_17[549]),
        .O(\write_buffer.wr_buf_out_data_reg[495] [4]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_12_17_i_2__6
       (.I0(init_calib_complete_reg_rep__25_0),
        .I1(mem_reg_0_15_12_17[550]),
        .O(\write_buffer.wr_buf_out_data_reg[503] [4]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_12_17_i_2__7
       (.I0(init_calib_complete_reg_rep__25_0),
        .I1(mem_reg_0_15_12_17[551]),
        .O(\write_buffer.wr_buf_out_data_reg[511] [4]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_12_17_i_3__1
       (.I0(init_calib_complete_reg_rep__26_0),
        .I1(mem_reg_0_15_12_17[569]),
        .O(\write_buffer.wr_buf_out_data_reg[463] [7]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_12_17_i_3__2
       (.I0(init_calib_complete_reg_rep__26_0),
        .I1(mem_reg_0_15_12_17[570]),
        .O(\write_buffer.wr_buf_out_data_reg[471] [7]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_12_17_i_3__3
       (.I0(init_calib_complete_reg_rep__26_0),
        .I1(mem_reg_0_15_12_17[571]),
        .O(\write_buffer.wr_buf_out_data_reg[479] [7]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_12_17_i_3__4
       (.I0(init_calib_complete_reg_rep__26_0),
        .I1(mem_reg_0_15_12_17[573]),
        .O(\write_buffer.wr_buf_out_data_reg[495] [7]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_12_17_i_3__5
       (.I0(init_calib_complete_reg_rep__26_0),
        .I1(mem_reg_0_15_12_17[574]),
        .O(\write_buffer.wr_buf_out_data_reg[503] [7]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_12_17_i_3__6
       (.I0(init_calib_complete_reg_rep__26_0),
        .I1(mem_reg_0_15_12_17[575]),
        .O(\write_buffer.wr_buf_out_data_reg[511] [7]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_12_17_i_4__1
       (.I0(init_calib_complete_reg_rep__26_0),
        .I1(mem_reg_0_15_12_17[561]),
        .O(\write_buffer.wr_buf_out_data_reg[463] [6]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_12_17_i_4__2
       (.I0(init_calib_complete_reg_rep__26_0),
        .I1(mem_reg_0_15_12_17[562]),
        .O(\write_buffer.wr_buf_out_data_reg[471] [6]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_12_17_i_4__3
       (.I0(init_calib_complete_reg_rep__26_0),
        .I1(mem_reg_0_15_12_17[563]),
        .O(\write_buffer.wr_buf_out_data_reg[479] [6]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_12_17_i_4__4
       (.I0(init_calib_complete_reg_rep__26_0),
        .I1(mem_reg_0_15_12_17[565]),
        .O(\write_buffer.wr_buf_out_data_reg[495] [6]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_12_17_i_4__5
       (.I0(init_calib_complete_reg_rep__26_0),
        .I1(mem_reg_0_15_12_17[566]),
        .O(\write_buffer.wr_buf_out_data_reg[503] [6]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_12_17_i_4__6
       (.I0(init_calib_complete_reg_rep__26_0),
        .I1(mem_reg_0_15_12_17[567]),
        .O(\write_buffer.wr_buf_out_data_reg[511] [6]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_6_11_i_1__0
       (.I0(init_calib_complete_reg_rep__25_0),
        .I1(mem_reg_0_15_12_17[521]),
        .O(\write_buffer.wr_buf_out_data_reg[463] [1]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_6_11_i_1__1
       (.I0(init_calib_complete_reg_rep__25_0),
        .I1(mem_reg_0_15_12_17[522]),
        .O(\write_buffer.wr_buf_out_data_reg[471] [1]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_6_11_i_1__2
       (.I0(init_calib_complete_reg_rep__25_0),
        .I1(mem_reg_0_15_12_17[523]),
        .O(\write_buffer.wr_buf_out_data_reg[479] [1]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_6_11_i_1__3
       (.I0(init_calib_complete_reg_rep__25_0),
        .I1(mem_reg_0_15_12_17[525]),
        .O(\write_buffer.wr_buf_out_data_reg[495] [1]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_6_11_i_1__4
       (.I0(init_calib_complete_reg_rep__25_0),
        .I1(mem_reg_0_15_12_17[526]),
        .O(\write_buffer.wr_buf_out_data_reg[503] [1]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_6_11_i_1__5
       (.I0(init_calib_complete_reg_rep__25_0),
        .I1(mem_reg_0_15_12_17[527]),
        .O(\write_buffer.wr_buf_out_data_reg[511] [1]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_6_11_i_1__6
       (.I0(init_calib_complete_reg_rep__26_0),
        .I1(mem_reg_0_15_12_17[568]),
        .O(\write_buffer.wr_buf_out_data_reg[455] [7]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_6_11_i_1__7
       (.I0(init_calib_complete_reg_rep__26_0),
        .I1(mem_reg_0_15_12_17[572]),
        .O(\write_buffer.wr_buf_out_data_reg[487] [7]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_6_11_i_2__0
       (.I0(init_calib_complete_reg_rep__25_0),
        .I1(mem_reg_0_15_12_17[513]),
        .O(\write_buffer.wr_buf_out_data_reg[463] [0]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_6_11_i_2__1
       (.I0(init_calib_complete_reg_rep__25_0),
        .I1(mem_reg_0_15_12_17[514]),
        .O(\write_buffer.wr_buf_out_data_reg[471] [0]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_6_11_i_2__2
       (.I0(init_calib_complete_reg_rep__25_0),
        .I1(mem_reg_0_15_12_17[515]),
        .O(\write_buffer.wr_buf_out_data_reg[479] [0]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_6_11_i_2__3
       (.I0(init_calib_complete_reg_rep__25_0),
        .I1(mem_reg_0_15_12_17[517]),
        .O(\write_buffer.wr_buf_out_data_reg[495] [0]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_6_11_i_2__4
       (.I0(init_calib_complete_reg_rep__25_0),
        .I1(mem_reg_0_15_12_17[518]),
        .O(\write_buffer.wr_buf_out_data_reg[503] [0]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_6_11_i_2__5
       (.I0(init_calib_complete_reg_rep__25_0),
        .I1(mem_reg_0_15_12_17[519]),
        .O(\write_buffer.wr_buf_out_data_reg[511] [0]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_6_11_i_2__6
       (.I0(init_calib_complete_reg_rep__26_0),
        .I1(mem_reg_0_15_12_17[560]),
        .O(\write_buffer.wr_buf_out_data_reg[455] [6]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_6_11_i_2__7
       (.I0(init_calib_complete_reg_rep__26_0),
        .I1(mem_reg_0_15_12_17[564]),
        .O(\write_buffer.wr_buf_out_data_reg[487] [6]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_6_11_i_3__2
       (.I0(init_calib_complete_reg_rep__25_0),
        .I1(mem_reg_0_15_12_17[537]),
        .O(\write_buffer.wr_buf_out_data_reg[463] [3]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_6_11_i_3__3
       (.I0(init_calib_complete_reg_rep__25_0),
        .I1(mem_reg_0_15_12_17[538]),
        .O(\write_buffer.wr_buf_out_data_reg[471] [3]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_6_11_i_3__4
       (.I0(init_calib_complete_reg_rep__25_0),
        .I1(mem_reg_0_15_12_17[539]),
        .O(\write_buffer.wr_buf_out_data_reg[479] [3]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_6_11_i_3__5
       (.I0(init_calib_complete_reg_rep__25_0),
        .I1(mem_reg_0_15_12_17[541]),
        .O(\write_buffer.wr_buf_out_data_reg[495] [3]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_6_11_i_3__6
       (.I0(init_calib_complete_reg_rep__25_0),
        .I1(mem_reg_0_15_12_17[542]),
        .O(\write_buffer.wr_buf_out_data_reg[503] [3]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_6_11_i_3__7
       (.I0(init_calib_complete_reg_rep__25_0),
        .I1(mem_reg_0_15_12_17[543]),
        .O(\write_buffer.wr_buf_out_data_reg[511] [3]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_6_11_i_4__2
       (.I0(init_calib_complete_reg_rep__25_0),
        .I1(mem_reg_0_15_12_17[529]),
        .O(\write_buffer.wr_buf_out_data_reg[463] [2]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_6_11_i_4__3
       (.I0(init_calib_complete_reg_rep__25_0),
        .I1(mem_reg_0_15_12_17[530]),
        .O(\write_buffer.wr_buf_out_data_reg[471] [2]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_6_11_i_4__4
       (.I0(init_calib_complete_reg_rep__25_0),
        .I1(mem_reg_0_15_12_17[531]),
        .O(\write_buffer.wr_buf_out_data_reg[479] [2]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_6_11_i_4__5
       (.I0(init_calib_complete_reg_rep__25_0),
        .I1(mem_reg_0_15_12_17[533]),
        .O(\write_buffer.wr_buf_out_data_reg[495] [2]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_6_11_i_4__6
       (.I0(init_calib_complete_reg_rep__25_0),
        .I1(mem_reg_0_15_12_17[534]),
        .O(\write_buffer.wr_buf_out_data_reg[503] [2]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_6_11_i_4__7
       (.I0(init_calib_complete_reg_rep__25_0),
        .I1(mem_reg_0_15_12_17[535]),
        .O(\write_buffer.wr_buf_out_data_reg[511] [2]));
  (* SOFT_HLUTNM = "soft_lutpair629" *) 
  LUT5 #(
    .INIT(32'h0000F010)) 
    \phaser_in_gen.phaser_in_i_1 
       (.I0(calib_sel[1]),
        .I1(calib_sel[0]),
        .I2(\pi_dqs_found_lanes_r1_reg[0]_0 ),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[0]),
        .O(\calib_sel_reg[1]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair646" *) 
  LUT5 #(
    .INIT(32'h0000F010)) 
    \phaser_in_gen.phaser_in_i_10 
       (.I0(calib_sel[1]),
        .I1(calib_sel[0]),
        .I2(\pi_dqs_found_lanes_r1_reg[0]_1 [1]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[0]),
        .O(COUNTERLOADVAL[1]));
  (* SOFT_HLUTNM = "soft_lutpair646" *) 
  LUT5 #(
    .INIT(32'h0000CC40)) 
    \phaser_in_gen.phaser_in_i_10__0 
       (.I0(calib_sel[1]),
        .I1(\pi_dqs_found_lanes_r1_reg[0]_1 [1]),
        .I2(calib_sel[0]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[0]),
        .O(\calib_sel_reg[1]_48 [1]));
  (* SOFT_HLUTNM = "soft_lutpair651" *) 
  LUT5 #(
    .INIT(32'h0000CC08)) 
    \phaser_in_gen.phaser_in_i_10__1 
       (.I0(calib_sel[1]),
        .I1(\pi_dqs_found_lanes_r1_reg[0]_1 [1]),
        .I2(calib_sel[0]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[0]),
        .O(\calib_sel_reg[1]_49 [1]));
  (* SOFT_HLUTNM = "soft_lutpair651" *) 
  LUT5 #(
    .INIT(32'h0000AA80)) 
    \phaser_in_gen.phaser_in_i_10__2 
       (.I0(\pi_dqs_found_lanes_r1_reg[0]_1 [1]),
        .I1(calib_sel[0]),
        .I2(calib_sel[1]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[0]),
        .O(\pi_stg2_reg_l_reg[5] [1]));
  (* SOFT_HLUTNM = "soft_lutpair633" *) 
  LUT5 #(
    .INIT(32'h0000F010)) 
    \phaser_in_gen.phaser_in_i_10__3 
       (.I0(calib_sel[1]),
        .I1(calib_sel[0]),
        .I2(\pi_dqs_found_lanes_r1_reg[0]_1 [1]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[2]),
        .O(\calib_sel_reg[1]_50 [1]));
  (* SOFT_HLUTNM = "soft_lutpair639" *) 
  LUT5 #(
    .INIT(32'h0000CC40)) 
    \phaser_in_gen.phaser_in_i_10__4 
       (.I0(calib_sel[1]),
        .I1(\pi_dqs_found_lanes_r1_reg[0]_1 [1]),
        .I2(calib_sel[0]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[2]),
        .O(\calib_sel_reg[1]_51 [1]));
  (* SOFT_HLUTNM = "soft_lutpair639" *) 
  LUT5 #(
    .INIT(32'h0000CC08)) 
    \phaser_in_gen.phaser_in_i_10__5 
       (.I0(calib_sel[1]),
        .I1(\pi_dqs_found_lanes_r1_reg[0]_1 [1]),
        .I2(calib_sel[0]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[2]),
        .O(\calib_sel_reg[1]_52 [1]));
  (* SOFT_HLUTNM = "soft_lutpair633" *) 
  LUT5 #(
    .INIT(32'h0000AA80)) 
    \phaser_in_gen.phaser_in_i_10__6 
       (.I0(\pi_dqs_found_lanes_r1_reg[0]_1 [1]),
        .I1(calib_sel[0]),
        .I2(calib_sel[1]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[2]),
        .O(\pi_stg2_reg_l_reg[5]_0 [1]));
  (* SOFT_HLUTNM = "soft_lutpair647" *) 
  LUT5 #(
    .INIT(32'h0000F010)) 
    \phaser_in_gen.phaser_in_i_11 
       (.I0(calib_sel[1]),
        .I1(calib_sel[0]),
        .I2(\pi_dqs_found_lanes_r1_reg[0]_1 [0]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[0]),
        .O(COUNTERLOADVAL[0]));
  (* SOFT_HLUTNM = "soft_lutpair647" *) 
  LUT5 #(
    .INIT(32'h0000CC40)) 
    \phaser_in_gen.phaser_in_i_11__0 
       (.I0(calib_sel[1]),
        .I1(\pi_dqs_found_lanes_r1_reg[0]_1 [0]),
        .I2(calib_sel[0]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[0]),
        .O(\calib_sel_reg[1]_48 [0]));
  (* SOFT_HLUTNM = "soft_lutpair650" *) 
  LUT5 #(
    .INIT(32'h0000CC08)) 
    \phaser_in_gen.phaser_in_i_11__1 
       (.I0(calib_sel[1]),
        .I1(\pi_dqs_found_lanes_r1_reg[0]_1 [0]),
        .I2(calib_sel[0]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[0]),
        .O(\calib_sel_reg[1]_49 [0]));
  (* SOFT_HLUTNM = "soft_lutpair650" *) 
  LUT5 #(
    .INIT(32'h0000AA80)) 
    \phaser_in_gen.phaser_in_i_11__2 
       (.I0(\pi_dqs_found_lanes_r1_reg[0]_1 [0]),
        .I1(calib_sel[0]),
        .I2(calib_sel[1]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[0]),
        .O(\pi_stg2_reg_l_reg[5] [0]));
  (* SOFT_HLUTNM = "soft_lutpair610" *) 
  LUT5 #(
    .INIT(32'h0000F010)) 
    \phaser_in_gen.phaser_in_i_11__3 
       (.I0(calib_sel[1]),
        .I1(calib_sel[0]),
        .I2(\pi_dqs_found_lanes_r1_reg[0]_1 [0]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[2]),
        .O(\calib_sel_reg[1]_50 [0]));
  (* SOFT_HLUTNM = "soft_lutpair642" *) 
  LUT5 #(
    .INIT(32'h0000CC40)) 
    \phaser_in_gen.phaser_in_i_11__4 
       (.I0(calib_sel[1]),
        .I1(\pi_dqs_found_lanes_r1_reg[0]_1 [0]),
        .I2(calib_sel[0]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[2]),
        .O(\calib_sel_reg[1]_51 [0]));
  (* SOFT_HLUTNM = "soft_lutpair642" *) 
  LUT5 #(
    .INIT(32'h0000CC08)) 
    \phaser_in_gen.phaser_in_i_11__5 
       (.I0(calib_sel[1]),
        .I1(\pi_dqs_found_lanes_r1_reg[0]_1 [0]),
        .I2(calib_sel[0]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[2]),
        .O(\calib_sel_reg[1]_52 [0]));
  (* SOFT_HLUTNM = "soft_lutpair610" *) 
  LUT5 #(
    .INIT(32'h0000AA80)) 
    \phaser_in_gen.phaser_in_i_11__6 
       (.I0(\pi_dqs_found_lanes_r1_reg[0]_1 [0]),
        .I1(calib_sel[0]),
        .I2(calib_sel[1]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[2]),
        .O(\pi_stg2_reg_l_reg[5]_0 [0]));
  (* SOFT_HLUTNM = "soft_lutpair629" *) 
  LUT5 #(
    .INIT(32'h0000CC40)) 
    \phaser_in_gen.phaser_in_i_1__0 
       (.I0(calib_sel[1]),
        .I1(\pi_dqs_found_lanes_r1_reg[0]_0 ),
        .I2(calib_sel[0]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[0]),
        .O(\calib_sel_reg[1]_17 ));
  (* SOFT_HLUTNM = "soft_lutpair630" *) 
  LUT5 #(
    .INIT(32'h0000CC08)) 
    \phaser_in_gen.phaser_in_i_1__1 
       (.I0(calib_sel[1]),
        .I1(\pi_dqs_found_lanes_r1_reg[0]_0 ),
        .I2(calib_sel[0]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[0]),
        .O(\calib_sel_reg[1]_23 ));
  (* SOFT_HLUTNM = "soft_lutpair630" *) 
  LUT5 #(
    .INIT(32'h0000AA80)) 
    \phaser_in_gen.phaser_in_i_1__2 
       (.I0(\pi_dqs_found_lanes_r1_reg[0]_0 ),
        .I1(calib_sel[0]),
        .I2(calib_sel[1]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[0]),
        .O(pi_stg2_load_reg));
  (* SOFT_HLUTNM = "soft_lutpair631" *) 
  LUT5 #(
    .INIT(32'h0000F010)) 
    \phaser_in_gen.phaser_in_i_1__3 
       (.I0(calib_sel[1]),
        .I1(calib_sel[0]),
        .I2(\pi_dqs_found_lanes_r1_reg[0]_0 ),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[2]),
        .O(\calib_sel_reg[1]_31 ));
  (* SOFT_HLUTNM = "soft_lutpair631" *) 
  LUT5 #(
    .INIT(32'h0000CC40)) 
    \phaser_in_gen.phaser_in_i_1__4 
       (.I0(calib_sel[1]),
        .I1(\pi_dqs_found_lanes_r1_reg[0]_0 ),
        .I2(calib_sel[0]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[2]),
        .O(\calib_sel_reg[1]_41 ));
  (* SOFT_HLUTNM = "soft_lutpair632" *) 
  LUT5 #(
    .INIT(32'h0000CC08)) 
    \phaser_in_gen.phaser_in_i_1__5 
       (.I0(calib_sel[1]),
        .I1(\pi_dqs_found_lanes_r1_reg[0]_0 ),
        .I2(calib_sel[0]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[2]),
        .O(\calib_sel_reg[1]_47 ));
  (* SOFT_HLUTNM = "soft_lutpair632" *) 
  LUT5 #(
    .INIT(32'h0000AA80)) 
    \phaser_in_gen.phaser_in_i_1__6 
       (.I0(\pi_dqs_found_lanes_r1_reg[0]_0 ),
        .I1(calib_sel[0]),
        .I2(calib_sel[1]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[2]),
        .O(pi_stg2_load_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair654" *) 
  LUT4 #(
    .INIT(16'h00F1)) 
    \phaser_in_gen.phaser_in_i_2 
       (.I0(calib_sel[1]),
        .I1(calib_sel[0]),
        .I2(calib_in_common),
        .I3(calib_zero_inputs[0]),
        .O(\calib_sel_reg[1]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair654" *) 
  LUT4 #(
    .INIT(16'h00F8)) 
    \phaser_in_gen.phaser_in_i_2__0 
       (.I0(calib_sel[1]),
        .I1(calib_sel[0]),
        .I2(calib_in_common),
        .I3(calib_zero_inputs[0]),
        .O(\calib_sel_reg[1]_9 ));
  (* SOFT_HLUTNM = "soft_lutpair657" *) 
  LUT4 #(
    .INIT(16'h00F2)) 
    \phaser_in_gen.phaser_in_i_2__1 
       (.I0(calib_sel[1]),
        .I1(calib_sel[0]),
        .I2(calib_in_common),
        .I3(calib_zero_inputs[0]),
        .O(\calib_sel_reg[1]_11 ));
  (* SOFT_HLUTNM = "soft_lutpair657" *) 
  LUT4 #(
    .INIT(16'h00F2)) 
    \phaser_in_gen.phaser_in_i_2__2 
       (.I0(calib_sel[0]),
        .I1(calib_sel[1]),
        .I2(calib_in_common),
        .I3(calib_zero_inputs[0]),
        .O(\calib_sel_reg[0]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair656" *) 
  LUT4 #(
    .INIT(16'h00F1)) 
    \phaser_in_gen.phaser_in_i_2__3 
       (.I0(calib_sel[1]),
        .I1(calib_sel[0]),
        .I2(calib_in_common),
        .I3(calib_zero_inputs[2]),
        .O(\calib_sel_reg[1]_24 ));
  (* SOFT_HLUTNM = "soft_lutpair656" *) 
  LUT4 #(
    .INIT(16'h00F8)) 
    \phaser_in_gen.phaser_in_i_2__4 
       (.I0(calib_sel[1]),
        .I1(calib_sel[0]),
        .I2(calib_in_common),
        .I3(calib_zero_inputs[2]),
        .O(\calib_sel_reg[1]_33 ));
  (* SOFT_HLUTNM = "soft_lutpair658" *) 
  LUT4 #(
    .INIT(16'h00F2)) 
    \phaser_in_gen.phaser_in_i_2__5 
       (.I0(calib_sel[1]),
        .I1(calib_sel[0]),
        .I2(calib_in_common),
        .I3(calib_zero_inputs[2]),
        .O(\calib_sel_reg[1]_35 ));
  (* SOFT_HLUTNM = "soft_lutpair658" *) 
  LUT4 #(
    .INIT(16'h00F2)) 
    \phaser_in_gen.phaser_in_i_2__6 
       (.I0(calib_sel[0]),
        .I1(calib_sel[1]),
        .I2(calib_in_common),
        .I3(calib_zero_inputs[2]),
        .O(\calib_sel_reg[0]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair612" *) 
  LUT5 #(
    .INIT(32'h0000F010)) 
    \phaser_in_gen.phaser_in_i_3 
       (.I0(calib_sel[1]),
        .I1(calib_sel[0]),
        .I2(out),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[0]),
        .O(\calib_sel_reg[1]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair612" *) 
  LUT5 #(
    .INIT(32'h0000CC40)) 
    \phaser_in_gen.phaser_in_i_3__0 
       (.I0(calib_sel[1]),
        .I1(out),
        .I2(calib_sel[0]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[0]),
        .O(\calib_sel_reg[1]_15 ));
  (* SOFT_HLUTNM = "soft_lutpair613" *) 
  LUT5 #(
    .INIT(32'h0000CC08)) 
    \phaser_in_gen.phaser_in_i_3__1 
       (.I0(calib_sel[1]),
        .I1(out),
        .I2(calib_sel[0]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[0]),
        .O(\calib_sel_reg[1]_21 ));
  (* SOFT_HLUTNM = "soft_lutpair613" *) 
  LUT5 #(
    .INIT(32'h0000AA80)) 
    \phaser_in_gen.phaser_in_i_3__2 
       (.I0(out),
        .I1(calib_sel[0]),
        .I2(calib_sel[1]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[0]),
        .O(\calib_sel_reg[0]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair614" *) 
  LUT5 #(
    .INIT(32'h0000F010)) 
    \phaser_in_gen.phaser_in_i_3__3 
       (.I0(calib_sel[1]),
        .I1(calib_sel[0]),
        .I2(out),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[2]),
        .O(\calib_sel_reg[1]_25 ));
  (* SOFT_HLUTNM = "soft_lutpair614" *) 
  LUT5 #(
    .INIT(32'h0000CC40)) 
    \phaser_in_gen.phaser_in_i_3__4 
       (.I0(calib_sel[1]),
        .I1(out),
        .I2(calib_sel[0]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[2]),
        .O(\calib_sel_reg[1]_39 ));
  (* SOFT_HLUTNM = "soft_lutpair615" *) 
  LUT5 #(
    .INIT(32'h0000CC08)) 
    \phaser_in_gen.phaser_in_i_3__5 
       (.I0(calib_sel[1]),
        .I1(out),
        .I2(calib_sel[0]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[2]),
        .O(\calib_sel_reg[1]_45 ));
  (* SOFT_HLUTNM = "soft_lutpair615" *) 
  LUT5 #(
    .INIT(32'h0000AA80)) 
    \phaser_in_gen.phaser_in_i_3__6 
       (.I0(out),
        .I1(calib_sel[0]),
        .I2(calib_sel[1]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[2]),
        .O(\calib_sel_reg[0]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair617" *) 
  LUT5 #(
    .INIT(32'h0000F010)) 
    \phaser_in_gen.phaser_in_i_4 
       (.I0(calib_sel[1]),
        .I1(calib_sel[0]),
        .I2(\pi_dqs_found_lanes_r1_reg[0] ),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[0]),
        .O(\calib_sel_reg[1]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair617" *) 
  LUT5 #(
    .INIT(32'h0000CC40)) 
    \phaser_in_gen.phaser_in_i_4__0 
       (.I0(calib_sel[1]),
        .I1(\pi_dqs_found_lanes_r1_reg[0] ),
        .I2(calib_sel[0]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[0]),
        .O(\calib_sel_reg[1]_16 ));
  (* SOFT_HLUTNM = "soft_lutpair618" *) 
  LUT5 #(
    .INIT(32'h0000CC08)) 
    \phaser_in_gen.phaser_in_i_4__1 
       (.I0(calib_sel[1]),
        .I1(\pi_dqs_found_lanes_r1_reg[0] ),
        .I2(calib_sel[0]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[0]),
        .O(\calib_sel_reg[1]_22 ));
  (* SOFT_HLUTNM = "soft_lutpair618" *) 
  LUT5 #(
    .INIT(32'h0000AA80)) 
    \phaser_in_gen.phaser_in_i_4__2 
       (.I0(\pi_dqs_found_lanes_r1_reg[0] ),
        .I1(calib_sel[0]),
        .I2(calib_sel[1]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[0]),
        .O(\calib_sel_reg[0]_3 ));
  (* SOFT_HLUTNM = "soft_lutpair619" *) 
  LUT5 #(
    .INIT(32'h0000F010)) 
    \phaser_in_gen.phaser_in_i_4__3 
       (.I0(calib_sel[1]),
        .I1(calib_sel[0]),
        .I2(\pi_dqs_found_lanes_r1_reg[0] ),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[2]),
        .O(\calib_sel_reg[1]_30 ));
  (* SOFT_HLUTNM = "soft_lutpair619" *) 
  LUT5 #(
    .INIT(32'h0000CC40)) 
    \phaser_in_gen.phaser_in_i_4__4 
       (.I0(calib_sel[1]),
        .I1(\pi_dqs_found_lanes_r1_reg[0] ),
        .I2(calib_sel[0]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[2]),
        .O(\calib_sel_reg[1]_40 ));
  (* SOFT_HLUTNM = "soft_lutpair620" *) 
  LUT5 #(
    .INIT(32'h0000CC08)) 
    \phaser_in_gen.phaser_in_i_4__5 
       (.I0(calib_sel[1]),
        .I1(\pi_dqs_found_lanes_r1_reg[0] ),
        .I2(calib_sel[0]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[2]),
        .O(\calib_sel_reg[1]_46 ));
  (* SOFT_HLUTNM = "soft_lutpair620" *) 
  LUT5 #(
    .INIT(32'h0000AA80)) 
    \phaser_in_gen.phaser_in_i_4__6 
       (.I0(\pi_dqs_found_lanes_r1_reg[0] ),
        .I1(calib_sel[0]),
        .I2(calib_sel[1]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[2]),
        .O(\calib_sel_reg[0]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair625" *) 
  LUT5 #(
    .INIT(32'h0000F010)) 
    \phaser_in_gen.phaser_in_i_5 
       (.I0(calib_sel[1]),
        .I1(calib_sel[0]),
        .I2(ififo_rst_reg[0]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[0]),
        .O(\calib_sel_reg[1]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair625" *) 
  LUT5 #(
    .INIT(32'h0000CC40)) 
    \phaser_in_gen.phaser_in_i_5__0 
       (.I0(calib_sel[1]),
        .I1(ififo_rst_reg[0]),
        .I2(calib_sel[0]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[0]),
        .O(\calib_sel_reg[1]_14 ));
  (* SOFT_HLUTNM = "soft_lutpair626" *) 
  LUT5 #(
    .INIT(32'h0000CC08)) 
    \phaser_in_gen.phaser_in_i_5__1 
       (.I0(calib_sel[1]),
        .I1(ififo_rst_reg[0]),
        .I2(calib_sel[0]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[0]),
        .O(\calib_sel_reg[1]_20 ));
  (* SOFT_HLUTNM = "soft_lutpair626" *) 
  LUT5 #(
    .INIT(32'h0000AA80)) 
    \phaser_in_gen.phaser_in_i_5__2 
       (.I0(ififo_rst_reg[0]),
        .I1(calib_sel[0]),
        .I2(calib_sel[1]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[0]),
        .O(\pi_rst_stg1_cal_reg[0] ));
  (* SOFT_HLUTNM = "soft_lutpair627" *) 
  LUT5 #(
    .INIT(32'h0000F010)) 
    \phaser_in_gen.phaser_in_i_5__3 
       (.I0(calib_sel[1]),
        .I1(calib_sel[0]),
        .I2(ififo_rst_reg[1]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[2]),
        .O(\calib_sel_reg[1]_29 ));
  (* SOFT_HLUTNM = "soft_lutpair627" *) 
  LUT5 #(
    .INIT(32'h0000CC40)) 
    \phaser_in_gen.phaser_in_i_5__4 
       (.I0(calib_sel[1]),
        .I1(ififo_rst_reg[1]),
        .I2(calib_sel[0]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[2]),
        .O(\calib_sel_reg[1]_38 ));
  (* SOFT_HLUTNM = "soft_lutpair628" *) 
  LUT5 #(
    .INIT(32'h0000CC08)) 
    \phaser_in_gen.phaser_in_i_5__5 
       (.I0(calib_sel[1]),
        .I1(ififo_rst_reg[1]),
        .I2(calib_sel[0]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[2]),
        .O(\calib_sel_reg[1]_44 ));
  (* SOFT_HLUTNM = "soft_lutpair628" *) 
  LUT5 #(
    .INIT(32'h0000AA80)) 
    \phaser_in_gen.phaser_in_i_5__6 
       (.I0(ififo_rst_reg[1]),
        .I1(calib_sel[0]),
        .I2(calib_sel[1]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[2]),
        .O(\pi_rst_stg1_cal_reg[2] ));
  (* SOFT_HLUTNM = "soft_lutpair641" *) 
  LUT5 #(
    .INIT(32'h0000F010)) 
    \phaser_in_gen.phaser_in_i_6 
       (.I0(calib_sel[1]),
        .I1(calib_sel[0]),
        .I2(\pi_dqs_found_lanes_r1_reg[0]_1 [5]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[0]),
        .O(COUNTERLOADVAL[5]));
  (* SOFT_HLUTNM = "soft_lutpair649" *) 
  LUT5 #(
    .INIT(32'h0000CC40)) 
    \phaser_in_gen.phaser_in_i_6__0 
       (.I0(calib_sel[1]),
        .I1(\pi_dqs_found_lanes_r1_reg[0]_1 [5]),
        .I2(calib_sel[0]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[0]),
        .O(\calib_sel_reg[1]_48 [5]));
  (* SOFT_HLUTNM = "soft_lutpair641" *) 
  LUT5 #(
    .INIT(32'h0000CC08)) 
    \phaser_in_gen.phaser_in_i_6__1 
       (.I0(calib_sel[1]),
        .I1(\pi_dqs_found_lanes_r1_reg[0]_1 [5]),
        .I2(calib_sel[0]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[0]),
        .O(\calib_sel_reg[1]_49 [5]));
  (* SOFT_HLUTNM = "soft_lutpair649" *) 
  LUT5 #(
    .INIT(32'h0000AA80)) 
    \phaser_in_gen.phaser_in_i_6__2 
       (.I0(\pi_dqs_found_lanes_r1_reg[0]_1 [5]),
        .I1(calib_sel[0]),
        .I2(calib_sel[1]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[0]),
        .O(\pi_stg2_reg_l_reg[5] [5]));
  (* SOFT_HLUTNM = "soft_lutpair635" *) 
  LUT5 #(
    .INIT(32'h0000F010)) 
    \phaser_in_gen.phaser_in_i_6__3 
       (.I0(calib_sel[1]),
        .I1(calib_sel[0]),
        .I2(\pi_dqs_found_lanes_r1_reg[0]_1 [5]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[2]),
        .O(\calib_sel_reg[1]_50 [5]));
  (* SOFT_HLUTNM = "soft_lutpair643" *) 
  LUT5 #(
    .INIT(32'h0000CC40)) 
    \phaser_in_gen.phaser_in_i_6__4 
       (.I0(calib_sel[1]),
        .I1(\pi_dqs_found_lanes_r1_reg[0]_1 [5]),
        .I2(calib_sel[0]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[2]),
        .O(\calib_sel_reg[1]_51 [5]));
  (* SOFT_HLUTNM = "soft_lutpair635" *) 
  LUT5 #(
    .INIT(32'h0000CC08)) 
    \phaser_in_gen.phaser_in_i_6__5 
       (.I0(calib_sel[1]),
        .I1(\pi_dqs_found_lanes_r1_reg[0]_1 [5]),
        .I2(calib_sel[0]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[2]),
        .O(\calib_sel_reg[1]_52 [5]));
  (* SOFT_HLUTNM = "soft_lutpair643" *) 
  LUT5 #(
    .INIT(32'h0000AA80)) 
    \phaser_in_gen.phaser_in_i_6__6 
       (.I0(\pi_dqs_found_lanes_r1_reg[0]_1 [5]),
        .I1(calib_sel[0]),
        .I2(calib_sel[1]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[2]),
        .O(\pi_stg2_reg_l_reg[5]_0 [5]));
  (* SOFT_HLUTNM = "soft_lutpair634" *) 
  LUT5 #(
    .INIT(32'h0000F010)) 
    \phaser_in_gen.phaser_in_i_7 
       (.I0(calib_sel[1]),
        .I1(calib_sel[0]),
        .I2(\pi_dqs_found_lanes_r1_reg[0]_1 [4]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[0]),
        .O(COUNTERLOADVAL[4]));
  (* SOFT_HLUTNM = "soft_lutpair648" *) 
  LUT5 #(
    .INIT(32'h0000CC40)) 
    \phaser_in_gen.phaser_in_i_7__0 
       (.I0(calib_sel[1]),
        .I1(\pi_dqs_found_lanes_r1_reg[0]_1 [4]),
        .I2(calib_sel[0]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[0]),
        .O(\calib_sel_reg[1]_48 [4]));
  (* SOFT_HLUTNM = "soft_lutpair634" *) 
  LUT5 #(
    .INIT(32'h0000CC08)) 
    \phaser_in_gen.phaser_in_i_7__1 
       (.I0(calib_sel[1]),
        .I1(\pi_dqs_found_lanes_r1_reg[0]_1 [4]),
        .I2(calib_sel[0]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[0]),
        .O(\calib_sel_reg[1]_49 [4]));
  (* SOFT_HLUTNM = "soft_lutpair648" *) 
  LUT5 #(
    .INIT(32'h0000AA80)) 
    \phaser_in_gen.phaser_in_i_7__2 
       (.I0(\pi_dqs_found_lanes_r1_reg[0]_1 [4]),
        .I1(calib_sel[0]),
        .I2(calib_sel[1]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[0]),
        .O(\pi_stg2_reg_l_reg[5] [4]));
  (* SOFT_HLUTNM = "soft_lutpair611" *) 
  LUT5 #(
    .INIT(32'h0000F010)) 
    \phaser_in_gen.phaser_in_i_7__3 
       (.I0(calib_sel[1]),
        .I1(calib_sel[0]),
        .I2(\pi_dqs_found_lanes_r1_reg[0]_1 [4]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[2]),
        .O(\calib_sel_reg[1]_50 [4]));
  (* SOFT_HLUTNM = "soft_lutpair636" *) 
  LUT5 #(
    .INIT(32'h0000CC40)) 
    \phaser_in_gen.phaser_in_i_7__4 
       (.I0(calib_sel[1]),
        .I1(\pi_dqs_found_lanes_r1_reg[0]_1 [4]),
        .I2(calib_sel[0]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[2]),
        .O(\calib_sel_reg[1]_51 [4]));
  (* SOFT_HLUTNM = "soft_lutpair636" *) 
  LUT5 #(
    .INIT(32'h0000CC08)) 
    \phaser_in_gen.phaser_in_i_7__5 
       (.I0(calib_sel[1]),
        .I1(\pi_dqs_found_lanes_r1_reg[0]_1 [4]),
        .I2(calib_sel[0]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[2]),
        .O(\calib_sel_reg[1]_52 [4]));
  (* SOFT_HLUTNM = "soft_lutpair611" *) 
  LUT5 #(
    .INIT(32'h0000AA80)) 
    \phaser_in_gen.phaser_in_i_7__6 
       (.I0(\pi_dqs_found_lanes_r1_reg[0]_1 [4]),
        .I1(calib_sel[0]),
        .I2(calib_sel[1]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[2]),
        .O(\pi_stg2_reg_l_reg[5]_0 [4]));
  (* SOFT_HLUTNM = "soft_lutpair644" *) 
  LUT5 #(
    .INIT(32'h0000F010)) 
    \phaser_in_gen.phaser_in_i_8 
       (.I0(calib_sel[1]),
        .I1(calib_sel[0]),
        .I2(\pi_dqs_found_lanes_r1_reg[0]_1 [3]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[0]),
        .O(COUNTERLOADVAL[3]));
  (* SOFT_HLUTNM = "soft_lutpair644" *) 
  LUT5 #(
    .INIT(32'h0000CC40)) 
    \phaser_in_gen.phaser_in_i_8__0 
       (.I0(calib_sel[1]),
        .I1(\pi_dqs_found_lanes_r1_reg[0]_1 [3]),
        .I2(calib_sel[0]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[0]),
        .O(\calib_sel_reg[1]_48 [3]));
  (* SOFT_HLUTNM = "soft_lutpair653" *) 
  LUT5 #(
    .INIT(32'h0000CC08)) 
    \phaser_in_gen.phaser_in_i_8__1 
       (.I0(calib_sel[1]),
        .I1(\pi_dqs_found_lanes_r1_reg[0]_1 [3]),
        .I2(calib_sel[0]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[0]),
        .O(\calib_sel_reg[1]_49 [3]));
  (* SOFT_HLUTNM = "soft_lutpair653" *) 
  LUT5 #(
    .INIT(32'h0000AA80)) 
    \phaser_in_gen.phaser_in_i_8__2 
       (.I0(\pi_dqs_found_lanes_r1_reg[0]_1 [3]),
        .I1(calib_sel[0]),
        .I2(calib_sel[1]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[0]),
        .O(\pi_stg2_reg_l_reg[5] [3]));
  (* SOFT_HLUTNM = "soft_lutpair616" *) 
  LUT5 #(
    .INIT(32'h0000F010)) 
    \phaser_in_gen.phaser_in_i_8__3 
       (.I0(calib_sel[1]),
        .I1(calib_sel[0]),
        .I2(\pi_dqs_found_lanes_r1_reg[0]_1 [3]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[2]),
        .O(\calib_sel_reg[1]_50 [3]));
  (* SOFT_HLUTNM = "soft_lutpair637" *) 
  LUT5 #(
    .INIT(32'h0000CC40)) 
    \phaser_in_gen.phaser_in_i_8__4 
       (.I0(calib_sel[1]),
        .I1(\pi_dqs_found_lanes_r1_reg[0]_1 [3]),
        .I2(calib_sel[0]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[2]),
        .O(\calib_sel_reg[1]_51 [3]));
  (* SOFT_HLUTNM = "soft_lutpair637" *) 
  LUT5 #(
    .INIT(32'h0000CC08)) 
    \phaser_in_gen.phaser_in_i_8__5 
       (.I0(calib_sel[1]),
        .I1(\pi_dqs_found_lanes_r1_reg[0]_1 [3]),
        .I2(calib_sel[0]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[2]),
        .O(\calib_sel_reg[1]_52 [3]));
  (* SOFT_HLUTNM = "soft_lutpair616" *) 
  LUT5 #(
    .INIT(32'h0000AA80)) 
    \phaser_in_gen.phaser_in_i_8__6 
       (.I0(\pi_dqs_found_lanes_r1_reg[0]_1 [3]),
        .I1(calib_sel[0]),
        .I2(calib_sel[1]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[2]),
        .O(\pi_stg2_reg_l_reg[5]_0 [3]));
  (* SOFT_HLUTNM = "soft_lutpair645" *) 
  LUT5 #(
    .INIT(32'h0000F010)) 
    \phaser_in_gen.phaser_in_i_9 
       (.I0(calib_sel[1]),
        .I1(calib_sel[0]),
        .I2(\pi_dqs_found_lanes_r1_reg[0]_1 [2]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[0]),
        .O(COUNTERLOADVAL[2]));
  (* SOFT_HLUTNM = "soft_lutpair645" *) 
  LUT5 #(
    .INIT(32'h0000CC40)) 
    \phaser_in_gen.phaser_in_i_9__0 
       (.I0(calib_sel[1]),
        .I1(\pi_dqs_found_lanes_r1_reg[0]_1 [2]),
        .I2(calib_sel[0]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[0]),
        .O(\calib_sel_reg[1]_48 [2]));
  (* SOFT_HLUTNM = "soft_lutpair652" *) 
  LUT5 #(
    .INIT(32'h0000CC08)) 
    \phaser_in_gen.phaser_in_i_9__1 
       (.I0(calib_sel[1]),
        .I1(\pi_dqs_found_lanes_r1_reg[0]_1 [2]),
        .I2(calib_sel[0]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[0]),
        .O(\calib_sel_reg[1]_49 [2]));
  (* SOFT_HLUTNM = "soft_lutpair652" *) 
  LUT5 #(
    .INIT(32'h0000AA80)) 
    \phaser_in_gen.phaser_in_i_9__2 
       (.I0(\pi_dqs_found_lanes_r1_reg[0]_1 [2]),
        .I1(calib_sel[0]),
        .I2(calib_sel[1]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[0]),
        .O(\pi_stg2_reg_l_reg[5] [2]));
  (* SOFT_HLUTNM = "soft_lutpair638" *) 
  LUT5 #(
    .INIT(32'h0000F010)) 
    \phaser_in_gen.phaser_in_i_9__3 
       (.I0(calib_sel[1]),
        .I1(calib_sel[0]),
        .I2(\pi_dqs_found_lanes_r1_reg[0]_1 [2]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[2]),
        .O(\calib_sel_reg[1]_50 [2]));
  (* SOFT_HLUTNM = "soft_lutpair640" *) 
  LUT5 #(
    .INIT(32'h0000CC40)) 
    \phaser_in_gen.phaser_in_i_9__4 
       (.I0(calib_sel[1]),
        .I1(\pi_dqs_found_lanes_r1_reg[0]_1 [2]),
        .I2(calib_sel[0]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[2]),
        .O(\calib_sel_reg[1]_51 [2]));
  (* SOFT_HLUTNM = "soft_lutpair638" *) 
  LUT5 #(
    .INIT(32'h0000CC08)) 
    \phaser_in_gen.phaser_in_i_9__5 
       (.I0(calib_sel[1]),
        .I1(\pi_dqs_found_lanes_r1_reg[0]_1 [2]),
        .I2(calib_sel[0]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[2]),
        .O(\calib_sel_reg[1]_52 [2]));
  (* SOFT_HLUTNM = "soft_lutpair640" *) 
  LUT5 #(
    .INIT(32'h0000AA80)) 
    \phaser_in_gen.phaser_in_i_9__6 
       (.I0(\pi_dqs_found_lanes_r1_reg[0]_1 [2]),
        .I1(calib_sel[0]),
        .I2(calib_sel[1]),
        .I3(calib_in_common),
        .I4(calib_zero_inputs[2]),
        .O(\pi_stg2_reg_l_reg[5]_0 [2]));
  (* SOFT_HLUTNM = "soft_lutpair655" *) 
  LUT4 #(
    .INIT(16'h0040)) 
    phaser_out_i_2__7
       (.I0(calib_in_common),
        .I1(calib_sel[1]),
        .I2(calib_sel[0]),
        .I3(calib_zero_inputs[1]),
        .O(\gen_byte_sel_div2.calib_in_common_reg_4 ));
  (* SOFT_HLUTNM = "soft_lutpair655" *) 
  LUT4 #(
    .INIT(16'h0004)) 
    phaser_out_i_2__8
       (.I0(calib_in_common),
        .I1(calib_sel[0]),
        .I2(calib_sel[1]),
        .I3(calib_zero_inputs[1]),
        .O(\gen_byte_sel_div2.calib_in_common_reg_5 ));
  (* SOFT_HLUTNM = "soft_lutpair659" *) 
  LUT4 #(
    .INIT(16'h0004)) 
    phaser_out_i_2__9
       (.I0(calib_in_common),
        .I1(calib_sel[1]),
        .I2(calib_sel[0]),
        .I3(calib_zero_inputs[1]),
        .O(C_po_counter_read_en38_out));
  LUT3 #(
    .INIT(8'hFE)) 
    phy_if_reset0
       (.I0(phy_if_reset_w),
        .I1(reset_if),
        .I2(wrlvl_final_if_rst),
        .O(phy_if_reset0__0));
  FDRE phy_if_reset_reg
       (.C(\dout_o_reg[15] ),
        .CE(1'b1),
        .D(phy_if_reset0__0),
        .Q(phy_if_reset),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hFE)) 
    pi_en_stg2_f
       (.I0(tempmon_pi_f_en_r),
        .I1(rdlvl_pi_stg2_f_en),
        .I2(prbs_pi_stg2_f_en),
        .O(pi_fine_enable));
  LUT3 #(
    .INIT(8'hFE)) 
    pi_stg2_f_incdec
       (.I0(tempmon_pi_f_inc_r),
        .I1(rdlvl_pi_stg2_f_incdec),
        .I2(prbs_pi_stg2_f_incdec),
        .O(pi_fine_inc));
  (* SOFT_HLUTNM = "soft_lutpair659" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \po_counter_read_val[8]_i_1__1 
       (.I0(calib_sel[0]),
        .I1(calib_sel[1]),
        .O(SR));
  LUT3 #(
    .INIT(8'hFE)) 
    po_en_stg2_f0
       (.I0(dqs_po_en_stg2_f),
        .I1(cmd_po_en_stg2_f),
        .I2(ck_po_stg2_f_en),
        .O(po_enstg2_f));
  FDRE prbs_rdlvl_done_r1_reg
       (.C(\dout_o_reg[15] ),
        .CE(1'b1),
        .D(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_7 ),
        .Q(prbs_rdlvl_done_r1),
        .R(1'b0));
  FDRE rdlvl_stg1_done_r1_reg
       (.C(\dout_o_reg[15] ),
        .CE(1'b1),
        .D(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_10 ),
        .Q(rdlvl_stg1_done_r1),
        .R(1'b0));
  (* srl_name = "\u_mig_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/reset_if_r8_reg_srl8 " *) 
  SRL16E reset_if_r8_reg_srl8
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(\dout_o_reg[15] ),
        .D(reset_if),
        .Q(reset_if_r8_reg_srl8_n_0));
  FDRE reset_if_r9_reg
       (.C(\dout_o_reg[15] ),
        .CE(1'b1),
        .D(reset_if_r8_reg_srl8_n_0),
        .Q(reset_if_r9),
        .R(1'b0));
  FDRE reset_if_reg
       (.C(\dout_o_reg[15] ),
        .CE(1'b1),
        .D(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_29 ),
        .Q(reset_if),
        .R(1'b0));
  FDRE tempmon_pi_f_en_r_reg
       (.C(\dout_o_reg[15] ),
        .CE(1'b1),
        .D(tempmon_sel_pi_incdec),
        .Q(tempmon_pi_f_en_r),
        .R(\corse_inc_reg[6][2] [0]));
  FDRE tempmon_pi_f_inc_r_reg
       (.C(\dout_o_reg[15] ),
        .CE(1'b1),
        .D(tempmon_pi_f_inc),
        .Q(tempmon_pi_f_inc_r),
        .R(\corse_inc_reg[6][2] [0]));
  mig_mig_7series_v4_2_ddr_phy_init u_ddr_phy_init
       (.D({sel,u_ddr_phy_init_n_22,u_ddr_phy_init_n_23,u_ddr_phy_init_n_24,u_ddr_phy_init_n_25,u_ddr_phy_init_n_26,u_ddr_phy_init_n_27,u_ddr_phy_init_n_28}),
        .D1(D1),
        .D2(D2),
        .D3(D3),
        .D4(D4),
        .D5(D5),
        .D6(D6),
        .D7(D7),
        .D8(D8),
        .D9(D9),
        .E(samples_cnt_r),
        .Q(u_ddr_phy_init_n_29),
        .SR(u_ddr_phy_init_n_689),
        .app_rd_data_valid(app_rd_data_valid),
        .app_rd_data_valid_0(app_rd_data_valid_0),
        .calib_complete(calib_complete),
        .\calib_data_offset_0_reg[0]_0 (\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_38 ),
        .\calib_data_offset_0_reg[1]_0 (\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_37 ),
        .\calib_data_offset_0_reg[2]_0 (\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_36 ),
        .\calib_data_offset_0_reg[3]_0 (rd_data_offset_ranks_0),
        .\calib_data_offset_0_reg[3]_1 (\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_28 ),
        .\calib_data_offset_0_reg[4]_0 (\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_35 ),
        .\calib_data_offset_0_reg[5]_0 (\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_34 ),
        .\calib_data_offset_1_reg[0]_0 (\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_43 ),
        .\calib_data_offset_1_reg[1]_0 (\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_42 ),
        .\calib_data_offset_1_reg[2]_0 (\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_41 ),
        .\calib_data_offset_1_reg[3]_0 (rd_data_offset_ranks_1),
        .\calib_data_offset_1_reg[3]_1 (\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_29 ),
        .\calib_data_offset_1_reg[4]_0 (\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_40 ),
        .\calib_data_offset_1_reg[5]_0 (\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_39 ),
        .\calib_data_offset_2_reg[0]_0 (\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_48 ),
        .\calib_data_offset_2_reg[1]_0 (\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_47 ),
        .\calib_data_offset_2_reg[2]_0 (\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_46 ),
        .\calib_data_offset_2_reg[3]_0 (rd_data_offset_ranks_2),
        .\calib_data_offset_2_reg[3]_1 (\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_30 ),
        .\calib_data_offset_2_reg[4]_0 (\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_45 ),
        .\calib_data_offset_2_reg[5]_0 (\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_44 ),
        .\calib_seq_reg[0]_0 (Q),
        .\calib_seq_reg[1]_0 (D),
        .ck_addr_cmd_delay_done(ck_addr_cmd_delay_done),
        .\cmd_pipe_plus.mc_cas_n_reg[1] (\cmd_pipe_plus.mc_cas_n_reg[1] ),
        .\cmd_pipe_plus.mc_cke_reg[3] (\cmd_pipe_plus.mc_cke_reg[3] ),
        .\cmd_pipe_plus.mc_cke_reg[3]_0 (\cmd_pipe_plus.mc_cke_reg[3]_0 ),
        .\cmd_pipe_plus.mc_data_offset_1_reg[5] (\cmd_pipe_plus.mc_data_offset_1_reg[5] ),
        .\cmd_pipe_plus.mc_data_offset_2_reg[5] (\cmd_pipe_plus.mc_data_offset_2_reg[5] ),
        .\cmd_pipe_plus.mc_odt_reg[0] (\cmd_pipe_plus.mc_odt_reg[0] ),
        .\cmd_pipe_plus.mc_ras_n_reg[1] (\cmd_pipe_plus.mc_ras_n_reg[1] ),
        .\cmd_pipe_plus.mc_we_n_reg[1] (\cmd_pipe_plus.mc_we_n_reg[1] ),
        .\cnt_pwron_ce_r_reg[0]_0 (cal2_if_reset_reg),
        .complex_act_start(complex_act_start),
        .\complex_num_writes_reg[1]_0 (\complex_num_writes_reg[1] ),
        .complex_ocal_reset_rd_addr(complex_ocal_reset_rd_addr),
        .complex_oclkdelay_calib_done_r1_reg_0(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_7 ),
        .complex_pi_incdec_done(complex_pi_incdec_done),
        .d_in({d_in[37:14],d_in[11:0]}),
        .\data_offset_1_i1_reg[0] (\data_offset_1_i1_reg[0] ),
        .\data_offset_1_i1_reg[1] (\data_offset_1_i1_reg[1] ),
        .\data_offset_1_i1_reg[2] (\data_offset_1_i1_reg[2] ),
        .\data_offset_1_i1_reg[4] (\data_offset_1_i1_reg[4] ),
        .\data_offset_1_i1_reg[5] (\data_offset_1_i1_reg[5] ),
        .\data_offset_2_i1_reg[0] (\data_offset_2_i1_reg[0] ),
        .\data_offset_2_i1_reg[1] (\data_offset_2_i1_reg[1] ),
        .\data_offset_2_i1_reg[2] (\data_offset_2_i1_reg[2] ),
        .\data_offset_2_i1_reg[4] (\data_offset_2_i1_reg[4] ),
        .\data_offset_2_i1_reg[5] (\data_offset_2_i1_reg[5] ),
        .ddr3_lm_done_r_reg_0(u_ddr_phy_wrcal_n_3),
        .detect_pi_found_dqs(detect_pi_found_dqs),
        .done_dqs_tap_inc(done_dqs_tap_inc),
        .dqs_found_prech_req(dqs_found_prech_req),
        .\en_cnt_div4.enable_wrlvl_cnt_reg[2]_0 (\en_cnt_div4.enable_wrlvl_cnt_reg[2] ),
        .\en_cnt_div4.enable_wrlvl_cnt_reg[4]_0 (\en_cnt_div4.enable_wrlvl_cnt_reg[4] ),
        .first_rdlvl_pat_r(first_rdlvl_pat_r),
        .first_wrcal_pat_r(first_wrcal_pat_r),
        .\gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0 (\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_49 ),
        .\gen_no_mirror.div_clk_loop[0].phy_address_reg[2]_0 (\gen_no_mirror.div_clk_loop[0].phy_address_reg[2] ),
        .\gen_no_mirror.div_clk_loop[0].phy_address_reg[8]_0 (\gen_no_mirror.div_clk_loop[0].phy_address_reg[8] ),
        .\gen_no_mirror.div_clk_loop[0].phy_address_reg[9]_0 (\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] ),
        .\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0]_0 (\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] ),
        .\gen_no_mirror.div_clk_loop[0].phy_bank_reg[1]_0 (\gen_no_mirror.div_clk_loop[0].phy_bank_reg[1] ),
        .if_empty(if_empty),
        .init_complete_r1_timing_reg_0(init_complete_r1_timing_reg),
        .init_dqsfound_done_r2(init_dqsfound_done_r2),
        .\init_state_r[0]_i_14_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_23 ),
        .\init_state_r[0]_i_4_0 (u_ddr_phy_wrcal_n_4),
        .\init_state_r[0]_i_4_1 (\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_51 ),
        .\init_state_r[1]_i_6_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_30 ),
        .\init_state_r[2]_i_3_0 (\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_50 ),
        .\init_state_r[2]_i_4_0 (u_ddr_phy_wrcal_n_37),
        .\init_state_r[3]_i_4_0 (u_ddr_phy_wrcal_n_38),
        .\init_state_r[4]_i_10_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_22 ),
        .\init_state_r[4]_i_17_0 (u_ddr_phy_wrcal_n_39),
        .\init_state_r_reg[4]_0 (\init_state_r_reg[4] ),
        .\init_state_r_reg[4]_1 (u_ddr_phy_init_n_683),
        .mc_address(mc_address),
        .mc_bank(mc_bank),
        .mc_cas_n(mc_cas_n),
        .mc_cke(mc_cke),
        .mc_cmd(mc_cmd),
        .mc_data_offset(mc_data_offset),
        .mc_data_offset_1(mc_data_offset_1),
        .mc_data_offset_2(mc_data_offset_2),
        .mc_odt(mc_odt),
        .mc_ras_n(mc_ras_n),
        .mc_we_n(mc_we_n),
        .mc_wrdata_en(mc_wrdata_en),
        .mem_out(mem_out),
        .mem_reg_0_15_18_23(init_calib_complete_reg_rep__19_n_0),
        .mem_reg_0_15_18_23_0(init_calib_complete_reg_rep__20_n_0),
        .mem_reg_0_15_36_41(init_calib_complete_reg_rep__14_n_0),
        .mem_reg_0_15_36_41_0(init_calib_complete_reg_rep__21_n_0),
        .mem_reg_0_15_36_41_1(init_calib_complete_reg_rep__22_n_0),
        .mem_reg_0_15_48_53(init_calib_complete_reg_rep__15_n_0),
        .mem_reg_0_15_54_59(init_calib_complete_reg_rep__16_n_0),
        .mem_reg_0_15_54_59_0(init_calib_complete_reg_rep__23_n_0),
        .mem_reg_0_15_66_71(init_calib_complete_reg_rep__17_n_0),
        .mem_reg_0_15_72_77(init_calib_complete_reg_rep__18_n_0),
        .mem_reg_0_15_78_79(mem_reg_0_15_12_17[511:0]),
        .mem_reg_0_15_78_79_0(init_calib_complete_reg_rep__24_0),
        .mpr_rdlvl_start_reg_0(u_ddr_phy_init_n_701),
        .mux_rd_valid_r0(mux_rd_valid_r0),
        .mux_reset_n(mux_reset_n),
        .num_samples_done_r(num_samples_done_r),
        .\one_rank.stg1_wr_done_reg_0 (u_ddr_phy_init_n_13),
        .out_fifo(out_fifo),
        .out_fifo_0(out_fifo_0),
        .out_fifo_1(out_fifo_1),
        .out_fifo_10(out_fifo_9),
        .out_fifo_11(init_calib_complete_reg_rep__10_n_0),
        .out_fifo_12(out_fifo_10),
        .out_fifo_13(out_fifo_11),
        .out_fifo_14(out_fifo_12),
        .out_fifo_15(out_fifo_13),
        .out_fifo_16(out_fifo_14),
        .out_fifo_17(out_fifo_15),
        .out_fifo_18(out_fifo_16),
        .out_fifo_19(out_fifo_17),
        .out_fifo_2(init_calib_complete_reg_rep__11_0),
        .out_fifo_20(init_calib_complete_reg_rep__9_n_0),
        .out_fifo_21(init_calib_complete_reg_rep__8_n_0),
        .out_fifo_22(init_calib_complete_reg_rep__7_n_0),
        .out_fifo_23(init_calib_complete_reg_rep__6_n_0),
        .out_fifo_24(init_calib_complete_reg_rep__5_n_0),
        .out_fifo_25(init_calib_complete_reg_rep__4_n_0),
        .out_fifo_26(init_calib_complete_reg_rep__3_n_0),
        .out_fifo_27(init_calib_complete_reg_rep__2_n_0),
        .out_fifo_28(init_calib_complete_reg_rep__1_n_0),
        .out_fifo_29(out_fifo_18),
        .out_fifo_3(out_fifo_2),
        .out_fifo_30(out_fifo_19),
        .out_fifo_31(init_calib_complete_reg_rep__0_0),
        .out_fifo_4(out_fifo_3),
        .out_fifo_5(out_fifo_4),
        .out_fifo_6(out_fifo_5),
        .out_fifo_7(out_fifo_6),
        .out_fifo_8(out_fifo_7),
        .out_fifo_9(out_fifo_8),
        .phy_cmd_wr_en(phy_cmd_wr_en),
        .\phy_ctl_wd_i1_reg[0] (init_calib_complete_reg_rep__13_n_0),
        .\phy_ctl_wd_i1_reg[17] (\phy_ctl_wd_i1_reg[17] ),
        .\phy_ctl_wd_i1_reg[18] (\phy_ctl_wd_i1_reg[18] ),
        .\phy_ctl_wd_i1_reg[19] (\phy_ctl_wd_i1_reg[19] ),
        .\phy_ctl_wd_i1_reg[21] (\phy_ctl_wd_i1_reg[21] ),
        .\phy_ctl_wd_i1_reg[22] (\phy_ctl_wd_i1_reg[22] ),
        .phy_ctl_wr_i1_reg(init_calib_complete_reg_rep__12_0),
        .phy_data_wr_en(phy_data_wr_en),
        .phy_dout(phy_dout),
        .phy_read_calib(phy_read_calib),
        .phy_write_calib(phy_write_calib),
        .pi_calib_done(pi_calib_done),
        .pi_dqs_found_done_r1(pi_dqs_found_done_r1),
        .pi_dqs_found_done_r1_reg_0(\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_2 ),
        .pi_dqs_found_rank_done(pi_dqs_found_rank_done),
        .pi_dqs_found_start_reg_0(u_ddr_phy_init_n_700),
        .pi_phase_locked_all_r1_reg_0(pi_phase_locked_all_r1_reg),
        .prbs_last_byte_done(prbs_last_byte_done),
        .prbs_out({prbs_out[508],prbs_out[504],prbs_out[383],prbs_out[379],prbs_out[318:317],prbs_out[314:313],prbs_out[254],prbs_out[250],prbs_out[189],prbs_out[185],prbs_out[127:126],prbs_out[123:122],prbs_out[63],prbs_out[60:59],prbs_out[56]}),
        .prbs_rdlvl_done_pulse0(prbs_rdlvl_done_pulse0),
        .prbs_rdlvl_done_pulse_reg_0(prbs_rdlvl_done_pulse_reg),
        .prbs_rdlvl_done_r1(prbs_rdlvl_done_r1),
        .prbs_rdlvl_done_reg(u_ddr_phy_init_n_686),
        .prbs_rdlvl_done_reg_0(u_ddr_phy_init_n_688),
        .prbs_rdlvl_start_r(prbs_rdlvl_start_r),
        .prbs_rdlvl_start_reg_0(u_ddr_phy_init_n_679),
        .prbs_rdlvl_start_reg_1(u_ddr_phy_init_n_680),
        .prbs_rdlvl_start_reg_2(\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_10 ),
        .prech_done(prech_done),
        .prech_req(prech_req),
        .prech_req_posedge_r_reg_0(u_ddr_phy_init_n_3),
        .prech_req_posedge_r_reg_1(\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_2 ),
        .\rd_addr_reg[1] (u_ddr_phy_init_n_687),
        .\rd_addr_reg[3] (u_ddr_prbs_gen_n_45),
        .\rd_addr_reg[7] (\idelay_tap_cnt_r_reg[0][0][4] ),
        .\rd_addr_reg[7]_0 (u_ddr_prbs_gen_n_0),
        .rdlvl_last_byte_done(rdlvl_last_byte_done),
        .rdlvl_pi_incdec(rdlvl_pi_incdec),
        .rdlvl_prech_req(rdlvl_prech_req),
        .\rdlvl_start_dly0_r_reg[14]_0 (\dout_o_reg[15] ),
        .rdlvl_stg1_done_r1(rdlvl_stg1_done_r1),
        .rdlvl_stg1_rank_done(rdlvl_stg1_rank_done),
        .rdlvl_stg1_start_int_reg_0(u_ddr_phy_init_n_684),
        .rdlvl_stg1_start_reg_0(rdlvl_stg1_start_reg),
        .\read_fifo.tail_r (\read_fifo.tail_r ),
        .\read_fifo.tail_r_reg[0] (\read_fifo.tail_r_reg[0] ),
        .reset_rd_addr(reset_rd_addr),
        .reset_rd_addr0(reset_rd_addr0),
        .\row_cnt_victim_rotate.complex_row_cnt_reg[1]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_19 ),
        .\row_cnt_victim_rotate.complex_row_cnt_reg[2]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_20 ),
        .\row_cnt_victim_rotate.complex_row_cnt_reg[3]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_18 ),
        .\row_cnt_victim_rotate.complex_row_cnt_reg[6]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_1 ),
        .\samples_cnt_r_reg[11] (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_11 ),
        .stg1_wr_done(stg1_wr_done),
        .\stg1_wr_rd_cnt_reg[3]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_19 ),
        .\victim_sel_reg[0]_0 (\victim_sel_reg[0] ),
        .wl_sm_start(wl_sm_start),
        .wl_sm_start_reg_0(u_ddr_phy_init_n_677),
        .wr_level_done_r5(wr_level_done_r5),
        .wr_lvl_start_reg_0(u_ddr_phy_init_n_15),
        .wrcal_prech_req(wrcal_prech_req),
        .wrcal_rd_wait(wrcal_rd_wait),
        .wrcal_resume_w(wrcal_resume_w),
        .wrcal_sanity_chk(wrcal_sanity_chk),
        .wrcal_start_reg_0(u_ddr_phy_init_n_699),
        .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[120]_0 (u_ddr_prbs_gen_n_18),
        .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[121]_0 (u_ddr_prbs_gen_n_40),
        .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[124]_0 (u_ddr_prbs_gen_n_17),
        .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[125]_0 (u_ddr_prbs_gen_n_39),
        .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[184]_0 (u_ddr_prbs_gen_n_16),
        .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[186]_0 (u_ddr_prbs_gen_n_15),
        .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187]_0 (u_ddr_phy_wrcal_n_22),
        .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187]_1 (u_ddr_prbs_gen_n_38),
        .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[188]_0 (u_ddr_prbs_gen_n_14),
        .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[190]_0 (u_ddr_prbs_gen_n_13),
        .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[191]_0 (u_ddr_prbs_gen_n_37),
        .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[248]_0 (u_ddr_prbs_gen_n_36),
        .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[249]_0 (u_ddr_prbs_gen_n_12),
        .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[251]_0 (u_ddr_prbs_gen_n_11),
        .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[252]_0 (u_ddr_prbs_gen_n_35),
        .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[253]_0 (u_ddr_prbs_gen_n_10),
        .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[255]_0 (u_ddr_prbs_gen_n_9),
        .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[312]_0 (u_ddr_prbs_gen_n_34),
        .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[315]_0 (u_ddr_prbs_gen_n_8),
        .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[316]_0 (u_ddr_prbs_gen_n_33),
        .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[319]_0 (u_ddr_prbs_gen_n_7),
        .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[376]_0 (u_ddr_prbs_gen_n_6),
        .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[377]_0 (u_ddr_prbs_gen_n_32),
        .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[378]_0 (u_ddr_prbs_gen_n_31),
        .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[380]_0 (u_ddr_prbs_gen_n_5),
        .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[381]_0 (u_ddr_prbs_gen_n_30),
        .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[382]_0 (u_ddr_prbs_gen_n_29),
        .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[440]_0 (u_ddr_prbs_gen_n_28),
        .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[441]_0 (u_ddr_prbs_gen_n_4),
        .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[442]_0 (u_ddr_prbs_gen_n_27),
        .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[443]_0 (u_ddr_prbs_gen_n_26),
        .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[444]_0 (u_ddr_prbs_gen_n_25),
        .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[445]_0 (u_ddr_prbs_gen_n_3),
        .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[446]_0 (u_ddr_prbs_gen_n_24),
        .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[447]_0 (u_ddr_prbs_gen_n_23),
        .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[505]_0 (u_ddr_prbs_gen_n_22),
        .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[506]_0 (u_ddr_prbs_gen_n_2),
        .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[507]_0 (u_ddr_prbs_gen_n_21),
        .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[508]_0 (u_ddr_phy_wrcal_n_40),
        .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[509]_0 (u_ddr_prbs_gen_n_20),
        .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[510]_0 (u_ddr_prbs_gen_n_1),
        .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0 (u_ddr_prbs_gen_n_19),
        .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_20 ),
        .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57]_0 (u_ddr_prbs_gen_n_44),
        .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[58]_0 (u_ddr_prbs_gen_n_43),
        .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[61]_0 (u_ddr_prbs_gen_n_42),
        .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[62]_0 (u_ddr_prbs_gen_n_41),
        .\write_buffer.wr_buf_out_data_reg[448] (\write_buffer.wr_buf_out_data_reg[448] ),
        .\write_buffer.wr_buf_out_data_reg[450] (\write_buffer.wr_buf_out_data_reg[450] ),
        .\write_buffer.wr_buf_out_data_reg[451] (\write_buffer.wr_buf_out_data_reg[451] ),
        .\write_buffer.wr_buf_out_data_reg[452] (\write_buffer.wr_buf_out_data_reg[452] ),
        .\write_buffer.wr_buf_out_data_reg[453] (\write_buffer.wr_buf_out_data_reg[453] ),
        .\write_buffer.wr_buf_out_data_reg[454] (\write_buffer.wr_buf_out_data_reg[454] ),
        .\write_buffer.wr_buf_out_data_reg[455] (\write_buffer.wr_buf_out_data_reg[455]_0 ),
        .\write_buffer.wr_buf_out_data_reg[455]_0 (\write_buffer.wr_buf_out_data_reg[455] [71:8]),
        .\write_buffer.wr_buf_out_data_reg[456] (\write_buffer.wr_buf_out_data_reg[456] ),
        .\write_buffer.wr_buf_out_data_reg[457] (\write_buffer.wr_buf_out_data_reg[457] ),
        .\write_buffer.wr_buf_out_data_reg[458] (\write_buffer.wr_buf_out_data_reg[458] ),
        .\write_buffer.wr_buf_out_data_reg[459] (\write_buffer.wr_buf_out_data_reg[459] ),
        .\write_buffer.wr_buf_out_data_reg[460] (\write_buffer.wr_buf_out_data_reg[460] ),
        .\write_buffer.wr_buf_out_data_reg[461] (\write_buffer.wr_buf_out_data_reg[461] ),
        .\write_buffer.wr_buf_out_data_reg[462] (\write_buffer.wr_buf_out_data_reg[462] ),
        .\write_buffer.wr_buf_out_data_reg[463] (\write_buffer.wr_buf_out_data_reg[463]_0 ),
        .\write_buffer.wr_buf_out_data_reg[463]_0 (\write_buffer.wr_buf_out_data_reg[463] [71:8]),
        .\write_buffer.wr_buf_out_data_reg[464] (\write_buffer.wr_buf_out_data_reg[464] ),
        .\write_buffer.wr_buf_out_data_reg[465] (\write_buffer.wr_buf_out_data_reg[465] ),
        .\write_buffer.wr_buf_out_data_reg[466] (\write_buffer.wr_buf_out_data_reg[466] ),
        .\write_buffer.wr_buf_out_data_reg[467] (\write_buffer.wr_buf_out_data_reg[467] ),
        .\write_buffer.wr_buf_out_data_reg[468] (\write_buffer.wr_buf_out_data_reg[468] ),
        .\write_buffer.wr_buf_out_data_reg[469] (\write_buffer.wr_buf_out_data_reg[469] ),
        .\write_buffer.wr_buf_out_data_reg[470] (\write_buffer.wr_buf_out_data_reg[470] ),
        .\write_buffer.wr_buf_out_data_reg[471] (\write_buffer.wr_buf_out_data_reg[471]_0 ),
        .\write_buffer.wr_buf_out_data_reg[471]_0 (\write_buffer.wr_buf_out_data_reg[471] [71:8]),
        .\write_buffer.wr_buf_out_data_reg[472] (\write_buffer.wr_buf_out_data_reg[472] ),
        .\write_buffer.wr_buf_out_data_reg[473] (\write_buffer.wr_buf_out_data_reg[473] ),
        .\write_buffer.wr_buf_out_data_reg[474] (\write_buffer.wr_buf_out_data_reg[474] ),
        .\write_buffer.wr_buf_out_data_reg[475] (\write_buffer.wr_buf_out_data_reg[475] ),
        .\write_buffer.wr_buf_out_data_reg[476] (\write_buffer.wr_buf_out_data_reg[476] ),
        .\write_buffer.wr_buf_out_data_reg[477] (\write_buffer.wr_buf_out_data_reg[477] ),
        .\write_buffer.wr_buf_out_data_reg[478] (\write_buffer.wr_buf_out_data_reg[478] ),
        .\write_buffer.wr_buf_out_data_reg[479] (\write_buffer.wr_buf_out_data_reg[479]_0 ),
        .\write_buffer.wr_buf_out_data_reg[479]_0 (\write_buffer.wr_buf_out_data_reg[479] [71:8]),
        .\write_buffer.wr_buf_out_data_reg[480] (\write_buffer.wr_buf_out_data_reg[480] ),
        .\write_buffer.wr_buf_out_data_reg[481] (\write_buffer.wr_buf_out_data_reg[481] ),
        .\write_buffer.wr_buf_out_data_reg[482] (\write_buffer.wr_buf_out_data_reg[482] ),
        .\write_buffer.wr_buf_out_data_reg[483] (\write_buffer.wr_buf_out_data_reg[483] ),
        .\write_buffer.wr_buf_out_data_reg[484] (\write_buffer.wr_buf_out_data_reg[484] ),
        .\write_buffer.wr_buf_out_data_reg[485] (\write_buffer.wr_buf_out_data_reg[485] ),
        .\write_buffer.wr_buf_out_data_reg[486] (\write_buffer.wr_buf_out_data_reg[486] ),
        .\write_buffer.wr_buf_out_data_reg[487] (\write_buffer.wr_buf_out_data_reg[487]_0 ),
        .\write_buffer.wr_buf_out_data_reg[487]_0 (\write_buffer.wr_buf_out_data_reg[487] [71:8]),
        .\write_buffer.wr_buf_out_data_reg[488] (\write_buffer.wr_buf_out_data_reg[488] ),
        .\write_buffer.wr_buf_out_data_reg[489] (\write_buffer.wr_buf_out_data_reg[489] ),
        .\write_buffer.wr_buf_out_data_reg[490] (\write_buffer.wr_buf_out_data_reg[490] ),
        .\write_buffer.wr_buf_out_data_reg[491] (\write_buffer.wr_buf_out_data_reg[491] ),
        .\write_buffer.wr_buf_out_data_reg[492] (\write_buffer.wr_buf_out_data_reg[492] ),
        .\write_buffer.wr_buf_out_data_reg[493] (\write_buffer.wr_buf_out_data_reg[493] ),
        .\write_buffer.wr_buf_out_data_reg[494] (\write_buffer.wr_buf_out_data_reg[494] ),
        .\write_buffer.wr_buf_out_data_reg[495] (\write_buffer.wr_buf_out_data_reg[495]_0 ),
        .\write_buffer.wr_buf_out_data_reg[495]_0 (\write_buffer.wr_buf_out_data_reg[495] [71:8]),
        .\write_buffer.wr_buf_out_data_reg[496] (\write_buffer.wr_buf_out_data_reg[496] ),
        .\write_buffer.wr_buf_out_data_reg[497] (\write_buffer.wr_buf_out_data_reg[497] ),
        .\write_buffer.wr_buf_out_data_reg[498] (\write_buffer.wr_buf_out_data_reg[498] ),
        .\write_buffer.wr_buf_out_data_reg[499] (\write_buffer.wr_buf_out_data_reg[499] ),
        .\write_buffer.wr_buf_out_data_reg[500] (\write_buffer.wr_buf_out_data_reg[500] ),
        .\write_buffer.wr_buf_out_data_reg[501] (\write_buffer.wr_buf_out_data_reg[501] ),
        .\write_buffer.wr_buf_out_data_reg[502] (\write_buffer.wr_buf_out_data_reg[502] ),
        .\write_buffer.wr_buf_out_data_reg[503] (\write_buffer.wr_buf_out_data_reg[503]_0 ),
        .\write_buffer.wr_buf_out_data_reg[503]_0 (\write_buffer.wr_buf_out_data_reg[503] [71:8]),
        .\write_buffer.wr_buf_out_data_reg[504] (\write_buffer.wr_buf_out_data_reg[504] ),
        .\write_buffer.wr_buf_out_data_reg[505] (\write_buffer.wr_buf_out_data_reg[505] ),
        .\write_buffer.wr_buf_out_data_reg[506] (\write_buffer.wr_buf_out_data_reg[506] ),
        .\write_buffer.wr_buf_out_data_reg[507] (\write_buffer.wr_buf_out_data_reg[507] ),
        .\write_buffer.wr_buf_out_data_reg[508] (\write_buffer.wr_buf_out_data_reg[508] ),
        .\write_buffer.wr_buf_out_data_reg[509] (\write_buffer.wr_buf_out_data_reg[509] ),
        .\write_buffer.wr_buf_out_data_reg[510] (\write_buffer.wr_buf_out_data_reg[510] ),
        .\write_buffer.wr_buf_out_data_reg[511] (\write_buffer.wr_buf_out_data_reg[511]_0 ),
        .\write_buffer.wr_buf_out_data_reg[511]_0 (\write_buffer.wr_buf_out_data_reg[511] [71:8]),
        .write_calib_reg_0(\not_empty_wait_cnt_reg[4] ),
        .wrlvl_byte_redo(wrlvl_byte_redo),
        .wrlvl_done_r1(wrlvl_done_r1),
        .wrlvl_done_r_reg_0(\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_5 ),
        .wrlvl_final_if_rst(wrlvl_final_if_rst),
        .wrlvl_rank_done(wrlvl_rank_done));
  mig_mig_7series_v4_2_ddr_phy_wrcal u_ddr_phy_wrcal
       (.E(rd_active_r),
        .LD0(LD0),
        .LD0_0(LD0_0),
        .LD0_1(LD0_1),
        .LD0_2(LD0_2),
        .LD0_3(LD0_3),
        .LD0_4(LD0_4),
        .LD0_5(LD0_5),
        .LD0_6(LD0_6),
        .Q({po_stg2_wrcal_cnt,\po_stg2_wrcal_cnt_reg[2] }),
        .cal2_done_r_reg_0(\rdlvl_dqs_tap_cnt_r_reg[0][0][2] [0]),
        .cal2_if_reset_reg_0(cal2_if_reset_reg),
        .\cal2_state_r_reg[0]_0 (u_ddr_phy_init_n_699),
        .calib_in_common(calib_in_common),
        .\corse_cnt[0][2]_i_3 (wl_state_r__0),
        .\corse_cnt[0][2]_i_3_0 (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_46 ),
        .done_dqs_dec238_out(done_dqs_dec238_out),
        .early1_data_reg_0(u_ddr_phy_wrcal_n_6),
        .early1_data_reg_1(u_ddr_phy_wrcal_n_24),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] ),
        .idelay_ce_int(idelay_ce_int),
        .idelay_ld_rst(idelay_ld_rst),
        .idelay_ld_rst_10(idelay_ld_rst_10),
        .idelay_ld_rst_11(idelay_ld_rst_11),
        .idelay_ld_rst_12(idelay_ld_rst_12),
        .idelay_ld_rst_13(idelay_ld_rst_13),
        .idelay_ld_rst_7(idelay_ld_rst_7),
        .idelay_ld_rst_8(idelay_ld_rst_8),
        .idelay_ld_rst_9(idelay_ld_rst_9),
        .\idelay_tap_cnt_r_reg[0][0][4] (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_15 ),
        .\idelay_tap_cnt_r_reg[0][0][4]_0 (\idelay_tap_cnt_r_reg[0][0][4] ),
        .\idelay_tap_cnt_r_reg[0][1][4] (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_26 ),
        .\idelay_tap_cnt_r_reg[0][2][4] (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_25 ),
        .\idelay_tap_cnt_r_reg[0][4][4] (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_14 ),
        .\idelay_tap_cnt_r_reg[0][4][4]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_23 ),
        .\idelay_tap_cnt_r_reg[0][4][4]_1 (\idelay_tap_cnt_r_reg[0][4][4] ),
        .\idelay_tap_cnt_r_reg[0][5][4] (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_27 ),
        .\idelay_tap_cnt_r_reg[0][5][4]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_22 ),
        .\idelay_tap_cnt_r_reg[0][6][4] (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_24 ),
        .\idelay_tap_cnt_r_reg[0][7][4] (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_28 ),
        .\init_state_r[2]_i_14 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl_n_7 ),
        .\init_state_r[3]_i_13 (\dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr_n_2 ),
        .\init_state_r[3]_i_13_0 (u_ddr_phy_init_n_684),
        .\init_state_r[4]_i_27 (u_ddr_phy_init_n_3),
        .\input_[9].iserdes_dq_.idelay_dq.idelaye2 ({calib_zero_inputs[2],calib_zero_inputs[0]}),
        .\input_[9].iserdes_dq_.idelay_dq.idelaye2_0 (calib_sel[0]),
        .\input_[9].iserdes_dq_.idelay_dq.idelaye2_1 (calib_sel[1]),
        .\not_empty_wait_cnt_reg[4]_0 (\not_empty_wait_cnt_reg[4] ),
        .p_0_out(p_0_out),
        .phy_if_reset_w(phy_if_reset_w),
        .phy_rddata_en(phy_rddata_en),
        .\po_stg2_wrcal_cnt_reg[0]_0 (u_ddr_phy_wrcal_n_25),
        .\po_stg2_wrcal_cnt_reg[0]_1 (u_ddr_phy_wrcal_n_27),
        .\po_stg2_wrcal_cnt_reg[0]_2 (u_ddr_phy_wrcal_n_28),
        .\po_stg2_wrcal_cnt_reg[0]_3 (u_ddr_phy_wrcal_n_29),
        .\po_stg2_wrcal_cnt_reg[0]_4 (u_ddr_phy_wrcal_n_30),
        .\po_stg2_wrcal_cnt_reg[0]_5 (u_ddr_phy_wrcal_n_31),
        .\po_stg2_wrcal_cnt_reg[0]_6 (u_ddr_phy_wrcal_n_32),
        .\po_stg2_wrcal_cnt_reg[0]_7 (u_ddr_phy_wrcal_n_34),
        .\po_stg2_wrcal_cnt_reg[0]_8 (u_ddr_phy_wrcal_n_35),
        .\po_stg2_wrcal_cnt_reg[1]_0 (u_ddr_phy_wrcal_n_26),
        .\po_stg2_wrcal_cnt_reg[1]_1 (u_ddr_phy_wrcal_n_33),
        .\po_stg2_wrcal_cnt_reg[1]_2 (u_ddr_phy_wrcal_n_36),
        .\po_stg2_wrcal_cnt_reg[2]_0 (u_ddr_phy_wrcal_n_23),
        .\po_stg2_wrcal_cnt_reg[3]_0 (u_ddr_phy_wrcal_n_8),
        .prech_done(prech_done),
        .wrcal_done_reg_0(u_ddr_phy_wrcal_n_3),
        .wrcal_done_reg_1(u_ddr_phy_wrcal_n_22),
        .wrcal_done_reg_2(u_ddr_phy_wrcal_n_37),
        .wrcal_done_reg_3(u_ddr_phy_wrcal_n_38),
        .wrcal_done_reg_4(u_ddr_phy_wrcal_n_40),
        .wrcal_pat_resume_reg_0(\dout_o_reg[15] ),
        .wrcal_prech_req(wrcal_prech_req),
        .wrcal_rd_wait(wrcal_rd_wait),
        .wrcal_resume_w(wrcal_resume_w),
        .wrcal_sanity_chk(wrcal_sanity_chk),
        .wrcal_sanity_chk_done_reg_0(u_ddr_phy_wrcal_n_4),
        .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[508] (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_10 ),
        .wrlvl_byte_done(wrlvl_byte_done),
        .wrlvl_byte_redo(wrlvl_byte_redo),
        .wrlvl_byte_redo_r(wrlvl_byte_redo_r),
        .wrlvl_byte_redo_reg_0(u_ddr_phy_wrcal_n_39),
        .wrlvl_done_r1(wrlvl_done_r1),
        .\wrlvl_redo_corse_inc[2]_i_7 (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_45 ),
        .\wrlvl_redo_corse_inc[2]_i_7_0 (\mb_wrlvl_inst.u_ddr_phy_wrlvl_n_44 ));
  mig_mig_7series_v4_2_ddr_prbs_gen u_ddr_prbs_gen
       (.D({sel,u_ddr_phy_init_n_22,u_ddr_phy_init_n_23,u_ddr_phy_init_n_24,u_ddr_phy_init_n_25,u_ddr_phy_init_n_26,u_ddr_phy_init_n_27,u_ddr_phy_init_n_28}),
        .E(u_ddr_phy_init_n_686),
        .Q(u_ddr_prbs_gen_n_45),
        .SR(u_ddr_phy_init_n_689),
        .\dout_o_reg[10]_0 (u_ddr_prbs_gen_n_5),
        .\dout_o_reg[10]_1 (u_ddr_prbs_gen_n_6),
        .\dout_o_reg[10]_2 (u_ddr_prbs_gen_n_29),
        .\dout_o_reg[10]_3 (u_ddr_prbs_gen_n_31),
        .\dout_o_reg[11]_0 (u_ddr_prbs_gen_n_7),
        .\dout_o_reg[11]_1 (u_ddr_prbs_gen_n_8),
        .\dout_o_reg[11]_2 (u_ddr_prbs_gen_n_33),
        .\dout_o_reg[11]_3 (u_ddr_prbs_gen_n_34),
        .\dout_o_reg[12]_0 (u_ddr_prbs_gen_n_9),
        .\dout_o_reg[12]_1 (u_ddr_prbs_gen_n_10),
        .\dout_o_reg[12]_2 (u_ddr_prbs_gen_n_11),
        .\dout_o_reg[12]_3 (u_ddr_prbs_gen_n_12),
        .\dout_o_reg[12]_4 (u_ddr_prbs_gen_n_35),
        .\dout_o_reg[12]_5 (u_ddr_prbs_gen_n_36),
        .\dout_o_reg[13]_0 (u_ddr_prbs_gen_n_13),
        .\dout_o_reg[13]_1 (u_ddr_prbs_gen_n_14),
        .\dout_o_reg[13]_2 (u_ddr_prbs_gen_n_15),
        .\dout_o_reg[13]_3 (u_ddr_prbs_gen_n_16),
        .\dout_o_reg[14]_0 (u_ddr_prbs_gen_n_17),
        .\dout_o_reg[14]_1 (u_ddr_prbs_gen_n_18),
        .\dout_o_reg[15]_0 (u_ddr_prbs_gen_n_41),
        .\dout_o_reg[15]_1 (u_ddr_prbs_gen_n_43),
        .\dout_o_reg[15]_2 (\dout_o_reg[15] ),
        .\dout_o_reg[6]_0 (u_ddr_prbs_gen_n_39),
        .\dout_o_reg[8]_0 (u_ddr_prbs_gen_n_19),
        .\dout_o_reg[8]_1 (u_ddr_prbs_gen_n_20),
        .\dout_o_reg[8]_2 (u_ddr_prbs_gen_n_21),
        .\dout_o_reg[8]_3 (u_ddr_prbs_gen_n_22),
        .\dout_o_reg[9]_0 (u_ddr_prbs_gen_n_3),
        .\dout_o_reg[9]_1 (u_ddr_prbs_gen_n_4),
        .\dout_o_reg[9]_2 (u_ddr_prbs_gen_n_24),
        .\dout_o_reg[9]_3 (u_ddr_prbs_gen_n_27),
        .first_rdlvl_pat_r(first_rdlvl_pat_r),
        .first_wrcal_pat_r(first_wrcal_pat_r),
        .first_wrcal_pat_r_reg(u_ddr_prbs_gen_n_1),
        .first_wrcal_pat_r_reg_0(u_ddr_prbs_gen_n_2),
        .if_empty(if_empty),
        .phy_if_empty_r_reg_0(u_ddr_prbs_gen_n_0),
        .prbs_out({prbs_out[511:504],prbs_out[447:440],prbs_out[383:376],prbs_out[319:312],prbs_out[255:248],prbs_out[191:184],prbs_out[127:120],prbs_out[63:56]}),
        .\rd_addr_reg[0]_0 (u_ddr_phy_init_n_688),
        .\rd_addr_reg[3]_0 (u_ddr_phy_init_n_687),
        .rdlvl_stg1_done_int_reg(u_ddr_prbs_gen_n_23),
        .rdlvl_stg1_done_int_reg_0(u_ddr_prbs_gen_n_25),
        .rdlvl_stg1_done_int_reg_1(u_ddr_prbs_gen_n_26),
        .rdlvl_stg1_done_int_reg_2(u_ddr_prbs_gen_n_28),
        .rdlvl_stg1_done_int_reg_3(u_ddr_prbs_gen_n_30),
        .rdlvl_stg1_done_int_reg_4(u_ddr_prbs_gen_n_32),
        .rdlvl_stg1_done_int_reg_5(u_ddr_prbs_gen_n_37),
        .rdlvl_stg1_done_int_reg_6(u_ddr_prbs_gen_n_38),
        .\victim_sel_rotate.sel_reg[56]_0 (\rdlvl_dqs_tap_cnt_r_reg[0][0][2] [0]),
        .wrcal_done_reg(u_ddr_prbs_gen_n_40),
        .wrcal_done_reg_0(u_ddr_prbs_gen_n_42),
        .wrcal_done_reg_1(u_ddr_prbs_gen_n_44),
        .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511] (u_ddr_phy_wrcal_n_3),
        .\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0 (\ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl_n_10 ));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_if_post_fifo" *) 
module mig_mig_7series_v4_2_ddr_if_post_fifo
   (\rd_mux_sel_r_reg[2] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ,
    \rd_mux_sel_r_reg[2]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ,
    \rd_mux_sel_r_reg[2]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ,
    \rd_mux_sel_r_reg[2]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ,
    \rd_mux_sel_r_reg[2]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ,
    \rd_mux_sel_r_reg[2]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ,
    \rd_mux_sel_r_reg[2]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ,
    \rd_mux_sel_r_reg[2]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ,
    \rd_mux_sel_r_reg[2]_7 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ,
    \rd_mux_sel_r_reg[2]_8 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ,
    \rd_mux_sel_r_reg[2]_9 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ,
    \rd_mux_sel_r_reg[2]_10 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ,
    \rd_mux_sel_r_reg[2]_11 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ,
    \rd_mux_sel_r_reg[2]_12 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ,
    \rd_mux_sel_r_reg[2]_13 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ,
    \rd_mux_sel_r_reg[2]_14 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] ,
    \rd_mux_sel_r_reg[2]_15 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ,
    \rd_mux_sel_r_reg[2]_16 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ,
    \rd_mux_sel_r_reg[2]_17 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ,
    \rd_mux_sel_r_reg[2]_18 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ,
    \rd_mux_sel_r_reg[2]_19 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ,
    \rd_mux_sel_r_reg[2]_20 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ,
    \rd_mux_sel_r_reg[2]_21 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ,
    \rd_mux_sel_r_reg[2]_22 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] ,
    \rd_mux_sel_r_reg[2]_23 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ,
    \rd_mux_sel_r_reg[2]_24 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ,
    \rd_mux_sel_r_reg[2]_25 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ,
    \rd_mux_sel_r_reg[2]_26 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ,
    \rd_mux_sel_r_reg[2]_27 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ,
    \rd_mux_sel_r_reg[2]_28 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ,
    \rd_mux_sel_r_reg[2]_29 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ,
    \rd_mux_sel_r_reg[2]_30 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] ,
    \rd_mux_sel_r_reg[2]_31 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ,
    \rd_mux_sel_r_reg[2]_32 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ,
    \rd_mux_sel_r_reg[2]_33 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ,
    \rd_mux_sel_r_reg[2]_34 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ,
    \rd_mux_sel_r_reg[2]_35 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ,
    \rd_mux_sel_r_reg[2]_36 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ,
    \rd_mux_sel_r_reg[2]_37 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ,
    \rd_mux_sel_r_reg[2]_38 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] ,
    \rd_mux_sel_r_reg[2]_39 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ,
    \rd_mux_sel_r_reg[2]_40 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ,
    \rd_mux_sel_r_reg[2]_41 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ,
    \rd_mux_sel_r_reg[2]_42 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ,
    \rd_mux_sel_r_reg[2]_43 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ,
    \rd_mux_sel_r_reg[2]_44 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ,
    \rd_mux_sel_r_reg[2]_45 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ,
    \rd_mux_sel_r_reg[2]_46 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] ,
    \rd_mux_sel_r_reg[2]_47 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ,
    \rd_mux_sel_r_reg[2]_48 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ,
    \rd_mux_sel_r_reg[2]_49 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ,
    \rd_mux_sel_r_reg[2]_50 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ,
    \rd_mux_sel_r_reg[2]_51 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ,
    \rd_mux_sel_r_reg[2]_52 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ,
    \rd_mux_sel_r_reg[2]_53 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ,
    \rd_mux_sel_r_reg[2]_54 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] ,
    \rd_mux_sel_r_reg[2]_55 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ,
    \rd_mux_sel_r_reg[2]_56 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ,
    \rd_mux_sel_r_reg[2]_57 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ,
    \rd_mux_sel_r_reg[2]_58 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ,
    \rd_mux_sel_r_reg[2]_59 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ,
    \rd_mux_sel_r_reg[2]_60 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ,
    \rd_mux_sel_r_reg[2]_61 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ,
    \rd_mux_sel_r_reg[2]_62 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ,
    p_0_out,
    \po_stg2_wrcal_cnt_reg[2] ,
    \po_stg2_wrcal_cnt_reg[2]_0 ,
    \po_stg2_wrcal_cnt_reg[2]_1 ,
    \po_stg2_wrcal_cnt_reg[2]_2 ,
    \po_stg2_wrcal_cnt_reg[2]_3 ,
    \po_stg2_wrcal_cnt_reg[2]_4 ,
    \po_stg2_wrcal_cnt_reg[2]_5 ,
    \po_stg2_wrcal_cnt_reg[2]_6 ,
    \po_stg2_wrcal_cnt_reg[2]_7 ,
    \po_stg2_wrcal_cnt_reg[2]_8 ,
    \po_stg2_wrcal_cnt_reg[2]_9 ,
    \po_stg2_wrcal_cnt_reg[2]_10 ,
    \po_stg2_wrcal_cnt_reg[2]_11 ,
    \po_stg2_wrcal_cnt_reg[2]_12 ,
    \po_stg2_wrcal_cnt_reg[2]_13 ,
    \po_stg2_wrcal_cnt_reg[2]_14 ,
    \po_stg2_wrcal_cnt_reg[2]_15 ,
    \po_stg2_wrcal_cnt_reg[2]_16 ,
    \po_stg2_wrcal_cnt_reg[2]_17 ,
    \po_stg2_wrcal_cnt_reg[2]_18 ,
    \po_stg2_wrcal_cnt_reg[2]_19 ,
    \po_stg2_wrcal_cnt_reg[2]_20 ,
    \po_stg2_wrcal_cnt_reg[2]_21 ,
    \po_stg2_wrcal_cnt_reg[2]_22 ,
    \po_stg2_wrcal_cnt_reg[2]_23 ,
    \po_stg2_wrcal_cnt_reg[2]_24 ,
    \po_stg2_wrcal_cnt_reg[2]_25 ,
    \po_stg2_wrcal_cnt_reg[2]_26 ,
    \po_stg2_wrcal_cnt_reg[2]_27 ,
    \po_stg2_wrcal_cnt_reg[2]_28 ,
    \po_stg2_wrcal_cnt_reg[2]_29 ,
    \po_stg2_wrcal_cnt_reg[2]_30 ,
    \po_stg2_wrcal_cnt_reg[2]_31 ,
    \po_stg2_wrcal_cnt_reg[2]_32 ,
    \po_stg2_wrcal_cnt_reg[2]_33 ,
    \po_stg2_wrcal_cnt_reg[2]_34 ,
    \po_stg2_wrcal_cnt_reg[2]_35 ,
    \po_stg2_wrcal_cnt_reg[2]_36 ,
    \po_stg2_wrcal_cnt_reg[2]_37 ,
    \po_stg2_wrcal_cnt_reg[2]_38 ,
    \po_stg2_wrcal_cnt_reg[2]_39 ,
    \po_stg2_wrcal_cnt_reg[2]_40 ,
    \po_stg2_wrcal_cnt_reg[2]_41 ,
    \po_stg2_wrcal_cnt_reg[2]_42 ,
    \po_stg2_wrcal_cnt_reg[2]_43 ,
    \po_stg2_wrcal_cnt_reg[2]_44 ,
    \po_stg2_wrcal_cnt_reg[2]_45 ,
    \po_stg2_wrcal_cnt_reg[2]_46 ,
    \po_stg2_wrcal_cnt_reg[2]_47 ,
    \po_stg2_wrcal_cnt_reg[2]_48 ,
    \po_stg2_wrcal_cnt_reg[2]_49 ,
    \po_stg2_wrcal_cnt_reg[2]_50 ,
    \po_stg2_wrcal_cnt_reg[2]_51 ,
    \po_stg2_wrcal_cnt_reg[2]_52 ,
    \po_stg2_wrcal_cnt_reg[2]_53 ,
    \po_stg2_wrcal_cnt_reg[2]_54 ,
    \po_stg2_wrcal_cnt_reg[2]_55 ,
    \po_stg2_wrcal_cnt_reg[2]_56 ,
    \po_stg2_wrcal_cnt_reg[2]_57 ,
    \po_stg2_wrcal_cnt_reg[2]_58 ,
    \po_stg2_wrcal_cnt_reg[2]_59 ,
    \po_stg2_wrcal_cnt_reg[2]_60 ,
    \po_stg2_wrcal_cnt_reg[2]_61 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ,
    if_empty_v,
    ififo_rst,
    \rd_ptr_timing_reg[1]_0 ,
    if_empty_r_0,
    \my_full_reg[1]_0 ,
    \gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ,
    \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1 ,
    \gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1 ,
    \gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1 ,
    \gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 ,
    \gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_1 ,
    \gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_1 ,
    \gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_1 ,
    \gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_1 ,
    \gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_1 ,
    \gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 ,
    \gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_1 ,
    \gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 ,
    \gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_1 ,
    \gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 ,
    \gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_1 ,
    \gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 ,
    \gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_1 ,
    \gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 ,
    \gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_1 ,
    \gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 ,
    \gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_1 ,
    \gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 ,
    \gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_1 ,
    \gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 ,
    \gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_1 ,
    \gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 ,
    \gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_1 ,
    \gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 ,
    \gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_1 ,
    \gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 ,
    \gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_1 ,
    \gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 ,
    \gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_1 ,
    \gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 ,
    \gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_1 ,
    \gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 ,
    \gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_1 ,
    \gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 ,
    \gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_1 ,
    \gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 ,
    \gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_1 ,
    \gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 ,
    \gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_1 ,
    \gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 ,
    \gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_1 ,
    \gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 ,
    \gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_1 ,
    \gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 ,
    \gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_1 ,
    \gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 ,
    \gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_1 ,
    \gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 ,
    \gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_1 ,
    \gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 ,
    \gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_1 ,
    \gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 ,
    \gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_1 ,
    \gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1 ,
    \gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_1 ,
    \gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 ,
    \gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_1 ,
    \gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 ,
    \gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_1 ,
    \gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_3 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_2 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_2 ,
    \my_full_reg[1]_1 ,
    \my_full_reg[1]_2 ,
    \my_full_reg[1]_3 ,
    \my_full_reg[1]_4 ,
    \my_full_reg[1]_5 ,
    Q,
    phy_if_empty_r_reg,
    if_empty_r,
    phy_if_empty_r_reg_0);
  output \rd_mux_sel_r_reg[2] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ;
  output \rd_mux_sel_r_reg[2]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ;
  output \rd_mux_sel_r_reg[2]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ;
  output \rd_mux_sel_r_reg[2]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ;
  output \rd_mux_sel_r_reg[2]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ;
  output \rd_mux_sel_r_reg[2]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ;
  output \rd_mux_sel_r_reg[2]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ;
  output \rd_mux_sel_r_reg[2]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ;
  output \rd_mux_sel_r_reg[2]_7 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ;
  output \rd_mux_sel_r_reg[2]_8 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ;
  output \rd_mux_sel_r_reg[2]_9 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ;
  output \rd_mux_sel_r_reg[2]_10 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ;
  output \rd_mux_sel_r_reg[2]_11 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ;
  output \rd_mux_sel_r_reg[2]_12 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ;
  output \rd_mux_sel_r_reg[2]_13 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ;
  output \rd_mux_sel_r_reg[2]_14 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] ;
  output \rd_mux_sel_r_reg[2]_15 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ;
  output \rd_mux_sel_r_reg[2]_16 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ;
  output \rd_mux_sel_r_reg[2]_17 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ;
  output \rd_mux_sel_r_reg[2]_18 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ;
  output \rd_mux_sel_r_reg[2]_19 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ;
  output \rd_mux_sel_r_reg[2]_20 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ;
  output \rd_mux_sel_r_reg[2]_21 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ;
  output \rd_mux_sel_r_reg[2]_22 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] ;
  output \rd_mux_sel_r_reg[2]_23 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ;
  output \rd_mux_sel_r_reg[2]_24 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ;
  output \rd_mux_sel_r_reg[2]_25 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ;
  output \rd_mux_sel_r_reg[2]_26 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ;
  output \rd_mux_sel_r_reg[2]_27 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ;
  output \rd_mux_sel_r_reg[2]_28 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ;
  output \rd_mux_sel_r_reg[2]_29 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ;
  output \rd_mux_sel_r_reg[2]_30 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] ;
  output \rd_mux_sel_r_reg[2]_31 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ;
  output \rd_mux_sel_r_reg[2]_32 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ;
  output \rd_mux_sel_r_reg[2]_33 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ;
  output \rd_mux_sel_r_reg[2]_34 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ;
  output \rd_mux_sel_r_reg[2]_35 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ;
  output \rd_mux_sel_r_reg[2]_36 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ;
  output \rd_mux_sel_r_reg[2]_37 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ;
  output \rd_mux_sel_r_reg[2]_38 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] ;
  output \rd_mux_sel_r_reg[2]_39 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ;
  output \rd_mux_sel_r_reg[2]_40 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ;
  output \rd_mux_sel_r_reg[2]_41 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ;
  output \rd_mux_sel_r_reg[2]_42 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ;
  output \rd_mux_sel_r_reg[2]_43 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ;
  output \rd_mux_sel_r_reg[2]_44 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ;
  output \rd_mux_sel_r_reg[2]_45 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ;
  output \rd_mux_sel_r_reg[2]_46 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] ;
  output \rd_mux_sel_r_reg[2]_47 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ;
  output \rd_mux_sel_r_reg[2]_48 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ;
  output \rd_mux_sel_r_reg[2]_49 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ;
  output \rd_mux_sel_r_reg[2]_50 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ;
  output \rd_mux_sel_r_reg[2]_51 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ;
  output \rd_mux_sel_r_reg[2]_52 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ;
  output \rd_mux_sel_r_reg[2]_53 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ;
  output \rd_mux_sel_r_reg[2]_54 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] ;
  output \rd_mux_sel_r_reg[2]_55 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ;
  output \rd_mux_sel_r_reg[2]_56 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ;
  output \rd_mux_sel_r_reg[2]_57 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ;
  output \rd_mux_sel_r_reg[2]_58 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ;
  output \rd_mux_sel_r_reg[2]_59 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ;
  output \rd_mux_sel_r_reg[2]_60 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ;
  output \rd_mux_sel_r_reg[2]_61 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ;
  output \rd_mux_sel_r_reg[2]_62 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ;
  output p_0_out;
  output \po_stg2_wrcal_cnt_reg[2] ;
  output \po_stg2_wrcal_cnt_reg[2]_0 ;
  output \po_stg2_wrcal_cnt_reg[2]_1 ;
  output \po_stg2_wrcal_cnt_reg[2]_2 ;
  output \po_stg2_wrcal_cnt_reg[2]_3 ;
  output \po_stg2_wrcal_cnt_reg[2]_4 ;
  output \po_stg2_wrcal_cnt_reg[2]_5 ;
  output \po_stg2_wrcal_cnt_reg[2]_6 ;
  output \po_stg2_wrcal_cnt_reg[2]_7 ;
  output \po_stg2_wrcal_cnt_reg[2]_8 ;
  output \po_stg2_wrcal_cnt_reg[2]_9 ;
  output \po_stg2_wrcal_cnt_reg[2]_10 ;
  output \po_stg2_wrcal_cnt_reg[2]_11 ;
  output \po_stg2_wrcal_cnt_reg[2]_12 ;
  output \po_stg2_wrcal_cnt_reg[2]_13 ;
  output \po_stg2_wrcal_cnt_reg[2]_14 ;
  output \po_stg2_wrcal_cnt_reg[2]_15 ;
  output \po_stg2_wrcal_cnt_reg[2]_16 ;
  output \po_stg2_wrcal_cnt_reg[2]_17 ;
  output \po_stg2_wrcal_cnt_reg[2]_18 ;
  output \po_stg2_wrcal_cnt_reg[2]_19 ;
  output \po_stg2_wrcal_cnt_reg[2]_20 ;
  output \po_stg2_wrcal_cnt_reg[2]_21 ;
  output \po_stg2_wrcal_cnt_reg[2]_22 ;
  output \po_stg2_wrcal_cnt_reg[2]_23 ;
  output \po_stg2_wrcal_cnt_reg[2]_24 ;
  output \po_stg2_wrcal_cnt_reg[2]_25 ;
  output \po_stg2_wrcal_cnt_reg[2]_26 ;
  output \po_stg2_wrcal_cnt_reg[2]_27 ;
  output \po_stg2_wrcal_cnt_reg[2]_28 ;
  output \po_stg2_wrcal_cnt_reg[2]_29 ;
  output \po_stg2_wrcal_cnt_reg[2]_30 ;
  output \po_stg2_wrcal_cnt_reg[2]_31 ;
  output \po_stg2_wrcal_cnt_reg[2]_32 ;
  output \po_stg2_wrcal_cnt_reg[2]_33 ;
  output \po_stg2_wrcal_cnt_reg[2]_34 ;
  output \po_stg2_wrcal_cnt_reg[2]_35 ;
  output \po_stg2_wrcal_cnt_reg[2]_36 ;
  output \po_stg2_wrcal_cnt_reg[2]_37 ;
  output \po_stg2_wrcal_cnt_reg[2]_38 ;
  output \po_stg2_wrcal_cnt_reg[2]_39 ;
  output \po_stg2_wrcal_cnt_reg[2]_40 ;
  output \po_stg2_wrcal_cnt_reg[2]_41 ;
  output \po_stg2_wrcal_cnt_reg[2]_42 ;
  output \po_stg2_wrcal_cnt_reg[2]_43 ;
  output \po_stg2_wrcal_cnt_reg[2]_44 ;
  output \po_stg2_wrcal_cnt_reg[2]_45 ;
  output \po_stg2_wrcal_cnt_reg[2]_46 ;
  output \po_stg2_wrcal_cnt_reg[2]_47 ;
  output \po_stg2_wrcal_cnt_reg[2]_48 ;
  output \po_stg2_wrcal_cnt_reg[2]_49 ;
  output \po_stg2_wrcal_cnt_reg[2]_50 ;
  output \po_stg2_wrcal_cnt_reg[2]_51 ;
  output \po_stg2_wrcal_cnt_reg[2]_52 ;
  output \po_stg2_wrcal_cnt_reg[2]_53 ;
  output \po_stg2_wrcal_cnt_reg[2]_54 ;
  output \po_stg2_wrcal_cnt_reg[2]_55 ;
  output \po_stg2_wrcal_cnt_reg[2]_56 ;
  output \po_stg2_wrcal_cnt_reg[2]_57 ;
  output \po_stg2_wrcal_cnt_reg[2]_58 ;
  output \po_stg2_wrcal_cnt_reg[2]_59 ;
  output \po_stg2_wrcal_cnt_reg[2]_60 ;
  output \po_stg2_wrcal_cnt_reg[2]_61 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;
  output [0:0]if_empty_v;
  input ififo_rst;
  input \rd_ptr_timing_reg[1]_0 ;
  input [0:0]if_empty_r_0;
  input \my_full_reg[1]_0 ;
  input [2:0]\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ;
  input \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1 ;
  input \gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1 ;
  input \gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1 ;
  input \gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 ;
  input \gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_1 ;
  input \gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_1 ;
  input \gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_1 ;
  input \gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_1 ;
  input \gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_1 ;
  input \gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 ;
  input \gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_1 ;
  input \gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 ;
  input \gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_1 ;
  input \gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 ;
  input \gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_1 ;
  input \gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 ;
  input \gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_1 ;
  input \gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 ;
  input \gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_1 ;
  input \gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 ;
  input \gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_1 ;
  input \gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 ;
  input \gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_1 ;
  input \gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 ;
  input \gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_1 ;
  input \gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 ;
  input \gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_1 ;
  input \gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 ;
  input \gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_1 ;
  input \gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 ;
  input \gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_1 ;
  input \gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 ;
  input \gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_1 ;
  input \gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 ;
  input \gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_1 ;
  input \gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 ;
  input \gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_1 ;
  input \gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 ;
  input \gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_1 ;
  input \gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 ;
  input \gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_1 ;
  input \gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 ;
  input \gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_1 ;
  input \gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 ;
  input \gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_1 ;
  input \gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 ;
  input \gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_1 ;
  input \gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 ;
  input \gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_1 ;
  input \gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 ;
  input \gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_1 ;
  input \gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 ;
  input \gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_1 ;
  input \gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 ;
  input \gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_1 ;
  input \gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 ;
  input \gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_1 ;
  input \gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1 ;
  input \gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_1 ;
  input \gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 ;
  input \gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_1 ;
  input \gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 ;
  input \gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_1 ;
  input \gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 ;
  input [2:0]\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_3 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_2 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_2 ;
  input \my_full_reg[1]_1 ;
  input \my_full_reg[1]_2 ;
  input \my_full_reg[1]_3 ;
  input \my_full_reg[1]_4 ;
  input \my_full_reg[1]_5 ;
  input [67:0]Q;
  input [0:0]phy_if_empty_r_reg;
  input [0:0]if_empty_r;
  input phy_if_empty_r_reg_0;

  wire [67:0]Q;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ;
  wire \gen_mux_rd[0].mux_rd_fall0_r1[0]_i_2_n_0 ;
  wire \gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_fall1_r1[0]_i_2_n_0 ;
  wire \gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_fall2_r1[0]_i_2_n_0 ;
  wire \gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_fall3_r1[0]_i_2_n_0 ;
  wire \gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise0_r1[0]_i_2_n_0 ;
  wire [2:0]\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]_0 ;
  wire \gen_mux_rd[0].mux_rd_rise1_r1[0]_i_2_n_0 ;
  wire \gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise2_r1[0]_i_2_n_0 ;
  wire \gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise3_r1[0]_i_2_n_0 ;
  wire \gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ;
  wire \gen_mux_rd[1].mux_rd_fall0_r1[1]_i_2_n_0 ;
  wire \gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_fall1_r1[1]_i_2_n_0 ;
  wire \gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_fall2_r1[1]_i_2_n_0 ;
  wire \gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_fall3_r1[1]_i_2_n_0 ;
  wire \gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_rise0_r1[1]_i_2_n_0 ;
  wire \gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_rise1_r1[1]_i_2_n_0 ;
  wire \gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_rise2_r1[1]_i_2_n_0 ;
  wire \gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_rise3_r1[1]_i_2_n_0 ;
  wire \gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ;
  wire \gen_mux_rd[2].mux_rd_fall0_r1[2]_i_2_n_0 ;
  wire \gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_fall1_r1[2]_i_2_n_0 ;
  wire \gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_fall2_r1[2]_i_2_n_0 ;
  wire \gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_fall3_r1[2]_i_2_n_0 ;
  wire \gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise0_r1[2]_i_2_n_0 ;
  wire \gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise1_r1[2]_i_2_n_0 ;
  wire \gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise2_r1[2]_i_2_n_0 ;
  wire \gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise3_r1[2]_i_2_n_0 ;
  wire \gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ;
  wire \gen_mux_rd[3].mux_rd_fall0_r1[3]_i_2_n_0 ;
  wire \gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_fall1_r1[3]_i_2_n_0 ;
  wire \gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_fall2_r1[3]_i_2_n_0 ;
  wire \gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_fall3_r1[3]_i_2_n_0 ;
  wire \gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_rise0_r1[3]_i_2_n_0 ;
  wire \gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_rise1_r1[3]_i_2_n_0 ;
  wire \gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_rise2_r1[3]_i_2_n_0 ;
  wire \gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_rise3_r1[3]_i_2_n_0 ;
  wire \gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ;
  wire \gen_mux_rd[4].mux_rd_fall0_r1[4]_i_2_n_0 ;
  wire \gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_fall1_r1[4]_i_2_n_0 ;
  wire \gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_fall2_r1[4]_i_2_n_0 ;
  wire \gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_fall3_r1[4]_i_2_n_0 ;
  wire \gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise0_r1[4]_i_2_n_0 ;
  wire \gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise1_r1[4]_i_2_n_0 ;
  wire \gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise2_r1[4]_i_2_n_0 ;
  wire \gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise3_r1[4]_i_2_n_0 ;
  wire \gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ;
  wire \gen_mux_rd[5].mux_rd_fall0_r1[5]_i_2_n_0 ;
  wire \gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_fall1_r1[5]_i_2_n_0 ;
  wire \gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_fall2_r1[5]_i_2_n_0 ;
  wire \gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_fall3_r1[5]_i_2_n_0 ;
  wire \gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_rise0_r1[5]_i_2_n_0 ;
  wire \gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_rise1_r1[5]_i_2_n_0 ;
  wire \gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_rise2_r1[5]_i_2_n_0 ;
  wire \gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_rise3_r1[5]_i_2_n_0 ;
  wire \gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ;
  wire \gen_mux_rd[6].mux_rd_fall0_r1[6]_i_2_n_0 ;
  wire \gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_fall1_r1[6]_i_2_n_0 ;
  wire \gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_fall2_r1[6]_i_2_n_0 ;
  wire \gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_fall3_r1[6]_i_2_n_0 ;
  wire \gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise0_r1[6]_i_2_n_0 ;
  wire \gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise1_r1[6]_i_2_n_0 ;
  wire \gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise2_r1[6]_i_2_n_0 ;
  wire \gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise3_r1[6]_i_2_n_0 ;
  wire \gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ;
  wire \gen_mux_rd[7].mux_rd_fall0_r1[7]_i_2_n_0 ;
  wire \gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_fall1_r1[7]_i_2_n_0 ;
  wire \gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_fall2_r1[7]_i_2_n_0 ;
  wire \gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_fall3_r1[7]_i_2_n_0 ;
  wire \gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_rise0_r1[7]_i_2_n_0 ;
  wire \gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_rise1_r1[7]_i_2_n_0 ;
  wire \gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_rise2_r1[7]_i_2_n_0 ;
  wire \gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_rise3_r1[7]_i_2_n_0 ;
  wire \gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r[0]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r[0]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r[0]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r[0]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r[0]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r[0]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_1 ;
  wire [2:0]\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_3 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r[0]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r[0]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r[1]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r[1]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r[1]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r[1]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r[1]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r[1]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r[1]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r[1]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r[2]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r[2]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r[2]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r[2]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r[2]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r[2]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r[2]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r[2]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r[3]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r[3]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r[3]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r[3]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r[3]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r[3]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r[3]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r[3]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r[4]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r[4]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r[4]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r[4]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r[4]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r[4]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r[4]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r[4]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r[5]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r[5]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r[5]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r[5]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r[5]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r[5]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r[5]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r[5]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r[6]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r[6]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r[6]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r[6]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r[6]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r[6]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r[6]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r[6]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r[7]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r[7]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r[7]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r[7]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r[7]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r[7]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r[7]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r[7]_i_2_n_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_2 ;
  wire [0:0]if_empty_r;
  wire [0:0]if_empty_r_0;
  wire [0:0]if_empty_v;
  wire ififo_rst;
  wire [79:16]mem_out;
  wire mem_reg_0_3_12_17_n_0;
  wire mem_reg_0_3_12_17_n_1;
  wire mem_reg_0_3_12_17_n_2;
  wire mem_reg_0_3_12_17_n_3;
  wire [4:0]my_empty;
  wire \my_empty[4]_i_1__2_n_0 ;
  wire \my_empty[4]_i_2__6_n_0 ;
  wire my_empty_inst_rep__6_n_0;
  wire \my_empty_reg[4]_rep__0_n_0 ;
  wire \my_empty_reg[4]_rep_n_0 ;
  wire [1:0]my_full;
  wire \my_full[0]_i_1__6_n_0 ;
  wire \my_full[1]_i_1__6_n_0 ;
  wire \my_full[1]_i_2__6_n_0 ;
  wire \my_full_reg[1]_0 ;
  wire \my_full_reg[1]_1 ;
  wire \my_full_reg[1]_2 ;
  wire \my_full_reg[1]_3 ;
  wire \my_full_reg[1]_4 ;
  wire \my_full_reg[1]_5 ;
  wire p_0_out;
  wire [0:0]phy_if_empty_r_reg;
  wire phy_if_empty_r_reg_0;
  wire \po_stg2_wrcal_cnt_reg[2] ;
  wire \po_stg2_wrcal_cnt_reg[2]_0 ;
  wire \po_stg2_wrcal_cnt_reg[2]_1 ;
  wire \po_stg2_wrcal_cnt_reg[2]_10 ;
  wire \po_stg2_wrcal_cnt_reg[2]_11 ;
  wire \po_stg2_wrcal_cnt_reg[2]_12 ;
  wire \po_stg2_wrcal_cnt_reg[2]_13 ;
  wire \po_stg2_wrcal_cnt_reg[2]_14 ;
  wire \po_stg2_wrcal_cnt_reg[2]_15 ;
  wire \po_stg2_wrcal_cnt_reg[2]_16 ;
  wire \po_stg2_wrcal_cnt_reg[2]_17 ;
  wire \po_stg2_wrcal_cnt_reg[2]_18 ;
  wire \po_stg2_wrcal_cnt_reg[2]_19 ;
  wire \po_stg2_wrcal_cnt_reg[2]_2 ;
  wire \po_stg2_wrcal_cnt_reg[2]_20 ;
  wire \po_stg2_wrcal_cnt_reg[2]_21 ;
  wire \po_stg2_wrcal_cnt_reg[2]_22 ;
  wire \po_stg2_wrcal_cnt_reg[2]_23 ;
  wire \po_stg2_wrcal_cnt_reg[2]_24 ;
  wire \po_stg2_wrcal_cnt_reg[2]_25 ;
  wire \po_stg2_wrcal_cnt_reg[2]_26 ;
  wire \po_stg2_wrcal_cnt_reg[2]_27 ;
  wire \po_stg2_wrcal_cnt_reg[2]_28 ;
  wire \po_stg2_wrcal_cnt_reg[2]_29 ;
  wire \po_stg2_wrcal_cnt_reg[2]_3 ;
  wire \po_stg2_wrcal_cnt_reg[2]_30 ;
  wire \po_stg2_wrcal_cnt_reg[2]_31 ;
  wire \po_stg2_wrcal_cnt_reg[2]_32 ;
  wire \po_stg2_wrcal_cnt_reg[2]_33 ;
  wire \po_stg2_wrcal_cnt_reg[2]_34 ;
  wire \po_stg2_wrcal_cnt_reg[2]_35 ;
  wire \po_stg2_wrcal_cnt_reg[2]_36 ;
  wire \po_stg2_wrcal_cnt_reg[2]_37 ;
  wire \po_stg2_wrcal_cnt_reg[2]_38 ;
  wire \po_stg2_wrcal_cnt_reg[2]_39 ;
  wire \po_stg2_wrcal_cnt_reg[2]_4 ;
  wire \po_stg2_wrcal_cnt_reg[2]_40 ;
  wire \po_stg2_wrcal_cnt_reg[2]_41 ;
  wire \po_stg2_wrcal_cnt_reg[2]_42 ;
  wire \po_stg2_wrcal_cnt_reg[2]_43 ;
  wire \po_stg2_wrcal_cnt_reg[2]_44 ;
  wire \po_stg2_wrcal_cnt_reg[2]_45 ;
  wire \po_stg2_wrcal_cnt_reg[2]_46 ;
  wire \po_stg2_wrcal_cnt_reg[2]_47 ;
  wire \po_stg2_wrcal_cnt_reg[2]_48 ;
  wire \po_stg2_wrcal_cnt_reg[2]_49 ;
  wire \po_stg2_wrcal_cnt_reg[2]_5 ;
  wire \po_stg2_wrcal_cnt_reg[2]_50 ;
  wire \po_stg2_wrcal_cnt_reg[2]_51 ;
  wire \po_stg2_wrcal_cnt_reg[2]_52 ;
  wire \po_stg2_wrcal_cnt_reg[2]_53 ;
  wire \po_stg2_wrcal_cnt_reg[2]_54 ;
  wire \po_stg2_wrcal_cnt_reg[2]_55 ;
  wire \po_stg2_wrcal_cnt_reg[2]_56 ;
  wire \po_stg2_wrcal_cnt_reg[2]_57 ;
  wire \po_stg2_wrcal_cnt_reg[2]_58 ;
  wire \po_stg2_wrcal_cnt_reg[2]_59 ;
  wire \po_stg2_wrcal_cnt_reg[2]_6 ;
  wire \po_stg2_wrcal_cnt_reg[2]_60 ;
  wire \po_stg2_wrcal_cnt_reg[2]_61 ;
  wire \po_stg2_wrcal_cnt_reg[2]_7 ;
  wire \po_stg2_wrcal_cnt_reg[2]_8 ;
  wire \po_stg2_wrcal_cnt_reg[2]_9 ;
  wire \rd_mux_sel_r_reg[2] ;
  wire \rd_mux_sel_r_reg[2]_0 ;
  wire \rd_mux_sel_r_reg[2]_1 ;
  wire \rd_mux_sel_r_reg[2]_10 ;
  wire \rd_mux_sel_r_reg[2]_11 ;
  wire \rd_mux_sel_r_reg[2]_12 ;
  wire \rd_mux_sel_r_reg[2]_13 ;
  wire \rd_mux_sel_r_reg[2]_14 ;
  wire \rd_mux_sel_r_reg[2]_15 ;
  wire \rd_mux_sel_r_reg[2]_16 ;
  wire \rd_mux_sel_r_reg[2]_17 ;
  wire \rd_mux_sel_r_reg[2]_18 ;
  wire \rd_mux_sel_r_reg[2]_19 ;
  wire \rd_mux_sel_r_reg[2]_2 ;
  wire \rd_mux_sel_r_reg[2]_20 ;
  wire \rd_mux_sel_r_reg[2]_21 ;
  wire \rd_mux_sel_r_reg[2]_22 ;
  wire \rd_mux_sel_r_reg[2]_23 ;
  wire \rd_mux_sel_r_reg[2]_24 ;
  wire \rd_mux_sel_r_reg[2]_25 ;
  wire \rd_mux_sel_r_reg[2]_26 ;
  wire \rd_mux_sel_r_reg[2]_27 ;
  wire \rd_mux_sel_r_reg[2]_28 ;
  wire \rd_mux_sel_r_reg[2]_29 ;
  wire \rd_mux_sel_r_reg[2]_3 ;
  wire \rd_mux_sel_r_reg[2]_30 ;
  wire \rd_mux_sel_r_reg[2]_31 ;
  wire \rd_mux_sel_r_reg[2]_32 ;
  wire \rd_mux_sel_r_reg[2]_33 ;
  wire \rd_mux_sel_r_reg[2]_34 ;
  wire \rd_mux_sel_r_reg[2]_35 ;
  wire \rd_mux_sel_r_reg[2]_36 ;
  wire \rd_mux_sel_r_reg[2]_37 ;
  wire \rd_mux_sel_r_reg[2]_38 ;
  wire \rd_mux_sel_r_reg[2]_39 ;
  wire \rd_mux_sel_r_reg[2]_4 ;
  wire \rd_mux_sel_r_reg[2]_40 ;
  wire \rd_mux_sel_r_reg[2]_41 ;
  wire \rd_mux_sel_r_reg[2]_42 ;
  wire \rd_mux_sel_r_reg[2]_43 ;
  wire \rd_mux_sel_r_reg[2]_44 ;
  wire \rd_mux_sel_r_reg[2]_45 ;
  wire \rd_mux_sel_r_reg[2]_46 ;
  wire \rd_mux_sel_r_reg[2]_47 ;
  wire \rd_mux_sel_r_reg[2]_48 ;
  wire \rd_mux_sel_r_reg[2]_49 ;
  wire \rd_mux_sel_r_reg[2]_5 ;
  wire \rd_mux_sel_r_reg[2]_50 ;
  wire \rd_mux_sel_r_reg[2]_51 ;
  wire \rd_mux_sel_r_reg[2]_52 ;
  wire \rd_mux_sel_r_reg[2]_53 ;
  wire \rd_mux_sel_r_reg[2]_54 ;
  wire \rd_mux_sel_r_reg[2]_55 ;
  wire \rd_mux_sel_r_reg[2]_56 ;
  wire \rd_mux_sel_r_reg[2]_57 ;
  wire \rd_mux_sel_r_reg[2]_58 ;
  wire \rd_mux_sel_r_reg[2]_59 ;
  wire \rd_mux_sel_r_reg[2]_6 ;
  wire \rd_mux_sel_r_reg[2]_60 ;
  wire \rd_mux_sel_r_reg[2]_61 ;
  wire \rd_mux_sel_r_reg[2]_62 ;
  wire \rd_mux_sel_r_reg[2]_7 ;
  wire \rd_mux_sel_r_reg[2]_8 ;
  wire \rd_mux_sel_r_reg[2]_9 ;
  wire [1:0]rd_ptr;
  wire \rd_ptr[0]_i_1__6_n_0 ;
  wire \rd_ptr[1]_i_1__6_n_0 ;
  (* RTL_KEEP = "true" *) (* syn_maxfan = "10" *) wire [1:0]rd_ptr_timing;
  wire \rd_ptr_timing[0]_i_1__14_n_0 ;
  wire \rd_ptr_timing[1]_i_1__14_n_0 ;
  wire \rd_ptr_timing_reg[1]_0 ;
  (* MAX_FANOUT = "40" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire wr_en;
  wire [1:0]wr_ptr;
  wire \wr_ptr[0]_i_1__14_n_0 ;
  wire \wr_ptr[1]_i_1__14_n_0 ;
  wire [1:0]NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_66_71_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_72_77_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_78_79_DOB_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_78_79_DOC_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_78_79_DOD_UNCONNECTED;

  (* SOFT_HLUTNM = "soft_lutpair1103" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[152]_INST_0 
       (.I0(Q[6]),
        .I1(my_empty_inst_rep__6_n_0),
        .I2(mem_out[18]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ));
  (* SOFT_HLUTNM = "soft_lutpair1098" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[153]_INST_0 
       (.I0(Q[14]),
        .I1(my_empty_inst_rep__6_n_0),
        .I2(mem_out[26]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ));
  (* SOFT_HLUTNM = "soft_lutpair1107" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[154]_INST_0 
       (.I0(Q[22]),
        .I1(my_empty_inst_rep__6_n_0),
        .I2(mem_out[34]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ));
  (* SOFT_HLUTNM = "soft_lutpair1101" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[155]_INST_0 
       (.I0(Q[30]),
        .I1(my_empty_inst_rep__6_n_0),
        .I2(mem_out[42]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ));
  (* SOFT_HLUTNM = "soft_lutpair1096" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[156]_INST_0 
       (.I0(Q[38]),
        .I1(my_empty[4]),
        .I2(mem_out[50]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ));
  (* SOFT_HLUTNM = "soft_lutpair1105" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[157]_INST_0 
       (.I0(Q[46]),
        .I1(my_empty[4]),
        .I2(mem_out[58]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ));
  (* SOFT_HLUTNM = "soft_lutpair1099" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[158]_INST_0 
       (.I0(Q[54]),
        .I1(my_empty[4]),
        .I2(mem_out[66]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ));
  (* SOFT_HLUTNM = "soft_lutpair1095" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[159]_INST_0 
       (.I0(Q[62]),
        .I1(my_empty[4]),
        .I2(mem_out[74]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] ));
  (* SOFT_HLUTNM = "soft_lutpair1122" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[216]_INST_0 
       (.I0(Q[7]),
        .I1(my_empty_inst_rep__6_n_0),
        .I2(mem_out[19]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ));
  (* SOFT_HLUTNM = "soft_lutpair1112" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[217]_INST_0 
       (.I0(Q[15]),
        .I1(my_empty_inst_rep__6_n_0),
        .I2(mem_out[27]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ));
  (* SOFT_HLUTNM = "soft_lutpair1118" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[218]_INST_0 
       (.I0(Q[23]),
        .I1(my_empty_inst_rep__6_n_0),
        .I2(mem_out[35]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ));
  (* SOFT_HLUTNM = "soft_lutpair1118" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[219]_INST_0 
       (.I0(Q[31]),
        .I1(my_empty_inst_rep__6_n_0),
        .I2(mem_out[43]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ));
  (* SOFT_HLUTNM = "soft_lutpair1110" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[220]_INST_0 
       (.I0(Q[39]),
        .I1(my_empty[4]),
        .I2(mem_out[51]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ));
  (* SOFT_HLUTNM = "soft_lutpair1117" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[221]_INST_0 
       (.I0(Q[47]),
        .I1(my_empty[4]),
        .I2(mem_out[59]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ));
  (* SOFT_HLUTNM = "soft_lutpair1116" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[222]_INST_0 
       (.I0(Q[55]),
        .I1(my_empty[4]),
        .I2(mem_out[67]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ));
  (* SOFT_HLUTNM = "soft_lutpair1106" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[223]_INST_0 
       (.I0(Q[63]),
        .I1(my_empty[4]),
        .I2(mem_out[75]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] ));
  (* SOFT_HLUTNM = "soft_lutpair1108" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[24]_INST_0 
       (.I0(Q[4]),
        .I1(my_empty_inst_rep__6_n_0),
        .I2(mem_out[16]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ));
  (* SOFT_HLUTNM = "soft_lutpair1102" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[25]_INST_0 
       (.I0(Q[12]),
        .I1(my_empty_inst_rep__6_n_0),
        .I2(mem_out[24]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ));
  (* SOFT_HLUTNM = "soft_lutpair1097" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[26]_INST_0 
       (.I0(Q[20]),
        .I1(my_empty_inst_rep__6_n_0),
        .I2(mem_out[32]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ));
  (* SOFT_HLUTNM = "soft_lutpair1092" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[27]_INST_0 
       (.I0(Q[28]),
        .I1(my_empty_inst_rep__6_n_0),
        .I2(mem_out[40]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ));
  (* SOFT_HLUTNM = "soft_lutpair1098" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[280]_INST_0 
       (.I0(Q[8]),
        .I1(my_empty_inst_rep__6_n_0),
        .I2(mem_out[20]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ));
  (* SOFT_HLUTNM = "soft_lutpair1107" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[281]_INST_0 
       (.I0(Q[16]),
        .I1(my_empty_inst_rep__6_n_0),
        .I2(mem_out[28]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ));
  (* SOFT_HLUTNM = "soft_lutpair1101" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[282]_INST_0 
       (.I0(Q[24]),
        .I1(my_empty_inst_rep__6_n_0),
        .I2(mem_out[36]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ));
  (* SOFT_HLUTNM = "soft_lutpair1092" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[283]_INST_0 
       (.I0(Q[32]),
        .I1(my_empty_inst_rep__6_n_0),
        .I2(mem_out[44]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ));
  (* SOFT_HLUTNM = "soft_lutpair1105" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[284]_INST_0 
       (.I0(Q[40]),
        .I1(my_empty[4]),
        .I2(mem_out[52]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ));
  (* SOFT_HLUTNM = "soft_lutpair1100" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[285]_INST_0 
       (.I0(Q[48]),
        .I1(my_empty[4]),
        .I2(mem_out[60]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ));
  (* SOFT_HLUTNM = "soft_lutpair1095" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[286]_INST_0 
       (.I0(Q[56]),
        .I1(my_empty[4]),
        .I2(mem_out[68]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ));
  (* SOFT_HLUTNM = "soft_lutpair1104" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[287]_INST_0 
       (.I0(Q[64]),
        .I1(my_empty[4]),
        .I2(mem_out[76]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] ));
  (* SOFT_HLUTNM = "soft_lutpair1094" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[28]_INST_0 
       (.I0(Q[36]),
        .I1(my_empty[4]),
        .I2(mem_out[48]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ));
  (* SOFT_HLUTNM = "soft_lutpair1093" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[29]_INST_0 
       (.I0(Q[44]),
        .I1(my_empty[4]),
        .I2(mem_out[56]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ));
  (* SOFT_HLUTNM = "soft_lutpair1094" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[30]_INST_0 
       (.I0(Q[52]),
        .I1(my_empty[4]),
        .I2(mem_out[64]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ));
  (* SOFT_HLUTNM = "soft_lutpair1093" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[31]_INST_0 
       (.I0(Q[60]),
        .I1(my_empty[4]),
        .I2(mem_out[72]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ));
  (* SOFT_HLUTNM = "soft_lutpair1113" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[344]_INST_0 
       (.I0(Q[9]),
        .I1(my_empty_inst_rep__6_n_0),
        .I2(mem_out[21]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ));
  (* SOFT_HLUTNM = "soft_lutpair1121" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[345]_INST_0 
       (.I0(Q[17]),
        .I1(my_empty_inst_rep__6_n_0),
        .I2(mem_out[29]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ));
  (* SOFT_HLUTNM = "soft_lutpair1120" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[346]_INST_0 
       (.I0(Q[25]),
        .I1(my_empty_inst_rep__6_n_0),
        .I2(mem_out[37]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ));
  (* SOFT_HLUTNM = "soft_lutpair1111" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[347]_INST_0 
       (.I0(Q[33]),
        .I1(my_empty_inst_rep__6_n_0),
        .I2(mem_out[45]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ));
  (* SOFT_HLUTNM = "soft_lutpair1119" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[348]_INST_0 
       (.I0(Q[41]),
        .I1(my_empty[4]),
        .I2(mem_out[53]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ));
  (* SOFT_HLUTNM = "soft_lutpair1116" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[349]_INST_0 
       (.I0(Q[49]),
        .I1(my_empty[4]),
        .I2(mem_out[61]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ));
  (* SOFT_HLUTNM = "soft_lutpair1106" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[350]_INST_0 
       (.I0(Q[57]),
        .I1(my_empty[4]),
        .I2(mem_out[69]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ));
  (* SOFT_HLUTNM = "soft_lutpair1114" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[351]_INST_0 
       (.I0(Q[65]),
        .I1(my_empty[4]),
        .I2(mem_out[77]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] ));
  (* SOFT_HLUTNM = "soft_lutpair1108" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[408]_INST_0 
       (.I0(Q[10]),
        .I1(my_empty_inst_rep__6_n_0),
        .I2(mem_out[22]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ));
  (* SOFT_HLUTNM = "soft_lutpair1102" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[409]_INST_0 
       (.I0(Q[18]),
        .I1(my_empty_inst_rep__6_n_0),
        .I2(mem_out[30]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ));
  (* SOFT_HLUTNM = "soft_lutpair1097" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[410]_INST_0 
       (.I0(Q[26]),
        .I1(my_empty_inst_rep__6_n_0),
        .I2(mem_out[38]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ));
  (* SOFT_HLUTNM = "soft_lutpair1103" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[411]_INST_0 
       (.I0(Q[34]),
        .I1(my_empty_inst_rep__6_n_0),
        .I2(mem_out[46]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ));
  (* SOFT_HLUTNM = "soft_lutpair1100" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[412]_INST_0 
       (.I0(Q[42]),
        .I1(my_empty[4]),
        .I2(mem_out[54]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ));
  (* SOFT_HLUTNM = "soft_lutpair1096" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[413]_INST_0 
       (.I0(Q[50]),
        .I1(my_empty[4]),
        .I2(mem_out[62]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ));
  (* SOFT_HLUTNM = "soft_lutpair1104" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[414]_INST_0 
       (.I0(Q[58]),
        .I1(my_empty[4]),
        .I2(mem_out[70]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ));
  (* SOFT_HLUTNM = "soft_lutpair1099" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[415]_INST_0 
       (.I0(Q[66]),
        .I1(my_empty[4]),
        .I2(mem_out[78]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] ));
  (* SOFT_HLUTNM = "soft_lutpair1123" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[472]_INST_0 
       (.I0(Q[11]),
        .I1(my_empty_inst_rep__6_n_0),
        .I2(mem_out[23]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ));
  (* SOFT_HLUTNM = "soft_lutpair1121" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[473]_INST_0 
       (.I0(Q[19]),
        .I1(my_empty_inst_rep__6_n_0),
        .I2(mem_out[31]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ));
  (* SOFT_HLUTNM = "soft_lutpair1111" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[474]_INST_0 
       (.I0(Q[27]),
        .I1(my_empty_inst_rep__6_n_0),
        .I2(mem_out[39]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ));
  (* SOFT_HLUTNM = "soft_lutpair1113" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[475]_INST_0 
       (.I0(Q[35]),
        .I1(my_empty_inst_rep__6_n_0),
        .I2(mem_out[47]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ));
  (* SOFT_HLUTNM = "soft_lutpair1117" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[476]_INST_0 
       (.I0(Q[43]),
        .I1(my_empty[4]),
        .I2(mem_out[55]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ));
  (* SOFT_HLUTNM = "soft_lutpair1109" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[477]_INST_0 
       (.I0(Q[51]),
        .I1(my_empty[4]),
        .I2(mem_out[63]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ));
  (* SOFT_HLUTNM = "soft_lutpair1115" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[478]_INST_0 
       (.I0(Q[59]),
        .I1(my_empty[4]),
        .I2(mem_out[71]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ));
  (* SOFT_HLUTNM = "soft_lutpair1114" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[479]_INST_0 
       (.I0(Q[67]),
        .I1(my_empty[4]),
        .I2(mem_out[79]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ));
  (* SOFT_HLUTNM = "soft_lutpair1123" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[88]_INST_0 
       (.I0(Q[5]),
        .I1(my_empty_inst_rep__6_n_0),
        .I2(mem_out[17]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ));
  (* SOFT_HLUTNM = "soft_lutpair1122" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[89]_INST_0 
       (.I0(Q[13]),
        .I1(my_empty_inst_rep__6_n_0),
        .I2(mem_out[25]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ));
  (* SOFT_HLUTNM = "soft_lutpair1112" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[90]_INST_0 
       (.I0(Q[21]),
        .I1(my_empty_inst_rep__6_n_0),
        .I2(mem_out[33]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ));
  (* SOFT_HLUTNM = "soft_lutpair1120" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[91]_INST_0 
       (.I0(Q[29]),
        .I1(my_empty_inst_rep__6_n_0),
        .I2(mem_out[41]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ));
  (* SOFT_HLUTNM = "soft_lutpair1119" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[92]_INST_0 
       (.I0(Q[37]),
        .I1(my_empty[4]),
        .I2(mem_out[49]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ));
  (* SOFT_HLUTNM = "soft_lutpair1110" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[93]_INST_0 
       (.I0(Q[45]),
        .I1(my_empty[4]),
        .I2(mem_out[57]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ));
  (* SOFT_HLUTNM = "soft_lutpair1109" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[94]_INST_0 
       (.I0(Q[53]),
        .I1(my_empty[4]),
        .I2(mem_out[65]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ));
  (* SOFT_HLUTNM = "soft_lutpair1115" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[95]_INST_0 
       (.I0(Q[61]),
        .I1(my_empty[4]),
        .I2(mem_out[73]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[0].mux_rd_fall0_r1[0]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_1 ),
        .O(\gen_mux_rd[0].mux_rd_fall0_r1[0]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[0].mux_rd_fall0_r1_reg[0]_i_1 
       (.I0(\gen_mux_rd[0].mux_rd_fall0_r1[0]_i_2_n_0 ),
        .I1(\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ),
        .O(\rd_mux_sel_r_reg[2]_7 ),
        .S(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[0].mux_rd_fall1_r1[0]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_1 ),
        .O(\gen_mux_rd[0].mux_rd_fall1_r1[0]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[0].mux_rd_fall1_r1_reg[0]_i_1 
       (.I0(\gen_mux_rd[0].mux_rd_fall1_r1[0]_i_2_n_0 ),
        .I1(\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ),
        .O(\rd_mux_sel_r_reg[2]_23 ),
        .S(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[0].mux_rd_fall2_r1[0]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_1 ),
        .O(\gen_mux_rd[0].mux_rd_fall2_r1[0]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[0].mux_rd_fall2_r1_reg[0]_i_1 
       (.I0(\gen_mux_rd[0].mux_rd_fall2_r1[0]_i_2_n_0 ),
        .I1(\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ),
        .O(\rd_mux_sel_r_reg[2]_39 ),
        .S(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[0].mux_rd_fall3_r1[0]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_1 ),
        .O(\gen_mux_rd[0].mux_rd_fall3_r1[0]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[0].mux_rd_fall3_r1_reg[0]_i_1 
       (.I0(\gen_mux_rd[0].mux_rd_fall3_r1[0]_i_2_n_0 ),
        .I1(\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ),
        .O(\rd_mux_sel_r_reg[2]_55 ),
        .S(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[0].mux_rd_rise0_r1[0]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1 ),
        .O(\gen_mux_rd[0].mux_rd_rise0_r1[0]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]_i_1 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r1[0]_i_2_n_0 ),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0]_0 ),
        .O(\rd_mux_sel_r_reg[2] ),
        .S(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[0].mux_rd_rise1_r1[0]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_1 ),
        .O(\gen_mux_rd[0].mux_rd_rise1_r1[0]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[0].mux_rd_rise1_r1_reg[0]_i_1 
       (.I0(\gen_mux_rd[0].mux_rd_rise1_r1[0]_i_2_n_0 ),
        .I1(\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ),
        .O(\rd_mux_sel_r_reg[2]_15 ),
        .S(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[0].mux_rd_rise2_r1[0]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_1 ),
        .O(\gen_mux_rd[0].mux_rd_rise2_r1[0]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[0].mux_rd_rise2_r1_reg[0]_i_1 
       (.I0(\gen_mux_rd[0].mux_rd_rise2_r1[0]_i_2_n_0 ),
        .I1(\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ),
        .O(\rd_mux_sel_r_reg[2]_31 ),
        .S(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[0].mux_rd_rise3_r1[0]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_1 ),
        .O(\gen_mux_rd[0].mux_rd_rise3_r1[0]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[0].mux_rd_rise3_r1_reg[0]_i_1 
       (.I0(\gen_mux_rd[0].mux_rd_rise3_r1[0]_i_2_n_0 ),
        .I1(\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ),
        .O(\rd_mux_sel_r_reg[2]_47 ),
        .S(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[1].mux_rd_fall0_r1[1]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 ),
        .O(\gen_mux_rd[1].mux_rd_fall0_r1[1]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[1].mux_rd_fall0_r1_reg[1]_i_1 
       (.I0(\gen_mux_rd[1].mux_rd_fall0_r1[1]_i_2_n_0 ),
        .I1(\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ),
        .O(\rd_mux_sel_r_reg[2]_8 ),
        .S(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[1].mux_rd_fall1_r1[1]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 ),
        .O(\gen_mux_rd[1].mux_rd_fall1_r1[1]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[1].mux_rd_fall1_r1_reg[1]_i_1 
       (.I0(\gen_mux_rd[1].mux_rd_fall1_r1[1]_i_2_n_0 ),
        .I1(\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ),
        .O(\rd_mux_sel_r_reg[2]_24 ),
        .S(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[1].mux_rd_fall2_r1[1]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 ),
        .O(\gen_mux_rd[1].mux_rd_fall2_r1[1]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[1].mux_rd_fall2_r1_reg[1]_i_1 
       (.I0(\gen_mux_rd[1].mux_rd_fall2_r1[1]_i_2_n_0 ),
        .I1(\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ),
        .O(\rd_mux_sel_r_reg[2]_40 ),
        .S(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[1].mux_rd_fall3_r1[1]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1 ),
        .O(\gen_mux_rd[1].mux_rd_fall3_r1[1]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[1].mux_rd_fall3_r1_reg[1]_i_1 
       (.I0(\gen_mux_rd[1].mux_rd_fall3_r1[1]_i_2_n_0 ),
        .I1(\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ),
        .O(\rd_mux_sel_r_reg[2]_56 ),
        .S(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[1].mux_rd_rise0_r1[1]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1 ),
        .O(\gen_mux_rd[1].mux_rd_rise0_r1[1]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[1].mux_rd_rise0_r1_reg[1]_i_1 
       (.I0(\gen_mux_rd[1].mux_rd_rise0_r1[1]_i_2_n_0 ),
        .I1(\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ),
        .O(\rd_mux_sel_r_reg[2]_0 ),
        .S(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[1].mux_rd_rise1_r1[1]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 ),
        .O(\gen_mux_rd[1].mux_rd_rise1_r1[1]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[1].mux_rd_rise1_r1_reg[1]_i_1 
       (.I0(\gen_mux_rd[1].mux_rd_rise1_r1[1]_i_2_n_0 ),
        .I1(\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ),
        .O(\rd_mux_sel_r_reg[2]_16 ),
        .S(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[1].mux_rd_rise2_r1[1]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 ),
        .O(\gen_mux_rd[1].mux_rd_rise2_r1[1]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[1].mux_rd_rise2_r1_reg[1]_i_1 
       (.I0(\gen_mux_rd[1].mux_rd_rise2_r1[1]_i_2_n_0 ),
        .I1(\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ),
        .O(\rd_mux_sel_r_reg[2]_32 ),
        .S(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[1].mux_rd_rise3_r1[1]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 ),
        .O(\gen_mux_rd[1].mux_rd_rise3_r1[1]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[1].mux_rd_rise3_r1_reg[1]_i_1 
       (.I0(\gen_mux_rd[1].mux_rd_rise3_r1[1]_i_2_n_0 ),
        .I1(\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ),
        .O(\rd_mux_sel_r_reg[2]_48 ),
        .S(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[2].mux_rd_fall0_r1[2]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_1 ),
        .O(\gen_mux_rd[2].mux_rd_fall0_r1[2]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[2].mux_rd_fall0_r1_reg[2]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall0_r1[2]_i_2_n_0 ),
        .I1(\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ),
        .O(\rd_mux_sel_r_reg[2]_9 ),
        .S(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[2].mux_rd_fall1_r1[2]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_1 ),
        .O(\gen_mux_rd[2].mux_rd_fall1_r1[2]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[2].mux_rd_fall1_r1_reg[2]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall1_r1[2]_i_2_n_0 ),
        .I1(\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ),
        .O(\rd_mux_sel_r_reg[2]_25 ),
        .S(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[2].mux_rd_fall2_r1[2]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_1 ),
        .O(\gen_mux_rd[2].mux_rd_fall2_r1[2]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[2].mux_rd_fall2_r1_reg[2]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall2_r1[2]_i_2_n_0 ),
        .I1(\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ),
        .O(\rd_mux_sel_r_reg[2]_41 ),
        .S(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[2].mux_rd_fall3_r1[2]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_1 ),
        .O(\gen_mux_rd[2].mux_rd_fall3_r1[2]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[2].mux_rd_fall3_r1_reg[2]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r1[2]_i_2_n_0 ),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ),
        .O(\rd_mux_sel_r_reg[2]_57 ),
        .S(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[2].mux_rd_rise0_r1[2]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1 ),
        .O(\gen_mux_rd[2].mux_rd_rise0_r1[2]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[2].mux_rd_rise0_r1_reg[2]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_rise0_r1[2]_i_2_n_0 ),
        .I1(\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ),
        .O(\rd_mux_sel_r_reg[2]_1 ),
        .S(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[2].mux_rd_rise1_r1[2]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_1 ),
        .O(\gen_mux_rd[2].mux_rd_rise1_r1[2]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[2].mux_rd_rise1_r1_reg[2]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_rise1_r1[2]_i_2_n_0 ),
        .I1(\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ),
        .O(\rd_mux_sel_r_reg[2]_17 ),
        .S(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[2].mux_rd_rise2_r1[2]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_1 ),
        .O(\gen_mux_rd[2].mux_rd_rise2_r1[2]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[2].mux_rd_rise2_r1_reg[2]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_rise2_r1[2]_i_2_n_0 ),
        .I1(\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ),
        .O(\rd_mux_sel_r_reg[2]_33 ),
        .S(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[2].mux_rd_rise3_r1[2]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_1 ),
        .O(\gen_mux_rd[2].mux_rd_rise3_r1[2]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[2].mux_rd_rise3_r1_reg[2]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_rise3_r1[2]_i_2_n_0 ),
        .I1(\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ),
        .O(\rd_mux_sel_r_reg[2]_49 ),
        .S(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[3].mux_rd_fall0_r1[3]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 ),
        .O(\gen_mux_rd[3].mux_rd_fall0_r1[3]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[3].mux_rd_fall0_r1_reg[3]_i_1 
       (.I0(\gen_mux_rd[3].mux_rd_fall0_r1[3]_i_2_n_0 ),
        .I1(\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ),
        .O(\rd_mux_sel_r_reg[2]_10 ),
        .S(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[3].mux_rd_fall1_r1[3]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 ),
        .O(\gen_mux_rd[3].mux_rd_fall1_r1[3]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[3].mux_rd_fall1_r1_reg[3]_i_1 
       (.I0(\gen_mux_rd[3].mux_rd_fall1_r1[3]_i_2_n_0 ),
        .I1(\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ),
        .O(\rd_mux_sel_r_reg[2]_26 ),
        .S(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[3].mux_rd_fall2_r1[3]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 ),
        .O(\gen_mux_rd[3].mux_rd_fall2_r1[3]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[3].mux_rd_fall2_r1_reg[3]_i_1 
       (.I0(\gen_mux_rd[3].mux_rd_fall2_r1[3]_i_2_n_0 ),
        .I1(\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ),
        .O(\rd_mux_sel_r_reg[2]_42 ),
        .S(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[3].mux_rd_fall3_r1[3]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 ),
        .O(\gen_mux_rd[3].mux_rd_fall3_r1[3]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[3].mux_rd_fall3_r1_reg[3]_i_1 
       (.I0(\gen_mux_rd[3].mux_rd_fall3_r1[3]_i_2_n_0 ),
        .I1(\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ),
        .O(\rd_mux_sel_r_reg[2]_58 ),
        .S(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[3].mux_rd_rise0_r1[3]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 ),
        .O(\gen_mux_rd[3].mux_rd_rise0_r1[3]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[3].mux_rd_rise0_r1_reg[3]_i_1 
       (.I0(\gen_mux_rd[3].mux_rd_rise0_r1[3]_i_2_n_0 ),
        .I1(\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ),
        .O(\rd_mux_sel_r_reg[2]_2 ),
        .S(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[3].mux_rd_rise1_r1[3]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 ),
        .O(\gen_mux_rd[3].mux_rd_rise1_r1[3]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[3].mux_rd_rise1_r1_reg[3]_i_1 
       (.I0(\gen_mux_rd[3].mux_rd_rise1_r1[3]_i_2_n_0 ),
        .I1(\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ),
        .O(\rd_mux_sel_r_reg[2]_18 ),
        .S(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[3].mux_rd_rise2_r1[3]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 ),
        .O(\gen_mux_rd[3].mux_rd_rise2_r1[3]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[3].mux_rd_rise2_r1_reg[3]_i_1 
       (.I0(\gen_mux_rd[3].mux_rd_rise2_r1[3]_i_2_n_0 ),
        .I1(\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ),
        .O(\rd_mux_sel_r_reg[2]_34 ),
        .S(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[3].mux_rd_rise3_r1[3]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 ),
        .O(\gen_mux_rd[3].mux_rd_rise3_r1[3]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[3].mux_rd_rise3_r1_reg[3]_i_1 
       (.I0(\gen_mux_rd[3].mux_rd_rise3_r1[3]_i_2_n_0 ),
        .I1(\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ),
        .O(\rd_mux_sel_r_reg[2]_50 ),
        .S(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[4].mux_rd_fall0_r1[4]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_1 ),
        .O(\gen_mux_rd[4].mux_rd_fall0_r1[4]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[4].mux_rd_fall0_r1_reg[4]_i_1 
       (.I0(\gen_mux_rd[4].mux_rd_fall0_r1[4]_i_2_n_0 ),
        .I1(\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ),
        .O(\rd_mux_sel_r_reg[2]_11 ),
        .S(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[4].mux_rd_fall1_r1[4]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_1 ),
        .O(\gen_mux_rd[4].mux_rd_fall1_r1[4]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[4].mux_rd_fall1_r1_reg[4]_i_1 
       (.I0(\gen_mux_rd[4].mux_rd_fall1_r1[4]_i_2_n_0 ),
        .I1(\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ),
        .O(\rd_mux_sel_r_reg[2]_27 ),
        .S(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[4].mux_rd_fall2_r1[4]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_1 ),
        .O(\gen_mux_rd[4].mux_rd_fall2_r1[4]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[4].mux_rd_fall2_r1_reg[4]_i_1 
       (.I0(\gen_mux_rd[4].mux_rd_fall2_r1[4]_i_2_n_0 ),
        .I1(\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ),
        .O(\rd_mux_sel_r_reg[2]_43 ),
        .S(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[4].mux_rd_fall3_r1[4]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_1 ),
        .O(\gen_mux_rd[4].mux_rd_fall3_r1[4]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[4].mux_rd_fall3_r1_reg[4]_i_1 
       (.I0(\gen_mux_rd[4].mux_rd_fall3_r1[4]_i_2_n_0 ),
        .I1(\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ),
        .O(\rd_mux_sel_r_reg[2]_59 ),
        .S(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[4].mux_rd_rise0_r1[4]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_1 ),
        .O(\gen_mux_rd[4].mux_rd_rise0_r1[4]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[4].mux_rd_rise0_r1_reg[4]_i_1 
       (.I0(\gen_mux_rd[4].mux_rd_rise0_r1[4]_i_2_n_0 ),
        .I1(\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ),
        .O(\rd_mux_sel_r_reg[2]_3 ),
        .S(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[4].mux_rd_rise1_r1[4]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_1 ),
        .O(\gen_mux_rd[4].mux_rd_rise1_r1[4]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[4].mux_rd_rise1_r1_reg[4]_i_1 
       (.I0(\gen_mux_rd[4].mux_rd_rise1_r1[4]_i_2_n_0 ),
        .I1(\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ),
        .O(\rd_mux_sel_r_reg[2]_19 ),
        .S(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[4].mux_rd_rise2_r1[4]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_1 ),
        .O(\gen_mux_rd[4].mux_rd_rise2_r1[4]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[4].mux_rd_rise2_r1_reg[4]_i_1 
       (.I0(\gen_mux_rd[4].mux_rd_rise2_r1[4]_i_2_n_0 ),
        .I1(\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ),
        .O(\rd_mux_sel_r_reg[2]_35 ),
        .S(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[4].mux_rd_rise3_r1[4]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_1 ),
        .O(\gen_mux_rd[4].mux_rd_rise3_r1[4]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[4].mux_rd_rise3_r1_reg[4]_i_1 
       (.I0(\gen_mux_rd[4].mux_rd_rise3_r1[4]_i_2_n_0 ),
        .I1(\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ),
        .O(\rd_mux_sel_r_reg[2]_51 ),
        .S(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[5].mux_rd_fall0_r1[5]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 ),
        .O(\gen_mux_rd[5].mux_rd_fall0_r1[5]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[5].mux_rd_fall0_r1_reg[5]_i_1 
       (.I0(\gen_mux_rd[5].mux_rd_fall0_r1[5]_i_2_n_0 ),
        .I1(\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ),
        .O(\rd_mux_sel_r_reg[2]_12 ),
        .S(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[5].mux_rd_fall1_r1[5]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 ),
        .O(\gen_mux_rd[5].mux_rd_fall1_r1[5]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[5].mux_rd_fall1_r1_reg[5]_i_1 
       (.I0(\gen_mux_rd[5].mux_rd_fall1_r1[5]_i_2_n_0 ),
        .I1(\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ),
        .O(\rd_mux_sel_r_reg[2]_28 ),
        .S(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[5].mux_rd_fall2_r1[5]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 ),
        .O(\gen_mux_rd[5].mux_rd_fall2_r1[5]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[5].mux_rd_fall2_r1_reg[5]_i_1 
       (.I0(\gen_mux_rd[5].mux_rd_fall2_r1[5]_i_2_n_0 ),
        .I1(\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ),
        .O(\rd_mux_sel_r_reg[2]_44 ),
        .S(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[5].mux_rd_fall3_r1[5]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 ),
        .O(\gen_mux_rd[5].mux_rd_fall3_r1[5]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[5].mux_rd_fall3_r1_reg[5]_i_1 
       (.I0(\gen_mux_rd[5].mux_rd_fall3_r1[5]_i_2_n_0 ),
        .I1(\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ),
        .O(\rd_mux_sel_r_reg[2]_60 ),
        .S(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[5].mux_rd_rise0_r1[5]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_1 ),
        .O(\gen_mux_rd[5].mux_rd_rise0_r1[5]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[5].mux_rd_rise0_r1_reg[5]_i_1 
       (.I0(\gen_mux_rd[5].mux_rd_rise0_r1[5]_i_2_n_0 ),
        .I1(\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ),
        .O(\rd_mux_sel_r_reg[2]_4 ),
        .S(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[5].mux_rd_rise1_r1[5]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 ),
        .O(\gen_mux_rd[5].mux_rd_rise1_r1[5]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[5].mux_rd_rise1_r1_reg[5]_i_1 
       (.I0(\gen_mux_rd[5].mux_rd_rise1_r1[5]_i_2_n_0 ),
        .I1(\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ),
        .O(\rd_mux_sel_r_reg[2]_20 ),
        .S(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[5].mux_rd_rise2_r1[5]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 ),
        .O(\gen_mux_rd[5].mux_rd_rise2_r1[5]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[5].mux_rd_rise2_r1_reg[5]_i_1 
       (.I0(\gen_mux_rd[5].mux_rd_rise2_r1[5]_i_2_n_0 ),
        .I1(\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ),
        .O(\rd_mux_sel_r_reg[2]_36 ),
        .S(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[5].mux_rd_rise3_r1[5]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 ),
        .O(\gen_mux_rd[5].mux_rd_rise3_r1[5]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[5].mux_rd_rise3_r1_reg[5]_i_1 
       (.I0(\gen_mux_rd[5].mux_rd_rise3_r1[5]_i_2_n_0 ),
        .I1(\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ),
        .O(\rd_mux_sel_r_reg[2]_52 ),
        .S(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[6].mux_rd_fall0_r1[6]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_1 ),
        .O(\gen_mux_rd[6].mux_rd_fall0_r1[6]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[6].mux_rd_fall0_r1_reg[6]_i_1 
       (.I0(\gen_mux_rd[6].mux_rd_fall0_r1[6]_i_2_n_0 ),
        .I1(\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ),
        .O(\rd_mux_sel_r_reg[2]_13 ),
        .S(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[6].mux_rd_fall1_r1[6]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_1 ),
        .O(\gen_mux_rd[6].mux_rd_fall1_r1[6]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[6].mux_rd_fall1_r1_reg[6]_i_1 
       (.I0(\gen_mux_rd[6].mux_rd_fall1_r1[6]_i_2_n_0 ),
        .I1(\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ),
        .O(\rd_mux_sel_r_reg[2]_29 ),
        .S(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[6].mux_rd_fall2_r1[6]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_1 ),
        .O(\gen_mux_rd[6].mux_rd_fall2_r1[6]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[6].mux_rd_fall2_r1_reg[6]_i_1 
       (.I0(\gen_mux_rd[6].mux_rd_fall2_r1[6]_i_2_n_0 ),
        .I1(\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ),
        .O(\rd_mux_sel_r_reg[2]_45 ),
        .S(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[6].mux_rd_fall3_r1[6]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_1 ),
        .O(\gen_mux_rd[6].mux_rd_fall3_r1[6]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[6].mux_rd_fall3_r1_reg[6]_i_1 
       (.I0(\gen_mux_rd[6].mux_rd_fall3_r1[6]_i_2_n_0 ),
        .I1(\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ),
        .O(\rd_mux_sel_r_reg[2]_61 ),
        .S(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[6].mux_rd_rise0_r1[6]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_1 ),
        .O(\gen_mux_rd[6].mux_rd_rise0_r1[6]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[6].mux_rd_rise0_r1_reg[6]_i_1 
       (.I0(\gen_mux_rd[6].mux_rd_rise0_r1[6]_i_2_n_0 ),
        .I1(\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ),
        .O(\rd_mux_sel_r_reg[2]_5 ),
        .S(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[6].mux_rd_rise1_r1[6]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_1 ),
        .O(\gen_mux_rd[6].mux_rd_rise1_r1[6]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[6].mux_rd_rise1_r1_reg[6]_i_1 
       (.I0(\gen_mux_rd[6].mux_rd_rise1_r1[6]_i_2_n_0 ),
        .I1(\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ),
        .O(\rd_mux_sel_r_reg[2]_21 ),
        .S(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[6].mux_rd_rise2_r1[6]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_1 ),
        .O(\gen_mux_rd[6].mux_rd_rise2_r1[6]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[6].mux_rd_rise2_r1_reg[6]_i_1 
       (.I0(\gen_mux_rd[6].mux_rd_rise2_r1[6]_i_2_n_0 ),
        .I1(\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ),
        .O(\rd_mux_sel_r_reg[2]_37 ),
        .S(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[6].mux_rd_rise3_r1[6]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_1 ),
        .O(\gen_mux_rd[6].mux_rd_rise3_r1[6]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[6].mux_rd_rise3_r1_reg[6]_i_1 
       (.I0(\gen_mux_rd[6].mux_rd_rise3_r1[6]_i_2_n_0 ),
        .I1(\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ),
        .O(\rd_mux_sel_r_reg[2]_53 ),
        .S(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[7].mux_rd_fall0_r1[7]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 ),
        .O(\gen_mux_rd[7].mux_rd_fall0_r1[7]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[7].mux_rd_fall0_r1_reg[7]_i_1 
       (.I0(\gen_mux_rd[7].mux_rd_fall0_r1[7]_i_2_n_0 ),
        .I1(\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ),
        .O(\rd_mux_sel_r_reg[2]_14 ),
        .S(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[7].mux_rd_fall1_r1[7]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 ),
        .O(\gen_mux_rd[7].mux_rd_fall1_r1[7]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[7].mux_rd_fall1_r1_reg[7]_i_1 
       (.I0(\gen_mux_rd[7].mux_rd_fall1_r1[7]_i_2_n_0 ),
        .I1(\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ),
        .O(\rd_mux_sel_r_reg[2]_30 ),
        .S(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[7].mux_rd_fall2_r1[7]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 ),
        .O(\gen_mux_rd[7].mux_rd_fall2_r1[7]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[7].mux_rd_fall2_r1_reg[7]_i_1 
       (.I0(\gen_mux_rd[7].mux_rd_fall2_r1[7]_i_2_n_0 ),
        .I1(\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ),
        .O(\rd_mux_sel_r_reg[2]_46 ),
        .S(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[7].mux_rd_fall3_r1[7]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 ),
        .O(\gen_mux_rd[7].mux_rd_fall3_r1[7]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[7].mux_rd_fall3_r1_reg[7]_i_1 
       (.I0(\gen_mux_rd[7].mux_rd_fall3_r1[7]_i_2_n_0 ),
        .I1(\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ),
        .O(\rd_mux_sel_r_reg[2]_62 ),
        .S(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[7].mux_rd_rise0_r1[7]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_1 ),
        .O(\gen_mux_rd[7].mux_rd_rise0_r1[7]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[7].mux_rd_rise0_r1_reg[7]_i_1 
       (.I0(\gen_mux_rd[7].mux_rd_rise0_r1[7]_i_2_n_0 ),
        .I1(\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ),
        .O(\rd_mux_sel_r_reg[2]_6 ),
        .S(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[7].mux_rd_rise1_r1[7]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 ),
        .O(\gen_mux_rd[7].mux_rd_rise1_r1[7]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[7].mux_rd_rise1_r1_reg[7]_i_1 
       (.I0(\gen_mux_rd[7].mux_rd_rise1_r1[7]_i_2_n_0 ),
        .I1(\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ),
        .O(\rd_mux_sel_r_reg[2]_22 ),
        .S(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[7].mux_rd_rise2_r1[7]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 ),
        .O(\gen_mux_rd[7].mux_rd_rise2_r1[7]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[7].mux_rd_rise2_r1_reg[7]_i_1 
       (.I0(\gen_mux_rd[7].mux_rd_rise2_r1[7]_i_2_n_0 ),
        .I1(\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ),
        .O(\rd_mux_sel_r_reg[2]_38 ),
        .S(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[7].mux_rd_rise3_r1[7]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 ),
        .O(\gen_mux_rd[7].mux_rd_rise3_r1[7]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[7].mux_rd_rise3_r1_reg[7]_i_1 
       (.I0(\gen_mux_rd[7].mux_rd_rise3_r1[7]_i_2_n_0 ),
        .I1(\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ),
        .O(\rd_mux_sel_r_reg[2]_54 ),
        .S(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r[0]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r[0]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r[0]_i_2_n_0 ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_2 ),
        .O(\po_stg2_wrcal_cnt_reg[2]_14 ),
        .S(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r[0]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r[0]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r[0]_i_2_n_0 ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_2 ),
        .O(\po_stg2_wrcal_cnt_reg[2]_54 ),
        .S(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r[0]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r[0]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r[0]_i_2_n_0 ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_2 ),
        .O(\po_stg2_wrcal_cnt_reg[2]_30 ),
        .S(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r[0]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r[0]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r[0]_i_2_n_0 ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_2 ),
        .O(\po_stg2_wrcal_cnt_reg[2]_6 ),
        .S(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r[0]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r[0]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r[0]_i_2_n_0 ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_2 ),
        .O(\po_stg2_wrcal_cnt_reg[2]_46 ),
        .S(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r[0]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r[0]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r[0]_i_2_n_0 ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_3 ),
        .O(p_0_out),
        .S(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r[0]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r[0]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r[0]_i_2_n_0 ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_2 ),
        .O(\po_stg2_wrcal_cnt_reg[2]_22 ),
        .S(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r[0]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r[0]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r[0]_i_2_n_0 ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_2 ),
        .O(\po_stg2_wrcal_cnt_reg[2]_38 ),
        .S(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r[1]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r[1]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r[1]_i_2_n_0 ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_2 ),
        .O(\po_stg2_wrcal_cnt_reg[2]_15 ),
        .S(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r[1]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r[1]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r[1]_i_2_n_0 ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_2 ),
        .O(\po_stg2_wrcal_cnt_reg[2]_55 ),
        .S(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r[1]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r[1]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r[1]_i_2_n_0 ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_2 ),
        .O(\po_stg2_wrcal_cnt_reg[2]_31 ),
        .S(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r[1]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r[1]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r[1]_i_2_n_0 ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_2 ),
        .O(\po_stg2_wrcal_cnt_reg[2]_7 ),
        .S(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r[1]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r[1]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r[1]_i_2_n_0 ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ),
        .O(\po_stg2_wrcal_cnt_reg[2]_47 ),
        .S(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r[1]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r[1]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r[1]_i_2_n_0 ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_2 ),
        .O(\po_stg2_wrcal_cnt_reg[2] ),
        .S(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r[1]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r[1]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r[1]_i_2_n_0 ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_2 ),
        .O(\po_stg2_wrcal_cnt_reg[2]_23 ),
        .S(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r[1]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r[1]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r[1]_i_2_n_0 ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_2 ),
        .O(\po_stg2_wrcal_cnt_reg[2]_39 ),
        .S(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r[2]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r[2]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r[2]_i_2_n_0 ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_2 ),
        .O(\po_stg2_wrcal_cnt_reg[2]_16 ),
        .S(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r[2]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r[2]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r[2]_i_2_n_0 ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_2 ),
        .O(\po_stg2_wrcal_cnt_reg[2]_56 ),
        .S(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r[2]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r[2]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r[2]_i_2_n_0 ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_2 ),
        .O(\po_stg2_wrcal_cnt_reg[2]_32 ),
        .S(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r[2]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r[2]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r[2]_i_2_n_0 ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_2 ),
        .O(\po_stg2_wrcal_cnt_reg[2]_8 ),
        .S(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r[2]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r[2]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r[2]_i_2_n_0 ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_2 ),
        .O(\po_stg2_wrcal_cnt_reg[2]_48 ),
        .S(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r[2]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r[2]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r[2]_i_2_n_0 ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_2 ),
        .O(\po_stg2_wrcal_cnt_reg[2]_0 ),
        .S(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r[2]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r[2]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r[2]_i_2_n_0 ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_2 ),
        .O(\po_stg2_wrcal_cnt_reg[2]_24 ),
        .S(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r[2]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r[2]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r[2]_i_2_n_0 ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_2 ),
        .O(\po_stg2_wrcal_cnt_reg[2]_40 ),
        .S(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r[3]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r[3]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r[3]_i_2_n_0 ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_2 ),
        .O(\po_stg2_wrcal_cnt_reg[2]_17 ),
        .S(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r[3]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r[3]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r[3]_i_2_n_0 ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_2 ),
        .O(\po_stg2_wrcal_cnt_reg[2]_57 ),
        .S(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r[3]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r[3]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r[3]_i_2_n_0 ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_2 ),
        .O(\po_stg2_wrcal_cnt_reg[2]_33 ),
        .S(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r[3]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r[3]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r[3]_i_2_n_0 ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_2 ),
        .O(\po_stg2_wrcal_cnt_reg[2]_9 ),
        .S(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r[3]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r[3]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r[3]_i_2_n_0 ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_2 ),
        .O(\po_stg2_wrcal_cnt_reg[2]_49 ),
        .S(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r[3]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r[3]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r[3]_i_2_n_0 ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_2 ),
        .O(\po_stg2_wrcal_cnt_reg[2]_1 ),
        .S(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r[3]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r[3]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r[3]_i_2_n_0 ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_2 ),
        .O(\po_stg2_wrcal_cnt_reg[2]_25 ),
        .S(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r[3]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r[3]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r[3]_i_2_n_0 ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_2 ),
        .O(\po_stg2_wrcal_cnt_reg[2]_41 ),
        .S(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r[4]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r[4]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r[4]_i_2_n_0 ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_2 ),
        .O(\po_stg2_wrcal_cnt_reg[2]_18 ),
        .S(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r[4]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r[4]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r[4]_i_2_n_0 ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_2 ),
        .O(\po_stg2_wrcal_cnt_reg[2]_58 ),
        .S(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r[4]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r[4]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r[4]_i_2_n_0 ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_2 ),
        .O(\po_stg2_wrcal_cnt_reg[2]_34 ),
        .S(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r[4]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r[4]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r[4]_i_2_n_0 ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_2 ),
        .O(\po_stg2_wrcal_cnt_reg[2]_10 ),
        .S(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r[4]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r[4]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r[4]_i_2_n_0 ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_2 ),
        .O(\po_stg2_wrcal_cnt_reg[2]_50 ),
        .S(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r[4]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r[4]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r[4]_i_2_n_0 ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_2 ),
        .O(\po_stg2_wrcal_cnt_reg[2]_2 ),
        .S(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r[4]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r[4]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r[4]_i_2_n_0 ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_2 ),
        .O(\po_stg2_wrcal_cnt_reg[2]_26 ),
        .S(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r[4]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r[4]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r[4]_i_2_n_0 ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_2 ),
        .O(\po_stg2_wrcal_cnt_reg[2]_42 ),
        .S(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r[5]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r[5]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r[5]_i_2_n_0 ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_2 ),
        .O(\po_stg2_wrcal_cnt_reg[2]_19 ),
        .S(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r[5]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r[5]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r[5]_i_2_n_0 ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_2 ),
        .O(\po_stg2_wrcal_cnt_reg[2]_59 ),
        .S(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r[5]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r[5]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r[5]_i_2_n_0 ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_2 ),
        .O(\po_stg2_wrcal_cnt_reg[2]_35 ),
        .S(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r[5]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r[5]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r[5]_i_2_n_0 ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_2 ),
        .O(\po_stg2_wrcal_cnt_reg[2]_11 ),
        .S(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r[5]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r[5]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r[5]_i_2_n_0 ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_2 ),
        .O(\po_stg2_wrcal_cnt_reg[2]_51 ),
        .S(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r[5]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r[5]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r[5]_i_2_n_0 ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_2 ),
        .O(\po_stg2_wrcal_cnt_reg[2]_3 ),
        .S(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r[5]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r[5]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r[5]_i_2_n_0 ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_2 ),
        .O(\po_stg2_wrcal_cnt_reg[2]_27 ),
        .S(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r[5]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r[5]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r[5]_i_2_n_0 ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_2 ),
        .O(\po_stg2_wrcal_cnt_reg[2]_43 ),
        .S(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r[6]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r[6]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r[6]_i_2_n_0 ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_2 ),
        .O(\po_stg2_wrcal_cnt_reg[2]_20 ),
        .S(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r[6]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r[6]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r[6]_i_2_n_0 ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_2 ),
        .O(\po_stg2_wrcal_cnt_reg[2]_60 ),
        .S(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r[6]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r[6]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r[6]_i_2_n_0 ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_2 ),
        .O(\po_stg2_wrcal_cnt_reg[2]_36 ),
        .S(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r[6]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r[6]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r[6]_i_2_n_0 ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_2 ),
        .O(\po_stg2_wrcal_cnt_reg[2]_12 ),
        .S(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r[6]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r[6]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r[6]_i_2_n_0 ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_2 ),
        .O(\po_stg2_wrcal_cnt_reg[2]_52 ),
        .S(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r[6]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r[6]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r[6]_i_2_n_0 ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_2 ),
        .O(\po_stg2_wrcal_cnt_reg[2]_4 ),
        .S(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r[6]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r[6]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r[6]_i_2_n_0 ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_2 ),
        .O(\po_stg2_wrcal_cnt_reg[2]_28 ),
        .S(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r[6]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r[6]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r[6]_i_2_n_0 ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_2 ),
        .O(\po_stg2_wrcal_cnt_reg[2]_44 ),
        .S(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r[7]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r[7]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r[7]_i_2_n_0 ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_2 ),
        .O(\po_stg2_wrcal_cnt_reg[2]_21 ),
        .S(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r[7]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r[7]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r[7]_i_2_n_0 ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_2 ),
        .O(\po_stg2_wrcal_cnt_reg[2]_61 ),
        .S(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r[7]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r[7]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r[7]_i_2_n_0 ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_2 ),
        .O(\po_stg2_wrcal_cnt_reg[2]_37 ),
        .S(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r[7]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r[7]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r[7]_i_2_n_0 ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_2 ),
        .O(\po_stg2_wrcal_cnt_reg[2]_13 ),
        .S(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r[7]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r[7]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r[7]_i_2_n_0 ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_2 ),
        .O(\po_stg2_wrcal_cnt_reg[2]_53 ),
        .S(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r[7]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r[7]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r[7]_i_2_n_0 ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_2 ),
        .O(\po_stg2_wrcal_cnt_reg[2]_5 ),
        .S(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r[7]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r[7]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r[7]_i_2_n_0 ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_2 ),
        .O(\po_stg2_wrcal_cnt_reg[2]_29 ),
        .S(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r[7]_i_2 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 ),
        .O(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r[7]_i_2_n_0 ));
  MUXF7 \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_i_1 
       (.I0(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r[7]_i_2_n_0 ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_2 ),
        .O(\po_stg2_wrcal_cnt_reg[2]_45 ),
        .S(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [2]));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "12" *) 
  (* ram_slice_end = "17" *) 
  RAM32M mem_reg_0_3_12_17
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[1:0]),
        .DIB(Q[3:2]),
        .DIC(Q[5:4]),
        .DID({1'b0,1'b0}),
        .DOA({mem_reg_0_3_12_17_n_0,mem_reg_0_3_12_17_n_1}),
        .DOB({mem_reg_0_3_12_17_n_2,mem_reg_0_3_12_17_n_3}),
        .DOC(mem_out[17:16]),
        .DOD(NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_timing_reg[1]_0 ),
        .WE(wr_en));
  LUT4 #(
    .INIT(16'h0151)) 
    mem_reg_0_3_12_17_i_1__1
       (.I0(if_empty_r_0),
        .I1(my_full[0]),
        .I2(\my_full_reg[1]_0 ),
        .I3(my_empty[2]),
        .O(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "18" *) 
  (* ram_slice_end = "23" *) 
  RAM32M mem_reg_0_3_18_23
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[7:6]),
        .DIB(Q[9:8]),
        .DIC(Q[11:10]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[19:18]),
        .DOB(mem_out[21:20]),
        .DOC(mem_out[23:22]),
        .DOD(NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_timing_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "24" *) 
  (* ram_slice_end = "29" *) 
  RAM32M mem_reg_0_3_24_29
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[13:12]),
        .DIB(Q[15:14]),
        .DIC(Q[17:16]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[25:24]),
        .DOB(mem_out[27:26]),
        .DOC(mem_out[29:28]),
        .DOD(NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_timing_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "30" *) 
  (* ram_slice_end = "35" *) 
  RAM32M mem_reg_0_3_30_35
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[19:18]),
        .DIB(Q[21:20]),
        .DIC(Q[23:22]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[31:30]),
        .DOB(mem_out[33:32]),
        .DOC(mem_out[35:34]),
        .DOD(NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_timing_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "36" *) 
  (* ram_slice_end = "41" *) 
  RAM32M mem_reg_0_3_36_41
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[25:24]),
        .DIB(Q[27:26]),
        .DIC(Q[29:28]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[37:36]),
        .DOB(mem_out[39:38]),
        .DOC(mem_out[41:40]),
        .DOD(NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_timing_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "42" *) 
  (* ram_slice_end = "47" *) 
  RAM32M mem_reg_0_3_42_47
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[31:30]),
        .DIB(Q[33:32]),
        .DIC(Q[35:34]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[43:42]),
        .DOB(mem_out[45:44]),
        .DOC(mem_out[47:46]),
        .DOD(NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_timing_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "48" *) 
  (* ram_slice_end = "53" *) 
  RAM32M mem_reg_0_3_48_53
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[37:36]),
        .DIB(Q[39:38]),
        .DIC(Q[41:40]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[49:48]),
        .DOB(mem_out[51:50]),
        .DOC(mem_out[53:52]),
        .DOD(NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_timing_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "54" *) 
  (* ram_slice_end = "59" *) 
  RAM32M mem_reg_0_3_54_59
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[43:42]),
        .DIB(Q[45:44]),
        .DIC(Q[47:46]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[55:54]),
        .DOB(mem_out[57:56]),
        .DOC(mem_out[59:58]),
        .DOD(NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_timing_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "60" *) 
  (* ram_slice_end = "65" *) 
  RAM32M mem_reg_0_3_60_65
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[49:48]),
        .DIB(Q[51:50]),
        .DIC(Q[53:52]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[61:60]),
        .DOB(mem_out[63:62]),
        .DOC(mem_out[65:64]),
        .DOD(NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_timing_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "66" *) 
  (* ram_slice_end = "71" *) 
  RAM32M mem_reg_0_3_66_71
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[55:54]),
        .DIB(Q[57:56]),
        .DIC(Q[59:58]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[67:66]),
        .DOB(mem_out[69:68]),
        .DOC(mem_out[71:70]),
        .DOD(NLW_mem_reg_0_3_66_71_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_timing_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "72" *) 
  (* ram_slice_end = "77" *) 
  RAM32M mem_reg_0_3_72_77
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[61:60]),
        .DIB(Q[63:62]),
        .DIC(Q[65:64]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[73:72]),
        .DOB(mem_out[75:74]),
        .DOC(mem_out[77:76]),
        .DOD(NLW_mem_reg_0_3_72_77_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_timing_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "78" *) 
  (* ram_slice_end = "79" *) 
  RAM32M mem_reg_0_3_78_79
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[67:66]),
        .DIB({1'b0,1'b0}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[79:78]),
        .DOB(NLW_mem_reg_0_3_78_79_DOB_UNCONNECTED[1:0]),
        .DOC(NLW_mem_reg_0_3_78_79_DOC_UNCONNECTED[1:0]),
        .DOD(NLW_mem_reg_0_3_78_79_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_timing_reg[1]_0 ),
        .WE(wr_en));
  LUT4 #(
    .INIT(16'h0018)) 
    \my_empty[4]_i_1__2 
       (.I0(\my_full_reg[1]_0 ),
        .I1(if_empty_r_0),
        .I2(my_empty[1]),
        .I3(my_full[1]),
        .O(\my_empty[4]_i_1__2_n_0 ));
  LUT5 #(
    .INIT(32'h00411400)) 
    \my_empty[4]_i_2__6 
       (.I0(my_empty[1]),
        .I1(wr_ptr[1]),
        .I2(rd_ptr[1]),
        .I3(rd_ptr[0]),
        .I4(wr_ptr[0]),
        .O(\my_empty[4]_i_2__6_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    my_empty_inst__27
       (.I0(\my_empty_reg[4]_rep_n_0 ),
        .O(my_empty[4]));
  (* SOFT_HLUTNM = "soft_lutpair1090" *) 
  LUT1 #(
    .INIT(2'h2)) 
    my_empty_inst__28
       (.I0(my_empty[0]),
        .O(my_empty[3]));
  (* SOFT_HLUTNM = "soft_lutpair1124" *) 
  LUT1 #(
    .INIT(2'h2)) 
    my_empty_inst__29
       (.I0(my_empty[0]),
        .O(my_empty[2]));
  (* SOFT_HLUTNM = "soft_lutpair1124" *) 
  LUT1 #(
    .INIT(2'h2)) 
    my_empty_inst__30
       (.I0(my_empty[0]),
        .O(my_empty[1]));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  LUT1 #(
    .INIT(2'h2)) 
    my_empty_inst_rep__6
       (.I0(\my_empty_reg[4]_rep__0_n_0 ),
        .O(my_empty_inst_rep__6_n_0));
  (* ORIG_CELL_NAME = "my_empty_reg[4]" *) 
  FDSE \my_empty_reg[4] 
       (.C(\rd_ptr_timing_reg[1]_0 ),
        .CE(\my_empty[4]_i_1__2_n_0 ),
        .D(\my_empty[4]_i_2__6_n_0 ),
        .Q(my_empty[0]),
        .S(ififo_rst));
  (* ORIG_CELL_NAME = "my_empty_reg[4]" *) 
  FDSE \my_empty_reg[4]_rep 
       (.C(\rd_ptr_timing_reg[1]_0 ),
        .CE(\my_empty[4]_i_1__2_n_0 ),
        .D(\my_empty[4]_i_2__6_n_0 ),
        .Q(\my_empty_reg[4]_rep_n_0 ),
        .S(ififo_rst));
  (* ORIG_CELL_NAME = "my_empty_reg[4]" *) 
  FDSE \my_empty_reg[4]_rep__0 
       (.C(\rd_ptr_timing_reg[1]_0 ),
        .CE(\my_empty[4]_i_1__2_n_0 ),
        .D(\my_empty[4]_i_2__6_n_0 ),
        .Q(\my_empty_reg[4]_rep__0_n_0 ),
        .S(ififo_rst));
  LUT6 #(
    .INIT(64'hAAAAEAABAAAA2AA8)) 
    \my_full[0]_i_1__6 
       (.I0(my_full[0]),
        .I1(\my_full_reg[1]_0 ),
        .I2(if_empty_r_0),
        .I3(my_full[1]),
        .I4(my_empty[1]),
        .I5(\my_full[1]_i_2__6_n_0 ),
        .O(\my_full[0]_i_1__6_n_0 ));
  LUT5 #(
    .INIT(32'hF0F1F070)) 
    \my_full[1]_i_1__6 
       (.I0(\my_full_reg[1]_0 ),
        .I1(if_empty_r_0),
        .I2(my_full[1]),
        .I3(my_empty[1]),
        .I4(\my_full[1]_i_2__6_n_0 ),
        .O(\my_full[1]_i_1__6_n_0 ));
  LUT5 #(
    .INIT(32'h00411400)) 
    \my_full[1]_i_2__6 
       (.I0(my_full[1]),
        .I1(rd_ptr[1]),
        .I2(wr_ptr[1]),
        .I3(wr_ptr[0]),
        .I4(rd_ptr[0]),
        .O(\my_full[1]_i_2__6_n_0 ));
  FDRE \my_full_reg[0] 
       (.C(\rd_ptr_timing_reg[1]_0 ),
        .CE(1'b1),
        .D(\my_full[0]_i_1__6_n_0 ),
        .Q(my_full[0]),
        .R(ififo_rst));
  FDRE \my_full_reg[1] 
       (.C(\rd_ptr_timing_reg[1]_0 ),
        .CE(1'b1),
        .D(\my_full[1]_i_1__6_n_0 ),
        .Q(my_full[1]),
        .R(ififo_rst));
  (* SOFT_HLUTNM = "soft_lutpair1090" *) 
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    phy_if_empty_r_i_3
       (.I0(my_empty[0]),
        .I1(if_empty_r_0),
        .I2(phy_if_empty_r_reg),
        .I3(if_empty_r),
        .I4(phy_if_empty_r_reg_0),
        .O(if_empty_v));
  (* SOFT_HLUTNM = "soft_lutpair1091" *) 
  LUT3 #(
    .INIT(8'hD2)) 
    \rd_ptr[0]_i_1__6 
       (.I0(\my_full_reg[1]_0 ),
        .I1(my_empty[1]),
        .I2(rd_ptr[0]),
        .O(\rd_ptr[0]_i_1__6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1091" *) 
  LUT4 #(
    .INIT(16'hF708)) 
    \rd_ptr[1]_i_1__6 
       (.I0(rd_ptr[0]),
        .I1(\my_full_reg[1]_0 ),
        .I2(my_empty[1]),
        .I3(rd_ptr[1]),
        .O(\rd_ptr[1]_i_1__6_n_0 ));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[0] 
       (.C(\rd_ptr_timing_reg[1]_0 ),
        .CE(1'b1),
        .D(\rd_ptr[0]_i_1__6_n_0 ),
        .Q(rd_ptr[0]),
        .R(ififo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[1] 
       (.C(\rd_ptr_timing_reg[1]_0 ),
        .CE(1'b1),
        .D(\rd_ptr[1]_i_1__6_n_0 ),
        .Q(rd_ptr[1]),
        .R(ififo_rst));
  LUT4 #(
    .INIT(16'hF704)) 
    \rd_ptr_timing[0]_i_1__14 
       (.I0(rd_ptr[0]),
        .I1(\my_full_reg[1]_0 ),
        .I2(my_empty[1]),
        .I3(rd_ptr_timing[0]),
        .O(\rd_ptr_timing[0]_i_1__14_n_0 ));
  LUT5 #(
    .INIT(32'hFF6F0060)) 
    \rd_ptr_timing[1]_i_1__14 
       (.I0(rd_ptr[0]),
        .I1(rd_ptr[1]),
        .I2(\my_full_reg[1]_0 ),
        .I3(my_empty[1]),
        .I4(rd_ptr_timing[1]),
        .O(\rd_ptr_timing[1]_i_1__14_n_0 ));
  (* KEEP = "yes" *) 
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_timing_reg[0] 
       (.C(\rd_ptr_timing_reg[1]_0 ),
        .CE(1'b1),
        .D(\rd_ptr_timing[0]_i_1__14_n_0 ),
        .Q(rd_ptr_timing[0]),
        .R(ififo_rst));
  (* KEEP = "yes" *) 
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_timing_reg[1] 
       (.C(\rd_ptr_timing_reg[1]_0 ),
        .CE(1'b1),
        .D(\rd_ptr_timing[1]_i_1__14_n_0 ),
        .Q(rd_ptr_timing[1]),
        .R(ififo_rst));
  LUT5 #(
    .INIT(32'hFECE0131)) 
    \wr_ptr[0]_i_1__14 
       (.I0(my_full[1]),
        .I1(if_empty_r_0),
        .I2(\my_full_reg[1]_0 ),
        .I3(my_empty[1]),
        .I4(wr_ptr[0]),
        .O(\wr_ptr[0]_i_1__14_n_0 ));
  LUT6 #(
    .INIT(64'hFFFDF5FD00020A02)) 
    \wr_ptr[1]_i_1__14 
       (.I0(wr_ptr[0]),
        .I1(my_full[1]),
        .I2(if_empty_r_0),
        .I3(\my_full_reg[1]_0 ),
        .I4(my_empty[1]),
        .I5(wr_ptr[1]),
        .O(\wr_ptr[1]_i_1__14_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \wr_ptr[1]_i_2__3 
       (.I0(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),
        .I1(\my_full_reg[1]_1 ),
        .I2(\my_full_reg[1]_2 ),
        .I3(\my_full_reg[1]_3 ),
        .I4(\my_full_reg[1]_4 ),
        .I5(\my_full_reg[1]_5 ),
        .O(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \wr_ptr[1]_i_2__4 
       (.I0(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),
        .I1(\my_full_reg[1]_5 ),
        .I2(\my_full_reg[1]_2 ),
        .I3(\my_full_reg[1]_3 ),
        .I4(\my_full_reg[1]_4 ),
        .I5(\my_full_reg[1]_1 ),
        .O(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \wr_ptr[1]_i_2__5 
       (.I0(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),
        .I1(\my_full_reg[1]_5 ),
        .I2(\my_full_reg[1]_1 ),
        .I3(\my_full_reg[1]_3 ),
        .I4(\my_full_reg[1]_4 ),
        .I5(\my_full_reg[1]_2 ),
        .O(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ));
  LUT2 #(
    .INIT(4'h8)) 
    \wr_ptr[1]_i_6 
       (.I0(if_empty_r_0),
        .I1(my_empty[3]),
        .O(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[0] 
       (.C(\rd_ptr_timing_reg[1]_0 ),
        .CE(1'b1),
        .D(\wr_ptr[0]_i_1__14_n_0 ),
        .Q(wr_ptr[0]),
        .R(ififo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[1] 
       (.C(\rd_ptr_timing_reg[1]_0 ),
        .CE(1'b1),
        .D(\wr_ptr[1]_i_1__14_n_0 ),
        .Q(wr_ptr[1]),
        .R(ififo_rst));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_if_post_fifo" *) 
module mig_mig_7series_v4_2_ddr_if_post_fifo_15
   (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ,
    ififo_rst,
    \rd_ptr_reg[1]_0 ,
    if_empty_r_0,
    \my_full_reg[1]_0 ,
    \wr_ptr[1]_i_2__2 ,
    if_empty_r,
    Q,
    \my_full_reg[1]_1 ,
    \my_full_reg[1]_2 ,
    \my_full_reg[1]_3 ,
    \my_full_reg[1]_4 ,
    \my_full_reg[1]_5 );
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;
  input ififo_rst;
  input \rd_ptr_reg[1]_0 ;
  input [0:0]if_empty_r_0;
  input \my_full_reg[1]_0 ;
  input [1:0]\wr_ptr[1]_i_2__2 ;
  input [0:0]if_empty_r;
  input [67:0]Q;
  input \my_full_reg[1]_1 ;
  input \my_full_reg[1]_2 ;
  input \my_full_reg[1]_3 ;
  input \my_full_reg[1]_4 ;
  input \my_full_reg[1]_5 ;

  wire [67:0]Q;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ;
  wire [0:0]if_empty_r;
  wire [0:0]if_empty_r_0;
  wire ififo_rst;
  wire [79:16]mem_out;
  wire mem_reg_0_3_12_17_n_0;
  wire mem_reg_0_3_12_17_n_1;
  wire mem_reg_0_3_12_17_n_2;
  wire mem_reg_0_3_12_17_n_3;
  wire [4:0]my_empty;
  wire \my_empty[4]_i_1__1_n_0 ;
  wire \my_empty[4]_i_2__5_n_0 ;
  wire my_empty_inst_rep__5_n_0;
  wire \my_empty_reg[4]_rep__0_n_0 ;
  wire \my_empty_reg[4]_rep_n_0 ;
  wire [1:0]my_full;
  wire \my_full[0]_i_1__5_n_0 ;
  wire \my_full[1]_i_1__5_n_0 ;
  wire \my_full[1]_i_2__5_n_0 ;
  wire \my_full_reg[1]_0 ;
  wire \my_full_reg[1]_1 ;
  wire \my_full_reg[1]_2 ;
  wire \my_full_reg[1]_3 ;
  wire \my_full_reg[1]_4 ;
  wire \my_full_reg[1]_5 ;
  wire [1:0]rd_ptr;
  wire \rd_ptr[0]_i_1__5_n_0 ;
  wire \rd_ptr[1]_i_1__5_n_0 ;
  wire \rd_ptr_reg[1]_0 ;
  (* RTL_KEEP = "true" *) (* syn_maxfan = "10" *) wire [1:0]rd_ptr_timing;
  wire \rd_ptr_timing[0]_i_1__12_n_0 ;
  wire \rd_ptr_timing[1]_i_1__12_n_0 ;
  (* MAX_FANOUT = "40" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire wr_en;
  wire [1:0]wr_ptr;
  wire \wr_ptr[0]_i_1__12_n_0 ;
  wire \wr_ptr[1]_i_1__12_n_0 ;
  wire [1:0]\wr_ptr[1]_i_2__2 ;
  wire [1:0]NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_66_71_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_72_77_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_78_79_DOB_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_78_79_DOC_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_78_79_DOD_UNCONNECTED;

  (* SOFT_HLUTNM = "soft_lutpair1052" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[144]_INST_0 
       (.I0(Q[6]),
        .I1(my_empty_inst_rep__5_n_0),
        .I2(mem_out[18]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ));
  (* SOFT_HLUTNM = "soft_lutpair1047" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[145]_INST_0 
       (.I0(Q[14]),
        .I1(my_empty_inst_rep__5_n_0),
        .I2(mem_out[26]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ));
  (* SOFT_HLUTNM = "soft_lutpair1056" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[146]_INST_0 
       (.I0(Q[22]),
        .I1(my_empty_inst_rep__5_n_0),
        .I2(mem_out[34]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ));
  (* SOFT_HLUTNM = "soft_lutpair1050" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[147]_INST_0 
       (.I0(Q[30]),
        .I1(my_empty_inst_rep__5_n_0),
        .I2(mem_out[42]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ));
  (* SOFT_HLUTNM = "soft_lutpair1045" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[148]_INST_0 
       (.I0(Q[38]),
        .I1(my_empty[4]),
        .I2(mem_out[50]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ));
  (* SOFT_HLUTNM = "soft_lutpair1054" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[149]_INST_0 
       (.I0(Q[46]),
        .I1(my_empty[4]),
        .I2(mem_out[58]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ));
  (* SOFT_HLUTNM = "soft_lutpair1048" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[150]_INST_0 
       (.I0(Q[54]),
        .I1(my_empty[4]),
        .I2(mem_out[66]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ));
  (* SOFT_HLUTNM = "soft_lutpair1044" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[151]_INST_0 
       (.I0(Q[62]),
        .I1(my_empty[4]),
        .I2(mem_out[74]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] ));
  (* SOFT_HLUTNM = "soft_lutpair1058" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[16]_INST_0 
       (.I0(Q[4]),
        .I1(my_empty_inst_rep__5_n_0),
        .I2(mem_out[16]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ));
  (* SOFT_HLUTNM = "soft_lutpair1051" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[17]_INST_0 
       (.I0(Q[12]),
        .I1(my_empty_inst_rep__5_n_0),
        .I2(mem_out[24]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ));
  (* SOFT_HLUTNM = "soft_lutpair1046" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[18]_INST_0 
       (.I0(Q[20]),
        .I1(my_empty_inst_rep__5_n_0),
        .I2(mem_out[32]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ));
  (* SOFT_HLUTNM = "soft_lutpair1056" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[19]_INST_0 
       (.I0(Q[28]),
        .I1(my_empty_inst_rep__5_n_0),
        .I2(mem_out[40]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ));
  (* SOFT_HLUTNM = "soft_lutpair1071" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[208]_INST_0 
       (.I0(Q[7]),
        .I1(my_empty_inst_rep__5_n_0),
        .I2(mem_out[19]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ));
  (* SOFT_HLUTNM = "soft_lutpair1062" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[209]_INST_0 
       (.I0(Q[15]),
        .I1(my_empty_inst_rep__5_n_0),
        .I2(mem_out[27]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ));
  (* SOFT_HLUTNM = "soft_lutpair1043" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[20]_INST_0 
       (.I0(Q[36]),
        .I1(my_empty[4]),
        .I2(mem_out[48]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ));
  (* SOFT_HLUTNM = "soft_lutpair1067" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[210]_INST_0 
       (.I0(Q[23]),
        .I1(my_empty_inst_rep__5_n_0),
        .I2(mem_out[35]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ));
  (* SOFT_HLUTNM = "soft_lutpair1067" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[211]_INST_0 
       (.I0(Q[31]),
        .I1(my_empty_inst_rep__5_n_0),
        .I2(mem_out[43]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ));
  (* SOFT_HLUTNM = "soft_lutpair1060" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[212]_INST_0 
       (.I0(Q[39]),
        .I1(my_empty[4]),
        .I2(mem_out[51]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ));
  (* SOFT_HLUTNM = "soft_lutpair1066" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[213]_INST_0 
       (.I0(Q[47]),
        .I1(my_empty[4]),
        .I2(mem_out[59]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ));
  (* SOFT_HLUTNM = "soft_lutpair1065" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[214]_INST_0 
       (.I0(Q[55]),
        .I1(my_empty[4]),
        .I2(mem_out[67]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ));
  (* SOFT_HLUTNM = "soft_lutpair1055" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[215]_INST_0 
       (.I0(Q[63]),
        .I1(my_empty[4]),
        .I2(mem_out[75]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] ));
  (* SOFT_HLUTNM = "soft_lutpair1042" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[21]_INST_0 
       (.I0(Q[44]),
        .I1(my_empty[4]),
        .I2(mem_out[56]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ));
  (* SOFT_HLUTNM = "soft_lutpair1043" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[22]_INST_0 
       (.I0(Q[52]),
        .I1(my_empty[4]),
        .I2(mem_out[64]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ));
  (* SOFT_HLUTNM = "soft_lutpair1042" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[23]_INST_0 
       (.I0(Q[60]),
        .I1(my_empty[4]),
        .I2(mem_out[72]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ));
  (* SOFT_HLUTNM = "soft_lutpair1047" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[272]_INST_0 
       (.I0(Q[8]),
        .I1(my_empty_inst_rep__5_n_0),
        .I2(mem_out[20]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ));
  (* SOFT_HLUTNM = "soft_lutpair1041" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[273]_INST_0 
       (.I0(Q[16]),
        .I1(my_empty_inst_rep__5_n_0),
        .I2(mem_out[28]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ));
  (* SOFT_HLUTNM = "soft_lutpair1050" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[274]_INST_0 
       (.I0(Q[24]),
        .I1(my_empty_inst_rep__5_n_0),
        .I2(mem_out[36]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ));
  (* SOFT_HLUTNM = "soft_lutpair1041" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[275]_INST_0 
       (.I0(Q[32]),
        .I1(my_empty_inst_rep__5_n_0),
        .I2(mem_out[44]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ));
  (* SOFT_HLUTNM = "soft_lutpair1054" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[276]_INST_0 
       (.I0(Q[40]),
        .I1(my_empty[4]),
        .I2(mem_out[52]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ));
  (* SOFT_HLUTNM = "soft_lutpair1049" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[277]_INST_0 
       (.I0(Q[48]),
        .I1(my_empty[4]),
        .I2(mem_out[60]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ));
  (* SOFT_HLUTNM = "soft_lutpair1044" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[278]_INST_0 
       (.I0(Q[56]),
        .I1(my_empty[4]),
        .I2(mem_out[68]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ));
  (* SOFT_HLUTNM = "soft_lutpair1053" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[279]_INST_0 
       (.I0(Q[64]),
        .I1(my_empty[4]),
        .I2(mem_out[76]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] ));
  (* SOFT_HLUTNM = "soft_lutpair1063" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[336]_INST_0 
       (.I0(Q[9]),
        .I1(my_empty_inst_rep__5_n_0),
        .I2(mem_out[21]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ));
  (* SOFT_HLUTNM = "soft_lutpair1070" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[337]_INST_0 
       (.I0(Q[17]),
        .I1(my_empty_inst_rep__5_n_0),
        .I2(mem_out[29]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ));
  (* SOFT_HLUTNM = "soft_lutpair1070" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[338]_INST_0 
       (.I0(Q[25]),
        .I1(my_empty_inst_rep__5_n_0),
        .I2(mem_out[37]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ));
  (* SOFT_HLUTNM = "soft_lutpair1061" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[339]_INST_0 
       (.I0(Q[33]),
        .I1(my_empty_inst_rep__5_n_0),
        .I2(mem_out[45]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ));
  (* SOFT_HLUTNM = "soft_lutpair1069" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[340]_INST_0 
       (.I0(Q[41]),
        .I1(my_empty[4]),
        .I2(mem_out[53]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ));
  (* SOFT_HLUTNM = "soft_lutpair1059" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[341]_INST_0 
       (.I0(Q[49]),
        .I1(my_empty[4]),
        .I2(mem_out[61]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ));
  (* SOFT_HLUTNM = "soft_lutpair1055" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[342]_INST_0 
       (.I0(Q[57]),
        .I1(my_empty[4]),
        .I2(mem_out[69]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ));
  (* SOFT_HLUTNM = "soft_lutpair1064" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[343]_INST_0 
       (.I0(Q[65]),
        .I1(my_empty[4]),
        .I2(mem_out[77]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] ));
  (* SOFT_HLUTNM = "soft_lutpair1058" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[400]_INST_0 
       (.I0(Q[10]),
        .I1(my_empty_inst_rep__5_n_0),
        .I2(mem_out[22]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ));
  (* SOFT_HLUTNM = "soft_lutpair1051" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[401]_INST_0 
       (.I0(Q[18]),
        .I1(my_empty_inst_rep__5_n_0),
        .I2(mem_out[30]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ));
  (* SOFT_HLUTNM = "soft_lutpair1046" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[402]_INST_0 
       (.I0(Q[26]),
        .I1(my_empty_inst_rep__5_n_0),
        .I2(mem_out[38]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ));
  (* SOFT_HLUTNM = "soft_lutpair1052" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[403]_INST_0 
       (.I0(Q[34]),
        .I1(my_empty_inst_rep__5_n_0),
        .I2(mem_out[46]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ));
  (* SOFT_HLUTNM = "soft_lutpair1049" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[404]_INST_0 
       (.I0(Q[42]),
        .I1(my_empty[4]),
        .I2(mem_out[54]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ));
  (* SOFT_HLUTNM = "soft_lutpair1045" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[405]_INST_0 
       (.I0(Q[50]),
        .I1(my_empty[4]),
        .I2(mem_out[62]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ));
  (* SOFT_HLUTNM = "soft_lutpair1053" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[406]_INST_0 
       (.I0(Q[58]),
        .I1(my_empty[4]),
        .I2(mem_out[70]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ));
  (* SOFT_HLUTNM = "soft_lutpair1048" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[407]_INST_0 
       (.I0(Q[66]),
        .I1(my_empty[4]),
        .I2(mem_out[78]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] ));
  (* SOFT_HLUTNM = "soft_lutpair1072" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[464]_INST_0 
       (.I0(Q[11]),
        .I1(my_empty_inst_rep__5_n_0),
        .I2(mem_out[23]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ));
  (* SOFT_HLUTNM = "soft_lutpair1068" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[465]_INST_0 
       (.I0(Q[19]),
        .I1(my_empty_inst_rep__5_n_0),
        .I2(mem_out[31]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ));
  (* SOFT_HLUTNM = "soft_lutpair1061" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[466]_INST_0 
       (.I0(Q[27]),
        .I1(my_empty_inst_rep__5_n_0),
        .I2(mem_out[39]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ));
  (* SOFT_HLUTNM = "soft_lutpair1063" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[467]_INST_0 
       (.I0(Q[35]),
        .I1(my_empty_inst_rep__5_n_0),
        .I2(mem_out[47]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ));
  (* SOFT_HLUTNM = "soft_lutpair1066" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[468]_INST_0 
       (.I0(Q[43]),
        .I1(my_empty[4]),
        .I2(mem_out[55]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ));
  (* SOFT_HLUTNM = "soft_lutpair1057" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[469]_INST_0 
       (.I0(Q[51]),
        .I1(my_empty[4]),
        .I2(mem_out[63]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ));
  (* SOFT_HLUTNM = "soft_lutpair1065" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[470]_INST_0 
       (.I0(Q[59]),
        .I1(my_empty[4]),
        .I2(mem_out[71]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ));
  (* SOFT_HLUTNM = "soft_lutpair1060" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[471]_INST_0 
       (.I0(Q[67]),
        .I1(my_empty[4]),
        .I2(mem_out[79]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ));
  (* SOFT_HLUTNM = "soft_lutpair1072" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[80]_INST_0 
       (.I0(Q[5]),
        .I1(my_empty_inst_rep__5_n_0),
        .I2(mem_out[17]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ));
  (* SOFT_HLUTNM = "soft_lutpair1071" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[81]_INST_0 
       (.I0(Q[13]),
        .I1(my_empty_inst_rep__5_n_0),
        .I2(mem_out[25]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ));
  (* SOFT_HLUTNM = "soft_lutpair1062" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[82]_INST_0 
       (.I0(Q[21]),
        .I1(my_empty_inst_rep__5_n_0),
        .I2(mem_out[33]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ));
  (* SOFT_HLUTNM = "soft_lutpair1068" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[83]_INST_0 
       (.I0(Q[29]),
        .I1(my_empty_inst_rep__5_n_0),
        .I2(mem_out[41]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ));
  (* SOFT_HLUTNM = "soft_lutpair1069" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[84]_INST_0 
       (.I0(Q[37]),
        .I1(my_empty[4]),
        .I2(mem_out[49]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ));
  (* SOFT_HLUTNM = "soft_lutpair1059" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[85]_INST_0 
       (.I0(Q[45]),
        .I1(my_empty[4]),
        .I2(mem_out[57]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ));
  (* SOFT_HLUTNM = "soft_lutpair1057" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[86]_INST_0 
       (.I0(Q[53]),
        .I1(my_empty[4]),
        .I2(mem_out[65]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ));
  (* SOFT_HLUTNM = "soft_lutpair1064" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[87]_INST_0 
       (.I0(Q[61]),
        .I1(my_empty[4]),
        .I2(mem_out[73]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "12" *) 
  (* ram_slice_end = "17" *) 
  RAM32M mem_reg_0_3_12_17
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[1:0]),
        .DIB(Q[3:2]),
        .DIC(Q[5:4]),
        .DID({1'b0,1'b0}),
        .DOA({mem_reg_0_3_12_17_n_0,mem_reg_0_3_12_17_n_1}),
        .DOB({mem_reg_0_3_12_17_n_2,mem_reg_0_3_12_17_n_3}),
        .DOC(mem_out[17:16]),
        .DOD(NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_reg[1]_0 ),
        .WE(wr_en));
  LUT4 #(
    .INIT(16'h0151)) 
    mem_reg_0_3_12_17_i_1__0
       (.I0(if_empty_r_0),
        .I1(my_full[0]),
        .I2(\my_full_reg[1]_0 ),
        .I3(my_empty[2]),
        .O(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "18" *) 
  (* ram_slice_end = "23" *) 
  RAM32M mem_reg_0_3_18_23
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[7:6]),
        .DIB(Q[9:8]),
        .DIC(Q[11:10]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[19:18]),
        .DOB(mem_out[21:20]),
        .DOC(mem_out[23:22]),
        .DOD(NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "24" *) 
  (* ram_slice_end = "29" *) 
  RAM32M mem_reg_0_3_24_29
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[13:12]),
        .DIB(Q[15:14]),
        .DIC(Q[17:16]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[25:24]),
        .DOB(mem_out[27:26]),
        .DOC(mem_out[29:28]),
        .DOD(NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "30" *) 
  (* ram_slice_end = "35" *) 
  RAM32M mem_reg_0_3_30_35
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[19:18]),
        .DIB(Q[21:20]),
        .DIC(Q[23:22]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[31:30]),
        .DOB(mem_out[33:32]),
        .DOC(mem_out[35:34]),
        .DOD(NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "36" *) 
  (* ram_slice_end = "41" *) 
  RAM32M mem_reg_0_3_36_41
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[25:24]),
        .DIB(Q[27:26]),
        .DIC(Q[29:28]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[37:36]),
        .DOB(mem_out[39:38]),
        .DOC(mem_out[41:40]),
        .DOD(NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "42" *) 
  (* ram_slice_end = "47" *) 
  RAM32M mem_reg_0_3_42_47
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[31:30]),
        .DIB(Q[33:32]),
        .DIC(Q[35:34]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[43:42]),
        .DOB(mem_out[45:44]),
        .DOC(mem_out[47:46]),
        .DOD(NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "48" *) 
  (* ram_slice_end = "53" *) 
  RAM32M mem_reg_0_3_48_53
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[37:36]),
        .DIB(Q[39:38]),
        .DIC(Q[41:40]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[49:48]),
        .DOB(mem_out[51:50]),
        .DOC(mem_out[53:52]),
        .DOD(NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "54" *) 
  (* ram_slice_end = "59" *) 
  RAM32M mem_reg_0_3_54_59
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[43:42]),
        .DIB(Q[45:44]),
        .DIC(Q[47:46]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[55:54]),
        .DOB(mem_out[57:56]),
        .DOC(mem_out[59:58]),
        .DOD(NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "60" *) 
  (* ram_slice_end = "65" *) 
  RAM32M mem_reg_0_3_60_65
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[49:48]),
        .DIB(Q[51:50]),
        .DIC(Q[53:52]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[61:60]),
        .DOB(mem_out[63:62]),
        .DOC(mem_out[65:64]),
        .DOD(NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "66" *) 
  (* ram_slice_end = "71" *) 
  RAM32M mem_reg_0_3_66_71
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[55:54]),
        .DIB(Q[57:56]),
        .DIC(Q[59:58]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[67:66]),
        .DOB(mem_out[69:68]),
        .DOC(mem_out[71:70]),
        .DOD(NLW_mem_reg_0_3_66_71_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "72" *) 
  (* ram_slice_end = "77" *) 
  RAM32M mem_reg_0_3_72_77
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[61:60]),
        .DIB(Q[63:62]),
        .DIC(Q[65:64]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[73:72]),
        .DOB(mem_out[75:74]),
        .DOC(mem_out[77:76]),
        .DOD(NLW_mem_reg_0_3_72_77_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "78" *) 
  (* ram_slice_end = "79" *) 
  RAM32M mem_reg_0_3_78_79
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[67:66]),
        .DIB({1'b0,1'b0}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[79:78]),
        .DOB(NLW_mem_reg_0_3_78_79_DOB_UNCONNECTED[1:0]),
        .DOC(NLW_mem_reg_0_3_78_79_DOC_UNCONNECTED[1:0]),
        .DOD(NLW_mem_reg_0_3_78_79_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_reg[1]_0 ),
        .WE(wr_en));
  LUT4 #(
    .INIT(16'h0018)) 
    \my_empty[4]_i_1__1 
       (.I0(\my_full_reg[1]_0 ),
        .I1(if_empty_r_0),
        .I2(my_empty[1]),
        .I3(my_full[1]),
        .O(\my_empty[4]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'h00411400)) 
    \my_empty[4]_i_2__5 
       (.I0(my_empty[1]),
        .I1(wr_ptr[1]),
        .I2(rd_ptr[1]),
        .I3(rd_ptr[0]),
        .I4(wr_ptr[0]),
        .O(\my_empty[4]_i_2__5_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    my_empty_inst__23
       (.I0(\my_empty_reg[4]_rep_n_0 ),
        .O(my_empty[4]));
  (* SOFT_HLUTNM = "soft_lutpair1039" *) 
  LUT1 #(
    .INIT(2'h2)) 
    my_empty_inst__24
       (.I0(my_empty[0]),
        .O(my_empty[3]));
  (* SOFT_HLUTNM = "soft_lutpair1073" *) 
  LUT1 #(
    .INIT(2'h2)) 
    my_empty_inst__25
       (.I0(my_empty[0]),
        .O(my_empty[2]));
  (* SOFT_HLUTNM = "soft_lutpair1073" *) 
  LUT1 #(
    .INIT(2'h2)) 
    my_empty_inst__26
       (.I0(my_empty[0]),
        .O(my_empty[1]));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  LUT1 #(
    .INIT(2'h2)) 
    my_empty_inst_rep__5
       (.I0(\my_empty_reg[4]_rep__0_n_0 ),
        .O(my_empty_inst_rep__5_n_0));
  (* ORIG_CELL_NAME = "my_empty_reg[4]" *) 
  FDSE \my_empty_reg[4] 
       (.C(\rd_ptr_reg[1]_0 ),
        .CE(\my_empty[4]_i_1__1_n_0 ),
        .D(\my_empty[4]_i_2__5_n_0 ),
        .Q(my_empty[0]),
        .S(ififo_rst));
  (* ORIG_CELL_NAME = "my_empty_reg[4]" *) 
  FDSE \my_empty_reg[4]_rep 
       (.C(\rd_ptr_reg[1]_0 ),
        .CE(\my_empty[4]_i_1__1_n_0 ),
        .D(\my_empty[4]_i_2__5_n_0 ),
        .Q(\my_empty_reg[4]_rep_n_0 ),
        .S(ififo_rst));
  (* ORIG_CELL_NAME = "my_empty_reg[4]" *) 
  FDSE \my_empty_reg[4]_rep__0 
       (.C(\rd_ptr_reg[1]_0 ),
        .CE(\my_empty[4]_i_1__1_n_0 ),
        .D(\my_empty[4]_i_2__5_n_0 ),
        .Q(\my_empty_reg[4]_rep__0_n_0 ),
        .S(ififo_rst));
  LUT6 #(
    .INIT(64'hAAAAEAABAAAA2AA8)) 
    \my_full[0]_i_1__5 
       (.I0(my_full[0]),
        .I1(\my_full_reg[1]_0 ),
        .I2(if_empty_r_0),
        .I3(my_full[1]),
        .I4(my_empty[1]),
        .I5(\my_full[1]_i_2__5_n_0 ),
        .O(\my_full[0]_i_1__5_n_0 ));
  LUT5 #(
    .INIT(32'hF0F1F070)) 
    \my_full[1]_i_1__5 
       (.I0(\my_full_reg[1]_0 ),
        .I1(if_empty_r_0),
        .I2(my_full[1]),
        .I3(my_empty[1]),
        .I4(\my_full[1]_i_2__5_n_0 ),
        .O(\my_full[1]_i_1__5_n_0 ));
  LUT5 #(
    .INIT(32'h00411400)) 
    \my_full[1]_i_2__5 
       (.I0(my_full[1]),
        .I1(rd_ptr[1]),
        .I2(wr_ptr[1]),
        .I3(wr_ptr[0]),
        .I4(rd_ptr[0]),
        .O(\my_full[1]_i_2__5_n_0 ));
  FDRE \my_full_reg[0] 
       (.C(\rd_ptr_reg[1]_0 ),
        .CE(1'b1),
        .D(\my_full[0]_i_1__5_n_0 ),
        .Q(my_full[0]),
        .R(ififo_rst));
  FDRE \my_full_reg[1] 
       (.C(\rd_ptr_reg[1]_0 ),
        .CE(1'b1),
        .D(\my_full[1]_i_1__5_n_0 ),
        .Q(my_full[1]),
        .R(ififo_rst));
  (* SOFT_HLUTNM = "soft_lutpair1039" *) 
  LUT4 #(
    .INIT(16'hF888)) 
    phy_if_empty_r_i_4
       (.I0(if_empty_r_0),
        .I1(my_empty[0]),
        .I2(if_empty_r),
        .I3(\wr_ptr[1]_i_2__2 [0]),
        .O(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair1040" *) 
  LUT3 #(
    .INIT(8'hD2)) 
    \rd_ptr[0]_i_1__5 
       (.I0(\my_full_reg[1]_0 ),
        .I1(my_empty[1]),
        .I2(rd_ptr[0]),
        .O(\rd_ptr[0]_i_1__5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1040" *) 
  LUT4 #(
    .INIT(16'hF708)) 
    \rd_ptr[1]_i_1__5 
       (.I0(rd_ptr[0]),
        .I1(\my_full_reg[1]_0 ),
        .I2(my_empty[1]),
        .I3(rd_ptr[1]),
        .O(\rd_ptr[1]_i_1__5_n_0 ));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[0] 
       (.C(\rd_ptr_reg[1]_0 ),
        .CE(1'b1),
        .D(\rd_ptr[0]_i_1__5_n_0 ),
        .Q(rd_ptr[0]),
        .R(ififo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[1] 
       (.C(\rd_ptr_reg[1]_0 ),
        .CE(1'b1),
        .D(\rd_ptr[1]_i_1__5_n_0 ),
        .Q(rd_ptr[1]),
        .R(ififo_rst));
  LUT4 #(
    .INIT(16'hF704)) 
    \rd_ptr_timing[0]_i_1__12 
       (.I0(rd_ptr[0]),
        .I1(\my_full_reg[1]_0 ),
        .I2(my_empty[1]),
        .I3(rd_ptr_timing[0]),
        .O(\rd_ptr_timing[0]_i_1__12_n_0 ));
  LUT5 #(
    .INIT(32'hFF6F0060)) 
    \rd_ptr_timing[1]_i_1__12 
       (.I0(rd_ptr[0]),
        .I1(rd_ptr[1]),
        .I2(\my_full_reg[1]_0 ),
        .I3(my_empty[1]),
        .I4(rd_ptr_timing[1]),
        .O(\rd_ptr_timing[1]_i_1__12_n_0 ));
  (* KEEP = "yes" *) 
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_timing_reg[0] 
       (.C(\rd_ptr_reg[1]_0 ),
        .CE(1'b1),
        .D(\rd_ptr_timing[0]_i_1__12_n_0 ),
        .Q(rd_ptr_timing[0]),
        .R(ififo_rst));
  (* KEEP = "yes" *) 
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_timing_reg[1] 
       (.C(\rd_ptr_reg[1]_0 ),
        .CE(1'b1),
        .D(\rd_ptr_timing[1]_i_1__12_n_0 ),
        .Q(rd_ptr_timing[1]),
        .R(ififo_rst));
  LUT5 #(
    .INIT(32'hFECE0131)) 
    \wr_ptr[0]_i_1__12 
       (.I0(my_full[1]),
        .I1(if_empty_r_0),
        .I2(\my_full_reg[1]_0 ),
        .I3(my_empty[1]),
        .I4(wr_ptr[0]),
        .O(\wr_ptr[0]_i_1__12_n_0 ));
  LUT6 #(
    .INIT(64'hFFFDF5FD00020A02)) 
    \wr_ptr[1]_i_1__12 
       (.I0(wr_ptr[0]),
        .I1(my_full[1]),
        .I2(if_empty_r_0),
        .I3(\my_full_reg[1]_0 ),
        .I4(my_empty[1]),
        .I5(wr_ptr[1]),
        .O(\wr_ptr[1]_i_1__12_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \wr_ptr[1]_i_2__6 
       (.I0(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),
        .I1(\my_full_reg[1]_1 ),
        .I2(\my_full_reg[1]_2 ),
        .I3(\my_full_reg[1]_3 ),
        .I4(\my_full_reg[1]_4 ),
        .I5(\my_full_reg[1]_5 ),
        .O(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1038" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \wr_ptr[1]_i_4__0 
       (.I0(if_empty_r_0),
        .I1(my_empty[3]),
        .O(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1038" *) 
  LUT4 #(
    .INIT(16'hF888)) 
    \wr_ptr[1]_i_4__2 
       (.I0(my_empty[3]),
        .I1(if_empty_r_0),
        .I2(\wr_ptr[1]_i_2__2 [1]),
        .I3(if_empty_r),
        .O(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[0] 
       (.C(\rd_ptr_reg[1]_0 ),
        .CE(1'b1),
        .D(\wr_ptr[0]_i_1__12_n_0 ),
        .Q(wr_ptr[0]),
        .R(ififo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[1] 
       (.C(\rd_ptr_reg[1]_0 ),
        .CE(1'b1),
        .D(\wr_ptr[1]_i_1__12_n_0 ),
        .Q(wr_ptr[1]),
        .R(ififo_rst));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_if_post_fifo" *) 
module mig_mig_7series_v4_2_ddr_if_post_fifo_18
   (\my_empty_reg[4]_0 ,
    \my_empty_reg[4]_1 ,
    \rd_mux_sel_r_reg[0] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ,
    \rd_mux_sel_r_reg[0]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ,
    \rd_mux_sel_r_reg[0]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ,
    \rd_mux_sel_r_reg[0]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ,
    \rd_mux_sel_r_reg[0]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ,
    \rd_mux_sel_r_reg[0]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ,
    \rd_mux_sel_r_reg[0]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ,
    \rd_mux_sel_r_reg[0]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ,
    \rd_mux_sel_r_reg[0]_7 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ,
    \rd_mux_sel_r_reg[0]_8 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ,
    \rd_mux_sel_r_reg[0]_9 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ,
    \rd_mux_sel_r_reg[0]_10 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ,
    \rd_mux_sel_r_reg[0]_11 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ,
    \rd_mux_sel_r_reg[0]_12 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ,
    \rd_mux_sel_r_reg[0]_13 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ,
    \rd_mux_sel_r_reg[0]_14 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] ,
    \rd_mux_sel_r_reg[0]_15 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ,
    \rd_mux_sel_r_reg[0]_16 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ,
    \rd_mux_sel_r_reg[0]_17 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ,
    \rd_mux_sel_r_reg[0]_18 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ,
    \rd_mux_sel_r_reg[0]_19 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ,
    \rd_mux_sel_r_reg[0]_20 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ,
    \rd_mux_sel_r_reg[0]_21 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ,
    \rd_mux_sel_r_reg[0]_22 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] ,
    \rd_mux_sel_r_reg[0]_23 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ,
    \rd_mux_sel_r_reg[0]_24 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ,
    \rd_mux_sel_r_reg[0]_25 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ,
    \rd_mux_sel_r_reg[0]_26 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ,
    \rd_mux_sel_r_reg[0]_27 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ,
    \rd_mux_sel_r_reg[0]_28 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ,
    \rd_mux_sel_r_reg[0]_29 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ,
    \rd_mux_sel_r_reg[0]_30 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] ,
    \rd_mux_sel_r_reg[0]_31 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ,
    \rd_mux_sel_r_reg[0]_32 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ,
    \rd_mux_sel_r_reg[0]_33 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ,
    \rd_mux_sel_r_reg[0]_34 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ,
    \rd_mux_sel_r_reg[0]_35 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ,
    \rd_mux_sel_r_reg[0]_36 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ,
    \rd_mux_sel_r_reg[0]_37 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ,
    \rd_mux_sel_r_reg[0]_38 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] ,
    \rd_mux_sel_r_reg[0]_39 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ,
    \rd_mux_sel_r_reg[0]_40 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ,
    \rd_mux_sel_r_reg[0]_41 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ,
    \rd_mux_sel_r_reg[0]_42 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ,
    \rd_mux_sel_r_reg[0]_43 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ,
    \rd_mux_sel_r_reg[0]_44 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ,
    \rd_mux_sel_r_reg[0]_45 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ,
    \rd_mux_sel_r_reg[0]_46 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] ,
    \rd_mux_sel_r_reg[0]_47 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ,
    \rd_mux_sel_r_reg[0]_48 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ,
    \rd_mux_sel_r_reg[0]_49 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ,
    \rd_mux_sel_r_reg[0]_50 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ,
    \rd_mux_sel_r_reg[0]_51 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ,
    \rd_mux_sel_r_reg[0]_52 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ,
    \rd_mux_sel_r_reg[0]_53 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ,
    \rd_mux_sel_r_reg[0]_54 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] ,
    \rd_mux_sel_r_reg[0]_55 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ,
    \rd_mux_sel_r_reg[0]_56 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ,
    \rd_mux_sel_r_reg[0]_57 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ,
    \rd_mux_sel_r_reg[0]_58 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ,
    \rd_mux_sel_r_reg[0]_59 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ,
    \rd_mux_sel_r_reg[0]_60 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ,
    \rd_mux_sel_r_reg[0]_61 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ,
    \rd_mux_sel_r_reg[0]_62 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,
    ififo_rst,
    \rd_ptr_timing_reg[1]_0 ,
    \my_full_reg[1]_0 ,
    \my_full_reg[1]_1 ,
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0] ,
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ,
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1 ,
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_2 ,
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1 ,
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2] ,
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ,
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1 ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 ,
    \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ,
    \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0 ,
    \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_1 ,
    \gen_mux_rd[5].mux_rd_rise0_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_1 ,
    \gen_mux_rd[6].mux_rd_rise0_r_reg[6] ,
    \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0 ,
    \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_1 ,
    \gen_mux_rd[7].mux_rd_rise0_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_1 ,
    \gen_mux_rd[0].mux_rd_fall0_r_reg[0] ,
    \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0 ,
    \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_1 ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 ,
    \gen_mux_rd[2].mux_rd_fall0_r_reg[2] ,
    \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0 ,
    \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_1 ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 ,
    \gen_mux_rd[4].mux_rd_fall0_r_reg[4] ,
    \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0 ,
    \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_1 ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 ,
    \gen_mux_rd[6].mux_rd_fall0_r_reg[6] ,
    \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0 ,
    \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_1 ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 ,
    \gen_mux_rd[0].mux_rd_rise1_r_reg[0] ,
    \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0 ,
    \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_1 ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 ,
    \gen_mux_rd[2].mux_rd_rise1_r_reg[2] ,
    \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0 ,
    \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_1 ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 ,
    \gen_mux_rd[4].mux_rd_rise1_r_reg[4] ,
    \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0 ,
    \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_1 ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 ,
    \gen_mux_rd[6].mux_rd_rise1_r_reg[6] ,
    \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0 ,
    \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_1 ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 ,
    \gen_mux_rd[0].mux_rd_fall1_r_reg[0] ,
    \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0 ,
    \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_1 ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 ,
    \gen_mux_rd[2].mux_rd_fall1_r_reg[2] ,
    \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0 ,
    \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_1 ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 ,
    \gen_mux_rd[4].mux_rd_fall1_r_reg[4] ,
    \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0 ,
    \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_1 ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 ,
    \gen_mux_rd[6].mux_rd_fall1_r_reg[6] ,
    \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0 ,
    \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_1 ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 ,
    \gen_mux_rd[0].mux_rd_rise2_r_reg[0] ,
    \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0 ,
    \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_1 ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 ,
    \gen_mux_rd[2].mux_rd_rise2_r_reg[2] ,
    \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0 ,
    \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_1 ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 ,
    \gen_mux_rd[4].mux_rd_rise2_r_reg[4] ,
    \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0 ,
    \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_1 ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 ,
    \gen_mux_rd[6].mux_rd_rise2_r_reg[6] ,
    \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0 ,
    \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_1 ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 ,
    \gen_mux_rd[0].mux_rd_fall2_r_reg[0] ,
    \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0 ,
    \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_1 ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 ,
    \gen_mux_rd[2].mux_rd_fall2_r_reg[2] ,
    \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0 ,
    \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_1 ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 ,
    \gen_mux_rd[4].mux_rd_fall2_r_reg[4] ,
    \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0 ,
    \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_1 ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 ,
    \gen_mux_rd[6].mux_rd_fall2_r_reg[6] ,
    \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0 ,
    \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_1 ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 ,
    \gen_mux_rd[0].mux_rd_rise3_r_reg[0] ,
    \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0 ,
    \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_1 ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 ,
    \gen_mux_rd[2].mux_rd_rise3_r_reg[2] ,
    \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0 ,
    \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_1 ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 ,
    \gen_mux_rd[4].mux_rd_rise3_r_reg[4] ,
    \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0 ,
    \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_1 ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 ,
    \gen_mux_rd[6].mux_rd_rise3_r_reg[6] ,
    \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0 ,
    \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_1 ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 ,
    \gen_mux_rd[0].mux_rd_fall3_r_reg[0] ,
    \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0 ,
    \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_1 ,
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1 ,
    \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ,
    \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 ,
    \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_1 ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 ,
    \gen_mux_rd[4].mux_rd_fall3_r_reg[4] ,
    \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0 ,
    \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_1 ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 ,
    \gen_mux_rd[6].mux_rd_fall3_r_reg[6] ,
    \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0 ,
    \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_1 ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 ,
    Q);
  output \my_empty_reg[4]_0 ;
  output [0:0]\my_empty_reg[4]_1 ;
  output \rd_mux_sel_r_reg[0] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ;
  output \rd_mux_sel_r_reg[0]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ;
  output \rd_mux_sel_r_reg[0]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ;
  output \rd_mux_sel_r_reg[0]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ;
  output \rd_mux_sel_r_reg[0]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ;
  output \rd_mux_sel_r_reg[0]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ;
  output \rd_mux_sel_r_reg[0]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ;
  output \rd_mux_sel_r_reg[0]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ;
  output \rd_mux_sel_r_reg[0]_7 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ;
  output \rd_mux_sel_r_reg[0]_8 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ;
  output \rd_mux_sel_r_reg[0]_9 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ;
  output \rd_mux_sel_r_reg[0]_10 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ;
  output \rd_mux_sel_r_reg[0]_11 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ;
  output \rd_mux_sel_r_reg[0]_12 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ;
  output \rd_mux_sel_r_reg[0]_13 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ;
  output \rd_mux_sel_r_reg[0]_14 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] ;
  output \rd_mux_sel_r_reg[0]_15 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ;
  output \rd_mux_sel_r_reg[0]_16 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ;
  output \rd_mux_sel_r_reg[0]_17 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ;
  output \rd_mux_sel_r_reg[0]_18 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ;
  output \rd_mux_sel_r_reg[0]_19 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ;
  output \rd_mux_sel_r_reg[0]_20 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ;
  output \rd_mux_sel_r_reg[0]_21 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ;
  output \rd_mux_sel_r_reg[0]_22 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] ;
  output \rd_mux_sel_r_reg[0]_23 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ;
  output \rd_mux_sel_r_reg[0]_24 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ;
  output \rd_mux_sel_r_reg[0]_25 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ;
  output \rd_mux_sel_r_reg[0]_26 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ;
  output \rd_mux_sel_r_reg[0]_27 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ;
  output \rd_mux_sel_r_reg[0]_28 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ;
  output \rd_mux_sel_r_reg[0]_29 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ;
  output \rd_mux_sel_r_reg[0]_30 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] ;
  output \rd_mux_sel_r_reg[0]_31 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ;
  output \rd_mux_sel_r_reg[0]_32 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ;
  output \rd_mux_sel_r_reg[0]_33 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ;
  output \rd_mux_sel_r_reg[0]_34 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ;
  output \rd_mux_sel_r_reg[0]_35 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ;
  output \rd_mux_sel_r_reg[0]_36 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ;
  output \rd_mux_sel_r_reg[0]_37 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ;
  output \rd_mux_sel_r_reg[0]_38 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] ;
  output \rd_mux_sel_r_reg[0]_39 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ;
  output \rd_mux_sel_r_reg[0]_40 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ;
  output \rd_mux_sel_r_reg[0]_41 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ;
  output \rd_mux_sel_r_reg[0]_42 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ;
  output \rd_mux_sel_r_reg[0]_43 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ;
  output \rd_mux_sel_r_reg[0]_44 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ;
  output \rd_mux_sel_r_reg[0]_45 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ;
  output \rd_mux_sel_r_reg[0]_46 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] ;
  output \rd_mux_sel_r_reg[0]_47 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ;
  output \rd_mux_sel_r_reg[0]_48 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ;
  output \rd_mux_sel_r_reg[0]_49 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ;
  output \rd_mux_sel_r_reg[0]_50 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ;
  output \rd_mux_sel_r_reg[0]_51 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ;
  output \rd_mux_sel_r_reg[0]_52 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ;
  output \rd_mux_sel_r_reg[0]_53 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ;
  output \rd_mux_sel_r_reg[0]_54 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] ;
  output \rd_mux_sel_r_reg[0]_55 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ;
  output \rd_mux_sel_r_reg[0]_56 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ;
  output \rd_mux_sel_r_reg[0]_57 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ;
  output \rd_mux_sel_r_reg[0]_58 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ;
  output \rd_mux_sel_r_reg[0]_59 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ;
  output \rd_mux_sel_r_reg[0]_60 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ;
  output \rd_mux_sel_r_reg[0]_61 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ;
  output \rd_mux_sel_r_reg[0]_62 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  input ififo_rst;
  input \rd_ptr_timing_reg[1]_0 ;
  input \my_full_reg[1]_0 ;
  input \my_full_reg[1]_1 ;
  input [1:0]\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;
  input \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ;
  input \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1 ;
  input \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_2 ;
  input \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;
  input \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ;
  input \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1 ;
  input \gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;
  input \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ;
  input \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1 ;
  input \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  input \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ;
  input \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 ;
  input \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;
  input \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0 ;
  input \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_1 ;
  input \gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;
  input \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0 ;
  input \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_1 ;
  input \gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;
  input \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0 ;
  input \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_1 ;
  input \gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;
  input \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0 ;
  input \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_1 ;
  input \gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;
  input \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0 ;
  input \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_1 ;
  input \gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  input \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ;
  input \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 ;
  input \gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;
  input \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0 ;
  input \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_1 ;
  input \gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  input \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ;
  input \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 ;
  input \gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;
  input \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0 ;
  input \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_1 ;
  input \gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  input \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ;
  input \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 ;
  input \gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;
  input \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0 ;
  input \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_1 ;
  input \gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  input \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ;
  input \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 ;
  input \gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;
  input \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0 ;
  input \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_1 ;
  input \gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  input \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ;
  input \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 ;
  input \gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;
  input \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0 ;
  input \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_1 ;
  input \gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  input \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ;
  input \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 ;
  input \gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;
  input \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0 ;
  input \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_1 ;
  input \gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  input \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ;
  input \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 ;
  input \gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;
  input \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0 ;
  input \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_1 ;
  input \gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  input \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ;
  input \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 ;
  input \gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;
  input \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0 ;
  input \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_1 ;
  input \gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  input \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ;
  input \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 ;
  input \gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;
  input \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0 ;
  input \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_1 ;
  input \gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  input \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ;
  input \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 ;
  input \gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;
  input \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0 ;
  input \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_1 ;
  input \gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  input \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ;
  input \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 ;
  input \gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;
  input \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0 ;
  input \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_1 ;
  input \gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  input \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ;
  input \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 ;
  input \gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;
  input \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0 ;
  input \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_1 ;
  input \gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  input \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ;
  input \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 ;
  input \gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;
  input \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0 ;
  input \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_1 ;
  input \gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  input \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ;
  input \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 ;
  input \gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;
  input \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0 ;
  input \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_1 ;
  input \gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  input \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ;
  input \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 ;
  input \gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;
  input \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0 ;
  input \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_1 ;
  input \gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  input \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ;
  input \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 ;
  input \gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;
  input \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0 ;
  input \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_1 ;
  input \gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  input \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ;
  input \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 ;
  input \gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;
  input \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0 ;
  input \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_1 ;
  input \gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  input \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ;
  input \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 ;
  input \gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;
  input \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0 ;
  input \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_1 ;
  input \gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  input \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ;
  input \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 ;
  input \gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;
  input \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0 ;
  input \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_1 ;
  input \gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  input \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ;
  input \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 ;
  input \gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;
  input \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0 ;
  input \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_1 ;
  input \gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  input \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ;
  input \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 ;
  input \gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;
  input \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0 ;
  input \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_1 ;
  input \gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  input \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ;
  input \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 ;
  input \gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;
  input \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0 ;
  input \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_1 ;
  input \gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  input \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ;
  input \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 ;
  input \gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;
  input \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0 ;
  input \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_1 ;
  input \gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  input \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ;
  input \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 ;
  input \gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;
  input \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0 ;
  input \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_1 ;
  input \gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  input \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ;
  input \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1 ;
  input \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  input \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 ;
  input \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_1 ;
  input \gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  input \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ;
  input \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 ;
  input \gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;
  input \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0 ;
  input \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_1 ;
  input \gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  input \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ;
  input \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 ;
  input \gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;
  input \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0 ;
  input \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_1 ;
  input \gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  input \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ;
  input \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 ;
  input [67:0]Q;

  wire [67:0]Q;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ;
  wire \gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0 ;
  wire \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_1 ;
  wire \gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0 ;
  wire \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_1 ;
  wire \gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0 ;
  wire \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_1 ;
  wire \gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0 ;
  wire \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_1 ;
  wire [1:0]\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ;
  wire \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1 ;
  wire \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_2 ;
  wire \gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0 ;
  wire \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_1 ;
  wire \gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0 ;
  wire \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_1 ;
  wire \gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0 ;
  wire \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_1 ;
  wire \gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 ;
  wire \gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 ;
  wire \gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 ;
  wire \gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1 ;
  wire \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1 ;
  wire \gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 ;
  wire \gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 ;
  wire \gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 ;
  wire \gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0 ;
  wire \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_1 ;
  wire \gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0 ;
  wire \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_1 ;
  wire \gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0 ;
  wire \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_1 ;
  wire \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 ;
  wire \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_1 ;
  wire \gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ;
  wire \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1 ;
  wire \gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0 ;
  wire \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_1 ;
  wire \gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0 ;
  wire \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_1 ;
  wire \gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0 ;
  wire \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_1 ;
  wire \gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 ;
  wire \gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 ;
  wire \gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 ;
  wire \gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 ;
  wire \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 ;
  wire \gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 ;
  wire \gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 ;
  wire \gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 ;
  wire \gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0 ;
  wire \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_1 ;
  wire \gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0 ;
  wire \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_1 ;
  wire \gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0 ;
  wire \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_1 ;
  wire \gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0 ;
  wire \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_1 ;
  wire \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0 ;
  wire \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_1 ;
  wire \gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0 ;
  wire \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_1 ;
  wire \gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0 ;
  wire \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_1 ;
  wire \gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0 ;
  wire \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_1 ;
  wire \gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 ;
  wire \gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 ;
  wire \gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 ;
  wire \gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 ;
  wire \gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_1 ;
  wire \gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 ;
  wire \gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 ;
  wire \gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 ;
  wire \gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0 ;
  wire \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_1 ;
  wire \gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0 ;
  wire \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_1 ;
  wire \gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0 ;
  wire \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_1 ;
  wire \gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0 ;
  wire \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_1 ;
  wire \gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0 ;
  wire \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_1 ;
  wire \gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0 ;
  wire \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_1 ;
  wire \gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0 ;
  wire \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_1 ;
  wire \gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0 ;
  wire \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_1 ;
  wire \gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 ;
  wire \gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 ;
  wire \gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 ;
  wire \gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 ;
  wire \gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_1 ;
  wire \gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 ;
  wire \gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 ;
  wire \gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 ;
  wire ififo_rst;
  wire [79:16]mem_out;
  wire mem_reg_0_3_12_17_n_0;
  wire mem_reg_0_3_12_17_n_1;
  wire mem_reg_0_3_12_17_n_2;
  wire mem_reg_0_3_12_17_n_3;
  wire [4:1]my_empty;
  wire \my_empty[4]_i_1__0_n_0 ;
  wire \my_empty[4]_i_2__4_n_0 ;
  wire my_empty_inst_rep__4_n_0;
  wire \my_empty_reg[4]_0 ;
  wire [0:0]\my_empty_reg[4]_1 ;
  wire \my_empty_reg[4]_rep__0_n_0 ;
  wire \my_empty_reg[4]_rep_n_0 ;
  wire [1:0]my_full;
  wire \my_full[0]_i_1__4_n_0 ;
  wire \my_full[1]_i_1__4_n_0 ;
  wire \my_full[1]_i_2__4_n_0 ;
  wire \my_full_reg[1]_0 ;
  wire \my_full_reg[1]_1 ;
  wire \rd_mux_sel_r_reg[0] ;
  wire \rd_mux_sel_r_reg[0]_0 ;
  wire \rd_mux_sel_r_reg[0]_1 ;
  wire \rd_mux_sel_r_reg[0]_10 ;
  wire \rd_mux_sel_r_reg[0]_11 ;
  wire \rd_mux_sel_r_reg[0]_12 ;
  wire \rd_mux_sel_r_reg[0]_13 ;
  wire \rd_mux_sel_r_reg[0]_14 ;
  wire \rd_mux_sel_r_reg[0]_15 ;
  wire \rd_mux_sel_r_reg[0]_16 ;
  wire \rd_mux_sel_r_reg[0]_17 ;
  wire \rd_mux_sel_r_reg[0]_18 ;
  wire \rd_mux_sel_r_reg[0]_19 ;
  wire \rd_mux_sel_r_reg[0]_2 ;
  wire \rd_mux_sel_r_reg[0]_20 ;
  wire \rd_mux_sel_r_reg[0]_21 ;
  wire \rd_mux_sel_r_reg[0]_22 ;
  wire \rd_mux_sel_r_reg[0]_23 ;
  wire \rd_mux_sel_r_reg[0]_24 ;
  wire \rd_mux_sel_r_reg[0]_25 ;
  wire \rd_mux_sel_r_reg[0]_26 ;
  wire \rd_mux_sel_r_reg[0]_27 ;
  wire \rd_mux_sel_r_reg[0]_28 ;
  wire \rd_mux_sel_r_reg[0]_29 ;
  wire \rd_mux_sel_r_reg[0]_3 ;
  wire \rd_mux_sel_r_reg[0]_30 ;
  wire \rd_mux_sel_r_reg[0]_31 ;
  wire \rd_mux_sel_r_reg[0]_32 ;
  wire \rd_mux_sel_r_reg[0]_33 ;
  wire \rd_mux_sel_r_reg[0]_34 ;
  wire \rd_mux_sel_r_reg[0]_35 ;
  wire \rd_mux_sel_r_reg[0]_36 ;
  wire \rd_mux_sel_r_reg[0]_37 ;
  wire \rd_mux_sel_r_reg[0]_38 ;
  wire \rd_mux_sel_r_reg[0]_39 ;
  wire \rd_mux_sel_r_reg[0]_4 ;
  wire \rd_mux_sel_r_reg[0]_40 ;
  wire \rd_mux_sel_r_reg[0]_41 ;
  wire \rd_mux_sel_r_reg[0]_42 ;
  wire \rd_mux_sel_r_reg[0]_43 ;
  wire \rd_mux_sel_r_reg[0]_44 ;
  wire \rd_mux_sel_r_reg[0]_45 ;
  wire \rd_mux_sel_r_reg[0]_46 ;
  wire \rd_mux_sel_r_reg[0]_47 ;
  wire \rd_mux_sel_r_reg[0]_48 ;
  wire \rd_mux_sel_r_reg[0]_49 ;
  wire \rd_mux_sel_r_reg[0]_5 ;
  wire \rd_mux_sel_r_reg[0]_50 ;
  wire \rd_mux_sel_r_reg[0]_51 ;
  wire \rd_mux_sel_r_reg[0]_52 ;
  wire \rd_mux_sel_r_reg[0]_53 ;
  wire \rd_mux_sel_r_reg[0]_54 ;
  wire \rd_mux_sel_r_reg[0]_55 ;
  wire \rd_mux_sel_r_reg[0]_56 ;
  wire \rd_mux_sel_r_reg[0]_57 ;
  wire \rd_mux_sel_r_reg[0]_58 ;
  wire \rd_mux_sel_r_reg[0]_59 ;
  wire \rd_mux_sel_r_reg[0]_6 ;
  wire \rd_mux_sel_r_reg[0]_60 ;
  wire \rd_mux_sel_r_reg[0]_61 ;
  wire \rd_mux_sel_r_reg[0]_62 ;
  wire \rd_mux_sel_r_reg[0]_7 ;
  wire \rd_mux_sel_r_reg[0]_8 ;
  wire \rd_mux_sel_r_reg[0]_9 ;
  wire [1:0]rd_ptr;
  wire \rd_ptr[0]_i_1__4_n_0 ;
  wire \rd_ptr[1]_i_1__4_n_0 ;
  (* RTL_KEEP = "true" *) (* syn_maxfan = "10" *) wire [1:0]rd_ptr_timing;
  wire \rd_ptr_timing[0]_i_1__10_n_0 ;
  wire \rd_ptr_timing[1]_i_1__10_n_0 ;
  wire \rd_ptr_timing_reg[1]_0 ;
  (* MAX_FANOUT = "40" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire wr_en;
  wire [1:0]wr_ptr;
  wire \wr_ptr[0]_i_1__10_n_0 ;
  wire \wr_ptr[1]_i_1__10_n_0 ;
  wire [1:0]NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_66_71_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_72_77_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_78_79_DOB_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_78_79_DOC_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_78_79_DOD_UNCONNECTED;

  (* SOFT_HLUTNM = "soft_lutpair994" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[10]_INST_0 
       (.I0(Q[20]),
        .I1(my_empty_inst_rep__4_n_0),
        .I2(mem_out[32]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ));
  (* SOFT_HLUTNM = "soft_lutpair1003" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[11]_INST_0 
       (.I0(Q[28]),
        .I1(my_empty_inst_rep__4_n_0),
        .I2(mem_out[40]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ));
  (* SOFT_HLUTNM = "soft_lutpair991" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[12]_INST_0 
       (.I0(Q[36]),
        .I1(my_empty[4]),
        .I2(mem_out[48]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ));
  (* SOFT_HLUTNM = "soft_lutpair1000" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[136]_INST_0 
       (.I0(Q[6]),
        .I1(my_empty_inst_rep__4_n_0),
        .I2(mem_out[18]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ));
  (* SOFT_HLUTNM = "soft_lutpair995" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[137]_INST_0 
       (.I0(Q[14]),
        .I1(my_empty_inst_rep__4_n_0),
        .I2(mem_out[26]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ));
  (* SOFT_HLUTNM = "soft_lutpair1003" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[138]_INST_0 
       (.I0(Q[22]),
        .I1(my_empty_inst_rep__4_n_0),
        .I2(mem_out[34]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ));
  (* SOFT_HLUTNM = "soft_lutpair998" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[139]_INST_0 
       (.I0(Q[30]),
        .I1(my_empty_inst_rep__4_n_0),
        .I2(mem_out[42]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ));
  (* SOFT_HLUTNM = "soft_lutpair990" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[13]_INST_0 
       (.I0(Q[44]),
        .I1(my_empty[4]),
        .I2(mem_out[56]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ));
  (* SOFT_HLUTNM = "soft_lutpair993" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[140]_INST_0 
       (.I0(Q[38]),
        .I1(my_empty[4]),
        .I2(mem_out[50]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ));
  (* SOFT_HLUTNM = "soft_lutpair1002" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[141]_INST_0 
       (.I0(Q[46]),
        .I1(my_empty[4]),
        .I2(mem_out[58]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ));
  (* SOFT_HLUTNM = "soft_lutpair996" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[142]_INST_0 
       (.I0(Q[54]),
        .I1(my_empty[4]),
        .I2(mem_out[66]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ));
  (* SOFT_HLUTNM = "soft_lutpair992" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[143]_INST_0 
       (.I0(Q[62]),
        .I1(my_empty[4]),
        .I2(mem_out[74]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] ));
  (* SOFT_HLUTNM = "soft_lutpair991" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[14]_INST_0 
       (.I0(Q[52]),
        .I1(my_empty[4]),
        .I2(mem_out[64]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ));
  (* SOFT_HLUTNM = "soft_lutpair990" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[15]_INST_0 
       (.I0(Q[60]),
        .I1(my_empty[4]),
        .I2(mem_out[72]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ));
  (* SOFT_HLUTNM = "soft_lutpair1020" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[200]_INST_0 
       (.I0(Q[7]),
        .I1(my_empty_inst_rep__4_n_0),
        .I2(mem_out[19]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ));
  (* SOFT_HLUTNM = "soft_lutpair1009" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[201]_INST_0 
       (.I0(Q[15]),
        .I1(my_empty_inst_rep__4_n_0),
        .I2(mem_out[27]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ));
  (* SOFT_HLUTNM = "soft_lutpair1018" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[202]_INST_0 
       (.I0(Q[23]),
        .I1(my_empty_inst_rep__4_n_0),
        .I2(mem_out[35]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ));
  (* SOFT_HLUTNM = "soft_lutpair1015" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[203]_INST_0 
       (.I0(Q[31]),
        .I1(my_empty_inst_rep__4_n_0),
        .I2(mem_out[43]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ));
  (* SOFT_HLUTNM = "soft_lutpair1007" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[204]_INST_0 
       (.I0(Q[39]),
        .I1(my_empty[4]),
        .I2(mem_out[51]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ));
  (* SOFT_HLUTNM = "soft_lutpair1014" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[205]_INST_0 
       (.I0(Q[47]),
        .I1(my_empty[4]),
        .I2(mem_out[59]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ));
  (* SOFT_HLUTNM = "soft_lutpair1013" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[206]_INST_0 
       (.I0(Q[55]),
        .I1(my_empty[4]),
        .I2(mem_out[67]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ));
  (* SOFT_HLUTNM = "soft_lutpair1004" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[207]_INST_0 
       (.I0(Q[63]),
        .I1(my_empty[4]),
        .I2(mem_out[75]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] ));
  (* SOFT_HLUTNM = "soft_lutpair995" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[264]_INST_0 
       (.I0(Q[8]),
        .I1(my_empty_inst_rep__4_n_0),
        .I2(mem_out[20]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ));
  (* SOFT_HLUTNM = "soft_lutpair989" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[265]_INST_0 
       (.I0(Q[16]),
        .I1(my_empty_inst_rep__4_n_0),
        .I2(mem_out[28]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ));
  (* SOFT_HLUTNM = "soft_lutpair998" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[266]_INST_0 
       (.I0(Q[24]),
        .I1(my_empty_inst_rep__4_n_0),
        .I2(mem_out[36]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ));
  (* SOFT_HLUTNM = "soft_lutpair989" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[267]_INST_0 
       (.I0(Q[32]),
        .I1(my_empty_inst_rep__4_n_0),
        .I2(mem_out[44]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ));
  (* SOFT_HLUTNM = "soft_lutpair1002" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[268]_INST_0 
       (.I0(Q[40]),
        .I1(my_empty[4]),
        .I2(mem_out[52]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ));
  (* SOFT_HLUTNM = "soft_lutpair997" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[269]_INST_0 
       (.I0(Q[48]),
        .I1(my_empty[4]),
        .I2(mem_out[60]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ));
  (* SOFT_HLUTNM = "soft_lutpair992" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[270]_INST_0 
       (.I0(Q[56]),
        .I1(my_empty[4]),
        .I2(mem_out[68]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ));
  (* SOFT_HLUTNM = "soft_lutpair1001" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[271]_INST_0 
       (.I0(Q[64]),
        .I1(my_empty[4]),
        .I2(mem_out[76]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] ));
  (* SOFT_HLUTNM = "soft_lutpair1010" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[328]_INST_0 
       (.I0(Q[9]),
        .I1(my_empty_inst_rep__4_n_0),
        .I2(mem_out[21]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ));
  (* SOFT_HLUTNM = "soft_lutpair1018" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[329]_INST_0 
       (.I0(Q[17]),
        .I1(my_empty_inst_rep__4_n_0),
        .I2(mem_out[29]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ));
  (* SOFT_HLUTNM = "soft_lutpair1017" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[330]_INST_0 
       (.I0(Q[25]),
        .I1(my_empty_inst_rep__4_n_0),
        .I2(mem_out[37]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ));
  (* SOFT_HLUTNM = "soft_lutpair1008" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[331]_INST_0 
       (.I0(Q[33]),
        .I1(my_empty_inst_rep__4_n_0),
        .I2(mem_out[45]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ));
  (* SOFT_HLUTNM = "soft_lutpair1016" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[332]_INST_0 
       (.I0(Q[41]),
        .I1(my_empty[4]),
        .I2(mem_out[53]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ));
  (* SOFT_HLUTNM = "soft_lutpair1006" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[333]_INST_0 
       (.I0(Q[49]),
        .I1(my_empty[4]),
        .I2(mem_out[61]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ));
  (* SOFT_HLUTNM = "soft_lutpair1004" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[334]_INST_0 
       (.I0(Q[57]),
        .I1(my_empty[4]),
        .I2(mem_out[69]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ));
  (* SOFT_HLUTNM = "soft_lutpair1011" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[335]_INST_0 
       (.I0(Q[65]),
        .I1(my_empty[4]),
        .I2(mem_out[77]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] ));
  (* SOFT_HLUTNM = "soft_lutpair1005" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[392]_INST_0 
       (.I0(Q[10]),
        .I1(my_empty_inst_rep__4_n_0),
        .I2(mem_out[22]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ));
  (* SOFT_HLUTNM = "soft_lutpair999" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[393]_INST_0 
       (.I0(Q[18]),
        .I1(my_empty_inst_rep__4_n_0),
        .I2(mem_out[30]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ));
  (* SOFT_HLUTNM = "soft_lutpair994" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[394]_INST_0 
       (.I0(Q[26]),
        .I1(my_empty_inst_rep__4_n_0),
        .I2(mem_out[38]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ));
  (* SOFT_HLUTNM = "soft_lutpair1000" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[395]_INST_0 
       (.I0(Q[34]),
        .I1(my_empty_inst_rep__4_n_0),
        .I2(mem_out[46]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ));
  (* SOFT_HLUTNM = "soft_lutpair997" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[396]_INST_0 
       (.I0(Q[42]),
        .I1(my_empty[4]),
        .I2(mem_out[54]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ));
  (* SOFT_HLUTNM = "soft_lutpair993" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[397]_INST_0 
       (.I0(Q[50]),
        .I1(my_empty[4]),
        .I2(mem_out[62]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ));
  (* SOFT_HLUTNM = "soft_lutpair1001" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[398]_INST_0 
       (.I0(Q[58]),
        .I1(my_empty[4]),
        .I2(mem_out[70]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ));
  (* SOFT_HLUTNM = "soft_lutpair996" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[399]_INST_0 
       (.I0(Q[66]),
        .I1(my_empty[4]),
        .I2(mem_out[78]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] ));
  (* SOFT_HLUTNM = "soft_lutpair1020" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[456]_INST_0 
       (.I0(Q[11]),
        .I1(my_empty_inst_rep__4_n_0),
        .I2(mem_out[23]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ));
  (* SOFT_HLUTNM = "soft_lutpair1015" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[457]_INST_0 
       (.I0(Q[19]),
        .I1(my_empty_inst_rep__4_n_0),
        .I2(mem_out[31]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ));
  (* SOFT_HLUTNM = "soft_lutpair1008" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[458]_INST_0 
       (.I0(Q[27]),
        .I1(my_empty_inst_rep__4_n_0),
        .I2(mem_out[39]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ));
  (* SOFT_HLUTNM = "soft_lutpair1010" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[459]_INST_0 
       (.I0(Q[35]),
        .I1(my_empty_inst_rep__4_n_0),
        .I2(mem_out[47]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ));
  (* SOFT_HLUTNM = "soft_lutpair1014" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[460]_INST_0 
       (.I0(Q[43]),
        .I1(my_empty[4]),
        .I2(mem_out[55]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ));
  (* SOFT_HLUTNM = "soft_lutpair1006" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[461]_INST_0 
       (.I0(Q[51]),
        .I1(my_empty[4]),
        .I2(mem_out[63]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ));
  (* SOFT_HLUTNM = "soft_lutpair1012" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[462]_INST_0 
       (.I0(Q[59]),
        .I1(my_empty[4]),
        .I2(mem_out[71]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ));
  (* SOFT_HLUTNM = "soft_lutpair1011" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[463]_INST_0 
       (.I0(Q[67]),
        .I1(my_empty[4]),
        .I2(mem_out[79]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ));
  (* SOFT_HLUTNM = "soft_lutpair1019" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[72]_INST_0 
       (.I0(Q[5]),
        .I1(my_empty_inst_rep__4_n_0),
        .I2(mem_out[17]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ));
  (* SOFT_HLUTNM = "soft_lutpair1019" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[73]_INST_0 
       (.I0(Q[13]),
        .I1(my_empty_inst_rep__4_n_0),
        .I2(mem_out[25]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ));
  (* SOFT_HLUTNM = "soft_lutpair1009" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[74]_INST_0 
       (.I0(Q[21]),
        .I1(my_empty_inst_rep__4_n_0),
        .I2(mem_out[33]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ));
  (* SOFT_HLUTNM = "soft_lutpair1017" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[75]_INST_0 
       (.I0(Q[29]),
        .I1(my_empty_inst_rep__4_n_0),
        .I2(mem_out[41]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ));
  (* SOFT_HLUTNM = "soft_lutpair1016" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[76]_INST_0 
       (.I0(Q[37]),
        .I1(my_empty[4]),
        .I2(mem_out[49]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ));
  (* SOFT_HLUTNM = "soft_lutpair1007" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[77]_INST_0 
       (.I0(Q[45]),
        .I1(my_empty[4]),
        .I2(mem_out[57]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ));
  (* SOFT_HLUTNM = "soft_lutpair1013" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[78]_INST_0 
       (.I0(Q[53]),
        .I1(my_empty[4]),
        .I2(mem_out[65]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ));
  (* SOFT_HLUTNM = "soft_lutpair1012" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[79]_INST_0 
       (.I0(Q[61]),
        .I1(my_empty[4]),
        .I2(mem_out[73]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] ));
  (* SOFT_HLUTNM = "soft_lutpair1005" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[8]_INST_0 
       (.I0(Q[4]),
        .I1(my_empty_inst_rep__4_n_0),
        .I2(mem_out[16]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ));
  (* SOFT_HLUTNM = "soft_lutpair999" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[9]_INST_0 
       (.I0(Q[12]),
        .I1(my_empty_inst_rep__4_n_0),
        .I2(mem_out[24]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[0].mux_rd_fall0_r[0]_i_3 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ),
        .I3(\gen_mux_rd[0].mux_rd_fall0_r_reg[0] ),
        .I4(\gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0 ),
        .I5(\gen_mux_rd[0].mux_rd_fall0_r_reg[0]_1 ),
        .O(\rd_mux_sel_r_reg[0]_7 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[0].mux_rd_fall1_r[0]_i_3 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ),
        .I3(\gen_mux_rd[0].mux_rd_fall1_r_reg[0] ),
        .I4(\gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0 ),
        .I5(\gen_mux_rd[0].mux_rd_fall1_r_reg[0]_1 ),
        .O(\rd_mux_sel_r_reg[0]_23 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[0].mux_rd_fall2_r[0]_i_3 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ),
        .I3(\gen_mux_rd[0].mux_rd_fall2_r_reg[0] ),
        .I4(\gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0 ),
        .I5(\gen_mux_rd[0].mux_rd_fall2_r_reg[0]_1 ),
        .O(\rd_mux_sel_r_reg[0]_39 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[0].mux_rd_fall3_r[0]_i_3 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ),
        .I3(\gen_mux_rd[0].mux_rd_fall3_r_reg[0] ),
        .I4(\gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0 ),
        .I5(\gen_mux_rd[0].mux_rd_fall3_r_reg[0]_1 ),
        .O(\rd_mux_sel_r_reg[0]_55 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[0].mux_rd_rise0_r[0]_i_4 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ),
        .I3(\gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1 ),
        .I5(\gen_mux_rd[0].mux_rd_rise0_r_reg[0]_2 ),
        .O(\rd_mux_sel_r_reg[0] ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[0].mux_rd_rise1_r[0]_i_3 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ),
        .I3(\gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .I4(\gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0 ),
        .I5(\gen_mux_rd[0].mux_rd_rise1_r_reg[0]_1 ),
        .O(\rd_mux_sel_r_reg[0]_15 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[0].mux_rd_rise2_r[0]_i_3 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ),
        .I3(\gen_mux_rd[0].mux_rd_rise2_r_reg[0] ),
        .I4(\gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0 ),
        .I5(\gen_mux_rd[0].mux_rd_rise2_r_reg[0]_1 ),
        .O(\rd_mux_sel_r_reg[0]_31 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[0].mux_rd_rise3_r[0]_i_3 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ),
        .I3(\gen_mux_rd[0].mux_rd_rise3_r_reg[0] ),
        .I4(\gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0 ),
        .I5(\gen_mux_rd[0].mux_rd_rise3_r_reg[0]_1 ),
        .O(\rd_mux_sel_r_reg[0]_47 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[1].mux_rd_fall0_r[1]_i_3 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ),
        .I3(\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ),
        .I4(\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ),
        .I5(\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 ),
        .O(\rd_mux_sel_r_reg[0]_8 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[1].mux_rd_fall1_r[1]_i_3 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ),
        .I3(\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ),
        .I4(\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ),
        .I5(\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 ),
        .O(\rd_mux_sel_r_reg[0]_24 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[1].mux_rd_fall2_r[1]_i_3 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ),
        .I3(\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ),
        .I4(\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ),
        .I5(\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 ),
        .O(\rd_mux_sel_r_reg[0]_40 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[1].mux_rd_fall3_r[1]_i_3 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ),
        .I3(\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ),
        .I4(\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ),
        .I5(\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1 ),
        .O(\rd_mux_sel_r_reg[0]_56 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[1].mux_rd_rise0_r[1]_i_3 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ),
        .I3(\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ),
        .I4(\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ),
        .I5(\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1 ),
        .O(\rd_mux_sel_r_reg[0]_0 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[1].mux_rd_rise1_r[1]_i_3 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ),
        .I3(\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ),
        .I4(\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ),
        .I5(\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 ),
        .O(\rd_mux_sel_r_reg[0]_16 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[1].mux_rd_rise2_r[1]_i_3 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ),
        .I3(\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ),
        .I4(\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ),
        .I5(\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 ),
        .O(\rd_mux_sel_r_reg[0]_32 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[1].mux_rd_rise3_r[1]_i_3 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ),
        .I3(\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ),
        .I4(\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ),
        .I5(\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 ),
        .O(\rd_mux_sel_r_reg[0]_48 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[2].mux_rd_fall0_r[2]_i_3 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ),
        .I3(\gen_mux_rd[2].mux_rd_fall0_r_reg[2] ),
        .I4(\gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0 ),
        .I5(\gen_mux_rd[2].mux_rd_fall0_r_reg[2]_1 ),
        .O(\rd_mux_sel_r_reg[0]_9 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[2].mux_rd_fall1_r[2]_i_3 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ),
        .I3(\gen_mux_rd[2].mux_rd_fall1_r_reg[2] ),
        .I4(\gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0 ),
        .I5(\gen_mux_rd[2].mux_rd_fall1_r_reg[2]_1 ),
        .O(\rd_mux_sel_r_reg[0]_25 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[2].mux_rd_fall2_r[2]_i_3 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ),
        .I3(\gen_mux_rd[2].mux_rd_fall2_r_reg[2] ),
        .I4(\gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0 ),
        .I5(\gen_mux_rd[2].mux_rd_fall2_r_reg[2]_1 ),
        .O(\rd_mux_sel_r_reg[0]_41 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[2].mux_rd_fall3_r[2]_i_3 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ),
        .I3(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ),
        .I4(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 ),
        .I5(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_1 ),
        .O(\rd_mux_sel_r_reg[0]_57 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[2].mux_rd_rise0_r[2]_i_3 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ),
        .I3(\gen_mux_rd[2].mux_rd_rise0_r_reg[2] ),
        .I4(\gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ),
        .I5(\gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1 ),
        .O(\rd_mux_sel_r_reg[0]_1 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[2].mux_rd_rise1_r[2]_i_3 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ),
        .I3(\gen_mux_rd[2].mux_rd_rise1_r_reg[2] ),
        .I4(\gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0 ),
        .I5(\gen_mux_rd[2].mux_rd_rise1_r_reg[2]_1 ),
        .O(\rd_mux_sel_r_reg[0]_17 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[2].mux_rd_rise2_r[2]_i_3 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ),
        .I3(\gen_mux_rd[2].mux_rd_rise2_r_reg[2] ),
        .I4(\gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0 ),
        .I5(\gen_mux_rd[2].mux_rd_rise2_r_reg[2]_1 ),
        .O(\rd_mux_sel_r_reg[0]_33 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[2].mux_rd_rise3_r[2]_i_3 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ),
        .I3(\gen_mux_rd[2].mux_rd_rise3_r_reg[2] ),
        .I4(\gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0 ),
        .I5(\gen_mux_rd[2].mux_rd_rise3_r_reg[2]_1 ),
        .O(\rd_mux_sel_r_reg[0]_49 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[3].mux_rd_fall0_r[3]_i_3 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ),
        .I3(\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ),
        .I4(\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ),
        .I5(\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 ),
        .O(\rd_mux_sel_r_reg[0]_10 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[3].mux_rd_fall1_r[3]_i_3 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ),
        .I3(\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ),
        .I4(\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ),
        .I5(\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 ),
        .O(\rd_mux_sel_r_reg[0]_26 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[3].mux_rd_fall2_r[3]_i_3 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ),
        .I3(\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ),
        .I4(\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ),
        .I5(\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 ),
        .O(\rd_mux_sel_r_reg[0]_42 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[3].mux_rd_fall3_r[3]_i_3 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ),
        .I3(\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ),
        .I4(\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ),
        .I5(\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 ),
        .O(\rd_mux_sel_r_reg[0]_58 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[3].mux_rd_rise0_r[3]_i_3 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ),
        .I3(\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ),
        .I4(\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ),
        .I5(\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 ),
        .O(\rd_mux_sel_r_reg[0]_2 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[3].mux_rd_rise1_r[3]_i_3 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ),
        .I3(\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ),
        .I4(\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ),
        .I5(\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 ),
        .O(\rd_mux_sel_r_reg[0]_18 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[3].mux_rd_rise2_r[3]_i_3 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ),
        .I3(\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ),
        .I4(\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ),
        .I5(\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 ),
        .O(\rd_mux_sel_r_reg[0]_34 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[3].mux_rd_rise3_r[3]_i_3 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ),
        .I3(\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ),
        .I4(\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ),
        .I5(\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 ),
        .O(\rd_mux_sel_r_reg[0]_50 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[4].mux_rd_fall0_r[4]_i_3 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ),
        .I3(\gen_mux_rd[4].mux_rd_fall0_r_reg[4] ),
        .I4(\gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0 ),
        .I5(\gen_mux_rd[4].mux_rd_fall0_r_reg[4]_1 ),
        .O(\rd_mux_sel_r_reg[0]_11 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[4].mux_rd_fall1_r[4]_i_3 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ),
        .I3(\gen_mux_rd[4].mux_rd_fall1_r_reg[4] ),
        .I4(\gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0 ),
        .I5(\gen_mux_rd[4].mux_rd_fall1_r_reg[4]_1 ),
        .O(\rd_mux_sel_r_reg[0]_27 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[4].mux_rd_fall2_r[4]_i_3 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ),
        .I3(\gen_mux_rd[4].mux_rd_fall2_r_reg[4] ),
        .I4(\gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0 ),
        .I5(\gen_mux_rd[4].mux_rd_fall2_r_reg[4]_1 ),
        .O(\rd_mux_sel_r_reg[0]_43 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[4].mux_rd_fall3_r[4]_i_3 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ),
        .I3(\gen_mux_rd[4].mux_rd_fall3_r_reg[4] ),
        .I4(\gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0 ),
        .I5(\gen_mux_rd[4].mux_rd_fall3_r_reg[4]_1 ),
        .O(\rd_mux_sel_r_reg[0]_59 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[4].mux_rd_rise0_r[4]_i_3 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ),
        .I3(\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .I4(\gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0 ),
        .I5(\gen_mux_rd[4].mux_rd_rise0_r_reg[4]_1 ),
        .O(\rd_mux_sel_r_reg[0]_3 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[4].mux_rd_rise1_r[4]_i_3 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ),
        .I3(\gen_mux_rd[4].mux_rd_rise1_r_reg[4] ),
        .I4(\gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0 ),
        .I5(\gen_mux_rd[4].mux_rd_rise1_r_reg[4]_1 ),
        .O(\rd_mux_sel_r_reg[0]_19 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[4].mux_rd_rise2_r[4]_i_3 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ),
        .I3(\gen_mux_rd[4].mux_rd_rise2_r_reg[4] ),
        .I4(\gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0 ),
        .I5(\gen_mux_rd[4].mux_rd_rise2_r_reg[4]_1 ),
        .O(\rd_mux_sel_r_reg[0]_35 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[4].mux_rd_rise3_r[4]_i_3 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ),
        .I3(\gen_mux_rd[4].mux_rd_rise3_r_reg[4] ),
        .I4(\gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0 ),
        .I5(\gen_mux_rd[4].mux_rd_rise3_r_reg[4]_1 ),
        .O(\rd_mux_sel_r_reg[0]_51 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[5].mux_rd_fall0_r[5]_i_3 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ),
        .I3(\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ),
        .I4(\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ),
        .I5(\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 ),
        .O(\rd_mux_sel_r_reg[0]_12 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[5].mux_rd_fall1_r[5]_i_3 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ),
        .I3(\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ),
        .I4(\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ),
        .I5(\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 ),
        .O(\rd_mux_sel_r_reg[0]_28 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[5].mux_rd_fall2_r[5]_i_3 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ),
        .I3(\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ),
        .I4(\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ),
        .I5(\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 ),
        .O(\rd_mux_sel_r_reg[0]_44 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[5].mux_rd_fall3_r[5]_i_3 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ),
        .I3(\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ),
        .I4(\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ),
        .I5(\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 ),
        .O(\rd_mux_sel_r_reg[0]_60 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[5].mux_rd_rise0_r[5]_i_3 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ),
        .I3(\gen_mux_rd[5].mux_rd_rise0_r_reg[5] ),
        .I4(\gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0 ),
        .I5(\gen_mux_rd[5].mux_rd_rise0_r_reg[5]_1 ),
        .O(\rd_mux_sel_r_reg[0]_4 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[5].mux_rd_rise1_r[5]_i_3 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ),
        .I3(\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ),
        .I4(\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ),
        .I5(\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 ),
        .O(\rd_mux_sel_r_reg[0]_20 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[5].mux_rd_rise2_r[5]_i_3 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ),
        .I3(\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ),
        .I4(\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ),
        .I5(\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 ),
        .O(\rd_mux_sel_r_reg[0]_36 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[5].mux_rd_rise3_r[5]_i_3 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ),
        .I3(\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ),
        .I4(\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ),
        .I5(\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 ),
        .O(\rd_mux_sel_r_reg[0]_52 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[6].mux_rd_fall0_r[6]_i_3 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ),
        .I3(\gen_mux_rd[6].mux_rd_fall0_r_reg[6] ),
        .I4(\gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0 ),
        .I5(\gen_mux_rd[6].mux_rd_fall0_r_reg[6]_1 ),
        .O(\rd_mux_sel_r_reg[0]_13 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[6].mux_rd_fall1_r[6]_i_3 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ),
        .I3(\gen_mux_rd[6].mux_rd_fall1_r_reg[6] ),
        .I4(\gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0 ),
        .I5(\gen_mux_rd[6].mux_rd_fall1_r_reg[6]_1 ),
        .O(\rd_mux_sel_r_reg[0]_29 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[6].mux_rd_fall2_r[6]_i_3 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ),
        .I3(\gen_mux_rd[6].mux_rd_fall2_r_reg[6] ),
        .I4(\gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0 ),
        .I5(\gen_mux_rd[6].mux_rd_fall2_r_reg[6]_1 ),
        .O(\rd_mux_sel_r_reg[0]_45 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[6].mux_rd_fall3_r[6]_i_3 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ),
        .I3(\gen_mux_rd[6].mux_rd_fall3_r_reg[6] ),
        .I4(\gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0 ),
        .I5(\gen_mux_rd[6].mux_rd_fall3_r_reg[6]_1 ),
        .O(\rd_mux_sel_r_reg[0]_61 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[6].mux_rd_rise0_r[6]_i_3 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ),
        .I3(\gen_mux_rd[6].mux_rd_rise0_r_reg[6] ),
        .I4(\gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0 ),
        .I5(\gen_mux_rd[6].mux_rd_rise0_r_reg[6]_1 ),
        .O(\rd_mux_sel_r_reg[0]_5 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[6].mux_rd_rise1_r[6]_i_3 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ),
        .I3(\gen_mux_rd[6].mux_rd_rise1_r_reg[6] ),
        .I4(\gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0 ),
        .I5(\gen_mux_rd[6].mux_rd_rise1_r_reg[6]_1 ),
        .O(\rd_mux_sel_r_reg[0]_21 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[6].mux_rd_rise2_r[6]_i_3 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ),
        .I3(\gen_mux_rd[6].mux_rd_rise2_r_reg[6] ),
        .I4(\gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0 ),
        .I5(\gen_mux_rd[6].mux_rd_rise2_r_reg[6]_1 ),
        .O(\rd_mux_sel_r_reg[0]_37 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[6].mux_rd_rise3_r[6]_i_3 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ),
        .I3(\gen_mux_rd[6].mux_rd_rise3_r_reg[6] ),
        .I4(\gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0 ),
        .I5(\gen_mux_rd[6].mux_rd_rise3_r_reg[6]_1 ),
        .O(\rd_mux_sel_r_reg[0]_53 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[7].mux_rd_fall0_r[7]_i_3 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] ),
        .I3(\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ),
        .I4(\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ),
        .I5(\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 ),
        .O(\rd_mux_sel_r_reg[0]_14 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[7].mux_rd_fall1_r[7]_i_3 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] ),
        .I3(\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ),
        .I4(\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ),
        .I5(\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 ),
        .O(\rd_mux_sel_r_reg[0]_30 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[7].mux_rd_fall2_r[7]_i_3 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] ),
        .I3(\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ),
        .I4(\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ),
        .I5(\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 ),
        .O(\rd_mux_sel_r_reg[0]_46 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[7].mux_rd_fall3_r[7]_i_3 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ),
        .I3(\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ),
        .I4(\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ),
        .I5(\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 ),
        .O(\rd_mux_sel_r_reg[0]_62 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[7].mux_rd_rise0_r[7]_i_3 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ),
        .I3(\gen_mux_rd[7].mux_rd_rise0_r_reg[7] ),
        .I4(\gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0 ),
        .I5(\gen_mux_rd[7].mux_rd_rise0_r_reg[7]_1 ),
        .O(\rd_mux_sel_r_reg[0]_6 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[7].mux_rd_rise1_r[7]_i_3 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] ),
        .I3(\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ),
        .I4(\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ),
        .I5(\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 ),
        .O(\rd_mux_sel_r_reg[0]_22 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[7].mux_rd_rise2_r[7]_i_3 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] ),
        .I3(\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ),
        .I4(\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ),
        .I5(\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 ),
        .O(\rd_mux_sel_r_reg[0]_38 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[7].mux_rd_rise3_r[7]_i_3 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] ),
        .I3(\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ),
        .I4(\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ),
        .I5(\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 ),
        .O(\rd_mux_sel_r_reg[0]_54 ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "12" *) 
  (* ram_slice_end = "17" *) 
  RAM32M mem_reg_0_3_12_17
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[1:0]),
        .DIB(Q[3:2]),
        .DIC(Q[5:4]),
        .DID({1'b0,1'b0}),
        .DOA({mem_reg_0_3_12_17_n_0,mem_reg_0_3_12_17_n_1}),
        .DOB({mem_reg_0_3_12_17_n_2,mem_reg_0_3_12_17_n_3}),
        .DOC(mem_out[17:16]),
        .DOD(NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_timing_reg[1]_0 ),
        .WE(wr_en));
  LUT4 #(
    .INIT(16'h0151)) 
    mem_reg_0_3_12_17_i_1
       (.I0(\my_full_reg[1]_0 ),
        .I1(my_full[0]),
        .I2(\my_full_reg[1]_1 ),
        .I3(my_empty[2]),
        .O(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "18" *) 
  (* ram_slice_end = "23" *) 
  RAM32M mem_reg_0_3_18_23
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[7:6]),
        .DIB(Q[9:8]),
        .DIC(Q[11:10]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[19:18]),
        .DOB(mem_out[21:20]),
        .DOC(mem_out[23:22]),
        .DOD(NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_timing_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "24" *) 
  (* ram_slice_end = "29" *) 
  RAM32M mem_reg_0_3_24_29
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[13:12]),
        .DIB(Q[15:14]),
        .DIC(Q[17:16]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[25:24]),
        .DOB(mem_out[27:26]),
        .DOC(mem_out[29:28]),
        .DOD(NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_timing_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "30" *) 
  (* ram_slice_end = "35" *) 
  RAM32M mem_reg_0_3_30_35
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[19:18]),
        .DIB(Q[21:20]),
        .DIC(Q[23:22]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[31:30]),
        .DOB(mem_out[33:32]),
        .DOC(mem_out[35:34]),
        .DOD(NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_timing_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "36" *) 
  (* ram_slice_end = "41" *) 
  RAM32M mem_reg_0_3_36_41
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[25:24]),
        .DIB(Q[27:26]),
        .DIC(Q[29:28]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[37:36]),
        .DOB(mem_out[39:38]),
        .DOC(mem_out[41:40]),
        .DOD(NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_timing_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "42" *) 
  (* ram_slice_end = "47" *) 
  RAM32M mem_reg_0_3_42_47
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[31:30]),
        .DIB(Q[33:32]),
        .DIC(Q[35:34]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[43:42]),
        .DOB(mem_out[45:44]),
        .DOC(mem_out[47:46]),
        .DOD(NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_timing_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "48" *) 
  (* ram_slice_end = "53" *) 
  RAM32M mem_reg_0_3_48_53
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[37:36]),
        .DIB(Q[39:38]),
        .DIC(Q[41:40]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[49:48]),
        .DOB(mem_out[51:50]),
        .DOC(mem_out[53:52]),
        .DOD(NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_timing_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "54" *) 
  (* ram_slice_end = "59" *) 
  RAM32M mem_reg_0_3_54_59
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[43:42]),
        .DIB(Q[45:44]),
        .DIC(Q[47:46]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[55:54]),
        .DOB(mem_out[57:56]),
        .DOC(mem_out[59:58]),
        .DOD(NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_timing_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "60" *) 
  (* ram_slice_end = "65" *) 
  RAM32M mem_reg_0_3_60_65
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[49:48]),
        .DIB(Q[51:50]),
        .DIC(Q[53:52]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[61:60]),
        .DOB(mem_out[63:62]),
        .DOC(mem_out[65:64]),
        .DOD(NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_timing_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "66" *) 
  (* ram_slice_end = "71" *) 
  RAM32M mem_reg_0_3_66_71
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[55:54]),
        .DIB(Q[57:56]),
        .DIC(Q[59:58]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[67:66]),
        .DOB(mem_out[69:68]),
        .DOC(mem_out[71:70]),
        .DOD(NLW_mem_reg_0_3_66_71_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_timing_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "72" *) 
  (* ram_slice_end = "77" *) 
  RAM32M mem_reg_0_3_72_77
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[61:60]),
        .DIB(Q[63:62]),
        .DIC(Q[65:64]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[73:72]),
        .DOB(mem_out[75:74]),
        .DOC(mem_out[77:76]),
        .DOD(NLW_mem_reg_0_3_72_77_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_timing_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "78" *) 
  (* ram_slice_end = "79" *) 
  RAM32M mem_reg_0_3_78_79
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[67:66]),
        .DIB({1'b0,1'b0}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[79:78]),
        .DOB(NLW_mem_reg_0_3_78_79_DOB_UNCONNECTED[1:0]),
        .DOC(NLW_mem_reg_0_3_78_79_DOC_UNCONNECTED[1:0]),
        .DOD(NLW_mem_reg_0_3_78_79_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_timing_reg[1]_0 ),
        .WE(wr_en));
  LUT4 #(
    .INIT(16'h0018)) 
    \my_empty[4]_i_1__0 
       (.I0(\my_full_reg[1]_1 ),
        .I1(\my_full_reg[1]_0 ),
        .I2(my_empty[1]),
        .I3(my_full[1]),
        .O(\my_empty[4]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'h00411400)) 
    \my_empty[4]_i_2__4 
       (.I0(my_empty[1]),
        .I1(wr_ptr[1]),
        .I2(rd_ptr[1]),
        .I3(rd_ptr[0]),
        .I4(wr_ptr[0]),
        .O(\my_empty[4]_i_2__4_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    my_empty_inst__19
       (.I0(\my_empty_reg[4]_rep_n_0 ),
        .O(my_empty[4]));
  (* SOFT_HLUTNM = "soft_lutpair1021" *) 
  LUT1 #(
    .INIT(2'h2)) 
    my_empty_inst__20
       (.I0(\my_empty_reg[4]_0 ),
        .O(\my_empty_reg[4]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair1021" *) 
  LUT1 #(
    .INIT(2'h2)) 
    my_empty_inst__21
       (.I0(\my_empty_reg[4]_0 ),
        .O(my_empty[2]));
  LUT1 #(
    .INIT(2'h2)) 
    my_empty_inst__22
       (.I0(\my_empty_reg[4]_0 ),
        .O(my_empty[1]));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  LUT1 #(
    .INIT(2'h2)) 
    my_empty_inst_rep__4
       (.I0(\my_empty_reg[4]_rep__0_n_0 ),
        .O(my_empty_inst_rep__4_n_0));
  (* ORIG_CELL_NAME = "my_empty_reg[4]" *) 
  FDSE \my_empty_reg[4] 
       (.C(\rd_ptr_timing_reg[1]_0 ),
        .CE(\my_empty[4]_i_1__0_n_0 ),
        .D(\my_empty[4]_i_2__4_n_0 ),
        .Q(\my_empty_reg[4]_0 ),
        .S(ififo_rst));
  (* ORIG_CELL_NAME = "my_empty_reg[4]" *) 
  FDSE \my_empty_reg[4]_rep 
       (.C(\rd_ptr_timing_reg[1]_0 ),
        .CE(\my_empty[4]_i_1__0_n_0 ),
        .D(\my_empty[4]_i_2__4_n_0 ),
        .Q(\my_empty_reg[4]_rep_n_0 ),
        .S(ififo_rst));
  (* ORIG_CELL_NAME = "my_empty_reg[4]" *) 
  FDSE \my_empty_reg[4]_rep__0 
       (.C(\rd_ptr_timing_reg[1]_0 ),
        .CE(\my_empty[4]_i_1__0_n_0 ),
        .D(\my_empty[4]_i_2__4_n_0 ),
        .Q(\my_empty_reg[4]_rep__0_n_0 ),
        .S(ififo_rst));
  LUT6 #(
    .INIT(64'hAAAAEAABAAAA2AA8)) 
    \my_full[0]_i_1__4 
       (.I0(my_full[0]),
        .I1(\my_full_reg[1]_1 ),
        .I2(\my_full_reg[1]_0 ),
        .I3(my_full[1]),
        .I4(my_empty[1]),
        .I5(\my_full[1]_i_2__4_n_0 ),
        .O(\my_full[0]_i_1__4_n_0 ));
  LUT5 #(
    .INIT(32'hF0F1F070)) 
    \my_full[1]_i_1__4 
       (.I0(\my_full_reg[1]_1 ),
        .I1(\my_full_reg[1]_0 ),
        .I2(my_full[1]),
        .I3(my_empty[1]),
        .I4(\my_full[1]_i_2__4_n_0 ),
        .O(\my_full[1]_i_1__4_n_0 ));
  LUT5 #(
    .INIT(32'h00411400)) 
    \my_full[1]_i_2__4 
       (.I0(my_full[1]),
        .I1(rd_ptr[1]),
        .I2(wr_ptr[1]),
        .I3(wr_ptr[0]),
        .I4(rd_ptr[0]),
        .O(\my_full[1]_i_2__4_n_0 ));
  FDRE \my_full_reg[0] 
       (.C(\rd_ptr_timing_reg[1]_0 ),
        .CE(1'b1),
        .D(\my_full[0]_i_1__4_n_0 ),
        .Q(my_full[0]),
        .R(ififo_rst));
  FDRE \my_full_reg[1] 
       (.C(\rd_ptr_timing_reg[1]_0 ),
        .CE(1'b1),
        .D(\my_full[1]_i_1__4_n_0 ),
        .Q(my_full[1]),
        .R(ififo_rst));
  (* SOFT_HLUTNM = "soft_lutpair988" *) 
  LUT3 #(
    .INIT(8'hD2)) 
    \rd_ptr[0]_i_1__4 
       (.I0(\my_full_reg[1]_1 ),
        .I1(my_empty[1]),
        .I2(rd_ptr[0]),
        .O(\rd_ptr[0]_i_1__4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair988" *) 
  LUT4 #(
    .INIT(16'hF708)) 
    \rd_ptr[1]_i_1__4 
       (.I0(rd_ptr[0]),
        .I1(\my_full_reg[1]_1 ),
        .I2(my_empty[1]),
        .I3(rd_ptr[1]),
        .O(\rd_ptr[1]_i_1__4_n_0 ));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[0] 
       (.C(\rd_ptr_timing_reg[1]_0 ),
        .CE(1'b1),
        .D(\rd_ptr[0]_i_1__4_n_0 ),
        .Q(rd_ptr[0]),
        .R(ififo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[1] 
       (.C(\rd_ptr_timing_reg[1]_0 ),
        .CE(1'b1),
        .D(\rd_ptr[1]_i_1__4_n_0 ),
        .Q(rd_ptr[1]),
        .R(ififo_rst));
  LUT4 #(
    .INIT(16'hF704)) 
    \rd_ptr_timing[0]_i_1__10 
       (.I0(rd_ptr[0]),
        .I1(\my_full_reg[1]_1 ),
        .I2(my_empty[1]),
        .I3(rd_ptr_timing[0]),
        .O(\rd_ptr_timing[0]_i_1__10_n_0 ));
  LUT5 #(
    .INIT(32'hFF6F0060)) 
    \rd_ptr_timing[1]_i_1__10 
       (.I0(rd_ptr[0]),
        .I1(rd_ptr[1]),
        .I2(\my_full_reg[1]_1 ),
        .I3(my_empty[1]),
        .I4(rd_ptr_timing[1]),
        .O(\rd_ptr_timing[1]_i_1__10_n_0 ));
  (* KEEP = "yes" *) 
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_timing_reg[0] 
       (.C(\rd_ptr_timing_reg[1]_0 ),
        .CE(1'b1),
        .D(\rd_ptr_timing[0]_i_1__10_n_0 ),
        .Q(rd_ptr_timing[0]),
        .R(ififo_rst));
  (* KEEP = "yes" *) 
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_timing_reg[1] 
       (.C(\rd_ptr_timing_reg[1]_0 ),
        .CE(1'b1),
        .D(\rd_ptr_timing[1]_i_1__10_n_0 ),
        .Q(rd_ptr_timing[1]),
        .R(ififo_rst));
  LUT5 #(
    .INIT(32'hFECE0131)) 
    \wr_ptr[0]_i_1__10 
       (.I0(my_full[1]),
        .I1(\my_full_reg[1]_0 ),
        .I2(\my_full_reg[1]_1 ),
        .I3(my_empty[1]),
        .I4(wr_ptr[0]),
        .O(\wr_ptr[0]_i_1__10_n_0 ));
  LUT6 #(
    .INIT(64'hFFFDF5FD00020A02)) 
    \wr_ptr[1]_i_1__10 
       (.I0(wr_ptr[0]),
        .I1(my_full[1]),
        .I2(\my_full_reg[1]_0 ),
        .I3(\my_full_reg[1]_1 ),
        .I4(my_empty[1]),
        .I5(wr_ptr[1]),
        .O(\wr_ptr[1]_i_1__10_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \wr_ptr[1]_i_3__2 
       (.I0(\my_full_reg[1]_0 ),
        .I1(\my_empty_reg[4]_1 ),
        .O(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[0] 
       (.C(\rd_ptr_timing_reg[1]_0 ),
        .CE(1'b1),
        .D(\wr_ptr[0]_i_1__10_n_0 ),
        .Q(wr_ptr[0]),
        .R(ififo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[1] 
       (.C(\rd_ptr_timing_reg[1]_0 ),
        .CE(1'b1),
        .D(\wr_ptr[1]_i_1__10_n_0 ),
        .Q(wr_ptr[1]),
        .R(ififo_rst));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_if_post_fifo" *) 
module mig_mig_7series_v4_2_ddr_if_post_fifo_20
   (\my_empty_reg[4]_0 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ,
    ififo_rst,
    \rd_ptr_reg[1]_0 ,
    \my_full_reg[1]_0 ,
    \my_full_reg[1]_1 ,
    Q);
  output \my_empty_reg[4]_0 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ;
  input ififo_rst;
  input \rd_ptr_reg[1]_0 ;
  input \my_full_reg[1]_0 ;
  input \my_full_reg[1]_1 ;
  input [67:0]Q;

  wire [67:0]Q;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ;
  wire ififo_rst;
  wire [79:8]mem_out;
  wire mem_reg_0_3_60_65_n_4;
  wire mem_reg_0_3_60_65_n_5;
  wire mem_reg_0_3_6_11_n_0;
  wire mem_reg_0_3_6_11_n_1;
  wire [4:1]my_empty;
  wire \my_empty[4]_i_1_n_0 ;
  wire \my_empty[4]_i_2__3_n_0 ;
  wire my_empty_inst_rep__3_n_0;
  wire \my_empty_reg[4]_0 ;
  wire \my_empty_reg[4]_rep__0_n_0 ;
  wire \my_empty_reg[4]_rep_n_0 ;
  wire [1:0]my_full;
  wire \my_full[0]_i_1__3_n_0 ;
  wire \my_full[1]_i_1__3_n_0 ;
  wire \my_full[1]_i_2__3_n_0 ;
  wire \my_full_reg[1]_0 ;
  wire \my_full_reg[1]_1 ;
  wire [1:0]rd_ptr;
  wire \rd_ptr[0]_i_1__3_n_0 ;
  wire \rd_ptr[1]_i_1__3_n_0 ;
  wire \rd_ptr_reg[1]_0 ;
  (* RTL_KEEP = "true" *) (* syn_maxfan = "10" *) wire [1:0]rd_ptr_timing;
  wire \rd_ptr_timing[0]_i_1__8_n_0 ;
  wire \rd_ptr_timing[1]_i_1__8_n_0 ;
  (* MAX_FANOUT = "40" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire wr_en;
  wire [1:0]wr_ptr;
  wire \wr_ptr[0]_i_1__8_n_0 ;
  wire \wr_ptr[1]_i_1__8_n_0 ;
  wire [1:0]NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_6_11_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_72_77_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_78_79_DOB_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_78_79_DOC_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_78_79_DOD_UNCONNECTED;

  (* SOFT_HLUTNM = "soft_lutpair946" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[0]_INST_0 
       (.I0(Q[2]),
        .I1(my_empty_inst_rep__3_n_0),
        .I2(mem_out[8]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ));
  (* SOFT_HLUTNM = "soft_lutpair955" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[128]_INST_0 
       (.I0(Q[4]),
        .I1(my_empty_inst_rep__3_n_0),
        .I2(mem_out[10]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ));
  (* SOFT_HLUTNM = "soft_lutpair950" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[129]_INST_0 
       (.I0(Q[12]),
        .I1(my_empty_inst_rep__3_n_0),
        .I2(mem_out[18]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ));
  (* SOFT_HLUTNM = "soft_lutpair944" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[130]_INST_0 
       (.I0(Q[20]),
        .I1(my_empty_inst_rep__3_n_0),
        .I2(mem_out[26]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ));
  (* SOFT_HLUTNM = "soft_lutpair953" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[131]_INST_0 
       (.I0(Q[28]),
        .I1(my_empty_inst_rep__3_n_0),
        .I2(mem_out[34]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ));
  (* SOFT_HLUTNM = "soft_lutpair948" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[132]_INST_0 
       (.I0(Q[36]),
        .I1(my_empty[4]),
        .I2(mem_out[42]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ));
  (* SOFT_HLUTNM = "soft_lutpair943" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[133]_INST_0 
       (.I0(Q[44]),
        .I1(my_empty[4]),
        .I2(mem_out[50]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ));
  (* SOFT_HLUTNM = "soft_lutpair951" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[134]_INST_0 
       (.I0(Q[52]),
        .I1(my_empty[4]),
        .I2(mem_out[58]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ));
  (* SOFT_HLUTNM = "soft_lutpair942" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[135]_INST_0 
       (.I0(Q[62]),
        .I1(my_empty[4]),
        .I2(mem_out[74]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] ));
  (* SOFT_HLUTNM = "soft_lutpair969" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[192]_INST_0 
       (.I0(Q[5]),
        .I1(my_empty_inst_rep__3_n_0),
        .I2(mem_out[11]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ));
  (* SOFT_HLUTNM = "soft_lutpair969" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[193]_INST_0 
       (.I0(Q[13]),
        .I1(my_empty_inst_rep__3_n_0),
        .I2(mem_out[19]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ));
  (* SOFT_HLUTNM = "soft_lutpair959" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[194]_INST_0 
       (.I0(Q[21]),
        .I1(my_empty_inst_rep__3_n_0),
        .I2(mem_out[27]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ));
  (* SOFT_HLUTNM = "soft_lutpair967" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[195]_INST_0 
       (.I0(Q[29]),
        .I1(my_empty_inst_rep__3_n_0),
        .I2(mem_out[35]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ));
  (* SOFT_HLUTNM = "soft_lutpair966" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[196]_INST_0 
       (.I0(Q[37]),
        .I1(my_empty[4]),
        .I2(mem_out[43]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ));
  (* SOFT_HLUTNM = "soft_lutpair957" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[197]_INST_0 
       (.I0(Q[45]),
        .I1(my_empty[4]),
        .I2(mem_out[51]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ));
  (* SOFT_HLUTNM = "soft_lutpair963" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[198]_INST_0 
       (.I0(Q[53]),
        .I1(my_empty[4]),
        .I2(mem_out[59]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ));
  (* SOFT_HLUTNM = "soft_lutpair954" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[199]_INST_0 
       (.I0(Q[63]),
        .I1(my_empty[4]),
        .I2(mem_out[75]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] ));
  (* SOFT_HLUTNM = "soft_lutpair955" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[1]_INST_0 
       (.I0(Q[10]),
        .I1(my_empty_inst_rep__3_n_0),
        .I2(mem_out[16]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ));
  (* SOFT_HLUTNM = "soft_lutpair950" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[256]_INST_0 
       (.I0(Q[6]),
        .I1(my_empty_inst_rep__3_n_0),
        .I2(mem_out[12]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ));
  (* SOFT_HLUTNM = "soft_lutpair945" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[257]_INST_0 
       (.I0(Q[14]),
        .I1(my_empty_inst_rep__3_n_0),
        .I2(mem_out[20]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ));
  (* SOFT_HLUTNM = "soft_lutpair953" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[258]_INST_0 
       (.I0(Q[22]),
        .I1(my_empty_inst_rep__3_n_0),
        .I2(mem_out[28]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ));
  (* SOFT_HLUTNM = "soft_lutpair946" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[259]_INST_0 
       (.I0(Q[30]),
        .I1(my_empty_inst_rep__3_n_0),
        .I2(mem_out[36]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ));
  (* SOFT_HLUTNM = "soft_lutpair943" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[260]_INST_0 
       (.I0(Q[38]),
        .I1(my_empty[4]),
        .I2(mem_out[44]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ));
  (* SOFT_HLUTNM = "soft_lutpair952" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[261]_INST_0 
       (.I0(Q[46]),
        .I1(my_empty[4]),
        .I2(mem_out[52]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ));
  (* SOFT_HLUTNM = "soft_lutpair947" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[262]_INST_0 
       (.I0(Q[54]),
        .I1(my_empty[4]),
        .I2(mem_out[60]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ));
  (* SOFT_HLUTNM = "soft_lutpair951" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[263]_INST_0 
       (.I0(Q[64]),
        .I1(my_empty[4]),
        .I2(mem_out[76]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] ));
  (* SOFT_HLUTNM = "soft_lutpair949" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[2]_INST_0 
       (.I0(Q[18]),
        .I1(my_empty_inst_rep__3_n_0),
        .I2(mem_out[24]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ));
  (* SOFT_HLUTNM = "soft_lutpair970" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[320]_INST_0 
       (.I0(Q[7]),
        .I1(my_empty_inst_rep__3_n_0),
        .I2(mem_out[13]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ));
  (* SOFT_HLUTNM = "soft_lutpair959" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[321]_INST_0 
       (.I0(Q[15]),
        .I1(my_empty_inst_rep__3_n_0),
        .I2(mem_out[21]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ));
  (* SOFT_HLUTNM = "soft_lutpair968" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[322]_INST_0 
       (.I0(Q[23]),
        .I1(my_empty_inst_rep__3_n_0),
        .I2(mem_out[29]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ));
  (* SOFT_HLUTNM = "soft_lutpair965" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[323]_INST_0 
       (.I0(Q[31]),
        .I1(my_empty_inst_rep__3_n_0),
        .I2(mem_out[37]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ));
  (* SOFT_HLUTNM = "soft_lutpair957" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[324]_INST_0 
       (.I0(Q[39]),
        .I1(my_empty[4]),
        .I2(mem_out[45]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ));
  (* SOFT_HLUTNM = "soft_lutpair963" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[325]_INST_0 
       (.I0(Q[47]),
        .I1(my_empty[4]),
        .I2(mem_out[53]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ));
  (* SOFT_HLUTNM = "soft_lutpair962" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[326]_INST_0 
       (.I0(Q[55]),
        .I1(my_empty[4]),
        .I2(mem_out[61]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ));
  (* SOFT_HLUTNM = "soft_lutpair961" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[327]_INST_0 
       (.I0(Q[65]),
        .I1(my_empty[4]),
        .I2(mem_out[77]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] ));
  (* SOFT_HLUTNM = "soft_lutpair945" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[384]_INST_0 
       (.I0(Q[8]),
        .I1(my_empty_inst_rep__3_n_0),
        .I2(mem_out[14]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ));
  (* SOFT_HLUTNM = "soft_lutpair939" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[385]_INST_0 
       (.I0(Q[16]),
        .I1(my_empty_inst_rep__3_n_0),
        .I2(mem_out[22]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ));
  (* SOFT_HLUTNM = "soft_lutpair949" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[386]_INST_0 
       (.I0(Q[24]),
        .I1(my_empty_inst_rep__3_n_0),
        .I2(mem_out[30]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ));
  (* SOFT_HLUTNM = "soft_lutpair939" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[387]_INST_0 
       (.I0(Q[32]),
        .I1(my_empty_inst_rep__3_n_0),
        .I2(mem_out[38]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ));
  (* SOFT_HLUTNM = "soft_lutpair952" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[388]_INST_0 
       (.I0(Q[40]),
        .I1(my_empty[4]),
        .I2(mem_out[46]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ));
  (* SOFT_HLUTNM = "soft_lutpair948" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[389]_INST_0 
       (.I0(Q[48]),
        .I1(my_empty[4]),
        .I2(mem_out[54]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ));
  (* SOFT_HLUTNM = "soft_lutpair942" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[390]_INST_0 
       (.I0(Q[56]),
        .I1(my_empty[4]),
        .I2(mem_out[62]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ));
  (* SOFT_HLUTNM = "soft_lutpair947" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[391]_INST_0 
       (.I0(Q[66]),
        .I1(my_empty[4]),
        .I2(mem_out[78]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] ));
  (* SOFT_HLUTNM = "soft_lutpair944" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[3]_INST_0 
       (.I0(Q[26]),
        .I1(my_empty_inst_rep__3_n_0),
        .I2(mem_out[32]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ));
  (* SOFT_HLUTNM = "soft_lutpair960" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[448]_INST_0 
       (.I0(Q[9]),
        .I1(my_empty_inst_rep__3_n_0),
        .I2(mem_out[15]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ));
  (* SOFT_HLUTNM = "soft_lutpair968" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[449]_INST_0 
       (.I0(Q[17]),
        .I1(my_empty_inst_rep__3_n_0),
        .I2(mem_out[23]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ));
  (* SOFT_HLUTNM = "soft_lutpair967" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[450]_INST_0 
       (.I0(Q[25]),
        .I1(my_empty_inst_rep__3_n_0),
        .I2(mem_out[31]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ));
  (* SOFT_HLUTNM = "soft_lutpair958" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[451]_INST_0 
       (.I0(Q[33]),
        .I1(my_empty_inst_rep__3_n_0),
        .I2(mem_out[39]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ));
  (* SOFT_HLUTNM = "soft_lutpair964" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[452]_INST_0 
       (.I0(Q[41]),
        .I1(my_empty[4]),
        .I2(mem_out[47]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ));
  (* SOFT_HLUTNM = "soft_lutpair956" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[453]_INST_0 
       (.I0(Q[49]),
        .I1(my_empty[4]),
        .I2(mem_out[55]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ));
  (* SOFT_HLUTNM = "soft_lutpair954" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[454]_INST_0 
       (.I0(Q[57]),
        .I1(my_empty[4]),
        .I2(mem_out[63]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ));
  (* SOFT_HLUTNM = "soft_lutpair961" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[455]_INST_0 
       (.I0(Q[67]),
        .I1(my_empty[4]),
        .I2(mem_out[79]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ));
  (* SOFT_HLUTNM = "soft_lutpair941" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[4]_INST_0 
       (.I0(Q[34]),
        .I1(my_empty[4]),
        .I2(mem_out[40]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ));
  (* SOFT_HLUTNM = "soft_lutpair941" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[5]_INST_0 
       (.I0(Q[42]),
        .I1(my_empty[4]),
        .I2(mem_out[48]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ));
  (* SOFT_HLUTNM = "soft_lutpair960" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[64]_INST_0 
       (.I0(Q[3]),
        .I1(my_empty_inst_rep__3_n_0),
        .I2(mem_out[9]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ));
  (* SOFT_HLUTNM = "soft_lutpair970" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[65]_INST_0 
       (.I0(Q[11]),
        .I1(my_empty_inst_rep__3_n_0),
        .I2(mem_out[17]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ));
  (* SOFT_HLUTNM = "soft_lutpair965" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[66]_INST_0 
       (.I0(Q[19]),
        .I1(my_empty_inst_rep__3_n_0),
        .I2(mem_out[25]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ));
  (* SOFT_HLUTNM = "soft_lutpair958" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[67]_INST_0 
       (.I0(Q[27]),
        .I1(my_empty_inst_rep__3_n_0),
        .I2(mem_out[33]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ));
  (* SOFT_HLUTNM = "soft_lutpair966" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[68]_INST_0 
       (.I0(Q[35]),
        .I1(my_empty[4]),
        .I2(mem_out[41]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ));
  (* SOFT_HLUTNM = "soft_lutpair964" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[69]_INST_0 
       (.I0(Q[43]),
        .I1(my_empty[4]),
        .I2(mem_out[49]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ));
  (* SOFT_HLUTNM = "soft_lutpair940" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[6]_INST_0 
       (.I0(Q[50]),
        .I1(my_empty[4]),
        .I2(mem_out[56]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ));
  (* SOFT_HLUTNM = "soft_lutpair956" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[70]_INST_0 
       (.I0(Q[51]),
        .I1(my_empty[4]),
        .I2(mem_out[57]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ));
  (* SOFT_HLUTNM = "soft_lutpair962" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[71]_INST_0 
       (.I0(Q[61]),
        .I1(my_empty[4]),
        .I2(mem_out[73]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] ));
  (* SOFT_HLUTNM = "soft_lutpair940" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[7]_INST_0 
       (.I0(Q[60]),
        .I1(my_empty[4]),
        .I2(mem_out[72]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "12" *) 
  (* ram_slice_end = "17" *) 
  RAM32M mem_reg_0_3_12_17
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[7:6]),
        .DIB(Q[9:8]),
        .DIC(Q[11:10]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[13:12]),
        .DOB(mem_out[15:14]),
        .DOC(mem_out[17:16]),
        .DOD(NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "18" *) 
  (* ram_slice_end = "23" *) 
  RAM32M mem_reg_0_3_18_23
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[13:12]),
        .DIB(Q[15:14]),
        .DIC(Q[17:16]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[19:18]),
        .DOB(mem_out[21:20]),
        .DOC(mem_out[23:22]),
        .DOD(NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "24" *) 
  (* ram_slice_end = "29" *) 
  RAM32M mem_reg_0_3_24_29
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[19:18]),
        .DIB(Q[21:20]),
        .DIC(Q[23:22]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[25:24]),
        .DOB(mem_out[27:26]),
        .DOC(mem_out[29:28]),
        .DOD(NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "30" *) 
  (* ram_slice_end = "35" *) 
  RAM32M mem_reg_0_3_30_35
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[25:24]),
        .DIB(Q[27:26]),
        .DIC(Q[29:28]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[31:30]),
        .DOB(mem_out[33:32]),
        .DOC(mem_out[35:34]),
        .DOD(NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "36" *) 
  (* ram_slice_end = "41" *) 
  RAM32M mem_reg_0_3_36_41
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[31:30]),
        .DIB(Q[33:32]),
        .DIC(Q[35:34]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[37:36]),
        .DOB(mem_out[39:38]),
        .DOC(mem_out[41:40]),
        .DOD(NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "42" *) 
  (* ram_slice_end = "47" *) 
  RAM32M mem_reg_0_3_42_47
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[37:36]),
        .DIB(Q[39:38]),
        .DIC(Q[41:40]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[43:42]),
        .DOB(mem_out[45:44]),
        .DOC(mem_out[47:46]),
        .DOD(NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "48" *) 
  (* ram_slice_end = "53" *) 
  RAM32M mem_reg_0_3_48_53
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[43:42]),
        .DIB(Q[45:44]),
        .DIC(Q[47:46]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[49:48]),
        .DOB(mem_out[51:50]),
        .DOC(mem_out[53:52]),
        .DOD(NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "54" *) 
  (* ram_slice_end = "59" *) 
  RAM32M mem_reg_0_3_54_59
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[49:48]),
        .DIB(Q[51:50]),
        .DIC(Q[53:52]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[55:54]),
        .DOB(mem_out[57:56]),
        .DOC(mem_out[59:58]),
        .DOD(NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "60" *) 
  (* ram_slice_end = "65" *) 
  RAM32M mem_reg_0_3_60_65
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[55:54]),
        .DIB(Q[57:56]),
        .DIC(Q[59:58]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[61:60]),
        .DOB(mem_out[63:62]),
        .DOC({mem_reg_0_3_60_65_n_4,mem_reg_0_3_60_65_n_5}),
        .DOD(NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "6" *) 
  (* ram_slice_end = "11" *) 
  RAM32M mem_reg_0_3_6_11
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[1:0]),
        .DIB(Q[3:2]),
        .DIC(Q[5:4]),
        .DID({1'b0,1'b0}),
        .DOA({mem_reg_0_3_6_11_n_0,mem_reg_0_3_6_11_n_1}),
        .DOB(mem_out[9:8]),
        .DOC(mem_out[11:10]),
        .DOD(NLW_mem_reg_0_3_6_11_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_reg[1]_0 ),
        .WE(wr_en));
  LUT4 #(
    .INIT(16'h0151)) 
    mem_reg_0_3_6_11_i_1
       (.I0(\my_full_reg[1]_0 ),
        .I1(my_full[0]),
        .I2(\my_full_reg[1]_1 ),
        .I3(my_empty[2]),
        .O(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "72" *) 
  (* ram_slice_end = "77" *) 
  RAM32M mem_reg_0_3_72_77
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[61:60]),
        .DIB(Q[63:62]),
        .DIC(Q[65:64]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[73:72]),
        .DOB(mem_out[75:74]),
        .DOC(mem_out[77:76]),
        .DOD(NLW_mem_reg_0_3_72_77_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "78" *) 
  (* ram_slice_end = "79" *) 
  RAM32M mem_reg_0_3_78_79
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[67:66]),
        .DIB({1'b0,1'b0}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[79:78]),
        .DOB(NLW_mem_reg_0_3_78_79_DOB_UNCONNECTED[1:0]),
        .DOC(NLW_mem_reg_0_3_78_79_DOC_UNCONNECTED[1:0]),
        .DOD(NLW_mem_reg_0_3_78_79_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_reg[1]_0 ),
        .WE(wr_en));
  LUT4 #(
    .INIT(16'h0018)) 
    \my_empty[4]_i_1 
       (.I0(\my_full_reg[1]_1 ),
        .I1(\my_full_reg[1]_0 ),
        .I2(my_empty[1]),
        .I3(my_full[1]),
        .O(\my_empty[4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00411400)) 
    \my_empty[4]_i_2__3 
       (.I0(my_empty[1]),
        .I1(wr_ptr[1]),
        .I2(rd_ptr[1]),
        .I3(rd_ptr[0]),
        .I4(wr_ptr[0]),
        .O(\my_empty[4]_i_2__3_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    my_empty_inst__15
       (.I0(\my_empty_reg[4]_rep_n_0 ),
        .O(my_empty[4]));
  (* SOFT_HLUTNM = "soft_lutpair971" *) 
  LUT1 #(
    .INIT(2'h2)) 
    my_empty_inst__16
       (.I0(\my_empty_reg[4]_0 ),
        .O(my_empty[3]));
  (* SOFT_HLUTNM = "soft_lutpair971" *) 
  LUT1 #(
    .INIT(2'h2)) 
    my_empty_inst__17
       (.I0(\my_empty_reg[4]_0 ),
        .O(my_empty[2]));
  LUT1 #(
    .INIT(2'h2)) 
    my_empty_inst__18
       (.I0(\my_empty_reg[4]_0 ),
        .O(my_empty[1]));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  LUT1 #(
    .INIT(2'h2)) 
    my_empty_inst_rep__3
       (.I0(\my_empty_reg[4]_rep__0_n_0 ),
        .O(my_empty_inst_rep__3_n_0));
  (* ORIG_CELL_NAME = "my_empty_reg[4]" *) 
  FDSE \my_empty_reg[4] 
       (.C(\rd_ptr_reg[1]_0 ),
        .CE(\my_empty[4]_i_1_n_0 ),
        .D(\my_empty[4]_i_2__3_n_0 ),
        .Q(\my_empty_reg[4]_0 ),
        .S(ififo_rst));
  (* ORIG_CELL_NAME = "my_empty_reg[4]" *) 
  FDSE \my_empty_reg[4]_rep 
       (.C(\rd_ptr_reg[1]_0 ),
        .CE(\my_empty[4]_i_1_n_0 ),
        .D(\my_empty[4]_i_2__3_n_0 ),
        .Q(\my_empty_reg[4]_rep_n_0 ),
        .S(ififo_rst));
  (* ORIG_CELL_NAME = "my_empty_reg[4]" *) 
  FDSE \my_empty_reg[4]_rep__0 
       (.C(\rd_ptr_reg[1]_0 ),
        .CE(\my_empty[4]_i_1_n_0 ),
        .D(\my_empty[4]_i_2__3_n_0 ),
        .Q(\my_empty_reg[4]_rep__0_n_0 ),
        .S(ififo_rst));
  LUT6 #(
    .INIT(64'hAAAAEAABAAAA2AA8)) 
    \my_full[0]_i_1__3 
       (.I0(my_full[0]),
        .I1(\my_full_reg[1]_1 ),
        .I2(\my_full_reg[1]_0 ),
        .I3(my_full[1]),
        .I4(my_empty[1]),
        .I5(\my_full[1]_i_2__3_n_0 ),
        .O(\my_full[0]_i_1__3_n_0 ));
  LUT5 #(
    .INIT(32'hF0F1F070)) 
    \my_full[1]_i_1__3 
       (.I0(\my_full_reg[1]_1 ),
        .I1(\my_full_reg[1]_0 ),
        .I2(my_full[1]),
        .I3(my_empty[1]),
        .I4(\my_full[1]_i_2__3_n_0 ),
        .O(\my_full[1]_i_1__3_n_0 ));
  LUT5 #(
    .INIT(32'h00411400)) 
    \my_full[1]_i_2__3 
       (.I0(my_full[1]),
        .I1(rd_ptr[1]),
        .I2(wr_ptr[1]),
        .I3(wr_ptr[0]),
        .I4(rd_ptr[0]),
        .O(\my_full[1]_i_2__3_n_0 ));
  FDRE \my_full_reg[0] 
       (.C(\rd_ptr_reg[1]_0 ),
        .CE(1'b1),
        .D(\my_full[0]_i_1__3_n_0 ),
        .Q(my_full[0]),
        .R(ififo_rst));
  FDRE \my_full_reg[1] 
       (.C(\rd_ptr_reg[1]_0 ),
        .CE(1'b1),
        .D(\my_full[1]_i_1__3_n_0 ),
        .Q(my_full[1]),
        .R(ififo_rst));
  (* SOFT_HLUTNM = "soft_lutpair938" *) 
  LUT3 #(
    .INIT(8'hD2)) 
    \rd_ptr[0]_i_1__3 
       (.I0(\my_full_reg[1]_1 ),
        .I1(my_empty[1]),
        .I2(rd_ptr[0]),
        .O(\rd_ptr[0]_i_1__3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair938" *) 
  LUT4 #(
    .INIT(16'hF708)) 
    \rd_ptr[1]_i_1__3 
       (.I0(rd_ptr[0]),
        .I1(\my_full_reg[1]_1 ),
        .I2(my_empty[1]),
        .I3(rd_ptr[1]),
        .O(\rd_ptr[1]_i_1__3_n_0 ));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[0] 
       (.C(\rd_ptr_reg[1]_0 ),
        .CE(1'b1),
        .D(\rd_ptr[0]_i_1__3_n_0 ),
        .Q(rd_ptr[0]),
        .R(ififo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[1] 
       (.C(\rd_ptr_reg[1]_0 ),
        .CE(1'b1),
        .D(\rd_ptr[1]_i_1__3_n_0 ),
        .Q(rd_ptr[1]),
        .R(ififo_rst));
  LUT4 #(
    .INIT(16'hF704)) 
    \rd_ptr_timing[0]_i_1__8 
       (.I0(rd_ptr[0]),
        .I1(\my_full_reg[1]_1 ),
        .I2(my_empty[1]),
        .I3(rd_ptr_timing[0]),
        .O(\rd_ptr_timing[0]_i_1__8_n_0 ));
  LUT5 #(
    .INIT(32'hFF6F0060)) 
    \rd_ptr_timing[1]_i_1__8 
       (.I0(rd_ptr[0]),
        .I1(rd_ptr[1]),
        .I2(\my_full_reg[1]_1 ),
        .I3(my_empty[1]),
        .I4(rd_ptr_timing[1]),
        .O(\rd_ptr_timing[1]_i_1__8_n_0 ));
  (* KEEP = "yes" *) 
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_timing_reg[0] 
       (.C(\rd_ptr_reg[1]_0 ),
        .CE(1'b1),
        .D(\rd_ptr_timing[0]_i_1__8_n_0 ),
        .Q(rd_ptr_timing[0]),
        .R(ififo_rst));
  (* KEEP = "yes" *) 
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_timing_reg[1] 
       (.C(\rd_ptr_reg[1]_0 ),
        .CE(1'b1),
        .D(\rd_ptr_timing[1]_i_1__8_n_0 ),
        .Q(rd_ptr_timing[1]),
        .R(ififo_rst));
  LUT5 #(
    .INIT(32'hFECE0131)) 
    \wr_ptr[0]_i_1__8 
       (.I0(my_full[1]),
        .I1(\my_full_reg[1]_0 ),
        .I2(\my_full_reg[1]_1 ),
        .I3(my_empty[1]),
        .I4(wr_ptr[0]),
        .O(\wr_ptr[0]_i_1__8_n_0 ));
  LUT6 #(
    .INIT(64'hFFFDF5FD00020A02)) 
    \wr_ptr[1]_i_1__8 
       (.I0(wr_ptr[0]),
        .I1(my_full[1]),
        .I2(\my_full_reg[1]_0 ),
        .I3(\my_full_reg[1]_1 ),
        .I4(my_empty[1]),
        .I5(wr_ptr[1]),
        .O(\wr_ptr[1]_i_1__8_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \wr_ptr[1]_i_5 
       (.I0(\my_full_reg[1]_0 ),
        .I1(my_empty[3]),
        .O(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[0] 
       (.C(\rd_ptr_reg[1]_0 ),
        .CE(1'b1),
        .D(\wr_ptr[0]_i_1__8_n_0 ),
        .Q(wr_ptr[0]),
        .R(ififo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[1] 
       (.C(\rd_ptr_reg[1]_0 ),
        .CE(1'b1),
        .D(\wr_ptr[1]_i_1__8_n_0 ),
        .Q(wr_ptr[1]),
        .R(ififo_rst));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_if_post_fifo" *) 
module mig_mig_7series_v4_2_ddr_if_post_fifo_30
   (\my_empty_reg[4]_0 ,
    \my_empty_reg[4]_1 ,
    \rd_mux_sel_r_reg[1] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ,
    \rd_mux_sel_r_reg[1]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ,
    \rd_mux_sel_r_reg[1]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ,
    \rd_mux_sel_r_reg[1]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ,
    \rd_mux_sel_r_reg[1]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ,
    \rd_mux_sel_r_reg[1]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ,
    \rd_mux_sel_r_reg[1]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ,
    \rd_mux_sel_r_reg[1]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ,
    \rd_mux_sel_r_reg[1]_7 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ,
    \rd_mux_sel_r_reg[1]_8 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ,
    \rd_mux_sel_r_reg[1]_9 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ,
    \rd_mux_sel_r_reg[1]_10 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ,
    \rd_mux_sel_r_reg[1]_11 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ,
    \rd_mux_sel_r_reg[1]_12 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ,
    \rd_mux_sel_r_reg[1]_13 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ,
    \rd_mux_sel_r_reg[1]_14 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] ,
    \rd_mux_sel_r_reg[1]_15 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ,
    \rd_mux_sel_r_reg[1]_16 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ,
    \rd_mux_sel_r_reg[1]_17 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ,
    \rd_mux_sel_r_reg[1]_18 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ,
    \rd_mux_sel_r_reg[1]_19 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ,
    \rd_mux_sel_r_reg[1]_20 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ,
    \rd_mux_sel_r_reg[1]_21 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ,
    \rd_mux_sel_r_reg[1]_22 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] ,
    \rd_mux_sel_r_reg[1]_23 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ,
    \rd_mux_sel_r_reg[1]_24 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ,
    \rd_mux_sel_r_reg[1]_25 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ,
    \rd_mux_sel_r_reg[1]_26 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ,
    \rd_mux_sel_r_reg[1]_27 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ,
    \rd_mux_sel_r_reg[1]_28 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ,
    \rd_mux_sel_r_reg[1]_29 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ,
    \rd_mux_sel_r_reg[1]_30 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] ,
    \rd_mux_sel_r_reg[1]_31 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ,
    \rd_mux_sel_r_reg[1]_32 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ,
    \rd_mux_sel_r_reg[1]_33 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ,
    \rd_mux_sel_r_reg[1]_34 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ,
    \rd_mux_sel_r_reg[1]_35 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ,
    \rd_mux_sel_r_reg[1]_36 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ,
    \rd_mux_sel_r_reg[1]_37 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ,
    \rd_mux_sel_r_reg[1]_38 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] ,
    \rd_mux_sel_r_reg[1]_39 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ,
    \rd_mux_sel_r_reg[1]_40 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ,
    \rd_mux_sel_r_reg[1]_41 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ,
    \rd_mux_sel_r_reg[1]_42 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ,
    \rd_mux_sel_r_reg[1]_43 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ,
    \rd_mux_sel_r_reg[1]_44 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ,
    \rd_mux_sel_r_reg[1]_45 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ,
    \rd_mux_sel_r_reg[1]_46 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] ,
    \rd_mux_sel_r_reg[1]_47 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ,
    \rd_mux_sel_r_reg[1]_48 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ,
    \rd_mux_sel_r_reg[1]_49 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ,
    \rd_mux_sel_r_reg[1]_50 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ,
    \rd_mux_sel_r_reg[1]_51 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ,
    \rd_mux_sel_r_reg[1]_52 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ,
    \rd_mux_sel_r_reg[1]_53 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ,
    \rd_mux_sel_r_reg[1]_54 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] ,
    \rd_mux_sel_r_reg[1]_55 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ,
    \rd_mux_sel_r_reg[1]_56 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ,
    \rd_mux_sel_r_reg[1]_57 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ,
    \rd_mux_sel_r_reg[1]_58 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ,
    \rd_mux_sel_r_reg[1]_59 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ,
    \rd_mux_sel_r_reg[1]_60 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ,
    \rd_mux_sel_r_reg[1]_61 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ,
    \rd_mux_sel_r_reg[1]_62 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ,
    \po_stg2_wrcal_cnt_reg[1] ,
    \po_stg2_wrcal_cnt_reg[1]_0 ,
    \po_stg2_wrcal_cnt_reg[1]_1 ,
    \po_stg2_wrcal_cnt_reg[1]_2 ,
    \po_stg2_wrcal_cnt_reg[1]_3 ,
    \po_stg2_wrcal_cnt_reg[1]_4 ,
    \po_stg2_wrcal_cnt_reg[1]_5 ,
    \po_stg2_wrcal_cnt_reg[1]_6 ,
    \po_stg2_wrcal_cnt_reg[1]_7 ,
    \po_stg2_wrcal_cnt_reg[1]_8 ,
    \po_stg2_wrcal_cnt_reg[1]_9 ,
    \po_stg2_wrcal_cnt_reg[1]_10 ,
    \po_stg2_wrcal_cnt_reg[1]_11 ,
    \po_stg2_wrcal_cnt_reg[1]_12 ,
    \po_stg2_wrcal_cnt_reg[1]_13 ,
    \po_stg2_wrcal_cnt_reg[1]_14 ,
    \po_stg2_wrcal_cnt_reg[1]_15 ,
    \po_stg2_wrcal_cnt_reg[1]_16 ,
    \po_stg2_wrcal_cnt_reg[1]_17 ,
    \po_stg2_wrcal_cnt_reg[1]_18 ,
    \po_stg2_wrcal_cnt_reg[1]_19 ,
    \po_stg2_wrcal_cnt_reg[1]_20 ,
    \po_stg2_wrcal_cnt_reg[1]_21 ,
    \po_stg2_wrcal_cnt_reg[1]_22 ,
    \po_stg2_wrcal_cnt_reg[1]_23 ,
    \po_stg2_wrcal_cnt_reg[1]_24 ,
    \po_stg2_wrcal_cnt_reg[1]_25 ,
    \po_stg2_wrcal_cnt_reg[1]_26 ,
    \po_stg2_wrcal_cnt_reg[1]_27 ,
    \po_stg2_wrcal_cnt_reg[1]_28 ,
    \po_stg2_wrcal_cnt_reg[1]_29 ,
    \po_stg2_wrcal_cnt_reg[1]_30 ,
    \po_stg2_wrcal_cnt_reg[1]_31 ,
    \po_stg2_wrcal_cnt_reg[1]_32 ,
    \po_stg2_wrcal_cnt_reg[1]_33 ,
    \po_stg2_wrcal_cnt_reg[1]_34 ,
    \po_stg2_wrcal_cnt_reg[1]_35 ,
    \po_stg2_wrcal_cnt_reg[1]_36 ,
    \po_stg2_wrcal_cnt_reg[1]_37 ,
    \po_stg2_wrcal_cnt_reg[1]_38 ,
    \po_stg2_wrcal_cnt_reg[1]_39 ,
    \po_stg2_wrcal_cnt_reg[1]_40 ,
    \po_stg2_wrcal_cnt_reg[1]_41 ,
    \po_stg2_wrcal_cnt_reg[1]_42 ,
    \po_stg2_wrcal_cnt_reg[1]_43 ,
    \po_stg2_wrcal_cnt_reg[1]_44 ,
    \po_stg2_wrcal_cnt_reg[1]_45 ,
    \po_stg2_wrcal_cnt_reg[1]_46 ,
    \po_stg2_wrcal_cnt_reg[1]_47 ,
    \po_stg2_wrcal_cnt_reg[1]_48 ,
    \po_stg2_wrcal_cnt_reg[1]_49 ,
    \po_stg2_wrcal_cnt_reg[1]_50 ,
    \po_stg2_wrcal_cnt_reg[1]_51 ,
    \po_stg2_wrcal_cnt_reg[1]_52 ,
    \po_stg2_wrcal_cnt_reg[1]_53 ,
    \po_stg2_wrcal_cnt_reg[1]_54 ,
    \po_stg2_wrcal_cnt_reg[1]_55 ,
    \po_stg2_wrcal_cnt_reg[1]_56 ,
    \po_stg2_wrcal_cnt_reg[1]_57 ,
    \po_stg2_wrcal_cnt_reg[1]_58 ,
    \po_stg2_wrcal_cnt_reg[1]_59 ,
    \po_stg2_wrcal_cnt_reg[1]_60 ,
    \po_stg2_wrcal_cnt_reg[1]_61 ,
    \po_stg2_wrcal_cnt_reg[1]_62 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ,
    ififo_rst,
    \rd_ptr_reg[1]_0 ,
    \my_full_reg[1]_0 ,
    \my_full_reg[1]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ,
    \gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 ,
    \my_full_reg[1]_2 ,
    \my_full_reg[1]_3 ,
    \my_full_reg[1]_4 ,
    \my_full_reg[1]_5 ,
    \my_full_reg[1]_6 ,
    \my_full_reg[1]_7 ,
    \my_full_reg[1]_8 ,
    \my_full_reg[1]_9 ,
    \wr_ptr[1]_i_2__2 ,
    if_empty_r,
    Q);
  output \my_empty_reg[4]_0 ;
  output [0:0]\my_empty_reg[4]_1 ;
  output \rd_mux_sel_r_reg[1] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ;
  output \rd_mux_sel_r_reg[1]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ;
  output \rd_mux_sel_r_reg[1]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ;
  output \rd_mux_sel_r_reg[1]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ;
  output \rd_mux_sel_r_reg[1]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ;
  output \rd_mux_sel_r_reg[1]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ;
  output \rd_mux_sel_r_reg[1]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ;
  output \rd_mux_sel_r_reg[1]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ;
  output \rd_mux_sel_r_reg[1]_7 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ;
  output \rd_mux_sel_r_reg[1]_8 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ;
  output \rd_mux_sel_r_reg[1]_9 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ;
  output \rd_mux_sel_r_reg[1]_10 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ;
  output \rd_mux_sel_r_reg[1]_11 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ;
  output \rd_mux_sel_r_reg[1]_12 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ;
  output \rd_mux_sel_r_reg[1]_13 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ;
  output \rd_mux_sel_r_reg[1]_14 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] ;
  output \rd_mux_sel_r_reg[1]_15 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ;
  output \rd_mux_sel_r_reg[1]_16 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ;
  output \rd_mux_sel_r_reg[1]_17 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ;
  output \rd_mux_sel_r_reg[1]_18 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ;
  output \rd_mux_sel_r_reg[1]_19 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ;
  output \rd_mux_sel_r_reg[1]_20 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ;
  output \rd_mux_sel_r_reg[1]_21 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ;
  output \rd_mux_sel_r_reg[1]_22 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] ;
  output \rd_mux_sel_r_reg[1]_23 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ;
  output \rd_mux_sel_r_reg[1]_24 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ;
  output \rd_mux_sel_r_reg[1]_25 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ;
  output \rd_mux_sel_r_reg[1]_26 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ;
  output \rd_mux_sel_r_reg[1]_27 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ;
  output \rd_mux_sel_r_reg[1]_28 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ;
  output \rd_mux_sel_r_reg[1]_29 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ;
  output \rd_mux_sel_r_reg[1]_30 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] ;
  output \rd_mux_sel_r_reg[1]_31 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ;
  output \rd_mux_sel_r_reg[1]_32 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ;
  output \rd_mux_sel_r_reg[1]_33 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ;
  output \rd_mux_sel_r_reg[1]_34 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ;
  output \rd_mux_sel_r_reg[1]_35 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ;
  output \rd_mux_sel_r_reg[1]_36 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ;
  output \rd_mux_sel_r_reg[1]_37 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ;
  output \rd_mux_sel_r_reg[1]_38 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] ;
  output \rd_mux_sel_r_reg[1]_39 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ;
  output \rd_mux_sel_r_reg[1]_40 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ;
  output \rd_mux_sel_r_reg[1]_41 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ;
  output \rd_mux_sel_r_reg[1]_42 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ;
  output \rd_mux_sel_r_reg[1]_43 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ;
  output \rd_mux_sel_r_reg[1]_44 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ;
  output \rd_mux_sel_r_reg[1]_45 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ;
  output \rd_mux_sel_r_reg[1]_46 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] ;
  output \rd_mux_sel_r_reg[1]_47 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ;
  output \rd_mux_sel_r_reg[1]_48 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ;
  output \rd_mux_sel_r_reg[1]_49 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ;
  output \rd_mux_sel_r_reg[1]_50 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ;
  output \rd_mux_sel_r_reg[1]_51 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ;
  output \rd_mux_sel_r_reg[1]_52 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ;
  output \rd_mux_sel_r_reg[1]_53 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ;
  output \rd_mux_sel_r_reg[1]_54 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] ;
  output \rd_mux_sel_r_reg[1]_55 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ;
  output \rd_mux_sel_r_reg[1]_56 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ;
  output \rd_mux_sel_r_reg[1]_57 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ;
  output \rd_mux_sel_r_reg[1]_58 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ;
  output \rd_mux_sel_r_reg[1]_59 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ;
  output \rd_mux_sel_r_reg[1]_60 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ;
  output \rd_mux_sel_r_reg[1]_61 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ;
  output \rd_mux_sel_r_reg[1]_62 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ;
  output \po_stg2_wrcal_cnt_reg[1] ;
  output \po_stg2_wrcal_cnt_reg[1]_0 ;
  output \po_stg2_wrcal_cnt_reg[1]_1 ;
  output \po_stg2_wrcal_cnt_reg[1]_2 ;
  output \po_stg2_wrcal_cnt_reg[1]_3 ;
  output \po_stg2_wrcal_cnt_reg[1]_4 ;
  output \po_stg2_wrcal_cnt_reg[1]_5 ;
  output \po_stg2_wrcal_cnt_reg[1]_6 ;
  output \po_stg2_wrcal_cnt_reg[1]_7 ;
  output \po_stg2_wrcal_cnt_reg[1]_8 ;
  output \po_stg2_wrcal_cnt_reg[1]_9 ;
  output \po_stg2_wrcal_cnt_reg[1]_10 ;
  output \po_stg2_wrcal_cnt_reg[1]_11 ;
  output \po_stg2_wrcal_cnt_reg[1]_12 ;
  output \po_stg2_wrcal_cnt_reg[1]_13 ;
  output \po_stg2_wrcal_cnt_reg[1]_14 ;
  output \po_stg2_wrcal_cnt_reg[1]_15 ;
  output \po_stg2_wrcal_cnt_reg[1]_16 ;
  output \po_stg2_wrcal_cnt_reg[1]_17 ;
  output \po_stg2_wrcal_cnt_reg[1]_18 ;
  output \po_stg2_wrcal_cnt_reg[1]_19 ;
  output \po_stg2_wrcal_cnt_reg[1]_20 ;
  output \po_stg2_wrcal_cnt_reg[1]_21 ;
  output \po_stg2_wrcal_cnt_reg[1]_22 ;
  output \po_stg2_wrcal_cnt_reg[1]_23 ;
  output \po_stg2_wrcal_cnt_reg[1]_24 ;
  output \po_stg2_wrcal_cnt_reg[1]_25 ;
  output \po_stg2_wrcal_cnt_reg[1]_26 ;
  output \po_stg2_wrcal_cnt_reg[1]_27 ;
  output \po_stg2_wrcal_cnt_reg[1]_28 ;
  output \po_stg2_wrcal_cnt_reg[1]_29 ;
  output \po_stg2_wrcal_cnt_reg[1]_30 ;
  output \po_stg2_wrcal_cnt_reg[1]_31 ;
  output \po_stg2_wrcal_cnt_reg[1]_32 ;
  output \po_stg2_wrcal_cnt_reg[1]_33 ;
  output \po_stg2_wrcal_cnt_reg[1]_34 ;
  output \po_stg2_wrcal_cnt_reg[1]_35 ;
  output \po_stg2_wrcal_cnt_reg[1]_36 ;
  output \po_stg2_wrcal_cnt_reg[1]_37 ;
  output \po_stg2_wrcal_cnt_reg[1]_38 ;
  output \po_stg2_wrcal_cnt_reg[1]_39 ;
  output \po_stg2_wrcal_cnt_reg[1]_40 ;
  output \po_stg2_wrcal_cnt_reg[1]_41 ;
  output \po_stg2_wrcal_cnt_reg[1]_42 ;
  output \po_stg2_wrcal_cnt_reg[1]_43 ;
  output \po_stg2_wrcal_cnt_reg[1]_44 ;
  output \po_stg2_wrcal_cnt_reg[1]_45 ;
  output \po_stg2_wrcal_cnt_reg[1]_46 ;
  output \po_stg2_wrcal_cnt_reg[1]_47 ;
  output \po_stg2_wrcal_cnt_reg[1]_48 ;
  output \po_stg2_wrcal_cnt_reg[1]_49 ;
  output \po_stg2_wrcal_cnt_reg[1]_50 ;
  output \po_stg2_wrcal_cnt_reg[1]_51 ;
  output \po_stg2_wrcal_cnt_reg[1]_52 ;
  output \po_stg2_wrcal_cnt_reg[1]_53 ;
  output \po_stg2_wrcal_cnt_reg[1]_54 ;
  output \po_stg2_wrcal_cnt_reg[1]_55 ;
  output \po_stg2_wrcal_cnt_reg[1]_56 ;
  output \po_stg2_wrcal_cnt_reg[1]_57 ;
  output \po_stg2_wrcal_cnt_reg[1]_58 ;
  output \po_stg2_wrcal_cnt_reg[1]_59 ;
  output \po_stg2_wrcal_cnt_reg[1]_60 ;
  output \po_stg2_wrcal_cnt_reg[1]_61 ;
  output \po_stg2_wrcal_cnt_reg[1]_62 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;
  input ififo_rst;
  input \rd_ptr_reg[1]_0 ;
  input \my_full_reg[1]_0 ;
  input \my_full_reg[1]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;
  input [1:0]\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_1 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 ;
  input [1:0]\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 ;
  input \my_full_reg[1]_2 ;
  input \my_full_reg[1]_3 ;
  input \my_full_reg[1]_4 ;
  input \my_full_reg[1]_5 ;
  input \my_full_reg[1]_6 ;
  input \my_full_reg[1]_7 ;
  input \my_full_reg[1]_8 ;
  input \my_full_reg[1]_9 ;
  input [0:0]\wr_ptr[1]_i_2__2 ;
  input [0:0]if_empty_r;
  input [67:0]Q;

  wire [67:0]Q;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ;
  wire [1:0]\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_1 ;
  wire [1:0]\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 ;
  wire [0:0]if_empty_r;
  wire ififo_rst;
  wire [79:16]mem_out;
  wire mem_reg_0_3_12_17_n_0;
  wire mem_reg_0_3_12_17_n_1;
  wire mem_reg_0_3_12_17_n_2;
  wire mem_reg_0_3_12_17_n_3;
  wire [4:1]my_empty;
  wire \my_empty[4]_i_1__6_n_0 ;
  wire \my_empty[4]_i_2__2_n_0 ;
  wire my_empty_inst_rep__2_n_0;
  wire \my_empty_reg[4]_0 ;
  wire [0:0]\my_empty_reg[4]_1 ;
  wire \my_empty_reg[4]_rep__0_n_0 ;
  wire \my_empty_reg[4]_rep_n_0 ;
  wire [1:0]my_full;
  wire \my_full[0]_i_1__2_n_0 ;
  wire \my_full[1]_i_1__2_n_0 ;
  wire \my_full[1]_i_2__2_n_0 ;
  wire \my_full_reg[1]_0 ;
  wire \my_full_reg[1]_1 ;
  wire \my_full_reg[1]_2 ;
  wire \my_full_reg[1]_3 ;
  wire \my_full_reg[1]_4 ;
  wire \my_full_reg[1]_5 ;
  wire \my_full_reg[1]_6 ;
  wire \my_full_reg[1]_7 ;
  wire \my_full_reg[1]_8 ;
  wire \my_full_reg[1]_9 ;
  wire \po_stg2_wrcal_cnt_reg[1] ;
  wire \po_stg2_wrcal_cnt_reg[1]_0 ;
  wire \po_stg2_wrcal_cnt_reg[1]_1 ;
  wire \po_stg2_wrcal_cnt_reg[1]_10 ;
  wire \po_stg2_wrcal_cnt_reg[1]_11 ;
  wire \po_stg2_wrcal_cnt_reg[1]_12 ;
  wire \po_stg2_wrcal_cnt_reg[1]_13 ;
  wire \po_stg2_wrcal_cnt_reg[1]_14 ;
  wire \po_stg2_wrcal_cnt_reg[1]_15 ;
  wire \po_stg2_wrcal_cnt_reg[1]_16 ;
  wire \po_stg2_wrcal_cnt_reg[1]_17 ;
  wire \po_stg2_wrcal_cnt_reg[1]_18 ;
  wire \po_stg2_wrcal_cnt_reg[1]_19 ;
  wire \po_stg2_wrcal_cnt_reg[1]_2 ;
  wire \po_stg2_wrcal_cnt_reg[1]_20 ;
  wire \po_stg2_wrcal_cnt_reg[1]_21 ;
  wire \po_stg2_wrcal_cnt_reg[1]_22 ;
  wire \po_stg2_wrcal_cnt_reg[1]_23 ;
  wire \po_stg2_wrcal_cnt_reg[1]_24 ;
  wire \po_stg2_wrcal_cnt_reg[1]_25 ;
  wire \po_stg2_wrcal_cnt_reg[1]_26 ;
  wire \po_stg2_wrcal_cnt_reg[1]_27 ;
  wire \po_stg2_wrcal_cnt_reg[1]_28 ;
  wire \po_stg2_wrcal_cnt_reg[1]_29 ;
  wire \po_stg2_wrcal_cnt_reg[1]_3 ;
  wire \po_stg2_wrcal_cnt_reg[1]_30 ;
  wire \po_stg2_wrcal_cnt_reg[1]_31 ;
  wire \po_stg2_wrcal_cnt_reg[1]_32 ;
  wire \po_stg2_wrcal_cnt_reg[1]_33 ;
  wire \po_stg2_wrcal_cnt_reg[1]_34 ;
  wire \po_stg2_wrcal_cnt_reg[1]_35 ;
  wire \po_stg2_wrcal_cnt_reg[1]_36 ;
  wire \po_stg2_wrcal_cnt_reg[1]_37 ;
  wire \po_stg2_wrcal_cnt_reg[1]_38 ;
  wire \po_stg2_wrcal_cnt_reg[1]_39 ;
  wire \po_stg2_wrcal_cnt_reg[1]_4 ;
  wire \po_stg2_wrcal_cnt_reg[1]_40 ;
  wire \po_stg2_wrcal_cnt_reg[1]_41 ;
  wire \po_stg2_wrcal_cnt_reg[1]_42 ;
  wire \po_stg2_wrcal_cnt_reg[1]_43 ;
  wire \po_stg2_wrcal_cnt_reg[1]_44 ;
  wire \po_stg2_wrcal_cnt_reg[1]_45 ;
  wire \po_stg2_wrcal_cnt_reg[1]_46 ;
  wire \po_stg2_wrcal_cnt_reg[1]_47 ;
  wire \po_stg2_wrcal_cnt_reg[1]_48 ;
  wire \po_stg2_wrcal_cnt_reg[1]_49 ;
  wire \po_stg2_wrcal_cnt_reg[1]_5 ;
  wire \po_stg2_wrcal_cnt_reg[1]_50 ;
  wire \po_stg2_wrcal_cnt_reg[1]_51 ;
  wire \po_stg2_wrcal_cnt_reg[1]_52 ;
  wire \po_stg2_wrcal_cnt_reg[1]_53 ;
  wire \po_stg2_wrcal_cnt_reg[1]_54 ;
  wire \po_stg2_wrcal_cnt_reg[1]_55 ;
  wire \po_stg2_wrcal_cnt_reg[1]_56 ;
  wire \po_stg2_wrcal_cnt_reg[1]_57 ;
  wire \po_stg2_wrcal_cnt_reg[1]_58 ;
  wire \po_stg2_wrcal_cnt_reg[1]_59 ;
  wire \po_stg2_wrcal_cnt_reg[1]_6 ;
  wire \po_stg2_wrcal_cnt_reg[1]_60 ;
  wire \po_stg2_wrcal_cnt_reg[1]_61 ;
  wire \po_stg2_wrcal_cnt_reg[1]_62 ;
  wire \po_stg2_wrcal_cnt_reg[1]_7 ;
  wire \po_stg2_wrcal_cnt_reg[1]_8 ;
  wire \po_stg2_wrcal_cnt_reg[1]_9 ;
  wire \rd_mux_sel_r_reg[1] ;
  wire \rd_mux_sel_r_reg[1]_0 ;
  wire \rd_mux_sel_r_reg[1]_1 ;
  wire \rd_mux_sel_r_reg[1]_10 ;
  wire \rd_mux_sel_r_reg[1]_11 ;
  wire \rd_mux_sel_r_reg[1]_12 ;
  wire \rd_mux_sel_r_reg[1]_13 ;
  wire \rd_mux_sel_r_reg[1]_14 ;
  wire \rd_mux_sel_r_reg[1]_15 ;
  wire \rd_mux_sel_r_reg[1]_16 ;
  wire \rd_mux_sel_r_reg[1]_17 ;
  wire \rd_mux_sel_r_reg[1]_18 ;
  wire \rd_mux_sel_r_reg[1]_19 ;
  wire \rd_mux_sel_r_reg[1]_2 ;
  wire \rd_mux_sel_r_reg[1]_20 ;
  wire \rd_mux_sel_r_reg[1]_21 ;
  wire \rd_mux_sel_r_reg[1]_22 ;
  wire \rd_mux_sel_r_reg[1]_23 ;
  wire \rd_mux_sel_r_reg[1]_24 ;
  wire \rd_mux_sel_r_reg[1]_25 ;
  wire \rd_mux_sel_r_reg[1]_26 ;
  wire \rd_mux_sel_r_reg[1]_27 ;
  wire \rd_mux_sel_r_reg[1]_28 ;
  wire \rd_mux_sel_r_reg[1]_29 ;
  wire \rd_mux_sel_r_reg[1]_3 ;
  wire \rd_mux_sel_r_reg[1]_30 ;
  wire \rd_mux_sel_r_reg[1]_31 ;
  wire \rd_mux_sel_r_reg[1]_32 ;
  wire \rd_mux_sel_r_reg[1]_33 ;
  wire \rd_mux_sel_r_reg[1]_34 ;
  wire \rd_mux_sel_r_reg[1]_35 ;
  wire \rd_mux_sel_r_reg[1]_36 ;
  wire \rd_mux_sel_r_reg[1]_37 ;
  wire \rd_mux_sel_r_reg[1]_38 ;
  wire \rd_mux_sel_r_reg[1]_39 ;
  wire \rd_mux_sel_r_reg[1]_4 ;
  wire \rd_mux_sel_r_reg[1]_40 ;
  wire \rd_mux_sel_r_reg[1]_41 ;
  wire \rd_mux_sel_r_reg[1]_42 ;
  wire \rd_mux_sel_r_reg[1]_43 ;
  wire \rd_mux_sel_r_reg[1]_44 ;
  wire \rd_mux_sel_r_reg[1]_45 ;
  wire \rd_mux_sel_r_reg[1]_46 ;
  wire \rd_mux_sel_r_reg[1]_47 ;
  wire \rd_mux_sel_r_reg[1]_48 ;
  wire \rd_mux_sel_r_reg[1]_49 ;
  wire \rd_mux_sel_r_reg[1]_5 ;
  wire \rd_mux_sel_r_reg[1]_50 ;
  wire \rd_mux_sel_r_reg[1]_51 ;
  wire \rd_mux_sel_r_reg[1]_52 ;
  wire \rd_mux_sel_r_reg[1]_53 ;
  wire \rd_mux_sel_r_reg[1]_54 ;
  wire \rd_mux_sel_r_reg[1]_55 ;
  wire \rd_mux_sel_r_reg[1]_56 ;
  wire \rd_mux_sel_r_reg[1]_57 ;
  wire \rd_mux_sel_r_reg[1]_58 ;
  wire \rd_mux_sel_r_reg[1]_59 ;
  wire \rd_mux_sel_r_reg[1]_6 ;
  wire \rd_mux_sel_r_reg[1]_60 ;
  wire \rd_mux_sel_r_reg[1]_61 ;
  wire \rd_mux_sel_r_reg[1]_62 ;
  wire \rd_mux_sel_r_reg[1]_7 ;
  wire \rd_mux_sel_r_reg[1]_8 ;
  wire \rd_mux_sel_r_reg[1]_9 ;
  wire [1:0]rd_ptr;
  wire \rd_ptr[0]_i_1__2_n_0 ;
  wire \rd_ptr[1]_i_1__2_n_0 ;
  wire \rd_ptr_reg[1]_0 ;
  (* RTL_KEEP = "true" *) (* syn_maxfan = "10" *) wire [1:0]rd_ptr_timing;
  wire \rd_ptr_timing[0]_i_1__6_n_0 ;
  wire \rd_ptr_timing[1]_i_1__6_n_0 ;
  (* MAX_FANOUT = "40" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire wr_en;
  wire [1:0]wr_ptr;
  wire \wr_ptr[0]_i_1__6_n_0 ;
  wire \wr_ptr[1]_i_1__6_n_0 ;
  wire [0:0]\wr_ptr[1]_i_2__2 ;
  wire \wr_ptr[1]_i_3__1_n_0 ;
  wire [1:0]NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_66_71_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_72_77_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_78_79_DOB_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_78_79_DOC_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_78_79_DOD_UNCONNECTED;

  (* SOFT_HLUTNM = "soft_lutpair846" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[120]_INST_0 
       (.I0(Q[5]),
        .I1(my_empty_inst_rep__2_n_0),
        .I2(mem_out[17]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ));
  (* SOFT_HLUTNM = "soft_lutpair845" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[121]_INST_0 
       (.I0(Q[13]),
        .I1(my_empty_inst_rep__2_n_0),
        .I2(mem_out[25]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ));
  (* SOFT_HLUTNM = "soft_lutpair836" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[122]_INST_0 
       (.I0(Q[21]),
        .I1(my_empty_inst_rep__2_n_0),
        .I2(mem_out[33]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ));
  (* SOFT_HLUTNM = "soft_lutpair842" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[123]_INST_0 
       (.I0(Q[29]),
        .I1(my_empty_inst_rep__2_n_0),
        .I2(mem_out[41]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ));
  (* SOFT_HLUTNM = "soft_lutpair843" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[124]_INST_0 
       (.I0(Q[37]),
        .I1(my_empty[4]),
        .I2(mem_out[49]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ));
  (* SOFT_HLUTNM = "soft_lutpair833" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[125]_INST_0 
       (.I0(Q[45]),
        .I1(my_empty[4]),
        .I2(mem_out[57]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ));
  (* SOFT_HLUTNM = "soft_lutpair832" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[126]_INST_0 
       (.I0(Q[53]),
        .I1(my_empty[4]),
        .I2(mem_out[65]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ));
  (* SOFT_HLUTNM = "soft_lutpair838" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[127]_INST_0 
       (.I0(Q[61]),
        .I1(my_empty[4]),
        .I2(mem_out[73]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] ));
  (* SOFT_HLUTNM = "soft_lutpair826" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[184]_INST_0 
       (.I0(Q[6]),
        .I1(my_empty_inst_rep__2_n_0),
        .I2(mem_out[18]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ));
  (* SOFT_HLUTNM = "soft_lutpair821" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[185]_INST_0 
       (.I0(Q[14]),
        .I1(my_empty_inst_rep__2_n_0),
        .I2(mem_out[26]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ));
  (* SOFT_HLUTNM = "soft_lutpair830" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[186]_INST_0 
       (.I0(Q[22]),
        .I1(my_empty_inst_rep__2_n_0),
        .I2(mem_out[34]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ));
  (* SOFT_HLUTNM = "soft_lutpair824" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[187]_INST_0 
       (.I0(Q[30]),
        .I1(my_empty_inst_rep__2_n_0),
        .I2(mem_out[42]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ));
  (* SOFT_HLUTNM = "soft_lutpair819" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[188]_INST_0 
       (.I0(Q[38]),
        .I1(my_empty[4]),
        .I2(mem_out[50]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ));
  (* SOFT_HLUTNM = "soft_lutpair828" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[189]_INST_0 
       (.I0(Q[46]),
        .I1(my_empty[4]),
        .I2(mem_out[58]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ));
  (* SOFT_HLUTNM = "soft_lutpair822" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[190]_INST_0 
       (.I0(Q[54]),
        .I1(my_empty[4]),
        .I2(mem_out[66]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ));
  (* SOFT_HLUTNM = "soft_lutpair818" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[191]_INST_0 
       (.I0(Q[62]),
        .I1(my_empty[4]),
        .I2(mem_out[74]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] ));
  (* SOFT_HLUTNM = "soft_lutpair845" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[248]_INST_0 
       (.I0(Q[7]),
        .I1(my_empty_inst_rep__2_n_0),
        .I2(mem_out[19]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ));
  (* SOFT_HLUTNM = "soft_lutpair836" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[249]_INST_0 
       (.I0(Q[15]),
        .I1(my_empty_inst_rep__2_n_0),
        .I2(mem_out[27]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ));
  (* SOFT_HLUTNM = "soft_lutpair841" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[250]_INST_0 
       (.I0(Q[23]),
        .I1(my_empty_inst_rep__2_n_0),
        .I2(mem_out[35]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ));
  (* SOFT_HLUTNM = "soft_lutpair841" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[251]_INST_0 
       (.I0(Q[31]),
        .I1(my_empty_inst_rep__2_n_0),
        .I2(mem_out[43]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ));
  (* SOFT_HLUTNM = "soft_lutpair834" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[252]_INST_0 
       (.I0(Q[39]),
        .I1(my_empty[4]),
        .I2(mem_out[51]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ));
  (* SOFT_HLUTNM = "soft_lutpair833" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[253]_INST_0 
       (.I0(Q[47]),
        .I1(my_empty[4]),
        .I2(mem_out[59]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ));
  (* SOFT_HLUTNM = "soft_lutpair839" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[254]_INST_0 
       (.I0(Q[55]),
        .I1(my_empty[4]),
        .I2(mem_out[67]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ));
  (* SOFT_HLUTNM = "soft_lutpair829" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[255]_INST_0 
       (.I0(Q[63]),
        .I1(my_empty[4]),
        .I2(mem_out[75]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] ));
  (* SOFT_HLUTNM = "soft_lutpair821" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[312]_INST_0 
       (.I0(Q[8]),
        .I1(my_empty_inst_rep__2_n_0),
        .I2(mem_out[20]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ));
  (* SOFT_HLUTNM = "soft_lutpair831" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[313]_INST_0 
       (.I0(Q[16]),
        .I1(my_empty_inst_rep__2_n_0),
        .I2(mem_out[28]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ));
  (* SOFT_HLUTNM = "soft_lutpair824" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[314]_INST_0 
       (.I0(Q[24]),
        .I1(my_empty_inst_rep__2_n_0),
        .I2(mem_out[36]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ));
  (* SOFT_HLUTNM = "soft_lutpair815" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[315]_INST_0 
       (.I0(Q[32]),
        .I1(my_empty_inst_rep__2_n_0),
        .I2(mem_out[44]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ));
  (* SOFT_HLUTNM = "soft_lutpair828" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[316]_INST_0 
       (.I0(Q[40]),
        .I1(my_empty[4]),
        .I2(mem_out[52]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ));
  (* SOFT_HLUTNM = "soft_lutpair823" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[317]_INST_0 
       (.I0(Q[48]),
        .I1(my_empty[4]),
        .I2(mem_out[60]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ));
  (* SOFT_HLUTNM = "soft_lutpair818" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[318]_INST_0 
       (.I0(Q[56]),
        .I1(my_empty[4]),
        .I2(mem_out[68]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ));
  (* SOFT_HLUTNM = "soft_lutpair827" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[319]_INST_0 
       (.I0(Q[64]),
        .I1(my_empty[4]),
        .I2(mem_out[76]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] ));
  (* SOFT_HLUTNM = "soft_lutpair837" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[376]_INST_0 
       (.I0(Q[9]),
        .I1(my_empty_inst_rep__2_n_0),
        .I2(mem_out[21]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ));
  (* SOFT_HLUTNM = "soft_lutpair844" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[377]_INST_0 
       (.I0(Q[17]),
        .I1(my_empty_inst_rep__2_n_0),
        .I2(mem_out[29]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ));
  (* SOFT_HLUTNM = "soft_lutpair844" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[378]_INST_0 
       (.I0(Q[25]),
        .I1(my_empty_inst_rep__2_n_0),
        .I2(mem_out[37]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ));
  (* SOFT_HLUTNM = "soft_lutpair835" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[379]_INST_0 
       (.I0(Q[33]),
        .I1(my_empty_inst_rep__2_n_0),
        .I2(mem_out[45]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ));
  (* SOFT_HLUTNM = "soft_lutpair843" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[380]_INST_0 
       (.I0(Q[41]),
        .I1(my_empty[4]),
        .I2(mem_out[53]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ));
  (* SOFT_HLUTNM = "soft_lutpair840" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[381]_INST_0 
       (.I0(Q[49]),
        .I1(my_empty[4]),
        .I2(mem_out[61]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ));
  (* SOFT_HLUTNM = "soft_lutpair829" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[382]_INST_0 
       (.I0(Q[57]),
        .I1(my_empty[4]),
        .I2(mem_out[69]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ));
  (* SOFT_HLUTNM = "soft_lutpair838" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[383]_INST_0 
       (.I0(Q[65]),
        .I1(my_empty[4]),
        .I2(mem_out[77]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] ));
  (* SOFT_HLUTNM = "soft_lutpair815" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[440]_INST_0 
       (.I0(Q[10]),
        .I1(my_empty_inst_rep__2_n_0),
        .I2(mem_out[22]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ));
  (* SOFT_HLUTNM = "soft_lutpair825" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[441]_INST_0 
       (.I0(Q[18]),
        .I1(my_empty_inst_rep__2_n_0),
        .I2(mem_out[30]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ));
  (* SOFT_HLUTNM = "soft_lutpair820" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[442]_INST_0 
       (.I0(Q[26]),
        .I1(my_empty_inst_rep__2_n_0),
        .I2(mem_out[38]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ));
  (* SOFT_HLUTNM = "soft_lutpair826" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[443]_INST_0 
       (.I0(Q[34]),
        .I1(my_empty_inst_rep__2_n_0),
        .I2(mem_out[46]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ));
  (* SOFT_HLUTNM = "soft_lutpair823" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[444]_INST_0 
       (.I0(Q[42]),
        .I1(my_empty[4]),
        .I2(mem_out[54]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ));
  (* SOFT_HLUTNM = "soft_lutpair819" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[445]_INST_0 
       (.I0(Q[50]),
        .I1(my_empty[4]),
        .I2(mem_out[62]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ));
  (* SOFT_HLUTNM = "soft_lutpair827" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[446]_INST_0 
       (.I0(Q[58]),
        .I1(my_empty[4]),
        .I2(mem_out[70]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ));
  (* SOFT_HLUTNM = "soft_lutpair822" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[447]_INST_0 
       (.I0(Q[66]),
        .I1(my_empty[4]),
        .I2(mem_out[78]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] ));
  (* SOFT_HLUTNM = "soft_lutpair846" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[504]_INST_0 
       (.I0(Q[11]),
        .I1(my_empty_inst_rep__2_n_0),
        .I2(mem_out[23]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ));
  (* SOFT_HLUTNM = "soft_lutpair842" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[505]_INST_0 
       (.I0(Q[19]),
        .I1(my_empty_inst_rep__2_n_0),
        .I2(mem_out[31]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ));
  (* SOFT_HLUTNM = "soft_lutpair835" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[506]_INST_0 
       (.I0(Q[27]),
        .I1(my_empty_inst_rep__2_n_0),
        .I2(mem_out[39]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ));
  (* SOFT_HLUTNM = "soft_lutpair837" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[507]_INST_0 
       (.I0(Q[35]),
        .I1(my_empty_inst_rep__2_n_0),
        .I2(mem_out[47]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ));
  (* SOFT_HLUTNM = "soft_lutpair840" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[508]_INST_0 
       (.I0(Q[43]),
        .I1(my_empty[4]),
        .I2(mem_out[55]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ));
  (* SOFT_HLUTNM = "soft_lutpair832" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[509]_INST_0 
       (.I0(Q[51]),
        .I1(my_empty[4]),
        .I2(mem_out[63]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ));
  (* SOFT_HLUTNM = "soft_lutpair839" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[510]_INST_0 
       (.I0(Q[59]),
        .I1(my_empty[4]),
        .I2(mem_out[71]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ));
  (* SOFT_HLUTNM = "soft_lutpair834" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[511]_INST_0 
       (.I0(Q[67]),
        .I1(my_empty[4]),
        .I2(mem_out[79]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ));
  (* SOFT_HLUTNM = "soft_lutpair831" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[56]_INST_0 
       (.I0(Q[4]),
        .I1(my_empty_inst_rep__2_n_0),
        .I2(mem_out[16]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ));
  (* SOFT_HLUTNM = "soft_lutpair825" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[57]_INST_0 
       (.I0(Q[12]),
        .I1(my_empty_inst_rep__2_n_0),
        .I2(mem_out[24]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ));
  (* SOFT_HLUTNM = "soft_lutpair820" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[58]_INST_0 
       (.I0(Q[20]),
        .I1(my_empty_inst_rep__2_n_0),
        .I2(mem_out[32]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ));
  (* SOFT_HLUTNM = "soft_lutpair830" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[59]_INST_0 
       (.I0(Q[28]),
        .I1(my_empty_inst_rep__2_n_0),
        .I2(mem_out[40]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ));
  (* SOFT_HLUTNM = "soft_lutpair817" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[60]_INST_0 
       (.I0(Q[36]),
        .I1(my_empty[4]),
        .I2(mem_out[48]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ));
  (* SOFT_HLUTNM = "soft_lutpair816" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[61]_INST_0 
       (.I0(Q[44]),
        .I1(my_empty[4]),
        .I2(mem_out[56]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ));
  (* SOFT_HLUTNM = "soft_lutpair817" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[62]_INST_0 
       (.I0(Q[52]),
        .I1(my_empty[4]),
        .I2(mem_out[64]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ));
  (* SOFT_HLUTNM = "soft_lutpair816" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[63]_INST_0 
       (.I0(Q[60]),
        .I1(my_empty[4]),
        .I2(mem_out[72]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[0].mux_rd_fall0_r1[0]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_1 ),
        .O(\rd_mux_sel_r_reg[1]_7 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[0].mux_rd_fall1_r1[0]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_1 ),
        .O(\rd_mux_sel_r_reg[1]_23 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[0].mux_rd_fall2_r1[0]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_1 ),
        .O(\rd_mux_sel_r_reg[1]_39 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[0].mux_rd_fall3_r1[0]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_1 ),
        .O(\rd_mux_sel_r_reg[1]_55 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[0].mux_rd_rise0_r1[0]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1 ),
        .O(\rd_mux_sel_r_reg[1] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[0].mux_rd_rise1_r1[0]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_1 ),
        .O(\rd_mux_sel_r_reg[1]_15 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[0].mux_rd_rise2_r1[0]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_1 ),
        .O(\rd_mux_sel_r_reg[1]_31 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[0].mux_rd_rise3_r1[0]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_1 ),
        .O(\rd_mux_sel_r_reg[1]_47 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[1].mux_rd_fall0_r1[1]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 ),
        .O(\rd_mux_sel_r_reg[1]_8 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[1].mux_rd_fall1_r1[1]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 ),
        .O(\rd_mux_sel_r_reg[1]_24 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[1].mux_rd_fall2_r1[1]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 ),
        .O(\rd_mux_sel_r_reg[1]_40 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[1].mux_rd_fall3_r1[1]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1 ),
        .O(\rd_mux_sel_r_reg[1]_56 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[1].mux_rd_rise0_r1[1]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1 ),
        .O(\rd_mux_sel_r_reg[1]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[1].mux_rd_rise1_r1[1]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 ),
        .O(\rd_mux_sel_r_reg[1]_16 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[1].mux_rd_rise2_r1[1]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 ),
        .O(\rd_mux_sel_r_reg[1]_32 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[1].mux_rd_rise3_r1[1]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 ),
        .O(\rd_mux_sel_r_reg[1]_48 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[2].mux_rd_fall0_r1[2]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_1 ),
        .O(\rd_mux_sel_r_reg[1]_9 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[2].mux_rd_fall1_r1[2]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_1 ),
        .O(\rd_mux_sel_r_reg[1]_25 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[2].mux_rd_fall2_r1[2]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_1 ),
        .O(\rd_mux_sel_r_reg[1]_41 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[2].mux_rd_fall3_r1[2]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_1 ),
        .O(\rd_mux_sel_r_reg[1]_57 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[2].mux_rd_rise0_r1[2]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1 ),
        .O(\rd_mux_sel_r_reg[1]_1 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[2].mux_rd_rise1_r1[2]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_1 ),
        .O(\rd_mux_sel_r_reg[1]_17 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[2].mux_rd_rise2_r1[2]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_1 ),
        .O(\rd_mux_sel_r_reg[1]_33 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[2].mux_rd_rise3_r1[2]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_1 ),
        .O(\rd_mux_sel_r_reg[1]_49 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[3].mux_rd_fall0_r1[3]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 ),
        .O(\rd_mux_sel_r_reg[1]_10 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[3].mux_rd_fall1_r1[3]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 ),
        .O(\rd_mux_sel_r_reg[1]_26 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[3].mux_rd_fall2_r1[3]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 ),
        .O(\rd_mux_sel_r_reg[1]_42 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[3].mux_rd_fall3_r1[3]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 ),
        .O(\rd_mux_sel_r_reg[1]_58 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[3].mux_rd_rise0_r1[3]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 ),
        .O(\rd_mux_sel_r_reg[1]_2 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[3].mux_rd_rise1_r1[3]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 ),
        .O(\rd_mux_sel_r_reg[1]_18 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[3].mux_rd_rise2_r1[3]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 ),
        .O(\rd_mux_sel_r_reg[1]_34 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[3].mux_rd_rise3_r1[3]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 ),
        .O(\rd_mux_sel_r_reg[1]_50 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[4].mux_rd_fall0_r1[4]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_1 ),
        .O(\rd_mux_sel_r_reg[1]_11 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[4].mux_rd_fall1_r1[4]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_1 ),
        .O(\rd_mux_sel_r_reg[1]_27 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[4].mux_rd_fall2_r1[4]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_1 ),
        .O(\rd_mux_sel_r_reg[1]_43 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[4].mux_rd_fall3_r1[4]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_1 ),
        .O(\rd_mux_sel_r_reg[1]_59 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[4].mux_rd_rise0_r1[4]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_1 ),
        .O(\rd_mux_sel_r_reg[1]_3 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[4].mux_rd_rise1_r1[4]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_1 ),
        .O(\rd_mux_sel_r_reg[1]_19 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[4].mux_rd_rise2_r1[4]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_1 ),
        .O(\rd_mux_sel_r_reg[1]_35 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[4].mux_rd_rise3_r1[4]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_1 ),
        .O(\rd_mux_sel_r_reg[1]_51 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[5].mux_rd_fall0_r1[5]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 ),
        .O(\rd_mux_sel_r_reg[1]_12 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[5].mux_rd_fall1_r1[5]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 ),
        .O(\rd_mux_sel_r_reg[1]_28 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[5].mux_rd_fall2_r1[5]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 ),
        .O(\rd_mux_sel_r_reg[1]_44 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[5].mux_rd_fall3_r1[5]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 ),
        .O(\rd_mux_sel_r_reg[1]_60 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[5].mux_rd_rise0_r1[5]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_1 ),
        .O(\rd_mux_sel_r_reg[1]_4 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[5].mux_rd_rise1_r1[5]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 ),
        .O(\rd_mux_sel_r_reg[1]_20 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[5].mux_rd_rise2_r1[5]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 ),
        .O(\rd_mux_sel_r_reg[1]_36 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[5].mux_rd_rise3_r1[5]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 ),
        .O(\rd_mux_sel_r_reg[1]_52 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[6].mux_rd_fall0_r1[6]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_1 ),
        .O(\rd_mux_sel_r_reg[1]_13 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[6].mux_rd_fall1_r1[6]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_1 ),
        .O(\rd_mux_sel_r_reg[1]_29 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[6].mux_rd_fall2_r1[6]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_1 ),
        .O(\rd_mux_sel_r_reg[1]_45 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[6].mux_rd_fall3_r1[6]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_1 ),
        .O(\rd_mux_sel_r_reg[1]_61 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[6].mux_rd_rise0_r1[6]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_1 ),
        .O(\rd_mux_sel_r_reg[1]_5 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[6].mux_rd_rise1_r1[6]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_1 ),
        .O(\rd_mux_sel_r_reg[1]_21 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[6].mux_rd_rise2_r1[6]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_1 ),
        .O(\rd_mux_sel_r_reg[1]_37 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[6].mux_rd_rise3_r1[6]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_1 ),
        .O(\rd_mux_sel_r_reg[1]_53 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[7].mux_rd_fall0_r1[7]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 ),
        .O(\rd_mux_sel_r_reg[1]_14 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[7].mux_rd_fall1_r1[7]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 ),
        .O(\rd_mux_sel_r_reg[1]_30 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[7].mux_rd_fall2_r1[7]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 ),
        .O(\rd_mux_sel_r_reg[1]_46 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[7].mux_rd_fall3_r1[7]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 ),
        .O(\rd_mux_sel_r_reg[1]_62 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[7].mux_rd_rise0_r1[7]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_1 ),
        .O(\rd_mux_sel_r_reg[1]_6 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[7].mux_rd_rise1_r1[7]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 ),
        .O(\rd_mux_sel_r_reg[1]_22 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[7].mux_rd_rise2_r1[7]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 ),
        .O(\rd_mux_sel_r_reg[1]_38 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd[7].mux_rd_rise3_r1[7]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] ),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 ),
        .O(\rd_mux_sel_r_reg[1]_54 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r[0]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_1 ),
        .O(\po_stg2_wrcal_cnt_reg[1]_15 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r[0]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_1 ),
        .O(\po_stg2_wrcal_cnt_reg[1]_55 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r[0]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_1 ),
        .O(\po_stg2_wrcal_cnt_reg[1]_31 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r[0]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_1 ),
        .O(\po_stg2_wrcal_cnt_reg[1]_7 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r[0]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1 ),
        .O(\po_stg2_wrcal_cnt_reg[1]_47 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r[0]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_1 ),
        .O(\po_stg2_wrcal_cnt_reg[1] ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r[0]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_1 ),
        .O(\po_stg2_wrcal_cnt_reg[1]_23 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r[0]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_1 ),
        .O(\po_stg2_wrcal_cnt_reg[1]_39 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r[1]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 ),
        .O(\po_stg2_wrcal_cnt_reg[1]_16 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r[1]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 ),
        .O(\po_stg2_wrcal_cnt_reg[1]_56 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r[1]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 ),
        .O(\po_stg2_wrcal_cnt_reg[1]_32 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r[1]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1 ),
        .O(\po_stg2_wrcal_cnt_reg[1]_8 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r[1]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1 ),
        .O(\po_stg2_wrcal_cnt_reg[1]_48 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r[1]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 ),
        .O(\po_stg2_wrcal_cnt_reg[1]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r[1]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 ),
        .O(\po_stg2_wrcal_cnt_reg[1]_24 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r[1]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 ),
        .O(\po_stg2_wrcal_cnt_reg[1]_40 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r[2]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_1 ),
        .O(\po_stg2_wrcal_cnt_reg[1]_17 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r[2]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_1 ),
        .O(\po_stg2_wrcal_cnt_reg[1]_57 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r[2]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_1 ),
        .O(\po_stg2_wrcal_cnt_reg[1]_33 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r[2]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_1 ),
        .O(\po_stg2_wrcal_cnt_reg[1]_9 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r[2]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1 ),
        .O(\po_stg2_wrcal_cnt_reg[1]_49 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r[2]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_1 ),
        .O(\po_stg2_wrcal_cnt_reg[1]_1 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r[2]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_1 ),
        .O(\po_stg2_wrcal_cnt_reg[1]_25 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r[2]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_1 ),
        .O(\po_stg2_wrcal_cnt_reg[1]_41 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r[3]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 ),
        .O(\po_stg2_wrcal_cnt_reg[1]_18 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r[3]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 ),
        .O(\po_stg2_wrcal_cnt_reg[1]_58 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r[3]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 ),
        .O(\po_stg2_wrcal_cnt_reg[1]_34 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r[3]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 ),
        .O(\po_stg2_wrcal_cnt_reg[1]_10 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r[3]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 ),
        .O(\po_stg2_wrcal_cnt_reg[1]_50 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r[3]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 ),
        .O(\po_stg2_wrcal_cnt_reg[1]_2 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r[3]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 ),
        .O(\po_stg2_wrcal_cnt_reg[1]_26 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r[3]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 ),
        .O(\po_stg2_wrcal_cnt_reg[1]_42 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r[4]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_1 ),
        .O(\po_stg2_wrcal_cnt_reg[1]_19 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r[4]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_1 ),
        .O(\po_stg2_wrcal_cnt_reg[1]_59 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r[4]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_1 ),
        .O(\po_stg2_wrcal_cnt_reg[1]_35 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r[4]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_1 ),
        .O(\po_stg2_wrcal_cnt_reg[1]_11 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r[4]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_1 ),
        .O(\po_stg2_wrcal_cnt_reg[1]_51 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r[4]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_1 ),
        .O(\po_stg2_wrcal_cnt_reg[1]_3 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r[4]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_1 ),
        .O(\po_stg2_wrcal_cnt_reg[1]_27 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r[4]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_1 ),
        .O(\po_stg2_wrcal_cnt_reg[1]_43 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r[5]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 ),
        .O(\po_stg2_wrcal_cnt_reg[1]_20 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r[5]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 ),
        .O(\po_stg2_wrcal_cnt_reg[1]_60 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r[5]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 ),
        .O(\po_stg2_wrcal_cnt_reg[1]_36 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r[5]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 ),
        .O(\po_stg2_wrcal_cnt_reg[1]_12 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r[5]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_1 ),
        .O(\po_stg2_wrcal_cnt_reg[1]_52 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r[5]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 ),
        .O(\po_stg2_wrcal_cnt_reg[1]_4 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r[5]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 ),
        .O(\po_stg2_wrcal_cnt_reg[1]_28 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r[5]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 ),
        .O(\po_stg2_wrcal_cnt_reg[1]_44 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r[6]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_1 ),
        .O(\po_stg2_wrcal_cnt_reg[1]_21 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r[6]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_1 ),
        .O(\po_stg2_wrcal_cnt_reg[1]_61 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r[6]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_1 ),
        .O(\po_stg2_wrcal_cnt_reg[1]_37 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r[6]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_1 ),
        .O(\po_stg2_wrcal_cnt_reg[1]_13 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r[6]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_1 ),
        .O(\po_stg2_wrcal_cnt_reg[1]_53 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r[6]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_1 ),
        .O(\po_stg2_wrcal_cnt_reg[1]_5 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r[6]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_1 ),
        .O(\po_stg2_wrcal_cnt_reg[1]_29 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r[6]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_1 ),
        .O(\po_stg2_wrcal_cnt_reg[1]_45 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r[7]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 ),
        .O(\po_stg2_wrcal_cnt_reg[1]_22 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r[7]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 ),
        .O(\po_stg2_wrcal_cnt_reg[1]_62 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r[7]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 ),
        .O(\po_stg2_wrcal_cnt_reg[1]_38 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r[7]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 ),
        .O(\po_stg2_wrcal_cnt_reg[1]_14 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r[7]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_1 ),
        .O(\po_stg2_wrcal_cnt_reg[1]_54 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r[7]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 ),
        .O(\po_stg2_wrcal_cnt_reg[1]_6 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r[7]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 ),
        .O(\po_stg2_wrcal_cnt_reg[1]_30 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r[7]_i_3 
       (.I0(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] ),
        .I1(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] ),
        .I2(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [1]),
        .I3(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ),
        .I4(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 [0]),
        .I5(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 ),
        .O(\po_stg2_wrcal_cnt_reg[1]_46 ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "12" *) 
  (* ram_slice_end = "17" *) 
  RAM32M mem_reg_0_3_12_17
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[1:0]),
        .DIB(Q[3:2]),
        .DIC(Q[5:4]),
        .DID({1'b0,1'b0}),
        .DOA({mem_reg_0_3_12_17_n_0,mem_reg_0_3_12_17_n_1}),
        .DOB({mem_reg_0_3_12_17_n_2,mem_reg_0_3_12_17_n_3}),
        .DOC(mem_out[17:16]),
        .DOD(NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_reg[1]_0 ),
        .WE(wr_en));
  LUT4 #(
    .INIT(16'h0151)) 
    mem_reg_0_3_12_17_i_1__4
       (.I0(\my_full_reg[1]_0 ),
        .I1(my_full[0]),
        .I2(\my_full_reg[1]_1 ),
        .I3(my_empty[2]),
        .O(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "18" *) 
  (* ram_slice_end = "23" *) 
  RAM32M mem_reg_0_3_18_23
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[7:6]),
        .DIB(Q[9:8]),
        .DIC(Q[11:10]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[19:18]),
        .DOB(mem_out[21:20]),
        .DOC(mem_out[23:22]),
        .DOD(NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "24" *) 
  (* ram_slice_end = "29" *) 
  RAM32M mem_reg_0_3_24_29
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[13:12]),
        .DIB(Q[15:14]),
        .DIC(Q[17:16]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[25:24]),
        .DOB(mem_out[27:26]),
        .DOC(mem_out[29:28]),
        .DOD(NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "30" *) 
  (* ram_slice_end = "35" *) 
  RAM32M mem_reg_0_3_30_35
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[19:18]),
        .DIB(Q[21:20]),
        .DIC(Q[23:22]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[31:30]),
        .DOB(mem_out[33:32]),
        .DOC(mem_out[35:34]),
        .DOD(NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "36" *) 
  (* ram_slice_end = "41" *) 
  RAM32M mem_reg_0_3_36_41
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[25:24]),
        .DIB(Q[27:26]),
        .DIC(Q[29:28]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[37:36]),
        .DOB(mem_out[39:38]),
        .DOC(mem_out[41:40]),
        .DOD(NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "42" *) 
  (* ram_slice_end = "47" *) 
  RAM32M mem_reg_0_3_42_47
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[31:30]),
        .DIB(Q[33:32]),
        .DIC(Q[35:34]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[43:42]),
        .DOB(mem_out[45:44]),
        .DOC(mem_out[47:46]),
        .DOD(NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "48" *) 
  (* ram_slice_end = "53" *) 
  RAM32M mem_reg_0_3_48_53
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[37:36]),
        .DIB(Q[39:38]),
        .DIC(Q[41:40]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[49:48]),
        .DOB(mem_out[51:50]),
        .DOC(mem_out[53:52]),
        .DOD(NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "54" *) 
  (* ram_slice_end = "59" *) 
  RAM32M mem_reg_0_3_54_59
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[43:42]),
        .DIB(Q[45:44]),
        .DIC(Q[47:46]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[55:54]),
        .DOB(mem_out[57:56]),
        .DOC(mem_out[59:58]),
        .DOD(NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "60" *) 
  (* ram_slice_end = "65" *) 
  RAM32M mem_reg_0_3_60_65
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[49:48]),
        .DIB(Q[51:50]),
        .DIC(Q[53:52]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[61:60]),
        .DOB(mem_out[63:62]),
        .DOC(mem_out[65:64]),
        .DOD(NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "66" *) 
  (* ram_slice_end = "71" *) 
  RAM32M mem_reg_0_3_66_71
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[55:54]),
        .DIB(Q[57:56]),
        .DIC(Q[59:58]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[67:66]),
        .DOB(mem_out[69:68]),
        .DOC(mem_out[71:70]),
        .DOD(NLW_mem_reg_0_3_66_71_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "72" *) 
  (* ram_slice_end = "77" *) 
  RAM32M mem_reg_0_3_72_77
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[61:60]),
        .DIB(Q[63:62]),
        .DIC(Q[65:64]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[73:72]),
        .DOB(mem_out[75:74]),
        .DOC(mem_out[77:76]),
        .DOD(NLW_mem_reg_0_3_72_77_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "78" *) 
  (* ram_slice_end = "79" *) 
  RAM32M mem_reg_0_3_78_79
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[67:66]),
        .DIB({1'b0,1'b0}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[79:78]),
        .DOB(NLW_mem_reg_0_3_78_79_DOB_UNCONNECTED[1:0]),
        .DOC(NLW_mem_reg_0_3_78_79_DOC_UNCONNECTED[1:0]),
        .DOD(NLW_mem_reg_0_3_78_79_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_reg[1]_0 ),
        .WE(wr_en));
  LUT4 #(
    .INIT(16'h0018)) 
    \my_empty[4]_i_1__6 
       (.I0(\my_full_reg[1]_1 ),
        .I1(\my_full_reg[1]_0 ),
        .I2(my_empty[1]),
        .I3(my_full[1]),
        .O(\my_empty[4]_i_1__6_n_0 ));
  LUT5 #(
    .INIT(32'h00411400)) 
    \my_empty[4]_i_2__2 
       (.I0(my_empty[1]),
        .I1(wr_ptr[1]),
        .I2(rd_ptr[1]),
        .I3(rd_ptr[0]),
        .I4(wr_ptr[0]),
        .O(\my_empty[4]_i_2__2_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    my_empty_inst__11
       (.I0(\my_empty_reg[4]_rep_n_0 ),
        .O(my_empty[4]));
  (* SOFT_HLUTNM = "soft_lutpair847" *) 
  LUT1 #(
    .INIT(2'h2)) 
    my_empty_inst__12
       (.I0(\my_empty_reg[4]_0 ),
        .O(\my_empty_reg[4]_1 ));
  LUT1 #(
    .INIT(2'h2)) 
    my_empty_inst__13
       (.I0(\my_empty_reg[4]_0 ),
        .O(my_empty[2]));
  (* SOFT_HLUTNM = "soft_lutpair847" *) 
  LUT1 #(
    .INIT(2'h2)) 
    my_empty_inst__14
       (.I0(\my_empty_reg[4]_0 ),
        .O(my_empty[1]));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  LUT1 #(
    .INIT(2'h2)) 
    my_empty_inst_rep__2
       (.I0(\my_empty_reg[4]_rep__0_n_0 ),
        .O(my_empty_inst_rep__2_n_0));
  (* ORIG_CELL_NAME = "my_empty_reg[4]" *) 
  FDSE \my_empty_reg[4] 
       (.C(\rd_ptr_reg[1]_0 ),
        .CE(\my_empty[4]_i_1__6_n_0 ),
        .D(\my_empty[4]_i_2__2_n_0 ),
        .Q(\my_empty_reg[4]_0 ),
        .S(ififo_rst));
  (* ORIG_CELL_NAME = "my_empty_reg[4]" *) 
  FDSE \my_empty_reg[4]_rep 
       (.C(\rd_ptr_reg[1]_0 ),
        .CE(\my_empty[4]_i_1__6_n_0 ),
        .D(\my_empty[4]_i_2__2_n_0 ),
        .Q(\my_empty_reg[4]_rep_n_0 ),
        .S(ififo_rst));
  (* ORIG_CELL_NAME = "my_empty_reg[4]" *) 
  FDSE \my_empty_reg[4]_rep__0 
       (.C(\rd_ptr_reg[1]_0 ),
        .CE(\my_empty[4]_i_1__6_n_0 ),
        .D(\my_empty[4]_i_2__2_n_0 ),
        .Q(\my_empty_reg[4]_rep__0_n_0 ),
        .S(ififo_rst));
  LUT6 #(
    .INIT(64'hAAAAEAABAAAA2AA8)) 
    \my_full[0]_i_1__2 
       (.I0(my_full[0]),
        .I1(\my_full_reg[1]_1 ),
        .I2(\my_full_reg[1]_0 ),
        .I3(my_full[1]),
        .I4(my_empty[1]),
        .I5(\my_full[1]_i_2__2_n_0 ),
        .O(\my_full[0]_i_1__2_n_0 ));
  LUT5 #(
    .INIT(32'hF0F1F070)) 
    \my_full[1]_i_1__2 
       (.I0(\my_full_reg[1]_1 ),
        .I1(\my_full_reg[1]_0 ),
        .I2(my_full[1]),
        .I3(my_empty[1]),
        .I4(\my_full[1]_i_2__2_n_0 ),
        .O(\my_full[1]_i_1__2_n_0 ));
  LUT5 #(
    .INIT(32'h00411400)) 
    \my_full[1]_i_2__2 
       (.I0(my_full[1]),
        .I1(rd_ptr[1]),
        .I2(wr_ptr[1]),
        .I3(wr_ptr[0]),
        .I4(rd_ptr[0]),
        .O(\my_full[1]_i_2__2_n_0 ));
  FDRE \my_full_reg[0] 
       (.C(\rd_ptr_reg[1]_0 ),
        .CE(1'b1),
        .D(\my_full[0]_i_1__2_n_0 ),
        .Q(my_full[0]),
        .R(ififo_rst));
  FDRE \my_full_reg[1] 
       (.C(\rd_ptr_reg[1]_0 ),
        .CE(1'b1),
        .D(\my_full[1]_i_1__2_n_0 ),
        .Q(my_full[1]),
        .R(ififo_rst));
  (* SOFT_HLUTNM = "soft_lutpair814" *) 
  LUT3 #(
    .INIT(8'hD2)) 
    \rd_ptr[0]_i_1__2 
       (.I0(\my_full_reg[1]_1 ),
        .I1(my_empty[1]),
        .I2(rd_ptr[0]),
        .O(\rd_ptr[0]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair814" *) 
  LUT4 #(
    .INIT(16'hF708)) 
    \rd_ptr[1]_i_1__2 
       (.I0(rd_ptr[0]),
        .I1(\my_full_reg[1]_1 ),
        .I2(my_empty[1]),
        .I3(rd_ptr[1]),
        .O(\rd_ptr[1]_i_1__2_n_0 ));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[0] 
       (.C(\rd_ptr_reg[1]_0 ),
        .CE(1'b1),
        .D(\rd_ptr[0]_i_1__2_n_0 ),
        .Q(rd_ptr[0]),
        .R(ififo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[1] 
       (.C(\rd_ptr_reg[1]_0 ),
        .CE(1'b1),
        .D(\rd_ptr[1]_i_1__2_n_0 ),
        .Q(rd_ptr[1]),
        .R(ififo_rst));
  LUT4 #(
    .INIT(16'hF704)) 
    \rd_ptr_timing[0]_i_1__6 
       (.I0(rd_ptr[0]),
        .I1(\my_full_reg[1]_1 ),
        .I2(my_empty[1]),
        .I3(rd_ptr_timing[0]),
        .O(\rd_ptr_timing[0]_i_1__6_n_0 ));
  LUT5 #(
    .INIT(32'hFF6F0060)) 
    \rd_ptr_timing[1]_i_1__6 
       (.I0(rd_ptr[0]),
        .I1(rd_ptr[1]),
        .I2(\my_full_reg[1]_1 ),
        .I3(my_empty[1]),
        .I4(rd_ptr_timing[1]),
        .O(\rd_ptr_timing[1]_i_1__6_n_0 ));
  (* KEEP = "yes" *) 
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_timing_reg[0] 
       (.C(\rd_ptr_reg[1]_0 ),
        .CE(1'b1),
        .D(\rd_ptr_timing[0]_i_1__6_n_0 ),
        .Q(rd_ptr_timing[0]),
        .R(ififo_rst));
  (* KEEP = "yes" *) 
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_timing_reg[1] 
       (.C(\rd_ptr_reg[1]_0 ),
        .CE(1'b1),
        .D(\rd_ptr_timing[1]_i_1__6_n_0 ),
        .Q(rd_ptr_timing[1]),
        .R(ififo_rst));
  LUT5 #(
    .INIT(32'hFECE0131)) 
    \wr_ptr[0]_i_1__6 
       (.I0(my_full[1]),
        .I1(\my_full_reg[1]_0 ),
        .I2(\my_full_reg[1]_1 ),
        .I3(my_empty[1]),
        .I4(wr_ptr[0]),
        .O(\wr_ptr[0]_i_1__6_n_0 ));
  LUT6 #(
    .INIT(64'hFFFDF5FD00020A02)) 
    \wr_ptr[1]_i_1__6 
       (.I0(wr_ptr[0]),
        .I1(my_full[1]),
        .I2(\my_full_reg[1]_0 ),
        .I3(\my_full_reg[1]_1 ),
        .I4(my_empty[1]),
        .I5(wr_ptr[1]),
        .O(\wr_ptr[1]_i_1__6_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \wr_ptr[1]_i_2 
       (.I0(\wr_ptr[1]_i_3__1_n_0 ),
        .I1(\my_full_reg[1]_2 ),
        .I2(\my_full_reg[1]_3 ),
        .I3(\my_full_reg[1]_4 ),
        .I4(\my_full_reg[1]_5 ),
        .I5(\my_full_reg[1]_6 ),
        .O(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \wr_ptr[1]_i_2__0 
       (.I0(\wr_ptr[1]_i_3__1_n_0 ),
        .I1(\my_full_reg[1]_2 ),
        .I2(\my_full_reg[1]_3 ),
        .I3(\my_full_reg[1]_4 ),
        .I4(\my_full_reg[1]_7 ),
        .I5(\my_full_reg[1]_8 ),
        .O(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \wr_ptr[1]_i_2__1 
       (.I0(\wr_ptr[1]_i_3__1_n_0 ),
        .I1(\my_full_reg[1]_2 ),
        .I2(\my_full_reg[1]_3 ),
        .I3(\my_full_reg[1]_4 ),
        .I4(\my_full_reg[1]_7 ),
        .I5(\my_full_reg[1]_9 ),
        .O(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair813" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \wr_ptr[1]_i_3__1 
       (.I0(\my_full_reg[1]_0 ),
        .I1(\my_empty_reg[4]_1 ),
        .O(\wr_ptr[1]_i_3__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair813" *) 
  LUT4 #(
    .INIT(16'hF888)) 
    \wr_ptr[1]_i_4 
       (.I0(\my_empty_reg[4]_1 ),
        .I1(\my_full_reg[1]_0 ),
        .I2(\wr_ptr[1]_i_2__2 ),
        .I3(if_empty_r),
        .O(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 ));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[0] 
       (.C(\rd_ptr_reg[1]_0 ),
        .CE(1'b1),
        .D(\wr_ptr[0]_i_1__6_n_0 ),
        .Q(wr_ptr[0]),
        .R(ififo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[1] 
       (.C(\rd_ptr_reg[1]_0 ),
        .CE(1'b1),
        .D(\wr_ptr[1]_i_1__6_n_0 ),
        .Q(wr_ptr[1]),
        .R(ififo_rst));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_if_post_fifo" *) 
module mig_mig_7series_v4_2_ddr_if_post_fifo_33
   (\my_empty_reg[4]_0 ,
    \my_empty_reg[4]_1 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ,
    ififo_rst,
    \rd_ptr_timing_reg[1]_0 ,
    \wr_ptr_reg[0]_0 ,
    \my_full_reg[1]_0 ,
    \wr_ptr[1]_i_2__6 ,
    if_empty_r,
    Q,
    \my_full_reg[1]_1 ,
    \my_full_reg[1]_2 ,
    \my_full_reg[1]_3 ,
    \my_full_reg[1]_4 ,
    \my_full_reg[1]_5 );
  output \my_empty_reg[4]_0 ;
  output [0:0]\my_empty_reg[4]_1 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  input ififo_rst;
  input \rd_ptr_timing_reg[1]_0 ;
  input \wr_ptr_reg[0]_0 ;
  input \my_full_reg[1]_0 ;
  input [0:0]\wr_ptr[1]_i_2__6 ;
  input [0:0]if_empty_r;
  input [67:0]Q;
  input \my_full_reg[1]_1 ;
  input \my_full_reg[1]_2 ;
  input \my_full_reg[1]_3 ;
  input \my_full_reg[1]_4 ;
  input \my_full_reg[1]_5 ;

  wire [67:0]Q;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ;
  wire [0:0]if_empty_r;
  wire ififo_rst;
  wire [79:16]mem_out;
  wire mem_reg_0_3_12_17_n_0;
  wire mem_reg_0_3_12_17_n_1;
  wire mem_reg_0_3_12_17_n_2;
  wire mem_reg_0_3_12_17_n_3;
  wire [4:1]my_empty;
  wire \my_empty[4]_i_1__5_n_0 ;
  wire \my_empty[4]_i_2__1_n_0 ;
  wire my_empty_inst_rep__1_n_0;
  wire \my_empty_reg[4]_0 ;
  wire [0:0]\my_empty_reg[4]_1 ;
  wire \my_empty_reg[4]_rep__0_n_0 ;
  wire \my_empty_reg[4]_rep_n_0 ;
  wire [1:0]my_full;
  wire \my_full[0]_i_1__1_n_0 ;
  wire \my_full[1]_i_1__1_n_0 ;
  wire \my_full[1]_i_2__1_n_0 ;
  wire \my_full_reg[1]_0 ;
  wire \my_full_reg[1]_1 ;
  wire \my_full_reg[1]_2 ;
  wire \my_full_reg[1]_3 ;
  wire \my_full_reg[1]_4 ;
  wire \my_full_reg[1]_5 ;
  wire [1:0]rd_ptr;
  wire \rd_ptr[0]_i_1__1_n_0 ;
  wire \rd_ptr[1]_i_1__1_n_0 ;
  (* RTL_KEEP = "true" *) (* syn_maxfan = "10" *) wire [1:0]rd_ptr_timing;
  wire \rd_ptr_timing[0]_i_1__4_n_0 ;
  wire \rd_ptr_timing[1]_i_1__4_n_0 ;
  wire \rd_ptr_timing_reg[1]_0 ;
  (* MAX_FANOUT = "40" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire wr_en;
  wire [1:0]wr_ptr;
  wire \wr_ptr[0]_i_1__4_n_0 ;
  wire \wr_ptr[1]_i_1__4_n_0 ;
  wire [0:0]\wr_ptr[1]_i_2__6 ;
  wire \wr_ptr[1]_i_3__0_n_0 ;
  wire \wr_ptr_reg[0]_0 ;
  wire [1:0]NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_66_71_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_72_77_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_78_79_DOB_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_78_79_DOC_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_78_79_DOD_UNCONNECTED;

  (* SOFT_HLUTNM = "soft_lutpair794" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[112]_INST_0 
       (.I0(Q[5]),
        .I1(my_empty_inst_rep__1_n_0),
        .I2(mem_out[17]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ));
  (* SOFT_HLUTNM = "soft_lutpair794" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[113]_INST_0 
       (.I0(Q[13]),
        .I1(my_empty_inst_rep__1_n_0),
        .I2(mem_out[25]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ));
  (* SOFT_HLUTNM = "soft_lutpair785" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[114]_INST_0 
       (.I0(Q[21]),
        .I1(my_empty_inst_rep__1_n_0),
        .I2(mem_out[33]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ));
  (* SOFT_HLUTNM = "soft_lutpair792" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[115]_INST_0 
       (.I0(Q[29]),
        .I1(my_empty_inst_rep__1_n_0),
        .I2(mem_out[41]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ));
  (* SOFT_HLUTNM = "soft_lutpair791" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[116]_INST_0 
       (.I0(Q[37]),
        .I1(my_empty[4]),
        .I2(mem_out[49]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ));
  (* SOFT_HLUTNM = "soft_lutpair782" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[117]_INST_0 
       (.I0(Q[45]),
        .I1(my_empty[4]),
        .I2(mem_out[57]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ));
  (* SOFT_HLUTNM = "soft_lutpair789" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[118]_INST_0 
       (.I0(Q[53]),
        .I1(my_empty[4]),
        .I2(mem_out[65]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ));
  (* SOFT_HLUTNM = "soft_lutpair787" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[119]_INST_0 
       (.I0(Q[61]),
        .I1(my_empty[4]),
        .I2(mem_out[73]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] ));
  (* SOFT_HLUTNM = "soft_lutpair775" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[176]_INST_0 
       (.I0(Q[6]),
        .I1(my_empty_inst_rep__1_n_0),
        .I2(mem_out[18]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ));
  (* SOFT_HLUTNM = "soft_lutpair770" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[177]_INST_0 
       (.I0(Q[14]),
        .I1(my_empty_inst_rep__1_n_0),
        .I2(mem_out[26]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ));
  (* SOFT_HLUTNM = "soft_lutpair778" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[178]_INST_0 
       (.I0(Q[22]),
        .I1(my_empty_inst_rep__1_n_0),
        .I2(mem_out[34]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ));
  (* SOFT_HLUTNM = "soft_lutpair773" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[179]_INST_0 
       (.I0(Q[30]),
        .I1(my_empty_inst_rep__1_n_0),
        .I2(mem_out[42]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ));
  (* SOFT_HLUTNM = "soft_lutpair768" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[180]_INST_0 
       (.I0(Q[38]),
        .I1(my_empty[4]),
        .I2(mem_out[50]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ));
  (* SOFT_HLUTNM = "soft_lutpair777" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[181]_INST_0 
       (.I0(Q[46]),
        .I1(my_empty[4]),
        .I2(mem_out[58]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ));
  (* SOFT_HLUTNM = "soft_lutpair771" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[182]_INST_0 
       (.I0(Q[54]),
        .I1(my_empty[4]),
        .I2(mem_out[66]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ));
  (* SOFT_HLUTNM = "soft_lutpair767" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[183]_INST_0 
       (.I0(Q[62]),
        .I1(my_empty[4]),
        .I2(mem_out[74]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] ));
  (* SOFT_HLUTNM = "soft_lutpair795" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[240]_INST_0 
       (.I0(Q[7]),
        .I1(my_empty_inst_rep__1_n_0),
        .I2(mem_out[19]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ));
  (* SOFT_HLUTNM = "soft_lutpair785" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[241]_INST_0 
       (.I0(Q[15]),
        .I1(my_empty_inst_rep__1_n_0),
        .I2(mem_out[27]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ));
  (* SOFT_HLUTNM = "soft_lutpair793" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[242]_INST_0 
       (.I0(Q[23]),
        .I1(my_empty_inst_rep__1_n_0),
        .I2(mem_out[35]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ));
  (* SOFT_HLUTNM = "soft_lutpair790" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[243]_INST_0 
       (.I0(Q[31]),
        .I1(my_empty_inst_rep__1_n_0),
        .I2(mem_out[43]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ));
  (* SOFT_HLUTNM = "soft_lutpair783" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[244]_INST_0 
       (.I0(Q[39]),
        .I1(my_empty[4]),
        .I2(mem_out[51]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ));
  (* SOFT_HLUTNM = "soft_lutpair782" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[245]_INST_0 
       (.I0(Q[47]),
        .I1(my_empty[4]),
        .I2(mem_out[59]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ));
  (* SOFT_HLUTNM = "soft_lutpair788" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[246]_INST_0 
       (.I0(Q[55]),
        .I1(my_empty[4]),
        .I2(mem_out[67]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ));
  (* SOFT_HLUTNM = "soft_lutpair779" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[247]_INST_0 
       (.I0(Q[63]),
        .I1(my_empty[4]),
        .I2(mem_out[75]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] ));
  (* SOFT_HLUTNM = "soft_lutpair770" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[304]_INST_0 
       (.I0(Q[8]),
        .I1(my_empty_inst_rep__1_n_0),
        .I2(mem_out[20]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ));
  (* SOFT_HLUTNM = "soft_lutpair780" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[305]_INST_0 
       (.I0(Q[16]),
        .I1(my_empty_inst_rep__1_n_0),
        .I2(mem_out[28]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ));
  (* SOFT_HLUTNM = "soft_lutpair773" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[306]_INST_0 
       (.I0(Q[24]),
        .I1(my_empty_inst_rep__1_n_0),
        .I2(mem_out[36]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ));
  (* SOFT_HLUTNM = "soft_lutpair764" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[307]_INST_0 
       (.I0(Q[32]),
        .I1(my_empty_inst_rep__1_n_0),
        .I2(mem_out[44]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ));
  (* SOFT_HLUTNM = "soft_lutpair777" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[308]_INST_0 
       (.I0(Q[40]),
        .I1(my_empty[4]),
        .I2(mem_out[52]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ));
  (* SOFT_HLUTNM = "soft_lutpair772" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[309]_INST_0 
       (.I0(Q[48]),
        .I1(my_empty[4]),
        .I2(mem_out[60]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ));
  (* SOFT_HLUTNM = "soft_lutpair767" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[310]_INST_0 
       (.I0(Q[56]),
        .I1(my_empty[4]),
        .I2(mem_out[68]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ));
  (* SOFT_HLUTNM = "soft_lutpair776" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[311]_INST_0 
       (.I0(Q[64]),
        .I1(my_empty[4]),
        .I2(mem_out[76]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] ));
  (* SOFT_HLUTNM = "soft_lutpair786" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[368]_INST_0 
       (.I0(Q[9]),
        .I1(my_empty_inst_rep__1_n_0),
        .I2(mem_out[21]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ));
  (* SOFT_HLUTNM = "soft_lutpair793" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[369]_INST_0 
       (.I0(Q[17]),
        .I1(my_empty_inst_rep__1_n_0),
        .I2(mem_out[29]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ));
  (* SOFT_HLUTNM = "soft_lutpair792" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[370]_INST_0 
       (.I0(Q[25]),
        .I1(my_empty_inst_rep__1_n_0),
        .I2(mem_out[37]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ));
  (* SOFT_HLUTNM = "soft_lutpair784" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[371]_INST_0 
       (.I0(Q[33]),
        .I1(my_empty_inst_rep__1_n_0),
        .I2(mem_out[45]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ));
  (* SOFT_HLUTNM = "soft_lutpair791" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[372]_INST_0 
       (.I0(Q[41]),
        .I1(my_empty[4]),
        .I2(mem_out[53]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ));
  (* SOFT_HLUTNM = "soft_lutpair781" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[373]_INST_0 
       (.I0(Q[49]),
        .I1(my_empty[4]),
        .I2(mem_out[61]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ));
  (* SOFT_HLUTNM = "soft_lutpair779" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[374]_INST_0 
       (.I0(Q[57]),
        .I1(my_empty[4]),
        .I2(mem_out[69]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ));
  (* SOFT_HLUTNM = "soft_lutpair787" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[375]_INST_0 
       (.I0(Q[65]),
        .I1(my_empty[4]),
        .I2(mem_out[77]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] ));
  (* SOFT_HLUTNM = "soft_lutpair764" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[432]_INST_0 
       (.I0(Q[10]),
        .I1(my_empty_inst_rep__1_n_0),
        .I2(mem_out[22]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ));
  (* SOFT_HLUTNM = "soft_lutpair774" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[433]_INST_0 
       (.I0(Q[18]),
        .I1(my_empty_inst_rep__1_n_0),
        .I2(mem_out[30]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ));
  (* SOFT_HLUTNM = "soft_lutpair769" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[434]_INST_0 
       (.I0(Q[26]),
        .I1(my_empty_inst_rep__1_n_0),
        .I2(mem_out[38]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ));
  (* SOFT_HLUTNM = "soft_lutpair775" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[435]_INST_0 
       (.I0(Q[34]),
        .I1(my_empty_inst_rep__1_n_0),
        .I2(mem_out[46]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ));
  (* SOFT_HLUTNM = "soft_lutpair772" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[436]_INST_0 
       (.I0(Q[42]),
        .I1(my_empty[4]),
        .I2(mem_out[54]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ));
  (* SOFT_HLUTNM = "soft_lutpair768" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[437]_INST_0 
       (.I0(Q[50]),
        .I1(my_empty[4]),
        .I2(mem_out[62]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ));
  (* SOFT_HLUTNM = "soft_lutpair776" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[438]_INST_0 
       (.I0(Q[58]),
        .I1(my_empty[4]),
        .I2(mem_out[70]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ));
  (* SOFT_HLUTNM = "soft_lutpair771" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[439]_INST_0 
       (.I0(Q[66]),
        .I1(my_empty[4]),
        .I2(mem_out[78]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] ));
  (* SOFT_HLUTNM = "soft_lutpair780" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[48]_INST_0 
       (.I0(Q[4]),
        .I1(my_empty_inst_rep__1_n_0),
        .I2(mem_out[16]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ));
  (* SOFT_HLUTNM = "soft_lutpair795" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[496]_INST_0 
       (.I0(Q[11]),
        .I1(my_empty_inst_rep__1_n_0),
        .I2(mem_out[23]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ));
  (* SOFT_HLUTNM = "soft_lutpair790" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[497]_INST_0 
       (.I0(Q[19]),
        .I1(my_empty_inst_rep__1_n_0),
        .I2(mem_out[31]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ));
  (* SOFT_HLUTNM = "soft_lutpair784" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[498]_INST_0 
       (.I0(Q[27]),
        .I1(my_empty_inst_rep__1_n_0),
        .I2(mem_out[39]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ));
  (* SOFT_HLUTNM = "soft_lutpair786" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[499]_INST_0 
       (.I0(Q[35]),
        .I1(my_empty_inst_rep__1_n_0),
        .I2(mem_out[47]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ));
  (* SOFT_HLUTNM = "soft_lutpair774" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[49]_INST_0 
       (.I0(Q[12]),
        .I1(my_empty_inst_rep__1_n_0),
        .I2(mem_out[24]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ));
  (* SOFT_HLUTNM = "soft_lutpair789" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[500]_INST_0 
       (.I0(Q[43]),
        .I1(my_empty[4]),
        .I2(mem_out[55]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ));
  (* SOFT_HLUTNM = "soft_lutpair781" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[501]_INST_0 
       (.I0(Q[51]),
        .I1(my_empty[4]),
        .I2(mem_out[63]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ));
  (* SOFT_HLUTNM = "soft_lutpair788" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[502]_INST_0 
       (.I0(Q[59]),
        .I1(my_empty[4]),
        .I2(mem_out[71]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ));
  (* SOFT_HLUTNM = "soft_lutpair783" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[503]_INST_0 
       (.I0(Q[67]),
        .I1(my_empty[4]),
        .I2(mem_out[79]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ));
  (* SOFT_HLUTNM = "soft_lutpair769" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[50]_INST_0 
       (.I0(Q[20]),
        .I1(my_empty_inst_rep__1_n_0),
        .I2(mem_out[32]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ));
  (* SOFT_HLUTNM = "soft_lutpair778" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[51]_INST_0 
       (.I0(Q[28]),
        .I1(my_empty_inst_rep__1_n_0),
        .I2(mem_out[40]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ));
  (* SOFT_HLUTNM = "soft_lutpair766" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[52]_INST_0 
       (.I0(Q[36]),
        .I1(my_empty[4]),
        .I2(mem_out[48]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ));
  (* SOFT_HLUTNM = "soft_lutpair765" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[53]_INST_0 
       (.I0(Q[44]),
        .I1(my_empty[4]),
        .I2(mem_out[56]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ));
  (* SOFT_HLUTNM = "soft_lutpair766" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[54]_INST_0 
       (.I0(Q[52]),
        .I1(my_empty[4]),
        .I2(mem_out[64]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ));
  (* SOFT_HLUTNM = "soft_lutpair765" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[55]_INST_0 
       (.I0(Q[60]),
        .I1(my_empty[4]),
        .I2(mem_out[72]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "12" *) 
  (* ram_slice_end = "17" *) 
  RAM32M mem_reg_0_3_12_17
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[1:0]),
        .DIB(Q[3:2]),
        .DIC(Q[5:4]),
        .DID({1'b0,1'b0}),
        .DOA({mem_reg_0_3_12_17_n_0,mem_reg_0_3_12_17_n_1}),
        .DOB({mem_reg_0_3_12_17_n_2,mem_reg_0_3_12_17_n_3}),
        .DOC(mem_out[17:16]),
        .DOD(NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_timing_reg[1]_0 ),
        .WE(wr_en));
  LUT4 #(
    .INIT(16'h0151)) 
    mem_reg_0_3_12_17_i_1__3
       (.I0(\wr_ptr_reg[0]_0 ),
        .I1(my_full[0]),
        .I2(\my_full_reg[1]_0 ),
        .I3(my_empty[2]),
        .O(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "18" *) 
  (* ram_slice_end = "23" *) 
  RAM32M mem_reg_0_3_18_23
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[7:6]),
        .DIB(Q[9:8]),
        .DIC(Q[11:10]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[19:18]),
        .DOB(mem_out[21:20]),
        .DOC(mem_out[23:22]),
        .DOD(NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_timing_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "24" *) 
  (* ram_slice_end = "29" *) 
  RAM32M mem_reg_0_3_24_29
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[13:12]),
        .DIB(Q[15:14]),
        .DIC(Q[17:16]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[25:24]),
        .DOB(mem_out[27:26]),
        .DOC(mem_out[29:28]),
        .DOD(NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_timing_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "30" *) 
  (* ram_slice_end = "35" *) 
  RAM32M mem_reg_0_3_30_35
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[19:18]),
        .DIB(Q[21:20]),
        .DIC(Q[23:22]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[31:30]),
        .DOB(mem_out[33:32]),
        .DOC(mem_out[35:34]),
        .DOD(NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_timing_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "36" *) 
  (* ram_slice_end = "41" *) 
  RAM32M mem_reg_0_3_36_41
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[25:24]),
        .DIB(Q[27:26]),
        .DIC(Q[29:28]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[37:36]),
        .DOB(mem_out[39:38]),
        .DOC(mem_out[41:40]),
        .DOD(NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_timing_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "42" *) 
  (* ram_slice_end = "47" *) 
  RAM32M mem_reg_0_3_42_47
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[31:30]),
        .DIB(Q[33:32]),
        .DIC(Q[35:34]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[43:42]),
        .DOB(mem_out[45:44]),
        .DOC(mem_out[47:46]),
        .DOD(NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_timing_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "48" *) 
  (* ram_slice_end = "53" *) 
  RAM32M mem_reg_0_3_48_53
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[37:36]),
        .DIB(Q[39:38]),
        .DIC(Q[41:40]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[49:48]),
        .DOB(mem_out[51:50]),
        .DOC(mem_out[53:52]),
        .DOD(NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_timing_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "54" *) 
  (* ram_slice_end = "59" *) 
  RAM32M mem_reg_0_3_54_59
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[43:42]),
        .DIB(Q[45:44]),
        .DIC(Q[47:46]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[55:54]),
        .DOB(mem_out[57:56]),
        .DOC(mem_out[59:58]),
        .DOD(NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_timing_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "60" *) 
  (* ram_slice_end = "65" *) 
  RAM32M mem_reg_0_3_60_65
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[49:48]),
        .DIB(Q[51:50]),
        .DIC(Q[53:52]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[61:60]),
        .DOB(mem_out[63:62]),
        .DOC(mem_out[65:64]),
        .DOD(NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_timing_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "66" *) 
  (* ram_slice_end = "71" *) 
  RAM32M mem_reg_0_3_66_71
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[55:54]),
        .DIB(Q[57:56]),
        .DIC(Q[59:58]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[67:66]),
        .DOB(mem_out[69:68]),
        .DOC(mem_out[71:70]),
        .DOD(NLW_mem_reg_0_3_66_71_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_timing_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "72" *) 
  (* ram_slice_end = "77" *) 
  RAM32M mem_reg_0_3_72_77
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[61:60]),
        .DIB(Q[63:62]),
        .DIC(Q[65:64]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[73:72]),
        .DOB(mem_out[75:74]),
        .DOC(mem_out[77:76]),
        .DOD(NLW_mem_reg_0_3_72_77_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_timing_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "78" *) 
  (* ram_slice_end = "79" *) 
  RAM32M mem_reg_0_3_78_79
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[67:66]),
        .DIB({1'b0,1'b0}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[79:78]),
        .DOB(NLW_mem_reg_0_3_78_79_DOB_UNCONNECTED[1:0]),
        .DOC(NLW_mem_reg_0_3_78_79_DOC_UNCONNECTED[1:0]),
        .DOD(NLW_mem_reg_0_3_78_79_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_timing_reg[1]_0 ),
        .WE(wr_en));
  LUT4 #(
    .INIT(16'h0018)) 
    \my_empty[4]_i_1__5 
       (.I0(\my_full_reg[1]_0 ),
        .I1(\wr_ptr_reg[0]_0 ),
        .I2(my_empty[1]),
        .I3(my_full[1]),
        .O(\my_empty[4]_i_1__5_n_0 ));
  LUT5 #(
    .INIT(32'h00411400)) 
    \my_empty[4]_i_2__1 
       (.I0(my_empty[1]),
        .I1(wr_ptr[1]),
        .I2(rd_ptr[1]),
        .I3(rd_ptr[0]),
        .I4(wr_ptr[0]),
        .O(\my_empty[4]_i_2__1_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    my_empty_inst__10
       (.I0(\my_empty_reg[4]_0 ),
        .O(my_empty[1]));
  LUT1 #(
    .INIT(2'h2)) 
    my_empty_inst__7
       (.I0(\my_empty_reg[4]_rep_n_0 ),
        .O(my_empty[4]));
  (* SOFT_HLUTNM = "soft_lutpair796" *) 
  LUT1 #(
    .INIT(2'h2)) 
    my_empty_inst__8
       (.I0(\my_empty_reg[4]_0 ),
        .O(\my_empty_reg[4]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair796" *) 
  LUT1 #(
    .INIT(2'h2)) 
    my_empty_inst__9
       (.I0(\my_empty_reg[4]_0 ),
        .O(my_empty[2]));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  LUT1 #(
    .INIT(2'h2)) 
    my_empty_inst_rep__1
       (.I0(\my_empty_reg[4]_rep__0_n_0 ),
        .O(my_empty_inst_rep__1_n_0));
  (* ORIG_CELL_NAME = "my_empty_reg[4]" *) 
  FDSE \my_empty_reg[4] 
       (.C(\rd_ptr_timing_reg[1]_0 ),
        .CE(\my_empty[4]_i_1__5_n_0 ),
        .D(\my_empty[4]_i_2__1_n_0 ),
        .Q(\my_empty_reg[4]_0 ),
        .S(ififo_rst));
  (* ORIG_CELL_NAME = "my_empty_reg[4]" *) 
  FDSE \my_empty_reg[4]_rep 
       (.C(\rd_ptr_timing_reg[1]_0 ),
        .CE(\my_empty[4]_i_1__5_n_0 ),
        .D(\my_empty[4]_i_2__1_n_0 ),
        .Q(\my_empty_reg[4]_rep_n_0 ),
        .S(ififo_rst));
  (* ORIG_CELL_NAME = "my_empty_reg[4]" *) 
  FDSE \my_empty_reg[4]_rep__0 
       (.C(\rd_ptr_timing_reg[1]_0 ),
        .CE(\my_empty[4]_i_1__5_n_0 ),
        .D(\my_empty[4]_i_2__1_n_0 ),
        .Q(\my_empty_reg[4]_rep__0_n_0 ),
        .S(ififo_rst));
  LUT6 #(
    .INIT(64'hAAAAEAABAAAA2AA8)) 
    \my_full[0]_i_1__1 
       (.I0(my_full[0]),
        .I1(\my_full_reg[1]_0 ),
        .I2(\wr_ptr_reg[0]_0 ),
        .I3(my_full[1]),
        .I4(my_empty[1]),
        .I5(\my_full[1]_i_2__1_n_0 ),
        .O(\my_full[0]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'hF0F1F070)) 
    \my_full[1]_i_1__1 
       (.I0(\my_full_reg[1]_0 ),
        .I1(\wr_ptr_reg[0]_0 ),
        .I2(my_full[1]),
        .I3(my_empty[1]),
        .I4(\my_full[1]_i_2__1_n_0 ),
        .O(\my_full[1]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'h00411400)) 
    \my_full[1]_i_2__1 
       (.I0(my_full[1]),
        .I1(rd_ptr[1]),
        .I2(wr_ptr[1]),
        .I3(wr_ptr[0]),
        .I4(rd_ptr[0]),
        .O(\my_full[1]_i_2__1_n_0 ));
  FDRE \my_full_reg[0] 
       (.C(\rd_ptr_timing_reg[1]_0 ),
        .CE(1'b1),
        .D(\my_full[0]_i_1__1_n_0 ),
        .Q(my_full[0]),
        .R(ififo_rst));
  FDRE \my_full_reg[1] 
       (.C(\rd_ptr_timing_reg[1]_0 ),
        .CE(1'b1),
        .D(\my_full[1]_i_1__1_n_0 ),
        .Q(my_full[1]),
        .R(ififo_rst));
  (* SOFT_HLUTNM = "soft_lutpair763" *) 
  LUT3 #(
    .INIT(8'hD2)) 
    \rd_ptr[0]_i_1__1 
       (.I0(\my_full_reg[1]_0 ),
        .I1(my_empty[1]),
        .I2(rd_ptr[0]),
        .O(\rd_ptr[0]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair763" *) 
  LUT4 #(
    .INIT(16'hF708)) 
    \rd_ptr[1]_i_1__1 
       (.I0(rd_ptr[0]),
        .I1(\my_full_reg[1]_0 ),
        .I2(my_empty[1]),
        .I3(rd_ptr[1]),
        .O(\rd_ptr[1]_i_1__1_n_0 ));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[0] 
       (.C(\rd_ptr_timing_reg[1]_0 ),
        .CE(1'b1),
        .D(\rd_ptr[0]_i_1__1_n_0 ),
        .Q(rd_ptr[0]),
        .R(ififo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[1] 
       (.C(\rd_ptr_timing_reg[1]_0 ),
        .CE(1'b1),
        .D(\rd_ptr[1]_i_1__1_n_0 ),
        .Q(rd_ptr[1]),
        .R(ififo_rst));
  LUT4 #(
    .INIT(16'hF704)) 
    \rd_ptr_timing[0]_i_1__4 
       (.I0(rd_ptr[0]),
        .I1(\my_full_reg[1]_0 ),
        .I2(my_empty[1]),
        .I3(rd_ptr_timing[0]),
        .O(\rd_ptr_timing[0]_i_1__4_n_0 ));
  LUT5 #(
    .INIT(32'hFF6F0060)) 
    \rd_ptr_timing[1]_i_1__4 
       (.I0(rd_ptr[0]),
        .I1(rd_ptr[1]),
        .I2(\my_full_reg[1]_0 ),
        .I3(my_empty[1]),
        .I4(rd_ptr_timing[1]),
        .O(\rd_ptr_timing[1]_i_1__4_n_0 ));
  (* KEEP = "yes" *) 
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_timing_reg[0] 
       (.C(\rd_ptr_timing_reg[1]_0 ),
        .CE(1'b1),
        .D(\rd_ptr_timing[0]_i_1__4_n_0 ),
        .Q(rd_ptr_timing[0]),
        .R(ififo_rst));
  (* KEEP = "yes" *) 
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_timing_reg[1] 
       (.C(\rd_ptr_timing_reg[1]_0 ),
        .CE(1'b1),
        .D(\rd_ptr_timing[1]_i_1__4_n_0 ),
        .Q(rd_ptr_timing[1]),
        .R(ififo_rst));
  LUT5 #(
    .INIT(32'hFECE0131)) 
    \wr_ptr[0]_i_1__4 
       (.I0(my_full[1]),
        .I1(\wr_ptr_reg[0]_0 ),
        .I2(\my_full_reg[1]_0 ),
        .I3(my_empty[1]),
        .I4(wr_ptr[0]),
        .O(\wr_ptr[0]_i_1__4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFDF5FD00020A02)) 
    \wr_ptr[1]_i_1__4 
       (.I0(wr_ptr[0]),
        .I1(my_full[1]),
        .I2(\wr_ptr_reg[0]_0 ),
        .I3(\my_full_reg[1]_0 ),
        .I4(my_empty[1]),
        .I5(wr_ptr[1]),
        .O(\wr_ptr[1]_i_1__4_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \wr_ptr[1]_i_2__2 
       (.I0(\wr_ptr[1]_i_3__0_n_0 ),
        .I1(\my_full_reg[1]_1 ),
        .I2(\my_full_reg[1]_2 ),
        .I3(\my_full_reg[1]_3 ),
        .I4(\my_full_reg[1]_4 ),
        .I5(\my_full_reg[1]_5 ),
        .O(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair762" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \wr_ptr[1]_i_3__0 
       (.I0(\wr_ptr_reg[0]_0 ),
        .I1(\my_empty_reg[4]_1 ),
        .O(\wr_ptr[1]_i_3__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair762" *) 
  LUT4 #(
    .INIT(16'hF888)) 
    \wr_ptr[1]_i_3__3 
       (.I0(\my_empty_reg[4]_1 ),
        .I1(\wr_ptr_reg[0]_0 ),
        .I2(\wr_ptr[1]_i_2__6 ),
        .I3(if_empty_r),
        .O(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[0] 
       (.C(\rd_ptr_timing_reg[1]_0 ),
        .CE(1'b1),
        .D(\wr_ptr[0]_i_1__4_n_0 ),
        .Q(wr_ptr[0]),
        .R(ififo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[1] 
       (.C(\rd_ptr_timing_reg[1]_0 ),
        .CE(1'b1),
        .D(\wr_ptr[1]_i_1__4_n_0 ),
        .Q(wr_ptr[1]),
        .R(ififo_rst));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_if_post_fifo" *) 
module mig_mig_7series_v4_2_ddr_if_post_fifo_36
   (\my_empty_reg[4]_0 ,
    \my_empty_reg[4]_1 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ,
    \rd_mux_sel_r_reg[2] ,
    \rd_mux_sel_r_reg[2]_0 ,
    \rd_mux_sel_r_reg[2]_1 ,
    \rd_mux_sel_r_reg[2]_2 ,
    \rd_mux_sel_r_reg[2]_3 ,
    \rd_mux_sel_r_reg[2]_4 ,
    \rd_mux_sel_r_reg[2]_5 ,
    \rd_mux_sel_r_reg[2]_6 ,
    \rd_mux_sel_r_reg[2]_7 ,
    \rd_mux_sel_r_reg[2]_8 ,
    \rd_mux_sel_r_reg[2]_9 ,
    \rd_mux_sel_r_reg[2]_10 ,
    \rd_mux_sel_r_reg[2]_11 ,
    \rd_mux_sel_r_reg[2]_12 ,
    \rd_mux_sel_r_reg[2]_13 ,
    \rd_mux_sel_r_reg[2]_14 ,
    \rd_mux_sel_r_reg[2]_15 ,
    \rd_mux_sel_r_reg[2]_16 ,
    \rd_mux_sel_r_reg[2]_17 ,
    \rd_mux_sel_r_reg[2]_18 ,
    \rd_mux_sel_r_reg[2]_19 ,
    \rd_mux_sel_r_reg[2]_20 ,
    \rd_mux_sel_r_reg[2]_21 ,
    \rd_mux_sel_r_reg[2]_22 ,
    \rd_mux_sel_r_reg[2]_23 ,
    \rd_mux_sel_r_reg[2]_24 ,
    \rd_mux_sel_r_reg[2]_25 ,
    \rd_mux_sel_r_reg[2]_26 ,
    \rd_mux_sel_r_reg[2]_27 ,
    \rd_mux_sel_r_reg[2]_28 ,
    \rd_mux_sel_r_reg[2]_29 ,
    \rd_mux_sel_r_reg[2]_30 ,
    \rd_mux_sel_r_reg[2]_31 ,
    \rd_mux_sel_r_reg[2]_32 ,
    \rd_mux_sel_r_reg[2]_33 ,
    \rd_mux_sel_r_reg[2]_34 ,
    \rd_mux_sel_r_reg[2]_35 ,
    \rd_mux_sel_r_reg[2]_36 ,
    \rd_mux_sel_r_reg[2]_37 ,
    \rd_mux_sel_r_reg[2]_38 ,
    \rd_mux_sel_r_reg[2]_39 ,
    \rd_mux_sel_r_reg[2]_40 ,
    \rd_mux_sel_r_reg[2]_41 ,
    \rd_mux_sel_r_reg[2]_42 ,
    \rd_mux_sel_r_reg[2]_43 ,
    \rd_mux_sel_r_reg[2]_44 ,
    \rd_mux_sel_r_reg[2]_45 ,
    \rd_mux_sel_r_reg[2]_46 ,
    \rd_mux_sel_r_reg[2]_47 ,
    \rd_mux_sel_r_reg[2]_48 ,
    \rd_mux_sel_r_reg[2]_49 ,
    \rd_mux_sel_r_reg[2]_50 ,
    \rd_mux_sel_r_reg[2]_51 ,
    \rd_mux_sel_r_reg[2]_52 ,
    \rd_mux_sel_r_reg[2]_53 ,
    \rd_mux_sel_r_reg[2]_54 ,
    \rd_mux_sel_r_reg[2]_55 ,
    \rd_mux_sel_r_reg[2]_56 ,
    \rd_mux_sel_r_reg[2]_57 ,
    \rd_mux_sel_r_reg[2]_58 ,
    \rd_mux_sel_r_reg[2]_59 ,
    \rd_mux_sel_r_reg[2]_60 ,
    \rd_mux_sel_r_reg[2]_61 ,
    \rd_mux_sel_r_reg[2]_62 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ,
    ififo_rst,
    \rd_ptr_reg[1]_0 ,
    \wr_ptr_reg[0]_0 ,
    \my_full_reg[1]_0 ,
    my_empty,
    \wr_ptr[1]_i_2__0 ,
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0] ,
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ,
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1 ,
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_2 ,
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1 ,
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2] ,
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ,
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1 ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 ,
    \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ,
    \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0 ,
    \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_1 ,
    \gen_mux_rd[5].mux_rd_rise0_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_1 ,
    \gen_mux_rd[6].mux_rd_rise0_r_reg[6] ,
    \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0 ,
    \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_1 ,
    \gen_mux_rd[7].mux_rd_rise0_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_1 ,
    \gen_mux_rd[0].mux_rd_fall0_r_reg[0] ,
    \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0 ,
    \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_1 ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 ,
    \gen_mux_rd[2].mux_rd_fall0_r_reg[2] ,
    \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0 ,
    \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_1 ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 ,
    \gen_mux_rd[4].mux_rd_fall0_r_reg[4] ,
    \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0 ,
    \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_1 ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 ,
    \gen_mux_rd[6].mux_rd_fall0_r_reg[6] ,
    \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0 ,
    \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_1 ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 ,
    \gen_mux_rd[0].mux_rd_rise1_r_reg[0] ,
    \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0 ,
    \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_1 ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 ,
    \gen_mux_rd[2].mux_rd_rise1_r_reg[2] ,
    \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0 ,
    \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_1 ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 ,
    \gen_mux_rd[4].mux_rd_rise1_r_reg[4] ,
    \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0 ,
    \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_1 ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 ,
    \gen_mux_rd[6].mux_rd_rise1_r_reg[6] ,
    \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0 ,
    \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_1 ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 ,
    \gen_mux_rd[0].mux_rd_fall1_r_reg[0] ,
    \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0 ,
    \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_1 ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 ,
    \gen_mux_rd[2].mux_rd_fall1_r_reg[2] ,
    \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0 ,
    \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_1 ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 ,
    \gen_mux_rd[4].mux_rd_fall1_r_reg[4] ,
    \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0 ,
    \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_1 ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 ,
    \gen_mux_rd[6].mux_rd_fall1_r_reg[6] ,
    \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0 ,
    \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_1 ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 ,
    \gen_mux_rd[0].mux_rd_rise2_r_reg[0] ,
    \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0 ,
    \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_1 ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 ,
    \gen_mux_rd[2].mux_rd_rise2_r_reg[2] ,
    \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0 ,
    \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_1 ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 ,
    \gen_mux_rd[4].mux_rd_rise2_r_reg[4] ,
    \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0 ,
    \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_1 ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 ,
    \gen_mux_rd[6].mux_rd_rise2_r_reg[6] ,
    \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0 ,
    \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_1 ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 ,
    \gen_mux_rd[0].mux_rd_fall2_r_reg[0] ,
    \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0 ,
    \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_1 ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 ,
    \gen_mux_rd[2].mux_rd_fall2_r_reg[2] ,
    \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0 ,
    \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_1 ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 ,
    \gen_mux_rd[4].mux_rd_fall2_r_reg[4] ,
    \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0 ,
    \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_1 ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 ,
    \gen_mux_rd[6].mux_rd_fall2_r_reg[6] ,
    \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0 ,
    \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_1 ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 ,
    \gen_mux_rd[0].mux_rd_rise3_r_reg[0] ,
    \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0 ,
    \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_1 ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 ,
    \gen_mux_rd[2].mux_rd_rise3_r_reg[2] ,
    \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0 ,
    \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_1 ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 ,
    \gen_mux_rd[4].mux_rd_rise3_r_reg[4] ,
    \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0 ,
    \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_1 ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 ,
    \gen_mux_rd[6].mux_rd_rise3_r_reg[6] ,
    \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0 ,
    \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_1 ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 ,
    \gen_mux_rd[0].mux_rd_fall3_r_reg[0] ,
    \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0 ,
    \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_1 ,
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1] ,
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1 ,
    \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ,
    \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 ,
    \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_1 ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3] ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 ,
    \gen_mux_rd[4].mux_rd_fall3_r_reg[4] ,
    \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0 ,
    \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_1 ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5] ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 ,
    \gen_mux_rd[6].mux_rd_fall3_r_reg[6] ,
    \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0 ,
    \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_1 ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7] ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 ,
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ,
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_3 ,
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_2 ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_2 ,
    \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_2 ,
    \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_2 ,
    \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_2 ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_2 ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_2 ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_2 ,
    \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_2 ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_2 ,
    \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_2 ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_2 ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_2 ,
    \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_2 ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_2 ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_2 ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_2 ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_2 ,
    \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_2 ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_2 ,
    \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_2 ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_2 ,
    \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_2 ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_2 ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_2 ,
    \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_2 ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_2 ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_2 ,
    \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_2 ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_2 ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_2 ,
    \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_2 ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_2 ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_2 ,
    \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_2 ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_2 ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_2 ,
    \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_2 ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_2 ,
    \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_2 ,
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_2 ,
    \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_2 ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_2 ,
    \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_2 ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_2 ,
    \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_2 ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_2 ,
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_3 ,
    \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_2 ,
    \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_2 ,
    \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_2 ,
    \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_2 ,
    \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_2 ,
    \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_2 ,
    \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_2 ,
    \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_2 ,
    \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_2 ,
    \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_2 ,
    \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_2 ,
    \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_2 ,
    \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_2 ,
    \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_2 ,
    Q);
  output \my_empty_reg[4]_0 ;
  output [0:0]\my_empty_reg[4]_1 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ;
  output \rd_mux_sel_r_reg[2] ;
  output \rd_mux_sel_r_reg[2]_0 ;
  output \rd_mux_sel_r_reg[2]_1 ;
  output \rd_mux_sel_r_reg[2]_2 ;
  output \rd_mux_sel_r_reg[2]_3 ;
  output \rd_mux_sel_r_reg[2]_4 ;
  output \rd_mux_sel_r_reg[2]_5 ;
  output \rd_mux_sel_r_reg[2]_6 ;
  output \rd_mux_sel_r_reg[2]_7 ;
  output \rd_mux_sel_r_reg[2]_8 ;
  output \rd_mux_sel_r_reg[2]_9 ;
  output \rd_mux_sel_r_reg[2]_10 ;
  output \rd_mux_sel_r_reg[2]_11 ;
  output \rd_mux_sel_r_reg[2]_12 ;
  output \rd_mux_sel_r_reg[2]_13 ;
  output \rd_mux_sel_r_reg[2]_14 ;
  output \rd_mux_sel_r_reg[2]_15 ;
  output \rd_mux_sel_r_reg[2]_16 ;
  output \rd_mux_sel_r_reg[2]_17 ;
  output \rd_mux_sel_r_reg[2]_18 ;
  output \rd_mux_sel_r_reg[2]_19 ;
  output \rd_mux_sel_r_reg[2]_20 ;
  output \rd_mux_sel_r_reg[2]_21 ;
  output \rd_mux_sel_r_reg[2]_22 ;
  output \rd_mux_sel_r_reg[2]_23 ;
  output \rd_mux_sel_r_reg[2]_24 ;
  output \rd_mux_sel_r_reg[2]_25 ;
  output \rd_mux_sel_r_reg[2]_26 ;
  output \rd_mux_sel_r_reg[2]_27 ;
  output \rd_mux_sel_r_reg[2]_28 ;
  output \rd_mux_sel_r_reg[2]_29 ;
  output \rd_mux_sel_r_reg[2]_30 ;
  output \rd_mux_sel_r_reg[2]_31 ;
  output \rd_mux_sel_r_reg[2]_32 ;
  output \rd_mux_sel_r_reg[2]_33 ;
  output \rd_mux_sel_r_reg[2]_34 ;
  output \rd_mux_sel_r_reg[2]_35 ;
  output \rd_mux_sel_r_reg[2]_36 ;
  output \rd_mux_sel_r_reg[2]_37 ;
  output \rd_mux_sel_r_reg[2]_38 ;
  output \rd_mux_sel_r_reg[2]_39 ;
  output \rd_mux_sel_r_reg[2]_40 ;
  output \rd_mux_sel_r_reg[2]_41 ;
  output \rd_mux_sel_r_reg[2]_42 ;
  output \rd_mux_sel_r_reg[2]_43 ;
  output \rd_mux_sel_r_reg[2]_44 ;
  output \rd_mux_sel_r_reg[2]_45 ;
  output \rd_mux_sel_r_reg[2]_46 ;
  output \rd_mux_sel_r_reg[2]_47 ;
  output \rd_mux_sel_r_reg[2]_48 ;
  output \rd_mux_sel_r_reg[2]_49 ;
  output \rd_mux_sel_r_reg[2]_50 ;
  output \rd_mux_sel_r_reg[2]_51 ;
  output \rd_mux_sel_r_reg[2]_52 ;
  output \rd_mux_sel_r_reg[2]_53 ;
  output \rd_mux_sel_r_reg[2]_54 ;
  output \rd_mux_sel_r_reg[2]_55 ;
  output \rd_mux_sel_r_reg[2]_56 ;
  output \rd_mux_sel_r_reg[2]_57 ;
  output \rd_mux_sel_r_reg[2]_58 ;
  output \rd_mux_sel_r_reg[2]_59 ;
  output \rd_mux_sel_r_reg[2]_60 ;
  output \rd_mux_sel_r_reg[2]_61 ;
  output \rd_mux_sel_r_reg[2]_62 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  input ififo_rst;
  input \rd_ptr_reg[1]_0 ;
  input \wr_ptr_reg[0]_0 ;
  input \my_full_reg[1]_0 ;
  input [0:0]my_empty;
  input \wr_ptr[1]_i_2__0 ;
  input [1:0]\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;
  input \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ;
  input \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1 ;
  input \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_2 ;
  input \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;
  input \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ;
  input \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1 ;
  input \gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;
  input \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ;
  input \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1 ;
  input \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  input \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ;
  input \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 ;
  input \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;
  input \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0 ;
  input \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_1 ;
  input \gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;
  input \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0 ;
  input \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_1 ;
  input \gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;
  input \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0 ;
  input \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_1 ;
  input \gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;
  input \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0 ;
  input \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_1 ;
  input \gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;
  input \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0 ;
  input \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_1 ;
  input \gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  input \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ;
  input \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 ;
  input \gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;
  input \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0 ;
  input \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_1 ;
  input \gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  input \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ;
  input \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 ;
  input \gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;
  input \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0 ;
  input \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_1 ;
  input \gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  input \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ;
  input \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 ;
  input \gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;
  input \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0 ;
  input \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_1 ;
  input \gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  input \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ;
  input \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 ;
  input \gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;
  input \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0 ;
  input \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_1 ;
  input \gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  input \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ;
  input \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 ;
  input \gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;
  input \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0 ;
  input \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_1 ;
  input \gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  input \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ;
  input \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 ;
  input \gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;
  input \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0 ;
  input \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_1 ;
  input \gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  input \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ;
  input \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 ;
  input \gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;
  input \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0 ;
  input \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_1 ;
  input \gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  input \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ;
  input \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 ;
  input \gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;
  input \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0 ;
  input \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_1 ;
  input \gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  input \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ;
  input \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 ;
  input \gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;
  input \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0 ;
  input \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_1 ;
  input \gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  input \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ;
  input \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 ;
  input \gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;
  input \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0 ;
  input \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_1 ;
  input \gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  input \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ;
  input \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 ;
  input \gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;
  input \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0 ;
  input \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_1 ;
  input \gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  input \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ;
  input \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 ;
  input \gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;
  input \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0 ;
  input \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_1 ;
  input \gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  input \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ;
  input \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 ;
  input \gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;
  input \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0 ;
  input \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_1 ;
  input \gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  input \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ;
  input \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 ;
  input \gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;
  input \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0 ;
  input \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_1 ;
  input \gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  input \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ;
  input \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 ;
  input \gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;
  input \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0 ;
  input \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_1 ;
  input \gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  input \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ;
  input \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 ;
  input \gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;
  input \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0 ;
  input \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_1 ;
  input \gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  input \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ;
  input \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 ;
  input \gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;
  input \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0 ;
  input \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_1 ;
  input \gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  input \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ;
  input \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 ;
  input \gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;
  input \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0 ;
  input \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_1 ;
  input \gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  input \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ;
  input \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 ;
  input \gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;
  input \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0 ;
  input \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_1 ;
  input \gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  input \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ;
  input \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 ;
  input \gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;
  input \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0 ;
  input \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_1 ;
  input \gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  input \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ;
  input \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 ;
  input \gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;
  input \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0 ;
  input \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_1 ;
  input \gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  input \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ;
  input \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 ;
  input \gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;
  input \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0 ;
  input \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_1 ;
  input \gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  input \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ;
  input \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 ;
  input \gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;
  input \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0 ;
  input \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_1 ;
  input \gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  input \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ;
  input \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 ;
  input \gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;
  input \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0 ;
  input \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_1 ;
  input \gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  input \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ;
  input \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1 ;
  input \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  input \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 ;
  input \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_1 ;
  input \gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  input \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ;
  input \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 ;
  input \gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;
  input \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0 ;
  input \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_1 ;
  input \gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  input \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ;
  input \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 ;
  input \gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;
  input \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0 ;
  input \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_1 ;
  input \gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  input \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ;
  input \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 ;
  input \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ;
  input \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_3 ;
  input \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_2 ;
  input \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_2 ;
  input \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_2 ;
  input \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_2 ;
  input \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_2 ;
  input \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_2 ;
  input \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_2 ;
  input \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_2 ;
  input \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_2 ;
  input \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_2 ;
  input \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 ;
  input \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_2 ;
  input \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_2 ;
  input \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_2 ;
  input \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_2 ;
  input \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_2 ;
  input \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_2 ;
  input \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_2 ;
  input \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_2 ;
  input \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_2 ;
  input \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_2 ;
  input \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_2 ;
  input \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_2 ;
  input \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_2 ;
  input \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_2 ;
  input \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_2 ;
  input \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_2 ;
  input \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_2 ;
  input \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_2 ;
  input \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_2 ;
  input \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_2 ;
  input \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_2 ;
  input \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_2 ;
  input \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_2 ;
  input \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_2 ;
  input \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_2 ;
  input \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_2 ;
  input \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_2 ;
  input \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_2 ;
  input \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_2 ;
  input \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_2 ;
  input \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_2 ;
  input \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_2 ;
  input \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_2 ;
  input \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_2 ;
  input \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_2 ;
  input \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_2 ;
  input \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_2 ;
  input \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_3 ;
  input \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_2 ;
  input \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_2 ;
  input \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_2 ;
  input \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_2 ;
  input \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_2 ;
  input \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_2 ;
  input \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_2 ;
  input \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_2 ;
  input \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_2 ;
  input \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_2 ;
  input \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_2 ;
  input \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_2 ;
  input \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_2 ;
  input \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_2 ;
  input [67:0]Q;

  wire [67:0]Q;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ;
  wire \gen_mux_rd[0].mux_rd_fall0_r[0]_i_2_n_0 ;
  wire \gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0 ;
  wire \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_1 ;
  wire \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_2 ;
  wire \gen_mux_rd[0].mux_rd_fall1_r[0]_i_2_n_0 ;
  wire \gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0 ;
  wire \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_1 ;
  wire \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_2 ;
  wire \gen_mux_rd[0].mux_rd_fall2_r[0]_i_2_n_0 ;
  wire \gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0 ;
  wire \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_1 ;
  wire \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_2 ;
  wire \gen_mux_rd[0].mux_rd_fall3_r[0]_i_2_n_0 ;
  wire \gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0 ;
  wire \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_1 ;
  wire \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_2 ;
  wire \gen_mux_rd[0].mux_rd_rise0_r[0]_i_3_n_0 ;
  wire [1:0]\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ;
  wire \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1 ;
  wire \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_2 ;
  wire \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_3 ;
  wire \gen_mux_rd[0].mux_rd_rise1_r[0]_i_2_n_0 ;
  wire \gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0 ;
  wire \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_1 ;
  wire \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 ;
  wire \gen_mux_rd[0].mux_rd_rise2_r[0]_i_2_n_0 ;
  wire \gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0 ;
  wire \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_1 ;
  wire \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_2 ;
  wire \gen_mux_rd[0].mux_rd_rise3_r[0]_i_2_n_0 ;
  wire \gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0 ;
  wire \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_1 ;
  wire \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_2 ;
  wire \gen_mux_rd[1].mux_rd_fall0_r[1]_i_2_n_0 ;
  wire \gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 ;
  wire \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_2 ;
  wire \gen_mux_rd[1].mux_rd_fall1_r[1]_i_2_n_0 ;
  wire \gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 ;
  wire \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_2 ;
  wire \gen_mux_rd[1].mux_rd_fall2_r[1]_i_2_n_0 ;
  wire \gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 ;
  wire \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_2 ;
  wire \gen_mux_rd[1].mux_rd_fall3_r[1]_i_2_n_0 ;
  wire \gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1 ;
  wire \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_2 ;
  wire \gen_mux_rd[1].mux_rd_rise0_r[1]_i_2_n_0 ;
  wire \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1 ;
  wire \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ;
  wire \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_3 ;
  wire \gen_mux_rd[1].mux_rd_rise1_r[1]_i_2_n_0 ;
  wire \gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 ;
  wire \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_2 ;
  wire \gen_mux_rd[1].mux_rd_rise2_r[1]_i_2_n_0 ;
  wire \gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 ;
  wire \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_2 ;
  wire \gen_mux_rd[1].mux_rd_rise3_r[1]_i_2_n_0 ;
  wire \gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 ;
  wire \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_2 ;
  wire \gen_mux_rd[2].mux_rd_fall0_r[2]_i_2_n_0 ;
  wire \gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0 ;
  wire \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_1 ;
  wire \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_2 ;
  wire \gen_mux_rd[2].mux_rd_fall1_r[2]_i_2_n_0 ;
  wire \gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0 ;
  wire \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_1 ;
  wire \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_2 ;
  wire \gen_mux_rd[2].mux_rd_fall2_r[2]_i_2_n_0 ;
  wire \gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0 ;
  wire \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_1 ;
  wire \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_2 ;
  wire \gen_mux_rd[2].mux_rd_fall3_r[2]_i_2_n_0 ;
  wire \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 ;
  wire \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_1 ;
  wire \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_2 ;
  wire \gen_mux_rd[2].mux_rd_rise0_r[2]_i_2_n_0 ;
  wire \gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ;
  wire \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1 ;
  wire \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_2 ;
  wire \gen_mux_rd[2].mux_rd_rise1_r[2]_i_2_n_0 ;
  wire \gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0 ;
  wire \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_1 ;
  wire \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_2 ;
  wire \gen_mux_rd[2].mux_rd_rise2_r[2]_i_2_n_0 ;
  wire \gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0 ;
  wire \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_1 ;
  wire \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_2 ;
  wire \gen_mux_rd[2].mux_rd_rise3_r[2]_i_2_n_0 ;
  wire \gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0 ;
  wire \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_1 ;
  wire \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_2 ;
  wire \gen_mux_rd[3].mux_rd_fall0_r[3]_i_2_n_0 ;
  wire \gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 ;
  wire \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_2 ;
  wire \gen_mux_rd[3].mux_rd_fall1_r[3]_i_2_n_0 ;
  wire \gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 ;
  wire \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_2 ;
  wire \gen_mux_rd[3].mux_rd_fall2_r[3]_i_2_n_0 ;
  wire \gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 ;
  wire \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_2 ;
  wire \gen_mux_rd[3].mux_rd_fall3_r[3]_i_2_n_0 ;
  wire \gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 ;
  wire \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_2 ;
  wire \gen_mux_rd[3].mux_rd_rise0_r[3]_i_2_n_0 ;
  wire \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 ;
  wire \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_2 ;
  wire \gen_mux_rd[3].mux_rd_rise1_r[3]_i_2_n_0 ;
  wire \gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 ;
  wire \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_2 ;
  wire \gen_mux_rd[3].mux_rd_rise2_r[3]_i_2_n_0 ;
  wire \gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 ;
  wire \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_2 ;
  wire \gen_mux_rd[3].mux_rd_rise3_r[3]_i_2_n_0 ;
  wire \gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 ;
  wire \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_2 ;
  wire \gen_mux_rd[4].mux_rd_fall0_r[4]_i_2_n_0 ;
  wire \gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0 ;
  wire \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_1 ;
  wire \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_2 ;
  wire \gen_mux_rd[4].mux_rd_fall1_r[4]_i_2_n_0 ;
  wire \gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0 ;
  wire \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_1 ;
  wire \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_2 ;
  wire \gen_mux_rd[4].mux_rd_fall2_r[4]_i_2_n_0 ;
  wire \gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0 ;
  wire \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_1 ;
  wire \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_2 ;
  wire \gen_mux_rd[4].mux_rd_fall3_r[4]_i_2_n_0 ;
  wire \gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0 ;
  wire \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_1 ;
  wire \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_2 ;
  wire \gen_mux_rd[4].mux_rd_rise0_r[4]_i_2_n_0 ;
  wire \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0 ;
  wire \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_1 ;
  wire \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_2 ;
  wire \gen_mux_rd[4].mux_rd_rise1_r[4]_i_2_n_0 ;
  wire \gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0 ;
  wire \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_1 ;
  wire \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_2 ;
  wire \gen_mux_rd[4].mux_rd_rise2_r[4]_i_2_n_0 ;
  wire \gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0 ;
  wire \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_1 ;
  wire \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_2 ;
  wire \gen_mux_rd[4].mux_rd_rise3_r[4]_i_2_n_0 ;
  wire \gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0 ;
  wire \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_1 ;
  wire \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_2 ;
  wire \gen_mux_rd[5].mux_rd_fall0_r[5]_i_2_n_0 ;
  wire \gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 ;
  wire \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_2 ;
  wire \gen_mux_rd[5].mux_rd_fall1_r[5]_i_2_n_0 ;
  wire \gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 ;
  wire \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_2 ;
  wire \gen_mux_rd[5].mux_rd_fall2_r[5]_i_2_n_0 ;
  wire \gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 ;
  wire \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_2 ;
  wire \gen_mux_rd[5].mux_rd_fall3_r[5]_i_2_n_0 ;
  wire \gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 ;
  wire \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_2 ;
  wire \gen_mux_rd[5].mux_rd_rise0_r[5]_i_2_n_0 ;
  wire \gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_1 ;
  wire \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_2 ;
  wire \gen_mux_rd[5].mux_rd_rise1_r[5]_i_2_n_0 ;
  wire \gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 ;
  wire \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_2 ;
  wire \gen_mux_rd[5].mux_rd_rise2_r[5]_i_2_n_0 ;
  wire \gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 ;
  wire \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_2 ;
  wire \gen_mux_rd[5].mux_rd_rise3_r[5]_i_2_n_0 ;
  wire \gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 ;
  wire \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_2 ;
  wire \gen_mux_rd[6].mux_rd_fall0_r[6]_i_2_n_0 ;
  wire \gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0 ;
  wire \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_1 ;
  wire \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_2 ;
  wire \gen_mux_rd[6].mux_rd_fall1_r[6]_i_2_n_0 ;
  wire \gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0 ;
  wire \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_1 ;
  wire \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_2 ;
  wire \gen_mux_rd[6].mux_rd_fall2_r[6]_i_2_n_0 ;
  wire \gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0 ;
  wire \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_1 ;
  wire \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_2 ;
  wire \gen_mux_rd[6].mux_rd_fall3_r[6]_i_2_n_0 ;
  wire \gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0 ;
  wire \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_1 ;
  wire \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_2 ;
  wire \gen_mux_rd[6].mux_rd_rise0_r[6]_i_2_n_0 ;
  wire \gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0 ;
  wire \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_1 ;
  wire \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_2 ;
  wire \gen_mux_rd[6].mux_rd_rise1_r[6]_i_2_n_0 ;
  wire \gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0 ;
  wire \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_1 ;
  wire \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_2 ;
  wire \gen_mux_rd[6].mux_rd_rise2_r[6]_i_2_n_0 ;
  wire \gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0 ;
  wire \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_1 ;
  wire \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_2 ;
  wire \gen_mux_rd[6].mux_rd_rise3_r[6]_i_2_n_0 ;
  wire \gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0 ;
  wire \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_1 ;
  wire \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_2 ;
  wire \gen_mux_rd[7].mux_rd_fall0_r[7]_i_2_n_0 ;
  wire \gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 ;
  wire \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_2 ;
  wire \gen_mux_rd[7].mux_rd_fall1_r[7]_i_2_n_0 ;
  wire \gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 ;
  wire \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_2 ;
  wire \gen_mux_rd[7].mux_rd_fall2_r[7]_i_2_n_0 ;
  wire \gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 ;
  wire \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_2 ;
  wire \gen_mux_rd[7].mux_rd_fall3_r[7]_i_2_n_0 ;
  wire \gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 ;
  wire \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_2 ;
  wire \gen_mux_rd[7].mux_rd_rise0_r[7]_i_2_n_0 ;
  wire \gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_1 ;
  wire \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_2 ;
  wire \gen_mux_rd[7].mux_rd_rise1_r[7]_i_2_n_0 ;
  wire \gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 ;
  wire \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_2 ;
  wire \gen_mux_rd[7].mux_rd_rise2_r[7]_i_2_n_0 ;
  wire \gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 ;
  wire \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_2 ;
  wire \gen_mux_rd[7].mux_rd_rise3_r[7]_i_2_n_0 ;
  wire \gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 ;
  wire \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_2 ;
  wire ififo_rst;
  wire [79:16]mem_out;
  wire mem_reg_0_3_12_17_n_0;
  wire mem_reg_0_3_12_17_n_1;
  wire mem_reg_0_3_12_17_n_2;
  wire mem_reg_0_3_12_17_n_3;
  wire [0:0]my_empty;
  wire \my_empty[4]_i_1__4_n_0 ;
  wire \my_empty[4]_i_2__0_n_0 ;
  wire [4:1]my_empty_0;
  wire my_empty_inst_rep__0_n_0;
  wire \my_empty_reg[4]_0 ;
  wire [0:0]\my_empty_reg[4]_1 ;
  wire \my_empty_reg[4]_rep__0_n_0 ;
  wire \my_empty_reg[4]_rep_n_0 ;
  wire [1:0]my_full;
  wire \my_full[0]_i_1__0_n_0 ;
  wire \my_full[1]_i_1__0_n_0 ;
  wire \my_full[1]_i_2__0_n_0 ;
  wire \my_full_reg[1]_0 ;
  wire \rd_mux_sel_r_reg[2] ;
  wire \rd_mux_sel_r_reg[2]_0 ;
  wire \rd_mux_sel_r_reg[2]_1 ;
  wire \rd_mux_sel_r_reg[2]_10 ;
  wire \rd_mux_sel_r_reg[2]_11 ;
  wire \rd_mux_sel_r_reg[2]_12 ;
  wire \rd_mux_sel_r_reg[2]_13 ;
  wire \rd_mux_sel_r_reg[2]_14 ;
  wire \rd_mux_sel_r_reg[2]_15 ;
  wire \rd_mux_sel_r_reg[2]_16 ;
  wire \rd_mux_sel_r_reg[2]_17 ;
  wire \rd_mux_sel_r_reg[2]_18 ;
  wire \rd_mux_sel_r_reg[2]_19 ;
  wire \rd_mux_sel_r_reg[2]_2 ;
  wire \rd_mux_sel_r_reg[2]_20 ;
  wire \rd_mux_sel_r_reg[2]_21 ;
  wire \rd_mux_sel_r_reg[2]_22 ;
  wire \rd_mux_sel_r_reg[2]_23 ;
  wire \rd_mux_sel_r_reg[2]_24 ;
  wire \rd_mux_sel_r_reg[2]_25 ;
  wire \rd_mux_sel_r_reg[2]_26 ;
  wire \rd_mux_sel_r_reg[2]_27 ;
  wire \rd_mux_sel_r_reg[2]_28 ;
  wire \rd_mux_sel_r_reg[2]_29 ;
  wire \rd_mux_sel_r_reg[2]_3 ;
  wire \rd_mux_sel_r_reg[2]_30 ;
  wire \rd_mux_sel_r_reg[2]_31 ;
  wire \rd_mux_sel_r_reg[2]_32 ;
  wire \rd_mux_sel_r_reg[2]_33 ;
  wire \rd_mux_sel_r_reg[2]_34 ;
  wire \rd_mux_sel_r_reg[2]_35 ;
  wire \rd_mux_sel_r_reg[2]_36 ;
  wire \rd_mux_sel_r_reg[2]_37 ;
  wire \rd_mux_sel_r_reg[2]_38 ;
  wire \rd_mux_sel_r_reg[2]_39 ;
  wire \rd_mux_sel_r_reg[2]_4 ;
  wire \rd_mux_sel_r_reg[2]_40 ;
  wire \rd_mux_sel_r_reg[2]_41 ;
  wire \rd_mux_sel_r_reg[2]_42 ;
  wire \rd_mux_sel_r_reg[2]_43 ;
  wire \rd_mux_sel_r_reg[2]_44 ;
  wire \rd_mux_sel_r_reg[2]_45 ;
  wire \rd_mux_sel_r_reg[2]_46 ;
  wire \rd_mux_sel_r_reg[2]_47 ;
  wire \rd_mux_sel_r_reg[2]_48 ;
  wire \rd_mux_sel_r_reg[2]_49 ;
  wire \rd_mux_sel_r_reg[2]_5 ;
  wire \rd_mux_sel_r_reg[2]_50 ;
  wire \rd_mux_sel_r_reg[2]_51 ;
  wire \rd_mux_sel_r_reg[2]_52 ;
  wire \rd_mux_sel_r_reg[2]_53 ;
  wire \rd_mux_sel_r_reg[2]_54 ;
  wire \rd_mux_sel_r_reg[2]_55 ;
  wire \rd_mux_sel_r_reg[2]_56 ;
  wire \rd_mux_sel_r_reg[2]_57 ;
  wire \rd_mux_sel_r_reg[2]_58 ;
  wire \rd_mux_sel_r_reg[2]_59 ;
  wire \rd_mux_sel_r_reg[2]_6 ;
  wire \rd_mux_sel_r_reg[2]_60 ;
  wire \rd_mux_sel_r_reg[2]_61 ;
  wire \rd_mux_sel_r_reg[2]_62 ;
  wire \rd_mux_sel_r_reg[2]_7 ;
  wire \rd_mux_sel_r_reg[2]_8 ;
  wire \rd_mux_sel_r_reg[2]_9 ;
  wire [1:0]rd_ptr;
  wire \rd_ptr[0]_i_1__0_n_0 ;
  wire \rd_ptr[1]_i_1__0_n_0 ;
  wire \rd_ptr_reg[1]_0 ;
  (* RTL_KEEP = "true" *) (* syn_maxfan = "10" *) wire [1:0]rd_ptr_timing;
  wire \rd_ptr_timing[0]_i_1__2_n_0 ;
  wire \rd_ptr_timing[1]_i_1__2_n_0 ;
  (* MAX_FANOUT = "40" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire wr_en;
  wire [1:0]wr_ptr;
  wire \wr_ptr[0]_i_1__2_n_0 ;
  wire \wr_ptr[1]_i_1__2_n_0 ;
  wire \wr_ptr[1]_i_2__0 ;
  wire \wr_ptr_reg[0]_0 ;
  wire [1:0]NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_66_71_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_72_77_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_78_79_DOB_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_78_79_DOC_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_78_79_DOD_UNCONNECTED;

  (* SOFT_HLUTNM = "soft_lutpair743" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[104]_INST_0 
       (.I0(Q[5]),
        .I1(my_empty_inst_rep__0_n_0),
        .I2(mem_out[17]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ));
  (* SOFT_HLUTNM = "soft_lutpair743" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[105]_INST_0 
       (.I0(Q[13]),
        .I1(my_empty_inst_rep__0_n_0),
        .I2(mem_out[25]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ));
  (* SOFT_HLUTNM = "soft_lutpair733" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[106]_INST_0 
       (.I0(Q[21]),
        .I1(my_empty_inst_rep__0_n_0),
        .I2(mem_out[33]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ));
  (* SOFT_HLUTNM = "soft_lutpair741" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[107]_INST_0 
       (.I0(Q[29]),
        .I1(my_empty_inst_rep__0_n_0),
        .I2(mem_out[41]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ));
  (* SOFT_HLUTNM = "soft_lutpair740" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[108]_INST_0 
       (.I0(Q[37]),
        .I1(my_empty_0[4]),
        .I2(mem_out[49]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ));
  (* SOFT_HLUTNM = "soft_lutpair731" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[109]_INST_0 
       (.I0(Q[45]),
        .I1(my_empty_0[4]),
        .I2(mem_out[57]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ));
  (* SOFT_HLUTNM = "soft_lutpair737" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[110]_INST_0 
       (.I0(Q[53]),
        .I1(my_empty_0[4]),
        .I2(mem_out[65]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ));
  (* SOFT_HLUTNM = "soft_lutpair736" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[111]_INST_0 
       (.I0(Q[61]),
        .I1(my_empty_0[4]),
        .I2(mem_out[73]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] ));
  (* SOFT_HLUTNM = "soft_lutpair724" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[168]_INST_0 
       (.I0(Q[6]),
        .I1(my_empty_inst_rep__0_n_0),
        .I2(mem_out[18]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ));
  (* SOFT_HLUTNM = "soft_lutpair719" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[169]_INST_0 
       (.I0(Q[14]),
        .I1(my_empty_inst_rep__0_n_0),
        .I2(mem_out[26]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ));
  (* SOFT_HLUTNM = "soft_lutpair713" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[170]_INST_0 
       (.I0(Q[22]),
        .I1(my_empty_inst_rep__0_n_0),
        .I2(mem_out[34]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ));
  (* SOFT_HLUTNM = "soft_lutpair722" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[171]_INST_0 
       (.I0(Q[30]),
        .I1(my_empty_inst_rep__0_n_0),
        .I2(mem_out[42]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ));
  (* SOFT_HLUTNM = "soft_lutpair717" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[172]_INST_0 
       (.I0(Q[38]),
        .I1(my_empty_0[4]),
        .I2(mem_out[50]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ));
  (* SOFT_HLUTNM = "soft_lutpair726" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[173]_INST_0 
       (.I0(Q[46]),
        .I1(my_empty_0[4]),
        .I2(mem_out[58]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ));
  (* SOFT_HLUTNM = "soft_lutpair720" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[174]_INST_0 
       (.I0(Q[54]),
        .I1(my_empty_0[4]),
        .I2(mem_out[66]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ));
  (* SOFT_HLUTNM = "soft_lutpair716" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[175]_INST_0 
       (.I0(Q[62]),
        .I1(my_empty_0[4]),
        .I2(mem_out[74]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] ));
  (* SOFT_HLUTNM = "soft_lutpair744" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[232]_INST_0 
       (.I0(Q[7]),
        .I1(my_empty_inst_rep__0_n_0),
        .I2(mem_out[19]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ));
  (* SOFT_HLUTNM = "soft_lutpair733" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[233]_INST_0 
       (.I0(Q[15]),
        .I1(my_empty_inst_rep__0_n_0),
        .I2(mem_out[27]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ));
  (* SOFT_HLUTNM = "soft_lutpair742" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[234]_INST_0 
       (.I0(Q[23]),
        .I1(my_empty_inst_rep__0_n_0),
        .I2(mem_out[35]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ));
  (* SOFT_HLUTNM = "soft_lutpair739" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[235]_INST_0 
       (.I0(Q[31]),
        .I1(my_empty_inst_rep__0_n_0),
        .I2(mem_out[43]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ));
  (* SOFT_HLUTNM = "soft_lutpair731" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[236]_INST_0 
       (.I0(Q[39]),
        .I1(my_empty_0[4]),
        .I2(mem_out[51]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ));
  (* SOFT_HLUTNM = "soft_lutpair738" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[237]_INST_0 
       (.I0(Q[47]),
        .I1(my_empty_0[4]),
        .I2(mem_out[59]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ));
  (* SOFT_HLUTNM = "soft_lutpair737" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[238]_INST_0 
       (.I0(Q[55]),
        .I1(my_empty_0[4]),
        .I2(mem_out[67]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ));
  (* SOFT_HLUTNM = "soft_lutpair728" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[239]_INST_0 
       (.I0(Q[63]),
        .I1(my_empty_0[4]),
        .I2(mem_out[75]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] ));
  (* SOFT_HLUTNM = "soft_lutpair719" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[296]_INST_0 
       (.I0(Q[8]),
        .I1(my_empty_inst_rep__0_n_0),
        .I2(mem_out[20]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ));
  (* SOFT_HLUTNM = "soft_lutpair727" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[297]_INST_0 
       (.I0(Q[16]),
        .I1(my_empty_inst_rep__0_n_0),
        .I2(mem_out[28]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ));
  (* SOFT_HLUTNM = "soft_lutpair722" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[298]_INST_0 
       (.I0(Q[24]),
        .I1(my_empty_inst_rep__0_n_0),
        .I2(mem_out[36]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ));
  (* SOFT_HLUTNM = "soft_lutpair713" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[299]_INST_0 
       (.I0(Q[32]),
        .I1(my_empty_inst_rep__0_n_0),
        .I2(mem_out[44]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ));
  (* SOFT_HLUTNM = "soft_lutpair726" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[300]_INST_0 
       (.I0(Q[40]),
        .I1(my_empty_0[4]),
        .I2(mem_out[52]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ));
  (* SOFT_HLUTNM = "soft_lutpair721" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[301]_INST_0 
       (.I0(Q[48]),
        .I1(my_empty_0[4]),
        .I2(mem_out[60]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ));
  (* SOFT_HLUTNM = "soft_lutpair716" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[302]_INST_0 
       (.I0(Q[56]),
        .I1(my_empty_0[4]),
        .I2(mem_out[68]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ));
  (* SOFT_HLUTNM = "soft_lutpair725" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[303]_INST_0 
       (.I0(Q[64]),
        .I1(my_empty_0[4]),
        .I2(mem_out[76]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] ));
  (* SOFT_HLUTNM = "soft_lutpair734" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[360]_INST_0 
       (.I0(Q[9]),
        .I1(my_empty_inst_rep__0_n_0),
        .I2(mem_out[21]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ));
  (* SOFT_HLUTNM = "soft_lutpair742" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[361]_INST_0 
       (.I0(Q[17]),
        .I1(my_empty_inst_rep__0_n_0),
        .I2(mem_out[29]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ));
  (* SOFT_HLUTNM = "soft_lutpair741" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[362]_INST_0 
       (.I0(Q[25]),
        .I1(my_empty_inst_rep__0_n_0),
        .I2(mem_out[37]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ));
  (* SOFT_HLUTNM = "soft_lutpair732" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[363]_INST_0 
       (.I0(Q[33]),
        .I1(my_empty_inst_rep__0_n_0),
        .I2(mem_out[45]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ));
  (* SOFT_HLUTNM = "soft_lutpair740" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[364]_INST_0 
       (.I0(Q[41]),
        .I1(my_empty_0[4]),
        .I2(mem_out[53]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ));
  (* SOFT_HLUTNM = "soft_lutpair730" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[365]_INST_0 
       (.I0(Q[49]),
        .I1(my_empty_0[4]),
        .I2(mem_out[61]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ));
  (* SOFT_HLUTNM = "soft_lutpair728" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[366]_INST_0 
       (.I0(Q[57]),
        .I1(my_empty_0[4]),
        .I2(mem_out[69]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ));
  (* SOFT_HLUTNM = "soft_lutpair735" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[367]_INST_0 
       (.I0(Q[65]),
        .I1(my_empty_0[4]),
        .I2(mem_out[77]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] ));
  (* SOFT_HLUTNM = "soft_lutpair729" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[40]_INST_0 
       (.I0(Q[4]),
        .I1(my_empty_inst_rep__0_n_0),
        .I2(mem_out[16]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ));
  (* SOFT_HLUTNM = "soft_lutpair723" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[41]_INST_0 
       (.I0(Q[12]),
        .I1(my_empty_inst_rep__0_n_0),
        .I2(mem_out[24]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ));
  (* SOFT_HLUTNM = "soft_lutpair729" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[424]_INST_0 
       (.I0(Q[10]),
        .I1(my_empty_inst_rep__0_n_0),
        .I2(mem_out[22]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ));
  (* SOFT_HLUTNM = "soft_lutpair723" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[425]_INST_0 
       (.I0(Q[18]),
        .I1(my_empty_inst_rep__0_n_0),
        .I2(mem_out[30]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ));
  (* SOFT_HLUTNM = "soft_lutpair718" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[426]_INST_0 
       (.I0(Q[26]),
        .I1(my_empty_inst_rep__0_n_0),
        .I2(mem_out[38]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ));
  (* SOFT_HLUTNM = "soft_lutpair724" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[427]_INST_0 
       (.I0(Q[34]),
        .I1(my_empty_inst_rep__0_n_0),
        .I2(mem_out[46]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ));
  (* SOFT_HLUTNM = "soft_lutpair721" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[428]_INST_0 
       (.I0(Q[42]),
        .I1(my_empty_0[4]),
        .I2(mem_out[54]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ));
  (* SOFT_HLUTNM = "soft_lutpair717" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[429]_INST_0 
       (.I0(Q[50]),
        .I1(my_empty_0[4]),
        .I2(mem_out[62]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ));
  (* SOFT_HLUTNM = "soft_lutpair718" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[42]_INST_0 
       (.I0(Q[20]),
        .I1(my_empty_inst_rep__0_n_0),
        .I2(mem_out[32]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ));
  (* SOFT_HLUTNM = "soft_lutpair725" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[430]_INST_0 
       (.I0(Q[58]),
        .I1(my_empty_0[4]),
        .I2(mem_out[70]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ));
  (* SOFT_HLUTNM = "soft_lutpair720" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[431]_INST_0 
       (.I0(Q[66]),
        .I1(my_empty_0[4]),
        .I2(mem_out[78]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] ));
  (* SOFT_HLUTNM = "soft_lutpair727" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[43]_INST_0 
       (.I0(Q[28]),
        .I1(my_empty_inst_rep__0_n_0),
        .I2(mem_out[40]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ));
  (* SOFT_HLUTNM = "soft_lutpair715" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[44]_INST_0 
       (.I0(Q[36]),
        .I1(my_empty_0[4]),
        .I2(mem_out[48]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ));
  (* SOFT_HLUTNM = "soft_lutpair714" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[45]_INST_0 
       (.I0(Q[44]),
        .I1(my_empty_0[4]),
        .I2(mem_out[56]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ));
  (* SOFT_HLUTNM = "soft_lutpair715" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[46]_INST_0 
       (.I0(Q[52]),
        .I1(my_empty_0[4]),
        .I2(mem_out[64]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ));
  (* SOFT_HLUTNM = "soft_lutpair714" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[47]_INST_0 
       (.I0(Q[60]),
        .I1(my_empty_0[4]),
        .I2(mem_out[72]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ));
  (* SOFT_HLUTNM = "soft_lutpair744" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[488]_INST_0 
       (.I0(Q[11]),
        .I1(my_empty_inst_rep__0_n_0),
        .I2(mem_out[23]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ));
  (* SOFT_HLUTNM = "soft_lutpair739" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[489]_INST_0 
       (.I0(Q[19]),
        .I1(my_empty_inst_rep__0_n_0),
        .I2(mem_out[31]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ));
  (* SOFT_HLUTNM = "soft_lutpair732" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[490]_INST_0 
       (.I0(Q[27]),
        .I1(my_empty_inst_rep__0_n_0),
        .I2(mem_out[39]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ));
  (* SOFT_HLUTNM = "soft_lutpair734" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[491]_INST_0 
       (.I0(Q[35]),
        .I1(my_empty_inst_rep__0_n_0),
        .I2(mem_out[47]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ));
  (* SOFT_HLUTNM = "soft_lutpair738" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[492]_INST_0 
       (.I0(Q[43]),
        .I1(my_empty_0[4]),
        .I2(mem_out[55]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ));
  (* SOFT_HLUTNM = "soft_lutpair730" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[493]_INST_0 
       (.I0(Q[51]),
        .I1(my_empty_0[4]),
        .I2(mem_out[63]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ));
  (* SOFT_HLUTNM = "soft_lutpair736" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[494]_INST_0 
       (.I0(Q[59]),
        .I1(my_empty_0[4]),
        .I2(mem_out[71]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ));
  (* SOFT_HLUTNM = "soft_lutpair735" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[495]_INST_0 
       (.I0(Q[67]),
        .I1(my_empty_0[4]),
        .I2(mem_out[79]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[0].mux_rd_fall0_r[0]_i_2 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ),
        .I3(\gen_mux_rd[0].mux_rd_fall0_r_reg[0] ),
        .I4(\gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0 ),
        .I5(\gen_mux_rd[0].mux_rd_fall0_r_reg[0]_1 ),
        .O(\gen_mux_rd[0].mux_rd_fall0_r[0]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_i_1 
       (.I0(\gen_mux_rd[0].mux_rd_fall0_r[0]_i_2_n_0 ),
        .I1(\gen_mux_rd[0].mux_rd_fall0_r_reg[0]_2 ),
        .O(\rd_mux_sel_r_reg[2]_50 ),
        .S(\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[0].mux_rd_fall1_r[0]_i_2 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ),
        .I3(\gen_mux_rd[0].mux_rd_fall1_r_reg[0] ),
        .I4(\gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0 ),
        .I5(\gen_mux_rd[0].mux_rd_fall1_r_reg[0]_1 ),
        .O(\gen_mux_rd[0].mux_rd_fall1_r[0]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_i_1 
       (.I0(\gen_mux_rd[0].mux_rd_fall1_r[0]_i_2_n_0 ),
        .I1(\gen_mux_rd[0].mux_rd_fall1_r_reg[0]_2 ),
        .O(\rd_mux_sel_r_reg[2]_55 ),
        .S(\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[0].mux_rd_fall2_r[0]_i_2 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ),
        .I3(\gen_mux_rd[0].mux_rd_fall2_r_reg[0] ),
        .I4(\gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0 ),
        .I5(\gen_mux_rd[0].mux_rd_fall2_r_reg[0]_1 ),
        .O(\gen_mux_rd[0].mux_rd_fall2_r[0]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_i_1 
       (.I0(\gen_mux_rd[0].mux_rd_fall2_r[0]_i_2_n_0 ),
        .I1(\gen_mux_rd[0].mux_rd_fall2_r_reg[0]_2 ),
        .O(\rd_mux_sel_r_reg[2]_59 ),
        .S(\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[0].mux_rd_fall3_r[0]_i_2 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ),
        .I3(\gen_mux_rd[0].mux_rd_fall3_r_reg[0] ),
        .I4(\gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0 ),
        .I5(\gen_mux_rd[0].mux_rd_fall3_r_reg[0]_1 ),
        .O(\gen_mux_rd[0].mux_rd_fall3_r[0]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_i_1 
       (.I0(\gen_mux_rd[0].mux_rd_fall3_r[0]_i_2_n_0 ),
        .I1(\gen_mux_rd[0].mux_rd_fall3_r_reg[0]_2 ),
        .O(\rd_mux_sel_r_reg[2]_40 ),
        .S(\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[0].mux_rd_rise0_r[0]_i_3 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ),
        .I3(\gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ),
        .I4(\gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1 ),
        .I5(\gen_mux_rd[0].mux_rd_rise0_r_reg[0]_2 ),
        .O(\gen_mux_rd[0].mux_rd_rise0_r[0]_i_3_n_0 ));
  MUXF7 \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_i_1 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r[0]_i_3_n_0 ),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0]_3 ),
        .O(\rd_mux_sel_r_reg[2]_48 ),
        .S(\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[0].mux_rd_rise1_r[0]_i_2 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ),
        .I3(\gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .I4(\gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0 ),
        .I5(\gen_mux_rd[0].mux_rd_rise1_r_reg[0]_1 ),
        .O(\gen_mux_rd[0].mux_rd_rise1_r[0]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_i_1 
       (.I0(\gen_mux_rd[0].mux_rd_rise1_r[0]_i_2_n_0 ),
        .I1(\gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 ),
        .O(\rd_mux_sel_r_reg[2]_10 ),
        .S(\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[0].mux_rd_rise2_r[0]_i_2 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ),
        .I3(\gen_mux_rd[0].mux_rd_rise2_r_reg[0] ),
        .I4(\gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0 ),
        .I5(\gen_mux_rd[0].mux_rd_rise2_r_reg[0]_1 ),
        .O(\gen_mux_rd[0].mux_rd_rise2_r[0]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_i_1 
       (.I0(\gen_mux_rd[0].mux_rd_rise2_r[0]_i_2_n_0 ),
        .I1(\gen_mux_rd[0].mux_rd_rise2_r_reg[0]_2 ),
        .O(\rd_mux_sel_r_reg[2]_21 ),
        .S(\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[0].mux_rd_rise3_r[0]_i_2 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ),
        .I3(\gen_mux_rd[0].mux_rd_rise3_r_reg[0] ),
        .I4(\gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0 ),
        .I5(\gen_mux_rd[0].mux_rd_rise3_r_reg[0]_1 ),
        .O(\gen_mux_rd[0].mux_rd_rise3_r[0]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_i_1 
       (.I0(\gen_mux_rd[0].mux_rd_rise3_r[0]_i_2_n_0 ),
        .I1(\gen_mux_rd[0].mux_rd_rise3_r_reg[0]_2 ),
        .O(\rd_mux_sel_r_reg[2]_61 ),
        .S(\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[1].mux_rd_fall0_r[1]_i_2 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ),
        .I3(\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ),
        .I4(\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ),
        .I5(\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 ),
        .O(\gen_mux_rd[1].mux_rd_fall0_r[1]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_i_1 
       (.I0(\gen_mux_rd[1].mux_rd_fall0_r[1]_i_2_n_0 ),
        .I1(\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_2 ),
        .O(\rd_mux_sel_r_reg[2]_5 ),
        .S(\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[1].mux_rd_fall1_r[1]_i_2 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ),
        .I3(\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ),
        .I4(\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ),
        .I5(\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 ),
        .O(\gen_mux_rd[1].mux_rd_fall1_r[1]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_i_1 
       (.I0(\gen_mux_rd[1].mux_rd_fall1_r[1]_i_2_n_0 ),
        .I1(\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_2 ),
        .O(\rd_mux_sel_r_reg[2]_16 ),
        .S(\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[1].mux_rd_fall2_r[1]_i_2 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ),
        .I3(\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ),
        .I4(\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ),
        .I5(\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 ),
        .O(\gen_mux_rd[1].mux_rd_fall2_r[1]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_i_1 
       (.I0(\gen_mux_rd[1].mux_rd_fall2_r[1]_i_2_n_0 ),
        .I1(\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_2 ),
        .O(\rd_mux_sel_r_reg[2]_28 ),
        .S(\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[1].mux_rd_fall3_r[1]_i_2 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ),
        .I3(\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ),
        .I4(\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ),
        .I5(\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1 ),
        .O(\gen_mux_rd[1].mux_rd_fall3_r[1]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_i_1 
       (.I0(\gen_mux_rd[1].mux_rd_fall3_r[1]_i_2_n_0 ),
        .I1(\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_2 ),
        .O(\rd_mux_sel_r_reg[2]_41 ),
        .S(\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[1].mux_rd_rise0_r[1]_i_2 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ),
        .I3(\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ),
        .I4(\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ),
        .I5(\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1 ),
        .O(\gen_mux_rd[1].mux_rd_rise0_r[1]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_i_1 
       (.I0(\gen_mux_rd[1].mux_rd_rise0_r[1]_i_2_n_0 ),
        .I1(\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_3 ),
        .O(\rd_mux_sel_r_reg[2] ),
        .S(\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[1].mux_rd_rise1_r[1]_i_2 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ),
        .I3(\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ),
        .I4(\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ),
        .I5(\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 ),
        .O(\gen_mux_rd[1].mux_rd_rise1_r[1]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_i_1 
       (.I0(\gen_mux_rd[1].mux_rd_rise1_r[1]_i_2_n_0 ),
        .I1(\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_2 ),
        .O(\rd_mux_sel_r_reg[2]_11 ),
        .S(\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[1].mux_rd_rise2_r[1]_i_2 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ),
        .I3(\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ),
        .I4(\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ),
        .I5(\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 ),
        .O(\gen_mux_rd[1].mux_rd_rise2_r[1]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_i_1 
       (.I0(\gen_mux_rd[1].mux_rd_rise2_r[1]_i_2_n_0 ),
        .I1(\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_2 ),
        .O(\rd_mux_sel_r_reg[2]_22 ),
        .S(\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[1].mux_rd_rise3_r[1]_i_2 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ),
        .I3(\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ),
        .I4(\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ),
        .I5(\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 ),
        .O(\gen_mux_rd[1].mux_rd_rise3_r[1]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_i_1 
       (.I0(\gen_mux_rd[1].mux_rd_rise3_r[1]_i_2_n_0 ),
        .I1(\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_2 ),
        .O(\rd_mux_sel_r_reg[2]_34 ),
        .S(\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[2].mux_rd_fall0_r[2]_i_2 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ),
        .I3(\gen_mux_rd[2].mux_rd_fall0_r_reg[2] ),
        .I4(\gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0 ),
        .I5(\gen_mux_rd[2].mux_rd_fall0_r_reg[2]_1 ),
        .O(\gen_mux_rd[2].mux_rd_fall0_r[2]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall0_r[2]_i_2_n_0 ),
        .I1(\gen_mux_rd[2].mux_rd_fall0_r_reg[2]_2 ),
        .O(\rd_mux_sel_r_reg[2]_51 ),
        .S(\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[2].mux_rd_fall1_r[2]_i_2 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ),
        .I3(\gen_mux_rd[2].mux_rd_fall1_r_reg[2] ),
        .I4(\gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0 ),
        .I5(\gen_mux_rd[2].mux_rd_fall1_r_reg[2]_1 ),
        .O(\gen_mux_rd[2].mux_rd_fall1_r[2]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall1_r[2]_i_2_n_0 ),
        .I1(\gen_mux_rd[2].mux_rd_fall1_r_reg[2]_2 ),
        .O(\rd_mux_sel_r_reg[2]_56 ),
        .S(\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[2].mux_rd_fall2_r[2]_i_2 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ),
        .I3(\gen_mux_rd[2].mux_rd_fall2_r_reg[2] ),
        .I4(\gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0 ),
        .I5(\gen_mux_rd[2].mux_rd_fall2_r_reg[2]_1 ),
        .O(\gen_mux_rd[2].mux_rd_fall2_r[2]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall2_r[2]_i_2_n_0 ),
        .I1(\gen_mux_rd[2].mux_rd_fall2_r_reg[2]_2 ),
        .O(\rd_mux_sel_r_reg[2]_29 ),
        .S(\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[2].mux_rd_fall3_r[2]_i_2 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ),
        .I3(\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ),
        .I4(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 ),
        .I5(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_1 ),
        .O(\gen_mux_rd[2].mux_rd_fall3_r[2]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_fall3_r[2]_i_2_n_0 ),
        .I1(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_2 ),
        .O(\rd_mux_sel_r_reg[2]_42 ),
        .S(\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[2].mux_rd_rise0_r[2]_i_2 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ),
        .I3(\gen_mux_rd[2].mux_rd_rise0_r_reg[2] ),
        .I4(\gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ),
        .I5(\gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1 ),
        .O(\gen_mux_rd[2].mux_rd_rise0_r[2]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_rise0_r[2]_i_2_n_0 ),
        .I1(\gen_mux_rd[2].mux_rd_rise0_r_reg[2]_2 ),
        .O(\rd_mux_sel_r_reg[2]_0 ),
        .S(\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[2].mux_rd_rise1_r[2]_i_2 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ),
        .I3(\gen_mux_rd[2].mux_rd_rise1_r_reg[2] ),
        .I4(\gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0 ),
        .I5(\gen_mux_rd[2].mux_rd_rise1_r_reg[2]_1 ),
        .O(\gen_mux_rd[2].mux_rd_rise1_r[2]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_rise1_r[2]_i_2_n_0 ),
        .I1(\gen_mux_rd[2].mux_rd_rise1_r_reg[2]_2 ),
        .O(\rd_mux_sel_r_reg[2]_53 ),
        .S(\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[2].mux_rd_rise2_r[2]_i_2 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ),
        .I3(\gen_mux_rd[2].mux_rd_rise2_r_reg[2] ),
        .I4(\gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0 ),
        .I5(\gen_mux_rd[2].mux_rd_rise2_r_reg[2]_1 ),
        .O(\gen_mux_rd[2].mux_rd_rise2_r[2]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_rise2_r[2]_i_2_n_0 ),
        .I1(\gen_mux_rd[2].mux_rd_rise2_r_reg[2]_2 ),
        .O(\rd_mux_sel_r_reg[2]_23 ),
        .S(\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[2].mux_rd_rise3_r[2]_i_2 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ),
        .I3(\gen_mux_rd[2].mux_rd_rise3_r_reg[2] ),
        .I4(\gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0 ),
        .I5(\gen_mux_rd[2].mux_rd_rise3_r_reg[2]_1 ),
        .O(\gen_mux_rd[2].mux_rd_rise3_r[2]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_i_1 
       (.I0(\gen_mux_rd[2].mux_rd_rise3_r[2]_i_2_n_0 ),
        .I1(\gen_mux_rd[2].mux_rd_rise3_r_reg[2]_2 ),
        .O(\rd_mux_sel_r_reg[2]_35 ),
        .S(\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[3].mux_rd_fall0_r[3]_i_2 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ),
        .I3(\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ),
        .I4(\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ),
        .I5(\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 ),
        .O(\gen_mux_rd[3].mux_rd_fall0_r[3]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_i_1 
       (.I0(\gen_mux_rd[3].mux_rd_fall0_r[3]_i_2_n_0 ),
        .I1(\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_2 ),
        .O(\rd_mux_sel_r_reg[2]_6 ),
        .S(\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[3].mux_rd_fall1_r[3]_i_2 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ),
        .I3(\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ),
        .I4(\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ),
        .I5(\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 ),
        .O(\gen_mux_rd[3].mux_rd_fall1_r[3]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_i_1 
       (.I0(\gen_mux_rd[3].mux_rd_fall1_r[3]_i_2_n_0 ),
        .I1(\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_2 ),
        .O(\rd_mux_sel_r_reg[2]_17 ),
        .S(\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[3].mux_rd_fall2_r[3]_i_2 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ),
        .I3(\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ),
        .I4(\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ),
        .I5(\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 ),
        .O(\gen_mux_rd[3].mux_rd_fall2_r[3]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_i_1 
       (.I0(\gen_mux_rd[3].mux_rd_fall2_r[3]_i_2_n_0 ),
        .I1(\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_2 ),
        .O(\rd_mux_sel_r_reg[2]_30 ),
        .S(\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[3].mux_rd_fall3_r[3]_i_2 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ),
        .I3(\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ),
        .I4(\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ),
        .I5(\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 ),
        .O(\gen_mux_rd[3].mux_rd_fall3_r[3]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_i_1 
       (.I0(\gen_mux_rd[3].mux_rd_fall3_r[3]_i_2_n_0 ),
        .I1(\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_2 ),
        .O(\rd_mux_sel_r_reg[2]_43 ),
        .S(\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[3].mux_rd_rise0_r[3]_i_2 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ),
        .I3(\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ),
        .I4(\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ),
        .I5(\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 ),
        .O(\gen_mux_rd[3].mux_rd_rise0_r[3]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_i_1 
       (.I0(\gen_mux_rd[3].mux_rd_rise0_r[3]_i_2_n_0 ),
        .I1(\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_2 ),
        .O(\rd_mux_sel_r_reg[2]_1 ),
        .S(\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[3].mux_rd_rise1_r[3]_i_2 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ),
        .I3(\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ),
        .I4(\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ),
        .I5(\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 ),
        .O(\gen_mux_rd[3].mux_rd_rise1_r[3]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_i_1 
       (.I0(\gen_mux_rd[3].mux_rd_rise1_r[3]_i_2_n_0 ),
        .I1(\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_2 ),
        .O(\rd_mux_sel_r_reg[2]_12 ),
        .S(\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[3].mux_rd_rise2_r[3]_i_2 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ),
        .I3(\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ),
        .I4(\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ),
        .I5(\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 ),
        .O(\gen_mux_rd[3].mux_rd_rise2_r[3]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_i_1 
       (.I0(\gen_mux_rd[3].mux_rd_rise2_r[3]_i_2_n_0 ),
        .I1(\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_2 ),
        .O(\rd_mux_sel_r_reg[2]_24 ),
        .S(\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[3].mux_rd_rise3_r[3]_i_2 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ),
        .I3(\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ),
        .I4(\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ),
        .I5(\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 ),
        .O(\gen_mux_rd[3].mux_rd_rise3_r[3]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_i_1 
       (.I0(\gen_mux_rd[3].mux_rd_rise3_r[3]_i_2_n_0 ),
        .I1(\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_2 ),
        .O(\rd_mux_sel_r_reg[2]_36 ),
        .S(\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[4].mux_rd_fall0_r[4]_i_2 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ),
        .I3(\gen_mux_rd[4].mux_rd_fall0_r_reg[4] ),
        .I4(\gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0 ),
        .I5(\gen_mux_rd[4].mux_rd_fall0_r_reg[4]_1 ),
        .O(\gen_mux_rd[4].mux_rd_fall0_r[4]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_i_1 
       (.I0(\gen_mux_rd[4].mux_rd_fall0_r[4]_i_2_n_0 ),
        .I1(\gen_mux_rd[4].mux_rd_fall0_r_reg[4]_2 ),
        .O(\rd_mux_sel_r_reg[2]_52 ),
        .S(\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[4].mux_rd_fall1_r[4]_i_2 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ),
        .I3(\gen_mux_rd[4].mux_rd_fall1_r_reg[4] ),
        .I4(\gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0 ),
        .I5(\gen_mux_rd[4].mux_rd_fall1_r_reg[4]_1 ),
        .O(\gen_mux_rd[4].mux_rd_fall1_r[4]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_i_1 
       (.I0(\gen_mux_rd[4].mux_rd_fall1_r[4]_i_2_n_0 ),
        .I1(\gen_mux_rd[4].mux_rd_fall1_r_reg[4]_2 ),
        .O(\rd_mux_sel_r_reg[2]_57 ),
        .S(\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[4].mux_rd_fall2_r[4]_i_2 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ),
        .I3(\gen_mux_rd[4].mux_rd_fall2_r_reg[4] ),
        .I4(\gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0 ),
        .I5(\gen_mux_rd[4].mux_rd_fall2_r_reg[4]_1 ),
        .O(\gen_mux_rd[4].mux_rd_fall2_r[4]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_i_1 
       (.I0(\gen_mux_rd[4].mux_rd_fall2_r[4]_i_2_n_0 ),
        .I1(\gen_mux_rd[4].mux_rd_fall2_r_reg[4]_2 ),
        .O(\rd_mux_sel_r_reg[2]_60 ),
        .S(\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[4].mux_rd_fall3_r[4]_i_2 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ),
        .I3(\gen_mux_rd[4].mux_rd_fall3_r_reg[4] ),
        .I4(\gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0 ),
        .I5(\gen_mux_rd[4].mux_rd_fall3_r_reg[4]_1 ),
        .O(\gen_mux_rd[4].mux_rd_fall3_r[4]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_i_1 
       (.I0(\gen_mux_rd[4].mux_rd_fall3_r[4]_i_2_n_0 ),
        .I1(\gen_mux_rd[4].mux_rd_fall3_r_reg[4]_2 ),
        .O(\rd_mux_sel_r_reg[2]_44 ),
        .S(\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[4].mux_rd_rise0_r[4]_i_2 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ),
        .I3(\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .I4(\gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0 ),
        .I5(\gen_mux_rd[4].mux_rd_rise0_r_reg[4]_1 ),
        .O(\gen_mux_rd[4].mux_rd_rise0_r[4]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_i_1 
       (.I0(\gen_mux_rd[4].mux_rd_rise0_r[4]_i_2_n_0 ),
        .I1(\gen_mux_rd[4].mux_rd_rise0_r_reg[4]_2 ),
        .O(\rd_mux_sel_r_reg[2]_49 ),
        .S(\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[4].mux_rd_rise1_r[4]_i_2 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ),
        .I3(\gen_mux_rd[4].mux_rd_rise1_r_reg[4] ),
        .I4(\gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0 ),
        .I5(\gen_mux_rd[4].mux_rd_rise1_r_reg[4]_1 ),
        .O(\gen_mux_rd[4].mux_rd_rise1_r[4]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_i_1 
       (.I0(\gen_mux_rd[4].mux_rd_rise1_r[4]_i_2_n_0 ),
        .I1(\gen_mux_rd[4].mux_rd_rise1_r_reg[4]_2 ),
        .O(\rd_mux_sel_r_reg[2]_54 ),
        .S(\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[4].mux_rd_rise2_r[4]_i_2 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ),
        .I3(\gen_mux_rd[4].mux_rd_rise2_r_reg[4] ),
        .I4(\gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0 ),
        .I5(\gen_mux_rd[4].mux_rd_rise2_r_reg[4]_1 ),
        .O(\gen_mux_rd[4].mux_rd_rise2_r[4]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_i_1 
       (.I0(\gen_mux_rd[4].mux_rd_rise2_r[4]_i_2_n_0 ),
        .I1(\gen_mux_rd[4].mux_rd_rise2_r_reg[4]_2 ),
        .O(\rd_mux_sel_r_reg[2]_58 ),
        .S(\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[4].mux_rd_rise3_r[4]_i_2 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ),
        .I3(\gen_mux_rd[4].mux_rd_rise3_r_reg[4] ),
        .I4(\gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0 ),
        .I5(\gen_mux_rd[4].mux_rd_rise3_r_reg[4]_1 ),
        .O(\gen_mux_rd[4].mux_rd_rise3_r[4]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_i_1 
       (.I0(\gen_mux_rd[4].mux_rd_rise3_r[4]_i_2_n_0 ),
        .I1(\gen_mux_rd[4].mux_rd_rise3_r_reg[4]_2 ),
        .O(\rd_mux_sel_r_reg[2]_62 ),
        .S(\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[5].mux_rd_fall0_r[5]_i_2 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ),
        .I3(\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ),
        .I4(\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ),
        .I5(\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 ),
        .O(\gen_mux_rd[5].mux_rd_fall0_r[5]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_i_1 
       (.I0(\gen_mux_rd[5].mux_rd_fall0_r[5]_i_2_n_0 ),
        .I1(\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_2 ),
        .O(\rd_mux_sel_r_reg[2]_7 ),
        .S(\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[5].mux_rd_fall1_r[5]_i_2 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ),
        .I3(\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ),
        .I4(\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ),
        .I5(\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 ),
        .O(\gen_mux_rd[5].mux_rd_fall1_r[5]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_i_1 
       (.I0(\gen_mux_rd[5].mux_rd_fall1_r[5]_i_2_n_0 ),
        .I1(\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_2 ),
        .O(\rd_mux_sel_r_reg[2]_18 ),
        .S(\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[5].mux_rd_fall2_r[5]_i_2 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ),
        .I3(\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ),
        .I4(\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ),
        .I5(\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 ),
        .O(\gen_mux_rd[5].mux_rd_fall2_r[5]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_i_1 
       (.I0(\gen_mux_rd[5].mux_rd_fall2_r[5]_i_2_n_0 ),
        .I1(\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_2 ),
        .O(\rd_mux_sel_r_reg[2]_31 ),
        .S(\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[5].mux_rd_fall3_r[5]_i_2 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ),
        .I3(\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ),
        .I4(\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ),
        .I5(\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 ),
        .O(\gen_mux_rd[5].mux_rd_fall3_r[5]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_i_1 
       (.I0(\gen_mux_rd[5].mux_rd_fall3_r[5]_i_2_n_0 ),
        .I1(\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_2 ),
        .O(\rd_mux_sel_r_reg[2]_45 ),
        .S(\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[5].mux_rd_rise0_r[5]_i_2 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ),
        .I3(\gen_mux_rd[5].mux_rd_rise0_r_reg[5] ),
        .I4(\gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0 ),
        .I5(\gen_mux_rd[5].mux_rd_rise0_r_reg[5]_1 ),
        .O(\gen_mux_rd[5].mux_rd_rise0_r[5]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_i_1 
       (.I0(\gen_mux_rd[5].mux_rd_rise0_r[5]_i_2_n_0 ),
        .I1(\gen_mux_rd[5].mux_rd_rise0_r_reg[5]_2 ),
        .O(\rd_mux_sel_r_reg[2]_2 ),
        .S(\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[5].mux_rd_rise1_r[5]_i_2 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ),
        .I3(\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ),
        .I4(\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ),
        .I5(\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 ),
        .O(\gen_mux_rd[5].mux_rd_rise1_r[5]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_i_1 
       (.I0(\gen_mux_rd[5].mux_rd_rise1_r[5]_i_2_n_0 ),
        .I1(\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_2 ),
        .O(\rd_mux_sel_r_reg[2]_13 ),
        .S(\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[5].mux_rd_rise2_r[5]_i_2 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ),
        .I3(\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ),
        .I4(\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ),
        .I5(\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 ),
        .O(\gen_mux_rd[5].mux_rd_rise2_r[5]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_i_1 
       (.I0(\gen_mux_rd[5].mux_rd_rise2_r[5]_i_2_n_0 ),
        .I1(\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_2 ),
        .O(\rd_mux_sel_r_reg[2]_25 ),
        .S(\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[5].mux_rd_rise3_r[5]_i_2 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ),
        .I3(\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ),
        .I4(\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ),
        .I5(\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 ),
        .O(\gen_mux_rd[5].mux_rd_rise3_r[5]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_i_1 
       (.I0(\gen_mux_rd[5].mux_rd_rise3_r[5]_i_2_n_0 ),
        .I1(\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_2 ),
        .O(\rd_mux_sel_r_reg[2]_37 ),
        .S(\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[6].mux_rd_fall0_r[6]_i_2 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ),
        .I3(\gen_mux_rd[6].mux_rd_fall0_r_reg[6] ),
        .I4(\gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0 ),
        .I5(\gen_mux_rd[6].mux_rd_fall0_r_reg[6]_1 ),
        .O(\gen_mux_rd[6].mux_rd_fall0_r[6]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_i_1 
       (.I0(\gen_mux_rd[6].mux_rd_fall0_r[6]_i_2_n_0 ),
        .I1(\gen_mux_rd[6].mux_rd_fall0_r_reg[6]_2 ),
        .O(\rd_mux_sel_r_reg[2]_8 ),
        .S(\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[6].mux_rd_fall1_r[6]_i_2 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ),
        .I3(\gen_mux_rd[6].mux_rd_fall1_r_reg[6] ),
        .I4(\gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0 ),
        .I5(\gen_mux_rd[6].mux_rd_fall1_r_reg[6]_1 ),
        .O(\gen_mux_rd[6].mux_rd_fall1_r[6]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_i_1 
       (.I0(\gen_mux_rd[6].mux_rd_fall1_r[6]_i_2_n_0 ),
        .I1(\gen_mux_rd[6].mux_rd_fall1_r_reg[6]_2 ),
        .O(\rd_mux_sel_r_reg[2]_19 ),
        .S(\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[6].mux_rd_fall2_r[6]_i_2 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ),
        .I3(\gen_mux_rd[6].mux_rd_fall2_r_reg[6] ),
        .I4(\gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0 ),
        .I5(\gen_mux_rd[6].mux_rd_fall2_r_reg[6]_1 ),
        .O(\gen_mux_rd[6].mux_rd_fall2_r[6]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_i_1 
       (.I0(\gen_mux_rd[6].mux_rd_fall2_r[6]_i_2_n_0 ),
        .I1(\gen_mux_rd[6].mux_rd_fall2_r_reg[6]_2 ),
        .O(\rd_mux_sel_r_reg[2]_32 ),
        .S(\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[6].mux_rd_fall3_r[6]_i_2 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ),
        .I3(\gen_mux_rd[6].mux_rd_fall3_r_reg[6] ),
        .I4(\gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0 ),
        .I5(\gen_mux_rd[6].mux_rd_fall3_r_reg[6]_1 ),
        .O(\gen_mux_rd[6].mux_rd_fall3_r[6]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_i_1 
       (.I0(\gen_mux_rd[6].mux_rd_fall3_r[6]_i_2_n_0 ),
        .I1(\gen_mux_rd[6].mux_rd_fall3_r_reg[6]_2 ),
        .O(\rd_mux_sel_r_reg[2]_46 ),
        .S(\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[6].mux_rd_rise0_r[6]_i_2 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ),
        .I3(\gen_mux_rd[6].mux_rd_rise0_r_reg[6] ),
        .I4(\gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0 ),
        .I5(\gen_mux_rd[6].mux_rd_rise0_r_reg[6]_1 ),
        .O(\gen_mux_rd[6].mux_rd_rise0_r[6]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_i_1 
       (.I0(\gen_mux_rd[6].mux_rd_rise0_r[6]_i_2_n_0 ),
        .I1(\gen_mux_rd[6].mux_rd_rise0_r_reg[6]_2 ),
        .O(\rd_mux_sel_r_reg[2]_3 ),
        .S(\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[6].mux_rd_rise1_r[6]_i_2 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ),
        .I3(\gen_mux_rd[6].mux_rd_rise1_r_reg[6] ),
        .I4(\gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0 ),
        .I5(\gen_mux_rd[6].mux_rd_rise1_r_reg[6]_1 ),
        .O(\gen_mux_rd[6].mux_rd_rise1_r[6]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_i_1 
       (.I0(\gen_mux_rd[6].mux_rd_rise1_r[6]_i_2_n_0 ),
        .I1(\gen_mux_rd[6].mux_rd_rise1_r_reg[6]_2 ),
        .O(\rd_mux_sel_r_reg[2]_14 ),
        .S(\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[6].mux_rd_rise2_r[6]_i_2 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ),
        .I3(\gen_mux_rd[6].mux_rd_rise2_r_reg[6] ),
        .I4(\gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0 ),
        .I5(\gen_mux_rd[6].mux_rd_rise2_r_reg[6]_1 ),
        .O(\gen_mux_rd[6].mux_rd_rise2_r[6]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_i_1 
       (.I0(\gen_mux_rd[6].mux_rd_rise2_r[6]_i_2_n_0 ),
        .I1(\gen_mux_rd[6].mux_rd_rise2_r_reg[6]_2 ),
        .O(\rd_mux_sel_r_reg[2]_26 ),
        .S(\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[6].mux_rd_rise3_r[6]_i_2 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ),
        .I3(\gen_mux_rd[6].mux_rd_rise3_r_reg[6] ),
        .I4(\gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0 ),
        .I5(\gen_mux_rd[6].mux_rd_rise3_r_reg[6]_1 ),
        .O(\gen_mux_rd[6].mux_rd_rise3_r[6]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_i_1 
       (.I0(\gen_mux_rd[6].mux_rd_rise3_r[6]_i_2_n_0 ),
        .I1(\gen_mux_rd[6].mux_rd_rise3_r_reg[6]_2 ),
        .O(\rd_mux_sel_r_reg[2]_38 ),
        .S(\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[7].mux_rd_fall0_r[7]_i_2 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] ),
        .I3(\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ),
        .I4(\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ),
        .I5(\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 ),
        .O(\gen_mux_rd[7].mux_rd_fall0_r[7]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_i_1 
       (.I0(\gen_mux_rd[7].mux_rd_fall0_r[7]_i_2_n_0 ),
        .I1(\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_2 ),
        .O(\rd_mux_sel_r_reg[2]_9 ),
        .S(\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[7].mux_rd_fall1_r[7]_i_2 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] ),
        .I3(\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ),
        .I4(\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ),
        .I5(\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 ),
        .O(\gen_mux_rd[7].mux_rd_fall1_r[7]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_i_1 
       (.I0(\gen_mux_rd[7].mux_rd_fall1_r[7]_i_2_n_0 ),
        .I1(\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_2 ),
        .O(\rd_mux_sel_r_reg[2]_20 ),
        .S(\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[7].mux_rd_fall2_r[7]_i_2 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] ),
        .I3(\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ),
        .I4(\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ),
        .I5(\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 ),
        .O(\gen_mux_rd[7].mux_rd_fall2_r[7]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_i_1 
       (.I0(\gen_mux_rd[7].mux_rd_fall2_r[7]_i_2_n_0 ),
        .I1(\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_2 ),
        .O(\rd_mux_sel_r_reg[2]_33 ),
        .S(\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[7].mux_rd_fall3_r[7]_i_2 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ),
        .I3(\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ),
        .I4(\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ),
        .I5(\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 ),
        .O(\gen_mux_rd[7].mux_rd_fall3_r[7]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_i_1 
       (.I0(\gen_mux_rd[7].mux_rd_fall3_r[7]_i_2_n_0 ),
        .I1(\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_2 ),
        .O(\rd_mux_sel_r_reg[2]_47 ),
        .S(\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[7].mux_rd_rise0_r[7]_i_2 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ),
        .I3(\gen_mux_rd[7].mux_rd_rise0_r_reg[7] ),
        .I4(\gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0 ),
        .I5(\gen_mux_rd[7].mux_rd_rise0_r_reg[7]_1 ),
        .O(\gen_mux_rd[7].mux_rd_rise0_r[7]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_i_1 
       (.I0(\gen_mux_rd[7].mux_rd_rise0_r[7]_i_2_n_0 ),
        .I1(\gen_mux_rd[7].mux_rd_rise0_r_reg[7]_2 ),
        .O(\rd_mux_sel_r_reg[2]_4 ),
        .S(\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[7].mux_rd_rise1_r[7]_i_2 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] ),
        .I3(\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ),
        .I4(\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ),
        .I5(\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 ),
        .O(\gen_mux_rd[7].mux_rd_rise1_r[7]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_i_1 
       (.I0(\gen_mux_rd[7].mux_rd_rise1_r[7]_i_2_n_0 ),
        .I1(\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_2 ),
        .O(\rd_mux_sel_r_reg[2]_15 ),
        .S(\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[7].mux_rd_rise2_r[7]_i_2 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] ),
        .I3(\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ),
        .I4(\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ),
        .I5(\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 ),
        .O(\gen_mux_rd[7].mux_rd_rise2_r[7]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_i_1 
       (.I0(\gen_mux_rd[7].mux_rd_rise2_r[7]_i_2_n_0 ),
        .I1(\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_2 ),
        .O(\rd_mux_sel_r_reg[2]_27 ),
        .S(\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ));
  LUT6 #(
    .INIT(64'hFDB97531ECA86420)) 
    \gen_mux_rd[7].mux_rd_rise3_r[7]_i_2 
       (.I0(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [0]),
        .I1(\gen_mux_rd[0].mux_rd_rise0_r_reg[0] [1]),
        .I2(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] ),
        .I3(\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ),
        .I4(\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ),
        .I5(\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 ),
        .O(\gen_mux_rd[7].mux_rd_rise3_r[7]_i_2_n_0 ));
  MUXF7 \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_i_1 
       (.I0(\gen_mux_rd[7].mux_rd_rise3_r[7]_i_2_n_0 ),
        .I1(\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_2 ),
        .O(\rd_mux_sel_r_reg[2]_39 ),
        .S(\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "12" *) 
  (* ram_slice_end = "17" *) 
  RAM32M mem_reg_0_3_12_17
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[1:0]),
        .DIB(Q[3:2]),
        .DIC(Q[5:4]),
        .DID({1'b0,1'b0}),
        .DOA({mem_reg_0_3_12_17_n_0,mem_reg_0_3_12_17_n_1}),
        .DOB({mem_reg_0_3_12_17_n_2,mem_reg_0_3_12_17_n_3}),
        .DOC(mem_out[17:16]),
        .DOD(NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_reg[1]_0 ),
        .WE(wr_en));
  LUT4 #(
    .INIT(16'h0151)) 
    mem_reg_0_3_12_17_i_1__2
       (.I0(\wr_ptr_reg[0]_0 ),
        .I1(my_full[0]),
        .I2(\my_full_reg[1]_0 ),
        .I3(my_empty_0[2]),
        .O(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "18" *) 
  (* ram_slice_end = "23" *) 
  RAM32M mem_reg_0_3_18_23
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[7:6]),
        .DIB(Q[9:8]),
        .DIC(Q[11:10]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[19:18]),
        .DOB(mem_out[21:20]),
        .DOC(mem_out[23:22]),
        .DOD(NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "24" *) 
  (* ram_slice_end = "29" *) 
  RAM32M mem_reg_0_3_24_29
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[13:12]),
        .DIB(Q[15:14]),
        .DIC(Q[17:16]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[25:24]),
        .DOB(mem_out[27:26]),
        .DOC(mem_out[29:28]),
        .DOD(NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "30" *) 
  (* ram_slice_end = "35" *) 
  RAM32M mem_reg_0_3_30_35
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[19:18]),
        .DIB(Q[21:20]),
        .DIC(Q[23:22]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[31:30]),
        .DOB(mem_out[33:32]),
        .DOC(mem_out[35:34]),
        .DOD(NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "36" *) 
  (* ram_slice_end = "41" *) 
  RAM32M mem_reg_0_3_36_41
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[25:24]),
        .DIB(Q[27:26]),
        .DIC(Q[29:28]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[37:36]),
        .DOB(mem_out[39:38]),
        .DOC(mem_out[41:40]),
        .DOD(NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "42" *) 
  (* ram_slice_end = "47" *) 
  RAM32M mem_reg_0_3_42_47
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[31:30]),
        .DIB(Q[33:32]),
        .DIC(Q[35:34]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[43:42]),
        .DOB(mem_out[45:44]),
        .DOC(mem_out[47:46]),
        .DOD(NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "48" *) 
  (* ram_slice_end = "53" *) 
  RAM32M mem_reg_0_3_48_53
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[37:36]),
        .DIB(Q[39:38]),
        .DIC(Q[41:40]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[49:48]),
        .DOB(mem_out[51:50]),
        .DOC(mem_out[53:52]),
        .DOD(NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "54" *) 
  (* ram_slice_end = "59" *) 
  RAM32M mem_reg_0_3_54_59
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[43:42]),
        .DIB(Q[45:44]),
        .DIC(Q[47:46]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[55:54]),
        .DOB(mem_out[57:56]),
        .DOC(mem_out[59:58]),
        .DOD(NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "60" *) 
  (* ram_slice_end = "65" *) 
  RAM32M mem_reg_0_3_60_65
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[49:48]),
        .DIB(Q[51:50]),
        .DIC(Q[53:52]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[61:60]),
        .DOB(mem_out[63:62]),
        .DOC(mem_out[65:64]),
        .DOD(NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "66" *) 
  (* ram_slice_end = "71" *) 
  RAM32M mem_reg_0_3_66_71
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[55:54]),
        .DIB(Q[57:56]),
        .DIC(Q[59:58]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[67:66]),
        .DOB(mem_out[69:68]),
        .DOC(mem_out[71:70]),
        .DOD(NLW_mem_reg_0_3_66_71_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "72" *) 
  (* ram_slice_end = "77" *) 
  RAM32M mem_reg_0_3_72_77
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[61:60]),
        .DIB(Q[63:62]),
        .DIC(Q[65:64]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[73:72]),
        .DOB(mem_out[75:74]),
        .DOC(mem_out[77:76]),
        .DOD(NLW_mem_reg_0_3_72_77_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "78" *) 
  (* ram_slice_end = "79" *) 
  RAM32M mem_reg_0_3_78_79
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[67:66]),
        .DIB({1'b0,1'b0}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[79:78]),
        .DOB(NLW_mem_reg_0_3_78_79_DOB_UNCONNECTED[1:0]),
        .DOC(NLW_mem_reg_0_3_78_79_DOC_UNCONNECTED[1:0]),
        .DOD(NLW_mem_reg_0_3_78_79_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_reg[1]_0 ),
        .WE(wr_en));
  LUT4 #(
    .INIT(16'h0018)) 
    \my_empty[4]_i_1__4 
       (.I0(\my_full_reg[1]_0 ),
        .I1(\wr_ptr_reg[0]_0 ),
        .I2(my_empty_0[1]),
        .I3(my_full[1]),
        .O(\my_empty[4]_i_1__4_n_0 ));
  LUT5 #(
    .INIT(32'h00411400)) 
    \my_empty[4]_i_2__0 
       (.I0(my_empty_0[1]),
        .I1(wr_ptr[1]),
        .I2(rd_ptr[1]),
        .I3(rd_ptr[0]),
        .I4(wr_ptr[0]),
        .O(\my_empty[4]_i_2__0_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    my_empty_inst__3
       (.I0(\my_empty_reg[4]_rep_n_0 ),
        .O(my_empty_0[4]));
  (* SOFT_HLUTNM = "soft_lutpair745" *) 
  LUT1 #(
    .INIT(2'h2)) 
    my_empty_inst__4
       (.I0(\my_empty_reg[4]_0 ),
        .O(\my_empty_reg[4]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair745" *) 
  LUT1 #(
    .INIT(2'h2)) 
    my_empty_inst__5
       (.I0(\my_empty_reg[4]_0 ),
        .O(my_empty_0[2]));
  LUT1 #(
    .INIT(2'h2)) 
    my_empty_inst__6
       (.I0(\my_empty_reg[4]_0 ),
        .O(my_empty_0[1]));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  LUT1 #(
    .INIT(2'h2)) 
    my_empty_inst_rep__0
       (.I0(\my_empty_reg[4]_rep__0_n_0 ),
        .O(my_empty_inst_rep__0_n_0));
  (* ORIG_CELL_NAME = "my_empty_reg[4]" *) 
  FDSE \my_empty_reg[4] 
       (.C(\rd_ptr_reg[1]_0 ),
        .CE(\my_empty[4]_i_1__4_n_0 ),
        .D(\my_empty[4]_i_2__0_n_0 ),
        .Q(\my_empty_reg[4]_0 ),
        .S(ififo_rst));
  (* ORIG_CELL_NAME = "my_empty_reg[4]" *) 
  FDSE \my_empty_reg[4]_rep 
       (.C(\rd_ptr_reg[1]_0 ),
        .CE(\my_empty[4]_i_1__4_n_0 ),
        .D(\my_empty[4]_i_2__0_n_0 ),
        .Q(\my_empty_reg[4]_rep_n_0 ),
        .S(ififo_rst));
  (* ORIG_CELL_NAME = "my_empty_reg[4]" *) 
  FDSE \my_empty_reg[4]_rep__0 
       (.C(\rd_ptr_reg[1]_0 ),
        .CE(\my_empty[4]_i_1__4_n_0 ),
        .D(\my_empty[4]_i_2__0_n_0 ),
        .Q(\my_empty_reg[4]_rep__0_n_0 ),
        .S(ififo_rst));
  LUT6 #(
    .INIT(64'hAAAAEAABAAAA2AA8)) 
    \my_full[0]_i_1__0 
       (.I0(my_full[0]),
        .I1(\my_full_reg[1]_0 ),
        .I2(\wr_ptr_reg[0]_0 ),
        .I3(my_full[1]),
        .I4(my_empty_0[1]),
        .I5(\my_full[1]_i_2__0_n_0 ),
        .O(\my_full[0]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'hF0F1F070)) 
    \my_full[1]_i_1__0 
       (.I0(\my_full_reg[1]_0 ),
        .I1(\wr_ptr_reg[0]_0 ),
        .I2(my_full[1]),
        .I3(my_empty_0[1]),
        .I4(\my_full[1]_i_2__0_n_0 ),
        .O(\my_full[1]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'h00411400)) 
    \my_full[1]_i_2__0 
       (.I0(my_full[1]),
        .I1(rd_ptr[1]),
        .I2(wr_ptr[1]),
        .I3(wr_ptr[0]),
        .I4(rd_ptr[0]),
        .O(\my_full[1]_i_2__0_n_0 ));
  FDRE \my_full_reg[0] 
       (.C(\rd_ptr_reg[1]_0 ),
        .CE(1'b1),
        .D(\my_full[0]_i_1__0_n_0 ),
        .Q(my_full[0]),
        .R(ififo_rst));
  FDRE \my_full_reg[1] 
       (.C(\rd_ptr_reg[1]_0 ),
        .CE(1'b1),
        .D(\my_full[1]_i_1__0_n_0 ),
        .Q(my_full[1]),
        .R(ififo_rst));
  (* SOFT_HLUTNM = "soft_lutpair712" *) 
  LUT3 #(
    .INIT(8'hD2)) 
    \rd_ptr[0]_i_1__0 
       (.I0(\my_full_reg[1]_0 ),
        .I1(my_empty_0[1]),
        .I2(rd_ptr[0]),
        .O(\rd_ptr[0]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair712" *) 
  LUT4 #(
    .INIT(16'hF708)) 
    \rd_ptr[1]_i_1__0 
       (.I0(rd_ptr[0]),
        .I1(\my_full_reg[1]_0 ),
        .I2(my_empty_0[1]),
        .I3(rd_ptr[1]),
        .O(\rd_ptr[1]_i_1__0_n_0 ));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[0] 
       (.C(\rd_ptr_reg[1]_0 ),
        .CE(1'b1),
        .D(\rd_ptr[0]_i_1__0_n_0 ),
        .Q(rd_ptr[0]),
        .R(ififo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[1] 
       (.C(\rd_ptr_reg[1]_0 ),
        .CE(1'b1),
        .D(\rd_ptr[1]_i_1__0_n_0 ),
        .Q(rd_ptr[1]),
        .R(ififo_rst));
  LUT4 #(
    .INIT(16'hF704)) 
    \rd_ptr_timing[0]_i_1__2 
       (.I0(rd_ptr[0]),
        .I1(\my_full_reg[1]_0 ),
        .I2(my_empty_0[1]),
        .I3(rd_ptr_timing[0]),
        .O(\rd_ptr_timing[0]_i_1__2_n_0 ));
  LUT5 #(
    .INIT(32'hFF6F0060)) 
    \rd_ptr_timing[1]_i_1__2 
       (.I0(rd_ptr[0]),
        .I1(rd_ptr[1]),
        .I2(\my_full_reg[1]_0 ),
        .I3(my_empty_0[1]),
        .I4(rd_ptr_timing[1]),
        .O(\rd_ptr_timing[1]_i_1__2_n_0 ));
  (* KEEP = "yes" *) 
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_timing_reg[0] 
       (.C(\rd_ptr_reg[1]_0 ),
        .CE(1'b1),
        .D(\rd_ptr_timing[0]_i_1__2_n_0 ),
        .Q(rd_ptr_timing[0]),
        .R(ififo_rst));
  (* KEEP = "yes" *) 
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_timing_reg[1] 
       (.C(\rd_ptr_reg[1]_0 ),
        .CE(1'b1),
        .D(\rd_ptr_timing[1]_i_1__2_n_0 ),
        .Q(rd_ptr_timing[1]),
        .R(ififo_rst));
  LUT5 #(
    .INIT(32'hFECE0131)) 
    \wr_ptr[0]_i_1__2 
       (.I0(my_full[1]),
        .I1(\wr_ptr_reg[0]_0 ),
        .I2(\my_full_reg[1]_0 ),
        .I3(my_empty_0[1]),
        .I4(wr_ptr[0]),
        .O(\wr_ptr[0]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFDF5FD00020A02)) 
    \wr_ptr[1]_i_1__2 
       (.I0(wr_ptr[0]),
        .I1(my_full[1]),
        .I2(\wr_ptr_reg[0]_0 ),
        .I3(\my_full_reg[1]_0 ),
        .I4(my_empty_0[1]),
        .I5(wr_ptr[1]),
        .O(\wr_ptr[1]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair711" *) 
  LUT4 #(
    .INIT(16'hF888)) 
    \wr_ptr[1]_i_4__1 
       (.I0(\my_empty_reg[4]_1 ),
        .I1(\wr_ptr_reg[0]_0 ),
        .I2(my_empty),
        .I3(\wr_ptr[1]_i_2__0 ),
        .O(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ));
  (* SOFT_HLUTNM = "soft_lutpair711" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \wr_ptr[1]_i_7 
       (.I0(\wr_ptr_reg[0]_0 ),
        .I1(\my_empty_reg[4]_1 ),
        .O(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[0] 
       (.C(\rd_ptr_reg[1]_0 ),
        .CE(1'b1),
        .D(\wr_ptr[0]_i_1__2_n_0 ),
        .Q(wr_ptr[0]),
        .R(ififo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[1] 
       (.C(\rd_ptr_reg[1]_0 ),
        .CE(1'b1),
        .D(\wr_ptr[1]_i_1__2_n_0 ),
        .Q(wr_ptr[1]),
        .R(ififo_rst));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_if_post_fifo" *) 
module mig_mig_7series_v4_2_ddr_if_post_fifo_39
   (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ,
    if_empty,
    phy_rddata_en,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ,
    ififo_rst,
    \rd_ptr_timing_reg[1]_0 ,
    if_empty_r_0,
    my_empty,
    if_empty_r,
    \my_full_reg[1]_0 ,
    my_empty_0,
    \wr_ptr[1]_i_2 ,
    phy_if_empty_r_reg,
    if_empty_v,
    Q);
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  output if_empty;
  output phy_rddata_en;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ;
  input ififo_rst;
  input \rd_ptr_timing_reg[1]_0 ;
  input [0:0]if_empty_r_0;
  input [1:0]my_empty;
  input [0:0]if_empty_r;
  input \my_full_reg[1]_0 ;
  input [0:0]my_empty_0;
  input \wr_ptr[1]_i_2 ;
  input phy_if_empty_r_reg;
  input [0:0]if_empty_v;
  input [67:0]Q;

  wire [67:0]Q;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ;
  wire if_empty;
  wire [0:0]if_empty_r;
  wire [0:0]if_empty_r_0;
  wire [0:0]if_empty_v;
  wire ififo_rst;
  wire [79:8]mem_out;
  wire mem_reg_0_3_60_65_n_4;
  wire mem_reg_0_3_60_65_n_5;
  wire mem_reg_0_3_6_11_n_0;
  wire mem_reg_0_3_6_11_n_1;
  wire [1:0]my_empty;
  wire \my_empty[4]_i_1__3_n_0 ;
  wire \my_empty[4]_i_2_n_0 ;
  wire [0:0]my_empty_0;
  wire [4:0]my_empty_1;
  wire my_empty_inst_rep_n_0;
  wire \my_empty_reg[4]_rep__0_n_0 ;
  wire \my_empty_reg[4]_rep_n_0 ;
  wire [1:0]my_full;
  wire \my_full[0]_i_1_n_0 ;
  wire \my_full[1]_i_1_n_0 ;
  wire \my_full[1]_i_2_n_0 ;
  wire \my_full_reg[1]_0 ;
  wire phy_if_empty_r_reg;
  wire phy_rddata_en;
  wire [1:0]rd_ptr;
  wire \rd_ptr[0]_i_1_n_0 ;
  wire \rd_ptr[1]_i_1_n_0 ;
  (* RTL_KEEP = "true" *) (* syn_maxfan = "10" *) wire [1:0]rd_ptr_timing;
  wire \rd_ptr_timing[0]_i_1__0_n_0 ;
  wire \rd_ptr_timing[1]_i_1__0_n_0 ;
  wire \rd_ptr_timing_reg[1]_0 ;
  (* MAX_FANOUT = "40" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire wr_en;
  wire [1:0]wr_ptr;
  wire \wr_ptr[0]_i_1__0_n_0 ;
  wire \wr_ptr[1]_i_1__0_n_0 ;
  wire \wr_ptr[1]_i_2 ;
  wire [1:0]NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_6_11_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_72_77_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_78_79_DOB_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_78_79_DOC_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_3_78_79_DOD_UNCONNECTED;

  (* SOFT_HLUTNM = "soft_lutpair690" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[100]_INST_0 
       (.I0(Q[35]),
        .I1(my_empty_1[4]),
        .I2(mem_out[41]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ));
  (* SOFT_HLUTNM = "soft_lutpair687" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[101]_INST_0 
       (.I0(Q[43]),
        .I1(my_empty_1[4]),
        .I2(mem_out[49]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ));
  (* SOFT_HLUTNM = "soft_lutpair677" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[102]_INST_0 
       (.I0(Q[51]),
        .I1(my_empty_1[4]),
        .I2(mem_out[57]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ));
  (* SOFT_HLUTNM = "soft_lutpair685" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[103]_INST_0 
       (.I0(Q[61]),
        .I1(my_empty_1[4]),
        .I2(mem_out[73]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] ));
  (* SOFT_HLUTNM = "soft_lutpair678" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[160]_INST_0 
       (.I0(Q[4]),
        .I1(my_empty_inst_rep_n_0),
        .I2(mem_out[10]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ));
  (* SOFT_HLUTNM = "soft_lutpair673" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[161]_INST_0 
       (.I0(Q[12]),
        .I1(my_empty_inst_rep_n_0),
        .I2(mem_out[18]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ));
  (* SOFT_HLUTNM = "soft_lutpair667" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[162]_INST_0 
       (.I0(Q[20]),
        .I1(my_empty_inst_rep_n_0),
        .I2(mem_out[26]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ));
  (* SOFT_HLUTNM = "soft_lutpair676" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[163]_INST_0 
       (.I0(Q[28]),
        .I1(my_empty_inst_rep_n_0),
        .I2(mem_out[34]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ));
  (* SOFT_HLUTNM = "soft_lutpair671" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[164]_INST_0 
       (.I0(Q[36]),
        .I1(my_empty_1[4]),
        .I2(mem_out[42]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ));
  (* SOFT_HLUTNM = "soft_lutpair666" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[165]_INST_0 
       (.I0(Q[44]),
        .I1(my_empty_1[4]),
        .I2(mem_out[50]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ));
  (* SOFT_HLUTNM = "soft_lutpair674" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[166]_INST_0 
       (.I0(Q[52]),
        .I1(my_empty_1[4]),
        .I2(mem_out[58]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ));
  (* SOFT_HLUTNM = "soft_lutpair665" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[167]_INST_0 
       (.I0(Q[62]),
        .I1(my_empty_1[4]),
        .I2(mem_out[74]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] ));
  (* SOFT_HLUTNM = "soft_lutpair693" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[224]_INST_0 
       (.I0(Q[5]),
        .I1(my_empty_inst_rep_n_0),
        .I2(mem_out[11]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ));
  (* SOFT_HLUTNM = "soft_lutpair692" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[225]_INST_0 
       (.I0(Q[13]),
        .I1(my_empty_inst_rep_n_0),
        .I2(mem_out[19]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ));
  (* SOFT_HLUTNM = "soft_lutpair683" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[226]_INST_0 
       (.I0(Q[21]),
        .I1(my_empty_inst_rep_n_0),
        .I2(mem_out[27]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ));
  (* SOFT_HLUTNM = "soft_lutpair689" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[227]_INST_0 
       (.I0(Q[29]),
        .I1(my_empty_inst_rep_n_0),
        .I2(mem_out[35]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ));
  (* SOFT_HLUTNM = "soft_lutpair690" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[228]_INST_0 
       (.I0(Q[37]),
        .I1(my_empty_1[4]),
        .I2(mem_out[43]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ));
  (* SOFT_HLUTNM = "soft_lutpair680" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[229]_INST_0 
       (.I0(Q[45]),
        .I1(my_empty_1[4]),
        .I2(mem_out[51]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ));
  (* SOFT_HLUTNM = "soft_lutpair686" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[230]_INST_0 
       (.I0(Q[53]),
        .I1(my_empty_1[4]),
        .I2(mem_out[59]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ));
  (* SOFT_HLUTNM = "soft_lutpair677" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[231]_INST_0 
       (.I0(Q[63]),
        .I1(my_empty_1[4]),
        .I2(mem_out[75]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] ));
  (* SOFT_HLUTNM = "soft_lutpair673" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[288]_INST_0 
       (.I0(Q[6]),
        .I1(my_empty_inst_rep_n_0),
        .I2(mem_out[12]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ));
  (* SOFT_HLUTNM = "soft_lutpair668" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[289]_INST_0 
       (.I0(Q[14]),
        .I1(my_empty_inst_rep_n_0),
        .I2(mem_out[20]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ));
  (* SOFT_HLUTNM = "soft_lutpair676" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[290]_INST_0 
       (.I0(Q[22]),
        .I1(my_empty_inst_rep_n_0),
        .I2(mem_out[28]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ));
  (* SOFT_HLUTNM = "soft_lutpair669" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[291]_INST_0 
       (.I0(Q[30]),
        .I1(my_empty_inst_rep_n_0),
        .I2(mem_out[36]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ));
  (* SOFT_HLUTNM = "soft_lutpair666" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[292]_INST_0 
       (.I0(Q[38]),
        .I1(my_empty_1[4]),
        .I2(mem_out[44]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ));
  (* SOFT_HLUTNM = "soft_lutpair675" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[293]_INST_0 
       (.I0(Q[46]),
        .I1(my_empty_1[4]),
        .I2(mem_out[52]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ));
  (* SOFT_HLUTNM = "soft_lutpair670" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[294]_INST_0 
       (.I0(Q[54]),
        .I1(my_empty_1[4]),
        .I2(mem_out[60]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ));
  (* SOFT_HLUTNM = "soft_lutpair674" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[295]_INST_0 
       (.I0(Q[64]),
        .I1(my_empty_1[4]),
        .I2(mem_out[76]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] ));
  (* SOFT_HLUTNM = "soft_lutpair669" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[32]_INST_0 
       (.I0(Q[2]),
        .I1(my_empty_inst_rep_n_0),
        .I2(mem_out[8]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ));
  (* SOFT_HLUTNM = "soft_lutpair662" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[33]_INST_0 
       (.I0(Q[10]),
        .I1(my_empty_inst_rep_n_0),
        .I2(mem_out[16]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ));
  (* SOFT_HLUTNM = "soft_lutpair672" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[34]_INST_0 
       (.I0(Q[18]),
        .I1(my_empty_inst_rep_n_0),
        .I2(mem_out[24]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ));
  (* SOFT_HLUTNM = "soft_lutpair693" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[352]_INST_0 
       (.I0(Q[7]),
        .I1(my_empty_inst_rep_n_0),
        .I2(mem_out[13]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ));
  (* SOFT_HLUTNM = "soft_lutpair683" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[353]_INST_0 
       (.I0(Q[15]),
        .I1(my_empty_inst_rep_n_0),
        .I2(mem_out[21]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ));
  (* SOFT_HLUTNM = "soft_lutpair691" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[354]_INST_0 
       (.I0(Q[23]),
        .I1(my_empty_inst_rep_n_0),
        .I2(mem_out[29]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ));
  (* SOFT_HLUTNM = "soft_lutpair688" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[355]_INST_0 
       (.I0(Q[31]),
        .I1(my_empty_inst_rep_n_0),
        .I2(mem_out[37]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ));
  (* SOFT_HLUTNM = "soft_lutpair681" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[356]_INST_0 
       (.I0(Q[39]),
        .I1(my_empty_1[4]),
        .I2(mem_out[45]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ));
  (* SOFT_HLUTNM = "soft_lutpair680" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[357]_INST_0 
       (.I0(Q[47]),
        .I1(my_empty_1[4]),
        .I2(mem_out[53]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ));
  (* SOFT_HLUTNM = "soft_lutpair686" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[358]_INST_0 
       (.I0(Q[55]),
        .I1(my_empty_1[4]),
        .I2(mem_out[61]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ));
  (* SOFT_HLUTNM = "soft_lutpair685" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[359]_INST_0 
       (.I0(Q[65]),
        .I1(my_empty_1[4]),
        .I2(mem_out[77]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] ));
  (* SOFT_HLUTNM = "soft_lutpair667" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[35]_INST_0 
       (.I0(Q[26]),
        .I1(my_empty_inst_rep_n_0),
        .I2(mem_out[32]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ));
  (* SOFT_HLUTNM = "soft_lutpair664" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[36]_INST_0 
       (.I0(Q[34]),
        .I1(my_empty_1[4]),
        .I2(mem_out[40]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ));
  (* SOFT_HLUTNM = "soft_lutpair664" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[37]_INST_0 
       (.I0(Q[42]),
        .I1(my_empty_1[4]),
        .I2(mem_out[48]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ));
  (* SOFT_HLUTNM = "soft_lutpair663" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[38]_INST_0 
       (.I0(Q[50]),
        .I1(my_empty_1[4]),
        .I2(mem_out[56]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ));
  (* SOFT_HLUTNM = "soft_lutpair663" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[39]_INST_0 
       (.I0(Q[60]),
        .I1(my_empty_1[4]),
        .I2(mem_out[72]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ));
  (* SOFT_HLUTNM = "soft_lutpair668" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[416]_INST_0 
       (.I0(Q[8]),
        .I1(my_empty_inst_rep_n_0),
        .I2(mem_out[14]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ));
  (* SOFT_HLUTNM = "soft_lutpair678" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[417]_INST_0 
       (.I0(Q[16]),
        .I1(my_empty_inst_rep_n_0),
        .I2(mem_out[22]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ));
  (* SOFT_HLUTNM = "soft_lutpair672" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[418]_INST_0 
       (.I0(Q[24]),
        .I1(my_empty_inst_rep_n_0),
        .I2(mem_out[30]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ));
  (* SOFT_HLUTNM = "soft_lutpair662" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[419]_INST_0 
       (.I0(Q[32]),
        .I1(my_empty_inst_rep_n_0),
        .I2(mem_out[38]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ));
  (* SOFT_HLUTNM = "soft_lutpair675" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[420]_INST_0 
       (.I0(Q[40]),
        .I1(my_empty_1[4]),
        .I2(mem_out[46]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ));
  (* SOFT_HLUTNM = "soft_lutpair671" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[421]_INST_0 
       (.I0(Q[48]),
        .I1(my_empty_1[4]),
        .I2(mem_out[54]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ));
  (* SOFT_HLUTNM = "soft_lutpair665" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[422]_INST_0 
       (.I0(Q[56]),
        .I1(my_empty_1[4]),
        .I2(mem_out[62]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ));
  (* SOFT_HLUTNM = "soft_lutpair670" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[423]_INST_0 
       (.I0(Q[66]),
        .I1(my_empty_1[4]),
        .I2(mem_out[78]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] ));
  (* SOFT_HLUTNM = "soft_lutpair684" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[480]_INST_0 
       (.I0(Q[9]),
        .I1(my_empty_inst_rep_n_0),
        .I2(mem_out[15]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ));
  (* SOFT_HLUTNM = "soft_lutpair689" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[481]_INST_0 
       (.I0(Q[17]),
        .I1(my_empty_inst_rep_n_0),
        .I2(mem_out[23]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ));
  (* SOFT_HLUTNM = "soft_lutpair691" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[482]_INST_0 
       (.I0(Q[25]),
        .I1(my_empty_inst_rep_n_0),
        .I2(mem_out[31]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ));
  (* SOFT_HLUTNM = "soft_lutpair682" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[483]_INST_0 
       (.I0(Q[33]),
        .I1(my_empty_inst_rep_n_0),
        .I2(mem_out[39]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ));
  (* SOFT_HLUTNM = "soft_lutpair687" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[484]_INST_0 
       (.I0(Q[41]),
        .I1(my_empty_1[4]),
        .I2(mem_out[47]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ));
  (* SOFT_HLUTNM = "soft_lutpair679" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[485]_INST_0 
       (.I0(Q[49]),
        .I1(my_empty_1[4]),
        .I2(mem_out[55]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ));
  (* SOFT_HLUTNM = "soft_lutpair679" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[486]_INST_0 
       (.I0(Q[57]),
        .I1(my_empty_1[4]),
        .I2(mem_out[63]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ));
  (* SOFT_HLUTNM = "soft_lutpair681" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[487]_INST_0 
       (.I0(Q[67]),
        .I1(my_empty_1[4]),
        .I2(mem_out[79]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ));
  (* SOFT_HLUTNM = "soft_lutpair684" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[96]_INST_0 
       (.I0(Q[3]),
        .I1(my_empty_inst_rep_n_0),
        .I2(mem_out[9]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ));
  (* SOFT_HLUTNM = "soft_lutpair692" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[97]_INST_0 
       (.I0(Q[11]),
        .I1(my_empty_inst_rep_n_0),
        .I2(mem_out[17]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ));
  (* SOFT_HLUTNM = "soft_lutpair688" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[98]_INST_0 
       (.I0(Q[19]),
        .I1(my_empty_inst_rep_n_0),
        .I2(mem_out[25]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ));
  (* SOFT_HLUTNM = "soft_lutpair682" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \app_rd_data[99]_INST_0 
       (.I0(Q[27]),
        .I1(my_empty_inst_rep_n_0),
        .I2(mem_out[33]),
        .O(\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "12" *) 
  (* ram_slice_end = "17" *) 
  RAM32M mem_reg_0_3_12_17
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[7:6]),
        .DIB(Q[9:8]),
        .DIC(Q[11:10]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[13:12]),
        .DOB(mem_out[15:14]),
        .DOC(mem_out[17:16]),
        .DOD(NLW_mem_reg_0_3_12_17_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_timing_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "18" *) 
  (* ram_slice_end = "23" *) 
  RAM32M mem_reg_0_3_18_23
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[13:12]),
        .DIB(Q[15:14]),
        .DIC(Q[17:16]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[19:18]),
        .DOB(mem_out[21:20]),
        .DOC(mem_out[23:22]),
        .DOD(NLW_mem_reg_0_3_18_23_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_timing_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "24" *) 
  (* ram_slice_end = "29" *) 
  RAM32M mem_reg_0_3_24_29
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[19:18]),
        .DIB(Q[21:20]),
        .DIC(Q[23:22]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[25:24]),
        .DOB(mem_out[27:26]),
        .DOC(mem_out[29:28]),
        .DOD(NLW_mem_reg_0_3_24_29_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_timing_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "30" *) 
  (* ram_slice_end = "35" *) 
  RAM32M mem_reg_0_3_30_35
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[25:24]),
        .DIB(Q[27:26]),
        .DIC(Q[29:28]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[31:30]),
        .DOB(mem_out[33:32]),
        .DOC(mem_out[35:34]),
        .DOD(NLW_mem_reg_0_3_30_35_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_timing_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "36" *) 
  (* ram_slice_end = "41" *) 
  RAM32M mem_reg_0_3_36_41
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[31:30]),
        .DIB(Q[33:32]),
        .DIC(Q[35:34]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[37:36]),
        .DOB(mem_out[39:38]),
        .DOC(mem_out[41:40]),
        .DOD(NLW_mem_reg_0_3_36_41_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_timing_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "42" *) 
  (* ram_slice_end = "47" *) 
  RAM32M mem_reg_0_3_42_47
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[37:36]),
        .DIB(Q[39:38]),
        .DIC(Q[41:40]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[43:42]),
        .DOB(mem_out[45:44]),
        .DOC(mem_out[47:46]),
        .DOD(NLW_mem_reg_0_3_42_47_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_timing_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "48" *) 
  (* ram_slice_end = "53" *) 
  RAM32M mem_reg_0_3_48_53
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[43:42]),
        .DIB(Q[45:44]),
        .DIC(Q[47:46]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[49:48]),
        .DOB(mem_out[51:50]),
        .DOC(mem_out[53:52]),
        .DOD(NLW_mem_reg_0_3_48_53_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_timing_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "54" *) 
  (* ram_slice_end = "59" *) 
  RAM32M mem_reg_0_3_54_59
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[49:48]),
        .DIB(Q[51:50]),
        .DIC(Q[53:52]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[55:54]),
        .DOB(mem_out[57:56]),
        .DOC(mem_out[59:58]),
        .DOD(NLW_mem_reg_0_3_54_59_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_timing_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "60" *) 
  (* ram_slice_end = "65" *) 
  RAM32M mem_reg_0_3_60_65
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[55:54]),
        .DIB(Q[57:56]),
        .DIC(Q[59:58]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[61:60]),
        .DOB(mem_out[63:62]),
        .DOC({mem_reg_0_3_60_65_n_4,mem_reg_0_3_60_65_n_5}),
        .DOD(NLW_mem_reg_0_3_60_65_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_timing_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "6" *) 
  (* ram_slice_end = "11" *) 
  RAM32M mem_reg_0_3_6_11
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[1:0]),
        .DIB(Q[3:2]),
        .DIC(Q[5:4]),
        .DID({1'b0,1'b0}),
        .DOA({mem_reg_0_3_6_11_n_0,mem_reg_0_3_6_11_n_1}),
        .DOB(mem_out[9:8]),
        .DOC(mem_out[11:10]),
        .DOD(NLW_mem_reg_0_3_6_11_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_timing_reg[1]_0 ),
        .WE(wr_en));
  LUT4 #(
    .INIT(16'h0151)) 
    mem_reg_0_3_6_11_i_1__0
       (.I0(if_empty_r_0),
        .I1(my_full[0]),
        .I2(\my_full_reg[1]_0 ),
        .I3(my_empty_1[2]),
        .O(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "72" *) 
  (* ram_slice_end = "77" *) 
  RAM32M mem_reg_0_3_72_77
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[61:60]),
        .DIB(Q[63:62]),
        .DIC(Q[65:64]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[73:72]),
        .DOB(mem_out[75:74]),
        .DOC(mem_out[77:76]),
        .DOD(NLW_mem_reg_0_3_72_77_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_timing_reg[1]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "320" *) 
  (* RTL_RAM_NAME = "dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "3" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "78" *) 
  (* ram_slice_end = "79" *) 
  RAM32M mem_reg_0_3_78_79
       (.ADDRA({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRB({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRC({1'b0,1'b0,1'b0,rd_ptr_timing}),
        .ADDRD({1'b0,1'b0,1'b0,wr_ptr}),
        .DIA(Q[67:66]),
        .DIB({1'b0,1'b0}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[79:78]),
        .DOB(NLW_mem_reg_0_3_78_79_DOB_UNCONNECTED[1:0]),
        .DOC(NLW_mem_reg_0_3_78_79_DOC_UNCONNECTED[1:0]),
        .DOD(NLW_mem_reg_0_3_78_79_DOD_UNCONNECTED[1:0]),
        .WCLK(\rd_ptr_timing_reg[1]_0 ),
        .WE(wr_en));
  LUT4 #(
    .INIT(16'h0018)) 
    \my_empty[4]_i_1__3 
       (.I0(\my_full_reg[1]_0 ),
        .I1(if_empty_r_0),
        .I2(my_empty_1[1]),
        .I3(my_full[1]),
        .O(\my_empty[4]_i_1__3_n_0 ));
  LUT5 #(
    .INIT(32'h00411400)) 
    \my_empty[4]_i_2 
       (.I0(my_empty_1[1]),
        .I1(wr_ptr[1]),
        .I2(rd_ptr[1]),
        .I3(rd_ptr[0]),
        .I4(wr_ptr[0]),
        .O(\my_empty[4]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h2)) 
    my_empty_inst
       (.I0(\my_empty_reg[4]_rep_n_0 ),
        .O(my_empty_1[4]));
  (* SOFT_HLUTNM = "soft_lutpair694" *) 
  LUT1 #(
    .INIT(2'h2)) 
    my_empty_inst__0
       (.I0(my_empty_1[0]),
        .O(my_empty_1[3]));
  LUT1 #(
    .INIT(2'h2)) 
    my_empty_inst__1
       (.I0(my_empty_1[0]),
        .O(my_empty_1[2]));
  (* SOFT_HLUTNM = "soft_lutpair694" *) 
  LUT1 #(
    .INIT(2'h2)) 
    my_empty_inst__2
       (.I0(my_empty_1[0]),
        .O(my_empty_1[1]));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  LUT1 #(
    .INIT(2'h2)) 
    my_empty_inst_rep
       (.I0(\my_empty_reg[4]_rep__0_n_0 ),
        .O(my_empty_inst_rep_n_0));
  (* ORIG_CELL_NAME = "my_empty_reg[4]" *) 
  FDSE \my_empty_reg[4] 
       (.C(\rd_ptr_timing_reg[1]_0 ),
        .CE(\my_empty[4]_i_1__3_n_0 ),
        .D(\my_empty[4]_i_2_n_0 ),
        .Q(my_empty_1[0]),
        .S(ififo_rst));
  (* ORIG_CELL_NAME = "my_empty_reg[4]" *) 
  FDSE \my_empty_reg[4]_rep 
       (.C(\rd_ptr_timing_reg[1]_0 ),
        .CE(\my_empty[4]_i_1__3_n_0 ),
        .D(\my_empty[4]_i_2_n_0 ),
        .Q(\my_empty_reg[4]_rep_n_0 ),
        .S(ififo_rst));
  (* ORIG_CELL_NAME = "my_empty_reg[4]" *) 
  FDSE \my_empty_reg[4]_rep__0 
       (.C(\rd_ptr_timing_reg[1]_0 ),
        .CE(\my_empty[4]_i_1__3_n_0 ),
        .D(\my_empty[4]_i_2_n_0 ),
        .Q(\my_empty_reg[4]_rep__0_n_0 ),
        .S(ififo_rst));
  LUT6 #(
    .INIT(64'hAAAAEAABAAAA2AA8)) 
    \my_full[0]_i_1 
       (.I0(my_full[0]),
        .I1(\my_full_reg[1]_0 ),
        .I2(if_empty_r_0),
        .I3(my_full[1]),
        .I4(my_empty_1[1]),
        .I5(\my_full[1]_i_2_n_0 ),
        .O(\my_full[0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hF0F1F070)) 
    \my_full[1]_i_1 
       (.I0(\my_full_reg[1]_0 ),
        .I1(if_empty_r_0),
        .I2(my_full[1]),
        .I3(my_empty_1[1]),
        .I4(\my_full[1]_i_2_n_0 ),
        .O(\my_full[1]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00411400)) 
    \my_full[1]_i_2 
       (.I0(my_full[1]),
        .I1(rd_ptr[1]),
        .I2(wr_ptr[1]),
        .I3(wr_ptr[0]),
        .I4(rd_ptr[0]),
        .O(\my_full[1]_i_2_n_0 ));
  FDRE \my_full_reg[0] 
       (.C(\rd_ptr_timing_reg[1]_0 ),
        .CE(1'b1),
        .D(\my_full[0]_i_1_n_0 ),
        .Q(my_full[0]),
        .R(ififo_rst));
  FDRE \my_full_reg[1] 
       (.C(\rd_ptr_timing_reg[1]_0 ),
        .CE(1'b1),
        .D(\my_full[1]_i_1_n_0 ),
        .Q(my_full[1]),
        .R(ififo_rst));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFEAEAEA)) 
    phy_if_empty_r_i_1
       (.I0(phy_if_empty_r_reg),
        .I1(if_empty_r_0),
        .I2(my_empty_1[0]),
        .I3(if_empty_r),
        .I4(my_empty[0]),
        .I5(if_empty_v),
        .O(if_empty));
  LUT1 #(
    .INIT(2'h1)) 
    rd_active_r_i_1
       (.I0(if_empty),
        .O(phy_rddata_en));
  (* SOFT_HLUTNM = "soft_lutpair661" *) 
  LUT3 #(
    .INIT(8'hD2)) 
    \rd_ptr[0]_i_1 
       (.I0(\my_full_reg[1]_0 ),
        .I1(my_empty_1[1]),
        .I2(rd_ptr[0]),
        .O(\rd_ptr[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair661" *) 
  LUT4 #(
    .INIT(16'hF708)) 
    \rd_ptr[1]_i_1 
       (.I0(rd_ptr[0]),
        .I1(\my_full_reg[1]_0 ),
        .I2(my_empty_1[1]),
        .I3(rd_ptr[1]),
        .O(\rd_ptr[1]_i_1_n_0 ));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[0] 
       (.C(\rd_ptr_timing_reg[1]_0 ),
        .CE(1'b1),
        .D(\rd_ptr[0]_i_1_n_0 ),
        .Q(rd_ptr[0]),
        .R(ififo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[1] 
       (.C(\rd_ptr_timing_reg[1]_0 ),
        .CE(1'b1),
        .D(\rd_ptr[1]_i_1_n_0 ),
        .Q(rd_ptr[1]),
        .R(ififo_rst));
  LUT4 #(
    .INIT(16'hF704)) 
    \rd_ptr_timing[0]_i_1__0 
       (.I0(rd_ptr[0]),
        .I1(\my_full_reg[1]_0 ),
        .I2(my_empty_1[1]),
        .I3(rd_ptr_timing[0]),
        .O(\rd_ptr_timing[0]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'hFF6F0060)) 
    \rd_ptr_timing[1]_i_1__0 
       (.I0(rd_ptr[0]),
        .I1(rd_ptr[1]),
        .I2(\my_full_reg[1]_0 ),
        .I3(my_empty_1[1]),
        .I4(rd_ptr_timing[1]),
        .O(\rd_ptr_timing[1]_i_1__0_n_0 ));
  (* KEEP = "yes" *) 
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_timing_reg[0] 
       (.C(\rd_ptr_timing_reg[1]_0 ),
        .CE(1'b1),
        .D(\rd_ptr_timing[0]_i_1__0_n_0 ),
        .Q(rd_ptr_timing[0]),
        .R(ififo_rst));
  (* KEEP = "yes" *) 
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_timing_reg[1] 
       (.C(\rd_ptr_timing_reg[1]_0 ),
        .CE(1'b1),
        .D(\rd_ptr_timing[1]_i_1__0_n_0 ),
        .Q(rd_ptr_timing[1]),
        .R(ififo_rst));
  LUT5 #(
    .INIT(32'hFECE0131)) 
    \wr_ptr[0]_i_1__0 
       (.I0(my_full[1]),
        .I1(if_empty_r_0),
        .I2(\my_full_reg[1]_0 ),
        .I3(my_empty_1[1]),
        .I4(wr_ptr[0]),
        .O(\wr_ptr[0]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFFDF5FD00020A02)) 
    \wr_ptr[1]_i_1__0 
       (.I0(wr_ptr[0]),
        .I1(my_full[1]),
        .I2(if_empty_r_0),
        .I3(\my_full_reg[1]_0 ),
        .I4(my_empty_1[1]),
        .I5(wr_ptr[1]),
        .O(\wr_ptr[1]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair660" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \wr_ptr[1]_i_3 
       (.I0(if_empty_r_0),
        .I1(my_empty_1[3]),
        .O(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ));
  LUT4 #(
    .INIT(16'hF888)) 
    \wr_ptr[1]_i_5__0 
       (.I0(my_empty_1[3]),
        .I1(if_empty_r_0),
        .I2(my_empty[1]),
        .I3(if_empty_r),
        .O(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ));
  (* SOFT_HLUTNM = "soft_lutpair660" *) 
  LUT4 #(
    .INIT(16'hF888)) 
    \wr_ptr[1]_i_8 
       (.I0(my_empty_1[3]),
        .I1(if_empty_r_0),
        .I2(my_empty_0),
        .I3(\wr_ptr[1]_i_2 ),
        .O(\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[0] 
       (.C(\rd_ptr_timing_reg[1]_0 ),
        .CE(1'b1),
        .D(\wr_ptr[0]_i_1__0_n_0 ),
        .Q(wr_ptr[0]),
        .R(ififo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[1] 
       (.C(\rd_ptr_timing_reg[1]_0 ),
        .CE(1'b1),
        .D(\wr_ptr[1]_i_1__0_n_0 ),
        .Q(wr_ptr[1]),
        .R(ififo_rst));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_mc_phy" *) 
module mig_mig_7series_v4_2_ddr_mc_phy
   (out_dqs_4,
    ts_dqs_4,
    A_rst_primitives_reg,
    mem_dq_out,
    mem_dq_ts,
    in0,
    idelay_ld_rst,
    out_dqs_5,
    ts_dqs_5,
    A_rst_primitives_reg_0,
    idelay_ld_rst_0,
    out_dqs_6,
    ts_dqs_6,
    A_rst_primitives_reg_1,
    idelay_ld_rst_1,
    out_dqs_7,
    ts_dqs_7,
    A_rst_primitives_reg_2,
    idelay_ld_rst_2,
    out_dqs_0,
    ts_dqs_0,
    A_rst_primitives_reg_3,
    idelay_ld_rst_3,
    out_dqs_1,
    ts_dqs_1,
    A_rst_primitives_reg_4,
    idelay_ld_rst_4,
    out_dqs_2,
    ts_dqs_2,
    A_rst_primitives_reg_5,
    idelay_ld_rst_5,
    out_dqs_3,
    ts_dqs_3,
    A_rst_primitives_reg_6,
    idelay_ld_rst_6,
    phy_mc_ctl_full,
    rst_tmp,
    if_empty,
    \my_empty_reg[1] ,
    phy_mc_data_full,
    \my_empty_reg[1]_0 ,
    \my_empty_reg[1]_1 ,
    \my_empty_reg[1]_2 ,
    A_rst_primitives_reg_7,
    \my_empty_reg[1]_3 ,
    \my_empty_reg[1]_4 ,
    \my_empty_reg[1]_5 ,
    \my_empty_reg[1]_6 ,
    \my_empty_reg[1]_7 ,
    \my_empty_reg[1]_8 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_6 ,
    \rd_mux_sel_r_reg[2] ,
    \rd_mux_sel_r_reg[2]_0 ,
    \rd_mux_sel_r_reg[2]_1 ,
    \rd_mux_sel_r_reg[2]_2 ,
    \rd_mux_sel_r_reg[2]_3 ,
    \rd_mux_sel_r_reg[2]_4 ,
    \rd_mux_sel_r_reg[2]_5 ,
    \rd_mux_sel_r_reg[2]_6 ,
    \rd_mux_sel_r_reg[2]_7 ,
    \rd_mux_sel_r_reg[2]_8 ,
    \rd_mux_sel_r_reg[2]_9 ,
    \rd_mux_sel_r_reg[2]_10 ,
    \rd_mux_sel_r_reg[2]_11 ,
    \rd_mux_sel_r_reg[2]_12 ,
    \rd_mux_sel_r_reg[2]_13 ,
    \rd_mux_sel_r_reg[2]_14 ,
    \rd_mux_sel_r_reg[2]_15 ,
    \rd_mux_sel_r_reg[2]_16 ,
    \rd_mux_sel_r_reg[2]_17 ,
    \rd_mux_sel_r_reg[2]_18 ,
    \rd_mux_sel_r_reg[2]_19 ,
    \rd_mux_sel_r_reg[2]_20 ,
    \rd_mux_sel_r_reg[2]_21 ,
    \rd_mux_sel_r_reg[2]_22 ,
    \rd_mux_sel_r_reg[2]_23 ,
    \rd_mux_sel_r_reg[2]_24 ,
    \rd_mux_sel_r_reg[2]_25 ,
    \rd_mux_sel_r_reg[2]_26 ,
    \rd_mux_sel_r_reg[2]_27 ,
    \rd_mux_sel_r_reg[2]_28 ,
    \rd_mux_sel_r_reg[2]_29 ,
    \rd_mux_sel_r_reg[2]_30 ,
    \rd_mux_sel_r_reg[2]_31 ,
    \rd_mux_sel_r_reg[2]_32 ,
    \rd_mux_sel_r_reg[2]_33 ,
    \rd_mux_sel_r_reg[2]_34 ,
    \rd_mux_sel_r_reg[2]_35 ,
    \rd_mux_sel_r_reg[2]_36 ,
    \rd_mux_sel_r_reg[2]_37 ,
    \rd_mux_sel_r_reg[2]_38 ,
    \rd_mux_sel_r_reg[2]_39 ,
    \rd_mux_sel_r_reg[2]_40 ,
    \rd_mux_sel_r_reg[2]_41 ,
    \rd_mux_sel_r_reg[2]_42 ,
    \rd_mux_sel_r_reg[2]_43 ,
    \rd_mux_sel_r_reg[2]_44 ,
    \rd_mux_sel_r_reg[2]_45 ,
    \rd_mux_sel_r_reg[2]_46 ,
    \rd_mux_sel_r_reg[2]_47 ,
    \rd_mux_sel_r_reg[2]_48 ,
    \rd_mux_sel_r_reg[2]_49 ,
    \rd_mux_sel_r_reg[2]_50 ,
    \rd_mux_sel_r_reg[2]_51 ,
    \rd_mux_sel_r_reg[2]_52 ,
    \rd_mux_sel_r_reg[2]_53 ,
    \rd_mux_sel_r_reg[2]_54 ,
    \rd_mux_sel_r_reg[2]_55 ,
    \rd_mux_sel_r_reg[2]_56 ,
    \rd_mux_sel_r_reg[2]_57 ,
    \rd_mux_sel_r_reg[2]_58 ,
    \rd_mux_sel_r_reg[2]_59 ,
    \rd_mux_sel_r_reg[2]_60 ,
    \rd_mux_sel_r_reg[2]_61 ,
    \rd_mux_sel_r_reg[2]_62 ,
    phy_rddata_en,
    \rd_ptr_reg[3] ,
    \rd_ptr_reg[3]_0 ,
    \rd_ptr_reg[3]_1 ,
    \rd_ptr_reg[3]_2 ,
    \pi_counter_read_val_reg[5] ,
    \rd_ptr_reg[3]_3 ,
    \rd_ptr_reg[3]_4 ,
    \rd_ptr_reg[3]_5 ,
    \rd_ptr_reg[3]_6 ,
    \pi_counter_read_val_reg[5]_0 ,
    mem_out,
    \rd_ptr_reg[3]_7 ,
    \mcGo_r_reg[15]_0 ,
    \rd_mux_sel_r_reg[2]_63 ,
    \rd_mux_sel_r_reg[2]_64 ,
    \rd_mux_sel_r_reg[2]_65 ,
    \rd_mux_sel_r_reg[2]_66 ,
    \rd_mux_sel_r_reg[2]_67 ,
    \rd_mux_sel_r_reg[2]_68 ,
    \rd_mux_sel_r_reg[2]_69 ,
    \rd_mux_sel_r_reg[2]_70 ,
    \rd_mux_sel_r_reg[2]_71 ,
    \rd_mux_sel_r_reg[2]_72 ,
    \rd_mux_sel_r_reg[2]_73 ,
    \rd_mux_sel_r_reg[2]_74 ,
    \rd_mux_sel_r_reg[2]_75 ,
    \rd_mux_sel_r_reg[2]_76 ,
    \rd_mux_sel_r_reg[2]_77 ,
    \rd_mux_sel_r_reg[2]_78 ,
    \rd_mux_sel_r_reg[2]_79 ,
    \rd_mux_sel_r_reg[2]_80 ,
    \rd_mux_sel_r_reg[2]_81 ,
    \rd_mux_sel_r_reg[2]_82 ,
    \rd_mux_sel_r_reg[2]_83 ,
    \rd_mux_sel_r_reg[2]_84 ,
    \rd_mux_sel_r_reg[2]_85 ,
    \rd_mux_sel_r_reg[2]_86 ,
    \rd_mux_sel_r_reg[2]_87 ,
    \rd_mux_sel_r_reg[2]_88 ,
    \rd_mux_sel_r_reg[2]_89 ,
    \rd_mux_sel_r_reg[2]_90 ,
    \rd_mux_sel_r_reg[2]_91 ,
    \rd_mux_sel_r_reg[2]_92 ,
    \rd_mux_sel_r_reg[2]_93 ,
    \rd_mux_sel_r_reg[2]_94 ,
    \rd_mux_sel_r_reg[2]_95 ,
    \rd_mux_sel_r_reg[2]_96 ,
    \rd_mux_sel_r_reg[2]_97 ,
    \rd_mux_sel_r_reg[2]_98 ,
    \rd_mux_sel_r_reg[2]_99 ,
    \rd_mux_sel_r_reg[2]_100 ,
    \rd_mux_sel_r_reg[2]_101 ,
    \rd_mux_sel_r_reg[2]_102 ,
    \rd_mux_sel_r_reg[2]_103 ,
    \rd_mux_sel_r_reg[2]_104 ,
    \rd_mux_sel_r_reg[2]_105 ,
    \rd_mux_sel_r_reg[2]_106 ,
    \rd_mux_sel_r_reg[2]_107 ,
    \rd_mux_sel_r_reg[2]_108 ,
    \rd_mux_sel_r_reg[2]_109 ,
    \rd_mux_sel_r_reg[2]_110 ,
    \rd_mux_sel_r_reg[2]_111 ,
    \rd_mux_sel_r_reg[2]_112 ,
    \rd_mux_sel_r_reg[2]_113 ,
    \rd_mux_sel_r_reg[2]_114 ,
    \rd_mux_sel_r_reg[2]_115 ,
    \rd_mux_sel_r_reg[2]_116 ,
    \rd_mux_sel_r_reg[2]_117 ,
    \rd_mux_sel_r_reg[2]_118 ,
    \rd_mux_sel_r_reg[2]_119 ,
    \rd_mux_sel_r_reg[2]_120 ,
    \rd_mux_sel_r_reg[2]_121 ,
    \rd_mux_sel_r_reg[2]_122 ,
    \rd_mux_sel_r_reg[2]_123 ,
    \rd_mux_sel_r_reg[2]_124 ,
    \rd_mux_sel_r_reg[2]_125 ,
    \rd_mux_sel_r_reg[2]_126 ,
    \po_counter_read_val_reg[0] ,
    \po_counter_read_val_reg[1] ,
    \po_counter_read_val_reg[2] ,
    \po_counter_read_val_reg[3] ,
    \po_counter_read_val_reg[4] ,
    \po_counter_read_val_reg[5] ,
    \po_counter_read_val_reg[6] ,
    \po_counter_read_val_reg[7] ,
    \po_counter_read_val_reg[8] ,
    p_0_out,
    \po_stg2_wrcal_cnt_reg[2] ,
    \po_stg2_wrcal_cnt_reg[2]_0 ,
    \po_stg2_wrcal_cnt_reg[2]_1 ,
    \po_stg2_wrcal_cnt_reg[2]_2 ,
    \po_stg2_wrcal_cnt_reg[2]_3 ,
    \po_stg2_wrcal_cnt_reg[2]_4 ,
    \po_stg2_wrcal_cnt_reg[2]_5 ,
    \po_stg2_wrcal_cnt_reg[2]_6 ,
    \po_stg2_wrcal_cnt_reg[2]_7 ,
    \po_stg2_wrcal_cnt_reg[2]_8 ,
    \po_stg2_wrcal_cnt_reg[2]_9 ,
    \po_stg2_wrcal_cnt_reg[2]_10 ,
    \po_stg2_wrcal_cnt_reg[2]_11 ,
    \po_stg2_wrcal_cnt_reg[2]_12 ,
    \po_stg2_wrcal_cnt_reg[2]_13 ,
    \po_stg2_wrcal_cnt_reg[2]_14 ,
    \po_stg2_wrcal_cnt_reg[2]_15 ,
    \po_stg2_wrcal_cnt_reg[2]_16 ,
    \po_stg2_wrcal_cnt_reg[2]_17 ,
    \po_stg2_wrcal_cnt_reg[2]_18 ,
    \po_stg2_wrcal_cnt_reg[2]_19 ,
    \po_stg2_wrcal_cnt_reg[2]_20 ,
    \po_stg2_wrcal_cnt_reg[2]_21 ,
    \po_stg2_wrcal_cnt_reg[2]_22 ,
    \po_stg2_wrcal_cnt_reg[2]_23 ,
    \po_stg2_wrcal_cnt_reg[2]_24 ,
    \po_stg2_wrcal_cnt_reg[2]_25 ,
    \po_stg2_wrcal_cnt_reg[2]_26 ,
    \po_stg2_wrcal_cnt_reg[2]_27 ,
    \po_stg2_wrcal_cnt_reg[2]_28 ,
    \po_stg2_wrcal_cnt_reg[2]_29 ,
    \po_stg2_wrcal_cnt_reg[2]_30 ,
    \po_stg2_wrcal_cnt_reg[2]_31 ,
    \po_stg2_wrcal_cnt_reg[2]_32 ,
    \po_stg2_wrcal_cnt_reg[2]_33 ,
    \po_stg2_wrcal_cnt_reg[2]_34 ,
    \po_stg2_wrcal_cnt_reg[2]_35 ,
    \po_stg2_wrcal_cnt_reg[2]_36 ,
    \po_stg2_wrcal_cnt_reg[2]_37 ,
    \po_stg2_wrcal_cnt_reg[2]_38 ,
    \po_stg2_wrcal_cnt_reg[2]_39 ,
    \po_stg2_wrcal_cnt_reg[2]_40 ,
    \po_stg2_wrcal_cnt_reg[2]_41 ,
    \po_stg2_wrcal_cnt_reg[2]_42 ,
    \po_stg2_wrcal_cnt_reg[2]_43 ,
    \po_stg2_wrcal_cnt_reg[2]_44 ,
    \po_stg2_wrcal_cnt_reg[2]_45 ,
    \po_stg2_wrcal_cnt_reg[2]_46 ,
    \po_stg2_wrcal_cnt_reg[2]_47 ,
    \po_stg2_wrcal_cnt_reg[2]_48 ,
    \po_stg2_wrcal_cnt_reg[2]_49 ,
    \po_stg2_wrcal_cnt_reg[2]_50 ,
    \po_stg2_wrcal_cnt_reg[2]_51 ,
    \po_stg2_wrcal_cnt_reg[2]_52 ,
    \po_stg2_wrcal_cnt_reg[2]_53 ,
    \po_stg2_wrcal_cnt_reg[2]_54 ,
    \po_stg2_wrcal_cnt_reg[2]_55 ,
    \po_stg2_wrcal_cnt_reg[2]_56 ,
    \po_stg2_wrcal_cnt_reg[2]_57 ,
    \po_stg2_wrcal_cnt_reg[2]_58 ,
    \po_stg2_wrcal_cnt_reg[2]_59 ,
    \po_stg2_wrcal_cnt_reg[2]_60 ,
    \po_stg2_wrcal_cnt_reg[2]_61 ,
    ddr_ck_out,
    \my_empty_reg[1]_9 ,
    \rd_ptr_reg[3]_8 ,
    of_ctl_full_v,
    \po_counter_read_val_reg[8]_0 ,
    \po_counter_read_val_reg[8]_1 ,
    \po_counter_read_val_reg[8]_2 ,
    \po_counter_read_val_reg[8]_3 ,
    freq_refclk,
    mem_refclk,
    sync_pulse,
    \entry_cnt_reg[4] ,
    \my_full_reg[3] ,
    \my_full_reg[3]_0 ,
    \my_full_reg[3]_1 ,
    \my_full_reg[3]_2 ,
    \my_full_reg[3]_3 ,
    \po_counter_read_val_reg[8]_4 ,
    \po_counter_read_val_reg[8]_5 ,
    \po_counter_read_val_reg[8]_6 ,
    \po_counter_read_val_reg[8]_7 ,
    D1,
    D3,
    D4,
    D5,
    D6,
    D7,
    D8,
    \rd_ptr_reg[3]_9 ,
    phy_ctl_wr_i2,
    pll_locked,
    phy_read_calib,
    phy_mc_ctl_full_r_reg,
    phy_write_calib,
    Q,
    phy_mc_ctl_full_r_reg_0,
    \input_[9].iserdes_dq_.iserdesdq ,
    mem_dq_in,
    idelay_inc,
    LD0,
    CLKB0,
    \pi_dqs_found_lanes_r1_reg[0] ,
    \pi_dqs_found_lanes_r1_reg[0]_0 ,
    \pi_dqs_found_lanes_r1_reg[0]_1 ,
    \pi_dqs_found_lanes_r1_reg[0]_2 ,
    mem_dqs_in,
    ififo_rst_reg,
    COUNTERLOADVAL,
    \po_counter_read_val_reg[8]_8 ,
    \po_counter_read_val_reg[8]_9 ,
    \po_counter_read_val_reg[8]_10 ,
    \my_empty_reg[7] ,
    \my_empty_reg[7]_0 ,
    \my_empty_reg[7]_1 ,
    \my_empty_reg[7]_2 ,
    \my_empty_reg[7]_3 ,
    \my_empty_reg[7]_4 ,
    \my_empty_reg[7]_5 ,
    \my_empty_reg[7]_6 ,
    phy_if_reset,
    \input_[9].iserdes_dq_.iserdesdq_0 ,
    LD0_7,
    CLKB0_7,
    \pi_dqs_found_lanes_r1_reg[1] ,
    \pi_dqs_found_lanes_r1_reg[1]_0 ,
    \pi_dqs_found_lanes_r1_reg[1]_1 ,
    \pi_dqs_found_lanes_r1_reg[1]_2 ,
    ififo_rst_reg_0,
    \pi_dqs_found_lanes_r1_reg[1]_3 ,
    \po_counter_read_val_reg[8]_11 ,
    \po_counter_read_val_reg[8]_12 ,
    \po_counter_read_val_reg[8]_13 ,
    \my_empty_reg[7]_7 ,
    \my_empty_reg[7]_8 ,
    \my_empty_reg[7]_9 ,
    \my_empty_reg[7]_10 ,
    \my_empty_reg[7]_11 ,
    \my_empty_reg[7]_12 ,
    \my_empty_reg[7]_13 ,
    \my_empty_reg[7]_14 ,
    \input_[9].iserdes_dq_.iserdesdq_1 ,
    LD0_8,
    CLKB0_8,
    \pi_dqs_found_lanes_r1_reg[2] ,
    \pi_dqs_found_lanes_r1_reg[2]_0 ,
    \pi_dqs_found_lanes_r1_reg[2]_1 ,
    \pi_dqs_found_lanes_r1_reg[2]_2 ,
    ififo_rst_reg_1,
    \pi_dqs_found_lanes_r1_reg[2]_3 ,
    \po_counter_read_val_reg[8]_14 ,
    \po_counter_read_val_reg[8]_15 ,
    \po_counter_read_val_reg[8]_16 ,
    \my_empty_reg[7]_15 ,
    \my_empty_reg[7]_16 ,
    \my_empty_reg[7]_17 ,
    \my_empty_reg[7]_18 ,
    \my_empty_reg[7]_19 ,
    \my_empty_reg[7]_20 ,
    \my_empty_reg[7]_21 ,
    \my_empty_reg[7]_22 ,
    \input_[9].iserdes_dq_.iserdesdq_2 ,
    LD0_9,
    CLKB0_9,
    \pi_dqs_found_lanes_r1_reg[3] ,
    \pi_dqs_found_lanes_r1_reg[3]_0 ,
    \pi_dqs_found_lanes_r1_reg[3]_1 ,
    \pi_dqs_found_lanes_r1_reg[3]_2 ,
    ififo_rst_reg_2,
    \pi_dqs_found_lanes_r1_reg[3]_3 ,
    \po_counter_read_val_reg[8]_17 ,
    \po_counter_read_val_reg[8]_18 ,
    \po_counter_read_val_reg[8]_19 ,
    \my_empty_reg[7]_23 ,
    \my_empty_reg[7]_24 ,
    \my_empty_reg[7]_25 ,
    \my_empty_reg[7]_26 ,
    \my_empty_reg[7]_27 ,
    \my_empty_reg[7]_28 ,
    \my_empty_reg[7]_29 ,
    \my_empty_reg[7]_30 ,
    RST0,
    SR,
    \input_[9].iserdes_dq_.iserdesdq_3 ,
    LD0_10,
    CLKB0_10,
    \pi_dqs_found_lanes_r1_reg[8] ,
    \pi_dqs_found_lanes_r1_reg[8]_0 ,
    \pi_dqs_found_lanes_r1_reg[8]_1 ,
    \pi_dqs_found_lanes_r1_reg[8]_2 ,
    ififo_rst_reg_3,
    \pi_dqs_found_lanes_r1_reg[8]_3 ,
    \po_counter_read_val_reg[8]_20 ,
    \po_counter_read_val_reg[8]_21 ,
    \po_counter_read_val_reg[8]_22 ,
    \my_empty_reg[7]_31 ,
    D2,
    \my_empty_reg[7]_32 ,
    \my_empty_reg[7]_33 ,
    \my_empty_reg[7]_34 ,
    \my_empty_reg[7]_35 ,
    \my_empty_reg[7]_36 ,
    \my_empty_reg[7]_37 ,
    \input_[9].iserdes_dq_.iserdesdq_4 ,
    LD0_11,
    CLKB0_11,
    \pi_dqs_found_lanes_r1_reg[9] ,
    \pi_dqs_found_lanes_r1_reg[9]_0 ,
    \pi_dqs_found_lanes_r1_reg[9]_1 ,
    \pi_dqs_found_lanes_r1_reg[9]_2 ,
    ififo_rst_reg_4,
    \pi_dqs_found_lanes_r1_reg[9]_3 ,
    \po_counter_read_val_reg[8]_23 ,
    \po_counter_read_val_reg[8]_24 ,
    \po_counter_read_val_reg[8]_25 ,
    \my_empty_reg[7]_38 ,
    \my_empty_reg[7]_39 ,
    \my_empty_reg[7]_40 ,
    \my_empty_reg[7]_41 ,
    \my_empty_reg[7]_42 ,
    \my_empty_reg[7]_43 ,
    \my_empty_reg[7]_44 ,
    \my_empty_reg[7]_45 ,
    \input_[9].iserdes_dq_.iserdesdq_5 ,
    LD0_12,
    CLKB0_12,
    \pi_dqs_found_lanes_r1_reg[10] ,
    \pi_dqs_found_lanes_r1_reg[10]_0 ,
    \pi_dqs_found_lanes_r1_reg[10]_1 ,
    \pi_dqs_found_lanes_r1_reg[10]_2 ,
    ififo_rst_reg_5,
    \pi_dqs_found_lanes_r1_reg[10]_3 ,
    \po_counter_read_val_reg[8]_26 ,
    \po_counter_read_val_reg[8]_27 ,
    \po_counter_read_val_reg[8]_28 ,
    \my_empty_reg[7]_46 ,
    \my_empty_reg[7]_47 ,
    \my_empty_reg[7]_48 ,
    \my_empty_reg[7]_49 ,
    \my_empty_reg[7]_50 ,
    \my_empty_reg[7]_51 ,
    \my_empty_reg[7]_52 ,
    \my_empty_reg[7]_53 ,
    \input_[9].iserdes_dq_.iserdesdq_6 ,
    LD0_13,
    CLKB0_13,
    \pi_dqs_found_lanes_r1_reg[11] ,
    \pi_dqs_found_lanes_r1_reg[11]_0 ,
    \pi_dqs_found_lanes_r1_reg[11]_1 ,
    \pi_dqs_found_lanes_r1_reg[11]_2 ,
    ififo_rst_reg_6,
    \pi_dqs_found_lanes_r1_reg[11]_3 ,
    \po_counter_read_val_reg[8]_29 ,
    \po_counter_read_val_reg[8]_30 ,
    \po_counter_read_val_reg[8]_31 ,
    \my_empty_reg[7]_54 ,
    \my_empty_reg[7]_55 ,
    \my_empty_reg[7]_56 ,
    \my_empty_reg[7]_57 ,
    \my_empty_reg[7]_58 ,
    \my_empty_reg[7]_59 ,
    \my_empty_reg[7]_60 ,
    \my_empty_reg[7]_61 ,
    phy_mc_ctl_full_r_reg_1,
    \rstdiv2_sync_r_reg[11] ,
    iodelay_ctrl_rdy,
    out,
    phy_data_wr_en,
    phy_cmd_wr_en,
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0] ,
    out_fifo,
    mc_cas_n,
    mc_we_n,
    out_fifo_0,
    mc_ras_n,
    mc_cs_n,
    mc_address,
    out_fifo_1,
    out_fifo_2,
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ,
    phy_dout,
    out_fifo_i_75__5,
    out_fifo_i_75__6,
    out_fifo_i_75__7,
    out_fifo_i_75__0,
    out_fifo_i_75__1,
    out_fifo_i_75__2,
    out_fifo_i_75__3,
    out_fifo_i_47__8,
    mux_address,
    d_in,
    \po_counter_read_val_reg[0]_0 ,
    calib_sel,
    \gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ,
    C_po_coarse_enable26_out,
    C_po_counter_read_en38_out,
    C_po_fine_enable23_out,
    C_po_fine_inc29_out,
    \my_empty_reg[7]_62 ,
    \my_empty_reg[7]_63 ,
    \my_empty_reg[7]_64 ,
    \my_empty_reg[7]_65 ,
    D9,
    out_fifo_i_39,
    out_fifo_3);
  output out_dqs_4;
  output ts_dqs_4;
  output A_rst_primitives_reg;
  output [94:0]mem_dq_out;
  output [71:0]mem_dq_ts;
  output [7:0]in0;
  output idelay_ld_rst;
  output out_dqs_5;
  output ts_dqs_5;
  output A_rst_primitives_reg_0;
  output idelay_ld_rst_0;
  output out_dqs_6;
  output ts_dqs_6;
  output A_rst_primitives_reg_1;
  output idelay_ld_rst_1;
  output out_dqs_7;
  output ts_dqs_7;
  output A_rst_primitives_reg_2;
  output idelay_ld_rst_2;
  output out_dqs_0;
  output ts_dqs_0;
  output A_rst_primitives_reg_3;
  output idelay_ld_rst_3;
  output out_dqs_1;
  output ts_dqs_1;
  output A_rst_primitives_reg_4;
  output idelay_ld_rst_4;
  output out_dqs_2;
  output ts_dqs_2;
  output A_rst_primitives_reg_5;
  output idelay_ld_rst_5;
  output out_dqs_3;
  output ts_dqs_3;
  output A_rst_primitives_reg_6;
  output idelay_ld_rst_6;
  output phy_mc_ctl_full;
  output rst_tmp;
  output if_empty;
  output \my_empty_reg[1] ;
  output phy_mc_data_full;
  output \my_empty_reg[1]_0 ;
  output \my_empty_reg[1]_1 ;
  output \my_empty_reg[1]_2 ;
  output A_rst_primitives_reg_7;
  output \my_empty_reg[1]_3 ;
  output \my_empty_reg[1]_4 ;
  output \my_empty_reg[1]_5 ;
  output \my_empty_reg[1]_6 ;
  output \my_empty_reg[1]_7 ;
  output \my_empty_reg[1]_8 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_6 ;
  output \rd_mux_sel_r_reg[2] ;
  output \rd_mux_sel_r_reg[2]_0 ;
  output \rd_mux_sel_r_reg[2]_1 ;
  output \rd_mux_sel_r_reg[2]_2 ;
  output \rd_mux_sel_r_reg[2]_3 ;
  output \rd_mux_sel_r_reg[2]_4 ;
  output \rd_mux_sel_r_reg[2]_5 ;
  output \rd_mux_sel_r_reg[2]_6 ;
  output \rd_mux_sel_r_reg[2]_7 ;
  output \rd_mux_sel_r_reg[2]_8 ;
  output \rd_mux_sel_r_reg[2]_9 ;
  output \rd_mux_sel_r_reg[2]_10 ;
  output \rd_mux_sel_r_reg[2]_11 ;
  output \rd_mux_sel_r_reg[2]_12 ;
  output \rd_mux_sel_r_reg[2]_13 ;
  output \rd_mux_sel_r_reg[2]_14 ;
  output \rd_mux_sel_r_reg[2]_15 ;
  output \rd_mux_sel_r_reg[2]_16 ;
  output \rd_mux_sel_r_reg[2]_17 ;
  output \rd_mux_sel_r_reg[2]_18 ;
  output \rd_mux_sel_r_reg[2]_19 ;
  output \rd_mux_sel_r_reg[2]_20 ;
  output \rd_mux_sel_r_reg[2]_21 ;
  output \rd_mux_sel_r_reg[2]_22 ;
  output \rd_mux_sel_r_reg[2]_23 ;
  output \rd_mux_sel_r_reg[2]_24 ;
  output \rd_mux_sel_r_reg[2]_25 ;
  output \rd_mux_sel_r_reg[2]_26 ;
  output \rd_mux_sel_r_reg[2]_27 ;
  output \rd_mux_sel_r_reg[2]_28 ;
  output \rd_mux_sel_r_reg[2]_29 ;
  output \rd_mux_sel_r_reg[2]_30 ;
  output \rd_mux_sel_r_reg[2]_31 ;
  output \rd_mux_sel_r_reg[2]_32 ;
  output \rd_mux_sel_r_reg[2]_33 ;
  output \rd_mux_sel_r_reg[2]_34 ;
  output \rd_mux_sel_r_reg[2]_35 ;
  output \rd_mux_sel_r_reg[2]_36 ;
  output \rd_mux_sel_r_reg[2]_37 ;
  output \rd_mux_sel_r_reg[2]_38 ;
  output \rd_mux_sel_r_reg[2]_39 ;
  output \rd_mux_sel_r_reg[2]_40 ;
  output \rd_mux_sel_r_reg[2]_41 ;
  output \rd_mux_sel_r_reg[2]_42 ;
  output \rd_mux_sel_r_reg[2]_43 ;
  output \rd_mux_sel_r_reg[2]_44 ;
  output \rd_mux_sel_r_reg[2]_45 ;
  output \rd_mux_sel_r_reg[2]_46 ;
  output \rd_mux_sel_r_reg[2]_47 ;
  output \rd_mux_sel_r_reg[2]_48 ;
  output \rd_mux_sel_r_reg[2]_49 ;
  output \rd_mux_sel_r_reg[2]_50 ;
  output \rd_mux_sel_r_reg[2]_51 ;
  output \rd_mux_sel_r_reg[2]_52 ;
  output \rd_mux_sel_r_reg[2]_53 ;
  output \rd_mux_sel_r_reg[2]_54 ;
  output \rd_mux_sel_r_reg[2]_55 ;
  output \rd_mux_sel_r_reg[2]_56 ;
  output \rd_mux_sel_r_reg[2]_57 ;
  output \rd_mux_sel_r_reg[2]_58 ;
  output \rd_mux_sel_r_reg[2]_59 ;
  output \rd_mux_sel_r_reg[2]_60 ;
  output \rd_mux_sel_r_reg[2]_61 ;
  output \rd_mux_sel_r_reg[2]_62 ;
  output phy_rddata_en;
  output [63:0]\rd_ptr_reg[3] ;
  output [63:0]\rd_ptr_reg[3]_0 ;
  output [63:0]\rd_ptr_reg[3]_1 ;
  output [63:0]\rd_ptr_reg[3]_2 ;
  output [5:0]\pi_counter_read_val_reg[5] ;
  output [63:0]\rd_ptr_reg[3]_3 ;
  output [63:0]\rd_ptr_reg[3]_4 ;
  output [63:0]\rd_ptr_reg[3]_5 ;
  output [63:0]\rd_ptr_reg[3]_6 ;
  output [5:0]\pi_counter_read_val_reg[5]_0 ;
  output [11:0]mem_out;
  output [35:0]\rd_ptr_reg[3]_7 ;
  output [0:0]\mcGo_r_reg[15]_0 ;
  output \rd_mux_sel_r_reg[2]_63 ;
  output \rd_mux_sel_r_reg[2]_64 ;
  output \rd_mux_sel_r_reg[2]_65 ;
  output \rd_mux_sel_r_reg[2]_66 ;
  output \rd_mux_sel_r_reg[2]_67 ;
  output \rd_mux_sel_r_reg[2]_68 ;
  output \rd_mux_sel_r_reg[2]_69 ;
  output \rd_mux_sel_r_reg[2]_70 ;
  output \rd_mux_sel_r_reg[2]_71 ;
  output \rd_mux_sel_r_reg[2]_72 ;
  output \rd_mux_sel_r_reg[2]_73 ;
  output \rd_mux_sel_r_reg[2]_74 ;
  output \rd_mux_sel_r_reg[2]_75 ;
  output \rd_mux_sel_r_reg[2]_76 ;
  output \rd_mux_sel_r_reg[2]_77 ;
  output \rd_mux_sel_r_reg[2]_78 ;
  output \rd_mux_sel_r_reg[2]_79 ;
  output \rd_mux_sel_r_reg[2]_80 ;
  output \rd_mux_sel_r_reg[2]_81 ;
  output \rd_mux_sel_r_reg[2]_82 ;
  output \rd_mux_sel_r_reg[2]_83 ;
  output \rd_mux_sel_r_reg[2]_84 ;
  output \rd_mux_sel_r_reg[2]_85 ;
  output \rd_mux_sel_r_reg[2]_86 ;
  output \rd_mux_sel_r_reg[2]_87 ;
  output \rd_mux_sel_r_reg[2]_88 ;
  output \rd_mux_sel_r_reg[2]_89 ;
  output \rd_mux_sel_r_reg[2]_90 ;
  output \rd_mux_sel_r_reg[2]_91 ;
  output \rd_mux_sel_r_reg[2]_92 ;
  output \rd_mux_sel_r_reg[2]_93 ;
  output \rd_mux_sel_r_reg[2]_94 ;
  output \rd_mux_sel_r_reg[2]_95 ;
  output \rd_mux_sel_r_reg[2]_96 ;
  output \rd_mux_sel_r_reg[2]_97 ;
  output \rd_mux_sel_r_reg[2]_98 ;
  output \rd_mux_sel_r_reg[2]_99 ;
  output \rd_mux_sel_r_reg[2]_100 ;
  output \rd_mux_sel_r_reg[2]_101 ;
  output \rd_mux_sel_r_reg[2]_102 ;
  output \rd_mux_sel_r_reg[2]_103 ;
  output \rd_mux_sel_r_reg[2]_104 ;
  output \rd_mux_sel_r_reg[2]_105 ;
  output \rd_mux_sel_r_reg[2]_106 ;
  output \rd_mux_sel_r_reg[2]_107 ;
  output \rd_mux_sel_r_reg[2]_108 ;
  output \rd_mux_sel_r_reg[2]_109 ;
  output \rd_mux_sel_r_reg[2]_110 ;
  output \rd_mux_sel_r_reg[2]_111 ;
  output \rd_mux_sel_r_reg[2]_112 ;
  output \rd_mux_sel_r_reg[2]_113 ;
  output \rd_mux_sel_r_reg[2]_114 ;
  output \rd_mux_sel_r_reg[2]_115 ;
  output \rd_mux_sel_r_reg[2]_116 ;
  output \rd_mux_sel_r_reg[2]_117 ;
  output \rd_mux_sel_r_reg[2]_118 ;
  output \rd_mux_sel_r_reg[2]_119 ;
  output \rd_mux_sel_r_reg[2]_120 ;
  output \rd_mux_sel_r_reg[2]_121 ;
  output \rd_mux_sel_r_reg[2]_122 ;
  output \rd_mux_sel_r_reg[2]_123 ;
  output \rd_mux_sel_r_reg[2]_124 ;
  output \rd_mux_sel_r_reg[2]_125 ;
  output \rd_mux_sel_r_reg[2]_126 ;
  output \po_counter_read_val_reg[0] ;
  output \po_counter_read_val_reg[1] ;
  output \po_counter_read_val_reg[2] ;
  output \po_counter_read_val_reg[3] ;
  output \po_counter_read_val_reg[4] ;
  output \po_counter_read_val_reg[5] ;
  output \po_counter_read_val_reg[6] ;
  output \po_counter_read_val_reg[7] ;
  output \po_counter_read_val_reg[8] ;
  output p_0_out;
  output \po_stg2_wrcal_cnt_reg[2] ;
  output \po_stg2_wrcal_cnt_reg[2]_0 ;
  output \po_stg2_wrcal_cnt_reg[2]_1 ;
  output \po_stg2_wrcal_cnt_reg[2]_2 ;
  output \po_stg2_wrcal_cnt_reg[2]_3 ;
  output \po_stg2_wrcal_cnt_reg[2]_4 ;
  output \po_stg2_wrcal_cnt_reg[2]_5 ;
  output \po_stg2_wrcal_cnt_reg[2]_6 ;
  output \po_stg2_wrcal_cnt_reg[2]_7 ;
  output \po_stg2_wrcal_cnt_reg[2]_8 ;
  output \po_stg2_wrcal_cnt_reg[2]_9 ;
  output \po_stg2_wrcal_cnt_reg[2]_10 ;
  output \po_stg2_wrcal_cnt_reg[2]_11 ;
  output \po_stg2_wrcal_cnt_reg[2]_12 ;
  output \po_stg2_wrcal_cnt_reg[2]_13 ;
  output \po_stg2_wrcal_cnt_reg[2]_14 ;
  output \po_stg2_wrcal_cnt_reg[2]_15 ;
  output \po_stg2_wrcal_cnt_reg[2]_16 ;
  output \po_stg2_wrcal_cnt_reg[2]_17 ;
  output \po_stg2_wrcal_cnt_reg[2]_18 ;
  output \po_stg2_wrcal_cnt_reg[2]_19 ;
  output \po_stg2_wrcal_cnt_reg[2]_20 ;
  output \po_stg2_wrcal_cnt_reg[2]_21 ;
  output \po_stg2_wrcal_cnt_reg[2]_22 ;
  output \po_stg2_wrcal_cnt_reg[2]_23 ;
  output \po_stg2_wrcal_cnt_reg[2]_24 ;
  output \po_stg2_wrcal_cnt_reg[2]_25 ;
  output \po_stg2_wrcal_cnt_reg[2]_26 ;
  output \po_stg2_wrcal_cnt_reg[2]_27 ;
  output \po_stg2_wrcal_cnt_reg[2]_28 ;
  output \po_stg2_wrcal_cnt_reg[2]_29 ;
  output \po_stg2_wrcal_cnt_reg[2]_30 ;
  output \po_stg2_wrcal_cnt_reg[2]_31 ;
  output \po_stg2_wrcal_cnt_reg[2]_32 ;
  output \po_stg2_wrcal_cnt_reg[2]_33 ;
  output \po_stg2_wrcal_cnt_reg[2]_34 ;
  output \po_stg2_wrcal_cnt_reg[2]_35 ;
  output \po_stg2_wrcal_cnt_reg[2]_36 ;
  output \po_stg2_wrcal_cnt_reg[2]_37 ;
  output \po_stg2_wrcal_cnt_reg[2]_38 ;
  output \po_stg2_wrcal_cnt_reg[2]_39 ;
  output \po_stg2_wrcal_cnt_reg[2]_40 ;
  output \po_stg2_wrcal_cnt_reg[2]_41 ;
  output \po_stg2_wrcal_cnt_reg[2]_42 ;
  output \po_stg2_wrcal_cnt_reg[2]_43 ;
  output \po_stg2_wrcal_cnt_reg[2]_44 ;
  output \po_stg2_wrcal_cnt_reg[2]_45 ;
  output \po_stg2_wrcal_cnt_reg[2]_46 ;
  output \po_stg2_wrcal_cnt_reg[2]_47 ;
  output \po_stg2_wrcal_cnt_reg[2]_48 ;
  output \po_stg2_wrcal_cnt_reg[2]_49 ;
  output \po_stg2_wrcal_cnt_reg[2]_50 ;
  output \po_stg2_wrcal_cnt_reg[2]_51 ;
  output \po_stg2_wrcal_cnt_reg[2]_52 ;
  output \po_stg2_wrcal_cnt_reg[2]_53 ;
  output \po_stg2_wrcal_cnt_reg[2]_54 ;
  output \po_stg2_wrcal_cnt_reg[2]_55 ;
  output \po_stg2_wrcal_cnt_reg[2]_56 ;
  output \po_stg2_wrcal_cnt_reg[2]_57 ;
  output \po_stg2_wrcal_cnt_reg[2]_58 ;
  output \po_stg2_wrcal_cnt_reg[2]_59 ;
  output \po_stg2_wrcal_cnt_reg[2]_60 ;
  output \po_stg2_wrcal_cnt_reg[2]_61 ;
  output [1:0]ddr_ck_out;
  output \my_empty_reg[1]_9 ;
  output [23:0]\rd_ptr_reg[3]_8 ;
  output [0:0]of_ctl_full_v;
  input \po_counter_read_val_reg[8]_0 ;
  input \po_counter_read_val_reg[8]_1 ;
  input \po_counter_read_val_reg[8]_2 ;
  input \po_counter_read_val_reg[8]_3 ;
  input freq_refclk;
  input mem_refclk;
  input sync_pulse;
  input \entry_cnt_reg[4] ;
  input [3:0]\my_full_reg[3] ;
  input [0:0]\my_full_reg[3]_0 ;
  input [1:0]\my_full_reg[3]_1 ;
  input [0:0]\my_full_reg[3]_2 ;
  input [3:0]\my_full_reg[3]_3 ;
  input \po_counter_read_val_reg[8]_4 ;
  input \po_counter_read_val_reg[8]_5 ;
  input \po_counter_read_val_reg[8]_6 ;
  input \po_counter_read_val_reg[8]_7 ;
  input [3:0]D1;
  input [3:0]D3;
  input [3:0]D4;
  input [3:0]D5;
  input [7:0]D6;
  input [3:0]D7;
  input [3:0]D8;
  input [3:0]\rd_ptr_reg[3]_9 ;
  input phy_ctl_wr_i2;
  input pll_locked;
  input phy_read_calib;
  input phy_mc_ctl_full_r_reg;
  input phy_write_calib;
  input [10:0]Q;
  input [5:0]phy_mc_ctl_full_r_reg_0;
  input \input_[9].iserdes_dq_.iserdesdq ;
  input [63:0]mem_dq_in;
  input idelay_inc;
  input LD0;
  input CLKB0;
  input \pi_dqs_found_lanes_r1_reg[0] ;
  input \pi_dqs_found_lanes_r1_reg[0]_0 ;
  input \pi_dqs_found_lanes_r1_reg[0]_1 ;
  input \pi_dqs_found_lanes_r1_reg[0]_2 ;
  input [7:0]mem_dqs_in;
  input ififo_rst_reg;
  input [5:0]COUNTERLOADVAL;
  input \po_counter_read_val_reg[8]_8 ;
  input \po_counter_read_val_reg[8]_9 ;
  input \po_counter_read_val_reg[8]_10 ;
  input [7:0]\my_empty_reg[7] ;
  input [7:0]\my_empty_reg[7]_0 ;
  input [7:0]\my_empty_reg[7]_1 ;
  input [7:0]\my_empty_reg[7]_2 ;
  input [7:0]\my_empty_reg[7]_3 ;
  input [7:0]\my_empty_reg[7]_4 ;
  input [7:0]\my_empty_reg[7]_5 ;
  input [7:0]\my_empty_reg[7]_6 ;
  input phy_if_reset;
  input \input_[9].iserdes_dq_.iserdesdq_0 ;
  input LD0_7;
  input CLKB0_7;
  input \pi_dqs_found_lanes_r1_reg[1] ;
  input \pi_dqs_found_lanes_r1_reg[1]_0 ;
  input \pi_dqs_found_lanes_r1_reg[1]_1 ;
  input \pi_dqs_found_lanes_r1_reg[1]_2 ;
  input ififo_rst_reg_0;
  input [5:0]\pi_dqs_found_lanes_r1_reg[1]_3 ;
  input \po_counter_read_val_reg[8]_11 ;
  input \po_counter_read_val_reg[8]_12 ;
  input \po_counter_read_val_reg[8]_13 ;
  input [7:0]\my_empty_reg[7]_7 ;
  input [7:0]\my_empty_reg[7]_8 ;
  input [7:0]\my_empty_reg[7]_9 ;
  input [7:0]\my_empty_reg[7]_10 ;
  input [7:0]\my_empty_reg[7]_11 ;
  input [7:0]\my_empty_reg[7]_12 ;
  input [7:0]\my_empty_reg[7]_13 ;
  input [7:0]\my_empty_reg[7]_14 ;
  input \input_[9].iserdes_dq_.iserdesdq_1 ;
  input LD0_8;
  input CLKB0_8;
  input \pi_dqs_found_lanes_r1_reg[2] ;
  input \pi_dqs_found_lanes_r1_reg[2]_0 ;
  input \pi_dqs_found_lanes_r1_reg[2]_1 ;
  input \pi_dqs_found_lanes_r1_reg[2]_2 ;
  input ififo_rst_reg_1;
  input [5:0]\pi_dqs_found_lanes_r1_reg[2]_3 ;
  input \po_counter_read_val_reg[8]_14 ;
  input \po_counter_read_val_reg[8]_15 ;
  input \po_counter_read_val_reg[8]_16 ;
  input [7:0]\my_empty_reg[7]_15 ;
  input [7:0]\my_empty_reg[7]_16 ;
  input [7:0]\my_empty_reg[7]_17 ;
  input [7:0]\my_empty_reg[7]_18 ;
  input [7:0]\my_empty_reg[7]_19 ;
  input [7:0]\my_empty_reg[7]_20 ;
  input [7:0]\my_empty_reg[7]_21 ;
  input [7:0]\my_empty_reg[7]_22 ;
  input \input_[9].iserdes_dq_.iserdesdq_2 ;
  input LD0_9;
  input CLKB0_9;
  input \pi_dqs_found_lanes_r1_reg[3] ;
  input \pi_dqs_found_lanes_r1_reg[3]_0 ;
  input \pi_dqs_found_lanes_r1_reg[3]_1 ;
  input \pi_dqs_found_lanes_r1_reg[3]_2 ;
  input ififo_rst_reg_2;
  input [5:0]\pi_dqs_found_lanes_r1_reg[3]_3 ;
  input \po_counter_read_val_reg[8]_17 ;
  input \po_counter_read_val_reg[8]_18 ;
  input \po_counter_read_val_reg[8]_19 ;
  input [7:0]\my_empty_reg[7]_23 ;
  input [7:0]\my_empty_reg[7]_24 ;
  input [7:0]\my_empty_reg[7]_25 ;
  input [7:0]\my_empty_reg[7]_26 ;
  input [7:0]\my_empty_reg[7]_27 ;
  input [7:0]\my_empty_reg[7]_28 ;
  input [7:0]\my_empty_reg[7]_29 ;
  input [7:0]\my_empty_reg[7]_30 ;
  input RST0;
  input [0:0]SR;
  input \input_[9].iserdes_dq_.iserdesdq_3 ;
  input LD0_10;
  input CLKB0_10;
  input \pi_dqs_found_lanes_r1_reg[8] ;
  input \pi_dqs_found_lanes_r1_reg[8]_0 ;
  input \pi_dqs_found_lanes_r1_reg[8]_1 ;
  input \pi_dqs_found_lanes_r1_reg[8]_2 ;
  input ififo_rst_reg_3;
  input [5:0]\pi_dqs_found_lanes_r1_reg[8]_3 ;
  input \po_counter_read_val_reg[8]_20 ;
  input \po_counter_read_val_reg[8]_21 ;
  input \po_counter_read_val_reg[8]_22 ;
  input [7:0]\my_empty_reg[7]_31 ;
  input [7:0]D2;
  input [7:0]\my_empty_reg[7]_32 ;
  input [7:0]\my_empty_reg[7]_33 ;
  input [7:0]\my_empty_reg[7]_34 ;
  input [7:0]\my_empty_reg[7]_35 ;
  input [7:0]\my_empty_reg[7]_36 ;
  input [7:0]\my_empty_reg[7]_37 ;
  input \input_[9].iserdes_dq_.iserdesdq_4 ;
  input LD0_11;
  input CLKB0_11;
  input \pi_dqs_found_lanes_r1_reg[9] ;
  input \pi_dqs_found_lanes_r1_reg[9]_0 ;
  input \pi_dqs_found_lanes_r1_reg[9]_1 ;
  input \pi_dqs_found_lanes_r1_reg[9]_2 ;
  input ififo_rst_reg_4;
  input [5:0]\pi_dqs_found_lanes_r1_reg[9]_3 ;
  input \po_counter_read_val_reg[8]_23 ;
  input \po_counter_read_val_reg[8]_24 ;
  input \po_counter_read_val_reg[8]_25 ;
  input [7:0]\my_empty_reg[7]_38 ;
  input [7:0]\my_empty_reg[7]_39 ;
  input [7:0]\my_empty_reg[7]_40 ;
  input [7:0]\my_empty_reg[7]_41 ;
  input [7:0]\my_empty_reg[7]_42 ;
  input [7:0]\my_empty_reg[7]_43 ;
  input [7:0]\my_empty_reg[7]_44 ;
  input [7:0]\my_empty_reg[7]_45 ;
  input \input_[9].iserdes_dq_.iserdesdq_5 ;
  input LD0_12;
  input CLKB0_12;
  input \pi_dqs_found_lanes_r1_reg[10] ;
  input \pi_dqs_found_lanes_r1_reg[10]_0 ;
  input \pi_dqs_found_lanes_r1_reg[10]_1 ;
  input \pi_dqs_found_lanes_r1_reg[10]_2 ;
  input ififo_rst_reg_5;
  input [5:0]\pi_dqs_found_lanes_r1_reg[10]_3 ;
  input \po_counter_read_val_reg[8]_26 ;
  input \po_counter_read_val_reg[8]_27 ;
  input \po_counter_read_val_reg[8]_28 ;
  input [7:0]\my_empty_reg[7]_46 ;
  input [7:0]\my_empty_reg[7]_47 ;
  input [7:0]\my_empty_reg[7]_48 ;
  input [7:0]\my_empty_reg[7]_49 ;
  input [7:0]\my_empty_reg[7]_50 ;
  input [7:0]\my_empty_reg[7]_51 ;
  input [7:0]\my_empty_reg[7]_52 ;
  input [7:0]\my_empty_reg[7]_53 ;
  input \input_[9].iserdes_dq_.iserdesdq_6 ;
  input LD0_13;
  input CLKB0_13;
  input \pi_dqs_found_lanes_r1_reg[11] ;
  input \pi_dqs_found_lanes_r1_reg[11]_0 ;
  input \pi_dqs_found_lanes_r1_reg[11]_1 ;
  input \pi_dqs_found_lanes_r1_reg[11]_2 ;
  input ififo_rst_reg_6;
  input [5:0]\pi_dqs_found_lanes_r1_reg[11]_3 ;
  input \po_counter_read_val_reg[8]_29 ;
  input \po_counter_read_val_reg[8]_30 ;
  input \po_counter_read_val_reg[8]_31 ;
  input [7:0]\my_empty_reg[7]_54 ;
  input [7:0]\my_empty_reg[7]_55 ;
  input [7:0]\my_empty_reg[7]_56 ;
  input [7:0]\my_empty_reg[7]_57 ;
  input [7:0]\my_empty_reg[7]_58 ;
  input [7:0]\my_empty_reg[7]_59 ;
  input [7:0]\my_empty_reg[7]_60 ;
  input [7:0]\my_empty_reg[7]_61 ;
  input [5:0]phy_mc_ctl_full_r_reg_1;
  input \rstdiv2_sync_r_reg[11] ;
  input [0:0]iodelay_ctrl_rdy;
  input out;
  input phy_data_wr_en;
  input phy_cmd_wr_en;
  input [1:0]\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;
  input out_fifo;
  input [2:0]mc_cas_n;
  input [1:0]mc_we_n;
  input out_fifo_0;
  input [1:0]mc_ras_n;
  input [0:0]mc_cs_n;
  input [3:0]mc_address;
  input [63:0]out_fifo_1;
  input out_fifo_2;
  input \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;
  input [71:0]phy_dout;
  input [71:0]out_fifo_i_75__5;
  input [71:0]out_fifo_i_75__6;
  input [71:0]out_fifo_i_75__7;
  input [71:0]out_fifo_i_75__0;
  input [71:0]out_fifo_i_75__1;
  input [71:0]out_fifo_i_75__2;
  input [71:0]out_fifo_i_75__3;
  input [12:0]out_fifo_i_47__8;
  input [48:0]mux_address;
  input [4:0]d_in;
  input [0:0]\po_counter_read_val_reg[0]_0 ;
  input [3:0]calib_sel;
  input [2:0]\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ;
  input [2:0]\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;
  input C_po_coarse_enable26_out;
  input C_po_counter_read_en38_out;
  input C_po_fine_enable23_out;
  input C_po_fine_inc29_out;
  input [3:0]\my_empty_reg[7]_62 ;
  input [7:0]\my_empty_reg[7]_63 ;
  input [3:0]\my_empty_reg[7]_64 ;
  input [3:0]\my_empty_reg[7]_65 ;
  input [3:0]D9;
  input [11:0]out_fifo_i_39;
  input out_fifo_3;

  wire A_rst_primitives_reg;
  wire A_rst_primitives_reg_0;
  wire A_rst_primitives_reg_1;
  wire A_rst_primitives_reg_2;
  wire A_rst_primitives_reg_3;
  wire A_rst_primitives_reg_4;
  wire A_rst_primitives_reg_5;
  wire A_rst_primitives_reg_6;
  wire A_rst_primitives_reg_7;
  wire CLKB0;
  wire CLKB0_10;
  wire CLKB0_11;
  wire CLKB0_12;
  wire CLKB0_13;
  wire CLKB0_7;
  wire CLKB0_8;
  wire CLKB0_9;
  wire [5:0]COUNTERLOADVAL;
  wire C_po_coarse_enable26_out;
  wire C_po_counter_read_en38_out;
  wire C_po_fine_enable23_out;
  wire C_po_fine_inc29_out;
  wire [3:0]D1;
  wire [7:0]D2;
  wire [3:0]D3;
  wire [3:0]D4;
  wire [3:0]D5;
  wire [7:0]D6;
  wire [3:0]D7;
  wire [3:0]D8;
  wire [3:0]D9;
  wire LD0;
  wire LD0_10;
  wire LD0_11;
  wire LD0_12;
  wire LD0_13;
  wire LD0_7;
  wire LD0_8;
  wire LD0_9;
  wire [10:0]Q;
  wire RST0;
  wire [0:0]SR;
  wire [1:1]_phy_ctl_full_p;
  wire [2:0]_phy_ctl_full_p__0;
  wire [3:0]calib_sel;
  wire [4:0]d_in;
  wire [0:0]\ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ;
  wire [3:3]\ddr_byte_lane_B.ddr_byte_lane_B/if_empty_r ;
  wire [0:0]\ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ;
  wire [3:3]\ddr_byte_lane_C.ddr_byte_lane_C/if_empty_r ;
  wire [1:0]ddr_ck_out;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_101 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_103 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_111 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_369 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_371 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_373 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_375 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_377 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_379 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_381 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_383 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_385 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_387 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_389 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_391 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_393 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_395 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_397 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_399 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_401 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_403 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_405 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_407 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_409 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_411 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_413 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_415 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_417 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_419 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_421 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_423 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_425 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_427 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_429 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_431 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_433 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_435 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_437 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_439 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_441 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_443 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_445 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_447 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_449 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_451 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_453 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_455 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_457 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_459 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_461 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_463 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_465 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_467 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_469 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_471 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_473 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_475 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_477 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_479 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_481 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_483 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_485 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_487 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_489 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_491 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_493 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_495 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_497 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_498 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_499 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_500 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_501 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_502 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_503 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_504 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_505 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_506 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_507 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_508 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_509 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_510 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_511 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_512 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_513 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_514 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_515 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_516 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_517 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_518 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_519 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_520 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_521 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_522 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_523 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_524 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_525 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_526 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_527 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_528 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_529 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_530 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_531 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_532 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_533 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_534 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_535 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_536 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_537 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_538 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_539 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_540 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_541 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_542 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_543 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_544 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_545 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_546 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_547 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_548 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_549 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_550 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_551 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_552 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_553 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_554 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_555 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_556 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_557 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_558 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_559 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_560 ;
  wire \ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_97 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_100 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_104 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_108 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_112 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_116 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_120 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_124 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_128 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_132 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_136 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_140 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_144 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_148 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_152 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_156 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_160 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_164 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_168 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_172 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_176 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_180 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_184 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_188 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_192 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_196 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_200 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_204 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_208 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_212 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_216 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_220 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_224 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_228 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_232 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_236 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_240 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_244 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_248 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_252 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_256 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_260 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_264 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_268 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_272 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_276 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_280 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_284 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_288 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_292 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_296 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_300 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_304 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_308 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_312 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_316 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_320 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_324 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_328 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_332 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_336 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_340 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_344 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_348 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_352 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_356 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_360 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_809 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_810 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_826 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_827 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_93 ;
  wire \ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_97 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ;
  wire \entry_cnt_reg[4] ;
  wire freq_refclk;
  wire [2:0]\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ;
  wire [1:0]\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;
  wire \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;
  wire [2:0]\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;
  wire idelay_inc;
  wire idelay_ld_rst;
  wire idelay_ld_rst_0;
  wire idelay_ld_rst_1;
  wire idelay_ld_rst_2;
  wire idelay_ld_rst_3;
  wire idelay_ld_rst_4;
  wire idelay_ld_rst_5;
  wire idelay_ld_rst_6;
  wire if_empty;
  wire [2:2]if_empty_v;
  wire ififo_rst_reg;
  wire ififo_rst_reg_0;
  wire ififo_rst_reg_1;
  wire ififo_rst_reg_2;
  wire ififo_rst_reg_3;
  wire ififo_rst_reg_4;
  wire ififo_rst_reg_5;
  wire ififo_rst_reg_6;
  wire [7:0]in0;
  wire \input_[9].iserdes_dq_.iserdesdq ;
  wire \input_[9].iserdes_dq_.iserdesdq_0 ;
  wire \input_[9].iserdes_dq_.iserdesdq_1 ;
  wire \input_[9].iserdes_dq_.iserdesdq_2 ;
  wire \input_[9].iserdes_dq_.iserdesdq_3 ;
  wire \input_[9].iserdes_dq_.iserdesdq_4 ;
  wire \input_[9].iserdes_dq_.iserdesdq_5 ;
  wire \input_[9].iserdes_dq_.iserdesdq_6 ;
  wire [0:0]iodelay_ctrl_rdy;
  wire [14:0]mcGo_r;
  wire mcGo_r1__0;
  wire [0:0]\mcGo_r_reg[15]_0 ;
  wire [2:0]mcGo_w;
  wire [1:1]mcGo_w__0;
  wire [3:0]mc_address;
  wire [2:0]mc_cas_n;
  wire [0:0]mc_cs_n;
  wire [1:0]mc_ras_n;
  wire [1:0]mc_we_n;
  wire [63:0]mem_dq_in;
  wire [94:0]mem_dq_out;
  wire [71:0]mem_dq_ts;
  wire [7:0]mem_dqs_in;
  wire [11:0]mem_out;
  wire mem_refclk;
  wire [48:0]mux_address;
  wire \my_empty_reg[1] ;
  wire \my_empty_reg[1]_0 ;
  wire \my_empty_reg[1]_1 ;
  wire \my_empty_reg[1]_2 ;
  wire \my_empty_reg[1]_3 ;
  wire \my_empty_reg[1]_4 ;
  wire \my_empty_reg[1]_5 ;
  wire \my_empty_reg[1]_6 ;
  wire \my_empty_reg[1]_7 ;
  wire \my_empty_reg[1]_8 ;
  wire \my_empty_reg[1]_9 ;
  wire [7:0]\my_empty_reg[7] ;
  wire [7:0]\my_empty_reg[7]_0 ;
  wire [7:0]\my_empty_reg[7]_1 ;
  wire [7:0]\my_empty_reg[7]_10 ;
  wire [7:0]\my_empty_reg[7]_11 ;
  wire [7:0]\my_empty_reg[7]_12 ;
  wire [7:0]\my_empty_reg[7]_13 ;
  wire [7:0]\my_empty_reg[7]_14 ;
  wire [7:0]\my_empty_reg[7]_15 ;
  wire [7:0]\my_empty_reg[7]_16 ;
  wire [7:0]\my_empty_reg[7]_17 ;
  wire [7:0]\my_empty_reg[7]_18 ;
  wire [7:0]\my_empty_reg[7]_19 ;
  wire [7:0]\my_empty_reg[7]_2 ;
  wire [7:0]\my_empty_reg[7]_20 ;
  wire [7:0]\my_empty_reg[7]_21 ;
  wire [7:0]\my_empty_reg[7]_22 ;
  wire [7:0]\my_empty_reg[7]_23 ;
  wire [7:0]\my_empty_reg[7]_24 ;
  wire [7:0]\my_empty_reg[7]_25 ;
  wire [7:0]\my_empty_reg[7]_26 ;
  wire [7:0]\my_empty_reg[7]_27 ;
  wire [7:0]\my_empty_reg[7]_28 ;
  wire [7:0]\my_empty_reg[7]_29 ;
  wire [7:0]\my_empty_reg[7]_3 ;
  wire [7:0]\my_empty_reg[7]_30 ;
  wire [7:0]\my_empty_reg[7]_31 ;
  wire [7:0]\my_empty_reg[7]_32 ;
  wire [7:0]\my_empty_reg[7]_33 ;
  wire [7:0]\my_empty_reg[7]_34 ;
  wire [7:0]\my_empty_reg[7]_35 ;
  wire [7:0]\my_empty_reg[7]_36 ;
  wire [7:0]\my_empty_reg[7]_37 ;
  wire [7:0]\my_empty_reg[7]_38 ;
  wire [7:0]\my_empty_reg[7]_39 ;
  wire [7:0]\my_empty_reg[7]_4 ;
  wire [7:0]\my_empty_reg[7]_40 ;
  wire [7:0]\my_empty_reg[7]_41 ;
  wire [7:0]\my_empty_reg[7]_42 ;
  wire [7:0]\my_empty_reg[7]_43 ;
  wire [7:0]\my_empty_reg[7]_44 ;
  wire [7:0]\my_empty_reg[7]_45 ;
  wire [7:0]\my_empty_reg[7]_46 ;
  wire [7:0]\my_empty_reg[7]_47 ;
  wire [7:0]\my_empty_reg[7]_48 ;
  wire [7:0]\my_empty_reg[7]_49 ;
  wire [7:0]\my_empty_reg[7]_5 ;
  wire [7:0]\my_empty_reg[7]_50 ;
  wire [7:0]\my_empty_reg[7]_51 ;
  wire [7:0]\my_empty_reg[7]_52 ;
  wire [7:0]\my_empty_reg[7]_53 ;
  wire [7:0]\my_empty_reg[7]_54 ;
  wire [7:0]\my_empty_reg[7]_55 ;
  wire [7:0]\my_empty_reg[7]_56 ;
  wire [7:0]\my_empty_reg[7]_57 ;
  wire [7:0]\my_empty_reg[7]_58 ;
  wire [7:0]\my_empty_reg[7]_59 ;
  wire [7:0]\my_empty_reg[7]_6 ;
  wire [7:0]\my_empty_reg[7]_60 ;
  wire [7:0]\my_empty_reg[7]_61 ;
  wire [3:0]\my_empty_reg[7]_62 ;
  wire [7:0]\my_empty_reg[7]_63 ;
  wire [3:0]\my_empty_reg[7]_64 ;
  wire [3:0]\my_empty_reg[7]_65 ;
  wire [7:0]\my_empty_reg[7]_7 ;
  wire [7:0]\my_empty_reg[7]_8 ;
  wire [7:0]\my_empty_reg[7]_9 ;
  wire [3:0]\my_full_reg[3] ;
  wire [0:0]\my_full_reg[3]_0 ;
  wire [1:0]\my_full_reg[3]_1 ;
  wire [0:0]\my_full_reg[3]_2 ;
  wire [3:0]\my_full_reg[3]_3 ;
  wire [0:0]of_ctl_full_v;
  wire out;
  wire out_dqs_0;
  wire out_dqs_1;
  wire out_dqs_2;
  wire out_dqs_3;
  wire out_dqs_4;
  wire out_dqs_5;
  wire out_dqs_6;
  wire out_dqs_7;
  wire out_fifo;
  wire out_fifo_0;
  wire [63:0]out_fifo_1;
  wire out_fifo_2;
  wire out_fifo_3;
  wire [11:0]out_fifo_i_39;
  wire [12:0]out_fifo_i_47__8;
  wire [71:0]out_fifo_i_75__0;
  wire [71:0]out_fifo_i_75__1;
  wire [71:0]out_fifo_i_75__2;
  wire [71:0]out_fifo_i_75__3;
  wire [71:0]out_fifo_i_75__5;
  wire [71:0]out_fifo_i_75__6;
  wire [71:0]out_fifo_i_75__7;
  wire p_0_out;
  wire phy_cmd_wr_en;
  wire phy_ctl_mstr_empty;
  wire phy_ctl_wr_i2;
  wire phy_data_wr_en;
  wire [71:0]phy_dout;
  wire phy_if_empty_r_i_2_n_0;
  wire phy_if_reset;
  wire phy_mc_ctl_full;
  wire phy_mc_ctl_full_r_reg;
  wire [5:0]phy_mc_ctl_full_r_reg_0;
  wire [5:0]phy_mc_ctl_full_r_reg_1;
  wire phy_mc_data_full;
  wire phy_rddata_en;
  wire phy_read_calib;
  wire phy_write_calib;
  wire [5:0]\pi_counter_read_val_reg[5] ;
  wire [5:0]\pi_counter_read_val_reg[5]_0 ;
  wire \pi_dqs_found_lanes_r1_reg[0] ;
  wire \pi_dqs_found_lanes_r1_reg[0]_0 ;
  wire \pi_dqs_found_lanes_r1_reg[0]_1 ;
  wire \pi_dqs_found_lanes_r1_reg[0]_2 ;
  wire \pi_dqs_found_lanes_r1_reg[10] ;
  wire \pi_dqs_found_lanes_r1_reg[10]_0 ;
  wire \pi_dqs_found_lanes_r1_reg[10]_1 ;
  wire \pi_dqs_found_lanes_r1_reg[10]_2 ;
  wire [5:0]\pi_dqs_found_lanes_r1_reg[10]_3 ;
  wire \pi_dqs_found_lanes_r1_reg[11] ;
  wire \pi_dqs_found_lanes_r1_reg[11]_0 ;
  wire \pi_dqs_found_lanes_r1_reg[11]_1 ;
  wire \pi_dqs_found_lanes_r1_reg[11]_2 ;
  wire [5:0]\pi_dqs_found_lanes_r1_reg[11]_3 ;
  wire \pi_dqs_found_lanes_r1_reg[1] ;
  wire \pi_dqs_found_lanes_r1_reg[1]_0 ;
  wire \pi_dqs_found_lanes_r1_reg[1]_1 ;
  wire \pi_dqs_found_lanes_r1_reg[1]_2 ;
  wire [5:0]\pi_dqs_found_lanes_r1_reg[1]_3 ;
  wire \pi_dqs_found_lanes_r1_reg[2] ;
  wire \pi_dqs_found_lanes_r1_reg[2]_0 ;
  wire \pi_dqs_found_lanes_r1_reg[2]_1 ;
  wire \pi_dqs_found_lanes_r1_reg[2]_2 ;
  wire [5:0]\pi_dqs_found_lanes_r1_reg[2]_3 ;
  wire \pi_dqs_found_lanes_r1_reg[3] ;
  wire \pi_dqs_found_lanes_r1_reg[3]_0 ;
  wire \pi_dqs_found_lanes_r1_reg[3]_1 ;
  wire \pi_dqs_found_lanes_r1_reg[3]_2 ;
  wire [5:0]\pi_dqs_found_lanes_r1_reg[3]_3 ;
  wire \pi_dqs_found_lanes_r1_reg[8] ;
  wire \pi_dqs_found_lanes_r1_reg[8]_0 ;
  wire \pi_dqs_found_lanes_r1_reg[8]_1 ;
  wire \pi_dqs_found_lanes_r1_reg[8]_2 ;
  wire [5:0]\pi_dqs_found_lanes_r1_reg[8]_3 ;
  wire \pi_dqs_found_lanes_r1_reg[9] ;
  wire \pi_dqs_found_lanes_r1_reg[9]_0 ;
  wire \pi_dqs_found_lanes_r1_reg[9]_1 ;
  wire \pi_dqs_found_lanes_r1_reg[9]_2 ;
  wire [5:0]\pi_dqs_found_lanes_r1_reg[9]_3 ;
  wire pll_locked;
  wire \po_counter_read_val_reg[0] ;
  wire [0:0]\po_counter_read_val_reg[0]_0 ;
  wire \po_counter_read_val_reg[1] ;
  wire \po_counter_read_val_reg[2] ;
  wire \po_counter_read_val_reg[3] ;
  wire \po_counter_read_val_reg[4] ;
  wire \po_counter_read_val_reg[5] ;
  wire \po_counter_read_val_reg[6] ;
  wire \po_counter_read_val_reg[7] ;
  wire \po_counter_read_val_reg[8] ;
  wire \po_counter_read_val_reg[8]_0 ;
  wire \po_counter_read_val_reg[8]_1 ;
  wire \po_counter_read_val_reg[8]_10 ;
  wire \po_counter_read_val_reg[8]_11 ;
  wire \po_counter_read_val_reg[8]_12 ;
  wire \po_counter_read_val_reg[8]_13 ;
  wire \po_counter_read_val_reg[8]_14 ;
  wire \po_counter_read_val_reg[8]_15 ;
  wire \po_counter_read_val_reg[8]_16 ;
  wire \po_counter_read_val_reg[8]_17 ;
  wire \po_counter_read_val_reg[8]_18 ;
  wire \po_counter_read_val_reg[8]_19 ;
  wire \po_counter_read_val_reg[8]_2 ;
  wire \po_counter_read_val_reg[8]_20 ;
  wire \po_counter_read_val_reg[8]_21 ;
  wire \po_counter_read_val_reg[8]_22 ;
  wire \po_counter_read_val_reg[8]_23 ;
  wire \po_counter_read_val_reg[8]_24 ;
  wire \po_counter_read_val_reg[8]_25 ;
  wire \po_counter_read_val_reg[8]_26 ;
  wire \po_counter_read_val_reg[8]_27 ;
  wire \po_counter_read_val_reg[8]_28 ;
  wire \po_counter_read_val_reg[8]_29 ;
  wire \po_counter_read_val_reg[8]_3 ;
  wire \po_counter_read_val_reg[8]_30 ;
  wire \po_counter_read_val_reg[8]_31 ;
  wire \po_counter_read_val_reg[8]_4 ;
  wire \po_counter_read_val_reg[8]_5 ;
  wire \po_counter_read_val_reg[8]_6 ;
  wire \po_counter_read_val_reg[8]_7 ;
  wire \po_counter_read_val_reg[8]_8 ;
  wire \po_counter_read_val_reg[8]_9 ;
  wire [8:0]\po_counter_read_val_w[0]_0 ;
  wire [8:0]\po_counter_read_val_w[2]_2 ;
  wire \po_stg2_wrcal_cnt_reg[2] ;
  wire \po_stg2_wrcal_cnt_reg[2]_0 ;
  wire \po_stg2_wrcal_cnt_reg[2]_1 ;
  wire \po_stg2_wrcal_cnt_reg[2]_10 ;
  wire \po_stg2_wrcal_cnt_reg[2]_11 ;
  wire \po_stg2_wrcal_cnt_reg[2]_12 ;
  wire \po_stg2_wrcal_cnt_reg[2]_13 ;
  wire \po_stg2_wrcal_cnt_reg[2]_14 ;
  wire \po_stg2_wrcal_cnt_reg[2]_15 ;
  wire \po_stg2_wrcal_cnt_reg[2]_16 ;
  wire \po_stg2_wrcal_cnt_reg[2]_17 ;
  wire \po_stg2_wrcal_cnt_reg[2]_18 ;
  wire \po_stg2_wrcal_cnt_reg[2]_19 ;
  wire \po_stg2_wrcal_cnt_reg[2]_2 ;
  wire \po_stg2_wrcal_cnt_reg[2]_20 ;
  wire \po_stg2_wrcal_cnt_reg[2]_21 ;
  wire \po_stg2_wrcal_cnt_reg[2]_22 ;
  wire \po_stg2_wrcal_cnt_reg[2]_23 ;
  wire \po_stg2_wrcal_cnt_reg[2]_24 ;
  wire \po_stg2_wrcal_cnt_reg[2]_25 ;
  wire \po_stg2_wrcal_cnt_reg[2]_26 ;
  wire \po_stg2_wrcal_cnt_reg[2]_27 ;
  wire \po_stg2_wrcal_cnt_reg[2]_28 ;
  wire \po_stg2_wrcal_cnt_reg[2]_29 ;
  wire \po_stg2_wrcal_cnt_reg[2]_3 ;
  wire \po_stg2_wrcal_cnt_reg[2]_30 ;
  wire \po_stg2_wrcal_cnt_reg[2]_31 ;
  wire \po_stg2_wrcal_cnt_reg[2]_32 ;
  wire \po_stg2_wrcal_cnt_reg[2]_33 ;
  wire \po_stg2_wrcal_cnt_reg[2]_34 ;
  wire \po_stg2_wrcal_cnt_reg[2]_35 ;
  wire \po_stg2_wrcal_cnt_reg[2]_36 ;
  wire \po_stg2_wrcal_cnt_reg[2]_37 ;
  wire \po_stg2_wrcal_cnt_reg[2]_38 ;
  wire \po_stg2_wrcal_cnt_reg[2]_39 ;
  wire \po_stg2_wrcal_cnt_reg[2]_4 ;
  wire \po_stg2_wrcal_cnt_reg[2]_40 ;
  wire \po_stg2_wrcal_cnt_reg[2]_41 ;
  wire \po_stg2_wrcal_cnt_reg[2]_42 ;
  wire \po_stg2_wrcal_cnt_reg[2]_43 ;
  wire \po_stg2_wrcal_cnt_reg[2]_44 ;
  wire \po_stg2_wrcal_cnt_reg[2]_45 ;
  wire \po_stg2_wrcal_cnt_reg[2]_46 ;
  wire \po_stg2_wrcal_cnt_reg[2]_47 ;
  wire \po_stg2_wrcal_cnt_reg[2]_48 ;
  wire \po_stg2_wrcal_cnt_reg[2]_49 ;
  wire \po_stg2_wrcal_cnt_reg[2]_5 ;
  wire \po_stg2_wrcal_cnt_reg[2]_50 ;
  wire \po_stg2_wrcal_cnt_reg[2]_51 ;
  wire \po_stg2_wrcal_cnt_reg[2]_52 ;
  wire \po_stg2_wrcal_cnt_reg[2]_53 ;
  wire \po_stg2_wrcal_cnt_reg[2]_54 ;
  wire \po_stg2_wrcal_cnt_reg[2]_55 ;
  wire \po_stg2_wrcal_cnt_reg[2]_56 ;
  wire \po_stg2_wrcal_cnt_reg[2]_57 ;
  wire \po_stg2_wrcal_cnt_reg[2]_58 ;
  wire \po_stg2_wrcal_cnt_reg[2]_59 ;
  wire \po_stg2_wrcal_cnt_reg[2]_6 ;
  wire \po_stg2_wrcal_cnt_reg[2]_60 ;
  wire \po_stg2_wrcal_cnt_reg[2]_61 ;
  wire \po_stg2_wrcal_cnt_reg[2]_7 ;
  wire \po_stg2_wrcal_cnt_reg[2]_8 ;
  wire \po_stg2_wrcal_cnt_reg[2]_9 ;
  wire rclk_delay_11;
  wire rclk_delay_11_0;
  wire \rclk_delay_reg[10]_srl11_i_1__0_n_0 ;
  wire \rclk_delay_reg[10]_srl11_i_1_n_0 ;
  wire \rd_mux_sel_r_reg[2] ;
  wire \rd_mux_sel_r_reg[2]_0 ;
  wire \rd_mux_sel_r_reg[2]_1 ;
  wire \rd_mux_sel_r_reg[2]_10 ;
  wire \rd_mux_sel_r_reg[2]_100 ;
  wire \rd_mux_sel_r_reg[2]_101 ;
  wire \rd_mux_sel_r_reg[2]_102 ;
  wire \rd_mux_sel_r_reg[2]_103 ;
  wire \rd_mux_sel_r_reg[2]_104 ;
  wire \rd_mux_sel_r_reg[2]_105 ;
  wire \rd_mux_sel_r_reg[2]_106 ;
  wire \rd_mux_sel_r_reg[2]_107 ;
  wire \rd_mux_sel_r_reg[2]_108 ;
  wire \rd_mux_sel_r_reg[2]_109 ;
  wire \rd_mux_sel_r_reg[2]_11 ;
  wire \rd_mux_sel_r_reg[2]_110 ;
  wire \rd_mux_sel_r_reg[2]_111 ;
  wire \rd_mux_sel_r_reg[2]_112 ;
  wire \rd_mux_sel_r_reg[2]_113 ;
  wire \rd_mux_sel_r_reg[2]_114 ;
  wire \rd_mux_sel_r_reg[2]_115 ;
  wire \rd_mux_sel_r_reg[2]_116 ;
  wire \rd_mux_sel_r_reg[2]_117 ;
  wire \rd_mux_sel_r_reg[2]_118 ;
  wire \rd_mux_sel_r_reg[2]_119 ;
  wire \rd_mux_sel_r_reg[2]_12 ;
  wire \rd_mux_sel_r_reg[2]_120 ;
  wire \rd_mux_sel_r_reg[2]_121 ;
  wire \rd_mux_sel_r_reg[2]_122 ;
  wire \rd_mux_sel_r_reg[2]_123 ;
  wire \rd_mux_sel_r_reg[2]_124 ;
  wire \rd_mux_sel_r_reg[2]_125 ;
  wire \rd_mux_sel_r_reg[2]_126 ;
  wire \rd_mux_sel_r_reg[2]_13 ;
  wire \rd_mux_sel_r_reg[2]_14 ;
  wire \rd_mux_sel_r_reg[2]_15 ;
  wire \rd_mux_sel_r_reg[2]_16 ;
  wire \rd_mux_sel_r_reg[2]_17 ;
  wire \rd_mux_sel_r_reg[2]_18 ;
  wire \rd_mux_sel_r_reg[2]_19 ;
  wire \rd_mux_sel_r_reg[2]_2 ;
  wire \rd_mux_sel_r_reg[2]_20 ;
  wire \rd_mux_sel_r_reg[2]_21 ;
  wire \rd_mux_sel_r_reg[2]_22 ;
  wire \rd_mux_sel_r_reg[2]_23 ;
  wire \rd_mux_sel_r_reg[2]_24 ;
  wire \rd_mux_sel_r_reg[2]_25 ;
  wire \rd_mux_sel_r_reg[2]_26 ;
  wire \rd_mux_sel_r_reg[2]_27 ;
  wire \rd_mux_sel_r_reg[2]_28 ;
  wire \rd_mux_sel_r_reg[2]_29 ;
  wire \rd_mux_sel_r_reg[2]_3 ;
  wire \rd_mux_sel_r_reg[2]_30 ;
  wire \rd_mux_sel_r_reg[2]_31 ;
  wire \rd_mux_sel_r_reg[2]_32 ;
  wire \rd_mux_sel_r_reg[2]_33 ;
  wire \rd_mux_sel_r_reg[2]_34 ;
  wire \rd_mux_sel_r_reg[2]_35 ;
  wire \rd_mux_sel_r_reg[2]_36 ;
  wire \rd_mux_sel_r_reg[2]_37 ;
  wire \rd_mux_sel_r_reg[2]_38 ;
  wire \rd_mux_sel_r_reg[2]_39 ;
  wire \rd_mux_sel_r_reg[2]_4 ;
  wire \rd_mux_sel_r_reg[2]_40 ;
  wire \rd_mux_sel_r_reg[2]_41 ;
  wire \rd_mux_sel_r_reg[2]_42 ;
  wire \rd_mux_sel_r_reg[2]_43 ;
  wire \rd_mux_sel_r_reg[2]_44 ;
  wire \rd_mux_sel_r_reg[2]_45 ;
  wire \rd_mux_sel_r_reg[2]_46 ;
  wire \rd_mux_sel_r_reg[2]_47 ;
  wire \rd_mux_sel_r_reg[2]_48 ;
  wire \rd_mux_sel_r_reg[2]_49 ;
  wire \rd_mux_sel_r_reg[2]_5 ;
  wire \rd_mux_sel_r_reg[2]_50 ;
  wire \rd_mux_sel_r_reg[2]_51 ;
  wire \rd_mux_sel_r_reg[2]_52 ;
  wire \rd_mux_sel_r_reg[2]_53 ;
  wire \rd_mux_sel_r_reg[2]_54 ;
  wire \rd_mux_sel_r_reg[2]_55 ;
  wire \rd_mux_sel_r_reg[2]_56 ;
  wire \rd_mux_sel_r_reg[2]_57 ;
  wire \rd_mux_sel_r_reg[2]_58 ;
  wire \rd_mux_sel_r_reg[2]_59 ;
  wire \rd_mux_sel_r_reg[2]_6 ;
  wire \rd_mux_sel_r_reg[2]_60 ;
  wire \rd_mux_sel_r_reg[2]_61 ;
  wire \rd_mux_sel_r_reg[2]_62 ;
  wire \rd_mux_sel_r_reg[2]_63 ;
  wire \rd_mux_sel_r_reg[2]_64 ;
  wire \rd_mux_sel_r_reg[2]_65 ;
  wire \rd_mux_sel_r_reg[2]_66 ;
  wire \rd_mux_sel_r_reg[2]_67 ;
  wire \rd_mux_sel_r_reg[2]_68 ;
  wire \rd_mux_sel_r_reg[2]_69 ;
  wire \rd_mux_sel_r_reg[2]_7 ;
  wire \rd_mux_sel_r_reg[2]_70 ;
  wire \rd_mux_sel_r_reg[2]_71 ;
  wire \rd_mux_sel_r_reg[2]_72 ;
  wire \rd_mux_sel_r_reg[2]_73 ;
  wire \rd_mux_sel_r_reg[2]_74 ;
  wire \rd_mux_sel_r_reg[2]_75 ;
  wire \rd_mux_sel_r_reg[2]_76 ;
  wire \rd_mux_sel_r_reg[2]_77 ;
  wire \rd_mux_sel_r_reg[2]_78 ;
  wire \rd_mux_sel_r_reg[2]_79 ;
  wire \rd_mux_sel_r_reg[2]_8 ;
  wire \rd_mux_sel_r_reg[2]_80 ;
  wire \rd_mux_sel_r_reg[2]_81 ;
  wire \rd_mux_sel_r_reg[2]_82 ;
  wire \rd_mux_sel_r_reg[2]_83 ;
  wire \rd_mux_sel_r_reg[2]_84 ;
  wire \rd_mux_sel_r_reg[2]_85 ;
  wire \rd_mux_sel_r_reg[2]_86 ;
  wire \rd_mux_sel_r_reg[2]_87 ;
  wire \rd_mux_sel_r_reg[2]_88 ;
  wire \rd_mux_sel_r_reg[2]_89 ;
  wire \rd_mux_sel_r_reg[2]_9 ;
  wire \rd_mux_sel_r_reg[2]_90 ;
  wire \rd_mux_sel_r_reg[2]_91 ;
  wire \rd_mux_sel_r_reg[2]_92 ;
  wire \rd_mux_sel_r_reg[2]_93 ;
  wire \rd_mux_sel_r_reg[2]_94 ;
  wire \rd_mux_sel_r_reg[2]_95 ;
  wire \rd_mux_sel_r_reg[2]_96 ;
  wire \rd_mux_sel_r_reg[2]_97 ;
  wire \rd_mux_sel_r_reg[2]_98 ;
  wire \rd_mux_sel_r_reg[2]_99 ;
  wire [63:0]\rd_ptr_reg[3] ;
  wire [63:0]\rd_ptr_reg[3]_0 ;
  wire [63:0]\rd_ptr_reg[3]_1 ;
  wire [63:0]\rd_ptr_reg[3]_2 ;
  wire [63:0]\rd_ptr_reg[3]_3 ;
  wire [63:0]\rd_ptr_reg[3]_4 ;
  wire [63:0]\rd_ptr_reg[3]_5 ;
  wire [63:0]\rd_ptr_reg[3]_6 ;
  wire [35:0]\rd_ptr_reg[3]_7 ;
  wire [23:0]\rd_ptr_reg[3]_8 ;
  wire [3:0]\rd_ptr_reg[3]_9 ;
  wire [1:1]ref_dll_lock_w;
  wire [2:0]ref_dll_lock_w__0;
  wire rst_out_i_1__0_n_0;
  wire rst_out_i_1_n_0;
  wire rst_primitives;
  wire rst_primitives_1;
  wire rst_primitives_i_1__0_n_0;
  wire rst_primitives_i_1_n_0;
  wire rst_tmp;
  wire \rstdiv2_sync_r_reg[11] ;
  wire sync_pulse;
  wire ts_dqs_0;
  wire ts_dqs_1;
  wire ts_dqs_2;
  wire ts_dqs_3;
  wire ts_dqs_4;
  wire ts_dqs_5;
  wire ts_dqs_6;
  wire ts_dqs_7;

  mig_mig_7series_v4_2_ddr_phy_4lanes \ddr_phy_4lanes_0.u_ddr_phy_4lanes 
       (.A_rst_primitives_reg_0(A_rst_primitives_reg),
        .A_rst_primitives_reg_1(A_rst_primitives_reg_0),
        .A_rst_primitives_reg_2(A_rst_primitives_reg_1),
        .A_rst_primitives_reg_3(A_rst_primitives_reg_2),
        .A_rst_primitives_reg_4(A_rst_primitives_reg_7),
        .CLKB0(CLKB0),
        .CLKB0_7(CLKB0_7),
        .CLKB0_8(CLKB0_8),
        .CLKB0_9(CLKB0_9),
        .COUNTERLOADVAL(COUNTERLOADVAL),
        .LD0(LD0),
        .LD0_7(LD0_7),
        .LD0_8(LD0_8),
        .LD0_9(LD0_9),
        .Q(Q),
        .RST0(RST0),
        .SR(SR),
        ._phy_ctl_full_p__0(_phy_ctl_full_p__0[0]),
        .calib_sel(calib_sel[1:0]),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_103 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_111 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ),
        .\entry_cnt_reg[4] (\entry_cnt_reg[4] ),
        .freq_refclk(freq_refclk),
        .\gen_mux_rd[0].mux_rd_fall0_r_reg[0] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ),
        .\gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_136 ),
        .\gen_mux_rd[0].mux_rd_fall1_r_reg[0] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ),
        .\gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_200 ),
        .\gen_mux_rd[0].mux_rd_fall2_r_reg[0] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ),
        .\gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_264 ),
        .\gen_mux_rd[0].mux_rd_fall3_r_reg[0] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_4 ),
        .\gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_328 ),
        .\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] (\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] [1:0]),
        .\gen_mux_rd[0].mux_rd_rise0_r_reg[0] (\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ),
        .\gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_104 ),
        .\gen_mux_rd[0].mux_rd_rise1_r_reg[0] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_4 ),
        .\gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_168 ),
        .\gen_mux_rd[0].mux_rd_rise2_r_reg[0] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_4 ),
        .\gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_232 ),
        .\gen_mux_rd[0].mux_rd_rise3_r_reg[0] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ),
        .\gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_296 ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_4 ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_140 ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_4 ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_204 ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_4 ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_268 ),
        .\gen_mux_rd[1].mux_rd_fall3_r_reg[1] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_4 ),
        .\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_332 ),
        .\gen_mux_rd[1].mux_rd_rise0_r_reg[1] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_4 ),
        .\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_108 ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_4 ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_172 ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_4 ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_236 ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_4 ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_300 ),
        .\gen_mux_rd[2].mux_rd_fall0_r_reg[2] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ),
        .\gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_144 ),
        .\gen_mux_rd[2].mux_rd_fall1_r_reg[2] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ),
        .\gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_208 ),
        .\gen_mux_rd[2].mux_rd_fall2_r_reg[2] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_4 ),
        .\gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_272 ),
        .\gen_mux_rd[2].mux_rd_fall3_r_reg[2] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_4 ),
        .\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_336 ),
        .\gen_mux_rd[2].mux_rd_rise0_r_reg[2] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_4 ),
        .\gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_112 ),
        .\gen_mux_rd[2].mux_rd_rise1_r_reg[2] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ),
        .\gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_176 ),
        .\gen_mux_rd[2].mux_rd_rise2_r_reg[2] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_4 ),
        .\gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_240 ),
        .\gen_mux_rd[2].mux_rd_rise3_r_reg[2] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_4 ),
        .\gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_304 ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_4 ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_148 ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_4 ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_212 ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_4 ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_276 ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_4 ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_340 ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_4 ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_116 ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_4 ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_180 ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_4 ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_244 ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_4 ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_308 ),
        .\gen_mux_rd[4].mux_rd_fall0_r_reg[4] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ),
        .\gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_152 ),
        .\gen_mux_rd[4].mux_rd_fall1_r_reg[4] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ),
        .\gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_216 ),
        .\gen_mux_rd[4].mux_rd_fall2_r_reg[4] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ),
        .\gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_280 ),
        .\gen_mux_rd[4].mux_rd_fall3_r_reg[4] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_4 ),
        .\gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_344 ),
        .\gen_mux_rd[4].mux_rd_rise0_r_reg[4] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ),
        .\gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_120 ),
        .\gen_mux_rd[4].mux_rd_rise1_r_reg[4] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ),
        .\gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_184 ),
        .\gen_mux_rd[4].mux_rd_rise2_r_reg[4] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ),
        .\gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_248 ),
        .\gen_mux_rd[4].mux_rd_rise3_r_reg[4] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ),
        .\gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_312 ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_4 ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_156 ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_4 ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_220 ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_4 ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_284 ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_4 ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_348 ),
        .\gen_mux_rd[5].mux_rd_rise0_r_reg[5] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_4 ),
        .\gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_124 ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_4 ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_188 ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_4 ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_252 ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_4 ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_316 ),
        .\gen_mux_rd[6].mux_rd_fall0_r_reg[6] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_4 ),
        .\gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_160 ),
        .\gen_mux_rd[6].mux_rd_fall1_r_reg[6] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_4 ),
        .\gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_224 ),
        .\gen_mux_rd[6].mux_rd_fall2_r_reg[6] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_4 ),
        .\gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_288 ),
        .\gen_mux_rd[6].mux_rd_fall3_r_reg[6] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_4 ),
        .\gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_352 ),
        .\gen_mux_rd[6].mux_rd_rise0_r_reg[6] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_4 ),
        .\gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_128 ),
        .\gen_mux_rd[6].mux_rd_rise1_r_reg[6] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_4 ),
        .\gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_192 ),
        .\gen_mux_rd[6].mux_rd_rise2_r_reg[6] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_4 ),
        .\gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_256 ),
        .\gen_mux_rd[6].mux_rd_rise3_r_reg[6] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_4 ),
        .\gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_320 ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_5 ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_164 ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_5 ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_228 ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_5 ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_292 ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_5 ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_356 ),
        .\gen_mux_rd[7].mux_rd_rise0_r_reg[7] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_5 ),
        .\gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_132 ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_5 ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_196 ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_5 ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_260 ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_5 ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_324 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] [1:0]),
        .idelay_inc(idelay_inc),
        .idelay_ld_rst(idelay_ld_rst),
        .idelay_ld_rst_0(idelay_ld_rst_0),
        .idelay_ld_rst_1(idelay_ld_rst_1),
        .idelay_ld_rst_2(idelay_ld_rst_2),
        .if_empty(if_empty),
        .if_empty_r(\ddr_byte_lane_B.ddr_byte_lane_B/if_empty_r ),
        .if_empty_r_0(\ddr_byte_lane_C.ddr_byte_lane_C/if_empty_r ),
        .if_empty_v(if_empty_v),
        .ififo_rst_reg(ififo_rst_reg),
        .ififo_rst_reg_0(ififo_rst_reg_0),
        .ififo_rst_reg_1(ififo_rst_reg_1),
        .ififo_rst_reg_2(ififo_rst_reg_2),
        .in0(in0[3:0]),
        .\input_[9].iserdes_dq_.iserdesdq (\input_[9].iserdes_dq_.iserdesdq ),
        .\input_[9].iserdes_dq_.iserdesdq_0 (\input_[9].iserdes_dq_.iserdesdq_0 ),
        .\input_[9].iserdes_dq_.iserdesdq_1 (\input_[9].iserdes_dq_.iserdesdq_1 ),
        .\input_[9].iserdes_dq_.iserdesdq_2 (\input_[9].iserdes_dq_.iserdesdq_2 ),
        .mcGo_w(mcGo_w[0]),
        .mem_dq_in(mem_dq_in[31:0]),
        .mem_dq_out(mem_dq_out[35:0]),
        .mem_dq_ts(mem_dq_ts[35:0]),
        .mem_dqs_in(mem_dqs_in[3:0]),
        .mem_refclk(mem_refclk),
        .\my_empty_reg[1] (\my_empty_reg[1] ),
        .\my_empty_reg[1]_0 (\my_empty_reg[1]_0 ),
        .\my_empty_reg[1]_1 (\my_empty_reg[1]_1 ),
        .\my_empty_reg[1]_2 (\my_empty_reg[1]_2 ),
        .\my_empty_reg[4] (\ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ),
        .\my_empty_reg[4]_0 (\ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ),
        .\my_empty_reg[7] (\my_empty_reg[7] ),
        .\my_empty_reg[7]_0 (\my_empty_reg[7]_0 ),
        .\my_empty_reg[7]_1 (\my_empty_reg[7]_1 ),
        .\my_empty_reg[7]_10 (\my_empty_reg[7]_10 ),
        .\my_empty_reg[7]_11 (\my_empty_reg[7]_11 ),
        .\my_empty_reg[7]_12 (\my_empty_reg[7]_12 ),
        .\my_empty_reg[7]_13 (\my_empty_reg[7]_13 ),
        .\my_empty_reg[7]_14 (\my_empty_reg[7]_14 ),
        .\my_empty_reg[7]_15 (\my_empty_reg[7]_15 ),
        .\my_empty_reg[7]_16 (\my_empty_reg[7]_16 ),
        .\my_empty_reg[7]_17 (\my_empty_reg[7]_17 ),
        .\my_empty_reg[7]_18 (\my_empty_reg[7]_18 ),
        .\my_empty_reg[7]_19 (\my_empty_reg[7]_19 ),
        .\my_empty_reg[7]_2 (\my_empty_reg[7]_2 ),
        .\my_empty_reg[7]_20 (\my_empty_reg[7]_20 ),
        .\my_empty_reg[7]_21 (\my_empty_reg[7]_21 ),
        .\my_empty_reg[7]_22 (\my_empty_reg[7]_22 ),
        .\my_empty_reg[7]_23 (\my_empty_reg[7]_23 ),
        .\my_empty_reg[7]_24 (\my_empty_reg[7]_24 ),
        .\my_empty_reg[7]_25 (\my_empty_reg[7]_25 ),
        .\my_empty_reg[7]_26 (\my_empty_reg[7]_26 ),
        .\my_empty_reg[7]_27 (\my_empty_reg[7]_27 ),
        .\my_empty_reg[7]_28 (\my_empty_reg[7]_28 ),
        .\my_empty_reg[7]_29 (\my_empty_reg[7]_29 ),
        .\my_empty_reg[7]_3 (\my_empty_reg[7]_3 ),
        .\my_empty_reg[7]_30 (\my_empty_reg[7]_30 ),
        .\my_empty_reg[7]_4 (\my_empty_reg[7]_4 ),
        .\my_empty_reg[7]_5 (\my_empty_reg[7]_5 ),
        .\my_empty_reg[7]_6 (\my_empty_reg[7]_6 ),
        .\my_empty_reg[7]_7 (\my_empty_reg[7]_7 ),
        .\my_empty_reg[7]_8 (\my_empty_reg[7]_8 ),
        .\my_empty_reg[7]_9 (\my_empty_reg[7]_9 ),
        .\my_full_reg[1] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_100 ),
        .\my_full_reg[1]_0 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_827 ),
        .\my_full_reg[1]_1 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_826 ),
        .ofs_rdy_r_reg(\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_810 ),
        .ofs_rdy_r_reg_0(\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_809 ),
        .out_dqs_4(out_dqs_4),
        .out_dqs_5(out_dqs_5),
        .out_dqs_6(out_dqs_6),
        .out_dqs_7(out_dqs_7),
        .out_fifo(out_fifo_0),
        .out_fifo_0({out_fifo_1[63:60],out_fifo_1[55:52],out_fifo_1[47:44],out_fifo_1[39:36],out_fifo_1[31:28],out_fifo_1[23:20],out_fifo_1[15:12],out_fifo_1[7:4]}),
        .out_fifo_1(out_fifo_2),
        .out_fifo_i_75__5(out_fifo_i_75__5),
        .out_fifo_i_75__6(out_fifo_i_75__6),
        .out_fifo_i_75__7(out_fifo_i_75__7),
        .phy_ctl_mstr_empty(phy_ctl_mstr_empty),
        .phy_ctl_wr_i2(phy_ctl_wr_i2),
        .phy_ctl_wr_i2_reg(\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_97 ),
        .phy_data_wr_en(phy_data_wr_en),
        .phy_dout(phy_dout),
        .phy_if_empty_r_reg(phy_if_empty_r_i_2_n_0),
        .phy_if_reset(phy_if_reset),
        .phy_mc_ctl_full_r_reg(phy_mc_ctl_full_r_reg),
        .phy_mc_data_full(phy_mc_data_full),
        .phy_rddata_en(phy_rddata_en),
        .phy_read_calib(phy_read_calib),
        .phy_write_calib(phy_write_calib),
        .\pi_counter_read_val_reg[5]_0 (\pi_counter_read_val_reg[5] ),
        .\pi_dqs_found_lanes_r1_reg[0] (\pi_dqs_found_lanes_r1_reg[0] ),
        .\pi_dqs_found_lanes_r1_reg[0]_0 (\pi_dqs_found_lanes_r1_reg[0]_0 ),
        .\pi_dqs_found_lanes_r1_reg[0]_1 (\pi_dqs_found_lanes_r1_reg[0]_1 ),
        .\pi_dqs_found_lanes_r1_reg[0]_2 (\pi_dqs_found_lanes_r1_reg[0]_2 ),
        .\pi_dqs_found_lanes_r1_reg[1] (\pi_dqs_found_lanes_r1_reg[1] ),
        .\pi_dqs_found_lanes_r1_reg[1]_0 (\pi_dqs_found_lanes_r1_reg[1]_0 ),
        .\pi_dqs_found_lanes_r1_reg[1]_1 (\pi_dqs_found_lanes_r1_reg[1]_1 ),
        .\pi_dqs_found_lanes_r1_reg[1]_2 (\pi_dqs_found_lanes_r1_reg[1]_2 ),
        .\pi_dqs_found_lanes_r1_reg[1]_3 (\pi_dqs_found_lanes_r1_reg[1]_3 ),
        .\pi_dqs_found_lanes_r1_reg[2] (\pi_dqs_found_lanes_r1_reg[2] ),
        .\pi_dqs_found_lanes_r1_reg[2]_0 (\pi_dqs_found_lanes_r1_reg[2]_0 ),
        .\pi_dqs_found_lanes_r1_reg[2]_1 (\pi_dqs_found_lanes_r1_reg[2]_1 ),
        .\pi_dqs_found_lanes_r1_reg[2]_2 (\pi_dqs_found_lanes_r1_reg[2]_2 ),
        .\pi_dqs_found_lanes_r1_reg[2]_3 (\pi_dqs_found_lanes_r1_reg[2]_3 ),
        .\pi_dqs_found_lanes_r1_reg[3] (\pi_dqs_found_lanes_r1_reg[3] ),
        .\pi_dqs_found_lanes_r1_reg[3]_0 (\pi_dqs_found_lanes_r1_reg[3]_0 ),
        .\pi_dqs_found_lanes_r1_reg[3]_1 (\pi_dqs_found_lanes_r1_reg[3]_1 ),
        .\pi_dqs_found_lanes_r1_reg[3]_2 (\pi_dqs_found_lanes_r1_reg[3]_2 ),
        .\pi_dqs_found_lanes_r1_reg[3]_3 (\pi_dqs_found_lanes_r1_reg[3]_3 ),
        .pi_phase_locked_all_r1_reg(\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_360 ),
        .pll_locked(pll_locked),
        .\po_counter_read_val_reg[8]_0 (\po_counter_read_val_w[0]_0 ),
        .\po_counter_read_val_reg[8]_1 (\po_counter_read_val_reg[8]_8 ),
        .\po_counter_read_val_reg[8]_10 (\po_counter_read_val_reg[8]_17 ),
        .\po_counter_read_val_reg[8]_11 (\po_counter_read_val_reg[8]_18 ),
        .\po_counter_read_val_reg[8]_12 (\po_counter_read_val_reg[8]_19 ),
        .\po_counter_read_val_reg[8]_2 (\po_counter_read_val_reg[8]_9 ),
        .\po_counter_read_val_reg[8]_3 (\po_counter_read_val_reg[8]_10 ),
        .\po_counter_read_val_reg[8]_4 (\po_counter_read_val_reg[8]_11 ),
        .\po_counter_read_val_reg[8]_5 (\po_counter_read_val_reg[8]_12 ),
        .\po_counter_read_val_reg[8]_6 (\po_counter_read_val_reg[8]_13 ),
        .\po_counter_read_val_reg[8]_7 (\po_counter_read_val_reg[8]_14 ),
        .\po_counter_read_val_reg[8]_8 (\po_counter_read_val_reg[8]_15 ),
        .\po_counter_read_val_reg[8]_9 (\po_counter_read_val_reg[8]_16 ),
        .\po_stg2_wrcal_cnt_reg[1] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_497 ),
        .\po_stg2_wrcal_cnt_reg[1]_0 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_498 ),
        .\po_stg2_wrcal_cnt_reg[1]_1 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_499 ),
        .\po_stg2_wrcal_cnt_reg[1]_10 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_508 ),
        .\po_stg2_wrcal_cnt_reg[1]_11 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_509 ),
        .\po_stg2_wrcal_cnt_reg[1]_12 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_510 ),
        .\po_stg2_wrcal_cnt_reg[1]_13 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_511 ),
        .\po_stg2_wrcal_cnt_reg[1]_14 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_512 ),
        .\po_stg2_wrcal_cnt_reg[1]_15 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_513 ),
        .\po_stg2_wrcal_cnt_reg[1]_16 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_514 ),
        .\po_stg2_wrcal_cnt_reg[1]_17 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_515 ),
        .\po_stg2_wrcal_cnt_reg[1]_18 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_516 ),
        .\po_stg2_wrcal_cnt_reg[1]_19 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_517 ),
        .\po_stg2_wrcal_cnt_reg[1]_2 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_500 ),
        .\po_stg2_wrcal_cnt_reg[1]_20 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_518 ),
        .\po_stg2_wrcal_cnt_reg[1]_21 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_519 ),
        .\po_stg2_wrcal_cnt_reg[1]_22 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_520 ),
        .\po_stg2_wrcal_cnt_reg[1]_23 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_521 ),
        .\po_stg2_wrcal_cnt_reg[1]_24 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_522 ),
        .\po_stg2_wrcal_cnt_reg[1]_25 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_523 ),
        .\po_stg2_wrcal_cnt_reg[1]_26 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_524 ),
        .\po_stg2_wrcal_cnt_reg[1]_27 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_525 ),
        .\po_stg2_wrcal_cnt_reg[1]_28 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_526 ),
        .\po_stg2_wrcal_cnt_reg[1]_29 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_527 ),
        .\po_stg2_wrcal_cnt_reg[1]_3 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_501 ),
        .\po_stg2_wrcal_cnt_reg[1]_30 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_528 ),
        .\po_stg2_wrcal_cnt_reg[1]_31 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_529 ),
        .\po_stg2_wrcal_cnt_reg[1]_32 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_530 ),
        .\po_stg2_wrcal_cnt_reg[1]_33 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_531 ),
        .\po_stg2_wrcal_cnt_reg[1]_34 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_532 ),
        .\po_stg2_wrcal_cnt_reg[1]_35 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_533 ),
        .\po_stg2_wrcal_cnt_reg[1]_36 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_534 ),
        .\po_stg2_wrcal_cnt_reg[1]_37 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_535 ),
        .\po_stg2_wrcal_cnt_reg[1]_38 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_536 ),
        .\po_stg2_wrcal_cnt_reg[1]_39 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_537 ),
        .\po_stg2_wrcal_cnt_reg[1]_4 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_502 ),
        .\po_stg2_wrcal_cnt_reg[1]_40 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_538 ),
        .\po_stg2_wrcal_cnt_reg[1]_41 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_539 ),
        .\po_stg2_wrcal_cnt_reg[1]_42 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_540 ),
        .\po_stg2_wrcal_cnt_reg[1]_43 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_541 ),
        .\po_stg2_wrcal_cnt_reg[1]_44 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_542 ),
        .\po_stg2_wrcal_cnt_reg[1]_45 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_543 ),
        .\po_stg2_wrcal_cnt_reg[1]_46 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_544 ),
        .\po_stg2_wrcal_cnt_reg[1]_47 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_545 ),
        .\po_stg2_wrcal_cnt_reg[1]_48 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_546 ),
        .\po_stg2_wrcal_cnt_reg[1]_49 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_547 ),
        .\po_stg2_wrcal_cnt_reg[1]_5 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_503 ),
        .\po_stg2_wrcal_cnt_reg[1]_50 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_548 ),
        .\po_stg2_wrcal_cnt_reg[1]_51 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_549 ),
        .\po_stg2_wrcal_cnt_reg[1]_52 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_550 ),
        .\po_stg2_wrcal_cnt_reg[1]_53 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_551 ),
        .\po_stg2_wrcal_cnt_reg[1]_54 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_552 ),
        .\po_stg2_wrcal_cnt_reg[1]_55 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_553 ),
        .\po_stg2_wrcal_cnt_reg[1]_56 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_554 ),
        .\po_stg2_wrcal_cnt_reg[1]_57 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_555 ),
        .\po_stg2_wrcal_cnt_reg[1]_58 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_556 ),
        .\po_stg2_wrcal_cnt_reg[1]_59 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_557 ),
        .\po_stg2_wrcal_cnt_reg[1]_6 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_504 ),
        .\po_stg2_wrcal_cnt_reg[1]_60 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_558 ),
        .\po_stg2_wrcal_cnt_reg[1]_61 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_559 ),
        .\po_stg2_wrcal_cnt_reg[1]_62 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_560 ),
        .\po_stg2_wrcal_cnt_reg[1]_7 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_505 ),
        .\po_stg2_wrcal_cnt_reg[1]_8 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_506 ),
        .\po_stg2_wrcal_cnt_reg[1]_9 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_507 ),
        .rclk_delay_11(rclk_delay_11),
        .\rclk_delay_reg[11]_0 (\rclk_delay_reg[10]_srl11_i_1_n_0 ),
        .\rd_mux_sel_r_reg[1] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_369 ),
        .\rd_mux_sel_r_reg[1]_0 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_371 ),
        .\rd_mux_sel_r_reg[1]_1 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_373 ),
        .\rd_mux_sel_r_reg[1]_10 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_391 ),
        .\rd_mux_sel_r_reg[1]_11 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_393 ),
        .\rd_mux_sel_r_reg[1]_12 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_395 ),
        .\rd_mux_sel_r_reg[1]_13 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_397 ),
        .\rd_mux_sel_r_reg[1]_14 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_399 ),
        .\rd_mux_sel_r_reg[1]_15 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_401 ),
        .\rd_mux_sel_r_reg[1]_16 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_403 ),
        .\rd_mux_sel_r_reg[1]_17 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_405 ),
        .\rd_mux_sel_r_reg[1]_18 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_407 ),
        .\rd_mux_sel_r_reg[1]_19 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_409 ),
        .\rd_mux_sel_r_reg[1]_2 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_375 ),
        .\rd_mux_sel_r_reg[1]_20 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_411 ),
        .\rd_mux_sel_r_reg[1]_21 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_413 ),
        .\rd_mux_sel_r_reg[1]_22 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_415 ),
        .\rd_mux_sel_r_reg[1]_23 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_417 ),
        .\rd_mux_sel_r_reg[1]_24 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_419 ),
        .\rd_mux_sel_r_reg[1]_25 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_421 ),
        .\rd_mux_sel_r_reg[1]_26 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_423 ),
        .\rd_mux_sel_r_reg[1]_27 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_425 ),
        .\rd_mux_sel_r_reg[1]_28 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_427 ),
        .\rd_mux_sel_r_reg[1]_29 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_429 ),
        .\rd_mux_sel_r_reg[1]_3 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_377 ),
        .\rd_mux_sel_r_reg[1]_30 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_431 ),
        .\rd_mux_sel_r_reg[1]_31 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_433 ),
        .\rd_mux_sel_r_reg[1]_32 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_435 ),
        .\rd_mux_sel_r_reg[1]_33 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_437 ),
        .\rd_mux_sel_r_reg[1]_34 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_439 ),
        .\rd_mux_sel_r_reg[1]_35 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_441 ),
        .\rd_mux_sel_r_reg[1]_36 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_443 ),
        .\rd_mux_sel_r_reg[1]_37 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_445 ),
        .\rd_mux_sel_r_reg[1]_38 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_447 ),
        .\rd_mux_sel_r_reg[1]_39 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_449 ),
        .\rd_mux_sel_r_reg[1]_4 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_379 ),
        .\rd_mux_sel_r_reg[1]_40 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_451 ),
        .\rd_mux_sel_r_reg[1]_41 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_453 ),
        .\rd_mux_sel_r_reg[1]_42 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_455 ),
        .\rd_mux_sel_r_reg[1]_43 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_457 ),
        .\rd_mux_sel_r_reg[1]_44 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_459 ),
        .\rd_mux_sel_r_reg[1]_45 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_461 ),
        .\rd_mux_sel_r_reg[1]_46 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_463 ),
        .\rd_mux_sel_r_reg[1]_47 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_465 ),
        .\rd_mux_sel_r_reg[1]_48 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_467 ),
        .\rd_mux_sel_r_reg[1]_49 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_469 ),
        .\rd_mux_sel_r_reg[1]_5 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_381 ),
        .\rd_mux_sel_r_reg[1]_50 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_471 ),
        .\rd_mux_sel_r_reg[1]_51 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_473 ),
        .\rd_mux_sel_r_reg[1]_52 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_475 ),
        .\rd_mux_sel_r_reg[1]_53 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_477 ),
        .\rd_mux_sel_r_reg[1]_54 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_479 ),
        .\rd_mux_sel_r_reg[1]_55 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_481 ),
        .\rd_mux_sel_r_reg[1]_56 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_483 ),
        .\rd_mux_sel_r_reg[1]_57 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_485 ),
        .\rd_mux_sel_r_reg[1]_58 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_487 ),
        .\rd_mux_sel_r_reg[1]_59 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_489 ),
        .\rd_mux_sel_r_reg[1]_6 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_383 ),
        .\rd_mux_sel_r_reg[1]_60 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_491 ),
        .\rd_mux_sel_r_reg[1]_61 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_493 ),
        .\rd_mux_sel_r_reg[1]_62 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_495 ),
        .\rd_mux_sel_r_reg[1]_7 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_385 ),
        .\rd_mux_sel_r_reg[1]_8 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_387 ),
        .\rd_mux_sel_r_reg[1]_9 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_389 ),
        .\rd_mux_sel_r_reg[2] (\rd_mux_sel_r_reg[2] ),
        .\rd_mux_sel_r_reg[2]_0 (\rd_mux_sel_r_reg[2]_0 ),
        .\rd_mux_sel_r_reg[2]_1 (\rd_mux_sel_r_reg[2]_1 ),
        .\rd_mux_sel_r_reg[2]_10 (\rd_mux_sel_r_reg[2]_10 ),
        .\rd_mux_sel_r_reg[2]_11 (\rd_mux_sel_r_reg[2]_11 ),
        .\rd_mux_sel_r_reg[2]_12 (\rd_mux_sel_r_reg[2]_12 ),
        .\rd_mux_sel_r_reg[2]_13 (\rd_mux_sel_r_reg[2]_13 ),
        .\rd_mux_sel_r_reg[2]_14 (\rd_mux_sel_r_reg[2]_14 ),
        .\rd_mux_sel_r_reg[2]_15 (\rd_mux_sel_r_reg[2]_15 ),
        .\rd_mux_sel_r_reg[2]_16 (\rd_mux_sel_r_reg[2]_16 ),
        .\rd_mux_sel_r_reg[2]_17 (\rd_mux_sel_r_reg[2]_17 ),
        .\rd_mux_sel_r_reg[2]_18 (\rd_mux_sel_r_reg[2]_18 ),
        .\rd_mux_sel_r_reg[2]_19 (\rd_mux_sel_r_reg[2]_19 ),
        .\rd_mux_sel_r_reg[2]_2 (\rd_mux_sel_r_reg[2]_2 ),
        .\rd_mux_sel_r_reg[2]_20 (\rd_mux_sel_r_reg[2]_20 ),
        .\rd_mux_sel_r_reg[2]_21 (\rd_mux_sel_r_reg[2]_21 ),
        .\rd_mux_sel_r_reg[2]_22 (\rd_mux_sel_r_reg[2]_22 ),
        .\rd_mux_sel_r_reg[2]_23 (\rd_mux_sel_r_reg[2]_23 ),
        .\rd_mux_sel_r_reg[2]_24 (\rd_mux_sel_r_reg[2]_24 ),
        .\rd_mux_sel_r_reg[2]_25 (\rd_mux_sel_r_reg[2]_25 ),
        .\rd_mux_sel_r_reg[2]_26 (\rd_mux_sel_r_reg[2]_26 ),
        .\rd_mux_sel_r_reg[2]_27 (\rd_mux_sel_r_reg[2]_27 ),
        .\rd_mux_sel_r_reg[2]_28 (\rd_mux_sel_r_reg[2]_28 ),
        .\rd_mux_sel_r_reg[2]_29 (\rd_mux_sel_r_reg[2]_29 ),
        .\rd_mux_sel_r_reg[2]_3 (\rd_mux_sel_r_reg[2]_3 ),
        .\rd_mux_sel_r_reg[2]_30 (\rd_mux_sel_r_reg[2]_30 ),
        .\rd_mux_sel_r_reg[2]_31 (\rd_mux_sel_r_reg[2]_31 ),
        .\rd_mux_sel_r_reg[2]_32 (\rd_mux_sel_r_reg[2]_32 ),
        .\rd_mux_sel_r_reg[2]_33 (\rd_mux_sel_r_reg[2]_33 ),
        .\rd_mux_sel_r_reg[2]_34 (\rd_mux_sel_r_reg[2]_34 ),
        .\rd_mux_sel_r_reg[2]_35 (\rd_mux_sel_r_reg[2]_35 ),
        .\rd_mux_sel_r_reg[2]_36 (\rd_mux_sel_r_reg[2]_36 ),
        .\rd_mux_sel_r_reg[2]_37 (\rd_mux_sel_r_reg[2]_37 ),
        .\rd_mux_sel_r_reg[2]_38 (\rd_mux_sel_r_reg[2]_38 ),
        .\rd_mux_sel_r_reg[2]_39 (\rd_mux_sel_r_reg[2]_39 ),
        .\rd_mux_sel_r_reg[2]_4 (\rd_mux_sel_r_reg[2]_4 ),
        .\rd_mux_sel_r_reg[2]_40 (\rd_mux_sel_r_reg[2]_40 ),
        .\rd_mux_sel_r_reg[2]_41 (\rd_mux_sel_r_reg[2]_41 ),
        .\rd_mux_sel_r_reg[2]_42 (\rd_mux_sel_r_reg[2]_42 ),
        .\rd_mux_sel_r_reg[2]_43 (\rd_mux_sel_r_reg[2]_43 ),
        .\rd_mux_sel_r_reg[2]_44 (\rd_mux_sel_r_reg[2]_44 ),
        .\rd_mux_sel_r_reg[2]_45 (\rd_mux_sel_r_reg[2]_45 ),
        .\rd_mux_sel_r_reg[2]_46 (\rd_mux_sel_r_reg[2]_46 ),
        .\rd_mux_sel_r_reg[2]_47 (\rd_mux_sel_r_reg[2]_47 ),
        .\rd_mux_sel_r_reg[2]_48 (\rd_mux_sel_r_reg[2]_48 ),
        .\rd_mux_sel_r_reg[2]_49 (\rd_mux_sel_r_reg[2]_49 ),
        .\rd_mux_sel_r_reg[2]_5 (\rd_mux_sel_r_reg[2]_5 ),
        .\rd_mux_sel_r_reg[2]_50 (\rd_mux_sel_r_reg[2]_50 ),
        .\rd_mux_sel_r_reg[2]_51 (\rd_mux_sel_r_reg[2]_51 ),
        .\rd_mux_sel_r_reg[2]_52 (\rd_mux_sel_r_reg[2]_52 ),
        .\rd_mux_sel_r_reg[2]_53 (\rd_mux_sel_r_reg[2]_53 ),
        .\rd_mux_sel_r_reg[2]_54 (\rd_mux_sel_r_reg[2]_54 ),
        .\rd_mux_sel_r_reg[2]_55 (\rd_mux_sel_r_reg[2]_55 ),
        .\rd_mux_sel_r_reg[2]_56 (\rd_mux_sel_r_reg[2]_56 ),
        .\rd_mux_sel_r_reg[2]_57 (\rd_mux_sel_r_reg[2]_57 ),
        .\rd_mux_sel_r_reg[2]_58 (\rd_mux_sel_r_reg[2]_58 ),
        .\rd_mux_sel_r_reg[2]_59 (\rd_mux_sel_r_reg[2]_59 ),
        .\rd_mux_sel_r_reg[2]_6 (\rd_mux_sel_r_reg[2]_6 ),
        .\rd_mux_sel_r_reg[2]_60 (\rd_mux_sel_r_reg[2]_60 ),
        .\rd_mux_sel_r_reg[2]_61 (\rd_mux_sel_r_reg[2]_61 ),
        .\rd_mux_sel_r_reg[2]_62 (\rd_mux_sel_r_reg[2]_62 ),
        .\rd_mux_sel_r_reg[2]_7 (\rd_mux_sel_r_reg[2]_7 ),
        .\rd_mux_sel_r_reg[2]_8 (\rd_mux_sel_r_reg[2]_8 ),
        .\rd_mux_sel_r_reg[2]_9 (\rd_mux_sel_r_reg[2]_9 ),
        .\rd_ptr_reg[3] (\rd_ptr_reg[3] ),
        .\rd_ptr_reg[3]_0 (\rd_ptr_reg[3]_0 ),
        .\rd_ptr_reg[3]_1 (\rd_ptr_reg[3]_1 ),
        .\rd_ptr_reg[3]_2 (\rd_ptr_reg[3]_2 ),
        .ref_dll_lock_w__0(ref_dll_lock_w__0[0]),
        .rst_out_reg_0(\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_101 ),
        .rst_out_reg_1(rst_out_i_1_n_0),
        .rst_primitives(rst_primitives),
        .rst_primitives_reg_0(rst_primitives_i_1_n_0),
        .sync_pulse(sync_pulse),
        .ts_dqs_4(ts_dqs_4),
        .ts_dqs_5(ts_dqs_5),
        .ts_dqs_6(ts_dqs_6),
        .ts_dqs_7(ts_dqs_7));
  mig_mig_7series_v4_2_ddr_phy_4lanes__parameterized0 \ddr_phy_4lanes_1.u_ddr_phy_4lanes 
       (.C_po_coarse_enable26_out(C_po_coarse_enable26_out),
        .C_po_counter_read_en38_out(C_po_counter_read_en38_out),
        .C_po_fine_enable23_out(C_po_fine_enable23_out),
        .C_po_fine_inc29_out(C_po_fine_inc29_out),
        .D1(D1),
        .D3(D3),
        .D4(D4),
        .D5(D5),
        .D6(D6),
        .D7(D7),
        .D8(D8),
        .D9(D9),
        .PHYCTLWD({Q[10:9],phy_mc_ctl_full_r_reg_0,Q[2:0]}),
        .Q(\po_counter_read_val_w[2]_2 ),
        .RST0(RST0),
        .SR(SR),
        ._phy_ctl_full_p(_phy_ctl_full_p),
        .calib_sel(calib_sel),
        .d_in(d_in),
        .ddr_ck_out(ddr_ck_out),
        .freq_refclk(freq_refclk),
        .mcGo_w__0(mcGo_w__0),
        .mc_address(mc_address),
        .mc_cas_n(mc_cas_n),
        .mc_cs_n(mc_cs_n),
        .mc_ras_n(mc_ras_n),
        .mc_we_n(mc_we_n),
        .mem_dq_out(mem_dq_out[58:36]),
        .mem_out(mem_out),
        .mem_refclk(mem_refclk),
        .mux_address(mux_address),
        .\my_empty_reg[1] (\my_empty_reg[1]_7 ),
        .\my_empty_reg[1]_0 (\my_empty_reg[1]_8 ),
        .\my_empty_reg[1]_1 (\my_empty_reg[1]_9 ),
        .\my_empty_reg[7] (\my_empty_reg[7]_62 ),
        .\my_empty_reg[7]_0 (\my_empty_reg[7]_63 ),
        .\my_empty_reg[7]_1 (\my_empty_reg[7]_64 ),
        .\my_empty_reg[7]_2 (\my_empty_reg[7]_65 ),
        .\my_full_reg[3] (\my_full_reg[3] ),
        .\my_full_reg[3]_0 (\my_full_reg[3]_0 ),
        .\my_full_reg[3]_1 (\my_full_reg[3]_1 ),
        .\my_full_reg[3]_2 (\my_full_reg[3]_2 ),
        .\my_full_reg[3]_3 (\my_full_reg[3]_3 ),
        .of_ctl_full_v(of_ctl_full_v),
        .out_fifo(out_fifo),
        .out_fifo_0(out_fifo_0),
        .out_fifo_1(out_fifo_3),
        .out_fifo_i_39(out_fifo_i_39),
        .out_fifo_i_47__8(out_fifo_i_47__8),
        .phy_cmd_wr_en(phy_cmd_wr_en),
        .phy_ctl_mstr_empty(phy_ctl_mstr_empty),
        .phy_ctl_wr_i2(phy_ctl_wr_i2),
        .phy_mc_ctl_full_r_reg(phy_mc_ctl_full_r_reg),
        .phy_read_calib(phy_read_calib),
        .phy_write_calib(phy_write_calib),
        .pll_locked(pll_locked),
        .\po_counter_read_val_reg[0]_0 (\po_counter_read_val_reg[0] ),
        .\po_counter_read_val_reg[0]_1 (\po_counter_read_val_reg[0]_0 ),
        .\po_counter_read_val_reg[1]_0 (\po_counter_read_val_reg[1] ),
        .\po_counter_read_val_reg[2]_0 (\po_counter_read_val_reg[2] ),
        .\po_counter_read_val_reg[3]_0 (\po_counter_read_val_reg[3] ),
        .\po_counter_read_val_reg[4]_0 (\po_counter_read_val_reg[4] ),
        .\po_counter_read_val_reg[5]_0 (\po_counter_read_val_reg[5] ),
        .\po_counter_read_val_reg[6]_0 (\po_counter_read_val_reg[6] ),
        .\po_counter_read_val_reg[7]_0 (\po_counter_read_val_reg[7] ),
        .\po_counter_read_val_reg[8]_0 (\po_counter_read_val_reg[8] ),
        .\po_counter_read_val_reg[8]_1 (\po_counter_read_val_reg[8]_0 ),
        .\po_counter_read_val_reg[8]_2 (\po_counter_read_val_reg[8]_1 ),
        .\po_counter_read_val_reg[8]_3 (\po_counter_read_val_reg[8]_2 ),
        .\po_counter_read_val_reg[8]_4 (\po_counter_read_val_reg[8]_3 ),
        .\po_counter_read_val_reg[8]_5 (\po_counter_read_val_reg[8]_4 ),
        .\po_counter_read_val_reg[8]_6 (\po_counter_read_val_reg[8]_5 ),
        .\po_counter_read_val_reg[8]_7 (\po_counter_read_val_reg[8]_6 ),
        .\po_counter_read_val_reg[8]_8 (\po_counter_read_val_reg[8]_7 ),
        .\po_rdval_cnt_reg[8] (\po_counter_read_val_w[0]_0 ),
        .\rd_ptr_reg[3] (\rd_ptr_reg[3]_7 ),
        .\rd_ptr_reg[3]_0 (\rd_ptr_reg[3]_8 ),
        .\rd_ptr_reg[3]_1 (\rd_ptr_reg[3]_9 ),
        .ref_dll_lock_w(ref_dll_lock_w),
        .sync_pulse(sync_pulse),
        .\wr_ptr_timing_reg[3] (\entry_cnt_reg[4] ));
  mig_mig_7series_v4_2_ddr_phy_4lanes_13 \ddr_phy_4lanes_2.u_ddr_phy_4lanes 
       (.A_rst_primitives_reg_0(A_rst_primitives_reg_3),
        .A_rst_primitives_reg_1(A_rst_primitives_reg_4),
        .A_rst_primitives_reg_2(A_rst_primitives_reg_5),
        .A_rst_primitives_reg_3(A_rst_primitives_reg_6),
        .A_rst_primitives_reg_4(\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_360 ),
        .CLKB0_10(CLKB0_10),
        .CLKB0_11(CLKB0_11),
        .CLKB0_12(CLKB0_12),
        .CLKB0_13(CLKB0_13),
        .D2(D2),
        .LD0_10(LD0_10),
        .LD0_11(LD0_11),
        .LD0_12(LD0_12),
        .LD0_13(LD0_13),
        .PHYCTLWD({Q[10:9],phy_mc_ctl_full_r_reg_1,Q[2:0]}),
        .Q(\po_counter_read_val_w[2]_2 ),
        .RST0(RST0),
        .SR(SR),
        ._phy_ctl_full_p__0(_phy_ctl_full_p__0[2]),
        .calib_sel(calib_sel[1:0]),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_100 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_826 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_827 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ),
        .\entry_cnt_reg[4] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_809 ),
        .\entry_cnt_reg[4]_0 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_810 ),
        .\entry_cnt_reg[4]_1 (\entry_cnt_reg[4] ),
        .freq_refclk(freq_refclk),
        .\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_385 ),
        .\gen_mux_rd[0].mux_rd_fall0_r_reg[0] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_4 ),
        .\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_417 ),
        .\gen_mux_rd[0].mux_rd_fall1_r_reg[0] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_4 ),
        .\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_449 ),
        .\gen_mux_rd[0].mux_rd_fall2_r_reg[0] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_4 ),
        .\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_481 ),
        .\gen_mux_rd[0].mux_rd_fall3_r_reg[0] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ),
        .\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] (\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ),
        .\gen_mux_rd[0].mux_rd_rise0_r1_reg[0]_0 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_369 ),
        .\gen_mux_rd[0].mux_rd_rise0_r_reg[0] (\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_4 ),
        .\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_401 ),
        .\gen_mux_rd[0].mux_rd_rise1_r_reg[0] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ),
        .\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_433 ),
        .\gen_mux_rd[0].mux_rd_rise2_r_reg[0] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ),
        .\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_465 ),
        .\gen_mux_rd[0].mux_rd_rise3_r_reg[0] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_4 ),
        .\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_387 ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ),
        .\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_419 ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ),
        .\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_451 ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ),
        .\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_483 ),
        .\gen_mux_rd[1].mux_rd_fall3_r_reg[1] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ),
        .\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_371 ),
        .\gen_mux_rd[1].mux_rd_rise0_r_reg[1] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ),
        .\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_403 ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ),
        .\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_435 ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ),
        .\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_467 ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ),
        .\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_389 ),
        .\gen_mux_rd[2].mux_rd_fall0_r_reg[2] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_4 ),
        .\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_421 ),
        .\gen_mux_rd[2].mux_rd_fall1_r_reg[2] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_4 ),
        .\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_453 ),
        .\gen_mux_rd[2].mux_rd_fall2_r_reg[2] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ),
        .\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_485 ),
        .\gen_mux_rd[2].mux_rd_fall3_r_reg[2] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ),
        .\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_373 ),
        .\gen_mux_rd[2].mux_rd_rise0_r_reg[2] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ),
        .\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_405 ),
        .\gen_mux_rd[2].mux_rd_rise1_r_reg[2] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_4 ),
        .\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_437 ),
        .\gen_mux_rd[2].mux_rd_rise2_r_reg[2] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ),
        .\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_469 ),
        .\gen_mux_rd[2].mux_rd_rise3_r_reg[2] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ),
        .\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_391 ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ),
        .\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_423 ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ),
        .\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_455 ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ),
        .\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_487 ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ),
        .\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_375 ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ),
        .\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_407 ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ),
        .\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_439 ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ),
        .\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_471 ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ),
        .\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_393 ),
        .\gen_mux_rd[4].mux_rd_fall0_r_reg[4] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_4 ),
        .\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_425 ),
        .\gen_mux_rd[4].mux_rd_fall1_r_reg[4] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_4 ),
        .\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_457 ),
        .\gen_mux_rd[4].mux_rd_fall2_r_reg[4] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_4 ),
        .\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_489 ),
        .\gen_mux_rd[4].mux_rd_fall3_r_reg[4] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ),
        .\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_377 ),
        .\gen_mux_rd[4].mux_rd_rise0_r_reg[4] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_4 ),
        .\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_409 ),
        .\gen_mux_rd[4].mux_rd_rise1_r_reg[4] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_4 ),
        .\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_441 ),
        .\gen_mux_rd[4].mux_rd_rise2_r_reg[4] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_4 ),
        .\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_473 ),
        .\gen_mux_rd[4].mux_rd_rise3_r_reg[4] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_4 ),
        .\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_395 ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ),
        .\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_427 ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ),
        .\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_459 ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ),
        .\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_491 ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ),
        .\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_379 ),
        .\gen_mux_rd[5].mux_rd_rise0_r_reg[5] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ),
        .\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_411 ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ),
        .\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_443 ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ),
        .\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_475 ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ),
        .\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_397 ),
        .\gen_mux_rd[6].mux_rd_fall0_r_reg[6] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ),
        .\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_429 ),
        .\gen_mux_rd[6].mux_rd_fall1_r_reg[6] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ),
        .\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_461 ),
        .\gen_mux_rd[6].mux_rd_fall2_r_reg[6] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ),
        .\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_493 ),
        .\gen_mux_rd[6].mux_rd_fall3_r_reg[6] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ),
        .\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_381 ),
        .\gen_mux_rd[6].mux_rd_rise0_r_reg[6] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ),
        .\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_413 ),
        .\gen_mux_rd[6].mux_rd_rise1_r_reg[6] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ),
        .\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_445 ),
        .\gen_mux_rd[6].mux_rd_rise2_r_reg[6] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ),
        .\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_477 ),
        .\gen_mux_rd[6].mux_rd_rise3_r_reg[6] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ),
        .\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_399 ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1 ),
        .\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_431 ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1 ),
        .\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_463 ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1 ),
        .\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_495 ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1 ),
        .\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_383 ),
        .\gen_mux_rd[7].mux_rd_rise0_r_reg[7] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1 ),
        .\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_415 ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1 ),
        .\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_447 ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1 ),
        .\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_479 ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_513 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_553 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_529 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_505 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_545 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_497 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_521 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_537 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_514 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_554 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_530 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_506 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_546 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_498 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_522 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_538 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_515 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_555 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_531 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_507 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_547 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_499 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_523 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_539 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_516 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_556 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_532 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_508 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_548 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_500 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_524 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_540 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_517 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_557 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_533 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_509 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_549 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_501 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_525 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_541 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_518 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_558 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_534 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_510 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_550 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_502 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_526 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_542 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_519 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_559 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_535 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_511 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_551 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_503 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_527 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_543 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_520 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_560 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_536 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_512 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_552 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_504 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_528 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_544 ),
        .idelay_inc(idelay_inc),
        .idelay_ld_rst_3(idelay_ld_rst_3),
        .idelay_ld_rst_4(idelay_ld_rst_4),
        .idelay_ld_rst_5(idelay_ld_rst_5),
        .idelay_ld_rst_6(idelay_ld_rst_6),
        .if_empty_v(if_empty_v),
        .ififo_rst_reg(ififo_rst_reg_3),
        .ififo_rst_reg_0(ififo_rst_reg_4),
        .ififo_rst_reg_1(ififo_rst_reg_5),
        .ififo_rst_reg_2(ififo_rst_reg_6),
        .in0(in0[7:4]),
        .\input_[9].iserdes_dq_.iserdesdq (\input_[9].iserdes_dq_.iserdesdq_3 ),
        .\input_[9].iserdes_dq_.iserdesdq_0 (\input_[9].iserdes_dq_.iserdesdq_4 ),
        .\input_[9].iserdes_dq_.iserdesdq_1 (\input_[9].iserdes_dq_.iserdesdq_5 ),
        .\input_[9].iserdes_dq_.iserdesdq_2 (\input_[9].iserdes_dq_.iserdesdq_6 ),
        .mcGo_w(mcGo_w[2]),
        .mem_dq_in(mem_dq_in[63:32]),
        .mem_dq_out(mem_dq_out[94:59]),
        .mem_dq_ts(mem_dq_ts[71:36]),
        .mem_dqs_in(mem_dqs_in[7:4]),
        .mem_refclk(mem_refclk),
        .\my_empty_reg[1] (\my_empty_reg[1]_3 ),
        .\my_empty_reg[1]_0 (\my_empty_reg[1]_4 ),
        .\my_empty_reg[1]_1 (\my_empty_reg[1]_5 ),
        .\my_empty_reg[1]_2 (\my_empty_reg[1]_6 ),
        .\my_empty_reg[7] (\my_empty_reg[7]_31 ),
        .\my_empty_reg[7]_0 (\my_empty_reg[7]_32 ),
        .\my_empty_reg[7]_1 (\my_empty_reg[7]_33 ),
        .\my_empty_reg[7]_10 (\my_empty_reg[7]_42 ),
        .\my_empty_reg[7]_11 (\my_empty_reg[7]_43 ),
        .\my_empty_reg[7]_12 (\my_empty_reg[7]_44 ),
        .\my_empty_reg[7]_13 (\my_empty_reg[7]_45 ),
        .\my_empty_reg[7]_14 (\my_empty_reg[7]_46 ),
        .\my_empty_reg[7]_15 (\my_empty_reg[7]_47 ),
        .\my_empty_reg[7]_16 (\my_empty_reg[7]_48 ),
        .\my_empty_reg[7]_17 (\my_empty_reg[7]_49 ),
        .\my_empty_reg[7]_18 (\my_empty_reg[7]_50 ),
        .\my_empty_reg[7]_19 (\my_empty_reg[7]_51 ),
        .\my_empty_reg[7]_2 (\my_empty_reg[7]_34 ),
        .\my_empty_reg[7]_20 (\my_empty_reg[7]_52 ),
        .\my_empty_reg[7]_21 (\my_empty_reg[7]_53 ),
        .\my_empty_reg[7]_22 (\my_empty_reg[7]_54 ),
        .\my_empty_reg[7]_23 (\my_empty_reg[7]_55 ),
        .\my_empty_reg[7]_24 (\my_empty_reg[7]_56 ),
        .\my_empty_reg[7]_25 (\my_empty_reg[7]_57 ),
        .\my_empty_reg[7]_26 (\my_empty_reg[7]_58 ),
        .\my_empty_reg[7]_27 (\my_empty_reg[7]_59 ),
        .\my_empty_reg[7]_28 (\my_empty_reg[7]_60 ),
        .\my_empty_reg[7]_29 (\my_empty_reg[7]_61 ),
        .\my_empty_reg[7]_3 (\my_empty_reg[7]_35 ),
        .\my_empty_reg[7]_4 (\my_empty_reg[7]_36 ),
        .\my_empty_reg[7]_5 (\my_empty_reg[7]_37 ),
        .\my_empty_reg[7]_6 (\my_empty_reg[7]_38 ),
        .\my_empty_reg[7]_7 (\my_empty_reg[7]_39 ),
        .\my_empty_reg[7]_8 (\my_empty_reg[7]_40 ),
        .\my_empty_reg[7]_9 (\my_empty_reg[7]_41 ),
        .\my_full_reg[1] (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_111 ),
        .\my_full_reg[1]_0 (\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_103 ),
        .out_dqs_0(out_dqs_0),
        .out_dqs_1(out_dqs_1),
        .out_dqs_2(out_dqs_2),
        .out_dqs_3(out_dqs_3),
        .out_fifo(out_fifo_0),
        .out_fifo_0({out_fifo_1[59:56],out_fifo_1[51:48],out_fifo_1[43:40],out_fifo_1[35:32],out_fifo_1[27:24],out_fifo_1[19:16],out_fifo_1[11:8],out_fifo_1[3:0]}),
        .out_fifo_1(out_fifo_2),
        .out_fifo_i_75__0(out_fifo_i_75__0),
        .out_fifo_i_75__1(out_fifo_i_75__1),
        .out_fifo_i_75__2(out_fifo_i_75__2),
        .out_fifo_i_75__3(out_fifo_i_75__3),
        .p_0_out(p_0_out),
        .phy_ctl_mstr_empty(phy_ctl_mstr_empty),
        .phy_ctl_wr_i2(phy_ctl_wr_i2),
        .phy_ctl_wr_i2_reg(\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_93 ),
        .phy_data_wr_en(phy_data_wr_en),
        .phy_if_reset(phy_if_reset),
        .phy_mc_ctl_full_r_reg(phy_mc_ctl_full_r_reg),
        .phy_read_calib(phy_read_calib),
        .phy_write_calib(phy_write_calib),
        .\pi_counter_read_val_reg[5]_0 (\pi_counter_read_val_reg[5]_0 ),
        .\pi_dqs_found_lanes_r1_reg[10] (\pi_dqs_found_lanes_r1_reg[10] ),
        .\pi_dqs_found_lanes_r1_reg[10]_0 (\pi_dqs_found_lanes_r1_reg[10]_0 ),
        .\pi_dqs_found_lanes_r1_reg[10]_1 (\pi_dqs_found_lanes_r1_reg[10]_1 ),
        .\pi_dqs_found_lanes_r1_reg[10]_2 (\pi_dqs_found_lanes_r1_reg[10]_2 ),
        .\pi_dqs_found_lanes_r1_reg[10]_3 (\pi_dqs_found_lanes_r1_reg[10]_3 ),
        .\pi_dqs_found_lanes_r1_reg[11] (\pi_dqs_found_lanes_r1_reg[11] ),
        .\pi_dqs_found_lanes_r1_reg[11]_0 (\pi_dqs_found_lanes_r1_reg[11]_0 ),
        .\pi_dqs_found_lanes_r1_reg[11]_1 (\pi_dqs_found_lanes_r1_reg[11]_1 ),
        .\pi_dqs_found_lanes_r1_reg[11]_2 (\pi_dqs_found_lanes_r1_reg[11]_2 ),
        .\pi_dqs_found_lanes_r1_reg[11]_3 (\pi_dqs_found_lanes_r1_reg[11]_3 ),
        .\pi_dqs_found_lanes_r1_reg[8] (\pi_dqs_found_lanes_r1_reg[8] ),
        .\pi_dqs_found_lanes_r1_reg[8]_0 (\pi_dqs_found_lanes_r1_reg[8]_0 ),
        .\pi_dqs_found_lanes_r1_reg[8]_1 (\pi_dqs_found_lanes_r1_reg[8]_1 ),
        .\pi_dqs_found_lanes_r1_reg[8]_2 (\pi_dqs_found_lanes_r1_reg[8]_2 ),
        .\pi_dqs_found_lanes_r1_reg[8]_3 (\pi_dqs_found_lanes_r1_reg[8]_3 ),
        .\pi_dqs_found_lanes_r1_reg[9] (\pi_dqs_found_lanes_r1_reg[9] ),
        .\pi_dqs_found_lanes_r1_reg[9]_0 (\pi_dqs_found_lanes_r1_reg[9]_0 ),
        .\pi_dqs_found_lanes_r1_reg[9]_1 (\pi_dqs_found_lanes_r1_reg[9]_1 ),
        .\pi_dqs_found_lanes_r1_reg[9]_2 (\pi_dqs_found_lanes_r1_reg[9]_2 ),
        .\pi_dqs_found_lanes_r1_reg[9]_3 (\pi_dqs_found_lanes_r1_reg[9]_3 ),
        .pll_locked(pll_locked),
        .\po_counter_read_val_reg[8]_0 (\po_counter_read_val_reg[8]_20 ),
        .\po_counter_read_val_reg[8]_1 (\po_counter_read_val_reg[8]_21 ),
        .\po_counter_read_val_reg[8]_10 (\po_counter_read_val_reg[8]_30 ),
        .\po_counter_read_val_reg[8]_11 (\po_counter_read_val_reg[8]_31 ),
        .\po_counter_read_val_reg[8]_2 (\po_counter_read_val_reg[8]_22 ),
        .\po_counter_read_val_reg[8]_3 (\po_counter_read_val_reg[8]_23 ),
        .\po_counter_read_val_reg[8]_4 (\po_counter_read_val_reg[8]_24 ),
        .\po_counter_read_val_reg[8]_5 (\po_counter_read_val_reg[8]_25 ),
        .\po_counter_read_val_reg[8]_6 (\po_counter_read_val_reg[8]_26 ),
        .\po_counter_read_val_reg[8]_7 (\po_counter_read_val_reg[8]_27 ),
        .\po_counter_read_val_reg[8]_8 (\po_counter_read_val_reg[8]_28 ),
        .\po_counter_read_val_reg[8]_9 (\po_counter_read_val_reg[8]_29 ),
        .\po_stg2_wrcal_cnt_reg[2] (\po_stg2_wrcal_cnt_reg[2] ),
        .\po_stg2_wrcal_cnt_reg[2]_0 (\po_stg2_wrcal_cnt_reg[2]_0 ),
        .\po_stg2_wrcal_cnt_reg[2]_1 (\po_stg2_wrcal_cnt_reg[2]_1 ),
        .\po_stg2_wrcal_cnt_reg[2]_10 (\po_stg2_wrcal_cnt_reg[2]_10 ),
        .\po_stg2_wrcal_cnt_reg[2]_11 (\po_stg2_wrcal_cnt_reg[2]_11 ),
        .\po_stg2_wrcal_cnt_reg[2]_12 (\po_stg2_wrcal_cnt_reg[2]_12 ),
        .\po_stg2_wrcal_cnt_reg[2]_13 (\po_stg2_wrcal_cnt_reg[2]_13 ),
        .\po_stg2_wrcal_cnt_reg[2]_14 (\po_stg2_wrcal_cnt_reg[2]_14 ),
        .\po_stg2_wrcal_cnt_reg[2]_15 (\po_stg2_wrcal_cnt_reg[2]_15 ),
        .\po_stg2_wrcal_cnt_reg[2]_16 (\po_stg2_wrcal_cnt_reg[2]_16 ),
        .\po_stg2_wrcal_cnt_reg[2]_17 (\po_stg2_wrcal_cnt_reg[2]_17 ),
        .\po_stg2_wrcal_cnt_reg[2]_18 (\po_stg2_wrcal_cnt_reg[2]_18 ),
        .\po_stg2_wrcal_cnt_reg[2]_19 (\po_stg2_wrcal_cnt_reg[2]_19 ),
        .\po_stg2_wrcal_cnt_reg[2]_2 (\po_stg2_wrcal_cnt_reg[2]_2 ),
        .\po_stg2_wrcal_cnt_reg[2]_20 (\po_stg2_wrcal_cnt_reg[2]_20 ),
        .\po_stg2_wrcal_cnt_reg[2]_21 (\po_stg2_wrcal_cnt_reg[2]_21 ),
        .\po_stg2_wrcal_cnt_reg[2]_22 (\po_stg2_wrcal_cnt_reg[2]_22 ),
        .\po_stg2_wrcal_cnt_reg[2]_23 (\po_stg2_wrcal_cnt_reg[2]_23 ),
        .\po_stg2_wrcal_cnt_reg[2]_24 (\po_stg2_wrcal_cnt_reg[2]_24 ),
        .\po_stg2_wrcal_cnt_reg[2]_25 (\po_stg2_wrcal_cnt_reg[2]_25 ),
        .\po_stg2_wrcal_cnt_reg[2]_26 (\po_stg2_wrcal_cnt_reg[2]_26 ),
        .\po_stg2_wrcal_cnt_reg[2]_27 (\po_stg2_wrcal_cnt_reg[2]_27 ),
        .\po_stg2_wrcal_cnt_reg[2]_28 (\po_stg2_wrcal_cnt_reg[2]_28 ),
        .\po_stg2_wrcal_cnt_reg[2]_29 (\po_stg2_wrcal_cnt_reg[2]_29 ),
        .\po_stg2_wrcal_cnt_reg[2]_3 (\po_stg2_wrcal_cnt_reg[2]_3 ),
        .\po_stg2_wrcal_cnt_reg[2]_30 (\po_stg2_wrcal_cnt_reg[2]_30 ),
        .\po_stg2_wrcal_cnt_reg[2]_31 (\po_stg2_wrcal_cnt_reg[2]_31 ),
        .\po_stg2_wrcal_cnt_reg[2]_32 (\po_stg2_wrcal_cnt_reg[2]_32 ),
        .\po_stg2_wrcal_cnt_reg[2]_33 (\po_stg2_wrcal_cnt_reg[2]_33 ),
        .\po_stg2_wrcal_cnt_reg[2]_34 (\po_stg2_wrcal_cnt_reg[2]_34 ),
        .\po_stg2_wrcal_cnt_reg[2]_35 (\po_stg2_wrcal_cnt_reg[2]_35 ),
        .\po_stg2_wrcal_cnt_reg[2]_36 (\po_stg2_wrcal_cnt_reg[2]_36 ),
        .\po_stg2_wrcal_cnt_reg[2]_37 (\po_stg2_wrcal_cnt_reg[2]_37 ),
        .\po_stg2_wrcal_cnt_reg[2]_38 (\po_stg2_wrcal_cnt_reg[2]_38 ),
        .\po_stg2_wrcal_cnt_reg[2]_39 (\po_stg2_wrcal_cnt_reg[2]_39 ),
        .\po_stg2_wrcal_cnt_reg[2]_4 (\po_stg2_wrcal_cnt_reg[2]_4 ),
        .\po_stg2_wrcal_cnt_reg[2]_40 (\po_stg2_wrcal_cnt_reg[2]_40 ),
        .\po_stg2_wrcal_cnt_reg[2]_41 (\po_stg2_wrcal_cnt_reg[2]_41 ),
        .\po_stg2_wrcal_cnt_reg[2]_42 (\po_stg2_wrcal_cnt_reg[2]_42 ),
        .\po_stg2_wrcal_cnt_reg[2]_43 (\po_stg2_wrcal_cnt_reg[2]_43 ),
        .\po_stg2_wrcal_cnt_reg[2]_44 (\po_stg2_wrcal_cnt_reg[2]_44 ),
        .\po_stg2_wrcal_cnt_reg[2]_45 (\po_stg2_wrcal_cnt_reg[2]_45 ),
        .\po_stg2_wrcal_cnt_reg[2]_46 (\po_stg2_wrcal_cnt_reg[2]_46 ),
        .\po_stg2_wrcal_cnt_reg[2]_47 (\po_stg2_wrcal_cnt_reg[2]_47 ),
        .\po_stg2_wrcal_cnt_reg[2]_48 (\po_stg2_wrcal_cnt_reg[2]_48 ),
        .\po_stg2_wrcal_cnt_reg[2]_49 (\po_stg2_wrcal_cnt_reg[2]_49 ),
        .\po_stg2_wrcal_cnt_reg[2]_5 (\po_stg2_wrcal_cnt_reg[2]_5 ),
        .\po_stg2_wrcal_cnt_reg[2]_50 (\po_stg2_wrcal_cnt_reg[2]_50 ),
        .\po_stg2_wrcal_cnt_reg[2]_51 (\po_stg2_wrcal_cnt_reg[2]_51 ),
        .\po_stg2_wrcal_cnt_reg[2]_52 (\po_stg2_wrcal_cnt_reg[2]_52 ),
        .\po_stg2_wrcal_cnt_reg[2]_53 (\po_stg2_wrcal_cnt_reg[2]_53 ),
        .\po_stg2_wrcal_cnt_reg[2]_54 (\po_stg2_wrcal_cnt_reg[2]_54 ),
        .\po_stg2_wrcal_cnt_reg[2]_55 (\po_stg2_wrcal_cnt_reg[2]_55 ),
        .\po_stg2_wrcal_cnt_reg[2]_56 (\po_stg2_wrcal_cnt_reg[2]_56 ),
        .\po_stg2_wrcal_cnt_reg[2]_57 (\po_stg2_wrcal_cnt_reg[2]_57 ),
        .\po_stg2_wrcal_cnt_reg[2]_58 (\po_stg2_wrcal_cnt_reg[2]_58 ),
        .\po_stg2_wrcal_cnt_reg[2]_59 (\po_stg2_wrcal_cnt_reg[2]_59 ),
        .\po_stg2_wrcal_cnt_reg[2]_6 (\po_stg2_wrcal_cnt_reg[2]_6 ),
        .\po_stg2_wrcal_cnt_reg[2]_60 (\po_stg2_wrcal_cnt_reg[2]_60 ),
        .\po_stg2_wrcal_cnt_reg[2]_61 (\po_stg2_wrcal_cnt_reg[2]_61 ),
        .\po_stg2_wrcal_cnt_reg[2]_7 (\po_stg2_wrcal_cnt_reg[2]_7 ),
        .\po_stg2_wrcal_cnt_reg[2]_8 (\po_stg2_wrcal_cnt_reg[2]_8 ),
        .\po_stg2_wrcal_cnt_reg[2]_9 (\po_stg2_wrcal_cnt_reg[2]_9 ),
        .rclk_delay_11(rclk_delay_11_0),
        .\rclk_delay_reg[11]_0 (\rclk_delay_reg[10]_srl11_i_1__0_n_0 ),
        .\rd_mux_sel_r_reg[0] (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_104 ),
        .\rd_mux_sel_r_reg[0]_0 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_108 ),
        .\rd_mux_sel_r_reg[0]_1 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_112 ),
        .\rd_mux_sel_r_reg[0]_10 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_148 ),
        .\rd_mux_sel_r_reg[0]_11 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_152 ),
        .\rd_mux_sel_r_reg[0]_12 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_156 ),
        .\rd_mux_sel_r_reg[0]_13 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_160 ),
        .\rd_mux_sel_r_reg[0]_14 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_164 ),
        .\rd_mux_sel_r_reg[0]_15 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_168 ),
        .\rd_mux_sel_r_reg[0]_16 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_172 ),
        .\rd_mux_sel_r_reg[0]_17 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_176 ),
        .\rd_mux_sel_r_reg[0]_18 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_180 ),
        .\rd_mux_sel_r_reg[0]_19 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_184 ),
        .\rd_mux_sel_r_reg[0]_2 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_116 ),
        .\rd_mux_sel_r_reg[0]_20 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_188 ),
        .\rd_mux_sel_r_reg[0]_21 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_192 ),
        .\rd_mux_sel_r_reg[0]_22 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_196 ),
        .\rd_mux_sel_r_reg[0]_23 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_200 ),
        .\rd_mux_sel_r_reg[0]_24 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_204 ),
        .\rd_mux_sel_r_reg[0]_25 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_208 ),
        .\rd_mux_sel_r_reg[0]_26 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_212 ),
        .\rd_mux_sel_r_reg[0]_27 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_216 ),
        .\rd_mux_sel_r_reg[0]_28 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_220 ),
        .\rd_mux_sel_r_reg[0]_29 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_224 ),
        .\rd_mux_sel_r_reg[0]_3 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_120 ),
        .\rd_mux_sel_r_reg[0]_30 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_228 ),
        .\rd_mux_sel_r_reg[0]_31 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_232 ),
        .\rd_mux_sel_r_reg[0]_32 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_236 ),
        .\rd_mux_sel_r_reg[0]_33 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_240 ),
        .\rd_mux_sel_r_reg[0]_34 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_244 ),
        .\rd_mux_sel_r_reg[0]_35 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_248 ),
        .\rd_mux_sel_r_reg[0]_36 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_252 ),
        .\rd_mux_sel_r_reg[0]_37 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_256 ),
        .\rd_mux_sel_r_reg[0]_38 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_260 ),
        .\rd_mux_sel_r_reg[0]_39 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_264 ),
        .\rd_mux_sel_r_reg[0]_4 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_124 ),
        .\rd_mux_sel_r_reg[0]_40 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_268 ),
        .\rd_mux_sel_r_reg[0]_41 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_272 ),
        .\rd_mux_sel_r_reg[0]_42 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_276 ),
        .\rd_mux_sel_r_reg[0]_43 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_280 ),
        .\rd_mux_sel_r_reg[0]_44 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_284 ),
        .\rd_mux_sel_r_reg[0]_45 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_288 ),
        .\rd_mux_sel_r_reg[0]_46 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_292 ),
        .\rd_mux_sel_r_reg[0]_47 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_296 ),
        .\rd_mux_sel_r_reg[0]_48 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_300 ),
        .\rd_mux_sel_r_reg[0]_49 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_304 ),
        .\rd_mux_sel_r_reg[0]_5 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_128 ),
        .\rd_mux_sel_r_reg[0]_50 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_308 ),
        .\rd_mux_sel_r_reg[0]_51 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_312 ),
        .\rd_mux_sel_r_reg[0]_52 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_316 ),
        .\rd_mux_sel_r_reg[0]_53 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_320 ),
        .\rd_mux_sel_r_reg[0]_54 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_324 ),
        .\rd_mux_sel_r_reg[0]_55 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_328 ),
        .\rd_mux_sel_r_reg[0]_56 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_332 ),
        .\rd_mux_sel_r_reg[0]_57 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_336 ),
        .\rd_mux_sel_r_reg[0]_58 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_340 ),
        .\rd_mux_sel_r_reg[0]_59 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_344 ),
        .\rd_mux_sel_r_reg[0]_6 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_132 ),
        .\rd_mux_sel_r_reg[0]_60 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_348 ),
        .\rd_mux_sel_r_reg[0]_61 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_352 ),
        .\rd_mux_sel_r_reg[0]_62 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_356 ),
        .\rd_mux_sel_r_reg[0]_7 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_136 ),
        .\rd_mux_sel_r_reg[0]_8 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_140 ),
        .\rd_mux_sel_r_reg[0]_9 (\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_144 ),
        .\rd_mux_sel_r_reg[2] (\rd_mux_sel_r_reg[2]_63 ),
        .\rd_mux_sel_r_reg[2]_0 (\rd_mux_sel_r_reg[2]_64 ),
        .\rd_mux_sel_r_reg[2]_1 (\rd_mux_sel_r_reg[2]_65 ),
        .\rd_mux_sel_r_reg[2]_10 (\rd_mux_sel_r_reg[2]_74 ),
        .\rd_mux_sel_r_reg[2]_11 (\rd_mux_sel_r_reg[2]_75 ),
        .\rd_mux_sel_r_reg[2]_12 (\rd_mux_sel_r_reg[2]_76 ),
        .\rd_mux_sel_r_reg[2]_13 (\rd_mux_sel_r_reg[2]_77 ),
        .\rd_mux_sel_r_reg[2]_14 (\rd_mux_sel_r_reg[2]_78 ),
        .\rd_mux_sel_r_reg[2]_15 (\rd_mux_sel_r_reg[2]_79 ),
        .\rd_mux_sel_r_reg[2]_16 (\rd_mux_sel_r_reg[2]_80 ),
        .\rd_mux_sel_r_reg[2]_17 (\rd_mux_sel_r_reg[2]_81 ),
        .\rd_mux_sel_r_reg[2]_18 (\rd_mux_sel_r_reg[2]_82 ),
        .\rd_mux_sel_r_reg[2]_19 (\rd_mux_sel_r_reg[2]_83 ),
        .\rd_mux_sel_r_reg[2]_2 (\rd_mux_sel_r_reg[2]_66 ),
        .\rd_mux_sel_r_reg[2]_20 (\rd_mux_sel_r_reg[2]_84 ),
        .\rd_mux_sel_r_reg[2]_21 (\rd_mux_sel_r_reg[2]_85 ),
        .\rd_mux_sel_r_reg[2]_22 (\rd_mux_sel_r_reg[2]_86 ),
        .\rd_mux_sel_r_reg[2]_23 (\rd_mux_sel_r_reg[2]_87 ),
        .\rd_mux_sel_r_reg[2]_24 (\rd_mux_sel_r_reg[2]_88 ),
        .\rd_mux_sel_r_reg[2]_25 (\rd_mux_sel_r_reg[2]_89 ),
        .\rd_mux_sel_r_reg[2]_26 (\rd_mux_sel_r_reg[2]_90 ),
        .\rd_mux_sel_r_reg[2]_27 (\rd_mux_sel_r_reg[2]_91 ),
        .\rd_mux_sel_r_reg[2]_28 (\rd_mux_sel_r_reg[2]_92 ),
        .\rd_mux_sel_r_reg[2]_29 (\rd_mux_sel_r_reg[2]_93 ),
        .\rd_mux_sel_r_reg[2]_3 (\rd_mux_sel_r_reg[2]_67 ),
        .\rd_mux_sel_r_reg[2]_30 (\rd_mux_sel_r_reg[2]_94 ),
        .\rd_mux_sel_r_reg[2]_31 (\rd_mux_sel_r_reg[2]_95 ),
        .\rd_mux_sel_r_reg[2]_32 (\rd_mux_sel_r_reg[2]_96 ),
        .\rd_mux_sel_r_reg[2]_33 (\rd_mux_sel_r_reg[2]_97 ),
        .\rd_mux_sel_r_reg[2]_34 (\rd_mux_sel_r_reg[2]_98 ),
        .\rd_mux_sel_r_reg[2]_35 (\rd_mux_sel_r_reg[2]_99 ),
        .\rd_mux_sel_r_reg[2]_36 (\rd_mux_sel_r_reg[2]_100 ),
        .\rd_mux_sel_r_reg[2]_37 (\rd_mux_sel_r_reg[2]_101 ),
        .\rd_mux_sel_r_reg[2]_38 (\rd_mux_sel_r_reg[2]_102 ),
        .\rd_mux_sel_r_reg[2]_39 (\rd_mux_sel_r_reg[2]_103 ),
        .\rd_mux_sel_r_reg[2]_4 (\rd_mux_sel_r_reg[2]_68 ),
        .\rd_mux_sel_r_reg[2]_40 (\rd_mux_sel_r_reg[2]_104 ),
        .\rd_mux_sel_r_reg[2]_41 (\rd_mux_sel_r_reg[2]_105 ),
        .\rd_mux_sel_r_reg[2]_42 (\rd_mux_sel_r_reg[2]_106 ),
        .\rd_mux_sel_r_reg[2]_43 (\rd_mux_sel_r_reg[2]_107 ),
        .\rd_mux_sel_r_reg[2]_44 (\rd_mux_sel_r_reg[2]_108 ),
        .\rd_mux_sel_r_reg[2]_45 (\rd_mux_sel_r_reg[2]_109 ),
        .\rd_mux_sel_r_reg[2]_46 (\rd_mux_sel_r_reg[2]_110 ),
        .\rd_mux_sel_r_reg[2]_47 (\rd_mux_sel_r_reg[2]_111 ),
        .\rd_mux_sel_r_reg[2]_48 (\rd_mux_sel_r_reg[2]_112 ),
        .\rd_mux_sel_r_reg[2]_49 (\rd_mux_sel_r_reg[2]_113 ),
        .\rd_mux_sel_r_reg[2]_5 (\rd_mux_sel_r_reg[2]_69 ),
        .\rd_mux_sel_r_reg[2]_50 (\rd_mux_sel_r_reg[2]_114 ),
        .\rd_mux_sel_r_reg[2]_51 (\rd_mux_sel_r_reg[2]_115 ),
        .\rd_mux_sel_r_reg[2]_52 (\rd_mux_sel_r_reg[2]_116 ),
        .\rd_mux_sel_r_reg[2]_53 (\rd_mux_sel_r_reg[2]_117 ),
        .\rd_mux_sel_r_reg[2]_54 (\rd_mux_sel_r_reg[2]_118 ),
        .\rd_mux_sel_r_reg[2]_55 (\rd_mux_sel_r_reg[2]_119 ),
        .\rd_mux_sel_r_reg[2]_56 (\rd_mux_sel_r_reg[2]_120 ),
        .\rd_mux_sel_r_reg[2]_57 (\rd_mux_sel_r_reg[2]_121 ),
        .\rd_mux_sel_r_reg[2]_58 (\rd_mux_sel_r_reg[2]_122 ),
        .\rd_mux_sel_r_reg[2]_59 (\rd_mux_sel_r_reg[2]_123 ),
        .\rd_mux_sel_r_reg[2]_6 (\rd_mux_sel_r_reg[2]_70 ),
        .\rd_mux_sel_r_reg[2]_60 (\rd_mux_sel_r_reg[2]_124 ),
        .\rd_mux_sel_r_reg[2]_61 (\rd_mux_sel_r_reg[2]_125 ),
        .\rd_mux_sel_r_reg[2]_62 (\rd_mux_sel_r_reg[2]_126 ),
        .\rd_mux_sel_r_reg[2]_7 (\rd_mux_sel_r_reg[2]_71 ),
        .\rd_mux_sel_r_reg[2]_8 (\rd_mux_sel_r_reg[2]_72 ),
        .\rd_mux_sel_r_reg[2]_9 (\rd_mux_sel_r_reg[2]_73 ),
        .\rd_ptr_reg[3] (\rd_ptr_reg[3]_3 ),
        .\rd_ptr_reg[3]_0 (\rd_ptr_reg[3]_4 ),
        .\rd_ptr_reg[3]_1 (\rd_ptr_reg[3]_5 ),
        .\rd_ptr_reg[3]_2 (\rd_ptr_reg[3]_6 ),
        .ref_dll_lock_w__0(ref_dll_lock_w__0[2]),
        .rst_out_reg_0(\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_97 ),
        .rst_out_reg_1(rst_out_i_1__0_n_0),
        .rst_primitives(rst_primitives_1),
        .rst_primitives_reg_0(rst_primitives_i_1__0_n_0),
        .sync_pulse(sync_pulse),
        .ts_dqs_0(ts_dqs_0),
        .ts_dqs_1(ts_dqs_1),
        .ts_dqs_2(ts_dqs_2),
        .ts_dqs_3(ts_dqs_3));
  LUT3 #(
    .INIT(8'h80)) 
    mcGo_r1
       (.I0(mcGo_w[0]),
        .I1(mcGo_w[2]),
        .I2(mcGo_w__0),
        .O(mcGo_r1__0));
  FDRE \mcGo_r_reg[0] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(mcGo_r1__0),
        .Q(mcGo_r[0]),
        .R(SR));
  FDRE \mcGo_r_reg[10] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(mcGo_r[9]),
        .Q(mcGo_r[10]),
        .R(SR));
  FDRE \mcGo_r_reg[11] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(mcGo_r[10]),
        .Q(mcGo_r[11]),
        .R(SR));
  FDRE \mcGo_r_reg[12] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(mcGo_r[11]),
        .Q(mcGo_r[12]),
        .R(SR));
  FDRE \mcGo_r_reg[13] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(mcGo_r[12]),
        .Q(mcGo_r[13]),
        .R(SR));
  FDRE \mcGo_r_reg[14] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(mcGo_r[13]),
        .Q(mcGo_r[14]),
        .R(SR));
  FDRE \mcGo_r_reg[15] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(mcGo_r[14]),
        .Q(\mcGo_r_reg[15]_0 ),
        .R(SR));
  FDRE \mcGo_r_reg[1] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(mcGo_r[0]),
        .Q(mcGo_r[1]),
        .R(SR));
  FDRE \mcGo_r_reg[2] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(mcGo_r[1]),
        .Q(mcGo_r[2]),
        .R(SR));
  FDRE \mcGo_r_reg[3] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(mcGo_r[2]),
        .Q(mcGo_r[3]),
        .R(SR));
  FDRE \mcGo_r_reg[4] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(mcGo_r[3]),
        .Q(mcGo_r[4]),
        .R(SR));
  FDRE \mcGo_r_reg[5] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(mcGo_r[4]),
        .Q(mcGo_r[5]),
        .R(SR));
  FDRE \mcGo_r_reg[6] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(mcGo_r[5]),
        .Q(mcGo_r[6]),
        .R(SR));
  FDRE \mcGo_r_reg[7] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(mcGo_r[6]),
        .Q(mcGo_r[7]),
        .R(SR));
  FDRE \mcGo_r_reg[8] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(mcGo_r[7]),
        .Q(mcGo_r[8]),
        .R(SR));
  FDRE \mcGo_r_reg[9] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(mcGo_r[8]),
        .Q(mcGo_r[9]),
        .R(SR));
  LUT3 #(
    .INIT(8'hFE)) 
    phy_ctl_full0
       (.I0(_phy_ctl_full_p__0[0]),
        .I1(_phy_ctl_full_p__0[2]),
        .I2(_phy_ctl_full_p),
        .O(phy_mc_ctl_full));
  LUT4 #(
    .INIT(16'hF888)) 
    phy_if_empty_r_i_2
       (.I0(\ddr_byte_lane_C.ddr_byte_lane_C/if_empty_r ),
        .I1(\ddr_byte_lane_C.ddr_byte_lane_C/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ),
        .I2(\ddr_byte_lane_B.ddr_byte_lane_B/if_empty_r ),
        .I3(\ddr_byte_lane_B.ddr_byte_lane_B/dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ),
        .O(phy_if_empty_r_i_2_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    \rclk_delay_reg[10]_srl11_i_1 
       (.I0(rst_primitives),
        .O(\rclk_delay_reg[10]_srl11_i_1_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \rclk_delay_reg[10]_srl11_i_1__0 
       (.I0(rst_primitives_1),
        .O(\rclk_delay_reg[10]_srl11_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h7FFFFFFFFFFFFFFF)) 
    ref_dll_lock
       (.I0(ref_dll_lock_w__0[0]),
        .I1(ref_dll_lock_w__0[2]),
        .I2(ref_dll_lock_w),
        .I3(\rstdiv2_sync_r_reg[11] ),
        .I4(iodelay_ctrl_rdy),
        .I5(out),
        .O(rst_tmp));
  LUT2 #(
    .INIT(4'hE)) 
    rst_out_i_1
       (.I0(rclk_delay_11),
        .I1(\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_101 ),
        .O(rst_out_i_1_n_0));
  LUT2 #(
    .INIT(4'hE)) 
    rst_out_i_1__0
       (.I0(rclk_delay_11_0),
        .I1(\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_97 ),
        .O(rst_out_i_1__0_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    rst_primitives_i_1
       (.I0(\ddr_phy_4lanes_0.u_ddr_phy_4lanes_n_97 ),
        .O(rst_primitives_i_1_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    rst_primitives_i_1__0
       (.I0(\ddr_phy_4lanes_2.u_ddr_phy_4lanes_n_93 ),
        .O(rst_primitives_i_1__0_n_0));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_mc_phy_wrapper" *) 
module mig_mig_7series_v4_2_ddr_mc_phy_wrapper
   (ddr3_reset_n,
    ddr3_cas_n,
    ddr3_ras_n,
    ddr3_we_n,
    ddr3_addr,
    ddr3_ba,
    ddr3_cs_n,
    ddr3_odt,
    ddr3_cke,
    ddr3_dm,
    A_rst_primitives_reg,
    in0,
    idelay_ld_rst,
    A_rst_primitives_reg_0,
    idelay_ld_rst_0,
    A_rst_primitives_reg_1,
    idelay_ld_rst_1,
    A_rst_primitives_reg_2,
    idelay_ld_rst_2,
    A_rst_primitives_reg_3,
    idelay_ld_rst_3,
    A_rst_primitives_reg_4,
    idelay_ld_rst_4,
    A_rst_primitives_reg_5,
    idelay_ld_rst_5,
    A_rst_primitives_reg_6,
    idelay_ld_rst_6,
    phy_mc_ctl_full,
    rst_tmp,
    if_empty,
    \my_empty_reg[1] ,
    phy_mc_data_full,
    \my_empty_reg[1]_0 ,
    \my_empty_reg[1]_1 ,
    \my_empty_reg[1]_2 ,
    A_rst_primitives_reg_7,
    \my_empty_reg[1]_3 ,
    \my_empty_reg[1]_4 ,
    \my_empty_reg[1]_5 ,
    \my_empty_reg[1]_6 ,
    \my_empty_reg[1]_7 ,
    \my_empty_reg[1]_8 ,
    mem_out,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_6 ,
    \rd_mux_sel_r_reg[2] ,
    \rd_mux_sel_r_reg[2]_0 ,
    \rd_mux_sel_r_reg[2]_1 ,
    \rd_mux_sel_r_reg[2]_2 ,
    \rd_mux_sel_r_reg[2]_3 ,
    \rd_mux_sel_r_reg[2]_4 ,
    \rd_mux_sel_r_reg[2]_5 ,
    \rd_mux_sel_r_reg[2]_6 ,
    \rd_mux_sel_r_reg[2]_7 ,
    \rd_mux_sel_r_reg[2]_8 ,
    \rd_mux_sel_r_reg[2]_9 ,
    \rd_mux_sel_r_reg[2]_10 ,
    \rd_mux_sel_r_reg[2]_11 ,
    \rd_mux_sel_r_reg[2]_12 ,
    \rd_mux_sel_r_reg[2]_13 ,
    \rd_mux_sel_r_reg[2]_14 ,
    \rd_mux_sel_r_reg[2]_15 ,
    \rd_mux_sel_r_reg[2]_16 ,
    \rd_mux_sel_r_reg[2]_17 ,
    \rd_mux_sel_r_reg[2]_18 ,
    \rd_mux_sel_r_reg[2]_19 ,
    \rd_mux_sel_r_reg[2]_20 ,
    \rd_mux_sel_r_reg[2]_21 ,
    \rd_mux_sel_r_reg[2]_22 ,
    \rd_mux_sel_r_reg[2]_23 ,
    \rd_mux_sel_r_reg[2]_24 ,
    \rd_mux_sel_r_reg[2]_25 ,
    \rd_mux_sel_r_reg[2]_26 ,
    \rd_mux_sel_r_reg[2]_27 ,
    \rd_mux_sel_r_reg[2]_28 ,
    \rd_mux_sel_r_reg[2]_29 ,
    \rd_mux_sel_r_reg[2]_30 ,
    \rd_mux_sel_r_reg[2]_31 ,
    \rd_mux_sel_r_reg[2]_32 ,
    \rd_mux_sel_r_reg[2]_33 ,
    \rd_mux_sel_r_reg[2]_34 ,
    \rd_mux_sel_r_reg[2]_35 ,
    \rd_mux_sel_r_reg[2]_36 ,
    \rd_mux_sel_r_reg[2]_37 ,
    \rd_mux_sel_r_reg[2]_38 ,
    \rd_mux_sel_r_reg[2]_39 ,
    \rd_mux_sel_r_reg[2]_40 ,
    \rd_mux_sel_r_reg[2]_41 ,
    \rd_mux_sel_r_reg[2]_42 ,
    \rd_mux_sel_r_reg[2]_43 ,
    \rd_mux_sel_r_reg[2]_44 ,
    \rd_mux_sel_r_reg[2]_45 ,
    \rd_mux_sel_r_reg[2]_46 ,
    \rd_mux_sel_r_reg[2]_47 ,
    \rd_mux_sel_r_reg[2]_48 ,
    \rd_mux_sel_r_reg[2]_49 ,
    \rd_mux_sel_r_reg[2]_50 ,
    \rd_mux_sel_r_reg[2]_51 ,
    \rd_mux_sel_r_reg[2]_52 ,
    \rd_mux_sel_r_reg[2]_53 ,
    \rd_mux_sel_r_reg[2]_54 ,
    \rd_mux_sel_r_reg[2]_55 ,
    \rd_mux_sel_r_reg[2]_56 ,
    \rd_mux_sel_r_reg[2]_57 ,
    \rd_mux_sel_r_reg[2]_58 ,
    \rd_mux_sel_r_reg[2]_59 ,
    \rd_mux_sel_r_reg[2]_60 ,
    \rd_mux_sel_r_reg[2]_61 ,
    \rd_mux_sel_r_reg[2]_62 ,
    phy_rddata_en,
    \rd_ptr_reg[3] ,
    \rd_ptr_reg[3]_0 ,
    \rd_ptr_reg[3]_1 ,
    \rd_ptr_reg[3]_2 ,
    \pi_counter_read_val_reg[5] ,
    \rd_ptr_reg[3]_3 ,
    \rd_ptr_reg[3]_4 ,
    \rd_ptr_reg[3]_5 ,
    \rd_ptr_reg[3]_6 ,
    \pi_counter_read_val_reg[5]_0 ,
    \rd_ptr_reg[3]_7 ,
    \mcGo_r_reg[15] ,
    \rd_mux_sel_r_reg[2]_63 ,
    \rd_mux_sel_r_reg[2]_64 ,
    \rd_mux_sel_r_reg[2]_65 ,
    \rd_mux_sel_r_reg[2]_66 ,
    \rd_mux_sel_r_reg[2]_67 ,
    \rd_mux_sel_r_reg[2]_68 ,
    \rd_mux_sel_r_reg[2]_69 ,
    \rd_mux_sel_r_reg[2]_70 ,
    \rd_mux_sel_r_reg[2]_71 ,
    \rd_mux_sel_r_reg[2]_72 ,
    \rd_mux_sel_r_reg[2]_73 ,
    \rd_mux_sel_r_reg[2]_74 ,
    \rd_mux_sel_r_reg[2]_75 ,
    \rd_mux_sel_r_reg[2]_76 ,
    \rd_mux_sel_r_reg[2]_77 ,
    \rd_mux_sel_r_reg[2]_78 ,
    \rd_mux_sel_r_reg[2]_79 ,
    \rd_mux_sel_r_reg[2]_80 ,
    \rd_mux_sel_r_reg[2]_81 ,
    \rd_mux_sel_r_reg[2]_82 ,
    \rd_mux_sel_r_reg[2]_83 ,
    \rd_mux_sel_r_reg[2]_84 ,
    \rd_mux_sel_r_reg[2]_85 ,
    \rd_mux_sel_r_reg[2]_86 ,
    \rd_mux_sel_r_reg[2]_87 ,
    \rd_mux_sel_r_reg[2]_88 ,
    \rd_mux_sel_r_reg[2]_89 ,
    \rd_mux_sel_r_reg[2]_90 ,
    \rd_mux_sel_r_reg[2]_91 ,
    \rd_mux_sel_r_reg[2]_92 ,
    \rd_mux_sel_r_reg[2]_93 ,
    \rd_mux_sel_r_reg[2]_94 ,
    \rd_mux_sel_r_reg[2]_95 ,
    \rd_mux_sel_r_reg[2]_96 ,
    \rd_mux_sel_r_reg[2]_97 ,
    \rd_mux_sel_r_reg[2]_98 ,
    \rd_mux_sel_r_reg[2]_99 ,
    \rd_mux_sel_r_reg[2]_100 ,
    \rd_mux_sel_r_reg[2]_101 ,
    \rd_mux_sel_r_reg[2]_102 ,
    \rd_mux_sel_r_reg[2]_103 ,
    \rd_mux_sel_r_reg[2]_104 ,
    \rd_mux_sel_r_reg[2]_105 ,
    \rd_mux_sel_r_reg[2]_106 ,
    \rd_mux_sel_r_reg[2]_107 ,
    \rd_mux_sel_r_reg[2]_108 ,
    \rd_mux_sel_r_reg[2]_109 ,
    \rd_mux_sel_r_reg[2]_110 ,
    \rd_mux_sel_r_reg[2]_111 ,
    \rd_mux_sel_r_reg[2]_112 ,
    \rd_mux_sel_r_reg[2]_113 ,
    \rd_mux_sel_r_reg[2]_114 ,
    \rd_mux_sel_r_reg[2]_115 ,
    \rd_mux_sel_r_reg[2]_116 ,
    \rd_mux_sel_r_reg[2]_117 ,
    \rd_mux_sel_r_reg[2]_118 ,
    \rd_mux_sel_r_reg[2]_119 ,
    \rd_mux_sel_r_reg[2]_120 ,
    \rd_mux_sel_r_reg[2]_121 ,
    \rd_mux_sel_r_reg[2]_122 ,
    \rd_mux_sel_r_reg[2]_123 ,
    \rd_mux_sel_r_reg[2]_124 ,
    \rd_mux_sel_r_reg[2]_125 ,
    \rd_mux_sel_r_reg[2]_126 ,
    \po_counter_read_val_reg[0] ,
    \po_counter_read_val_reg[1] ,
    \po_counter_read_val_reg[2] ,
    \po_counter_read_val_reg[3] ,
    \po_counter_read_val_reg[4] ,
    \po_counter_read_val_reg[5] ,
    \po_counter_read_val_reg[6] ,
    \po_counter_read_val_reg[7] ,
    \po_counter_read_val_reg[8] ,
    p_0_out,
    \po_stg2_wrcal_cnt_reg[2] ,
    \po_stg2_wrcal_cnt_reg[2]_0 ,
    \po_stg2_wrcal_cnt_reg[2]_1 ,
    \po_stg2_wrcal_cnt_reg[2]_2 ,
    \po_stg2_wrcal_cnt_reg[2]_3 ,
    \po_stg2_wrcal_cnt_reg[2]_4 ,
    \po_stg2_wrcal_cnt_reg[2]_5 ,
    \po_stg2_wrcal_cnt_reg[2]_6 ,
    \po_stg2_wrcal_cnt_reg[2]_7 ,
    \po_stg2_wrcal_cnt_reg[2]_8 ,
    \po_stg2_wrcal_cnt_reg[2]_9 ,
    \po_stg2_wrcal_cnt_reg[2]_10 ,
    \po_stg2_wrcal_cnt_reg[2]_11 ,
    \po_stg2_wrcal_cnt_reg[2]_12 ,
    \po_stg2_wrcal_cnt_reg[2]_13 ,
    \po_stg2_wrcal_cnt_reg[2]_14 ,
    \po_stg2_wrcal_cnt_reg[2]_15 ,
    \po_stg2_wrcal_cnt_reg[2]_16 ,
    \po_stg2_wrcal_cnt_reg[2]_17 ,
    \po_stg2_wrcal_cnt_reg[2]_18 ,
    \po_stg2_wrcal_cnt_reg[2]_19 ,
    \po_stg2_wrcal_cnt_reg[2]_20 ,
    \po_stg2_wrcal_cnt_reg[2]_21 ,
    \po_stg2_wrcal_cnt_reg[2]_22 ,
    \po_stg2_wrcal_cnt_reg[2]_23 ,
    \po_stg2_wrcal_cnt_reg[2]_24 ,
    \po_stg2_wrcal_cnt_reg[2]_25 ,
    \po_stg2_wrcal_cnt_reg[2]_26 ,
    \po_stg2_wrcal_cnt_reg[2]_27 ,
    \po_stg2_wrcal_cnt_reg[2]_28 ,
    \po_stg2_wrcal_cnt_reg[2]_29 ,
    \po_stg2_wrcal_cnt_reg[2]_30 ,
    \po_stg2_wrcal_cnt_reg[2]_31 ,
    \po_stg2_wrcal_cnt_reg[2]_32 ,
    \po_stg2_wrcal_cnt_reg[2]_33 ,
    \po_stg2_wrcal_cnt_reg[2]_34 ,
    \po_stg2_wrcal_cnt_reg[2]_35 ,
    \po_stg2_wrcal_cnt_reg[2]_36 ,
    \po_stg2_wrcal_cnt_reg[2]_37 ,
    \po_stg2_wrcal_cnt_reg[2]_38 ,
    \po_stg2_wrcal_cnt_reg[2]_39 ,
    \po_stg2_wrcal_cnt_reg[2]_40 ,
    \po_stg2_wrcal_cnt_reg[2]_41 ,
    \po_stg2_wrcal_cnt_reg[2]_42 ,
    \po_stg2_wrcal_cnt_reg[2]_43 ,
    \po_stg2_wrcal_cnt_reg[2]_44 ,
    \po_stg2_wrcal_cnt_reg[2]_45 ,
    \po_stg2_wrcal_cnt_reg[2]_46 ,
    \po_stg2_wrcal_cnt_reg[2]_47 ,
    \po_stg2_wrcal_cnt_reg[2]_48 ,
    \po_stg2_wrcal_cnt_reg[2]_49 ,
    \po_stg2_wrcal_cnt_reg[2]_50 ,
    \po_stg2_wrcal_cnt_reg[2]_51 ,
    \po_stg2_wrcal_cnt_reg[2]_52 ,
    \po_stg2_wrcal_cnt_reg[2]_53 ,
    \po_stg2_wrcal_cnt_reg[2]_54 ,
    \po_stg2_wrcal_cnt_reg[2]_55 ,
    \po_stg2_wrcal_cnt_reg[2]_56 ,
    \po_stg2_wrcal_cnt_reg[2]_57 ,
    \po_stg2_wrcal_cnt_reg[2]_58 ,
    \po_stg2_wrcal_cnt_reg[2]_59 ,
    \po_stg2_wrcal_cnt_reg[2]_60 ,
    \po_stg2_wrcal_cnt_reg[2]_61 ,
    ddr_ck_out,
    \my_empty_reg[1]_9 ,
    \rd_ptr_reg[3]_8 ,
    of_ctl_full_v,
    ddr3_dq,
    ddr3_dqs_p,
    ddr3_dqs_n,
    mux_reset_n,
    idle,
    mmcm_ps_clk,
    rst_sync_r1,
    phy_cmd_wr_en,
    \entry_cnt_reg[4] ,
    \po_counter_read_val_reg[8]_0 ,
    \po_counter_read_val_reg[8]_1 ,
    \po_counter_read_val_reg[8]_2 ,
    \po_counter_read_val_reg[8]_3 ,
    freq_refclk,
    mem_refclk,
    sync_pulse,
    \my_full_reg[3] ,
    \my_full_reg[3]_0 ,
    \my_full_reg[3]_1 ,
    \my_full_reg[3]_2 ,
    \my_full_reg[3]_3 ,
    \po_counter_read_val_reg[8]_4 ,
    \po_counter_read_val_reg[8]_5 ,
    \po_counter_read_val_reg[8]_6 ,
    \po_counter_read_val_reg[8]_7 ,
    D1,
    D3,
    D4,
    D5,
    D6,
    D7,
    D8,
    \rd_ptr_reg[3]_9 ,
    pll_locked,
    phy_read_calib,
    phy_mc_ctl_full_r_reg,
    phy_write_calib,
    \input_[9].iserdes_dq_.iserdesdq ,
    idelay_inc,
    LD0,
    CLKB0,
    \pi_dqs_found_lanes_r1_reg[0] ,
    \pi_dqs_found_lanes_r1_reg[0]_0 ,
    \pi_dqs_found_lanes_r1_reg[0]_1 ,
    \pi_dqs_found_lanes_r1_reg[0]_2 ,
    ififo_rst_reg,
    COUNTERLOADVAL,
    \po_counter_read_val_reg[8]_8 ,
    \po_counter_read_val_reg[8]_9 ,
    \po_counter_read_val_reg[8]_10 ,
    \my_empty_reg[7] ,
    \my_empty_reg[7]_0 ,
    \my_empty_reg[7]_1 ,
    \my_empty_reg[7]_2 ,
    \my_empty_reg[7]_3 ,
    \my_empty_reg[7]_4 ,
    \my_empty_reg[7]_5 ,
    \my_empty_reg[7]_6 ,
    phy_if_reset,
    \input_[9].iserdes_dq_.iserdesdq_0 ,
    LD0_7,
    CLKB0_7,
    \pi_dqs_found_lanes_r1_reg[1] ,
    \pi_dqs_found_lanes_r1_reg[1]_0 ,
    \pi_dqs_found_lanes_r1_reg[1]_1 ,
    \pi_dqs_found_lanes_r1_reg[1]_2 ,
    ififo_rst_reg_0,
    \pi_dqs_found_lanes_r1_reg[1]_3 ,
    \po_counter_read_val_reg[8]_11 ,
    \po_counter_read_val_reg[8]_12 ,
    \po_counter_read_val_reg[8]_13 ,
    \my_empty_reg[7]_7 ,
    \my_empty_reg[7]_8 ,
    \my_empty_reg[7]_9 ,
    \my_empty_reg[7]_10 ,
    \my_empty_reg[7]_11 ,
    \my_empty_reg[7]_12 ,
    \my_empty_reg[7]_13 ,
    \my_empty_reg[7]_14 ,
    \input_[9].iserdes_dq_.iserdesdq_1 ,
    LD0_8,
    CLKB0_8,
    \pi_dqs_found_lanes_r1_reg[2] ,
    \pi_dqs_found_lanes_r1_reg[2]_0 ,
    \pi_dqs_found_lanes_r1_reg[2]_1 ,
    \pi_dqs_found_lanes_r1_reg[2]_2 ,
    ififo_rst_reg_1,
    \pi_dqs_found_lanes_r1_reg[2]_3 ,
    \po_counter_read_val_reg[8]_14 ,
    \po_counter_read_val_reg[8]_15 ,
    \po_counter_read_val_reg[8]_16 ,
    \my_empty_reg[7]_15 ,
    \my_empty_reg[7]_16 ,
    \my_empty_reg[7]_17 ,
    \my_empty_reg[7]_18 ,
    \my_empty_reg[7]_19 ,
    \my_empty_reg[7]_20 ,
    \my_empty_reg[7]_21 ,
    \my_empty_reg[7]_22 ,
    \input_[9].iserdes_dq_.iserdesdq_2 ,
    LD0_9,
    CLKB0_9,
    \pi_dqs_found_lanes_r1_reg[3] ,
    \pi_dqs_found_lanes_r1_reg[3]_0 ,
    \pi_dqs_found_lanes_r1_reg[3]_1 ,
    \pi_dqs_found_lanes_r1_reg[3]_2 ,
    ififo_rst_reg_2,
    \pi_dqs_found_lanes_r1_reg[3]_3 ,
    \po_counter_read_val_reg[8]_17 ,
    \po_counter_read_val_reg[8]_18 ,
    \po_counter_read_val_reg[8]_19 ,
    \my_empty_reg[7]_23 ,
    \my_empty_reg[7]_24 ,
    \my_empty_reg[7]_25 ,
    \my_empty_reg[7]_26 ,
    \my_empty_reg[7]_27 ,
    \my_empty_reg[7]_28 ,
    \my_empty_reg[7]_29 ,
    \my_empty_reg[7]_30 ,
    RST0,
    SR,
    \input_[9].iserdes_dq_.iserdesdq_3 ,
    LD0_10,
    CLKB0_10,
    \pi_dqs_found_lanes_r1_reg[8] ,
    \pi_dqs_found_lanes_r1_reg[8]_0 ,
    \pi_dqs_found_lanes_r1_reg[8]_1 ,
    \pi_dqs_found_lanes_r1_reg[8]_2 ,
    ififo_rst_reg_3,
    \pi_dqs_found_lanes_r1_reg[8]_3 ,
    \po_counter_read_val_reg[8]_20 ,
    \po_counter_read_val_reg[8]_21 ,
    \po_counter_read_val_reg[8]_22 ,
    \my_empty_reg[7]_31 ,
    D2,
    \my_empty_reg[7]_32 ,
    \my_empty_reg[7]_33 ,
    \my_empty_reg[7]_34 ,
    \my_empty_reg[7]_35 ,
    \my_empty_reg[7]_36 ,
    \my_empty_reg[7]_37 ,
    \input_[9].iserdes_dq_.iserdesdq_4 ,
    LD0_11,
    CLKB0_11,
    \pi_dqs_found_lanes_r1_reg[9] ,
    \pi_dqs_found_lanes_r1_reg[9]_0 ,
    \pi_dqs_found_lanes_r1_reg[9]_1 ,
    \pi_dqs_found_lanes_r1_reg[9]_2 ,
    ififo_rst_reg_4,
    \pi_dqs_found_lanes_r1_reg[9]_3 ,
    \po_counter_read_val_reg[8]_23 ,
    \po_counter_read_val_reg[8]_24 ,
    \po_counter_read_val_reg[8]_25 ,
    \my_empty_reg[7]_38 ,
    \my_empty_reg[7]_39 ,
    \my_empty_reg[7]_40 ,
    \my_empty_reg[7]_41 ,
    \my_empty_reg[7]_42 ,
    \my_empty_reg[7]_43 ,
    \my_empty_reg[7]_44 ,
    \my_empty_reg[7]_45 ,
    \input_[9].iserdes_dq_.iserdesdq_5 ,
    LD0_12,
    CLKB0_12,
    \pi_dqs_found_lanes_r1_reg[10] ,
    \pi_dqs_found_lanes_r1_reg[10]_0 ,
    \pi_dqs_found_lanes_r1_reg[10]_1 ,
    \pi_dqs_found_lanes_r1_reg[10]_2 ,
    ififo_rst_reg_5,
    \pi_dqs_found_lanes_r1_reg[10]_3 ,
    \po_counter_read_val_reg[8]_26 ,
    \po_counter_read_val_reg[8]_27 ,
    \po_counter_read_val_reg[8]_28 ,
    \my_empty_reg[7]_46 ,
    \my_empty_reg[7]_47 ,
    \my_empty_reg[7]_48 ,
    \my_empty_reg[7]_49 ,
    \my_empty_reg[7]_50 ,
    \my_empty_reg[7]_51 ,
    \my_empty_reg[7]_52 ,
    \my_empty_reg[7]_53 ,
    \input_[9].iserdes_dq_.iserdesdq_6 ,
    LD0_13,
    CLKB0_13,
    \pi_dqs_found_lanes_r1_reg[11] ,
    \pi_dqs_found_lanes_r1_reg[11]_0 ,
    \pi_dqs_found_lanes_r1_reg[11]_1 ,
    \pi_dqs_found_lanes_r1_reg[11]_2 ,
    ififo_rst_reg_6,
    \pi_dqs_found_lanes_r1_reg[11]_3 ,
    \po_counter_read_val_reg[8]_29 ,
    \po_counter_read_val_reg[8]_30 ,
    \po_counter_read_val_reg[8]_31 ,
    \my_empty_reg[7]_54 ,
    \my_empty_reg[7]_55 ,
    \my_empty_reg[7]_56 ,
    \my_empty_reg[7]_57 ,
    \my_empty_reg[7]_58 ,
    \my_empty_reg[7]_59 ,
    \my_empty_reg[7]_60 ,
    \my_empty_reg[7]_61 ,
    \rstdiv2_sync_r_reg[11] ,
    iodelay_ctrl_rdy,
    out,
    phy_data_wr_en,
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0] ,
    out_fifo,
    mc_cas_n,
    mc_we_n,
    out_fifo_0,
    mc_ras_n,
    mc_cs_n,
    mc_address,
    Q,
    out_fifo_1,
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ,
    D,
    \data_offset_1_i1_reg[5]_0 ,
    \data_offset_2_i1_reg[5]_0 ,
    phy_dout,
    out_fifo_i_75__5,
    out_fifo_i_75__6,
    out_fifo_i_75__7,
    out_fifo_i_75__0,
    out_fifo_i_75__1,
    out_fifo_i_75__2,
    out_fifo_i_75__3,
    out_fifo_i_47__8,
    mux_address,
    d_in,
    \po_counter_read_val_reg[0]_0 ,
    calib_sel,
    \gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ,
    C_po_coarse_enable26_out,
    C_po_counter_read_en38_out,
    C_po_fine_enable23_out,
    C_po_fine_inc29_out,
    \my_empty_reg[7]_62 ,
    \my_empty_reg[7]_63 ,
    \my_empty_reg[7]_64 ,
    \my_empty_reg[7]_65 ,
    D9,
    out_fifo_i_39,
    out_fifo_2);
  output ddr3_reset_n;
  output ddr3_cas_n;
  output ddr3_ras_n;
  output ddr3_we_n;
  output [13:0]ddr3_addr;
  output [2:0]ddr3_ba;
  output [0:0]ddr3_cs_n;
  output [0:0]ddr3_odt;
  output [0:0]ddr3_cke;
  output [7:0]ddr3_dm;
  output A_rst_primitives_reg;
  output [7:0]in0;
  output idelay_ld_rst;
  output A_rst_primitives_reg_0;
  output idelay_ld_rst_0;
  output A_rst_primitives_reg_1;
  output idelay_ld_rst_1;
  output A_rst_primitives_reg_2;
  output idelay_ld_rst_2;
  output A_rst_primitives_reg_3;
  output idelay_ld_rst_3;
  output A_rst_primitives_reg_4;
  output idelay_ld_rst_4;
  output A_rst_primitives_reg_5;
  output idelay_ld_rst_5;
  output A_rst_primitives_reg_6;
  output idelay_ld_rst_6;
  output phy_mc_ctl_full;
  output rst_tmp;
  output if_empty;
  output \my_empty_reg[1] ;
  output phy_mc_data_full;
  output \my_empty_reg[1]_0 ;
  output \my_empty_reg[1]_1 ;
  output \my_empty_reg[1]_2 ;
  output A_rst_primitives_reg_7;
  output \my_empty_reg[1]_3 ;
  output \my_empty_reg[1]_4 ;
  output \my_empty_reg[1]_5 ;
  output \my_empty_reg[1]_6 ;
  output \my_empty_reg[1]_7 ;
  output \my_empty_reg[1]_8 ;
  output [11:0]mem_out;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_6 ;
  output \rd_mux_sel_r_reg[2] ;
  output \rd_mux_sel_r_reg[2]_0 ;
  output \rd_mux_sel_r_reg[2]_1 ;
  output \rd_mux_sel_r_reg[2]_2 ;
  output \rd_mux_sel_r_reg[2]_3 ;
  output \rd_mux_sel_r_reg[2]_4 ;
  output \rd_mux_sel_r_reg[2]_5 ;
  output \rd_mux_sel_r_reg[2]_6 ;
  output \rd_mux_sel_r_reg[2]_7 ;
  output \rd_mux_sel_r_reg[2]_8 ;
  output \rd_mux_sel_r_reg[2]_9 ;
  output \rd_mux_sel_r_reg[2]_10 ;
  output \rd_mux_sel_r_reg[2]_11 ;
  output \rd_mux_sel_r_reg[2]_12 ;
  output \rd_mux_sel_r_reg[2]_13 ;
  output \rd_mux_sel_r_reg[2]_14 ;
  output \rd_mux_sel_r_reg[2]_15 ;
  output \rd_mux_sel_r_reg[2]_16 ;
  output \rd_mux_sel_r_reg[2]_17 ;
  output \rd_mux_sel_r_reg[2]_18 ;
  output \rd_mux_sel_r_reg[2]_19 ;
  output \rd_mux_sel_r_reg[2]_20 ;
  output \rd_mux_sel_r_reg[2]_21 ;
  output \rd_mux_sel_r_reg[2]_22 ;
  output \rd_mux_sel_r_reg[2]_23 ;
  output \rd_mux_sel_r_reg[2]_24 ;
  output \rd_mux_sel_r_reg[2]_25 ;
  output \rd_mux_sel_r_reg[2]_26 ;
  output \rd_mux_sel_r_reg[2]_27 ;
  output \rd_mux_sel_r_reg[2]_28 ;
  output \rd_mux_sel_r_reg[2]_29 ;
  output \rd_mux_sel_r_reg[2]_30 ;
  output \rd_mux_sel_r_reg[2]_31 ;
  output \rd_mux_sel_r_reg[2]_32 ;
  output \rd_mux_sel_r_reg[2]_33 ;
  output \rd_mux_sel_r_reg[2]_34 ;
  output \rd_mux_sel_r_reg[2]_35 ;
  output \rd_mux_sel_r_reg[2]_36 ;
  output \rd_mux_sel_r_reg[2]_37 ;
  output \rd_mux_sel_r_reg[2]_38 ;
  output \rd_mux_sel_r_reg[2]_39 ;
  output \rd_mux_sel_r_reg[2]_40 ;
  output \rd_mux_sel_r_reg[2]_41 ;
  output \rd_mux_sel_r_reg[2]_42 ;
  output \rd_mux_sel_r_reg[2]_43 ;
  output \rd_mux_sel_r_reg[2]_44 ;
  output \rd_mux_sel_r_reg[2]_45 ;
  output \rd_mux_sel_r_reg[2]_46 ;
  output \rd_mux_sel_r_reg[2]_47 ;
  output \rd_mux_sel_r_reg[2]_48 ;
  output \rd_mux_sel_r_reg[2]_49 ;
  output \rd_mux_sel_r_reg[2]_50 ;
  output \rd_mux_sel_r_reg[2]_51 ;
  output \rd_mux_sel_r_reg[2]_52 ;
  output \rd_mux_sel_r_reg[2]_53 ;
  output \rd_mux_sel_r_reg[2]_54 ;
  output \rd_mux_sel_r_reg[2]_55 ;
  output \rd_mux_sel_r_reg[2]_56 ;
  output \rd_mux_sel_r_reg[2]_57 ;
  output \rd_mux_sel_r_reg[2]_58 ;
  output \rd_mux_sel_r_reg[2]_59 ;
  output \rd_mux_sel_r_reg[2]_60 ;
  output \rd_mux_sel_r_reg[2]_61 ;
  output \rd_mux_sel_r_reg[2]_62 ;
  output phy_rddata_en;
  output [63:0]\rd_ptr_reg[3] ;
  output [63:0]\rd_ptr_reg[3]_0 ;
  output [63:0]\rd_ptr_reg[3]_1 ;
  output [63:0]\rd_ptr_reg[3]_2 ;
  output [5:0]\pi_counter_read_val_reg[5] ;
  output [63:0]\rd_ptr_reg[3]_3 ;
  output [63:0]\rd_ptr_reg[3]_4 ;
  output [63:0]\rd_ptr_reg[3]_5 ;
  output [63:0]\rd_ptr_reg[3]_6 ;
  output [5:0]\pi_counter_read_val_reg[5]_0 ;
  output [35:0]\rd_ptr_reg[3]_7 ;
  output [0:0]\mcGo_r_reg[15] ;
  output \rd_mux_sel_r_reg[2]_63 ;
  output \rd_mux_sel_r_reg[2]_64 ;
  output \rd_mux_sel_r_reg[2]_65 ;
  output \rd_mux_sel_r_reg[2]_66 ;
  output \rd_mux_sel_r_reg[2]_67 ;
  output \rd_mux_sel_r_reg[2]_68 ;
  output \rd_mux_sel_r_reg[2]_69 ;
  output \rd_mux_sel_r_reg[2]_70 ;
  output \rd_mux_sel_r_reg[2]_71 ;
  output \rd_mux_sel_r_reg[2]_72 ;
  output \rd_mux_sel_r_reg[2]_73 ;
  output \rd_mux_sel_r_reg[2]_74 ;
  output \rd_mux_sel_r_reg[2]_75 ;
  output \rd_mux_sel_r_reg[2]_76 ;
  output \rd_mux_sel_r_reg[2]_77 ;
  output \rd_mux_sel_r_reg[2]_78 ;
  output \rd_mux_sel_r_reg[2]_79 ;
  output \rd_mux_sel_r_reg[2]_80 ;
  output \rd_mux_sel_r_reg[2]_81 ;
  output \rd_mux_sel_r_reg[2]_82 ;
  output \rd_mux_sel_r_reg[2]_83 ;
  output \rd_mux_sel_r_reg[2]_84 ;
  output \rd_mux_sel_r_reg[2]_85 ;
  output \rd_mux_sel_r_reg[2]_86 ;
  output \rd_mux_sel_r_reg[2]_87 ;
  output \rd_mux_sel_r_reg[2]_88 ;
  output \rd_mux_sel_r_reg[2]_89 ;
  output \rd_mux_sel_r_reg[2]_90 ;
  output \rd_mux_sel_r_reg[2]_91 ;
  output \rd_mux_sel_r_reg[2]_92 ;
  output \rd_mux_sel_r_reg[2]_93 ;
  output \rd_mux_sel_r_reg[2]_94 ;
  output \rd_mux_sel_r_reg[2]_95 ;
  output \rd_mux_sel_r_reg[2]_96 ;
  output \rd_mux_sel_r_reg[2]_97 ;
  output \rd_mux_sel_r_reg[2]_98 ;
  output \rd_mux_sel_r_reg[2]_99 ;
  output \rd_mux_sel_r_reg[2]_100 ;
  output \rd_mux_sel_r_reg[2]_101 ;
  output \rd_mux_sel_r_reg[2]_102 ;
  output \rd_mux_sel_r_reg[2]_103 ;
  output \rd_mux_sel_r_reg[2]_104 ;
  output \rd_mux_sel_r_reg[2]_105 ;
  output \rd_mux_sel_r_reg[2]_106 ;
  output \rd_mux_sel_r_reg[2]_107 ;
  output \rd_mux_sel_r_reg[2]_108 ;
  output \rd_mux_sel_r_reg[2]_109 ;
  output \rd_mux_sel_r_reg[2]_110 ;
  output \rd_mux_sel_r_reg[2]_111 ;
  output \rd_mux_sel_r_reg[2]_112 ;
  output \rd_mux_sel_r_reg[2]_113 ;
  output \rd_mux_sel_r_reg[2]_114 ;
  output \rd_mux_sel_r_reg[2]_115 ;
  output \rd_mux_sel_r_reg[2]_116 ;
  output \rd_mux_sel_r_reg[2]_117 ;
  output \rd_mux_sel_r_reg[2]_118 ;
  output \rd_mux_sel_r_reg[2]_119 ;
  output \rd_mux_sel_r_reg[2]_120 ;
  output \rd_mux_sel_r_reg[2]_121 ;
  output \rd_mux_sel_r_reg[2]_122 ;
  output \rd_mux_sel_r_reg[2]_123 ;
  output \rd_mux_sel_r_reg[2]_124 ;
  output \rd_mux_sel_r_reg[2]_125 ;
  output \rd_mux_sel_r_reg[2]_126 ;
  output \po_counter_read_val_reg[0] ;
  output \po_counter_read_val_reg[1] ;
  output \po_counter_read_val_reg[2] ;
  output \po_counter_read_val_reg[3] ;
  output \po_counter_read_val_reg[4] ;
  output \po_counter_read_val_reg[5] ;
  output \po_counter_read_val_reg[6] ;
  output \po_counter_read_val_reg[7] ;
  output \po_counter_read_val_reg[8] ;
  output p_0_out;
  output \po_stg2_wrcal_cnt_reg[2] ;
  output \po_stg2_wrcal_cnt_reg[2]_0 ;
  output \po_stg2_wrcal_cnt_reg[2]_1 ;
  output \po_stg2_wrcal_cnt_reg[2]_2 ;
  output \po_stg2_wrcal_cnt_reg[2]_3 ;
  output \po_stg2_wrcal_cnt_reg[2]_4 ;
  output \po_stg2_wrcal_cnt_reg[2]_5 ;
  output \po_stg2_wrcal_cnt_reg[2]_6 ;
  output \po_stg2_wrcal_cnt_reg[2]_7 ;
  output \po_stg2_wrcal_cnt_reg[2]_8 ;
  output \po_stg2_wrcal_cnt_reg[2]_9 ;
  output \po_stg2_wrcal_cnt_reg[2]_10 ;
  output \po_stg2_wrcal_cnt_reg[2]_11 ;
  output \po_stg2_wrcal_cnt_reg[2]_12 ;
  output \po_stg2_wrcal_cnt_reg[2]_13 ;
  output \po_stg2_wrcal_cnt_reg[2]_14 ;
  output \po_stg2_wrcal_cnt_reg[2]_15 ;
  output \po_stg2_wrcal_cnt_reg[2]_16 ;
  output \po_stg2_wrcal_cnt_reg[2]_17 ;
  output \po_stg2_wrcal_cnt_reg[2]_18 ;
  output \po_stg2_wrcal_cnt_reg[2]_19 ;
  output \po_stg2_wrcal_cnt_reg[2]_20 ;
  output \po_stg2_wrcal_cnt_reg[2]_21 ;
  output \po_stg2_wrcal_cnt_reg[2]_22 ;
  output \po_stg2_wrcal_cnt_reg[2]_23 ;
  output \po_stg2_wrcal_cnt_reg[2]_24 ;
  output \po_stg2_wrcal_cnt_reg[2]_25 ;
  output \po_stg2_wrcal_cnt_reg[2]_26 ;
  output \po_stg2_wrcal_cnt_reg[2]_27 ;
  output \po_stg2_wrcal_cnt_reg[2]_28 ;
  output \po_stg2_wrcal_cnt_reg[2]_29 ;
  output \po_stg2_wrcal_cnt_reg[2]_30 ;
  output \po_stg2_wrcal_cnt_reg[2]_31 ;
  output \po_stg2_wrcal_cnt_reg[2]_32 ;
  output \po_stg2_wrcal_cnt_reg[2]_33 ;
  output \po_stg2_wrcal_cnt_reg[2]_34 ;
  output \po_stg2_wrcal_cnt_reg[2]_35 ;
  output \po_stg2_wrcal_cnt_reg[2]_36 ;
  output \po_stg2_wrcal_cnt_reg[2]_37 ;
  output \po_stg2_wrcal_cnt_reg[2]_38 ;
  output \po_stg2_wrcal_cnt_reg[2]_39 ;
  output \po_stg2_wrcal_cnt_reg[2]_40 ;
  output \po_stg2_wrcal_cnt_reg[2]_41 ;
  output \po_stg2_wrcal_cnt_reg[2]_42 ;
  output \po_stg2_wrcal_cnt_reg[2]_43 ;
  output \po_stg2_wrcal_cnt_reg[2]_44 ;
  output \po_stg2_wrcal_cnt_reg[2]_45 ;
  output \po_stg2_wrcal_cnt_reg[2]_46 ;
  output \po_stg2_wrcal_cnt_reg[2]_47 ;
  output \po_stg2_wrcal_cnt_reg[2]_48 ;
  output \po_stg2_wrcal_cnt_reg[2]_49 ;
  output \po_stg2_wrcal_cnt_reg[2]_50 ;
  output \po_stg2_wrcal_cnt_reg[2]_51 ;
  output \po_stg2_wrcal_cnt_reg[2]_52 ;
  output \po_stg2_wrcal_cnt_reg[2]_53 ;
  output \po_stg2_wrcal_cnt_reg[2]_54 ;
  output \po_stg2_wrcal_cnt_reg[2]_55 ;
  output \po_stg2_wrcal_cnt_reg[2]_56 ;
  output \po_stg2_wrcal_cnt_reg[2]_57 ;
  output \po_stg2_wrcal_cnt_reg[2]_58 ;
  output \po_stg2_wrcal_cnt_reg[2]_59 ;
  output \po_stg2_wrcal_cnt_reg[2]_60 ;
  output \po_stg2_wrcal_cnt_reg[2]_61 ;
  output [1:0]ddr_ck_out;
  output \my_empty_reg[1]_9 ;
  output [23:0]\rd_ptr_reg[3]_8 ;
  output [0:0]of_ctl_full_v;
  inout [63:0]ddr3_dq;
  inout [7:0]ddr3_dqs_p;
  inout [7:0]ddr3_dqs_n;
  input mux_reset_n;
  input idle;
  input mmcm_ps_clk;
  input rst_sync_r1;
  input phy_cmd_wr_en;
  input \entry_cnt_reg[4] ;
  input \po_counter_read_val_reg[8]_0 ;
  input \po_counter_read_val_reg[8]_1 ;
  input \po_counter_read_val_reg[8]_2 ;
  input \po_counter_read_val_reg[8]_3 ;
  input freq_refclk;
  input mem_refclk;
  input sync_pulse;
  input [3:0]\my_full_reg[3] ;
  input [0:0]\my_full_reg[3]_0 ;
  input [1:0]\my_full_reg[3]_1 ;
  input [0:0]\my_full_reg[3]_2 ;
  input [3:0]\my_full_reg[3]_3 ;
  input \po_counter_read_val_reg[8]_4 ;
  input \po_counter_read_val_reg[8]_5 ;
  input \po_counter_read_val_reg[8]_6 ;
  input \po_counter_read_val_reg[8]_7 ;
  input [3:0]D1;
  input [3:0]D3;
  input [3:0]D4;
  input [3:0]D5;
  input [7:0]D6;
  input [3:0]D7;
  input [3:0]D8;
  input [3:0]\rd_ptr_reg[3]_9 ;
  input pll_locked;
  input phy_read_calib;
  input phy_mc_ctl_full_r_reg;
  input phy_write_calib;
  input \input_[9].iserdes_dq_.iserdesdq ;
  input idelay_inc;
  input LD0;
  input CLKB0;
  input \pi_dqs_found_lanes_r1_reg[0] ;
  input \pi_dqs_found_lanes_r1_reg[0]_0 ;
  input \pi_dqs_found_lanes_r1_reg[0]_1 ;
  input \pi_dqs_found_lanes_r1_reg[0]_2 ;
  input ififo_rst_reg;
  input [5:0]COUNTERLOADVAL;
  input \po_counter_read_val_reg[8]_8 ;
  input \po_counter_read_val_reg[8]_9 ;
  input \po_counter_read_val_reg[8]_10 ;
  input [7:0]\my_empty_reg[7] ;
  input [7:0]\my_empty_reg[7]_0 ;
  input [7:0]\my_empty_reg[7]_1 ;
  input [7:0]\my_empty_reg[7]_2 ;
  input [7:0]\my_empty_reg[7]_3 ;
  input [7:0]\my_empty_reg[7]_4 ;
  input [7:0]\my_empty_reg[7]_5 ;
  input [7:0]\my_empty_reg[7]_6 ;
  input phy_if_reset;
  input \input_[9].iserdes_dq_.iserdesdq_0 ;
  input LD0_7;
  input CLKB0_7;
  input \pi_dqs_found_lanes_r1_reg[1] ;
  input \pi_dqs_found_lanes_r1_reg[1]_0 ;
  input \pi_dqs_found_lanes_r1_reg[1]_1 ;
  input \pi_dqs_found_lanes_r1_reg[1]_2 ;
  input ififo_rst_reg_0;
  input [5:0]\pi_dqs_found_lanes_r1_reg[1]_3 ;
  input \po_counter_read_val_reg[8]_11 ;
  input \po_counter_read_val_reg[8]_12 ;
  input \po_counter_read_val_reg[8]_13 ;
  input [7:0]\my_empty_reg[7]_7 ;
  input [7:0]\my_empty_reg[7]_8 ;
  input [7:0]\my_empty_reg[7]_9 ;
  input [7:0]\my_empty_reg[7]_10 ;
  input [7:0]\my_empty_reg[7]_11 ;
  input [7:0]\my_empty_reg[7]_12 ;
  input [7:0]\my_empty_reg[7]_13 ;
  input [7:0]\my_empty_reg[7]_14 ;
  input \input_[9].iserdes_dq_.iserdesdq_1 ;
  input LD0_8;
  input CLKB0_8;
  input \pi_dqs_found_lanes_r1_reg[2] ;
  input \pi_dqs_found_lanes_r1_reg[2]_0 ;
  input \pi_dqs_found_lanes_r1_reg[2]_1 ;
  input \pi_dqs_found_lanes_r1_reg[2]_2 ;
  input ififo_rst_reg_1;
  input [5:0]\pi_dqs_found_lanes_r1_reg[2]_3 ;
  input \po_counter_read_val_reg[8]_14 ;
  input \po_counter_read_val_reg[8]_15 ;
  input \po_counter_read_val_reg[8]_16 ;
  input [7:0]\my_empty_reg[7]_15 ;
  input [7:0]\my_empty_reg[7]_16 ;
  input [7:0]\my_empty_reg[7]_17 ;
  input [7:0]\my_empty_reg[7]_18 ;
  input [7:0]\my_empty_reg[7]_19 ;
  input [7:0]\my_empty_reg[7]_20 ;
  input [7:0]\my_empty_reg[7]_21 ;
  input [7:0]\my_empty_reg[7]_22 ;
  input \input_[9].iserdes_dq_.iserdesdq_2 ;
  input LD0_9;
  input CLKB0_9;
  input \pi_dqs_found_lanes_r1_reg[3] ;
  input \pi_dqs_found_lanes_r1_reg[3]_0 ;
  input \pi_dqs_found_lanes_r1_reg[3]_1 ;
  input \pi_dqs_found_lanes_r1_reg[3]_2 ;
  input ififo_rst_reg_2;
  input [5:0]\pi_dqs_found_lanes_r1_reg[3]_3 ;
  input \po_counter_read_val_reg[8]_17 ;
  input \po_counter_read_val_reg[8]_18 ;
  input \po_counter_read_val_reg[8]_19 ;
  input [7:0]\my_empty_reg[7]_23 ;
  input [7:0]\my_empty_reg[7]_24 ;
  input [7:0]\my_empty_reg[7]_25 ;
  input [7:0]\my_empty_reg[7]_26 ;
  input [7:0]\my_empty_reg[7]_27 ;
  input [7:0]\my_empty_reg[7]_28 ;
  input [7:0]\my_empty_reg[7]_29 ;
  input [7:0]\my_empty_reg[7]_30 ;
  input RST0;
  input [0:0]SR;
  input \input_[9].iserdes_dq_.iserdesdq_3 ;
  input LD0_10;
  input CLKB0_10;
  input \pi_dqs_found_lanes_r1_reg[8] ;
  input \pi_dqs_found_lanes_r1_reg[8]_0 ;
  input \pi_dqs_found_lanes_r1_reg[8]_1 ;
  input \pi_dqs_found_lanes_r1_reg[8]_2 ;
  input ififo_rst_reg_3;
  input [5:0]\pi_dqs_found_lanes_r1_reg[8]_3 ;
  input \po_counter_read_val_reg[8]_20 ;
  input \po_counter_read_val_reg[8]_21 ;
  input \po_counter_read_val_reg[8]_22 ;
  input [7:0]\my_empty_reg[7]_31 ;
  input [7:0]D2;
  input [7:0]\my_empty_reg[7]_32 ;
  input [7:0]\my_empty_reg[7]_33 ;
  input [7:0]\my_empty_reg[7]_34 ;
  input [7:0]\my_empty_reg[7]_35 ;
  input [7:0]\my_empty_reg[7]_36 ;
  input [7:0]\my_empty_reg[7]_37 ;
  input \input_[9].iserdes_dq_.iserdesdq_4 ;
  input LD0_11;
  input CLKB0_11;
  input \pi_dqs_found_lanes_r1_reg[9] ;
  input \pi_dqs_found_lanes_r1_reg[9]_0 ;
  input \pi_dqs_found_lanes_r1_reg[9]_1 ;
  input \pi_dqs_found_lanes_r1_reg[9]_2 ;
  input ififo_rst_reg_4;
  input [5:0]\pi_dqs_found_lanes_r1_reg[9]_3 ;
  input \po_counter_read_val_reg[8]_23 ;
  input \po_counter_read_val_reg[8]_24 ;
  input \po_counter_read_val_reg[8]_25 ;
  input [7:0]\my_empty_reg[7]_38 ;
  input [7:0]\my_empty_reg[7]_39 ;
  input [7:0]\my_empty_reg[7]_40 ;
  input [7:0]\my_empty_reg[7]_41 ;
  input [7:0]\my_empty_reg[7]_42 ;
  input [7:0]\my_empty_reg[7]_43 ;
  input [7:0]\my_empty_reg[7]_44 ;
  input [7:0]\my_empty_reg[7]_45 ;
  input \input_[9].iserdes_dq_.iserdesdq_5 ;
  input LD0_12;
  input CLKB0_12;
  input \pi_dqs_found_lanes_r1_reg[10] ;
  input \pi_dqs_found_lanes_r1_reg[10]_0 ;
  input \pi_dqs_found_lanes_r1_reg[10]_1 ;
  input \pi_dqs_found_lanes_r1_reg[10]_2 ;
  input ififo_rst_reg_5;
  input [5:0]\pi_dqs_found_lanes_r1_reg[10]_3 ;
  input \po_counter_read_val_reg[8]_26 ;
  input \po_counter_read_val_reg[8]_27 ;
  input \po_counter_read_val_reg[8]_28 ;
  input [7:0]\my_empty_reg[7]_46 ;
  input [7:0]\my_empty_reg[7]_47 ;
  input [7:0]\my_empty_reg[7]_48 ;
  input [7:0]\my_empty_reg[7]_49 ;
  input [7:0]\my_empty_reg[7]_50 ;
  input [7:0]\my_empty_reg[7]_51 ;
  input [7:0]\my_empty_reg[7]_52 ;
  input [7:0]\my_empty_reg[7]_53 ;
  input \input_[9].iserdes_dq_.iserdesdq_6 ;
  input LD0_13;
  input CLKB0_13;
  input \pi_dqs_found_lanes_r1_reg[11] ;
  input \pi_dqs_found_lanes_r1_reg[11]_0 ;
  input \pi_dqs_found_lanes_r1_reg[11]_1 ;
  input \pi_dqs_found_lanes_r1_reg[11]_2 ;
  input ififo_rst_reg_6;
  input [5:0]\pi_dqs_found_lanes_r1_reg[11]_3 ;
  input \po_counter_read_val_reg[8]_29 ;
  input \po_counter_read_val_reg[8]_30 ;
  input \po_counter_read_val_reg[8]_31 ;
  input [7:0]\my_empty_reg[7]_54 ;
  input [7:0]\my_empty_reg[7]_55 ;
  input [7:0]\my_empty_reg[7]_56 ;
  input [7:0]\my_empty_reg[7]_57 ;
  input [7:0]\my_empty_reg[7]_58 ;
  input [7:0]\my_empty_reg[7]_59 ;
  input [7:0]\my_empty_reg[7]_60 ;
  input [7:0]\my_empty_reg[7]_61 ;
  input \rstdiv2_sync_r_reg[11] ;
  input [0:0]iodelay_ctrl_rdy;
  input out;
  input phy_data_wr_en;
  input [1:0]\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;
  input out_fifo;
  input [2:0]mc_cas_n;
  input [1:0]mc_we_n;
  input out_fifo_0;
  input [1:0]mc_ras_n;
  input [0:0]mc_cs_n;
  input [3:0]mc_address;
  input [63:0]Q;
  input out_fifo_1;
  input \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;
  input [10:0]D;
  input [5:0]\data_offset_1_i1_reg[5]_0 ;
  input [5:0]\data_offset_2_i1_reg[5]_0 ;
  input [71:0]phy_dout;
  input [71:0]out_fifo_i_75__5;
  input [71:0]out_fifo_i_75__6;
  input [71:0]out_fifo_i_75__7;
  input [71:0]out_fifo_i_75__0;
  input [71:0]out_fifo_i_75__1;
  input [71:0]out_fifo_i_75__2;
  input [71:0]out_fifo_i_75__3;
  input [12:0]out_fifo_i_47__8;
  input [48:0]mux_address;
  input [4:0]d_in;
  input [0:0]\po_counter_read_val_reg[0]_0 ;
  input [3:0]calib_sel;
  input [2:0]\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ;
  input [2:0]\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;
  input C_po_coarse_enable26_out;
  input C_po_counter_read_en38_out;
  input C_po_fine_enable23_out;
  input C_po_fine_inc29_out;
  input [3:0]\my_empty_reg[7]_62 ;
  input [7:0]\my_empty_reg[7]_63 ;
  input [3:0]\my_empty_reg[7]_64 ;
  input [3:0]\my_empty_reg[7]_65 ;
  input [3:0]D9;
  input [11:0]out_fifo_i_39;
  input out_fifo_2;

  wire A_rst_primitives_reg;
  wire A_rst_primitives_reg_0;
  wire A_rst_primitives_reg_1;
  wire A_rst_primitives_reg_2;
  wire A_rst_primitives_reg_3;
  wire A_rst_primitives_reg_4;
  wire A_rst_primitives_reg_5;
  wire A_rst_primitives_reg_6;
  wire A_rst_primitives_reg_7;
  wire CLKB0;
  wire CLKB0_10;
  wire CLKB0_11;
  wire CLKB0_12;
  wire CLKB0_13;
  wire CLKB0_7;
  wire CLKB0_8;
  wire CLKB0_9;
  wire [5:0]COUNTERLOADVAL;
  wire C_po_coarse_enable26_out;
  wire C_po_counter_read_en38_out;
  wire C_po_fine_enable23_out;
  wire C_po_fine_inc29_out;
  wire [10:0]D;
  wire [3:0]D1;
  wire [7:0]D2;
  wire [3:0]D3;
  wire [3:0]D4;
  wire [3:0]D5;
  wire [7:0]D6;
  wire [3:0]D7;
  wire [3:0]D8;
  wire [3:0]D9;
  wire LD0;
  wire LD0_10;
  wire LD0_11;
  wire LD0_12;
  wire LD0_13;
  wire LD0_7;
  wire LD0_8;
  wire LD0_9;
  wire [63:0]Q;
  wire RST0;
  wire [0:0]SR;
  wire [3:0]calib_sel;
  wire [4:0]d_in;
  wire [5:0]data_offset_1_i1;
  wire [5:0]\data_offset_1_i1_reg[5]_0 ;
  wire [5:0]data_offset_1_i2;
  wire [5:0]data_offset_2_i1;
  wire [5:0]\data_offset_2_i1_reg[5]_0 ;
  wire [5:0]data_offset_2_i2;
  wire [13:0]ddr3_addr;
  wire [2:0]ddr3_ba;
  wire ddr3_cas_n;
  wire [0:0]ddr3_cke;
  wire [0:0]ddr3_cs_n;
  wire [7:0]ddr3_dm;
  wire [63:0]ddr3_dq;
  wire [7:0]ddr3_dqs_n;
  wire [7:0]ddr3_dqs_p;
  wire [0:0]ddr3_odt;
  wire ddr3_ras_n;
  wire ddr3_reset_n;
  wire ddr3_we_n;
  wire [1:0]ddr_ck_out;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ;
  wire \entry_cnt_reg[4] ;
  wire freq_refclk;
  wire [2:0]\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ;
  wire [1:0]\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;
  wire \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;
  wire [2:0]\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;
  wire idelay_inc;
  wire idelay_ld_rst;
  wire idelay_ld_rst_0;
  wire idelay_ld_rst_1;
  wire idelay_ld_rst_2;
  wire idelay_ld_rst_3;
  wire idelay_ld_rst_4;
  wire idelay_ld_rst_5;
  wire idelay_ld_rst_6;
  wire idle;
  wire if_empty;
  wire ififo_rst_reg;
  wire ififo_rst_reg_0;
  wire ififo_rst_reg_1;
  wire ififo_rst_reg_2;
  wire ififo_rst_reg_3;
  wire ififo_rst_reg_4;
  wire ififo_rst_reg_5;
  wire ififo_rst_reg_6;
  wire [7:0]in0;
  wire in_dqs_lpbk_to_iddr_0;
  wire in_dqs_lpbk_to_iddr_1;
  wire in_dqs_lpbk_to_iddr_2;
  wire in_dqs_lpbk_to_iddr_3;
  wire in_dqs_lpbk_to_iddr_4;
  wire in_dqs_lpbk_to_iddr_5;
  wire in_dqs_lpbk_to_iddr_6;
  wire in_dqs_lpbk_to_iddr_7;
  wire \input_[9].iserdes_dq_.iserdesdq ;
  wire \input_[9].iserdes_dq_.iserdesdq_0 ;
  wire \input_[9].iserdes_dq_.iserdesdq_1 ;
  wire \input_[9].iserdes_dq_.iserdesdq_2 ;
  wire \input_[9].iserdes_dq_.iserdesdq_3 ;
  wire \input_[9].iserdes_dq_.iserdesdq_4 ;
  wire \input_[9].iserdes_dq_.iserdesdq_5 ;
  wire \input_[9].iserdes_dq_.iserdesdq_6 ;
  wire [0:0]iodelay_ctrl_rdy;
  wire [0:0]\mcGo_r_reg[15] ;
  wire [3:0]mc_address;
  wire [2:0]mc_cas_n;
  wire [0:0]mc_cs_n;
  wire [1:0]mc_ras_n;
  wire [1:0]mc_we_n;
  wire [119:1]mem_dq_in;
  wire [141:0]mem_dq_out;
  wire [141:0]mem_dq_ts;
  wire [11:0]mem_dqs_in;
  wire [11:0]mem_out;
  wire mem_refclk;
  wire mmcm_ps_clk;
  wire [48:0]mux_address;
  wire mux_reset_n;
  wire \my_empty_reg[1] ;
  wire \my_empty_reg[1]_0 ;
  wire \my_empty_reg[1]_1 ;
  wire \my_empty_reg[1]_2 ;
  wire \my_empty_reg[1]_3 ;
  wire \my_empty_reg[1]_4 ;
  wire \my_empty_reg[1]_5 ;
  wire \my_empty_reg[1]_6 ;
  wire \my_empty_reg[1]_7 ;
  wire \my_empty_reg[1]_8 ;
  wire \my_empty_reg[1]_9 ;
  wire [7:0]\my_empty_reg[7] ;
  wire [7:0]\my_empty_reg[7]_0 ;
  wire [7:0]\my_empty_reg[7]_1 ;
  wire [7:0]\my_empty_reg[7]_10 ;
  wire [7:0]\my_empty_reg[7]_11 ;
  wire [7:0]\my_empty_reg[7]_12 ;
  wire [7:0]\my_empty_reg[7]_13 ;
  wire [7:0]\my_empty_reg[7]_14 ;
  wire [7:0]\my_empty_reg[7]_15 ;
  wire [7:0]\my_empty_reg[7]_16 ;
  wire [7:0]\my_empty_reg[7]_17 ;
  wire [7:0]\my_empty_reg[7]_18 ;
  wire [7:0]\my_empty_reg[7]_19 ;
  wire [7:0]\my_empty_reg[7]_2 ;
  wire [7:0]\my_empty_reg[7]_20 ;
  wire [7:0]\my_empty_reg[7]_21 ;
  wire [7:0]\my_empty_reg[7]_22 ;
  wire [7:0]\my_empty_reg[7]_23 ;
  wire [7:0]\my_empty_reg[7]_24 ;
  wire [7:0]\my_empty_reg[7]_25 ;
  wire [7:0]\my_empty_reg[7]_26 ;
  wire [7:0]\my_empty_reg[7]_27 ;
  wire [7:0]\my_empty_reg[7]_28 ;
  wire [7:0]\my_empty_reg[7]_29 ;
  wire [7:0]\my_empty_reg[7]_3 ;
  wire [7:0]\my_empty_reg[7]_30 ;
  wire [7:0]\my_empty_reg[7]_31 ;
  wire [7:0]\my_empty_reg[7]_32 ;
  wire [7:0]\my_empty_reg[7]_33 ;
  wire [7:0]\my_empty_reg[7]_34 ;
  wire [7:0]\my_empty_reg[7]_35 ;
  wire [7:0]\my_empty_reg[7]_36 ;
  wire [7:0]\my_empty_reg[7]_37 ;
  wire [7:0]\my_empty_reg[7]_38 ;
  wire [7:0]\my_empty_reg[7]_39 ;
  wire [7:0]\my_empty_reg[7]_4 ;
  wire [7:0]\my_empty_reg[7]_40 ;
  wire [7:0]\my_empty_reg[7]_41 ;
  wire [7:0]\my_empty_reg[7]_42 ;
  wire [7:0]\my_empty_reg[7]_43 ;
  wire [7:0]\my_empty_reg[7]_44 ;
  wire [7:0]\my_empty_reg[7]_45 ;
  wire [7:0]\my_empty_reg[7]_46 ;
  wire [7:0]\my_empty_reg[7]_47 ;
  wire [7:0]\my_empty_reg[7]_48 ;
  wire [7:0]\my_empty_reg[7]_49 ;
  wire [7:0]\my_empty_reg[7]_5 ;
  wire [7:0]\my_empty_reg[7]_50 ;
  wire [7:0]\my_empty_reg[7]_51 ;
  wire [7:0]\my_empty_reg[7]_52 ;
  wire [7:0]\my_empty_reg[7]_53 ;
  wire [7:0]\my_empty_reg[7]_54 ;
  wire [7:0]\my_empty_reg[7]_55 ;
  wire [7:0]\my_empty_reg[7]_56 ;
  wire [7:0]\my_empty_reg[7]_57 ;
  wire [7:0]\my_empty_reg[7]_58 ;
  wire [7:0]\my_empty_reg[7]_59 ;
  wire [7:0]\my_empty_reg[7]_6 ;
  wire [7:0]\my_empty_reg[7]_60 ;
  wire [7:0]\my_empty_reg[7]_61 ;
  wire [3:0]\my_empty_reg[7]_62 ;
  wire [7:0]\my_empty_reg[7]_63 ;
  wire [3:0]\my_empty_reg[7]_64 ;
  wire [3:0]\my_empty_reg[7]_65 ;
  wire [7:0]\my_empty_reg[7]_7 ;
  wire [7:0]\my_empty_reg[7]_8 ;
  wire [7:0]\my_empty_reg[7]_9 ;
  wire [3:0]\my_full_reg[3] ;
  wire [0:0]\my_full_reg[3]_0 ;
  wire [1:0]\my_full_reg[3]_1 ;
  wire [0:0]\my_full_reg[3]_2 ;
  wire [3:0]\my_full_reg[3]_3 ;
  wire [0:0]of_ctl_full_v;
  wire out;
  wire out_dqs_0;
  wire out_dqs_1;
  wire out_dqs_2;
  wire out_dqs_3;
  wire out_dqs_4;
  wire out_dqs_5;
  wire out_dqs_6;
  wire out_dqs_7;
  wire out_fifo;
  wire out_fifo_0;
  wire out_fifo_1;
  wire out_fifo_2;
  wire [11:0]out_fifo_i_39;
  wire [12:0]out_fifo_i_47__8;
  wire [71:0]out_fifo_i_75__0;
  wire [71:0]out_fifo_i_75__1;
  wire [71:0]out_fifo_i_75__2;
  wire [71:0]out_fifo_i_75__3;
  wire [71:0]out_fifo_i_75__5;
  wire [71:0]out_fifo_i_75__6;
  wire [71:0]out_fifo_i_75__7;
  wire p_0_out;
  wire phy_cmd_wr_en;
  wire [24:0]phy_ctl_wd_i1;
  wire [24:0]phy_ctl_wd_i2;
  wire phy_ctl_wr_i1;
  wire phy_ctl_wr_i2;
  wire phy_data_wr_en;
  wire [71:0]phy_dout;
  wire phy_if_reset;
  wire phy_mc_ctl_full;
  wire phy_mc_ctl_full_r_reg;
  wire phy_mc_data_full;
  wire phy_rddata_en;
  wire phy_read_calib;
  wire phy_write_calib;
  wire [5:0]\pi_counter_read_val_reg[5] ;
  wire [5:0]\pi_counter_read_val_reg[5]_0 ;
  wire \pi_dqs_found_lanes_r1_reg[0] ;
  wire \pi_dqs_found_lanes_r1_reg[0]_0 ;
  wire \pi_dqs_found_lanes_r1_reg[0]_1 ;
  wire \pi_dqs_found_lanes_r1_reg[0]_2 ;
  wire \pi_dqs_found_lanes_r1_reg[10] ;
  wire \pi_dqs_found_lanes_r1_reg[10]_0 ;
  wire \pi_dqs_found_lanes_r1_reg[10]_1 ;
  wire \pi_dqs_found_lanes_r1_reg[10]_2 ;
  wire [5:0]\pi_dqs_found_lanes_r1_reg[10]_3 ;
  wire \pi_dqs_found_lanes_r1_reg[11] ;
  wire \pi_dqs_found_lanes_r1_reg[11]_0 ;
  wire \pi_dqs_found_lanes_r1_reg[11]_1 ;
  wire \pi_dqs_found_lanes_r1_reg[11]_2 ;
  wire [5:0]\pi_dqs_found_lanes_r1_reg[11]_3 ;
  wire \pi_dqs_found_lanes_r1_reg[1] ;
  wire \pi_dqs_found_lanes_r1_reg[1]_0 ;
  wire \pi_dqs_found_lanes_r1_reg[1]_1 ;
  wire \pi_dqs_found_lanes_r1_reg[1]_2 ;
  wire [5:0]\pi_dqs_found_lanes_r1_reg[1]_3 ;
  wire \pi_dqs_found_lanes_r1_reg[2] ;
  wire \pi_dqs_found_lanes_r1_reg[2]_0 ;
  wire \pi_dqs_found_lanes_r1_reg[2]_1 ;
  wire \pi_dqs_found_lanes_r1_reg[2]_2 ;
  wire [5:0]\pi_dqs_found_lanes_r1_reg[2]_3 ;
  wire \pi_dqs_found_lanes_r1_reg[3] ;
  wire \pi_dqs_found_lanes_r1_reg[3]_0 ;
  wire \pi_dqs_found_lanes_r1_reg[3]_1 ;
  wire \pi_dqs_found_lanes_r1_reg[3]_2 ;
  wire [5:0]\pi_dqs_found_lanes_r1_reg[3]_3 ;
  wire \pi_dqs_found_lanes_r1_reg[8] ;
  wire \pi_dqs_found_lanes_r1_reg[8]_0 ;
  wire \pi_dqs_found_lanes_r1_reg[8]_1 ;
  wire \pi_dqs_found_lanes_r1_reg[8]_2 ;
  wire [5:0]\pi_dqs_found_lanes_r1_reg[8]_3 ;
  wire \pi_dqs_found_lanes_r1_reg[9] ;
  wire \pi_dqs_found_lanes_r1_reg[9]_0 ;
  wire \pi_dqs_found_lanes_r1_reg[9]_1 ;
  wire \pi_dqs_found_lanes_r1_reg[9]_2 ;
  wire [5:0]\pi_dqs_found_lanes_r1_reg[9]_3 ;
  wire pll_locked;
  wire \po_counter_read_val_reg[0] ;
  wire [0:0]\po_counter_read_val_reg[0]_0 ;
  wire \po_counter_read_val_reg[1] ;
  wire \po_counter_read_val_reg[2] ;
  wire \po_counter_read_val_reg[3] ;
  wire \po_counter_read_val_reg[4] ;
  wire \po_counter_read_val_reg[5] ;
  wire \po_counter_read_val_reg[6] ;
  wire \po_counter_read_val_reg[7] ;
  wire \po_counter_read_val_reg[8] ;
  wire \po_counter_read_val_reg[8]_0 ;
  wire \po_counter_read_val_reg[8]_1 ;
  wire \po_counter_read_val_reg[8]_10 ;
  wire \po_counter_read_val_reg[8]_11 ;
  wire \po_counter_read_val_reg[8]_12 ;
  wire \po_counter_read_val_reg[8]_13 ;
  wire \po_counter_read_val_reg[8]_14 ;
  wire \po_counter_read_val_reg[8]_15 ;
  wire \po_counter_read_val_reg[8]_16 ;
  wire \po_counter_read_val_reg[8]_17 ;
  wire \po_counter_read_val_reg[8]_18 ;
  wire \po_counter_read_val_reg[8]_19 ;
  wire \po_counter_read_val_reg[8]_2 ;
  wire \po_counter_read_val_reg[8]_20 ;
  wire \po_counter_read_val_reg[8]_21 ;
  wire \po_counter_read_val_reg[8]_22 ;
  wire \po_counter_read_val_reg[8]_23 ;
  wire \po_counter_read_val_reg[8]_24 ;
  wire \po_counter_read_val_reg[8]_25 ;
  wire \po_counter_read_val_reg[8]_26 ;
  wire \po_counter_read_val_reg[8]_27 ;
  wire \po_counter_read_val_reg[8]_28 ;
  wire \po_counter_read_val_reg[8]_29 ;
  wire \po_counter_read_val_reg[8]_3 ;
  wire \po_counter_read_val_reg[8]_30 ;
  wire \po_counter_read_val_reg[8]_31 ;
  wire \po_counter_read_val_reg[8]_4 ;
  wire \po_counter_read_val_reg[8]_5 ;
  wire \po_counter_read_val_reg[8]_6 ;
  wire \po_counter_read_val_reg[8]_7 ;
  wire \po_counter_read_val_reg[8]_8 ;
  wire \po_counter_read_val_reg[8]_9 ;
  wire \po_stg2_wrcal_cnt_reg[2] ;
  wire \po_stg2_wrcal_cnt_reg[2]_0 ;
  wire \po_stg2_wrcal_cnt_reg[2]_1 ;
  wire \po_stg2_wrcal_cnt_reg[2]_10 ;
  wire \po_stg2_wrcal_cnt_reg[2]_11 ;
  wire \po_stg2_wrcal_cnt_reg[2]_12 ;
  wire \po_stg2_wrcal_cnt_reg[2]_13 ;
  wire \po_stg2_wrcal_cnt_reg[2]_14 ;
  wire \po_stg2_wrcal_cnt_reg[2]_15 ;
  wire \po_stg2_wrcal_cnt_reg[2]_16 ;
  wire \po_stg2_wrcal_cnt_reg[2]_17 ;
  wire \po_stg2_wrcal_cnt_reg[2]_18 ;
  wire \po_stg2_wrcal_cnt_reg[2]_19 ;
  wire \po_stg2_wrcal_cnt_reg[2]_2 ;
  wire \po_stg2_wrcal_cnt_reg[2]_20 ;
  wire \po_stg2_wrcal_cnt_reg[2]_21 ;
  wire \po_stg2_wrcal_cnt_reg[2]_22 ;
  wire \po_stg2_wrcal_cnt_reg[2]_23 ;
  wire \po_stg2_wrcal_cnt_reg[2]_24 ;
  wire \po_stg2_wrcal_cnt_reg[2]_25 ;
  wire \po_stg2_wrcal_cnt_reg[2]_26 ;
  wire \po_stg2_wrcal_cnt_reg[2]_27 ;
  wire \po_stg2_wrcal_cnt_reg[2]_28 ;
  wire \po_stg2_wrcal_cnt_reg[2]_29 ;
  wire \po_stg2_wrcal_cnt_reg[2]_3 ;
  wire \po_stg2_wrcal_cnt_reg[2]_30 ;
  wire \po_stg2_wrcal_cnt_reg[2]_31 ;
  wire \po_stg2_wrcal_cnt_reg[2]_32 ;
  wire \po_stg2_wrcal_cnt_reg[2]_33 ;
  wire \po_stg2_wrcal_cnt_reg[2]_34 ;
  wire \po_stg2_wrcal_cnt_reg[2]_35 ;
  wire \po_stg2_wrcal_cnt_reg[2]_36 ;
  wire \po_stg2_wrcal_cnt_reg[2]_37 ;
  wire \po_stg2_wrcal_cnt_reg[2]_38 ;
  wire \po_stg2_wrcal_cnt_reg[2]_39 ;
  wire \po_stg2_wrcal_cnt_reg[2]_4 ;
  wire \po_stg2_wrcal_cnt_reg[2]_40 ;
  wire \po_stg2_wrcal_cnt_reg[2]_41 ;
  wire \po_stg2_wrcal_cnt_reg[2]_42 ;
  wire \po_stg2_wrcal_cnt_reg[2]_43 ;
  wire \po_stg2_wrcal_cnt_reg[2]_44 ;
  wire \po_stg2_wrcal_cnt_reg[2]_45 ;
  wire \po_stg2_wrcal_cnt_reg[2]_46 ;
  wire \po_stg2_wrcal_cnt_reg[2]_47 ;
  wire \po_stg2_wrcal_cnt_reg[2]_48 ;
  wire \po_stg2_wrcal_cnt_reg[2]_49 ;
  wire \po_stg2_wrcal_cnt_reg[2]_5 ;
  wire \po_stg2_wrcal_cnt_reg[2]_50 ;
  wire \po_stg2_wrcal_cnt_reg[2]_51 ;
  wire \po_stg2_wrcal_cnt_reg[2]_52 ;
  wire \po_stg2_wrcal_cnt_reg[2]_53 ;
  wire \po_stg2_wrcal_cnt_reg[2]_54 ;
  wire \po_stg2_wrcal_cnt_reg[2]_55 ;
  wire \po_stg2_wrcal_cnt_reg[2]_56 ;
  wire \po_stg2_wrcal_cnt_reg[2]_57 ;
  wire \po_stg2_wrcal_cnt_reg[2]_58 ;
  wire \po_stg2_wrcal_cnt_reg[2]_59 ;
  wire \po_stg2_wrcal_cnt_reg[2]_6 ;
  wire \po_stg2_wrcal_cnt_reg[2]_60 ;
  wire \po_stg2_wrcal_cnt_reg[2]_61 ;
  wire \po_stg2_wrcal_cnt_reg[2]_7 ;
  wire \po_stg2_wrcal_cnt_reg[2]_8 ;
  wire \po_stg2_wrcal_cnt_reg[2]_9 ;
  wire \rd_mux_sel_r_reg[2] ;
  wire \rd_mux_sel_r_reg[2]_0 ;
  wire \rd_mux_sel_r_reg[2]_1 ;
  wire \rd_mux_sel_r_reg[2]_10 ;
  wire \rd_mux_sel_r_reg[2]_100 ;
  wire \rd_mux_sel_r_reg[2]_101 ;
  wire \rd_mux_sel_r_reg[2]_102 ;
  wire \rd_mux_sel_r_reg[2]_103 ;
  wire \rd_mux_sel_r_reg[2]_104 ;
  wire \rd_mux_sel_r_reg[2]_105 ;
  wire \rd_mux_sel_r_reg[2]_106 ;
  wire \rd_mux_sel_r_reg[2]_107 ;
  wire \rd_mux_sel_r_reg[2]_108 ;
  wire \rd_mux_sel_r_reg[2]_109 ;
  wire \rd_mux_sel_r_reg[2]_11 ;
  wire \rd_mux_sel_r_reg[2]_110 ;
  wire \rd_mux_sel_r_reg[2]_111 ;
  wire \rd_mux_sel_r_reg[2]_112 ;
  wire \rd_mux_sel_r_reg[2]_113 ;
  wire \rd_mux_sel_r_reg[2]_114 ;
  wire \rd_mux_sel_r_reg[2]_115 ;
  wire \rd_mux_sel_r_reg[2]_116 ;
  wire \rd_mux_sel_r_reg[2]_117 ;
  wire \rd_mux_sel_r_reg[2]_118 ;
  wire \rd_mux_sel_r_reg[2]_119 ;
  wire \rd_mux_sel_r_reg[2]_12 ;
  wire \rd_mux_sel_r_reg[2]_120 ;
  wire \rd_mux_sel_r_reg[2]_121 ;
  wire \rd_mux_sel_r_reg[2]_122 ;
  wire \rd_mux_sel_r_reg[2]_123 ;
  wire \rd_mux_sel_r_reg[2]_124 ;
  wire \rd_mux_sel_r_reg[2]_125 ;
  wire \rd_mux_sel_r_reg[2]_126 ;
  wire \rd_mux_sel_r_reg[2]_13 ;
  wire \rd_mux_sel_r_reg[2]_14 ;
  wire \rd_mux_sel_r_reg[2]_15 ;
  wire \rd_mux_sel_r_reg[2]_16 ;
  wire \rd_mux_sel_r_reg[2]_17 ;
  wire \rd_mux_sel_r_reg[2]_18 ;
  wire \rd_mux_sel_r_reg[2]_19 ;
  wire \rd_mux_sel_r_reg[2]_2 ;
  wire \rd_mux_sel_r_reg[2]_20 ;
  wire \rd_mux_sel_r_reg[2]_21 ;
  wire \rd_mux_sel_r_reg[2]_22 ;
  wire \rd_mux_sel_r_reg[2]_23 ;
  wire \rd_mux_sel_r_reg[2]_24 ;
  wire \rd_mux_sel_r_reg[2]_25 ;
  wire \rd_mux_sel_r_reg[2]_26 ;
  wire \rd_mux_sel_r_reg[2]_27 ;
  wire \rd_mux_sel_r_reg[2]_28 ;
  wire \rd_mux_sel_r_reg[2]_29 ;
  wire \rd_mux_sel_r_reg[2]_3 ;
  wire \rd_mux_sel_r_reg[2]_30 ;
  wire \rd_mux_sel_r_reg[2]_31 ;
  wire \rd_mux_sel_r_reg[2]_32 ;
  wire \rd_mux_sel_r_reg[2]_33 ;
  wire \rd_mux_sel_r_reg[2]_34 ;
  wire \rd_mux_sel_r_reg[2]_35 ;
  wire \rd_mux_sel_r_reg[2]_36 ;
  wire \rd_mux_sel_r_reg[2]_37 ;
  wire \rd_mux_sel_r_reg[2]_38 ;
  wire \rd_mux_sel_r_reg[2]_39 ;
  wire \rd_mux_sel_r_reg[2]_4 ;
  wire \rd_mux_sel_r_reg[2]_40 ;
  wire \rd_mux_sel_r_reg[2]_41 ;
  wire \rd_mux_sel_r_reg[2]_42 ;
  wire \rd_mux_sel_r_reg[2]_43 ;
  wire \rd_mux_sel_r_reg[2]_44 ;
  wire \rd_mux_sel_r_reg[2]_45 ;
  wire \rd_mux_sel_r_reg[2]_46 ;
  wire \rd_mux_sel_r_reg[2]_47 ;
  wire \rd_mux_sel_r_reg[2]_48 ;
  wire \rd_mux_sel_r_reg[2]_49 ;
  wire \rd_mux_sel_r_reg[2]_5 ;
  wire \rd_mux_sel_r_reg[2]_50 ;
  wire \rd_mux_sel_r_reg[2]_51 ;
  wire \rd_mux_sel_r_reg[2]_52 ;
  wire \rd_mux_sel_r_reg[2]_53 ;
  wire \rd_mux_sel_r_reg[2]_54 ;
  wire \rd_mux_sel_r_reg[2]_55 ;
  wire \rd_mux_sel_r_reg[2]_56 ;
  wire \rd_mux_sel_r_reg[2]_57 ;
  wire \rd_mux_sel_r_reg[2]_58 ;
  wire \rd_mux_sel_r_reg[2]_59 ;
  wire \rd_mux_sel_r_reg[2]_6 ;
  wire \rd_mux_sel_r_reg[2]_60 ;
  wire \rd_mux_sel_r_reg[2]_61 ;
  wire \rd_mux_sel_r_reg[2]_62 ;
  wire \rd_mux_sel_r_reg[2]_63 ;
  wire \rd_mux_sel_r_reg[2]_64 ;
  wire \rd_mux_sel_r_reg[2]_65 ;
  wire \rd_mux_sel_r_reg[2]_66 ;
  wire \rd_mux_sel_r_reg[2]_67 ;
  wire \rd_mux_sel_r_reg[2]_68 ;
  wire \rd_mux_sel_r_reg[2]_69 ;
  wire \rd_mux_sel_r_reg[2]_7 ;
  wire \rd_mux_sel_r_reg[2]_70 ;
  wire \rd_mux_sel_r_reg[2]_71 ;
  wire \rd_mux_sel_r_reg[2]_72 ;
  wire \rd_mux_sel_r_reg[2]_73 ;
  wire \rd_mux_sel_r_reg[2]_74 ;
  wire \rd_mux_sel_r_reg[2]_75 ;
  wire \rd_mux_sel_r_reg[2]_76 ;
  wire \rd_mux_sel_r_reg[2]_77 ;
  wire \rd_mux_sel_r_reg[2]_78 ;
  wire \rd_mux_sel_r_reg[2]_79 ;
  wire \rd_mux_sel_r_reg[2]_8 ;
  wire \rd_mux_sel_r_reg[2]_80 ;
  wire \rd_mux_sel_r_reg[2]_81 ;
  wire \rd_mux_sel_r_reg[2]_82 ;
  wire \rd_mux_sel_r_reg[2]_83 ;
  wire \rd_mux_sel_r_reg[2]_84 ;
  wire \rd_mux_sel_r_reg[2]_85 ;
  wire \rd_mux_sel_r_reg[2]_86 ;
  wire \rd_mux_sel_r_reg[2]_87 ;
  wire \rd_mux_sel_r_reg[2]_88 ;
  wire \rd_mux_sel_r_reg[2]_89 ;
  wire \rd_mux_sel_r_reg[2]_9 ;
  wire \rd_mux_sel_r_reg[2]_90 ;
  wire \rd_mux_sel_r_reg[2]_91 ;
  wire \rd_mux_sel_r_reg[2]_92 ;
  wire \rd_mux_sel_r_reg[2]_93 ;
  wire \rd_mux_sel_r_reg[2]_94 ;
  wire \rd_mux_sel_r_reg[2]_95 ;
  wire \rd_mux_sel_r_reg[2]_96 ;
  wire \rd_mux_sel_r_reg[2]_97 ;
  wire \rd_mux_sel_r_reg[2]_98 ;
  wire \rd_mux_sel_r_reg[2]_99 ;
  wire [63:0]\rd_ptr_reg[3] ;
  wire [63:0]\rd_ptr_reg[3]_0 ;
  wire [63:0]\rd_ptr_reg[3]_1 ;
  wire [63:0]\rd_ptr_reg[3]_2 ;
  wire [63:0]\rd_ptr_reg[3]_3 ;
  wire [63:0]\rd_ptr_reg[3]_4 ;
  wire [63:0]\rd_ptr_reg[3]_5 ;
  wire [63:0]\rd_ptr_reg[3]_6 ;
  wire [35:0]\rd_ptr_reg[3]_7 ;
  wire [23:0]\rd_ptr_reg[3]_8 ;
  wire [3:0]\rd_ptr_reg[3]_9 ;
  wire rst_sync_r1;
  wire rst_tmp;
  wire \rstdiv2_sync_r_reg[11] ;
  wire sync_pulse;
  wire ts_dqs_0;
  wire ts_dqs_1;
  wire ts_dqs_2;
  wire ts_dqs_3;
  wire ts_dqs_4;
  wire ts_dqs_5;
  wire ts_dqs_6;
  wire ts_dqs_7;

  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \cke_odt_thru_outfifo.gen_cke_obuf[0].u_cs_n_obuf 
       (.I(mem_dq_out[67]),
        .O(ddr3_cke));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \cke_odt_thru_outfifo.gen_odt_obuf.gen_odt_obuf[0].u_cs_n_obuf 
       (.I(mem_dq_out[62]),
        .O(ddr3_odt));
  FDRE \data_offset_1_i1_reg[0] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(\data_offset_1_i1_reg[5]_0 [0]),
        .Q(data_offset_1_i1[0]),
        .R(1'b0));
  FDRE \data_offset_1_i1_reg[1] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(\data_offset_1_i1_reg[5]_0 [1]),
        .Q(data_offset_1_i1[1]),
        .R(1'b0));
  FDRE \data_offset_1_i1_reg[2] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(\data_offset_1_i1_reg[5]_0 [2]),
        .Q(data_offset_1_i1[2]),
        .R(1'b0));
  FDRE \data_offset_1_i1_reg[3] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(\data_offset_1_i1_reg[5]_0 [3]),
        .Q(data_offset_1_i1[3]),
        .R(1'b0));
  FDRE \data_offset_1_i1_reg[4] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(\data_offset_1_i1_reg[5]_0 [4]),
        .Q(data_offset_1_i1[4]),
        .R(1'b0));
  FDRE \data_offset_1_i1_reg[5] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(\data_offset_1_i1_reg[5]_0 [5]),
        .Q(data_offset_1_i1[5]),
        .R(1'b0));
  FDRE \data_offset_1_i2_reg[0] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(data_offset_1_i1[0]),
        .Q(data_offset_1_i2[0]),
        .R(1'b0));
  FDRE \data_offset_1_i2_reg[1] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(data_offset_1_i1[1]),
        .Q(data_offset_1_i2[1]),
        .R(1'b0));
  FDRE \data_offset_1_i2_reg[2] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(data_offset_1_i1[2]),
        .Q(data_offset_1_i2[2]),
        .R(1'b0));
  FDRE \data_offset_1_i2_reg[3] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(data_offset_1_i1[3]),
        .Q(data_offset_1_i2[3]),
        .R(1'b0));
  FDRE \data_offset_1_i2_reg[4] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(data_offset_1_i1[4]),
        .Q(data_offset_1_i2[4]),
        .R(1'b0));
  FDRE \data_offset_1_i2_reg[5] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(data_offset_1_i1[5]),
        .Q(data_offset_1_i2[5]),
        .R(1'b0));
  FDRE \data_offset_2_i1_reg[0] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(\data_offset_2_i1_reg[5]_0 [0]),
        .Q(data_offset_2_i1[0]),
        .R(1'b0));
  FDRE \data_offset_2_i1_reg[1] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(\data_offset_2_i1_reg[5]_0 [1]),
        .Q(data_offset_2_i1[1]),
        .R(1'b0));
  FDRE \data_offset_2_i1_reg[2] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(\data_offset_2_i1_reg[5]_0 [2]),
        .Q(data_offset_2_i1[2]),
        .R(1'b0));
  FDRE \data_offset_2_i1_reg[3] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(\data_offset_2_i1_reg[5]_0 [3]),
        .Q(data_offset_2_i1[3]),
        .R(1'b0));
  FDRE \data_offset_2_i1_reg[4] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(\data_offset_2_i1_reg[5]_0 [4]),
        .Q(data_offset_2_i1[4]),
        .R(1'b0));
  FDRE \data_offset_2_i1_reg[5] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(\data_offset_2_i1_reg[5]_0 [5]),
        .Q(data_offset_2_i1[5]),
        .R(1'b0));
  FDRE \data_offset_2_i2_reg[0] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(data_offset_2_i1[0]),
        .Q(data_offset_2_i2[0]),
        .R(1'b0));
  FDRE \data_offset_2_i2_reg[1] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(data_offset_2_i1[1]),
        .Q(data_offset_2_i2[1]),
        .R(1'b0));
  FDRE \data_offset_2_i2_reg[2] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(data_offset_2_i1[2]),
        .Q(data_offset_2_i2[2]),
        .R(1'b0));
  FDRE \data_offset_2_i2_reg[3] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(data_offset_2_i1[3]),
        .Q(data_offset_2_i2[3]),
        .R(1'b0));
  FDRE \data_offset_2_i2_reg[4] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(data_offset_2_i1[4]),
        .Q(data_offset_2_i2[4]),
        .R(1'b0));
  FDRE \data_offset_2_i2_reg[5] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(data_offset_2_i1[5]),
        .Q(data_offset_2_i2[5]),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_addr_obuf[0].u_addr_obuf 
       (.I(mem_dq_out[95]),
        .O(ddr3_addr[0]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_addr_obuf[10].u_addr_obuf 
       (.I(mem_dq_out[87]),
        .O(ddr3_addr[10]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_addr_obuf[11].u_addr_obuf 
       (.I(mem_dq_out[89]),
        .O(ddr3_addr[11]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_addr_obuf[12].u_addr_obuf 
       (.I(mem_dq_out[90]),
        .O(ddr3_addr[12]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_addr_obuf[13].u_addr_obuf 
       (.I(mem_dq_out[86]),
        .O(ddr3_addr[13]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_addr_obuf[1].u_addr_obuf 
       (.I(mem_dq_out[92]),
        .O(ddr3_addr[1]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_addr_obuf[2].u_addr_obuf 
       (.I(mem_dq_out[80]),
        .O(ddr3_addr[2]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_addr_obuf[3].u_addr_obuf 
       (.I(mem_dq_out[94]),
        .O(ddr3_addr[3]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_addr_obuf[4].u_addr_obuf 
       (.I(mem_dq_out[88]),
        .O(ddr3_addr[4]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_addr_obuf[5].u_addr_obuf 
       (.I(mem_dq_out[91]),
        .O(ddr3_addr[5]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_addr_obuf[6].u_addr_obuf 
       (.I(mem_dq_out[81]),
        .O(ddr3_addr[6]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_addr_obuf[7].u_addr_obuf 
       (.I(mem_dq_out[85]),
        .O(ddr3_addr[7]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_addr_obuf[8].u_addr_obuf 
       (.I(mem_dq_out[76]),
        .O(ddr3_addr[8]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_addr_obuf[9].u_addr_obuf 
       (.I(mem_dq_out[93]),
        .O(ddr3_addr[9]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_bank_obuf[0].u_bank_obuf 
       (.I(mem_dq_out[83]),
        .O(ddr3_ba[0]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_bank_obuf[1].u_bank_obuf 
       (.I(mem_dq_out[82]),
        .O(ddr3_ba[1]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_bank_obuf[2].u_bank_obuf 
       (.I(mem_dq_out[77]),
        .O(ddr3_ba[2]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_cs_n_obuf.gen_cs_obuf[0].u_cs_n_obuf 
       (.I(mem_dq_out[64]),
        .O(ddr3_cs_n));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUFT #(
    .IOSTANDARD("DEFAULT")) 
    \gen_dm_obuf.loop_dm[0].u_dm_obuf 
       (.I(mem_dq_out[96]),
        .O(ddr3_dm[0]),
        .T(mem_dq_ts[96]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUFT #(
    .IOSTANDARD("DEFAULT")) 
    \gen_dm_obuf.loop_dm[1].u_dm_obuf 
       (.I(mem_dq_out[109]),
        .O(ddr3_dm[1]),
        .T(mem_dq_ts[109]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUFT #(
    .IOSTANDARD("DEFAULT")) 
    \gen_dm_obuf.loop_dm[2].u_dm_obuf 
       (.I(mem_dq_out[121]),
        .O(ddr3_dm[2]),
        .T(mem_dq_ts[121]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUFT #(
    .IOSTANDARD("DEFAULT")) 
    \gen_dm_obuf.loop_dm[3].u_dm_obuf 
       (.I(mem_dq_out[133]),
        .O(ddr3_dm[3]),
        .T(mem_dq_ts[133]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUFT #(
    .IOSTANDARD("DEFAULT")) 
    \gen_dm_obuf.loop_dm[4].u_dm_obuf 
       (.I(mem_dq_out[0]),
        .O(ddr3_dm[4]),
        .T(mem_dq_ts[0]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUFT #(
    .IOSTANDARD("DEFAULT")) 
    \gen_dm_obuf.loop_dm[5].u_dm_obuf 
       (.I(mem_dq_out[13]),
        .O(ddr3_dm[5]),
        .T(mem_dq_ts[13]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUFT #(
    .IOSTANDARD("DEFAULT")) 
    \gen_dm_obuf.loop_dm[6].u_dm_obuf 
       (.I(mem_dq_out[25]),
        .O(ddr3_dm[6]),
        .T(mem_dq_ts[25]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUFT #(
    .IOSTANDARD("DEFAULT")) 
    \gen_dm_obuf.loop_dm[7].u_dm_obuf 
       (.I(mem_dq_out[37]),
        .O(ddr3_dm[7]),
        .T(mem_dq_ts[37]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[0].u_iobuf_dq 
       (.I(mem_dq_out[97]),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[0]),
        .O(mem_dq_in[81]),
        .T(mem_dq_ts[97]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[10].u_iobuf_dq 
       (.I(mem_dq_out[112]),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[10]),
        .O(mem_dq_in[94]),
        .T(mem_dq_ts[112]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[11].u_iobuf_dq 
       (.I(mem_dq_out[113]),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[11]),
        .O(mem_dq_in[95]),
        .T(mem_dq_ts[113]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[12].u_iobuf_dq 
       (.I(mem_dq_out[114]),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[12]),
        .O(mem_dq_in[96]),
        .T(mem_dq_ts[114]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[13].u_iobuf_dq 
       (.I(mem_dq_out[115]),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[13]),
        .O(mem_dq_in[97]),
        .T(mem_dq_ts[115]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[14].u_iobuf_dq 
       (.I(mem_dq_out[116]),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[14]),
        .O(mem_dq_in[98]),
        .T(mem_dq_ts[116]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[15].u_iobuf_dq 
       (.I(mem_dq_out[117]),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[15]),
        .O(mem_dq_in[99]),
        .T(mem_dq_ts[117]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[16].u_iobuf_dq 
       (.I(mem_dq_out[122]),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[16]),
        .O(mem_dq_in[102]),
        .T(mem_dq_ts[122]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[17].u_iobuf_dq 
       (.I(mem_dq_out[123]),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[17]),
        .O(mem_dq_in[103]),
        .T(mem_dq_ts[123]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[18].u_iobuf_dq 
       (.I(mem_dq_out[124]),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[18]),
        .O(mem_dq_in[104]),
        .T(mem_dq_ts[124]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[19].u_iobuf_dq 
       (.I(mem_dq_out[125]),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[19]),
        .O(mem_dq_in[105]),
        .T(mem_dq_ts[125]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[1].u_iobuf_dq 
       (.I(mem_dq_out[98]),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[1]),
        .O(mem_dq_in[82]),
        .T(mem_dq_ts[98]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[20].u_iobuf_dq 
       (.I(mem_dq_out[126]),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[20]),
        .O(mem_dq_in[106]),
        .T(mem_dq_ts[126]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[21].u_iobuf_dq 
       (.I(mem_dq_out[127]),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[21]),
        .O(mem_dq_in[107]),
        .T(mem_dq_ts[127]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[22].u_iobuf_dq 
       (.I(mem_dq_out[128]),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[22]),
        .O(mem_dq_in[108]),
        .T(mem_dq_ts[128]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[23].u_iobuf_dq 
       (.I(mem_dq_out[129]),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[23]),
        .O(mem_dq_in[109]),
        .T(mem_dq_ts[129]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[24].u_iobuf_dq 
       (.I(mem_dq_out[134]),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[24]),
        .O(mem_dq_in[112]),
        .T(mem_dq_ts[134]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[25].u_iobuf_dq 
       (.I(mem_dq_out[135]),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[25]),
        .O(mem_dq_in[113]),
        .T(mem_dq_ts[135]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[26].u_iobuf_dq 
       (.I(mem_dq_out[136]),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[26]),
        .O(mem_dq_in[114]),
        .T(mem_dq_ts[136]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[27].u_iobuf_dq 
       (.I(mem_dq_out[137]),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[27]),
        .O(mem_dq_in[115]),
        .T(mem_dq_ts[137]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[28].u_iobuf_dq 
       (.I(mem_dq_out[138]),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[28]),
        .O(mem_dq_in[116]),
        .T(mem_dq_ts[138]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[29].u_iobuf_dq 
       (.I(mem_dq_out[139]),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[29]),
        .O(mem_dq_in[117]),
        .T(mem_dq_ts[139]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[2].u_iobuf_dq 
       (.I(mem_dq_out[99]),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[2]),
        .O(mem_dq_in[83]),
        .T(mem_dq_ts[99]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[30].u_iobuf_dq 
       (.I(mem_dq_out[140]),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[30]),
        .O(mem_dq_in[118]),
        .T(mem_dq_ts[140]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[31].u_iobuf_dq 
       (.I(mem_dq_out[141]),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[31]),
        .O(mem_dq_in[119]),
        .T(mem_dq_ts[141]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[32].u_iobuf_dq 
       (.I(mem_dq_out[1]),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[32]),
        .O(mem_dq_in[1]),
        .T(mem_dq_ts[1]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[33].u_iobuf_dq 
       (.I(mem_dq_out[2]),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[33]),
        .O(mem_dq_in[2]),
        .T(mem_dq_ts[2]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[34].u_iobuf_dq 
       (.I(mem_dq_out[3]),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[34]),
        .O(mem_dq_in[3]),
        .T(mem_dq_ts[3]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[35].u_iobuf_dq 
       (.I(mem_dq_out[4]),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[35]),
        .O(mem_dq_in[4]),
        .T(mem_dq_ts[4]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[36].u_iobuf_dq 
       (.I(mem_dq_out[5]),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[36]),
        .O(mem_dq_in[5]),
        .T(mem_dq_ts[5]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[37].u_iobuf_dq 
       (.I(mem_dq_out[6]),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[37]),
        .O(mem_dq_in[6]),
        .T(mem_dq_ts[6]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[38].u_iobuf_dq 
       (.I(mem_dq_out[7]),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[38]),
        .O(mem_dq_in[7]),
        .T(mem_dq_ts[7]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[39].u_iobuf_dq 
       (.I(mem_dq_out[9]),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[39]),
        .O(mem_dq_in[9]),
        .T(mem_dq_ts[9]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[3].u_iobuf_dq 
       (.I(mem_dq_out[100]),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[3]),
        .O(mem_dq_in[84]),
        .T(mem_dq_ts[100]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[40].u_iobuf_dq 
       (.I(mem_dq_out[14]),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[40]),
        .O(mem_dq_in[12]),
        .T(mem_dq_ts[14]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[41].u_iobuf_dq 
       (.I(mem_dq_out[15]),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[41]),
        .O(mem_dq_in[13]),
        .T(mem_dq_ts[15]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[42].u_iobuf_dq 
       (.I(mem_dq_out[16]),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[42]),
        .O(mem_dq_in[14]),
        .T(mem_dq_ts[16]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[43].u_iobuf_dq 
       (.I(mem_dq_out[17]),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[43]),
        .O(mem_dq_in[15]),
        .T(mem_dq_ts[17]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[44].u_iobuf_dq 
       (.I(mem_dq_out[18]),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[44]),
        .O(mem_dq_in[16]),
        .T(mem_dq_ts[18]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[45].u_iobuf_dq 
       (.I(mem_dq_out[19]),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[45]),
        .O(mem_dq_in[17]),
        .T(mem_dq_ts[19]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[46].u_iobuf_dq 
       (.I(mem_dq_out[20]),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[46]),
        .O(mem_dq_in[18]),
        .T(mem_dq_ts[20]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[47].u_iobuf_dq 
       (.I(mem_dq_out[21]),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[47]),
        .O(mem_dq_in[19]),
        .T(mem_dq_ts[21]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[48].u_iobuf_dq 
       (.I(mem_dq_out[26]),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[48]),
        .O(mem_dq_in[22]),
        .T(mem_dq_ts[26]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[49].u_iobuf_dq 
       (.I(mem_dq_out[27]),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[49]),
        .O(mem_dq_in[23]),
        .T(mem_dq_ts[27]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[4].u_iobuf_dq 
       (.I(mem_dq_out[101]),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[4]),
        .O(mem_dq_in[85]),
        .T(mem_dq_ts[101]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[50].u_iobuf_dq 
       (.I(mem_dq_out[28]),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[50]),
        .O(mem_dq_in[24]),
        .T(mem_dq_ts[28]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[51].u_iobuf_dq 
       (.I(mem_dq_out[29]),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[51]),
        .O(mem_dq_in[25]),
        .T(mem_dq_ts[29]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[52].u_iobuf_dq 
       (.I(mem_dq_out[30]),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[52]),
        .O(mem_dq_in[26]),
        .T(mem_dq_ts[30]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[53].u_iobuf_dq 
       (.I(mem_dq_out[31]),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[53]),
        .O(mem_dq_in[27]),
        .T(mem_dq_ts[31]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[54].u_iobuf_dq 
       (.I(mem_dq_out[32]),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[54]),
        .O(mem_dq_in[28]),
        .T(mem_dq_ts[32]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[55].u_iobuf_dq 
       (.I(mem_dq_out[33]),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[55]),
        .O(mem_dq_in[29]),
        .T(mem_dq_ts[33]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[56].u_iobuf_dq 
       (.I(mem_dq_out[38]),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[56]),
        .O(mem_dq_in[32]),
        .T(mem_dq_ts[38]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[57].u_iobuf_dq 
       (.I(mem_dq_out[39]),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[57]),
        .O(mem_dq_in[33]),
        .T(mem_dq_ts[39]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[58].u_iobuf_dq 
       (.I(mem_dq_out[40]),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[58]),
        .O(mem_dq_in[34]),
        .T(mem_dq_ts[40]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[59].u_iobuf_dq 
       (.I(mem_dq_out[41]),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[59]),
        .O(mem_dq_in[35]),
        .T(mem_dq_ts[41]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[5].u_iobuf_dq 
       (.I(mem_dq_out[102]),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[5]),
        .O(mem_dq_in[86]),
        .T(mem_dq_ts[102]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[60].u_iobuf_dq 
       (.I(mem_dq_out[42]),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[60]),
        .O(mem_dq_in[36]),
        .T(mem_dq_ts[42]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[61].u_iobuf_dq 
       (.I(mem_dq_out[43]),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[61]),
        .O(mem_dq_in[37]),
        .T(mem_dq_ts[43]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[62].u_iobuf_dq 
       (.I(mem_dq_out[44]),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[62]),
        .O(mem_dq_in[38]),
        .T(mem_dq_ts[44]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[63].u_iobuf_dq 
       (.I(mem_dq_out[45]),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[63]),
        .O(mem_dq_in[39]),
        .T(mem_dq_ts[45]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[6].u_iobuf_dq 
       (.I(mem_dq_out[103]),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[6]),
        .O(mem_dq_in[87]),
        .T(mem_dq_ts[103]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[7].u_iobuf_dq 
       (.I(mem_dq_out[105]),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[7]),
        .O(mem_dq_in[89]),
        .T(mem_dq_ts[105]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[8].u_iobuf_dq 
       (.I(mem_dq_out[110]),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[8]),
        .O(mem_dq_in[92]),
        .T(mem_dq_ts[110]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUF_INTERMDISABLE #(
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("TRUE")) 
    \gen_dq_iobuf_HR.gen_dq_iobuf[9].u_iobuf_dq 
       (.I(mem_dq_out[111]),
        .IBUFDISABLE(idle),
        .INTERMDISABLE(idle),
        .IO(ddr3_dq[9]),
        .O(mem_dq_in[93]),
        .T(mem_dq_ts[111]));
  mig_mig_7series_v4_2_poc_pd \gen_dqs_iobuf_HR.gen_dqs_iobuf[0].gen_dqs_diff.u_iddr_edge_det 
       (.in_dqs_lpbk_to_iddr_0(in_dqs_lpbk_to_iddr_0),
        .mmcm_ps_clk(mmcm_ps_clk),
        .rst_sync_r1(rst_sync_r1));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFDS_DIFF_OUT_INTERMDISABLE #(
    .DQS_BIAS("TRUE"),
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("FALSE")) 
    \gen_dqs_iobuf_HR.gen_dqs_iobuf[0].gen_dqs_diff.u_iobuf_dqs 
       (.I(out_dqs_0),
        .IBUFDISABLE(1'b0),
        .INTERMDISABLE(idle),
        .IO(ddr3_dqs_p[0]),
        .IOB(ddr3_dqs_n[0]),
        .O(mem_dqs_in[8]),
        .OB(in_dqs_lpbk_to_iddr_0),
        .TM(ts_dqs_0),
        .TS(ts_dqs_0));
  mig_mig_7series_v4_2_poc_pd_5 \gen_dqs_iobuf_HR.gen_dqs_iobuf[1].gen_dqs_diff.u_iddr_edge_det 
       (.in_dqs_lpbk_to_iddr_1(in_dqs_lpbk_to_iddr_1),
        .mmcm_ps_clk(mmcm_ps_clk),
        .rst_sync_r1(rst_sync_r1));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFDS_DIFF_OUT_INTERMDISABLE #(
    .DQS_BIAS("TRUE"),
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("FALSE")) 
    \gen_dqs_iobuf_HR.gen_dqs_iobuf[1].gen_dqs_diff.u_iobuf_dqs 
       (.I(out_dqs_1),
        .IBUFDISABLE(1'b0),
        .INTERMDISABLE(idle),
        .IO(ddr3_dqs_p[1]),
        .IOB(ddr3_dqs_n[1]),
        .O(mem_dqs_in[9]),
        .OB(in_dqs_lpbk_to_iddr_1),
        .TM(ts_dqs_1),
        .TS(ts_dqs_1));
  mig_mig_7series_v4_2_poc_pd_6 \gen_dqs_iobuf_HR.gen_dqs_iobuf[2].gen_dqs_diff.u_iddr_edge_det 
       (.in_dqs_lpbk_to_iddr_2(in_dqs_lpbk_to_iddr_2),
        .mmcm_ps_clk(mmcm_ps_clk),
        .rst_sync_r1(rst_sync_r1));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFDS_DIFF_OUT_INTERMDISABLE #(
    .DQS_BIAS("TRUE"),
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("FALSE")) 
    \gen_dqs_iobuf_HR.gen_dqs_iobuf[2].gen_dqs_diff.u_iobuf_dqs 
       (.I(out_dqs_2),
        .IBUFDISABLE(1'b0),
        .INTERMDISABLE(idle),
        .IO(ddr3_dqs_p[2]),
        .IOB(ddr3_dqs_n[2]),
        .O(mem_dqs_in[10]),
        .OB(in_dqs_lpbk_to_iddr_2),
        .TM(ts_dqs_2),
        .TS(ts_dqs_2));
  mig_mig_7series_v4_2_poc_pd_7 \gen_dqs_iobuf_HR.gen_dqs_iobuf[3].gen_dqs_diff.u_iddr_edge_det 
       (.in_dqs_lpbk_to_iddr_3(in_dqs_lpbk_to_iddr_3),
        .mmcm_ps_clk(mmcm_ps_clk),
        .rst_sync_r1(rst_sync_r1));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFDS_DIFF_OUT_INTERMDISABLE #(
    .DQS_BIAS("TRUE"),
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("FALSE")) 
    \gen_dqs_iobuf_HR.gen_dqs_iobuf[3].gen_dqs_diff.u_iobuf_dqs 
       (.I(out_dqs_3),
        .IBUFDISABLE(1'b0),
        .INTERMDISABLE(idle),
        .IO(ddr3_dqs_p[3]),
        .IOB(ddr3_dqs_n[3]),
        .O(mem_dqs_in[11]),
        .OB(in_dqs_lpbk_to_iddr_3),
        .TM(ts_dqs_3),
        .TS(ts_dqs_3));
  mig_mig_7series_v4_2_poc_pd_8 \gen_dqs_iobuf_HR.gen_dqs_iobuf[4].gen_dqs_diff.u_iddr_edge_det 
       (.in_dqs_lpbk_to_iddr_4(in_dqs_lpbk_to_iddr_4),
        .mmcm_ps_clk(mmcm_ps_clk),
        .rst_sync_r1(rst_sync_r1));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFDS_DIFF_OUT_INTERMDISABLE #(
    .DQS_BIAS("TRUE"),
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("FALSE")) 
    \gen_dqs_iobuf_HR.gen_dqs_iobuf[4].gen_dqs_diff.u_iobuf_dqs 
       (.I(out_dqs_4),
        .IBUFDISABLE(1'b0),
        .INTERMDISABLE(idle),
        .IO(ddr3_dqs_p[4]),
        .IOB(ddr3_dqs_n[4]),
        .O(mem_dqs_in[0]),
        .OB(in_dqs_lpbk_to_iddr_4),
        .TM(ts_dqs_4),
        .TS(ts_dqs_4));
  mig_mig_7series_v4_2_poc_pd_9 \gen_dqs_iobuf_HR.gen_dqs_iobuf[5].gen_dqs_diff.u_iddr_edge_det 
       (.in_dqs_lpbk_to_iddr_5(in_dqs_lpbk_to_iddr_5),
        .mmcm_ps_clk(mmcm_ps_clk),
        .rst_sync_r1(rst_sync_r1));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFDS_DIFF_OUT_INTERMDISABLE #(
    .DQS_BIAS("TRUE"),
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("FALSE")) 
    \gen_dqs_iobuf_HR.gen_dqs_iobuf[5].gen_dqs_diff.u_iobuf_dqs 
       (.I(out_dqs_5),
        .IBUFDISABLE(1'b0),
        .INTERMDISABLE(idle),
        .IO(ddr3_dqs_p[5]),
        .IOB(ddr3_dqs_n[5]),
        .O(mem_dqs_in[1]),
        .OB(in_dqs_lpbk_to_iddr_5),
        .TM(ts_dqs_5),
        .TS(ts_dqs_5));
  mig_mig_7series_v4_2_poc_pd_10 \gen_dqs_iobuf_HR.gen_dqs_iobuf[6].gen_dqs_diff.u_iddr_edge_det 
       (.in_dqs_lpbk_to_iddr_6(in_dqs_lpbk_to_iddr_6),
        .mmcm_ps_clk(mmcm_ps_clk),
        .rst_sync_r1(rst_sync_r1));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFDS_DIFF_OUT_INTERMDISABLE #(
    .DQS_BIAS("TRUE"),
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("FALSE")) 
    \gen_dqs_iobuf_HR.gen_dqs_iobuf[6].gen_dqs_diff.u_iobuf_dqs 
       (.I(out_dqs_6),
        .IBUFDISABLE(1'b0),
        .INTERMDISABLE(idle),
        .IO(ddr3_dqs_p[6]),
        .IOB(ddr3_dqs_n[6]),
        .O(mem_dqs_in[2]),
        .OB(in_dqs_lpbk_to_iddr_6),
        .TM(ts_dqs_6),
        .TS(ts_dqs_6));
  mig_mig_7series_v4_2_poc_pd_11 \gen_dqs_iobuf_HR.gen_dqs_iobuf[7].gen_dqs_diff.u_iddr_edge_det 
       (.in_dqs_lpbk_to_iddr_7(in_dqs_lpbk_to_iddr_7),
        .mmcm_ps_clk(mmcm_ps_clk),
        .rst_sync_r1(rst_sync_r1));
  (* BOX_TYPE = "PRIMITIVE" *) 
  IOBUFDS_DIFF_OUT_INTERMDISABLE #(
    .DQS_BIAS("TRUE"),
    .IOSTANDARD("DEFAULT"),
    .SIM_DEVICE("7SERIES"),
    .USE_IBUFDISABLE("FALSE")) 
    \gen_dqs_iobuf_HR.gen_dqs_iobuf[7].gen_dqs_diff.u_iobuf_dqs 
       (.I(out_dqs_7),
        .IBUFDISABLE(1'b0),
        .INTERMDISABLE(idle),
        .IO(ddr3_dqs_p[7]),
        .IOB(ddr3_dqs_n[7]),
        .O(mem_dqs_in[3]),
        .OB(in_dqs_lpbk_to_iddr_7),
        .TM(ts_dqs_7),
        .TS(ts_dqs_7));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    \gen_reset_obuf.u_reset_obuf 
       (.I(mux_reset_n),
        .O(ddr3_reset_n));
  mig_mig_7series_v4_2_ddr_of_pre_fifo \genblk24.phy_ctl_pre_fifo_0 
       (.SR(SR),
        .\rd_ptr_timing_reg[0]_0 (\entry_cnt_reg[4] ));
  mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized0 \genblk24.phy_ctl_pre_fifo_1 
       (.SR(SR),
        .\rd_ptr_timing_reg[0]_0 (\entry_cnt_reg[4] ));
  mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized0_12 \genblk24.phy_ctl_pre_fifo_2 
       (.SR(SR),
        .\rd_ptr_timing_reg[0]_0 (\entry_cnt_reg[4] ));
  FDRE \phy_ctl_wd_i1_reg[0] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(D[0]),
        .Q(phy_ctl_wd_i1[0]),
        .R(1'b0));
  FDRE \phy_ctl_wd_i1_reg[17] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(D[3]),
        .Q(phy_ctl_wd_i1[17]),
        .R(1'b0));
  FDRE \phy_ctl_wd_i1_reg[18] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(D[4]),
        .Q(phy_ctl_wd_i1[18]),
        .R(1'b0));
  FDRE \phy_ctl_wd_i1_reg[19] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(D[5]),
        .Q(phy_ctl_wd_i1[19]),
        .R(1'b0));
  FDRE \phy_ctl_wd_i1_reg[1] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(D[1]),
        .Q(phy_ctl_wd_i1[1]),
        .R(1'b0));
  FDRE \phy_ctl_wd_i1_reg[20] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(D[6]),
        .Q(phy_ctl_wd_i1[20]),
        .R(1'b0));
  FDRE \phy_ctl_wd_i1_reg[21] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(D[7]),
        .Q(phy_ctl_wd_i1[21]),
        .R(1'b0));
  FDRE \phy_ctl_wd_i1_reg[22] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(D[8]),
        .Q(phy_ctl_wd_i1[22]),
        .R(1'b0));
  FDRE \phy_ctl_wd_i1_reg[23] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(D[9]),
        .Q(phy_ctl_wd_i1[23]),
        .R(1'b0));
  FDRE \phy_ctl_wd_i1_reg[24] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(D[10]),
        .Q(phy_ctl_wd_i1[24]),
        .R(1'b0));
  FDRE \phy_ctl_wd_i1_reg[2] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(D[2]),
        .Q(phy_ctl_wd_i1[2]),
        .R(1'b0));
  FDRE \phy_ctl_wd_i2_reg[0] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(phy_ctl_wd_i1[0]),
        .Q(phy_ctl_wd_i2[0]),
        .R(1'b0));
  FDRE \phy_ctl_wd_i2_reg[17] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(phy_ctl_wd_i1[17]),
        .Q(phy_ctl_wd_i2[17]),
        .R(1'b0));
  FDRE \phy_ctl_wd_i2_reg[18] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(phy_ctl_wd_i1[18]),
        .Q(phy_ctl_wd_i2[18]),
        .R(1'b0));
  FDRE \phy_ctl_wd_i2_reg[19] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(phy_ctl_wd_i1[19]),
        .Q(phy_ctl_wd_i2[19]),
        .R(1'b0));
  FDRE \phy_ctl_wd_i2_reg[1] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(phy_ctl_wd_i1[1]),
        .Q(phy_ctl_wd_i2[1]),
        .R(1'b0));
  FDRE \phy_ctl_wd_i2_reg[20] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(phy_ctl_wd_i1[20]),
        .Q(phy_ctl_wd_i2[20]),
        .R(1'b0));
  FDRE \phy_ctl_wd_i2_reg[21] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(phy_ctl_wd_i1[21]),
        .Q(phy_ctl_wd_i2[21]),
        .R(1'b0));
  FDRE \phy_ctl_wd_i2_reg[22] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(phy_ctl_wd_i1[22]),
        .Q(phy_ctl_wd_i2[22]),
        .R(1'b0));
  FDRE \phy_ctl_wd_i2_reg[23] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(phy_ctl_wd_i1[23]),
        .Q(phy_ctl_wd_i2[23]),
        .R(1'b0));
  FDRE \phy_ctl_wd_i2_reg[24] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(phy_ctl_wd_i1[24]),
        .Q(phy_ctl_wd_i2[24]),
        .R(1'b0));
  FDRE \phy_ctl_wd_i2_reg[2] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(phy_ctl_wd_i1[2]),
        .Q(phy_ctl_wd_i2[2]),
        .R(1'b0));
  FDRE phy_ctl_wr_i1_reg
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(phy_cmd_wr_en),
        .Q(phy_ctl_wr_i1),
        .R(1'b0));
  FDRE phy_ctl_wr_i2_reg
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(phy_ctl_wr_i1),
        .Q(phy_ctl_wr_i2),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    u_cas_n_obuf
       (.I(mem_dq_out[65]),
        .O(ddr3_cas_n));
  mig_mig_7series_v4_2_ddr_mc_phy u_ddr_mc_phy
       (.A_rst_primitives_reg(A_rst_primitives_reg),
        .A_rst_primitives_reg_0(A_rst_primitives_reg_0),
        .A_rst_primitives_reg_1(A_rst_primitives_reg_1),
        .A_rst_primitives_reg_2(A_rst_primitives_reg_2),
        .A_rst_primitives_reg_3(A_rst_primitives_reg_3),
        .A_rst_primitives_reg_4(A_rst_primitives_reg_4),
        .A_rst_primitives_reg_5(A_rst_primitives_reg_5),
        .A_rst_primitives_reg_6(A_rst_primitives_reg_6),
        .A_rst_primitives_reg_7(A_rst_primitives_reg_7),
        .CLKB0(CLKB0),
        .CLKB0_10(CLKB0_10),
        .CLKB0_11(CLKB0_11),
        .CLKB0_12(CLKB0_12),
        .CLKB0_13(CLKB0_13),
        .CLKB0_7(CLKB0_7),
        .CLKB0_8(CLKB0_8),
        .CLKB0_9(CLKB0_9),
        .COUNTERLOADVAL(COUNTERLOADVAL),
        .C_po_coarse_enable26_out(C_po_coarse_enable26_out),
        .C_po_counter_read_en38_out(C_po_counter_read_en38_out),
        .C_po_fine_enable23_out(C_po_fine_enable23_out),
        .C_po_fine_inc29_out(C_po_fine_inc29_out),
        .D1(D1),
        .D2(D2),
        .D3(D3),
        .D4(D4),
        .D5(D5),
        .D6(D6),
        .D7(D7),
        .D8(D8),
        .D9(D9),
        .LD0(LD0),
        .LD0_10(LD0_10),
        .LD0_11(LD0_11),
        .LD0_12(LD0_12),
        .LD0_13(LD0_13),
        .LD0_7(LD0_7),
        .LD0_8(LD0_8),
        .LD0_9(LD0_9),
        .Q({phy_ctl_wd_i2[24:17],phy_ctl_wd_i2[2:0]}),
        .RST0(RST0),
        .SR(SR),
        .calib_sel(calib_sel),
        .d_in(d_in),
        .ddr_ck_out(ddr_ck_out),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ),
        .\entry_cnt_reg[4] (\entry_cnt_reg[4] ),
        .freq_refclk(freq_refclk),
        .\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] (\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ),
        .\gen_mux_rd[0].mux_rd_rise0_r_reg[0] (\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ),
        .\gen_mux_rd[1].mux_rd_rise0_r_reg[1] (\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .idelay_inc(idelay_inc),
        .idelay_ld_rst(idelay_ld_rst),
        .idelay_ld_rst_0(idelay_ld_rst_0),
        .idelay_ld_rst_1(idelay_ld_rst_1),
        .idelay_ld_rst_2(idelay_ld_rst_2),
        .idelay_ld_rst_3(idelay_ld_rst_3),
        .idelay_ld_rst_4(idelay_ld_rst_4),
        .idelay_ld_rst_5(idelay_ld_rst_5),
        .idelay_ld_rst_6(idelay_ld_rst_6),
        .if_empty(if_empty),
        .ififo_rst_reg(ififo_rst_reg),
        .ififo_rst_reg_0(ififo_rst_reg_0),
        .ififo_rst_reg_1(ififo_rst_reg_1),
        .ififo_rst_reg_2(ififo_rst_reg_2),
        .ififo_rst_reg_3(ififo_rst_reg_3),
        .ififo_rst_reg_4(ififo_rst_reg_4),
        .ififo_rst_reg_5(ififo_rst_reg_5),
        .ififo_rst_reg_6(ififo_rst_reg_6),
        .in0(in0),
        .\input_[9].iserdes_dq_.iserdesdq (\input_[9].iserdes_dq_.iserdesdq ),
        .\input_[9].iserdes_dq_.iserdesdq_0 (\input_[9].iserdes_dq_.iserdesdq_0 ),
        .\input_[9].iserdes_dq_.iserdesdq_1 (\input_[9].iserdes_dq_.iserdesdq_1 ),
        .\input_[9].iserdes_dq_.iserdesdq_2 (\input_[9].iserdes_dq_.iserdesdq_2 ),
        .\input_[9].iserdes_dq_.iserdesdq_3 (\input_[9].iserdes_dq_.iserdesdq_3 ),
        .\input_[9].iserdes_dq_.iserdesdq_4 (\input_[9].iserdes_dq_.iserdesdq_4 ),
        .\input_[9].iserdes_dq_.iserdesdq_5 (\input_[9].iserdes_dq_.iserdesdq_5 ),
        .\input_[9].iserdes_dq_.iserdesdq_6 (\input_[9].iserdes_dq_.iserdesdq_6 ),
        .iodelay_ctrl_rdy(iodelay_ctrl_rdy),
        .\mcGo_r_reg[15]_0 (\mcGo_r_reg[15] ),
        .mc_address(mc_address),
        .mc_cas_n(mc_cas_n),
        .mc_cs_n(mc_cs_n),
        .mc_ras_n(mc_ras_n),
        .mc_we_n(mc_we_n),
        .mem_dq_in({mem_dq_in[119:112],mem_dq_in[109:102],mem_dq_in[99:92],mem_dq_in[89],mem_dq_in[87:81],mem_dq_in[39:32],mem_dq_in[29:22],mem_dq_in[19:12],mem_dq_in[9],mem_dq_in[7:1]}),
        .mem_dq_out({mem_dq_out[141:133],mem_dq_out[129:121],mem_dq_out[117:109],mem_dq_out[105],mem_dq_out[103:85],mem_dq_out[83:80],mem_dq_out[77:76],mem_dq_out[71:70],mem_dq_out[67],mem_dq_out[65:64],mem_dq_out[62],mem_dq_out[45:37],mem_dq_out[33:25],mem_dq_out[21:13],mem_dq_out[9],mem_dq_out[7:0]}),
        .mem_dq_ts({mem_dq_ts[141:133],mem_dq_ts[129:121],mem_dq_ts[117:109],mem_dq_ts[105],mem_dq_ts[103:96],mem_dq_ts[45:37],mem_dq_ts[33:25],mem_dq_ts[21:13],mem_dq_ts[9],mem_dq_ts[7:0]}),
        .mem_dqs_in({mem_dqs_in[11:8],mem_dqs_in[3:0]}),
        .mem_out(mem_out),
        .mem_refclk(mem_refclk),
        .mux_address(mux_address),
        .\my_empty_reg[1] (\my_empty_reg[1] ),
        .\my_empty_reg[1]_0 (\my_empty_reg[1]_0 ),
        .\my_empty_reg[1]_1 (\my_empty_reg[1]_1 ),
        .\my_empty_reg[1]_2 (\my_empty_reg[1]_2 ),
        .\my_empty_reg[1]_3 (\my_empty_reg[1]_3 ),
        .\my_empty_reg[1]_4 (\my_empty_reg[1]_4 ),
        .\my_empty_reg[1]_5 (\my_empty_reg[1]_5 ),
        .\my_empty_reg[1]_6 (\my_empty_reg[1]_6 ),
        .\my_empty_reg[1]_7 (\my_empty_reg[1]_7 ),
        .\my_empty_reg[1]_8 (\my_empty_reg[1]_8 ),
        .\my_empty_reg[1]_9 (\my_empty_reg[1]_9 ),
        .\my_empty_reg[7] (\my_empty_reg[7] ),
        .\my_empty_reg[7]_0 (\my_empty_reg[7]_0 ),
        .\my_empty_reg[7]_1 (\my_empty_reg[7]_1 ),
        .\my_empty_reg[7]_10 (\my_empty_reg[7]_10 ),
        .\my_empty_reg[7]_11 (\my_empty_reg[7]_11 ),
        .\my_empty_reg[7]_12 (\my_empty_reg[7]_12 ),
        .\my_empty_reg[7]_13 (\my_empty_reg[7]_13 ),
        .\my_empty_reg[7]_14 (\my_empty_reg[7]_14 ),
        .\my_empty_reg[7]_15 (\my_empty_reg[7]_15 ),
        .\my_empty_reg[7]_16 (\my_empty_reg[7]_16 ),
        .\my_empty_reg[7]_17 (\my_empty_reg[7]_17 ),
        .\my_empty_reg[7]_18 (\my_empty_reg[7]_18 ),
        .\my_empty_reg[7]_19 (\my_empty_reg[7]_19 ),
        .\my_empty_reg[7]_2 (\my_empty_reg[7]_2 ),
        .\my_empty_reg[7]_20 (\my_empty_reg[7]_20 ),
        .\my_empty_reg[7]_21 (\my_empty_reg[7]_21 ),
        .\my_empty_reg[7]_22 (\my_empty_reg[7]_22 ),
        .\my_empty_reg[7]_23 (\my_empty_reg[7]_23 ),
        .\my_empty_reg[7]_24 (\my_empty_reg[7]_24 ),
        .\my_empty_reg[7]_25 (\my_empty_reg[7]_25 ),
        .\my_empty_reg[7]_26 (\my_empty_reg[7]_26 ),
        .\my_empty_reg[7]_27 (\my_empty_reg[7]_27 ),
        .\my_empty_reg[7]_28 (\my_empty_reg[7]_28 ),
        .\my_empty_reg[7]_29 (\my_empty_reg[7]_29 ),
        .\my_empty_reg[7]_3 (\my_empty_reg[7]_3 ),
        .\my_empty_reg[7]_30 (\my_empty_reg[7]_30 ),
        .\my_empty_reg[7]_31 (\my_empty_reg[7]_31 ),
        .\my_empty_reg[7]_32 (\my_empty_reg[7]_32 ),
        .\my_empty_reg[7]_33 (\my_empty_reg[7]_33 ),
        .\my_empty_reg[7]_34 (\my_empty_reg[7]_34 ),
        .\my_empty_reg[7]_35 (\my_empty_reg[7]_35 ),
        .\my_empty_reg[7]_36 (\my_empty_reg[7]_36 ),
        .\my_empty_reg[7]_37 (\my_empty_reg[7]_37 ),
        .\my_empty_reg[7]_38 (\my_empty_reg[7]_38 ),
        .\my_empty_reg[7]_39 (\my_empty_reg[7]_39 ),
        .\my_empty_reg[7]_4 (\my_empty_reg[7]_4 ),
        .\my_empty_reg[7]_40 (\my_empty_reg[7]_40 ),
        .\my_empty_reg[7]_41 (\my_empty_reg[7]_41 ),
        .\my_empty_reg[7]_42 (\my_empty_reg[7]_42 ),
        .\my_empty_reg[7]_43 (\my_empty_reg[7]_43 ),
        .\my_empty_reg[7]_44 (\my_empty_reg[7]_44 ),
        .\my_empty_reg[7]_45 (\my_empty_reg[7]_45 ),
        .\my_empty_reg[7]_46 (\my_empty_reg[7]_46 ),
        .\my_empty_reg[7]_47 (\my_empty_reg[7]_47 ),
        .\my_empty_reg[7]_48 (\my_empty_reg[7]_48 ),
        .\my_empty_reg[7]_49 (\my_empty_reg[7]_49 ),
        .\my_empty_reg[7]_5 (\my_empty_reg[7]_5 ),
        .\my_empty_reg[7]_50 (\my_empty_reg[7]_50 ),
        .\my_empty_reg[7]_51 (\my_empty_reg[7]_51 ),
        .\my_empty_reg[7]_52 (\my_empty_reg[7]_52 ),
        .\my_empty_reg[7]_53 (\my_empty_reg[7]_53 ),
        .\my_empty_reg[7]_54 (\my_empty_reg[7]_54 ),
        .\my_empty_reg[7]_55 (\my_empty_reg[7]_55 ),
        .\my_empty_reg[7]_56 (\my_empty_reg[7]_56 ),
        .\my_empty_reg[7]_57 (\my_empty_reg[7]_57 ),
        .\my_empty_reg[7]_58 (\my_empty_reg[7]_58 ),
        .\my_empty_reg[7]_59 (\my_empty_reg[7]_59 ),
        .\my_empty_reg[7]_6 (\my_empty_reg[7]_6 ),
        .\my_empty_reg[7]_60 (\my_empty_reg[7]_60 ),
        .\my_empty_reg[7]_61 (\my_empty_reg[7]_61 ),
        .\my_empty_reg[7]_62 (\my_empty_reg[7]_62 ),
        .\my_empty_reg[7]_63 (\my_empty_reg[7]_63 ),
        .\my_empty_reg[7]_64 (\my_empty_reg[7]_64 ),
        .\my_empty_reg[7]_65 (\my_empty_reg[7]_65 ),
        .\my_empty_reg[7]_7 (\my_empty_reg[7]_7 ),
        .\my_empty_reg[7]_8 (\my_empty_reg[7]_8 ),
        .\my_empty_reg[7]_9 (\my_empty_reg[7]_9 ),
        .\my_full_reg[3] (\my_full_reg[3] ),
        .\my_full_reg[3]_0 (\my_full_reg[3]_0 ),
        .\my_full_reg[3]_1 (\my_full_reg[3]_1 ),
        .\my_full_reg[3]_2 (\my_full_reg[3]_2 ),
        .\my_full_reg[3]_3 (\my_full_reg[3]_3 ),
        .of_ctl_full_v(of_ctl_full_v),
        .out(out),
        .out_dqs_0(out_dqs_0),
        .out_dqs_1(out_dqs_1),
        .out_dqs_2(out_dqs_2),
        .out_dqs_3(out_dqs_3),
        .out_dqs_4(out_dqs_4),
        .out_dqs_5(out_dqs_5),
        .out_dqs_6(out_dqs_6),
        .out_dqs_7(out_dqs_7),
        .out_fifo(out_fifo),
        .out_fifo_0(out_fifo_0),
        .out_fifo_1(Q),
        .out_fifo_2(out_fifo_1),
        .out_fifo_3(out_fifo_2),
        .out_fifo_i_39(out_fifo_i_39),
        .out_fifo_i_47__8(out_fifo_i_47__8),
        .out_fifo_i_75__0(out_fifo_i_75__0),
        .out_fifo_i_75__1(out_fifo_i_75__1),
        .out_fifo_i_75__2(out_fifo_i_75__2),
        .out_fifo_i_75__3(out_fifo_i_75__3),
        .out_fifo_i_75__5(out_fifo_i_75__5),
        .out_fifo_i_75__6(out_fifo_i_75__6),
        .out_fifo_i_75__7(out_fifo_i_75__7),
        .p_0_out(p_0_out),
        .phy_cmd_wr_en(phy_cmd_wr_en),
        .phy_ctl_wr_i2(phy_ctl_wr_i2),
        .phy_data_wr_en(phy_data_wr_en),
        .phy_dout(phy_dout),
        .phy_if_reset(phy_if_reset),
        .phy_mc_ctl_full(phy_mc_ctl_full),
        .phy_mc_ctl_full_r_reg(phy_mc_ctl_full_r_reg),
        .phy_mc_ctl_full_r_reg_0(data_offset_1_i2),
        .phy_mc_ctl_full_r_reg_1(data_offset_2_i2),
        .phy_mc_data_full(phy_mc_data_full),
        .phy_rddata_en(phy_rddata_en),
        .phy_read_calib(phy_read_calib),
        .phy_write_calib(phy_write_calib),
        .\pi_counter_read_val_reg[5] (\pi_counter_read_val_reg[5] ),
        .\pi_counter_read_val_reg[5]_0 (\pi_counter_read_val_reg[5]_0 ),
        .\pi_dqs_found_lanes_r1_reg[0] (\pi_dqs_found_lanes_r1_reg[0] ),
        .\pi_dqs_found_lanes_r1_reg[0]_0 (\pi_dqs_found_lanes_r1_reg[0]_0 ),
        .\pi_dqs_found_lanes_r1_reg[0]_1 (\pi_dqs_found_lanes_r1_reg[0]_1 ),
        .\pi_dqs_found_lanes_r1_reg[0]_2 (\pi_dqs_found_lanes_r1_reg[0]_2 ),
        .\pi_dqs_found_lanes_r1_reg[10] (\pi_dqs_found_lanes_r1_reg[10] ),
        .\pi_dqs_found_lanes_r1_reg[10]_0 (\pi_dqs_found_lanes_r1_reg[10]_0 ),
        .\pi_dqs_found_lanes_r1_reg[10]_1 (\pi_dqs_found_lanes_r1_reg[10]_1 ),
        .\pi_dqs_found_lanes_r1_reg[10]_2 (\pi_dqs_found_lanes_r1_reg[10]_2 ),
        .\pi_dqs_found_lanes_r1_reg[10]_3 (\pi_dqs_found_lanes_r1_reg[10]_3 ),
        .\pi_dqs_found_lanes_r1_reg[11] (\pi_dqs_found_lanes_r1_reg[11] ),
        .\pi_dqs_found_lanes_r1_reg[11]_0 (\pi_dqs_found_lanes_r1_reg[11]_0 ),
        .\pi_dqs_found_lanes_r1_reg[11]_1 (\pi_dqs_found_lanes_r1_reg[11]_1 ),
        .\pi_dqs_found_lanes_r1_reg[11]_2 (\pi_dqs_found_lanes_r1_reg[11]_2 ),
        .\pi_dqs_found_lanes_r1_reg[11]_3 (\pi_dqs_found_lanes_r1_reg[11]_3 ),
        .\pi_dqs_found_lanes_r1_reg[1] (\pi_dqs_found_lanes_r1_reg[1] ),
        .\pi_dqs_found_lanes_r1_reg[1]_0 (\pi_dqs_found_lanes_r1_reg[1]_0 ),
        .\pi_dqs_found_lanes_r1_reg[1]_1 (\pi_dqs_found_lanes_r1_reg[1]_1 ),
        .\pi_dqs_found_lanes_r1_reg[1]_2 (\pi_dqs_found_lanes_r1_reg[1]_2 ),
        .\pi_dqs_found_lanes_r1_reg[1]_3 (\pi_dqs_found_lanes_r1_reg[1]_3 ),
        .\pi_dqs_found_lanes_r1_reg[2] (\pi_dqs_found_lanes_r1_reg[2] ),
        .\pi_dqs_found_lanes_r1_reg[2]_0 (\pi_dqs_found_lanes_r1_reg[2]_0 ),
        .\pi_dqs_found_lanes_r1_reg[2]_1 (\pi_dqs_found_lanes_r1_reg[2]_1 ),
        .\pi_dqs_found_lanes_r1_reg[2]_2 (\pi_dqs_found_lanes_r1_reg[2]_2 ),
        .\pi_dqs_found_lanes_r1_reg[2]_3 (\pi_dqs_found_lanes_r1_reg[2]_3 ),
        .\pi_dqs_found_lanes_r1_reg[3] (\pi_dqs_found_lanes_r1_reg[3] ),
        .\pi_dqs_found_lanes_r1_reg[3]_0 (\pi_dqs_found_lanes_r1_reg[3]_0 ),
        .\pi_dqs_found_lanes_r1_reg[3]_1 (\pi_dqs_found_lanes_r1_reg[3]_1 ),
        .\pi_dqs_found_lanes_r1_reg[3]_2 (\pi_dqs_found_lanes_r1_reg[3]_2 ),
        .\pi_dqs_found_lanes_r1_reg[3]_3 (\pi_dqs_found_lanes_r1_reg[3]_3 ),
        .\pi_dqs_found_lanes_r1_reg[8] (\pi_dqs_found_lanes_r1_reg[8] ),
        .\pi_dqs_found_lanes_r1_reg[8]_0 (\pi_dqs_found_lanes_r1_reg[8]_0 ),
        .\pi_dqs_found_lanes_r1_reg[8]_1 (\pi_dqs_found_lanes_r1_reg[8]_1 ),
        .\pi_dqs_found_lanes_r1_reg[8]_2 (\pi_dqs_found_lanes_r1_reg[8]_2 ),
        .\pi_dqs_found_lanes_r1_reg[8]_3 (\pi_dqs_found_lanes_r1_reg[8]_3 ),
        .\pi_dqs_found_lanes_r1_reg[9] (\pi_dqs_found_lanes_r1_reg[9] ),
        .\pi_dqs_found_lanes_r1_reg[9]_0 (\pi_dqs_found_lanes_r1_reg[9]_0 ),
        .\pi_dqs_found_lanes_r1_reg[9]_1 (\pi_dqs_found_lanes_r1_reg[9]_1 ),
        .\pi_dqs_found_lanes_r1_reg[9]_2 (\pi_dqs_found_lanes_r1_reg[9]_2 ),
        .\pi_dqs_found_lanes_r1_reg[9]_3 (\pi_dqs_found_lanes_r1_reg[9]_3 ),
        .pll_locked(pll_locked),
        .\po_counter_read_val_reg[0] (\po_counter_read_val_reg[0] ),
        .\po_counter_read_val_reg[0]_0 (\po_counter_read_val_reg[0]_0 ),
        .\po_counter_read_val_reg[1] (\po_counter_read_val_reg[1] ),
        .\po_counter_read_val_reg[2] (\po_counter_read_val_reg[2] ),
        .\po_counter_read_val_reg[3] (\po_counter_read_val_reg[3] ),
        .\po_counter_read_val_reg[4] (\po_counter_read_val_reg[4] ),
        .\po_counter_read_val_reg[5] (\po_counter_read_val_reg[5] ),
        .\po_counter_read_val_reg[6] (\po_counter_read_val_reg[6] ),
        .\po_counter_read_val_reg[7] (\po_counter_read_val_reg[7] ),
        .\po_counter_read_val_reg[8] (\po_counter_read_val_reg[8] ),
        .\po_counter_read_val_reg[8]_0 (\po_counter_read_val_reg[8]_0 ),
        .\po_counter_read_val_reg[8]_1 (\po_counter_read_val_reg[8]_1 ),
        .\po_counter_read_val_reg[8]_10 (\po_counter_read_val_reg[8]_10 ),
        .\po_counter_read_val_reg[8]_11 (\po_counter_read_val_reg[8]_11 ),
        .\po_counter_read_val_reg[8]_12 (\po_counter_read_val_reg[8]_12 ),
        .\po_counter_read_val_reg[8]_13 (\po_counter_read_val_reg[8]_13 ),
        .\po_counter_read_val_reg[8]_14 (\po_counter_read_val_reg[8]_14 ),
        .\po_counter_read_val_reg[8]_15 (\po_counter_read_val_reg[8]_15 ),
        .\po_counter_read_val_reg[8]_16 (\po_counter_read_val_reg[8]_16 ),
        .\po_counter_read_val_reg[8]_17 (\po_counter_read_val_reg[8]_17 ),
        .\po_counter_read_val_reg[8]_18 (\po_counter_read_val_reg[8]_18 ),
        .\po_counter_read_val_reg[8]_19 (\po_counter_read_val_reg[8]_19 ),
        .\po_counter_read_val_reg[8]_2 (\po_counter_read_val_reg[8]_2 ),
        .\po_counter_read_val_reg[8]_20 (\po_counter_read_val_reg[8]_20 ),
        .\po_counter_read_val_reg[8]_21 (\po_counter_read_val_reg[8]_21 ),
        .\po_counter_read_val_reg[8]_22 (\po_counter_read_val_reg[8]_22 ),
        .\po_counter_read_val_reg[8]_23 (\po_counter_read_val_reg[8]_23 ),
        .\po_counter_read_val_reg[8]_24 (\po_counter_read_val_reg[8]_24 ),
        .\po_counter_read_val_reg[8]_25 (\po_counter_read_val_reg[8]_25 ),
        .\po_counter_read_val_reg[8]_26 (\po_counter_read_val_reg[8]_26 ),
        .\po_counter_read_val_reg[8]_27 (\po_counter_read_val_reg[8]_27 ),
        .\po_counter_read_val_reg[8]_28 (\po_counter_read_val_reg[8]_28 ),
        .\po_counter_read_val_reg[8]_29 (\po_counter_read_val_reg[8]_29 ),
        .\po_counter_read_val_reg[8]_3 (\po_counter_read_val_reg[8]_3 ),
        .\po_counter_read_val_reg[8]_30 (\po_counter_read_val_reg[8]_30 ),
        .\po_counter_read_val_reg[8]_31 (\po_counter_read_val_reg[8]_31 ),
        .\po_counter_read_val_reg[8]_4 (\po_counter_read_val_reg[8]_4 ),
        .\po_counter_read_val_reg[8]_5 (\po_counter_read_val_reg[8]_5 ),
        .\po_counter_read_val_reg[8]_6 (\po_counter_read_val_reg[8]_6 ),
        .\po_counter_read_val_reg[8]_7 (\po_counter_read_val_reg[8]_7 ),
        .\po_counter_read_val_reg[8]_8 (\po_counter_read_val_reg[8]_8 ),
        .\po_counter_read_val_reg[8]_9 (\po_counter_read_val_reg[8]_9 ),
        .\po_stg2_wrcal_cnt_reg[2] (\po_stg2_wrcal_cnt_reg[2] ),
        .\po_stg2_wrcal_cnt_reg[2]_0 (\po_stg2_wrcal_cnt_reg[2]_0 ),
        .\po_stg2_wrcal_cnt_reg[2]_1 (\po_stg2_wrcal_cnt_reg[2]_1 ),
        .\po_stg2_wrcal_cnt_reg[2]_10 (\po_stg2_wrcal_cnt_reg[2]_10 ),
        .\po_stg2_wrcal_cnt_reg[2]_11 (\po_stg2_wrcal_cnt_reg[2]_11 ),
        .\po_stg2_wrcal_cnt_reg[2]_12 (\po_stg2_wrcal_cnt_reg[2]_12 ),
        .\po_stg2_wrcal_cnt_reg[2]_13 (\po_stg2_wrcal_cnt_reg[2]_13 ),
        .\po_stg2_wrcal_cnt_reg[2]_14 (\po_stg2_wrcal_cnt_reg[2]_14 ),
        .\po_stg2_wrcal_cnt_reg[2]_15 (\po_stg2_wrcal_cnt_reg[2]_15 ),
        .\po_stg2_wrcal_cnt_reg[2]_16 (\po_stg2_wrcal_cnt_reg[2]_16 ),
        .\po_stg2_wrcal_cnt_reg[2]_17 (\po_stg2_wrcal_cnt_reg[2]_17 ),
        .\po_stg2_wrcal_cnt_reg[2]_18 (\po_stg2_wrcal_cnt_reg[2]_18 ),
        .\po_stg2_wrcal_cnt_reg[2]_19 (\po_stg2_wrcal_cnt_reg[2]_19 ),
        .\po_stg2_wrcal_cnt_reg[2]_2 (\po_stg2_wrcal_cnt_reg[2]_2 ),
        .\po_stg2_wrcal_cnt_reg[2]_20 (\po_stg2_wrcal_cnt_reg[2]_20 ),
        .\po_stg2_wrcal_cnt_reg[2]_21 (\po_stg2_wrcal_cnt_reg[2]_21 ),
        .\po_stg2_wrcal_cnt_reg[2]_22 (\po_stg2_wrcal_cnt_reg[2]_22 ),
        .\po_stg2_wrcal_cnt_reg[2]_23 (\po_stg2_wrcal_cnt_reg[2]_23 ),
        .\po_stg2_wrcal_cnt_reg[2]_24 (\po_stg2_wrcal_cnt_reg[2]_24 ),
        .\po_stg2_wrcal_cnt_reg[2]_25 (\po_stg2_wrcal_cnt_reg[2]_25 ),
        .\po_stg2_wrcal_cnt_reg[2]_26 (\po_stg2_wrcal_cnt_reg[2]_26 ),
        .\po_stg2_wrcal_cnt_reg[2]_27 (\po_stg2_wrcal_cnt_reg[2]_27 ),
        .\po_stg2_wrcal_cnt_reg[2]_28 (\po_stg2_wrcal_cnt_reg[2]_28 ),
        .\po_stg2_wrcal_cnt_reg[2]_29 (\po_stg2_wrcal_cnt_reg[2]_29 ),
        .\po_stg2_wrcal_cnt_reg[2]_3 (\po_stg2_wrcal_cnt_reg[2]_3 ),
        .\po_stg2_wrcal_cnt_reg[2]_30 (\po_stg2_wrcal_cnt_reg[2]_30 ),
        .\po_stg2_wrcal_cnt_reg[2]_31 (\po_stg2_wrcal_cnt_reg[2]_31 ),
        .\po_stg2_wrcal_cnt_reg[2]_32 (\po_stg2_wrcal_cnt_reg[2]_32 ),
        .\po_stg2_wrcal_cnt_reg[2]_33 (\po_stg2_wrcal_cnt_reg[2]_33 ),
        .\po_stg2_wrcal_cnt_reg[2]_34 (\po_stg2_wrcal_cnt_reg[2]_34 ),
        .\po_stg2_wrcal_cnt_reg[2]_35 (\po_stg2_wrcal_cnt_reg[2]_35 ),
        .\po_stg2_wrcal_cnt_reg[2]_36 (\po_stg2_wrcal_cnt_reg[2]_36 ),
        .\po_stg2_wrcal_cnt_reg[2]_37 (\po_stg2_wrcal_cnt_reg[2]_37 ),
        .\po_stg2_wrcal_cnt_reg[2]_38 (\po_stg2_wrcal_cnt_reg[2]_38 ),
        .\po_stg2_wrcal_cnt_reg[2]_39 (\po_stg2_wrcal_cnt_reg[2]_39 ),
        .\po_stg2_wrcal_cnt_reg[2]_4 (\po_stg2_wrcal_cnt_reg[2]_4 ),
        .\po_stg2_wrcal_cnt_reg[2]_40 (\po_stg2_wrcal_cnt_reg[2]_40 ),
        .\po_stg2_wrcal_cnt_reg[2]_41 (\po_stg2_wrcal_cnt_reg[2]_41 ),
        .\po_stg2_wrcal_cnt_reg[2]_42 (\po_stg2_wrcal_cnt_reg[2]_42 ),
        .\po_stg2_wrcal_cnt_reg[2]_43 (\po_stg2_wrcal_cnt_reg[2]_43 ),
        .\po_stg2_wrcal_cnt_reg[2]_44 (\po_stg2_wrcal_cnt_reg[2]_44 ),
        .\po_stg2_wrcal_cnt_reg[2]_45 (\po_stg2_wrcal_cnt_reg[2]_45 ),
        .\po_stg2_wrcal_cnt_reg[2]_46 (\po_stg2_wrcal_cnt_reg[2]_46 ),
        .\po_stg2_wrcal_cnt_reg[2]_47 (\po_stg2_wrcal_cnt_reg[2]_47 ),
        .\po_stg2_wrcal_cnt_reg[2]_48 (\po_stg2_wrcal_cnt_reg[2]_48 ),
        .\po_stg2_wrcal_cnt_reg[2]_49 (\po_stg2_wrcal_cnt_reg[2]_49 ),
        .\po_stg2_wrcal_cnt_reg[2]_5 (\po_stg2_wrcal_cnt_reg[2]_5 ),
        .\po_stg2_wrcal_cnt_reg[2]_50 (\po_stg2_wrcal_cnt_reg[2]_50 ),
        .\po_stg2_wrcal_cnt_reg[2]_51 (\po_stg2_wrcal_cnt_reg[2]_51 ),
        .\po_stg2_wrcal_cnt_reg[2]_52 (\po_stg2_wrcal_cnt_reg[2]_52 ),
        .\po_stg2_wrcal_cnt_reg[2]_53 (\po_stg2_wrcal_cnt_reg[2]_53 ),
        .\po_stg2_wrcal_cnt_reg[2]_54 (\po_stg2_wrcal_cnt_reg[2]_54 ),
        .\po_stg2_wrcal_cnt_reg[2]_55 (\po_stg2_wrcal_cnt_reg[2]_55 ),
        .\po_stg2_wrcal_cnt_reg[2]_56 (\po_stg2_wrcal_cnt_reg[2]_56 ),
        .\po_stg2_wrcal_cnt_reg[2]_57 (\po_stg2_wrcal_cnt_reg[2]_57 ),
        .\po_stg2_wrcal_cnt_reg[2]_58 (\po_stg2_wrcal_cnt_reg[2]_58 ),
        .\po_stg2_wrcal_cnt_reg[2]_59 (\po_stg2_wrcal_cnt_reg[2]_59 ),
        .\po_stg2_wrcal_cnt_reg[2]_6 (\po_stg2_wrcal_cnt_reg[2]_6 ),
        .\po_stg2_wrcal_cnt_reg[2]_60 (\po_stg2_wrcal_cnt_reg[2]_60 ),
        .\po_stg2_wrcal_cnt_reg[2]_61 (\po_stg2_wrcal_cnt_reg[2]_61 ),
        .\po_stg2_wrcal_cnt_reg[2]_7 (\po_stg2_wrcal_cnt_reg[2]_7 ),
        .\po_stg2_wrcal_cnt_reg[2]_8 (\po_stg2_wrcal_cnt_reg[2]_8 ),
        .\po_stg2_wrcal_cnt_reg[2]_9 (\po_stg2_wrcal_cnt_reg[2]_9 ),
        .\rd_mux_sel_r_reg[2] (\rd_mux_sel_r_reg[2] ),
        .\rd_mux_sel_r_reg[2]_0 (\rd_mux_sel_r_reg[2]_0 ),
        .\rd_mux_sel_r_reg[2]_1 (\rd_mux_sel_r_reg[2]_1 ),
        .\rd_mux_sel_r_reg[2]_10 (\rd_mux_sel_r_reg[2]_10 ),
        .\rd_mux_sel_r_reg[2]_100 (\rd_mux_sel_r_reg[2]_100 ),
        .\rd_mux_sel_r_reg[2]_101 (\rd_mux_sel_r_reg[2]_101 ),
        .\rd_mux_sel_r_reg[2]_102 (\rd_mux_sel_r_reg[2]_102 ),
        .\rd_mux_sel_r_reg[2]_103 (\rd_mux_sel_r_reg[2]_103 ),
        .\rd_mux_sel_r_reg[2]_104 (\rd_mux_sel_r_reg[2]_104 ),
        .\rd_mux_sel_r_reg[2]_105 (\rd_mux_sel_r_reg[2]_105 ),
        .\rd_mux_sel_r_reg[2]_106 (\rd_mux_sel_r_reg[2]_106 ),
        .\rd_mux_sel_r_reg[2]_107 (\rd_mux_sel_r_reg[2]_107 ),
        .\rd_mux_sel_r_reg[2]_108 (\rd_mux_sel_r_reg[2]_108 ),
        .\rd_mux_sel_r_reg[2]_109 (\rd_mux_sel_r_reg[2]_109 ),
        .\rd_mux_sel_r_reg[2]_11 (\rd_mux_sel_r_reg[2]_11 ),
        .\rd_mux_sel_r_reg[2]_110 (\rd_mux_sel_r_reg[2]_110 ),
        .\rd_mux_sel_r_reg[2]_111 (\rd_mux_sel_r_reg[2]_111 ),
        .\rd_mux_sel_r_reg[2]_112 (\rd_mux_sel_r_reg[2]_112 ),
        .\rd_mux_sel_r_reg[2]_113 (\rd_mux_sel_r_reg[2]_113 ),
        .\rd_mux_sel_r_reg[2]_114 (\rd_mux_sel_r_reg[2]_114 ),
        .\rd_mux_sel_r_reg[2]_115 (\rd_mux_sel_r_reg[2]_115 ),
        .\rd_mux_sel_r_reg[2]_116 (\rd_mux_sel_r_reg[2]_116 ),
        .\rd_mux_sel_r_reg[2]_117 (\rd_mux_sel_r_reg[2]_117 ),
        .\rd_mux_sel_r_reg[2]_118 (\rd_mux_sel_r_reg[2]_118 ),
        .\rd_mux_sel_r_reg[2]_119 (\rd_mux_sel_r_reg[2]_119 ),
        .\rd_mux_sel_r_reg[2]_12 (\rd_mux_sel_r_reg[2]_12 ),
        .\rd_mux_sel_r_reg[2]_120 (\rd_mux_sel_r_reg[2]_120 ),
        .\rd_mux_sel_r_reg[2]_121 (\rd_mux_sel_r_reg[2]_121 ),
        .\rd_mux_sel_r_reg[2]_122 (\rd_mux_sel_r_reg[2]_122 ),
        .\rd_mux_sel_r_reg[2]_123 (\rd_mux_sel_r_reg[2]_123 ),
        .\rd_mux_sel_r_reg[2]_124 (\rd_mux_sel_r_reg[2]_124 ),
        .\rd_mux_sel_r_reg[2]_125 (\rd_mux_sel_r_reg[2]_125 ),
        .\rd_mux_sel_r_reg[2]_126 (\rd_mux_sel_r_reg[2]_126 ),
        .\rd_mux_sel_r_reg[2]_13 (\rd_mux_sel_r_reg[2]_13 ),
        .\rd_mux_sel_r_reg[2]_14 (\rd_mux_sel_r_reg[2]_14 ),
        .\rd_mux_sel_r_reg[2]_15 (\rd_mux_sel_r_reg[2]_15 ),
        .\rd_mux_sel_r_reg[2]_16 (\rd_mux_sel_r_reg[2]_16 ),
        .\rd_mux_sel_r_reg[2]_17 (\rd_mux_sel_r_reg[2]_17 ),
        .\rd_mux_sel_r_reg[2]_18 (\rd_mux_sel_r_reg[2]_18 ),
        .\rd_mux_sel_r_reg[2]_19 (\rd_mux_sel_r_reg[2]_19 ),
        .\rd_mux_sel_r_reg[2]_2 (\rd_mux_sel_r_reg[2]_2 ),
        .\rd_mux_sel_r_reg[2]_20 (\rd_mux_sel_r_reg[2]_20 ),
        .\rd_mux_sel_r_reg[2]_21 (\rd_mux_sel_r_reg[2]_21 ),
        .\rd_mux_sel_r_reg[2]_22 (\rd_mux_sel_r_reg[2]_22 ),
        .\rd_mux_sel_r_reg[2]_23 (\rd_mux_sel_r_reg[2]_23 ),
        .\rd_mux_sel_r_reg[2]_24 (\rd_mux_sel_r_reg[2]_24 ),
        .\rd_mux_sel_r_reg[2]_25 (\rd_mux_sel_r_reg[2]_25 ),
        .\rd_mux_sel_r_reg[2]_26 (\rd_mux_sel_r_reg[2]_26 ),
        .\rd_mux_sel_r_reg[2]_27 (\rd_mux_sel_r_reg[2]_27 ),
        .\rd_mux_sel_r_reg[2]_28 (\rd_mux_sel_r_reg[2]_28 ),
        .\rd_mux_sel_r_reg[2]_29 (\rd_mux_sel_r_reg[2]_29 ),
        .\rd_mux_sel_r_reg[2]_3 (\rd_mux_sel_r_reg[2]_3 ),
        .\rd_mux_sel_r_reg[2]_30 (\rd_mux_sel_r_reg[2]_30 ),
        .\rd_mux_sel_r_reg[2]_31 (\rd_mux_sel_r_reg[2]_31 ),
        .\rd_mux_sel_r_reg[2]_32 (\rd_mux_sel_r_reg[2]_32 ),
        .\rd_mux_sel_r_reg[2]_33 (\rd_mux_sel_r_reg[2]_33 ),
        .\rd_mux_sel_r_reg[2]_34 (\rd_mux_sel_r_reg[2]_34 ),
        .\rd_mux_sel_r_reg[2]_35 (\rd_mux_sel_r_reg[2]_35 ),
        .\rd_mux_sel_r_reg[2]_36 (\rd_mux_sel_r_reg[2]_36 ),
        .\rd_mux_sel_r_reg[2]_37 (\rd_mux_sel_r_reg[2]_37 ),
        .\rd_mux_sel_r_reg[2]_38 (\rd_mux_sel_r_reg[2]_38 ),
        .\rd_mux_sel_r_reg[2]_39 (\rd_mux_sel_r_reg[2]_39 ),
        .\rd_mux_sel_r_reg[2]_4 (\rd_mux_sel_r_reg[2]_4 ),
        .\rd_mux_sel_r_reg[2]_40 (\rd_mux_sel_r_reg[2]_40 ),
        .\rd_mux_sel_r_reg[2]_41 (\rd_mux_sel_r_reg[2]_41 ),
        .\rd_mux_sel_r_reg[2]_42 (\rd_mux_sel_r_reg[2]_42 ),
        .\rd_mux_sel_r_reg[2]_43 (\rd_mux_sel_r_reg[2]_43 ),
        .\rd_mux_sel_r_reg[2]_44 (\rd_mux_sel_r_reg[2]_44 ),
        .\rd_mux_sel_r_reg[2]_45 (\rd_mux_sel_r_reg[2]_45 ),
        .\rd_mux_sel_r_reg[2]_46 (\rd_mux_sel_r_reg[2]_46 ),
        .\rd_mux_sel_r_reg[2]_47 (\rd_mux_sel_r_reg[2]_47 ),
        .\rd_mux_sel_r_reg[2]_48 (\rd_mux_sel_r_reg[2]_48 ),
        .\rd_mux_sel_r_reg[2]_49 (\rd_mux_sel_r_reg[2]_49 ),
        .\rd_mux_sel_r_reg[2]_5 (\rd_mux_sel_r_reg[2]_5 ),
        .\rd_mux_sel_r_reg[2]_50 (\rd_mux_sel_r_reg[2]_50 ),
        .\rd_mux_sel_r_reg[2]_51 (\rd_mux_sel_r_reg[2]_51 ),
        .\rd_mux_sel_r_reg[2]_52 (\rd_mux_sel_r_reg[2]_52 ),
        .\rd_mux_sel_r_reg[2]_53 (\rd_mux_sel_r_reg[2]_53 ),
        .\rd_mux_sel_r_reg[2]_54 (\rd_mux_sel_r_reg[2]_54 ),
        .\rd_mux_sel_r_reg[2]_55 (\rd_mux_sel_r_reg[2]_55 ),
        .\rd_mux_sel_r_reg[2]_56 (\rd_mux_sel_r_reg[2]_56 ),
        .\rd_mux_sel_r_reg[2]_57 (\rd_mux_sel_r_reg[2]_57 ),
        .\rd_mux_sel_r_reg[2]_58 (\rd_mux_sel_r_reg[2]_58 ),
        .\rd_mux_sel_r_reg[2]_59 (\rd_mux_sel_r_reg[2]_59 ),
        .\rd_mux_sel_r_reg[2]_6 (\rd_mux_sel_r_reg[2]_6 ),
        .\rd_mux_sel_r_reg[2]_60 (\rd_mux_sel_r_reg[2]_60 ),
        .\rd_mux_sel_r_reg[2]_61 (\rd_mux_sel_r_reg[2]_61 ),
        .\rd_mux_sel_r_reg[2]_62 (\rd_mux_sel_r_reg[2]_62 ),
        .\rd_mux_sel_r_reg[2]_63 (\rd_mux_sel_r_reg[2]_63 ),
        .\rd_mux_sel_r_reg[2]_64 (\rd_mux_sel_r_reg[2]_64 ),
        .\rd_mux_sel_r_reg[2]_65 (\rd_mux_sel_r_reg[2]_65 ),
        .\rd_mux_sel_r_reg[2]_66 (\rd_mux_sel_r_reg[2]_66 ),
        .\rd_mux_sel_r_reg[2]_67 (\rd_mux_sel_r_reg[2]_67 ),
        .\rd_mux_sel_r_reg[2]_68 (\rd_mux_sel_r_reg[2]_68 ),
        .\rd_mux_sel_r_reg[2]_69 (\rd_mux_sel_r_reg[2]_69 ),
        .\rd_mux_sel_r_reg[2]_7 (\rd_mux_sel_r_reg[2]_7 ),
        .\rd_mux_sel_r_reg[2]_70 (\rd_mux_sel_r_reg[2]_70 ),
        .\rd_mux_sel_r_reg[2]_71 (\rd_mux_sel_r_reg[2]_71 ),
        .\rd_mux_sel_r_reg[2]_72 (\rd_mux_sel_r_reg[2]_72 ),
        .\rd_mux_sel_r_reg[2]_73 (\rd_mux_sel_r_reg[2]_73 ),
        .\rd_mux_sel_r_reg[2]_74 (\rd_mux_sel_r_reg[2]_74 ),
        .\rd_mux_sel_r_reg[2]_75 (\rd_mux_sel_r_reg[2]_75 ),
        .\rd_mux_sel_r_reg[2]_76 (\rd_mux_sel_r_reg[2]_76 ),
        .\rd_mux_sel_r_reg[2]_77 (\rd_mux_sel_r_reg[2]_77 ),
        .\rd_mux_sel_r_reg[2]_78 (\rd_mux_sel_r_reg[2]_78 ),
        .\rd_mux_sel_r_reg[2]_79 (\rd_mux_sel_r_reg[2]_79 ),
        .\rd_mux_sel_r_reg[2]_8 (\rd_mux_sel_r_reg[2]_8 ),
        .\rd_mux_sel_r_reg[2]_80 (\rd_mux_sel_r_reg[2]_80 ),
        .\rd_mux_sel_r_reg[2]_81 (\rd_mux_sel_r_reg[2]_81 ),
        .\rd_mux_sel_r_reg[2]_82 (\rd_mux_sel_r_reg[2]_82 ),
        .\rd_mux_sel_r_reg[2]_83 (\rd_mux_sel_r_reg[2]_83 ),
        .\rd_mux_sel_r_reg[2]_84 (\rd_mux_sel_r_reg[2]_84 ),
        .\rd_mux_sel_r_reg[2]_85 (\rd_mux_sel_r_reg[2]_85 ),
        .\rd_mux_sel_r_reg[2]_86 (\rd_mux_sel_r_reg[2]_86 ),
        .\rd_mux_sel_r_reg[2]_87 (\rd_mux_sel_r_reg[2]_87 ),
        .\rd_mux_sel_r_reg[2]_88 (\rd_mux_sel_r_reg[2]_88 ),
        .\rd_mux_sel_r_reg[2]_89 (\rd_mux_sel_r_reg[2]_89 ),
        .\rd_mux_sel_r_reg[2]_9 (\rd_mux_sel_r_reg[2]_9 ),
        .\rd_mux_sel_r_reg[2]_90 (\rd_mux_sel_r_reg[2]_90 ),
        .\rd_mux_sel_r_reg[2]_91 (\rd_mux_sel_r_reg[2]_91 ),
        .\rd_mux_sel_r_reg[2]_92 (\rd_mux_sel_r_reg[2]_92 ),
        .\rd_mux_sel_r_reg[2]_93 (\rd_mux_sel_r_reg[2]_93 ),
        .\rd_mux_sel_r_reg[2]_94 (\rd_mux_sel_r_reg[2]_94 ),
        .\rd_mux_sel_r_reg[2]_95 (\rd_mux_sel_r_reg[2]_95 ),
        .\rd_mux_sel_r_reg[2]_96 (\rd_mux_sel_r_reg[2]_96 ),
        .\rd_mux_sel_r_reg[2]_97 (\rd_mux_sel_r_reg[2]_97 ),
        .\rd_mux_sel_r_reg[2]_98 (\rd_mux_sel_r_reg[2]_98 ),
        .\rd_mux_sel_r_reg[2]_99 (\rd_mux_sel_r_reg[2]_99 ),
        .\rd_ptr_reg[3] (\rd_ptr_reg[3] ),
        .\rd_ptr_reg[3]_0 (\rd_ptr_reg[3]_0 ),
        .\rd_ptr_reg[3]_1 (\rd_ptr_reg[3]_1 ),
        .\rd_ptr_reg[3]_2 (\rd_ptr_reg[3]_2 ),
        .\rd_ptr_reg[3]_3 (\rd_ptr_reg[3]_3 ),
        .\rd_ptr_reg[3]_4 (\rd_ptr_reg[3]_4 ),
        .\rd_ptr_reg[3]_5 (\rd_ptr_reg[3]_5 ),
        .\rd_ptr_reg[3]_6 (\rd_ptr_reg[3]_6 ),
        .\rd_ptr_reg[3]_7 (\rd_ptr_reg[3]_7 ),
        .\rd_ptr_reg[3]_8 (\rd_ptr_reg[3]_8 ),
        .\rd_ptr_reg[3]_9 (\rd_ptr_reg[3]_9 ),
        .rst_tmp(rst_tmp),
        .\rstdiv2_sync_r_reg[11] (\rstdiv2_sync_r_reg[11] ),
        .sync_pulse(sync_pulse),
        .ts_dqs_0(ts_dqs_0),
        .ts_dqs_1(ts_dqs_1),
        .ts_dqs_2(ts_dqs_2),
        .ts_dqs_3(ts_dqs_3),
        .ts_dqs_4(ts_dqs_4),
        .ts_dqs_5(ts_dqs_5),
        .ts_dqs_6(ts_dqs_6),
        .ts_dqs_7(ts_dqs_7));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    u_ras_n_obuf
       (.I(mem_dq_out[70]),
        .O(ddr3_ras_n));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* CAPACITANCE = "DONT_CARE" *) 
  OBUF #(
    .IOSTANDARD("DEFAULT")) 
    u_we_n_obuf
       (.I(mem_dq_out[71]),
        .O(ddr3_we_n));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_of_pre_fifo" *) 
module mig_mig_7series_v4_2_ddr_of_pre_fifo
   (SR,
    \rd_ptr_timing_reg[0]_0 );
  input [0:0]SR;
  input \rd_ptr_timing_reg[0]_0 ;

  wire [0:0]SR;
  (* MAX_FANOUT = "50" *) (* RTL_KEEP = "true" *) (* RTL_MAX_FANOUT = "found" *) 
  (* syn_maxfan = "10" *) wire [2:0]rd_ptr_timing;
  wire \rd_ptr_timing_reg[0]_0 ;
  (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) wire wr_en;
  (* MAX_FANOUT = "50" *) (* RTL_KEEP = "true" *) (* RTL_MAX_FANOUT = "found" *) 
  (* syn_maxfan = "10" *) wire [2:0]wr_ptr_timing;

  LUT1 #(
    .INIT(2'h2)) 
    i_0
       (.I0(1'b0),
        .O(wr_en));
  (* KEEP = "yes" *) 
  (* RTL_MAX_FANOUT = "found" *) 
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_timing_reg[0] 
       (.C(\rd_ptr_timing_reg[0]_0 ),
        .CE(1'b0),
        .D(1'b1),
        .Q(rd_ptr_timing[0]),
        .R(SR));
  (* KEEP = "yes" *) 
  (* RTL_MAX_FANOUT = "found" *) 
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_timing_reg[1] 
       (.C(\rd_ptr_timing_reg[0]_0 ),
        .CE(1'b0),
        .D(1'b0),
        .Q(rd_ptr_timing[1]),
        .R(SR));
  (* KEEP = "yes" *) 
  (* RTL_MAX_FANOUT = "found" *) 
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_timing_reg[2] 
       (.C(\rd_ptr_timing_reg[0]_0 ),
        .CE(1'b0),
        .D(1'b0),
        .Q(rd_ptr_timing[2]),
        .R(SR));
  (* KEEP = "yes" *) 
  (* RTL_MAX_FANOUT = "found" *) 
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_timing_reg[0] 
       (.C(\rd_ptr_timing_reg[0]_0 ),
        .CE(1'b0),
        .D(1'b1),
        .Q(wr_ptr_timing[0]),
        .R(SR));
  (* KEEP = "yes" *) 
  (* RTL_MAX_FANOUT = "found" *) 
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_timing_reg[1] 
       (.C(\rd_ptr_timing_reg[0]_0 ),
        .CE(1'b0),
        .D(1'b0),
        .Q(wr_ptr_timing[1]),
        .R(SR));
  (* KEEP = "yes" *) 
  (* RTL_MAX_FANOUT = "found" *) 
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_timing_reg[2] 
       (.C(\rd_ptr_timing_reg[0]_0 ),
        .CE(1'b0),
        .D(1'b0),
        .Q(wr_ptr_timing[2]),
        .R(SR));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_of_pre_fifo" *) 
module mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized0
   (SR,
    \rd_ptr_timing_reg[0]_0 );
  input [0:0]SR;
  input \rd_ptr_timing_reg[0]_0 ;

  wire [0:0]SR;
  (* MAX_FANOUT = "50" *) (* RTL_KEEP = "true" *) (* RTL_MAX_FANOUT = "found" *) 
  (* syn_maxfan = "10" *) wire [2:0]rd_ptr_timing;
  wire \rd_ptr_timing_reg[0]_0 ;
  (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) wire wr_en;
  (* MAX_FANOUT = "50" *) (* RTL_KEEP = "true" *) (* RTL_MAX_FANOUT = "found" *) 
  (* syn_maxfan = "10" *) wire [2:0]wr_ptr_timing;

  LUT1 #(
    .INIT(2'h2)) 
    i_0
       (.I0(1'b0),
        .O(wr_en));
  (* KEEP = "yes" *) 
  (* RTL_MAX_FANOUT = "found" *) 
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_timing_reg[0] 
       (.C(\rd_ptr_timing_reg[0]_0 ),
        .CE(1'b0),
        .D(1'b1),
        .Q(rd_ptr_timing[0]),
        .R(SR));
  (* KEEP = "yes" *) 
  (* RTL_MAX_FANOUT = "found" *) 
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_timing_reg[1] 
       (.C(\rd_ptr_timing_reg[0]_0 ),
        .CE(1'b0),
        .D(1'b0),
        .Q(rd_ptr_timing[1]),
        .R(SR));
  (* KEEP = "yes" *) 
  (* RTL_MAX_FANOUT = "found" *) 
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_timing_reg[2] 
       (.C(\rd_ptr_timing_reg[0]_0 ),
        .CE(1'b0),
        .D(1'b0),
        .Q(rd_ptr_timing[2]),
        .R(SR));
  (* KEEP = "yes" *) 
  (* RTL_MAX_FANOUT = "found" *) 
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_timing_reg[0] 
       (.C(\rd_ptr_timing_reg[0]_0 ),
        .CE(1'b0),
        .D(1'b1),
        .Q(wr_ptr_timing[0]),
        .R(SR));
  (* KEEP = "yes" *) 
  (* RTL_MAX_FANOUT = "found" *) 
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_timing_reg[1] 
       (.C(\rd_ptr_timing_reg[0]_0 ),
        .CE(1'b0),
        .D(1'b0),
        .Q(wr_ptr_timing[1]),
        .R(SR));
  (* KEEP = "yes" *) 
  (* RTL_MAX_FANOUT = "found" *) 
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_timing_reg[2] 
       (.C(\rd_ptr_timing_reg[0]_0 ),
        .CE(1'b0),
        .D(1'b0),
        .Q(wr_ptr_timing[2]),
        .R(SR));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_of_pre_fifo" *) 
module mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized0_12
   (SR,
    \rd_ptr_timing_reg[0]_0 );
  input [0:0]SR;
  input \rd_ptr_timing_reg[0]_0 ;

  wire [0:0]SR;
  (* MAX_FANOUT = "50" *) (* RTL_KEEP = "true" *) (* RTL_MAX_FANOUT = "found" *) 
  (* syn_maxfan = "10" *) wire [2:0]rd_ptr_timing;
  wire \rd_ptr_timing_reg[0]_0 ;
  (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) wire wr_en;
  (* MAX_FANOUT = "50" *) (* RTL_KEEP = "true" *) (* RTL_MAX_FANOUT = "found" *) 
  (* syn_maxfan = "10" *) wire [2:0]wr_ptr_timing;

  LUT1 #(
    .INIT(2'h2)) 
    i_0
       (.I0(1'b0),
        .O(wr_en));
  (* KEEP = "yes" *) 
  (* RTL_MAX_FANOUT = "found" *) 
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_timing_reg[0] 
       (.C(\rd_ptr_timing_reg[0]_0 ),
        .CE(1'b0),
        .D(1'b1),
        .Q(rd_ptr_timing[0]),
        .R(SR));
  (* KEEP = "yes" *) 
  (* RTL_MAX_FANOUT = "found" *) 
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_timing_reg[1] 
       (.C(\rd_ptr_timing_reg[0]_0 ),
        .CE(1'b0),
        .D(1'b0),
        .Q(rd_ptr_timing[1]),
        .R(SR));
  (* KEEP = "yes" *) 
  (* RTL_MAX_FANOUT = "found" *) 
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_timing_reg[2] 
       (.C(\rd_ptr_timing_reg[0]_0 ),
        .CE(1'b0),
        .D(1'b0),
        .Q(rd_ptr_timing[2]),
        .R(SR));
  (* KEEP = "yes" *) 
  (* RTL_MAX_FANOUT = "found" *) 
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_timing_reg[0] 
       (.C(\rd_ptr_timing_reg[0]_0 ),
        .CE(1'b0),
        .D(1'b1),
        .Q(wr_ptr_timing[0]),
        .R(SR));
  (* KEEP = "yes" *) 
  (* RTL_MAX_FANOUT = "found" *) 
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_timing_reg[1] 
       (.C(\rd_ptr_timing_reg[0]_0 ),
        .CE(1'b0),
        .D(1'b0),
        .Q(wr_ptr_timing[1]),
        .R(SR));
  (* KEEP = "yes" *) 
  (* RTL_MAX_FANOUT = "found" *) 
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_timing_reg[2] 
       (.C(\rd_ptr_timing_reg[0]_0 ),
        .CE(1'b0),
        .D(1'b0),
        .Q(wr_ptr_timing[2]),
        .R(SR));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_of_pre_fifo" *) 
module mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1
   (\my_empty_reg[1]_0 ,
    \my_empty_reg[1]_1 ,
    D0,
    D1,
    \rd_ptr_reg[3]_0 ,
    Q,
    ofifo_rst,
    \entry_cnt_reg[4]_0 ,
    \my_empty_reg[7]_0 ,
    phy_data_wr_en,
    out_fifo,
    out_fifo_0,
    out_fifo_1,
    out_fifo_i_75__3);
  output \my_empty_reg[1]_0 ;
  output \my_empty_reg[1]_1 ;
  output [7:0]D0;
  output [7:0]D1;
  output [63:0]\rd_ptr_reg[3]_0 ;
  output [2:0]Q;
  input ofifo_rst;
  input \entry_cnt_reg[4]_0 ;
  input \my_empty_reg[7]_0 ;
  input phy_data_wr_en;
  input out_fifo;
  input [7:0]out_fifo_0;
  input out_fifo_1;
  input [71:0]out_fifo_i_75__3;

  wire [7:0]D0;
  wire [7:0]D1;
  wire [2:0]Q;
  wire entry_cnt10_out__0;
  wire \entry_cnt[0]_i_1__6_n_0 ;
  wire \entry_cnt[1]_i_1__6_n_0 ;
  wire \entry_cnt[2]_i_1__6_n_0 ;
  wire \entry_cnt[3]_i_1__6_n_0 ;
  wire \entry_cnt[4]_i_1__6_n_0 ;
  wire \entry_cnt[4]_i_2__6_n_0 ;
  wire \entry_cnt_reg[4]_0 ;
  wire \entry_cnt_reg_n_0_[0] ;
  wire \entry_cnt_reg_n_0_[1] ;
  wire mem_reg_0_15_0_5_n_0;
  wire mem_reg_0_15_0_5_n_1;
  wire mem_reg_0_15_0_5_n_2;
  wire mem_reg_0_15_0_5_n_3;
  wire mem_reg_0_15_0_5_n_4;
  wire mem_reg_0_15_0_5_n_5;
  wire mem_reg_0_15_12_17_n_0;
  wire mem_reg_0_15_12_17_n_1;
  wire mem_reg_0_15_12_17_n_2;
  wire mem_reg_0_15_12_17_n_3;
  wire mem_reg_0_15_6_11_n_0;
  wire mem_reg_0_15_6_11_n_1;
  wire mem_reg_0_15_6_11_n_2;
  wire mem_reg_0_15_6_11_n_3;
  wire mem_reg_0_15_6_11_n_4;
  wire mem_reg_0_15_6_11_n_5;
  wire my_empty0;
  wire \my_empty[1]_i_1__7_n_0 ;
  wire \my_empty[7]_i_1__7_n_0 ;
  wire \my_empty[7]_i_3__7_n_0 ;
  wire \my_empty[7]_i_4__7_n_0 ;
  wire \my_empty_reg[1]_0 ;
  wire \my_empty_reg[1]_1 ;
  wire \my_empty_reg[7]_0 ;
  wire \my_empty_reg_n_0_[7] ;
  wire my_full0;
  wire \my_full[4]_i_1__7_n_0 ;
  wire \my_full[4]_i_3__7_n_0 ;
  wire \my_full[4]_i_4__7_n_0 ;
  wire \my_full_reg_n_0_[4] ;
  wire [3:0]nxt_rd_ptr;
  wire [3:0]nxt_wr_ptr;
  wire ofifo_rst;
  wire out_fifo;
  wire [7:0]out_fifo_0;
  wire out_fifo_1;
  wire [71:0]out_fifo_i_75__3;
  wire phy_data_wr_en;
  wire [63:0]\rd_ptr_reg[3]_0 ;
  wire \rd_ptr_reg_n_0_[0] ;
  wire \rd_ptr_reg_n_0_[1] ;
  wire \rd_ptr_reg_n_0_[2] ;
  wire \rd_ptr_reg_n_0_[3] ;
  wire [3:0]rd_ptr_timing;
  wire \rd_ptr_timing[3]_i_1__7_n_0 ;
  (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) wire wr_en;
  wire [3:0]wr_ptr;
  wire wr_ptr0;
  wire [3:0]wr_ptr_timing;
  wire [1:0]NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED;

  (* SOFT_HLUTNM = "soft_lutpair1126" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \entry_cnt[0]_i_1__6 
       (.I0(\entry_cnt_reg_n_0_[0] ),
        .O(\entry_cnt[0]_i_1__6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1125" *) 
  LUT5 #(
    .INIT(32'hAA6A5595)) 
    \entry_cnt[1]_i_1__6 
       (.I0(\entry_cnt_reg_n_0_[0] ),
        .I1(\my_empty_reg[7]_0 ),
        .I2(phy_data_wr_en),
        .I3(\my_full_reg_n_0_[4] ),
        .I4(\entry_cnt_reg_n_0_[1] ),
        .O(\entry_cnt[1]_i_1__6_n_0 ));
  LUT6 #(
    .INIT(64'hFF7F0080AAEA5515)) 
    \entry_cnt[2]_i_1__6 
       (.I0(\entry_cnt_reg_n_0_[0] ),
        .I1(\my_empty_reg[7]_0 ),
        .I2(phy_data_wr_en),
        .I3(\my_full_reg_n_0_[4] ),
        .I4(Q[0]),
        .I5(\entry_cnt_reg_n_0_[1] ),
        .O(\entry_cnt[2]_i_1__6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1126" *) 
  LUT5 #(
    .INIT(32'h7F80FE01)) 
    \entry_cnt[3]_i_1__6 
       (.I0(entry_cnt10_out__0),
        .I1(\entry_cnt_reg_n_0_[0] ),
        .I2(\entry_cnt_reg_n_0_[1] ),
        .I3(Q[1]),
        .I4(Q[0]),
        .O(\entry_cnt[3]_i_1__6_n_0 ));
  LUT4 #(
    .INIT(16'h5003)) 
    \entry_cnt[4]_i_1__6 
       (.I0(\my_full_reg_n_0_[4] ),
        .I1(\my_empty_reg_n_0_[7] ),
        .I2(\my_empty_reg[7]_0 ),
        .I3(phy_data_wr_en),
        .O(\entry_cnt[4]_i_1__6_n_0 ));
  LUT6 #(
    .INIT(64'h7FFF8000FFFE0001)) 
    \entry_cnt[4]_i_2__6 
       (.I0(\entry_cnt_reg_n_0_[1] ),
        .I1(\entry_cnt_reg_n_0_[0] ),
        .I2(entry_cnt10_out__0),
        .I3(Q[0]),
        .I4(Q[2]),
        .I5(Q[1]),
        .O(\entry_cnt[4]_i_2__6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1125" *) 
  LUT3 #(
    .INIT(8'h08)) 
    \entry_cnt[4]_i_3__6 
       (.I0(\my_empty_reg[7]_0 ),
        .I1(phy_data_wr_en),
        .I2(\my_full_reg_n_0_[4] ),
        .O(entry_cnt10_out__0));
  FDRE \entry_cnt_reg[0] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(\entry_cnt[4]_i_1__6_n_0 ),
        .D(\entry_cnt[0]_i_1__6_n_0 ),
        .Q(\entry_cnt_reg_n_0_[0] ),
        .R(ofifo_rst));
  FDRE \entry_cnt_reg[1] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(\entry_cnt[4]_i_1__6_n_0 ),
        .D(\entry_cnt[1]_i_1__6_n_0 ),
        .Q(\entry_cnt_reg_n_0_[1] ),
        .R(ofifo_rst));
  FDRE \entry_cnt_reg[2] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(\entry_cnt[4]_i_1__6_n_0 ),
        .D(\entry_cnt[2]_i_1__6_n_0 ),
        .Q(Q[0]),
        .R(ofifo_rst));
  FDRE \entry_cnt_reg[3] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(\entry_cnt[4]_i_1__6_n_0 ),
        .D(\entry_cnt[3]_i_1__6_n_0 ),
        .Q(Q[1]),
        .R(ofifo_rst));
  FDRE \entry_cnt_reg[4] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(\entry_cnt[4]_i_1__6_n_0 ),
        .D(\entry_cnt[4]_i_2__6_n_0 ),
        .Q(Q[2]),
        .R(ofifo_rst));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "0" *) 
  (* ram_slice_end = "5" *) 
  RAM32M mem_reg_0_15_0_5
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA({1'b0,1'b0}),
        .DIB({1'b0,1'b0}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA({mem_reg_0_15_0_5_n_0,mem_reg_0_15_0_5_n_1}),
        .DOB({mem_reg_0_15_0_5_n_2,mem_reg_0_15_0_5_n_3}),
        .DOC({mem_reg_0_15_0_5_n_4,mem_reg_0_15_0_5_n_5}),
        .DOD(NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED[1:0]),
        .WCLK(\entry_cnt_reg[4]_0 ),
        .WE(wr_en));
  LUT4 #(
    .INIT(16'h2700)) 
    mem_reg_0_15_0_5_i_1__6
       (.I0(\my_empty_reg[7]_0 ),
        .I1(\my_full_reg_n_0_[4] ),
        .I2(\my_empty_reg[1]_1 ),
        .I3(phy_data_wr_en),
        .O(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "12" *) 
  (* ram_slice_end = "17" *) 
  RAM32M mem_reg_0_15_12_17
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__3[5:4]),
        .DIB(out_fifo_i_75__3[7:6]),
        .DIC(out_fifo_i_75__3[9:8]),
        .DID({1'b0,1'b0}),
        .DOA({mem_reg_0_15_12_17_n_0,mem_reg_0_15_12_17_n_1}),
        .DOB({mem_reg_0_15_12_17_n_2,mem_reg_0_15_12_17_n_3}),
        .DOC(\rd_ptr_reg[3]_0 [1:0]),
        .DOD(NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED[1:0]),
        .WCLK(\entry_cnt_reg[4]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "18" *) 
  (* ram_slice_end = "23" *) 
  RAM32M mem_reg_0_15_18_23
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__3[11:10]),
        .DIB(out_fifo_i_75__3[13:12]),
        .DIC(out_fifo_i_75__3[15:14]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [3:2]),
        .DOB(\rd_ptr_reg[3]_0 [5:4]),
        .DOC(\rd_ptr_reg[3]_0 [7:6]),
        .DOD(NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED[1:0]),
        .WCLK(\entry_cnt_reg[4]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "24" *) 
  (* ram_slice_end = "29" *) 
  RAM32M mem_reg_0_15_24_29
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__3[17:16]),
        .DIB(out_fifo_i_75__3[19:18]),
        .DIC(out_fifo_i_75__3[21:20]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [9:8]),
        .DOB(\rd_ptr_reg[3]_0 [11:10]),
        .DOC(\rd_ptr_reg[3]_0 [13:12]),
        .DOD(NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED[1:0]),
        .WCLK(\entry_cnt_reg[4]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "30" *) 
  (* ram_slice_end = "35" *) 
  RAM32M mem_reg_0_15_30_35
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__3[23:22]),
        .DIB(out_fifo_i_75__3[25:24]),
        .DIC(out_fifo_i_75__3[27:26]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [15:14]),
        .DOB(\rd_ptr_reg[3]_0 [17:16]),
        .DOC(\rd_ptr_reg[3]_0 [19:18]),
        .DOD(NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED[1:0]),
        .WCLK(\entry_cnt_reg[4]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "36" *) 
  (* ram_slice_end = "41" *) 
  RAM32M mem_reg_0_15_36_41
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__3[29:28]),
        .DIB(out_fifo_i_75__3[31:30]),
        .DIC(out_fifo_i_75__3[33:32]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [21:20]),
        .DOB(\rd_ptr_reg[3]_0 [23:22]),
        .DOC(\rd_ptr_reg[3]_0 [25:24]),
        .DOD(NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED[1:0]),
        .WCLK(\entry_cnt_reg[4]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "42" *) 
  (* ram_slice_end = "47" *) 
  RAM32M mem_reg_0_15_42_47
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__3[35:34]),
        .DIB(out_fifo_i_75__3[37:36]),
        .DIC(out_fifo_i_75__3[39:38]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [27:26]),
        .DOB(\rd_ptr_reg[3]_0 [29:28]),
        .DOC(\rd_ptr_reg[3]_0 [31:30]),
        .DOD(NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED[1:0]),
        .WCLK(\entry_cnt_reg[4]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "48" *) 
  (* ram_slice_end = "53" *) 
  RAM32M mem_reg_0_15_48_53
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__3[41:40]),
        .DIB(out_fifo_i_75__3[43:42]),
        .DIC(out_fifo_i_75__3[45:44]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [33:32]),
        .DOB(\rd_ptr_reg[3]_0 [35:34]),
        .DOC(\rd_ptr_reg[3]_0 [37:36]),
        .DOD(NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED[1:0]),
        .WCLK(\entry_cnt_reg[4]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "54" *) 
  (* ram_slice_end = "59" *) 
  RAM32M mem_reg_0_15_54_59
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__3[47:46]),
        .DIB(out_fifo_i_75__3[49:48]),
        .DIC(out_fifo_i_75__3[51:50]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [39:38]),
        .DOB(\rd_ptr_reg[3]_0 [41:40]),
        .DOC(\rd_ptr_reg[3]_0 [43:42]),
        .DOD(NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED[1:0]),
        .WCLK(\entry_cnt_reg[4]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "60" *) 
  (* ram_slice_end = "65" *) 
  RAM32M mem_reg_0_15_60_65
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__3[53:52]),
        .DIB(out_fifo_i_75__3[55:54]),
        .DIC(out_fifo_i_75__3[57:56]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [45:44]),
        .DOB(\rd_ptr_reg[3]_0 [47:46]),
        .DOC(\rd_ptr_reg[3]_0 [49:48]),
        .DOD(NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED[1:0]),
        .WCLK(\entry_cnt_reg[4]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "66" *) 
  (* ram_slice_end = "71" *) 
  RAM32M mem_reg_0_15_66_71
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__3[59:58]),
        .DIB(out_fifo_i_75__3[61:60]),
        .DIC(out_fifo_i_75__3[63:62]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [51:50]),
        .DOB(\rd_ptr_reg[3]_0 [53:52]),
        .DOC(\rd_ptr_reg[3]_0 [55:54]),
        .DOD(NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED[1:0]),
        .WCLK(\entry_cnt_reg[4]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "6" *) 
  (* ram_slice_end = "11" *) 
  RAM32M mem_reg_0_15_6_11
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA({1'b0,1'b0}),
        .DIB(out_fifo_i_75__3[1:0]),
        .DIC(out_fifo_i_75__3[3:2]),
        .DID({1'b0,1'b0}),
        .DOA({mem_reg_0_15_6_11_n_0,mem_reg_0_15_6_11_n_1}),
        .DOB({mem_reg_0_15_6_11_n_2,mem_reg_0_15_6_11_n_3}),
        .DOC({mem_reg_0_15_6_11_n_4,mem_reg_0_15_6_11_n_5}),
        .DOD(NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED[1:0]),
        .WCLK(\entry_cnt_reg[4]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "72" *) 
  (* ram_slice_end = "77" *) 
  RAM32M mem_reg_0_15_72_77
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__3[65:64]),
        .DIB(out_fifo_i_75__3[67:66]),
        .DIC(out_fifo_i_75__3[69:68]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [57:56]),
        .DOB(\rd_ptr_reg[3]_0 [59:58]),
        .DOC(\rd_ptr_reg[3]_0 [61:60]),
        .DOD(NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED[1:0]),
        .WCLK(\entry_cnt_reg[4]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "78" *) 
  (* ram_slice_end = "79" *) 
  RAM32M mem_reg_0_15_78_79
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__3[71:70]),
        .DIB({1'b0,1'b0}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [63:62]),
        .DOB(NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED[1:0]),
        .DOC(NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED[1:0]),
        .DOD(NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED[1:0]),
        .WCLK(\entry_cnt_reg[4]_0 ),
        .WE(wr_en));
  LUT6 #(
    .INIT(64'hFFFFFFFFF701F700)) 
    \my_empty[1]_i_1__7 
       (.I0(\my_empty_reg[7]_0 ),
        .I1(phy_data_wr_en),
        .I2(\my_full_reg_n_0_[4] ),
        .I3(\my_empty_reg[1]_1 ),
        .I4(my_empty0),
        .I5(ofifo_rst),
        .O(\my_empty[1]_i_1__7_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFF701F700)) 
    \my_empty[7]_i_1__7 
       (.I0(\my_empty_reg[7]_0 ),
        .I1(phy_data_wr_en),
        .I2(\my_full_reg_n_0_[4] ),
        .I3(\my_empty_reg_n_0_[7] ),
        .I4(my_empty0),
        .I5(ofifo_rst),
        .O(\my_empty[7]_i_1__7_n_0 ));
  LUT5 #(
    .INIT(32'h4A400D08)) 
    \my_empty[7]_i_2__7 
       (.I0(wr_ptr_timing[2]),
        .I1(\my_empty[7]_i_3__7_n_0 ),
        .I2(wr_ptr_timing[3]),
        .I3(\my_empty[7]_i_4__7_n_0 ),
        .I4(\rd_ptr_reg_n_0_[2] ),
        .O(my_empty0));
  (* SOFT_HLUTNM = "soft_lutpair1128" *) 
  LUT5 #(
    .INIT(32'h00000040)) 
    \my_empty[7]_i_3__7 
       (.I0(wr_ptr_timing[1]),
        .I1(\rd_ptr_reg_n_0_[0] ),
        .I2(\rd_ptr_reg_n_0_[1] ),
        .I3(\rd_ptr_reg_n_0_[3] ),
        .I4(wr_ptr_timing[0]),
        .O(\my_empty[7]_i_3__7_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1128" *) 
  LUT5 #(
    .INIT(32'h84210842)) 
    \my_empty[7]_i_4__7 
       (.I0(wr_ptr_timing[0]),
        .I1(wr_ptr_timing[1]),
        .I2(\rd_ptr_reg_n_0_[0] ),
        .I3(\rd_ptr_reg_n_0_[1] ),
        .I4(\rd_ptr_reg_n_0_[3] ),
        .O(\my_empty[7]_i_4__7_n_0 ));
  (* syn_maxfan = "3" *) 
  FDRE \my_empty_reg[1] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(1'b1),
        .D(\my_empty[1]_i_1__7_n_0 ),
        .Q(\my_empty_reg[1]_1 ),
        .R(1'b0));
  (* syn_maxfan = "3" *) 
  FDRE \my_empty_reg[7] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(1'b1),
        .D(\my_empty[7]_i_1__7_n_0 ),
        .Q(\my_empty_reg_n_0_[7] ),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h00000000FFFC0080)) 
    \my_full[4]_i_1__7 
       (.I0(my_full0),
        .I1(phy_data_wr_en),
        .I2(\my_empty_reg[7]_0 ),
        .I3(\my_empty_reg_n_0_[7] ),
        .I4(\my_full_reg_n_0_[4] ),
        .I5(ofifo_rst),
        .O(\my_full[4]_i_1__7_n_0 ));
  LUT5 #(
    .INIT(32'h4A400D08)) 
    \my_full[4]_i_2__7 
       (.I0(rd_ptr_timing[2]),
        .I1(\my_full[4]_i_3__7_n_0 ),
        .I2(rd_ptr_timing[3]),
        .I3(\my_full[4]_i_4__7_n_0 ),
        .I4(wr_ptr[2]),
        .O(my_full0));
  (* SOFT_HLUTNM = "soft_lutpair1127" *) 
  LUT5 #(
    .INIT(32'h00000040)) 
    \my_full[4]_i_3__7 
       (.I0(rd_ptr_timing[1]),
        .I1(wr_ptr[0]),
        .I2(wr_ptr[1]),
        .I3(wr_ptr[3]),
        .I4(rd_ptr_timing[0]),
        .O(\my_full[4]_i_3__7_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1127" *) 
  LUT5 #(
    .INIT(32'h84210842)) 
    \my_full[4]_i_4__7 
       (.I0(rd_ptr_timing[0]),
        .I1(rd_ptr_timing[1]),
        .I2(wr_ptr[0]),
        .I3(wr_ptr[1]),
        .I4(wr_ptr[3]),
        .O(\my_full[4]_i_4__7_n_0 ));
  (* syn_maxfan = "3" *) 
  FDRE \my_full_reg[4] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(1'b1),
        .D(\my_full[4]_i_1__7_n_0 ),
        .Q(\my_full_reg_n_0_[4] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair1129" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_10__6
       (.I0(out_fifo_1),
        .I1(out_fifo_0[7]),
        .I2(mem_reg_0_15_12_17_n_2),
        .I3(\my_empty_reg[1]_1 ),
        .O(D1[7]));
  (* SOFT_HLUTNM = "soft_lutpair1136" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_11__6
       (.I0(out_fifo_1),
        .I1(out_fifo_0[6]),
        .I2(mem_reg_0_15_12_17_n_3),
        .I3(\my_empty_reg[1]_1 ),
        .O(D1[6]));
  (* SOFT_HLUTNM = "soft_lutpair1131" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_12__6
       (.I0(out_fifo_1),
        .I1(out_fifo_0[5]),
        .I2(mem_reg_0_15_12_17_n_0),
        .I3(\my_empty_reg[1]_1 ),
        .O(D1[5]));
  (* SOFT_HLUTNM = "soft_lutpair1134" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_13__6
       (.I0(out_fifo_1),
        .I1(out_fifo_0[4]),
        .I2(mem_reg_0_15_12_17_n_1),
        .I3(\my_empty_reg[1]_1 ),
        .O(D1[4]));
  (* SOFT_HLUTNM = "soft_lutpair1132" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_14__6
       (.I0(out_fifo_1),
        .I1(out_fifo_0[3]),
        .I2(mem_reg_0_15_6_11_n_4),
        .I3(\my_empty_reg[1]_1 ),
        .O(D1[3]));
  (* SOFT_HLUTNM = "soft_lutpair1133" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_15__6
       (.I0(out_fifo_1),
        .I1(out_fifo_0[2]),
        .I2(mem_reg_0_15_6_11_n_5),
        .I3(\my_empty_reg[1]_1 ),
        .O(D1[2]));
  (* SOFT_HLUTNM = "soft_lutpair1130" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_16__6
       (.I0(out_fifo),
        .I1(out_fifo_0[1]),
        .I2(mem_reg_0_15_6_11_n_2),
        .I3(\my_empty_reg[1]_1 ),
        .O(D1[1]));
  (* SOFT_HLUTNM = "soft_lutpair1138" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_17__6
       (.I0(out_fifo),
        .I1(out_fifo_0[0]),
        .I2(mem_reg_0_15_6_11_n_3),
        .I3(\my_empty_reg[1]_1 ),
        .O(D1[0]));
  LUT3 #(
    .INIT(8'h0D)) 
    out_fifo_i_1__7
       (.I0(\my_empty_reg[1]_1 ),
        .I1(phy_data_wr_en),
        .I2(\my_empty_reg[7]_0 ),
        .O(\my_empty_reg[1]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1134" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_2__5
       (.I0(mem_reg_0_15_6_11_n_0),
        .I1(\my_empty_reg[1]_1 ),
        .O(D0[7]));
  (* SOFT_HLUTNM = "soft_lutpair1130" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_3__5
       (.I0(mem_reg_0_15_6_11_n_1),
        .I1(\my_empty_reg[1]_1 ),
        .O(D0[6]));
  (* SOFT_HLUTNM = "soft_lutpair1136" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_4__5
       (.I0(mem_reg_0_15_0_5_n_4),
        .I1(\my_empty_reg[1]_1 ),
        .O(D0[5]));
  (* SOFT_HLUTNM = "soft_lutpair1132" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_5__5
       (.I0(mem_reg_0_15_0_5_n_5),
        .I1(\my_empty_reg[1]_1 ),
        .O(D0[4]));
  (* SOFT_HLUTNM = "soft_lutpair1133" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_6__5
       (.I0(mem_reg_0_15_0_5_n_2),
        .I1(\my_empty_reg[1]_1 ),
        .O(D0[3]));
  (* SOFT_HLUTNM = "soft_lutpair1129" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_7__5
       (.I0(mem_reg_0_15_0_5_n_3),
        .I1(\my_empty_reg[1]_1 ),
        .O(D0[2]));
  (* SOFT_HLUTNM = "soft_lutpair1138" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_8__5
       (.I0(mem_reg_0_15_0_5_n_0),
        .I1(\my_empty_reg[1]_1 ),
        .O(D0[1]));
  (* SOFT_HLUTNM = "soft_lutpair1131" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_9__5
       (.I0(mem_reg_0_15_0_5_n_1),
        .I1(\my_empty_reg[1]_1 ),
        .O(D0[0]));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[0] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(\rd_ptr_timing[3]_i_1__7_n_0 ),
        .D(nxt_rd_ptr[0]),
        .Q(\rd_ptr_reg_n_0_[0] ),
        .R(ofifo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[1] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(\rd_ptr_timing[3]_i_1__7_n_0 ),
        .D(nxt_rd_ptr[1]),
        .Q(\rd_ptr_reg_n_0_[1] ),
        .R(ofifo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[2] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(\rd_ptr_timing[3]_i_1__7_n_0 ),
        .D(nxt_rd_ptr[2]),
        .Q(\rd_ptr_reg_n_0_[2] ),
        .R(ofifo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[3] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(\rd_ptr_timing[3]_i_1__7_n_0 ),
        .D(nxt_rd_ptr[3]),
        .Q(\rd_ptr_reg_n_0_[3] ),
        .R(ofifo_rst));
  (* SOFT_HLUTNM = "soft_lutpair1140" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rd_ptr_timing[0]_i_1__15 
       (.I0(\rd_ptr_reg_n_0_[3] ),
        .I1(\rd_ptr_reg_n_0_[0] ),
        .O(nxt_rd_ptr[0]));
  (* SOFT_HLUTNM = "soft_lutpair1140" *) 
  LUT3 #(
    .INIT(8'hB4)) 
    \rd_ptr_timing[1]_i_1__15 
       (.I0(\rd_ptr_reg_n_0_[3] ),
        .I1(\rd_ptr_reg_n_0_[0] ),
        .I2(\rd_ptr_reg_n_0_[1] ),
        .O(nxt_rd_ptr[1]));
  (* SOFT_HLUTNM = "soft_lutpair1137" *) 
  LUT4 #(
    .INIT(16'hAA6A)) 
    \rd_ptr_timing[2]_i_1__7 
       (.I0(\rd_ptr_reg_n_0_[2] ),
        .I1(\rd_ptr_reg_n_0_[0] ),
        .I2(\rd_ptr_reg_n_0_[1] ),
        .I3(\rd_ptr_reg_n_0_[3] ),
        .O(nxt_rd_ptr[2]));
  LUT2 #(
    .INIT(4'h1)) 
    \rd_ptr_timing[3]_i_1__7 
       (.I0(\my_empty_reg[7]_0 ),
        .I1(\my_empty_reg_n_0_[7] ),
        .O(\rd_ptr_timing[3]_i_1__7_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1137" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \rd_ptr_timing[3]_i_2__7 
       (.I0(\rd_ptr_reg_n_0_[3] ),
        .I1(\rd_ptr_reg_n_0_[1] ),
        .I2(\rd_ptr_reg_n_0_[0] ),
        .I3(\rd_ptr_reg_n_0_[2] ),
        .O(nxt_rd_ptr[3]));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[0] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(\rd_ptr_timing[3]_i_1__7_n_0 ),
        .D(nxt_rd_ptr[0]),
        .Q(rd_ptr_timing[0]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[1] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(\rd_ptr_timing[3]_i_1__7_n_0 ),
        .D(nxt_rd_ptr[1]),
        .Q(rd_ptr_timing[1]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[2] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(\rd_ptr_timing[3]_i_1__7_n_0 ),
        .D(nxt_rd_ptr[2]),
        .Q(rd_ptr_timing[2]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[3] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(\rd_ptr_timing[3]_i_1__7_n_0 ),
        .D(nxt_rd_ptr[3]),
        .Q(rd_ptr_timing[3]),
        .R(ofifo_rst));
  (* SOFT_HLUTNM = "soft_lutpair1139" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \wr_ptr[0]_i_1__15 
       (.I0(wr_ptr[3]),
        .I1(wr_ptr[0]),
        .O(nxt_wr_ptr[0]));
  (* SOFT_HLUTNM = "soft_lutpair1139" *) 
  LUT3 #(
    .INIT(8'hB4)) 
    \wr_ptr[1]_i_1__15 
       (.I0(wr_ptr[3]),
        .I1(wr_ptr[0]),
        .I2(wr_ptr[1]),
        .O(nxt_wr_ptr[1]));
  (* SOFT_HLUTNM = "soft_lutpair1135" *) 
  LUT4 #(
    .INIT(16'hAA6A)) 
    \wr_ptr[2]_i_1__7 
       (.I0(wr_ptr[2]),
        .I1(wr_ptr[0]),
        .I2(wr_ptr[1]),
        .I3(wr_ptr[3]),
        .O(nxt_wr_ptr[2]));
  LUT4 #(
    .INIT(16'h082A)) 
    \wr_ptr[3]_i_1__7 
       (.I0(phy_data_wr_en),
        .I1(\my_empty_reg[7]_0 ),
        .I2(\my_full_reg_n_0_[4] ),
        .I3(\my_empty_reg_n_0_[7] ),
        .O(wr_ptr0));
  (* SOFT_HLUTNM = "soft_lutpair1135" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \wr_ptr[3]_i_2__6 
       (.I0(wr_ptr[3]),
        .I1(wr_ptr[1]),
        .I2(wr_ptr[0]),
        .I3(wr_ptr[2]),
        .O(nxt_wr_ptr[3]));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[0] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[0]),
        .Q(wr_ptr[0]),
        .R(ofifo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[1] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[1]),
        .Q(wr_ptr[1]),
        .R(ofifo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[2] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[2]),
        .Q(wr_ptr[2]),
        .R(ofifo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[3] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[3]),
        .Q(wr_ptr[3]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[0] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[0]),
        .Q(wr_ptr_timing[0]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[1] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[1]),
        .Q(wr_ptr_timing[1]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[2] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[2]),
        .Q(wr_ptr_timing[2]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[3] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[3]),
        .Q(wr_ptr_timing[3]),
        .R(ofifo_rst));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_of_pre_fifo" *) 
module mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_16
   (\my_empty_reg[1]_0 ,
    \my_empty_reg[1]_1 ,
    D0,
    D1,
    \rd_ptr_reg[3]_0 ,
    Q,
    ofifo_rst,
    \wr_ptr_timing_reg[3]_0 ,
    \my_empty_reg[7]_0 ,
    phy_data_wr_en,
    out_fifo,
    out_fifo_0,
    out_fifo_1,
    out_fifo_i_75__2);
  output \my_empty_reg[1]_0 ;
  output \my_empty_reg[1]_1 ;
  output [7:0]D0;
  output [7:0]D1;
  output [63:0]\rd_ptr_reg[3]_0 ;
  output [2:0]Q;
  input ofifo_rst;
  input \wr_ptr_timing_reg[3]_0 ;
  input \my_empty_reg[7]_0 ;
  input phy_data_wr_en;
  input out_fifo;
  input [7:0]out_fifo_0;
  input out_fifo_1;
  input [71:0]out_fifo_i_75__2;

  wire [7:0]D0;
  wire [7:0]D1;
  wire [2:0]Q;
  wire entry_cnt10_out__0;
  wire \entry_cnt[0]_i_1__5_n_0 ;
  wire \entry_cnt[1]_i_1__5_n_0 ;
  wire \entry_cnt[2]_i_1__5_n_0 ;
  wire \entry_cnt[3]_i_1__5_n_0 ;
  wire \entry_cnt[4]_i_1__5_n_0 ;
  wire \entry_cnt[4]_i_2__5_n_0 ;
  wire \entry_cnt_reg_n_0_[0] ;
  wire \entry_cnt_reg_n_0_[1] ;
  wire mem_reg_0_15_0_5_n_0;
  wire mem_reg_0_15_0_5_n_1;
  wire mem_reg_0_15_0_5_n_2;
  wire mem_reg_0_15_0_5_n_3;
  wire mem_reg_0_15_0_5_n_4;
  wire mem_reg_0_15_0_5_n_5;
  wire mem_reg_0_15_12_17_n_0;
  wire mem_reg_0_15_12_17_n_1;
  wire mem_reg_0_15_12_17_n_2;
  wire mem_reg_0_15_12_17_n_3;
  wire mem_reg_0_15_6_11_n_0;
  wire mem_reg_0_15_6_11_n_1;
  wire mem_reg_0_15_6_11_n_2;
  wire mem_reg_0_15_6_11_n_3;
  wire mem_reg_0_15_6_11_n_4;
  wire mem_reg_0_15_6_11_n_5;
  wire my_empty0;
  wire \my_empty[1]_i_1__6_n_0 ;
  wire \my_empty[7]_i_1__6_n_0 ;
  wire \my_empty[7]_i_3__6_n_0 ;
  wire \my_empty[7]_i_4__6_n_0 ;
  wire \my_empty_reg[1]_0 ;
  wire \my_empty_reg[1]_1 ;
  wire \my_empty_reg[7]_0 ;
  wire \my_empty_reg_n_0_[7] ;
  wire my_full0;
  wire \my_full[4]_i_1__6_n_0 ;
  wire \my_full[4]_i_3__6_n_0 ;
  wire \my_full[4]_i_4__6_n_0 ;
  wire \my_full_reg_n_0_[4] ;
  wire [3:0]nxt_rd_ptr;
  wire [3:0]nxt_wr_ptr;
  wire ofifo_rst;
  wire out_fifo;
  wire [7:0]out_fifo_0;
  wire out_fifo_1;
  wire [71:0]out_fifo_i_75__2;
  wire phy_data_wr_en;
  wire [63:0]\rd_ptr_reg[3]_0 ;
  wire \rd_ptr_reg_n_0_[0] ;
  wire \rd_ptr_reg_n_0_[1] ;
  wire \rd_ptr_reg_n_0_[2] ;
  wire \rd_ptr_reg_n_0_[3] ;
  wire [3:0]rd_ptr_timing;
  wire \rd_ptr_timing[3]_i_1__6_n_0 ;
  (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) wire wr_en;
  wire [3:0]wr_ptr;
  wire wr_ptr0;
  wire [3:0]wr_ptr_timing;
  wire \wr_ptr_timing_reg[3]_0 ;
  wire [1:0]NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED;

  (* SOFT_HLUTNM = "soft_lutpair1075" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \entry_cnt[0]_i_1__5 
       (.I0(\entry_cnt_reg_n_0_[0] ),
        .O(\entry_cnt[0]_i_1__5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1074" *) 
  LUT5 #(
    .INIT(32'hAA6A5595)) 
    \entry_cnt[1]_i_1__5 
       (.I0(\entry_cnt_reg_n_0_[0] ),
        .I1(\my_empty_reg[7]_0 ),
        .I2(phy_data_wr_en),
        .I3(\my_full_reg_n_0_[4] ),
        .I4(\entry_cnt_reg_n_0_[1] ),
        .O(\entry_cnt[1]_i_1__5_n_0 ));
  LUT6 #(
    .INIT(64'hFF7F0080AAEA5515)) 
    \entry_cnt[2]_i_1__5 
       (.I0(\entry_cnt_reg_n_0_[0] ),
        .I1(\my_empty_reg[7]_0 ),
        .I2(phy_data_wr_en),
        .I3(\my_full_reg_n_0_[4] ),
        .I4(Q[0]),
        .I5(\entry_cnt_reg_n_0_[1] ),
        .O(\entry_cnt[2]_i_1__5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1075" *) 
  LUT5 #(
    .INIT(32'h7F80FE01)) 
    \entry_cnt[3]_i_1__5 
       (.I0(entry_cnt10_out__0),
        .I1(\entry_cnt_reg_n_0_[0] ),
        .I2(\entry_cnt_reg_n_0_[1] ),
        .I3(Q[1]),
        .I4(Q[0]),
        .O(\entry_cnt[3]_i_1__5_n_0 ));
  LUT4 #(
    .INIT(16'h5003)) 
    \entry_cnt[4]_i_1__5 
       (.I0(\my_full_reg_n_0_[4] ),
        .I1(\my_empty_reg_n_0_[7] ),
        .I2(\my_empty_reg[7]_0 ),
        .I3(phy_data_wr_en),
        .O(\entry_cnt[4]_i_1__5_n_0 ));
  LUT6 #(
    .INIT(64'h7FFF8000FFFE0001)) 
    \entry_cnt[4]_i_2__5 
       (.I0(\entry_cnt_reg_n_0_[1] ),
        .I1(\entry_cnt_reg_n_0_[0] ),
        .I2(entry_cnt10_out__0),
        .I3(Q[0]),
        .I4(Q[2]),
        .I5(Q[1]),
        .O(\entry_cnt[4]_i_2__5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1074" *) 
  LUT3 #(
    .INIT(8'h08)) 
    \entry_cnt[4]_i_3__5 
       (.I0(\my_empty_reg[7]_0 ),
        .I1(phy_data_wr_en),
        .I2(\my_full_reg_n_0_[4] ),
        .O(entry_cnt10_out__0));
  FDRE \entry_cnt_reg[0] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(\entry_cnt[4]_i_1__5_n_0 ),
        .D(\entry_cnt[0]_i_1__5_n_0 ),
        .Q(\entry_cnt_reg_n_0_[0] ),
        .R(ofifo_rst));
  FDRE \entry_cnt_reg[1] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(\entry_cnt[4]_i_1__5_n_0 ),
        .D(\entry_cnt[1]_i_1__5_n_0 ),
        .Q(\entry_cnt_reg_n_0_[1] ),
        .R(ofifo_rst));
  FDRE \entry_cnt_reg[2] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(\entry_cnt[4]_i_1__5_n_0 ),
        .D(\entry_cnt[2]_i_1__5_n_0 ),
        .Q(Q[0]),
        .R(ofifo_rst));
  FDRE \entry_cnt_reg[3] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(\entry_cnt[4]_i_1__5_n_0 ),
        .D(\entry_cnt[3]_i_1__5_n_0 ),
        .Q(Q[1]),
        .R(ofifo_rst));
  FDRE \entry_cnt_reg[4] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(\entry_cnt[4]_i_1__5_n_0 ),
        .D(\entry_cnt[4]_i_2__5_n_0 ),
        .Q(Q[2]),
        .R(ofifo_rst));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "0" *) 
  (* ram_slice_end = "5" *) 
  RAM32M mem_reg_0_15_0_5
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA({1'b0,1'b0}),
        .DIB({1'b0,1'b0}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA({mem_reg_0_15_0_5_n_0,mem_reg_0_15_0_5_n_1}),
        .DOB({mem_reg_0_15_0_5_n_2,mem_reg_0_15_0_5_n_3}),
        .DOC({mem_reg_0_15_0_5_n_4,mem_reg_0_15_0_5_n_5}),
        .DOD(NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED[1:0]),
        .WCLK(\wr_ptr_timing_reg[3]_0 ),
        .WE(wr_en));
  LUT4 #(
    .INIT(16'h2700)) 
    mem_reg_0_15_0_5_i_1__5
       (.I0(\my_empty_reg[7]_0 ),
        .I1(\my_full_reg_n_0_[4] ),
        .I2(\my_empty_reg[1]_1 ),
        .I3(phy_data_wr_en),
        .O(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "12" *) 
  (* ram_slice_end = "17" *) 
  RAM32M mem_reg_0_15_12_17
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__2[5:4]),
        .DIB(out_fifo_i_75__2[7:6]),
        .DIC(out_fifo_i_75__2[9:8]),
        .DID({1'b0,1'b0}),
        .DOA({mem_reg_0_15_12_17_n_0,mem_reg_0_15_12_17_n_1}),
        .DOB({mem_reg_0_15_12_17_n_2,mem_reg_0_15_12_17_n_3}),
        .DOC(\rd_ptr_reg[3]_0 [1:0]),
        .DOD(NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED[1:0]),
        .WCLK(\wr_ptr_timing_reg[3]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "18" *) 
  (* ram_slice_end = "23" *) 
  RAM32M mem_reg_0_15_18_23
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__2[11:10]),
        .DIB(out_fifo_i_75__2[13:12]),
        .DIC(out_fifo_i_75__2[15:14]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [3:2]),
        .DOB(\rd_ptr_reg[3]_0 [5:4]),
        .DOC(\rd_ptr_reg[3]_0 [7:6]),
        .DOD(NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED[1:0]),
        .WCLK(\wr_ptr_timing_reg[3]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "24" *) 
  (* ram_slice_end = "29" *) 
  RAM32M mem_reg_0_15_24_29
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__2[17:16]),
        .DIB(out_fifo_i_75__2[19:18]),
        .DIC(out_fifo_i_75__2[21:20]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [9:8]),
        .DOB(\rd_ptr_reg[3]_0 [11:10]),
        .DOC(\rd_ptr_reg[3]_0 [13:12]),
        .DOD(NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED[1:0]),
        .WCLK(\wr_ptr_timing_reg[3]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "30" *) 
  (* ram_slice_end = "35" *) 
  RAM32M mem_reg_0_15_30_35
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__2[23:22]),
        .DIB(out_fifo_i_75__2[25:24]),
        .DIC(out_fifo_i_75__2[27:26]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [15:14]),
        .DOB(\rd_ptr_reg[3]_0 [17:16]),
        .DOC(\rd_ptr_reg[3]_0 [19:18]),
        .DOD(NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED[1:0]),
        .WCLK(\wr_ptr_timing_reg[3]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "36" *) 
  (* ram_slice_end = "41" *) 
  RAM32M mem_reg_0_15_36_41
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__2[29:28]),
        .DIB(out_fifo_i_75__2[31:30]),
        .DIC(out_fifo_i_75__2[33:32]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [21:20]),
        .DOB(\rd_ptr_reg[3]_0 [23:22]),
        .DOC(\rd_ptr_reg[3]_0 [25:24]),
        .DOD(NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED[1:0]),
        .WCLK(\wr_ptr_timing_reg[3]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "42" *) 
  (* ram_slice_end = "47" *) 
  RAM32M mem_reg_0_15_42_47
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__2[35:34]),
        .DIB(out_fifo_i_75__2[37:36]),
        .DIC(out_fifo_i_75__2[39:38]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [27:26]),
        .DOB(\rd_ptr_reg[3]_0 [29:28]),
        .DOC(\rd_ptr_reg[3]_0 [31:30]),
        .DOD(NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED[1:0]),
        .WCLK(\wr_ptr_timing_reg[3]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "48" *) 
  (* ram_slice_end = "53" *) 
  RAM32M mem_reg_0_15_48_53
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__2[41:40]),
        .DIB(out_fifo_i_75__2[43:42]),
        .DIC(out_fifo_i_75__2[45:44]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [33:32]),
        .DOB(\rd_ptr_reg[3]_0 [35:34]),
        .DOC(\rd_ptr_reg[3]_0 [37:36]),
        .DOD(NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED[1:0]),
        .WCLK(\wr_ptr_timing_reg[3]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "54" *) 
  (* ram_slice_end = "59" *) 
  RAM32M mem_reg_0_15_54_59
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__2[47:46]),
        .DIB(out_fifo_i_75__2[49:48]),
        .DIC(out_fifo_i_75__2[51:50]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [39:38]),
        .DOB(\rd_ptr_reg[3]_0 [41:40]),
        .DOC(\rd_ptr_reg[3]_0 [43:42]),
        .DOD(NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED[1:0]),
        .WCLK(\wr_ptr_timing_reg[3]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "60" *) 
  (* ram_slice_end = "65" *) 
  RAM32M mem_reg_0_15_60_65
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__2[53:52]),
        .DIB(out_fifo_i_75__2[55:54]),
        .DIC(out_fifo_i_75__2[57:56]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [45:44]),
        .DOB(\rd_ptr_reg[3]_0 [47:46]),
        .DOC(\rd_ptr_reg[3]_0 [49:48]),
        .DOD(NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED[1:0]),
        .WCLK(\wr_ptr_timing_reg[3]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "66" *) 
  (* ram_slice_end = "71" *) 
  RAM32M mem_reg_0_15_66_71
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__2[59:58]),
        .DIB(out_fifo_i_75__2[61:60]),
        .DIC(out_fifo_i_75__2[63:62]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [51:50]),
        .DOB(\rd_ptr_reg[3]_0 [53:52]),
        .DOC(\rd_ptr_reg[3]_0 [55:54]),
        .DOD(NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED[1:0]),
        .WCLK(\wr_ptr_timing_reg[3]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "6" *) 
  (* ram_slice_end = "11" *) 
  RAM32M mem_reg_0_15_6_11
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA({1'b0,1'b0}),
        .DIB(out_fifo_i_75__2[1:0]),
        .DIC(out_fifo_i_75__2[3:2]),
        .DID({1'b0,1'b0}),
        .DOA({mem_reg_0_15_6_11_n_0,mem_reg_0_15_6_11_n_1}),
        .DOB({mem_reg_0_15_6_11_n_2,mem_reg_0_15_6_11_n_3}),
        .DOC({mem_reg_0_15_6_11_n_4,mem_reg_0_15_6_11_n_5}),
        .DOD(NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED[1:0]),
        .WCLK(\wr_ptr_timing_reg[3]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "72" *) 
  (* ram_slice_end = "77" *) 
  RAM32M mem_reg_0_15_72_77
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__2[65:64]),
        .DIB(out_fifo_i_75__2[67:66]),
        .DIC(out_fifo_i_75__2[69:68]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [57:56]),
        .DOB(\rd_ptr_reg[3]_0 [59:58]),
        .DOC(\rd_ptr_reg[3]_0 [61:60]),
        .DOD(NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED[1:0]),
        .WCLK(\wr_ptr_timing_reg[3]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "78" *) 
  (* ram_slice_end = "79" *) 
  RAM32M mem_reg_0_15_78_79
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__2[71:70]),
        .DIB({1'b0,1'b0}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [63:62]),
        .DOB(NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED[1:0]),
        .DOC(NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED[1:0]),
        .DOD(NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED[1:0]),
        .WCLK(\wr_ptr_timing_reg[3]_0 ),
        .WE(wr_en));
  LUT6 #(
    .INIT(64'hFFFFFFFFF701F700)) 
    \my_empty[1]_i_1__6 
       (.I0(\my_empty_reg[7]_0 ),
        .I1(phy_data_wr_en),
        .I2(\my_full_reg_n_0_[4] ),
        .I3(\my_empty_reg[1]_1 ),
        .I4(my_empty0),
        .I5(ofifo_rst),
        .O(\my_empty[1]_i_1__6_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFF701F700)) 
    \my_empty[7]_i_1__6 
       (.I0(\my_empty_reg[7]_0 ),
        .I1(phy_data_wr_en),
        .I2(\my_full_reg_n_0_[4] ),
        .I3(\my_empty_reg_n_0_[7] ),
        .I4(my_empty0),
        .I5(ofifo_rst),
        .O(\my_empty[7]_i_1__6_n_0 ));
  LUT5 #(
    .INIT(32'h4A400D08)) 
    \my_empty[7]_i_2__6 
       (.I0(wr_ptr_timing[2]),
        .I1(\my_empty[7]_i_3__6_n_0 ),
        .I2(wr_ptr_timing[3]),
        .I3(\my_empty[7]_i_4__6_n_0 ),
        .I4(\rd_ptr_reg_n_0_[2] ),
        .O(my_empty0));
  (* SOFT_HLUTNM = "soft_lutpair1077" *) 
  LUT5 #(
    .INIT(32'h00000040)) 
    \my_empty[7]_i_3__6 
       (.I0(wr_ptr_timing[1]),
        .I1(\rd_ptr_reg_n_0_[0] ),
        .I2(\rd_ptr_reg_n_0_[1] ),
        .I3(\rd_ptr_reg_n_0_[3] ),
        .I4(wr_ptr_timing[0]),
        .O(\my_empty[7]_i_3__6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1077" *) 
  LUT5 #(
    .INIT(32'h84210842)) 
    \my_empty[7]_i_4__6 
       (.I0(wr_ptr_timing[0]),
        .I1(wr_ptr_timing[1]),
        .I2(\rd_ptr_reg_n_0_[0] ),
        .I3(\rd_ptr_reg_n_0_[1] ),
        .I4(\rd_ptr_reg_n_0_[3] ),
        .O(\my_empty[7]_i_4__6_n_0 ));
  (* syn_maxfan = "3" *) 
  FDRE \my_empty_reg[1] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(1'b1),
        .D(\my_empty[1]_i_1__6_n_0 ),
        .Q(\my_empty_reg[1]_1 ),
        .R(1'b0));
  (* syn_maxfan = "3" *) 
  FDRE \my_empty_reg[7] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(1'b1),
        .D(\my_empty[7]_i_1__6_n_0 ),
        .Q(\my_empty_reg_n_0_[7] ),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h00000000FFFC0080)) 
    \my_full[4]_i_1__6 
       (.I0(my_full0),
        .I1(phy_data_wr_en),
        .I2(\my_empty_reg[7]_0 ),
        .I3(\my_empty_reg_n_0_[7] ),
        .I4(\my_full_reg_n_0_[4] ),
        .I5(ofifo_rst),
        .O(\my_full[4]_i_1__6_n_0 ));
  LUT5 #(
    .INIT(32'h4A400D08)) 
    \my_full[4]_i_2__6 
       (.I0(rd_ptr_timing[2]),
        .I1(\my_full[4]_i_3__6_n_0 ),
        .I2(rd_ptr_timing[3]),
        .I3(\my_full[4]_i_4__6_n_0 ),
        .I4(wr_ptr[2]),
        .O(my_full0));
  (* SOFT_HLUTNM = "soft_lutpair1076" *) 
  LUT5 #(
    .INIT(32'h00000040)) 
    \my_full[4]_i_3__6 
       (.I0(rd_ptr_timing[1]),
        .I1(wr_ptr[0]),
        .I2(wr_ptr[1]),
        .I3(wr_ptr[3]),
        .I4(rd_ptr_timing[0]),
        .O(\my_full[4]_i_3__6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1076" *) 
  LUT5 #(
    .INIT(32'h84210842)) 
    \my_full[4]_i_4__6 
       (.I0(rd_ptr_timing[0]),
        .I1(rd_ptr_timing[1]),
        .I2(wr_ptr[0]),
        .I3(wr_ptr[1]),
        .I4(wr_ptr[3]),
        .O(\my_full[4]_i_4__6_n_0 ));
  (* syn_maxfan = "3" *) 
  FDRE \my_full_reg[4] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(1'b1),
        .D(\my_full[4]_i_1__6_n_0 ),
        .Q(\my_full_reg_n_0_[4] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair1078" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_10__5
       (.I0(out_fifo_1),
        .I1(out_fifo_0[7]),
        .I2(mem_reg_0_15_12_17_n_2),
        .I3(\my_empty_reg[1]_1 ),
        .O(D1[7]));
  (* SOFT_HLUTNM = "soft_lutpair1085" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_11__5
       (.I0(out_fifo_1),
        .I1(out_fifo_0[6]),
        .I2(mem_reg_0_15_12_17_n_3),
        .I3(\my_empty_reg[1]_1 ),
        .O(D1[6]));
  (* SOFT_HLUTNM = "soft_lutpair1080" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_12__5
       (.I0(out_fifo_1),
        .I1(out_fifo_0[5]),
        .I2(mem_reg_0_15_12_17_n_0),
        .I3(\my_empty_reg[1]_1 ),
        .O(D1[5]));
  (* SOFT_HLUTNM = "soft_lutpair1083" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_13__5
       (.I0(out_fifo_1),
        .I1(out_fifo_0[4]),
        .I2(mem_reg_0_15_12_17_n_1),
        .I3(\my_empty_reg[1]_1 ),
        .O(D1[4]));
  (* SOFT_HLUTNM = "soft_lutpair1081" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_14__5
       (.I0(out_fifo_1),
        .I1(out_fifo_0[3]),
        .I2(mem_reg_0_15_6_11_n_4),
        .I3(\my_empty_reg[1]_1 ),
        .O(D1[3]));
  (* SOFT_HLUTNM = "soft_lutpair1082" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_15__5
       (.I0(out_fifo_1),
        .I1(out_fifo_0[2]),
        .I2(mem_reg_0_15_6_11_n_5),
        .I3(\my_empty_reg[1]_1 ),
        .O(D1[2]));
  (* SOFT_HLUTNM = "soft_lutpair1079" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_16__5
       (.I0(out_fifo),
        .I1(out_fifo_0[1]),
        .I2(mem_reg_0_15_6_11_n_2),
        .I3(\my_empty_reg[1]_1 ),
        .O(D1[1]));
  (* SOFT_HLUTNM = "soft_lutpair1087" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_17__5
       (.I0(out_fifo),
        .I1(out_fifo_0[0]),
        .I2(mem_reg_0_15_6_11_n_3),
        .I3(\my_empty_reg[1]_1 ),
        .O(D1[0]));
  LUT3 #(
    .INIT(8'h0D)) 
    out_fifo_i_1__6
       (.I0(\my_empty_reg[1]_1 ),
        .I1(phy_data_wr_en),
        .I2(\my_empty_reg[7]_0 ),
        .O(\my_empty_reg[1]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1083" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_2__4
       (.I0(mem_reg_0_15_6_11_n_0),
        .I1(\my_empty_reg[1]_1 ),
        .O(D0[7]));
  (* SOFT_HLUTNM = "soft_lutpair1079" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_3__4
       (.I0(mem_reg_0_15_6_11_n_1),
        .I1(\my_empty_reg[1]_1 ),
        .O(D0[6]));
  (* SOFT_HLUTNM = "soft_lutpair1085" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_4__4
       (.I0(mem_reg_0_15_0_5_n_4),
        .I1(\my_empty_reg[1]_1 ),
        .O(D0[5]));
  (* SOFT_HLUTNM = "soft_lutpair1081" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_5__4
       (.I0(mem_reg_0_15_0_5_n_5),
        .I1(\my_empty_reg[1]_1 ),
        .O(D0[4]));
  (* SOFT_HLUTNM = "soft_lutpair1082" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_6__4
       (.I0(mem_reg_0_15_0_5_n_2),
        .I1(\my_empty_reg[1]_1 ),
        .O(D0[3]));
  (* SOFT_HLUTNM = "soft_lutpair1078" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_7__4
       (.I0(mem_reg_0_15_0_5_n_3),
        .I1(\my_empty_reg[1]_1 ),
        .O(D0[2]));
  (* SOFT_HLUTNM = "soft_lutpair1087" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_8__4
       (.I0(mem_reg_0_15_0_5_n_0),
        .I1(\my_empty_reg[1]_1 ),
        .O(D0[1]));
  (* SOFT_HLUTNM = "soft_lutpair1080" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_9__4
       (.I0(mem_reg_0_15_0_5_n_1),
        .I1(\my_empty_reg[1]_1 ),
        .O(D0[0]));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[0] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(\rd_ptr_timing[3]_i_1__6_n_0 ),
        .D(nxt_rd_ptr[0]),
        .Q(\rd_ptr_reg_n_0_[0] ),
        .R(ofifo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[1] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(\rd_ptr_timing[3]_i_1__6_n_0 ),
        .D(nxt_rd_ptr[1]),
        .Q(\rd_ptr_reg_n_0_[1] ),
        .R(ofifo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[2] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(\rd_ptr_timing[3]_i_1__6_n_0 ),
        .D(nxt_rd_ptr[2]),
        .Q(\rd_ptr_reg_n_0_[2] ),
        .R(ofifo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[3] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(\rd_ptr_timing[3]_i_1__6_n_0 ),
        .D(nxt_rd_ptr[3]),
        .Q(\rd_ptr_reg_n_0_[3] ),
        .R(ofifo_rst));
  (* SOFT_HLUTNM = "soft_lutpair1089" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rd_ptr_timing[0]_i_1__13 
       (.I0(\rd_ptr_reg_n_0_[3] ),
        .I1(\rd_ptr_reg_n_0_[0] ),
        .O(nxt_rd_ptr[0]));
  (* SOFT_HLUTNM = "soft_lutpair1089" *) 
  LUT3 #(
    .INIT(8'hB4)) 
    \rd_ptr_timing[1]_i_1__13 
       (.I0(\rd_ptr_reg_n_0_[3] ),
        .I1(\rd_ptr_reg_n_0_[0] ),
        .I2(\rd_ptr_reg_n_0_[1] ),
        .O(nxt_rd_ptr[1]));
  (* SOFT_HLUTNM = "soft_lutpair1086" *) 
  LUT4 #(
    .INIT(16'hAA6A)) 
    \rd_ptr_timing[2]_i_1__6 
       (.I0(\rd_ptr_reg_n_0_[2] ),
        .I1(\rd_ptr_reg_n_0_[0] ),
        .I2(\rd_ptr_reg_n_0_[1] ),
        .I3(\rd_ptr_reg_n_0_[3] ),
        .O(nxt_rd_ptr[2]));
  LUT2 #(
    .INIT(4'h1)) 
    \rd_ptr_timing[3]_i_1__6 
       (.I0(\my_empty_reg[7]_0 ),
        .I1(\my_empty_reg_n_0_[7] ),
        .O(\rd_ptr_timing[3]_i_1__6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1086" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \rd_ptr_timing[3]_i_2__6 
       (.I0(\rd_ptr_reg_n_0_[3] ),
        .I1(\rd_ptr_reg_n_0_[1] ),
        .I2(\rd_ptr_reg_n_0_[0] ),
        .I3(\rd_ptr_reg_n_0_[2] ),
        .O(nxt_rd_ptr[3]));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[0] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(\rd_ptr_timing[3]_i_1__6_n_0 ),
        .D(nxt_rd_ptr[0]),
        .Q(rd_ptr_timing[0]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[1] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(\rd_ptr_timing[3]_i_1__6_n_0 ),
        .D(nxt_rd_ptr[1]),
        .Q(rd_ptr_timing[1]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[2] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(\rd_ptr_timing[3]_i_1__6_n_0 ),
        .D(nxt_rd_ptr[2]),
        .Q(rd_ptr_timing[2]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[3] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(\rd_ptr_timing[3]_i_1__6_n_0 ),
        .D(nxt_rd_ptr[3]),
        .Q(rd_ptr_timing[3]),
        .R(ofifo_rst));
  (* SOFT_HLUTNM = "soft_lutpair1088" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \wr_ptr[0]_i_1__13 
       (.I0(wr_ptr[3]),
        .I1(wr_ptr[0]),
        .O(nxt_wr_ptr[0]));
  (* SOFT_HLUTNM = "soft_lutpair1088" *) 
  LUT3 #(
    .INIT(8'hB4)) 
    \wr_ptr[1]_i_1__13 
       (.I0(wr_ptr[3]),
        .I1(wr_ptr[0]),
        .I2(wr_ptr[1]),
        .O(nxt_wr_ptr[1]));
  (* SOFT_HLUTNM = "soft_lutpair1084" *) 
  LUT4 #(
    .INIT(16'hAA6A)) 
    \wr_ptr[2]_i_1__6 
       (.I0(wr_ptr[2]),
        .I1(wr_ptr[0]),
        .I2(wr_ptr[1]),
        .I3(wr_ptr[3]),
        .O(nxt_wr_ptr[2]));
  LUT4 #(
    .INIT(16'h082A)) 
    \wr_ptr[3]_i_1__6 
       (.I0(phy_data_wr_en),
        .I1(\my_empty_reg[7]_0 ),
        .I2(\my_full_reg_n_0_[4] ),
        .I3(\my_empty_reg_n_0_[7] ),
        .O(wr_ptr0));
  (* SOFT_HLUTNM = "soft_lutpair1084" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \wr_ptr[3]_i_2__5 
       (.I0(wr_ptr[3]),
        .I1(wr_ptr[1]),
        .I2(wr_ptr[0]),
        .I3(wr_ptr[2]),
        .O(nxt_wr_ptr[3]));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[0] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[0]),
        .Q(wr_ptr[0]),
        .R(ofifo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[1] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[1]),
        .Q(wr_ptr[1]),
        .R(ofifo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[2] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[2]),
        .Q(wr_ptr[2]),
        .R(ofifo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[3] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[3]),
        .Q(wr_ptr[3]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[0] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[0]),
        .Q(wr_ptr_timing[0]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[1] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[1]),
        .Q(wr_ptr_timing[1]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[2] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[2]),
        .Q(wr_ptr_timing[2]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[3] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[3]),
        .Q(wr_ptr_timing[3]),
        .R(ofifo_rst));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_of_pre_fifo" *) 
module mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_19
   (\my_empty_reg[1]_0 ,
    \my_empty_reg[1]_1 ,
    D0,
    D1,
    \rd_ptr_reg[3]_0 ,
    Q,
    ofifo_rst,
    \entry_cnt_reg[4]_0 ,
    \my_empty_reg[7]_0 ,
    phy_data_wr_en,
    out_fifo,
    out_fifo_0,
    out_fifo_1,
    out_fifo_i_75__1);
  output \my_empty_reg[1]_0 ;
  output \my_empty_reg[1]_1 ;
  output [7:0]D0;
  output [7:0]D1;
  output [63:0]\rd_ptr_reg[3]_0 ;
  output [2:0]Q;
  input ofifo_rst;
  input \entry_cnt_reg[4]_0 ;
  input \my_empty_reg[7]_0 ;
  input phy_data_wr_en;
  input out_fifo;
  input [7:0]out_fifo_0;
  input out_fifo_1;
  input [71:0]out_fifo_i_75__1;

  wire [7:0]D0;
  wire [7:0]D1;
  wire [2:0]Q;
  wire entry_cnt10_out__0;
  wire \entry_cnt[0]_i_1__4_n_0 ;
  wire \entry_cnt[1]_i_1__4_n_0 ;
  wire \entry_cnt[2]_i_1__4_n_0 ;
  wire \entry_cnt[3]_i_1__4_n_0 ;
  wire \entry_cnt[4]_i_1__4_n_0 ;
  wire \entry_cnt[4]_i_2__4_n_0 ;
  wire \entry_cnt_reg[4]_0 ;
  wire \entry_cnt_reg_n_0_[0] ;
  wire \entry_cnt_reg_n_0_[1] ;
  wire mem_reg_0_15_0_5_n_0;
  wire mem_reg_0_15_0_5_n_1;
  wire mem_reg_0_15_0_5_n_2;
  wire mem_reg_0_15_0_5_n_3;
  wire mem_reg_0_15_0_5_n_4;
  wire mem_reg_0_15_0_5_n_5;
  wire mem_reg_0_15_12_17_n_0;
  wire mem_reg_0_15_12_17_n_1;
  wire mem_reg_0_15_12_17_n_2;
  wire mem_reg_0_15_12_17_n_3;
  wire mem_reg_0_15_6_11_n_0;
  wire mem_reg_0_15_6_11_n_1;
  wire mem_reg_0_15_6_11_n_2;
  wire mem_reg_0_15_6_11_n_3;
  wire mem_reg_0_15_6_11_n_4;
  wire mem_reg_0_15_6_11_n_5;
  wire my_empty0;
  wire \my_empty[1]_i_1__5_n_0 ;
  wire \my_empty[7]_i_1__5_n_0 ;
  wire \my_empty[7]_i_3__5_n_0 ;
  wire \my_empty[7]_i_4__5_n_0 ;
  wire \my_empty_reg[1]_0 ;
  wire \my_empty_reg[1]_1 ;
  wire \my_empty_reg[7]_0 ;
  wire \my_empty_reg_n_0_[7] ;
  wire my_full0;
  wire \my_full[4]_i_1__5_n_0 ;
  wire \my_full[4]_i_3__5_n_0 ;
  wire \my_full[4]_i_4__5_n_0 ;
  wire \my_full_reg_n_0_[4] ;
  wire [3:0]nxt_rd_ptr;
  wire [3:0]nxt_wr_ptr;
  wire ofifo_rst;
  wire out_fifo;
  wire [7:0]out_fifo_0;
  wire out_fifo_1;
  wire [71:0]out_fifo_i_75__1;
  wire phy_data_wr_en;
  wire [63:0]\rd_ptr_reg[3]_0 ;
  wire \rd_ptr_reg_n_0_[0] ;
  wire \rd_ptr_reg_n_0_[1] ;
  wire \rd_ptr_reg_n_0_[2] ;
  wire \rd_ptr_reg_n_0_[3] ;
  wire [3:0]rd_ptr_timing;
  wire \rd_ptr_timing[3]_i_1__5_n_0 ;
  (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) wire wr_en;
  wire [3:0]wr_ptr;
  wire wr_ptr0;
  wire [3:0]wr_ptr_timing;
  wire [1:0]NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED;

  (* SOFT_HLUTNM = "soft_lutpair1023" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \entry_cnt[0]_i_1__4 
       (.I0(\entry_cnt_reg_n_0_[0] ),
        .O(\entry_cnt[0]_i_1__4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1022" *) 
  LUT5 #(
    .INIT(32'hAA6A5595)) 
    \entry_cnt[1]_i_1__4 
       (.I0(\entry_cnt_reg_n_0_[0] ),
        .I1(\my_empty_reg[7]_0 ),
        .I2(phy_data_wr_en),
        .I3(\my_full_reg_n_0_[4] ),
        .I4(\entry_cnt_reg_n_0_[1] ),
        .O(\entry_cnt[1]_i_1__4_n_0 ));
  LUT6 #(
    .INIT(64'hFF7F0080AAEA5515)) 
    \entry_cnt[2]_i_1__4 
       (.I0(\entry_cnt_reg_n_0_[0] ),
        .I1(\my_empty_reg[7]_0 ),
        .I2(phy_data_wr_en),
        .I3(\my_full_reg_n_0_[4] ),
        .I4(Q[0]),
        .I5(\entry_cnt_reg_n_0_[1] ),
        .O(\entry_cnt[2]_i_1__4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1023" *) 
  LUT5 #(
    .INIT(32'h7F80FE01)) 
    \entry_cnt[3]_i_1__4 
       (.I0(entry_cnt10_out__0),
        .I1(\entry_cnt_reg_n_0_[0] ),
        .I2(\entry_cnt_reg_n_0_[1] ),
        .I3(Q[1]),
        .I4(Q[0]),
        .O(\entry_cnt[3]_i_1__4_n_0 ));
  LUT4 #(
    .INIT(16'h5003)) 
    \entry_cnt[4]_i_1__4 
       (.I0(\my_full_reg_n_0_[4] ),
        .I1(\my_empty_reg_n_0_[7] ),
        .I2(\my_empty_reg[7]_0 ),
        .I3(phy_data_wr_en),
        .O(\entry_cnt[4]_i_1__4_n_0 ));
  LUT6 #(
    .INIT(64'h7FFF8000FFFE0001)) 
    \entry_cnt[4]_i_2__4 
       (.I0(\entry_cnt_reg_n_0_[1] ),
        .I1(\entry_cnt_reg_n_0_[0] ),
        .I2(entry_cnt10_out__0),
        .I3(Q[0]),
        .I4(Q[2]),
        .I5(Q[1]),
        .O(\entry_cnt[4]_i_2__4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1022" *) 
  LUT3 #(
    .INIT(8'h08)) 
    \entry_cnt[4]_i_3__4 
       (.I0(\my_empty_reg[7]_0 ),
        .I1(phy_data_wr_en),
        .I2(\my_full_reg_n_0_[4] ),
        .O(entry_cnt10_out__0));
  FDRE \entry_cnt_reg[0] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(\entry_cnt[4]_i_1__4_n_0 ),
        .D(\entry_cnt[0]_i_1__4_n_0 ),
        .Q(\entry_cnt_reg_n_0_[0] ),
        .R(ofifo_rst));
  FDRE \entry_cnt_reg[1] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(\entry_cnt[4]_i_1__4_n_0 ),
        .D(\entry_cnt[1]_i_1__4_n_0 ),
        .Q(\entry_cnt_reg_n_0_[1] ),
        .R(ofifo_rst));
  FDRE \entry_cnt_reg[2] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(\entry_cnt[4]_i_1__4_n_0 ),
        .D(\entry_cnt[2]_i_1__4_n_0 ),
        .Q(Q[0]),
        .R(ofifo_rst));
  FDRE \entry_cnt_reg[3] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(\entry_cnt[4]_i_1__4_n_0 ),
        .D(\entry_cnt[3]_i_1__4_n_0 ),
        .Q(Q[1]),
        .R(ofifo_rst));
  FDRE \entry_cnt_reg[4] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(\entry_cnt[4]_i_1__4_n_0 ),
        .D(\entry_cnt[4]_i_2__4_n_0 ),
        .Q(Q[2]),
        .R(ofifo_rst));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "0" *) 
  (* ram_slice_end = "5" *) 
  RAM32M mem_reg_0_15_0_5
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA({1'b0,1'b0}),
        .DIB({1'b0,1'b0}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA({mem_reg_0_15_0_5_n_0,mem_reg_0_15_0_5_n_1}),
        .DOB({mem_reg_0_15_0_5_n_2,mem_reg_0_15_0_5_n_3}),
        .DOC({mem_reg_0_15_0_5_n_4,mem_reg_0_15_0_5_n_5}),
        .DOD(NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED[1:0]),
        .WCLK(\entry_cnt_reg[4]_0 ),
        .WE(wr_en));
  LUT4 #(
    .INIT(16'h2700)) 
    mem_reg_0_15_0_5_i_1__4
       (.I0(\my_empty_reg[7]_0 ),
        .I1(\my_full_reg_n_0_[4] ),
        .I2(\my_empty_reg[1]_1 ),
        .I3(phy_data_wr_en),
        .O(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "12" *) 
  (* ram_slice_end = "17" *) 
  RAM32M mem_reg_0_15_12_17
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__1[5:4]),
        .DIB(out_fifo_i_75__1[7:6]),
        .DIC(out_fifo_i_75__1[9:8]),
        .DID({1'b0,1'b0}),
        .DOA({mem_reg_0_15_12_17_n_0,mem_reg_0_15_12_17_n_1}),
        .DOB({mem_reg_0_15_12_17_n_2,mem_reg_0_15_12_17_n_3}),
        .DOC(\rd_ptr_reg[3]_0 [1:0]),
        .DOD(NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED[1:0]),
        .WCLK(\entry_cnt_reg[4]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "18" *) 
  (* ram_slice_end = "23" *) 
  RAM32M mem_reg_0_15_18_23
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__1[11:10]),
        .DIB(out_fifo_i_75__1[13:12]),
        .DIC(out_fifo_i_75__1[15:14]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [3:2]),
        .DOB(\rd_ptr_reg[3]_0 [5:4]),
        .DOC(\rd_ptr_reg[3]_0 [7:6]),
        .DOD(NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED[1:0]),
        .WCLK(\entry_cnt_reg[4]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "24" *) 
  (* ram_slice_end = "29" *) 
  RAM32M mem_reg_0_15_24_29
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__1[17:16]),
        .DIB(out_fifo_i_75__1[19:18]),
        .DIC(out_fifo_i_75__1[21:20]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [9:8]),
        .DOB(\rd_ptr_reg[3]_0 [11:10]),
        .DOC(\rd_ptr_reg[3]_0 [13:12]),
        .DOD(NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED[1:0]),
        .WCLK(\entry_cnt_reg[4]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "30" *) 
  (* ram_slice_end = "35" *) 
  RAM32M mem_reg_0_15_30_35
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__1[23:22]),
        .DIB(out_fifo_i_75__1[25:24]),
        .DIC(out_fifo_i_75__1[27:26]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [15:14]),
        .DOB(\rd_ptr_reg[3]_0 [17:16]),
        .DOC(\rd_ptr_reg[3]_0 [19:18]),
        .DOD(NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED[1:0]),
        .WCLK(\entry_cnt_reg[4]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "36" *) 
  (* ram_slice_end = "41" *) 
  RAM32M mem_reg_0_15_36_41
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__1[29:28]),
        .DIB(out_fifo_i_75__1[31:30]),
        .DIC(out_fifo_i_75__1[33:32]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [21:20]),
        .DOB(\rd_ptr_reg[3]_0 [23:22]),
        .DOC(\rd_ptr_reg[3]_0 [25:24]),
        .DOD(NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED[1:0]),
        .WCLK(\entry_cnt_reg[4]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "42" *) 
  (* ram_slice_end = "47" *) 
  RAM32M mem_reg_0_15_42_47
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__1[35:34]),
        .DIB(out_fifo_i_75__1[37:36]),
        .DIC(out_fifo_i_75__1[39:38]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [27:26]),
        .DOB(\rd_ptr_reg[3]_0 [29:28]),
        .DOC(\rd_ptr_reg[3]_0 [31:30]),
        .DOD(NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED[1:0]),
        .WCLK(\entry_cnt_reg[4]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "48" *) 
  (* ram_slice_end = "53" *) 
  RAM32M mem_reg_0_15_48_53
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__1[41:40]),
        .DIB(out_fifo_i_75__1[43:42]),
        .DIC(out_fifo_i_75__1[45:44]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [33:32]),
        .DOB(\rd_ptr_reg[3]_0 [35:34]),
        .DOC(\rd_ptr_reg[3]_0 [37:36]),
        .DOD(NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED[1:0]),
        .WCLK(\entry_cnt_reg[4]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "54" *) 
  (* ram_slice_end = "59" *) 
  RAM32M mem_reg_0_15_54_59
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__1[47:46]),
        .DIB(out_fifo_i_75__1[49:48]),
        .DIC(out_fifo_i_75__1[51:50]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [39:38]),
        .DOB(\rd_ptr_reg[3]_0 [41:40]),
        .DOC(\rd_ptr_reg[3]_0 [43:42]),
        .DOD(NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED[1:0]),
        .WCLK(\entry_cnt_reg[4]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "60" *) 
  (* ram_slice_end = "65" *) 
  RAM32M mem_reg_0_15_60_65
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__1[53:52]),
        .DIB(out_fifo_i_75__1[55:54]),
        .DIC(out_fifo_i_75__1[57:56]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [45:44]),
        .DOB(\rd_ptr_reg[3]_0 [47:46]),
        .DOC(\rd_ptr_reg[3]_0 [49:48]),
        .DOD(NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED[1:0]),
        .WCLK(\entry_cnt_reg[4]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "66" *) 
  (* ram_slice_end = "71" *) 
  RAM32M mem_reg_0_15_66_71
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__1[59:58]),
        .DIB(out_fifo_i_75__1[61:60]),
        .DIC(out_fifo_i_75__1[63:62]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [51:50]),
        .DOB(\rd_ptr_reg[3]_0 [53:52]),
        .DOC(\rd_ptr_reg[3]_0 [55:54]),
        .DOD(NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED[1:0]),
        .WCLK(\entry_cnt_reg[4]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "6" *) 
  (* ram_slice_end = "11" *) 
  RAM32M mem_reg_0_15_6_11
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA({1'b0,1'b0}),
        .DIB(out_fifo_i_75__1[1:0]),
        .DIC(out_fifo_i_75__1[3:2]),
        .DID({1'b0,1'b0}),
        .DOA({mem_reg_0_15_6_11_n_0,mem_reg_0_15_6_11_n_1}),
        .DOB({mem_reg_0_15_6_11_n_2,mem_reg_0_15_6_11_n_3}),
        .DOC({mem_reg_0_15_6_11_n_4,mem_reg_0_15_6_11_n_5}),
        .DOD(NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED[1:0]),
        .WCLK(\entry_cnt_reg[4]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "72" *) 
  (* ram_slice_end = "77" *) 
  RAM32M mem_reg_0_15_72_77
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__1[65:64]),
        .DIB(out_fifo_i_75__1[67:66]),
        .DIC(out_fifo_i_75__1[69:68]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [57:56]),
        .DOB(\rd_ptr_reg[3]_0 [59:58]),
        .DOC(\rd_ptr_reg[3]_0 [61:60]),
        .DOD(NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED[1:0]),
        .WCLK(\entry_cnt_reg[4]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "78" *) 
  (* ram_slice_end = "79" *) 
  RAM32M mem_reg_0_15_78_79
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__1[71:70]),
        .DIB({1'b0,1'b0}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [63:62]),
        .DOB(NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED[1:0]),
        .DOC(NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED[1:0]),
        .DOD(NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED[1:0]),
        .WCLK(\entry_cnt_reg[4]_0 ),
        .WE(wr_en));
  LUT6 #(
    .INIT(64'hFFFFFFFFF701F700)) 
    \my_empty[1]_i_1__5 
       (.I0(\my_empty_reg[7]_0 ),
        .I1(phy_data_wr_en),
        .I2(\my_full_reg_n_0_[4] ),
        .I3(\my_empty_reg[1]_1 ),
        .I4(my_empty0),
        .I5(ofifo_rst),
        .O(\my_empty[1]_i_1__5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFF701F700)) 
    \my_empty[7]_i_1__5 
       (.I0(\my_empty_reg[7]_0 ),
        .I1(phy_data_wr_en),
        .I2(\my_full_reg_n_0_[4] ),
        .I3(\my_empty_reg_n_0_[7] ),
        .I4(my_empty0),
        .I5(ofifo_rst),
        .O(\my_empty[7]_i_1__5_n_0 ));
  LUT5 #(
    .INIT(32'h4A400D08)) 
    \my_empty[7]_i_2__5 
       (.I0(wr_ptr_timing[2]),
        .I1(\my_empty[7]_i_3__5_n_0 ),
        .I2(wr_ptr_timing[3]),
        .I3(\my_empty[7]_i_4__5_n_0 ),
        .I4(\rd_ptr_reg_n_0_[2] ),
        .O(my_empty0));
  (* SOFT_HLUTNM = "soft_lutpair1025" *) 
  LUT5 #(
    .INIT(32'h00000040)) 
    \my_empty[7]_i_3__5 
       (.I0(wr_ptr_timing[1]),
        .I1(\rd_ptr_reg_n_0_[0] ),
        .I2(\rd_ptr_reg_n_0_[1] ),
        .I3(\rd_ptr_reg_n_0_[3] ),
        .I4(wr_ptr_timing[0]),
        .O(\my_empty[7]_i_3__5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1025" *) 
  LUT5 #(
    .INIT(32'h84210842)) 
    \my_empty[7]_i_4__5 
       (.I0(wr_ptr_timing[0]),
        .I1(wr_ptr_timing[1]),
        .I2(\rd_ptr_reg_n_0_[0] ),
        .I3(\rd_ptr_reg_n_0_[1] ),
        .I4(\rd_ptr_reg_n_0_[3] ),
        .O(\my_empty[7]_i_4__5_n_0 ));
  (* syn_maxfan = "3" *) 
  FDRE \my_empty_reg[1] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(1'b1),
        .D(\my_empty[1]_i_1__5_n_0 ),
        .Q(\my_empty_reg[1]_1 ),
        .R(1'b0));
  (* syn_maxfan = "3" *) 
  FDRE \my_empty_reg[7] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(1'b1),
        .D(\my_empty[7]_i_1__5_n_0 ),
        .Q(\my_empty_reg_n_0_[7] ),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h00000000FFFC0080)) 
    \my_full[4]_i_1__5 
       (.I0(my_full0),
        .I1(phy_data_wr_en),
        .I2(\my_empty_reg[7]_0 ),
        .I3(\my_empty_reg_n_0_[7] ),
        .I4(\my_full_reg_n_0_[4] ),
        .I5(ofifo_rst),
        .O(\my_full[4]_i_1__5_n_0 ));
  LUT5 #(
    .INIT(32'h4A400D08)) 
    \my_full[4]_i_2__5 
       (.I0(rd_ptr_timing[2]),
        .I1(\my_full[4]_i_3__5_n_0 ),
        .I2(rd_ptr_timing[3]),
        .I3(\my_full[4]_i_4__5_n_0 ),
        .I4(wr_ptr[2]),
        .O(my_full0));
  (* SOFT_HLUTNM = "soft_lutpair1024" *) 
  LUT5 #(
    .INIT(32'h00000040)) 
    \my_full[4]_i_3__5 
       (.I0(rd_ptr_timing[1]),
        .I1(wr_ptr[0]),
        .I2(wr_ptr[1]),
        .I3(wr_ptr[3]),
        .I4(rd_ptr_timing[0]),
        .O(\my_full[4]_i_3__5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1024" *) 
  LUT5 #(
    .INIT(32'h84210842)) 
    \my_full[4]_i_4__5 
       (.I0(rd_ptr_timing[0]),
        .I1(rd_ptr_timing[1]),
        .I2(wr_ptr[0]),
        .I3(wr_ptr[1]),
        .I4(wr_ptr[3]),
        .O(\my_full[4]_i_4__5_n_0 ));
  (* syn_maxfan = "3" *) 
  FDRE \my_full_reg[4] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(1'b1),
        .D(\my_full[4]_i_1__5_n_0 ),
        .Q(\my_full_reg_n_0_[4] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair1026" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_10__4
       (.I0(out_fifo_1),
        .I1(out_fifo_0[7]),
        .I2(mem_reg_0_15_12_17_n_2),
        .I3(\my_empty_reg[1]_1 ),
        .O(D1[7]));
  (* SOFT_HLUTNM = "soft_lutpair1033" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_11__4
       (.I0(out_fifo_1),
        .I1(out_fifo_0[6]),
        .I2(mem_reg_0_15_12_17_n_3),
        .I3(\my_empty_reg[1]_1 ),
        .O(D1[6]));
  (* SOFT_HLUTNM = "soft_lutpair1028" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_12__4
       (.I0(out_fifo_1),
        .I1(out_fifo_0[5]),
        .I2(mem_reg_0_15_12_17_n_0),
        .I3(\my_empty_reg[1]_1 ),
        .O(D1[5]));
  (* SOFT_HLUTNM = "soft_lutpair1031" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_13__4
       (.I0(out_fifo_1),
        .I1(out_fifo_0[4]),
        .I2(mem_reg_0_15_12_17_n_1),
        .I3(\my_empty_reg[1]_1 ),
        .O(D1[4]));
  (* SOFT_HLUTNM = "soft_lutpair1029" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_14__4
       (.I0(out_fifo_1),
        .I1(out_fifo_0[3]),
        .I2(mem_reg_0_15_6_11_n_4),
        .I3(\my_empty_reg[1]_1 ),
        .O(D1[3]));
  (* SOFT_HLUTNM = "soft_lutpair1030" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_15__4
       (.I0(out_fifo_1),
        .I1(out_fifo_0[2]),
        .I2(mem_reg_0_15_6_11_n_5),
        .I3(\my_empty_reg[1]_1 ),
        .O(D1[2]));
  (* SOFT_HLUTNM = "soft_lutpair1027" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_16__4
       (.I0(out_fifo),
        .I1(out_fifo_0[1]),
        .I2(mem_reg_0_15_6_11_n_2),
        .I3(\my_empty_reg[1]_1 ),
        .O(D1[1]));
  (* SOFT_HLUTNM = "soft_lutpair1035" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_17__4
       (.I0(out_fifo),
        .I1(out_fifo_0[0]),
        .I2(mem_reg_0_15_6_11_n_3),
        .I3(\my_empty_reg[1]_1 ),
        .O(D1[0]));
  LUT3 #(
    .INIT(8'h0D)) 
    out_fifo_i_1__5
       (.I0(\my_empty_reg[1]_1 ),
        .I1(phy_data_wr_en),
        .I2(\my_empty_reg[7]_0 ),
        .O(\my_empty_reg[1]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1031" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_2__3
       (.I0(mem_reg_0_15_6_11_n_0),
        .I1(\my_empty_reg[1]_1 ),
        .O(D0[7]));
  (* SOFT_HLUTNM = "soft_lutpair1027" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_3__3
       (.I0(mem_reg_0_15_6_11_n_1),
        .I1(\my_empty_reg[1]_1 ),
        .O(D0[6]));
  (* SOFT_HLUTNM = "soft_lutpair1033" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_4__3
       (.I0(mem_reg_0_15_0_5_n_4),
        .I1(\my_empty_reg[1]_1 ),
        .O(D0[5]));
  (* SOFT_HLUTNM = "soft_lutpair1029" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_5__3
       (.I0(mem_reg_0_15_0_5_n_5),
        .I1(\my_empty_reg[1]_1 ),
        .O(D0[4]));
  (* SOFT_HLUTNM = "soft_lutpair1030" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_6__3
       (.I0(mem_reg_0_15_0_5_n_2),
        .I1(\my_empty_reg[1]_1 ),
        .O(D0[3]));
  (* SOFT_HLUTNM = "soft_lutpair1026" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_7__3
       (.I0(mem_reg_0_15_0_5_n_3),
        .I1(\my_empty_reg[1]_1 ),
        .O(D0[2]));
  (* SOFT_HLUTNM = "soft_lutpair1035" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_8__3
       (.I0(mem_reg_0_15_0_5_n_0),
        .I1(\my_empty_reg[1]_1 ),
        .O(D0[1]));
  (* SOFT_HLUTNM = "soft_lutpair1028" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_9__3
       (.I0(mem_reg_0_15_0_5_n_1),
        .I1(\my_empty_reg[1]_1 ),
        .O(D0[0]));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[0] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(\rd_ptr_timing[3]_i_1__5_n_0 ),
        .D(nxt_rd_ptr[0]),
        .Q(\rd_ptr_reg_n_0_[0] ),
        .R(ofifo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[1] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(\rd_ptr_timing[3]_i_1__5_n_0 ),
        .D(nxt_rd_ptr[1]),
        .Q(\rd_ptr_reg_n_0_[1] ),
        .R(ofifo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[2] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(\rd_ptr_timing[3]_i_1__5_n_0 ),
        .D(nxt_rd_ptr[2]),
        .Q(\rd_ptr_reg_n_0_[2] ),
        .R(ofifo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[3] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(\rd_ptr_timing[3]_i_1__5_n_0 ),
        .D(nxt_rd_ptr[3]),
        .Q(\rd_ptr_reg_n_0_[3] ),
        .R(ofifo_rst));
  (* SOFT_HLUTNM = "soft_lutpair1037" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rd_ptr_timing[0]_i_1__11 
       (.I0(\rd_ptr_reg_n_0_[3] ),
        .I1(\rd_ptr_reg_n_0_[0] ),
        .O(nxt_rd_ptr[0]));
  (* SOFT_HLUTNM = "soft_lutpair1037" *) 
  LUT3 #(
    .INIT(8'hB4)) 
    \rd_ptr_timing[1]_i_1__11 
       (.I0(\rd_ptr_reg_n_0_[3] ),
        .I1(\rd_ptr_reg_n_0_[0] ),
        .I2(\rd_ptr_reg_n_0_[1] ),
        .O(nxt_rd_ptr[1]));
  (* SOFT_HLUTNM = "soft_lutpair1034" *) 
  LUT4 #(
    .INIT(16'hAA6A)) 
    \rd_ptr_timing[2]_i_1__5 
       (.I0(\rd_ptr_reg_n_0_[2] ),
        .I1(\rd_ptr_reg_n_0_[0] ),
        .I2(\rd_ptr_reg_n_0_[1] ),
        .I3(\rd_ptr_reg_n_0_[3] ),
        .O(nxt_rd_ptr[2]));
  LUT2 #(
    .INIT(4'h1)) 
    \rd_ptr_timing[3]_i_1__5 
       (.I0(\my_empty_reg[7]_0 ),
        .I1(\my_empty_reg_n_0_[7] ),
        .O(\rd_ptr_timing[3]_i_1__5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1034" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \rd_ptr_timing[3]_i_2__5 
       (.I0(\rd_ptr_reg_n_0_[3] ),
        .I1(\rd_ptr_reg_n_0_[1] ),
        .I2(\rd_ptr_reg_n_0_[0] ),
        .I3(\rd_ptr_reg_n_0_[2] ),
        .O(nxt_rd_ptr[3]));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[0] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(\rd_ptr_timing[3]_i_1__5_n_0 ),
        .D(nxt_rd_ptr[0]),
        .Q(rd_ptr_timing[0]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[1] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(\rd_ptr_timing[3]_i_1__5_n_0 ),
        .D(nxt_rd_ptr[1]),
        .Q(rd_ptr_timing[1]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[2] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(\rd_ptr_timing[3]_i_1__5_n_0 ),
        .D(nxt_rd_ptr[2]),
        .Q(rd_ptr_timing[2]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[3] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(\rd_ptr_timing[3]_i_1__5_n_0 ),
        .D(nxt_rd_ptr[3]),
        .Q(rd_ptr_timing[3]),
        .R(ofifo_rst));
  (* SOFT_HLUTNM = "soft_lutpair1036" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \wr_ptr[0]_i_1__11 
       (.I0(wr_ptr[3]),
        .I1(wr_ptr[0]),
        .O(nxt_wr_ptr[0]));
  (* SOFT_HLUTNM = "soft_lutpair1036" *) 
  LUT3 #(
    .INIT(8'hB4)) 
    \wr_ptr[1]_i_1__11 
       (.I0(wr_ptr[3]),
        .I1(wr_ptr[0]),
        .I2(wr_ptr[1]),
        .O(nxt_wr_ptr[1]));
  (* SOFT_HLUTNM = "soft_lutpair1032" *) 
  LUT4 #(
    .INIT(16'hAA6A)) 
    \wr_ptr[2]_i_1__5 
       (.I0(wr_ptr[2]),
        .I1(wr_ptr[0]),
        .I2(wr_ptr[1]),
        .I3(wr_ptr[3]),
        .O(nxt_wr_ptr[2]));
  LUT4 #(
    .INIT(16'h082A)) 
    \wr_ptr[3]_i_1__5 
       (.I0(phy_data_wr_en),
        .I1(\my_empty_reg[7]_0 ),
        .I2(\my_full_reg_n_0_[4] ),
        .I3(\my_empty_reg_n_0_[7] ),
        .O(wr_ptr0));
  (* SOFT_HLUTNM = "soft_lutpair1032" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \wr_ptr[3]_i_2__4 
       (.I0(wr_ptr[3]),
        .I1(wr_ptr[1]),
        .I2(wr_ptr[0]),
        .I3(wr_ptr[2]),
        .O(nxt_wr_ptr[3]));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[0] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[0]),
        .Q(wr_ptr[0]),
        .R(ofifo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[1] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[1]),
        .Q(wr_ptr[1]),
        .R(ofifo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[2] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[2]),
        .Q(wr_ptr[2]),
        .R(ofifo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[3] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[3]),
        .Q(wr_ptr[3]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[0] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[0]),
        .Q(wr_ptr_timing[0]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[1] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[1]),
        .Q(wr_ptr_timing[1]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[2] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[2]),
        .Q(wr_ptr_timing[2]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[3] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[3]),
        .Q(wr_ptr_timing[3]),
        .R(ofifo_rst));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_of_pre_fifo" *) 
module mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_21
   (\my_empty_reg[1]_0 ,
    \my_empty_reg[1]_1 ,
    D8,
    D0,
    \rd_ptr_reg[3]_0 ,
    Q,
    ofifo_rst,
    \wr_ptr_timing_reg[3]_0 ,
    \my_empty_reg[7]_0 ,
    phy_data_wr_en,
    out_fifo,
    out_fifo_0,
    out_fifo_1,
    out_fifo_i_75__0);
  output \my_empty_reg[1]_0 ;
  output \my_empty_reg[1]_1 ;
  output [7:0]D8;
  output [7:0]D0;
  output [63:0]\rd_ptr_reg[3]_0 ;
  output [2:0]Q;
  input ofifo_rst;
  input \wr_ptr_timing_reg[3]_0 ;
  input \my_empty_reg[7]_0 ;
  input phy_data_wr_en;
  input out_fifo;
  input [7:0]out_fifo_0;
  input out_fifo_1;
  input [71:0]out_fifo_i_75__0;

  wire [7:0]D0;
  wire [7:0]D8;
  wire [2:0]Q;
  wire entry_cnt10_out__0;
  wire \entry_cnt[0]_i_1__3_n_0 ;
  wire \entry_cnt[1]_i_1__3_n_0 ;
  wire \entry_cnt[2]_i_1__3_n_0 ;
  wire \entry_cnt[3]_i_1__3_n_0 ;
  wire \entry_cnt[4]_i_1__3_n_0 ;
  wire \entry_cnt[4]_i_2__3_n_0 ;
  wire \entry_cnt_reg_n_0_[0] ;
  wire \entry_cnt_reg_n_0_[1] ;
  wire mem_reg_0_15_0_5_n_0;
  wire mem_reg_0_15_0_5_n_1;
  wire mem_reg_0_15_0_5_n_2;
  wire mem_reg_0_15_0_5_n_3;
  wire mem_reg_0_15_0_5_n_4;
  wire mem_reg_0_15_0_5_n_5;
  wire mem_reg_0_15_60_65_n_4;
  wire mem_reg_0_15_60_65_n_5;
  wire mem_reg_0_15_66_71_n_0;
  wire mem_reg_0_15_66_71_n_1;
  wire mem_reg_0_15_66_71_n_2;
  wire mem_reg_0_15_66_71_n_3;
  wire mem_reg_0_15_66_71_n_4;
  wire mem_reg_0_15_66_71_n_5;
  wire mem_reg_0_15_6_11_n_0;
  wire mem_reg_0_15_6_11_n_1;
  wire my_empty0;
  wire \my_empty[1]_i_1__4_n_0 ;
  wire \my_empty[7]_i_1__4_n_0 ;
  wire \my_empty[7]_i_3__4_n_0 ;
  wire \my_empty[7]_i_4__4_n_0 ;
  wire \my_empty_reg[1]_0 ;
  wire \my_empty_reg[1]_1 ;
  wire \my_empty_reg[7]_0 ;
  wire \my_empty_reg_n_0_[7] ;
  wire my_full0;
  wire \my_full[4]_i_1__4_n_0 ;
  wire \my_full[4]_i_3__4_n_0 ;
  wire \my_full[4]_i_4__4_n_0 ;
  wire \my_full_reg_n_0_[4] ;
  wire [3:0]nxt_rd_ptr;
  wire [3:0]nxt_wr_ptr;
  wire ofifo_rst;
  wire out_fifo;
  wire [7:0]out_fifo_0;
  wire out_fifo_1;
  wire [71:0]out_fifo_i_75__0;
  wire phy_data_wr_en;
  wire [63:0]\rd_ptr_reg[3]_0 ;
  wire \rd_ptr_reg_n_0_[0] ;
  wire \rd_ptr_reg_n_0_[1] ;
  wire \rd_ptr_reg_n_0_[2] ;
  wire \rd_ptr_reg_n_0_[3] ;
  wire [3:0]rd_ptr_timing;
  wire \rd_ptr_timing[3]_i_1__4_n_0 ;
  (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) wire wr_en;
  wire [3:0]wr_ptr;
  wire wr_ptr0;
  wire [3:0]wr_ptr_timing;
  wire \wr_ptr_timing_reg[3]_0 ;
  wire [1:0]NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED;

  (* SOFT_HLUTNM = "soft_lutpair975" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \entry_cnt[0]_i_1__3 
       (.I0(\entry_cnt_reg_n_0_[0] ),
        .O(\entry_cnt[0]_i_1__3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair972" *) 
  LUT5 #(
    .INIT(32'hAA6A5595)) 
    \entry_cnt[1]_i_1__3 
       (.I0(\entry_cnt_reg_n_0_[0] ),
        .I1(\my_empty_reg[7]_0 ),
        .I2(phy_data_wr_en),
        .I3(\my_full_reg_n_0_[4] ),
        .I4(\entry_cnt_reg_n_0_[1] ),
        .O(\entry_cnt[1]_i_1__3_n_0 ));
  LUT6 #(
    .INIT(64'hFF7F0080AAEA5515)) 
    \entry_cnt[2]_i_1__3 
       (.I0(\entry_cnt_reg_n_0_[0] ),
        .I1(\my_empty_reg[7]_0 ),
        .I2(phy_data_wr_en),
        .I3(\my_full_reg_n_0_[4] ),
        .I4(Q[0]),
        .I5(\entry_cnt_reg_n_0_[1] ),
        .O(\entry_cnt[2]_i_1__3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair975" *) 
  LUT5 #(
    .INIT(32'h7F80FE01)) 
    \entry_cnt[3]_i_1__3 
       (.I0(entry_cnt10_out__0),
        .I1(\entry_cnt_reg_n_0_[0] ),
        .I2(\entry_cnt_reg_n_0_[1] ),
        .I3(Q[1]),
        .I4(Q[0]),
        .O(\entry_cnt[3]_i_1__3_n_0 ));
  LUT4 #(
    .INIT(16'h5003)) 
    \entry_cnt[4]_i_1__3 
       (.I0(\my_full_reg_n_0_[4] ),
        .I1(\my_empty_reg_n_0_[7] ),
        .I2(\my_empty_reg[7]_0 ),
        .I3(phy_data_wr_en),
        .O(\entry_cnt[4]_i_1__3_n_0 ));
  LUT6 #(
    .INIT(64'h7FFF8000FFFE0001)) 
    \entry_cnt[4]_i_2__3 
       (.I0(\entry_cnt_reg_n_0_[1] ),
        .I1(\entry_cnt_reg_n_0_[0] ),
        .I2(entry_cnt10_out__0),
        .I3(Q[0]),
        .I4(Q[2]),
        .I5(Q[1]),
        .O(\entry_cnt[4]_i_2__3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair972" *) 
  LUT3 #(
    .INIT(8'h08)) 
    \entry_cnt[4]_i_3__3 
       (.I0(\my_empty_reg[7]_0 ),
        .I1(phy_data_wr_en),
        .I2(\my_full_reg_n_0_[4] ),
        .O(entry_cnt10_out__0));
  FDRE \entry_cnt_reg[0] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(\entry_cnt[4]_i_1__3_n_0 ),
        .D(\entry_cnt[0]_i_1__3_n_0 ),
        .Q(\entry_cnt_reg_n_0_[0] ),
        .R(ofifo_rst));
  FDRE \entry_cnt_reg[1] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(\entry_cnt[4]_i_1__3_n_0 ),
        .D(\entry_cnt[1]_i_1__3_n_0 ),
        .Q(\entry_cnt_reg_n_0_[1] ),
        .R(ofifo_rst));
  FDRE \entry_cnt_reg[2] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(\entry_cnt[4]_i_1__3_n_0 ),
        .D(\entry_cnt[2]_i_1__3_n_0 ),
        .Q(Q[0]),
        .R(ofifo_rst));
  FDRE \entry_cnt_reg[3] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(\entry_cnt[4]_i_1__3_n_0 ),
        .D(\entry_cnt[3]_i_1__3_n_0 ),
        .Q(Q[1]),
        .R(ofifo_rst));
  FDRE \entry_cnt_reg[4] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(\entry_cnt[4]_i_1__3_n_0 ),
        .D(\entry_cnt[4]_i_2__3_n_0 ),
        .Q(Q[2]),
        .R(ofifo_rst));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "0" *) 
  (* ram_slice_end = "5" *) 
  RAM32M mem_reg_0_15_0_5
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__0[1:0]),
        .DIB(out_fifo_i_75__0[3:2]),
        .DIC(out_fifo_i_75__0[5:4]),
        .DID({1'b0,1'b0}),
        .DOA({mem_reg_0_15_0_5_n_0,mem_reg_0_15_0_5_n_1}),
        .DOB({mem_reg_0_15_0_5_n_2,mem_reg_0_15_0_5_n_3}),
        .DOC({mem_reg_0_15_0_5_n_4,mem_reg_0_15_0_5_n_5}),
        .DOD(NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED[1:0]),
        .WCLK(\wr_ptr_timing_reg[3]_0 ),
        .WE(wr_en));
  LUT4 #(
    .INIT(16'h2700)) 
    mem_reg_0_15_0_5_i_1__3
       (.I0(\my_empty_reg[7]_0 ),
        .I1(\my_full_reg_n_0_[4] ),
        .I2(\my_empty_reg[1]_1 ),
        .I3(phy_data_wr_en),
        .O(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "12" *) 
  (* ram_slice_end = "17" *) 
  RAM32M mem_reg_0_15_12_17
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__0[13:12]),
        .DIB(out_fifo_i_75__0[15:14]),
        .DIC(out_fifo_i_75__0[17:16]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [5:4]),
        .DOB(\rd_ptr_reg[3]_0 [7:6]),
        .DOC(\rd_ptr_reg[3]_0 [9:8]),
        .DOD(NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED[1:0]),
        .WCLK(\wr_ptr_timing_reg[3]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "18" *) 
  (* ram_slice_end = "23" *) 
  RAM32M mem_reg_0_15_18_23
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__0[19:18]),
        .DIB(out_fifo_i_75__0[21:20]),
        .DIC(out_fifo_i_75__0[23:22]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [11:10]),
        .DOB(\rd_ptr_reg[3]_0 [13:12]),
        .DOC(\rd_ptr_reg[3]_0 [15:14]),
        .DOD(NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED[1:0]),
        .WCLK(\wr_ptr_timing_reg[3]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "24" *) 
  (* ram_slice_end = "29" *) 
  RAM32M mem_reg_0_15_24_29
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__0[25:24]),
        .DIB(out_fifo_i_75__0[27:26]),
        .DIC(out_fifo_i_75__0[29:28]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [17:16]),
        .DOB(\rd_ptr_reg[3]_0 [19:18]),
        .DOC(\rd_ptr_reg[3]_0 [21:20]),
        .DOD(NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED[1:0]),
        .WCLK(\wr_ptr_timing_reg[3]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "30" *) 
  (* ram_slice_end = "35" *) 
  RAM32M mem_reg_0_15_30_35
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__0[31:30]),
        .DIB(out_fifo_i_75__0[33:32]),
        .DIC(out_fifo_i_75__0[35:34]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [23:22]),
        .DOB(\rd_ptr_reg[3]_0 [25:24]),
        .DOC(\rd_ptr_reg[3]_0 [27:26]),
        .DOD(NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED[1:0]),
        .WCLK(\wr_ptr_timing_reg[3]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "36" *) 
  (* ram_slice_end = "41" *) 
  RAM32M mem_reg_0_15_36_41
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__0[37:36]),
        .DIB(out_fifo_i_75__0[39:38]),
        .DIC(out_fifo_i_75__0[41:40]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [29:28]),
        .DOB(\rd_ptr_reg[3]_0 [31:30]),
        .DOC(\rd_ptr_reg[3]_0 [33:32]),
        .DOD(NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED[1:0]),
        .WCLK(\wr_ptr_timing_reg[3]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "42" *) 
  (* ram_slice_end = "47" *) 
  RAM32M mem_reg_0_15_42_47
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__0[43:42]),
        .DIB(out_fifo_i_75__0[45:44]),
        .DIC(out_fifo_i_75__0[47:46]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [35:34]),
        .DOB(\rd_ptr_reg[3]_0 [37:36]),
        .DOC(\rd_ptr_reg[3]_0 [39:38]),
        .DOD(NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED[1:0]),
        .WCLK(\wr_ptr_timing_reg[3]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "48" *) 
  (* ram_slice_end = "53" *) 
  RAM32M mem_reg_0_15_48_53
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__0[49:48]),
        .DIB(out_fifo_i_75__0[51:50]),
        .DIC(out_fifo_i_75__0[53:52]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [41:40]),
        .DOB(\rd_ptr_reg[3]_0 [43:42]),
        .DOC(\rd_ptr_reg[3]_0 [45:44]),
        .DOD(NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED[1:0]),
        .WCLK(\wr_ptr_timing_reg[3]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "54" *) 
  (* ram_slice_end = "59" *) 
  RAM32M mem_reg_0_15_54_59
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__0[55:54]),
        .DIB(out_fifo_i_75__0[57:56]),
        .DIC(out_fifo_i_75__0[59:58]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [47:46]),
        .DOB(\rd_ptr_reg[3]_0 [49:48]),
        .DOC(\rd_ptr_reg[3]_0 [51:50]),
        .DOD(NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED[1:0]),
        .WCLK(\wr_ptr_timing_reg[3]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "60" *) 
  (* ram_slice_end = "65" *) 
  RAM32M mem_reg_0_15_60_65
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__0[61:60]),
        .DIB(out_fifo_i_75__0[63:62]),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [53:52]),
        .DOB(\rd_ptr_reg[3]_0 [55:54]),
        .DOC({mem_reg_0_15_60_65_n_4,mem_reg_0_15_60_65_n_5}),
        .DOD(NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED[1:0]),
        .WCLK(\wr_ptr_timing_reg[3]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "66" *) 
  (* ram_slice_end = "71" *) 
  RAM32M mem_reg_0_15_66_71
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA({1'b0,1'b0}),
        .DIB({1'b0,1'b0}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA({mem_reg_0_15_66_71_n_0,mem_reg_0_15_66_71_n_1}),
        .DOB({mem_reg_0_15_66_71_n_2,mem_reg_0_15_66_71_n_3}),
        .DOC({mem_reg_0_15_66_71_n_4,mem_reg_0_15_66_71_n_5}),
        .DOD(NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED[1:0]),
        .WCLK(\wr_ptr_timing_reg[3]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "6" *) 
  (* ram_slice_end = "11" *) 
  RAM32M mem_reg_0_15_6_11
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__0[7:6]),
        .DIB(out_fifo_i_75__0[9:8]),
        .DIC(out_fifo_i_75__0[11:10]),
        .DID({1'b0,1'b0}),
        .DOA({mem_reg_0_15_6_11_n_0,mem_reg_0_15_6_11_n_1}),
        .DOB(\rd_ptr_reg[3]_0 [1:0]),
        .DOC(\rd_ptr_reg[3]_0 [3:2]),
        .DOD(NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED[1:0]),
        .WCLK(\wr_ptr_timing_reg[3]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "72" *) 
  (* ram_slice_end = "77" *) 
  RAM32M mem_reg_0_15_72_77
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__0[65:64]),
        .DIB(out_fifo_i_75__0[67:66]),
        .DIC(out_fifo_i_75__0[69:68]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [57:56]),
        .DOB(\rd_ptr_reg[3]_0 [59:58]),
        .DOC(\rd_ptr_reg[3]_0 [61:60]),
        .DOD(NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED[1:0]),
        .WCLK(\wr_ptr_timing_reg[3]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "78" *) 
  (* ram_slice_end = "79" *) 
  RAM32M mem_reg_0_15_78_79
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__0[71:70]),
        .DIB({1'b0,1'b0}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [63:62]),
        .DOB(NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED[1:0]),
        .DOC(NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED[1:0]),
        .DOD(NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED[1:0]),
        .WCLK(\wr_ptr_timing_reg[3]_0 ),
        .WE(wr_en));
  LUT6 #(
    .INIT(64'hFFFFFFFFF701F700)) 
    \my_empty[1]_i_1__4 
       (.I0(\my_empty_reg[7]_0 ),
        .I1(phy_data_wr_en),
        .I2(\my_full_reg_n_0_[4] ),
        .I3(\my_empty_reg[1]_1 ),
        .I4(my_empty0),
        .I5(ofifo_rst),
        .O(\my_empty[1]_i_1__4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFF701F700)) 
    \my_empty[7]_i_1__4 
       (.I0(\my_empty_reg[7]_0 ),
        .I1(phy_data_wr_en),
        .I2(\my_full_reg_n_0_[4] ),
        .I3(\my_empty_reg_n_0_[7] ),
        .I4(my_empty0),
        .I5(ofifo_rst),
        .O(\my_empty[7]_i_1__4_n_0 ));
  LUT5 #(
    .INIT(32'h4A400D08)) 
    \my_empty[7]_i_2__4 
       (.I0(wr_ptr_timing[2]),
        .I1(\my_empty[7]_i_3__4_n_0 ),
        .I2(wr_ptr_timing[3]),
        .I3(\my_empty[7]_i_4__4_n_0 ),
        .I4(\rd_ptr_reg_n_0_[2] ),
        .O(my_empty0));
  (* SOFT_HLUTNM = "soft_lutpair974" *) 
  LUT5 #(
    .INIT(32'h00000040)) 
    \my_empty[7]_i_3__4 
       (.I0(wr_ptr_timing[1]),
        .I1(\rd_ptr_reg_n_0_[0] ),
        .I2(\rd_ptr_reg_n_0_[1] ),
        .I3(\rd_ptr_reg_n_0_[3] ),
        .I4(wr_ptr_timing[0]),
        .O(\my_empty[7]_i_3__4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair974" *) 
  LUT5 #(
    .INIT(32'h84210842)) 
    \my_empty[7]_i_4__4 
       (.I0(wr_ptr_timing[0]),
        .I1(wr_ptr_timing[1]),
        .I2(\rd_ptr_reg_n_0_[0] ),
        .I3(\rd_ptr_reg_n_0_[1] ),
        .I4(\rd_ptr_reg_n_0_[3] ),
        .O(\my_empty[7]_i_4__4_n_0 ));
  (* syn_maxfan = "3" *) 
  FDRE \my_empty_reg[1] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(1'b1),
        .D(\my_empty[1]_i_1__4_n_0 ),
        .Q(\my_empty_reg[1]_1 ),
        .R(1'b0));
  (* syn_maxfan = "3" *) 
  FDRE \my_empty_reg[7] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(1'b1),
        .D(\my_empty[7]_i_1__4_n_0 ),
        .Q(\my_empty_reg_n_0_[7] ),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h00000000FFFC0080)) 
    \my_full[4]_i_1__4 
       (.I0(my_full0),
        .I1(phy_data_wr_en),
        .I2(\my_empty_reg[7]_0 ),
        .I3(\my_empty_reg_n_0_[7] ),
        .I4(\my_full_reg_n_0_[4] ),
        .I5(ofifo_rst),
        .O(\my_full[4]_i_1__4_n_0 ));
  LUT5 #(
    .INIT(32'h4A400D08)) 
    \my_full[4]_i_2__4 
       (.I0(rd_ptr_timing[2]),
        .I1(\my_full[4]_i_3__4_n_0 ),
        .I2(rd_ptr_timing[3]),
        .I3(\my_full[4]_i_4__4_n_0 ),
        .I4(wr_ptr[2]),
        .O(my_full0));
  (* SOFT_HLUTNM = "soft_lutpair973" *) 
  LUT5 #(
    .INIT(32'h00000040)) 
    \my_full[4]_i_3__4 
       (.I0(rd_ptr_timing[1]),
        .I1(wr_ptr[0]),
        .I2(wr_ptr[1]),
        .I3(wr_ptr[3]),
        .I4(rd_ptr_timing[0]),
        .O(\my_full[4]_i_3__4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair973" *) 
  LUT5 #(
    .INIT(32'h84210842)) 
    \my_full[4]_i_4__4 
       (.I0(rd_ptr_timing[0]),
        .I1(rd_ptr_timing[1]),
        .I2(wr_ptr[0]),
        .I3(wr_ptr[1]),
        .I4(wr_ptr[3]),
        .O(\my_full[4]_i_4__4_n_0 ));
  (* syn_maxfan = "3" *) 
  FDRE \my_full_reg[4] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(1'b1),
        .D(\my_full[4]_i_1__4_n_0 ),
        .Q(\my_full_reg_n_0_[4] ),
        .R(1'b0));
  LUT3 #(
    .INIT(8'h0D)) 
    out_fifo_i_1__4
       (.I0(\my_empty_reg[1]_1 ),
        .I1(phy_data_wr_en),
        .I2(\my_empty_reg[7]_0 ),
        .O(\my_empty_reg[1]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair981" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_2__8
       (.I0(out_fifo_1),
        .I1(out_fifo_0[7]),
        .I2(mem_reg_0_15_6_11_n_0),
        .I3(\my_empty_reg[1]_1 ),
        .O(D0[7]));
  (* SOFT_HLUTNM = "soft_lutpair980" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_3__8
       (.I0(out_fifo_1),
        .I1(out_fifo_0[6]),
        .I2(mem_reg_0_15_6_11_n_1),
        .I3(\my_empty_reg[1]_1 ),
        .O(D0[6]));
  (* SOFT_HLUTNM = "soft_lutpair976" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_4__8
       (.I0(out_fifo_1),
        .I1(out_fifo_0[5]),
        .I2(mem_reg_0_15_0_5_n_4),
        .I3(\my_empty_reg[1]_1 ),
        .O(D0[5]));
  (* SOFT_HLUTNM = "soft_lutpair979" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_5__8
       (.I0(out_fifo_1),
        .I1(out_fifo_0[4]),
        .I2(mem_reg_0_15_0_5_n_5),
        .I3(\my_empty_reg[1]_1 ),
        .O(D0[4]));
  (* SOFT_HLUTNM = "soft_lutpair981" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_66__0
       (.I0(mem_reg_0_15_66_71_n_4),
        .I1(\my_empty_reg[1]_1 ),
        .O(D8[7]));
  (* SOFT_HLUTNM = "soft_lutpair978" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_67__0
       (.I0(mem_reg_0_15_66_71_n_5),
        .I1(\my_empty_reg[1]_1 ),
        .O(D8[6]));
  (* SOFT_HLUTNM = "soft_lutpair980" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_68__0
       (.I0(mem_reg_0_15_66_71_n_2),
        .I1(\my_empty_reg[1]_1 ),
        .O(D8[5]));
  (* SOFT_HLUTNM = "soft_lutpair976" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_69__0
       (.I0(mem_reg_0_15_66_71_n_3),
        .I1(\my_empty_reg[1]_1 ),
        .O(D8[4]));
  (* SOFT_HLUTNM = "soft_lutpair978" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_6__8
       (.I0(out_fifo_1),
        .I1(out_fifo_0[3]),
        .I2(mem_reg_0_15_0_5_n_2),
        .I3(\my_empty_reg[1]_1 ),
        .O(D0[3]));
  (* SOFT_HLUTNM = "soft_lutpair982" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_70__0
       (.I0(mem_reg_0_15_66_71_n_0),
        .I1(\my_empty_reg[1]_1 ),
        .O(D8[3]));
  (* SOFT_HLUTNM = "soft_lutpair977" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_71__0
       (.I0(mem_reg_0_15_66_71_n_1),
        .I1(\my_empty_reg[1]_1 ),
        .O(D8[2]));
  (* SOFT_HLUTNM = "soft_lutpair983" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_72__0
       (.I0(mem_reg_0_15_60_65_n_4),
        .I1(\my_empty_reg[1]_1 ),
        .O(D8[1]));
  (* SOFT_HLUTNM = "soft_lutpair979" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_73__0
       (.I0(mem_reg_0_15_60_65_n_5),
        .I1(\my_empty_reg[1]_1 ),
        .O(D8[0]));
  (* SOFT_HLUTNM = "soft_lutpair983" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_7__8
       (.I0(out_fifo_1),
        .I1(out_fifo_0[2]),
        .I2(mem_reg_0_15_0_5_n_3),
        .I3(\my_empty_reg[1]_1 ),
        .O(D0[2]));
  (* SOFT_HLUTNM = "soft_lutpair977" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_8__8
       (.I0(out_fifo),
        .I1(out_fifo_0[1]),
        .I2(mem_reg_0_15_0_5_n_0),
        .I3(\my_empty_reg[1]_1 ),
        .O(D0[1]));
  (* SOFT_HLUTNM = "soft_lutpair982" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_9__8
       (.I0(out_fifo),
        .I1(out_fifo_0[0]),
        .I2(mem_reg_0_15_0_5_n_1),
        .I3(\my_empty_reg[1]_1 ),
        .O(D0[0]));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[0] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(\rd_ptr_timing[3]_i_1__4_n_0 ),
        .D(nxt_rd_ptr[0]),
        .Q(\rd_ptr_reg_n_0_[0] ),
        .R(ofifo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[1] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(\rd_ptr_timing[3]_i_1__4_n_0 ),
        .D(nxt_rd_ptr[1]),
        .Q(\rd_ptr_reg_n_0_[1] ),
        .R(ofifo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[2] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(\rd_ptr_timing[3]_i_1__4_n_0 ),
        .D(nxt_rd_ptr[2]),
        .Q(\rd_ptr_reg_n_0_[2] ),
        .R(ofifo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[3] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(\rd_ptr_timing[3]_i_1__4_n_0 ),
        .D(nxt_rd_ptr[3]),
        .Q(\rd_ptr_reg_n_0_[3] ),
        .R(ofifo_rst));
  (* SOFT_HLUTNM = "soft_lutpair987" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rd_ptr_timing[0]_i_1__9 
       (.I0(\rd_ptr_reg_n_0_[3] ),
        .I1(\rd_ptr_reg_n_0_[0] ),
        .O(nxt_rd_ptr[0]));
  (* SOFT_HLUTNM = "soft_lutpair987" *) 
  LUT3 #(
    .INIT(8'hB4)) 
    \rd_ptr_timing[1]_i_1__9 
       (.I0(\rd_ptr_reg_n_0_[3] ),
        .I1(\rd_ptr_reg_n_0_[0] ),
        .I2(\rd_ptr_reg_n_0_[1] ),
        .O(nxt_rd_ptr[1]));
  (* SOFT_HLUTNM = "soft_lutpair985" *) 
  LUT4 #(
    .INIT(16'hAA6A)) 
    \rd_ptr_timing[2]_i_1__4 
       (.I0(\rd_ptr_reg_n_0_[2] ),
        .I1(\rd_ptr_reg_n_0_[0] ),
        .I2(\rd_ptr_reg_n_0_[1] ),
        .I3(\rd_ptr_reg_n_0_[3] ),
        .O(nxt_rd_ptr[2]));
  LUT2 #(
    .INIT(4'h1)) 
    \rd_ptr_timing[3]_i_1__4 
       (.I0(\my_empty_reg[7]_0 ),
        .I1(\my_empty_reg_n_0_[7] ),
        .O(\rd_ptr_timing[3]_i_1__4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair985" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \rd_ptr_timing[3]_i_2__4 
       (.I0(\rd_ptr_reg_n_0_[3] ),
        .I1(\rd_ptr_reg_n_0_[1] ),
        .I2(\rd_ptr_reg_n_0_[0] ),
        .I3(\rd_ptr_reg_n_0_[2] ),
        .O(nxt_rd_ptr[3]));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[0] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(\rd_ptr_timing[3]_i_1__4_n_0 ),
        .D(nxt_rd_ptr[0]),
        .Q(rd_ptr_timing[0]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[1] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(\rd_ptr_timing[3]_i_1__4_n_0 ),
        .D(nxt_rd_ptr[1]),
        .Q(rd_ptr_timing[1]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[2] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(\rd_ptr_timing[3]_i_1__4_n_0 ),
        .D(nxt_rd_ptr[2]),
        .Q(rd_ptr_timing[2]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[3] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(\rd_ptr_timing[3]_i_1__4_n_0 ),
        .D(nxt_rd_ptr[3]),
        .Q(rd_ptr_timing[3]),
        .R(ofifo_rst));
  (* SOFT_HLUTNM = "soft_lutpair986" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \wr_ptr[0]_i_1__9 
       (.I0(wr_ptr[3]),
        .I1(wr_ptr[0]),
        .O(nxt_wr_ptr[0]));
  (* SOFT_HLUTNM = "soft_lutpair986" *) 
  LUT3 #(
    .INIT(8'hB4)) 
    \wr_ptr[1]_i_1__9 
       (.I0(wr_ptr[3]),
        .I1(wr_ptr[0]),
        .I2(wr_ptr[1]),
        .O(nxt_wr_ptr[1]));
  (* SOFT_HLUTNM = "soft_lutpair984" *) 
  LUT4 #(
    .INIT(16'hAA6A)) 
    \wr_ptr[2]_i_1__4 
       (.I0(wr_ptr[2]),
        .I1(wr_ptr[0]),
        .I2(wr_ptr[1]),
        .I3(wr_ptr[3]),
        .O(nxt_wr_ptr[2]));
  LUT4 #(
    .INIT(16'h082A)) 
    \wr_ptr[3]_i_1__4 
       (.I0(phy_data_wr_en),
        .I1(\my_empty_reg[7]_0 ),
        .I2(\my_full_reg_n_0_[4] ),
        .I3(\my_empty_reg_n_0_[7] ),
        .O(wr_ptr0));
  (* SOFT_HLUTNM = "soft_lutpair984" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \wr_ptr[3]_i_2__3 
       (.I0(wr_ptr[3]),
        .I1(wr_ptr[1]),
        .I2(wr_ptr[0]),
        .I3(wr_ptr[2]),
        .O(nxt_wr_ptr[3]));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[0] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[0]),
        .Q(wr_ptr[0]),
        .R(ofifo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[1] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[1]),
        .Q(wr_ptr[1]),
        .R(ofifo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[2] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[2]),
        .Q(wr_ptr[2]),
        .R(ofifo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[3] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[3]),
        .Q(wr_ptr[3]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[0] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[0]),
        .Q(wr_ptr_timing[0]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[1] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[1]),
        .Q(wr_ptr_timing[1]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[2] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[2]),
        .Q(wr_ptr_timing[2]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[3] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[3]),
        .Q(wr_ptr_timing[3]),
        .R(ofifo_rst));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_of_pre_fifo" *) 
module mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_22
   (\my_empty_reg[1]_0 ,
    \my_empty_reg[1]_1 ,
    D0,
    D1,
    D2,
    D3,
    D4,
    D7,
    D8,
    D9,
    D5,
    \rd_ptr_reg[3]_0 ,
    SR,
    \wr_ptr_timing_reg[3]_0 ,
    phy_cmd_wr_en,
    \rd_ptr_reg[3]_1 ,
    out_fifo,
    mc_cas_n,
    mc_address,
    out_fifo_0,
    d_in,
    out_fifo_1);
  output \my_empty_reg[1]_0 ;
  output \my_empty_reg[1]_1 ;
  output [7:0]D0;
  output [3:0]D1;
  output [7:0]D2;
  output [3:0]D3;
  output [3:0]D4;
  output [3:0]D7;
  output [3:0]D8;
  output [1:0]D9;
  output [3:0]D5;
  output [35:0]\rd_ptr_reg[3]_0 ;
  input [0:0]SR;
  input \wr_ptr_timing_reg[3]_0 ;
  input phy_cmd_wr_en;
  input \rd_ptr_reg[3]_1 ;
  input out_fifo;
  input [0:0]mc_cas_n;
  input [3:0]mc_address;
  input out_fifo_0;
  input [41:0]d_in;
  input out_fifo_1;

  wire [7:0]D0;
  wire [3:0]D1;
  wire [7:0]D2;
  wire [3:0]D3;
  wire [3:0]D4;
  wire [3:0]D5;
  wire [3:0]D7;
  wire [3:0]D8;
  wire [1:0]D9;
  wire [0:0]SR;
  wire [41:0]d_in;
  wire [3:0]mc_address;
  wire [0:0]mc_cas_n;
  wire mem_reg_0_15_0_5_n_0;
  wire mem_reg_0_15_0_5_n_1;
  wire mem_reg_0_15_0_5_n_2;
  wire mem_reg_0_15_0_5_n_3;
  wire mem_reg_0_15_0_5_n_4;
  wire mem_reg_0_15_0_5_n_5;
  wire mem_reg_0_15_12_17_n_0;
  wire mem_reg_0_15_12_17_n_1;
  wire mem_reg_0_15_12_17_n_2;
  wire mem_reg_0_15_12_17_n_3;
  wire mem_reg_0_15_12_17_n_4;
  wire mem_reg_0_15_12_17_n_5;
  wire mem_reg_0_15_18_23_n_0;
  wire mem_reg_0_15_18_23_n_1;
  wire mem_reg_0_15_18_23_n_2;
  wire mem_reg_0_15_18_23_n_3;
  wire mem_reg_0_15_18_23_n_4;
  wire mem_reg_0_15_18_23_n_5;
  wire mem_reg_0_15_24_29_n_4;
  wire mem_reg_0_15_24_29_n_5;
  wire mem_reg_0_15_30_35_n_0;
  wire mem_reg_0_15_30_35_n_1;
  wire mem_reg_0_15_36_41_n_0;
  wire mem_reg_0_15_36_41_n_1;
  wire mem_reg_0_15_36_41_n_2;
  wire mem_reg_0_15_36_41_n_3;
  wire mem_reg_0_15_36_41_n_4;
  wire mem_reg_0_15_36_41_n_5;
  wire mem_reg_0_15_42_47_n_0;
  wire mem_reg_0_15_42_47_n_1;
  wire mem_reg_0_15_60_65_n_0;
  wire mem_reg_0_15_60_65_n_1;
  wire mem_reg_0_15_60_65_n_2;
  wire mem_reg_0_15_60_65_n_3;
  wire mem_reg_0_15_66_71_n_2;
  wire mem_reg_0_15_66_71_n_3;
  wire mem_reg_0_15_66_71_n_4;
  wire mem_reg_0_15_66_71_n_5;
  wire mem_reg_0_15_6_11_n_0;
  wire mem_reg_0_15_6_11_n_1;
  wire mem_reg_0_15_72_77_n_4;
  wire mem_reg_0_15_72_77_n_5;
  wire \my_empty[1]_i_1_n_0 ;
  wire \my_empty[6]_i_1_n_0 ;
  wire \my_empty[6]_i_2__0_n_0 ;
  wire \my_empty[6]_i_3__0_n_0 ;
  wire \my_empty[6]_i_4__0_n_0 ;
  wire \my_empty_reg[1]_0 ;
  wire \my_empty_reg[1]_1 ;
  wire \my_empty_reg_n_0_[6] ;
  wire \my_full[3]_i_1__0_n_0 ;
  wire \my_full[3]_i_2__0_n_0 ;
  wire \my_full[3]_i_3__0_n_0 ;
  wire \my_full[3]_i_4__0_n_0 ;
  wire \my_full_reg_n_0_[3] ;
  wire [3:0]nxt_rd_ptr;
  wire [3:0]nxt_wr_ptr;
  wire out_fifo;
  wire out_fifo_0;
  wire out_fifo_1;
  wire phy_cmd_wr_en;
  wire \rd_ptr[0]_i_1__0_n_0 ;
  wire [35:0]\rd_ptr_reg[3]_0 ;
  wire \rd_ptr_reg[3]_1 ;
  wire \rd_ptr_reg_n_0_[0] ;
  wire \rd_ptr_reg_n_0_[1] ;
  wire \rd_ptr_reg_n_0_[2] ;
  wire \rd_ptr_reg_n_0_[3] ;
  wire [3:0]rd_ptr_timing;
  (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) wire wr_en;
  wire [3:0]wr_ptr;
  wire wr_ptr0__0;
  wire [3:0]wr_ptr_timing;
  wire \wr_ptr_timing_reg[3]_0 ;
  wire [1:0]NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED;

  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "0" *) 
  (* ram_slice_end = "5" *) 
  RAM32M mem_reg_0_15_0_5
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA({1'b0,1'b0}),
        .DIB({1'b0,1'b0}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA({mem_reg_0_15_0_5_n_0,mem_reg_0_15_0_5_n_1}),
        .DOB({mem_reg_0_15_0_5_n_2,mem_reg_0_15_0_5_n_3}),
        .DOC({mem_reg_0_15_0_5_n_4,mem_reg_0_15_0_5_n_5}),
        .DOD(NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED[1:0]),
        .WCLK(\wr_ptr_timing_reg[3]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "12" *) 
  (* ram_slice_end = "17" *) 
  RAM32M mem_reg_0_15_12_17
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA({1'b0,1'b0}),
        .DIB({1'b0,1'b0}),
        .DIC({d_in[15],d_in[4]}),
        .DID({1'b0,1'b0}),
        .DOA({mem_reg_0_15_12_17_n_0,mem_reg_0_15_12_17_n_1}),
        .DOB({mem_reg_0_15_12_17_n_2,mem_reg_0_15_12_17_n_3}),
        .DOC({mem_reg_0_15_12_17_n_4,mem_reg_0_15_12_17_n_5}),
        .DOD(NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED[1:0]),
        .WCLK(\wr_ptr_timing_reg[3]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "18" *) 
  (* ram_slice_end = "23" *) 
  RAM32M mem_reg_0_15_18_23
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA({d_in[17],d_in[5]}),
        .DIB({1'b0,1'b0}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA({mem_reg_0_15_18_23_n_0,mem_reg_0_15_18_23_n_1}),
        .DOB({mem_reg_0_15_18_23_n_2,mem_reg_0_15_18_23_n_3}),
        .DOC({mem_reg_0_15_18_23_n_4,mem_reg_0_15_18_23_n_5}),
        .DOD(NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED[1:0]),
        .WCLK(\wr_ptr_timing_reg[3]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "24" *) 
  (* ram_slice_end = "29" *) 
  RAM32M mem_reg_0_15_24_29
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(d_in[7:6]),
        .DIB(d_in[9:8]),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [5:4]),
        .DOB(\rd_ptr_reg[3]_0 [7:6]),
        .DOC({mem_reg_0_15_24_29_n_4,mem_reg_0_15_24_29_n_5}),
        .DOD(NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED[1:0]),
        .WCLK(\wr_ptr_timing_reg[3]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "30" *) 
  (* ram_slice_end = "35" *) 
  RAM32M mem_reg_0_15_30_35
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA({1'b0,1'b0}),
        .DIB(d_in[11:10]),
        .DIC(d_in[13:12]),
        .DID({1'b0,1'b0}),
        .DOA({mem_reg_0_15_30_35_n_0,mem_reg_0_15_30_35_n_1}),
        .DOB(\rd_ptr_reg[3]_0 [9:8]),
        .DOC(\rd_ptr_reg[3]_0 [11:10]),
        .DOD(NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED[1:0]),
        .WCLK(\wr_ptr_timing_reg[3]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "36" *) 
  (* ram_slice_end = "41" *) 
  RAM32M mem_reg_0_15_36_41
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA({1'b0,1'b0}),
        .DIB({1'b0,1'b0}),
        .DIC(d_in[15:14]),
        .DID({1'b0,1'b0}),
        .DOA({mem_reg_0_15_36_41_n_0,mem_reg_0_15_36_41_n_1}),
        .DOB({mem_reg_0_15_36_41_n_2,mem_reg_0_15_36_41_n_3}),
        .DOC({mem_reg_0_15_36_41_n_4,mem_reg_0_15_36_41_n_5}),
        .DOD(NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED[1:0]),
        .WCLK(\wr_ptr_timing_reg[3]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "42" *) 
  (* ram_slice_end = "47" *) 
  RAM32M mem_reg_0_15_42_47
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(d_in[17:16]),
        .DIB(d_in[19:18]),
        .DIC(d_in[21:20]),
        .DID({1'b0,1'b0}),
        .DOA({mem_reg_0_15_42_47_n_0,mem_reg_0_15_42_47_n_1}),
        .DOB(\rd_ptr_reg[3]_0 [13:12]),
        .DOC(\rd_ptr_reg[3]_0 [15:14]),
        .DOD(NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED[1:0]),
        .WCLK(\wr_ptr_timing_reg[3]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "48" *) 
  (* ram_slice_end = "53" *) 
  RAM32M mem_reg_0_15_48_53
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(d_in[23:22]),
        .DIB(d_in[25:24]),
        .DIC(d_in[27:26]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [17:16]),
        .DOB(\rd_ptr_reg[3]_0 [19:18]),
        .DOC(\rd_ptr_reg[3]_0 [21:20]),
        .DOD(NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED[1:0]),
        .WCLK(\wr_ptr_timing_reg[3]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "54" *) 
  (* ram_slice_end = "59" *) 
  RAM32M mem_reg_0_15_54_59
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(d_in[29:28]),
        .DIB(d_in[31:30]),
        .DIC(d_in[33:32]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [23:22]),
        .DOB(\rd_ptr_reg[3]_0 [25:24]),
        .DOC(\rd_ptr_reg[3]_0 [27:26]),
        .DOD(NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED[1:0]),
        .WCLK(\wr_ptr_timing_reg[3]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "60" *) 
  (* ram_slice_end = "65" *) 
  RAM32M mem_reg_0_15_60_65
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA({1'b0,1'b0}),
        .DIB({1'b0,1'b0}),
        .DIC(d_in[35:34]),
        .DID({1'b0,1'b0}),
        .DOA({mem_reg_0_15_60_65_n_0,mem_reg_0_15_60_65_n_1}),
        .DOB({mem_reg_0_15_60_65_n_2,mem_reg_0_15_60_65_n_3}),
        .DOC(\rd_ptr_reg[3]_0 [29:28]),
        .DOD(NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED[1:0]),
        .WCLK(\wr_ptr_timing_reg[3]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "66" *) 
  (* ram_slice_end = "71" *) 
  RAM32M mem_reg_0_15_66_71
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(d_in[37:36]),
        .DIB({1'b0,1'b0}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [31:30]),
        .DOB({mem_reg_0_15_66_71_n_2,mem_reg_0_15_66_71_n_3}),
        .DOC({mem_reg_0_15_66_71_n_4,mem_reg_0_15_66_71_n_5}),
        .DOD(NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED[1:0]),
        .WCLK(\wr_ptr_timing_reg[3]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "6" *) 
  (* ram_slice_end = "11" *) 
  RAM32M mem_reg_0_15_6_11
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA({1'b0,1'b0}),
        .DIB(d_in[1:0]),
        .DIC(d_in[3:2]),
        .DID({1'b0,1'b0}),
        .DOA({mem_reg_0_15_6_11_n_0,mem_reg_0_15_6_11_n_1}),
        .DOB(\rd_ptr_reg[3]_0 [1:0]),
        .DOC(\rd_ptr_reg[3]_0 [3:2]),
        .DOD(NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED[1:0]),
        .WCLK(\wr_ptr_timing_reg[3]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_D.ddr_byte_lane_D/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "72" *) 
  (* ram_slice_end = "77" *) 
  RAM32M mem_reg_0_15_72_77
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(d_in[39:38]),
        .DIB(d_in[41:40]),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [33:32]),
        .DOB(\rd_ptr_reg[3]_0 [35:34]),
        .DOC({mem_reg_0_15_72_77_n_4,mem_reg_0_15_72_77_n_5}),
        .DOD(NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED[1:0]),
        .WCLK(\wr_ptr_timing_reg[3]_0 ),
        .WE(wr_en));
  (* SOFT_HLUTNM = "soft_lutpair912" *) 
  LUT5 #(
    .INIT(32'hC0CCCCCE)) 
    \my_empty[1]_i_1 
       (.I0(\my_empty[6]_i_2__0_n_0 ),
        .I1(\my_empty_reg[1]_0 ),
        .I2(\my_full_reg_n_0_[3] ),
        .I3(phy_cmd_wr_en),
        .I4(\rd_ptr_reg[3]_1 ),
        .O(\my_empty[1]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hC0CCCCCE)) 
    \my_empty[6]_i_1 
       (.I0(\my_empty[6]_i_2__0_n_0 ),
        .I1(\my_empty_reg_n_0_[6] ),
        .I2(\my_full_reg_n_0_[3] ),
        .I3(phy_cmd_wr_en),
        .I4(\rd_ptr_reg[3]_1 ),
        .O(\my_empty[6]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h4A400D08)) 
    \my_empty[6]_i_2__0 
       (.I0(wr_ptr_timing[2]),
        .I1(\my_empty[6]_i_3__0_n_0 ),
        .I2(wr_ptr_timing[3]),
        .I3(\my_empty[6]_i_4__0_n_0 ),
        .I4(\rd_ptr_reg_n_0_[2] ),
        .O(\my_empty[6]_i_2__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair911" *) 
  LUT5 #(
    .INIT(32'h00000040)) 
    \my_empty[6]_i_3__0 
       (.I0(wr_ptr_timing[1]),
        .I1(\rd_ptr_reg_n_0_[0] ),
        .I2(\rd_ptr_reg_n_0_[1] ),
        .I3(\rd_ptr_reg_n_0_[3] ),
        .I4(wr_ptr_timing[0]),
        .O(\my_empty[6]_i_3__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair911" *) 
  LUT5 #(
    .INIT(32'h84210842)) 
    \my_empty[6]_i_4__0 
       (.I0(wr_ptr_timing[0]),
        .I1(wr_ptr_timing[1]),
        .I2(\rd_ptr_reg_n_0_[0] ),
        .I3(\rd_ptr_reg_n_0_[1] ),
        .I4(\rd_ptr_reg_n_0_[3] ),
        .O(\my_empty[6]_i_4__0_n_0 ));
  (* syn_maxfan = "3" *) 
  FDSE \my_empty_reg[1] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(1'b1),
        .D(\my_empty[1]_i_1_n_0 ),
        .Q(\my_empty_reg[1]_0 ),
        .S(SR));
  (* syn_maxfan = "3" *) 
  FDSE \my_empty_reg[6] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(1'b1),
        .D(\my_empty[6]_i_1_n_0 ),
        .Q(\my_empty_reg_n_0_[6] ),
        .S(SR));
  LUT6 #(
    .INIT(64'h00000000FFFC0080)) 
    \my_full[3]_i_1__0 
       (.I0(\my_full[3]_i_2__0_n_0 ),
        .I1(phy_cmd_wr_en),
        .I2(\rd_ptr_reg[3]_1 ),
        .I3(\my_empty_reg_n_0_[6] ),
        .I4(\my_full_reg_n_0_[3] ),
        .I5(SR),
        .O(\my_full[3]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'h4A400D08)) 
    \my_full[3]_i_2__0 
       (.I0(rd_ptr_timing[2]),
        .I1(\my_full[3]_i_3__0_n_0 ),
        .I2(rd_ptr_timing[3]),
        .I3(\my_full[3]_i_4__0_n_0 ),
        .I4(wr_ptr[2]),
        .O(\my_full[3]_i_2__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair910" *) 
  LUT5 #(
    .INIT(32'h00000040)) 
    \my_full[3]_i_3__0 
       (.I0(rd_ptr_timing[1]),
        .I1(wr_ptr[0]),
        .I2(wr_ptr[1]),
        .I3(wr_ptr[3]),
        .I4(rd_ptr_timing[0]),
        .O(\my_full[3]_i_3__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair910" *) 
  LUT5 #(
    .INIT(32'h84210842)) 
    \my_full[3]_i_4__0 
       (.I0(rd_ptr_timing[0]),
        .I1(rd_ptr_timing[1]),
        .I2(wr_ptr[0]),
        .I3(wr_ptr[1]),
        .I4(wr_ptr[3]),
        .O(\my_full[3]_i_4__0_n_0 ));
  (* syn_maxfan = "3" *) 
  FDRE \my_full_reg[3] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(1'b1),
        .D(\my_full[3]_i_1__0_n_0 ),
        .Q(\my_full_reg_n_0_[3] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair927" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_10__1
       (.I0(mem_reg_0_15_12_17_n_2),
        .I1(\my_empty_reg[1]_0 ),
        .O(D1[3]));
  (* SOFT_HLUTNM = "soft_lutpair915" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_11__1
       (.I0(mem_reg_0_15_12_17_n_3),
        .I1(\my_empty_reg[1]_0 ),
        .O(D1[2]));
  (* SOFT_HLUTNM = "soft_lutpair928" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_12__1
       (.I0(mem_reg_0_15_12_17_n_0),
        .I1(\my_empty_reg[1]_0 ),
        .O(D1[1]));
  (* SOFT_HLUTNM = "soft_lutpair923" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_13__1
       (.I0(mem_reg_0_15_12_17_n_1),
        .I1(\my_empty_reg[1]_0 ),
        .O(D1[0]));
  (* SOFT_HLUTNM = "soft_lutpair925" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_18
       (.I0(mem_reg_0_15_18_23_n_4),
        .I1(\my_empty_reg[1]_0 ),
        .O(D2[7]));
  (* SOFT_HLUTNM = "soft_lutpair928" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_19
       (.I0(mem_reg_0_15_18_23_n_5),
        .I1(\my_empty_reg[1]_0 ),
        .O(D2[6]));
  (* SOFT_HLUTNM = "soft_lutpair912" *) 
  LUT3 #(
    .INIT(8'h0D)) 
    out_fifo_i_1__9
       (.I0(\my_empty_reg[1]_0 ),
        .I1(phy_cmd_wr_en),
        .I2(\rd_ptr_reg[3]_1 ),
        .O(\my_empty_reg[1]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair929" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_20__0
       (.I0(mem_reg_0_15_18_23_n_2),
        .I1(\my_empty_reg[1]_0 ),
        .O(D2[5]));
  (* SOFT_HLUTNM = "soft_lutpair925" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_21__0
       (.I0(mem_reg_0_15_18_23_n_3),
        .I1(\my_empty_reg[1]_0 ),
        .O(D2[4]));
  (* SOFT_HLUTNM = "soft_lutpair921" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    out_fifo_i_22
       (.I0(out_fifo_1),
        .I1(mem_reg_0_15_18_23_n_0),
        .I2(\my_empty_reg[1]_0 ),
        .O(D2[3]));
  (* SOFT_HLUTNM = "soft_lutpair913" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_23__9
       (.I0(mc_address[3]),
        .I1(out_fifo_0),
        .I2(mem_reg_0_15_18_23_n_1),
        .I3(\my_empty_reg[1]_0 ),
        .O(D2[2]));
  (* SOFT_HLUTNM = "soft_lutpair916" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_24__0
       (.I0(out_fifo),
        .I1(mc_cas_n),
        .I2(mem_reg_0_15_12_17_n_4),
        .I3(\my_empty_reg[1]_0 ),
        .O(D2[1]));
  (* SOFT_HLUTNM = "soft_lutpair915" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_25__9
       (.I0(mc_address[1]),
        .I1(out_fifo_0),
        .I2(mem_reg_0_15_12_17_n_5),
        .I3(\my_empty_reg[1]_0 ),
        .O(D2[0]));
  (* SOFT_HLUTNM = "soft_lutpair932" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_26__0
       (.I0(mem_reg_0_15_30_35_n_0),
        .I1(\my_empty_reg[1]_0 ),
        .O(D3[3]));
  (* SOFT_HLUTNM = "soft_lutpair927" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_27
       (.I0(mem_reg_0_15_30_35_n_1),
        .I1(\my_empty_reg[1]_0 ),
        .O(D3[2]));
  (* SOFT_HLUTNM = "soft_lutpair930" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_28
       (.I0(mem_reg_0_15_24_29_n_4),
        .I1(\my_empty_reg[1]_0 ),
        .O(D3[1]));
  (* SOFT_HLUTNM = "soft_lutpair924" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_29
       (.I0(mem_reg_0_15_24_29_n_5),
        .I1(\my_empty_reg[1]_0 ),
        .O(D3[0]));
  (* SOFT_HLUTNM = "soft_lutpair929" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_2__7
       (.I0(mem_reg_0_15_6_11_n_0),
        .I1(\my_empty_reg[1]_0 ),
        .O(D0[7]));
  (* SOFT_HLUTNM = "soft_lutpair937" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_34__1
       (.I0(mem_reg_0_15_36_41_n_2),
        .I1(\my_empty_reg[1]_0 ),
        .O(D4[3]));
  (* SOFT_HLUTNM = "soft_lutpair923" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_35__0
       (.I0(mem_reg_0_15_36_41_n_3),
        .I1(\my_empty_reg[1]_0 ),
        .O(D4[2]));
  (* SOFT_HLUTNM = "soft_lutpair937" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_36__0
       (.I0(mem_reg_0_15_36_41_n_0),
        .I1(\my_empty_reg[1]_0 ),
        .O(D4[1]));
  (* SOFT_HLUTNM = "soft_lutpair933" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_37__0
       (.I0(mem_reg_0_15_36_41_n_1),
        .I1(\my_empty_reg[1]_0 ),
        .O(D4[0]));
  (* SOFT_HLUTNM = "soft_lutpair918" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_3__7
       (.I0(mem_reg_0_15_6_11_n_1),
        .I1(\my_empty_reg[1]_0 ),
        .O(D0[6]));
  (* SOFT_HLUTNM = "soft_lutpair921" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    out_fifo_i_46
       (.I0(out_fifo_1),
        .I1(mem_reg_0_15_42_47_n_0),
        .I2(\my_empty_reg[1]_0 ),
        .O(D5[3]));
  (* SOFT_HLUTNM = "soft_lutpair918" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_47__9
       (.I0(mc_address[2]),
        .I1(out_fifo_0),
        .I2(mem_reg_0_15_42_47_n_1),
        .I3(\my_empty_reg[1]_0 ),
        .O(D5[2]));
  (* SOFT_HLUTNM = "soft_lutpair916" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_48__0
       (.I0(out_fifo),
        .I1(mc_cas_n),
        .I2(mem_reg_0_15_36_41_n_4),
        .I3(\my_empty_reg[1]_0 ),
        .O(D5[1]));
  (* SOFT_HLUTNM = "soft_lutpair919" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_49__9
       (.I0(mc_address[0]),
        .I1(out_fifo_0),
        .I2(mem_reg_0_15_36_41_n_5),
        .I3(\my_empty_reg[1]_0 ),
        .O(D5[0]));
  (* SOFT_HLUTNM = "soft_lutpair930" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_4__7
       (.I0(mem_reg_0_15_0_5_n_4),
        .I1(\my_empty_reg[1]_0 ),
        .O(D0[5]));
  (* SOFT_HLUTNM = "soft_lutpair933" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_58
       (.I0(mem_reg_0_15_60_65_n_2),
        .I1(\my_empty_reg[1]_0 ),
        .O(D7[3]));
  (* SOFT_HLUTNM = "soft_lutpair931" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_59
       (.I0(mem_reg_0_15_60_65_n_3),
        .I1(\my_empty_reg[1]_0 ),
        .O(D7[2]));
  (* SOFT_HLUTNM = "soft_lutpair924" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_5__7
       (.I0(mem_reg_0_15_0_5_n_5),
        .I1(\my_empty_reg[1]_0 ),
        .O(D0[4]));
  (* SOFT_HLUTNM = "soft_lutpair935" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_60
       (.I0(mem_reg_0_15_60_65_n_0),
        .I1(\my_empty_reg[1]_0 ),
        .O(D7[1]));
  (* SOFT_HLUTNM = "soft_lutpair932" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_61
       (.I0(mem_reg_0_15_60_65_n_1),
        .I1(\my_empty_reg[1]_0 ),
        .O(D7[0]));
  (* SOFT_HLUTNM = "soft_lutpair936" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_66__1
       (.I0(mem_reg_0_15_66_71_n_4),
        .I1(\my_empty_reg[1]_0 ),
        .O(D8[3]));
  (* SOFT_HLUTNM = "soft_lutpair934" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_67__1
       (.I0(mem_reg_0_15_66_71_n_5),
        .I1(\my_empty_reg[1]_0 ),
        .O(D8[2]));
  (* SOFT_HLUTNM = "soft_lutpair934" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_68__1
       (.I0(mem_reg_0_15_66_71_n_2),
        .I1(\my_empty_reg[1]_0 ),
        .O(D8[1]));
  (* SOFT_HLUTNM = "soft_lutpair926" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_69__1
       (.I0(mem_reg_0_15_66_71_n_3),
        .I1(\my_empty_reg[1]_0 ),
        .O(D8[0]));
  (* SOFT_HLUTNM = "soft_lutpair926" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_6__7
       (.I0(mem_reg_0_15_0_5_n_2),
        .I1(\my_empty_reg[1]_0 ),
        .O(D0[3]));
  (* SOFT_HLUTNM = "soft_lutpair936" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_74
       (.I0(mem_reg_0_15_72_77_n_4),
        .I1(\my_empty_reg[1]_0 ),
        .O(D9[1]));
  (* SOFT_HLUTNM = "soft_lutpair935" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_75
       (.I0(mem_reg_0_15_72_77_n_5),
        .I1(\my_empty_reg[1]_0 ),
        .O(D9[0]));
  (* SOFT_HLUTNM = "soft_lutpair913" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_7__7
       (.I0(mem_reg_0_15_0_5_n_3),
        .I1(\my_empty_reg[1]_0 ),
        .O(D0[2]));
  (* SOFT_HLUTNM = "soft_lutpair931" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_8__7
       (.I0(mem_reg_0_15_0_5_n_0),
        .I1(\my_empty_reg[1]_0 ),
        .O(D0[1]));
  (* SOFT_HLUTNM = "soft_lutpair919" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_9__7
       (.I0(mem_reg_0_15_0_5_n_1),
        .I1(\my_empty_reg[1]_0 ),
        .O(D0[0]));
  LUT4 #(
    .INIT(16'h2700)) 
    p_17_out
       (.I0(\rd_ptr_reg[3]_1 ),
        .I1(\my_full_reg_n_0_[3] ),
        .I2(\my_empty_reg[1]_0 ),
        .I3(phy_cmd_wr_en),
        .O(wr_en));
  LUT2 #(
    .INIT(4'h1)) 
    \rd_ptr[0]_i_1__0 
       (.I0(\rd_ptr_reg[3]_1 ),
        .I1(\my_empty_reg_n_0_[6] ),
        .O(\rd_ptr[0]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair920" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rd_ptr[0]_i_2__0 
       (.I0(\rd_ptr_reg_n_0_[3] ),
        .I1(\rd_ptr_reg_n_0_[0] ),
        .O(nxt_rd_ptr[0]));
  (* SOFT_HLUTNM = "soft_lutpair920" *) 
  LUT3 #(
    .INIT(8'hB4)) 
    \rd_ptr[1]_i_1__0 
       (.I0(\rd_ptr_reg_n_0_[3] ),
        .I1(\rd_ptr_reg_n_0_[0] ),
        .I2(\rd_ptr_reg_n_0_[1] ),
        .O(nxt_rd_ptr[1]));
  (* SOFT_HLUTNM = "soft_lutpair917" *) 
  LUT4 #(
    .INIT(16'hAA6A)) 
    \rd_ptr[2]_i_1__0 
       (.I0(\rd_ptr_reg_n_0_[2] ),
        .I1(\rd_ptr_reg_n_0_[0] ),
        .I2(\rd_ptr_reg_n_0_[1] ),
        .I3(\rd_ptr_reg_n_0_[3] ),
        .O(nxt_rd_ptr[2]));
  (* SOFT_HLUTNM = "soft_lutpair917" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \rd_ptr[3]_i_1__0 
       (.I0(\rd_ptr_reg_n_0_[3] ),
        .I1(\rd_ptr_reg_n_0_[1] ),
        .I2(\rd_ptr_reg_n_0_[0] ),
        .I3(\rd_ptr_reg_n_0_[2] ),
        .O(nxt_rd_ptr[3]));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[0] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(\rd_ptr[0]_i_1__0_n_0 ),
        .D(nxt_rd_ptr[0]),
        .Q(\rd_ptr_reg_n_0_[0] ),
        .R(SR));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[1] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(\rd_ptr[0]_i_1__0_n_0 ),
        .D(nxt_rd_ptr[1]),
        .Q(\rd_ptr_reg_n_0_[1] ),
        .R(SR));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[2] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(\rd_ptr[0]_i_1__0_n_0 ),
        .D(nxt_rd_ptr[2]),
        .Q(\rd_ptr_reg_n_0_[2] ),
        .R(SR));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[3] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(\rd_ptr[0]_i_1__0_n_0 ),
        .D(nxt_rd_ptr[3]),
        .Q(\rd_ptr_reg_n_0_[3] ),
        .R(SR));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[0] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(\rd_ptr[0]_i_1__0_n_0 ),
        .D(nxt_rd_ptr[0]),
        .Q(rd_ptr_timing[0]),
        .R(SR));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[1] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(\rd_ptr[0]_i_1__0_n_0 ),
        .D(nxt_rd_ptr[1]),
        .Q(rd_ptr_timing[1]),
        .R(SR));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[2] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(\rd_ptr[0]_i_1__0_n_0 ),
        .D(nxt_rd_ptr[2]),
        .Q(rd_ptr_timing[2]),
        .R(SR));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[3] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(\rd_ptr[0]_i_1__0_n_0 ),
        .D(nxt_rd_ptr[3]),
        .Q(rd_ptr_timing[3]),
        .R(SR));
  LUT4 #(
    .INIT(16'h082A)) 
    wr_ptr0
       (.I0(phy_cmd_wr_en),
        .I1(\rd_ptr_reg[3]_1 ),
        .I2(\my_full_reg_n_0_[3] ),
        .I3(\my_empty_reg_n_0_[6] ),
        .O(wr_ptr0__0));
  (* SOFT_HLUTNM = "soft_lutpair922" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \wr_ptr[0]_i_1__17 
       (.I0(wr_ptr[3]),
        .I1(wr_ptr[0]),
        .O(nxt_wr_ptr[0]));
  (* SOFT_HLUTNM = "soft_lutpair922" *) 
  LUT3 #(
    .INIT(8'hB4)) 
    \wr_ptr[1]_i_1__17 
       (.I0(wr_ptr[3]),
        .I1(wr_ptr[0]),
        .I2(wr_ptr[1]),
        .O(nxt_wr_ptr[1]));
  (* SOFT_HLUTNM = "soft_lutpair914" *) 
  LUT4 #(
    .INIT(16'hAA6A)) 
    \wr_ptr[2]_i_1__9 
       (.I0(wr_ptr[2]),
        .I1(wr_ptr[0]),
        .I2(wr_ptr[1]),
        .I3(wr_ptr[3]),
        .O(nxt_wr_ptr[2]));
  (* SOFT_HLUTNM = "soft_lutpair914" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \wr_ptr[3]_i_1__9 
       (.I0(wr_ptr[3]),
        .I1(wr_ptr[1]),
        .I2(wr_ptr[0]),
        .I3(wr_ptr[2]),
        .O(nxt_wr_ptr[3]));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[0] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(wr_ptr0__0),
        .D(nxt_wr_ptr[0]),
        .Q(wr_ptr[0]),
        .R(SR));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[1] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(wr_ptr0__0),
        .D(nxt_wr_ptr[1]),
        .Q(wr_ptr[1]),
        .R(SR));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[2] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(wr_ptr0__0),
        .D(nxt_wr_ptr[2]),
        .Q(wr_ptr[2]),
        .R(SR));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[3] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(wr_ptr0__0),
        .D(nxt_wr_ptr[3]),
        .Q(wr_ptr[3]),
        .R(SR));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[0] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(wr_ptr0__0),
        .D(nxt_wr_ptr[0]),
        .Q(wr_ptr_timing[0]),
        .R(SR));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[1] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(wr_ptr0__0),
        .D(nxt_wr_ptr[1]),
        .Q(wr_ptr_timing[1]),
        .R(SR));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[2] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(wr_ptr0__0),
        .D(nxt_wr_ptr[2]),
        .Q(wr_ptr_timing[2]),
        .R(SR));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[3] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(wr_ptr0__0),
        .D(nxt_wr_ptr[3]),
        .Q(wr_ptr_timing[3]),
        .R(SR));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_of_pre_fifo" *) 
module mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_23
   (\my_empty_reg[1]_0 ,
    \my_empty_reg[1]_1 ,
    D0,
    D3,
    D4,
    D6,
    D7,
    D8,
    D9,
    \rd_ptr_reg[3]_0 ,
    SR,
    \wr_ptr_timing_reg[3]_0 ,
    phy_cmd_wr_en,
    \my_empty_reg[7]_0 ,
    phy_dout);
  output \my_empty_reg[1]_0 ;
  output \my_empty_reg[1]_1 ;
  output [5:0]D0;
  output [1:0]D3;
  output [3:0]D4;
  output [3:0]D6;
  output [7:0]D7;
  output [3:0]D8;
  output [1:0]D9;
  output [23:0]\rd_ptr_reg[3]_0 ;
  input [0:0]SR;
  input \wr_ptr_timing_reg[3]_0 ;
  input phy_cmd_wr_en;
  input \my_empty_reg[7]_0 ;
  input [23:0]phy_dout;

  wire [5:0]D0;
  wire [1:0]D3;
  wire [3:0]D4;
  wire [3:0]D6;
  wire [7:0]D7;
  wire [3:0]D8;
  wire [1:0]D9;
  wire [0:0]SR;
  wire [77:2]mem_out;
  wire my_empty0;
  wire \my_empty[1]_i_1_n_0 ;
  wire \my_empty[7]_i_1_n_0 ;
  wire \my_empty[7]_i_3_n_0 ;
  wire \my_empty[7]_i_4_n_0 ;
  wire \my_empty_reg[1]_0 ;
  wire \my_empty_reg[1]_1 ;
  wire \my_empty_reg[7]_0 ;
  wire \my_empty_reg_n_0_[7] ;
  wire my_full0;
  wire \my_full[4]_i_1_n_0 ;
  wire \my_full[4]_i_3_n_0 ;
  wire \my_full[4]_i_4_n_0 ;
  wire \my_full_reg_n_0_[4] ;
  wire [3:0]nxt_rd_ptr;
  wire [3:0]nxt_wr_ptr;
  wire phy_cmd_wr_en;
  wire [23:0]phy_dout;
  wire [3:0]rd_ptr;
  wire [23:0]\rd_ptr_reg[3]_0 ;
  wire [3:0]rd_ptr_timing;
  wire \rd_ptr_timing[3]_i_1_n_0 ;
  (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) wire wr_en;
  wire [3:0]wr_ptr;
  wire wr_ptr0__0;
  wire [3:0]wr_ptr_timing;
  wire \wr_ptr_timing_reg[3]_0 ;
  wire [1:0]NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED;

  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "30" *) 
  (* ram_slice_end = "35" *) 
  RAM32M mem_reg_0_15_30_35
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA({1'b0,1'b0}),
        .DIB(phy_dout[1:0]),
        .DIC(phy_dout[3:2]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[31:30]),
        .DOB(\rd_ptr_reg[3]_0 [1:0]),
        .DOC(\rd_ptr_reg[3]_0 [3:2]),
        .DOD(NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED[1:0]),
        .WCLK(\wr_ptr_timing_reg[3]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "36" *) 
  (* ram_slice_end = "41" *) 
  RAM32M mem_reg_0_15_36_41
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA({1'b0,1'b0}),
        .DIB({1'b0,1'b0}),
        .DIC(phy_dout[5:4]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[37:36]),
        .DOB(mem_out[39:38]),
        .DOC(\rd_ptr_reg[3]_0 [5:4]),
        .DOD(NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED[1:0]),
        .WCLK(\wr_ptr_timing_reg[3]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "42" *) 
  (* ram_slice_end = "47" *) 
  RAM32M mem_reg_0_15_42_47
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[7:6]),
        .DIB(phy_dout[9:8]),
        .DIC(phy_dout[11:10]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [7:6]),
        .DOB(\rd_ptr_reg[3]_0 [9:8]),
        .DOC(\rd_ptr_reg[3]_0 [11:10]),
        .DOD(NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED[1:0]),
        .WCLK(\wr_ptr_timing_reg[3]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "48" *) 
  (* ram_slice_end = "53" *) 
  RAM32M mem_reg_0_15_48_53
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA({1'b0,1'b0}),
        .DIB({1'b0,1'b0}),
        .DIC(phy_dout[13:12]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[49:48]),
        .DOB(mem_out[51:50]),
        .DOC(\rd_ptr_reg[3]_0 [13:12]),
        .DOD(NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED[1:0]),
        .WCLK(\wr_ptr_timing_reg[3]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "54" *) 
  (* ram_slice_end = "59" *) 
  RAM32M mem_reg_0_15_54_59
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[15:14]),
        .DIB({1'b0,1'b0}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [15:14]),
        .DOB(mem_out[57:56]),
        .DOC(mem_out[59:58]),
        .DOD(NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED[1:0]),
        .WCLK(\wr_ptr_timing_reg[3]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "60" *) 
  (* ram_slice_end = "65" *) 
  RAM32M mem_reg_0_15_60_65
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA({1'b0,1'b0}),
        .DIB({1'b0,1'b0}),
        .DIC(phy_dout[17:16]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[61:60]),
        .DOB(mem_out[63:62]),
        .DOC(\rd_ptr_reg[3]_0 [17:16]),
        .DOD(NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED[1:0]),
        .WCLK(\wr_ptr_timing_reg[3]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "66" *) 
  (* ram_slice_end = "71" *) 
  RAM32M mem_reg_0_15_66_71
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[19:18]),
        .DIB({1'b0,1'b0}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [19:18]),
        .DOB(mem_out[69:68]),
        .DOC(mem_out[71:70]),
        .DOD(NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED[1:0]),
        .WCLK(\wr_ptr_timing_reg[3]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "6" *) 
  (* ram_slice_end = "11" *) 
  RAM32M mem_reg_0_15_6_11
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA({1'b0,1'b0}),
        .DIB({1'b0,1'b0}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[7:6]),
        .DOB(mem_out[3:2]),
        .DOC(mem_out[5:4]),
        .DOD(NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED[1:0]),
        .WCLK(\wr_ptr_timing_reg[3]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "72" *) 
  (* ram_slice_end = "77" *) 
  RAM32M mem_reg_0_15_72_77
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[21:20]),
        .DIB(phy_dout[23:22]),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [21:20]),
        .DOB(\rd_ptr_reg[3]_0 [23:22]),
        .DOC(mem_out[77:76]),
        .DOD(NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED[1:0]),
        .WCLK(\wr_ptr_timing_reg[3]_0 ),
        .WE(wr_en));
  LUT6 #(
    .INIT(64'hFFFFFFFFF701F700)) 
    \my_empty[1]_i_1 
       (.I0(\my_empty_reg[7]_0 ),
        .I1(phy_cmd_wr_en),
        .I2(\my_full_reg_n_0_[4] ),
        .I3(\my_empty_reg[1]_1 ),
        .I4(my_empty0),
        .I5(SR),
        .O(\my_empty[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFF701F700)) 
    \my_empty[7]_i_1 
       (.I0(\my_empty_reg[7]_0 ),
        .I1(phy_cmd_wr_en),
        .I2(\my_full_reg_n_0_[4] ),
        .I3(\my_empty_reg_n_0_[7] ),
        .I4(my_empty0),
        .I5(SR),
        .O(\my_empty[7]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h4A400D08)) 
    \my_empty[7]_i_2 
       (.I0(wr_ptr_timing[2]),
        .I1(\my_empty[7]_i_3_n_0 ),
        .I2(wr_ptr_timing[3]),
        .I3(\my_empty[7]_i_4_n_0 ),
        .I4(rd_ptr[2]),
        .O(my_empty0));
  (* SOFT_HLUTNM = "soft_lutpair889" *) 
  LUT5 #(
    .INIT(32'h00000040)) 
    \my_empty[7]_i_3 
       (.I0(wr_ptr_timing[1]),
        .I1(rd_ptr[0]),
        .I2(rd_ptr[1]),
        .I3(rd_ptr[3]),
        .I4(wr_ptr_timing[0]),
        .O(\my_empty[7]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair889" *) 
  LUT5 #(
    .INIT(32'h84210842)) 
    \my_empty[7]_i_4 
       (.I0(wr_ptr_timing[0]),
        .I1(wr_ptr_timing[1]),
        .I2(rd_ptr[0]),
        .I3(rd_ptr[1]),
        .I4(rd_ptr[3]),
        .O(\my_empty[7]_i_4_n_0 ));
  (* syn_maxfan = "3" *) 
  FDRE \my_empty_reg[1] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(1'b1),
        .D(\my_empty[1]_i_1_n_0 ),
        .Q(\my_empty_reg[1]_1 ),
        .R(1'b0));
  (* syn_maxfan = "3" *) 
  FDRE \my_empty_reg[7] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(1'b1),
        .D(\my_empty[7]_i_1_n_0 ),
        .Q(\my_empty_reg_n_0_[7] ),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h00000000FFFC0080)) 
    \my_full[4]_i_1 
       (.I0(my_full0),
        .I1(phy_cmd_wr_en),
        .I2(\my_empty_reg[7]_0 ),
        .I3(\my_empty_reg_n_0_[7] ),
        .I4(\my_full_reg_n_0_[4] ),
        .I5(SR),
        .O(\my_full[4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h4A400D08)) 
    \my_full[4]_i_2 
       (.I0(rd_ptr_timing[2]),
        .I1(\my_full[4]_i_3_n_0 ),
        .I2(rd_ptr_timing[3]),
        .I3(\my_full[4]_i_4_n_0 ),
        .I4(wr_ptr[2]),
        .O(my_full0));
  (* SOFT_HLUTNM = "soft_lutpair890" *) 
  LUT5 #(
    .INIT(32'h00000040)) 
    \my_full[4]_i_3 
       (.I0(rd_ptr_timing[1]),
        .I1(wr_ptr[0]),
        .I2(wr_ptr[1]),
        .I3(wr_ptr[3]),
        .I4(rd_ptr_timing[0]),
        .O(\my_full[4]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair890" *) 
  LUT5 #(
    .INIT(32'h84210842)) 
    \my_full[4]_i_4 
       (.I0(rd_ptr_timing[0]),
        .I1(rd_ptr_timing[1]),
        .I2(wr_ptr[0]),
        .I3(wr_ptr[1]),
        .I4(wr_ptr[3]),
        .O(\my_full[4]_i_4_n_0 ));
  (* syn_maxfan = "3" *) 
  FDRE \my_full_reg[4] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(1'b1),
        .D(\my_full[4]_i_1_n_0 ),
        .Q(\my_full_reg_n_0_[4] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair893" *) 
  LUT3 #(
    .INIT(8'h0D)) 
    out_fifo_i_1
       (.I0(\my_empty_reg[1]_1 ),
        .I1(phy_cmd_wr_en),
        .I2(\my_empty_reg[7]_0 ),
        .O(\my_empty_reg[1]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair907" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_10
       (.I0(mem_out[39]),
        .I1(\my_empty_reg[1]_1 ),
        .O(D4[3]));
  (* SOFT_HLUTNM = "soft_lutpair903" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_11
       (.I0(mem_out[38]),
        .I1(\my_empty_reg[1]_1 ),
        .O(D4[2]));
  (* SOFT_HLUTNM = "soft_lutpair908" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_12
       (.I0(mem_out[37]),
        .I1(\my_empty_reg[1]_1 ),
        .O(D4[1]));
  (* SOFT_HLUTNM = "soft_lutpair899" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_13
       (.I0(mem_out[36]),
        .I1(\my_empty_reg[1]_1 ),
        .O(D4[0]));
  (* SOFT_HLUTNM = "soft_lutpair899" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_2
       (.I0(mem_out[7]),
        .I1(\my_empty_reg[1]_1 ),
        .O(D0[5]));
  (* SOFT_HLUTNM = "soft_lutpair896" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_3
       (.I0(mem_out[6]),
        .I1(\my_empty_reg[1]_1 ),
        .O(D0[4]));
  (* SOFT_HLUTNM = "soft_lutpair902" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_30
       (.I0(mem_out[51]),
        .I1(\my_empty_reg[1]_1 ),
        .O(D6[3]));
  (* SOFT_HLUTNM = "soft_lutpair902" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_31
       (.I0(mem_out[50]),
        .I1(\my_empty_reg[1]_1 ),
        .O(D6[2]));
  (* SOFT_HLUTNM = "soft_lutpair908" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_32
       (.I0(mem_out[49]),
        .I1(\my_empty_reg[1]_1 ),
        .O(D6[1]));
  (* SOFT_HLUTNM = "soft_lutpair904" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_33
       (.I0(mem_out[48]),
        .I1(\my_empty_reg[1]_1 ),
        .O(D6[0]));
  (* SOFT_HLUTNM = "soft_lutpair905" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_34
       (.I0(mem_out[63]),
        .I1(\my_empty_reg[1]_1 ),
        .O(D7[7]));
  (* SOFT_HLUTNM = "soft_lutpair903" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_35
       (.I0(mem_out[62]),
        .I1(\my_empty_reg[1]_1 ),
        .O(D7[6]));
  (* SOFT_HLUTNM = "soft_lutpair909" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_36
       (.I0(mem_out[61]),
        .I1(\my_empty_reg[1]_1 ),
        .O(D7[5]));
  (* SOFT_HLUTNM = "soft_lutpair900" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_37
       (.I0(mem_out[60]),
        .I1(\my_empty_reg[1]_1 ),
        .O(D7[4]));
  (* SOFT_HLUTNM = "soft_lutpair909" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_38
       (.I0(mem_out[59]),
        .I1(\my_empty_reg[1]_1 ),
        .O(D7[3]));
  (* SOFT_HLUTNM = "soft_lutpair896" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_39
       (.I0(mem_out[58]),
        .I1(\my_empty_reg[1]_1 ),
        .O(D7[2]));
  (* SOFT_HLUTNM = "soft_lutpair900" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_4
       (.I0(mem_out[5]),
        .I1(\my_empty_reg[1]_1 ),
        .O(D0[3]));
  (* SOFT_HLUTNM = "soft_lutpair906" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_40
       (.I0(mem_out[57]),
        .I1(\my_empty_reg[1]_1 ),
        .O(D7[1]));
  (* SOFT_HLUTNM = "soft_lutpair901" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_41
       (.I0(mem_out[56]),
        .I1(\my_empty_reg[1]_1 ),
        .O(D7[0]));
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_42
       (.I0(mem_out[71]),
        .I1(\my_empty_reg[1]_1 ),
        .O(D8[3]));
  (* SOFT_HLUTNM = "soft_lutpair898" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_43
       (.I0(mem_out[70]),
        .I1(\my_empty_reg[1]_1 ),
        .O(D8[2]));
  (* SOFT_HLUTNM = "soft_lutpair907" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_44
       (.I0(mem_out[69]),
        .I1(\my_empty_reg[1]_1 ),
        .O(D8[1]));
  (* SOFT_HLUTNM = "soft_lutpair904" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_45
       (.I0(mem_out[68]),
        .I1(\my_empty_reg[1]_1 ),
        .O(D8[0]));
  (* SOFT_HLUTNM = "soft_lutpair897" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_5
       (.I0(mem_out[4]),
        .I1(\my_empty_reg[1]_1 ),
        .O(D0[2]));
  (* SOFT_HLUTNM = "soft_lutpair906" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_50
       (.I0(mem_out[77]),
        .I1(\my_empty_reg[1]_1 ),
        .O(D9[1]));
  (* SOFT_HLUTNM = "soft_lutpair897" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_51
       (.I0(mem_out[76]),
        .I1(\my_empty_reg[1]_1 ),
        .O(D9[0]));
  (* SOFT_HLUTNM = "soft_lutpair898" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_6
       (.I0(mem_out[3]),
        .I1(\my_empty_reg[1]_1 ),
        .O(D0[1]));
  (* SOFT_HLUTNM = "soft_lutpair893" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_7
       (.I0(mem_out[2]),
        .I1(\my_empty_reg[1]_1 ),
        .O(D0[0]));
  (* SOFT_HLUTNM = "soft_lutpair905" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_8
       (.I0(mem_out[31]),
        .I1(\my_empty_reg[1]_1 ),
        .O(D3[1]));
  (* SOFT_HLUTNM = "soft_lutpair901" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_9
       (.I0(mem_out[30]),
        .I1(\my_empty_reg[1]_1 ),
        .O(D3[0]));
  LUT4 #(
    .INIT(16'h2700)) 
    p_17_out
       (.I0(\my_empty_reg[7]_0 ),
        .I1(\my_full_reg_n_0_[4] ),
        .I2(\my_empty_reg[1]_1 ),
        .I3(phy_cmd_wr_en),
        .O(wr_en));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[0] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(\rd_ptr_timing[3]_i_1_n_0 ),
        .D(nxt_rd_ptr[0]),
        .Q(rd_ptr[0]),
        .R(SR));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[1] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(\rd_ptr_timing[3]_i_1_n_0 ),
        .D(nxt_rd_ptr[1]),
        .Q(rd_ptr[1]),
        .R(SR));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[2] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(\rd_ptr_timing[3]_i_1_n_0 ),
        .D(nxt_rd_ptr[2]),
        .Q(rd_ptr[2]),
        .R(SR));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[3] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(\rd_ptr_timing[3]_i_1_n_0 ),
        .D(nxt_rd_ptr[3]),
        .Q(rd_ptr[3]),
        .R(SR));
  (* SOFT_HLUTNM = "soft_lutpair895" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rd_ptr_timing[0]_i_1 
       (.I0(rd_ptr[3]),
        .I1(rd_ptr[0]),
        .O(nxt_rd_ptr[0]));
  (* SOFT_HLUTNM = "soft_lutpair895" *) 
  LUT3 #(
    .INIT(8'hB4)) 
    \rd_ptr_timing[1]_i_1 
       (.I0(rd_ptr[3]),
        .I1(rd_ptr[0]),
        .I2(rd_ptr[1]),
        .O(nxt_rd_ptr[1]));
  (* SOFT_HLUTNM = "soft_lutpair892" *) 
  LUT4 #(
    .INIT(16'hAA6A)) 
    \rd_ptr_timing[2]_i_1 
       (.I0(rd_ptr[2]),
        .I1(rd_ptr[0]),
        .I2(rd_ptr[1]),
        .I3(rd_ptr[3]),
        .O(nxt_rd_ptr[2]));
  LUT2 #(
    .INIT(4'h1)) 
    \rd_ptr_timing[3]_i_1 
       (.I0(\my_empty_reg[7]_0 ),
        .I1(\my_empty_reg_n_0_[7] ),
        .O(\rd_ptr_timing[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair892" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \rd_ptr_timing[3]_i_2 
       (.I0(rd_ptr[3]),
        .I1(rd_ptr[1]),
        .I2(rd_ptr[0]),
        .I3(rd_ptr[2]),
        .O(nxt_rd_ptr[3]));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[0] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(\rd_ptr_timing[3]_i_1_n_0 ),
        .D(nxt_rd_ptr[0]),
        .Q(rd_ptr_timing[0]),
        .R(SR));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[1] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(\rd_ptr_timing[3]_i_1_n_0 ),
        .D(nxt_rd_ptr[1]),
        .Q(rd_ptr_timing[1]),
        .R(SR));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[2] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(\rd_ptr_timing[3]_i_1_n_0 ),
        .D(nxt_rd_ptr[2]),
        .Q(rd_ptr_timing[2]),
        .R(SR));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[3] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(\rd_ptr_timing[3]_i_1_n_0 ),
        .D(nxt_rd_ptr[3]),
        .Q(rd_ptr_timing[3]),
        .R(SR));
  LUT4 #(
    .INIT(16'h082A)) 
    wr_ptr0
       (.I0(phy_cmd_wr_en),
        .I1(\my_empty_reg[7]_0 ),
        .I2(\my_full_reg_n_0_[4] ),
        .I3(\my_empty_reg_n_0_[7] ),
        .O(wr_ptr0__0));
  (* SOFT_HLUTNM = "soft_lutpair894" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \wr_ptr[0]_i_1 
       (.I0(wr_ptr[3]),
        .I1(wr_ptr[0]),
        .O(nxt_wr_ptr[0]));
  (* SOFT_HLUTNM = "soft_lutpair894" *) 
  LUT3 #(
    .INIT(8'hB4)) 
    \wr_ptr[1]_i_1 
       (.I0(wr_ptr[3]),
        .I1(wr_ptr[0]),
        .I2(wr_ptr[1]),
        .O(nxt_wr_ptr[1]));
  (* SOFT_HLUTNM = "soft_lutpair891" *) 
  LUT4 #(
    .INIT(16'hAA6A)) 
    \wr_ptr[2]_i_1 
       (.I0(wr_ptr[2]),
        .I1(wr_ptr[0]),
        .I2(wr_ptr[1]),
        .I3(wr_ptr[3]),
        .O(nxt_wr_ptr[2]));
  (* SOFT_HLUTNM = "soft_lutpair891" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \wr_ptr[3]_i_1 
       (.I0(wr_ptr[3]),
        .I1(wr_ptr[1]),
        .I2(wr_ptr[0]),
        .I3(wr_ptr[2]),
        .O(nxt_wr_ptr[3]));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[0] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(wr_ptr0__0),
        .D(nxt_wr_ptr[0]),
        .Q(wr_ptr[0]),
        .R(SR));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[1] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(wr_ptr0__0),
        .D(nxt_wr_ptr[1]),
        .Q(wr_ptr[1]),
        .R(SR));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[2] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(wr_ptr0__0),
        .D(nxt_wr_ptr[2]),
        .Q(wr_ptr[2]),
        .R(SR));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[3] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(wr_ptr0__0),
        .D(nxt_wr_ptr[3]),
        .Q(wr_ptr[3]),
        .R(SR));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[0] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(wr_ptr0__0),
        .D(nxt_wr_ptr[0]),
        .Q(wr_ptr_timing[0]),
        .R(SR));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[1] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(wr_ptr0__0),
        .D(nxt_wr_ptr[1]),
        .Q(wr_ptr_timing[1]),
        .R(SR));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[2] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(wr_ptr0__0),
        .D(nxt_wr_ptr[2]),
        .Q(wr_ptr_timing[2]),
        .R(SR));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[3] 
       (.C(\wr_ptr_timing_reg[3]_0 ),
        .CE(wr_ptr0__0),
        .D(nxt_wr_ptr[3]),
        .Q(wr_ptr_timing[3]),
        .R(SR));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_of_pre_fifo" *) 
module mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_24
   (\my_empty_reg[1]_0 ,
    \my_empty_reg[1]_1 ,
    D4,
    D5,
    D6,
    D3,
    D1,
    D2,
    mem_out,
    SR,
    \my_full_reg[3]_0 ,
    phy_cmd_wr_en,
    B_of_full,
    mc_we_n,
    out_fifo,
    mc_ras_n,
    mc_cs_n,
    mc_cas_n,
    out_fifo_i_47__8);
  output \my_empty_reg[1]_0 ;
  output \my_empty_reg[1]_1 ;
  output [6:0]D4;
  output [5:0]D5;
  output [6:0]D6;
  output [7:0]D3;
  output [3:0]D1;
  output [3:0]D2;
  output [11:0]mem_out;
  input [0:0]SR;
  input \my_full_reg[3]_0 ;
  input phy_cmd_wr_en;
  input B_of_full;
  input [1:0]mc_we_n;
  input out_fifo;
  input [1:0]mc_ras_n;
  input [0:0]mc_cs_n;
  input [1:0]mc_cas_n;
  input [12:0]out_fifo_i_47__8;

  wire B_of_full;
  wire [3:0]D1;
  wire [3:0]D2;
  wire [7:0]D3;
  wire [6:0]D4;
  wire [5:0]D5;
  wire [6:0]D6;
  wire [0:0]SR;
  wire [1:0]mc_cas_n;
  wire [0:0]mc_cs_n;
  wire [1:0]mc_ras_n;
  wire [1:0]mc_we_n;
  wire [11:0]mem_out;
  wire [55:2]mem_out_0;
  wire my_empty0;
  wire \my_empty[1]_i_1_n_0 ;
  wire \my_empty[6]_i_1_n_0 ;
  wire \my_empty[6]_i_3_n_0 ;
  wire \my_empty[6]_i_4_n_0 ;
  wire \my_empty_reg[1]_0 ;
  wire \my_empty_reg[1]_1 ;
  wire \my_empty_reg_n_0_[6] ;
  wire my_full0;
  wire \my_full[3]_i_1_n_0 ;
  wire \my_full[3]_i_3_n_0 ;
  wire \my_full[3]_i_4_n_0 ;
  wire \my_full_reg[3]_0 ;
  wire \my_full_reg_n_0_[3] ;
  wire [3:0]nxt_rd_ptr;
  wire [3:0]nxt_wr_ptr;
  wire out_fifo;
  wire [12:0]out_fifo_i_47__8;
  wire phy_cmd_wr_en;
  wire [3:0]rd_ptr;
  wire \rd_ptr[0]_i_1_n_0 ;
  wire [3:0]rd_ptr_timing;
  (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) wire wr_en;
  wire [3:0]wr_ptr;
  wire wr_ptr0__0;
  wire [3:0]wr_ptr_timing;
  wire [1:0]NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED;

  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "12" *) 
  (* ram_slice_end = "17" *) 
  RAM32M mem_reg_0_15_12_17
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA({1'b0,1'b0}),
        .DIB({1'b0,1'b0}),
        .DIC({out_fifo_i_47__8[0],out_fifo_i_47__8[0]}),
        .DID({1'b0,1'b0}),
        .DOA(mem_out_0[13:12]),
        .DOB(mem_out_0[15:14]),
        .DOC(mem_out[1:0]),
        .DOD(NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED[1:0]),
        .WCLK(\my_full_reg[3]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "18" *) 
  (* ram_slice_end = "23" *) 
  RAM32M mem_reg_0_15_18_23
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA({out_fifo_i_47__8[0],out_fifo_i_47__8[0]}),
        .DIB({1'b0,1'b0}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA(mem_out[3:2]),
        .DOB(mem_out_0[21:20]),
        .DOC(mem_out_0[23:22]),
        .DOD(NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED[1:0]),
        .WCLK(\my_full_reg[3]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "30" *) 
  (* ram_slice_end = "35" *) 
  RAM32M mem_reg_0_15_30_35
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA({1'b0,1'b0}),
        .DIB(out_fifo_i_47__8[2:1]),
        .DIC({1'b1,out_fifo_i_47__8[8]}),
        .DID({1'b0,1'b0}),
        .DOA(mem_out_0[31:30]),
        .DOB({mem_out[4],mem_out_0[32]}),
        .DOC(mem_out_0[35:34]),
        .DOD(NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED[1:0]),
        .WCLK(\my_full_reg[3]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "36" *) 
  (* ram_slice_end = "41" *) 
  RAM32M mem_reg_0_15_36_41
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA({1'b0,1'b0}),
        .DIB({1'b0,1'b0}),
        .DIC(out_fifo_i_47__8[4:3]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out_0[37:36]),
        .DOB(mem_out_0[39:38]),
        .DOC({mem_out[5],mem_out_0[40]}),
        .DOD(NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED[1:0]),
        .WCLK(\my_full_reg[3]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "42" *) 
  (* ram_slice_end = "47" *) 
  RAM32M mem_reg_0_15_42_47
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA({1'b1,out_fifo_i_47__8[5]}),
        .DIB(out_fifo_i_47__8[7:6]),
        .DIC({1'b1,out_fifo_i_47__8[8]}),
        .DID({1'b0,1'b0}),
        .DOA(mem_out_0[43:42]),
        .DOB({mem_out[6],mem_out_0[44]}),
        .DOC(mem_out_0[47:46]),
        .DOD(NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED[1:0]),
        .WCLK(\my_full_reg[3]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "48" *) 
  (* ram_slice_end = "53" *) 
  RAM32M mem_reg_0_15_48_53
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA({1'b0,1'b0}),
        .DIB({1'b0,1'b0}),
        .DIC(out_fifo_i_47__8[10:9]),
        .DID({1'b0,1'b0}),
        .DOA(mem_out_0[49:48]),
        .DOB(mem_out_0[51:50]),
        .DOC({mem_out[7],mem_out_0[52]}),
        .DOD(NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED[1:0]),
        .WCLK(\my_full_reg[3]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "54" *) 
  (* ram_slice_end = "59" *) 
  RAM32M mem_reg_0_15_54_59
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA({1'b1,out_fifo_i_47__8[11]}),
        .DIB({out_fifo_i_47__8[12],out_fifo_i_47__8[12]}),
        .DIC({out_fifo_i_47__8[12],out_fifo_i_47__8[12]}),
        .DID({1'b0,1'b0}),
        .DOA(mem_out_0[55:54]),
        .DOB(mem_out[9:8]),
        .DOC(mem_out[11:10]),
        .DOD(NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED[1:0]),
        .WCLK(\my_full_reg[3]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "ddr_byte_lane_B.ddr_byte_lane_B/of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "6" *) 
  (* ram_slice_end = "11" *) 
  RAM32M mem_reg_0_15_6_11
       (.ADDRA({1'b0,rd_ptr}),
        .ADDRB({1'b0,rd_ptr}),
        .ADDRC({1'b0,rd_ptr}),
        .ADDRD({1'b0,wr_ptr}),
        .DIA({1'b0,1'b0}),
        .DIB({1'b0,1'b0}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA(mem_out_0[7:6]),
        .DOB(mem_out_0[3:2]),
        .DOC(mem_out_0[5:4]),
        .DOD(NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED[1:0]),
        .WCLK(\my_full_reg[3]_0 ),
        .WE(wr_en));
  (* SOFT_HLUTNM = "soft_lutpair866" *) 
  LUT5 #(
    .INIT(32'hC0CCCCCE)) 
    \my_empty[1]_i_1 
       (.I0(my_empty0),
        .I1(\my_empty_reg[1]_0 ),
        .I2(\my_full_reg_n_0_[3] ),
        .I3(phy_cmd_wr_en),
        .I4(B_of_full),
        .O(\my_empty[1]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hC0CCCCCE)) 
    \my_empty[6]_i_1 
       (.I0(my_empty0),
        .I1(\my_empty_reg_n_0_[6] ),
        .I2(\my_full_reg_n_0_[3] ),
        .I3(phy_cmd_wr_en),
        .I4(B_of_full),
        .O(\my_empty[6]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h4A400D08)) 
    \my_empty[6]_i_2 
       (.I0(wr_ptr_timing[2]),
        .I1(\my_empty[6]_i_3_n_0 ),
        .I2(wr_ptr_timing[3]),
        .I3(\my_empty[6]_i_4_n_0 ),
        .I4(rd_ptr[2]),
        .O(my_empty0));
  (* SOFT_HLUTNM = "soft_lutpair865" *) 
  LUT5 #(
    .INIT(32'h00000040)) 
    \my_empty[6]_i_3 
       (.I0(wr_ptr_timing[1]),
        .I1(rd_ptr[0]),
        .I2(rd_ptr[1]),
        .I3(rd_ptr[3]),
        .I4(wr_ptr_timing[0]),
        .O(\my_empty[6]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair865" *) 
  LUT5 #(
    .INIT(32'h84210842)) 
    \my_empty[6]_i_4 
       (.I0(wr_ptr_timing[0]),
        .I1(wr_ptr_timing[1]),
        .I2(rd_ptr[0]),
        .I3(rd_ptr[1]),
        .I4(rd_ptr[3]),
        .O(\my_empty[6]_i_4_n_0 ));
  (* syn_maxfan = "3" *) 
  FDSE \my_empty_reg[1] 
       (.C(\my_full_reg[3]_0 ),
        .CE(1'b1),
        .D(\my_empty[1]_i_1_n_0 ),
        .Q(\my_empty_reg[1]_0 ),
        .S(SR));
  (* syn_maxfan = "3" *) 
  FDSE \my_empty_reg[6] 
       (.C(\my_full_reg[3]_0 ),
        .CE(1'b1),
        .D(\my_empty[6]_i_1_n_0 ),
        .Q(\my_empty_reg_n_0_[6] ),
        .S(SR));
  LUT6 #(
    .INIT(64'h00000000FFFC0080)) 
    \my_full[3]_i_1 
       (.I0(my_full0),
        .I1(phy_cmd_wr_en),
        .I2(B_of_full),
        .I3(\my_empty_reg_n_0_[6] ),
        .I4(\my_full_reg_n_0_[3] ),
        .I5(SR),
        .O(\my_full[3]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h4A400D08)) 
    \my_full[3]_i_2 
       (.I0(rd_ptr_timing[2]),
        .I1(\my_full[3]_i_3_n_0 ),
        .I2(rd_ptr_timing[3]),
        .I3(\my_full[3]_i_4_n_0 ),
        .I4(wr_ptr[2]),
        .O(my_full0));
  (* SOFT_HLUTNM = "soft_lutpair864" *) 
  LUT5 #(
    .INIT(32'h00000040)) 
    \my_full[3]_i_3 
       (.I0(rd_ptr_timing[1]),
        .I1(wr_ptr[0]),
        .I2(wr_ptr[1]),
        .I3(wr_ptr[3]),
        .I4(rd_ptr_timing[0]),
        .O(\my_full[3]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair864" *) 
  LUT5 #(
    .INIT(32'h84210842)) 
    \my_full[3]_i_4 
       (.I0(rd_ptr_timing[0]),
        .I1(rd_ptr_timing[1]),
        .I2(wr_ptr[0]),
        .I3(wr_ptr[1]),
        .I4(wr_ptr[3]),
        .O(\my_full[3]_i_4_n_0 ));
  (* syn_maxfan = "3" *) 
  FDRE \my_full_reg[3] 
       (.C(\my_full_reg[3]_0 ),
        .CE(1'b1),
        .D(\my_full[3]_i_1_n_0 ),
        .Q(\my_full_reg_n_0_[3] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair882" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_10__0
       (.I0(mem_out_0[13]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D1[1]));
  (* SOFT_HLUTNM = "soft_lutpair873" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_11__0
       (.I0(mem_out_0[12]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D1[0]));
  (* SOFT_HLUTNM = "soft_lutpair879" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_12__0
       (.I0(mem_out_0[23]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D2[3]));
  (* SOFT_HLUTNM = "soft_lutpair880" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_13__0
       (.I0(mem_out_0[22]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D2[2]));
  (* SOFT_HLUTNM = "soft_lutpair884" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_14
       (.I0(mem_out_0[21]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D2[1]));
  (* SOFT_HLUTNM = "soft_lutpair875" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_15
       (.I0(mem_out_0[20]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D2[0]));
  (* SOFT_HLUTNM = "soft_lutpair866" *) 
  LUT3 #(
    .INIT(8'h0D)) 
    out_fifo_i_1__8
       (.I0(\my_empty_reg[1]_0 ),
        .I1(phy_cmd_wr_en),
        .I2(B_of_full),
        .O(\my_empty_reg[1]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair886" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_20
       (.I0(mem_out_0[31]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D3[7]));
  (* SOFT_HLUTNM = "soft_lutpair883" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_21
       (.I0(mem_out_0[30]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D3[6]));
  (* SOFT_HLUTNM = "soft_lutpair886" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_22
       (.I0(mem_out_0[39]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D4[6]));
  (* SOFT_HLUTNM = "soft_lutpair881" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_23
       (.I0(mem_out_0[38]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D4[5]));
  (* SOFT_HLUTNM = "soft_lutpair887" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_24
       (.I0(mem_out_0[37]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D4[4]));
  (* SOFT_HLUTNM = "soft_lutpair878" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_25
       (.I0(mem_out_0[36]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D4[3]));
  (* SOFT_HLUTNM = "soft_lutpair888" *) 
  LUT2 #(
    .INIT(4'hE)) 
    out_fifo_i_26
       (.I0(mem_out_0[35]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D4[2]));
  (* SOFT_HLUTNM = "soft_lutpair867" *) 
  LUT4 #(
    .INIT(16'hBBF0)) 
    out_fifo_i_27__9
       (.I0(mc_ras_n[1]),
        .I1(out_fifo),
        .I2(mem_out_0[34]),
        .I3(\my_empty_reg[1]_0 ),
        .O(D4[1]));
  (* SOFT_HLUTNM = "soft_lutpair875" *) 
  LUT4 #(
    .INIT(16'hBBF0)) 
    out_fifo_i_29__9
       (.I0(mc_cs_n),
        .I1(out_fifo),
        .I2(mem_out_0[32]),
        .I3(\my_empty_reg[1]_0 ),
        .O(D4[0]));
  (* SOFT_HLUTNM = "soft_lutpair880" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_2__6
       (.I0(mem_out_0[7]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D3[1]));
  (* SOFT_HLUTNM = "soft_lutpair883" *) 
  LUT2 #(
    .INIT(4'hE)) 
    out_fifo_i_30__0
       (.I0(mem_out_0[47]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D5[5]));
  (* SOFT_HLUTNM = "soft_lutpair867" *) 
  LUT4 #(
    .INIT(16'hBBF0)) 
    out_fifo_i_31__9
       (.I0(mc_ras_n[1]),
        .I1(out_fifo),
        .I2(mem_out_0[46]),
        .I3(\my_empty_reg[1]_0 ),
        .O(D5[4]));
  (* SOFT_HLUTNM = "soft_lutpair870" *) 
  LUT4 #(
    .INIT(16'hBBF0)) 
    out_fifo_i_33__9
       (.I0(mc_ras_n[0]),
        .I1(out_fifo),
        .I2(mem_out_0[44]),
        .I3(\my_empty_reg[1]_0 ),
        .O(D5[3]));
  (* SOFT_HLUTNM = "soft_lutpair885" *) 
  LUT2 #(
    .INIT(4'hE)) 
    out_fifo_i_34__0
       (.I0(mem_out_0[43]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D5[2]));
  (* SOFT_HLUTNM = "soft_lutpair871" *) 
  LUT4 #(
    .INIT(16'hBBF0)) 
    out_fifo_i_35__9
       (.I0(mc_cas_n[1]),
        .I1(out_fifo),
        .I2(mem_out_0[42]),
        .I3(\my_empty_reg[1]_0 ),
        .O(D5[1]));
  (* SOFT_HLUTNM = "soft_lutpair872" *) 
  LUT4 #(
    .INIT(16'hBBF0)) 
    out_fifo_i_37__9
       (.I0(mc_cas_n[0]),
        .I1(out_fifo),
        .I2(mem_out_0[40]),
        .I3(\my_empty_reg[1]_0 ),
        .O(D5[0]));
  (* SOFT_HLUTNM = "soft_lutpair888" *) 
  LUT2 #(
    .INIT(4'hE)) 
    out_fifo_i_38__0
       (.I0(mem_out_0[55]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D6[6]));
  (* SOFT_HLUTNM = "soft_lutpair874" *) 
  LUT4 #(
    .INIT(16'hBBF0)) 
    out_fifo_i_39__9
       (.I0(mc_we_n[1]),
        .I1(out_fifo),
        .I2(mem_out_0[54]),
        .I3(\my_empty_reg[1]_0 ),
        .O(D6[5]));
  (* SOFT_HLUTNM = "soft_lutpair872" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_3__6
       (.I0(mem_out_0[6]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D3[0]));
  (* SOFT_HLUTNM = "soft_lutpair873" *) 
  LUT4 #(
    .INIT(16'hBBF0)) 
    out_fifo_i_41__9
       (.I0(mc_we_n[0]),
        .I1(out_fifo),
        .I2(mem_out_0[52]),
        .I3(\my_empty_reg[1]_0 ),
        .O(D6[4]));
  (* SOFT_HLUTNM = "soft_lutpair887" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_42__0
       (.I0(mem_out_0[51]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D6[3]));
  (* SOFT_HLUTNM = "soft_lutpair884" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_43__0
       (.I0(mem_out_0[50]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D6[2]));
  (* SOFT_HLUTNM = "soft_lutpair885" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_44__0
       (.I0(mem_out_0[49]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D6[1]));
  (* SOFT_HLUTNM = "soft_lutpair882" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_45__0
       (.I0(mem_out_0[48]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D6[0]));
  (* SOFT_HLUTNM = "soft_lutpair881" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_4__6
       (.I0(mem_out_0[5]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D3[5]));
  (* SOFT_HLUTNM = "soft_lutpair874" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_5__6
       (.I0(mem_out_0[4]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D3[4]));
  (* SOFT_HLUTNM = "soft_lutpair878" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_6__6
       (.I0(mem_out_0[3]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D3[3]));
  (* SOFT_HLUTNM = "soft_lutpair870" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_7__6
       (.I0(mem_out_0[2]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D3[2]));
  (* SOFT_HLUTNM = "soft_lutpair879" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_8__6
       (.I0(mem_out_0[15]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D1[3]));
  (* SOFT_HLUTNM = "soft_lutpair871" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_9__6
       (.I0(mem_out_0[14]),
        .I1(\my_empty_reg[1]_0 ),
        .O(D1[2]));
  LUT4 #(
    .INIT(16'h2700)) 
    p_17_out
       (.I0(B_of_full),
        .I1(\my_full_reg_n_0_[3] ),
        .I2(\my_empty_reg[1]_0 ),
        .I3(phy_cmd_wr_en),
        .O(wr_en));
  LUT2 #(
    .INIT(4'h1)) 
    \rd_ptr[0]_i_1 
       (.I0(B_of_full),
        .I1(\my_empty_reg_n_0_[6] ),
        .O(\rd_ptr[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair876" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rd_ptr[0]_i_2 
       (.I0(rd_ptr[3]),
        .I1(rd_ptr[0]),
        .O(nxt_rd_ptr[0]));
  (* SOFT_HLUTNM = "soft_lutpair876" *) 
  LUT3 #(
    .INIT(8'hB4)) 
    \rd_ptr[1]_i_1 
       (.I0(rd_ptr[3]),
        .I1(rd_ptr[0]),
        .I2(rd_ptr[1]),
        .O(nxt_rd_ptr[1]));
  (* SOFT_HLUTNM = "soft_lutpair869" *) 
  LUT4 #(
    .INIT(16'hAA6A)) 
    \rd_ptr[2]_i_1 
       (.I0(rd_ptr[2]),
        .I1(rd_ptr[0]),
        .I2(rd_ptr[1]),
        .I3(rd_ptr[3]),
        .O(nxt_rd_ptr[2]));
  (* SOFT_HLUTNM = "soft_lutpair869" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \rd_ptr[3]_i_1 
       (.I0(rd_ptr[3]),
        .I1(rd_ptr[1]),
        .I2(rd_ptr[0]),
        .I3(rd_ptr[2]),
        .O(nxt_rd_ptr[3]));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[0] 
       (.C(\my_full_reg[3]_0 ),
        .CE(\rd_ptr[0]_i_1_n_0 ),
        .D(nxt_rd_ptr[0]),
        .Q(rd_ptr[0]),
        .R(SR));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[1] 
       (.C(\my_full_reg[3]_0 ),
        .CE(\rd_ptr[0]_i_1_n_0 ),
        .D(nxt_rd_ptr[1]),
        .Q(rd_ptr[1]),
        .R(SR));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[2] 
       (.C(\my_full_reg[3]_0 ),
        .CE(\rd_ptr[0]_i_1_n_0 ),
        .D(nxt_rd_ptr[2]),
        .Q(rd_ptr[2]),
        .R(SR));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[3] 
       (.C(\my_full_reg[3]_0 ),
        .CE(\rd_ptr[0]_i_1_n_0 ),
        .D(nxt_rd_ptr[3]),
        .Q(rd_ptr[3]),
        .R(SR));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[0] 
       (.C(\my_full_reg[3]_0 ),
        .CE(\rd_ptr[0]_i_1_n_0 ),
        .D(nxt_rd_ptr[0]),
        .Q(rd_ptr_timing[0]),
        .R(SR));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[1] 
       (.C(\my_full_reg[3]_0 ),
        .CE(\rd_ptr[0]_i_1_n_0 ),
        .D(nxt_rd_ptr[1]),
        .Q(rd_ptr_timing[1]),
        .R(SR));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[2] 
       (.C(\my_full_reg[3]_0 ),
        .CE(\rd_ptr[0]_i_1_n_0 ),
        .D(nxt_rd_ptr[2]),
        .Q(rd_ptr_timing[2]),
        .R(SR));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[3] 
       (.C(\my_full_reg[3]_0 ),
        .CE(\rd_ptr[0]_i_1_n_0 ),
        .D(nxt_rd_ptr[3]),
        .Q(rd_ptr_timing[3]),
        .R(SR));
  LUT4 #(
    .INIT(16'h082A)) 
    wr_ptr0
       (.I0(phy_cmd_wr_en),
        .I1(B_of_full),
        .I2(\my_full_reg_n_0_[3] ),
        .I3(\my_empty_reg_n_0_[6] ),
        .O(wr_ptr0__0));
  (* SOFT_HLUTNM = "soft_lutpair877" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \wr_ptr[0]_i_1__16 
       (.I0(wr_ptr[3]),
        .I1(wr_ptr[0]),
        .O(nxt_wr_ptr[0]));
  (* SOFT_HLUTNM = "soft_lutpair877" *) 
  LUT3 #(
    .INIT(8'hB4)) 
    \wr_ptr[1]_i_1__16 
       (.I0(wr_ptr[3]),
        .I1(wr_ptr[0]),
        .I2(wr_ptr[1]),
        .O(nxt_wr_ptr[1]));
  (* SOFT_HLUTNM = "soft_lutpair868" *) 
  LUT4 #(
    .INIT(16'hAA6A)) 
    \wr_ptr[2]_i_1__8 
       (.I0(wr_ptr[2]),
        .I1(wr_ptr[0]),
        .I2(wr_ptr[1]),
        .I3(wr_ptr[3]),
        .O(nxt_wr_ptr[2]));
  (* SOFT_HLUTNM = "soft_lutpair868" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \wr_ptr[3]_i_1__8 
       (.I0(wr_ptr[3]),
        .I1(wr_ptr[1]),
        .I2(wr_ptr[0]),
        .I3(wr_ptr[2]),
        .O(nxt_wr_ptr[3]));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[0] 
       (.C(\my_full_reg[3]_0 ),
        .CE(wr_ptr0__0),
        .D(nxt_wr_ptr[0]),
        .Q(wr_ptr[0]),
        .R(SR));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[1] 
       (.C(\my_full_reg[3]_0 ),
        .CE(wr_ptr0__0),
        .D(nxt_wr_ptr[1]),
        .Q(wr_ptr[1]),
        .R(SR));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[2] 
       (.C(\my_full_reg[3]_0 ),
        .CE(wr_ptr0__0),
        .D(nxt_wr_ptr[2]),
        .Q(wr_ptr[2]),
        .R(SR));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[3] 
       (.C(\my_full_reg[3]_0 ),
        .CE(wr_ptr0__0),
        .D(nxt_wr_ptr[3]),
        .Q(wr_ptr[3]),
        .R(SR));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[0] 
       (.C(\my_full_reg[3]_0 ),
        .CE(wr_ptr0__0),
        .D(nxt_wr_ptr[0]),
        .Q(wr_ptr_timing[0]),
        .R(SR));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[1] 
       (.C(\my_full_reg[3]_0 ),
        .CE(wr_ptr0__0),
        .D(nxt_wr_ptr[1]),
        .Q(wr_ptr_timing[1]),
        .R(SR));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[2] 
       (.C(\my_full_reg[3]_0 ),
        .CE(wr_ptr0__0),
        .D(nxt_wr_ptr[2]),
        .Q(wr_ptr_timing[2]),
        .R(SR));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[3] 
       (.C(\my_full_reg[3]_0 ),
        .CE(wr_ptr0__0),
        .D(nxt_wr_ptr[3]),
        .Q(wr_ptr_timing[3]),
        .R(SR));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_of_pre_fifo" *) 
module mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_31
   (\my_empty_reg[1]_0 ,
    \my_empty_reg[1]_1 ,
    D0,
    D1,
    \rd_ptr_reg[3]_0 ,
    Q,
    ofifo_rst,
    \entry_cnt_reg[4]_0 ,
    \my_empty_reg[7]_0 ,
    phy_data_wr_en,
    out_fifo,
    out_fifo_0,
    out_fifo_1,
    out_fifo_i_75__7);
  output \my_empty_reg[1]_0 ;
  output \my_empty_reg[1]_1 ;
  output [7:0]D0;
  output [7:0]D1;
  output [63:0]\rd_ptr_reg[3]_0 ;
  output [2:0]Q;
  input ofifo_rst;
  input \entry_cnt_reg[4]_0 ;
  input \my_empty_reg[7]_0 ;
  input phy_data_wr_en;
  input out_fifo;
  input [7:0]out_fifo_0;
  input out_fifo_1;
  input [71:0]out_fifo_i_75__7;

  wire [7:0]D0;
  wire [7:0]D1;
  wire [2:0]Q;
  wire entry_cnt10_out__0;
  wire \entry_cnt[0]_i_1__2_n_0 ;
  wire \entry_cnt[1]_i_1__2_n_0 ;
  wire \entry_cnt[2]_i_1__2_n_0 ;
  wire \entry_cnt[3]_i_1__2_n_0 ;
  wire \entry_cnt[4]_i_1__2_n_0 ;
  wire \entry_cnt[4]_i_2__2_n_0 ;
  wire \entry_cnt_reg[4]_0 ;
  wire \entry_cnt_reg_n_0_[0] ;
  wire \entry_cnt_reg_n_0_[1] ;
  wire mem_reg_0_15_0_5_n_0;
  wire mem_reg_0_15_0_5_n_1;
  wire mem_reg_0_15_0_5_n_2;
  wire mem_reg_0_15_0_5_n_3;
  wire mem_reg_0_15_0_5_n_4;
  wire mem_reg_0_15_0_5_n_5;
  wire mem_reg_0_15_12_17_n_0;
  wire mem_reg_0_15_12_17_n_1;
  wire mem_reg_0_15_12_17_n_2;
  wire mem_reg_0_15_12_17_n_3;
  wire mem_reg_0_15_6_11_n_0;
  wire mem_reg_0_15_6_11_n_1;
  wire mem_reg_0_15_6_11_n_2;
  wire mem_reg_0_15_6_11_n_3;
  wire mem_reg_0_15_6_11_n_4;
  wire mem_reg_0_15_6_11_n_5;
  wire my_empty0;
  wire \my_empty[1]_i_1__3_n_0 ;
  wire \my_empty[7]_i_1__3_n_0 ;
  wire \my_empty[7]_i_3__3_n_0 ;
  wire \my_empty[7]_i_4__3_n_0 ;
  wire \my_empty_reg[1]_0 ;
  wire \my_empty_reg[1]_1 ;
  wire \my_empty_reg[7]_0 ;
  wire \my_empty_reg_n_0_[7] ;
  wire my_full0;
  wire \my_full[4]_i_1__3_n_0 ;
  wire \my_full[4]_i_3__3_n_0 ;
  wire \my_full[4]_i_4__3_n_0 ;
  wire \my_full_reg_n_0_[4] ;
  wire [3:0]nxt_rd_ptr;
  wire [3:0]nxt_wr_ptr;
  wire ofifo_rst;
  wire out_fifo;
  wire [7:0]out_fifo_0;
  wire out_fifo_1;
  wire [71:0]out_fifo_i_75__7;
  wire phy_data_wr_en;
  wire [63:0]\rd_ptr_reg[3]_0 ;
  wire \rd_ptr_reg_n_0_[0] ;
  wire \rd_ptr_reg_n_0_[1] ;
  wire \rd_ptr_reg_n_0_[2] ;
  wire \rd_ptr_reg_n_0_[3] ;
  wire [3:0]rd_ptr_timing;
  wire \rd_ptr_timing[3]_i_1__3_n_0 ;
  (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) wire wr_en;
  wire [3:0]wr_ptr;
  wire wr_ptr0;
  wire [3:0]wr_ptr_timing;
  wire [1:0]NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED;

  (* SOFT_HLUTNM = "soft_lutpair849" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \entry_cnt[0]_i_1__2 
       (.I0(\entry_cnt_reg_n_0_[0] ),
        .O(\entry_cnt[0]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair848" *) 
  LUT5 #(
    .INIT(32'hAA6A5595)) 
    \entry_cnt[1]_i_1__2 
       (.I0(\entry_cnt_reg_n_0_[0] ),
        .I1(\my_empty_reg[7]_0 ),
        .I2(phy_data_wr_en),
        .I3(\my_full_reg_n_0_[4] ),
        .I4(\entry_cnt_reg_n_0_[1] ),
        .O(\entry_cnt[1]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hFF7F0080AAEA5515)) 
    \entry_cnt[2]_i_1__2 
       (.I0(\entry_cnt_reg_n_0_[0] ),
        .I1(\my_empty_reg[7]_0 ),
        .I2(phy_data_wr_en),
        .I3(\my_full_reg_n_0_[4] ),
        .I4(Q[0]),
        .I5(\entry_cnt_reg_n_0_[1] ),
        .O(\entry_cnt[2]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair849" *) 
  LUT5 #(
    .INIT(32'h7F80FE01)) 
    \entry_cnt[3]_i_1__2 
       (.I0(entry_cnt10_out__0),
        .I1(\entry_cnt_reg_n_0_[0] ),
        .I2(\entry_cnt_reg_n_0_[1] ),
        .I3(Q[1]),
        .I4(Q[0]),
        .O(\entry_cnt[3]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h5003)) 
    \entry_cnt[4]_i_1__2 
       (.I0(\my_full_reg_n_0_[4] ),
        .I1(\my_empty_reg_n_0_[7] ),
        .I2(\my_empty_reg[7]_0 ),
        .I3(phy_data_wr_en),
        .O(\entry_cnt[4]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'h7FFF8000FFFE0001)) 
    \entry_cnt[4]_i_2__2 
       (.I0(\entry_cnt_reg_n_0_[1] ),
        .I1(\entry_cnt_reg_n_0_[0] ),
        .I2(entry_cnt10_out__0),
        .I3(Q[0]),
        .I4(Q[2]),
        .I5(Q[1]),
        .O(\entry_cnt[4]_i_2__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair848" *) 
  LUT3 #(
    .INIT(8'h08)) 
    \entry_cnt[4]_i_3__2 
       (.I0(\my_empty_reg[7]_0 ),
        .I1(phy_data_wr_en),
        .I2(\my_full_reg_n_0_[4] ),
        .O(entry_cnt10_out__0));
  FDRE \entry_cnt_reg[0] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(\entry_cnt[4]_i_1__2_n_0 ),
        .D(\entry_cnt[0]_i_1__2_n_0 ),
        .Q(\entry_cnt_reg_n_0_[0] ),
        .R(ofifo_rst));
  FDRE \entry_cnt_reg[1] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(\entry_cnt[4]_i_1__2_n_0 ),
        .D(\entry_cnt[1]_i_1__2_n_0 ),
        .Q(\entry_cnt_reg_n_0_[1] ),
        .R(ofifo_rst));
  FDRE \entry_cnt_reg[2] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(\entry_cnt[4]_i_1__2_n_0 ),
        .D(\entry_cnt[2]_i_1__2_n_0 ),
        .Q(Q[0]),
        .R(ofifo_rst));
  FDRE \entry_cnt_reg[3] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(\entry_cnt[4]_i_1__2_n_0 ),
        .D(\entry_cnt[3]_i_1__2_n_0 ),
        .Q(Q[1]),
        .R(ofifo_rst));
  FDRE \entry_cnt_reg[4] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(\entry_cnt[4]_i_1__2_n_0 ),
        .D(\entry_cnt[4]_i_2__2_n_0 ),
        .Q(Q[2]),
        .R(ofifo_rst));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "0" *) 
  (* ram_slice_end = "5" *) 
  RAM32M mem_reg_0_15_0_5
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA({1'b0,1'b0}),
        .DIB({1'b0,1'b0}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA({mem_reg_0_15_0_5_n_0,mem_reg_0_15_0_5_n_1}),
        .DOB({mem_reg_0_15_0_5_n_2,mem_reg_0_15_0_5_n_3}),
        .DOC({mem_reg_0_15_0_5_n_4,mem_reg_0_15_0_5_n_5}),
        .DOD(NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED[1:0]),
        .WCLK(\entry_cnt_reg[4]_0 ),
        .WE(wr_en));
  LUT4 #(
    .INIT(16'h2700)) 
    mem_reg_0_15_0_5_i_1__2
       (.I0(\my_empty_reg[7]_0 ),
        .I1(\my_full_reg_n_0_[4] ),
        .I2(\my_empty_reg[1]_1 ),
        .I3(phy_data_wr_en),
        .O(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "12" *) 
  (* ram_slice_end = "17" *) 
  RAM32M mem_reg_0_15_12_17
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__7[5:4]),
        .DIB(out_fifo_i_75__7[7:6]),
        .DIC(out_fifo_i_75__7[9:8]),
        .DID({1'b0,1'b0}),
        .DOA({mem_reg_0_15_12_17_n_0,mem_reg_0_15_12_17_n_1}),
        .DOB({mem_reg_0_15_12_17_n_2,mem_reg_0_15_12_17_n_3}),
        .DOC(\rd_ptr_reg[3]_0 [1:0]),
        .DOD(NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED[1:0]),
        .WCLK(\entry_cnt_reg[4]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "18" *) 
  (* ram_slice_end = "23" *) 
  RAM32M mem_reg_0_15_18_23
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__7[11:10]),
        .DIB(out_fifo_i_75__7[13:12]),
        .DIC(out_fifo_i_75__7[15:14]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [3:2]),
        .DOB(\rd_ptr_reg[3]_0 [5:4]),
        .DOC(\rd_ptr_reg[3]_0 [7:6]),
        .DOD(NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED[1:0]),
        .WCLK(\entry_cnt_reg[4]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "24" *) 
  (* ram_slice_end = "29" *) 
  RAM32M mem_reg_0_15_24_29
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__7[17:16]),
        .DIB(out_fifo_i_75__7[19:18]),
        .DIC(out_fifo_i_75__7[21:20]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [9:8]),
        .DOB(\rd_ptr_reg[3]_0 [11:10]),
        .DOC(\rd_ptr_reg[3]_0 [13:12]),
        .DOD(NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED[1:0]),
        .WCLK(\entry_cnt_reg[4]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "30" *) 
  (* ram_slice_end = "35" *) 
  RAM32M mem_reg_0_15_30_35
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__7[23:22]),
        .DIB(out_fifo_i_75__7[25:24]),
        .DIC(out_fifo_i_75__7[27:26]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [15:14]),
        .DOB(\rd_ptr_reg[3]_0 [17:16]),
        .DOC(\rd_ptr_reg[3]_0 [19:18]),
        .DOD(NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED[1:0]),
        .WCLK(\entry_cnt_reg[4]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "36" *) 
  (* ram_slice_end = "41" *) 
  RAM32M mem_reg_0_15_36_41
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__7[29:28]),
        .DIB(out_fifo_i_75__7[31:30]),
        .DIC(out_fifo_i_75__7[33:32]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [21:20]),
        .DOB(\rd_ptr_reg[3]_0 [23:22]),
        .DOC(\rd_ptr_reg[3]_0 [25:24]),
        .DOD(NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED[1:0]),
        .WCLK(\entry_cnt_reg[4]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "42" *) 
  (* ram_slice_end = "47" *) 
  RAM32M mem_reg_0_15_42_47
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__7[35:34]),
        .DIB(out_fifo_i_75__7[37:36]),
        .DIC(out_fifo_i_75__7[39:38]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [27:26]),
        .DOB(\rd_ptr_reg[3]_0 [29:28]),
        .DOC(\rd_ptr_reg[3]_0 [31:30]),
        .DOD(NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED[1:0]),
        .WCLK(\entry_cnt_reg[4]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "48" *) 
  (* ram_slice_end = "53" *) 
  RAM32M mem_reg_0_15_48_53
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__7[41:40]),
        .DIB(out_fifo_i_75__7[43:42]),
        .DIC(out_fifo_i_75__7[45:44]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [33:32]),
        .DOB(\rd_ptr_reg[3]_0 [35:34]),
        .DOC(\rd_ptr_reg[3]_0 [37:36]),
        .DOD(NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED[1:0]),
        .WCLK(\entry_cnt_reg[4]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "54" *) 
  (* ram_slice_end = "59" *) 
  RAM32M mem_reg_0_15_54_59
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__7[47:46]),
        .DIB(out_fifo_i_75__7[49:48]),
        .DIC(out_fifo_i_75__7[51:50]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [39:38]),
        .DOB(\rd_ptr_reg[3]_0 [41:40]),
        .DOC(\rd_ptr_reg[3]_0 [43:42]),
        .DOD(NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED[1:0]),
        .WCLK(\entry_cnt_reg[4]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "60" *) 
  (* ram_slice_end = "65" *) 
  RAM32M mem_reg_0_15_60_65
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__7[53:52]),
        .DIB(out_fifo_i_75__7[55:54]),
        .DIC(out_fifo_i_75__7[57:56]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [45:44]),
        .DOB(\rd_ptr_reg[3]_0 [47:46]),
        .DOC(\rd_ptr_reg[3]_0 [49:48]),
        .DOD(NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED[1:0]),
        .WCLK(\entry_cnt_reg[4]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "66" *) 
  (* ram_slice_end = "71" *) 
  RAM32M mem_reg_0_15_66_71
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__7[59:58]),
        .DIB(out_fifo_i_75__7[61:60]),
        .DIC(out_fifo_i_75__7[63:62]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [51:50]),
        .DOB(\rd_ptr_reg[3]_0 [53:52]),
        .DOC(\rd_ptr_reg[3]_0 [55:54]),
        .DOD(NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED[1:0]),
        .WCLK(\entry_cnt_reg[4]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "6" *) 
  (* ram_slice_end = "11" *) 
  RAM32M mem_reg_0_15_6_11
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA({1'b0,1'b0}),
        .DIB(out_fifo_i_75__7[1:0]),
        .DIC(out_fifo_i_75__7[3:2]),
        .DID({1'b0,1'b0}),
        .DOA({mem_reg_0_15_6_11_n_0,mem_reg_0_15_6_11_n_1}),
        .DOB({mem_reg_0_15_6_11_n_2,mem_reg_0_15_6_11_n_3}),
        .DOC({mem_reg_0_15_6_11_n_4,mem_reg_0_15_6_11_n_5}),
        .DOD(NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED[1:0]),
        .WCLK(\entry_cnt_reg[4]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "72" *) 
  (* ram_slice_end = "77" *) 
  RAM32M mem_reg_0_15_72_77
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__7[65:64]),
        .DIB(out_fifo_i_75__7[67:66]),
        .DIC(out_fifo_i_75__7[69:68]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [57:56]),
        .DOB(\rd_ptr_reg[3]_0 [59:58]),
        .DOC(\rd_ptr_reg[3]_0 [61:60]),
        .DOD(NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED[1:0]),
        .WCLK(\entry_cnt_reg[4]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "78" *) 
  (* ram_slice_end = "79" *) 
  RAM32M mem_reg_0_15_78_79
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__7[71:70]),
        .DIB({1'b0,1'b0}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [63:62]),
        .DOB(NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED[1:0]),
        .DOC(NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED[1:0]),
        .DOD(NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED[1:0]),
        .WCLK(\entry_cnt_reg[4]_0 ),
        .WE(wr_en));
  LUT6 #(
    .INIT(64'hFFFFFFFFF701F700)) 
    \my_empty[1]_i_1__3 
       (.I0(\my_empty_reg[7]_0 ),
        .I1(phy_data_wr_en),
        .I2(\my_full_reg_n_0_[4] ),
        .I3(\my_empty_reg[1]_1 ),
        .I4(my_empty0),
        .I5(ofifo_rst),
        .O(\my_empty[1]_i_1__3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFF701F700)) 
    \my_empty[7]_i_1__3 
       (.I0(\my_empty_reg[7]_0 ),
        .I1(phy_data_wr_en),
        .I2(\my_full_reg_n_0_[4] ),
        .I3(\my_empty_reg_n_0_[7] ),
        .I4(my_empty0),
        .I5(ofifo_rst),
        .O(\my_empty[7]_i_1__3_n_0 ));
  LUT5 #(
    .INIT(32'h4A400D08)) 
    \my_empty[7]_i_2__3 
       (.I0(wr_ptr_timing[2]),
        .I1(\my_empty[7]_i_3__3_n_0 ),
        .I2(wr_ptr_timing[3]),
        .I3(\my_empty[7]_i_4__3_n_0 ),
        .I4(\rd_ptr_reg_n_0_[2] ),
        .O(my_empty0));
  (* SOFT_HLUTNM = "soft_lutpair851" *) 
  LUT5 #(
    .INIT(32'h00000040)) 
    \my_empty[7]_i_3__3 
       (.I0(wr_ptr_timing[1]),
        .I1(\rd_ptr_reg_n_0_[0] ),
        .I2(\rd_ptr_reg_n_0_[1] ),
        .I3(\rd_ptr_reg_n_0_[3] ),
        .I4(wr_ptr_timing[0]),
        .O(\my_empty[7]_i_3__3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair851" *) 
  LUT5 #(
    .INIT(32'h84210842)) 
    \my_empty[7]_i_4__3 
       (.I0(wr_ptr_timing[0]),
        .I1(wr_ptr_timing[1]),
        .I2(\rd_ptr_reg_n_0_[0] ),
        .I3(\rd_ptr_reg_n_0_[1] ),
        .I4(\rd_ptr_reg_n_0_[3] ),
        .O(\my_empty[7]_i_4__3_n_0 ));
  (* syn_maxfan = "3" *) 
  FDRE \my_empty_reg[1] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(1'b1),
        .D(\my_empty[1]_i_1__3_n_0 ),
        .Q(\my_empty_reg[1]_1 ),
        .R(1'b0));
  (* syn_maxfan = "3" *) 
  FDRE \my_empty_reg[7] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(1'b1),
        .D(\my_empty[7]_i_1__3_n_0 ),
        .Q(\my_empty_reg_n_0_[7] ),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h00000000FFFC0080)) 
    \my_full[4]_i_1__3 
       (.I0(my_full0),
        .I1(phy_data_wr_en),
        .I2(\my_empty_reg[7]_0 ),
        .I3(\my_empty_reg_n_0_[7] ),
        .I4(\my_full_reg_n_0_[4] ),
        .I5(ofifo_rst),
        .O(\my_full[4]_i_1__3_n_0 ));
  LUT5 #(
    .INIT(32'h4A400D08)) 
    \my_full[4]_i_2__3 
       (.I0(rd_ptr_timing[2]),
        .I1(\my_full[4]_i_3__3_n_0 ),
        .I2(rd_ptr_timing[3]),
        .I3(\my_full[4]_i_4__3_n_0 ),
        .I4(wr_ptr[2]),
        .O(my_full0));
  (* SOFT_HLUTNM = "soft_lutpair850" *) 
  LUT5 #(
    .INIT(32'h00000040)) 
    \my_full[4]_i_3__3 
       (.I0(rd_ptr_timing[1]),
        .I1(wr_ptr[0]),
        .I2(wr_ptr[1]),
        .I3(wr_ptr[3]),
        .I4(rd_ptr_timing[0]),
        .O(\my_full[4]_i_3__3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair850" *) 
  LUT5 #(
    .INIT(32'h84210842)) 
    \my_full[4]_i_4__3 
       (.I0(rd_ptr_timing[0]),
        .I1(rd_ptr_timing[1]),
        .I2(wr_ptr[0]),
        .I3(wr_ptr[1]),
        .I4(wr_ptr[3]),
        .O(\my_full[4]_i_4__3_n_0 ));
  (* syn_maxfan = "3" *) 
  FDRE \my_full_reg[4] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(1'b1),
        .D(\my_full[4]_i_1__3_n_0 ),
        .Q(\my_full_reg_n_0_[4] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair852" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_10__9
       (.I0(out_fifo_1),
        .I1(out_fifo_0[7]),
        .I2(mem_reg_0_15_12_17_n_2),
        .I3(\my_empty_reg[1]_1 ),
        .O(D1[7]));
  (* SOFT_HLUTNM = "soft_lutpair859" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_11__9
       (.I0(out_fifo_1),
        .I1(out_fifo_0[6]),
        .I2(mem_reg_0_15_12_17_n_3),
        .I3(\my_empty_reg[1]_1 ),
        .O(D1[6]));
  (* SOFT_HLUTNM = "soft_lutpair854" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_12__9
       (.I0(out_fifo_1),
        .I1(out_fifo_0[5]),
        .I2(mem_reg_0_15_12_17_n_0),
        .I3(\my_empty_reg[1]_1 ),
        .O(D1[5]));
  (* SOFT_HLUTNM = "soft_lutpair857" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_13__9
       (.I0(out_fifo_1),
        .I1(out_fifo_0[4]),
        .I2(mem_reg_0_15_12_17_n_1),
        .I3(\my_empty_reg[1]_1 ),
        .O(D1[4]));
  (* SOFT_HLUTNM = "soft_lutpair855" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_14__9
       (.I0(out_fifo_1),
        .I1(out_fifo_0[3]),
        .I2(mem_reg_0_15_6_11_n_4),
        .I3(\my_empty_reg[1]_1 ),
        .O(D1[3]));
  (* SOFT_HLUTNM = "soft_lutpair856" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_15__9
       (.I0(out_fifo_1),
        .I1(out_fifo_0[2]),
        .I2(mem_reg_0_15_6_11_n_5),
        .I3(\my_empty_reg[1]_1 ),
        .O(D1[2]));
  (* SOFT_HLUTNM = "soft_lutpair853" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_16__9
       (.I0(out_fifo_1),
        .I1(out_fifo_0[1]),
        .I2(mem_reg_0_15_6_11_n_2),
        .I3(\my_empty_reg[1]_1 ),
        .O(D1[1]));
  (* SOFT_HLUTNM = "soft_lutpair861" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_17__9
       (.I0(out_fifo),
        .I1(out_fifo_0[0]),
        .I2(mem_reg_0_15_6_11_n_3),
        .I3(\my_empty_reg[1]_1 ),
        .O(D1[0]));
  LUT3 #(
    .INIT(8'h0D)) 
    out_fifo_i_1__3
       (.I0(\my_empty_reg[1]_1 ),
        .I1(phy_data_wr_en),
        .I2(\my_empty_reg[7]_0 ),
        .O(\my_empty_reg[1]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair857" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_2__2
       (.I0(mem_reg_0_15_6_11_n_0),
        .I1(\my_empty_reg[1]_1 ),
        .O(D0[7]));
  (* SOFT_HLUTNM = "soft_lutpair853" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_3__2
       (.I0(mem_reg_0_15_6_11_n_1),
        .I1(\my_empty_reg[1]_1 ),
        .O(D0[6]));
  (* SOFT_HLUTNM = "soft_lutpair859" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_4__2
       (.I0(mem_reg_0_15_0_5_n_4),
        .I1(\my_empty_reg[1]_1 ),
        .O(D0[5]));
  (* SOFT_HLUTNM = "soft_lutpair855" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_5__2
       (.I0(mem_reg_0_15_0_5_n_5),
        .I1(\my_empty_reg[1]_1 ),
        .O(D0[4]));
  (* SOFT_HLUTNM = "soft_lutpair856" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_6__2
       (.I0(mem_reg_0_15_0_5_n_2),
        .I1(\my_empty_reg[1]_1 ),
        .O(D0[3]));
  (* SOFT_HLUTNM = "soft_lutpair852" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_7__2
       (.I0(mem_reg_0_15_0_5_n_3),
        .I1(\my_empty_reg[1]_1 ),
        .O(D0[2]));
  (* SOFT_HLUTNM = "soft_lutpair861" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_8__2
       (.I0(mem_reg_0_15_0_5_n_0),
        .I1(\my_empty_reg[1]_1 ),
        .O(D0[1]));
  (* SOFT_HLUTNM = "soft_lutpair854" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_9__2
       (.I0(mem_reg_0_15_0_5_n_1),
        .I1(\my_empty_reg[1]_1 ),
        .O(D0[0]));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[0] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(\rd_ptr_timing[3]_i_1__3_n_0 ),
        .D(nxt_rd_ptr[0]),
        .Q(\rd_ptr_reg_n_0_[0] ),
        .R(ofifo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[1] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(\rd_ptr_timing[3]_i_1__3_n_0 ),
        .D(nxt_rd_ptr[1]),
        .Q(\rd_ptr_reg_n_0_[1] ),
        .R(ofifo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[2] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(\rd_ptr_timing[3]_i_1__3_n_0 ),
        .D(nxt_rd_ptr[2]),
        .Q(\rd_ptr_reg_n_0_[2] ),
        .R(ofifo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[3] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(\rd_ptr_timing[3]_i_1__3_n_0 ),
        .D(nxt_rd_ptr[3]),
        .Q(\rd_ptr_reg_n_0_[3] ),
        .R(ofifo_rst));
  (* SOFT_HLUTNM = "soft_lutpair863" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rd_ptr_timing[0]_i_1__7 
       (.I0(\rd_ptr_reg_n_0_[3] ),
        .I1(\rd_ptr_reg_n_0_[0] ),
        .O(nxt_rd_ptr[0]));
  (* SOFT_HLUTNM = "soft_lutpair863" *) 
  LUT3 #(
    .INIT(8'hB4)) 
    \rd_ptr_timing[1]_i_1__7 
       (.I0(\rd_ptr_reg_n_0_[3] ),
        .I1(\rd_ptr_reg_n_0_[0] ),
        .I2(\rd_ptr_reg_n_0_[1] ),
        .O(nxt_rd_ptr[1]));
  (* SOFT_HLUTNM = "soft_lutpair860" *) 
  LUT4 #(
    .INIT(16'hAA6A)) 
    \rd_ptr_timing[2]_i_1__3 
       (.I0(\rd_ptr_reg_n_0_[2] ),
        .I1(\rd_ptr_reg_n_0_[0] ),
        .I2(\rd_ptr_reg_n_0_[1] ),
        .I3(\rd_ptr_reg_n_0_[3] ),
        .O(nxt_rd_ptr[2]));
  LUT2 #(
    .INIT(4'h1)) 
    \rd_ptr_timing[3]_i_1__3 
       (.I0(\my_empty_reg[7]_0 ),
        .I1(\my_empty_reg_n_0_[7] ),
        .O(\rd_ptr_timing[3]_i_1__3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair860" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \rd_ptr_timing[3]_i_2__3 
       (.I0(\rd_ptr_reg_n_0_[3] ),
        .I1(\rd_ptr_reg_n_0_[1] ),
        .I2(\rd_ptr_reg_n_0_[0] ),
        .I3(\rd_ptr_reg_n_0_[2] ),
        .O(nxt_rd_ptr[3]));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[0] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(\rd_ptr_timing[3]_i_1__3_n_0 ),
        .D(nxt_rd_ptr[0]),
        .Q(rd_ptr_timing[0]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[1] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(\rd_ptr_timing[3]_i_1__3_n_0 ),
        .D(nxt_rd_ptr[1]),
        .Q(rd_ptr_timing[1]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[2] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(\rd_ptr_timing[3]_i_1__3_n_0 ),
        .D(nxt_rd_ptr[2]),
        .Q(rd_ptr_timing[2]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[3] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(\rd_ptr_timing[3]_i_1__3_n_0 ),
        .D(nxt_rd_ptr[3]),
        .Q(rd_ptr_timing[3]),
        .R(ofifo_rst));
  (* SOFT_HLUTNM = "soft_lutpair862" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \wr_ptr[0]_i_1__7 
       (.I0(wr_ptr[3]),
        .I1(wr_ptr[0]),
        .O(nxt_wr_ptr[0]));
  (* SOFT_HLUTNM = "soft_lutpair862" *) 
  LUT3 #(
    .INIT(8'hB4)) 
    \wr_ptr[1]_i_1__7 
       (.I0(wr_ptr[3]),
        .I1(wr_ptr[0]),
        .I2(wr_ptr[1]),
        .O(nxt_wr_ptr[1]));
  (* SOFT_HLUTNM = "soft_lutpair858" *) 
  LUT4 #(
    .INIT(16'hAA6A)) 
    \wr_ptr[2]_i_1__3 
       (.I0(wr_ptr[2]),
        .I1(wr_ptr[0]),
        .I2(wr_ptr[1]),
        .I3(wr_ptr[3]),
        .O(nxt_wr_ptr[2]));
  LUT4 #(
    .INIT(16'h082A)) 
    \wr_ptr[3]_i_1__3 
       (.I0(phy_data_wr_en),
        .I1(\my_empty_reg[7]_0 ),
        .I2(\my_full_reg_n_0_[4] ),
        .I3(\my_empty_reg_n_0_[7] ),
        .O(wr_ptr0));
  (* SOFT_HLUTNM = "soft_lutpair858" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \wr_ptr[3]_i_2__2 
       (.I0(wr_ptr[3]),
        .I1(wr_ptr[1]),
        .I2(wr_ptr[0]),
        .I3(wr_ptr[2]),
        .O(nxt_wr_ptr[3]));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[0] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[0]),
        .Q(wr_ptr[0]),
        .R(ofifo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[1] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[1]),
        .Q(wr_ptr[1]),
        .R(ofifo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[2] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[2]),
        .Q(wr_ptr[2]),
        .R(ofifo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[3] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[3]),
        .Q(wr_ptr[3]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[0] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[0]),
        .Q(wr_ptr_timing[0]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[1] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[1]),
        .Q(wr_ptr_timing[1]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[2] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[2]),
        .Q(wr_ptr_timing[2]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[3] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[3]),
        .Q(wr_ptr_timing[3]),
        .R(ofifo_rst));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_of_pre_fifo" *) 
module mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_34
   (phy_mc_data_full,
    \my_empty_reg[1]_0 ,
    \my_empty_reg[1]_1 ,
    D0,
    D1,
    \rd_ptr_reg[3]_0 ,
    Q,
    ofifo_rst,
    \my_full_reg[4]_0 ,
    ofs_rdy_r_reg,
    ofs_rdy_r_reg_0,
    ofs_rdy_r_reg_1,
    ofs_rdy_r_reg_2,
    \my_empty_reg[7]_0 ,
    phy_data_wr_en,
    out_fifo,
    out_fifo_0,
    out_fifo_1,
    out_fifo_i_75__6);
  output phy_mc_data_full;
  output \my_empty_reg[1]_0 ;
  output \my_empty_reg[1]_1 ;
  output [7:0]D0;
  output [7:0]D1;
  output [63:0]\rd_ptr_reg[3]_0 ;
  output [2:0]Q;
  input ofifo_rst;
  input \my_full_reg[4]_0 ;
  input ofs_rdy_r_reg;
  input ofs_rdy_r_reg_0;
  input ofs_rdy_r_reg_1;
  input ofs_rdy_r_reg_2;
  input \my_empty_reg[7]_0 ;
  input phy_data_wr_en;
  input out_fifo;
  input [7:0]out_fifo_0;
  input out_fifo_1;
  input [71:0]out_fifo_i_75__6;

  wire [7:0]D0;
  wire [7:0]D1;
  wire [2:0]Q;
  wire entry_cnt10_out__0;
  wire \entry_cnt[0]_i_1__1_n_0 ;
  wire \entry_cnt[1]_i_1__1_n_0 ;
  wire \entry_cnt[2]_i_1__1_n_0 ;
  wire \entry_cnt[3]_i_1__1_n_0 ;
  wire \entry_cnt[4]_i_1__1_n_0 ;
  wire \entry_cnt[4]_i_2__1_n_0 ;
  wire \entry_cnt_reg_n_0_[0] ;
  wire \entry_cnt_reg_n_0_[1] ;
  wire mem_reg_0_15_0_5_n_0;
  wire mem_reg_0_15_0_5_n_1;
  wire mem_reg_0_15_0_5_n_2;
  wire mem_reg_0_15_0_5_n_3;
  wire mem_reg_0_15_0_5_n_4;
  wire mem_reg_0_15_0_5_n_5;
  wire mem_reg_0_15_12_17_n_0;
  wire mem_reg_0_15_12_17_n_1;
  wire mem_reg_0_15_12_17_n_2;
  wire mem_reg_0_15_12_17_n_3;
  wire mem_reg_0_15_6_11_n_0;
  wire mem_reg_0_15_6_11_n_1;
  wire mem_reg_0_15_6_11_n_2;
  wire mem_reg_0_15_6_11_n_3;
  wire mem_reg_0_15_6_11_n_4;
  wire mem_reg_0_15_6_11_n_5;
  wire my_empty0;
  wire \my_empty[1]_i_1__2_n_0 ;
  wire \my_empty[7]_i_1__2_n_0 ;
  wire \my_empty[7]_i_3__2_n_0 ;
  wire \my_empty[7]_i_4__2_n_0 ;
  wire \my_empty_reg[1]_0 ;
  wire \my_empty_reg[1]_1 ;
  wire \my_empty_reg[7]_0 ;
  wire \my_empty_reg_n_0_[7] ;
  wire my_full0;
  wire \my_full[4]_i_1__2_n_0 ;
  wire \my_full[4]_i_3__2_n_0 ;
  wire \my_full[4]_i_4__2_n_0 ;
  wire \my_full_reg[4]_0 ;
  wire \my_full_reg_n_0_[4] ;
  wire [3:0]nxt_rd_ptr;
  wire [3:0]nxt_wr_ptr;
  wire ofifo_rst;
  wire ofs_rdy_r_reg;
  wire ofs_rdy_r_reg_0;
  wire ofs_rdy_r_reg_1;
  wire ofs_rdy_r_reg_2;
  wire out_fifo;
  wire [7:0]out_fifo_0;
  wire out_fifo_1;
  wire [71:0]out_fifo_i_75__6;
  wire phy_data_wr_en;
  wire phy_mc_data_full;
  wire [63:0]\rd_ptr_reg[3]_0 ;
  wire \rd_ptr_reg_n_0_[0] ;
  wire \rd_ptr_reg_n_0_[1] ;
  wire \rd_ptr_reg_n_0_[2] ;
  wire \rd_ptr_reg_n_0_[3] ;
  wire [3:0]rd_ptr_timing;
  wire \rd_ptr_timing[3]_i_1__2_n_0 ;
  (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) wire wr_en;
  wire [3:0]wr_ptr;
  wire wr_ptr0;
  wire [3:0]wr_ptr_timing;
  wire [1:0]NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED;

  (* SOFT_HLUTNM = "soft_lutpair800" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \entry_cnt[0]_i_1__1 
       (.I0(\entry_cnt_reg_n_0_[0] ),
        .O(\entry_cnt[0]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair799" *) 
  LUT5 #(
    .INIT(32'hAA6A5595)) 
    \entry_cnt[1]_i_1__1 
       (.I0(\entry_cnt_reg_n_0_[0] ),
        .I1(\my_empty_reg[7]_0 ),
        .I2(phy_data_wr_en),
        .I3(\my_full_reg_n_0_[4] ),
        .I4(\entry_cnt_reg_n_0_[1] ),
        .O(\entry_cnt[1]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hFF7F0080AAEA5515)) 
    \entry_cnt[2]_i_1__1 
       (.I0(\entry_cnt_reg_n_0_[0] ),
        .I1(\my_empty_reg[7]_0 ),
        .I2(phy_data_wr_en),
        .I3(\my_full_reg_n_0_[4] ),
        .I4(Q[0]),
        .I5(\entry_cnt_reg_n_0_[1] ),
        .O(\entry_cnt[2]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair800" *) 
  LUT5 #(
    .INIT(32'h7F80FE01)) 
    \entry_cnt[3]_i_1__1 
       (.I0(entry_cnt10_out__0),
        .I1(\entry_cnt_reg_n_0_[0] ),
        .I2(\entry_cnt_reg_n_0_[1] ),
        .I3(Q[1]),
        .I4(Q[0]),
        .O(\entry_cnt[3]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h5003)) 
    \entry_cnt[4]_i_1__1 
       (.I0(\my_full_reg_n_0_[4] ),
        .I1(\my_empty_reg_n_0_[7] ),
        .I2(\my_empty_reg[7]_0 ),
        .I3(phy_data_wr_en),
        .O(\entry_cnt[4]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'h7FFF8000FFFE0001)) 
    \entry_cnt[4]_i_2__1 
       (.I0(\entry_cnt_reg_n_0_[1] ),
        .I1(\entry_cnt_reg_n_0_[0] ),
        .I2(entry_cnt10_out__0),
        .I3(Q[0]),
        .I4(Q[2]),
        .I5(Q[1]),
        .O(\entry_cnt[4]_i_2__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair799" *) 
  LUT3 #(
    .INIT(8'h08)) 
    \entry_cnt[4]_i_3__1 
       (.I0(\my_empty_reg[7]_0 ),
        .I1(phy_data_wr_en),
        .I2(\my_full_reg_n_0_[4] ),
        .O(entry_cnt10_out__0));
  FDRE \entry_cnt_reg[0] 
       (.C(\my_full_reg[4]_0 ),
        .CE(\entry_cnt[4]_i_1__1_n_0 ),
        .D(\entry_cnt[0]_i_1__1_n_0 ),
        .Q(\entry_cnt_reg_n_0_[0] ),
        .R(ofifo_rst));
  FDRE \entry_cnt_reg[1] 
       (.C(\my_full_reg[4]_0 ),
        .CE(\entry_cnt[4]_i_1__1_n_0 ),
        .D(\entry_cnt[1]_i_1__1_n_0 ),
        .Q(\entry_cnt_reg_n_0_[1] ),
        .R(ofifo_rst));
  FDRE \entry_cnt_reg[2] 
       (.C(\my_full_reg[4]_0 ),
        .CE(\entry_cnt[4]_i_1__1_n_0 ),
        .D(\entry_cnt[2]_i_1__1_n_0 ),
        .Q(Q[0]),
        .R(ofifo_rst));
  FDRE \entry_cnt_reg[3] 
       (.C(\my_full_reg[4]_0 ),
        .CE(\entry_cnt[4]_i_1__1_n_0 ),
        .D(\entry_cnt[3]_i_1__1_n_0 ),
        .Q(Q[1]),
        .R(ofifo_rst));
  FDRE \entry_cnt_reg[4] 
       (.C(\my_full_reg[4]_0 ),
        .CE(\entry_cnt[4]_i_1__1_n_0 ),
        .D(\entry_cnt[4]_i_2__1_n_0 ),
        .Q(Q[2]),
        .R(ofifo_rst));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "0" *) 
  (* ram_slice_end = "5" *) 
  RAM32M mem_reg_0_15_0_5
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA({1'b0,1'b0}),
        .DIB({1'b0,1'b0}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA({mem_reg_0_15_0_5_n_0,mem_reg_0_15_0_5_n_1}),
        .DOB({mem_reg_0_15_0_5_n_2,mem_reg_0_15_0_5_n_3}),
        .DOC({mem_reg_0_15_0_5_n_4,mem_reg_0_15_0_5_n_5}),
        .DOD(NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED[1:0]),
        .WCLK(\my_full_reg[4]_0 ),
        .WE(wr_en));
  LUT4 #(
    .INIT(16'h2700)) 
    mem_reg_0_15_0_5_i_1__1
       (.I0(\my_empty_reg[7]_0 ),
        .I1(\my_full_reg_n_0_[4] ),
        .I2(\my_empty_reg[1]_1 ),
        .I3(phy_data_wr_en),
        .O(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "12" *) 
  (* ram_slice_end = "17" *) 
  RAM32M mem_reg_0_15_12_17
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__6[5:4]),
        .DIB(out_fifo_i_75__6[7:6]),
        .DIC(out_fifo_i_75__6[9:8]),
        .DID({1'b0,1'b0}),
        .DOA({mem_reg_0_15_12_17_n_0,mem_reg_0_15_12_17_n_1}),
        .DOB({mem_reg_0_15_12_17_n_2,mem_reg_0_15_12_17_n_3}),
        .DOC(\rd_ptr_reg[3]_0 [1:0]),
        .DOD(NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED[1:0]),
        .WCLK(\my_full_reg[4]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "18" *) 
  (* ram_slice_end = "23" *) 
  RAM32M mem_reg_0_15_18_23
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__6[11:10]),
        .DIB(out_fifo_i_75__6[13:12]),
        .DIC(out_fifo_i_75__6[15:14]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [3:2]),
        .DOB(\rd_ptr_reg[3]_0 [5:4]),
        .DOC(\rd_ptr_reg[3]_0 [7:6]),
        .DOD(NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED[1:0]),
        .WCLK(\my_full_reg[4]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "24" *) 
  (* ram_slice_end = "29" *) 
  RAM32M mem_reg_0_15_24_29
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__6[17:16]),
        .DIB(out_fifo_i_75__6[19:18]),
        .DIC(out_fifo_i_75__6[21:20]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [9:8]),
        .DOB(\rd_ptr_reg[3]_0 [11:10]),
        .DOC(\rd_ptr_reg[3]_0 [13:12]),
        .DOD(NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED[1:0]),
        .WCLK(\my_full_reg[4]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "30" *) 
  (* ram_slice_end = "35" *) 
  RAM32M mem_reg_0_15_30_35
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__6[23:22]),
        .DIB(out_fifo_i_75__6[25:24]),
        .DIC(out_fifo_i_75__6[27:26]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [15:14]),
        .DOB(\rd_ptr_reg[3]_0 [17:16]),
        .DOC(\rd_ptr_reg[3]_0 [19:18]),
        .DOD(NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED[1:0]),
        .WCLK(\my_full_reg[4]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "36" *) 
  (* ram_slice_end = "41" *) 
  RAM32M mem_reg_0_15_36_41
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__6[29:28]),
        .DIB(out_fifo_i_75__6[31:30]),
        .DIC(out_fifo_i_75__6[33:32]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [21:20]),
        .DOB(\rd_ptr_reg[3]_0 [23:22]),
        .DOC(\rd_ptr_reg[3]_0 [25:24]),
        .DOD(NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED[1:0]),
        .WCLK(\my_full_reg[4]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "42" *) 
  (* ram_slice_end = "47" *) 
  RAM32M mem_reg_0_15_42_47
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__6[35:34]),
        .DIB(out_fifo_i_75__6[37:36]),
        .DIC(out_fifo_i_75__6[39:38]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [27:26]),
        .DOB(\rd_ptr_reg[3]_0 [29:28]),
        .DOC(\rd_ptr_reg[3]_0 [31:30]),
        .DOD(NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED[1:0]),
        .WCLK(\my_full_reg[4]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "48" *) 
  (* ram_slice_end = "53" *) 
  RAM32M mem_reg_0_15_48_53
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__6[41:40]),
        .DIB(out_fifo_i_75__6[43:42]),
        .DIC(out_fifo_i_75__6[45:44]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [33:32]),
        .DOB(\rd_ptr_reg[3]_0 [35:34]),
        .DOC(\rd_ptr_reg[3]_0 [37:36]),
        .DOD(NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED[1:0]),
        .WCLK(\my_full_reg[4]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "54" *) 
  (* ram_slice_end = "59" *) 
  RAM32M mem_reg_0_15_54_59
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__6[47:46]),
        .DIB(out_fifo_i_75__6[49:48]),
        .DIC(out_fifo_i_75__6[51:50]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [39:38]),
        .DOB(\rd_ptr_reg[3]_0 [41:40]),
        .DOC(\rd_ptr_reg[3]_0 [43:42]),
        .DOD(NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED[1:0]),
        .WCLK(\my_full_reg[4]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "60" *) 
  (* ram_slice_end = "65" *) 
  RAM32M mem_reg_0_15_60_65
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__6[53:52]),
        .DIB(out_fifo_i_75__6[55:54]),
        .DIC(out_fifo_i_75__6[57:56]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [45:44]),
        .DOB(\rd_ptr_reg[3]_0 [47:46]),
        .DOC(\rd_ptr_reg[3]_0 [49:48]),
        .DOD(NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED[1:0]),
        .WCLK(\my_full_reg[4]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "66" *) 
  (* ram_slice_end = "71" *) 
  RAM32M mem_reg_0_15_66_71
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__6[59:58]),
        .DIB(out_fifo_i_75__6[61:60]),
        .DIC(out_fifo_i_75__6[63:62]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [51:50]),
        .DOB(\rd_ptr_reg[3]_0 [53:52]),
        .DOC(\rd_ptr_reg[3]_0 [55:54]),
        .DOD(NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED[1:0]),
        .WCLK(\my_full_reg[4]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "6" *) 
  (* ram_slice_end = "11" *) 
  RAM32M mem_reg_0_15_6_11
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA({1'b0,1'b0}),
        .DIB(out_fifo_i_75__6[1:0]),
        .DIC(out_fifo_i_75__6[3:2]),
        .DID({1'b0,1'b0}),
        .DOA({mem_reg_0_15_6_11_n_0,mem_reg_0_15_6_11_n_1}),
        .DOB({mem_reg_0_15_6_11_n_2,mem_reg_0_15_6_11_n_3}),
        .DOC({mem_reg_0_15_6_11_n_4,mem_reg_0_15_6_11_n_5}),
        .DOD(NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED[1:0]),
        .WCLK(\my_full_reg[4]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "72" *) 
  (* ram_slice_end = "77" *) 
  RAM32M mem_reg_0_15_72_77
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__6[65:64]),
        .DIB(out_fifo_i_75__6[67:66]),
        .DIC(out_fifo_i_75__6[69:68]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [57:56]),
        .DOB(\rd_ptr_reg[3]_0 [59:58]),
        .DOC(\rd_ptr_reg[3]_0 [61:60]),
        .DOD(NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED[1:0]),
        .WCLK(\my_full_reg[4]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "78" *) 
  (* ram_slice_end = "79" *) 
  RAM32M mem_reg_0_15_78_79
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__6[71:70]),
        .DIB({1'b0,1'b0}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [63:62]),
        .DOB(NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED[1:0]),
        .DOC(NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED[1:0]),
        .DOD(NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED[1:0]),
        .WCLK(\my_full_reg[4]_0 ),
        .WE(wr_en));
  LUT6 #(
    .INIT(64'hFFFFFFFFF701F700)) 
    \my_empty[1]_i_1__2 
       (.I0(\my_empty_reg[7]_0 ),
        .I1(phy_data_wr_en),
        .I2(\my_full_reg_n_0_[4] ),
        .I3(\my_empty_reg[1]_1 ),
        .I4(my_empty0),
        .I5(ofifo_rst),
        .O(\my_empty[1]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFF701F700)) 
    \my_empty[7]_i_1__2 
       (.I0(\my_empty_reg[7]_0 ),
        .I1(phy_data_wr_en),
        .I2(\my_full_reg_n_0_[4] ),
        .I3(\my_empty_reg_n_0_[7] ),
        .I4(my_empty0),
        .I5(ofifo_rst),
        .O(\my_empty[7]_i_1__2_n_0 ));
  LUT5 #(
    .INIT(32'h4A400D08)) 
    \my_empty[7]_i_2__2 
       (.I0(wr_ptr_timing[2]),
        .I1(\my_empty[7]_i_3__2_n_0 ),
        .I2(wr_ptr_timing[3]),
        .I3(\my_empty[7]_i_4__2_n_0 ),
        .I4(\rd_ptr_reg_n_0_[2] ),
        .O(my_empty0));
  (* SOFT_HLUTNM = "soft_lutpair798" *) 
  LUT5 #(
    .INIT(32'h00000040)) 
    \my_empty[7]_i_3__2 
       (.I0(wr_ptr_timing[1]),
        .I1(\rd_ptr_reg_n_0_[0] ),
        .I2(\rd_ptr_reg_n_0_[1] ),
        .I3(\rd_ptr_reg_n_0_[3] ),
        .I4(wr_ptr_timing[0]),
        .O(\my_empty[7]_i_3__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair798" *) 
  LUT5 #(
    .INIT(32'h84210842)) 
    \my_empty[7]_i_4__2 
       (.I0(wr_ptr_timing[0]),
        .I1(wr_ptr_timing[1]),
        .I2(\rd_ptr_reg_n_0_[0] ),
        .I3(\rd_ptr_reg_n_0_[1] ),
        .I4(\rd_ptr_reg_n_0_[3] ),
        .O(\my_empty[7]_i_4__2_n_0 ));
  (* syn_maxfan = "3" *) 
  FDRE \my_empty_reg[1] 
       (.C(\my_full_reg[4]_0 ),
        .CE(1'b1),
        .D(\my_empty[1]_i_1__2_n_0 ),
        .Q(\my_empty_reg[1]_1 ),
        .R(1'b0));
  (* syn_maxfan = "3" *) 
  FDRE \my_empty_reg[7] 
       (.C(\my_full_reg[4]_0 ),
        .CE(1'b1),
        .D(\my_empty[7]_i_1__2_n_0 ),
        .Q(\my_empty_reg_n_0_[7] ),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h00000000FFFC0080)) 
    \my_full[4]_i_1__2 
       (.I0(my_full0),
        .I1(phy_data_wr_en),
        .I2(\my_empty_reg[7]_0 ),
        .I3(\my_empty_reg_n_0_[7] ),
        .I4(\my_full_reg_n_0_[4] ),
        .I5(ofifo_rst),
        .O(\my_full[4]_i_1__2_n_0 ));
  LUT5 #(
    .INIT(32'h4A400D08)) 
    \my_full[4]_i_2__2 
       (.I0(rd_ptr_timing[2]),
        .I1(\my_full[4]_i_3__2_n_0 ),
        .I2(rd_ptr_timing[3]),
        .I3(\my_full[4]_i_4__2_n_0 ),
        .I4(wr_ptr[2]),
        .O(my_full0));
  (* SOFT_HLUTNM = "soft_lutpair797" *) 
  LUT5 #(
    .INIT(32'h00000040)) 
    \my_full[4]_i_3__2 
       (.I0(rd_ptr_timing[1]),
        .I1(wr_ptr[0]),
        .I2(wr_ptr[1]),
        .I3(wr_ptr[3]),
        .I4(rd_ptr_timing[0]),
        .O(\my_full[4]_i_3__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair797" *) 
  LUT5 #(
    .INIT(32'h84210842)) 
    \my_full[4]_i_4__2 
       (.I0(rd_ptr_timing[0]),
        .I1(rd_ptr_timing[1]),
        .I2(wr_ptr[0]),
        .I3(wr_ptr[1]),
        .I4(wr_ptr[3]),
        .O(\my_full[4]_i_4__2_n_0 ));
  (* syn_maxfan = "3" *) 
  FDRE \my_full_reg[4] 
       (.C(\my_full_reg[4]_0 ),
        .CE(1'b1),
        .D(\my_full[4]_i_1__2_n_0 ),
        .Q(\my_full_reg_n_0_[4] ),
        .R(1'b0));
  LUT4 #(
    .INIT(16'hFFFE)) 
    ofs_rdy_r_i_2
       (.I0(ofs_rdy_r_reg),
        .I1(ofs_rdy_r_reg_0),
        .I2(ofs_rdy_r_reg_1),
        .I3(ofs_rdy_r_reg_2),
        .O(phy_mc_data_full));
  (* SOFT_HLUTNM = "soft_lutpair808" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_10__8
       (.I0(out_fifo_1),
        .I1(out_fifo_0[7]),
        .I2(mem_reg_0_15_12_17_n_2),
        .I3(\my_empty_reg[1]_1 ),
        .O(D1[7]));
  (* SOFT_HLUTNM = "soft_lutpair805" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_11__8
       (.I0(out_fifo_1),
        .I1(out_fifo_0[6]),
        .I2(mem_reg_0_15_12_17_n_3),
        .I3(\my_empty_reg[1]_1 ),
        .O(D1[6]));
  (* SOFT_HLUTNM = "soft_lutpair806" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_12__8
       (.I0(out_fifo_1),
        .I1(out_fifo_0[5]),
        .I2(mem_reg_0_15_12_17_n_0),
        .I3(\my_empty_reg[1]_1 ),
        .O(D1[5]));
  (* SOFT_HLUTNM = "soft_lutpair804" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_13__8
       (.I0(out_fifo_1),
        .I1(out_fifo_0[4]),
        .I2(mem_reg_0_15_12_17_n_1),
        .I3(\my_empty_reg[1]_1 ),
        .O(D1[4]));
  (* SOFT_HLUTNM = "soft_lutpair803" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_14__8
       (.I0(out_fifo_1),
        .I1(out_fifo_0[3]),
        .I2(mem_reg_0_15_6_11_n_4),
        .I3(\my_empty_reg[1]_1 ),
        .O(D1[3]));
  (* SOFT_HLUTNM = "soft_lutpair802" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_15__8
       (.I0(out_fifo_1),
        .I1(out_fifo_0[2]),
        .I2(mem_reg_0_15_6_11_n_5),
        .I3(\my_empty_reg[1]_1 ),
        .O(D1[2]));
  (* SOFT_HLUTNM = "soft_lutpair801" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_16__8
       (.I0(out_fifo),
        .I1(out_fifo_0[1]),
        .I2(mem_reg_0_15_6_11_n_2),
        .I3(\my_empty_reg[1]_1 ),
        .O(D1[1]));
  (* SOFT_HLUTNM = "soft_lutpair807" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_17__8
       (.I0(out_fifo),
        .I1(out_fifo_0[0]),
        .I2(mem_reg_0_15_6_11_n_3),
        .I3(\my_empty_reg[1]_1 ),
        .O(D1[0]));
  LUT3 #(
    .INIT(8'h0D)) 
    out_fifo_i_1__2
       (.I0(\my_empty_reg[1]_1 ),
        .I1(phy_data_wr_en),
        .I2(\my_empty_reg[7]_0 ),
        .O(\my_empty_reg[1]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair806" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_2__1
       (.I0(mem_reg_0_15_6_11_n_0),
        .I1(\my_empty_reg[1]_1 ),
        .O(D0[7]));
  (* SOFT_HLUTNM = "soft_lutpair802" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_3__1
       (.I0(mem_reg_0_15_6_11_n_1),
        .I1(\my_empty_reg[1]_1 ),
        .O(D0[6]));
  (* SOFT_HLUTNM = "soft_lutpair807" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_4__1
       (.I0(mem_reg_0_15_0_5_n_4),
        .I1(\my_empty_reg[1]_1 ),
        .O(D0[5]));
  (* SOFT_HLUTNM = "soft_lutpair804" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_5__1
       (.I0(mem_reg_0_15_0_5_n_5),
        .I1(\my_empty_reg[1]_1 ),
        .O(D0[4]));
  (* SOFT_HLUTNM = "soft_lutpair805" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_6__1
       (.I0(mem_reg_0_15_0_5_n_2),
        .I1(\my_empty_reg[1]_1 ),
        .O(D0[3]));
  (* SOFT_HLUTNM = "soft_lutpair801" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_7__1
       (.I0(mem_reg_0_15_0_5_n_3),
        .I1(\my_empty_reg[1]_1 ),
        .O(D0[2]));
  (* SOFT_HLUTNM = "soft_lutpair808" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_8__1
       (.I0(mem_reg_0_15_0_5_n_0),
        .I1(\my_empty_reg[1]_1 ),
        .O(D0[1]));
  (* SOFT_HLUTNM = "soft_lutpair803" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_9__1
       (.I0(mem_reg_0_15_0_5_n_1),
        .I1(\my_empty_reg[1]_1 ),
        .O(D0[0]));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[0] 
       (.C(\my_full_reg[4]_0 ),
        .CE(\rd_ptr_timing[3]_i_1__2_n_0 ),
        .D(nxt_rd_ptr[0]),
        .Q(\rd_ptr_reg_n_0_[0] ),
        .R(ofifo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[1] 
       (.C(\my_full_reg[4]_0 ),
        .CE(\rd_ptr_timing[3]_i_1__2_n_0 ),
        .D(nxt_rd_ptr[1]),
        .Q(\rd_ptr_reg_n_0_[1] ),
        .R(ofifo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[2] 
       (.C(\my_full_reg[4]_0 ),
        .CE(\rd_ptr_timing[3]_i_1__2_n_0 ),
        .D(nxt_rd_ptr[2]),
        .Q(\rd_ptr_reg_n_0_[2] ),
        .R(ofifo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[3] 
       (.C(\my_full_reg[4]_0 ),
        .CE(\rd_ptr_timing[3]_i_1__2_n_0 ),
        .D(nxt_rd_ptr[3]),
        .Q(\rd_ptr_reg_n_0_[3] ),
        .R(ofifo_rst));
  (* SOFT_HLUTNM = "soft_lutpair812" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rd_ptr_timing[0]_i_1__5 
       (.I0(\rd_ptr_reg_n_0_[3] ),
        .I1(\rd_ptr_reg_n_0_[0] ),
        .O(nxt_rd_ptr[0]));
  (* SOFT_HLUTNM = "soft_lutpair812" *) 
  LUT3 #(
    .INIT(8'hB4)) 
    \rd_ptr_timing[1]_i_1__5 
       (.I0(\rd_ptr_reg_n_0_[3] ),
        .I1(\rd_ptr_reg_n_0_[0] ),
        .I2(\rd_ptr_reg_n_0_[1] ),
        .O(nxt_rd_ptr[1]));
  (* SOFT_HLUTNM = "soft_lutpair810" *) 
  LUT4 #(
    .INIT(16'hAA6A)) 
    \rd_ptr_timing[2]_i_1__2 
       (.I0(\rd_ptr_reg_n_0_[2] ),
        .I1(\rd_ptr_reg_n_0_[0] ),
        .I2(\rd_ptr_reg_n_0_[1] ),
        .I3(\rd_ptr_reg_n_0_[3] ),
        .O(nxt_rd_ptr[2]));
  LUT2 #(
    .INIT(4'h1)) 
    \rd_ptr_timing[3]_i_1__2 
       (.I0(\my_empty_reg[7]_0 ),
        .I1(\my_empty_reg_n_0_[7] ),
        .O(\rd_ptr_timing[3]_i_1__2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair810" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \rd_ptr_timing[3]_i_2__2 
       (.I0(\rd_ptr_reg_n_0_[3] ),
        .I1(\rd_ptr_reg_n_0_[1] ),
        .I2(\rd_ptr_reg_n_0_[0] ),
        .I3(\rd_ptr_reg_n_0_[2] ),
        .O(nxt_rd_ptr[3]));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[0] 
       (.C(\my_full_reg[4]_0 ),
        .CE(\rd_ptr_timing[3]_i_1__2_n_0 ),
        .D(nxt_rd_ptr[0]),
        .Q(rd_ptr_timing[0]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[1] 
       (.C(\my_full_reg[4]_0 ),
        .CE(\rd_ptr_timing[3]_i_1__2_n_0 ),
        .D(nxt_rd_ptr[1]),
        .Q(rd_ptr_timing[1]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[2] 
       (.C(\my_full_reg[4]_0 ),
        .CE(\rd_ptr_timing[3]_i_1__2_n_0 ),
        .D(nxt_rd_ptr[2]),
        .Q(rd_ptr_timing[2]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[3] 
       (.C(\my_full_reg[4]_0 ),
        .CE(\rd_ptr_timing[3]_i_1__2_n_0 ),
        .D(nxt_rd_ptr[3]),
        .Q(rd_ptr_timing[3]),
        .R(ofifo_rst));
  (* SOFT_HLUTNM = "soft_lutpair811" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \wr_ptr[0]_i_1__5 
       (.I0(wr_ptr[3]),
        .I1(wr_ptr[0]),
        .O(nxt_wr_ptr[0]));
  (* SOFT_HLUTNM = "soft_lutpair811" *) 
  LUT3 #(
    .INIT(8'hB4)) 
    \wr_ptr[1]_i_1__5 
       (.I0(wr_ptr[3]),
        .I1(wr_ptr[0]),
        .I2(wr_ptr[1]),
        .O(nxt_wr_ptr[1]));
  (* SOFT_HLUTNM = "soft_lutpair809" *) 
  LUT4 #(
    .INIT(16'hAA6A)) 
    \wr_ptr[2]_i_1__2 
       (.I0(wr_ptr[2]),
        .I1(wr_ptr[0]),
        .I2(wr_ptr[1]),
        .I3(wr_ptr[3]),
        .O(nxt_wr_ptr[2]));
  LUT4 #(
    .INIT(16'h082A)) 
    \wr_ptr[3]_i_1__2 
       (.I0(phy_data_wr_en),
        .I1(\my_empty_reg[7]_0 ),
        .I2(\my_full_reg_n_0_[4] ),
        .I3(\my_empty_reg_n_0_[7] ),
        .O(wr_ptr0));
  (* SOFT_HLUTNM = "soft_lutpair809" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \wr_ptr[3]_i_2__1 
       (.I0(wr_ptr[3]),
        .I1(wr_ptr[1]),
        .I2(wr_ptr[0]),
        .I3(wr_ptr[2]),
        .O(nxt_wr_ptr[3]));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[0] 
       (.C(\my_full_reg[4]_0 ),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[0]),
        .Q(wr_ptr[0]),
        .R(ofifo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[1] 
       (.C(\my_full_reg[4]_0 ),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[1]),
        .Q(wr_ptr[1]),
        .R(ofifo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[2] 
       (.C(\my_full_reg[4]_0 ),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[2]),
        .Q(wr_ptr[2]),
        .R(ofifo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[3] 
       (.C(\my_full_reg[4]_0 ),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[3]),
        .Q(wr_ptr[3]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[0] 
       (.C(\my_full_reg[4]_0 ),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[0]),
        .Q(wr_ptr_timing[0]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[1] 
       (.C(\my_full_reg[4]_0 ),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[1]),
        .Q(wr_ptr_timing[1]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[2] 
       (.C(\my_full_reg[4]_0 ),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[2]),
        .Q(wr_ptr_timing[2]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[3] 
       (.C(\my_full_reg[4]_0 ),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[3]),
        .Q(wr_ptr_timing[3]),
        .R(ofifo_rst));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_of_pre_fifo" *) 
module mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_37
   (\my_empty_reg[1]_0 ,
    \my_empty_reg[1]_1 ,
    D0,
    D1,
    \rd_ptr_reg[3]_0 ,
    Q,
    ofifo_rst,
    \entry_cnt_reg[4]_0 ,
    \my_empty_reg[7]_0 ,
    phy_data_wr_en,
    out_fifo,
    out_fifo_0,
    out_fifo_1,
    out_fifo_i_75__5);
  output \my_empty_reg[1]_0 ;
  output \my_empty_reg[1]_1 ;
  output [7:0]D0;
  output [7:0]D1;
  output [63:0]\rd_ptr_reg[3]_0 ;
  output [2:0]Q;
  input ofifo_rst;
  input \entry_cnt_reg[4]_0 ;
  input \my_empty_reg[7]_0 ;
  input phy_data_wr_en;
  input out_fifo;
  input [7:0]out_fifo_0;
  input out_fifo_1;
  input [71:0]out_fifo_i_75__5;

  wire [7:0]D0;
  wire [7:0]D1;
  wire [2:0]Q;
  wire entry_cnt10_out__0;
  wire \entry_cnt[0]_i_1__0_n_0 ;
  wire \entry_cnt[1]_i_1__0_n_0 ;
  wire \entry_cnt[2]_i_1__0_n_0 ;
  wire \entry_cnt[3]_i_1__0_n_0 ;
  wire \entry_cnt[4]_i_1__0_n_0 ;
  wire \entry_cnt[4]_i_2__0_n_0 ;
  wire \entry_cnt_reg[4]_0 ;
  wire \entry_cnt_reg_n_0_[0] ;
  wire \entry_cnt_reg_n_0_[1] ;
  wire mem_reg_0_15_0_5_n_0;
  wire mem_reg_0_15_0_5_n_1;
  wire mem_reg_0_15_0_5_n_2;
  wire mem_reg_0_15_0_5_n_3;
  wire mem_reg_0_15_0_5_n_4;
  wire mem_reg_0_15_0_5_n_5;
  wire mem_reg_0_15_12_17_n_0;
  wire mem_reg_0_15_12_17_n_1;
  wire mem_reg_0_15_12_17_n_2;
  wire mem_reg_0_15_12_17_n_3;
  wire mem_reg_0_15_6_11_n_0;
  wire mem_reg_0_15_6_11_n_1;
  wire mem_reg_0_15_6_11_n_2;
  wire mem_reg_0_15_6_11_n_3;
  wire mem_reg_0_15_6_11_n_4;
  wire mem_reg_0_15_6_11_n_5;
  wire my_empty0;
  wire \my_empty[1]_i_1__1_n_0 ;
  wire \my_empty[7]_i_1__1_n_0 ;
  wire \my_empty[7]_i_3__1_n_0 ;
  wire \my_empty[7]_i_4__1_n_0 ;
  wire \my_empty_reg[1]_0 ;
  wire \my_empty_reg[1]_1 ;
  wire \my_empty_reg[7]_0 ;
  wire \my_empty_reg_n_0_[7] ;
  wire my_full0;
  wire \my_full[4]_i_1__1_n_0 ;
  wire \my_full[4]_i_3__1_n_0 ;
  wire \my_full[4]_i_4__1_n_0 ;
  wire \my_full_reg_n_0_[4] ;
  wire [3:0]nxt_rd_ptr;
  wire [3:0]nxt_wr_ptr;
  wire ofifo_rst;
  wire out_fifo;
  wire [7:0]out_fifo_0;
  wire out_fifo_1;
  wire [71:0]out_fifo_i_75__5;
  wire phy_data_wr_en;
  wire [63:0]\rd_ptr_reg[3]_0 ;
  wire \rd_ptr_reg_n_0_[0] ;
  wire \rd_ptr_reg_n_0_[1] ;
  wire \rd_ptr_reg_n_0_[2] ;
  wire \rd_ptr_reg_n_0_[3] ;
  wire [3:0]rd_ptr_timing;
  wire \rd_ptr_timing[3]_i_1__1_n_0 ;
  (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) wire wr_en;
  wire [3:0]wr_ptr;
  wire wr_ptr0;
  wire [3:0]wr_ptr_timing;
  wire [1:0]NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED;

  (* SOFT_HLUTNM = "soft_lutpair747" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \entry_cnt[0]_i_1__0 
       (.I0(\entry_cnt_reg_n_0_[0] ),
        .O(\entry_cnt[0]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair746" *) 
  LUT5 #(
    .INIT(32'hAA6A5595)) 
    \entry_cnt[1]_i_1__0 
       (.I0(\entry_cnt_reg_n_0_[0] ),
        .I1(\my_empty_reg[7]_0 ),
        .I2(phy_data_wr_en),
        .I3(\my_full_reg_n_0_[4] ),
        .I4(\entry_cnt_reg_n_0_[1] ),
        .O(\entry_cnt[1]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hFF7F0080AAEA5515)) 
    \entry_cnt[2]_i_1__0 
       (.I0(\entry_cnt_reg_n_0_[0] ),
        .I1(\my_empty_reg[7]_0 ),
        .I2(phy_data_wr_en),
        .I3(\my_full_reg_n_0_[4] ),
        .I4(Q[0]),
        .I5(\entry_cnt_reg_n_0_[1] ),
        .O(\entry_cnt[2]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair747" *) 
  LUT5 #(
    .INIT(32'h7F80FE01)) 
    \entry_cnt[3]_i_1__0 
       (.I0(entry_cnt10_out__0),
        .I1(\entry_cnt_reg_n_0_[0] ),
        .I2(\entry_cnt_reg_n_0_[1] ),
        .I3(Q[1]),
        .I4(Q[0]),
        .O(\entry_cnt[3]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h5003)) 
    \entry_cnt[4]_i_1__0 
       (.I0(\my_full_reg_n_0_[4] ),
        .I1(\my_empty_reg_n_0_[7] ),
        .I2(\my_empty_reg[7]_0 ),
        .I3(phy_data_wr_en),
        .O(\entry_cnt[4]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h7FFF8000FFFE0001)) 
    \entry_cnt[4]_i_2__0 
       (.I0(\entry_cnt_reg_n_0_[1] ),
        .I1(\entry_cnt_reg_n_0_[0] ),
        .I2(entry_cnt10_out__0),
        .I3(Q[0]),
        .I4(Q[2]),
        .I5(Q[1]),
        .O(\entry_cnt[4]_i_2__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair746" *) 
  LUT3 #(
    .INIT(8'h08)) 
    \entry_cnt[4]_i_3__0 
       (.I0(\my_empty_reg[7]_0 ),
        .I1(phy_data_wr_en),
        .I2(\my_full_reg_n_0_[4] ),
        .O(entry_cnt10_out__0));
  FDRE \entry_cnt_reg[0] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(\entry_cnt[4]_i_1__0_n_0 ),
        .D(\entry_cnt[0]_i_1__0_n_0 ),
        .Q(\entry_cnt_reg_n_0_[0] ),
        .R(ofifo_rst));
  FDRE \entry_cnt_reg[1] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(\entry_cnt[4]_i_1__0_n_0 ),
        .D(\entry_cnt[1]_i_1__0_n_0 ),
        .Q(\entry_cnt_reg_n_0_[1] ),
        .R(ofifo_rst));
  FDRE \entry_cnt_reg[2] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(\entry_cnt[4]_i_1__0_n_0 ),
        .D(\entry_cnt[2]_i_1__0_n_0 ),
        .Q(Q[0]),
        .R(ofifo_rst));
  FDRE \entry_cnt_reg[3] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(\entry_cnt[4]_i_1__0_n_0 ),
        .D(\entry_cnt[3]_i_1__0_n_0 ),
        .Q(Q[1]),
        .R(ofifo_rst));
  FDRE \entry_cnt_reg[4] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(\entry_cnt[4]_i_1__0_n_0 ),
        .D(\entry_cnt[4]_i_2__0_n_0 ),
        .Q(Q[2]),
        .R(ofifo_rst));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "0" *) 
  (* ram_slice_end = "5" *) 
  RAM32M mem_reg_0_15_0_5
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA({1'b0,1'b0}),
        .DIB({1'b0,1'b0}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA({mem_reg_0_15_0_5_n_0,mem_reg_0_15_0_5_n_1}),
        .DOB({mem_reg_0_15_0_5_n_2,mem_reg_0_15_0_5_n_3}),
        .DOC({mem_reg_0_15_0_5_n_4,mem_reg_0_15_0_5_n_5}),
        .DOD(NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED[1:0]),
        .WCLK(\entry_cnt_reg[4]_0 ),
        .WE(wr_en));
  LUT4 #(
    .INIT(16'h2700)) 
    mem_reg_0_15_0_5_i_1__0
       (.I0(\my_empty_reg[7]_0 ),
        .I1(\my_full_reg_n_0_[4] ),
        .I2(\my_empty_reg[1]_1 ),
        .I3(phy_data_wr_en),
        .O(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "12" *) 
  (* ram_slice_end = "17" *) 
  RAM32M mem_reg_0_15_12_17
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__5[5:4]),
        .DIB(out_fifo_i_75__5[7:6]),
        .DIC(out_fifo_i_75__5[9:8]),
        .DID({1'b0,1'b0}),
        .DOA({mem_reg_0_15_12_17_n_0,mem_reg_0_15_12_17_n_1}),
        .DOB({mem_reg_0_15_12_17_n_2,mem_reg_0_15_12_17_n_3}),
        .DOC(\rd_ptr_reg[3]_0 [1:0]),
        .DOD(NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED[1:0]),
        .WCLK(\entry_cnt_reg[4]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "18" *) 
  (* ram_slice_end = "23" *) 
  RAM32M mem_reg_0_15_18_23
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__5[11:10]),
        .DIB(out_fifo_i_75__5[13:12]),
        .DIC(out_fifo_i_75__5[15:14]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [3:2]),
        .DOB(\rd_ptr_reg[3]_0 [5:4]),
        .DOC(\rd_ptr_reg[3]_0 [7:6]),
        .DOD(NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED[1:0]),
        .WCLK(\entry_cnt_reg[4]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "24" *) 
  (* ram_slice_end = "29" *) 
  RAM32M mem_reg_0_15_24_29
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__5[17:16]),
        .DIB(out_fifo_i_75__5[19:18]),
        .DIC(out_fifo_i_75__5[21:20]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [9:8]),
        .DOB(\rd_ptr_reg[3]_0 [11:10]),
        .DOC(\rd_ptr_reg[3]_0 [13:12]),
        .DOD(NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED[1:0]),
        .WCLK(\entry_cnt_reg[4]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "30" *) 
  (* ram_slice_end = "35" *) 
  RAM32M mem_reg_0_15_30_35
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__5[23:22]),
        .DIB(out_fifo_i_75__5[25:24]),
        .DIC(out_fifo_i_75__5[27:26]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [15:14]),
        .DOB(\rd_ptr_reg[3]_0 [17:16]),
        .DOC(\rd_ptr_reg[3]_0 [19:18]),
        .DOD(NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED[1:0]),
        .WCLK(\entry_cnt_reg[4]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "36" *) 
  (* ram_slice_end = "41" *) 
  RAM32M mem_reg_0_15_36_41
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__5[29:28]),
        .DIB(out_fifo_i_75__5[31:30]),
        .DIC(out_fifo_i_75__5[33:32]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [21:20]),
        .DOB(\rd_ptr_reg[3]_0 [23:22]),
        .DOC(\rd_ptr_reg[3]_0 [25:24]),
        .DOD(NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED[1:0]),
        .WCLK(\entry_cnt_reg[4]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "42" *) 
  (* ram_slice_end = "47" *) 
  RAM32M mem_reg_0_15_42_47
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__5[35:34]),
        .DIB(out_fifo_i_75__5[37:36]),
        .DIC(out_fifo_i_75__5[39:38]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [27:26]),
        .DOB(\rd_ptr_reg[3]_0 [29:28]),
        .DOC(\rd_ptr_reg[3]_0 [31:30]),
        .DOD(NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED[1:0]),
        .WCLK(\entry_cnt_reg[4]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "48" *) 
  (* ram_slice_end = "53" *) 
  RAM32M mem_reg_0_15_48_53
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__5[41:40]),
        .DIB(out_fifo_i_75__5[43:42]),
        .DIC(out_fifo_i_75__5[45:44]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [33:32]),
        .DOB(\rd_ptr_reg[3]_0 [35:34]),
        .DOC(\rd_ptr_reg[3]_0 [37:36]),
        .DOD(NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED[1:0]),
        .WCLK(\entry_cnt_reg[4]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "54" *) 
  (* ram_slice_end = "59" *) 
  RAM32M mem_reg_0_15_54_59
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__5[47:46]),
        .DIB(out_fifo_i_75__5[49:48]),
        .DIC(out_fifo_i_75__5[51:50]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [39:38]),
        .DOB(\rd_ptr_reg[3]_0 [41:40]),
        .DOC(\rd_ptr_reg[3]_0 [43:42]),
        .DOD(NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED[1:0]),
        .WCLK(\entry_cnt_reg[4]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "60" *) 
  (* ram_slice_end = "65" *) 
  RAM32M mem_reg_0_15_60_65
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__5[53:52]),
        .DIB(out_fifo_i_75__5[55:54]),
        .DIC(out_fifo_i_75__5[57:56]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [45:44]),
        .DOB(\rd_ptr_reg[3]_0 [47:46]),
        .DOC(\rd_ptr_reg[3]_0 [49:48]),
        .DOD(NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED[1:0]),
        .WCLK(\entry_cnt_reg[4]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "66" *) 
  (* ram_slice_end = "71" *) 
  RAM32M mem_reg_0_15_66_71
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__5[59:58]),
        .DIB(out_fifo_i_75__5[61:60]),
        .DIC(out_fifo_i_75__5[63:62]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [51:50]),
        .DOB(\rd_ptr_reg[3]_0 [53:52]),
        .DOC(\rd_ptr_reg[3]_0 [55:54]),
        .DOD(NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED[1:0]),
        .WCLK(\entry_cnt_reg[4]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "6" *) 
  (* ram_slice_end = "11" *) 
  RAM32M mem_reg_0_15_6_11
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA({1'b0,1'b0}),
        .DIB(out_fifo_i_75__5[1:0]),
        .DIC(out_fifo_i_75__5[3:2]),
        .DID({1'b0,1'b0}),
        .DOA({mem_reg_0_15_6_11_n_0,mem_reg_0_15_6_11_n_1}),
        .DOB({mem_reg_0_15_6_11_n_2,mem_reg_0_15_6_11_n_3}),
        .DOC({mem_reg_0_15_6_11_n_4,mem_reg_0_15_6_11_n_5}),
        .DOD(NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED[1:0]),
        .WCLK(\entry_cnt_reg[4]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "72" *) 
  (* ram_slice_end = "77" *) 
  RAM32M mem_reg_0_15_72_77
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__5[65:64]),
        .DIB(out_fifo_i_75__5[67:66]),
        .DIC(out_fifo_i_75__5[69:68]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [57:56]),
        .DOB(\rd_ptr_reg[3]_0 [59:58]),
        .DOC(\rd_ptr_reg[3]_0 [61:60]),
        .DOD(NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED[1:0]),
        .WCLK(\entry_cnt_reg[4]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "78" *) 
  (* ram_slice_end = "79" *) 
  RAM32M mem_reg_0_15_78_79
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(out_fifo_i_75__5[71:70]),
        .DIB({1'b0,1'b0}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [63:62]),
        .DOB(NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED[1:0]),
        .DOC(NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED[1:0]),
        .DOD(NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED[1:0]),
        .WCLK(\entry_cnt_reg[4]_0 ),
        .WE(wr_en));
  LUT6 #(
    .INIT(64'hFFFFFFFFF701F700)) 
    \my_empty[1]_i_1__1 
       (.I0(\my_empty_reg[7]_0 ),
        .I1(phy_data_wr_en),
        .I2(\my_full_reg_n_0_[4] ),
        .I3(\my_empty_reg[1]_1 ),
        .I4(my_empty0),
        .I5(ofifo_rst),
        .O(\my_empty[1]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFF701F700)) 
    \my_empty[7]_i_1__1 
       (.I0(\my_empty_reg[7]_0 ),
        .I1(phy_data_wr_en),
        .I2(\my_full_reg_n_0_[4] ),
        .I3(\my_empty_reg_n_0_[7] ),
        .I4(my_empty0),
        .I5(ofifo_rst),
        .O(\my_empty[7]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'h4A400D08)) 
    \my_empty[7]_i_2__1 
       (.I0(wr_ptr_timing[2]),
        .I1(\my_empty[7]_i_3__1_n_0 ),
        .I2(wr_ptr_timing[3]),
        .I3(\my_empty[7]_i_4__1_n_0 ),
        .I4(\rd_ptr_reg_n_0_[2] ),
        .O(my_empty0));
  (* SOFT_HLUTNM = "soft_lutpair749" *) 
  LUT5 #(
    .INIT(32'h00000040)) 
    \my_empty[7]_i_3__1 
       (.I0(wr_ptr_timing[1]),
        .I1(\rd_ptr_reg_n_0_[0] ),
        .I2(\rd_ptr_reg_n_0_[1] ),
        .I3(\rd_ptr_reg_n_0_[3] ),
        .I4(wr_ptr_timing[0]),
        .O(\my_empty[7]_i_3__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair749" *) 
  LUT5 #(
    .INIT(32'h84210842)) 
    \my_empty[7]_i_4__1 
       (.I0(wr_ptr_timing[0]),
        .I1(wr_ptr_timing[1]),
        .I2(\rd_ptr_reg_n_0_[0] ),
        .I3(\rd_ptr_reg_n_0_[1] ),
        .I4(\rd_ptr_reg_n_0_[3] ),
        .O(\my_empty[7]_i_4__1_n_0 ));
  (* syn_maxfan = "3" *) 
  FDRE \my_empty_reg[1] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(1'b1),
        .D(\my_empty[1]_i_1__1_n_0 ),
        .Q(\my_empty_reg[1]_1 ),
        .R(1'b0));
  (* syn_maxfan = "3" *) 
  FDRE \my_empty_reg[7] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(1'b1),
        .D(\my_empty[7]_i_1__1_n_0 ),
        .Q(\my_empty_reg_n_0_[7] ),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h00000000FFFC0080)) 
    \my_full[4]_i_1__1 
       (.I0(my_full0),
        .I1(phy_data_wr_en),
        .I2(\my_empty_reg[7]_0 ),
        .I3(\my_empty_reg_n_0_[7] ),
        .I4(\my_full_reg_n_0_[4] ),
        .I5(ofifo_rst),
        .O(\my_full[4]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'h4A400D08)) 
    \my_full[4]_i_2__1 
       (.I0(rd_ptr_timing[2]),
        .I1(\my_full[4]_i_3__1_n_0 ),
        .I2(rd_ptr_timing[3]),
        .I3(\my_full[4]_i_4__1_n_0 ),
        .I4(wr_ptr[2]),
        .O(my_full0));
  (* SOFT_HLUTNM = "soft_lutpair748" *) 
  LUT5 #(
    .INIT(32'h00000040)) 
    \my_full[4]_i_3__1 
       (.I0(rd_ptr_timing[1]),
        .I1(wr_ptr[0]),
        .I2(wr_ptr[1]),
        .I3(wr_ptr[3]),
        .I4(rd_ptr_timing[0]),
        .O(\my_full[4]_i_3__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair748" *) 
  LUT5 #(
    .INIT(32'h84210842)) 
    \my_full[4]_i_4__1 
       (.I0(rd_ptr_timing[0]),
        .I1(rd_ptr_timing[1]),
        .I2(wr_ptr[0]),
        .I3(wr_ptr[1]),
        .I4(wr_ptr[3]),
        .O(\my_full[4]_i_4__1_n_0 ));
  (* syn_maxfan = "3" *) 
  FDRE \my_full_reg[4] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(1'b1),
        .D(\my_full[4]_i_1__1_n_0 ),
        .Q(\my_full_reg_n_0_[4] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair750" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_10__7
       (.I0(out_fifo_1),
        .I1(out_fifo_0[7]),
        .I2(mem_reg_0_15_12_17_n_2),
        .I3(\my_empty_reg[1]_1 ),
        .O(D1[7]));
  (* SOFT_HLUTNM = "soft_lutpair757" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_11__7
       (.I0(out_fifo_1),
        .I1(out_fifo_0[6]),
        .I2(mem_reg_0_15_12_17_n_3),
        .I3(\my_empty_reg[1]_1 ),
        .O(D1[6]));
  (* SOFT_HLUTNM = "soft_lutpair752" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_12__7
       (.I0(out_fifo_1),
        .I1(out_fifo_0[5]),
        .I2(mem_reg_0_15_12_17_n_0),
        .I3(\my_empty_reg[1]_1 ),
        .O(D1[5]));
  (* SOFT_HLUTNM = "soft_lutpair755" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_13__7
       (.I0(out_fifo_1),
        .I1(out_fifo_0[4]),
        .I2(mem_reg_0_15_12_17_n_1),
        .I3(\my_empty_reg[1]_1 ),
        .O(D1[4]));
  (* SOFT_HLUTNM = "soft_lutpair753" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_14__7
       (.I0(out_fifo_1),
        .I1(out_fifo_0[3]),
        .I2(mem_reg_0_15_6_11_n_4),
        .I3(\my_empty_reg[1]_1 ),
        .O(D1[3]));
  (* SOFT_HLUTNM = "soft_lutpair754" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_15__7
       (.I0(out_fifo_1),
        .I1(out_fifo_0[2]),
        .I2(mem_reg_0_15_6_11_n_5),
        .I3(\my_empty_reg[1]_1 ),
        .O(D1[2]));
  (* SOFT_HLUTNM = "soft_lutpair751" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_16__7
       (.I0(out_fifo),
        .I1(out_fifo_0[1]),
        .I2(mem_reg_0_15_6_11_n_2),
        .I3(\my_empty_reg[1]_1 ),
        .O(D1[1]));
  (* SOFT_HLUTNM = "soft_lutpair759" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_17__7
       (.I0(out_fifo),
        .I1(out_fifo_0[0]),
        .I2(mem_reg_0_15_6_11_n_3),
        .I3(\my_empty_reg[1]_1 ),
        .O(D1[0]));
  LUT3 #(
    .INIT(8'h0D)) 
    out_fifo_i_1__1
       (.I0(\my_empty_reg[1]_1 ),
        .I1(phy_data_wr_en),
        .I2(\my_empty_reg[7]_0 ),
        .O(\my_empty_reg[1]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair755" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_2__0
       (.I0(mem_reg_0_15_6_11_n_0),
        .I1(\my_empty_reg[1]_1 ),
        .O(D0[7]));
  (* SOFT_HLUTNM = "soft_lutpair751" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_3__0
       (.I0(mem_reg_0_15_6_11_n_1),
        .I1(\my_empty_reg[1]_1 ),
        .O(D0[6]));
  (* SOFT_HLUTNM = "soft_lutpair757" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_4__0
       (.I0(mem_reg_0_15_0_5_n_4),
        .I1(\my_empty_reg[1]_1 ),
        .O(D0[5]));
  (* SOFT_HLUTNM = "soft_lutpair753" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_5__0
       (.I0(mem_reg_0_15_0_5_n_5),
        .I1(\my_empty_reg[1]_1 ),
        .O(D0[4]));
  (* SOFT_HLUTNM = "soft_lutpair754" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_6__0
       (.I0(mem_reg_0_15_0_5_n_2),
        .I1(\my_empty_reg[1]_1 ),
        .O(D0[3]));
  (* SOFT_HLUTNM = "soft_lutpair750" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_7__0
       (.I0(mem_reg_0_15_0_5_n_3),
        .I1(\my_empty_reg[1]_1 ),
        .O(D0[2]));
  (* SOFT_HLUTNM = "soft_lutpair759" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_8__0
       (.I0(mem_reg_0_15_0_5_n_0),
        .I1(\my_empty_reg[1]_1 ),
        .O(D0[1]));
  (* SOFT_HLUTNM = "soft_lutpair752" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_9__0
       (.I0(mem_reg_0_15_0_5_n_1),
        .I1(\my_empty_reg[1]_1 ),
        .O(D0[0]));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[0] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(\rd_ptr_timing[3]_i_1__1_n_0 ),
        .D(nxt_rd_ptr[0]),
        .Q(\rd_ptr_reg_n_0_[0] ),
        .R(ofifo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[1] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(\rd_ptr_timing[3]_i_1__1_n_0 ),
        .D(nxt_rd_ptr[1]),
        .Q(\rd_ptr_reg_n_0_[1] ),
        .R(ofifo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[2] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(\rd_ptr_timing[3]_i_1__1_n_0 ),
        .D(nxt_rd_ptr[2]),
        .Q(\rd_ptr_reg_n_0_[2] ),
        .R(ofifo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[3] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(\rd_ptr_timing[3]_i_1__1_n_0 ),
        .D(nxt_rd_ptr[3]),
        .Q(\rd_ptr_reg_n_0_[3] ),
        .R(ofifo_rst));
  (* SOFT_HLUTNM = "soft_lutpair761" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rd_ptr_timing[0]_i_1__3 
       (.I0(\rd_ptr_reg_n_0_[3] ),
        .I1(\rd_ptr_reg_n_0_[0] ),
        .O(nxt_rd_ptr[0]));
  (* SOFT_HLUTNM = "soft_lutpair761" *) 
  LUT3 #(
    .INIT(8'hB4)) 
    \rd_ptr_timing[1]_i_1__3 
       (.I0(\rd_ptr_reg_n_0_[3] ),
        .I1(\rd_ptr_reg_n_0_[0] ),
        .I2(\rd_ptr_reg_n_0_[1] ),
        .O(nxt_rd_ptr[1]));
  (* SOFT_HLUTNM = "soft_lutpair758" *) 
  LUT4 #(
    .INIT(16'hAA6A)) 
    \rd_ptr_timing[2]_i_1__1 
       (.I0(\rd_ptr_reg_n_0_[2] ),
        .I1(\rd_ptr_reg_n_0_[0] ),
        .I2(\rd_ptr_reg_n_0_[1] ),
        .I3(\rd_ptr_reg_n_0_[3] ),
        .O(nxt_rd_ptr[2]));
  LUT2 #(
    .INIT(4'h1)) 
    \rd_ptr_timing[3]_i_1__1 
       (.I0(\my_empty_reg[7]_0 ),
        .I1(\my_empty_reg_n_0_[7] ),
        .O(\rd_ptr_timing[3]_i_1__1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair758" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \rd_ptr_timing[3]_i_2__1 
       (.I0(\rd_ptr_reg_n_0_[3] ),
        .I1(\rd_ptr_reg_n_0_[1] ),
        .I2(\rd_ptr_reg_n_0_[0] ),
        .I3(\rd_ptr_reg_n_0_[2] ),
        .O(nxt_rd_ptr[3]));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[0] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(\rd_ptr_timing[3]_i_1__1_n_0 ),
        .D(nxt_rd_ptr[0]),
        .Q(rd_ptr_timing[0]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[1] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(\rd_ptr_timing[3]_i_1__1_n_0 ),
        .D(nxt_rd_ptr[1]),
        .Q(rd_ptr_timing[1]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[2] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(\rd_ptr_timing[3]_i_1__1_n_0 ),
        .D(nxt_rd_ptr[2]),
        .Q(rd_ptr_timing[2]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[3] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(\rd_ptr_timing[3]_i_1__1_n_0 ),
        .D(nxt_rd_ptr[3]),
        .Q(rd_ptr_timing[3]),
        .R(ofifo_rst));
  (* SOFT_HLUTNM = "soft_lutpair760" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \wr_ptr[0]_i_1__3 
       (.I0(wr_ptr[3]),
        .I1(wr_ptr[0]),
        .O(nxt_wr_ptr[0]));
  (* SOFT_HLUTNM = "soft_lutpair760" *) 
  LUT3 #(
    .INIT(8'hB4)) 
    \wr_ptr[1]_i_1__3 
       (.I0(wr_ptr[3]),
        .I1(wr_ptr[0]),
        .I2(wr_ptr[1]),
        .O(nxt_wr_ptr[1]));
  (* SOFT_HLUTNM = "soft_lutpair756" *) 
  LUT4 #(
    .INIT(16'hAA6A)) 
    \wr_ptr[2]_i_1__1 
       (.I0(wr_ptr[2]),
        .I1(wr_ptr[0]),
        .I2(wr_ptr[1]),
        .I3(wr_ptr[3]),
        .O(nxt_wr_ptr[2]));
  LUT4 #(
    .INIT(16'h082A)) 
    \wr_ptr[3]_i_1__1 
       (.I0(phy_data_wr_en),
        .I1(\my_empty_reg[7]_0 ),
        .I2(\my_full_reg_n_0_[4] ),
        .I3(\my_empty_reg_n_0_[7] ),
        .O(wr_ptr0));
  (* SOFT_HLUTNM = "soft_lutpair756" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \wr_ptr[3]_i_2__0 
       (.I0(wr_ptr[3]),
        .I1(wr_ptr[1]),
        .I2(wr_ptr[0]),
        .I3(wr_ptr[2]),
        .O(nxt_wr_ptr[3]));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[0] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[0]),
        .Q(wr_ptr[0]),
        .R(ofifo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[1] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[1]),
        .Q(wr_ptr[1]),
        .R(ofifo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[2] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[2]),
        .Q(wr_ptr[2]),
        .R(ofifo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[3] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[3]),
        .Q(wr_ptr[3]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[0] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[0]),
        .Q(wr_ptr_timing[0]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[1] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[1]),
        .Q(wr_ptr_timing[1]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[2] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[2]),
        .Q(wr_ptr_timing[2]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[3] 
       (.C(\entry_cnt_reg[4]_0 ),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[3]),
        .Q(wr_ptr_timing[3]),
        .R(ofifo_rst));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_of_pre_fifo" *) 
module mig_mig_7series_v4_2_ddr_of_pre_fifo__parameterized1_40
   (\my_empty_reg[1]_0 ,
    \my_empty_reg[1]_1 ,
    D8,
    D0,
    \rd_ptr_reg[3]_0 ,
    Q,
    ofifo_rst,
    \my_full_reg[4]_0 ,
    \my_empty_reg[7]_0 ,
    phy_data_wr_en,
    out_fifo,
    out_fifo_0,
    out_fifo_1,
    phy_dout);
  output \my_empty_reg[1]_0 ;
  output \my_empty_reg[1]_1 ;
  output [7:0]D8;
  output [7:0]D0;
  output [63:0]\rd_ptr_reg[3]_0 ;
  output [2:0]Q;
  input ofifo_rst;
  input \my_full_reg[4]_0 ;
  input \my_empty_reg[7]_0 ;
  input phy_data_wr_en;
  input out_fifo;
  input [7:0]out_fifo_0;
  input out_fifo_1;
  input [71:0]phy_dout;

  wire [7:0]D0;
  wire [7:0]D8;
  wire [2:0]Q;
  wire entry_cnt10_out__0;
  wire \entry_cnt[0]_i_1_n_0 ;
  wire \entry_cnt[1]_i_1_n_0 ;
  wire \entry_cnt[2]_i_1_n_0 ;
  wire \entry_cnt[3]_i_1_n_0 ;
  wire \entry_cnt[4]_i_1_n_0 ;
  wire \entry_cnt[4]_i_2_n_0 ;
  wire \entry_cnt_reg_n_0_[0] ;
  wire \entry_cnt_reg_n_0_[1] ;
  wire mem_reg_0_15_0_5_n_0;
  wire mem_reg_0_15_0_5_n_1;
  wire mem_reg_0_15_0_5_n_2;
  wire mem_reg_0_15_0_5_n_3;
  wire mem_reg_0_15_0_5_n_4;
  wire mem_reg_0_15_0_5_n_5;
  wire mem_reg_0_15_60_65_n_4;
  wire mem_reg_0_15_60_65_n_5;
  wire mem_reg_0_15_66_71_n_0;
  wire mem_reg_0_15_66_71_n_1;
  wire mem_reg_0_15_66_71_n_2;
  wire mem_reg_0_15_66_71_n_3;
  wire mem_reg_0_15_66_71_n_4;
  wire mem_reg_0_15_66_71_n_5;
  wire mem_reg_0_15_6_11_n_0;
  wire mem_reg_0_15_6_11_n_1;
  wire my_empty0;
  wire \my_empty[1]_i_1__0_n_0 ;
  wire \my_empty[7]_i_1__0_n_0 ;
  wire \my_empty[7]_i_3__0_n_0 ;
  wire \my_empty[7]_i_4__0_n_0 ;
  wire \my_empty_reg[1]_0 ;
  wire \my_empty_reg[1]_1 ;
  wire \my_empty_reg[7]_0 ;
  wire \my_empty_reg_n_0_[7] ;
  wire my_full0;
  wire \my_full[4]_i_1__0_n_0 ;
  wire \my_full[4]_i_3__0_n_0 ;
  wire \my_full[4]_i_4__0_n_0 ;
  wire \my_full_reg[4]_0 ;
  wire \my_full_reg_n_0_[4] ;
  wire [3:0]nxt_rd_ptr;
  wire [3:0]nxt_wr_ptr;
  wire ofifo_rst;
  wire out_fifo;
  wire [7:0]out_fifo_0;
  wire out_fifo_1;
  wire phy_data_wr_en;
  wire [71:0]phy_dout;
  wire [63:0]\rd_ptr_reg[3]_0 ;
  wire \rd_ptr_reg_n_0_[0] ;
  wire \rd_ptr_reg_n_0_[1] ;
  wire \rd_ptr_reg_n_0_[2] ;
  wire \rd_ptr_reg_n_0_[3] ;
  wire [3:0]rd_ptr_timing;
  wire \rd_ptr_timing[3]_i_1__0_n_0 ;
  (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) wire wr_en;
  wire [3:0]wr_ptr;
  wire wr_ptr0;
  wire [3:0]wr_ptr_timing;
  wire [1:0]NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED;
  wire [1:0]NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED;

  (* SOFT_HLUTNM = "soft_lutpair698" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \entry_cnt[0]_i_1 
       (.I0(\entry_cnt_reg_n_0_[0] ),
        .O(\entry_cnt[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair695" *) 
  LUT5 #(
    .INIT(32'hAA6A5595)) 
    \entry_cnt[1]_i_1 
       (.I0(\entry_cnt_reg_n_0_[0] ),
        .I1(\my_empty_reg[7]_0 ),
        .I2(phy_data_wr_en),
        .I3(\my_full_reg_n_0_[4] ),
        .I4(\entry_cnt_reg_n_0_[1] ),
        .O(\entry_cnt[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFF7F0080AAEA5515)) 
    \entry_cnt[2]_i_1 
       (.I0(\entry_cnt_reg_n_0_[0] ),
        .I1(\my_empty_reg[7]_0 ),
        .I2(phy_data_wr_en),
        .I3(\my_full_reg_n_0_[4] ),
        .I4(Q[0]),
        .I5(\entry_cnt_reg_n_0_[1] ),
        .O(\entry_cnt[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair698" *) 
  LUT5 #(
    .INIT(32'h7F80FE01)) 
    \entry_cnt[3]_i_1 
       (.I0(entry_cnt10_out__0),
        .I1(\entry_cnt_reg_n_0_[0] ),
        .I2(\entry_cnt_reg_n_0_[1] ),
        .I3(Q[1]),
        .I4(Q[0]),
        .O(\entry_cnt[3]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h5003)) 
    \entry_cnt[4]_i_1 
       (.I0(\my_full_reg_n_0_[4] ),
        .I1(\my_empty_reg_n_0_[7] ),
        .I2(\my_empty_reg[7]_0 ),
        .I3(phy_data_wr_en),
        .O(\entry_cnt[4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h7FFF8000FFFE0001)) 
    \entry_cnt[4]_i_2 
       (.I0(\entry_cnt_reg_n_0_[1] ),
        .I1(\entry_cnt_reg_n_0_[0] ),
        .I2(entry_cnt10_out__0),
        .I3(Q[0]),
        .I4(Q[2]),
        .I5(Q[1]),
        .O(\entry_cnt[4]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair695" *) 
  LUT3 #(
    .INIT(8'h08)) 
    \entry_cnt[4]_i_3 
       (.I0(\my_empty_reg[7]_0 ),
        .I1(phy_data_wr_en),
        .I2(\my_full_reg_n_0_[4] ),
        .O(entry_cnt10_out__0));
  FDRE \entry_cnt_reg[0] 
       (.C(\my_full_reg[4]_0 ),
        .CE(\entry_cnt[4]_i_1_n_0 ),
        .D(\entry_cnt[0]_i_1_n_0 ),
        .Q(\entry_cnt_reg_n_0_[0] ),
        .R(ofifo_rst));
  FDRE \entry_cnt_reg[1] 
       (.C(\my_full_reg[4]_0 ),
        .CE(\entry_cnt[4]_i_1_n_0 ),
        .D(\entry_cnt[1]_i_1_n_0 ),
        .Q(\entry_cnt_reg_n_0_[1] ),
        .R(ofifo_rst));
  FDRE \entry_cnt_reg[2] 
       (.C(\my_full_reg[4]_0 ),
        .CE(\entry_cnt[4]_i_1_n_0 ),
        .D(\entry_cnt[2]_i_1_n_0 ),
        .Q(Q[0]),
        .R(ofifo_rst));
  FDRE \entry_cnt_reg[3] 
       (.C(\my_full_reg[4]_0 ),
        .CE(\entry_cnt[4]_i_1_n_0 ),
        .D(\entry_cnt[3]_i_1_n_0 ),
        .Q(Q[1]),
        .R(ofifo_rst));
  FDRE \entry_cnt_reg[4] 
       (.C(\my_full_reg[4]_0 ),
        .CE(\entry_cnt[4]_i_1_n_0 ),
        .D(\entry_cnt[4]_i_2_n_0 ),
        .Q(Q[2]),
        .R(ofifo_rst));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "0" *) 
  (* ram_slice_end = "5" *) 
  RAM32M mem_reg_0_15_0_5
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[1:0]),
        .DIB(phy_dout[3:2]),
        .DIC(phy_dout[5:4]),
        .DID({1'b0,1'b0}),
        .DOA({mem_reg_0_15_0_5_n_0,mem_reg_0_15_0_5_n_1}),
        .DOB({mem_reg_0_15_0_5_n_2,mem_reg_0_15_0_5_n_3}),
        .DOC({mem_reg_0_15_0_5_n_4,mem_reg_0_15_0_5_n_5}),
        .DOD(NLW_mem_reg_0_15_0_5_DOD_UNCONNECTED[1:0]),
        .WCLK(\my_full_reg[4]_0 ),
        .WE(wr_en));
  LUT4 #(
    .INIT(16'h2700)) 
    mem_reg_0_15_0_5_i_1
       (.I0(\my_empty_reg[7]_0 ),
        .I1(\my_full_reg_n_0_[4] ),
        .I2(\my_empty_reg[1]_1 ),
        .I3(phy_data_wr_en),
        .O(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "12" *) 
  (* ram_slice_end = "17" *) 
  RAM32M mem_reg_0_15_12_17
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[13:12]),
        .DIB(phy_dout[15:14]),
        .DIC(phy_dout[17:16]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [5:4]),
        .DOB(\rd_ptr_reg[3]_0 [7:6]),
        .DOC(\rd_ptr_reg[3]_0 [9:8]),
        .DOD(NLW_mem_reg_0_15_12_17_DOD_UNCONNECTED[1:0]),
        .WCLK(\my_full_reg[4]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "18" *) 
  (* ram_slice_end = "23" *) 
  RAM32M mem_reg_0_15_18_23
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[19:18]),
        .DIB(phy_dout[21:20]),
        .DIC(phy_dout[23:22]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [11:10]),
        .DOB(\rd_ptr_reg[3]_0 [13:12]),
        .DOC(\rd_ptr_reg[3]_0 [15:14]),
        .DOD(NLW_mem_reg_0_15_18_23_DOD_UNCONNECTED[1:0]),
        .WCLK(\my_full_reg[4]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "24" *) 
  (* ram_slice_end = "29" *) 
  RAM32M mem_reg_0_15_24_29
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[25:24]),
        .DIB(phy_dout[27:26]),
        .DIC(phy_dout[29:28]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [17:16]),
        .DOB(\rd_ptr_reg[3]_0 [19:18]),
        .DOC(\rd_ptr_reg[3]_0 [21:20]),
        .DOD(NLW_mem_reg_0_15_24_29_DOD_UNCONNECTED[1:0]),
        .WCLK(\my_full_reg[4]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "30" *) 
  (* ram_slice_end = "35" *) 
  RAM32M mem_reg_0_15_30_35
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[31:30]),
        .DIB(phy_dout[33:32]),
        .DIC(phy_dout[35:34]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [23:22]),
        .DOB(\rd_ptr_reg[3]_0 [25:24]),
        .DOC(\rd_ptr_reg[3]_0 [27:26]),
        .DOD(NLW_mem_reg_0_15_30_35_DOD_UNCONNECTED[1:0]),
        .WCLK(\my_full_reg[4]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "36" *) 
  (* ram_slice_end = "41" *) 
  RAM32M mem_reg_0_15_36_41
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[37:36]),
        .DIB(phy_dout[39:38]),
        .DIC(phy_dout[41:40]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [29:28]),
        .DOB(\rd_ptr_reg[3]_0 [31:30]),
        .DOC(\rd_ptr_reg[3]_0 [33:32]),
        .DOD(NLW_mem_reg_0_15_36_41_DOD_UNCONNECTED[1:0]),
        .WCLK(\my_full_reg[4]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "42" *) 
  (* ram_slice_end = "47" *) 
  RAM32M mem_reg_0_15_42_47
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[43:42]),
        .DIB(phy_dout[45:44]),
        .DIC(phy_dout[47:46]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [35:34]),
        .DOB(\rd_ptr_reg[3]_0 [37:36]),
        .DOC(\rd_ptr_reg[3]_0 [39:38]),
        .DOD(NLW_mem_reg_0_15_42_47_DOD_UNCONNECTED[1:0]),
        .WCLK(\my_full_reg[4]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "48" *) 
  (* ram_slice_end = "53" *) 
  RAM32M mem_reg_0_15_48_53
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[49:48]),
        .DIB(phy_dout[51:50]),
        .DIC(phy_dout[53:52]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [41:40]),
        .DOB(\rd_ptr_reg[3]_0 [43:42]),
        .DOC(\rd_ptr_reg[3]_0 [45:44]),
        .DOD(NLW_mem_reg_0_15_48_53_DOD_UNCONNECTED[1:0]),
        .WCLK(\my_full_reg[4]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "54" *) 
  (* ram_slice_end = "59" *) 
  RAM32M mem_reg_0_15_54_59
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[55:54]),
        .DIB(phy_dout[57:56]),
        .DIC(phy_dout[59:58]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [47:46]),
        .DOB(\rd_ptr_reg[3]_0 [49:48]),
        .DOC(\rd_ptr_reg[3]_0 [51:50]),
        .DOD(NLW_mem_reg_0_15_54_59_DOD_UNCONNECTED[1:0]),
        .WCLK(\my_full_reg[4]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "60" *) 
  (* ram_slice_end = "65" *) 
  RAM32M mem_reg_0_15_60_65
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[61:60]),
        .DIB(phy_dout[63:62]),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [53:52]),
        .DOB(\rd_ptr_reg[3]_0 [55:54]),
        .DOC({mem_reg_0_15_60_65_n_4,mem_reg_0_15_60_65_n_5}),
        .DOD(NLW_mem_reg_0_15_60_65_DOD_UNCONNECTED[1:0]),
        .WCLK(\my_full_reg[4]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "66" *) 
  (* ram_slice_end = "71" *) 
  RAM32M mem_reg_0_15_66_71
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA({1'b0,1'b0}),
        .DIB({1'b0,1'b0}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA({mem_reg_0_15_66_71_n_0,mem_reg_0_15_66_71_n_1}),
        .DOB({mem_reg_0_15_66_71_n_2,mem_reg_0_15_66_71_n_3}),
        .DOC({mem_reg_0_15_66_71_n_4,mem_reg_0_15_66_71_n_5}),
        .DOD(NLW_mem_reg_0_15_66_71_DOD_UNCONNECTED[1:0]),
        .WCLK(\my_full_reg[4]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "6" *) 
  (* ram_slice_end = "11" *) 
  RAM32M mem_reg_0_15_6_11
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[7:6]),
        .DIB(phy_dout[9:8]),
        .DIC(phy_dout[11:10]),
        .DID({1'b0,1'b0}),
        .DOA({mem_reg_0_15_6_11_n_0,mem_reg_0_15_6_11_n_1}),
        .DOB(\rd_ptr_reg[3]_0 [1:0]),
        .DOC(\rd_ptr_reg[3]_0 [3:2]),
        .DOD(NLW_mem_reg_0_15_6_11_DOD_UNCONNECTED[1:0]),
        .WCLK(\my_full_reg[4]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "72" *) 
  (* ram_slice_end = "77" *) 
  RAM32M mem_reg_0_15_72_77
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[65:64]),
        .DIB(phy_dout[67:66]),
        .DIC(phy_dout[69:68]),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [57:56]),
        .DOB(\rd_ptr_reg[3]_0 [59:58]),
        .DOC(\rd_ptr_reg[3]_0 [61:60]),
        .DOD(NLW_mem_reg_0_15_72_77_DOD_UNCONNECTED[1:0]),
        .WCLK(\my_full_reg[4]_0 ),
        .WE(wr_en));
  (* METHODOLOGY_DRC_VIOS = "" *) 
  (* RTL_RAM_BITS = "720" *) 
  (* RTL_RAM_NAME = "of_pre_fifo_gen.u_ddr_of_pre_fifo/mem" *) 
  (* ram_addr_begin = "0" *) 
  (* ram_addr_end = "8" *) 
  (* ram_offset = "0" *) 
  (* ram_slice_begin = "78" *) 
  (* ram_slice_end = "79" *) 
  RAM32M mem_reg_0_15_78_79
       (.ADDRA({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRB({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRC({1'b0,\rd_ptr_reg_n_0_[3] ,\rd_ptr_reg_n_0_[2] ,\rd_ptr_reg_n_0_[1] ,\rd_ptr_reg_n_0_[0] }),
        .ADDRD({1'b0,wr_ptr}),
        .DIA(phy_dout[71:70]),
        .DIB({1'b0,1'b0}),
        .DIC({1'b0,1'b0}),
        .DID({1'b0,1'b0}),
        .DOA(\rd_ptr_reg[3]_0 [63:62]),
        .DOB(NLW_mem_reg_0_15_78_79_DOB_UNCONNECTED[1:0]),
        .DOC(NLW_mem_reg_0_15_78_79_DOC_UNCONNECTED[1:0]),
        .DOD(NLW_mem_reg_0_15_78_79_DOD_UNCONNECTED[1:0]),
        .WCLK(\my_full_reg[4]_0 ),
        .WE(wr_en));
  LUT6 #(
    .INIT(64'hFFFFFFFFF701F700)) 
    \my_empty[1]_i_1__0 
       (.I0(\my_empty_reg[7]_0 ),
        .I1(phy_data_wr_en),
        .I2(\my_full_reg_n_0_[4] ),
        .I3(\my_empty_reg[1]_1 ),
        .I4(my_empty0),
        .I5(ofifo_rst),
        .O(\my_empty[1]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFF701F700)) 
    \my_empty[7]_i_1__0 
       (.I0(\my_empty_reg[7]_0 ),
        .I1(phy_data_wr_en),
        .I2(\my_full_reg_n_0_[4] ),
        .I3(\my_empty_reg_n_0_[7] ),
        .I4(my_empty0),
        .I5(ofifo_rst),
        .O(\my_empty[7]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'h4A400D08)) 
    \my_empty[7]_i_2__0 
       (.I0(wr_ptr_timing[2]),
        .I1(\my_empty[7]_i_3__0_n_0 ),
        .I2(wr_ptr_timing[3]),
        .I3(\my_empty[7]_i_4__0_n_0 ),
        .I4(\rd_ptr_reg_n_0_[2] ),
        .O(my_empty0));
  (* SOFT_HLUTNM = "soft_lutpair697" *) 
  LUT5 #(
    .INIT(32'h00000040)) 
    \my_empty[7]_i_3__0 
       (.I0(wr_ptr_timing[1]),
        .I1(\rd_ptr_reg_n_0_[0] ),
        .I2(\rd_ptr_reg_n_0_[1] ),
        .I3(\rd_ptr_reg_n_0_[3] ),
        .I4(wr_ptr_timing[0]),
        .O(\my_empty[7]_i_3__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair697" *) 
  LUT5 #(
    .INIT(32'h84210842)) 
    \my_empty[7]_i_4__0 
       (.I0(wr_ptr_timing[0]),
        .I1(wr_ptr_timing[1]),
        .I2(\rd_ptr_reg_n_0_[0] ),
        .I3(\rd_ptr_reg_n_0_[1] ),
        .I4(\rd_ptr_reg_n_0_[3] ),
        .O(\my_empty[7]_i_4__0_n_0 ));
  (* syn_maxfan = "3" *) 
  FDRE \my_empty_reg[1] 
       (.C(\my_full_reg[4]_0 ),
        .CE(1'b1),
        .D(\my_empty[1]_i_1__0_n_0 ),
        .Q(\my_empty_reg[1]_1 ),
        .R(1'b0));
  (* syn_maxfan = "3" *) 
  FDRE \my_empty_reg[7] 
       (.C(\my_full_reg[4]_0 ),
        .CE(1'b1),
        .D(\my_empty[7]_i_1__0_n_0 ),
        .Q(\my_empty_reg_n_0_[7] ),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h00000000FFFC0080)) 
    \my_full[4]_i_1__0 
       (.I0(my_full0),
        .I1(phy_data_wr_en),
        .I2(\my_empty_reg[7]_0 ),
        .I3(\my_empty_reg_n_0_[7] ),
        .I4(\my_full_reg_n_0_[4] ),
        .I5(ofifo_rst),
        .O(\my_full[4]_i_1__0_n_0 ));
  LUT5 #(
    .INIT(32'h4A400D08)) 
    \my_full[4]_i_2__0 
       (.I0(rd_ptr_timing[2]),
        .I1(\my_full[4]_i_3__0_n_0 ),
        .I2(rd_ptr_timing[3]),
        .I3(\my_full[4]_i_4__0_n_0 ),
        .I4(wr_ptr[2]),
        .O(my_full0));
  (* SOFT_HLUTNM = "soft_lutpair696" *) 
  LUT5 #(
    .INIT(32'h00000040)) 
    \my_full[4]_i_3__0 
       (.I0(rd_ptr_timing[1]),
        .I1(wr_ptr[0]),
        .I2(wr_ptr[1]),
        .I3(wr_ptr[3]),
        .I4(rd_ptr_timing[0]),
        .O(\my_full[4]_i_3__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair696" *) 
  LUT5 #(
    .INIT(32'h84210842)) 
    \my_full[4]_i_4__0 
       (.I0(rd_ptr_timing[0]),
        .I1(rd_ptr_timing[1]),
        .I2(wr_ptr[0]),
        .I3(wr_ptr[1]),
        .I4(wr_ptr[3]),
        .O(\my_full[4]_i_4__0_n_0 ));
  (* syn_maxfan = "3" *) 
  FDRE \my_full_reg[4] 
       (.C(\my_full_reg[4]_0 ),
        .CE(1'b1),
        .D(\my_full[4]_i_1__0_n_0 ),
        .Q(\my_full_reg_n_0_[4] ),
        .R(1'b0));
  LUT3 #(
    .INIT(8'h0D)) 
    out_fifo_i_1__0
       (.I0(\my_empty_reg[1]_1 ),
        .I1(phy_data_wr_en),
        .I2(\my_empty_reg[7]_0 ),
        .O(\my_empty_reg[1]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair704" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_2__9
       (.I0(out_fifo_1),
        .I1(out_fifo_0[7]),
        .I2(mem_reg_0_15_6_11_n_0),
        .I3(\my_empty_reg[1]_1 ),
        .O(D0[7]));
  (* SOFT_HLUTNM = "soft_lutpair703" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_3__9
       (.I0(out_fifo_1),
        .I1(out_fifo_0[6]),
        .I2(mem_reg_0_15_6_11_n_1),
        .I3(\my_empty_reg[1]_1 ),
        .O(D0[6]));
  (* SOFT_HLUTNM = "soft_lutpair699" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_4__9
       (.I0(out_fifo_1),
        .I1(out_fifo_0[5]),
        .I2(mem_reg_0_15_0_5_n_4),
        .I3(\my_empty_reg[1]_1 ),
        .O(D0[5]));
  (* SOFT_HLUTNM = "soft_lutpair702" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_5__9
       (.I0(out_fifo_1),
        .I1(out_fifo_0[4]),
        .I2(mem_reg_0_15_0_5_n_5),
        .I3(\my_empty_reg[1]_1 ),
        .O(D0[4]));
  (* SOFT_HLUTNM = "soft_lutpair704" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_66
       (.I0(mem_reg_0_15_66_71_n_4),
        .I1(\my_empty_reg[1]_1 ),
        .O(D8[7]));
  (* SOFT_HLUTNM = "soft_lutpair701" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_67
       (.I0(mem_reg_0_15_66_71_n_5),
        .I1(\my_empty_reg[1]_1 ),
        .O(D8[6]));
  (* SOFT_HLUTNM = "soft_lutpair703" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_68
       (.I0(mem_reg_0_15_66_71_n_2),
        .I1(\my_empty_reg[1]_1 ),
        .O(D8[5]));
  (* SOFT_HLUTNM = "soft_lutpair699" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_69
       (.I0(mem_reg_0_15_66_71_n_3),
        .I1(\my_empty_reg[1]_1 ),
        .O(D8[4]));
  (* SOFT_HLUTNM = "soft_lutpair701" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_6__9
       (.I0(out_fifo_1),
        .I1(out_fifo_0[3]),
        .I2(mem_reg_0_15_0_5_n_2),
        .I3(\my_empty_reg[1]_1 ),
        .O(D0[3]));
  (* SOFT_HLUTNM = "soft_lutpair705" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_70
       (.I0(mem_reg_0_15_66_71_n_0),
        .I1(\my_empty_reg[1]_1 ),
        .O(D8[3]));
  (* SOFT_HLUTNM = "soft_lutpair700" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_71
       (.I0(mem_reg_0_15_66_71_n_1),
        .I1(\my_empty_reg[1]_1 ),
        .O(D8[2]));
  (* SOFT_HLUTNM = "soft_lutpair706" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_72
       (.I0(mem_reg_0_15_60_65_n_4),
        .I1(\my_empty_reg[1]_1 ),
        .O(D8[1]));
  (* SOFT_HLUTNM = "soft_lutpair702" *) 
  LUT2 #(
    .INIT(4'h2)) 
    out_fifo_i_73
       (.I0(mem_reg_0_15_60_65_n_5),
        .I1(\my_empty_reg[1]_1 ),
        .O(D8[0]));
  (* SOFT_HLUTNM = "soft_lutpair706" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_7__9
       (.I0(out_fifo_1),
        .I1(out_fifo_0[2]),
        .I2(mem_reg_0_15_0_5_n_3),
        .I3(\my_empty_reg[1]_1 ),
        .O(D0[2]));
  (* SOFT_HLUTNM = "soft_lutpair700" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_8__9
       (.I0(out_fifo),
        .I1(out_fifo_0[1]),
        .I2(mem_reg_0_15_0_5_n_0),
        .I3(\my_empty_reg[1]_1 ),
        .O(D0[1]));
  (* SOFT_HLUTNM = "soft_lutpair705" *) 
  LUT4 #(
    .INIT(16'h88F0)) 
    out_fifo_i_9__9
       (.I0(out_fifo),
        .I1(out_fifo_0[0]),
        .I2(mem_reg_0_15_0_5_n_1),
        .I3(\my_empty_reg[1]_1 ),
        .O(D0[0]));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[0] 
       (.C(\my_full_reg[4]_0 ),
        .CE(\rd_ptr_timing[3]_i_1__0_n_0 ),
        .D(nxt_rd_ptr[0]),
        .Q(\rd_ptr_reg_n_0_[0] ),
        .R(ofifo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[1] 
       (.C(\my_full_reg[4]_0 ),
        .CE(\rd_ptr_timing[3]_i_1__0_n_0 ),
        .D(nxt_rd_ptr[1]),
        .Q(\rd_ptr_reg_n_0_[1] ),
        .R(ofifo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[2] 
       (.C(\my_full_reg[4]_0 ),
        .CE(\rd_ptr_timing[3]_i_1__0_n_0 ),
        .D(nxt_rd_ptr[2]),
        .Q(\rd_ptr_reg_n_0_[2] ),
        .R(ofifo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \rd_ptr_reg[3] 
       (.C(\my_full_reg[4]_0 ),
        .CE(\rd_ptr_timing[3]_i_1__0_n_0 ),
        .D(nxt_rd_ptr[3]),
        .Q(\rd_ptr_reg_n_0_[3] ),
        .R(ofifo_rst));
  (* SOFT_HLUTNM = "soft_lutpair710" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rd_ptr_timing[0]_i_1__1 
       (.I0(\rd_ptr_reg_n_0_[3] ),
        .I1(\rd_ptr_reg_n_0_[0] ),
        .O(nxt_rd_ptr[0]));
  (* SOFT_HLUTNM = "soft_lutpair710" *) 
  LUT3 #(
    .INIT(8'hB4)) 
    \rd_ptr_timing[1]_i_1__1 
       (.I0(\rd_ptr_reg_n_0_[3] ),
        .I1(\rd_ptr_reg_n_0_[0] ),
        .I2(\rd_ptr_reg_n_0_[1] ),
        .O(nxt_rd_ptr[1]));
  (* SOFT_HLUTNM = "soft_lutpair708" *) 
  LUT4 #(
    .INIT(16'hAA6A)) 
    \rd_ptr_timing[2]_i_1__0 
       (.I0(\rd_ptr_reg_n_0_[2] ),
        .I1(\rd_ptr_reg_n_0_[0] ),
        .I2(\rd_ptr_reg_n_0_[1] ),
        .I3(\rd_ptr_reg_n_0_[3] ),
        .O(nxt_rd_ptr[2]));
  LUT2 #(
    .INIT(4'h1)) 
    \rd_ptr_timing[3]_i_1__0 
       (.I0(\my_empty_reg[7]_0 ),
        .I1(\my_empty_reg_n_0_[7] ),
        .O(\rd_ptr_timing[3]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair708" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \rd_ptr_timing[3]_i_2__0 
       (.I0(\rd_ptr_reg_n_0_[3] ),
        .I1(\rd_ptr_reg_n_0_[1] ),
        .I2(\rd_ptr_reg_n_0_[0] ),
        .I3(\rd_ptr_reg_n_0_[2] ),
        .O(nxt_rd_ptr[3]));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[0] 
       (.C(\my_full_reg[4]_0 ),
        .CE(\rd_ptr_timing[3]_i_1__0_n_0 ),
        .D(nxt_rd_ptr[0]),
        .Q(rd_ptr_timing[0]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[1] 
       (.C(\my_full_reg[4]_0 ),
        .CE(\rd_ptr_timing[3]_i_1__0_n_0 ),
        .D(nxt_rd_ptr[1]),
        .Q(rd_ptr_timing[1]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[2] 
       (.C(\my_full_reg[4]_0 ),
        .CE(\rd_ptr_timing[3]_i_1__0_n_0 ),
        .D(nxt_rd_ptr[2]),
        .Q(rd_ptr_timing[2]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \rd_ptr_timing_reg[3] 
       (.C(\my_full_reg[4]_0 ),
        .CE(\rd_ptr_timing[3]_i_1__0_n_0 ),
        .D(nxt_rd_ptr[3]),
        .Q(rd_ptr_timing[3]),
        .R(ofifo_rst));
  (* SOFT_HLUTNM = "soft_lutpair709" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \wr_ptr[0]_i_1__1 
       (.I0(wr_ptr[3]),
        .I1(wr_ptr[0]),
        .O(nxt_wr_ptr[0]));
  (* SOFT_HLUTNM = "soft_lutpair709" *) 
  LUT3 #(
    .INIT(8'hB4)) 
    \wr_ptr[1]_i_1__1 
       (.I0(wr_ptr[3]),
        .I1(wr_ptr[0]),
        .I2(wr_ptr[1]),
        .O(nxt_wr_ptr[1]));
  (* SOFT_HLUTNM = "soft_lutpair707" *) 
  LUT4 #(
    .INIT(16'hAA6A)) 
    \wr_ptr[2]_i_1__0 
       (.I0(wr_ptr[2]),
        .I1(wr_ptr[0]),
        .I2(wr_ptr[1]),
        .I3(wr_ptr[3]),
        .O(nxt_wr_ptr[2]));
  LUT4 #(
    .INIT(16'h082A)) 
    \wr_ptr[3]_i_1__0 
       (.I0(phy_data_wr_en),
        .I1(\my_empty_reg[7]_0 ),
        .I2(\my_full_reg_n_0_[4] ),
        .I3(\my_empty_reg_n_0_[7] ),
        .O(wr_ptr0));
  (* SOFT_HLUTNM = "soft_lutpair707" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \wr_ptr[3]_i_2 
       (.I0(wr_ptr[3]),
        .I1(wr_ptr[1]),
        .I2(wr_ptr[0]),
        .I3(wr_ptr[2]),
        .O(nxt_wr_ptr[3]));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[0] 
       (.C(\my_full_reg[4]_0 ),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[0]),
        .Q(wr_ptr[0]),
        .R(ofifo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[1] 
       (.C(\my_full_reg[4]_0 ),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[1]),
        .Q(wr_ptr[1]),
        .R(ofifo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[2] 
       (.C(\my_full_reg[4]_0 ),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[2]),
        .Q(wr_ptr[2]),
        .R(ofifo_rst));
  (* syn_maxfan = "10" *) 
  FDRE \wr_ptr_reg[3] 
       (.C(\my_full_reg[4]_0 ),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[3]),
        .Q(wr_ptr[3]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[0] 
       (.C(\my_full_reg[4]_0 ),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[0]),
        .Q(wr_ptr_timing[0]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[1] 
       (.C(\my_full_reg[4]_0 ),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[1]),
        .Q(wr_ptr_timing[1]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[2] 
       (.C(\my_full_reg[4]_0 ),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[2]),
        .Q(wr_ptr_timing[2]),
        .R(ofifo_rst));
  (* KEEP = "yes" *) 
  FDRE \wr_ptr_timing_reg[3] 
       (.C(\my_full_reg[4]_0 ),
        .CE(wr_ptr0),
        .D(nxt_wr_ptr[3]),
        .Q(wr_ptr_timing[3]),
        .R(ofifo_rst));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_phy_4lanes" *) 
module mig_mig_7series_v4_2_ddr_phy_4lanes
   (out_dqs_4,
    ts_dqs_4,
    A_rst_primitives_reg_0,
    mem_dq_out,
    mem_dq_ts,
    in0,
    idelay_ld_rst,
    out_dqs_5,
    ts_dqs_5,
    A_rst_primitives_reg_1,
    if_empty_r,
    \my_empty_reg[4] ,
    idelay_ld_rst_0,
    out_dqs_6,
    ts_dqs_6,
    A_rst_primitives_reg_2,
    if_empty_r_0,
    \my_empty_reg[4]_0 ,
    idelay_ld_rst_1,
    out_dqs_7,
    ts_dqs_7,
    A_rst_primitives_reg_3,
    idelay_ld_rst_2,
    _phy_ctl_full_p__0,
    phy_ctl_wr_i2_reg,
    ref_dll_lock_w__0,
    rst_primitives,
    mcGo_w,
    rst_out_reg_0,
    rclk_delay_11,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,
    if_empty,
    \my_empty_reg[1] ,
    phy_mc_data_full,
    \my_empty_reg[1]_0 ,
    \my_empty_reg[1]_1 ,
    \my_empty_reg[1]_2 ,
    A_rst_primitives_reg_4,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1 ,
    \rd_mux_sel_r_reg[2] ,
    \rd_mux_sel_r_reg[2]_0 ,
    \rd_mux_sel_r_reg[2]_1 ,
    \rd_mux_sel_r_reg[2]_2 ,
    \rd_mux_sel_r_reg[2]_3 ,
    \rd_mux_sel_r_reg[2]_4 ,
    \rd_mux_sel_r_reg[2]_5 ,
    \rd_mux_sel_r_reg[2]_6 ,
    \rd_mux_sel_r_reg[2]_7 ,
    \rd_mux_sel_r_reg[2]_8 ,
    \rd_mux_sel_r_reg[2]_9 ,
    \rd_mux_sel_r_reg[2]_10 ,
    \rd_mux_sel_r_reg[2]_11 ,
    \rd_mux_sel_r_reg[2]_12 ,
    \rd_mux_sel_r_reg[2]_13 ,
    \rd_mux_sel_r_reg[2]_14 ,
    \rd_mux_sel_r_reg[2]_15 ,
    \rd_mux_sel_r_reg[2]_16 ,
    \rd_mux_sel_r_reg[2]_17 ,
    \rd_mux_sel_r_reg[2]_18 ,
    \rd_mux_sel_r_reg[2]_19 ,
    \rd_mux_sel_r_reg[2]_20 ,
    \rd_mux_sel_r_reg[2]_21 ,
    \rd_mux_sel_r_reg[2]_22 ,
    \rd_mux_sel_r_reg[2]_23 ,
    \rd_mux_sel_r_reg[2]_24 ,
    \rd_mux_sel_r_reg[2]_25 ,
    \rd_mux_sel_r_reg[2]_26 ,
    \rd_mux_sel_r_reg[2]_27 ,
    \rd_mux_sel_r_reg[2]_28 ,
    \rd_mux_sel_r_reg[2]_29 ,
    \rd_mux_sel_r_reg[2]_30 ,
    \rd_mux_sel_r_reg[2]_31 ,
    \rd_mux_sel_r_reg[2]_32 ,
    \rd_mux_sel_r_reg[2]_33 ,
    \rd_mux_sel_r_reg[2]_34 ,
    \rd_mux_sel_r_reg[2]_35 ,
    \rd_mux_sel_r_reg[2]_36 ,
    \rd_mux_sel_r_reg[2]_37 ,
    \rd_mux_sel_r_reg[2]_38 ,
    \rd_mux_sel_r_reg[2]_39 ,
    \rd_mux_sel_r_reg[2]_40 ,
    \rd_mux_sel_r_reg[2]_41 ,
    \rd_mux_sel_r_reg[2]_42 ,
    \rd_mux_sel_r_reg[2]_43 ,
    \rd_mux_sel_r_reg[2]_44 ,
    \rd_mux_sel_r_reg[2]_45 ,
    \rd_mux_sel_r_reg[2]_46 ,
    \rd_mux_sel_r_reg[2]_47 ,
    \rd_mux_sel_r_reg[2]_48 ,
    \rd_mux_sel_r_reg[2]_49 ,
    \rd_mux_sel_r_reg[2]_50 ,
    \rd_mux_sel_r_reg[2]_51 ,
    \rd_mux_sel_r_reg[2]_52 ,
    \rd_mux_sel_r_reg[2]_53 ,
    \rd_mux_sel_r_reg[2]_54 ,
    \rd_mux_sel_r_reg[2]_55 ,
    \rd_mux_sel_r_reg[2]_56 ,
    \rd_mux_sel_r_reg[2]_57 ,
    \rd_mux_sel_r_reg[2]_58 ,
    \rd_mux_sel_r_reg[2]_59 ,
    \rd_mux_sel_r_reg[2]_60 ,
    \rd_mux_sel_r_reg[2]_61 ,
    \rd_mux_sel_r_reg[2]_62 ,
    phy_rddata_en,
    \rd_mux_sel_r_reg[1] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ,
    \rd_mux_sel_r_reg[1]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ,
    \rd_mux_sel_r_reg[1]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ,
    \rd_mux_sel_r_reg[1]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ,
    \rd_mux_sel_r_reg[1]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ,
    \rd_mux_sel_r_reg[1]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ,
    \rd_mux_sel_r_reg[1]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ,
    \rd_mux_sel_r_reg[1]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_2 ,
    \rd_mux_sel_r_reg[1]_7 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2 ,
    \rd_mux_sel_r_reg[1]_8 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2 ,
    \rd_mux_sel_r_reg[1]_9 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2 ,
    \rd_mux_sel_r_reg[1]_10 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2 ,
    \rd_mux_sel_r_reg[1]_11 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2 ,
    \rd_mux_sel_r_reg[1]_12 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2 ,
    \rd_mux_sel_r_reg[1]_13 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ,
    \rd_mux_sel_r_reg[1]_14 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_2 ,
    \rd_mux_sel_r_reg[1]_15 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2 ,
    \rd_mux_sel_r_reg[1]_16 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2 ,
    \rd_mux_sel_r_reg[1]_17 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2 ,
    \rd_mux_sel_r_reg[1]_18 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2 ,
    \rd_mux_sel_r_reg[1]_19 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2 ,
    \rd_mux_sel_r_reg[1]_20 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2 ,
    \rd_mux_sel_r_reg[1]_21 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ,
    \rd_mux_sel_r_reg[1]_22 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_2 ,
    \rd_mux_sel_r_reg[1]_23 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2 ,
    \rd_mux_sel_r_reg[1]_24 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2 ,
    \rd_mux_sel_r_reg[1]_25 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2 ,
    \rd_mux_sel_r_reg[1]_26 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2 ,
    \rd_mux_sel_r_reg[1]_27 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2 ,
    \rd_mux_sel_r_reg[1]_28 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2 ,
    \rd_mux_sel_r_reg[1]_29 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ,
    \rd_mux_sel_r_reg[1]_30 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_2 ,
    \rd_mux_sel_r_reg[1]_31 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2 ,
    \rd_mux_sel_r_reg[1]_32 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2 ,
    \rd_mux_sel_r_reg[1]_33 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2 ,
    \rd_mux_sel_r_reg[1]_34 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2 ,
    \rd_mux_sel_r_reg[1]_35 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2 ,
    \rd_mux_sel_r_reg[1]_36 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2 ,
    \rd_mux_sel_r_reg[1]_37 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ,
    \rd_mux_sel_r_reg[1]_38 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_2 ,
    \rd_mux_sel_r_reg[1]_39 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2 ,
    \rd_mux_sel_r_reg[1]_40 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2 ,
    \rd_mux_sel_r_reg[1]_41 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2 ,
    \rd_mux_sel_r_reg[1]_42 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2 ,
    \rd_mux_sel_r_reg[1]_43 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2 ,
    \rd_mux_sel_r_reg[1]_44 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2 ,
    \rd_mux_sel_r_reg[1]_45 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ,
    \rd_mux_sel_r_reg[1]_46 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_2 ,
    \rd_mux_sel_r_reg[1]_47 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2 ,
    \rd_mux_sel_r_reg[1]_48 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2 ,
    \rd_mux_sel_r_reg[1]_49 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2 ,
    \rd_mux_sel_r_reg[1]_50 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2 ,
    \rd_mux_sel_r_reg[1]_51 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2 ,
    \rd_mux_sel_r_reg[1]_52 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2 ,
    \rd_mux_sel_r_reg[1]_53 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ,
    \rd_mux_sel_r_reg[1]_54 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_2 ,
    \rd_mux_sel_r_reg[1]_55 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2 ,
    \rd_mux_sel_r_reg[1]_56 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2 ,
    \rd_mux_sel_r_reg[1]_57 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2 ,
    \rd_mux_sel_r_reg[1]_58 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2 ,
    \rd_mux_sel_r_reg[1]_59 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2 ,
    \rd_mux_sel_r_reg[1]_60 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2 ,
    \rd_mux_sel_r_reg[1]_61 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ,
    \rd_mux_sel_r_reg[1]_62 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2 ,
    \po_stg2_wrcal_cnt_reg[1] ,
    \po_stg2_wrcal_cnt_reg[1]_0 ,
    \po_stg2_wrcal_cnt_reg[1]_1 ,
    \po_stg2_wrcal_cnt_reg[1]_2 ,
    \po_stg2_wrcal_cnt_reg[1]_3 ,
    \po_stg2_wrcal_cnt_reg[1]_4 ,
    \po_stg2_wrcal_cnt_reg[1]_5 ,
    \po_stg2_wrcal_cnt_reg[1]_6 ,
    \po_stg2_wrcal_cnt_reg[1]_7 ,
    \po_stg2_wrcal_cnt_reg[1]_8 ,
    \po_stg2_wrcal_cnt_reg[1]_9 ,
    \po_stg2_wrcal_cnt_reg[1]_10 ,
    \po_stg2_wrcal_cnt_reg[1]_11 ,
    \po_stg2_wrcal_cnt_reg[1]_12 ,
    \po_stg2_wrcal_cnt_reg[1]_13 ,
    \po_stg2_wrcal_cnt_reg[1]_14 ,
    \po_stg2_wrcal_cnt_reg[1]_15 ,
    \po_stg2_wrcal_cnt_reg[1]_16 ,
    \po_stg2_wrcal_cnt_reg[1]_17 ,
    \po_stg2_wrcal_cnt_reg[1]_18 ,
    \po_stg2_wrcal_cnt_reg[1]_19 ,
    \po_stg2_wrcal_cnt_reg[1]_20 ,
    \po_stg2_wrcal_cnt_reg[1]_21 ,
    \po_stg2_wrcal_cnt_reg[1]_22 ,
    \po_stg2_wrcal_cnt_reg[1]_23 ,
    \po_stg2_wrcal_cnt_reg[1]_24 ,
    \po_stg2_wrcal_cnt_reg[1]_25 ,
    \po_stg2_wrcal_cnt_reg[1]_26 ,
    \po_stg2_wrcal_cnt_reg[1]_27 ,
    \po_stg2_wrcal_cnt_reg[1]_28 ,
    \po_stg2_wrcal_cnt_reg[1]_29 ,
    \po_stg2_wrcal_cnt_reg[1]_30 ,
    \po_stg2_wrcal_cnt_reg[1]_31 ,
    \po_stg2_wrcal_cnt_reg[1]_32 ,
    \po_stg2_wrcal_cnt_reg[1]_33 ,
    \po_stg2_wrcal_cnt_reg[1]_34 ,
    \po_stg2_wrcal_cnt_reg[1]_35 ,
    \po_stg2_wrcal_cnt_reg[1]_36 ,
    \po_stg2_wrcal_cnt_reg[1]_37 ,
    \po_stg2_wrcal_cnt_reg[1]_38 ,
    \po_stg2_wrcal_cnt_reg[1]_39 ,
    \po_stg2_wrcal_cnt_reg[1]_40 ,
    \po_stg2_wrcal_cnt_reg[1]_41 ,
    \po_stg2_wrcal_cnt_reg[1]_42 ,
    \po_stg2_wrcal_cnt_reg[1]_43 ,
    \po_stg2_wrcal_cnt_reg[1]_44 ,
    \po_stg2_wrcal_cnt_reg[1]_45 ,
    \po_stg2_wrcal_cnt_reg[1]_46 ,
    \po_stg2_wrcal_cnt_reg[1]_47 ,
    \po_stg2_wrcal_cnt_reg[1]_48 ,
    \po_stg2_wrcal_cnt_reg[1]_49 ,
    \po_stg2_wrcal_cnt_reg[1]_50 ,
    \po_stg2_wrcal_cnt_reg[1]_51 ,
    \po_stg2_wrcal_cnt_reg[1]_52 ,
    \po_stg2_wrcal_cnt_reg[1]_53 ,
    \po_stg2_wrcal_cnt_reg[1]_54 ,
    \po_stg2_wrcal_cnt_reg[1]_55 ,
    \po_stg2_wrcal_cnt_reg[1]_56 ,
    \po_stg2_wrcal_cnt_reg[1]_57 ,
    \po_stg2_wrcal_cnt_reg[1]_58 ,
    \po_stg2_wrcal_cnt_reg[1]_59 ,
    \po_stg2_wrcal_cnt_reg[1]_60 ,
    \po_stg2_wrcal_cnt_reg[1]_61 ,
    \po_stg2_wrcal_cnt_reg[1]_62 ,
    \rd_ptr_reg[3] ,
    \rd_ptr_reg[3]_0 ,
    \rd_ptr_reg[3]_1 ,
    \rd_ptr_reg[3]_2 ,
    \po_counter_read_val_reg[8]_0 ,
    \pi_counter_read_val_reg[5]_0 ,
    \entry_cnt_reg[4] ,
    \input_[9].iserdes_dq_.iserdesdq ,
    mem_dq_in,
    idelay_inc,
    LD0,
    CLKB0,
    \pi_dqs_found_lanes_r1_reg[0] ,
    \pi_dqs_found_lanes_r1_reg[0]_0 ,
    \pi_dqs_found_lanes_r1_reg[0]_1 ,
    \pi_dqs_found_lanes_r1_reg[0]_2 ,
    freq_refclk,
    mem_refclk,
    mem_dqs_in,
    ififo_rst_reg,
    sync_pulse,
    COUNTERLOADVAL,
    \po_counter_read_val_reg[8]_1 ,
    \po_counter_read_val_reg[8]_2 ,
    \po_counter_read_val_reg[8]_3 ,
    \my_empty_reg[7] ,
    \my_empty_reg[7]_0 ,
    \my_empty_reg[7]_1 ,
    \my_empty_reg[7]_2 ,
    \my_empty_reg[7]_3 ,
    \my_empty_reg[7]_4 ,
    \my_empty_reg[7]_5 ,
    \my_empty_reg[7]_6 ,
    phy_if_reset,
    \input_[9].iserdes_dq_.iserdesdq_0 ,
    LD0_7,
    CLKB0_7,
    \pi_dqs_found_lanes_r1_reg[1] ,
    \pi_dqs_found_lanes_r1_reg[1]_0 ,
    \pi_dqs_found_lanes_r1_reg[1]_1 ,
    \pi_dqs_found_lanes_r1_reg[1]_2 ,
    ififo_rst_reg_0,
    \pi_dqs_found_lanes_r1_reg[1]_3 ,
    \po_counter_read_val_reg[8]_4 ,
    \po_counter_read_val_reg[8]_5 ,
    \po_counter_read_val_reg[8]_6 ,
    \my_empty_reg[7]_7 ,
    \my_empty_reg[7]_8 ,
    \my_empty_reg[7]_9 ,
    \my_empty_reg[7]_10 ,
    \my_empty_reg[7]_11 ,
    \my_empty_reg[7]_12 ,
    \my_empty_reg[7]_13 ,
    \my_empty_reg[7]_14 ,
    \input_[9].iserdes_dq_.iserdesdq_1 ,
    LD0_8,
    CLKB0_8,
    \pi_dqs_found_lanes_r1_reg[2] ,
    \pi_dqs_found_lanes_r1_reg[2]_0 ,
    \pi_dqs_found_lanes_r1_reg[2]_1 ,
    \pi_dqs_found_lanes_r1_reg[2]_2 ,
    ififo_rst_reg_1,
    \pi_dqs_found_lanes_r1_reg[2]_3 ,
    \po_counter_read_val_reg[8]_7 ,
    \po_counter_read_val_reg[8]_8 ,
    \po_counter_read_val_reg[8]_9 ,
    \my_empty_reg[7]_15 ,
    \my_empty_reg[7]_16 ,
    \my_empty_reg[7]_17 ,
    \my_empty_reg[7]_18 ,
    \my_empty_reg[7]_19 ,
    \my_empty_reg[7]_20 ,
    \my_empty_reg[7]_21 ,
    \my_empty_reg[7]_22 ,
    \input_[9].iserdes_dq_.iserdesdq_2 ,
    LD0_9,
    CLKB0_9,
    \pi_dqs_found_lanes_r1_reg[3] ,
    \pi_dqs_found_lanes_r1_reg[3]_0 ,
    \pi_dqs_found_lanes_r1_reg[3]_1 ,
    \pi_dqs_found_lanes_r1_reg[3]_2 ,
    ififo_rst_reg_2,
    \pi_dqs_found_lanes_r1_reg[3]_3 ,
    \po_counter_read_val_reg[8]_10 ,
    \po_counter_read_val_reg[8]_11 ,
    \po_counter_read_val_reg[8]_12 ,
    \my_empty_reg[7]_23 ,
    \my_empty_reg[7]_24 ,
    \my_empty_reg[7]_25 ,
    \my_empty_reg[7]_26 ,
    \my_empty_reg[7]_27 ,
    \my_empty_reg[7]_28 ,
    \my_empty_reg[7]_29 ,
    \my_empty_reg[7]_30 ,
    phy_ctl_mstr_empty,
    phy_ctl_wr_i2,
    pll_locked,
    phy_read_calib,
    phy_mc_ctl_full_r_reg,
    phy_write_calib,
    Q,
    RST0,
    rst_primitives_reg_0,
    rst_out_reg_1,
    SR,
    \rclk_delay_reg[11]_0 ,
    phy_if_empty_r_reg,
    if_empty_v,
    phy_data_wr_en,
    ofs_rdy_r_reg,
    ofs_rdy_r_reg_0,
    pi_phase_locked_all_r1_reg,
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0] ,
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ,
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ,
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ,
    \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_rise0_r_reg[5] ,
    \gen_mux_rd[6].mux_rd_rise0_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_rise0_r_reg[7] ,
    \gen_mux_rd[0].mux_rd_fall0_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1] ,
    \gen_mux_rd[2].mux_rd_fall0_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3] ,
    \gen_mux_rd[4].mux_rd_fall0_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5] ,
    \gen_mux_rd[6].mux_rd_fall0_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7] ,
    \gen_mux_rd[0].mux_rd_rise1_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1] ,
    \gen_mux_rd[2].mux_rd_rise1_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3] ,
    \gen_mux_rd[4].mux_rd_rise1_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5] ,
    \gen_mux_rd[6].mux_rd_rise1_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7] ,
    \gen_mux_rd[0].mux_rd_fall1_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1] ,
    \gen_mux_rd[2].mux_rd_fall1_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3] ,
    \gen_mux_rd[4].mux_rd_fall1_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5] ,
    \gen_mux_rd[6].mux_rd_fall1_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7] ,
    \gen_mux_rd[0].mux_rd_rise2_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1] ,
    \gen_mux_rd[2].mux_rd_rise2_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3] ,
    \gen_mux_rd[4].mux_rd_rise2_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5] ,
    \gen_mux_rd[6].mux_rd_rise2_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7] ,
    \gen_mux_rd[0].mux_rd_fall2_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1] ,
    \gen_mux_rd[2].mux_rd_fall2_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3] ,
    \gen_mux_rd[4].mux_rd_fall2_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5] ,
    \gen_mux_rd[6].mux_rd_fall2_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7] ,
    \gen_mux_rd[0].mux_rd_rise3_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1] ,
    \gen_mux_rd[2].mux_rd_rise3_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3] ,
    \gen_mux_rd[4].mux_rd_rise3_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5] ,
    \gen_mux_rd[6].mux_rd_rise3_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7] ,
    \gen_mux_rd[0].mux_rd_fall3_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1] ,
    \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3] ,
    \gen_mux_rd[4].mux_rd_fall3_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5] ,
    \gen_mux_rd[6].mux_rd_fall3_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7] ,
    out_fifo,
    out_fifo_0,
    out_fifo_1,
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ,
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1 ,
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ,
    \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0 ,
    \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0 ,
    \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0 ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ,
    \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0 ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ,
    \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0 ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ,
    \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0 ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ,
    \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0 ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ,
    \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0 ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ,
    \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0 ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ,
    \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0 ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ,
    \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0 ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ,
    \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0 ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ,
    \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0 ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ,
    \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0 ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ,
    \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0 ,
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ,
    \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ,
    \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0 ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ,
    \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0 ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ,
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1 ,
    \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0 ,
    \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0 ,
    \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0 ,
    \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0 ,
    \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0 ,
    \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0 ,
    \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0 ,
    \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0 ,
    \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0 ,
    \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0 ,
    \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0 ,
    \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0 ,
    \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0 ,
    \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0 ,
    \gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ,
    phy_dout,
    out_fifo_i_75__5,
    out_fifo_i_75__6,
    out_fifo_i_75__7,
    \my_full_reg[1] ,
    \my_full_reg[1]_0 ,
    \my_full_reg[1]_1 ,
    calib_sel);
  output out_dqs_4;
  output ts_dqs_4;
  output A_rst_primitives_reg_0;
  output [35:0]mem_dq_out;
  output [35:0]mem_dq_ts;
  output [3:0]in0;
  output idelay_ld_rst;
  output out_dqs_5;
  output ts_dqs_5;
  output A_rst_primitives_reg_1;
  output [0:0]if_empty_r;
  output [0:0]\my_empty_reg[4] ;
  output idelay_ld_rst_0;
  output out_dqs_6;
  output ts_dqs_6;
  output A_rst_primitives_reg_2;
  output [0:0]if_empty_r_0;
  output [0:0]\my_empty_reg[4]_0 ;
  output idelay_ld_rst_1;
  output out_dqs_7;
  output ts_dqs_7;
  output A_rst_primitives_reg_3;
  output idelay_ld_rst_2;
  output [0:0]_phy_ctl_full_p__0;
  output phy_ctl_wr_i2_reg;
  output [0:0]ref_dll_lock_w__0;
  output rst_primitives;
  output [0:0]mcGo_w;
  output rst_out_reg_0;
  output rclk_delay_11;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  output if_empty;
  output \my_empty_reg[1] ;
  output phy_mc_data_full;
  output \my_empty_reg[1]_0 ;
  output \my_empty_reg[1]_1 ;
  output \my_empty_reg[1]_2 ;
  output A_rst_primitives_reg_4;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1 ;
  output \rd_mux_sel_r_reg[2] ;
  output \rd_mux_sel_r_reg[2]_0 ;
  output \rd_mux_sel_r_reg[2]_1 ;
  output \rd_mux_sel_r_reg[2]_2 ;
  output \rd_mux_sel_r_reg[2]_3 ;
  output \rd_mux_sel_r_reg[2]_4 ;
  output \rd_mux_sel_r_reg[2]_5 ;
  output \rd_mux_sel_r_reg[2]_6 ;
  output \rd_mux_sel_r_reg[2]_7 ;
  output \rd_mux_sel_r_reg[2]_8 ;
  output \rd_mux_sel_r_reg[2]_9 ;
  output \rd_mux_sel_r_reg[2]_10 ;
  output \rd_mux_sel_r_reg[2]_11 ;
  output \rd_mux_sel_r_reg[2]_12 ;
  output \rd_mux_sel_r_reg[2]_13 ;
  output \rd_mux_sel_r_reg[2]_14 ;
  output \rd_mux_sel_r_reg[2]_15 ;
  output \rd_mux_sel_r_reg[2]_16 ;
  output \rd_mux_sel_r_reg[2]_17 ;
  output \rd_mux_sel_r_reg[2]_18 ;
  output \rd_mux_sel_r_reg[2]_19 ;
  output \rd_mux_sel_r_reg[2]_20 ;
  output \rd_mux_sel_r_reg[2]_21 ;
  output \rd_mux_sel_r_reg[2]_22 ;
  output \rd_mux_sel_r_reg[2]_23 ;
  output \rd_mux_sel_r_reg[2]_24 ;
  output \rd_mux_sel_r_reg[2]_25 ;
  output \rd_mux_sel_r_reg[2]_26 ;
  output \rd_mux_sel_r_reg[2]_27 ;
  output \rd_mux_sel_r_reg[2]_28 ;
  output \rd_mux_sel_r_reg[2]_29 ;
  output \rd_mux_sel_r_reg[2]_30 ;
  output \rd_mux_sel_r_reg[2]_31 ;
  output \rd_mux_sel_r_reg[2]_32 ;
  output \rd_mux_sel_r_reg[2]_33 ;
  output \rd_mux_sel_r_reg[2]_34 ;
  output \rd_mux_sel_r_reg[2]_35 ;
  output \rd_mux_sel_r_reg[2]_36 ;
  output \rd_mux_sel_r_reg[2]_37 ;
  output \rd_mux_sel_r_reg[2]_38 ;
  output \rd_mux_sel_r_reg[2]_39 ;
  output \rd_mux_sel_r_reg[2]_40 ;
  output \rd_mux_sel_r_reg[2]_41 ;
  output \rd_mux_sel_r_reg[2]_42 ;
  output \rd_mux_sel_r_reg[2]_43 ;
  output \rd_mux_sel_r_reg[2]_44 ;
  output \rd_mux_sel_r_reg[2]_45 ;
  output \rd_mux_sel_r_reg[2]_46 ;
  output \rd_mux_sel_r_reg[2]_47 ;
  output \rd_mux_sel_r_reg[2]_48 ;
  output \rd_mux_sel_r_reg[2]_49 ;
  output \rd_mux_sel_r_reg[2]_50 ;
  output \rd_mux_sel_r_reg[2]_51 ;
  output \rd_mux_sel_r_reg[2]_52 ;
  output \rd_mux_sel_r_reg[2]_53 ;
  output \rd_mux_sel_r_reg[2]_54 ;
  output \rd_mux_sel_r_reg[2]_55 ;
  output \rd_mux_sel_r_reg[2]_56 ;
  output \rd_mux_sel_r_reg[2]_57 ;
  output \rd_mux_sel_r_reg[2]_58 ;
  output \rd_mux_sel_r_reg[2]_59 ;
  output \rd_mux_sel_r_reg[2]_60 ;
  output \rd_mux_sel_r_reg[2]_61 ;
  output \rd_mux_sel_r_reg[2]_62 ;
  output phy_rddata_en;
  output \rd_mux_sel_r_reg[1] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ;
  output \rd_mux_sel_r_reg[1]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ;
  output \rd_mux_sel_r_reg[1]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ;
  output \rd_mux_sel_r_reg[1]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ;
  output \rd_mux_sel_r_reg[1]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ;
  output \rd_mux_sel_r_reg[1]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ;
  output \rd_mux_sel_r_reg[1]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ;
  output \rd_mux_sel_r_reg[1]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_2 ;
  output \rd_mux_sel_r_reg[1]_7 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2 ;
  output \rd_mux_sel_r_reg[1]_8 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2 ;
  output \rd_mux_sel_r_reg[1]_9 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2 ;
  output \rd_mux_sel_r_reg[1]_10 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2 ;
  output \rd_mux_sel_r_reg[1]_11 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2 ;
  output \rd_mux_sel_r_reg[1]_12 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2 ;
  output \rd_mux_sel_r_reg[1]_13 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ;
  output \rd_mux_sel_r_reg[1]_14 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_2 ;
  output \rd_mux_sel_r_reg[1]_15 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2 ;
  output \rd_mux_sel_r_reg[1]_16 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2 ;
  output \rd_mux_sel_r_reg[1]_17 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2 ;
  output \rd_mux_sel_r_reg[1]_18 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2 ;
  output \rd_mux_sel_r_reg[1]_19 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2 ;
  output \rd_mux_sel_r_reg[1]_20 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2 ;
  output \rd_mux_sel_r_reg[1]_21 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ;
  output \rd_mux_sel_r_reg[1]_22 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_2 ;
  output \rd_mux_sel_r_reg[1]_23 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2 ;
  output \rd_mux_sel_r_reg[1]_24 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2 ;
  output \rd_mux_sel_r_reg[1]_25 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2 ;
  output \rd_mux_sel_r_reg[1]_26 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2 ;
  output \rd_mux_sel_r_reg[1]_27 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2 ;
  output \rd_mux_sel_r_reg[1]_28 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2 ;
  output \rd_mux_sel_r_reg[1]_29 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ;
  output \rd_mux_sel_r_reg[1]_30 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_2 ;
  output \rd_mux_sel_r_reg[1]_31 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2 ;
  output \rd_mux_sel_r_reg[1]_32 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2 ;
  output \rd_mux_sel_r_reg[1]_33 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2 ;
  output \rd_mux_sel_r_reg[1]_34 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2 ;
  output \rd_mux_sel_r_reg[1]_35 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2 ;
  output \rd_mux_sel_r_reg[1]_36 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2 ;
  output \rd_mux_sel_r_reg[1]_37 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ;
  output \rd_mux_sel_r_reg[1]_38 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_2 ;
  output \rd_mux_sel_r_reg[1]_39 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2 ;
  output \rd_mux_sel_r_reg[1]_40 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2 ;
  output \rd_mux_sel_r_reg[1]_41 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2 ;
  output \rd_mux_sel_r_reg[1]_42 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2 ;
  output \rd_mux_sel_r_reg[1]_43 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2 ;
  output \rd_mux_sel_r_reg[1]_44 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2 ;
  output \rd_mux_sel_r_reg[1]_45 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ;
  output \rd_mux_sel_r_reg[1]_46 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_2 ;
  output \rd_mux_sel_r_reg[1]_47 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2 ;
  output \rd_mux_sel_r_reg[1]_48 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2 ;
  output \rd_mux_sel_r_reg[1]_49 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2 ;
  output \rd_mux_sel_r_reg[1]_50 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2 ;
  output \rd_mux_sel_r_reg[1]_51 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2 ;
  output \rd_mux_sel_r_reg[1]_52 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2 ;
  output \rd_mux_sel_r_reg[1]_53 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ;
  output \rd_mux_sel_r_reg[1]_54 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_2 ;
  output \rd_mux_sel_r_reg[1]_55 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2 ;
  output \rd_mux_sel_r_reg[1]_56 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2 ;
  output \rd_mux_sel_r_reg[1]_57 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2 ;
  output \rd_mux_sel_r_reg[1]_58 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2 ;
  output \rd_mux_sel_r_reg[1]_59 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2 ;
  output \rd_mux_sel_r_reg[1]_60 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2 ;
  output \rd_mux_sel_r_reg[1]_61 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ;
  output \rd_mux_sel_r_reg[1]_62 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2 ;
  output \po_stg2_wrcal_cnt_reg[1] ;
  output \po_stg2_wrcal_cnt_reg[1]_0 ;
  output \po_stg2_wrcal_cnt_reg[1]_1 ;
  output \po_stg2_wrcal_cnt_reg[1]_2 ;
  output \po_stg2_wrcal_cnt_reg[1]_3 ;
  output \po_stg2_wrcal_cnt_reg[1]_4 ;
  output \po_stg2_wrcal_cnt_reg[1]_5 ;
  output \po_stg2_wrcal_cnt_reg[1]_6 ;
  output \po_stg2_wrcal_cnt_reg[1]_7 ;
  output \po_stg2_wrcal_cnt_reg[1]_8 ;
  output \po_stg2_wrcal_cnt_reg[1]_9 ;
  output \po_stg2_wrcal_cnt_reg[1]_10 ;
  output \po_stg2_wrcal_cnt_reg[1]_11 ;
  output \po_stg2_wrcal_cnt_reg[1]_12 ;
  output \po_stg2_wrcal_cnt_reg[1]_13 ;
  output \po_stg2_wrcal_cnt_reg[1]_14 ;
  output \po_stg2_wrcal_cnt_reg[1]_15 ;
  output \po_stg2_wrcal_cnt_reg[1]_16 ;
  output \po_stg2_wrcal_cnt_reg[1]_17 ;
  output \po_stg2_wrcal_cnt_reg[1]_18 ;
  output \po_stg2_wrcal_cnt_reg[1]_19 ;
  output \po_stg2_wrcal_cnt_reg[1]_20 ;
  output \po_stg2_wrcal_cnt_reg[1]_21 ;
  output \po_stg2_wrcal_cnt_reg[1]_22 ;
  output \po_stg2_wrcal_cnt_reg[1]_23 ;
  output \po_stg2_wrcal_cnt_reg[1]_24 ;
  output \po_stg2_wrcal_cnt_reg[1]_25 ;
  output \po_stg2_wrcal_cnt_reg[1]_26 ;
  output \po_stg2_wrcal_cnt_reg[1]_27 ;
  output \po_stg2_wrcal_cnt_reg[1]_28 ;
  output \po_stg2_wrcal_cnt_reg[1]_29 ;
  output \po_stg2_wrcal_cnt_reg[1]_30 ;
  output \po_stg2_wrcal_cnt_reg[1]_31 ;
  output \po_stg2_wrcal_cnt_reg[1]_32 ;
  output \po_stg2_wrcal_cnt_reg[1]_33 ;
  output \po_stg2_wrcal_cnt_reg[1]_34 ;
  output \po_stg2_wrcal_cnt_reg[1]_35 ;
  output \po_stg2_wrcal_cnt_reg[1]_36 ;
  output \po_stg2_wrcal_cnt_reg[1]_37 ;
  output \po_stg2_wrcal_cnt_reg[1]_38 ;
  output \po_stg2_wrcal_cnt_reg[1]_39 ;
  output \po_stg2_wrcal_cnt_reg[1]_40 ;
  output \po_stg2_wrcal_cnt_reg[1]_41 ;
  output \po_stg2_wrcal_cnt_reg[1]_42 ;
  output \po_stg2_wrcal_cnt_reg[1]_43 ;
  output \po_stg2_wrcal_cnt_reg[1]_44 ;
  output \po_stg2_wrcal_cnt_reg[1]_45 ;
  output \po_stg2_wrcal_cnt_reg[1]_46 ;
  output \po_stg2_wrcal_cnt_reg[1]_47 ;
  output \po_stg2_wrcal_cnt_reg[1]_48 ;
  output \po_stg2_wrcal_cnt_reg[1]_49 ;
  output \po_stg2_wrcal_cnt_reg[1]_50 ;
  output \po_stg2_wrcal_cnt_reg[1]_51 ;
  output \po_stg2_wrcal_cnt_reg[1]_52 ;
  output \po_stg2_wrcal_cnt_reg[1]_53 ;
  output \po_stg2_wrcal_cnt_reg[1]_54 ;
  output \po_stg2_wrcal_cnt_reg[1]_55 ;
  output \po_stg2_wrcal_cnt_reg[1]_56 ;
  output \po_stg2_wrcal_cnt_reg[1]_57 ;
  output \po_stg2_wrcal_cnt_reg[1]_58 ;
  output \po_stg2_wrcal_cnt_reg[1]_59 ;
  output \po_stg2_wrcal_cnt_reg[1]_60 ;
  output \po_stg2_wrcal_cnt_reg[1]_61 ;
  output \po_stg2_wrcal_cnt_reg[1]_62 ;
  output [63:0]\rd_ptr_reg[3] ;
  output [63:0]\rd_ptr_reg[3]_0 ;
  output [63:0]\rd_ptr_reg[3]_1 ;
  output [63:0]\rd_ptr_reg[3]_2 ;
  output [8:0]\po_counter_read_val_reg[8]_0 ;
  output [5:0]\pi_counter_read_val_reg[5]_0 ;
  input \entry_cnt_reg[4] ;
  input \input_[9].iserdes_dq_.iserdesdq ;
  input [31:0]mem_dq_in;
  input idelay_inc;
  input LD0;
  input CLKB0;
  input \pi_dqs_found_lanes_r1_reg[0] ;
  input \pi_dqs_found_lanes_r1_reg[0]_0 ;
  input \pi_dqs_found_lanes_r1_reg[0]_1 ;
  input \pi_dqs_found_lanes_r1_reg[0]_2 ;
  input freq_refclk;
  input mem_refclk;
  input [3:0]mem_dqs_in;
  input ififo_rst_reg;
  input sync_pulse;
  input [5:0]COUNTERLOADVAL;
  input \po_counter_read_val_reg[8]_1 ;
  input \po_counter_read_val_reg[8]_2 ;
  input \po_counter_read_val_reg[8]_3 ;
  input [7:0]\my_empty_reg[7] ;
  input [7:0]\my_empty_reg[7]_0 ;
  input [7:0]\my_empty_reg[7]_1 ;
  input [7:0]\my_empty_reg[7]_2 ;
  input [7:0]\my_empty_reg[7]_3 ;
  input [7:0]\my_empty_reg[7]_4 ;
  input [7:0]\my_empty_reg[7]_5 ;
  input [7:0]\my_empty_reg[7]_6 ;
  input phy_if_reset;
  input \input_[9].iserdes_dq_.iserdesdq_0 ;
  input LD0_7;
  input CLKB0_7;
  input \pi_dqs_found_lanes_r1_reg[1] ;
  input \pi_dqs_found_lanes_r1_reg[1]_0 ;
  input \pi_dqs_found_lanes_r1_reg[1]_1 ;
  input \pi_dqs_found_lanes_r1_reg[1]_2 ;
  input ififo_rst_reg_0;
  input [5:0]\pi_dqs_found_lanes_r1_reg[1]_3 ;
  input \po_counter_read_val_reg[8]_4 ;
  input \po_counter_read_val_reg[8]_5 ;
  input \po_counter_read_val_reg[8]_6 ;
  input [7:0]\my_empty_reg[7]_7 ;
  input [7:0]\my_empty_reg[7]_8 ;
  input [7:0]\my_empty_reg[7]_9 ;
  input [7:0]\my_empty_reg[7]_10 ;
  input [7:0]\my_empty_reg[7]_11 ;
  input [7:0]\my_empty_reg[7]_12 ;
  input [7:0]\my_empty_reg[7]_13 ;
  input [7:0]\my_empty_reg[7]_14 ;
  input \input_[9].iserdes_dq_.iserdesdq_1 ;
  input LD0_8;
  input CLKB0_8;
  input \pi_dqs_found_lanes_r1_reg[2] ;
  input \pi_dqs_found_lanes_r1_reg[2]_0 ;
  input \pi_dqs_found_lanes_r1_reg[2]_1 ;
  input \pi_dqs_found_lanes_r1_reg[2]_2 ;
  input ififo_rst_reg_1;
  input [5:0]\pi_dqs_found_lanes_r1_reg[2]_3 ;
  input \po_counter_read_val_reg[8]_7 ;
  input \po_counter_read_val_reg[8]_8 ;
  input \po_counter_read_val_reg[8]_9 ;
  input [7:0]\my_empty_reg[7]_15 ;
  input [7:0]\my_empty_reg[7]_16 ;
  input [7:0]\my_empty_reg[7]_17 ;
  input [7:0]\my_empty_reg[7]_18 ;
  input [7:0]\my_empty_reg[7]_19 ;
  input [7:0]\my_empty_reg[7]_20 ;
  input [7:0]\my_empty_reg[7]_21 ;
  input [7:0]\my_empty_reg[7]_22 ;
  input \input_[9].iserdes_dq_.iserdesdq_2 ;
  input LD0_9;
  input CLKB0_9;
  input \pi_dqs_found_lanes_r1_reg[3] ;
  input \pi_dqs_found_lanes_r1_reg[3]_0 ;
  input \pi_dqs_found_lanes_r1_reg[3]_1 ;
  input \pi_dqs_found_lanes_r1_reg[3]_2 ;
  input ififo_rst_reg_2;
  input [5:0]\pi_dqs_found_lanes_r1_reg[3]_3 ;
  input \po_counter_read_val_reg[8]_10 ;
  input \po_counter_read_val_reg[8]_11 ;
  input \po_counter_read_val_reg[8]_12 ;
  input [7:0]\my_empty_reg[7]_23 ;
  input [7:0]\my_empty_reg[7]_24 ;
  input [7:0]\my_empty_reg[7]_25 ;
  input [7:0]\my_empty_reg[7]_26 ;
  input [7:0]\my_empty_reg[7]_27 ;
  input [7:0]\my_empty_reg[7]_28 ;
  input [7:0]\my_empty_reg[7]_29 ;
  input [7:0]\my_empty_reg[7]_30 ;
  input phy_ctl_mstr_empty;
  input phy_ctl_wr_i2;
  input pll_locked;
  input phy_read_calib;
  input phy_mc_ctl_full_r_reg;
  input phy_write_calib;
  input [10:0]Q;
  input RST0;
  input rst_primitives_reg_0;
  input rst_out_reg_1;
  input [0:0]SR;
  input \rclk_delay_reg[11]_0 ;
  input phy_if_empty_r_reg;
  input [0:0]if_empty_v;
  input phy_data_wr_en;
  input ofs_rdy_r_reg;
  input ofs_rdy_r_reg_0;
  input pi_phase_locked_all_r1_reg;
  input [1:0]\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;
  input \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ;
  input \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;
  input \gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;
  input \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  input \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;
  input \gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;
  input \gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;
  input \gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;
  input \gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;
  input \gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  input \gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;
  input \gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  input \gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;
  input \gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  input \gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;
  input \gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  input \gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;
  input \gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  input \gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;
  input \gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  input \gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;
  input \gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  input \gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;
  input \gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  input \gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;
  input \gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  input \gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;
  input \gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  input \gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;
  input \gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  input \gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;
  input \gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  input \gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;
  input \gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  input \gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;
  input \gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  input \gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;
  input \gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  input \gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;
  input \gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  input \gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;
  input \gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  input \gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;
  input \gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  input \gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;
  input \gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  input \gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;
  input \gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  input \gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;
  input \gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  input \gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;
  input \gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  input \gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;
  input \gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  input \gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;
  input \gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  input \gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;
  input \gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  input \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  input \gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  input \gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;
  input \gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  input \gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;
  input \gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  input out_fifo;
  input [31:0]out_fifo_0;
  input out_fifo_1;
  input \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ;
  input \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1 ;
  input \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ;
  input \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ;
  input \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0 ;
  input \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0 ;
  input \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0 ;
  input \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ;
  input \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ;
  input \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ;
  input \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0 ;
  input \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ;
  input \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0 ;
  input \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ;
  input \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ;
  input \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ;
  input \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0 ;
  input \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ;
  input \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ;
  input \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ;
  input \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ;
  input \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0 ;
  input \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ;
  input \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0 ;
  input \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ;
  input \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0 ;
  input \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ;
  input \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ;
  input \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0 ;
  input \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ;
  input \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ;
  input \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0 ;
  input \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ;
  input \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ;
  input \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0 ;
  input \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ;
  input \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ;
  input \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0 ;
  input \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ;
  input \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ;
  input \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0 ;
  input \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ;
  input \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0 ;
  input \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ;
  input \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 ;
  input \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ;
  input \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0 ;
  input \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ;
  input \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0 ;
  input \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ;
  input \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1 ;
  input \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0 ;
  input \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0 ;
  input \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0 ;
  input \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0 ;
  input \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0 ;
  input \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0 ;
  input \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0 ;
  input \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0 ;
  input \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0 ;
  input \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0 ;
  input \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0 ;
  input \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0 ;
  input \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0 ;
  input \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0 ;
  input [1:0]\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ;
  input [1:0]\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;
  input [71:0]phy_dout;
  input [71:0]out_fifo_i_75__5;
  input [71:0]out_fifo_i_75__6;
  input [71:0]out_fifo_i_75__7;
  input \my_full_reg[1] ;
  input \my_full_reg[1]_0 ;
  input \my_full_reg[1]_1 ;
  input [1:0]calib_sel;

  wire [5:0]A_pi_counter_read_val;
  (* async_reg = "true" *) wire A_pi_rst_div2;
  wire [8:0]A_po_counter_read_val;
  wire A_rst_primitives;
  wire A_rst_primitives_reg_0;
  wire A_rst_primitives_reg_1;
  wire A_rst_primitives_reg_2;
  wire A_rst_primitives_reg_3;
  wire A_rst_primitives_reg_4;
  (* async_reg = "true" *) wire B_pi_rst_div2;
  wire B_rclk;
  wire CLKB0;
  wire CLKB0_7;
  wire CLKB0_8;
  wire CLKB0_9;
  wire [5:0]COUNTERLOADVAL;
  wire [5:0]C_pi_counter_read_val;
  (* async_reg = "true" *) wire C_pi_rst_div2;
  wire [8:0]C_po_counter_read_val;
  wire [5:0]D_pi_counter_read_val;
  (* async_reg = "true" *) wire D_pi_rst_div2;
  wire [8:0]D_po_counter_read_val;
  wire LD0;
  wire LD0_7;
  wire LD0_8;
  wire LD0_9;
  wire [10:0]Q;
  wire RST0;
  wire [0:0]SR;
  wire [0:0]_phy_ctl_full_p__0;
  wire [1:0]calib_sel;
  wire \ddr_byte_lane_A.ddr_byte_lane_A_n_22 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A_n_40 ;
  wire \ddr_byte_lane_A.ddr_byte_lane_A_n_44 ;
  wire \ddr_byte_lane_B.ddr_byte_lane_B_n_158 ;
  wire \ddr_byte_lane_B.ddr_byte_lane_B_n_22 ;
  wire \ddr_byte_lane_B.ddr_byte_lane_B_n_223 ;
  wire \ddr_byte_lane_B.ddr_byte_lane_B_n_224 ;
  wire \ddr_byte_lane_B.ddr_byte_lane_B_n_225 ;
  wire \ddr_byte_lane_B.ddr_byte_lane_B_n_226 ;
  wire \ddr_byte_lane_B.ddr_byte_lane_B_n_227 ;
  wire \ddr_byte_lane_B.ddr_byte_lane_B_n_228 ;
  wire \ddr_byte_lane_B.ddr_byte_lane_B_n_229 ;
  wire \ddr_byte_lane_B.ddr_byte_lane_B_n_230 ;
  wire \ddr_byte_lane_B.ddr_byte_lane_B_n_231 ;
  wire \ddr_byte_lane_B.ddr_byte_lane_B_n_232 ;
  wire \ddr_byte_lane_B.ddr_byte_lane_B_n_233 ;
  wire \ddr_byte_lane_B.ddr_byte_lane_B_n_234 ;
  wire \ddr_byte_lane_B.ddr_byte_lane_B_n_235 ;
  wire \ddr_byte_lane_B.ddr_byte_lane_B_n_236 ;
  wire \ddr_byte_lane_B.ddr_byte_lane_B_n_237 ;
  wire \ddr_byte_lane_B.ddr_byte_lane_B_n_28 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C_n_109 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D_n_22 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D_n_236 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D_n_237 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D_n_238 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D_n_239 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ;
  wire [3:3]\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ;
  wire [3:3]\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_2 ;
  wire [3:0]\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_4 ;
  wire \entry_cnt_reg[4] ;
  wire freq_refclk;
  wire \gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0 ;
  wire \gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0 ;
  wire \gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0 ;
  wire \gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0 ;
  wire [1:0]\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ;
  wire [1:0]\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ;
  wire \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1 ;
  wire \gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0 ;
  wire \gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0 ;
  wire \gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0 ;
  wire \gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1 ;
  wire \gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ;
  wire \gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0 ;
  wire \gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0 ;
  wire \gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0 ;
  wire \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 ;
  wire \gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ;
  wire \gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0 ;
  wire \gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0 ;
  wire \gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0 ;
  wire \gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ;
  wire \gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0 ;
  wire \gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0 ;
  wire \gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0 ;
  wire \gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0 ;
  wire \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0 ;
  wire \gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0 ;
  wire \gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0 ;
  wire \gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0 ;
  wire \gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ;
  wire \gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0 ;
  wire \gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0 ;
  wire \gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0 ;
  wire \gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0 ;
  wire \gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0 ;
  wire \gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0 ;
  wire \gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0 ;
  wire \gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0 ;
  wire \gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ;
  wire [1:0]\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;
  wire idelay_inc;
  wire idelay_ld_rst;
  wire idelay_ld_rst_0;
  wire idelay_ld_rst_1;
  wire idelay_ld_rst_2;
  wire if_empty;
  wire [0:0]if_empty_r;
  wire [0:0]if_empty_r_0;
  wire [3:3]if_empty_r_5;
  wire [0:0]if_empty_v;
  wire ififo_rst_reg;
  wire ififo_rst_reg_0;
  wire ififo_rst_reg_1;
  wire ififo_rst_reg_2;
  wire [3:0]in0;
  wire \input_[9].iserdes_dq_.iserdesdq ;
  wire \input_[9].iserdes_dq_.iserdesdq_0 ;
  wire \input_[9].iserdes_dq_.iserdesdq_1 ;
  wire \input_[9].iserdes_dq_.iserdesdq_2 ;
  wire [0:0]mcGo_w;
  wire [31:0]mem_dq_in;
  wire [35:0]mem_dq_out;
  wire [35:0]mem_dq_ts;
  wire [3:0]mem_dqs_in;
  wire mem_refclk;
  wire \my_empty_reg[1] ;
  wire \my_empty_reg[1]_0 ;
  wire \my_empty_reg[1]_1 ;
  wire \my_empty_reg[1]_2 ;
  wire [0:0]\my_empty_reg[4] ;
  wire [0:0]\my_empty_reg[4]_0 ;
  wire [7:0]\my_empty_reg[7] ;
  wire [7:0]\my_empty_reg[7]_0 ;
  wire [7:0]\my_empty_reg[7]_1 ;
  wire [7:0]\my_empty_reg[7]_10 ;
  wire [7:0]\my_empty_reg[7]_11 ;
  wire [7:0]\my_empty_reg[7]_12 ;
  wire [7:0]\my_empty_reg[7]_13 ;
  wire [7:0]\my_empty_reg[7]_14 ;
  wire [7:0]\my_empty_reg[7]_15 ;
  wire [7:0]\my_empty_reg[7]_16 ;
  wire [7:0]\my_empty_reg[7]_17 ;
  wire [7:0]\my_empty_reg[7]_18 ;
  wire [7:0]\my_empty_reg[7]_19 ;
  wire [7:0]\my_empty_reg[7]_2 ;
  wire [7:0]\my_empty_reg[7]_20 ;
  wire [7:0]\my_empty_reg[7]_21 ;
  wire [7:0]\my_empty_reg[7]_22 ;
  wire [7:0]\my_empty_reg[7]_23 ;
  wire [7:0]\my_empty_reg[7]_24 ;
  wire [7:0]\my_empty_reg[7]_25 ;
  wire [7:0]\my_empty_reg[7]_26 ;
  wire [7:0]\my_empty_reg[7]_27 ;
  wire [7:0]\my_empty_reg[7]_28 ;
  wire [7:0]\my_empty_reg[7]_29 ;
  wire [7:0]\my_empty_reg[7]_3 ;
  wire [7:0]\my_empty_reg[7]_30 ;
  wire [7:0]\my_empty_reg[7]_4 ;
  wire [7:0]\my_empty_reg[7]_5 ;
  wire [7:0]\my_empty_reg[7]_6 ;
  wire [7:0]\my_empty_reg[7]_7 ;
  wire [7:0]\my_empty_reg[7]_8 ;
  wire [7:0]\my_empty_reg[7]_9 ;
  wire \my_full_reg[1] ;
  wire \my_full_reg[1]_0 ;
  wire \my_full_reg[1]_1 ;
  wire [4:2]\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg ;
  wire [4:2]\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_0 ;
  wire [4:2]\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_1 ;
  wire [4:2]\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_3 ;
  wire ofs_rdy_r_i_3_n_0;
  wire ofs_rdy_r_i_4_n_0;
  wire ofs_rdy_r_reg;
  wire ofs_rdy_r_reg_0;
  wire out_dqs_4;
  wire out_dqs_5;
  wire out_dqs_6;
  wire out_dqs_7;
  wire out_fifo;
  wire [31:0]out_fifo_0;
  wire out_fifo_1;
  wire [71:0]out_fifo_i_75__5;
  wire [71:0]out_fifo_i_75__6;
  wire [71:0]out_fifo_i_75__7;
  wire [15:0]phaser_ctl_bus;
  wire phy_control_i_n_0;
  wire phy_control_i_n_1;
  wire phy_control_i_n_14;
  wire phy_control_i_n_15;
  wire phy_control_i_n_16;
  wire phy_control_i_n_17;
  wire phy_ctl_mstr_empty;
  wire phy_ctl_wr_i2;
  wire phy_ctl_wr_i2_reg;
  wire phy_data_wr_en;
  wire [71:0]phy_dout;
  wire [1:0]phy_encalib;
  wire phy_if_empty_r_reg;
  wire phy_if_reset;
  wire phy_mc_ctl_full_r_reg;
  wire phy_mc_data_full;
  wire phy_rddata_en;
  wire phy_read_calib;
  wire phy_write_calib;
  wire [5:0]\pi_counter_read_val_reg[5]_0 ;
  wire \pi_dqs_found_lanes_r1_reg[0] ;
  wire \pi_dqs_found_lanes_r1_reg[0]_0 ;
  wire \pi_dqs_found_lanes_r1_reg[0]_1 ;
  wire \pi_dqs_found_lanes_r1_reg[0]_2 ;
  wire \pi_dqs_found_lanes_r1_reg[1] ;
  wire \pi_dqs_found_lanes_r1_reg[1]_0 ;
  wire \pi_dqs_found_lanes_r1_reg[1]_1 ;
  wire \pi_dqs_found_lanes_r1_reg[1]_2 ;
  wire [5:0]\pi_dqs_found_lanes_r1_reg[1]_3 ;
  wire \pi_dqs_found_lanes_r1_reg[2] ;
  wire \pi_dqs_found_lanes_r1_reg[2]_0 ;
  wire \pi_dqs_found_lanes_r1_reg[2]_1 ;
  wire \pi_dqs_found_lanes_r1_reg[2]_2 ;
  wire [5:0]\pi_dqs_found_lanes_r1_reg[2]_3 ;
  wire \pi_dqs_found_lanes_r1_reg[3] ;
  wire \pi_dqs_found_lanes_r1_reg[3]_0 ;
  wire \pi_dqs_found_lanes_r1_reg[3]_1 ;
  wire \pi_dqs_found_lanes_r1_reg[3]_2 ;
  wire [5:0]\pi_dqs_found_lanes_r1_reg[3]_3 ;
  wire pi_phase_locked_all_r1_reg;
  wire pll_locked;
  wire [8:0]\po_counter_read_val_reg[8]_0 ;
  wire \po_counter_read_val_reg[8]_1 ;
  wire \po_counter_read_val_reg[8]_10 ;
  wire \po_counter_read_val_reg[8]_11 ;
  wire \po_counter_read_val_reg[8]_12 ;
  wire \po_counter_read_val_reg[8]_2 ;
  wire \po_counter_read_val_reg[8]_3 ;
  wire \po_counter_read_val_reg[8]_4 ;
  wire \po_counter_read_val_reg[8]_5 ;
  wire \po_counter_read_val_reg[8]_6 ;
  wire \po_counter_read_val_reg[8]_7 ;
  wire \po_counter_read_val_reg[8]_8 ;
  wire \po_counter_read_val_reg[8]_9 ;
  wire \po_stg2_wrcal_cnt_reg[1] ;
  wire \po_stg2_wrcal_cnt_reg[1]_0 ;
  wire \po_stg2_wrcal_cnt_reg[1]_1 ;
  wire \po_stg2_wrcal_cnt_reg[1]_10 ;
  wire \po_stg2_wrcal_cnt_reg[1]_11 ;
  wire \po_stg2_wrcal_cnt_reg[1]_12 ;
  wire \po_stg2_wrcal_cnt_reg[1]_13 ;
  wire \po_stg2_wrcal_cnt_reg[1]_14 ;
  wire \po_stg2_wrcal_cnt_reg[1]_15 ;
  wire \po_stg2_wrcal_cnt_reg[1]_16 ;
  wire \po_stg2_wrcal_cnt_reg[1]_17 ;
  wire \po_stg2_wrcal_cnt_reg[1]_18 ;
  wire \po_stg2_wrcal_cnt_reg[1]_19 ;
  wire \po_stg2_wrcal_cnt_reg[1]_2 ;
  wire \po_stg2_wrcal_cnt_reg[1]_20 ;
  wire \po_stg2_wrcal_cnt_reg[1]_21 ;
  wire \po_stg2_wrcal_cnt_reg[1]_22 ;
  wire \po_stg2_wrcal_cnt_reg[1]_23 ;
  wire \po_stg2_wrcal_cnt_reg[1]_24 ;
  wire \po_stg2_wrcal_cnt_reg[1]_25 ;
  wire \po_stg2_wrcal_cnt_reg[1]_26 ;
  wire \po_stg2_wrcal_cnt_reg[1]_27 ;
  wire \po_stg2_wrcal_cnt_reg[1]_28 ;
  wire \po_stg2_wrcal_cnt_reg[1]_29 ;
  wire \po_stg2_wrcal_cnt_reg[1]_3 ;
  wire \po_stg2_wrcal_cnt_reg[1]_30 ;
  wire \po_stg2_wrcal_cnt_reg[1]_31 ;
  wire \po_stg2_wrcal_cnt_reg[1]_32 ;
  wire \po_stg2_wrcal_cnt_reg[1]_33 ;
  wire \po_stg2_wrcal_cnt_reg[1]_34 ;
  wire \po_stg2_wrcal_cnt_reg[1]_35 ;
  wire \po_stg2_wrcal_cnt_reg[1]_36 ;
  wire \po_stg2_wrcal_cnt_reg[1]_37 ;
  wire \po_stg2_wrcal_cnt_reg[1]_38 ;
  wire \po_stg2_wrcal_cnt_reg[1]_39 ;
  wire \po_stg2_wrcal_cnt_reg[1]_4 ;
  wire \po_stg2_wrcal_cnt_reg[1]_40 ;
  wire \po_stg2_wrcal_cnt_reg[1]_41 ;
  wire \po_stg2_wrcal_cnt_reg[1]_42 ;
  wire \po_stg2_wrcal_cnt_reg[1]_43 ;
  wire \po_stg2_wrcal_cnt_reg[1]_44 ;
  wire \po_stg2_wrcal_cnt_reg[1]_45 ;
  wire \po_stg2_wrcal_cnt_reg[1]_46 ;
  wire \po_stg2_wrcal_cnt_reg[1]_47 ;
  wire \po_stg2_wrcal_cnt_reg[1]_48 ;
  wire \po_stg2_wrcal_cnt_reg[1]_49 ;
  wire \po_stg2_wrcal_cnt_reg[1]_5 ;
  wire \po_stg2_wrcal_cnt_reg[1]_50 ;
  wire \po_stg2_wrcal_cnt_reg[1]_51 ;
  wire \po_stg2_wrcal_cnt_reg[1]_52 ;
  wire \po_stg2_wrcal_cnt_reg[1]_53 ;
  wire \po_stg2_wrcal_cnt_reg[1]_54 ;
  wire \po_stg2_wrcal_cnt_reg[1]_55 ;
  wire \po_stg2_wrcal_cnt_reg[1]_56 ;
  wire \po_stg2_wrcal_cnt_reg[1]_57 ;
  wire \po_stg2_wrcal_cnt_reg[1]_58 ;
  wire \po_stg2_wrcal_cnt_reg[1]_59 ;
  wire \po_stg2_wrcal_cnt_reg[1]_6 ;
  wire \po_stg2_wrcal_cnt_reg[1]_60 ;
  wire \po_stg2_wrcal_cnt_reg[1]_61 ;
  wire \po_stg2_wrcal_cnt_reg[1]_62 ;
  wire \po_stg2_wrcal_cnt_reg[1]_7 ;
  wire \po_stg2_wrcal_cnt_reg[1]_8 ;
  wire \po_stg2_wrcal_cnt_reg[1]_9 ;
  wire rclk_delay_11;
  wire \rclk_delay_reg[10]_srl11_n_0 ;
  wire \rclk_delay_reg[11]_0 ;
  wire \rd_mux_sel_r_reg[1] ;
  wire \rd_mux_sel_r_reg[1]_0 ;
  wire \rd_mux_sel_r_reg[1]_1 ;
  wire \rd_mux_sel_r_reg[1]_10 ;
  wire \rd_mux_sel_r_reg[1]_11 ;
  wire \rd_mux_sel_r_reg[1]_12 ;
  wire \rd_mux_sel_r_reg[1]_13 ;
  wire \rd_mux_sel_r_reg[1]_14 ;
  wire \rd_mux_sel_r_reg[1]_15 ;
  wire \rd_mux_sel_r_reg[1]_16 ;
  wire \rd_mux_sel_r_reg[1]_17 ;
  wire \rd_mux_sel_r_reg[1]_18 ;
  wire \rd_mux_sel_r_reg[1]_19 ;
  wire \rd_mux_sel_r_reg[1]_2 ;
  wire \rd_mux_sel_r_reg[1]_20 ;
  wire \rd_mux_sel_r_reg[1]_21 ;
  wire \rd_mux_sel_r_reg[1]_22 ;
  wire \rd_mux_sel_r_reg[1]_23 ;
  wire \rd_mux_sel_r_reg[1]_24 ;
  wire \rd_mux_sel_r_reg[1]_25 ;
  wire \rd_mux_sel_r_reg[1]_26 ;
  wire \rd_mux_sel_r_reg[1]_27 ;
  wire \rd_mux_sel_r_reg[1]_28 ;
  wire \rd_mux_sel_r_reg[1]_29 ;
  wire \rd_mux_sel_r_reg[1]_3 ;
  wire \rd_mux_sel_r_reg[1]_30 ;
  wire \rd_mux_sel_r_reg[1]_31 ;
  wire \rd_mux_sel_r_reg[1]_32 ;
  wire \rd_mux_sel_r_reg[1]_33 ;
  wire \rd_mux_sel_r_reg[1]_34 ;
  wire \rd_mux_sel_r_reg[1]_35 ;
  wire \rd_mux_sel_r_reg[1]_36 ;
  wire \rd_mux_sel_r_reg[1]_37 ;
  wire \rd_mux_sel_r_reg[1]_38 ;
  wire \rd_mux_sel_r_reg[1]_39 ;
  wire \rd_mux_sel_r_reg[1]_4 ;
  wire \rd_mux_sel_r_reg[1]_40 ;
  wire \rd_mux_sel_r_reg[1]_41 ;
  wire \rd_mux_sel_r_reg[1]_42 ;
  wire \rd_mux_sel_r_reg[1]_43 ;
  wire \rd_mux_sel_r_reg[1]_44 ;
  wire \rd_mux_sel_r_reg[1]_45 ;
  wire \rd_mux_sel_r_reg[1]_46 ;
  wire \rd_mux_sel_r_reg[1]_47 ;
  wire \rd_mux_sel_r_reg[1]_48 ;
  wire \rd_mux_sel_r_reg[1]_49 ;
  wire \rd_mux_sel_r_reg[1]_5 ;
  wire \rd_mux_sel_r_reg[1]_50 ;
  wire \rd_mux_sel_r_reg[1]_51 ;
  wire \rd_mux_sel_r_reg[1]_52 ;
  wire \rd_mux_sel_r_reg[1]_53 ;
  wire \rd_mux_sel_r_reg[1]_54 ;
  wire \rd_mux_sel_r_reg[1]_55 ;
  wire \rd_mux_sel_r_reg[1]_56 ;
  wire \rd_mux_sel_r_reg[1]_57 ;
  wire \rd_mux_sel_r_reg[1]_58 ;
  wire \rd_mux_sel_r_reg[1]_59 ;
  wire \rd_mux_sel_r_reg[1]_6 ;
  wire \rd_mux_sel_r_reg[1]_60 ;
  wire \rd_mux_sel_r_reg[1]_61 ;
  wire \rd_mux_sel_r_reg[1]_62 ;
  wire \rd_mux_sel_r_reg[1]_7 ;
  wire \rd_mux_sel_r_reg[1]_8 ;
  wire \rd_mux_sel_r_reg[1]_9 ;
  wire \rd_mux_sel_r_reg[2] ;
  wire \rd_mux_sel_r_reg[2]_0 ;
  wire \rd_mux_sel_r_reg[2]_1 ;
  wire \rd_mux_sel_r_reg[2]_10 ;
  wire \rd_mux_sel_r_reg[2]_11 ;
  wire \rd_mux_sel_r_reg[2]_12 ;
  wire \rd_mux_sel_r_reg[2]_13 ;
  wire \rd_mux_sel_r_reg[2]_14 ;
  wire \rd_mux_sel_r_reg[2]_15 ;
  wire \rd_mux_sel_r_reg[2]_16 ;
  wire \rd_mux_sel_r_reg[2]_17 ;
  wire \rd_mux_sel_r_reg[2]_18 ;
  wire \rd_mux_sel_r_reg[2]_19 ;
  wire \rd_mux_sel_r_reg[2]_2 ;
  wire \rd_mux_sel_r_reg[2]_20 ;
  wire \rd_mux_sel_r_reg[2]_21 ;
  wire \rd_mux_sel_r_reg[2]_22 ;
  wire \rd_mux_sel_r_reg[2]_23 ;
  wire \rd_mux_sel_r_reg[2]_24 ;
  wire \rd_mux_sel_r_reg[2]_25 ;
  wire \rd_mux_sel_r_reg[2]_26 ;
  wire \rd_mux_sel_r_reg[2]_27 ;
  wire \rd_mux_sel_r_reg[2]_28 ;
  wire \rd_mux_sel_r_reg[2]_29 ;
  wire \rd_mux_sel_r_reg[2]_3 ;
  wire \rd_mux_sel_r_reg[2]_30 ;
  wire \rd_mux_sel_r_reg[2]_31 ;
  wire \rd_mux_sel_r_reg[2]_32 ;
  wire \rd_mux_sel_r_reg[2]_33 ;
  wire \rd_mux_sel_r_reg[2]_34 ;
  wire \rd_mux_sel_r_reg[2]_35 ;
  wire \rd_mux_sel_r_reg[2]_36 ;
  wire \rd_mux_sel_r_reg[2]_37 ;
  wire \rd_mux_sel_r_reg[2]_38 ;
  wire \rd_mux_sel_r_reg[2]_39 ;
  wire \rd_mux_sel_r_reg[2]_4 ;
  wire \rd_mux_sel_r_reg[2]_40 ;
  wire \rd_mux_sel_r_reg[2]_41 ;
  wire \rd_mux_sel_r_reg[2]_42 ;
  wire \rd_mux_sel_r_reg[2]_43 ;
  wire \rd_mux_sel_r_reg[2]_44 ;
  wire \rd_mux_sel_r_reg[2]_45 ;
  wire \rd_mux_sel_r_reg[2]_46 ;
  wire \rd_mux_sel_r_reg[2]_47 ;
  wire \rd_mux_sel_r_reg[2]_48 ;
  wire \rd_mux_sel_r_reg[2]_49 ;
  wire \rd_mux_sel_r_reg[2]_5 ;
  wire \rd_mux_sel_r_reg[2]_50 ;
  wire \rd_mux_sel_r_reg[2]_51 ;
  wire \rd_mux_sel_r_reg[2]_52 ;
  wire \rd_mux_sel_r_reg[2]_53 ;
  wire \rd_mux_sel_r_reg[2]_54 ;
  wire \rd_mux_sel_r_reg[2]_55 ;
  wire \rd_mux_sel_r_reg[2]_56 ;
  wire \rd_mux_sel_r_reg[2]_57 ;
  wire \rd_mux_sel_r_reg[2]_58 ;
  wire \rd_mux_sel_r_reg[2]_59 ;
  wire \rd_mux_sel_r_reg[2]_6 ;
  wire \rd_mux_sel_r_reg[2]_60 ;
  wire \rd_mux_sel_r_reg[2]_61 ;
  wire \rd_mux_sel_r_reg[2]_62 ;
  wire \rd_mux_sel_r_reg[2]_7 ;
  wire \rd_mux_sel_r_reg[2]_8 ;
  wire \rd_mux_sel_r_reg[2]_9 ;
  wire [63:0]\rd_ptr_reg[3] ;
  wire [63:0]\rd_ptr_reg[3]_0 ;
  wire [63:0]\rd_ptr_reg[3]_1 ;
  wire [63:0]\rd_ptr_reg[3]_2 ;
  wire [0:0]ref_dll_lock_w__0;
  wire rst_out_reg_0;
  wire rst_out_reg_1;
  wire rst_primitives;
  wire rst_primitives_reg_0;
  wire rst_r4;
  wire sync_pulse;
  wire ts_dqs_4;
  wire ts_dqs_5;
  wire ts_dqs_6;
  wire ts_dqs_7;

  FDRE #(
    .INIT(1'b0)) 
    A_rst_primitives_reg
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rst_primitives),
        .Q(A_rst_primitives),
        .R(1'b0));
  mig_mig_7series_v4_2_ddr_byte_lane_25 \ddr_byte_lane_A.ddr_byte_lane_A 
       (.A_rst_primitives(A_rst_primitives),
        .A_rst_primitives_reg(A_rst_primitives_reg_0),
        .A_rst_primitives_reg_0(\ddr_byte_lane_A.ddr_byte_lane_A_n_22 ),
        .A_rst_primitives_reg_1(A_po_counter_read_val),
        .CLKB0(CLKB0),
        .COUNTERLOADVAL(COUNTERLOADVAL),
        .COUNTERREADVAL(A_pi_counter_read_val),
        .LD0(LD0),
        .PCENABLECALIB(phy_encalib),
        .Q(\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 (\ddr_byte_lane_A.ddr_byte_lane_A_n_40 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 (\ddr_byte_lane_A.ddr_byte_lane_A_n_44 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ),
        .freq_refclk(freq_refclk),
        .idelay_inc(idelay_inc),
        .idelay_ld_rst(idelay_ld_rst),
        .if_empty(if_empty),
        .if_empty_r(if_empty_r_5),
        .if_empty_v(if_empty_v),
        .ififo_rst_reg_0(ififo_rst_reg),
        .in0(in0[0]),
        .\input_[9].iserdes_dq_.iserdesdq (\input_[9].iserdes_dq_.iserdesdq ),
        .mem_dq_in(mem_dq_in[7:0]),
        .mem_dq_out(mem_dq_out[8:0]),
        .mem_dq_ts(mem_dq_ts[8:0]),
        .mem_dqs_in(mem_dqs_in[0]),
        .mem_refclk(mem_refclk),
        .my_empty({\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_4 [3],\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_4 [0]}),
        .my_empty_0(\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_2 ),
        .\my_empty_reg[1] (\my_empty_reg[1] ),
        .\my_empty_reg[7] (\my_empty_reg[7] ),
        .\my_empty_reg[7]_0 (\my_empty_reg[7]_0 ),
        .\my_empty_reg[7]_1 (\my_empty_reg[7]_1 ),
        .\my_empty_reg[7]_2 (\my_empty_reg[7]_2 ),
        .\my_empty_reg[7]_3 (\my_empty_reg[7]_3 ),
        .\my_empty_reg[7]_4 (\my_empty_reg[7]_4 ),
        .\my_empty_reg[7]_5 (\my_empty_reg[7]_5 ),
        .\my_empty_reg[7]_6 (\my_empty_reg[7]_6 ),
        .\my_full_reg[1] (\ddr_byte_lane_D.ddr_byte_lane_D_n_236 ),
        .\my_full_reg[4] (\entry_cnt_reg[4] ),
        .out_dqs_4(out_dqs_4),
        .out_fifo_0(out_fifo),
        .out_fifo_1({out_fifo_0[28],out_fifo_0[24],out_fifo_0[20],out_fifo_0[16],out_fifo_0[12],out_fifo_0[8],out_fifo_0[4],out_fifo_0[0]}),
        .out_fifo_2(out_fifo_1),
        .phaser_ctl_bus({phaser_ctl_bus[9:8],phaser_ctl_bus[4],phaser_ctl_bus[0]}),
        .phy_data_wr_en(phy_data_wr_en),
        .phy_dout(phy_dout),
        .phy_if_empty_r_reg(phy_if_empty_r_reg),
        .phy_if_reset(phy_if_reset),
        .phy_rddata_en(phy_rddata_en),
        .\pi_dqs_found_lanes_r1_reg[0] (\pi_dqs_found_lanes_r1_reg[0] ),
        .\pi_dqs_found_lanes_r1_reg[0]_0 (\pi_dqs_found_lanes_r1_reg[0]_0 ),
        .\pi_dqs_found_lanes_r1_reg[0]_1 (\pi_dqs_found_lanes_r1_reg[0]_1 ),
        .\pi_dqs_found_lanes_r1_reg[0]_2 (\pi_dqs_found_lanes_r1_reg[0]_2 ),
        .\po_counter_read_val_reg[8] (\po_counter_read_val_reg[8]_1 ),
        .\po_counter_read_val_reg[8]_0 (\po_counter_read_val_reg[8]_2 ),
        .\po_counter_read_val_reg[8]_1 (\po_counter_read_val_reg[8]_3 ),
        .\rd_ptr_reg[3] (\rd_ptr_reg[3] ),
        .rst_r4(rst_r4),
        .sync_pulse(sync_pulse),
        .ts_dqs_4(ts_dqs_4),
        .\wr_ptr[1]_i_2 (if_empty_r_0));
  mig_mig_7series_v4_2_ddr_byte_lane__parameterized0_26 \ddr_byte_lane_B.ddr_byte_lane_B 
       (.A_rst_primitives(A_rst_primitives),
        .A_rst_primitives_reg(A_rst_primitives_reg_1),
        .A_rst_primitives_reg_0(\ddr_byte_lane_B.ddr_byte_lane_B_n_22 ),
        .B_rclk(B_rclk),
        .CLKB0_7(CLKB0_7),
        .COUNTERREADVAL(A_pi_counter_read_val),
        .D({\ddr_byte_lane_B.ddr_byte_lane_B_n_223 ,\ddr_byte_lane_B.ddr_byte_lane_B_n_224 ,\ddr_byte_lane_B.ddr_byte_lane_B_n_225 ,\ddr_byte_lane_B.ddr_byte_lane_B_n_226 ,\ddr_byte_lane_B.ddr_byte_lane_B_n_227 ,\ddr_byte_lane_B.ddr_byte_lane_B_n_228 }),
        .LD0_7(LD0_7),
        .PCENABLECALIB(phy_encalib),
        .Q(\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_0 ),
        .calib_sel(calib_sel),
        .\calib_sel_reg[1] ({\ddr_byte_lane_B.ddr_byte_lane_B_n_229 ,\ddr_byte_lane_B.ddr_byte_lane_B_n_230 ,\ddr_byte_lane_B.ddr_byte_lane_B_n_231 ,\ddr_byte_lane_B.ddr_byte_lane_B_n_232 ,\ddr_byte_lane_B.ddr_byte_lane_B_n_233 ,\ddr_byte_lane_B.ddr_byte_lane_B_n_234 ,\ddr_byte_lane_B.ddr_byte_lane_B_n_235 ,\ddr_byte_lane_B.ddr_byte_lane_B_n_236 ,\ddr_byte_lane_B.ddr_byte_lane_B_n_237 }),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (if_empty_r),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 (\ddr_byte_lane_B.ddr_byte_lane_B_n_28 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 (\ddr_byte_lane_B.ddr_byte_lane_B_n_158 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ),
        .\entry_cnt_reg[4] (\entry_cnt_reg[4] ),
        .freq_refclk(freq_refclk),
        .\gen_mux_rd[0].mux_rd_fall0_r_reg[0] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ),
        .\gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0 (\gen_mux_rd[0].mux_rd_fall0_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_fall0_r_reg[0]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ),
        .\gen_mux_rd[0].mux_rd_fall0_r_reg[0]_2 (\gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0 ),
        .\gen_mux_rd[0].mux_rd_fall1_r_reg[0] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ),
        .\gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0 (\gen_mux_rd[0].mux_rd_fall1_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_fall1_r_reg[0]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ),
        .\gen_mux_rd[0].mux_rd_fall1_r_reg[0]_2 (\gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0 ),
        .\gen_mux_rd[0].mux_rd_fall2_r_reg[0] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ),
        .\gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0 (\gen_mux_rd[0].mux_rd_fall2_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_fall2_r_reg[0]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ),
        .\gen_mux_rd[0].mux_rd_fall2_r_reg[0]_2 (\gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0 ),
        .\gen_mux_rd[0].mux_rd_fall3_r_reg[0] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ),
        .\gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0 (\gen_mux_rd[0].mux_rd_fall3_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_fall3_r_reg[0]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ),
        .\gen_mux_rd[0].mux_rd_fall3_r_reg[0]_2 (\gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0 ),
        .\gen_mux_rd[0].mux_rd_rise0_r_reg[0] (\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ),
        .\gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1 (\gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ),
        .\gen_mux_rd[0].mux_rd_rise0_r_reg[0]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ),
        .\gen_mux_rd[0].mux_rd_rise0_r_reg[0]_3 (\gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1 ),
        .\gen_mux_rd[0].mux_rd_rise1_r_reg[0] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ),
        .\gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0 (\gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_rise1_r_reg[0]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ),
        .\gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 (\gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0 ),
        .\gen_mux_rd[0].mux_rd_rise2_r_reg[0] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ),
        .\gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0 (\gen_mux_rd[0].mux_rd_rise2_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_rise2_r_reg[0]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ),
        .\gen_mux_rd[0].mux_rd_rise2_r_reg[0]_2 (\gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0 ),
        .\gen_mux_rd[0].mux_rd_rise3_r_reg[0] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ),
        .\gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0 (\gen_mux_rd[0].mux_rd_rise3_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_rise3_r_reg[0]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ),
        .\gen_mux_rd[0].mux_rd_rise3_r_reg[0]_2 (\gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0 ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_2 (\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_2 (\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_2 (\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_fall3_r_reg[1] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ),
        .\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ),
        .\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_2 (\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_rise0_r_reg[1] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ),
        .\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ),
        .\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 (\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_3 (\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1 ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_2 (\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_2 (\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_2 (\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ),
        .\gen_mux_rd[2].mux_rd_fall0_r_reg[2] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ),
        .\gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0 (\gen_mux_rd[2].mux_rd_fall0_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_fall0_r_reg[2]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ),
        .\gen_mux_rd[2].mux_rd_fall0_r_reg[2]_2 (\gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0 ),
        .\gen_mux_rd[2].mux_rd_fall1_r_reg[2] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ),
        .\gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0 (\gen_mux_rd[2].mux_rd_fall1_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_fall1_r_reg[2]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ),
        .\gen_mux_rd[2].mux_rd_fall1_r_reg[2]_2 (\gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0 ),
        .\gen_mux_rd[2].mux_rd_fall2_r_reg[2] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ),
        .\gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0 (\gen_mux_rd[2].mux_rd_fall2_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_fall2_r_reg[2]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ),
        .\gen_mux_rd[2].mux_rd_fall2_r_reg[2]_2 (\gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0 ),
        .\gen_mux_rd[2].mux_rd_fall3_r_reg[2] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ),
        .\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 (\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ),
        .\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_2 (\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 ),
        .\gen_mux_rd[2].mux_rd_rise0_r_reg[2] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ),
        .\gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 (\gen_mux_rd[2].mux_rd_rise0_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ),
        .\gen_mux_rd[2].mux_rd_rise0_r_reg[2]_2 (\gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ),
        .\gen_mux_rd[2].mux_rd_rise1_r_reg[2] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ),
        .\gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0 (\gen_mux_rd[2].mux_rd_rise1_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_rise1_r_reg[2]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ),
        .\gen_mux_rd[2].mux_rd_rise1_r_reg[2]_2 (\gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0 ),
        .\gen_mux_rd[2].mux_rd_rise2_r_reg[2] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ),
        .\gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0 (\gen_mux_rd[2].mux_rd_rise2_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_rise2_r_reg[2]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ),
        .\gen_mux_rd[2].mux_rd_rise2_r_reg[2]_2 (\gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0 ),
        .\gen_mux_rd[2].mux_rd_rise3_r_reg[2] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ),
        .\gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0 (\gen_mux_rd[2].mux_rd_rise3_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_rise3_r_reg[2]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ),
        .\gen_mux_rd[2].mux_rd_rise3_r_reg[2]_2 (\gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0 ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_2 (\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_2 (\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_2 (\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_2 (\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_2 (\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_2 (\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_2 (\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_2 (\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ),
        .\gen_mux_rd[4].mux_rd_fall0_r_reg[4] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ),
        .\gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0 (\gen_mux_rd[4].mux_rd_fall0_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_fall0_r_reg[4]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ),
        .\gen_mux_rd[4].mux_rd_fall0_r_reg[4]_2 (\gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0 ),
        .\gen_mux_rd[4].mux_rd_fall1_r_reg[4] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ),
        .\gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0 (\gen_mux_rd[4].mux_rd_fall1_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_fall1_r_reg[4]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ),
        .\gen_mux_rd[4].mux_rd_fall1_r_reg[4]_2 (\gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0 ),
        .\gen_mux_rd[4].mux_rd_fall2_r_reg[4] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ),
        .\gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0 (\gen_mux_rd[4].mux_rd_fall2_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_fall2_r_reg[4]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ),
        .\gen_mux_rd[4].mux_rd_fall2_r_reg[4]_2 (\gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0 ),
        .\gen_mux_rd[4].mux_rd_fall3_r_reg[4] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ),
        .\gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0 (\gen_mux_rd[4].mux_rd_fall3_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_fall3_r_reg[4]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ),
        .\gen_mux_rd[4].mux_rd_fall3_r_reg[4]_2 (\gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0 ),
        .\gen_mux_rd[4].mux_rd_rise0_r_reg[4] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ),
        .\gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0 (\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_rise0_r_reg[4]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ),
        .\gen_mux_rd[4].mux_rd_rise0_r_reg[4]_2 (\gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0 ),
        .\gen_mux_rd[4].mux_rd_rise1_r_reg[4] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ),
        .\gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0 (\gen_mux_rd[4].mux_rd_rise1_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_rise1_r_reg[4]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ),
        .\gen_mux_rd[4].mux_rd_rise1_r_reg[4]_2 (\gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0 ),
        .\gen_mux_rd[4].mux_rd_rise2_r_reg[4] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ),
        .\gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0 (\gen_mux_rd[4].mux_rd_rise2_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_rise2_r_reg[4]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ),
        .\gen_mux_rd[4].mux_rd_rise2_r_reg[4]_2 (\gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0 ),
        .\gen_mux_rd[4].mux_rd_rise3_r_reg[4] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ),
        .\gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0 (\gen_mux_rd[4].mux_rd_rise3_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_rise3_r_reg[4]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ),
        .\gen_mux_rd[4].mux_rd_rise3_r_reg[4]_2 (\gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0 ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_2 (\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_2 (\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_2 (\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_2 (\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_rise0_r_reg[5] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ),
        .\gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_rise0_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise0_r_reg[5]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ),
        .\gen_mux_rd[5].mux_rd_rise0_r_reg[5]_2 (\gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_2 (\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_2 (\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_2 (\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ),
        .\gen_mux_rd[6].mux_rd_fall0_r_reg[6] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ),
        .\gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0 (\gen_mux_rd[6].mux_rd_fall0_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_fall0_r_reg[6]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ),
        .\gen_mux_rd[6].mux_rd_fall0_r_reg[6]_2 (\gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0 ),
        .\gen_mux_rd[6].mux_rd_fall1_r_reg[6] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ),
        .\gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0 (\gen_mux_rd[6].mux_rd_fall1_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_fall1_r_reg[6]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ),
        .\gen_mux_rd[6].mux_rd_fall1_r_reg[6]_2 (\gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0 ),
        .\gen_mux_rd[6].mux_rd_fall2_r_reg[6] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ),
        .\gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0 (\gen_mux_rd[6].mux_rd_fall2_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_fall2_r_reg[6]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ),
        .\gen_mux_rd[6].mux_rd_fall2_r_reg[6]_2 (\gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0 ),
        .\gen_mux_rd[6].mux_rd_fall3_r_reg[6] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ),
        .\gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0 (\gen_mux_rd[6].mux_rd_fall3_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_fall3_r_reg[6]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ),
        .\gen_mux_rd[6].mux_rd_fall3_r_reg[6]_2 (\gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0 ),
        .\gen_mux_rd[6].mux_rd_rise0_r_reg[6] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ),
        .\gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0 (\gen_mux_rd[6].mux_rd_rise0_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_rise0_r_reg[6]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ),
        .\gen_mux_rd[6].mux_rd_rise0_r_reg[6]_2 (\gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0 ),
        .\gen_mux_rd[6].mux_rd_rise1_r_reg[6] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ),
        .\gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0 (\gen_mux_rd[6].mux_rd_rise1_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_rise1_r_reg[6]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ),
        .\gen_mux_rd[6].mux_rd_rise1_r_reg[6]_2 (\gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0 ),
        .\gen_mux_rd[6].mux_rd_rise2_r_reg[6] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ),
        .\gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0 (\gen_mux_rd[6].mux_rd_rise2_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_rise2_r_reg[6]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ),
        .\gen_mux_rd[6].mux_rd_rise2_r_reg[6]_2 (\gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0 ),
        .\gen_mux_rd[6].mux_rd_rise3_r_reg[6] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ),
        .\gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0 (\gen_mux_rd[6].mux_rd_rise3_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_rise3_r_reg[6]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ),
        .\gen_mux_rd[6].mux_rd_rise3_r_reg[6]_2 (\gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0 ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1 ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_2 (\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1 ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_2 (\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1 ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_2 (\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1 ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_2 (\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_rise0_r_reg[7] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ),
        .\gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_rise0_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise0_r_reg[7]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1 ),
        .\gen_mux_rd[7].mux_rd_rise0_r_reg[7]_2 (\gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1 ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_2 (\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1 ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_2 (\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1 ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_2 (\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ),
        .idelay_inc(idelay_inc),
        .idelay_ld_rst_0(idelay_ld_rst_0),
        .ififo_rst_reg_0(ififo_rst_reg_0),
        .in0(in0[1]),
        .\input_[9].iserdes_dq_.iserdesdq (\input_[9].iserdes_dq_.iserdesdq_0 ),
        .mem_dq_in(mem_dq_in[15:8]),
        .mem_dq_out(mem_dq_out[17:9]),
        .mem_dq_ts(mem_dq_ts[17:9]),
        .mem_dqs_in(mem_dqs_in[1]),
        .mem_refclk(mem_refclk),
        .my_empty(\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_2 ),
        .\my_empty_reg[1] (\my_empty_reg[1]_0 ),
        .\my_empty_reg[4] (\my_empty_reg[4] ),
        .\my_empty_reg[4]_0 (\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ),
        .\my_empty_reg[7] (\my_empty_reg[7]_7 ),
        .\my_empty_reg[7]_0 (\my_empty_reg[7]_8 ),
        .\my_empty_reg[7]_1 (\my_empty_reg[7]_9 ),
        .\my_empty_reg[7]_2 (\my_empty_reg[7]_10 ),
        .\my_empty_reg[7]_3 (\my_empty_reg[7]_11 ),
        .\my_empty_reg[7]_4 (\my_empty_reg[7]_12 ),
        .\my_empty_reg[7]_5 (\my_empty_reg[7]_13 ),
        .\my_empty_reg[7]_6 (\my_empty_reg[7]_14 ),
        .\my_full_reg[1] (\ddr_byte_lane_D.ddr_byte_lane_D_n_237 ),
        .out_dqs_5(out_dqs_5),
        .out_fifo_0(out_fifo),
        .out_fifo_1({out_fifo_0[29],out_fifo_0[25],out_fifo_0[21],out_fifo_0[17],out_fifo_0[13],out_fifo_0[9],out_fifo_0[5],out_fifo_0[1]}),
        .out_fifo_2(out_fifo_1),
        .out_fifo_i_75__5(out_fifo_i_75__5),
        .phaser_ctl_bus({phaser_ctl_bus[11:10],phaser_ctl_bus[5],phaser_ctl_bus[1]}),
        .phy_data_wr_en(phy_data_wr_en),
        .phy_if_reset(phy_if_reset),
        .\pi_counter_read_val_reg[5] (D_pi_counter_read_val),
        .\pi_counter_read_val_reg[5]_0 (C_pi_counter_read_val),
        .\pi_dqs_found_lanes_r1_reg[1] (\pi_dqs_found_lanes_r1_reg[1] ),
        .\pi_dqs_found_lanes_r1_reg[1]_0 (\pi_dqs_found_lanes_r1_reg[1]_0 ),
        .\pi_dqs_found_lanes_r1_reg[1]_1 (\pi_dqs_found_lanes_r1_reg[1]_1 ),
        .\pi_dqs_found_lanes_r1_reg[1]_2 (\pi_dqs_found_lanes_r1_reg[1]_2 ),
        .\pi_dqs_found_lanes_r1_reg[1]_3 (\pi_dqs_found_lanes_r1_reg[1]_3 ),
        .\po_counter_read_val_reg[8] (\po_counter_read_val_reg[8]_4 ),
        .\po_counter_read_val_reg[8]_0 (\po_counter_read_val_reg[8]_5 ),
        .\po_counter_read_val_reg[8]_1 (\po_counter_read_val_reg[8]_6 ),
        .\po_counter_read_val_reg[8]_2 (A_po_counter_read_val),
        .\po_counter_read_val_reg[8]_3 (D_po_counter_read_val),
        .\po_counter_read_val_reg[8]_4 (C_po_counter_read_val),
        .\rd_mux_sel_r_reg[2] (\rd_mux_sel_r_reg[2] ),
        .\rd_mux_sel_r_reg[2]_0 (\rd_mux_sel_r_reg[2]_0 ),
        .\rd_mux_sel_r_reg[2]_1 (\rd_mux_sel_r_reg[2]_1 ),
        .\rd_mux_sel_r_reg[2]_10 (\rd_mux_sel_r_reg[2]_10 ),
        .\rd_mux_sel_r_reg[2]_11 (\rd_mux_sel_r_reg[2]_11 ),
        .\rd_mux_sel_r_reg[2]_12 (\rd_mux_sel_r_reg[2]_12 ),
        .\rd_mux_sel_r_reg[2]_13 (\rd_mux_sel_r_reg[2]_13 ),
        .\rd_mux_sel_r_reg[2]_14 (\rd_mux_sel_r_reg[2]_14 ),
        .\rd_mux_sel_r_reg[2]_15 (\rd_mux_sel_r_reg[2]_15 ),
        .\rd_mux_sel_r_reg[2]_16 (\rd_mux_sel_r_reg[2]_16 ),
        .\rd_mux_sel_r_reg[2]_17 (\rd_mux_sel_r_reg[2]_17 ),
        .\rd_mux_sel_r_reg[2]_18 (\rd_mux_sel_r_reg[2]_18 ),
        .\rd_mux_sel_r_reg[2]_19 (\rd_mux_sel_r_reg[2]_19 ),
        .\rd_mux_sel_r_reg[2]_2 (\rd_mux_sel_r_reg[2]_2 ),
        .\rd_mux_sel_r_reg[2]_20 (\rd_mux_sel_r_reg[2]_20 ),
        .\rd_mux_sel_r_reg[2]_21 (\rd_mux_sel_r_reg[2]_21 ),
        .\rd_mux_sel_r_reg[2]_22 (\rd_mux_sel_r_reg[2]_22 ),
        .\rd_mux_sel_r_reg[2]_23 (\rd_mux_sel_r_reg[2]_23 ),
        .\rd_mux_sel_r_reg[2]_24 (\rd_mux_sel_r_reg[2]_24 ),
        .\rd_mux_sel_r_reg[2]_25 (\rd_mux_sel_r_reg[2]_25 ),
        .\rd_mux_sel_r_reg[2]_26 (\rd_mux_sel_r_reg[2]_26 ),
        .\rd_mux_sel_r_reg[2]_27 (\rd_mux_sel_r_reg[2]_27 ),
        .\rd_mux_sel_r_reg[2]_28 (\rd_mux_sel_r_reg[2]_28 ),
        .\rd_mux_sel_r_reg[2]_29 (\rd_mux_sel_r_reg[2]_29 ),
        .\rd_mux_sel_r_reg[2]_3 (\rd_mux_sel_r_reg[2]_3 ),
        .\rd_mux_sel_r_reg[2]_30 (\rd_mux_sel_r_reg[2]_30 ),
        .\rd_mux_sel_r_reg[2]_31 (\rd_mux_sel_r_reg[2]_31 ),
        .\rd_mux_sel_r_reg[2]_32 (\rd_mux_sel_r_reg[2]_32 ),
        .\rd_mux_sel_r_reg[2]_33 (\rd_mux_sel_r_reg[2]_33 ),
        .\rd_mux_sel_r_reg[2]_34 (\rd_mux_sel_r_reg[2]_34 ),
        .\rd_mux_sel_r_reg[2]_35 (\rd_mux_sel_r_reg[2]_35 ),
        .\rd_mux_sel_r_reg[2]_36 (\rd_mux_sel_r_reg[2]_36 ),
        .\rd_mux_sel_r_reg[2]_37 (\rd_mux_sel_r_reg[2]_37 ),
        .\rd_mux_sel_r_reg[2]_38 (\rd_mux_sel_r_reg[2]_38 ),
        .\rd_mux_sel_r_reg[2]_39 (\rd_mux_sel_r_reg[2]_39 ),
        .\rd_mux_sel_r_reg[2]_4 (\rd_mux_sel_r_reg[2]_4 ),
        .\rd_mux_sel_r_reg[2]_40 (\rd_mux_sel_r_reg[2]_40 ),
        .\rd_mux_sel_r_reg[2]_41 (\rd_mux_sel_r_reg[2]_41 ),
        .\rd_mux_sel_r_reg[2]_42 (\rd_mux_sel_r_reg[2]_42 ),
        .\rd_mux_sel_r_reg[2]_43 (\rd_mux_sel_r_reg[2]_43 ),
        .\rd_mux_sel_r_reg[2]_44 (\rd_mux_sel_r_reg[2]_44 ),
        .\rd_mux_sel_r_reg[2]_45 (\rd_mux_sel_r_reg[2]_45 ),
        .\rd_mux_sel_r_reg[2]_46 (\rd_mux_sel_r_reg[2]_46 ),
        .\rd_mux_sel_r_reg[2]_47 (\rd_mux_sel_r_reg[2]_47 ),
        .\rd_mux_sel_r_reg[2]_48 (\rd_mux_sel_r_reg[2]_48 ),
        .\rd_mux_sel_r_reg[2]_49 (\rd_mux_sel_r_reg[2]_49 ),
        .\rd_mux_sel_r_reg[2]_5 (\rd_mux_sel_r_reg[2]_5 ),
        .\rd_mux_sel_r_reg[2]_50 (\rd_mux_sel_r_reg[2]_50 ),
        .\rd_mux_sel_r_reg[2]_51 (\rd_mux_sel_r_reg[2]_51 ),
        .\rd_mux_sel_r_reg[2]_52 (\rd_mux_sel_r_reg[2]_52 ),
        .\rd_mux_sel_r_reg[2]_53 (\rd_mux_sel_r_reg[2]_53 ),
        .\rd_mux_sel_r_reg[2]_54 (\rd_mux_sel_r_reg[2]_54 ),
        .\rd_mux_sel_r_reg[2]_55 (\rd_mux_sel_r_reg[2]_55 ),
        .\rd_mux_sel_r_reg[2]_56 (\rd_mux_sel_r_reg[2]_56 ),
        .\rd_mux_sel_r_reg[2]_57 (\rd_mux_sel_r_reg[2]_57 ),
        .\rd_mux_sel_r_reg[2]_58 (\rd_mux_sel_r_reg[2]_58 ),
        .\rd_mux_sel_r_reg[2]_59 (\rd_mux_sel_r_reg[2]_59 ),
        .\rd_mux_sel_r_reg[2]_6 (\rd_mux_sel_r_reg[2]_6 ),
        .\rd_mux_sel_r_reg[2]_60 (\rd_mux_sel_r_reg[2]_60 ),
        .\rd_mux_sel_r_reg[2]_61 (\rd_mux_sel_r_reg[2]_61 ),
        .\rd_mux_sel_r_reg[2]_62 (\rd_mux_sel_r_reg[2]_62 ),
        .\rd_mux_sel_r_reg[2]_7 (\rd_mux_sel_r_reg[2]_7 ),
        .\rd_mux_sel_r_reg[2]_8 (\rd_mux_sel_r_reg[2]_8 ),
        .\rd_mux_sel_r_reg[2]_9 (\rd_mux_sel_r_reg[2]_9 ),
        .\rd_ptr_reg[3] (\rd_ptr_reg[3]_0 ),
        .rst_r4(rst_r4),
        .sync_pulse(sync_pulse),
        .ts_dqs_5(ts_dqs_5),
        .\wr_ptr[1]_i_2__0 (if_empty_r_0));
  mig_mig_7series_v4_2_ddr_byte_lane__parameterized1_27 \ddr_byte_lane_C.ddr_byte_lane_C 
       (.A_rst_primitives(A_rst_primitives),
        .A_rst_primitives_reg(A_rst_primitives_reg_2),
        .A_rst_primitives_reg_0(C_pi_counter_read_val),
        .A_rst_primitives_reg_1(C_po_counter_read_val),
        .A_rst_primitives_reg_2(A_rst_primitives_reg_4),
        .CLKB0_8(CLKB0_8),
        .LD0_8(LD0_8),
        .PCENABLECALIB(phy_encalib),
        .Q(\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_1 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (if_empty_r_0),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 (\ddr_byte_lane_C.ddr_byte_lane_C_n_109 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ),
        .freq_refclk(freq_refclk),
        .idelay_inc(idelay_inc),
        .idelay_ld_rst_1(idelay_ld_rst_1),
        .if_empty_r(if_empty_r),
        .ififo_rst_reg_0(ififo_rst_reg_1),
        .in0(in0[2]),
        .\input_[9].iserdes_dq_.iserdesdq (\input_[9].iserdes_dq_.iserdesdq_1 ),
        .mem_dq_in(mem_dq_in[23:16]),
        .mem_dq_out(mem_dq_out[26:18]),
        .mem_dq_ts(mem_dq_ts[26:18]),
        .mem_dqs_in(mem_dqs_in[2]),
        .mem_refclk(mem_refclk),
        .\my_empty_reg[1] (\my_empty_reg[1]_1 ),
        .\my_empty_reg[4] (\my_empty_reg[4]_0 ),
        .\my_empty_reg[4]_0 (\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_2 ),
        .\my_empty_reg[7] (\my_empty_reg[7]_15 ),
        .\my_empty_reg[7]_0 (\my_empty_reg[7]_16 ),
        .\my_empty_reg[7]_1 (\my_empty_reg[7]_17 ),
        .\my_empty_reg[7]_2 (\my_empty_reg[7]_18 ),
        .\my_empty_reg[7]_3 (\my_empty_reg[7]_19 ),
        .\my_empty_reg[7]_4 (\my_empty_reg[7]_20 ),
        .\my_empty_reg[7]_5 (\my_empty_reg[7]_21 ),
        .\my_empty_reg[7]_6 (\my_empty_reg[7]_22 ),
        .\my_full_reg[1] (\ddr_byte_lane_D.ddr_byte_lane_D_n_238 ),
        .\my_full_reg[1]_0 (\my_full_reg[1] ),
        .\my_full_reg[1]_1 (\my_full_reg[1]_0 ),
        .\my_full_reg[1]_2 (\my_full_reg[1]_1 ),
        .\my_full_reg[1]_3 (\ddr_byte_lane_A.ddr_byte_lane_A_n_44 ),
        .\my_full_reg[1]_4 (\ddr_byte_lane_D.ddr_byte_lane_D_n_239 ),
        .\my_full_reg[4] (\entry_cnt_reg[4] ),
        .ofs_rdy_r_reg(ofs_rdy_r_i_3_n_0),
        .ofs_rdy_r_reg_0(ofs_rdy_r_i_4_n_0),
        .ofs_rdy_r_reg_1(ofs_rdy_r_reg),
        .ofs_rdy_r_reg_2(ofs_rdy_r_reg_0),
        .out_dqs_6(out_dqs_6),
        .out_fifo_0(out_fifo),
        .out_fifo_1({out_fifo_0[30],out_fifo_0[26],out_fifo_0[22],out_fifo_0[18],out_fifo_0[14],out_fifo_0[10],out_fifo_0[6],out_fifo_0[2]}),
        .out_fifo_2(out_fifo_1),
        .out_fifo_i_75__6(out_fifo_i_75__6),
        .phaser_ctl_bus({phaser_ctl_bus[13:12],phaser_ctl_bus[6],phaser_ctl_bus[2]}),
        .phy_data_wr_en(phy_data_wr_en),
        .phy_if_reset(phy_if_reset),
        .phy_mc_data_full(phy_mc_data_full),
        .\pi_dqs_found_lanes_r1_reg[2] (\pi_dqs_found_lanes_r1_reg[2] ),
        .\pi_dqs_found_lanes_r1_reg[2]_0 (\pi_dqs_found_lanes_r1_reg[2]_0 ),
        .\pi_dqs_found_lanes_r1_reg[2]_1 (\pi_dqs_found_lanes_r1_reg[2]_1 ),
        .\pi_dqs_found_lanes_r1_reg[2]_2 (\pi_dqs_found_lanes_r1_reg[2]_2 ),
        .\pi_dqs_found_lanes_r1_reg[2]_3 (\pi_dqs_found_lanes_r1_reg[2]_3 ),
        .pi_phase_locked_all_r1_reg(\ddr_byte_lane_B.ddr_byte_lane_B_n_22 ),
        .pi_phase_locked_all_r1_reg_0(\ddr_byte_lane_A.ddr_byte_lane_A_n_22 ),
        .pi_phase_locked_all_r1_reg_1(\ddr_byte_lane_D.ddr_byte_lane_D_n_22 ),
        .pi_phase_locked_all_r1_reg_2(pi_phase_locked_all_r1_reg),
        .\po_counter_read_val_reg[8] (\po_counter_read_val_reg[8]_7 ),
        .\po_counter_read_val_reg[8]_0 (\po_counter_read_val_reg[8]_8 ),
        .\po_counter_read_val_reg[8]_1 (\po_counter_read_val_reg[8]_9 ),
        .\rd_ptr_reg[3] (\rd_ptr_reg[3]_1 ),
        .rst_r4(rst_r4),
        .sync_pulse(sync_pulse),
        .ts_dqs_6(ts_dqs_6),
        .\wr_ptr[1]_i_2__6 (\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ));
  mig_mig_7series_v4_2_ddr_byte_lane__parameterized2_28 \ddr_byte_lane_D.ddr_byte_lane_D 
       (.A_rst_primitives(A_rst_primitives),
        .A_rst_primitives_reg(A_rst_primitives_reg_3),
        .A_rst_primitives_reg_0(\ddr_byte_lane_D.ddr_byte_lane_D_n_22 ),
        .A_rst_primitives_reg_1(D_pi_counter_read_val),
        .A_rst_primitives_reg_2(D_po_counter_read_val),
        .CLKB0_9(CLKB0_9),
        .LD0_9(LD0_9),
        .PCENABLECALIB(phy_encalib),
        .Q(\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_3 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (\ddr_byte_lane_D.ddr_byte_lane_D_n_236 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 (\ddr_byte_lane_D.ddr_byte_lane_D_n_237 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 (\ddr_byte_lane_D.ddr_byte_lane_D_n_238 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 (\ddr_byte_lane_D.ddr_byte_lane_D_n_239 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2 ),
        .\entry_cnt_reg[4] (\entry_cnt_reg[4] ),
        .freq_refclk(freq_refclk),
        .\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] (\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1 ),
        .idelay_inc(idelay_inc),
        .idelay_ld_rst_2(idelay_ld_rst_2),
        .if_empty_r(if_empty_r),
        .if_empty_r_0(if_empty_r_5),
        .ififo_rst_reg_0(ififo_rst_reg_2),
        .in0(in0[3]),
        .\input_[9].iserdes_dq_.iserdesdq (\input_[9].iserdes_dq_.iserdesdq_2 ),
        .mem_dq_in(mem_dq_in[31:24]),
        .mem_dq_out(mem_dq_out[35:27]),
        .mem_dq_ts(mem_dq_ts[35:27]),
        .mem_dqs_in(mem_dqs_in[3]),
        .mem_refclk(mem_refclk),
        .\my_empty_reg[1] (\my_empty_reg[1]_2 ),
        .\my_empty_reg[4] ({\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_4 [3],\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_4 [0]}),
        .\my_empty_reg[7] (\my_empty_reg[7]_23 ),
        .\my_empty_reg[7]_0 (\my_empty_reg[7]_24 ),
        .\my_empty_reg[7]_1 (\my_empty_reg[7]_25 ),
        .\my_empty_reg[7]_2 (\my_empty_reg[7]_26 ),
        .\my_empty_reg[7]_3 (\my_empty_reg[7]_27 ),
        .\my_empty_reg[7]_4 (\my_empty_reg[7]_28 ),
        .\my_empty_reg[7]_5 (\my_empty_reg[7]_29 ),
        .\my_empty_reg[7]_6 (\my_empty_reg[7]_30 ),
        .\my_full_reg[1] (\ddr_byte_lane_C.ddr_byte_lane_C_n_109 ),
        .\my_full_reg[1]_0 (\my_full_reg[1] ),
        .\my_full_reg[1]_1 (\my_full_reg[1]_0 ),
        .\my_full_reg[1]_2 (\my_full_reg[1]_1 ),
        .\my_full_reg[1]_3 (\ddr_byte_lane_B.ddr_byte_lane_B_n_158 ),
        .\my_full_reg[1]_4 (\ddr_byte_lane_A.ddr_byte_lane_A_n_40 ),
        .\my_full_reg[1]_5 (\ddr_byte_lane_A.ddr_byte_lane_A_n_44 ),
        .\my_full_reg[1]_6 (\ddr_byte_lane_B.ddr_byte_lane_B_n_28 ),
        .\my_full_reg[1]_7 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),
        .out_dqs_7(out_dqs_7),
        .out_fifo_0(out_fifo),
        .out_fifo_1({out_fifo_0[31],out_fifo_0[27],out_fifo_0[23],out_fifo_0[19],out_fifo_0[15],out_fifo_0[11],out_fifo_0[7],out_fifo_0[3]}),
        .out_fifo_2(out_fifo_1),
        .out_fifo_i_75__7(out_fifo_i_75__7),
        .phaser_ctl_bus({phaser_ctl_bus[15:14],phaser_ctl_bus[7],phaser_ctl_bus[3]}),
        .phy_data_wr_en(phy_data_wr_en),
        .phy_if_reset(phy_if_reset),
        .\pi_dqs_found_lanes_r1_reg[3] (\pi_dqs_found_lanes_r1_reg[3] ),
        .\pi_dqs_found_lanes_r1_reg[3]_0 (\pi_dqs_found_lanes_r1_reg[3]_0 ),
        .\pi_dqs_found_lanes_r1_reg[3]_1 (\pi_dqs_found_lanes_r1_reg[3]_1 ),
        .\pi_dqs_found_lanes_r1_reg[3]_2 (\pi_dqs_found_lanes_r1_reg[3]_2 ),
        .\pi_dqs_found_lanes_r1_reg[3]_3 (\pi_dqs_found_lanes_r1_reg[3]_3 ),
        .\po_counter_read_val_reg[8] (\po_counter_read_val_reg[8]_10 ),
        .\po_counter_read_val_reg[8]_0 (\po_counter_read_val_reg[8]_11 ),
        .\po_counter_read_val_reg[8]_1 (\po_counter_read_val_reg[8]_12 ),
        .\po_stg2_wrcal_cnt_reg[1] (\po_stg2_wrcal_cnt_reg[1] ),
        .\po_stg2_wrcal_cnt_reg[1]_0 (\po_stg2_wrcal_cnt_reg[1]_0 ),
        .\po_stg2_wrcal_cnt_reg[1]_1 (\po_stg2_wrcal_cnt_reg[1]_1 ),
        .\po_stg2_wrcal_cnt_reg[1]_10 (\po_stg2_wrcal_cnt_reg[1]_10 ),
        .\po_stg2_wrcal_cnt_reg[1]_11 (\po_stg2_wrcal_cnt_reg[1]_11 ),
        .\po_stg2_wrcal_cnt_reg[1]_12 (\po_stg2_wrcal_cnt_reg[1]_12 ),
        .\po_stg2_wrcal_cnt_reg[1]_13 (\po_stg2_wrcal_cnt_reg[1]_13 ),
        .\po_stg2_wrcal_cnt_reg[1]_14 (\po_stg2_wrcal_cnt_reg[1]_14 ),
        .\po_stg2_wrcal_cnt_reg[1]_15 (\po_stg2_wrcal_cnt_reg[1]_15 ),
        .\po_stg2_wrcal_cnt_reg[1]_16 (\po_stg2_wrcal_cnt_reg[1]_16 ),
        .\po_stg2_wrcal_cnt_reg[1]_17 (\po_stg2_wrcal_cnt_reg[1]_17 ),
        .\po_stg2_wrcal_cnt_reg[1]_18 (\po_stg2_wrcal_cnt_reg[1]_18 ),
        .\po_stg2_wrcal_cnt_reg[1]_19 (\po_stg2_wrcal_cnt_reg[1]_19 ),
        .\po_stg2_wrcal_cnt_reg[1]_2 (\po_stg2_wrcal_cnt_reg[1]_2 ),
        .\po_stg2_wrcal_cnt_reg[1]_20 (\po_stg2_wrcal_cnt_reg[1]_20 ),
        .\po_stg2_wrcal_cnt_reg[1]_21 (\po_stg2_wrcal_cnt_reg[1]_21 ),
        .\po_stg2_wrcal_cnt_reg[1]_22 (\po_stg2_wrcal_cnt_reg[1]_22 ),
        .\po_stg2_wrcal_cnt_reg[1]_23 (\po_stg2_wrcal_cnt_reg[1]_23 ),
        .\po_stg2_wrcal_cnt_reg[1]_24 (\po_stg2_wrcal_cnt_reg[1]_24 ),
        .\po_stg2_wrcal_cnt_reg[1]_25 (\po_stg2_wrcal_cnt_reg[1]_25 ),
        .\po_stg2_wrcal_cnt_reg[1]_26 (\po_stg2_wrcal_cnt_reg[1]_26 ),
        .\po_stg2_wrcal_cnt_reg[1]_27 (\po_stg2_wrcal_cnt_reg[1]_27 ),
        .\po_stg2_wrcal_cnt_reg[1]_28 (\po_stg2_wrcal_cnt_reg[1]_28 ),
        .\po_stg2_wrcal_cnt_reg[1]_29 (\po_stg2_wrcal_cnt_reg[1]_29 ),
        .\po_stg2_wrcal_cnt_reg[1]_3 (\po_stg2_wrcal_cnt_reg[1]_3 ),
        .\po_stg2_wrcal_cnt_reg[1]_30 (\po_stg2_wrcal_cnt_reg[1]_30 ),
        .\po_stg2_wrcal_cnt_reg[1]_31 (\po_stg2_wrcal_cnt_reg[1]_31 ),
        .\po_stg2_wrcal_cnt_reg[1]_32 (\po_stg2_wrcal_cnt_reg[1]_32 ),
        .\po_stg2_wrcal_cnt_reg[1]_33 (\po_stg2_wrcal_cnt_reg[1]_33 ),
        .\po_stg2_wrcal_cnt_reg[1]_34 (\po_stg2_wrcal_cnt_reg[1]_34 ),
        .\po_stg2_wrcal_cnt_reg[1]_35 (\po_stg2_wrcal_cnt_reg[1]_35 ),
        .\po_stg2_wrcal_cnt_reg[1]_36 (\po_stg2_wrcal_cnt_reg[1]_36 ),
        .\po_stg2_wrcal_cnt_reg[1]_37 (\po_stg2_wrcal_cnt_reg[1]_37 ),
        .\po_stg2_wrcal_cnt_reg[1]_38 (\po_stg2_wrcal_cnt_reg[1]_38 ),
        .\po_stg2_wrcal_cnt_reg[1]_39 (\po_stg2_wrcal_cnt_reg[1]_39 ),
        .\po_stg2_wrcal_cnt_reg[1]_4 (\po_stg2_wrcal_cnt_reg[1]_4 ),
        .\po_stg2_wrcal_cnt_reg[1]_40 (\po_stg2_wrcal_cnt_reg[1]_40 ),
        .\po_stg2_wrcal_cnt_reg[1]_41 (\po_stg2_wrcal_cnt_reg[1]_41 ),
        .\po_stg2_wrcal_cnt_reg[1]_42 (\po_stg2_wrcal_cnt_reg[1]_42 ),
        .\po_stg2_wrcal_cnt_reg[1]_43 (\po_stg2_wrcal_cnt_reg[1]_43 ),
        .\po_stg2_wrcal_cnt_reg[1]_44 (\po_stg2_wrcal_cnt_reg[1]_44 ),
        .\po_stg2_wrcal_cnt_reg[1]_45 (\po_stg2_wrcal_cnt_reg[1]_45 ),
        .\po_stg2_wrcal_cnt_reg[1]_46 (\po_stg2_wrcal_cnt_reg[1]_46 ),
        .\po_stg2_wrcal_cnt_reg[1]_47 (\po_stg2_wrcal_cnt_reg[1]_47 ),
        .\po_stg2_wrcal_cnt_reg[1]_48 (\po_stg2_wrcal_cnt_reg[1]_48 ),
        .\po_stg2_wrcal_cnt_reg[1]_49 (\po_stg2_wrcal_cnt_reg[1]_49 ),
        .\po_stg2_wrcal_cnt_reg[1]_5 (\po_stg2_wrcal_cnt_reg[1]_5 ),
        .\po_stg2_wrcal_cnt_reg[1]_50 (\po_stg2_wrcal_cnt_reg[1]_50 ),
        .\po_stg2_wrcal_cnt_reg[1]_51 (\po_stg2_wrcal_cnt_reg[1]_51 ),
        .\po_stg2_wrcal_cnt_reg[1]_52 (\po_stg2_wrcal_cnt_reg[1]_52 ),
        .\po_stg2_wrcal_cnt_reg[1]_53 (\po_stg2_wrcal_cnt_reg[1]_53 ),
        .\po_stg2_wrcal_cnt_reg[1]_54 (\po_stg2_wrcal_cnt_reg[1]_54 ),
        .\po_stg2_wrcal_cnt_reg[1]_55 (\po_stg2_wrcal_cnt_reg[1]_55 ),
        .\po_stg2_wrcal_cnt_reg[1]_56 (\po_stg2_wrcal_cnt_reg[1]_56 ),
        .\po_stg2_wrcal_cnt_reg[1]_57 (\po_stg2_wrcal_cnt_reg[1]_57 ),
        .\po_stg2_wrcal_cnt_reg[1]_58 (\po_stg2_wrcal_cnt_reg[1]_58 ),
        .\po_stg2_wrcal_cnt_reg[1]_59 (\po_stg2_wrcal_cnt_reg[1]_59 ),
        .\po_stg2_wrcal_cnt_reg[1]_6 (\po_stg2_wrcal_cnt_reg[1]_6 ),
        .\po_stg2_wrcal_cnt_reg[1]_60 (\po_stg2_wrcal_cnt_reg[1]_60 ),
        .\po_stg2_wrcal_cnt_reg[1]_61 (\po_stg2_wrcal_cnt_reg[1]_61 ),
        .\po_stg2_wrcal_cnt_reg[1]_62 (\po_stg2_wrcal_cnt_reg[1]_62 ),
        .\po_stg2_wrcal_cnt_reg[1]_7 (\po_stg2_wrcal_cnt_reg[1]_7 ),
        .\po_stg2_wrcal_cnt_reg[1]_8 (\po_stg2_wrcal_cnt_reg[1]_8 ),
        .\po_stg2_wrcal_cnt_reg[1]_9 (\po_stg2_wrcal_cnt_reg[1]_9 ),
        .\rd_mux_sel_r_reg[1] (\rd_mux_sel_r_reg[1] ),
        .\rd_mux_sel_r_reg[1]_0 (\rd_mux_sel_r_reg[1]_0 ),
        .\rd_mux_sel_r_reg[1]_1 (\rd_mux_sel_r_reg[1]_1 ),
        .\rd_mux_sel_r_reg[1]_10 (\rd_mux_sel_r_reg[1]_10 ),
        .\rd_mux_sel_r_reg[1]_11 (\rd_mux_sel_r_reg[1]_11 ),
        .\rd_mux_sel_r_reg[1]_12 (\rd_mux_sel_r_reg[1]_12 ),
        .\rd_mux_sel_r_reg[1]_13 (\rd_mux_sel_r_reg[1]_13 ),
        .\rd_mux_sel_r_reg[1]_14 (\rd_mux_sel_r_reg[1]_14 ),
        .\rd_mux_sel_r_reg[1]_15 (\rd_mux_sel_r_reg[1]_15 ),
        .\rd_mux_sel_r_reg[1]_16 (\rd_mux_sel_r_reg[1]_16 ),
        .\rd_mux_sel_r_reg[1]_17 (\rd_mux_sel_r_reg[1]_17 ),
        .\rd_mux_sel_r_reg[1]_18 (\rd_mux_sel_r_reg[1]_18 ),
        .\rd_mux_sel_r_reg[1]_19 (\rd_mux_sel_r_reg[1]_19 ),
        .\rd_mux_sel_r_reg[1]_2 (\rd_mux_sel_r_reg[1]_2 ),
        .\rd_mux_sel_r_reg[1]_20 (\rd_mux_sel_r_reg[1]_20 ),
        .\rd_mux_sel_r_reg[1]_21 (\rd_mux_sel_r_reg[1]_21 ),
        .\rd_mux_sel_r_reg[1]_22 (\rd_mux_sel_r_reg[1]_22 ),
        .\rd_mux_sel_r_reg[1]_23 (\rd_mux_sel_r_reg[1]_23 ),
        .\rd_mux_sel_r_reg[1]_24 (\rd_mux_sel_r_reg[1]_24 ),
        .\rd_mux_sel_r_reg[1]_25 (\rd_mux_sel_r_reg[1]_25 ),
        .\rd_mux_sel_r_reg[1]_26 (\rd_mux_sel_r_reg[1]_26 ),
        .\rd_mux_sel_r_reg[1]_27 (\rd_mux_sel_r_reg[1]_27 ),
        .\rd_mux_sel_r_reg[1]_28 (\rd_mux_sel_r_reg[1]_28 ),
        .\rd_mux_sel_r_reg[1]_29 (\rd_mux_sel_r_reg[1]_29 ),
        .\rd_mux_sel_r_reg[1]_3 (\rd_mux_sel_r_reg[1]_3 ),
        .\rd_mux_sel_r_reg[1]_30 (\rd_mux_sel_r_reg[1]_30 ),
        .\rd_mux_sel_r_reg[1]_31 (\rd_mux_sel_r_reg[1]_31 ),
        .\rd_mux_sel_r_reg[1]_32 (\rd_mux_sel_r_reg[1]_32 ),
        .\rd_mux_sel_r_reg[1]_33 (\rd_mux_sel_r_reg[1]_33 ),
        .\rd_mux_sel_r_reg[1]_34 (\rd_mux_sel_r_reg[1]_34 ),
        .\rd_mux_sel_r_reg[1]_35 (\rd_mux_sel_r_reg[1]_35 ),
        .\rd_mux_sel_r_reg[1]_36 (\rd_mux_sel_r_reg[1]_36 ),
        .\rd_mux_sel_r_reg[1]_37 (\rd_mux_sel_r_reg[1]_37 ),
        .\rd_mux_sel_r_reg[1]_38 (\rd_mux_sel_r_reg[1]_38 ),
        .\rd_mux_sel_r_reg[1]_39 (\rd_mux_sel_r_reg[1]_39 ),
        .\rd_mux_sel_r_reg[1]_4 (\rd_mux_sel_r_reg[1]_4 ),
        .\rd_mux_sel_r_reg[1]_40 (\rd_mux_sel_r_reg[1]_40 ),
        .\rd_mux_sel_r_reg[1]_41 (\rd_mux_sel_r_reg[1]_41 ),
        .\rd_mux_sel_r_reg[1]_42 (\rd_mux_sel_r_reg[1]_42 ),
        .\rd_mux_sel_r_reg[1]_43 (\rd_mux_sel_r_reg[1]_43 ),
        .\rd_mux_sel_r_reg[1]_44 (\rd_mux_sel_r_reg[1]_44 ),
        .\rd_mux_sel_r_reg[1]_45 (\rd_mux_sel_r_reg[1]_45 ),
        .\rd_mux_sel_r_reg[1]_46 (\rd_mux_sel_r_reg[1]_46 ),
        .\rd_mux_sel_r_reg[1]_47 (\rd_mux_sel_r_reg[1]_47 ),
        .\rd_mux_sel_r_reg[1]_48 (\rd_mux_sel_r_reg[1]_48 ),
        .\rd_mux_sel_r_reg[1]_49 (\rd_mux_sel_r_reg[1]_49 ),
        .\rd_mux_sel_r_reg[1]_5 (\rd_mux_sel_r_reg[1]_5 ),
        .\rd_mux_sel_r_reg[1]_50 (\rd_mux_sel_r_reg[1]_50 ),
        .\rd_mux_sel_r_reg[1]_51 (\rd_mux_sel_r_reg[1]_51 ),
        .\rd_mux_sel_r_reg[1]_52 (\rd_mux_sel_r_reg[1]_52 ),
        .\rd_mux_sel_r_reg[1]_53 (\rd_mux_sel_r_reg[1]_53 ),
        .\rd_mux_sel_r_reg[1]_54 (\rd_mux_sel_r_reg[1]_54 ),
        .\rd_mux_sel_r_reg[1]_55 (\rd_mux_sel_r_reg[1]_55 ),
        .\rd_mux_sel_r_reg[1]_56 (\rd_mux_sel_r_reg[1]_56 ),
        .\rd_mux_sel_r_reg[1]_57 (\rd_mux_sel_r_reg[1]_57 ),
        .\rd_mux_sel_r_reg[1]_58 (\rd_mux_sel_r_reg[1]_58 ),
        .\rd_mux_sel_r_reg[1]_59 (\rd_mux_sel_r_reg[1]_59 ),
        .\rd_mux_sel_r_reg[1]_6 (\rd_mux_sel_r_reg[1]_6 ),
        .\rd_mux_sel_r_reg[1]_60 (\rd_mux_sel_r_reg[1]_60 ),
        .\rd_mux_sel_r_reg[1]_61 (\rd_mux_sel_r_reg[1]_61 ),
        .\rd_mux_sel_r_reg[1]_62 (\rd_mux_sel_r_reg[1]_62 ),
        .\rd_mux_sel_r_reg[1]_7 (\rd_mux_sel_r_reg[1]_7 ),
        .\rd_mux_sel_r_reg[1]_8 (\rd_mux_sel_r_reg[1]_8 ),
        .\rd_mux_sel_r_reg[1]_9 (\rd_mux_sel_r_reg[1]_9 ),
        .\rd_ptr_reg[3] (\rd_ptr_reg[3]_2 ),
        .rst_r4(rst_r4),
        .sync_pulse(sync_pulse),
        .ts_dqs_7(ts_dqs_7),
        .\wr_ptr[1]_i_2__2 (\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ));
  LUT1 #(
    .INIT(2'h2)) 
    i_0
       (.I0(1'b0),
        .O(A_pi_rst_div2));
  LUT1 #(
    .INIT(2'h2)) 
    i_1
       (.I0(1'b0),
        .O(B_pi_rst_div2));
  LUT1 #(
    .INIT(2'h2)) 
    i_2
       (.I0(1'b0),
        .O(C_pi_rst_div2));
  LUT1 #(
    .INIT(2'h2)) 
    i_3
       (.I0(1'b0),
        .O(D_pi_rst_div2));
  FDRE #(
    .INIT(1'b0)) 
    mcGo_reg
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rst_out_reg_0),
        .Q(mcGo_w),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    ofs_rdy_r_i_3
       (.I0(\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_1 [4]),
        .I1(\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_1 [2]),
        .I2(\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_1 [3]),
        .I3(\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_0 [4]),
        .I4(\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_0 [2]),
        .I5(\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_0 [3]),
        .O(ofs_rdy_r_i_3_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    ofs_rdy_r_i_4
       (.I0(\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg [4]),
        .I1(\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg [2]),
        .I2(\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg [3]),
        .I3(\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_3 [4]),
        .I4(\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_3 [2]),
        .I5(\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_3 [3]),
        .O(ofs_rdy_r_i_4_n_0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  PHASER_REF #(
    .IS_PWRDWN_INVERTED(1'b0),
    .IS_RST_INVERTED(1'b0)) 
    phaser_ref_i
       (.CLKIN(freq_refclk),
        .LOCKED(ref_dll_lock_w__0),
        .PWRDWN(1'b0),
        .RST(RST0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  PHY_CONTROL #(
    .AO_TOGGLE(1),
    .AO_WRLVL_EN(4'b0000),
    .BURST_MODE("TRUE"),
    .CLK_RATIO(4),
    .CMD_OFFSET(8),
    .CO_DURATION(1),
    .DATA_CTL_A_N("TRUE"),
    .DATA_CTL_B_N("TRUE"),
    .DATA_CTL_C_N("TRUE"),
    .DATA_CTL_D_N("TRUE"),
    .DISABLE_SEQ_MATCH("TRUE"),
    .DI_DURATION(1),
    .DO_DURATION(1),
    .EVENTS_DELAY(18),
    .FOUR_WINDOW_CLOCKS(63),
    .MULTI_REGION("TRUE"),
    .PHY_COUNT_ENABLE("FALSE"),
    .RD_CMD_OFFSET_0(10),
    .RD_CMD_OFFSET_1(10),
    .RD_CMD_OFFSET_2(10),
    .RD_CMD_OFFSET_3(10),
    .RD_DURATION_0(6),
    .RD_DURATION_1(6),
    .RD_DURATION_2(6),
    .RD_DURATION_3(6),
    .SYNC_MODE("FALSE"),
    .WR_CMD_OFFSET_0(8),
    .WR_CMD_OFFSET_1(8),
    .WR_CMD_OFFSET_2(8),
    .WR_CMD_OFFSET_3(8),
    .WR_DURATION_0(7),
    .WR_DURATION_1(7),
    .WR_DURATION_2(7),
    .WR_DURATION_3(7)) 
    phy_control_i
       (.AUXOUTPUT({phy_control_i_n_14,phy_control_i_n_15,phy_control_i_n_16,phy_control_i_n_17}),
        .INBURSTPENDING(phaser_ctl_bus[7:4]),
        .INRANKA(phaser_ctl_bus[9:8]),
        .INRANKB(phaser_ctl_bus[11:10]),
        .INRANKC(phaser_ctl_bus[13:12]),
        .INRANKD(phaser_ctl_bus[15:14]),
        .MEMREFCLK(mem_refclk),
        .OUTBURSTPENDING(phaser_ctl_bus[3:0]),
        .PCENABLECALIB(phy_encalib),
        .PHYCLK(\entry_cnt_reg[4] ),
        .PHYCTLALMOSTFULL(phy_control_i_n_0),
        .PHYCTLEMPTY(phy_control_i_n_1),
        .PHYCTLFULL(_phy_ctl_full_p__0),
        .PHYCTLMSTREMPTY(phy_ctl_mstr_empty),
        .PHYCTLREADY(phy_ctl_wr_i2_reg),
        .PHYCTLWD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,Q[10:3],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,Q[2:0]}),
        .PHYCTLWRENABLE(phy_ctl_wr_i2),
        .PLLLOCK(pll_locked),
        .READCALIBENABLE(phy_read_calib),
        .REFDLLLOCK(ref_dll_lock_w__0),
        .RESET(phy_mc_ctl_full_r_reg),
        .SYNCIN(sync_pulse),
        .WRITECALIBENABLE(phy_write_calib));
  FDRE \pi_counter_read_val_reg[0] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(\ddr_byte_lane_B.ddr_byte_lane_B_n_228 ),
        .Q(\pi_counter_read_val_reg[5]_0 [0]),
        .R(1'b0));
  FDRE \pi_counter_read_val_reg[1] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(\ddr_byte_lane_B.ddr_byte_lane_B_n_227 ),
        .Q(\pi_counter_read_val_reg[5]_0 [1]),
        .R(1'b0));
  FDRE \pi_counter_read_val_reg[2] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(\ddr_byte_lane_B.ddr_byte_lane_B_n_226 ),
        .Q(\pi_counter_read_val_reg[5]_0 [2]),
        .R(1'b0));
  FDRE \pi_counter_read_val_reg[3] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(\ddr_byte_lane_B.ddr_byte_lane_B_n_225 ),
        .Q(\pi_counter_read_val_reg[5]_0 [3]),
        .R(1'b0));
  FDRE \pi_counter_read_val_reg[4] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(\ddr_byte_lane_B.ddr_byte_lane_B_n_224 ),
        .Q(\pi_counter_read_val_reg[5]_0 [4]),
        .R(1'b0));
  FDRE \pi_counter_read_val_reg[5] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(\ddr_byte_lane_B.ddr_byte_lane_B_n_223 ),
        .Q(\pi_counter_read_val_reg[5]_0 [5]),
        .R(1'b0));
  FDRE \po_counter_read_val_reg[0] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(\ddr_byte_lane_B.ddr_byte_lane_B_n_237 ),
        .Q(\po_counter_read_val_reg[8]_0 [0]),
        .R(1'b0));
  FDRE \po_counter_read_val_reg[1] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(\ddr_byte_lane_B.ddr_byte_lane_B_n_236 ),
        .Q(\po_counter_read_val_reg[8]_0 [1]),
        .R(1'b0));
  FDRE \po_counter_read_val_reg[2] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(\ddr_byte_lane_B.ddr_byte_lane_B_n_235 ),
        .Q(\po_counter_read_val_reg[8]_0 [2]),
        .R(1'b0));
  FDRE \po_counter_read_val_reg[3] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(\ddr_byte_lane_B.ddr_byte_lane_B_n_234 ),
        .Q(\po_counter_read_val_reg[8]_0 [3]),
        .R(1'b0));
  FDRE \po_counter_read_val_reg[4] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(\ddr_byte_lane_B.ddr_byte_lane_B_n_233 ),
        .Q(\po_counter_read_val_reg[8]_0 [4]),
        .R(1'b0));
  FDRE \po_counter_read_val_reg[5] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(\ddr_byte_lane_B.ddr_byte_lane_B_n_232 ),
        .Q(\po_counter_read_val_reg[8]_0 [5]),
        .R(1'b0));
  FDRE \po_counter_read_val_reg[6] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(\ddr_byte_lane_B.ddr_byte_lane_B_n_231 ),
        .Q(\po_counter_read_val_reg[8]_0 [6]),
        .R(1'b0));
  FDRE \po_counter_read_val_reg[7] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(\ddr_byte_lane_B.ddr_byte_lane_B_n_230 ),
        .Q(\po_counter_read_val_reg[8]_0 [7]),
        .R(1'b0));
  FDRE \po_counter_read_val_reg[8] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(\ddr_byte_lane_B.ddr_byte_lane_B_n_229 ),
        .Q(\po_counter_read_val_reg[8]_0 [8]),
        .R(1'b0));
  (* srl_bus_name = "\u_mig_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/rclk_delay_reg " *) 
  (* srl_name = "\u_mig_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/rclk_delay_reg[10]_srl11 " *) 
  SRL16E \rclk_delay_reg[10]_srl11 
       (.A0(1'b0),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b1),
        .CE(1'b1),
        .CLK(\entry_cnt_reg[4] ),
        .D(\rclk_delay_reg[11]_0 ),
        .Q(\rclk_delay_reg[10]_srl11_n_0 ));
  FDRE \rclk_delay_reg[11] 
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(\rclk_delay_reg[10]_srl11_n_0 ),
        .Q(rclk_delay_11),
        .R(1'b0));
  FDCE #(
    .INIT(1'b0)) 
    rst_out_reg
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .CLR(SR),
        .D(rst_out_reg_1),
        .Q(rst_out_reg_0));
  FDRE #(
    .INIT(1'b0)) 
    rst_primitives_reg
       (.C(\entry_cnt_reg[4] ),
        .CE(1'b1),
        .D(rst_primitives_reg_0),
        .Q(rst_primitives),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_phy_4lanes" *) 
module mig_mig_7series_v4_2_ddr_phy_4lanes_13
   (out_dqs_0,
    ts_dqs_0,
    A_rst_primitives_reg_0,
    mem_dq_out,
    mem_dq_ts,
    in0,
    idelay_ld_rst_3,
    out_dqs_1,
    ts_dqs_1,
    A_rst_primitives_reg_1,
    idelay_ld_rst_4,
    out_dqs_2,
    ts_dqs_2,
    A_rst_primitives_reg_2,
    idelay_ld_rst_5,
    out_dqs_3,
    ts_dqs_3,
    A_rst_primitives_reg_3,
    idelay_ld_rst_6,
    _phy_ctl_full_p__0,
    phy_ctl_wr_i2_reg,
    ref_dll_lock_w__0,
    rst_primitives,
    mcGo_w,
    rst_out_reg_0,
    rclk_delay_11,
    \my_empty_reg[1] ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ,
    \my_empty_reg[1]_0 ,
    \my_empty_reg[1]_1 ,
    \my_empty_reg[1]_2 ,
    \rd_mux_sel_r_reg[0] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ,
    \rd_mux_sel_r_reg[0]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ,
    \rd_mux_sel_r_reg[0]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ,
    \rd_mux_sel_r_reg[0]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ,
    \rd_mux_sel_r_reg[0]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ,
    \rd_mux_sel_r_reg[0]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ,
    \rd_mux_sel_r_reg[0]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ,
    \rd_mux_sel_r_reg[0]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1 ,
    \rd_mux_sel_r_reg[0]_7 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ,
    \rd_mux_sel_r_reg[0]_8 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ,
    \rd_mux_sel_r_reg[0]_9 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ,
    \rd_mux_sel_r_reg[0]_10 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ,
    \rd_mux_sel_r_reg[0]_11 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ,
    \rd_mux_sel_r_reg[0]_12 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ,
    \rd_mux_sel_r_reg[0]_13 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ,
    \rd_mux_sel_r_reg[0]_14 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1 ,
    \rd_mux_sel_r_reg[0]_15 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ,
    \rd_mux_sel_r_reg[0]_16 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ,
    \rd_mux_sel_r_reg[0]_17 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ,
    \rd_mux_sel_r_reg[0]_18 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ,
    \rd_mux_sel_r_reg[0]_19 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ,
    \rd_mux_sel_r_reg[0]_20 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ,
    \rd_mux_sel_r_reg[0]_21 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ,
    \rd_mux_sel_r_reg[0]_22 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1 ,
    \rd_mux_sel_r_reg[0]_23 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ,
    \rd_mux_sel_r_reg[0]_24 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ,
    \rd_mux_sel_r_reg[0]_25 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ,
    \rd_mux_sel_r_reg[0]_26 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ,
    \rd_mux_sel_r_reg[0]_27 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ,
    \rd_mux_sel_r_reg[0]_28 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ,
    \rd_mux_sel_r_reg[0]_29 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ,
    \rd_mux_sel_r_reg[0]_30 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1 ,
    \rd_mux_sel_r_reg[0]_31 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ,
    \rd_mux_sel_r_reg[0]_32 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ,
    \rd_mux_sel_r_reg[0]_33 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ,
    \rd_mux_sel_r_reg[0]_34 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ,
    \rd_mux_sel_r_reg[0]_35 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ,
    \rd_mux_sel_r_reg[0]_36 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ,
    \rd_mux_sel_r_reg[0]_37 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ,
    \rd_mux_sel_r_reg[0]_38 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1 ,
    \rd_mux_sel_r_reg[0]_39 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ,
    \rd_mux_sel_r_reg[0]_40 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ,
    \rd_mux_sel_r_reg[0]_41 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ,
    \rd_mux_sel_r_reg[0]_42 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ,
    \rd_mux_sel_r_reg[0]_43 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ,
    \rd_mux_sel_r_reg[0]_44 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ,
    \rd_mux_sel_r_reg[0]_45 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ,
    \rd_mux_sel_r_reg[0]_46 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1 ,
    \rd_mux_sel_r_reg[0]_47 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ,
    \rd_mux_sel_r_reg[0]_48 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ,
    \rd_mux_sel_r_reg[0]_49 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ,
    \rd_mux_sel_r_reg[0]_50 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ,
    \rd_mux_sel_r_reg[0]_51 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ,
    \rd_mux_sel_r_reg[0]_52 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ,
    \rd_mux_sel_r_reg[0]_53 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ,
    \rd_mux_sel_r_reg[0]_54 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1 ,
    \rd_mux_sel_r_reg[0]_55 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ,
    \rd_mux_sel_r_reg[0]_56 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ,
    \rd_mux_sel_r_reg[0]_57 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ,
    \rd_mux_sel_r_reg[0]_58 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ,
    \rd_mux_sel_r_reg[0]_59 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ,
    \rd_mux_sel_r_reg[0]_60 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ,
    \rd_mux_sel_r_reg[0]_61 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ,
    \rd_mux_sel_r_reg[0]_62 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1 ,
    A_rst_primitives_reg_4,
    \rd_mux_sel_r_reg[2] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ,
    \rd_mux_sel_r_reg[2]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ,
    \rd_mux_sel_r_reg[2]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ,
    \rd_mux_sel_r_reg[2]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ,
    \rd_mux_sel_r_reg[2]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ,
    \rd_mux_sel_r_reg[2]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ,
    \rd_mux_sel_r_reg[2]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ,
    \rd_mux_sel_r_reg[2]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_2 ,
    \rd_mux_sel_r_reg[2]_7 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2 ,
    \rd_mux_sel_r_reg[2]_8 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2 ,
    \rd_mux_sel_r_reg[2]_9 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2 ,
    \rd_mux_sel_r_reg[2]_10 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2 ,
    \rd_mux_sel_r_reg[2]_11 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2 ,
    \rd_mux_sel_r_reg[2]_12 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2 ,
    \rd_mux_sel_r_reg[2]_13 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ,
    \rd_mux_sel_r_reg[2]_14 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_2 ,
    \rd_mux_sel_r_reg[2]_15 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2 ,
    \rd_mux_sel_r_reg[2]_16 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2 ,
    \rd_mux_sel_r_reg[2]_17 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2 ,
    \rd_mux_sel_r_reg[2]_18 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2 ,
    \rd_mux_sel_r_reg[2]_19 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2 ,
    \rd_mux_sel_r_reg[2]_20 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2 ,
    \rd_mux_sel_r_reg[2]_21 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ,
    \rd_mux_sel_r_reg[2]_22 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_2 ,
    \rd_mux_sel_r_reg[2]_23 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2 ,
    \rd_mux_sel_r_reg[2]_24 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2 ,
    \rd_mux_sel_r_reg[2]_25 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2 ,
    \rd_mux_sel_r_reg[2]_26 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2 ,
    \rd_mux_sel_r_reg[2]_27 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2 ,
    \rd_mux_sel_r_reg[2]_28 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2 ,
    \rd_mux_sel_r_reg[2]_29 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ,
    \rd_mux_sel_r_reg[2]_30 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_2 ,
    \rd_mux_sel_r_reg[2]_31 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2 ,
    \rd_mux_sel_r_reg[2]_32 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2 ,
    \rd_mux_sel_r_reg[2]_33 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2 ,
    \rd_mux_sel_r_reg[2]_34 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2 ,
    \rd_mux_sel_r_reg[2]_35 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2 ,
    \rd_mux_sel_r_reg[2]_36 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2 ,
    \rd_mux_sel_r_reg[2]_37 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ,
    \rd_mux_sel_r_reg[2]_38 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_2 ,
    \rd_mux_sel_r_reg[2]_39 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2 ,
    \rd_mux_sel_r_reg[2]_40 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2 ,
    \rd_mux_sel_r_reg[2]_41 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2 ,
    \rd_mux_sel_r_reg[2]_42 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2 ,
    \rd_mux_sel_r_reg[2]_43 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2 ,
    \rd_mux_sel_r_reg[2]_44 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2 ,
    \rd_mux_sel_r_reg[2]_45 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ,
    \rd_mux_sel_r_reg[2]_46 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_2 ,
    \rd_mux_sel_r_reg[2]_47 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2 ,
    \rd_mux_sel_r_reg[2]_48 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2 ,
    \rd_mux_sel_r_reg[2]_49 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2 ,
    \rd_mux_sel_r_reg[2]_50 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2 ,
    \rd_mux_sel_r_reg[2]_51 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2 ,
    \rd_mux_sel_r_reg[2]_52 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2 ,
    \rd_mux_sel_r_reg[2]_53 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ,
    \rd_mux_sel_r_reg[2]_54 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_2 ,
    \rd_mux_sel_r_reg[2]_55 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2 ,
    \rd_mux_sel_r_reg[2]_56 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2 ,
    \rd_mux_sel_r_reg[2]_57 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2 ,
    \rd_mux_sel_r_reg[2]_58 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2 ,
    \rd_mux_sel_r_reg[2]_59 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2 ,
    \rd_mux_sel_r_reg[2]_60 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2 ,
    \rd_mux_sel_r_reg[2]_61 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ,
    \rd_mux_sel_r_reg[2]_62 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2 ,
    p_0_out,
    \po_stg2_wrcal_cnt_reg[2] ,
    \po_stg2_wrcal_cnt_reg[2]_0 ,
    \po_stg2_wrcal_cnt_reg[2]_1 ,
    \po_stg2_wrcal_cnt_reg[2]_2 ,
    \po_stg2_wrcal_cnt_reg[2]_3 ,
    \po_stg2_wrcal_cnt_reg[2]_4 ,
    \po_stg2_wrcal_cnt_reg[2]_5 ,
    \po_stg2_wrcal_cnt_reg[2]_6 ,
    \po_stg2_wrcal_cnt_reg[2]_7 ,
    \po_stg2_wrcal_cnt_reg[2]_8 ,
    \po_stg2_wrcal_cnt_reg[2]_9 ,
    \po_stg2_wrcal_cnt_reg[2]_10 ,
    \po_stg2_wrcal_cnt_reg[2]_11 ,
    \po_stg2_wrcal_cnt_reg[2]_12 ,
    \po_stg2_wrcal_cnt_reg[2]_13 ,
    \po_stg2_wrcal_cnt_reg[2]_14 ,
    \po_stg2_wrcal_cnt_reg[2]_15 ,
    \po_stg2_wrcal_cnt_reg[2]_16 ,
    \po_stg2_wrcal_cnt_reg[2]_17 ,
    \po_stg2_wrcal_cnt_reg[2]_18 ,
    \po_stg2_wrcal_cnt_reg[2]_19 ,
    \po_stg2_wrcal_cnt_reg[2]_20 ,
    \po_stg2_wrcal_cnt_reg[2]_21 ,
    \po_stg2_wrcal_cnt_reg[2]_22 ,
    \po_stg2_wrcal_cnt_reg[2]_23 ,
    \po_stg2_wrcal_cnt_reg[2]_24 ,
    \po_stg2_wrcal_cnt_reg[2]_25 ,
    \po_stg2_wrcal_cnt_reg[2]_26 ,
    \po_stg2_wrcal_cnt_reg[2]_27 ,
    \po_stg2_wrcal_cnt_reg[2]_28 ,
    \po_stg2_wrcal_cnt_reg[2]_29 ,
    \po_stg2_wrcal_cnt_reg[2]_30 ,
    \po_stg2_wrcal_cnt_reg[2]_31 ,
    \po_stg2_wrcal_cnt_reg[2]_32 ,
    \po_stg2_wrcal_cnt_reg[2]_33 ,
    \po_stg2_wrcal_cnt_reg[2]_34 ,
    \po_stg2_wrcal_cnt_reg[2]_35 ,
    \po_stg2_wrcal_cnt_reg[2]_36 ,
    \po_stg2_wrcal_cnt_reg[2]_37 ,
    \po_stg2_wrcal_cnt_reg[2]_38 ,
    \po_stg2_wrcal_cnt_reg[2]_39 ,
    \po_stg2_wrcal_cnt_reg[2]_40 ,
    \po_stg2_wrcal_cnt_reg[2]_41 ,
    \po_stg2_wrcal_cnt_reg[2]_42 ,
    \po_stg2_wrcal_cnt_reg[2]_43 ,
    \po_stg2_wrcal_cnt_reg[2]_44 ,
    \po_stg2_wrcal_cnt_reg[2]_45 ,
    \po_stg2_wrcal_cnt_reg[2]_46 ,
    \po_stg2_wrcal_cnt_reg[2]_47 ,
    \po_stg2_wrcal_cnt_reg[2]_48 ,
    \po_stg2_wrcal_cnt_reg[2]_49 ,
    \po_stg2_wrcal_cnt_reg[2]_50 ,
    \po_stg2_wrcal_cnt_reg[2]_51 ,
    \po_stg2_wrcal_cnt_reg[2]_52 ,
    \po_stg2_wrcal_cnt_reg[2]_53 ,
    \po_stg2_wrcal_cnt_reg[2]_54 ,
    \po_stg2_wrcal_cnt_reg[2]_55 ,
    \po_stg2_wrcal_cnt_reg[2]_56 ,
    \po_stg2_wrcal_cnt_reg[2]_57 ,
    \po_stg2_wrcal_cnt_reg[2]_58 ,
    \po_stg2_wrcal_cnt_reg[2]_59 ,
    \po_stg2_wrcal_cnt_reg[2]_60 ,
    \po_stg2_wrcal_cnt_reg[2]_61 ,
    \rd_ptr_reg[3] ,
    \rd_ptr_reg[3]_0 ,
    \rd_ptr_reg[3]_1 ,
    \rd_ptr_reg[3]_2 ,
    \entry_cnt_reg[4] ,
    \entry_cnt_reg[4]_0 ,
    Q,
    \pi_counter_read_val_reg[5]_0 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ,
    \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ,
    if_empty_v,
    \entry_cnt_reg[4]_1 ,
    \input_[9].iserdes_dq_.iserdesdq ,
    mem_dq_in,
    idelay_inc,
    LD0_10,
    CLKB0_10,
    \pi_dqs_found_lanes_r1_reg[8] ,
    \pi_dqs_found_lanes_r1_reg[8]_0 ,
    \pi_dqs_found_lanes_r1_reg[8]_1 ,
    \pi_dqs_found_lanes_r1_reg[8]_2 ,
    freq_refclk,
    mem_refclk,
    mem_dqs_in,
    ififo_rst_reg,
    sync_pulse,
    \pi_dqs_found_lanes_r1_reg[8]_3 ,
    \po_counter_read_val_reg[8]_0 ,
    \po_counter_read_val_reg[8]_1 ,
    \po_counter_read_val_reg[8]_2 ,
    \my_empty_reg[7] ,
    D2,
    \my_empty_reg[7]_0 ,
    \my_empty_reg[7]_1 ,
    \my_empty_reg[7]_2 ,
    \my_empty_reg[7]_3 ,
    \my_empty_reg[7]_4 ,
    \my_empty_reg[7]_5 ,
    phy_if_reset,
    \input_[9].iserdes_dq_.iserdesdq_0 ,
    LD0_11,
    CLKB0_11,
    \pi_dqs_found_lanes_r1_reg[9] ,
    \pi_dqs_found_lanes_r1_reg[9]_0 ,
    \pi_dqs_found_lanes_r1_reg[9]_1 ,
    \pi_dqs_found_lanes_r1_reg[9]_2 ,
    ififo_rst_reg_0,
    \pi_dqs_found_lanes_r1_reg[9]_3 ,
    \po_counter_read_val_reg[8]_3 ,
    \po_counter_read_val_reg[8]_4 ,
    \po_counter_read_val_reg[8]_5 ,
    \my_empty_reg[7]_6 ,
    \my_empty_reg[7]_7 ,
    \my_empty_reg[7]_8 ,
    \my_empty_reg[7]_9 ,
    \my_empty_reg[7]_10 ,
    \my_empty_reg[7]_11 ,
    \my_empty_reg[7]_12 ,
    \my_empty_reg[7]_13 ,
    \input_[9].iserdes_dq_.iserdesdq_1 ,
    LD0_12,
    CLKB0_12,
    \pi_dqs_found_lanes_r1_reg[10] ,
    \pi_dqs_found_lanes_r1_reg[10]_0 ,
    \pi_dqs_found_lanes_r1_reg[10]_1 ,
    \pi_dqs_found_lanes_r1_reg[10]_2 ,
    ififo_rst_reg_1,
    \pi_dqs_found_lanes_r1_reg[10]_3 ,
    \po_counter_read_val_reg[8]_6 ,
    \po_counter_read_val_reg[8]_7 ,
    \po_counter_read_val_reg[8]_8 ,
    \my_empty_reg[7]_14 ,
    \my_empty_reg[7]_15 ,
    \my_empty_reg[7]_16 ,
    \my_empty_reg[7]_17 ,
    \my_empty_reg[7]_18 ,
    \my_empty_reg[7]_19 ,
    \my_empty_reg[7]_20 ,
    \my_empty_reg[7]_21 ,
    \input_[9].iserdes_dq_.iserdesdq_2 ,
    LD0_13,
    CLKB0_13,
    \pi_dqs_found_lanes_r1_reg[11] ,
    \pi_dqs_found_lanes_r1_reg[11]_0 ,
    \pi_dqs_found_lanes_r1_reg[11]_1 ,
    \pi_dqs_found_lanes_r1_reg[11]_2 ,
    ififo_rst_reg_2,
    \pi_dqs_found_lanes_r1_reg[11]_3 ,
    \po_counter_read_val_reg[8]_9 ,
    \po_counter_read_val_reg[8]_10 ,
    \po_counter_read_val_reg[8]_11 ,
    \my_empty_reg[7]_22 ,
    \my_empty_reg[7]_23 ,
    \my_empty_reg[7]_24 ,
    \my_empty_reg[7]_25 ,
    \my_empty_reg[7]_26 ,
    \my_empty_reg[7]_27 ,
    \my_empty_reg[7]_28 ,
    \my_empty_reg[7]_29 ,
    phy_ctl_mstr_empty,
    phy_ctl_wr_i2,
    pll_locked,
    phy_read_calib,
    phy_mc_ctl_full_r_reg,
    phy_write_calib,
    PHYCTLWD,
    RST0,
    rst_primitives_reg_0,
    rst_out_reg_1,
    SR,
    \rclk_delay_reg[11]_0 ,
    phy_data_wr_en,
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0] ,
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ,
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ,
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ,
    \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_rise0_r_reg[5] ,
    \gen_mux_rd[6].mux_rd_rise0_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_rise0_r_reg[7] ,
    \gen_mux_rd[0].mux_rd_fall0_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1] ,
    \gen_mux_rd[2].mux_rd_fall0_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3] ,
    \gen_mux_rd[4].mux_rd_fall0_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5] ,
    \gen_mux_rd[6].mux_rd_fall0_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7] ,
    \gen_mux_rd[0].mux_rd_rise1_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1] ,
    \gen_mux_rd[2].mux_rd_rise1_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3] ,
    \gen_mux_rd[4].mux_rd_rise1_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5] ,
    \gen_mux_rd[6].mux_rd_rise1_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7] ,
    \gen_mux_rd[0].mux_rd_fall1_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1] ,
    \gen_mux_rd[2].mux_rd_fall1_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3] ,
    \gen_mux_rd[4].mux_rd_fall1_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5] ,
    \gen_mux_rd[6].mux_rd_fall1_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7] ,
    \gen_mux_rd[0].mux_rd_rise2_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1] ,
    \gen_mux_rd[2].mux_rd_rise2_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3] ,
    \gen_mux_rd[4].mux_rd_rise2_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5] ,
    \gen_mux_rd[6].mux_rd_rise2_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7] ,
    \gen_mux_rd[0].mux_rd_fall2_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1] ,
    \gen_mux_rd[2].mux_rd_fall2_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3] ,
    \gen_mux_rd[4].mux_rd_fall2_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5] ,
    \gen_mux_rd[6].mux_rd_fall2_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7] ,
    \gen_mux_rd[0].mux_rd_rise3_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1] ,
    \gen_mux_rd[2].mux_rd_rise3_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3] ,
    \gen_mux_rd[4].mux_rd_rise3_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5] ,
    \gen_mux_rd[6].mux_rd_rise3_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7] ,
    \gen_mux_rd[0].mux_rd_fall3_r_reg[0] ,
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1] ,
    \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3] ,
    \gen_mux_rd[4].mux_rd_fall3_r_reg[4] ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5] ,
    \gen_mux_rd[6].mux_rd_fall3_r_reg[6] ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7] ,
    out_fifo,
    out_fifo_0,
    out_fifo_1,
    \gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ,
    \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]_0 ,
    \gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ,
    \gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ,
    \gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ,
    \gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ,
    \gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ,
    \gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ,
    \gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ,
    \gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ,
    \gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ,
    \gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ,
    \gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ,
    \gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ,
    \gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ,
    \gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ,
    \gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ,
    \gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ,
    \gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ,
    \gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ,
    \gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ,
    \gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ,
    \gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ,
    \gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ,
    \gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ,
    \gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ,
    \gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ,
    \gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ,
    \gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ,
    \gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ,
    \gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ,
    \gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ,
    \gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ,
    \gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ,
    \gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ,
    \gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ,
    \gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ,
    \gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ,
    \gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ,
    \gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ,
    \gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ,
    \gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ,
    \gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ,
    \gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ,
    \gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ,
    \gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ,
    \gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ,
    \gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ,
    \gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ,
    \gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ,
    \gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ,
    \gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ,
    \gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ,
    \gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ,
    \gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ,
    \gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ,
    \gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ,
    \gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ,
    \gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ,
    \gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ,
    \gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ,
    \gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ,
    \gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ,
    \gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ,
    \gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ,
    out_fifo_i_75__0,
    out_fifo_i_75__1,
    out_fifo_i_75__2,
    out_fifo_i_75__3,
    \my_full_reg[1] ,
    \my_full_reg[1]_0 ,
    calib_sel);
  output out_dqs_0;
  output ts_dqs_0;
  output A_rst_primitives_reg_0;
  output [35:0]mem_dq_out;
  output [35:0]mem_dq_ts;
  output [3:0]in0;
  output idelay_ld_rst_3;
  output out_dqs_1;
  output ts_dqs_1;
  output A_rst_primitives_reg_1;
  output idelay_ld_rst_4;
  output out_dqs_2;
  output ts_dqs_2;
  output A_rst_primitives_reg_2;
  output idelay_ld_rst_5;
  output out_dqs_3;
  output ts_dqs_3;
  output A_rst_primitives_reg_3;
  output idelay_ld_rst_6;
  output [0:0]_phy_ctl_full_p__0;
  output phy_ctl_wr_i2_reg;
  output [0:0]ref_dll_lock_w__0;
  output rst_primitives;
  output [0:0]mcGo_w;
  output rst_out_reg_0;
  output rclk_delay_11;
  output \my_empty_reg[1] ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  output \my_empty_reg[1]_0 ;
  output \my_empty_reg[1]_1 ;
  output \my_empty_reg[1]_2 ;
  output \rd_mux_sel_r_reg[0] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ;
  output \rd_mux_sel_r_reg[0]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ;
  output \rd_mux_sel_r_reg[0]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ;
  output \rd_mux_sel_r_reg[0]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ;
  output \rd_mux_sel_r_reg[0]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ;
  output \rd_mux_sel_r_reg[0]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ;
  output \rd_mux_sel_r_reg[0]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ;
  output \rd_mux_sel_r_reg[0]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1 ;
  output \rd_mux_sel_r_reg[0]_7 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ;
  output \rd_mux_sel_r_reg[0]_8 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ;
  output \rd_mux_sel_r_reg[0]_9 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ;
  output \rd_mux_sel_r_reg[0]_10 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ;
  output \rd_mux_sel_r_reg[0]_11 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ;
  output \rd_mux_sel_r_reg[0]_12 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ;
  output \rd_mux_sel_r_reg[0]_13 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ;
  output \rd_mux_sel_r_reg[0]_14 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1 ;
  output \rd_mux_sel_r_reg[0]_15 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ;
  output \rd_mux_sel_r_reg[0]_16 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ;
  output \rd_mux_sel_r_reg[0]_17 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ;
  output \rd_mux_sel_r_reg[0]_18 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ;
  output \rd_mux_sel_r_reg[0]_19 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ;
  output \rd_mux_sel_r_reg[0]_20 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ;
  output \rd_mux_sel_r_reg[0]_21 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ;
  output \rd_mux_sel_r_reg[0]_22 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1 ;
  output \rd_mux_sel_r_reg[0]_23 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ;
  output \rd_mux_sel_r_reg[0]_24 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ;
  output \rd_mux_sel_r_reg[0]_25 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ;
  output \rd_mux_sel_r_reg[0]_26 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ;
  output \rd_mux_sel_r_reg[0]_27 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ;
  output \rd_mux_sel_r_reg[0]_28 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ;
  output \rd_mux_sel_r_reg[0]_29 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ;
  output \rd_mux_sel_r_reg[0]_30 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1 ;
  output \rd_mux_sel_r_reg[0]_31 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ;
  output \rd_mux_sel_r_reg[0]_32 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ;
  output \rd_mux_sel_r_reg[0]_33 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ;
  output \rd_mux_sel_r_reg[0]_34 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ;
  output \rd_mux_sel_r_reg[0]_35 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ;
  output \rd_mux_sel_r_reg[0]_36 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ;
  output \rd_mux_sel_r_reg[0]_37 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ;
  output \rd_mux_sel_r_reg[0]_38 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1 ;
  output \rd_mux_sel_r_reg[0]_39 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ;
  output \rd_mux_sel_r_reg[0]_40 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ;
  output \rd_mux_sel_r_reg[0]_41 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ;
  output \rd_mux_sel_r_reg[0]_42 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ;
  output \rd_mux_sel_r_reg[0]_43 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ;
  output \rd_mux_sel_r_reg[0]_44 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ;
  output \rd_mux_sel_r_reg[0]_45 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ;
  output \rd_mux_sel_r_reg[0]_46 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1 ;
  output \rd_mux_sel_r_reg[0]_47 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ;
  output \rd_mux_sel_r_reg[0]_48 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ;
  output \rd_mux_sel_r_reg[0]_49 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ;
  output \rd_mux_sel_r_reg[0]_50 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ;
  output \rd_mux_sel_r_reg[0]_51 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ;
  output \rd_mux_sel_r_reg[0]_52 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ;
  output \rd_mux_sel_r_reg[0]_53 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ;
  output \rd_mux_sel_r_reg[0]_54 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1 ;
  output \rd_mux_sel_r_reg[0]_55 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ;
  output \rd_mux_sel_r_reg[0]_56 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ;
  output \rd_mux_sel_r_reg[0]_57 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ;
  output \rd_mux_sel_r_reg[0]_58 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ;
  output \rd_mux_sel_r_reg[0]_59 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ;
  output \rd_mux_sel_r_reg[0]_60 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ;
  output \rd_mux_sel_r_reg[0]_61 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ;
  output \rd_mux_sel_r_reg[0]_62 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1 ;
  output A_rst_primitives_reg_4;
  output \rd_mux_sel_r_reg[2] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ;
  output \rd_mux_sel_r_reg[2]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ;
  output \rd_mux_sel_r_reg[2]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ;
  output \rd_mux_sel_r_reg[2]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ;
  output \rd_mux_sel_r_reg[2]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ;
  output \rd_mux_sel_r_reg[2]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ;
  output \rd_mux_sel_r_reg[2]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ;
  output \rd_mux_sel_r_reg[2]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_2 ;
  output \rd_mux_sel_r_reg[2]_7 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2 ;
  output \rd_mux_sel_r_reg[2]_8 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2 ;
  output \rd_mux_sel_r_reg[2]_9 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2 ;
  output \rd_mux_sel_r_reg[2]_10 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2 ;
  output \rd_mux_sel_r_reg[2]_11 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2 ;
  output \rd_mux_sel_r_reg[2]_12 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2 ;
  output \rd_mux_sel_r_reg[2]_13 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ;
  output \rd_mux_sel_r_reg[2]_14 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_2 ;
  output \rd_mux_sel_r_reg[2]_15 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2 ;
  output \rd_mux_sel_r_reg[2]_16 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2 ;
  output \rd_mux_sel_r_reg[2]_17 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2 ;
  output \rd_mux_sel_r_reg[2]_18 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2 ;
  output \rd_mux_sel_r_reg[2]_19 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2 ;
  output \rd_mux_sel_r_reg[2]_20 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2 ;
  output \rd_mux_sel_r_reg[2]_21 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ;
  output \rd_mux_sel_r_reg[2]_22 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_2 ;
  output \rd_mux_sel_r_reg[2]_23 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2 ;
  output \rd_mux_sel_r_reg[2]_24 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2 ;
  output \rd_mux_sel_r_reg[2]_25 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2 ;
  output \rd_mux_sel_r_reg[2]_26 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2 ;
  output \rd_mux_sel_r_reg[2]_27 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2 ;
  output \rd_mux_sel_r_reg[2]_28 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2 ;
  output \rd_mux_sel_r_reg[2]_29 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ;
  output \rd_mux_sel_r_reg[2]_30 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_2 ;
  output \rd_mux_sel_r_reg[2]_31 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2 ;
  output \rd_mux_sel_r_reg[2]_32 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2 ;
  output \rd_mux_sel_r_reg[2]_33 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2 ;
  output \rd_mux_sel_r_reg[2]_34 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2 ;
  output \rd_mux_sel_r_reg[2]_35 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2 ;
  output \rd_mux_sel_r_reg[2]_36 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2 ;
  output \rd_mux_sel_r_reg[2]_37 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ;
  output \rd_mux_sel_r_reg[2]_38 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_2 ;
  output \rd_mux_sel_r_reg[2]_39 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2 ;
  output \rd_mux_sel_r_reg[2]_40 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2 ;
  output \rd_mux_sel_r_reg[2]_41 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2 ;
  output \rd_mux_sel_r_reg[2]_42 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2 ;
  output \rd_mux_sel_r_reg[2]_43 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2 ;
  output \rd_mux_sel_r_reg[2]_44 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2 ;
  output \rd_mux_sel_r_reg[2]_45 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ;
  output \rd_mux_sel_r_reg[2]_46 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_2 ;
  output \rd_mux_sel_r_reg[2]_47 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2 ;
  output \rd_mux_sel_r_reg[2]_48 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2 ;
  output \rd_mux_sel_r_reg[2]_49 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2 ;
  output \rd_mux_sel_r_reg[2]_50 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2 ;
  output \rd_mux_sel_r_reg[2]_51 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2 ;
  output \rd_mux_sel_r_reg[2]_52 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2 ;
  output \rd_mux_sel_r_reg[2]_53 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ;
  output \rd_mux_sel_r_reg[2]_54 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_2 ;
  output \rd_mux_sel_r_reg[2]_55 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2 ;
  output \rd_mux_sel_r_reg[2]_56 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2 ;
  output \rd_mux_sel_r_reg[2]_57 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2 ;
  output \rd_mux_sel_r_reg[2]_58 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2 ;
  output \rd_mux_sel_r_reg[2]_59 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2 ;
  output \rd_mux_sel_r_reg[2]_60 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2 ;
  output \rd_mux_sel_r_reg[2]_61 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ;
  output \rd_mux_sel_r_reg[2]_62 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2 ;
  output p_0_out;
  output \po_stg2_wrcal_cnt_reg[2] ;
  output \po_stg2_wrcal_cnt_reg[2]_0 ;
  output \po_stg2_wrcal_cnt_reg[2]_1 ;
  output \po_stg2_wrcal_cnt_reg[2]_2 ;
  output \po_stg2_wrcal_cnt_reg[2]_3 ;
  output \po_stg2_wrcal_cnt_reg[2]_4 ;
  output \po_stg2_wrcal_cnt_reg[2]_5 ;
  output \po_stg2_wrcal_cnt_reg[2]_6 ;
  output \po_stg2_wrcal_cnt_reg[2]_7 ;
  output \po_stg2_wrcal_cnt_reg[2]_8 ;
  output \po_stg2_wrcal_cnt_reg[2]_9 ;
  output \po_stg2_wrcal_cnt_reg[2]_10 ;
  output \po_stg2_wrcal_cnt_reg[2]_11 ;
  output \po_stg2_wrcal_cnt_reg[2]_12 ;
  output \po_stg2_wrcal_cnt_reg[2]_13 ;
  output \po_stg2_wrcal_cnt_reg[2]_14 ;
  output \po_stg2_wrcal_cnt_reg[2]_15 ;
  output \po_stg2_wrcal_cnt_reg[2]_16 ;
  output \po_stg2_wrcal_cnt_reg[2]_17 ;
  output \po_stg2_wrcal_cnt_reg[2]_18 ;
  output \po_stg2_wrcal_cnt_reg[2]_19 ;
  output \po_stg2_wrcal_cnt_reg[2]_20 ;
  output \po_stg2_wrcal_cnt_reg[2]_21 ;
  output \po_stg2_wrcal_cnt_reg[2]_22 ;
  output \po_stg2_wrcal_cnt_reg[2]_23 ;
  output \po_stg2_wrcal_cnt_reg[2]_24 ;
  output \po_stg2_wrcal_cnt_reg[2]_25 ;
  output \po_stg2_wrcal_cnt_reg[2]_26 ;
  output \po_stg2_wrcal_cnt_reg[2]_27 ;
  output \po_stg2_wrcal_cnt_reg[2]_28 ;
  output \po_stg2_wrcal_cnt_reg[2]_29 ;
  output \po_stg2_wrcal_cnt_reg[2]_30 ;
  output \po_stg2_wrcal_cnt_reg[2]_31 ;
  output \po_stg2_wrcal_cnt_reg[2]_32 ;
  output \po_stg2_wrcal_cnt_reg[2]_33 ;
  output \po_stg2_wrcal_cnt_reg[2]_34 ;
  output \po_stg2_wrcal_cnt_reg[2]_35 ;
  output \po_stg2_wrcal_cnt_reg[2]_36 ;
  output \po_stg2_wrcal_cnt_reg[2]_37 ;
  output \po_stg2_wrcal_cnt_reg[2]_38 ;
  output \po_stg2_wrcal_cnt_reg[2]_39 ;
  output \po_stg2_wrcal_cnt_reg[2]_40 ;
  output \po_stg2_wrcal_cnt_reg[2]_41 ;
  output \po_stg2_wrcal_cnt_reg[2]_42 ;
  output \po_stg2_wrcal_cnt_reg[2]_43 ;
  output \po_stg2_wrcal_cnt_reg[2]_44 ;
  output \po_stg2_wrcal_cnt_reg[2]_45 ;
  output \po_stg2_wrcal_cnt_reg[2]_46 ;
  output \po_stg2_wrcal_cnt_reg[2]_47 ;
  output \po_stg2_wrcal_cnt_reg[2]_48 ;
  output \po_stg2_wrcal_cnt_reg[2]_49 ;
  output \po_stg2_wrcal_cnt_reg[2]_50 ;
  output \po_stg2_wrcal_cnt_reg[2]_51 ;
  output \po_stg2_wrcal_cnt_reg[2]_52 ;
  output \po_stg2_wrcal_cnt_reg[2]_53 ;
  output \po_stg2_wrcal_cnt_reg[2]_54 ;
  output \po_stg2_wrcal_cnt_reg[2]_55 ;
  output \po_stg2_wrcal_cnt_reg[2]_56 ;
  output \po_stg2_wrcal_cnt_reg[2]_57 ;
  output \po_stg2_wrcal_cnt_reg[2]_58 ;
  output \po_stg2_wrcal_cnt_reg[2]_59 ;
  output \po_stg2_wrcal_cnt_reg[2]_60 ;
  output \po_stg2_wrcal_cnt_reg[2]_61 ;
  output [63:0]\rd_ptr_reg[3] ;
  output [63:0]\rd_ptr_reg[3]_0 ;
  output [63:0]\rd_ptr_reg[3]_1 ;
  output [63:0]\rd_ptr_reg[3]_2 ;
  output \entry_cnt_reg[4] ;
  output \entry_cnt_reg[4]_0 ;
  output [8:0]Q;
  output [5:0]\pi_counter_read_val_reg[5]_0 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  output \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;
  output [0:0]if_empty_v;
  input \entry_cnt_reg[4]_1 ;
  input \input_[9].iserdes_dq_.iserdesdq ;
  input [31:0]mem_dq_in;
  input idelay_inc;
  input LD0_10;
  input CLKB0_10;
  input \pi_dqs_found_lanes_r1_reg[8] ;
  input \pi_dqs_found_lanes_r1_reg[8]_0 ;
  input \pi_dqs_found_lanes_r1_reg[8]_1 ;
  input \pi_dqs_found_lanes_r1_reg[8]_2 ;
  input freq_refclk;
  input mem_refclk;
  input [3:0]mem_dqs_in;
  input ififo_rst_reg;
  input sync_pulse;
  input [5:0]\pi_dqs_found_lanes_r1_reg[8]_3 ;
  input \po_counter_read_val_reg[8]_0 ;
  input \po_counter_read_val_reg[8]_1 ;
  input \po_counter_read_val_reg[8]_2 ;
  input [7:0]\my_empty_reg[7] ;
  input [7:0]D2;
  input [7:0]\my_empty_reg[7]_0 ;
  input [7:0]\my_empty_reg[7]_1 ;
  input [7:0]\my_empty_reg[7]_2 ;
  input [7:0]\my_empty_reg[7]_3 ;
  input [7:0]\my_empty_reg[7]_4 ;
  input [7:0]\my_empty_reg[7]_5 ;
  input phy_if_reset;
  input \input_[9].iserdes_dq_.iserdesdq_0 ;
  input LD0_11;
  input CLKB0_11;
  input \pi_dqs_found_lanes_r1_reg[9] ;
  input \pi_dqs_found_lanes_r1_reg[9]_0 ;
  input \pi_dqs_found_lanes_r1_reg[9]_1 ;
  input \pi_dqs_found_lanes_r1_reg[9]_2 ;
  input ififo_rst_reg_0;
  input [5:0]\pi_dqs_found_lanes_r1_reg[9]_3 ;
  input \po_counter_read_val_reg[8]_3 ;
  input \po_counter_read_val_reg[8]_4 ;
  input \po_counter_read_val_reg[8]_5 ;
  input [7:0]\my_empty_reg[7]_6 ;
  input [7:0]\my_empty_reg[7]_7 ;
  input [7:0]\my_empty_reg[7]_8 ;
  input [7:0]\my_empty_reg[7]_9 ;
  input [7:0]\my_empty_reg[7]_10 ;
  input [7:0]\my_empty_reg[7]_11 ;
  input [7:0]\my_empty_reg[7]_12 ;
  input [7:0]\my_empty_reg[7]_13 ;
  input \input_[9].iserdes_dq_.iserdesdq_1 ;
  input LD0_12;
  input CLKB0_12;
  input \pi_dqs_found_lanes_r1_reg[10] ;
  input \pi_dqs_found_lanes_r1_reg[10]_0 ;
  input \pi_dqs_found_lanes_r1_reg[10]_1 ;
  input \pi_dqs_found_lanes_r1_reg[10]_2 ;
  input ififo_rst_reg_1;
  input [5:0]\pi_dqs_found_lanes_r1_reg[10]_3 ;
  input \po_counter_read_val_reg[8]_6 ;
  input \po_counter_read_val_reg[8]_7 ;
  input \po_counter_read_val_reg[8]_8 ;
  input [7:0]\my_empty_reg[7]_14 ;
  input [7:0]\my_empty_reg[7]_15 ;
  input [7:0]\my_empty_reg[7]_16 ;
  input [7:0]\my_empty_reg[7]_17 ;
  input [7:0]\my_empty_reg[7]_18 ;
  input [7:0]\my_empty_reg[7]_19 ;
  input [7:0]\my_empty_reg[7]_20 ;
  input [7:0]\my_empty_reg[7]_21 ;
  input \input_[9].iserdes_dq_.iserdesdq_2 ;
  input LD0_13;
  input CLKB0_13;
  input \pi_dqs_found_lanes_r1_reg[11] ;
  input \pi_dqs_found_lanes_r1_reg[11]_0 ;
  input \pi_dqs_found_lanes_r1_reg[11]_1 ;
  input \pi_dqs_found_lanes_r1_reg[11]_2 ;
  input ififo_rst_reg_2;
  input [5:0]\pi_dqs_found_lanes_r1_reg[11]_3 ;
  input \po_counter_read_val_reg[8]_9 ;
  input \po_counter_read_val_reg[8]_10 ;
  input \po_counter_read_val_reg[8]_11 ;
  input [7:0]\my_empty_reg[7]_22 ;
  input [7:0]\my_empty_reg[7]_23 ;
  input [7:0]\my_empty_reg[7]_24 ;
  input [7:0]\my_empty_reg[7]_25 ;
  input [7:0]\my_empty_reg[7]_26 ;
  input [7:0]\my_empty_reg[7]_27 ;
  input [7:0]\my_empty_reg[7]_28 ;
  input [7:0]\my_empty_reg[7]_29 ;
  input phy_ctl_mstr_empty;
  input phy_ctl_wr_i2;
  input pll_locked;
  input phy_read_calib;
  input phy_mc_ctl_full_r_reg;
  input phy_write_calib;
  input [10:0]PHYCTLWD;
  input RST0;
  input rst_primitives_reg_0;
  input rst_out_reg_1;
  input [0:0]SR;
  input \rclk_delay_reg[11]_0 ;
  input phy_data_wr_en;
  input [1:0]\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;
  input \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ;
  input \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;
  input \gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;
  input \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  input \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;
  input \gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;
  input \gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;
  input \gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;
  input \gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;
  input \gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  input \gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;
  input \gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  input \gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;
  input \gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  input \gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;
  input \gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  input \gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;
  input \gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  input \gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;
  input \gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  input \gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;
  input \gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  input \gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;
  input \gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  input \gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;
  input \gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  input \gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;
  input \gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  input \gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;
  input \gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  input \gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;
  input \gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  input \gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;
  input \gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  input \gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;
  input \gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  input \gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;
  input \gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  input \gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;
  input \gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  input \gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;
  input \gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  input \gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;
  input \gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  input \gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;
  input \gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  input \gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;
  input \gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  input \gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;
  input \gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  input \gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;
  input \gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  input \gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;
  input \gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  input \gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;
  input \gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  input \gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;
  input \gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  input \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  input \gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  input \gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;
  input \gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  input \gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;
  input \gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  input out_fifo;
  input [31:0]out_fifo_0;
  input out_fifo_1;
  input [2:0]\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ;
  input \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]_0 ;
  input \gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ;
  input \gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ;
  input \gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ;
  input \gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ;
  input \gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ;
  input \gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ;
  input \gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ;
  input \gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ;
  input \gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ;
  input \gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ;
  input \gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ;
  input \gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ;
  input \gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ;
  input \gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ;
  input \gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ;
  input \gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ;
  input \gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ;
  input \gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ;
  input \gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ;
  input \gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ;
  input \gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ;
  input \gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ;
  input \gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ;
  input \gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ;
  input \gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ;
  input \gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ;
  input \gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ;
  input \gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ;
  input \gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ;
  input \gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ;
  input \gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ;
  input \gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ;
  input \gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ;
  input \gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ;
  input \gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ;
  input \gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ;
  input \gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ;
  input \gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ;
  input \gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ;
  input \gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ;
  input \gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ;
  input \gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ;
  input \gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ;
  input \gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ;
  input \gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ;
  input \gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ;
  input \gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ;
  input \gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ;
  input \gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ;
  input \gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ;
  input \gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ;
  input \gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ;
  input \gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ;
  input \gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ;
  input \gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ;
  input \gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ;
  input \gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ;
  input \gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ;
  input \gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ;
  input \gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ;
  input \gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ;
  input \gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ;
  input \gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ;
  input [2:0]\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  input [71:0]out_fifo_i_75__0;
  input [71:0]out_fifo_i_75__1;
  input [71:0]out_fifo_i_75__2;
  input [71:0]out_fifo_i_75__3;
  input \my_full_reg[1] ;
  input \my_full_reg[1]_0 ;
  input [1:0]calib_sel;

  wire [5:0]A_pi_counter_read_val;
  (* async_reg = "true" *) wire A_pi_rst_div2;
  wire [8:0]A_po_counter_read_val;
  wire A_rst_primitives;
  wire A_rst_primitives_reg_0;
  wire A_rst_primitives_reg_1;
  wire A_rst_primitives_reg_2;
  wire A_rst_primitives_reg_3;
  wire A_rst_primitives_reg_4;
  (* async_reg = "true" *) wire B_pi_rst_div2;
  wire B_rclk;
  wire CLKB0_10;
  wire CLKB0_11;
  wire CLKB0_12;
  wire CLKB0_13;
  wire [5:0]C_pi_counter_read_val;
  (* async_reg = "true" *) wire C_pi_rst_div2;
  wire [8:0]C_po_counter_read_val;
  wire [7:0]D2;
  wire [5:0]D_pi_counter_read_val;
  (* async_reg = "true" *) wire D_pi_rst_div2;
  wire [8:0]D_po_counter_read_val;
  wire LD0_10;
  wire LD0_11;
  wire LD0_12;
  wire LD0_13;
  wire [10:0]PHYCTLWD;
  wire [8:0]Q;
  wire RST0;
  wire [0:0]SR;
  wire [0:0]_phy_ctl_full_p__0;
  wire [1:0]calib_sel;
  wire \ddr_byte_lane_A.ddr_byte_lane_A_n_22 ;
  wire \ddr_byte_lane_B.ddr_byte_lane_B_n_157 ;
  wire \ddr_byte_lane_B.ddr_byte_lane_B_n_22 ;
  wire \ddr_byte_lane_B.ddr_byte_lane_B_n_222 ;
  wire \ddr_byte_lane_B.ddr_byte_lane_B_n_223 ;
  wire \ddr_byte_lane_B.ddr_byte_lane_B_n_224 ;
  wire \ddr_byte_lane_B.ddr_byte_lane_B_n_225 ;
  wire \ddr_byte_lane_B.ddr_byte_lane_B_n_226 ;
  wire \ddr_byte_lane_B.ddr_byte_lane_B_n_227 ;
  wire \ddr_byte_lane_B.ddr_byte_lane_B_n_228 ;
  wire \ddr_byte_lane_B.ddr_byte_lane_B_n_229 ;
  wire \ddr_byte_lane_B.ddr_byte_lane_B_n_230 ;
  wire \ddr_byte_lane_B.ddr_byte_lane_B_n_231 ;
  wire \ddr_byte_lane_B.ddr_byte_lane_B_n_232 ;
  wire \ddr_byte_lane_B.ddr_byte_lane_B_n_233 ;
  wire \ddr_byte_lane_B.ddr_byte_lane_B_n_234 ;
  wire \ddr_byte_lane_B.ddr_byte_lane_B_n_235 ;
  wire \ddr_byte_lane_B.ddr_byte_lane_B_n_236 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C_n_106 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C_n_107 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C_n_22 ;
  wire \ddr_byte_lane_C.ddr_byte_lane_C_n_41 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D_n_233 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D_n_235 ;
  wire \ddr_byte_lane_D.ddr_byte_lane_D_n_236 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ;
  wire [0:0]\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ;
  wire [3:0]\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_1 ;
  wire \entry_cnt_reg[4] ;
  wire \entry_cnt_reg[4]_0 ;
  wire \entry_cnt_reg[4]_1 ;
  wire freq_refclk;
  wire \gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;
  wire [2:0]\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]_0 ;
  wire [1:0]\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ;
  wire \gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ;
  wire \gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;
  wire \gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ;
  wire \gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  wire \gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ;
  wire \gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;
  wire \gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ;
  wire \gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  wire \gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ;
  wire \gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;
  wire \gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ;
  wire \gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  wire \gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ;
  wire \gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;
  wire \gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ;
  wire \gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ;
  wire [2:0]\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] ;
  wire idelay_inc;
  wire idelay_ld_rst_3;
  wire idelay_ld_rst_4;
  wire idelay_ld_rst_5;
  wire idelay_ld_rst_6;
  wire [3:3]if_empty_r;
  wire [3:3]if_empty_r_2;
  wire [0:0]if_empty_v;
  wire ififo_rst_reg;
  wire ififo_rst_reg_0;
  wire ififo_rst_reg_1;
  wire ififo_rst_reg_2;
  wire [3:0]in0;
  wire \input_[9].iserdes_dq_.iserdesdq ;
  wire \input_[9].iserdes_dq_.iserdesdq_0 ;
  wire \input_[9].iserdes_dq_.iserdesdq_1 ;
  wire \input_[9].iserdes_dq_.iserdesdq_2 ;
  wire [0:0]mcGo_w;
  wire [31:0]mem_dq_in;
  wire [35:0]mem_dq_out;
  wire [35:0]mem_dq_ts;
  wire [3:0]mem_dqs_in;
  wire mem_refclk;
  wire \my_empty_reg[1] ;
  wire \my_empty_reg[1]_0 ;
  wire \my_empty_reg[1]_1 ;
  wire \my_empty_reg[1]_2 ;
  wire [7:0]\my_empty_reg[7] ;
  wire [7:0]\my_empty_reg[7]_0 ;
  wire [7:0]\my_empty_reg[7]_1 ;
  wire [7:0]\my_empty_reg[7]_10 ;
  wire [7:0]\my_empty_reg[7]_11 ;
  wire [7:0]\my_empty_reg[7]_12 ;
  wire [7:0]\my_empty_reg[7]_13 ;
  wire [7:0]\my_empty_reg[7]_14 ;
  wire [7:0]\my_empty_reg[7]_15 ;
  wire [7:0]\my_empty_reg[7]_16 ;
  wire [7:0]\my_empty_reg[7]_17 ;
  wire [7:0]\my_empty_reg[7]_18 ;
  wire [7:0]\my_empty_reg[7]_19 ;
  wire [7:0]\my_empty_reg[7]_2 ;
  wire [7:0]\my_empty_reg[7]_20 ;
  wire [7:0]\my_empty_reg[7]_21 ;
  wire [7:0]\my_empty_reg[7]_22 ;
  wire [7:0]\my_empty_reg[7]_23 ;
  wire [7:0]\my_empty_reg[7]_24 ;
  wire [7:0]\my_empty_reg[7]_25 ;
  wire [7:0]\my_empty_reg[7]_26 ;
  wire [7:0]\my_empty_reg[7]_27 ;
  wire [7:0]\my_empty_reg[7]_28 ;
  wire [7:0]\my_empty_reg[7]_29 ;
  wire [7:0]\my_empty_reg[7]_3 ;
  wire [7:0]\my_empty_reg[7]_4 ;
  wire [7:0]\my_empty_reg[7]_5 ;
  wire [7:0]\my_empty_reg[7]_6 ;
  wire [7:0]\my_empty_reg[7]_7 ;
  wire [7:0]\my_empty_reg[7]_8 ;
  wire [7:0]\my_empty_reg[7]_9 ;
  wire \my_full_reg[1] ;
  wire \my_full_reg[1]_0 ;
  wire [4:2]\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg ;
  wire [4:2]\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_0 ;
  wire [4:2]\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_3 ;
  wire [4:2]\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_4 ;
  wire out_dqs_0;
  wire out_dqs_1;
  wire out_dqs_2;
  wire out_dqs_3;
  wire out_fifo;
  wire [31:0]out_fifo_0;
  wire out_fifo_1;
  wire [71:0]out_fifo_i_75__0;
  wire [71:0]out_fifo_i_75__1;
  wire [71:0]out_fifo_i_75__2;
  wire [71:0]out_fifo_i_75__3;
  wire p_0_out;
  wire [15:0]phaser_ctl_bus;
  wire phy_control_i_n_0;
  wire phy_control_i_n_1;
  wire phy_control_i_n_14;
  wire phy_control_i_n_15;
  wire phy_control_i_n_16;
  wire phy_control_i_n_17;
  wire phy_ctl_mstr_empty;
  wire phy_ctl_wr_i2;
  wire phy_ctl_wr_i2_reg;
  wire phy_data_wr_en;
  wire [1:0]phy_encalib;
  wire phy_if_reset;
  wire phy_mc_ctl_full_r_reg;
  wire phy_read_calib;
  wire phy_write_calib;
  wire [5:0]\pi_counter_read_val_reg[5]_0 ;
  wire \pi_dqs_found_lanes_r1_reg[10] ;
  wire \pi_dqs_found_lanes_r1_reg[10]_0 ;
  wire \pi_dqs_found_lanes_r1_reg[10]_1 ;
  wire \pi_dqs_found_lanes_r1_reg[10]_2 ;
  wire [5:0]\pi_dqs_found_lanes_r1_reg[10]_3 ;
  wire \pi_dqs_found_lanes_r1_reg[11] ;
  wire \pi_dqs_found_lanes_r1_reg[11]_0 ;
  wire \pi_dqs_found_lanes_r1_reg[11]_1 ;
  wire \pi_dqs_found_lanes_r1_reg[11]_2 ;
  wire [5:0]\pi_dqs_found_lanes_r1_reg[11]_3 ;
  wire \pi_dqs_found_lanes_r1_reg[8] ;
  wire \pi_dqs_found_lanes_r1_reg[8]_0 ;
  wire \pi_dqs_found_lanes_r1_reg[8]_1 ;
  wire \pi_dqs_found_lanes_r1_reg[8]_2 ;
  wire [5:0]\pi_dqs_found_lanes_r1_reg[8]_3 ;
  wire \pi_dqs_found_lanes_r1_reg[9] ;
  wire \pi_dqs_found_lanes_r1_reg[9]_0 ;
  wire \pi_dqs_found_lanes_r1_reg[9]_1 ;
  wire \pi_dqs_found_lanes_r1_reg[9]_2 ;
  wire [5:0]\pi_dqs_found_lanes_r1_reg[9]_3 ;
  wire pll_locked;
  wire \po_counter_read_val_reg[8]_0 ;
  wire \po_counter_read_val_reg[8]_1 ;
  wire \po_counter_read_val_reg[8]_10 ;
  wire \po_counter_read_val_reg[8]_11 ;
  wire \po_counter_read_val_reg[8]_2 ;
  wire \po_counter_read_val_reg[8]_3 ;
  wire \po_counter_read_val_reg[8]_4 ;
  wire \po_counter_read_val_reg[8]_5 ;
  wire \po_counter_read_val_reg[8]_6 ;
  wire \po_counter_read_val_reg[8]_7 ;
  wire \po_counter_read_val_reg[8]_8 ;
  wire \po_counter_read_val_reg[8]_9 ;
  wire \po_stg2_wrcal_cnt_reg[2] ;
  wire \po_stg2_wrcal_cnt_reg[2]_0 ;
  wire \po_stg2_wrcal_cnt_reg[2]_1 ;
  wire \po_stg2_wrcal_cnt_reg[2]_10 ;
  wire \po_stg2_wrcal_cnt_reg[2]_11 ;
  wire \po_stg2_wrcal_cnt_reg[2]_12 ;
  wire \po_stg2_wrcal_cnt_reg[2]_13 ;
  wire \po_stg2_wrcal_cnt_reg[2]_14 ;
  wire \po_stg2_wrcal_cnt_reg[2]_15 ;
  wire \po_stg2_wrcal_cnt_reg[2]_16 ;
  wire \po_stg2_wrcal_cnt_reg[2]_17 ;
  wire \po_stg2_wrcal_cnt_reg[2]_18 ;
  wire \po_stg2_wrcal_cnt_reg[2]_19 ;
  wire \po_stg2_wrcal_cnt_reg[2]_2 ;
  wire \po_stg2_wrcal_cnt_reg[2]_20 ;
  wire \po_stg2_wrcal_cnt_reg[2]_21 ;
  wire \po_stg2_wrcal_cnt_reg[2]_22 ;
  wire \po_stg2_wrcal_cnt_reg[2]_23 ;
  wire \po_stg2_wrcal_cnt_reg[2]_24 ;
  wire \po_stg2_wrcal_cnt_reg[2]_25 ;
  wire \po_stg2_wrcal_cnt_reg[2]_26 ;
  wire \po_stg2_wrcal_cnt_reg[2]_27 ;
  wire \po_stg2_wrcal_cnt_reg[2]_28 ;
  wire \po_stg2_wrcal_cnt_reg[2]_29 ;
  wire \po_stg2_wrcal_cnt_reg[2]_3 ;
  wire \po_stg2_wrcal_cnt_reg[2]_30 ;
  wire \po_stg2_wrcal_cnt_reg[2]_31 ;
  wire \po_stg2_wrcal_cnt_reg[2]_32 ;
  wire \po_stg2_wrcal_cnt_reg[2]_33 ;
  wire \po_stg2_wrcal_cnt_reg[2]_34 ;
  wire \po_stg2_wrcal_cnt_reg[2]_35 ;
  wire \po_stg2_wrcal_cnt_reg[2]_36 ;
  wire \po_stg2_wrcal_cnt_reg[2]_37 ;
  wire \po_stg2_wrcal_cnt_reg[2]_38 ;
  wire \po_stg2_wrcal_cnt_reg[2]_39 ;
  wire \po_stg2_wrcal_cnt_reg[2]_4 ;
  wire \po_stg2_wrcal_cnt_reg[2]_40 ;
  wire \po_stg2_wrcal_cnt_reg[2]_41 ;
  wire \po_stg2_wrcal_cnt_reg[2]_42 ;
  wire \po_stg2_wrcal_cnt_reg[2]_43 ;
  wire \po_stg2_wrcal_cnt_reg[2]_44 ;
  wire \po_stg2_wrcal_cnt_reg[2]_45 ;
  wire \po_stg2_wrcal_cnt_reg[2]_46 ;
  wire \po_stg2_wrcal_cnt_reg[2]_47 ;
  wire \po_stg2_wrcal_cnt_reg[2]_48 ;
  wire \po_stg2_wrcal_cnt_reg[2]_49 ;
  wire \po_stg2_wrcal_cnt_reg[2]_5 ;
  wire \po_stg2_wrcal_cnt_reg[2]_50 ;
  wire \po_stg2_wrcal_cnt_reg[2]_51 ;
  wire \po_stg2_wrcal_cnt_reg[2]_52 ;
  wire \po_stg2_wrcal_cnt_reg[2]_53 ;
  wire \po_stg2_wrcal_cnt_reg[2]_54 ;
  wire \po_stg2_wrcal_cnt_reg[2]_55 ;
  wire \po_stg2_wrcal_cnt_reg[2]_56 ;
  wire \po_stg2_wrcal_cnt_reg[2]_57 ;
  wire \po_stg2_wrcal_cnt_reg[2]_58 ;
  wire \po_stg2_wrcal_cnt_reg[2]_59 ;
  wire \po_stg2_wrcal_cnt_reg[2]_6 ;
  wire \po_stg2_wrcal_cnt_reg[2]_60 ;
  wire \po_stg2_wrcal_cnt_reg[2]_61 ;
  wire \po_stg2_wrcal_cnt_reg[2]_7 ;
  wire \po_stg2_wrcal_cnt_reg[2]_8 ;
  wire \po_stg2_wrcal_cnt_reg[2]_9 ;
  wire rclk_delay_11;
  wire \rclk_delay_reg[10]_srl11_n_0 ;
  wire \rclk_delay_reg[11]_0 ;
  wire \rd_mux_sel_r_reg[0] ;
  wire \rd_mux_sel_r_reg[0]_0 ;
  wire \rd_mux_sel_r_reg[0]_1 ;
  wire \rd_mux_sel_r_reg[0]_10 ;
  wire \rd_mux_sel_r_reg[0]_11 ;
  wire \rd_mux_sel_r_reg[0]_12 ;
  wire \rd_mux_sel_r_reg[0]_13 ;
  wire \rd_mux_sel_r_reg[0]_14 ;
  wire \rd_mux_sel_r_reg[0]_15 ;
  wire \rd_mux_sel_r_reg[0]_16 ;
  wire \rd_mux_sel_r_reg[0]_17 ;
  wire \rd_mux_sel_r_reg[0]_18 ;
  wire \rd_mux_sel_r_reg[0]_19 ;
  wire \rd_mux_sel_r_reg[0]_2 ;
  wire \rd_mux_sel_r_reg[0]_20 ;
  wire \rd_mux_sel_r_reg[0]_21 ;
  wire \rd_mux_sel_r_reg[0]_22 ;
  wire \rd_mux_sel_r_reg[0]_23 ;
  wire \rd_mux_sel_r_reg[0]_24 ;
  wire \rd_mux_sel_r_reg[0]_25 ;
  wire \rd_mux_sel_r_reg[0]_26 ;
  wire \rd_mux_sel_r_reg[0]_27 ;
  wire \rd_mux_sel_r_reg[0]_28 ;
  wire \rd_mux_sel_r_reg[0]_29 ;
  wire \rd_mux_sel_r_reg[0]_3 ;
  wire \rd_mux_sel_r_reg[0]_30 ;
  wire \rd_mux_sel_r_reg[0]_31 ;
  wire \rd_mux_sel_r_reg[0]_32 ;
  wire \rd_mux_sel_r_reg[0]_33 ;
  wire \rd_mux_sel_r_reg[0]_34 ;
  wire \rd_mux_sel_r_reg[0]_35 ;
  wire \rd_mux_sel_r_reg[0]_36 ;
  wire \rd_mux_sel_r_reg[0]_37 ;
  wire \rd_mux_sel_r_reg[0]_38 ;
  wire \rd_mux_sel_r_reg[0]_39 ;
  wire \rd_mux_sel_r_reg[0]_4 ;
  wire \rd_mux_sel_r_reg[0]_40 ;
  wire \rd_mux_sel_r_reg[0]_41 ;
  wire \rd_mux_sel_r_reg[0]_42 ;
  wire \rd_mux_sel_r_reg[0]_43 ;
  wire \rd_mux_sel_r_reg[0]_44 ;
  wire \rd_mux_sel_r_reg[0]_45 ;
  wire \rd_mux_sel_r_reg[0]_46 ;
  wire \rd_mux_sel_r_reg[0]_47 ;
  wire \rd_mux_sel_r_reg[0]_48 ;
  wire \rd_mux_sel_r_reg[0]_49 ;
  wire \rd_mux_sel_r_reg[0]_5 ;
  wire \rd_mux_sel_r_reg[0]_50 ;
  wire \rd_mux_sel_r_reg[0]_51 ;
  wire \rd_mux_sel_r_reg[0]_52 ;
  wire \rd_mux_sel_r_reg[0]_53 ;
  wire \rd_mux_sel_r_reg[0]_54 ;
  wire \rd_mux_sel_r_reg[0]_55 ;
  wire \rd_mux_sel_r_reg[0]_56 ;
  wire \rd_mux_sel_r_reg[0]_57 ;
  wire \rd_mux_sel_r_reg[0]_58 ;
  wire \rd_mux_sel_r_reg[0]_59 ;
  wire \rd_mux_sel_r_reg[0]_6 ;
  wire \rd_mux_sel_r_reg[0]_60 ;
  wire \rd_mux_sel_r_reg[0]_61 ;
  wire \rd_mux_sel_r_reg[0]_62 ;
  wire \rd_mux_sel_r_reg[0]_7 ;
  wire \rd_mux_sel_r_reg[0]_8 ;
  wire \rd_mux_sel_r_reg[0]_9 ;
  wire \rd_mux_sel_r_reg[2] ;
  wire \rd_mux_sel_r_reg[2]_0 ;
  wire \rd_mux_sel_r_reg[2]_1 ;
  wire \rd_mux_sel_r_reg[2]_10 ;
  wire \rd_mux_sel_r_reg[2]_11 ;
  wire \rd_mux_sel_r_reg[2]_12 ;
  wire \rd_mux_sel_r_reg[2]_13 ;
  wire \rd_mux_sel_r_reg[2]_14 ;
  wire \rd_mux_sel_r_reg[2]_15 ;
  wire \rd_mux_sel_r_reg[2]_16 ;
  wire \rd_mux_sel_r_reg[2]_17 ;
  wire \rd_mux_sel_r_reg[2]_18 ;
  wire \rd_mux_sel_r_reg[2]_19 ;
  wire \rd_mux_sel_r_reg[2]_2 ;
  wire \rd_mux_sel_r_reg[2]_20 ;
  wire \rd_mux_sel_r_reg[2]_21 ;
  wire \rd_mux_sel_r_reg[2]_22 ;
  wire \rd_mux_sel_r_reg[2]_23 ;
  wire \rd_mux_sel_r_reg[2]_24 ;
  wire \rd_mux_sel_r_reg[2]_25 ;
  wire \rd_mux_sel_r_reg[2]_26 ;
  wire \rd_mux_sel_r_reg[2]_27 ;
  wire \rd_mux_sel_r_reg[2]_28 ;
  wire \rd_mux_sel_r_reg[2]_29 ;
  wire \rd_mux_sel_r_reg[2]_3 ;
  wire \rd_mux_sel_r_reg[2]_30 ;
  wire \rd_mux_sel_r_reg[2]_31 ;
  wire \rd_mux_sel_r_reg[2]_32 ;
  wire \rd_mux_sel_r_reg[2]_33 ;
  wire \rd_mux_sel_r_reg[2]_34 ;
  wire \rd_mux_sel_r_reg[2]_35 ;
  wire \rd_mux_sel_r_reg[2]_36 ;
  wire \rd_mux_sel_r_reg[2]_37 ;
  wire \rd_mux_sel_r_reg[2]_38 ;
  wire \rd_mux_sel_r_reg[2]_39 ;
  wire \rd_mux_sel_r_reg[2]_4 ;
  wire \rd_mux_sel_r_reg[2]_40 ;
  wire \rd_mux_sel_r_reg[2]_41 ;
  wire \rd_mux_sel_r_reg[2]_42 ;
  wire \rd_mux_sel_r_reg[2]_43 ;
  wire \rd_mux_sel_r_reg[2]_44 ;
  wire \rd_mux_sel_r_reg[2]_45 ;
  wire \rd_mux_sel_r_reg[2]_46 ;
  wire \rd_mux_sel_r_reg[2]_47 ;
  wire \rd_mux_sel_r_reg[2]_48 ;
  wire \rd_mux_sel_r_reg[2]_49 ;
  wire \rd_mux_sel_r_reg[2]_5 ;
  wire \rd_mux_sel_r_reg[2]_50 ;
  wire \rd_mux_sel_r_reg[2]_51 ;
  wire \rd_mux_sel_r_reg[2]_52 ;
  wire \rd_mux_sel_r_reg[2]_53 ;
  wire \rd_mux_sel_r_reg[2]_54 ;
  wire \rd_mux_sel_r_reg[2]_55 ;
  wire \rd_mux_sel_r_reg[2]_56 ;
  wire \rd_mux_sel_r_reg[2]_57 ;
  wire \rd_mux_sel_r_reg[2]_58 ;
  wire \rd_mux_sel_r_reg[2]_59 ;
  wire \rd_mux_sel_r_reg[2]_6 ;
  wire \rd_mux_sel_r_reg[2]_60 ;
  wire \rd_mux_sel_r_reg[2]_61 ;
  wire \rd_mux_sel_r_reg[2]_62 ;
  wire \rd_mux_sel_r_reg[2]_7 ;
  wire \rd_mux_sel_r_reg[2]_8 ;
  wire \rd_mux_sel_r_reg[2]_9 ;
  wire [63:0]\rd_ptr_reg[3] ;
  wire [63:0]\rd_ptr_reg[3]_0 ;
  wire [63:0]\rd_ptr_reg[3]_1 ;
  wire [63:0]\rd_ptr_reg[3]_2 ;
  wire [0:0]ref_dll_lock_w__0;
  wire rst_out_reg_0;
  wire rst_out_reg_1;
  wire rst_primitives;
  wire rst_primitives_reg_0;
  wire rst_r4;
  wire sync_pulse;
  wire ts_dqs_0;
  wire ts_dqs_1;
  wire ts_dqs_2;
  wire ts_dqs_3;

  FDRE #(
    .INIT(1'b0)) 
    A_rst_primitives_reg
       (.C(\entry_cnt_reg[4]_1 ),
        .CE(1'b1),
        .D(rst_primitives),
        .Q(A_rst_primitives),
        .R(1'b0));
  mig_mig_7series_v4_2_ddr_byte_lane \ddr_byte_lane_A.ddr_byte_lane_A 
       (.A_rst_primitives(A_rst_primitives),
        .A_rst_primitives_reg(A_rst_primitives_reg_0),
        .A_rst_primitives_reg_0(\ddr_byte_lane_A.ddr_byte_lane_A_n_22 ),
        .A_rst_primitives_reg_1(A_po_counter_read_val),
        .CLKB0_10(CLKB0_10),
        .COUNTERREADVAL(A_pi_counter_read_val),
        .D2(D2),
        .LD0_10(LD0_10),
        .PCENABLECALIB(phy_encalib),
        .Q(\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ),
        .freq_refclk(freq_refclk),
        .idelay_inc(idelay_inc),
        .idelay_ld_rst_3(idelay_ld_rst_3),
        .if_empty_r(if_empty_r),
        .ififo_rst_reg_0(ififo_rst_reg),
        .in0(in0[0]),
        .\input_[9].iserdes_dq_.iserdesdq (\input_[9].iserdes_dq_.iserdesdq ),
        .mem_dq_in(mem_dq_in[7:0]),
        .mem_dq_out(mem_dq_out[8:0]),
        .mem_dq_ts(mem_dq_ts[8:0]),
        .mem_dqs_in(mem_dqs_in[0]),
        .mem_refclk(mem_refclk),
        .\my_empty_reg[1] (\my_empty_reg[1] ),
        .\my_empty_reg[4] (\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ),
        .\my_empty_reg[7] (\my_empty_reg[7] ),
        .\my_empty_reg[7]_0 (\my_empty_reg[7]_0 ),
        .\my_empty_reg[7]_1 (\my_empty_reg[7]_1 ),
        .\my_empty_reg[7]_2 (\my_empty_reg[7]_2 ),
        .\my_empty_reg[7]_3 (\my_empty_reg[7]_3 ),
        .\my_empty_reg[7]_4 (\my_empty_reg[7]_4 ),
        .\my_empty_reg[7]_5 (\my_empty_reg[7]_5 ),
        .\my_full_reg[1] (\ddr_byte_lane_D.ddr_byte_lane_D_n_233 ),
        .out_dqs_0(out_dqs_0),
        .out_fifo_0(out_fifo),
        .out_fifo_1({out_fifo_0[28],out_fifo_0[24],out_fifo_0[20],out_fifo_0[16],out_fifo_0[12],out_fifo_0[8],out_fifo_0[4],out_fifo_0[0]}),
        .out_fifo_2(out_fifo_1),
        .out_fifo_i_75__0(out_fifo_i_75__0),
        .phaser_ctl_bus({phaser_ctl_bus[9:8],phaser_ctl_bus[4],phaser_ctl_bus[0]}),
        .phy_data_wr_en(phy_data_wr_en),
        .phy_if_reset(phy_if_reset),
        .\pi_dqs_found_lanes_r1_reg[8] (\pi_dqs_found_lanes_r1_reg[8] ),
        .\pi_dqs_found_lanes_r1_reg[8]_0 (\pi_dqs_found_lanes_r1_reg[8]_0 ),
        .\pi_dqs_found_lanes_r1_reg[8]_1 (\pi_dqs_found_lanes_r1_reg[8]_1 ),
        .\pi_dqs_found_lanes_r1_reg[8]_2 (\pi_dqs_found_lanes_r1_reg[8]_2 ),
        .\pi_dqs_found_lanes_r1_reg[8]_3 (\pi_dqs_found_lanes_r1_reg[8]_3 ),
        .\po_counter_read_val_reg[8] (\po_counter_read_val_reg[8]_0 ),
        .\po_counter_read_val_reg[8]_0 (\po_counter_read_val_reg[8]_1 ),
        .\po_counter_read_val_reg[8]_1 (\po_counter_read_val_reg[8]_2 ),
        .\rd_ptr_reg[3] (\rd_ptr_reg[3] ),
        .rst_r4(rst_r4),
        .sync_pulse(sync_pulse),
        .ts_dqs_0(ts_dqs_0),
        .\wr_ptr_timing_reg[3] (\entry_cnt_reg[4]_1 ));
  mig_mig_7series_v4_2_ddr_byte_lane__parameterized0 \ddr_byte_lane_B.ddr_byte_lane_B 
       (.A_rst_primitives(A_rst_primitives),
        .A_rst_primitives_reg(A_rst_primitives_reg_1),
        .A_rst_primitives_reg_0(\ddr_byte_lane_B.ddr_byte_lane_B_n_22 ),
        .B_rclk(B_rclk),
        .CLKB0_11(CLKB0_11),
        .COUNTERREADVAL(A_pi_counter_read_val),
        .D({\ddr_byte_lane_B.ddr_byte_lane_B_n_222 ,\ddr_byte_lane_B.ddr_byte_lane_B_n_223 ,\ddr_byte_lane_B.ddr_byte_lane_B_n_224 ,\ddr_byte_lane_B.ddr_byte_lane_B_n_225 ,\ddr_byte_lane_B.ddr_byte_lane_B_n_226 ,\ddr_byte_lane_B.ddr_byte_lane_B_n_227 }),
        .LD0_11(LD0_11),
        .PCENABLECALIB(phy_encalib),
        .Q(\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_0 ),
        .calib_sel(calib_sel),
        .\calib_sel_reg[1] ({\ddr_byte_lane_B.ddr_byte_lane_B_n_228 ,\ddr_byte_lane_B.ddr_byte_lane_B_n_229 ,\ddr_byte_lane_B.ddr_byte_lane_B_n_230 ,\ddr_byte_lane_B.ddr_byte_lane_B_n_231 ,\ddr_byte_lane_B.ddr_byte_lane_B_n_232 ,\ddr_byte_lane_B.ddr_byte_lane_B_n_233 ,\ddr_byte_lane_B.ddr_byte_lane_B_n_234 ,\ddr_byte_lane_B.ddr_byte_lane_B_n_235 ,\ddr_byte_lane_B.ddr_byte_lane_B_n_236 }),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (\ddr_byte_lane_B.ddr_byte_lane_B_n_157 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ),
        .\entry_cnt_reg[4] (\entry_cnt_reg[4]_1 ),
        .freq_refclk(freq_refclk),
        .\gen_mux_rd[0].mux_rd_fall0_r_reg[0] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ),
        .\gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0 (\gen_mux_rd[0].mux_rd_fall0_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_fall0_r_reg[0]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ),
        .\gen_mux_rd[0].mux_rd_fall1_r_reg[0] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ),
        .\gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0 (\gen_mux_rd[0].mux_rd_fall1_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_fall1_r_reg[0]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ),
        .\gen_mux_rd[0].mux_rd_fall2_r_reg[0] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ),
        .\gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0 (\gen_mux_rd[0].mux_rd_fall2_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_fall2_r_reg[0]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ),
        .\gen_mux_rd[0].mux_rd_fall3_r_reg[0] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ),
        .\gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0 (\gen_mux_rd[0].mux_rd_fall3_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_fall3_r_reg[0]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ),
        .\gen_mux_rd[0].mux_rd_rise0_r_reg[0] (\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ),
        .\gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1 (\gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ),
        .\gen_mux_rd[0].mux_rd_rise0_r_reg[0]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ),
        .\gen_mux_rd[0].mux_rd_rise1_r_reg[0] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ),
        .\gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0 (\gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_rise1_r_reg[0]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ),
        .\gen_mux_rd[0].mux_rd_rise2_r_reg[0] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ),
        .\gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0 (\gen_mux_rd[0].mux_rd_rise2_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_rise2_r_reg[0]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ),
        .\gen_mux_rd[0].mux_rd_rise3_r_reg[0] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ),
        .\gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0 (\gen_mux_rd[0].mux_rd_rise3_r_reg[0] ),
        .\gen_mux_rd[0].mux_rd_rise3_r_reg[0]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_fall0_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_fall1_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_fall2_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ),
        .\gen_mux_rd[1].mux_rd_fall3_r_reg[1] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ),
        .\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_fall3_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ),
        .\gen_mux_rd[1].mux_rd_rise0_r_reg[1] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ),
        .\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_rise0_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_rise1_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_rise2_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 (\gen_mux_rd[1].mux_rd_rise3_r_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ),
        .\gen_mux_rd[2].mux_rd_fall0_r_reg[2] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ),
        .\gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0 (\gen_mux_rd[2].mux_rd_fall0_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_fall0_r_reg[2]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ),
        .\gen_mux_rd[2].mux_rd_fall1_r_reg[2] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ),
        .\gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0 (\gen_mux_rd[2].mux_rd_fall1_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_fall1_r_reg[2]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ),
        .\gen_mux_rd[2].mux_rd_fall2_r_reg[2] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ),
        .\gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0 (\gen_mux_rd[2].mux_rd_fall2_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_fall2_r_reg[2]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ),
        .\gen_mux_rd[2].mux_rd_fall3_r_reg[2] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ),
        .\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 (\gen_mux_rd[2].mux_rd_fall3_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ),
        .\gen_mux_rd[2].mux_rd_rise0_r_reg[2] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ),
        .\gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 (\gen_mux_rd[2].mux_rd_rise0_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ),
        .\gen_mux_rd[2].mux_rd_rise1_r_reg[2] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ),
        .\gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0 (\gen_mux_rd[2].mux_rd_rise1_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_rise1_r_reg[2]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ),
        .\gen_mux_rd[2].mux_rd_rise2_r_reg[2] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ),
        .\gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0 (\gen_mux_rd[2].mux_rd_rise2_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_rise2_r_reg[2]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ),
        .\gen_mux_rd[2].mux_rd_rise3_r_reg[2] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ),
        .\gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0 (\gen_mux_rd[2].mux_rd_rise3_r_reg[2] ),
        .\gen_mux_rd[2].mux_rd_rise3_r_reg[2]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_fall0_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_fall1_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_fall2_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_fall3_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_rise0_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_rise1_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_rise2_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 (\gen_mux_rd[3].mux_rd_rise3_r_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ),
        .\gen_mux_rd[4].mux_rd_fall0_r_reg[4] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ),
        .\gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0 (\gen_mux_rd[4].mux_rd_fall0_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_fall0_r_reg[4]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ),
        .\gen_mux_rd[4].mux_rd_fall1_r_reg[4] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ),
        .\gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0 (\gen_mux_rd[4].mux_rd_fall1_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_fall1_r_reg[4]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ),
        .\gen_mux_rd[4].mux_rd_fall2_r_reg[4] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ),
        .\gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0 (\gen_mux_rd[4].mux_rd_fall2_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_fall2_r_reg[4]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ),
        .\gen_mux_rd[4].mux_rd_fall3_r_reg[4] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ),
        .\gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0 (\gen_mux_rd[4].mux_rd_fall3_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_fall3_r_reg[4]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ),
        .\gen_mux_rd[4].mux_rd_rise0_r_reg[4] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ),
        .\gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0 (\gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_rise0_r_reg[4]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ),
        .\gen_mux_rd[4].mux_rd_rise1_r_reg[4] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ),
        .\gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0 (\gen_mux_rd[4].mux_rd_rise1_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_rise1_r_reg[4]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ),
        .\gen_mux_rd[4].mux_rd_rise2_r_reg[4] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ),
        .\gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0 (\gen_mux_rd[4].mux_rd_rise2_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_rise2_r_reg[4]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ),
        .\gen_mux_rd[4].mux_rd_rise3_r_reg[4] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ),
        .\gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0 (\gen_mux_rd[4].mux_rd_rise3_r_reg[4] ),
        .\gen_mux_rd[4].mux_rd_rise3_r_reg[4]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_fall0_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_fall1_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_fall2_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_fall3_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ),
        .\gen_mux_rd[5].mux_rd_rise0_r_reg[5] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ),
        .\gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_rise0_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise0_r_reg[5]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_rise1_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_rise2_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 (\gen_mux_rd[5].mux_rd_rise3_r_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ),
        .\gen_mux_rd[6].mux_rd_fall0_r_reg[6] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ),
        .\gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0 (\gen_mux_rd[6].mux_rd_fall0_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_fall0_r_reg[6]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ),
        .\gen_mux_rd[6].mux_rd_fall1_r_reg[6] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ),
        .\gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0 (\gen_mux_rd[6].mux_rd_fall1_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_fall1_r_reg[6]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ),
        .\gen_mux_rd[6].mux_rd_fall2_r_reg[6] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ),
        .\gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0 (\gen_mux_rd[6].mux_rd_fall2_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_fall2_r_reg[6]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ),
        .\gen_mux_rd[6].mux_rd_fall3_r_reg[6] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ),
        .\gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0 (\gen_mux_rd[6].mux_rd_fall3_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_fall3_r_reg[6]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ),
        .\gen_mux_rd[6].mux_rd_rise0_r_reg[6] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ),
        .\gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0 (\gen_mux_rd[6].mux_rd_rise0_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_rise0_r_reg[6]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ),
        .\gen_mux_rd[6].mux_rd_rise1_r_reg[6] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ),
        .\gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0 (\gen_mux_rd[6].mux_rd_rise1_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_rise1_r_reg[6]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ),
        .\gen_mux_rd[6].mux_rd_rise2_r_reg[6] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ),
        .\gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0 (\gen_mux_rd[6].mux_rd_rise2_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_rise2_r_reg[6]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ),
        .\gen_mux_rd[6].mux_rd_rise3_r_reg[6] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ),
        .\gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0 (\gen_mux_rd[6].mux_rd_rise3_r_reg[6] ),
        .\gen_mux_rd[6].mux_rd_rise3_r_reg[6]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_fall0_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1 ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_fall1_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1 ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_fall2_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1 ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_fall3_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1 ),
        .\gen_mux_rd[7].mux_rd_rise0_r_reg[7] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ),
        .\gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_rise0_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise0_r_reg[7]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1 ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_rise1_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1 ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_rise2_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1 ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 (\gen_mux_rd[7].mux_rd_rise3_r_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1 ),
        .idelay_inc(idelay_inc),
        .idelay_ld_rst_4(idelay_ld_rst_4),
        .if_empty_r(if_empty_r_2),
        .ififo_rst_reg_0(ififo_rst_reg_0),
        .in0(in0[1]),
        .\input_[9].iserdes_dq_.iserdesdq (\input_[9].iserdes_dq_.iserdesdq_0 ),
        .mem_dq_in(mem_dq_in[15:8]),
        .mem_dq_out(mem_dq_out[17:9]),
        .mem_dq_ts(mem_dq_ts[17:9]),
        .mem_dqs_in(mem_dqs_in[1]),
        .mem_refclk(mem_refclk),
        .\my_empty_reg[1] (\my_empty_reg[1]_0 ),
        .\my_empty_reg[4] ({\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_1 [3],\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_1 [0]}),
        .\my_empty_reg[7] (\my_empty_reg[7]_6 ),
        .\my_empty_reg[7]_0 (\my_empty_reg[7]_7 ),
        .\my_empty_reg[7]_1 (\my_empty_reg[7]_8 ),
        .\my_empty_reg[7]_2 (\my_empty_reg[7]_9 ),
        .\my_empty_reg[7]_3 (\my_empty_reg[7]_10 ),
        .\my_empty_reg[7]_4 (\my_empty_reg[7]_11 ),
        .\my_empty_reg[7]_5 (\my_empty_reg[7]_12 ),
        .\my_empty_reg[7]_6 (\my_empty_reg[7]_13 ),
        .\my_full_reg[1] (\ddr_byte_lane_D.ddr_byte_lane_D_n_235 ),
        .out_dqs_1(out_dqs_1),
        .out_fifo_0(out_fifo),
        .out_fifo_1({out_fifo_0[29],out_fifo_0[25],out_fifo_0[21],out_fifo_0[17],out_fifo_0[13],out_fifo_0[9],out_fifo_0[5],out_fifo_0[1]}),
        .out_fifo_2(out_fifo_1),
        .out_fifo_i_75__1(out_fifo_i_75__1),
        .phaser_ctl_bus({phaser_ctl_bus[11:10],phaser_ctl_bus[5],phaser_ctl_bus[1]}),
        .phy_data_wr_en(phy_data_wr_en),
        .phy_if_reset(phy_if_reset),
        .\pi_counter_read_val_reg[5] (D_pi_counter_read_val),
        .\pi_counter_read_val_reg[5]_0 (C_pi_counter_read_val),
        .\pi_dqs_found_lanes_r1_reg[9] (\pi_dqs_found_lanes_r1_reg[9] ),
        .\pi_dqs_found_lanes_r1_reg[9]_0 (\pi_dqs_found_lanes_r1_reg[9]_0 ),
        .\pi_dqs_found_lanes_r1_reg[9]_1 (\pi_dqs_found_lanes_r1_reg[9]_1 ),
        .\pi_dqs_found_lanes_r1_reg[9]_2 (\pi_dqs_found_lanes_r1_reg[9]_2 ),
        .\pi_dqs_found_lanes_r1_reg[9]_3 (\pi_dqs_found_lanes_r1_reg[9]_3 ),
        .\po_counter_read_val_reg[8] (\po_counter_read_val_reg[8]_3 ),
        .\po_counter_read_val_reg[8]_0 (\po_counter_read_val_reg[8]_4 ),
        .\po_counter_read_val_reg[8]_1 (\po_counter_read_val_reg[8]_5 ),
        .\po_counter_read_val_reg[8]_2 (A_po_counter_read_val),
        .\po_counter_read_val_reg[8]_3 (D_po_counter_read_val),
        .\po_counter_read_val_reg[8]_4 (C_po_counter_read_val),
        .\rd_mux_sel_r_reg[0] (\rd_mux_sel_r_reg[0] ),
        .\rd_mux_sel_r_reg[0]_0 (\rd_mux_sel_r_reg[0]_0 ),
        .\rd_mux_sel_r_reg[0]_1 (\rd_mux_sel_r_reg[0]_1 ),
        .\rd_mux_sel_r_reg[0]_10 (\rd_mux_sel_r_reg[0]_10 ),
        .\rd_mux_sel_r_reg[0]_11 (\rd_mux_sel_r_reg[0]_11 ),
        .\rd_mux_sel_r_reg[0]_12 (\rd_mux_sel_r_reg[0]_12 ),
        .\rd_mux_sel_r_reg[0]_13 (\rd_mux_sel_r_reg[0]_13 ),
        .\rd_mux_sel_r_reg[0]_14 (\rd_mux_sel_r_reg[0]_14 ),
        .\rd_mux_sel_r_reg[0]_15 (\rd_mux_sel_r_reg[0]_15 ),
        .\rd_mux_sel_r_reg[0]_16 (\rd_mux_sel_r_reg[0]_16 ),
        .\rd_mux_sel_r_reg[0]_17 (\rd_mux_sel_r_reg[0]_17 ),
        .\rd_mux_sel_r_reg[0]_18 (\rd_mux_sel_r_reg[0]_18 ),
        .\rd_mux_sel_r_reg[0]_19 (\rd_mux_sel_r_reg[0]_19 ),
        .\rd_mux_sel_r_reg[0]_2 (\rd_mux_sel_r_reg[0]_2 ),
        .\rd_mux_sel_r_reg[0]_20 (\rd_mux_sel_r_reg[0]_20 ),
        .\rd_mux_sel_r_reg[0]_21 (\rd_mux_sel_r_reg[0]_21 ),
        .\rd_mux_sel_r_reg[0]_22 (\rd_mux_sel_r_reg[0]_22 ),
        .\rd_mux_sel_r_reg[0]_23 (\rd_mux_sel_r_reg[0]_23 ),
        .\rd_mux_sel_r_reg[0]_24 (\rd_mux_sel_r_reg[0]_24 ),
        .\rd_mux_sel_r_reg[0]_25 (\rd_mux_sel_r_reg[0]_25 ),
        .\rd_mux_sel_r_reg[0]_26 (\rd_mux_sel_r_reg[0]_26 ),
        .\rd_mux_sel_r_reg[0]_27 (\rd_mux_sel_r_reg[0]_27 ),
        .\rd_mux_sel_r_reg[0]_28 (\rd_mux_sel_r_reg[0]_28 ),
        .\rd_mux_sel_r_reg[0]_29 (\rd_mux_sel_r_reg[0]_29 ),
        .\rd_mux_sel_r_reg[0]_3 (\rd_mux_sel_r_reg[0]_3 ),
        .\rd_mux_sel_r_reg[0]_30 (\rd_mux_sel_r_reg[0]_30 ),
        .\rd_mux_sel_r_reg[0]_31 (\rd_mux_sel_r_reg[0]_31 ),
        .\rd_mux_sel_r_reg[0]_32 (\rd_mux_sel_r_reg[0]_32 ),
        .\rd_mux_sel_r_reg[0]_33 (\rd_mux_sel_r_reg[0]_33 ),
        .\rd_mux_sel_r_reg[0]_34 (\rd_mux_sel_r_reg[0]_34 ),
        .\rd_mux_sel_r_reg[0]_35 (\rd_mux_sel_r_reg[0]_35 ),
        .\rd_mux_sel_r_reg[0]_36 (\rd_mux_sel_r_reg[0]_36 ),
        .\rd_mux_sel_r_reg[0]_37 (\rd_mux_sel_r_reg[0]_37 ),
        .\rd_mux_sel_r_reg[0]_38 (\rd_mux_sel_r_reg[0]_38 ),
        .\rd_mux_sel_r_reg[0]_39 (\rd_mux_sel_r_reg[0]_39 ),
        .\rd_mux_sel_r_reg[0]_4 (\rd_mux_sel_r_reg[0]_4 ),
        .\rd_mux_sel_r_reg[0]_40 (\rd_mux_sel_r_reg[0]_40 ),
        .\rd_mux_sel_r_reg[0]_41 (\rd_mux_sel_r_reg[0]_41 ),
        .\rd_mux_sel_r_reg[0]_42 (\rd_mux_sel_r_reg[0]_42 ),
        .\rd_mux_sel_r_reg[0]_43 (\rd_mux_sel_r_reg[0]_43 ),
        .\rd_mux_sel_r_reg[0]_44 (\rd_mux_sel_r_reg[0]_44 ),
        .\rd_mux_sel_r_reg[0]_45 (\rd_mux_sel_r_reg[0]_45 ),
        .\rd_mux_sel_r_reg[0]_46 (\rd_mux_sel_r_reg[0]_46 ),
        .\rd_mux_sel_r_reg[0]_47 (\rd_mux_sel_r_reg[0]_47 ),
        .\rd_mux_sel_r_reg[0]_48 (\rd_mux_sel_r_reg[0]_48 ),
        .\rd_mux_sel_r_reg[0]_49 (\rd_mux_sel_r_reg[0]_49 ),
        .\rd_mux_sel_r_reg[0]_5 (\rd_mux_sel_r_reg[0]_5 ),
        .\rd_mux_sel_r_reg[0]_50 (\rd_mux_sel_r_reg[0]_50 ),
        .\rd_mux_sel_r_reg[0]_51 (\rd_mux_sel_r_reg[0]_51 ),
        .\rd_mux_sel_r_reg[0]_52 (\rd_mux_sel_r_reg[0]_52 ),
        .\rd_mux_sel_r_reg[0]_53 (\rd_mux_sel_r_reg[0]_53 ),
        .\rd_mux_sel_r_reg[0]_54 (\rd_mux_sel_r_reg[0]_54 ),
        .\rd_mux_sel_r_reg[0]_55 (\rd_mux_sel_r_reg[0]_55 ),
        .\rd_mux_sel_r_reg[0]_56 (\rd_mux_sel_r_reg[0]_56 ),
        .\rd_mux_sel_r_reg[0]_57 (\rd_mux_sel_r_reg[0]_57 ),
        .\rd_mux_sel_r_reg[0]_58 (\rd_mux_sel_r_reg[0]_58 ),
        .\rd_mux_sel_r_reg[0]_59 (\rd_mux_sel_r_reg[0]_59 ),
        .\rd_mux_sel_r_reg[0]_6 (\rd_mux_sel_r_reg[0]_6 ),
        .\rd_mux_sel_r_reg[0]_60 (\rd_mux_sel_r_reg[0]_60 ),
        .\rd_mux_sel_r_reg[0]_61 (\rd_mux_sel_r_reg[0]_61 ),
        .\rd_mux_sel_r_reg[0]_62 (\rd_mux_sel_r_reg[0]_62 ),
        .\rd_mux_sel_r_reg[0]_7 (\rd_mux_sel_r_reg[0]_7 ),
        .\rd_mux_sel_r_reg[0]_8 (\rd_mux_sel_r_reg[0]_8 ),
        .\rd_mux_sel_r_reg[0]_9 (\rd_mux_sel_r_reg[0]_9 ),
        .\rd_ptr_reg[3] (\rd_ptr_reg[3]_0 ),
        .rst_r4(rst_r4),
        .sync_pulse(sync_pulse),
        .ts_dqs_1(ts_dqs_1));
  mig_mig_7series_v4_2_ddr_byte_lane__parameterized1 \ddr_byte_lane_C.ddr_byte_lane_C 
       (.A_rst_primitives(A_rst_primitives),
        .A_rst_primitives_reg(A_rst_primitives_reg_2),
        .A_rst_primitives_reg_0(\ddr_byte_lane_C.ddr_byte_lane_C_n_22 ),
        .A_rst_primitives_reg_1(C_pi_counter_read_val),
        .A_rst_primitives_reg_2(C_po_counter_read_val),
        .CLKB0_12(CLKB0_12),
        .LD0_12(LD0_12),
        .PCENABLECALIB(phy_encalib),
        .Q(\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_3 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3] ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 (\ddr_byte_lane_C.ddr_byte_lane_C_n_41 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 (\ddr_byte_lane_C.ddr_byte_lane_C_n_106 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 (\ddr_byte_lane_C.ddr_byte_lane_C_n_107 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ),
        .freq_refclk(freq_refclk),
        .idelay_inc(idelay_inc),
        .idelay_ld_rst_5(idelay_ld_rst_5),
        .if_empty_r(if_empty_r_2),
        .ififo_rst_reg_0(ififo_rst_reg_1),
        .in0(in0[2]),
        .\input_[9].iserdes_dq_.iserdesdq (\input_[9].iserdes_dq_.iserdesdq_1 ),
        .mem_dq_in(mem_dq_in[23:16]),
        .mem_dq_out(mem_dq_out[26:18]),
        .mem_dq_ts(mem_dq_ts[26:18]),
        .mem_dqs_in(mem_dqs_in[2]),
        .mem_refclk(mem_refclk),
        .\my_empty_reg[1] (\my_empty_reg[1]_1 ),
        .\my_empty_reg[7] (\my_empty_reg[7]_14 ),
        .\my_empty_reg[7]_0 (\my_empty_reg[7]_15 ),
        .\my_empty_reg[7]_1 (\my_empty_reg[7]_16 ),
        .\my_empty_reg[7]_2 (\my_empty_reg[7]_17 ),
        .\my_empty_reg[7]_3 (\my_empty_reg[7]_18 ),
        .\my_empty_reg[7]_4 (\my_empty_reg[7]_19 ),
        .\my_empty_reg[7]_5 (\my_empty_reg[7]_20 ),
        .\my_empty_reg[7]_6 (\my_empty_reg[7]_21 ),
        .\my_full_reg[1] (\ddr_byte_lane_D.ddr_byte_lane_D_n_236 ),
        .\my_full_reg[1]_0 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ),
        .\my_full_reg[1]_1 (\ddr_byte_lane_B.ddr_byte_lane_B_n_157 ),
        .\my_full_reg[1]_2 (\my_full_reg[1] ),
        .\my_full_reg[1]_3 (\my_full_reg[1]_0 ),
        .\my_full_reg[1]_4 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),
        .out_dqs_2(out_dqs_2),
        .out_fifo_0(out_fifo),
        .out_fifo_1({out_fifo_0[30],out_fifo_0[26],out_fifo_0[22],out_fifo_0[18],out_fifo_0[14],out_fifo_0[10],out_fifo_0[6],out_fifo_0[2]}),
        .out_fifo_2(out_fifo_1),
        .out_fifo_i_75__2(out_fifo_i_75__2),
        .phaser_ctl_bus({phaser_ctl_bus[13:12],phaser_ctl_bus[6],phaser_ctl_bus[2]}),
        .phy_data_wr_en(phy_data_wr_en),
        .phy_if_reset(phy_if_reset),
        .\pi_dqs_found_lanes_r1_reg[10] (\pi_dqs_found_lanes_r1_reg[10] ),
        .\pi_dqs_found_lanes_r1_reg[10]_0 (\pi_dqs_found_lanes_r1_reg[10]_0 ),
        .\pi_dqs_found_lanes_r1_reg[10]_1 (\pi_dqs_found_lanes_r1_reg[10]_1 ),
        .\pi_dqs_found_lanes_r1_reg[10]_2 (\pi_dqs_found_lanes_r1_reg[10]_2 ),
        .\pi_dqs_found_lanes_r1_reg[10]_3 (\pi_dqs_found_lanes_r1_reg[10]_3 ),
        .\po_counter_read_val_reg[8] (\po_counter_read_val_reg[8]_6 ),
        .\po_counter_read_val_reg[8]_0 (\po_counter_read_val_reg[8]_7 ),
        .\po_counter_read_val_reg[8]_1 (\po_counter_read_val_reg[8]_8 ),
        .\rd_ptr_reg[3] (\rd_ptr_reg[3]_1 ),
        .rst_r4(rst_r4),
        .sync_pulse(sync_pulse),
        .ts_dqs_2(ts_dqs_2),
        .\wr_ptr[1]_i_2__2 ({\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_1 [3],\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty_1 [0]}),
        .\wr_ptr_timing_reg[3] (\entry_cnt_reg[4]_1 ));
  mig_mig_7series_v4_2_ddr_byte_lane__parameterized2 \ddr_byte_lane_D.ddr_byte_lane_D 
       (.A_rst_primitives(A_rst_primitives),
        .A_rst_primitives_reg(A_rst_primitives_reg_3),
        .A_rst_primitives_reg_0(D_pi_counter_read_val),
        .A_rst_primitives_reg_1(D_po_counter_read_val),
        .A_rst_primitives_reg_2(A_rst_primitives_reg_4),
        .CLKB0_13(CLKB0_13),
        .LD0_13(LD0_13),
        .PCENABLECALIB(phy_encalib),
        .Q(\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_4 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 (\ddr_byte_lane_D.ddr_byte_lane_D_n_233 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_0 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_2 (\ddr_byte_lane_D.ddr_byte_lane_D_n_235 ),
        .\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_3 (\ddr_byte_lane_D.ddr_byte_lane_D_n_236 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2 ),
        .\entry_cnt_reg[4] (\entry_cnt_reg[4]_1 ),
        .freq_refclk(freq_refclk),
        .\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] (\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] ),
        .\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] (\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] ),
        .\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] (\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] ),
        .\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] (\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] ),
        .\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] (\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] ),
        .\gen_mux_rd[0].mux_rd_rise0_r1_reg[0]_0 (\gen_mux_rd[0].mux_rd_rise0_r1_reg[0]_0 ),
        .\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] (\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] ),
        .\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] (\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] ),
        .\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] (\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] ),
        .\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] (\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] (\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] (\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] ),
        .\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] (\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] (\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] (\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] (\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] ),
        .\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] (\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] ),
        .\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] (\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] ),
        .\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] (\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] ),
        .\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] (\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] ),
        .\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] (\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] ),
        .\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] (\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] ),
        .\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] (\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] ),
        .\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] (\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] ),
        .\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] (\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] ),
        .\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] (\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] (\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] (\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] ),
        .\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] (\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] (\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] (\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] (\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] ),
        .\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] (\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] ),
        .\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] (\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] ),
        .\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] (\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] ),
        .\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] (\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] ),
        .\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] (\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] ),
        .\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] (\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] ),
        .\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] (\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] ),
        .\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] (\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] ),
        .\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] (\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] ),
        .\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] (\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] (\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] (\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] ),
        .\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] (\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] (\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] (\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] (\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] ),
        .\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] (\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] ),
        .\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] (\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] ),
        .\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] (\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] ),
        .\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] (\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] ),
        .\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] (\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] ),
        .\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] (\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] ),
        .\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] (\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] ),
        .\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] (\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] ),
        .\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] (\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] ),
        .\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] (\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] (\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] (\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] ),
        .\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] (\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] (\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] (\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] (\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] ),
        .\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] (\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_2 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_2 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_2 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_2 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_2 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_2 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_3 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_2 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_2 (\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_2 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_2 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_2 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_2 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_2 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_2 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_2 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_2 (\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_2 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_2 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_2 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_2 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_2 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_2 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_2 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_2 (\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_2 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_2 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_2 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_2 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_2 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_2 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_2 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_2 (\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_2 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_2 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_2 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_2 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_2 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_2 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_2 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_2 (\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_2 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_2 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_2 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_2 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_2 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_2 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_2 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_2 (\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_2 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_2 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_2 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_2 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_2 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_2 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_2 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_2 (\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_2 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_2 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_2 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_2 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_2 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_2 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_2 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1 ),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_2 (\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] ),
        .idelay_inc(idelay_inc),
        .idelay_ld_rst_6(idelay_ld_rst_6),
        .if_empty_r(if_empty_r),
        .if_empty_v(if_empty_v),
        .ififo_rst_reg_0(ififo_rst_reg_2),
        .in0(in0[3]),
        .\input_[9].iserdes_dq_.iserdesdq (\input_[9].iserdes_dq_.iserdesdq_2 ),
        .mem_dq_in(mem_dq_in[31:24]),
        .mem_dq_out(mem_dq_out[35:27]),
        .mem_dq_ts(mem_dq_ts[35:27]),
        .mem_dqs_in(mem_dqs_in[3]),
        .mem_refclk(mem_refclk),
        .\my_empty_reg[1] (\my_empty_reg[1]_2 ),
        .\my_empty_reg[7] (\my_empty_reg[7]_22 ),
        .\my_empty_reg[7]_0 (\my_empty_reg[7]_23 ),
        .\my_empty_reg[7]_1 (\my_empty_reg[7]_24 ),
        .\my_empty_reg[7]_2 (\my_empty_reg[7]_25 ),
        .\my_empty_reg[7]_3 (\my_empty_reg[7]_26 ),
        .\my_empty_reg[7]_4 (\my_empty_reg[7]_27 ),
        .\my_empty_reg[7]_5 (\my_empty_reg[7]_28 ),
        .\my_empty_reg[7]_6 (\my_empty_reg[7]_29 ),
        .\my_full_reg[1] (\ddr_byte_lane_C.ddr_byte_lane_C_n_106 ),
        .\my_full_reg[1]_0 (\ddr_byte_lane_B.ddr_byte_lane_B_n_157 ),
        .\my_full_reg[1]_1 (\ddr_byte_lane_C.ddr_byte_lane_C_n_41 ),
        .\my_full_reg[1]_2 (\my_full_reg[1] ),
        .\my_full_reg[1]_3 (\my_full_reg[1]_0 ),
        .\my_full_reg[1]_4 (\dq_gen_40.if_post_fifo_gen.if_empty_r_reg[3]_1 ),
        .out_dqs_3(out_dqs_3),
        .out_fifo_0(out_fifo),
        .out_fifo_1({out_fifo_0[31],out_fifo_0[27],out_fifo_0[23],out_fifo_0[19],out_fifo_0[15],out_fifo_0[11],out_fifo_0[7],out_fifo_0[3]}),
        .out_fifo_2(out_fifo_1),
        .out_fifo_i_75__3(out_fifo_i_75__3),
        .p_0_out(p_0_out),
        .phaser_ctl_bus({phaser_ctl_bus[15:14],phaser_ctl_bus[7],phaser_ctl_bus[3]}),
        .phy_data_wr_en(phy_data_wr_en),
        .phy_if_empty_r_reg(\dq_gen_40.if_post_fifo_gen.u_ddr_if_post_fifo/my_empty ),
        .phy_if_empty_r_reg_0(\ddr_byte_lane_C.ddr_byte_lane_C_n_107 ),
        .phy_if_reset(phy_if_reset),
        .\pi_dqs_found_lanes_r1_reg[11] (\pi_dqs_found_lanes_r1_reg[11] ),
        .\pi_dqs_found_lanes_r1_reg[11]_0 (\pi_dqs_found_lanes_r1_reg[11]_0 ),
        .\pi_dqs_found_lanes_r1_reg[11]_1 (\pi_dqs_found_lanes_r1_reg[11]_1 ),
        .\pi_dqs_found_lanes_r1_reg[11]_2 (\pi_dqs_found_lanes_r1_reg[11]_2 ),
        .\pi_dqs_found_lanes_r1_reg[11]_3 (\pi_dqs_found_lanes_r1_reg[11]_3 ),
        .pi_phase_locked_all_r1_reg(\ddr_byte_lane_A.ddr_byte_lane_A_n_22 ),
        .pi_phase_locked_all_r1_reg_0(\ddr_byte_lane_B.ddr_byte_lane_B_n_22 ),
        .pi_phase_locked_all_r1_reg_1(\ddr_byte_lane_C.ddr_byte_lane_C_n_22 ),
        .\po_counter_read_val_reg[8] (\po_counter_read_val_reg[8]_9 ),
        .\po_counter_read_val_reg[8]_0 (\po_counter_read_val_reg[8]_10 ),
        .\po_counter_read_val_reg[8]_1 (\po_counter_read_val_reg[8]_11 ),
        .\po_stg2_wrcal_cnt_reg[2] (\po_stg2_wrcal_cnt_reg[2] ),
        .\po_stg2_wrcal_cnt_reg[2]_0 (\po_stg2_wrcal_cnt_reg[2]_0 ),
        .\po_stg2_wrcal_cnt_reg[2]_1 (\po_stg2_wrcal_cnt_reg[2]_1 ),
        .\po_stg2_wrcal_cnt_reg[2]_10 (\po_stg2_wrcal_cnt_reg[2]_10 ),
        .\po_stg2_wrcal_cnt_reg[2]_11 (\po_stg2_wrcal_cnt_reg[2]_11 ),
        .\po_stg2_wrcal_cnt_reg[2]_12 (\po_stg2_wrcal_cnt_reg[2]_12 ),
        .\po_stg2_wrcal_cnt_reg[2]_13 (\po_stg2_wrcal_cnt_reg[2]_13 ),
        .\po_stg2_wrcal_cnt_reg[2]_14 (\po_stg2_wrcal_cnt_reg[2]_14 ),
        .\po_stg2_wrcal_cnt_reg[2]_15 (\po_stg2_wrcal_cnt_reg[2]_15 ),
        .\po_stg2_wrcal_cnt_reg[2]_16 (\po_stg2_wrcal_cnt_reg[2]_16 ),
        .\po_stg2_wrcal_cnt_reg[2]_17 (\po_stg2_wrcal_cnt_reg[2]_17 ),
        .\po_stg2_wrcal_cnt_reg[2]_18 (\po_stg2_wrcal_cnt_reg[2]_18 ),
        .\po_stg2_wrcal_cnt_reg[2]_19 (\po_stg2_wrcal_cnt_reg[2]_19 ),
        .\po_stg2_wrcal_cnt_reg[2]_2 (\po_stg2_wrcal_cnt_reg[2]_2 ),
        .\po_stg2_wrcal_cnt_reg[2]_20 (\po_stg2_wrcal_cnt_reg[2]_20 ),
        .\po_stg2_wrcal_cnt_reg[2]_21 (\po_stg2_wrcal_cnt_reg[2]_21 ),
        .\po_stg2_wrcal_cnt_reg[2]_22 (\po_stg2_wrcal_cnt_reg[2]_22 ),
        .\po_stg2_wrcal_cnt_reg[2]_23 (\po_stg2_wrcal_cnt_reg[2]_23 ),
        .\po_stg2_wrcal_cnt_reg[2]_24 (\po_stg2_wrcal_cnt_reg[2]_24 ),
        .\po_stg2_wrcal_cnt_reg[2]_25 (\po_stg2_wrcal_cnt_reg[2]_25 ),
        .\po_stg2_wrcal_cnt_reg[2]_26 (\po_stg2_wrcal_cnt_reg[2]_26 ),
        .\po_stg2_wrcal_cnt_reg[2]_27 (\po_stg2_wrcal_cnt_reg[2]_27 ),
        .\po_stg2_wrcal_cnt_reg[2]_28 (\po_stg2_wrcal_cnt_reg[2]_28 ),
        .\po_stg2_wrcal_cnt_reg[2]_29 (\po_stg2_wrcal_cnt_reg[2]_29 ),
        .\po_stg2_wrcal_cnt_reg[2]_3 (\po_stg2_wrcal_cnt_reg[2]_3 ),
        .\po_stg2_wrcal_cnt_reg[2]_30 (\po_stg2_wrcal_cnt_reg[2]_30 ),
        .\po_stg2_wrcal_cnt_reg[2]_31 (\po_stg2_wrcal_cnt_reg[2]_31 ),
        .\po_stg2_wrcal_cnt_reg[2]_32 (\po_stg2_wrcal_cnt_reg[2]_32 ),
        .\po_stg2_wrcal_cnt_reg[2]_33 (\po_stg2_wrcal_cnt_reg[2]_33 ),
        .\po_stg2_wrcal_cnt_reg[2]_34 (\po_stg2_wrcal_cnt_reg[2]_34 ),
        .\po_stg2_wrcal_cnt_reg[2]_35 (\po_stg2_wrcal_cnt_reg[2]_35 ),
        .\po_stg2_wrcal_cnt_reg[2]_36 (\po_stg2_wrcal_cnt_reg[2]_36 ),
        .\po_stg2_wrcal_cnt_reg[2]_37 (\po_stg2_wrcal_cnt_reg[2]_37 ),
        .\po_stg2_wrcal_cnt_reg[2]_38 (\po_stg2_wrcal_cnt_reg[2]_38 ),
        .\po_stg2_wrcal_cnt_reg[2]_39 (\po_stg2_wrcal_cnt_reg[2]_39 ),
        .\po_stg2_wrcal_cnt_reg[2]_4 (\po_stg2_wrcal_cnt_reg[2]_4 ),
        .\po_stg2_wrcal_cnt_reg[2]_40 (\po_stg2_wrcal_cnt_reg[2]_40 ),
        .\po_stg2_wrcal_cnt_reg[2]_41 (\po_stg2_wrcal_cnt_reg[2]_41 ),
        .\po_stg2_wrcal_cnt_reg[2]_42 (\po_stg2_wrcal_cnt_reg[2]_42 ),
        .\po_stg2_wrcal_cnt_reg[2]_43 (\po_stg2_wrcal_cnt_reg[2]_43 ),
        .\po_stg2_wrcal_cnt_reg[2]_44 (\po_stg2_wrcal_cnt_reg[2]_44 ),
        .\po_stg2_wrcal_cnt_reg[2]_45 (\po_stg2_wrcal_cnt_reg[2]_45 ),
        .\po_stg2_wrcal_cnt_reg[2]_46 (\po_stg2_wrcal_cnt_reg[2]_46 ),
        .\po_stg2_wrcal_cnt_reg[2]_47 (\po_stg2_wrcal_cnt_reg[2]_47 ),
        .\po_stg2_wrcal_cnt_reg[2]_48 (\po_stg2_wrcal_cnt_reg[2]_48 ),
        .\po_stg2_wrcal_cnt_reg[2]_49 (\po_stg2_wrcal_cnt_reg[2]_49 ),
        .\po_stg2_wrcal_cnt_reg[2]_5 (\po_stg2_wrcal_cnt_reg[2]_5 ),
        .\po_stg2_wrcal_cnt_reg[2]_50 (\po_stg2_wrcal_cnt_reg[2]_50 ),
        .\po_stg2_wrcal_cnt_reg[2]_51 (\po_stg2_wrcal_cnt_reg[2]_51 ),
        .\po_stg2_wrcal_cnt_reg[2]_52 (\po_stg2_wrcal_cnt_reg[2]_52 ),
        .\po_stg2_wrcal_cnt_reg[2]_53 (\po_stg2_wrcal_cnt_reg[2]_53 ),
        .\po_stg2_wrcal_cnt_reg[2]_54 (\po_stg2_wrcal_cnt_reg[2]_54 ),
        .\po_stg2_wrcal_cnt_reg[2]_55 (\po_stg2_wrcal_cnt_reg[2]_55 ),
        .\po_stg2_wrcal_cnt_reg[2]_56 (\po_stg2_wrcal_cnt_reg[2]_56 ),
        .\po_stg2_wrcal_cnt_reg[2]_57 (\po_stg2_wrcal_cnt_reg[2]_57 ),
        .\po_stg2_wrcal_cnt_reg[2]_58 (\po_stg2_wrcal_cnt_reg[2]_58 ),
        .\po_stg2_wrcal_cnt_reg[2]_59 (\po_stg2_wrcal_cnt_reg[2]_59 ),
        .\po_stg2_wrcal_cnt_reg[2]_6 (\po_stg2_wrcal_cnt_reg[2]_6 ),
        .\po_stg2_wrcal_cnt_reg[2]_60 (\po_stg2_wrcal_cnt_reg[2]_60 ),
        .\po_stg2_wrcal_cnt_reg[2]_61 (\po_stg2_wrcal_cnt_reg[2]_61 ),
        .\po_stg2_wrcal_cnt_reg[2]_7 (\po_stg2_wrcal_cnt_reg[2]_7 ),
        .\po_stg2_wrcal_cnt_reg[2]_8 (\po_stg2_wrcal_cnt_reg[2]_8 ),
        .\po_stg2_wrcal_cnt_reg[2]_9 (\po_stg2_wrcal_cnt_reg[2]_9 ),
        .\rd_mux_sel_r_reg[2] (\rd_mux_sel_r_reg[2] ),
        .\rd_mux_sel_r_reg[2]_0 (\rd_mux_sel_r_reg[2]_0 ),
        .\rd_mux_sel_r_reg[2]_1 (\rd_mux_sel_r_reg[2]_1 ),
        .\rd_mux_sel_r_reg[2]_10 (\rd_mux_sel_r_reg[2]_10 ),
        .\rd_mux_sel_r_reg[2]_11 (\rd_mux_sel_r_reg[2]_11 ),
        .\rd_mux_sel_r_reg[2]_12 (\rd_mux_sel_r_reg[2]_12 ),
        .\rd_mux_sel_r_reg[2]_13 (\rd_mux_sel_r_reg[2]_13 ),
        .\rd_mux_sel_r_reg[2]_14 (\rd_mux_sel_r_reg[2]_14 ),
        .\rd_mux_sel_r_reg[2]_15 (\rd_mux_sel_r_reg[2]_15 ),
        .\rd_mux_sel_r_reg[2]_16 (\rd_mux_sel_r_reg[2]_16 ),
        .\rd_mux_sel_r_reg[2]_17 (\rd_mux_sel_r_reg[2]_17 ),
        .\rd_mux_sel_r_reg[2]_18 (\rd_mux_sel_r_reg[2]_18 ),
        .\rd_mux_sel_r_reg[2]_19 (\rd_mux_sel_r_reg[2]_19 ),
        .\rd_mux_sel_r_reg[2]_2 (\rd_mux_sel_r_reg[2]_2 ),
        .\rd_mux_sel_r_reg[2]_20 (\rd_mux_sel_r_reg[2]_20 ),
        .\rd_mux_sel_r_reg[2]_21 (\rd_mux_sel_r_reg[2]_21 ),
        .\rd_mux_sel_r_reg[2]_22 (\rd_mux_sel_r_reg[2]_22 ),
        .\rd_mux_sel_r_reg[2]_23 (\rd_mux_sel_r_reg[2]_23 ),
        .\rd_mux_sel_r_reg[2]_24 (\rd_mux_sel_r_reg[2]_24 ),
        .\rd_mux_sel_r_reg[2]_25 (\rd_mux_sel_r_reg[2]_25 ),
        .\rd_mux_sel_r_reg[2]_26 (\rd_mux_sel_r_reg[2]_26 ),
        .\rd_mux_sel_r_reg[2]_27 (\rd_mux_sel_r_reg[2]_27 ),
        .\rd_mux_sel_r_reg[2]_28 (\rd_mux_sel_r_reg[2]_28 ),
        .\rd_mux_sel_r_reg[2]_29 (\rd_mux_sel_r_reg[2]_29 ),
        .\rd_mux_sel_r_reg[2]_3 (\rd_mux_sel_r_reg[2]_3 ),
        .\rd_mux_sel_r_reg[2]_30 (\rd_mux_sel_r_reg[2]_30 ),
        .\rd_mux_sel_r_reg[2]_31 (\rd_mux_sel_r_reg[2]_31 ),
        .\rd_mux_sel_r_reg[2]_32 (\rd_mux_sel_r_reg[2]_32 ),
        .\rd_mux_sel_r_reg[2]_33 (\rd_mux_sel_r_reg[2]_33 ),
        .\rd_mux_sel_r_reg[2]_34 (\rd_mux_sel_r_reg[2]_34 ),
        .\rd_mux_sel_r_reg[2]_35 (\rd_mux_sel_r_reg[2]_35 ),
        .\rd_mux_sel_r_reg[2]_36 (\rd_mux_sel_r_reg[2]_36 ),
        .\rd_mux_sel_r_reg[2]_37 (\rd_mux_sel_r_reg[2]_37 ),
        .\rd_mux_sel_r_reg[2]_38 (\rd_mux_sel_r_reg[2]_38 ),
        .\rd_mux_sel_r_reg[2]_39 (\rd_mux_sel_r_reg[2]_39 ),
        .\rd_mux_sel_r_reg[2]_4 (\rd_mux_sel_r_reg[2]_4 ),
        .\rd_mux_sel_r_reg[2]_40 (\rd_mux_sel_r_reg[2]_40 ),
        .\rd_mux_sel_r_reg[2]_41 (\rd_mux_sel_r_reg[2]_41 ),
        .\rd_mux_sel_r_reg[2]_42 (\rd_mux_sel_r_reg[2]_42 ),
        .\rd_mux_sel_r_reg[2]_43 (\rd_mux_sel_r_reg[2]_43 ),
        .\rd_mux_sel_r_reg[2]_44 (\rd_mux_sel_r_reg[2]_44 ),
        .\rd_mux_sel_r_reg[2]_45 (\rd_mux_sel_r_reg[2]_45 ),
        .\rd_mux_sel_r_reg[2]_46 (\rd_mux_sel_r_reg[2]_46 ),
        .\rd_mux_sel_r_reg[2]_47 (\rd_mux_sel_r_reg[2]_47 ),
        .\rd_mux_sel_r_reg[2]_48 (\rd_mux_sel_r_reg[2]_48 ),
        .\rd_mux_sel_r_reg[2]_49 (\rd_mux_sel_r_reg[2]_49 ),
        .\rd_mux_sel_r_reg[2]_5 (\rd_mux_sel_r_reg[2]_5 ),
        .\rd_mux_sel_r_reg[2]_50 (\rd_mux_sel_r_reg[2]_50 ),
        .\rd_mux_sel_r_reg[2]_51 (\rd_mux_sel_r_reg[2]_51 ),
        .\rd_mux_sel_r_reg[2]_52 (\rd_mux_sel_r_reg[2]_52 ),
        .\rd_mux_sel_r_reg[2]_53 (\rd_mux_sel_r_reg[2]_53 ),
        .\rd_mux_sel_r_reg[2]_54 (\rd_mux_sel_r_reg[2]_54 ),
        .\rd_mux_sel_r_reg[2]_55 (\rd_mux_sel_r_reg[2]_55 ),
        .\rd_mux_sel_r_reg[2]_56 (\rd_mux_sel_r_reg[2]_56 ),
        .\rd_mux_sel_r_reg[2]_57 (\rd_mux_sel_r_reg[2]_57 ),
        .\rd_mux_sel_r_reg[2]_58 (\rd_mux_sel_r_reg[2]_58 ),
        .\rd_mux_sel_r_reg[2]_59 (\rd_mux_sel_r_reg[2]_59 ),
        .\rd_mux_sel_r_reg[2]_6 (\rd_mux_sel_r_reg[2]_6 ),
        .\rd_mux_sel_r_reg[2]_60 (\rd_mux_sel_r_reg[2]_60 ),
        .\rd_mux_sel_r_reg[2]_61 (\rd_mux_sel_r_reg[2]_61 ),
        .\rd_mux_sel_r_reg[2]_62 (\rd_mux_sel_r_reg[2]_62 ),
        .\rd_mux_sel_r_reg[2]_7 (\rd_mux_sel_r_reg[2]_7 ),
        .\rd_mux_sel_r_reg[2]_8 (\rd_mux_sel_r_reg[2]_8 ),
        .\rd_mux_sel_r_reg[2]_9 (\rd_mux_sel_r_reg[2]_9 ),
        .\rd_ptr_reg[3] (\rd_ptr_reg[3]_2 ),
        .rst_r4(rst_r4),
        .sync_pulse(sync_pulse),
        .ts_dqs_3(ts_dqs_3));
  LUT1 #(
    .INIT(2'h2)) 
    i_0
       (.I0(1'b0),
        .O(A_pi_rst_div2));
  LUT1 #(
    .INIT(2'h2)) 
    i_1
       (.I0(1'b0),
        .O(B_pi_rst_div2));
  LUT1 #(
    .INIT(2'h2)) 
    i_2
       (.I0(1'b0),
        .O(C_pi_rst_div2));
  LUT1 #(
    .INIT(2'h2)) 
    i_3
       (.I0(1'b0),
        .O(D_pi_rst_div2));
  FDRE #(
    .INIT(1'b0)) 
    mcGo_reg
       (.C(\entry_cnt_reg[4]_1 ),
        .CE(1'b1),
        .D(rst_out_reg_0),
        .Q(mcGo_w),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    ofs_rdy_r_i_5
       (.I0(\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_3 [4]),
        .I1(\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_3 [2]),
        .I2(\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_3 [3]),
        .I3(\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_0 [4]),
        .I4(\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_0 [2]),
        .I5(\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_0 [3]),
        .O(\entry_cnt_reg[4]_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    ofs_rdy_r_i_6
       (.I0(\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg [4]),
        .I1(\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg [2]),
        .I2(\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg [3]),
        .I3(\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_4 [4]),
        .I4(\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_4 [2]),
        .I5(\of_pre_fifo_gen.u_ddr_of_pre_fifo/entry_cnt_reg_4 [3]),
        .O(\entry_cnt_reg[4] ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  PHASER_REF #(
    .IS_PWRDWN_INVERTED(1'b0),
    .IS_RST_INVERTED(1'b0)) 
    phaser_ref_i
       (.CLKIN(freq_refclk),
        .LOCKED(ref_dll_lock_w__0),
        .PWRDWN(1'b0),
        .RST(RST0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  PHY_CONTROL #(
    .AO_TOGGLE(1),
    .AO_WRLVL_EN(4'b0000),
    .BURST_MODE("TRUE"),
    .CLK_RATIO(4),
    .CMD_OFFSET(8),
    .CO_DURATION(1),
    .DATA_CTL_A_N("TRUE"),
    .DATA_CTL_B_N("TRUE"),
    .DATA_CTL_C_N("TRUE"),
    .DATA_CTL_D_N("TRUE"),
    .DISABLE_SEQ_MATCH("TRUE"),
    .DI_DURATION(1),
    .DO_DURATION(1),
    .EVENTS_DELAY(18),
    .FOUR_WINDOW_CLOCKS(63),
    .MULTI_REGION("TRUE"),
    .PHY_COUNT_ENABLE("FALSE"),
    .RD_CMD_OFFSET_0(10),
    .RD_CMD_OFFSET_1(10),
    .RD_CMD_OFFSET_2(10),
    .RD_CMD_OFFSET_3(10),
    .RD_DURATION_0(6),
    .RD_DURATION_1(6),
    .RD_DURATION_2(6),
    .RD_DURATION_3(6),
    .SYNC_MODE("FALSE"),
    .WR_CMD_OFFSET_0(8),
    .WR_CMD_OFFSET_1(8),
    .WR_CMD_OFFSET_2(8),
    .WR_CMD_OFFSET_3(8),
    .WR_DURATION_0(7),
    .WR_DURATION_1(7),
    .WR_DURATION_2(7),
    .WR_DURATION_3(7)) 
    phy_control_i
       (.AUXOUTPUT({phy_control_i_n_14,phy_control_i_n_15,phy_control_i_n_16,phy_control_i_n_17}),
        .INBURSTPENDING(phaser_ctl_bus[7:4]),
        .INRANKA(phaser_ctl_bus[9:8]),
        .INRANKB(phaser_ctl_bus[11:10]),
        .INRANKC(phaser_ctl_bus[13:12]),
        .INRANKD(phaser_ctl_bus[15:14]),
        .MEMREFCLK(mem_refclk),
        .OUTBURSTPENDING(phaser_ctl_bus[3:0]),
        .PCENABLECALIB(phy_encalib),
        .PHYCLK(\entry_cnt_reg[4]_1 ),
        .PHYCTLALMOSTFULL(phy_control_i_n_0),
        .PHYCTLEMPTY(phy_control_i_n_1),
        .PHYCTLFULL(_phy_ctl_full_p__0),
        .PHYCTLMSTREMPTY(phy_ctl_mstr_empty),
        .PHYCTLREADY(phy_ctl_wr_i2_reg),
        .PHYCTLWD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,PHYCTLWD[10:3],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,PHYCTLWD[2:0]}),
        .PHYCTLWRENABLE(phy_ctl_wr_i2),
        .PLLLOCK(pll_locked),
        .READCALIBENABLE(phy_read_calib),
        .REFDLLLOCK(ref_dll_lock_w__0),
        .RESET(phy_mc_ctl_full_r_reg),
        .SYNCIN(sync_pulse),
        .WRITECALIBENABLE(phy_write_calib));
  FDRE \pi_counter_read_val_reg[0] 
       (.C(\entry_cnt_reg[4]_1 ),
        .CE(1'b1),
        .D(\ddr_byte_lane_B.ddr_byte_lane_B_n_227 ),
        .Q(\pi_counter_read_val_reg[5]_0 [0]),
        .R(1'b0));
  FDRE \pi_counter_read_val_reg[1] 
       (.C(\entry_cnt_reg[4]_1 ),
        .CE(1'b1),
        .D(\ddr_byte_lane_B.ddr_byte_lane_B_n_226 ),
        .Q(\pi_counter_read_val_reg[5]_0 [1]),
        .R(1'b0));
  FDRE \pi_counter_read_val_reg[2] 
       (.C(\entry_cnt_reg[4]_1 ),
        .CE(1'b1),
        .D(\ddr_byte_lane_B.ddr_byte_lane_B_n_225 ),
        .Q(\pi_counter_read_val_reg[5]_0 [2]),
        .R(1'b0));
  FDRE \pi_counter_read_val_reg[3] 
       (.C(\entry_cnt_reg[4]_1 ),
        .CE(1'b1),
        .D(\ddr_byte_lane_B.ddr_byte_lane_B_n_224 ),
        .Q(\pi_counter_read_val_reg[5]_0 [3]),
        .R(1'b0));
  FDRE \pi_counter_read_val_reg[4] 
       (.C(\entry_cnt_reg[4]_1 ),
        .CE(1'b1),
        .D(\ddr_byte_lane_B.ddr_byte_lane_B_n_223 ),
        .Q(\pi_counter_read_val_reg[5]_0 [4]),
        .R(1'b0));
  FDRE \pi_counter_read_val_reg[5] 
       (.C(\entry_cnt_reg[4]_1 ),
        .CE(1'b1),
        .D(\ddr_byte_lane_B.ddr_byte_lane_B_n_222 ),
        .Q(\pi_counter_read_val_reg[5]_0 [5]),
        .R(1'b0));
  FDRE \po_counter_read_val_reg[0] 
       (.C(\entry_cnt_reg[4]_1 ),
        .CE(1'b1),
        .D(\ddr_byte_lane_B.ddr_byte_lane_B_n_236 ),
        .Q(Q[0]),
        .R(1'b0));
  FDRE \po_counter_read_val_reg[1] 
       (.C(\entry_cnt_reg[4]_1 ),
        .CE(1'b1),
        .D(\ddr_byte_lane_B.ddr_byte_lane_B_n_235 ),
        .Q(Q[1]),
        .R(1'b0));
  FDRE \po_counter_read_val_reg[2] 
       (.C(\entry_cnt_reg[4]_1 ),
        .CE(1'b1),
        .D(\ddr_byte_lane_B.ddr_byte_lane_B_n_234 ),
        .Q(Q[2]),
        .R(1'b0));
  FDRE \po_counter_read_val_reg[3] 
       (.C(\entry_cnt_reg[4]_1 ),
        .CE(1'b1),
        .D(\ddr_byte_lane_B.ddr_byte_lane_B_n_233 ),
        .Q(Q[3]),
        .R(1'b0));
  FDRE \po_counter_read_val_reg[4] 
       (.C(\entry_cnt_reg[4]_1 ),
        .CE(1'b1),
        .D(\ddr_byte_lane_B.ddr_byte_lane_B_n_232 ),
        .Q(Q[4]),
        .R(1'b0));
  FDRE \po_counter_read_val_reg[5] 
       (.C(\entry_cnt_reg[4]_1 ),
        .CE(1'b1),
        .D(\ddr_byte_lane_B.ddr_byte_lane_B_n_231 ),
        .Q(Q[5]),
        .R(1'b0));
  FDRE \po_counter_read_val_reg[6] 
       (.C(\entry_cnt_reg[4]_1 ),
        .CE(1'b1),
        .D(\ddr_byte_lane_B.ddr_byte_lane_B_n_230 ),
        .Q(Q[6]),
        .R(1'b0));
  FDRE \po_counter_read_val_reg[7] 
       (.C(\entry_cnt_reg[4]_1 ),
        .CE(1'b1),
        .D(\ddr_byte_lane_B.ddr_byte_lane_B_n_229 ),
        .Q(Q[7]),
        .R(1'b0));
  FDRE \po_counter_read_val_reg[8] 
       (.C(\entry_cnt_reg[4]_1 ),
        .CE(1'b1),
        .D(\ddr_byte_lane_B.ddr_byte_lane_B_n_228 ),
        .Q(Q[8]),
        .R(1'b0));
  (* srl_bus_name = "\u_mig_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/rclk_delay_reg " *) 
  (* srl_name = "\u_mig_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/rclk_delay_reg[10]_srl11 " *) 
  SRL16E \rclk_delay_reg[10]_srl11 
       (.A0(1'b0),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b1),
        .CE(1'b1),
        .CLK(\entry_cnt_reg[4]_1 ),
        .D(\rclk_delay_reg[11]_0 ),
        .Q(\rclk_delay_reg[10]_srl11_n_0 ));
  FDRE \rclk_delay_reg[11] 
       (.C(\entry_cnt_reg[4]_1 ),
        .CE(1'b1),
        .D(\rclk_delay_reg[10]_srl11_n_0 ),
        .Q(rclk_delay_11),
        .R(1'b0));
  FDCE #(
    .INIT(1'b0)) 
    rst_out_reg
       (.C(\entry_cnt_reg[4]_1 ),
        .CE(1'b1),
        .CLR(SR),
        .D(rst_out_reg_1),
        .Q(rst_out_reg_0));
  FDRE #(
    .INIT(1'b0)) 
    rst_primitives_reg
       (.C(\entry_cnt_reg[4]_1 ),
        .CE(1'b1),
        .D(rst_primitives_reg_0),
        .Q(rst_primitives),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_phy_4lanes" *) 
module mig_mig_7series_v4_2_ddr_phy_4lanes__parameterized0
   (phy_ctl_mstr_empty,
    _phy_ctl_full_p,
    ref_dll_lock_w,
    mcGo_w__0,
    \my_empty_reg[1] ,
    \my_empty_reg[1]_0 ,
    mem_out,
    \rd_ptr_reg[3] ,
    mem_dq_out,
    \po_counter_read_val_reg[0]_0 ,
    \po_counter_read_val_reg[1]_0 ,
    \po_counter_read_val_reg[2]_0 ,
    \po_counter_read_val_reg[3]_0 ,
    \po_counter_read_val_reg[4]_0 ,
    \po_counter_read_val_reg[5]_0 ,
    \po_counter_read_val_reg[6]_0 ,
    \po_counter_read_val_reg[7]_0 ,
    \po_counter_read_val_reg[8]_0 ,
    ddr_ck_out,
    \my_empty_reg[1]_1 ,
    \rd_ptr_reg[3]_0 ,
    of_ctl_full_v,
    \po_counter_read_val_reg[8]_1 ,
    \po_counter_read_val_reg[8]_2 ,
    \po_counter_read_val_reg[8]_3 ,
    \po_counter_read_val_reg[8]_4 ,
    freq_refclk,
    mem_refclk,
    sync_pulse,
    \wr_ptr_timing_reg[3] ,
    \my_full_reg[3] ,
    \my_full_reg[3]_0 ,
    \my_full_reg[3]_1 ,
    \my_full_reg[3]_2 ,
    \my_full_reg[3]_3 ,
    \po_counter_read_val_reg[8]_5 ,
    \po_counter_read_val_reg[8]_6 ,
    \po_counter_read_val_reg[8]_7 ,
    \po_counter_read_val_reg[8]_8 ,
    D1,
    D3,
    D4,
    D5,
    D6,
    D7,
    D8,
    \rd_ptr_reg[3]_1 ,
    phy_ctl_wr_i2,
    pll_locked,
    phy_read_calib,
    phy_mc_ctl_full_r_reg,
    phy_write_calib,
    PHYCTLWD,
    RST0,
    SR,
    phy_cmd_wr_en,
    out_fifo,
    mc_cas_n,
    mc_we_n,
    out_fifo_0,
    mc_ras_n,
    mc_cs_n,
    mc_address,
    out_fifo_i_47__8,
    mux_address,
    d_in,
    \po_counter_read_val_reg[0]_1 ,
    calib_sel,
    Q,
    \po_rdval_cnt_reg[8] ,
    C_po_coarse_enable26_out,
    C_po_counter_read_en38_out,
    C_po_fine_enable23_out,
    C_po_fine_inc29_out,
    \my_empty_reg[7] ,
    \my_empty_reg[7]_0 ,
    \my_empty_reg[7]_1 ,
    \my_empty_reg[7]_2 ,
    D9,
    out_fifo_i_39,
    out_fifo_1);
  output phy_ctl_mstr_empty;
  output [0:0]_phy_ctl_full_p;
  output [0:0]ref_dll_lock_w;
  output [0:0]mcGo_w__0;
  output \my_empty_reg[1] ;
  output \my_empty_reg[1]_0 ;
  output [11:0]mem_out;
  output [35:0]\rd_ptr_reg[3] ;
  output [22:0]mem_dq_out;
  output \po_counter_read_val_reg[0]_0 ;
  output \po_counter_read_val_reg[1]_0 ;
  output \po_counter_read_val_reg[2]_0 ;
  output \po_counter_read_val_reg[3]_0 ;
  output \po_counter_read_val_reg[4]_0 ;
  output \po_counter_read_val_reg[5]_0 ;
  output \po_counter_read_val_reg[6]_0 ;
  output \po_counter_read_val_reg[7]_0 ;
  output \po_counter_read_val_reg[8]_0 ;
  output [1:0]ddr_ck_out;
  output \my_empty_reg[1]_1 ;
  output [23:0]\rd_ptr_reg[3]_0 ;
  output [0:0]of_ctl_full_v;
  input \po_counter_read_val_reg[8]_1 ;
  input \po_counter_read_val_reg[8]_2 ;
  input \po_counter_read_val_reg[8]_3 ;
  input \po_counter_read_val_reg[8]_4 ;
  input freq_refclk;
  input mem_refclk;
  input sync_pulse;
  input \wr_ptr_timing_reg[3] ;
  input [3:0]\my_full_reg[3] ;
  input [0:0]\my_full_reg[3]_0 ;
  input [1:0]\my_full_reg[3]_1 ;
  input [0:0]\my_full_reg[3]_2 ;
  input [3:0]\my_full_reg[3]_3 ;
  input \po_counter_read_val_reg[8]_5 ;
  input \po_counter_read_val_reg[8]_6 ;
  input \po_counter_read_val_reg[8]_7 ;
  input \po_counter_read_val_reg[8]_8 ;
  input [3:0]D1;
  input [3:0]D3;
  input [3:0]D4;
  input [3:0]D5;
  input [7:0]D6;
  input [3:0]D7;
  input [3:0]D8;
  input [3:0]\rd_ptr_reg[3]_1 ;
  input phy_ctl_wr_i2;
  input pll_locked;
  input phy_read_calib;
  input phy_mc_ctl_full_r_reg;
  input phy_write_calib;
  input [10:0]PHYCTLWD;
  input RST0;
  input [0:0]SR;
  input phy_cmd_wr_en;
  input out_fifo;
  input [2:0]mc_cas_n;
  input [1:0]mc_we_n;
  input out_fifo_0;
  input [1:0]mc_ras_n;
  input [0:0]mc_cs_n;
  input [3:0]mc_address;
  input [12:0]out_fifo_i_47__8;
  input [48:0]mux_address;
  input [4:0]d_in;
  input [0:0]\po_counter_read_val_reg[0]_1 ;
  input [3:0]calib_sel;
  input [8:0]Q;
  input [8:0]\po_rdval_cnt_reg[8] ;
  input C_po_coarse_enable26_out;
  input C_po_counter_read_en38_out;
  input C_po_fine_enable23_out;
  input C_po_fine_inc29_out;
  input [3:0]\my_empty_reg[7] ;
  input [7:0]\my_empty_reg[7]_0 ;
  input [3:0]\my_empty_reg[7]_1 ;
  input [3:0]\my_empty_reg[7]_2 ;
  input [3:0]D9;
  input [11:0]out_fifo_i_39;
  input out_fifo_1;

  (* async_reg = "true" *) wire A_pi_rst_div2;
  (* async_reg = "true" *) wire B_pi_rst_div2;
  wire B_rst_primitives;
  wire C_of_full;
  (* async_reg = "true" *) wire C_pi_rst_div2;
  wire C_po_coarse_enable26_out;
  wire C_po_counter_read_en38_out;
  wire [8:0]C_po_counter_read_val;
  wire C_po_fine_enable23_out;
  wire C_po_fine_inc29_out;
  wire [3:0]D1;
  wire [3:0]D3;
  wire [3:0]D4;
  wire [3:0]D5;
  wire [7:0]D6;
  wire [3:0]D7;
  wire [3:0]D8;
  wire [3:0]D9;
  wire D_of_full;
  (* async_reg = "true" *) wire D_pi_rst_div2;
  wire [8:0]D_po_counter_read_val;
  wire [10:0]PHYCTLWD;
  wire [8:0]Q;
  wire RST0;
  wire [0:0]SR;
  wire [0:0]_phy_ctl_full_p;
  wire [3:0]calib_sel;
  wire [4:0]d_in;
  wire \ddr_byte_lane_B.ddr_byte_lane_B_n_21 ;
  wire \ddr_byte_lane_B.ddr_byte_lane_B_n_22 ;
  wire \ddr_byte_lane_B.ddr_byte_lane_B_n_23 ;
  wire \ddr_byte_lane_B.ddr_byte_lane_B_n_24 ;
  wire \ddr_byte_lane_B.ddr_byte_lane_B_n_25 ;
  wire \ddr_byte_lane_B.ddr_byte_lane_B_n_26 ;
  wire \ddr_byte_lane_B.ddr_byte_lane_B_n_27 ;
  wire \ddr_byte_lane_B.ddr_byte_lane_B_n_28 ;
  wire \ddr_byte_lane_B.ddr_byte_lane_B_n_29 ;
  wire [1:0]ddr_ck_out;
  wire freq_refclk;
  wire [0:0]mcGo_w__0;
  wire [3:0]mc_address;
  wire [2:0]mc_cas_n;
  wire [0:0]mc_cs_n;
  wire [1:0]mc_ras_n;
  wire [1:0]mc_we_n;
  wire [22:0]mem_dq_out;
  wire [11:0]mem_out;
  wire mem_refclk;
  wire [48:0]mux_address;
  wire \my_empty_reg[1] ;
  wire \my_empty_reg[1]_0 ;
  wire \my_empty_reg[1]_1 ;
  wire [3:0]\my_empty_reg[7] ;
  wire [7:0]\my_empty_reg[7]_0 ;
  wire [3:0]\my_empty_reg[7]_1 ;
  wire [3:0]\my_empty_reg[7]_2 ;
  wire [3:0]\my_full_reg[3] ;
  wire [0:0]\my_full_reg[3]_0 ;
  wire [1:0]\my_full_reg[3]_1 ;
  wire [0:0]\my_full_reg[3]_2 ;
  wire [3:0]\my_full_reg[3]_3 ;
  wire [0:0]of_ctl_full_v;
  wire ofifo_rst;
  wire out_fifo;
  wire out_fifo_0;
  wire out_fifo_1;
  wire [11:0]out_fifo_i_39;
  wire [12:0]out_fifo_i_47__8;
  wire [2:2]phaser_ctl_bus;
  wire phy_cmd_wr_en;
  wire phy_control_i_n_0;
  wire phy_control_i_n_10;
  wire phy_control_i_n_11;
  wire phy_control_i_n_14;
  wire phy_control_i_n_15;
  wire phy_control_i_n_16;
  wire phy_control_i_n_17;
  wire phy_control_i_n_18;
  wire phy_control_i_n_19;
  wire phy_control_i_n_20;
  wire phy_control_i_n_21;
  wire phy_control_i_n_22;
  wire phy_control_i_n_24;
  wire phy_control_i_n_25;
  wire phy_control_i_n_3;
  wire phy_control_i_n_4;
  wire phy_control_i_n_5;
  wire phy_control_i_n_6;
  wire phy_control_i_n_7;
  wire phy_control_i_n_8;
  wire phy_control_i_n_9;
  wire phy_ctl_mstr_empty;
  wire phy_ctl_wr_i2;
  wire [1:0]phy_encalib;
  wire phy_mc_ctl_full_r_reg;
  wire phy_read_calib;
  wire phy_write_calib;
  wire pll_locked;
  wire \po_counter_read_val_reg[0]_0 ;
  wire [0:0]\po_counter_read_val_reg[0]_1 ;
  wire \po_counter_read_val_reg[1]_0 ;
  wire \po_counter_read_val_reg[2]_0 ;
  wire \po_counter_read_val_reg[3]_0 ;
  wire \po_counter_read_val_reg[4]_0 ;
  wire \po_counter_read_val_reg[5]_0 ;
  wire \po_counter_read_val_reg[6]_0 ;
  wire \po_counter_read_val_reg[7]_0 ;
  wire \po_counter_read_val_reg[8]_0 ;
  wire \po_counter_read_val_reg[8]_1 ;
  wire \po_counter_read_val_reg[8]_2 ;
  wire \po_counter_read_val_reg[8]_3 ;
  wire \po_counter_read_val_reg[8]_4 ;
  wire \po_counter_read_val_reg[8]_5 ;
  wire \po_counter_read_val_reg[8]_6 ;
  wire \po_counter_read_val_reg[8]_7 ;
  wire \po_counter_read_val_reg[8]_8 ;
  wire [8:0]\po_counter_read_val_w[1]_4 ;
  wire [8:0]\po_rdval_cnt_reg[8] ;
  wire rclk_delay_11;
  wire \rclk_delay_reg[10]_srl11_i_1__1_n_0 ;
  wire \rclk_delay_reg[10]_srl11_n_0 ;
  wire [35:0]\rd_ptr_reg[3] ;
  wire [23:0]\rd_ptr_reg[3]_0 ;
  wire [3:0]\rd_ptr_reg[3]_1 ;
  wire [0:0]ref_dll_lock_w;
  wire rst_out_i_1__1_n_0;
  wire rst_out_reg_n_0;
  wire rst_primitives;
  wire rst_primitives_i_1__1_n_0;
  wire sync_pulse;
  wire \wr_ptr_timing_reg[3] ;

  FDRE #(
    .INIT(1'b0)) 
    B_rst_primitives_reg
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rst_primitives),
        .Q(B_rst_primitives),
        .R(1'b0));
  mig_mig_7series_v4_2_ddr_byte_lane__parameterized3 \ddr_byte_lane_B.ddr_byte_lane_B 
       (.B_rst_primitives(B_rst_primitives),
        .COUNTERREADVAL(D_po_counter_read_val),
        .C_of_full(C_of_full),
        .D({\ddr_byte_lane_B.ddr_byte_lane_B_n_21 ,\ddr_byte_lane_B.ddr_byte_lane_B_n_22 ,\ddr_byte_lane_B.ddr_byte_lane_B_n_23 ,\ddr_byte_lane_B.ddr_byte_lane_B_n_24 ,\ddr_byte_lane_B.ddr_byte_lane_B_n_25 ,\ddr_byte_lane_B.ddr_byte_lane_B_n_26 ,\ddr_byte_lane_B.ddr_byte_lane_B_n_27 ,\ddr_byte_lane_B.ddr_byte_lane_B_n_28 ,\ddr_byte_lane_B.ddr_byte_lane_B_n_29 }),
        .D_of_full(D_of_full),
        .OUTBURSTPENDING(phy_control_i_n_24),
        .PCENABLECALIB(phy_encalib),
        .SR(ofifo_rst),
        .calib_sel(calib_sel[1:0]),
        .freq_refclk(freq_refclk),
        .mc_cas_n({mc_cas_n[2],mc_cas_n[0]}),
        .mc_cs_n(mc_cs_n),
        .mc_ras_n(mc_ras_n),
        .mc_we_n(mc_we_n),
        .mem_dq_out(mem_dq_out[5:0]),
        .mem_out(mem_out),
        .mem_refclk(mem_refclk),
        .\my_empty_reg[1] (\my_empty_reg[1] ),
        .\my_full_reg[3] (\wr_ptr_timing_reg[3] ),
        .\my_full_reg[3]_0 (\my_full_reg[3] ),
        .\my_full_reg[3]_1 (\my_full_reg[3]_0 ),
        .\my_full_reg[3]_2 (\my_full_reg[3]_1 ),
        .\my_full_reg[3]_3 (\my_full_reg[3]_2 ),
        .\my_full_reg[3]_4 (\my_full_reg[3]_3 ),
        .of_ctl_full_v(of_ctl_full_v),
        .out_fifo_0(out_fifo_0),
        .out_fifo_i_47__8(out_fifo_i_47__8),
        .phy_cmd_wr_en(phy_cmd_wr_en),
        .\po_counter_read_val_reg[8] (\po_counter_read_val_reg[8]_1 ),
        .\po_counter_read_val_reg[8]_0 (\po_counter_read_val_reg[8]_2 ),
        .\po_counter_read_val_reg[8]_1 (\po_counter_read_val_reg[8]_3 ),
        .\po_counter_read_val_reg[8]_2 (\po_counter_read_val_reg[8]_4 ),
        .\po_counter_read_val_reg[8]_3 (C_po_counter_read_val),
        .sync_pulse(sync_pulse));
  mig_mig_7series_v4_2_ddr_byte_lane__parameterized4 \ddr_byte_lane_C.ddr_byte_lane_C 
       (.B_rst_primitives(B_rst_primitives),
        .B_rst_primitives_reg(C_po_counter_read_val),
        .C_of_full(C_of_full),
        .C_po_coarse_enable26_out(C_po_coarse_enable26_out),
        .C_po_counter_read_en38_out(C_po_counter_read_en38_out),
        .C_po_fine_enable23_out(C_po_fine_enable23_out),
        .C_po_fine_inc29_out(C_po_fine_inc29_out),
        .D9(D9),
        .OUTBURSTPENDING(phaser_ctl_bus),
        .PCENABLECALIB(phy_encalib),
        .SR(ofifo_rst),
        .ddr_ck_out(ddr_ck_out),
        .freq_refclk(freq_refclk),
        .mem_dq_out(mem_dq_out[11:6]),
        .mem_refclk(mem_refclk),
        .\my_empty_reg[1] (\my_empty_reg[1]_1 ),
        .\my_empty_reg[7] (\my_empty_reg[7] ),
        .\my_empty_reg[7]_0 (\my_empty_reg[7]_0 ),
        .\my_empty_reg[7]_1 (\my_empty_reg[7]_1 ),
        .\my_empty_reg[7]_2 (\my_empty_reg[7]_2 ),
        .phy_cmd_wr_en(phy_cmd_wr_en),
        .phy_dout({mux_address[43],mux_address[31],mux_address[18],mux_address[6],mux_address[39],mux_address[27],mux_address[14],mux_address[2],out_fifo_i_39,mux_address[45],mux_address[33],mux_address[20],mux_address[8]}),
        .\rd_ptr_reg[3] (\rd_ptr_reg[3]_0 ),
        .sync_pulse(sync_pulse),
        .\wr_ptr_timing_reg[3] (\wr_ptr_timing_reg[3] ));
  mig_mig_7series_v4_2_ddr_byte_lane__parameterized5 \ddr_byte_lane_D.ddr_byte_lane_D 
       (.B_rst_primitives(B_rst_primitives),
        .COUNTERREADVAL(D_po_counter_read_val),
        .D1(D1),
        .D3(D3),
        .D4(D4),
        .D5(D5),
        .D6(D6),
        .D7(D7),
        .D8(D8),
        .D_of_full(D_of_full),
        .OUTBURSTPENDING(phy_control_i_n_22),
        .PCENABLECALIB(phy_encalib),
        .SR(ofifo_rst),
        .d_in({mux_address[46],mux_address[34],mux_address[21],mux_address[9],mux_address[38],mux_address[26],mux_address[13],mux_address[1],mux_address[42],mux_address[30],mux_address[17],mux_address[5],mux_address[37],mux_address[25],mux_address[12],mux_address[0],mux_address[48],mux_address[36],mux_address[23],mux_address[11],mux_address[40],mux_address[28],mux_address[15],mux_address[3],d_in[4:3],mux_address[24],d_in[2],mux_address[41],mux_address[29],mux_address[16],mux_address[4],mux_address[47],mux_address[35],mux_address[22],mux_address[10],d_in[1:0],mux_address[44],mux_address[32],mux_address[19],mux_address[7]}),
        .freq_refclk(freq_refclk),
        .mc_address(mc_address),
        .mc_cas_n(mc_cas_n[1]),
        .mem_dq_out(mem_dq_out[22:12]),
        .mem_refclk(mem_refclk),
        .\my_empty_reg[1] (\my_empty_reg[1]_0 ),
        .out_fifo_0(out_fifo),
        .out_fifo_1(out_fifo_0),
        .out_fifo_2(out_fifo_1),
        .phy_cmd_wr_en(phy_cmd_wr_en),
        .\po_counter_read_val_reg[8] (\po_counter_read_val_reg[8]_5 ),
        .\po_counter_read_val_reg[8]_0 (\po_counter_read_val_reg[8]_6 ),
        .\po_counter_read_val_reg[8]_1 (\po_counter_read_val_reg[8]_7 ),
        .\po_counter_read_val_reg[8]_2 (\po_counter_read_val_reg[8]_8 ),
        .\rd_ptr_reg[3] (\rd_ptr_reg[3] ),
        .\rd_ptr_reg[3]_0 (\rd_ptr_reg[3]_1 ),
        .sync_pulse(sync_pulse),
        .\wr_ptr_timing_reg[3] (\wr_ptr_timing_reg[3] ));
  LUT1 #(
    .INIT(2'h2)) 
    i_0
       (.I0(1'b0),
        .O(B_pi_rst_div2));
  LUT1 #(
    .INIT(2'h2)) 
    i_1
       (.I0(1'b0),
        .O(C_pi_rst_div2));
  LUT1 #(
    .INIT(2'h2)) 
    i_2
       (.I0(1'b0),
        .O(D_pi_rst_div2));
  LUT1 #(
    .INIT(2'h2)) 
    i_3
       (.I0(1'b0),
        .O(A_pi_rst_div2));
  FDRE #(
    .INIT(1'b0)) 
    mcGo_reg
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rst_out_reg_n_0),
        .Q(mcGo_w__0),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  PHASER_REF #(
    .IS_PWRDWN_INVERTED(1'b0),
    .IS_RST_INVERTED(1'b0)) 
    phaser_ref_i
       (.CLKIN(freq_refclk),
        .LOCKED(ref_dll_lock_w),
        .PWRDWN(1'b0),
        .RST(RST0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  PHY_CONTROL #(
    .AO_TOGGLE(1),
    .AO_WRLVL_EN(4'b0000),
    .BURST_MODE("TRUE"),
    .CLK_RATIO(4),
    .CMD_OFFSET(8),
    .CO_DURATION(1),
    .DATA_CTL_A_N("FALSE"),
    .DATA_CTL_B_N("FALSE"),
    .DATA_CTL_C_N("FALSE"),
    .DATA_CTL_D_N("FALSE"),
    .DISABLE_SEQ_MATCH("TRUE"),
    .DI_DURATION(1),
    .DO_DURATION(1),
    .EVENTS_DELAY(18),
    .FOUR_WINDOW_CLOCKS(63),
    .MULTI_REGION("TRUE"),
    .PHY_COUNT_ENABLE("FALSE"),
    .RD_CMD_OFFSET_0(10),
    .RD_CMD_OFFSET_1(10),
    .RD_CMD_OFFSET_2(10),
    .RD_CMD_OFFSET_3(10),
    .RD_DURATION_0(6),
    .RD_DURATION_1(6),
    .RD_DURATION_2(6),
    .RD_DURATION_3(6),
    .SYNC_MODE("FALSE"),
    .WR_CMD_OFFSET_0(8),
    .WR_CMD_OFFSET_1(8),
    .WR_CMD_OFFSET_2(8),
    .WR_CMD_OFFSET_3(8),
    .WR_DURATION_0(7),
    .WR_DURATION_1(7),
    .WR_DURATION_2(7),
    .WR_DURATION_3(7)) 
    phy_control_i
       (.AUXOUTPUT({phy_control_i_n_14,phy_control_i_n_15,phy_control_i_n_16,phy_control_i_n_17}),
        .INBURSTPENDING({phy_control_i_n_18,phy_control_i_n_19,phy_control_i_n_20,phy_control_i_n_21}),
        .INRANKA({phy_control_i_n_4,phy_control_i_n_5}),
        .INRANKB({phy_control_i_n_6,phy_control_i_n_7}),
        .INRANKC({phy_control_i_n_8,phy_control_i_n_9}),
        .INRANKD({phy_control_i_n_10,phy_control_i_n_11}),
        .MEMREFCLK(mem_refclk),
        .OUTBURSTPENDING({phy_control_i_n_22,phaser_ctl_bus,phy_control_i_n_24,phy_control_i_n_25}),
        .PCENABLECALIB(phy_encalib),
        .PHYCLK(\wr_ptr_timing_reg[3] ),
        .PHYCTLALMOSTFULL(phy_control_i_n_0),
        .PHYCTLEMPTY(phy_ctl_mstr_empty),
        .PHYCTLFULL(_phy_ctl_full_p),
        .PHYCTLMSTREMPTY(phy_ctl_mstr_empty),
        .PHYCTLREADY(phy_control_i_n_3),
        .PHYCTLWD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b1,PHYCTLWD[10:3],1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,PHYCTLWD[2:0]}),
        .PHYCTLWRENABLE(phy_ctl_wr_i2),
        .PLLLOCK(pll_locked),
        .READCALIBENABLE(phy_read_calib),
        .REFDLLLOCK(ref_dll_lock_w),
        .RESET(phy_mc_ctl_full_r_reg),
        .SYNCIN(sync_pulse),
        .WRITECALIBENABLE(phy_write_calib));
  FDRE \po_counter_read_val_reg[0] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(\ddr_byte_lane_B.ddr_byte_lane_B_n_29 ),
        .Q(\po_counter_read_val_w[1]_4 [0]),
        .R(\po_counter_read_val_reg[0]_1 ));
  FDRE \po_counter_read_val_reg[1] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(\ddr_byte_lane_B.ddr_byte_lane_B_n_28 ),
        .Q(\po_counter_read_val_w[1]_4 [1]),
        .R(\po_counter_read_val_reg[0]_1 ));
  FDRE \po_counter_read_val_reg[2] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(\ddr_byte_lane_B.ddr_byte_lane_B_n_27 ),
        .Q(\po_counter_read_val_w[1]_4 [2]),
        .R(\po_counter_read_val_reg[0]_1 ));
  FDRE \po_counter_read_val_reg[3] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(\ddr_byte_lane_B.ddr_byte_lane_B_n_26 ),
        .Q(\po_counter_read_val_w[1]_4 [3]),
        .R(\po_counter_read_val_reg[0]_1 ));
  FDRE \po_counter_read_val_reg[4] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(\ddr_byte_lane_B.ddr_byte_lane_B_n_25 ),
        .Q(\po_counter_read_val_w[1]_4 [4]),
        .R(\po_counter_read_val_reg[0]_1 ));
  FDRE \po_counter_read_val_reg[5] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(\ddr_byte_lane_B.ddr_byte_lane_B_n_24 ),
        .Q(\po_counter_read_val_w[1]_4 [5]),
        .R(\po_counter_read_val_reg[0]_1 ));
  FDRE \po_counter_read_val_reg[6] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(\ddr_byte_lane_B.ddr_byte_lane_B_n_23 ),
        .Q(\po_counter_read_val_w[1]_4 [6]),
        .R(\po_counter_read_val_reg[0]_1 ));
  FDRE \po_counter_read_val_reg[7] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(\ddr_byte_lane_B.ddr_byte_lane_B_n_22 ),
        .Q(\po_counter_read_val_w[1]_4 [7]),
        .R(\po_counter_read_val_reg[0]_1 ));
  FDRE \po_counter_read_val_reg[8] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(\ddr_byte_lane_B.ddr_byte_lane_B_n_21 ),
        .Q(\po_counter_read_val_w[1]_4 [8]),
        .R(\po_counter_read_val_reg[0]_1 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \po_rdval_cnt[0]_i_2 
       (.I0(\po_counter_read_val_w[1]_4 [0]),
        .I1(calib_sel[2]),
        .I2(Q[0]),
        .I3(calib_sel[3]),
        .I4(\po_rdval_cnt_reg[8] [0]),
        .O(\po_counter_read_val_reg[0]_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \po_rdval_cnt[1]_i_2 
       (.I0(\po_counter_read_val_w[1]_4 [1]),
        .I1(calib_sel[2]),
        .I2(Q[1]),
        .I3(calib_sel[3]),
        .I4(\po_rdval_cnt_reg[8] [1]),
        .O(\po_counter_read_val_reg[1]_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \po_rdval_cnt[2]_i_2 
       (.I0(\po_counter_read_val_w[1]_4 [2]),
        .I1(calib_sel[2]),
        .I2(Q[2]),
        .I3(calib_sel[3]),
        .I4(\po_rdval_cnt_reg[8] [2]),
        .O(\po_counter_read_val_reg[2]_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \po_rdval_cnt[3]_i_2 
       (.I0(\po_counter_read_val_w[1]_4 [3]),
        .I1(calib_sel[2]),
        .I2(Q[3]),
        .I3(calib_sel[3]),
        .I4(\po_rdval_cnt_reg[8] [3]),
        .O(\po_counter_read_val_reg[3]_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \po_rdval_cnt[4]_i_2 
       (.I0(\po_counter_read_val_w[1]_4 [4]),
        .I1(calib_sel[2]),
        .I2(Q[4]),
        .I3(calib_sel[3]),
        .I4(\po_rdval_cnt_reg[8] [4]),
        .O(\po_counter_read_val_reg[4]_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \po_rdval_cnt[5]_i_2 
       (.I0(\po_counter_read_val_w[1]_4 [5]),
        .I1(calib_sel[2]),
        .I2(Q[5]),
        .I3(calib_sel[3]),
        .I4(\po_rdval_cnt_reg[8] [5]),
        .O(\po_counter_read_val_reg[5]_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \po_rdval_cnt[6]_i_2 
       (.I0(\po_counter_read_val_w[1]_4 [6]),
        .I1(calib_sel[2]),
        .I2(Q[6]),
        .I3(calib_sel[3]),
        .I4(\po_rdval_cnt_reg[8] [6]),
        .O(\po_counter_read_val_reg[6]_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \po_rdval_cnt[7]_i_2 
       (.I0(\po_counter_read_val_w[1]_4 [7]),
        .I1(calib_sel[2]),
        .I2(Q[7]),
        .I3(calib_sel[3]),
        .I4(\po_rdval_cnt_reg[8] [7]),
        .O(\po_counter_read_val_reg[7]_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \po_rdval_cnt[8]_i_4 
       (.I0(\po_counter_read_val_w[1]_4 [8]),
        .I1(calib_sel[2]),
        .I2(Q[8]),
        .I3(calib_sel[3]),
        .I4(\po_rdval_cnt_reg[8] [8]),
        .O(\po_counter_read_val_reg[8]_0 ));
  (* srl_bus_name = "\u_mig_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/rclk_delay_reg " *) 
  (* srl_name = "\u_mig_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/rclk_delay_reg[10]_srl11 " *) 
  SRL16E \rclk_delay_reg[10]_srl11 
       (.A0(1'b0),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b1),
        .CE(1'b1),
        .CLK(\wr_ptr_timing_reg[3] ),
        .D(\rclk_delay_reg[10]_srl11_i_1__1_n_0 ),
        .Q(\rclk_delay_reg[10]_srl11_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \rclk_delay_reg[10]_srl11_i_1__1 
       (.I0(rst_primitives),
        .O(\rclk_delay_reg[10]_srl11_i_1__1_n_0 ));
  FDRE \rclk_delay_reg[11] 
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(\rclk_delay_reg[10]_srl11_n_0 ),
        .Q(rclk_delay_11),
        .R(1'b0));
  LUT2 #(
    .INIT(4'hE)) 
    rst_out_i_1__1
       (.I0(rclk_delay_11),
        .I1(rst_out_reg_n_0),
        .O(rst_out_i_1__1_n_0));
  FDCE #(
    .INIT(1'b0)) 
    rst_out_reg
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .CLR(SR),
        .D(rst_out_i_1__1_n_0),
        .Q(rst_out_reg_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    rst_primitives_i_1__1
       (.I0(phy_control_i_n_3),
        .O(rst_primitives_i_1__1_n_0));
  FDRE #(
    .INIT(1'b0)) 
    rst_primitives_reg
       (.C(\wr_ptr_timing_reg[3] ),
        .CE(1'b1),
        .D(rst_primitives_i_1__1_n_0),
        .Q(rst_primitives),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay" *) 
module mig_mig_7series_v4_2_ddr_phy_ck_addr_cmd_delay
   (ck_addr_cmd_delay_done,
    cmd_po_en_stg2_f,
    po_cnt_dec_2,
    delaydec_cnt_r10_in,
    ctl_lane_cnt,
    E,
    delay_done_r4_reg_0,
    po_en_stg2_f_reg_0,
    pi_fine_dly_dec_done,
    dqs_po_dec_done,
    \ctl_lane_cnt_reg[1]_0 ,
    \gen_byte_sel_div2.byte_sel_cnt_reg[0] ,
    tempmon_sel_pi_incdec,
    \gen_byte_sel_div2.byte_sel_cnt_reg[0]_0 ,
    \gen_byte_sel_div2.byte_sel_cnt_reg[0]_1 ,
    \gen_byte_sel_div2.byte_sel_cnt_reg[0]_2 ,
    cmd_delay_start0,
    p_1_in,
    SS,
    \wait_cnt_r_reg[0]_0 );
  output ck_addr_cmd_delay_done;
  output cmd_po_en_stg2_f;
  output po_cnt_dec_2;
  output delaydec_cnt_r10_in;
  output [2:0]ctl_lane_cnt;
  output [0:0]E;
  input delay_done_r4_reg_0;
  input po_en_stg2_f_reg_0;
  input pi_fine_dly_dec_done;
  input dqs_po_dec_done;
  input \ctl_lane_cnt_reg[1]_0 ;
  input \gen_byte_sel_div2.byte_sel_cnt_reg[0] ;
  input tempmon_sel_pi_incdec;
  input \gen_byte_sel_div2.byte_sel_cnt_reg[0]_0 ;
  input \gen_byte_sel_div2.byte_sel_cnt_reg[0]_1 ;
  input \gen_byte_sel_div2.byte_sel_cnt_reg[0]_2 ;
  input cmd_delay_start0;
  input p_1_in;
  input [0:0]SS;
  input [0:0]\wait_cnt_r_reg[0]_0 ;

  wire [0:0]E;
  wire [0:0]SS;
  wire ck_addr_cmd_delay_done;
  wire cmd_delay_start0;
  wire cmd_po_en_stg2_f;
  wire [2:0]ctl_lane_cnt;
  wire ctl_lane_cnt1;
  wire \ctl_lane_cnt[0]_i_1_n_0 ;
  wire \ctl_lane_cnt[1]_i_1_n_0 ;
  wire \ctl_lane_cnt[2]_i_1_n_0 ;
  wire \ctl_lane_cnt[2]_i_5_n_0 ;
  wire \ctl_lane_cnt_reg[1]_0 ;
  wire delay_dec_done;
  wire delay_dec_done_i_1_n_0;
  wire delay_dec_done_i_2_n_0;
  wire delay_done_r3_reg_srl3_n_0;
  wire delay_done_r4_reg_0;
  wire delaydec_cnt_r0;
  wire delaydec_cnt_r10_in;
  wire \delaydec_cnt_r[0]_i_1_n_0 ;
  wire \delaydec_cnt_r[1]_i_1_n_0 ;
  wire \delaydec_cnt_r[2]_i_1_n_0 ;
  wire \delaydec_cnt_r[3]_i_1_n_0 ;
  wire \delaydec_cnt_r[4]_i_1_n_0 ;
  wire \delaydec_cnt_r[5]_i_3_n_0 ;
  wire [5:0]delaydec_cnt_r_reg;
  wire dqs_po_dec_done;
  wire \gen_byte_sel_div2.byte_sel_cnt_reg[0] ;
  wire \gen_byte_sel_div2.byte_sel_cnt_reg[0]_0 ;
  wire \gen_byte_sel_div2.byte_sel_cnt_reg[0]_1 ;
  wire \gen_byte_sel_div2.byte_sel_cnt_reg[0]_2 ;
  wire p_1_in;
  wire pi_fine_dly_dec_done;
  wire po_cnt_dec_2;
  wire po_cnt_dec_i_1__0_n_0;
  wire po_cnt_inc1;
  wire po_cnt_inc2;
  wire po_en_stg2_f_reg_0;
  wire tempmon_sel_pi_incdec;
  wire wait_cnt_r0;
  wire [0:0]wait_cnt_r0__0;
  wire \wait_cnt_r[1]_i_1_n_0 ;
  wire \wait_cnt_r[2]_i_1__0_n_0 ;
  wire \wait_cnt_r[3]_i_3__0_n_0 ;
  wire [3:0]wait_cnt_r_reg;
  wire [0:0]\wait_cnt_r_reg[0]_0 ;

  LUT6 #(
    .INIT(64'h0000000006000000)) 
    \ctl_lane_cnt[0]_i_1 
       (.I0(ctl_lane_cnt[0]),
        .I1(delaydec_cnt_r10_in),
        .I2(\ctl_lane_cnt_reg[1]_0 ),
        .I3(pi_fine_dly_dec_done),
        .I4(dqs_po_dec_done),
        .I5(ctl_lane_cnt1),
        .O(\ctl_lane_cnt[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000DEEE0000)) 
    \ctl_lane_cnt[1]_i_1 
       (.I0(ctl_lane_cnt[1]),
        .I1(ctl_lane_cnt1),
        .I2(delaydec_cnt_r10_in),
        .I3(ctl_lane_cnt[0]),
        .I4(cmd_delay_start0),
        .I5(\ctl_lane_cnt_reg[1]_0 ),
        .O(\ctl_lane_cnt[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000006AAA)) 
    \ctl_lane_cnt[2]_i_1 
       (.I0(ctl_lane_cnt[2]),
        .I1(delaydec_cnt_r10_in),
        .I2(ctl_lane_cnt[1]),
        .I3(ctl_lane_cnt[0]),
        .I4(p_1_in),
        .I5(ctl_lane_cnt1),
        .O(\ctl_lane_cnt[2]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hA8AA)) 
    \ctl_lane_cnt[2]_i_2 
       (.I0(delay_dec_done_i_2_n_0),
        .I1(ctl_lane_cnt[2]),
        .I2(ctl_lane_cnt[0]),
        .I3(ctl_lane_cnt[1]),
        .O(delaydec_cnt_r10_in));
  LUT6 #(
    .INIT(64'h0000000000040000)) 
    \ctl_lane_cnt[2]_i_4 
       (.I0(\ctl_lane_cnt[2]_i_5_n_0 ),
        .I1(delaydec_cnt_r_reg[0]),
        .I2(delay_dec_done),
        .I3(ctl_lane_cnt[0]),
        .I4(ctl_lane_cnt[1]),
        .I5(ctl_lane_cnt[2]),
        .O(ctl_lane_cnt1));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \ctl_lane_cnt[2]_i_5 
       (.I0(delaydec_cnt_r_reg[1]),
        .I1(delaydec_cnt_r_reg[4]),
        .I2(delaydec_cnt_r_reg[5]),
        .I3(delaydec_cnt_r_reg[2]),
        .I4(delaydec_cnt_r_reg[3]),
        .O(\ctl_lane_cnt[2]_i_5_n_0 ));
  FDRE \ctl_lane_cnt_reg[0] 
       (.C(delay_done_r4_reg_0),
        .CE(1'b1),
        .D(\ctl_lane_cnt[0]_i_1_n_0 ),
        .Q(ctl_lane_cnt[0]),
        .R(1'b0));
  FDRE \ctl_lane_cnt_reg[1] 
       (.C(delay_done_r4_reg_0),
        .CE(1'b1),
        .D(\ctl_lane_cnt[1]_i_1_n_0 ),
        .Q(ctl_lane_cnt[1]),
        .R(1'b0));
  FDRE \ctl_lane_cnt_reg[2] 
       (.C(delay_done_r4_reg_0),
        .CE(1'b1),
        .D(\ctl_lane_cnt[2]_i_1_n_0 ),
        .Q(ctl_lane_cnt[2]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h00000000AAAAAEAA)) 
    delay_dec_done_i_1
       (.I0(delay_dec_done),
        .I1(delay_dec_done_i_2_n_0),
        .I2(ctl_lane_cnt[2]),
        .I3(ctl_lane_cnt[1]),
        .I4(ctl_lane_cnt[0]),
        .I5(p_1_in),
        .O(delay_dec_done_i_1_n_0));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    delay_dec_done_i_2
       (.I0(delaydec_cnt_r_reg[3]),
        .I1(delaydec_cnt_r_reg[2]),
        .I2(delaydec_cnt_r_reg[5]),
        .I3(delaydec_cnt_r_reg[4]),
        .I4(delaydec_cnt_r_reg[1]),
        .I5(delaydec_cnt_r_reg[0]),
        .O(delay_dec_done_i_2_n_0));
  FDRE delay_dec_done_reg
       (.C(delay_done_r4_reg_0),
        .CE(1'b1),
        .D(delay_dec_done_i_1_n_0),
        .Q(delay_dec_done),
        .R(1'b0));
  (* srl_name = "\u_mig_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay/delay_done_r3_reg_srl3 " *) 
  SRL16E delay_done_r3_reg_srl3
       (.A0(1'b0),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(delay_done_r4_reg_0),
        .D(delay_dec_done),
        .Q(delay_done_r3_reg_srl3_n_0));
  (* syn_maxfan = "10" *) 
  FDRE delay_done_r4_reg
       (.C(delay_done_r4_reg_0),
        .CE(1'b1),
        .D(delay_done_r3_reg_srl3_n_0),
        .Q(ck_addr_cmd_delay_done),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair297" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \delaydec_cnt_r[0]_i_1 
       (.I0(delaydec_cnt_r_reg[0]),
        .O(\delaydec_cnt_r[0]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \delaydec_cnt_r[1]_i_1 
       (.I0(delaydec_cnt_r_reg[0]),
        .I1(delaydec_cnt_r_reg[1]),
        .O(\delaydec_cnt_r[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair297" *) 
  LUT3 #(
    .INIT(8'hE1)) 
    \delaydec_cnt_r[2]_i_1 
       (.I0(delaydec_cnt_r_reg[1]),
        .I1(delaydec_cnt_r_reg[0]),
        .I2(delaydec_cnt_r_reg[2]),
        .O(\delaydec_cnt_r[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair295" *) 
  LUT4 #(
    .INIT(16'hFE01)) 
    \delaydec_cnt_r[3]_i_1 
       (.I0(delaydec_cnt_r_reg[2]),
        .I1(delaydec_cnt_r_reg[0]),
        .I2(delaydec_cnt_r_reg[1]),
        .I3(delaydec_cnt_r_reg[3]),
        .O(\delaydec_cnt_r[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair295" *) 
  LUT5 #(
    .INIT(32'hFFFE0001)) 
    \delaydec_cnt_r[4]_i_1 
       (.I0(delaydec_cnt_r_reg[3]),
        .I1(delaydec_cnt_r_reg[1]),
        .I2(delaydec_cnt_r_reg[0]),
        .I3(delaydec_cnt_r_reg[2]),
        .I4(delaydec_cnt_r_reg[4]),
        .O(\delaydec_cnt_r[4]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \delaydec_cnt_r[5]_i_2 
       (.I0(po_cnt_dec_2),
        .I1(po_cnt_inc2),
        .O(delaydec_cnt_r0));
  LUT6 #(
    .INIT(64'hFFFFFFFE00000001)) 
    \delaydec_cnt_r[5]_i_3 
       (.I0(delaydec_cnt_r_reg[4]),
        .I1(delaydec_cnt_r_reg[2]),
        .I2(delaydec_cnt_r_reg[0]),
        .I3(delaydec_cnt_r_reg[1]),
        .I4(delaydec_cnt_r_reg[3]),
        .I5(delaydec_cnt_r_reg[5]),
        .O(\delaydec_cnt_r[5]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \delaydec_cnt_r[5]_i_4 
       (.I0(delaydec_cnt_r_reg[2]),
        .I1(delaydec_cnt_r_reg[1]),
        .I2(delaydec_cnt_r_reg[5]),
        .I3(delaydec_cnt_r_reg[0]),
        .I4(delaydec_cnt_r_reg[3]),
        .I5(delaydec_cnt_r_reg[4]),
        .O(po_cnt_inc2));
  FDSE \delaydec_cnt_r_reg[0] 
       (.C(delay_done_r4_reg_0),
        .CE(delaydec_cnt_r0),
        .D(\delaydec_cnt_r[0]_i_1_n_0 ),
        .Q(delaydec_cnt_r_reg[0]),
        .S(SS));
  FDRE \delaydec_cnt_r_reg[1] 
       (.C(delay_done_r4_reg_0),
        .CE(delaydec_cnt_r0),
        .D(\delaydec_cnt_r[1]_i_1_n_0 ),
        .Q(delaydec_cnt_r_reg[1]),
        .R(SS));
  FDSE \delaydec_cnt_r_reg[2] 
       (.C(delay_done_r4_reg_0),
        .CE(delaydec_cnt_r0),
        .D(\delaydec_cnt_r[2]_i_1_n_0 ),
        .Q(delaydec_cnt_r_reg[2]),
        .S(SS));
  FDSE \delaydec_cnt_r_reg[3] 
       (.C(delay_done_r4_reg_0),
        .CE(delaydec_cnt_r0),
        .D(\delaydec_cnt_r[3]_i_1_n_0 ),
        .Q(delaydec_cnt_r_reg[3]),
        .S(SS));
  FDSE \delaydec_cnt_r_reg[4] 
       (.C(delay_done_r4_reg_0),
        .CE(delaydec_cnt_r0),
        .D(\delaydec_cnt_r[4]_i_1_n_0 ),
        .Q(delaydec_cnt_r_reg[4]),
        .S(SS));
  FDRE \delaydec_cnt_r_reg[5] 
       (.C(delay_done_r4_reg_0),
        .CE(delaydec_cnt_r0),
        .D(\delaydec_cnt_r[5]_i_3_n_0 ),
        .Q(delaydec_cnt_r_reg[5]),
        .R(SS));
  LUT6 #(
    .INIT(64'hA2AAAAAAAAAAAAAA)) 
    \gen_byte_sel_div2.byte_sel_cnt[3]_i_2 
       (.I0(ck_addr_cmd_delay_done),
        .I1(\gen_byte_sel_div2.byte_sel_cnt_reg[0] ),
        .I2(tempmon_sel_pi_incdec),
        .I3(\gen_byte_sel_div2.byte_sel_cnt_reg[0]_0 ),
        .I4(\gen_byte_sel_div2.byte_sel_cnt_reg[0]_1 ),
        .I5(\gen_byte_sel_div2.byte_sel_cnt_reg[0]_2 ),
        .O(E));
  LUT6 #(
    .INIT(64'h0000000000008000)) 
    po_cnt_dec_i_1__0
       (.I0(pi_fine_dly_dec_done),
        .I1(dqs_po_dec_done),
        .I2(po_cnt_inc2),
        .I3(po_cnt_inc1),
        .I4(delay_dec_done_i_2_n_0),
        .I5(\ctl_lane_cnt_reg[1]_0 ),
        .O(po_cnt_dec_i_1__0_n_0));
  (* SOFT_HLUTNM = "soft_lutpair296" *) 
  LUT4 #(
    .INIT(16'h0010)) 
    po_cnt_dec_i_2__0
       (.I0(wait_cnt_r_reg[2]),
        .I1(wait_cnt_r_reg[3]),
        .I2(wait_cnt_r_reg[0]),
        .I3(wait_cnt_r_reg[1]),
        .O(po_cnt_inc1));
  FDRE po_cnt_dec_reg
       (.C(delay_done_r4_reg_0),
        .CE(1'b1),
        .D(po_cnt_dec_i_1__0_n_0),
        .Q(po_cnt_dec_2),
        .R(1'b0));
  FDRE po_en_stg2_f_reg
       (.C(delay_done_r4_reg_0),
        .CE(1'b1),
        .D(po_cnt_dec_2),
        .Q(cmd_po_en_stg2_f),
        .R(po_en_stg2_f_reg_0));
  LUT1 #(
    .INIT(2'h1)) 
    \wait_cnt_r[0]_i_1 
       (.I0(wait_cnt_r_reg[0]),
        .O(wait_cnt_r0__0));
  (* SOFT_HLUTNM = "soft_lutpair298" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \wait_cnt_r[1]_i_1 
       (.I0(wait_cnt_r_reg[0]),
        .I1(wait_cnt_r_reg[1]),
        .O(\wait_cnt_r[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair298" *) 
  LUT3 #(
    .INIT(8'hE1)) 
    \wait_cnt_r[2]_i_1__0 
       (.I0(wait_cnt_r_reg[1]),
        .I1(wait_cnt_r_reg[0]),
        .I2(wait_cnt_r_reg[2]),
        .O(\wait_cnt_r[2]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h8888888888888880)) 
    \wait_cnt_r[3]_i_2 
       (.I0(pi_fine_dly_dec_done),
        .I1(dqs_po_dec_done),
        .I2(wait_cnt_r_reg[3]),
        .I3(wait_cnt_r_reg[0]),
        .I4(wait_cnt_r_reg[1]),
        .I5(wait_cnt_r_reg[2]),
        .O(wait_cnt_r0));
  (* SOFT_HLUTNM = "soft_lutpair296" *) 
  LUT4 #(
    .INIT(16'hFE01)) 
    \wait_cnt_r[3]_i_3__0 
       (.I0(wait_cnt_r_reg[2]),
        .I1(wait_cnt_r_reg[0]),
        .I2(wait_cnt_r_reg[1]),
        .I3(wait_cnt_r_reg[3]),
        .O(\wait_cnt_r[3]_i_3__0_n_0 ));
  FDRE \wait_cnt_r_reg[0] 
       (.C(delay_done_r4_reg_0),
        .CE(wait_cnt_r0),
        .D(wait_cnt_r0__0),
        .Q(wait_cnt_r_reg[0]),
        .R(\wait_cnt_r_reg[0]_0 ));
  FDRE \wait_cnt_r_reg[1] 
       (.C(delay_done_r4_reg_0),
        .CE(wait_cnt_r0),
        .D(\wait_cnt_r[1]_i_1_n_0 ),
        .Q(wait_cnt_r_reg[1]),
        .R(\wait_cnt_r_reg[0]_0 ));
  FDRE \wait_cnt_r_reg[2] 
       (.C(delay_done_r4_reg_0),
        .CE(wait_cnt_r0),
        .D(\wait_cnt_r[2]_i_1__0_n_0 ),
        .Q(wait_cnt_r_reg[2]),
        .R(\wait_cnt_r_reg[0]_0 ));
  FDSE \wait_cnt_r_reg[3] 
       (.C(delay_done_r4_reg_0),
        .CE(wait_cnt_r0),
        .D(\wait_cnt_r[3]_i_3__0_n_0 ),
        .Q(wait_cnt_r_reg[3]),
        .S(\wait_cnt_r_reg[0]_0 ));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_phy_dqs_found_cal_hr" *) 
module mig_mig_7series_v4_2_ddr_phy_dqs_found_cal_hr
   (init_dqsfound_done_r2,
    pi_dqs_found_rank_done,
    dqs_found_done_r_reg_0,
    fine_adjust_reg_0,
    dqs_found_prech_req,
    ck_po_stg2_f_indec,
    ck_po_stg2_f_en,
    \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0]_0 ,
    \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]_0 ,
    \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6]_0 ,
    \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11]_0 ,
    \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][12]_0 ,
    \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17]_0 ,
    Q,
    \rd_byte_data_offset_reg[0][9]_0 ,
    \rd_byte_data_offset_reg[0][15]_0 ,
    \rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9]_0 ,
    \rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][15]_0 ,
    \rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 ,
    pi_dqs_found_done_r1_reg,
    pi_dqs_found_done_r1_reg_0,
    pi_dqs_found_done_r1_reg_1,
    pi_dqs_found_done_r1_reg_2,
    pi_dqs_found_done_r1_reg_3,
    pi_dqs_found_done_r1_reg_4,
    pi_dqs_found_done_r1_reg_5,
    pi_dqs_found_done_r1_reg_6,
    pi_dqs_found_done_r1_reg_7,
    pi_dqs_found_done_r1_reg_8,
    pi_dqs_found_done_r1_reg_9,
    pi_dqs_found_done_r1_reg_10,
    pi_dqs_found_done_r1_reg_11,
    pi_dqs_found_done_r1_reg_12,
    pi_dqs_found_done_r1_reg_13,
    dqs_found_done_r_reg_1,
    dqs_found_done_r_reg_2,
    rank_done_r_reg_0,
    delay_done_r4_reg,
    \ctl_lane_cnt_reg[2]_0 ,
    \pi_rst_stg1_cal_reg[0]_0 ,
    ctl_lane_sel,
    \ctl_lane_cnt_reg[1]_0 ,
    \ctl_lane_cnt_reg[0]_0 ,
    SR,
    \gen_byte_sel_div2.ctl_lane_sel_reg[2] ,
    calib_sel1__1,
    \gen_byte_sel_div2.ctl_lane_sel_reg[2]_0 ,
    delay_done_r4_reg_0,
    \pi_rst_stg1_cal_reg[2]_0 ,
    init_dqsfound_done_r5_reg_0,
    in0,
    dqs_found_start_r_reg_0,
    \pi_dqs_found_any_bank_reg[0]_0 ,
    first_fail_detect_reg_0,
    detect_pi_found_dqs,
    init_dqsfound_done_r_reg_0,
    prech_done,
    \pi_rst_stg1_cal_r_reg[1]_0 ,
    pi_dqs_found_done_r1,
    \gen_no_mirror.div_clk_loop[0].phy_address_reg[10] ,
    \gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0 ,
    \init_state_r[2]_i_10 ,
    \init_state_r[0]_i_10 ,
    ck_addr_cmd_delay_done,
    pi_fine_dly_dec_done,
    dqs_po_dec_done,
    calib_in_common,
    ctl_lane_cnt,
    \gen_byte_sel_div2.ctl_lane_sel_reg[2]_1 ,
    \gen_byte_sel_div2.ctl_lane_sel_reg[1] ,
    \gen_byte_sel_div2.ctl_lane_sel_reg[0] ,
    \gen_byte_sel_div2.calib_in_common_reg ,
    pi_calib_done,
    calib_in_common4_out,
    \gen_byte_sel_div2.byte_sel_cnt_reg[0] ,
    cmd_delay_start0,
    \calib_sel_reg[0] ,
    \calib_sel_reg[1] ,
    \stable_pass_cnt_reg[0]_0 ,
    \init_dec_cnt_reg[4]_0 );
  output init_dqsfound_done_r2;
  output pi_dqs_found_rank_done;
  output dqs_found_done_r_reg_0;
  output fine_adjust_reg_0;
  output dqs_found_prech_req;
  output ck_po_stg2_f_indec;
  output ck_po_stg2_f_en;
  output \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0]_0 ;
  output [5:0]\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]_0 ;
  output \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6]_0 ;
  output [5:0]\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11]_0 ;
  output \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][12]_0 ;
  output [5:0]\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17]_0 ;
  output [0:0]Q;
  output [0:0]\rd_byte_data_offset_reg[0][9]_0 ;
  output [0:0]\rd_byte_data_offset_reg[0][15]_0 ;
  output [0:0]\rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9]_0 ;
  output [0:0]\rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][15]_0 ;
  output [0:0]\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 ;
  output pi_dqs_found_done_r1_reg;
  output pi_dqs_found_done_r1_reg_0;
  output pi_dqs_found_done_r1_reg_1;
  output pi_dqs_found_done_r1_reg_2;
  output pi_dqs_found_done_r1_reg_3;
  output pi_dqs_found_done_r1_reg_4;
  output pi_dqs_found_done_r1_reg_5;
  output pi_dqs_found_done_r1_reg_6;
  output pi_dqs_found_done_r1_reg_7;
  output pi_dqs_found_done_r1_reg_8;
  output pi_dqs_found_done_r1_reg_9;
  output pi_dqs_found_done_r1_reg_10;
  output pi_dqs_found_done_r1_reg_11;
  output pi_dqs_found_done_r1_reg_12;
  output pi_dqs_found_done_r1_reg_13;
  output dqs_found_done_r_reg_1;
  output dqs_found_done_r_reg_2;
  output rank_done_r_reg_0;
  output delay_done_r4_reg;
  output \ctl_lane_cnt_reg[2]_0 ;
  output \pi_rst_stg1_cal_reg[0]_0 ;
  output ctl_lane_sel;
  output \ctl_lane_cnt_reg[1]_0 ;
  output \ctl_lane_cnt_reg[0]_0 ;
  output [0:0]SR;
  output \gen_byte_sel_div2.ctl_lane_sel_reg[2] ;
  output calib_sel1__1;
  output \gen_byte_sel_div2.ctl_lane_sel_reg[2]_0 ;
  output delay_done_r4_reg_0;
  output [2:0]\pi_rst_stg1_cal_reg[2]_0 ;
  input init_dqsfound_done_r5_reg_0;
  input [7:0]in0;
  input dqs_found_start_r_reg_0;
  input [1:0]\pi_dqs_found_any_bank_reg[0]_0 ;
  input first_fail_detect_reg_0;
  input detect_pi_found_dqs;
  input init_dqsfound_done_r_reg_0;
  input prech_done;
  input \pi_rst_stg1_cal_r_reg[1]_0 ;
  input pi_dqs_found_done_r1;
  input \gen_no_mirror.div_clk_loop[0].phy_address_reg[10] ;
  input \gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0 ;
  input \init_state_r[2]_i_10 ;
  input \init_state_r[0]_i_10 ;
  input ck_addr_cmd_delay_done;
  input pi_fine_dly_dec_done;
  input dqs_po_dec_done;
  input calib_in_common;
  input [2:0]ctl_lane_cnt;
  input \gen_byte_sel_div2.ctl_lane_sel_reg[2]_1 ;
  input \gen_byte_sel_div2.ctl_lane_sel_reg[1] ;
  input \gen_byte_sel_div2.ctl_lane_sel_reg[0] ;
  input \gen_byte_sel_div2.calib_in_common_reg ;
  input pi_calib_done;
  input calib_in_common4_out;
  input \gen_byte_sel_div2.byte_sel_cnt_reg[0] ;
  input cmd_delay_start0;
  input [2:0]\calib_sel_reg[0] ;
  input \calib_sel_reg[1] ;
  input \stable_pass_cnt_reg[0]_0 ;
  input [0:0]\init_dec_cnt_reg[4]_0 ;

  wire \FSM_sequential_fine_adj_state_r[0]_i_1_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[0]_i_2_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[0]_i_3_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[0]_i_4_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[0]_i_5_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[0]_i_6_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[1]_i_10_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[1]_i_11_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[1]_i_12_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[1]_i_13_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[1]_i_14_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[1]_i_1_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[1]_i_2_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[1]_i_3_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[1]_i_4_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[1]_i_5_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[1]_i_6_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[1]_i_7_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[1]_i_8_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[1]_i_9_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[2]_i_1_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[2]_i_2_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[2]_i_3_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[2]_i_4_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[2]_i_5_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[3]_i_1_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[3]_i_2_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[3]_i_3_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[3]_i_4_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[3]_i_5_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[3]_i_6_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[3]_i_7_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[3]_i_8_n_0 ;
  wire \FSM_sequential_fine_adj_state_r[3]_i_9_n_0 ;
  wire [0:0]Q;
  wire [0:0]SR;
  wire byte_sel_cnt1;
  wire calib_in_common;
  wire calib_in_common4_out;
  wire calib_sel1__1;
  wire [2:0]\calib_sel_reg[0] ;
  wire \calib_sel_reg[1] ;
  wire ck_addr_cmd_delay_done;
  wire ck_po_stg2_f_en;
  wire ck_po_stg2_f_en_i_1_n_0;
  wire ck_po_stg2_f_indec;
  wire ck_po_stg2_f_indec_i_1_n_0;
  wire cmd_delay_start0;
  wire [2:0]ctl_lane_cnt;
  wire \ctl_lane_cnt[0]_i_1__0_n_0 ;
  wire \ctl_lane_cnt[1]_i_1__0_n_0 ;
  wire \ctl_lane_cnt[2]_i_1__0_n_0 ;
  wire ctl_lane_cnt_0;
  wire \ctl_lane_cnt_reg[0]_0 ;
  wire \ctl_lane_cnt_reg[1]_0 ;
  wire \ctl_lane_cnt_reg[2]_0 ;
  wire ctl_lane_sel;
  wire [5:0]dec_cnt;
  wire \dec_cnt[0]_i_2_n_0 ;
  wire \dec_cnt[1]_i_2_n_0 ;
  wire \dec_cnt[1]_i_3_n_0 ;
  wire \dec_cnt[2]_i_3_n_0 ;
  wire \dec_cnt[2]_i_4_n_0 ;
  wire \dec_cnt[2]_i_5_n_0 ;
  wire \dec_cnt[2]_i_6_n_0 ;
  wire \dec_cnt[2]_i_7_n_0 ;
  wire \dec_cnt[2]_i_8_n_0 ;
  wire \dec_cnt[2]_i_9_n_0 ;
  wire \dec_cnt[3]_i_2_n_0 ;
  wire \dec_cnt[3]_i_3_n_0 ;
  wire \dec_cnt[3]_i_4_n_0 ;
  wire \dec_cnt[4]_i_2_n_0 ;
  wire \dec_cnt[4]_i_3_n_0 ;
  wire \dec_cnt[4]_i_5_n_0 ;
  wire \dec_cnt[4]_i_6_n_0 ;
  wire \dec_cnt[4]_i_7_n_0 ;
  wire \dec_cnt[4]_i_8_n_0 ;
  wire \dec_cnt[4]_i_9_n_0 ;
  wire \dec_cnt[5]_i_10_n_0 ;
  wire \dec_cnt[5]_i_11_n_0 ;
  wire \dec_cnt[5]_i_12_n_0 ;
  wire \dec_cnt[5]_i_1_n_0 ;
  wire \dec_cnt[5]_i_3_n_0 ;
  wire \dec_cnt[5]_i_4_n_0 ;
  wire \dec_cnt[5]_i_5_n_0 ;
  wire \dec_cnt[5]_i_6_n_0 ;
  wire \dec_cnt[5]_i_7_n_0 ;
  wire \dec_cnt[5]_i_8_n_0 ;
  wire \dec_cnt[5]_i_9_n_0 ;
  wire \dec_cnt_reg[2]_i_2_n_0 ;
  wire \dec_cnt_reg[2]_i_2_n_1 ;
  wire \dec_cnt_reg[2]_i_2_n_2 ;
  wire \dec_cnt_reg[2]_i_2_n_3 ;
  wire \dec_cnt_reg[2]_i_2_n_4 ;
  wire \dec_cnt_reg[2]_i_2_n_5 ;
  wire \dec_cnt_reg[2]_i_2_n_6 ;
  wire \dec_cnt_reg[4]_i_4_n_3 ;
  wire \dec_cnt_reg[4]_i_4_n_6 ;
  wire \dec_cnt_reg[4]_i_4_n_7 ;
  wire \dec_cnt_reg_n_0_[0] ;
  wire \dec_cnt_reg_n_0_[1] ;
  wire \dec_cnt_reg_n_0_[2] ;
  wire \dec_cnt_reg_n_0_[3] ;
  wire \dec_cnt_reg_n_0_[4] ;
  wire \dec_cnt_reg_n_0_[5] ;
  wire delay_done_r4_reg;
  wire delay_done_r4_reg_0;
  wire detect_pi_found_dqs;
  wire detect_rd_cnt0;
  wire [3:0]detect_rd_cnt0__0;
  wire \detect_rd_cnt[1]_i_1_n_0 ;
  wire \detect_rd_cnt[3]_i_1_n_0 ;
  wire [3:0]detect_rd_cnt_reg;
  wire dqs_found_done_r0;
  wire dqs_found_done_r_i_4_n_0;
  wire dqs_found_done_r_reg_0;
  wire dqs_found_done_r_reg_1;
  wire dqs_found_done_r_reg_2;
  wire dqs_found_prech_req;
  wire dqs_found_prech_req_i_1_n_0;
  wire dqs_found_prech_req_i_2_n_0;
  wire dqs_found_prech_req_i_3_n_0;
  wire dqs_found_prech_req_i_4_n_0;
  wire dqs_found_start_r;
  wire dqs_found_start_r_reg_0;
  wire dqs_po_dec_done;
  wire final_data_offset;
  wire final_data_offset_mc;
  wire final_dec_done_i_1_n_0;
  wire final_dec_done_reg_n_0;
  wire [3:0]fine_adj_state_r;
  wire fine_adjust_done_r_i_1_n_0;
  wire fine_adjust_done_r_reg_n_0;
  wire fine_adjust_i_1_n_0;
  wire [2:0]fine_adjust_lane_cnt;
  wire fine_adjust_reg_0;
  wire first_fail_detect;
  wire first_fail_detect_i_1_n_0;
  wire first_fail_detect_reg_0;
  wire first_fail_detect_reg_n_0;
  wire \first_fail_taps[0]_i_1_n_0 ;
  wire \first_fail_taps[1]_i_1_n_0 ;
  wire \first_fail_taps[2]_i_1_n_0 ;
  wire \first_fail_taps[3]_i_1_n_0 ;
  wire \first_fail_taps[4]_i_1_n_0 ;
  wire \first_fail_taps[5]_i_2_n_0 ;
  wire \first_fail_taps[5]_i_3_n_0 ;
  wire \first_fail_taps[5]_i_4_n_0 ;
  wire \first_fail_taps[5]_i_5_n_0 ;
  wire \first_fail_taps_reg_n_0_[0] ;
  wire \first_fail_taps_reg_n_0_[1] ;
  wire \first_fail_taps_reg_n_0_[2] ;
  wire \first_fail_taps_reg_n_0_[3] ;
  wire \first_fail_taps_reg_n_0_[4] ;
  wire \first_fail_taps_reg_n_0_[5] ;
  wire \gen_byte_sel_div2.byte_sel_cnt_reg[0] ;
  wire \gen_byte_sel_div2.calib_in_common_i_2_n_0 ;
  wire \gen_byte_sel_div2.calib_in_common_i_3_n_0 ;
  wire \gen_byte_sel_div2.calib_in_common_reg ;
  wire \gen_byte_sel_div2.ctl_lane_sel_reg[0] ;
  wire \gen_byte_sel_div2.ctl_lane_sel_reg[1] ;
  wire \gen_byte_sel_div2.ctl_lane_sel_reg[2] ;
  wire \gen_byte_sel_div2.ctl_lane_sel_reg[2]_0 ;
  wire \gen_byte_sel_div2.ctl_lane_sel_reg[2]_1 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address_reg[10] ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0 ;
  wire [7:0]in0;
  wire inc_cnt;
  wire \inc_cnt[5]_i_3_n_0 ;
  wire \inc_cnt_reg_n_0_[0] ;
  wire \inc_cnt_reg_n_0_[1] ;
  wire \inc_cnt_reg_n_0_[2] ;
  wire \inc_cnt_reg_n_0_[3] ;
  wire \inc_cnt_reg_n_0_[4] ;
  wire \inc_cnt_reg_n_0_[5] ;
  wire init_dec_cnt;
  wire [5:0]init_dec_cnt0;
  wire \init_dec_cnt[1]_i_1_n_0 ;
  wire \init_dec_cnt[5]_i_3_n_0 ;
  wire [5:0]init_dec_cnt_reg;
  wire [0:0]\init_dec_cnt_reg[4]_0 ;
  wire init_dec_done_i_1_n_0;
  wire init_dec_done_reg_n_0;
  wire init_dqsfound_done_r1_reg_n_0;
  wire init_dqsfound_done_r2;
  wire init_dqsfound_done_r4_reg_srl2_n_0;
  wire init_dqsfound_done_r5;
  wire init_dqsfound_done_r5_reg_0;
  wire init_dqsfound_done_r_i_1_n_0;
  wire init_dqsfound_done_r_i_2_n_0;
  wire init_dqsfound_done_r_reg_0;
  wire \init_state_r[0]_i_10 ;
  wire \init_state_r[2]_i_10 ;
  wire n_0_0;
  wire n_0_1;
  wire n_0_2;
  wire n_0_3;
  wire [5:0]p_0_in;
  wire p_0_in17_in;
  wire p_0_in22_in;
  wire p_0_in62_in;
  wire [5:0]p_0_in__0;
  wire [5:0]p_1_in;
  wire p_1_in30_in;
  wire [5:2]p_1_in__0;
  wire [5:2]p_1_in__1;
  wire p_22_out;
  wire [2:0]p_8_out;
  wire pi_calib_done;
  wire [2:0]pi_dqs_found_all_bank;
  wire [2:0]pi_dqs_found_all_bank_r;
  wire [2:0]pi_dqs_found_any_bank;
  wire \pi_dqs_found_any_bank[0]_i_1_n_0 ;
  wire \pi_dqs_found_any_bank[2]_i_1_n_0 ;
  wire \pi_dqs_found_any_bank_r_reg_n_0_[0] ;
  wire [1:0]\pi_dqs_found_any_bank_reg[0]_0 ;
  wire pi_dqs_found_done_r1;
  wire pi_dqs_found_done_r1_reg;
  wire pi_dqs_found_done_r1_reg_0;
  wire pi_dqs_found_done_r1_reg_1;
  wire pi_dqs_found_done_r1_reg_10;
  wire pi_dqs_found_done_r1_reg_11;
  wire pi_dqs_found_done_r1_reg_12;
  wire pi_dqs_found_done_r1_reg_13;
  wire pi_dqs_found_done_r1_reg_2;
  wire pi_dqs_found_done_r1_reg_3;
  wire pi_dqs_found_done_r1_reg_4;
  wire pi_dqs_found_done_r1_reg_5;
  wire pi_dqs_found_done_r1_reg_6;
  wire pi_dqs_found_done_r1_reg_7;
  wire pi_dqs_found_done_r1_reg_8;
  wire pi_dqs_found_done_r1_reg_9;
  (* async_reg = "true" *) wire [11:0]pi_dqs_found_lanes_r1;
  (* async_reg = "true" *) wire [11:0]pi_dqs_found_lanes_r2;
  (* async_reg = "true" *) wire [11:0]pi_dqs_found_lanes_r3;
  wire pi_dqs_found_rank_done;
  wire pi_fine_dly_dec_done;
  wire \pi_rst_stg1_cal[0]_i_1_n_0 ;
  wire \pi_rst_stg1_cal[1]_i_1_n_0 ;
  wire \pi_rst_stg1_cal[2]_i_1_n_0 ;
  wire \pi_rst_stg1_cal_r1[0]_i_1_n_0 ;
  wire \pi_rst_stg1_cal_r1[1]_i_1_n_0 ;
  wire \pi_rst_stg1_cal_r1[2]_i_1_n_0 ;
  wire \pi_rst_stg1_cal_r1_reg_n_0_[0] ;
  wire \pi_rst_stg1_cal_r[0]_i_1_n_0 ;
  wire \pi_rst_stg1_cal_r[0]_i_2_n_0 ;
  wire \pi_rst_stg1_cal_r[1]_i_1_n_0 ;
  wire \pi_rst_stg1_cal_r[2]_i_1_n_0 ;
  wire \pi_rst_stg1_cal_r[2]_i_2_n_0 ;
  wire \pi_rst_stg1_cal_r_reg[1]_0 ;
  wire \pi_rst_stg1_cal_r_reg_n_0_[0] ;
  wire \pi_rst_stg1_cal_r_reg_n_0_[1] ;
  wire \pi_rst_stg1_cal_r_reg_n_0_[2] ;
  wire \pi_rst_stg1_cal_reg[0]_0 ;
  wire [2:0]\pi_rst_stg1_cal_reg[2]_0 ;
  wire prech_done;
  wire rank_done_r1;
  wire rank_done_r_i_1_n_0;
  wire rank_done_r_i_2_n_0;
  wire rank_done_r_reg_0;
  wire \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][0]_i_1_n_0 ;
  wire \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][1]_i_1_n_0 ;
  wire \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][2]_i_1_n_0 ;
  wire \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][3]_i_1_n_0 ;
  wire \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][4]_i_1_n_0 ;
  wire \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_2_n_0 ;
  wire \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0]_0 ;
  wire [5:0]\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]_0 ;
  wire [0:0]\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 ;
  wire \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][11]_i_1_n_0 ;
  wire [5:0]\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11]_0 ;
  wire \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6]_0 ;
  wire [0:0]\rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9]_0 ;
  wire \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][12]_i_1_n_0 ;
  wire \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][13]_i_1_n_0 ;
  wire \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][14]_i_1_n_0 ;
  wire \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][15]_i_1_n_0 ;
  wire \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][16]_i_1_n_0 ;
  wire \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][17]_i_1_n_0 ;
  wire \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][12]_0 ;
  wire [5:0]\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17]_0 ;
  wire [0:0]\rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][15]_0 ;
  wire \rank_final_loop[0].final_do_index[0][0]_i_1_n_0 ;
  wire \rank_final_loop[0].final_do_index[0][1]_i_1_n_0 ;
  wire \rank_final_loop[0].final_do_index[0][2]_i_1_n_0 ;
  wire \rank_final_loop[0].final_do_index_reg_n_0_[0][0] ;
  wire \rank_final_loop[0].final_do_index_reg_n_0_[0][1] ;
  wire \rank_final_loop[0].final_do_index_reg_n_0_[0][2] ;
  wire \rank_final_loop[0].final_do_max[0][0]_i_1_n_0 ;
  wire \rank_final_loop[0].final_do_max[0][1]_i_1_n_0 ;
  wire \rank_final_loop[0].final_do_max[0][2]_i_1_n_0 ;
  wire \rank_final_loop[0].final_do_max[0][3]_i_1_n_0 ;
  wire \rank_final_loop[0].final_do_max[0][4]_i_1_n_0 ;
  wire \rank_final_loop[0].final_do_max[0][5]_i_10_n_0 ;
  wire \rank_final_loop[0].final_do_max[0][5]_i_11_n_0 ;
  wire \rank_final_loop[0].final_do_max[0][5]_i_1_n_0 ;
  wire \rank_final_loop[0].final_do_max[0][5]_i_2_n_0 ;
  wire \rank_final_loop[0].final_do_max[0][5]_i_3_n_0 ;
  wire \rank_final_loop[0].final_do_max[0][5]_i_4_n_0 ;
  wire \rank_final_loop[0].final_do_max[0][5]_i_5_n_0 ;
  wire \rank_final_loop[0].final_do_max[0][5]_i_6_n_0 ;
  wire \rank_final_loop[0].final_do_max[0][5]_i_7_n_0 ;
  wire \rank_final_loop[0].final_do_max[0][5]_i_8_n_0 ;
  wire \rank_final_loop[0].final_do_max[0][5]_i_9_n_0 ;
  wire [5:0]\rank_final_loop[0].final_do_max_reg[0]_45 ;
  wire rd_byte_data_offset;
  wire \rd_byte_data_offset[0][11]_i_1_n_0 ;
  wire \rd_byte_data_offset[0][11]_i_2_n_0 ;
  wire \rd_byte_data_offset[0][11]_i_4_n_0 ;
  wire \rd_byte_data_offset[0][11]_i_5_n_0 ;
  wire \rd_byte_data_offset[0][13]_i_1_n_0 ;
  wire \rd_byte_data_offset[0][17]_i_1_n_0 ;
  wire \rd_byte_data_offset[0][17]_i_2_n_0 ;
  wire \rd_byte_data_offset[0][17]_i_4_n_0 ;
  wire \rd_byte_data_offset[0][1]_i_1_n_0 ;
  wire \rd_byte_data_offset[0][5]_i_1_n_0 ;
  wire \rd_byte_data_offset[0][5]_i_4_n_0 ;
  wire [0:0]\rd_byte_data_offset_reg[0][15]_0 ;
  wire [0:0]\rd_byte_data_offset_reg[0][9]_0 ;
  wire \rd_byte_data_offset_reg[0]_46 ;
  wire \rd_byte_data_offset_reg_n_0_[0][0] ;
  wire \rd_byte_data_offset_reg_n_0_[0][10] ;
  wire \rd_byte_data_offset_reg_n_0_[0][11] ;
  wire \rd_byte_data_offset_reg_n_0_[0][12] ;
  wire \rd_byte_data_offset_reg_n_0_[0][13] ;
  wire \rd_byte_data_offset_reg_n_0_[0][14] ;
  wire \rd_byte_data_offset_reg_n_0_[0][16] ;
  wire \rd_byte_data_offset_reg_n_0_[0][17] ;
  wire \rd_byte_data_offset_reg_n_0_[0][1] ;
  wire \rd_byte_data_offset_reg_n_0_[0][2] ;
  wire \rd_byte_data_offset_reg_n_0_[0][4] ;
  wire \rd_byte_data_offset_reg_n_0_[0][5] ;
  wire \rd_byte_data_offset_reg_n_0_[0][6] ;
  wire \rd_byte_data_offset_reg_n_0_[0][7] ;
  wire \rd_byte_data_offset_reg_n_0_[0][8] ;
  wire rd_data_offset_cal_done;
  wire [5:0]rd_data_offset_ranks_0;
  wire [5:0]rd_data_offset_ranks_1;
  wire [5:0]rd_data_offset_ranks_2;
  wire \rnk_cnt_r[0]_i_1_n_0 ;
  wire \rnk_cnt_r[1]_i_1_n_0 ;
  wire \rnk_cnt_r_reg_n_0_[0] ;
  wire \rnk_cnt_r_reg_n_0_[1] ;
  wire rst_dqs_find;
  wire rst_dqs_find_i_1_n_0;
  wire rst_dqs_find_i_2_n_0;
  wire rst_dqs_find_i_3_n_0;
  wire rst_dqs_find_i_4_n_0;
  wire rst_dqs_find_i_5_n_0;
  wire rst_dqs_find_i_6_n_0;
  wire rst_dqs_find_i_7_n_0;
  wire rst_dqs_find_r1;
  wire rst_dqs_find_r2;
  wire stable_pass_cnt;
  wire \stable_pass_cnt[5]_i_3_n_0 ;
  wire [5:1]stable_pass_cnt_reg;
  wire \stable_pass_cnt_reg[0]_0 ;
  wire \stable_pass_cnt_reg_n_0_[0] ;
  wire [0:0]\NLW_dec_cnt_reg[2]_i_2_O_UNCONNECTED ;
  wire [3:1]\NLW_dec_cnt_reg[4]_i_4_CO_UNCONNECTED ;
  wire [3:2]\NLW_dec_cnt_reg[4]_i_4_O_UNCONNECTED ;

  LUT6 #(
    .INIT(64'h2220222222222222)) 
    \FSM_sequential_fine_adj_state_r[0]_i_1 
       (.I0(\FSM_sequential_fine_adj_state_r[0]_i_2_n_0 ),
        .I1(\FSM_sequential_fine_adj_state_r[0]_i_3_n_0 ),
        .I2(\FSM_sequential_fine_adj_state_r[3]_i_4_n_0 ),
        .I3(fine_adj_state_r[1]),
        .I4(\FSM_sequential_fine_adj_state_r[0]_i_4_n_0 ),
        .I5(final_dec_done_reg_n_0),
        .O(\FSM_sequential_fine_adj_state_r[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFEFF)) 
    \FSM_sequential_fine_adj_state_r[0]_i_2 
       (.I0(\FSM_sequential_fine_adj_state_r[0]_i_5_n_0 ),
        .I1(fine_adj_state_r[1]),
        .I2(fine_adj_state_r[0]),
        .I3(fine_adj_state_r[3]),
        .I4(\init_dec_cnt[5]_i_3_n_0 ),
        .I5(\FSM_sequential_fine_adj_state_r[3]_i_4_n_0 ),
        .O(\FSM_sequential_fine_adj_state_r[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h3203FC3032033C30)) 
    \FSM_sequential_fine_adj_state_r[0]_i_3 
       (.I0(\FSM_sequential_fine_adj_state_r[0]_i_6_n_0 ),
        .I1(fine_adj_state_r[2]),
        .I2(fine_adj_state_r[1]),
        .I3(fine_adj_state_r[0]),
        .I4(fine_adj_state_r[3]),
        .I5(\init_dec_cnt[5]_i_3_n_0 ),
        .O(\FSM_sequential_fine_adj_state_r[0]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair294" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \FSM_sequential_fine_adj_state_r[0]_i_4 
       (.I0(fine_adj_state_r[0]),
        .I1(fine_adj_state_r[3]),
        .O(\FSM_sequential_fine_adj_state_r[0]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \FSM_sequential_fine_adj_state_r[0]_i_5 
       (.I0(\dec_cnt_reg_n_0_[5] ),
        .I1(\dec_cnt_reg_n_0_[3] ),
        .I2(\dec_cnt_reg_n_0_[0] ),
        .I3(\dec_cnt_reg_n_0_[1] ),
        .I4(\dec_cnt_reg_n_0_[2] ),
        .I5(\dec_cnt_reg_n_0_[4] ),
        .O(\FSM_sequential_fine_adj_state_r[0]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair246" *) 
  LUT5 #(
    .INIT(32'h00000400)) 
    \FSM_sequential_fine_adj_state_r[0]_i_6 
       (.I0(detect_rd_cnt_reg[3]),
        .I1(detect_pi_found_dqs),
        .I2(detect_rd_cnt_reg[2]),
        .I3(detect_rd_cnt_reg[0]),
        .I4(detect_rd_cnt_reg[1]),
        .O(\FSM_sequential_fine_adj_state_r[0]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hA0A2AAA2A0A0AAA0)) 
    \FSM_sequential_fine_adj_state_r[1]_i_1 
       (.I0(\FSM_sequential_fine_adj_state_r[1]_i_2_n_0 ),
        .I1(\FSM_sequential_fine_adj_state_r[1]_i_3_n_0 ),
        .I2(\FSM_sequential_fine_adj_state_r[1]_i_4_n_0 ),
        .I3(\FSM_sequential_fine_adj_state_r[1]_i_5_n_0 ),
        .I4(\FSM_sequential_fine_adj_state_r[1]_i_6_n_0 ),
        .I5(\FSM_sequential_fine_adj_state_r[1]_i_7_n_0 ),
        .O(\FSM_sequential_fine_adj_state_r[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0200000200020000)) 
    \FSM_sequential_fine_adj_state_r[1]_i_10 
       (.I0(\inc_cnt_reg_n_0_[5] ),
        .I1(\inc_cnt_reg_n_0_[0] ),
        .I2(\inc_cnt_reg_n_0_[1] ),
        .I3(\inc_cnt_reg_n_0_[3] ),
        .I4(\inc_cnt_reg_n_0_[4] ),
        .I5(\inc_cnt_reg_n_0_[2] ),
        .O(\FSM_sequential_fine_adj_state_r[1]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAAAA8)) 
    \FSM_sequential_fine_adj_state_r[1]_i_11 
       (.I0(\inc_cnt_reg_n_0_[5] ),
        .I1(\inc_cnt_reg_n_0_[2] ),
        .I2(\inc_cnt_reg_n_0_[4] ),
        .I3(\inc_cnt_reg_n_0_[3] ),
        .I4(\inc_cnt_reg_n_0_[1] ),
        .I5(\inc_cnt_reg_n_0_[0] ),
        .O(\FSM_sequential_fine_adj_state_r[1]_i_11_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000060000)) 
    \FSM_sequential_fine_adj_state_r[1]_i_12 
       (.I0(\inc_cnt_reg_n_0_[4] ),
        .I1(\inc_cnt_reg_n_0_[2] ),
        .I2(\inc_cnt_reg_n_0_[1] ),
        .I3(\inc_cnt_reg_n_0_[0] ),
        .I4(\inc_cnt_reg_n_0_[3] ),
        .I5(\inc_cnt_reg_n_0_[5] ),
        .O(\FSM_sequential_fine_adj_state_r[1]_i_12_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair288" *) 
  LUT3 #(
    .INIT(8'h4F)) 
    \FSM_sequential_fine_adj_state_r[1]_i_13 
       (.I0(\FSM_sequential_fine_adj_state_r[1]_i_11_n_0 ),
        .I1(\first_fail_taps[5]_i_3_n_0 ),
        .I2(first_fail_detect_reg_n_0),
        .O(\FSM_sequential_fine_adj_state_r[1]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'h7FFFFFFFFFFFFFFF)) 
    \FSM_sequential_fine_adj_state_r[1]_i_14 
       (.I0(\inc_cnt_reg_n_0_[5] ),
        .I1(\inc_cnt_reg_n_0_[3] ),
        .I2(\inc_cnt_reg_n_0_[1] ),
        .I3(\inc_cnt_reg_n_0_[4] ),
        .I4(\inc_cnt_reg_n_0_[2] ),
        .I5(\inc_cnt_reg_n_0_[0] ),
        .O(\FSM_sequential_fine_adj_state_r[1]_i_14_n_0 ));
  LUT6 #(
    .INIT(64'hABBBABBAFFFFFFFF)) 
    \FSM_sequential_fine_adj_state_r[1]_i_2 
       (.I0(\FSM_sequential_fine_adj_state_r[1]_i_8_n_0 ),
        .I1(\inc_cnt[5]_i_3_n_0 ),
        .I2(fine_adj_state_r[3]),
        .I3(fine_adj_state_r[2]),
        .I4(p_1_in30_in),
        .I5(\FSM_sequential_fine_adj_state_r[0]_i_2_n_0 ),
        .O(\FSM_sequential_fine_adj_state_r[1]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair252" *) 
  LUT5 #(
    .INIT(32'h10000000)) 
    \FSM_sequential_fine_adj_state_r[1]_i_3 
       (.I0(\FSM_sequential_fine_adj_state_r[1]_i_9_n_0 ),
        .I1(\FSM_sequential_fine_adj_state_r[1]_i_10_n_0 ),
        .I2(\FSM_sequential_fine_adj_state_r[1]_i_11_n_0 ),
        .I3(\first_fail_taps[5]_i_3_n_0 ),
        .I4(first_fail_detect_reg_n_0),
        .O(\FSM_sequential_fine_adj_state_r[1]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair267" *) 
  LUT3 #(
    .INIT(8'hBF)) 
    \FSM_sequential_fine_adj_state_r[1]_i_4 
       (.I0(fine_adj_state_r[0]),
        .I1(fine_adj_state_r[1]),
        .I2(fine_adj_state_r[3]),
        .O(\FSM_sequential_fine_adj_state_r[1]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair248" *) 
  LUT4 #(
    .INIT(16'h80FF)) 
    \FSM_sequential_fine_adj_state_r[1]_i_5 
       (.I0(pi_dqs_found_all_bank[0]),
        .I1(pi_dqs_found_all_bank[1]),
        .I2(pi_dqs_found_all_bank[2]),
        .I3(detect_pi_found_dqs),
        .O(\FSM_sequential_fine_adj_state_r[1]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h7FBFFFEBFFEBFFFF)) 
    \FSM_sequential_fine_adj_state_r[1]_i_6 
       (.I0(\inc_cnt_reg_n_0_[0] ),
        .I1(\inc_cnt_reg_n_0_[2] ),
        .I2(\inc_cnt_reg_n_0_[4] ),
        .I3(\inc_cnt_reg_n_0_[1] ),
        .I4(\inc_cnt_reg_n_0_[3] ),
        .I5(\inc_cnt_reg_n_0_[5] ),
        .O(\FSM_sequential_fine_adj_state_r[1]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair247" *) 
  LUT5 #(
    .INIT(32'hEFEFEFFF)) 
    \FSM_sequential_fine_adj_state_r[1]_i_7 
       (.I0(\FSM_sequential_fine_adj_state_r[1]_i_12_n_0 ),
        .I1(\dec_cnt[5]_i_6_n_0 ),
        .I2(\FSM_sequential_fine_adj_state_r[1]_i_13_n_0 ),
        .I3(first_fail_detect_reg_n_0),
        .I4(\FSM_sequential_fine_adj_state_r[1]_i_14_n_0 ),
        .O(\FSM_sequential_fine_adj_state_r[1]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h5050450050504550)) 
    \FSM_sequential_fine_adj_state_r[1]_i_8 
       (.I0(fine_adj_state_r[1]),
        .I1(\FSM_sequential_fine_adj_state_r[0]_i_6_n_0 ),
        .I2(fine_adj_state_r[0]),
        .I3(fine_adj_state_r[3]),
        .I4(fine_adj_state_r[2]),
        .I5(\FSM_sequential_fine_adj_state_r[3]_i_4_n_0 ),
        .O(\FSM_sequential_fine_adj_state_r[1]_i_8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair250" *) 
  LUT5 #(
    .INIT(32'h80000000)) 
    \FSM_sequential_fine_adj_state_r[1]_i_9 
       (.I0(\inc_cnt_reg_n_0_[0] ),
        .I1(\inc_cnt_reg_n_0_[2] ),
        .I2(\inc_cnt_reg_n_0_[4] ),
        .I3(\inc_cnt_reg_n_0_[1] ),
        .I4(\inc_cnt_reg_n_0_[3] ),
        .O(\FSM_sequential_fine_adj_state_r[1]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'h03C73FF003C73FC0)) 
    \FSM_sequential_fine_adj_state_r[2]_i_1 
       (.I0(\FSM_sequential_fine_adj_state_r[2]_i_2_n_0 ),
        .I1(fine_adj_state_r[1]),
        .I2(fine_adj_state_r[0]),
        .I3(fine_adj_state_r[2]),
        .I4(fine_adj_state_r[3]),
        .I5(\FSM_sequential_fine_adj_state_r[3]_i_4_n_0 ),
        .O(\FSM_sequential_fine_adj_state_r[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FFFF7F00)) 
    \FSM_sequential_fine_adj_state_r[2]_i_2 
       (.I0(pi_dqs_found_all_bank[0]),
        .I1(pi_dqs_found_all_bank[1]),
        .I2(pi_dqs_found_all_bank[2]),
        .I3(detect_pi_found_dqs),
        .I4(\FSM_sequential_fine_adj_state_r[2]_i_3_n_0 ),
        .I5(\FSM_sequential_fine_adj_state_r[2]_i_4_n_0 ),
        .O(\FSM_sequential_fine_adj_state_r[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFF79FFFFFF9F)) 
    \FSM_sequential_fine_adj_state_r[2]_i_3 
       (.I0(\inc_cnt_reg_n_0_[2] ),
        .I1(\inc_cnt_reg_n_0_[4] ),
        .I2(\inc_cnt_reg_n_0_[3] ),
        .I3(\inc_cnt_reg_n_0_[1] ),
        .I4(\inc_cnt_reg_n_0_[0] ),
        .I5(\inc_cnt_reg_n_0_[5] ),
        .O(\FSM_sequential_fine_adj_state_r[2]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'h0000F808)) 
    \FSM_sequential_fine_adj_state_r[2]_i_4 
       (.I0(\FSM_sequential_fine_adj_state_r[1]_i_10_n_0 ),
        .I1(\FSM_sequential_fine_adj_state_r[2]_i_5_n_0 ),
        .I2(\FSM_sequential_fine_adj_state_r[1]_i_13_n_0 ),
        .I3(\FSM_sequential_fine_adj_state_r[1]_i_12_n_0 ),
        .I4(\FSM_sequential_fine_adj_state_r[1]_i_5_n_0 ),
        .O(\FSM_sequential_fine_adj_state_r[2]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair280" *) 
  LUT3 #(
    .INIT(8'h08)) 
    \FSM_sequential_fine_adj_state_r[2]_i_5 
       (.I0(\FSM_sequential_fine_adj_state_r[1]_i_11_n_0 ),
        .I1(\first_fail_taps[5]_i_3_n_0 ),
        .I2(\FSM_sequential_fine_adj_state_r[1]_i_9_n_0 ),
        .O(\FSM_sequential_fine_adj_state_r[2]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF00008000)) 
    \FSM_sequential_fine_adj_state_r[3]_i_1 
       (.I0(fine_adj_state_r[1]),
        .I1(pi_dqs_found_all_bank[0]),
        .I2(pi_dqs_found_all_bank[1]),
        .I3(pi_dqs_found_all_bank[2]),
        .I4(fine_adj_state_r[3]),
        .I5(\FSM_sequential_fine_adj_state_r[3]_i_3_n_0 ),
        .O(\FSM_sequential_fine_adj_state_r[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000030CCCCE0)) 
    \FSM_sequential_fine_adj_state_r[3]_i_2 
       (.I0(\FSM_sequential_fine_adj_state_r[3]_i_4_n_0 ),
        .I1(fine_adj_state_r[3]),
        .I2(fine_adj_state_r[0]),
        .I3(fine_adj_state_r[2]),
        .I4(fine_adj_state_r[1]),
        .I5(\FSM_sequential_fine_adj_state_r[3]_i_5_n_0 ),
        .O(\FSM_sequential_fine_adj_state_r[3]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF0FF20FC2)) 
    \FSM_sequential_fine_adj_state_r[3]_i_3 
       (.I0(init_dqsfound_done_r5),
        .I1(fine_adj_state_r[1]),
        .I2(fine_adj_state_r[0]),
        .I3(fine_adj_state_r[2]),
        .I4(\FSM_sequential_fine_adj_state_r[3]_i_6_n_0 ),
        .I5(\FSM_sequential_fine_adj_state_r[3]_i_7_n_0 ),
        .O(\FSM_sequential_fine_adj_state_r[3]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \FSM_sequential_fine_adj_state_r[3]_i_4 
       (.I0(init_dec_cnt_reg[5]),
        .I1(init_dec_cnt_reg[3]),
        .I2(init_dec_cnt_reg[0]),
        .I3(init_dec_cnt_reg[1]),
        .I4(init_dec_cnt_reg[2]),
        .I5(init_dec_cnt_reg[4]),
        .O(\FSM_sequential_fine_adj_state_r[3]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h32FF323232323232)) 
    \FSM_sequential_fine_adj_state_r[3]_i_5 
       (.I0(\FSM_sequential_fine_adj_state_r[3]_i_8_n_0 ),
        .I1(\FSM_sequential_fine_adj_state_r[3]_i_9_n_0 ),
        .I2(\FSM_sequential_fine_adj_state_r[1]_i_3_n_0 ),
        .I3(\inc_cnt[5]_i_3_n_0 ),
        .I4(\FSM_sequential_fine_adj_state_r[1]_i_5_n_0 ),
        .I5(\FSM_sequential_fine_adj_state_r[1]_i_6_n_0 ),
        .O(\FSM_sequential_fine_adj_state_r[3]_i_5_n_0 ));
  LUT3 #(
    .INIT(8'h04)) 
    \FSM_sequential_fine_adj_state_r[3]_i_6 
       (.I0(pi_dqs_found_any_bank[2]),
        .I1(rst_dqs_find_r2),
        .I2(pi_dqs_found_any_bank[0]),
        .O(\FSM_sequential_fine_adj_state_r[3]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair249" *) 
  LUT5 #(
    .INIT(32'hEFCC2FCC)) 
    \FSM_sequential_fine_adj_state_r[3]_i_7 
       (.I0(detect_pi_found_dqs),
        .I1(fine_adj_state_r[2]),
        .I2(fine_adj_state_r[1]),
        .I3(fine_adj_state_r[3]),
        .I4(prech_done),
        .O(\FSM_sequential_fine_adj_state_r[3]_i_7_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair247" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \FSM_sequential_fine_adj_state_r[3]_i_8 
       (.I0(\FSM_sequential_fine_adj_state_r[1]_i_13_n_0 ),
        .I1(\FSM_sequential_fine_adj_state_r[1]_i_12_n_0 ),
        .O(\FSM_sequential_fine_adj_state_r[3]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFBBBF)) 
    \FSM_sequential_fine_adj_state_r[3]_i_9 
       (.I0(fine_adj_state_r[0]),
        .I1(fine_adj_state_r[1]),
        .I2(first_fail_detect_reg_n_0),
        .I3(\FSM_sequential_fine_adj_state_r[1]_i_14_n_0 ),
        .I4(\dec_cnt[5]_i_6_n_0 ),
        .I5(\FSM_sequential_fine_adj_state_r[1]_i_5_n_0 ),
        .O(\FSM_sequential_fine_adj_state_r[3]_i_9_n_0 ));
  (* FSM_ENCODED_STATES = "FINE_ADJ_INIT:0101,RST_WAIT:0001,RST_POSTWAIT1:0100,FINE_DEC_PREWAIT:1101,FINE_DEC_WAIT:1100,FINE_DEC:1011,PRECH_WAIT:1111,RST_POSTWAIT:0011,FINE_ADJ_IDLE:0000,FINE_INC_PREWAIT:1000,DETECT_DQSFOUND:1010,FINE_INC_WAIT:0111,DETECT_PREWAIT:1001,FINE_ADJ_DONE:0010,FINAL_WAIT:1110,FINE_INC:0110" *) 
  FDRE \FSM_sequential_fine_adj_state_r_reg[0] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(\FSM_sequential_fine_adj_state_r[3]_i_1_n_0 ),
        .D(\FSM_sequential_fine_adj_state_r[0]_i_1_n_0 ),
        .Q(fine_adj_state_r[0]),
        .R(\pi_dqs_found_any_bank_reg[0]_0 [1]));
  (* FSM_ENCODED_STATES = "FINE_ADJ_INIT:0101,RST_WAIT:0001,RST_POSTWAIT1:0100,FINE_DEC_PREWAIT:1101,FINE_DEC_WAIT:1100,FINE_DEC:1011,PRECH_WAIT:1111,RST_POSTWAIT:0011,FINE_ADJ_IDLE:0000,FINE_INC_PREWAIT:1000,DETECT_DQSFOUND:1010,FINE_INC_WAIT:0111,DETECT_PREWAIT:1001,FINE_ADJ_DONE:0010,FINAL_WAIT:1110,FINE_INC:0110" *) 
  FDRE \FSM_sequential_fine_adj_state_r_reg[1] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(\FSM_sequential_fine_adj_state_r[3]_i_1_n_0 ),
        .D(\FSM_sequential_fine_adj_state_r[1]_i_1_n_0 ),
        .Q(fine_adj_state_r[1]),
        .R(\pi_dqs_found_any_bank_reg[0]_0 [1]));
  (* FSM_ENCODED_STATES = "FINE_ADJ_INIT:0101,RST_WAIT:0001,RST_POSTWAIT1:0100,FINE_DEC_PREWAIT:1101,FINE_DEC_WAIT:1100,FINE_DEC:1011,PRECH_WAIT:1111,RST_POSTWAIT:0011,FINE_ADJ_IDLE:0000,FINE_INC_PREWAIT:1000,DETECT_DQSFOUND:1010,FINE_INC_WAIT:0111,DETECT_PREWAIT:1001,FINE_ADJ_DONE:0010,FINAL_WAIT:1110,FINE_INC:0110" *) 
  FDRE \FSM_sequential_fine_adj_state_r_reg[2] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(\FSM_sequential_fine_adj_state_r[3]_i_1_n_0 ),
        .D(\FSM_sequential_fine_adj_state_r[2]_i_1_n_0 ),
        .Q(fine_adj_state_r[2]),
        .R(\pi_dqs_found_any_bank_reg[0]_0 [1]));
  (* FSM_ENCODED_STATES = "FINE_ADJ_INIT:0101,RST_WAIT:0001,RST_POSTWAIT1:0100,FINE_DEC_PREWAIT:1101,FINE_DEC_WAIT:1100,FINE_DEC:1011,PRECH_WAIT:1111,RST_POSTWAIT:0011,FINE_ADJ_IDLE:0000,FINE_INC_PREWAIT:1000,DETECT_DQSFOUND:1010,FINE_INC_WAIT:0111,DETECT_PREWAIT:1001,FINE_ADJ_DONE:0010,FINAL_WAIT:1110,FINE_INC:0110" *) 
  FDRE \FSM_sequential_fine_adj_state_r_reg[3] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(\FSM_sequential_fine_adj_state_r[3]_i_1_n_0 ),
        .D(\FSM_sequential_fine_adj_state_r[3]_i_2_n_0 ),
        .Q(fine_adj_state_r[3]),
        .R(\pi_dqs_found_any_bank_reg[0]_0 [1]));
  (* SOFT_HLUTNM = "soft_lutpair273" *) 
  LUT4 #(
    .INIT(16'hCDC8)) 
    \calib_data_offset_0[0]_i_1 
       (.I0(pi_dqs_found_done_r1),
        .I1(rd_data_offset_ranks_0[0]),
        .I2(init_dqsfound_done_r2),
        .I3(\rd_byte_data_offset_reg_n_0_[0][0] ),
        .O(pi_dqs_found_done_r1_reg_3));
  (* SOFT_HLUTNM = "soft_lutpair278" *) 
  LUT4 #(
    .INIT(16'hCDC8)) 
    \calib_data_offset_0[1]_i_1 
       (.I0(pi_dqs_found_done_r1),
        .I1(rd_data_offset_ranks_0[1]),
        .I2(init_dqsfound_done_r2),
        .I3(\rd_byte_data_offset_reg_n_0_[0][1] ),
        .O(pi_dqs_found_done_r1_reg_2));
  LUT4 #(
    .INIT(16'hCDC8)) 
    \calib_data_offset_0[2]_i_1 
       (.I0(pi_dqs_found_done_r1),
        .I1(rd_data_offset_ranks_0[2]),
        .I2(init_dqsfound_done_r2),
        .I3(\rd_byte_data_offset_reg_n_0_[0][2] ),
        .O(pi_dqs_found_done_r1_reg_1));
  LUT4 #(
    .INIT(16'hCDC8)) 
    \calib_data_offset_0[4]_i_1 
       (.I0(pi_dqs_found_done_r1),
        .I1(rd_data_offset_ranks_0[4]),
        .I2(init_dqsfound_done_r2),
        .I3(\rd_byte_data_offset_reg_n_0_[0][4] ),
        .O(pi_dqs_found_done_r1_reg_0));
  LUT4 #(
    .INIT(16'hCDC8)) 
    \calib_data_offset_0[5]_i_2 
       (.I0(pi_dqs_found_done_r1),
        .I1(rd_data_offset_ranks_0[5]),
        .I2(init_dqsfound_done_r2),
        .I3(\rd_byte_data_offset_reg_n_0_[0][5] ),
        .O(pi_dqs_found_done_r1_reg));
  (* SOFT_HLUTNM = "soft_lutpair272" *) 
  LUT4 #(
    .INIT(16'hCDC8)) 
    \calib_data_offset_1[0]_i_1 
       (.I0(pi_dqs_found_done_r1),
        .I1(rd_data_offset_ranks_1[0]),
        .I2(init_dqsfound_done_r2),
        .I3(\rd_byte_data_offset_reg_n_0_[0][6] ),
        .O(pi_dqs_found_done_r1_reg_8));
  LUT4 #(
    .INIT(16'hCDC8)) 
    \calib_data_offset_1[1]_i_1 
       (.I0(pi_dqs_found_done_r1),
        .I1(rd_data_offset_ranks_1[1]),
        .I2(init_dqsfound_done_r2),
        .I3(\rd_byte_data_offset_reg_n_0_[0][7] ),
        .O(pi_dqs_found_done_r1_reg_7));
  LUT4 #(
    .INIT(16'hCDC8)) 
    \calib_data_offset_1[2]_i_1 
       (.I0(pi_dqs_found_done_r1),
        .I1(rd_data_offset_ranks_1[2]),
        .I2(init_dqsfound_done_r2),
        .I3(\rd_byte_data_offset_reg_n_0_[0][8] ),
        .O(pi_dqs_found_done_r1_reg_6));
  LUT4 #(
    .INIT(16'hCDC8)) 
    \calib_data_offset_1[4]_i_1 
       (.I0(pi_dqs_found_done_r1),
        .I1(rd_data_offset_ranks_1[4]),
        .I2(init_dqsfound_done_r2),
        .I3(\rd_byte_data_offset_reg_n_0_[0][10] ),
        .O(pi_dqs_found_done_r1_reg_5));
  LUT4 #(
    .INIT(16'hCDC8)) 
    \calib_data_offset_1[5]_i_1 
       (.I0(pi_dqs_found_done_r1),
        .I1(rd_data_offset_ranks_1[5]),
        .I2(init_dqsfound_done_r2),
        .I3(\rd_byte_data_offset_reg_n_0_[0][11] ),
        .O(pi_dqs_found_done_r1_reg_4));
  (* SOFT_HLUTNM = "soft_lutpair274" *) 
  LUT4 #(
    .INIT(16'hCDC8)) 
    \calib_data_offset_2[0]_i_1 
       (.I0(pi_dqs_found_done_r1),
        .I1(rd_data_offset_ranks_2[0]),
        .I2(init_dqsfound_done_r2),
        .I3(\rd_byte_data_offset_reg_n_0_[0][12] ),
        .O(pi_dqs_found_done_r1_reg_13));
  (* SOFT_HLUTNM = "soft_lutpair275" *) 
  LUT4 #(
    .INIT(16'hCDC8)) 
    \calib_data_offset_2[1]_i_1 
       (.I0(pi_dqs_found_done_r1),
        .I1(rd_data_offset_ranks_2[1]),
        .I2(init_dqsfound_done_r2),
        .I3(\rd_byte_data_offset_reg_n_0_[0][13] ),
        .O(pi_dqs_found_done_r1_reg_12));
  LUT4 #(
    .INIT(16'hCDC8)) 
    \calib_data_offset_2[2]_i_1 
       (.I0(pi_dqs_found_done_r1),
        .I1(rd_data_offset_ranks_2[2]),
        .I2(init_dqsfound_done_r2),
        .I3(\rd_byte_data_offset_reg_n_0_[0][14] ),
        .O(pi_dqs_found_done_r1_reg_11));
  LUT4 #(
    .INIT(16'hCDC8)) 
    \calib_data_offset_2[4]_i_1 
       (.I0(pi_dqs_found_done_r1),
        .I1(rd_data_offset_ranks_2[4]),
        .I2(init_dqsfound_done_r2),
        .I3(\rd_byte_data_offset_reg_n_0_[0][16] ),
        .O(pi_dqs_found_done_r1_reg_10));
  LUT4 #(
    .INIT(16'hCDC8)) 
    \calib_data_offset_2[5]_i_1 
       (.I0(pi_dqs_found_done_r1),
        .I1(rd_data_offset_ranks_2[5]),
        .I2(init_dqsfound_done_r2),
        .I3(\rd_byte_data_offset_reg_n_0_[0][17] ),
        .O(pi_dqs_found_done_r1_reg_9));
  LUT6 #(
    .INIT(64'h100010001FFF1000)) 
    \calib_sel[0]_i_1 
       (.I0(\gen_byte_sel_div2.ctl_lane_sel_reg[2]_1 ),
        .I1(\gen_byte_sel_div2.ctl_lane_sel_reg[0] ),
        .I2(calib_sel1__1),
        .I3(cmd_delay_start0),
        .I4(\calib_sel_reg[0] [0]),
        .I5(\calib_sel_reg[0] [2]),
        .O(\gen_byte_sel_div2.ctl_lane_sel_reg[2] ));
  LUT6 #(
    .INIT(64'h14FFFFFF14000000)) 
    \calib_sel[1]_i_1 
       (.I0(\gen_byte_sel_div2.ctl_lane_sel_reg[2]_1 ),
        .I1(\gen_byte_sel_div2.ctl_lane_sel_reg[1] ),
        .I2(\gen_byte_sel_div2.ctl_lane_sel_reg[0] ),
        .I3(calib_sel1__1),
        .I4(cmd_delay_start0),
        .I5(\calib_sel_reg[1] ),
        .O(\gen_byte_sel_div2.ctl_lane_sel_reg[2]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair268" *) 
  LUT3 #(
    .INIT(8'h4F)) 
    \calib_sel[1]_i_2 
       (.I0(fine_adjust_done_r_reg_n_0),
        .I1(rd_data_offset_cal_done),
        .I2(ck_addr_cmd_delay_done),
        .O(calib_sel1__1));
  (* SOFT_HLUTNM = "soft_lutpair268" *) 
  LUT5 #(
    .INIT(32'h08088808)) 
    \calib_sel[3]_i_1 
       (.I0(pi_fine_dly_dec_done),
        .I1(dqs_po_dec_done),
        .I2(ck_addr_cmd_delay_done),
        .I3(rd_data_offset_cal_done),
        .I4(fine_adjust_done_r_reg_n_0),
        .O(ctl_lane_sel));
  LUT6 #(
    .INIT(64'h000000000000A2FF)) 
    \calib_sel[4]_i_2 
       (.I0(ck_addr_cmd_delay_done),
        .I1(rd_data_offset_cal_done),
        .I2(fine_adjust_done_r_reg_n_0),
        .I3(cmd_delay_start0),
        .I4(\calib_sel_reg[0] [2]),
        .I5(\calib_sel_reg[0] [1]),
        .O(delay_done_r4_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair267" *) 
  LUT5 #(
    .INIT(32'hE7FF0280)) 
    ck_po_stg2_f_en_i_1
       (.I0(fine_adj_state_r[1]),
        .I1(fine_adj_state_r[0]),
        .I2(fine_adj_state_r[3]),
        .I3(fine_adj_state_r[2]),
        .I4(ck_po_stg2_f_en),
        .O(ck_po_stg2_f_en_i_1_n_0));
  FDRE ck_po_stg2_f_en_reg
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(ck_po_stg2_f_en_i_1_n_0),
        .Q(ck_po_stg2_f_en),
        .R(\pi_dqs_found_any_bank_reg[0]_0 [0]));
  (* SOFT_HLUTNM = "soft_lutpair261" *) 
  LUT5 #(
    .INIT(32'hE77F0200)) 
    ck_po_stg2_f_indec_i_1
       (.I0(fine_adj_state_r[1]),
        .I1(fine_adj_state_r[0]),
        .I2(fine_adj_state_r[3]),
        .I3(fine_adj_state_r[2]),
        .I4(ck_po_stg2_f_indec),
        .O(ck_po_stg2_f_indec_i_1_n_0));
  FDRE ck_po_stg2_f_indec_reg
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(ck_po_stg2_f_indec_i_1_n_0),
        .Q(ck_po_stg2_f_indec),
        .R(\pi_dqs_found_any_bank_reg[0]_0 [1]));
  LUT1 #(
    .INIT(2'h1)) 
    \cmd_pipe_plus.mc_data_offset[0]_i_1 
       (.I0(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]_0 [0]),
        .O(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \cmd_pipe_plus.mc_data_offset_1[0]_i_1 
       (.I0(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11]_0 [0]),
        .O(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \cmd_pipe_plus.mc_data_offset_2[0]_i_1 
       (.I0(\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17]_0 [0]),
        .O(\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][12]_0 ));
  LUT4 #(
    .INIT(16'h0FD0)) 
    \ctl_lane_cnt[0]_i_1__0 
       (.I0(fine_adjust_lane_cnt[1]),
        .I1(fine_adjust_lane_cnt[2]),
        .I2(ctl_lane_cnt_0),
        .I3(fine_adjust_lane_cnt[0]),
        .O(\ctl_lane_cnt[0]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair279" *) 
  LUT4 #(
    .INIT(16'h2FC0)) 
    \ctl_lane_cnt[1]_i_1__0 
       (.I0(fine_adjust_lane_cnt[2]),
        .I1(fine_adjust_lane_cnt[0]),
        .I2(ctl_lane_cnt_0),
        .I3(fine_adjust_lane_cnt[1]),
        .O(\ctl_lane_cnt[1]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair279" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \ctl_lane_cnt[2]_i_1__0 
       (.I0(fine_adjust_lane_cnt[1]),
        .I1(fine_adjust_lane_cnt[0]),
        .I2(ctl_lane_cnt_0),
        .I3(fine_adjust_lane_cnt[2]),
        .O(\ctl_lane_cnt[2]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair261" *) 
  LUT4 #(
    .INIT(16'h0280)) 
    \ctl_lane_cnt[2]_i_2__0 
       (.I0(fine_adj_state_r[2]),
        .I1(fine_adj_state_r[0]),
        .I2(fine_adj_state_r[1]),
        .I3(fine_adj_state_r[3]),
        .O(ctl_lane_cnt_0));
  FDRE \ctl_lane_cnt_reg[0] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(\ctl_lane_cnt[0]_i_1__0_n_0 ),
        .Q(fine_adjust_lane_cnt[0]),
        .R(\pi_dqs_found_any_bank_reg[0]_0 [1]));
  FDRE \ctl_lane_cnt_reg[1] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(\ctl_lane_cnt[1]_i_1__0_n_0 ),
        .Q(fine_adjust_lane_cnt[1]),
        .R(\pi_dqs_found_any_bank_reg[0]_0 [1]));
  FDRE \ctl_lane_cnt_reg[2] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(\ctl_lane_cnt[2]_i_1__0_n_0 ),
        .Q(fine_adjust_lane_cnt[2]),
        .R(\pi_dqs_found_any_bank_reg[0]_0 [1]));
  LUT6 #(
    .INIT(64'h4744474447447777)) 
    \dec_cnt[0]_i_1 
       (.I0(\dec_cnt_reg_n_0_[0] ),
        .I1(fine_adj_state_r[0]),
        .I2(\dec_cnt[4]_i_3_n_0 ),
        .I3(\dec_cnt_reg[2]_i_2_n_6 ),
        .I4(\FSM_sequential_fine_adj_state_r[1]_i_5_n_0 ),
        .I5(\dec_cnt[0]_i_2_n_0 ),
        .O(dec_cnt[0]));
  LUT6 #(
    .INIT(64'h8888BBB8BBBBBBB8)) 
    \dec_cnt[0]_i_2 
       (.I0(\inc_cnt_reg_n_0_[1] ),
        .I1(\dec_cnt[5]_i_6_n_0 ),
        .I2(\first_fail_taps_reg_n_0_[1] ),
        .I3(\first_fail_taps[5]_i_3_n_0 ),
        .I4(\FSM_sequential_fine_adj_state_r[1]_i_14_n_0 ),
        .I5(\dec_cnt_reg[2]_i_2_n_6 ),
        .O(\dec_cnt[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h909F90909F9F9F9F)) 
    \dec_cnt[1]_i_1 
       (.I0(\dec_cnt_reg_n_0_[0] ),
        .I1(\dec_cnt_reg_n_0_[1] ),
        .I2(fine_adj_state_r[0]),
        .I3(\dec_cnt[4]_i_3_n_0 ),
        .I4(\dec_cnt_reg[2]_i_2_n_5 ),
        .I5(\dec_cnt[1]_i_2_n_0 ),
        .O(dec_cnt[1]));
  LUT5 #(
    .INIT(32'hFEAEAEFE)) 
    \dec_cnt[1]_i_2 
       (.I0(\FSM_sequential_fine_adj_state_r[1]_i_5_n_0 ),
        .I1(\dec_cnt[1]_i_3_n_0 ),
        .I2(\dec_cnt[5]_i_6_n_0 ),
        .I3(\inc_cnt_reg_n_0_[2] ),
        .I4(\inc_cnt_reg_n_0_[1] ),
        .O(\dec_cnt[1]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h0EFE)) 
    \dec_cnt[1]_i_3 
       (.I0(\first_fail_taps_reg_n_0_[2] ),
        .I1(\first_fail_taps[5]_i_3_n_0 ),
        .I2(\FSM_sequential_fine_adj_state_r[1]_i_14_n_0 ),
        .I3(\dec_cnt_reg[2]_i_2_n_5 ),
        .O(\dec_cnt[1]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFF400F400F4FFF4)) 
    \dec_cnt[2]_i_1 
       (.I0(\dec_cnt[4]_i_3_n_0 ),
        .I1(\dec_cnt_reg[2]_i_2_n_4 ),
        .I2(\dec_cnt[2]_i_3_n_0 ),
        .I3(fine_adj_state_r[0]),
        .I4(\dec_cnt_reg_n_0_[2] ),
        .I5(\dec_cnt[2]_i_4_n_0 ),
        .O(dec_cnt[2]));
  LUT6 #(
    .INIT(64'h0151515151010101)) 
    \dec_cnt[2]_i_3 
       (.I0(\FSM_sequential_fine_adj_state_r[1]_i_5_n_0 ),
        .I1(\dec_cnt[2]_i_9_n_0 ),
        .I2(\dec_cnt[5]_i_6_n_0 ),
        .I3(\inc_cnt_reg_n_0_[1] ),
        .I4(\inc_cnt_reg_n_0_[2] ),
        .I5(\inc_cnt_reg_n_0_[3] ),
        .O(\dec_cnt[2]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \dec_cnt[2]_i_4 
       (.I0(\dec_cnt_reg_n_0_[0] ),
        .I1(\dec_cnt_reg_n_0_[1] ),
        .O(\dec_cnt[2]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \dec_cnt[2]_i_5 
       (.I0(\inc_cnt_reg_n_0_[3] ),
        .I1(\first_fail_taps_reg_n_0_[3] ),
        .O(\dec_cnt[2]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \dec_cnt[2]_i_6 
       (.I0(\inc_cnt_reg_n_0_[2] ),
        .I1(\first_fail_taps_reg_n_0_[2] ),
        .O(\dec_cnt[2]_i_6_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \dec_cnt[2]_i_7 
       (.I0(\inc_cnt_reg_n_0_[1] ),
        .I1(\first_fail_taps_reg_n_0_[1] ),
        .O(\dec_cnt[2]_i_7_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \dec_cnt[2]_i_8 
       (.I0(\inc_cnt_reg_n_0_[0] ),
        .I1(\first_fail_taps_reg_n_0_[0] ),
        .O(\dec_cnt[2]_i_8_n_0 ));
  LUT4 #(
    .INIT(16'h0EFE)) 
    \dec_cnt[2]_i_9 
       (.I0(\first_fail_taps_reg_n_0_[3] ),
        .I1(\first_fail_taps[5]_i_3_n_0 ),
        .I2(\FSM_sequential_fine_adj_state_r[1]_i_14_n_0 ),
        .I3(\dec_cnt_reg[2]_i_2_n_4 ),
        .O(\dec_cnt[2]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'h8A888A888A88AAAA)) 
    \dec_cnt[3]_i_1 
       (.I0(\dec_cnt[3]_i_2_n_0 ),
        .I1(fine_adj_state_r[0]),
        .I2(\dec_cnt[4]_i_3_n_0 ),
        .I3(\dec_cnt_reg[4]_i_4_n_7 ),
        .I4(\FSM_sequential_fine_adj_state_r[1]_i_5_n_0 ),
        .I5(\dec_cnt[3]_i_3_n_0 ),
        .O(dec_cnt[3]));
  (* SOFT_HLUTNM = "soft_lutpair269" *) 
  LUT5 #(
    .INIT(32'hFFFD5557)) 
    \dec_cnt[3]_i_2 
       (.I0(fine_adj_state_r[0]),
        .I1(\dec_cnt_reg_n_0_[2] ),
        .I2(\dec_cnt_reg_n_0_[1] ),
        .I3(\dec_cnt_reg_n_0_[0] ),
        .I4(\dec_cnt_reg_n_0_[3] ),
        .O(\dec_cnt[3]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h8888BBB8BBBBBBB8)) 
    \dec_cnt[3]_i_3 
       (.I0(\dec_cnt[3]_i_4_n_0 ),
        .I1(\dec_cnt[5]_i_6_n_0 ),
        .I2(\first_fail_taps_reg_n_0_[4] ),
        .I3(\first_fail_taps[5]_i_3_n_0 ),
        .I4(\FSM_sequential_fine_adj_state_r[1]_i_14_n_0 ),
        .I5(\dec_cnt_reg[4]_i_4_n_7 ),
        .O(\dec_cnt[3]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair271" *) 
  LUT4 #(
    .INIT(16'h9555)) 
    \dec_cnt[3]_i_4 
       (.I0(\inc_cnt_reg_n_0_[4] ),
        .I1(\inc_cnt_reg_n_0_[3] ),
        .I2(\inc_cnt_reg_n_0_[1] ),
        .I3(\inc_cnt_reg_n_0_[2] ),
        .O(\dec_cnt[3]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h909F90909F9F9F9F)) 
    \dec_cnt[4]_i_1 
       (.I0(\dec_cnt_reg_n_0_[4] ),
        .I1(\dec_cnt[4]_i_2_n_0 ),
        .I2(fine_adj_state_r[0]),
        .I3(\dec_cnt[4]_i_3_n_0 ),
        .I4(\dec_cnt_reg[4]_i_4_n_6 ),
        .I5(\dec_cnt[4]_i_5_n_0 ),
        .O(dec_cnt[4]));
  (* SOFT_HLUTNM = "soft_lutpair269" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    \dec_cnt[4]_i_2 
       (.I0(\dec_cnt_reg_n_0_[3] ),
        .I1(\dec_cnt_reg_n_0_[0] ),
        .I2(\dec_cnt_reg_n_0_[1] ),
        .I3(\dec_cnt_reg_n_0_[2] ),
        .O(\dec_cnt[4]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair262" *) 
  LUT5 #(
    .INIT(32'hAEEEEEEE)) 
    \dec_cnt[4]_i_3 
       (.I0(\dec_cnt[5]_i_11_n_0 ),
        .I1(detect_pi_found_dqs),
        .I2(pi_dqs_found_all_bank[2]),
        .I3(pi_dqs_found_all_bank[1]),
        .I4(pi_dqs_found_all_bank[0]),
        .O(\dec_cnt[4]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hAEFEFEAE)) 
    \dec_cnt[4]_i_5 
       (.I0(\FSM_sequential_fine_adj_state_r[1]_i_5_n_0 ),
        .I1(\dec_cnt[4]_i_8_n_0 ),
        .I2(\dec_cnt[5]_i_6_n_0 ),
        .I3(\dec_cnt[4]_i_9_n_0 ),
        .I4(\inc_cnt_reg_n_0_[5] ),
        .O(\dec_cnt[4]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \dec_cnt[4]_i_6 
       (.I0(\inc_cnt_reg_n_0_[5] ),
        .I1(\first_fail_taps_reg_n_0_[5] ),
        .O(\dec_cnt[4]_i_6_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \dec_cnt[4]_i_7 
       (.I0(\inc_cnt_reg_n_0_[4] ),
        .I1(\first_fail_taps_reg_n_0_[4] ),
        .O(\dec_cnt[4]_i_7_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair277" *) 
  LUT4 #(
    .INIT(16'h0EFE)) 
    \dec_cnt[4]_i_8 
       (.I0(\first_fail_taps_reg_n_0_[5] ),
        .I1(\first_fail_taps[5]_i_3_n_0 ),
        .I2(\FSM_sequential_fine_adj_state_r[1]_i_14_n_0 ),
        .I3(\dec_cnt_reg[4]_i_4_n_6 ),
        .O(\dec_cnt[4]_i_8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair257" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \dec_cnt[4]_i_9 
       (.I0(\inc_cnt_reg_n_0_[3] ),
        .I1(\inc_cnt_reg_n_0_[1] ),
        .I2(\inc_cnt_reg_n_0_[4] ),
        .I3(\inc_cnt_reg_n_0_[2] ),
        .O(\dec_cnt[4]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'h4444444455555554)) 
    \dec_cnt[5]_i_1 
       (.I0(\dec_cnt[5]_i_3_n_0 ),
        .I1(\dec_cnt[5]_i_4_n_0 ),
        .I2(\first_fail_taps[5]_i_5_n_0 ),
        .I3(\dec_cnt[5]_i_5_n_0 ),
        .I4(\dec_cnt[5]_i_6_n_0 ),
        .I5(\dec_cnt[5]_i_7_n_0 ),
        .O(\dec_cnt[5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair276" *) 
  LUT4 #(
    .INIT(16'h0010)) 
    \dec_cnt[5]_i_10 
       (.I0(\FSM_sequential_fine_adj_state_r[3]_i_4_n_0 ),
        .I1(fine_adjust_lane_cnt[2]),
        .I2(fine_adjust_lane_cnt[1]),
        .I3(fine_adjust_lane_cnt[0]),
        .O(\dec_cnt[5]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hFFFE0000FFFFFFFF)) 
    \dec_cnt[5]_i_11 
       (.I0(\first_fail_taps_reg_n_0_[2] ),
        .I1(\first_fail_taps_reg_n_0_[3] ),
        .I2(\first_fail_taps_reg_n_0_[1] ),
        .I3(\first_fail_taps_reg_n_0_[4] ),
        .I4(\first_fail_taps_reg_n_0_[5] ),
        .I5(first_fail_detect_reg_n_0),
        .O(\dec_cnt[5]_i_11_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair257" *) 
  LUT5 #(
    .INIT(32'h7FFFFFFF)) 
    \dec_cnt[5]_i_12 
       (.I0(\inc_cnt_reg_n_0_[2] ),
        .I1(\inc_cnt_reg_n_0_[4] ),
        .I2(\inc_cnt_reg_n_0_[1] ),
        .I3(\inc_cnt_reg_n_0_[3] ),
        .I4(\inc_cnt_reg_n_0_[5] ),
        .O(\dec_cnt[5]_i_12_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair249" *) 
  LUT3 #(
    .INIT(8'hBF)) 
    \dec_cnt[5]_i_3 
       (.I0(fine_adj_state_r[2]),
        .I1(fine_adj_state_r[1]),
        .I2(fine_adj_state_r[3]),
        .O(\dec_cnt[5]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h880F880088008800)) 
    \dec_cnt[5]_i_4 
       (.I0(\FSM_sequential_fine_adj_state_r[0]_i_5_n_0 ),
        .I1(\dec_cnt[5]_i_10_n_0 ),
        .I2(\FSM_sequential_fine_adj_state_r[1]_i_14_n_0 ),
        .I3(fine_adj_state_r[0]),
        .I4(p_1_in30_in),
        .I5(detect_pi_found_dqs),
        .O(\dec_cnt[5]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair277" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \dec_cnt[5]_i_5 
       (.I0(first_fail_detect_reg_n_0),
        .I1(\FSM_sequential_fine_adj_state_r[1]_i_14_n_0 ),
        .O(\dec_cnt[5]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair280" *) 
  LUT4 #(
    .INIT(16'h000E)) 
    \dec_cnt[5]_i_6 
       (.I0(\FSM_sequential_fine_adj_state_r[1]_i_9_n_0 ),
        .I1(\inc_cnt_reg_n_0_[5] ),
        .I2(\first_fail_taps[5]_i_3_n_0 ),
        .I3(first_fail_detect_reg_n_0),
        .O(\dec_cnt[5]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair248" *) 
  LUT5 #(
    .INIT(32'hFBBBBBBB)) 
    \dec_cnt[5]_i_7 
       (.I0(fine_adj_state_r[0]),
        .I1(detect_pi_found_dqs),
        .I2(pi_dqs_found_all_bank[2]),
        .I3(pi_dqs_found_all_bank[1]),
        .I4(pi_dqs_found_all_bank[0]),
        .O(\dec_cnt[5]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h88888888B8B888BB)) 
    \dec_cnt[5]_i_8 
       (.I0(\dec_cnt[5]_i_11_n_0 ),
        .I1(\FSM_sequential_fine_adj_state_r[1]_i_5_n_0 ),
        .I2(\inc_cnt_reg_n_0_[0] ),
        .I3(first_fail_detect_reg_n_0),
        .I4(\first_fail_taps[5]_i_3_n_0 ),
        .I5(\dec_cnt[5]_i_12_n_0 ),
        .O(\dec_cnt[5]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAAAA9)) 
    \dec_cnt[5]_i_9 
       (.I0(\dec_cnt_reg_n_0_[5] ),
        .I1(\dec_cnt_reg_n_0_[3] ),
        .I2(\dec_cnt_reg_n_0_[0] ),
        .I3(\dec_cnt_reg_n_0_[1] ),
        .I4(\dec_cnt_reg_n_0_[2] ),
        .I5(\dec_cnt_reg_n_0_[4] ),
        .O(\dec_cnt[5]_i_9_n_0 ));
  FDRE \dec_cnt_reg[0] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(\dec_cnt[5]_i_1_n_0 ),
        .D(dec_cnt[0]),
        .Q(\dec_cnt_reg_n_0_[0] ),
        .R(\pi_dqs_found_any_bank_reg[0]_0 [1]));
  FDRE \dec_cnt_reg[1] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(\dec_cnt[5]_i_1_n_0 ),
        .D(dec_cnt[1]),
        .Q(\dec_cnt_reg_n_0_[1] ),
        .R(\pi_dqs_found_any_bank_reg[0]_0 [1]));
  FDRE \dec_cnt_reg[2] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(\dec_cnt[5]_i_1_n_0 ),
        .D(dec_cnt[2]),
        .Q(\dec_cnt_reg_n_0_[2] ),
        .R(\pi_dqs_found_any_bank_reg[0]_0 [1]));
  CARRY4 \dec_cnt_reg[2]_i_2 
       (.CI(1'b0),
        .CO({\dec_cnt_reg[2]_i_2_n_0 ,\dec_cnt_reg[2]_i_2_n_1 ,\dec_cnt_reg[2]_i_2_n_2 ,\dec_cnt_reg[2]_i_2_n_3 }),
        .CYINIT(1'b1),
        .DI({\inc_cnt_reg_n_0_[3] ,\inc_cnt_reg_n_0_[2] ,\inc_cnt_reg_n_0_[1] ,\inc_cnt_reg_n_0_[0] }),
        .O({\dec_cnt_reg[2]_i_2_n_4 ,\dec_cnt_reg[2]_i_2_n_5 ,\dec_cnt_reg[2]_i_2_n_6 ,\NLW_dec_cnt_reg[2]_i_2_O_UNCONNECTED [0]}),
        .S({\dec_cnt[2]_i_5_n_0 ,\dec_cnt[2]_i_6_n_0 ,\dec_cnt[2]_i_7_n_0 ,\dec_cnt[2]_i_8_n_0 }));
  FDRE \dec_cnt_reg[3] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(\dec_cnt[5]_i_1_n_0 ),
        .D(dec_cnt[3]),
        .Q(\dec_cnt_reg_n_0_[3] ),
        .R(\pi_dqs_found_any_bank_reg[0]_0 [1]));
  FDRE \dec_cnt_reg[4] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(\dec_cnt[5]_i_1_n_0 ),
        .D(dec_cnt[4]),
        .Q(\dec_cnt_reg_n_0_[4] ),
        .R(\pi_dqs_found_any_bank_reg[0]_0 [1]));
  CARRY4 \dec_cnt_reg[4]_i_4 
       (.CI(\dec_cnt_reg[2]_i_2_n_0 ),
        .CO({\NLW_dec_cnt_reg[4]_i_4_CO_UNCONNECTED [3:1],\dec_cnt_reg[4]_i_4_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,\inc_cnt_reg_n_0_[4] }),
        .O({\NLW_dec_cnt_reg[4]_i_4_O_UNCONNECTED [3:2],\dec_cnt_reg[4]_i_4_n_6 ,\dec_cnt_reg[4]_i_4_n_7 }),
        .S({1'b0,1'b0,\dec_cnt[4]_i_6_n_0 ,\dec_cnt[4]_i_7_n_0 }));
  FDRE \dec_cnt_reg[5] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(\dec_cnt[5]_i_1_n_0 ),
        .D(dec_cnt[5]),
        .Q(\dec_cnt_reg_n_0_[5] ),
        .R(\pi_dqs_found_any_bank_reg[0]_0 [1]));
  MUXF7 \dec_cnt_reg[5]_i_2 
       (.I0(\dec_cnt[5]_i_8_n_0 ),
        .I1(\dec_cnt[5]_i_9_n_0 ),
        .O(dec_cnt[5]),
        .S(fine_adj_state_r[0]));
  LUT1 #(
    .INIT(2'h1)) 
    \detect_rd_cnt[0]_i_1 
       (.I0(detect_rd_cnt_reg[0]),
        .O(detect_rd_cnt0__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair289" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \detect_rd_cnt[1]_i_1 
       (.I0(detect_rd_cnt_reg[0]),
        .I1(detect_rd_cnt_reg[1]),
        .O(\detect_rd_cnt[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair289" *) 
  LUT3 #(
    .INIT(8'hA9)) 
    \detect_rd_cnt[2]_i_1 
       (.I0(detect_rd_cnt_reg[2]),
        .I1(detect_rd_cnt_reg[1]),
        .I2(detect_rd_cnt_reg[0]),
        .O(detect_rd_cnt0__0[2]));
  LUT5 #(
    .INIT(32'hAAAAAAAB)) 
    \detect_rd_cnt[3]_i_1 
       (.I0(init_dqsfound_done_r_reg_0),
        .I1(detect_rd_cnt_reg[3]),
        .I2(detect_rd_cnt_reg[1]),
        .I3(detect_rd_cnt_reg[0]),
        .I4(detect_rd_cnt_reg[2]),
        .O(\detect_rd_cnt[3]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hAAAAAAA8)) 
    \detect_rd_cnt[3]_i_2 
       (.I0(detect_pi_found_dqs),
        .I1(detect_rd_cnt_reg[3]),
        .I2(detect_rd_cnt_reg[1]),
        .I3(detect_rd_cnt_reg[0]),
        .I4(detect_rd_cnt_reg[2]),
        .O(detect_rd_cnt0));
  (* SOFT_HLUTNM = "soft_lutpair246" *) 
  LUT4 #(
    .INIT(16'hAAA9)) 
    \detect_rd_cnt[3]_i_3 
       (.I0(detect_rd_cnt_reg[3]),
        .I1(detect_rd_cnt_reg[2]),
        .I2(detect_rd_cnt_reg[0]),
        .I3(detect_rd_cnt_reg[1]),
        .O(detect_rd_cnt0__0[3]));
  FDSE \detect_rd_cnt_reg[0] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(detect_rd_cnt0),
        .D(detect_rd_cnt0__0[0]),
        .Q(detect_rd_cnt_reg[0]),
        .S(\detect_rd_cnt[3]_i_1_n_0 ));
  FDSE \detect_rd_cnt_reg[1] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(detect_rd_cnt0),
        .D(\detect_rd_cnt[1]_i_1_n_0 ),
        .Q(detect_rd_cnt_reg[1]),
        .S(\detect_rd_cnt[3]_i_1_n_0 ));
  FDSE \detect_rd_cnt_reg[2] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(detect_rd_cnt0),
        .D(detect_rd_cnt0__0[2]),
        .Q(detect_rd_cnt_reg[2]),
        .S(\detect_rd_cnt[3]_i_1_n_0 ));
  FDRE \detect_rd_cnt_reg[3] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(detect_rd_cnt0),
        .D(detect_rd_cnt0__0[3]),
        .Q(detect_rd_cnt_reg[3]),
        .R(\detect_rd_cnt[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000800000000000)) 
    dqs_found_done_r_i_1
       (.I0(p_1_in30_in),
        .I1(\rd_byte_data_offset_reg[0]_46 ),
        .I2(dqs_found_done_r_i_4_n_0),
        .I3(fine_adj_state_r[1]),
        .I4(fine_adj_state_r[0]),
        .I5(init_dqsfound_done_r1_reg_n_0),
        .O(dqs_found_done_r0));
  LUT3 #(
    .INIT(8'h80)) 
    dqs_found_done_r_i_2
       (.I0(pi_dqs_found_all_bank[2]),
        .I1(pi_dqs_found_all_bank[1]),
        .I2(pi_dqs_found_all_bank[0]),
        .O(p_1_in30_in));
  (* SOFT_HLUTNM = "soft_lutpair258" *) 
  LUT2 #(
    .INIT(4'h1)) 
    dqs_found_done_r_i_3
       (.I0(\rnk_cnt_r_reg_n_0_[0] ),
        .I1(\rnk_cnt_r_reg_n_0_[1] ),
        .O(\rd_byte_data_offset_reg[0]_46 ));
  LUT2 #(
    .INIT(4'h1)) 
    dqs_found_done_r_i_4
       (.I0(fine_adj_state_r[3]),
        .I1(fine_adj_state_r[2]),
        .O(dqs_found_done_r_i_4_n_0));
  FDRE dqs_found_done_r_reg
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(dqs_found_done_r0),
        .Q(dqs_found_done_r_reg_0),
        .R(\pi_dqs_found_any_bank_reg[0]_0 [0]));
  (* SOFT_HLUTNM = "soft_lutpair253" *) 
  LUT5 #(
    .INIT(32'hFFBF0080)) 
    dqs_found_prech_req_i_1
       (.I0(dqs_found_prech_req_i_2_n_0),
        .I1(fine_adj_state_r[1]),
        .I2(fine_adj_state_r[3]),
        .I3(dqs_found_prech_req_i_3_n_0),
        .I4(dqs_found_prech_req),
        .O(dqs_found_prech_req_i_1_n_0));
  LUT5 #(
    .INIT(32'h54545044)) 
    dqs_found_prech_req_i_2
       (.I0(fine_adj_state_r[2]),
        .I1(\FSM_sequential_fine_adj_state_r[1]_i_10_n_0 ),
        .I2(\FSM_sequential_fine_adj_state_r[1]_i_12_n_0 ),
        .I3(\FSM_sequential_fine_adj_state_r[1]_i_13_n_0 ),
        .I4(\FSM_sequential_fine_adj_state_r[1]_i_5_n_0 ),
        .O(dqs_found_prech_req_i_2_n_0));
  LUT6 #(
    .INIT(64'h5555FFFFFFFF00FC)) 
    dqs_found_prech_req_i_3
       (.I0(prech_done),
        .I1(dqs_found_prech_req_i_4_n_0),
        .I2(\FSM_sequential_fine_adj_state_r[2]_i_3_n_0 ),
        .I3(\FSM_sequential_fine_adj_state_r[2]_i_4_n_0 ),
        .I4(fine_adj_state_r[0]),
        .I5(fine_adj_state_r[2]),
        .O(dqs_found_prech_req_i_3_n_0));
  (* SOFT_HLUTNM = "soft_lutpair262" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    dqs_found_prech_req_i_4
       (.I0(detect_pi_found_dqs),
        .I1(pi_dqs_found_all_bank[0]),
        .I2(pi_dqs_found_all_bank[1]),
        .I3(pi_dqs_found_all_bank[2]),
        .O(dqs_found_prech_req_i_4_n_0));
  FDRE dqs_found_prech_req_reg
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(dqs_found_prech_req_i_1_n_0),
        .Q(dqs_found_prech_req),
        .R(\pi_dqs_found_any_bank_reg[0]_0 [0]));
  FDRE dqs_found_start_r_reg
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(dqs_found_start_r_reg_0),
        .Q(dqs_found_start_r),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair251" *) 
  LUT5 #(
    .INIT(32'hFFFF4440)) 
    final_dec_done_i_1
       (.I0(\FSM_sequential_fine_adj_state_r[0]_i_2_n_0 ),
        .I1(fine_adj_state_r[2]),
        .I2(init_dec_done_reg_n_0),
        .I3(\FSM_sequential_fine_adj_state_r[3]_i_4_n_0 ),
        .I4(final_dec_done_reg_n_0),
        .O(final_dec_done_i_1_n_0));
  FDRE final_dec_done_reg
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(final_dec_done_i_1_n_0),
        .Q(final_dec_done_reg_n_0),
        .R(\pi_dqs_found_any_bank_reg[0]_0 [1]));
  LUT6 #(
    .INIT(64'hFFFFFFFF01000000)) 
    fine_adjust_done_r_i_1
       (.I0(fine_adj_state_r[2]),
        .I1(fine_adj_state_r[3]),
        .I2(fine_adj_state_r[0]),
        .I3(p_1_in30_in),
        .I4(fine_adj_state_r[1]),
        .I5(fine_adjust_done_r_reg_n_0),
        .O(fine_adjust_done_r_i_1_n_0));
  FDRE fine_adjust_done_r_reg
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(fine_adjust_done_r_i_1_n_0),
        .Q(fine_adjust_done_r_reg_n_0),
        .R(\pi_dqs_found_any_bank_reg[0]_0 [1]));
  LUT6 #(
    .INIT(64'hFFFFFFFF00000004)) 
    fine_adjust_i_1
       (.I0(fine_adj_state_r[1]),
        .I1(init_dqsfound_done_r5),
        .I2(fine_adj_state_r[2]),
        .I3(fine_adj_state_r[3]),
        .I4(fine_adj_state_r[0]),
        .I5(fine_adjust_reg_0),
        .O(fine_adjust_i_1_n_0));
  FDRE fine_adjust_reg
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(fine_adjust_i_1_n_0),
        .Q(fine_adjust_reg_0),
        .R(\pi_dqs_found_any_bank_reg[0]_0 [1]));
  LUT6 #(
    .INIT(64'h00007FFFFFFFFFFF)) 
    first_fail_detect_i_1
       (.I0(stable_pass_cnt_reg[3]),
        .I1(stable_pass_cnt_reg[2]),
        .I2(stable_pass_cnt_reg[4]),
        .I3(stable_pass_cnt_reg[1]),
        .I4(stable_pass_cnt_reg[5]),
        .I5(first_fail_detect_reg_n_0),
        .O(first_fail_detect_i_1_n_0));
  FDRE first_fail_detect_reg
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(first_fail_detect),
        .D(first_fail_detect_i_1_n_0),
        .Q(first_fail_detect_reg_n_0),
        .R(first_fail_detect_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair284" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \first_fail_taps[0]_i_1 
       (.I0(\first_fail_taps[5]_i_3_n_0 ),
        .I1(\first_fail_taps[5]_i_5_n_0 ),
        .I2(\inc_cnt_reg_n_0_[0] ),
        .O(\first_fail_taps[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair287" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \first_fail_taps[1]_i_1 
       (.I0(\first_fail_taps[5]_i_3_n_0 ),
        .I1(\first_fail_taps[5]_i_5_n_0 ),
        .I2(\inc_cnt_reg_n_0_[1] ),
        .O(\first_fail_taps[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair288" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \first_fail_taps[2]_i_1 
       (.I0(\first_fail_taps[5]_i_3_n_0 ),
        .I1(\first_fail_taps[5]_i_5_n_0 ),
        .I2(\inc_cnt_reg_n_0_[2] ),
        .O(\first_fail_taps[2]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'hB8)) 
    \first_fail_taps[3]_i_1 
       (.I0(\first_fail_taps[5]_i_3_n_0 ),
        .I1(\first_fail_taps[5]_i_5_n_0 ),
        .I2(\inc_cnt_reg_n_0_[3] ),
        .O(\first_fail_taps[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair284" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \first_fail_taps[4]_i_1 
       (.I0(\first_fail_taps[5]_i_3_n_0 ),
        .I1(\first_fail_taps[5]_i_5_n_0 ),
        .I2(\inc_cnt_reg_n_0_[4] ),
        .O(\first_fail_taps[4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000D00000000)) 
    \first_fail_taps[5]_i_1 
       (.I0(first_fail_detect_reg_n_0),
        .I1(\first_fail_taps[5]_i_3_n_0 ),
        .I2(fine_adj_state_r[0]),
        .I3(\FSM_sequential_fine_adj_state_r[1]_i_5_n_0 ),
        .I4(fine_adj_state_r[2]),
        .I5(\first_fail_taps[5]_i_4_n_0 ),
        .O(first_fail_detect));
  (* SOFT_HLUTNM = "soft_lutpair287" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \first_fail_taps[5]_i_2 
       (.I0(\first_fail_taps[5]_i_3_n_0 ),
        .I1(\first_fail_taps[5]_i_5_n_0 ),
        .I2(\inc_cnt_reg_n_0_[5] ),
        .O(\first_fail_taps[5]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h15555555)) 
    \first_fail_taps[5]_i_3 
       (.I0(stable_pass_cnt_reg[5]),
        .I1(stable_pass_cnt_reg[1]),
        .I2(stable_pass_cnt_reg[4]),
        .I3(stable_pass_cnt_reg[2]),
        .I4(stable_pass_cnt_reg[3]),
        .O(\first_fail_taps[5]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair253" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \first_fail_taps[5]_i_4 
       (.I0(fine_adj_state_r[3]),
        .I1(fine_adj_state_r[1]),
        .O(\first_fail_taps[5]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair252" *) 
  LUT4 #(
    .INIT(16'h8A0A)) 
    \first_fail_taps[5]_i_5 
       (.I0(first_fail_detect_reg_n_0),
        .I1(\FSM_sequential_fine_adj_state_r[1]_i_9_n_0 ),
        .I2(\first_fail_taps[5]_i_3_n_0 ),
        .I3(\FSM_sequential_fine_adj_state_r[1]_i_11_n_0 ),
        .O(\first_fail_taps[5]_i_5_n_0 ));
  FDRE \first_fail_taps_reg[0] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(first_fail_detect),
        .D(\first_fail_taps[0]_i_1_n_0 ),
        .Q(\first_fail_taps_reg_n_0_[0] ),
        .R(\pi_dqs_found_any_bank_reg[0]_0 [0]));
  FDRE \first_fail_taps_reg[1] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(first_fail_detect),
        .D(\first_fail_taps[1]_i_1_n_0 ),
        .Q(\first_fail_taps_reg_n_0_[1] ),
        .R(\pi_dqs_found_any_bank_reg[0]_0 [0]));
  FDRE \first_fail_taps_reg[2] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(first_fail_detect),
        .D(\first_fail_taps[2]_i_1_n_0 ),
        .Q(\first_fail_taps_reg_n_0_[2] ),
        .R(\pi_dqs_found_any_bank_reg[0]_0 [0]));
  FDRE \first_fail_taps_reg[3] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(first_fail_detect),
        .D(\first_fail_taps[3]_i_1_n_0 ),
        .Q(\first_fail_taps_reg_n_0_[3] ),
        .R(\pi_dqs_found_any_bank_reg[0]_0 [0]));
  FDRE \first_fail_taps_reg[4] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(first_fail_detect),
        .D(\first_fail_taps[4]_i_1_n_0 ),
        .Q(\first_fail_taps_reg_n_0_[4] ),
        .R(\pi_dqs_found_any_bank_reg[0]_0 [0]));
  FDRE \first_fail_taps_reg[5] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(first_fail_detect),
        .D(\first_fail_taps[5]_i_2_n_0 ),
        .Q(\first_fail_taps_reg_n_0_[5] ),
        .R(\pi_dqs_found_any_bank_reg[0]_0 [0]));
  LUT6 #(
    .INIT(64'hFBFBFBFBBBFBFBFB)) 
    \gen_byte_sel_div2.byte_sel_cnt[3]_i_1 
       (.I0(\gen_byte_sel_div2.byte_sel_cnt_reg[0] ),
        .I1(cmd_delay_start0),
        .I2(ck_addr_cmd_delay_done),
        .I3(pi_calib_done),
        .I4(dqs_found_done_r_reg_0),
        .I5(byte_sel_cnt1),
        .O(SR));
  LUT2 #(
    .INIT(4'h2)) 
    \gen_byte_sel_div2.byte_sel_cnt[3]_i_4 
       (.I0(rd_data_offset_cal_done),
        .I1(fine_adjust_done_r_reg_n_0),
        .O(byte_sel_cnt1));
  LUT6 #(
    .INIT(64'h8FFFFFFF80FFFFFF)) 
    \gen_byte_sel_div2.calib_in_common_i_1 
       (.I0(\gen_byte_sel_div2.calib_in_common_i_2_n_0 ),
        .I1(ck_addr_cmd_delay_done),
        .I2(\gen_byte_sel_div2.calib_in_common_i_3_n_0 ),
        .I3(pi_fine_dly_dec_done),
        .I4(dqs_po_dec_done),
        .I5(calib_in_common),
        .O(delay_done_r4_reg));
  LUT6 #(
    .INIT(64'hFBFB08FBFBFBFBFB)) 
    \gen_byte_sel_div2.calib_in_common_i_2 
       (.I0(\pi_rst_stg1_cal_reg[0]_0 ),
        .I1(rd_data_offset_cal_done),
        .I2(fine_adjust_done_r_reg_n_0),
        .I3(dqs_found_done_r_reg_0),
        .I4(calib_in_common4_out),
        .I5(pi_calib_done),
        .O(\gen_byte_sel_div2.calib_in_common_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hDFDFFFDFFFFFFFFF)) 
    \gen_byte_sel_div2.calib_in_common_i_3 
       (.I0(dqs_found_done_r_reg_0),
        .I1(\gen_byte_sel_div2.calib_in_common_reg ),
        .I2(pi_calib_done),
        .I3(rd_data_offset_cal_done),
        .I4(fine_adjust_done_r_reg_n_0),
        .I5(ck_addr_cmd_delay_done),
        .O(\gen_byte_sel_div2.calib_in_common_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h2F20FFFF2F200000)) 
    \gen_byte_sel_div2.ctl_lane_sel[0]_i_1 
       (.I0(fine_adjust_lane_cnt[0]),
        .I1(\pi_rst_stg1_cal_reg[0]_0 ),
        .I2(ck_addr_cmd_delay_done),
        .I3(ctl_lane_cnt[0]),
        .I4(ctl_lane_sel),
        .I5(\gen_byte_sel_div2.ctl_lane_sel_reg[0] ),
        .O(\ctl_lane_cnt_reg[0]_0 ));
  LUT6 #(
    .INIT(64'h2F20FFFF2F200000)) 
    \gen_byte_sel_div2.ctl_lane_sel[1]_i_1 
       (.I0(fine_adjust_lane_cnt[1]),
        .I1(\pi_rst_stg1_cal_reg[0]_0 ),
        .I2(ck_addr_cmd_delay_done),
        .I3(ctl_lane_cnt[1]),
        .I4(ctl_lane_sel),
        .I5(\gen_byte_sel_div2.ctl_lane_sel_reg[1] ),
        .O(\ctl_lane_cnt_reg[1]_0 ));
  LUT6 #(
    .INIT(64'h2F20FFFF2F200000)) 
    \gen_byte_sel_div2.ctl_lane_sel[2]_i_1 
       (.I0(fine_adjust_lane_cnt[2]),
        .I1(\pi_rst_stg1_cal_reg[0]_0 ),
        .I2(ck_addr_cmd_delay_done),
        .I3(ctl_lane_cnt[2]),
        .I4(ctl_lane_sel),
        .I5(\gen_byte_sel_div2.ctl_lane_sel_reg[2]_1 ),
        .O(\ctl_lane_cnt_reg[2]_0 ));
  LUT3 #(
    .INIT(8'hFE)) 
    \gen_byte_sel_div2.ctl_lane_sel[2]_i_2 
       (.I0(\pi_rst_stg1_cal_reg[2]_0 [0]),
        .I1(\pi_rst_stg1_cal_reg[2]_0 [2]),
        .I2(\pi_rst_stg1_cal_reg[2]_0 [1]),
        .O(\pi_rst_stg1_cal_reg[0]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair286" *) 
  LUT3 #(
    .INIT(8'h80)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_4 
       (.I0(dqs_found_done_r_reg_0),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg[10] ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0 ),
        .O(dqs_found_done_r_reg_1));
  LUT1 #(
    .INIT(2'h2)) 
    i_0
       (.I0(1'b1),
        .O(n_0_0));
  LUT1 #(
    .INIT(2'h2)) 
    i_1
       (.I0(1'b1),
        .O(n_0_1));
  LUT1 #(
    .INIT(2'h2)) 
    i_2
       (.I0(1'b1),
        .O(n_0_2));
  LUT1 #(
    .INIT(2'h2)) 
    i_3
       (.I0(1'b1),
        .O(n_0_3));
  LUT1 #(
    .INIT(2'h1)) 
    \inc_cnt[0]_i_1 
       (.I0(\inc_cnt_reg_n_0_[0] ),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair290" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \inc_cnt[1]_i_1 
       (.I0(\inc_cnt_reg_n_0_[0] ),
        .I1(\inc_cnt_reg_n_0_[1] ),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair290" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \inc_cnt[2]_i_1 
       (.I0(\inc_cnt_reg_n_0_[2] ),
        .I1(\inc_cnt_reg_n_0_[1] ),
        .I2(\inc_cnt_reg_n_0_[0] ),
        .O(p_0_in[2]));
  (* SOFT_HLUTNM = "soft_lutpair271" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \inc_cnt[3]_i_1 
       (.I0(\inc_cnt_reg_n_0_[3] ),
        .I1(\inc_cnt_reg_n_0_[2] ),
        .I2(\inc_cnt_reg_n_0_[0] ),
        .I3(\inc_cnt_reg_n_0_[1] ),
        .O(p_0_in[3]));
  (* SOFT_HLUTNM = "soft_lutpair250" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \inc_cnt[4]_i_1 
       (.I0(\inc_cnt_reg_n_0_[4] ),
        .I1(\inc_cnt_reg_n_0_[3] ),
        .I2(\inc_cnt_reg_n_0_[1] ),
        .I3(\inc_cnt_reg_n_0_[0] ),
        .I4(\inc_cnt_reg_n_0_[2] ),
        .O(p_0_in[4]));
  LUT6 #(
    .INIT(64'h0000000000000400)) 
    \inc_cnt[5]_i_1 
       (.I0(fine_adjust_lane_cnt[0]),
        .I1(fine_adjust_lane_cnt[1]),
        .I2(fine_adjust_lane_cnt[2]),
        .I3(fine_adj_state_r[2]),
        .I4(\inc_cnt[5]_i_3_n_0 ),
        .I5(fine_adj_state_r[3]),
        .O(inc_cnt));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAAAAAA)) 
    \inc_cnt[5]_i_2 
       (.I0(\inc_cnt_reg_n_0_[5] ),
        .I1(\inc_cnt_reg_n_0_[3] ),
        .I2(\inc_cnt_reg_n_0_[1] ),
        .I3(\inc_cnt_reg_n_0_[4] ),
        .I4(\inc_cnt_reg_n_0_[2] ),
        .I5(\inc_cnt_reg_n_0_[0] ),
        .O(p_0_in[5]));
  (* SOFT_HLUTNM = "soft_lutpair294" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \inc_cnt[5]_i_3 
       (.I0(fine_adj_state_r[0]),
        .I1(fine_adj_state_r[1]),
        .O(\inc_cnt[5]_i_3_n_0 ));
  FDRE \inc_cnt_reg[0] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(inc_cnt),
        .D(p_0_in[0]),
        .Q(\inc_cnt_reg_n_0_[0] ),
        .R(\stable_pass_cnt_reg[0]_0 ));
  FDRE \inc_cnt_reg[1] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(inc_cnt),
        .D(p_0_in[1]),
        .Q(\inc_cnt_reg_n_0_[1] ),
        .R(\stable_pass_cnt_reg[0]_0 ));
  FDRE \inc_cnt_reg[2] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(inc_cnt),
        .D(p_0_in[2]),
        .Q(\inc_cnt_reg_n_0_[2] ),
        .R(\stable_pass_cnt_reg[0]_0 ));
  FDRE \inc_cnt_reg[3] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(inc_cnt),
        .D(p_0_in[3]),
        .Q(\inc_cnt_reg_n_0_[3] ),
        .R(\stable_pass_cnt_reg[0]_0 ));
  FDRE \inc_cnt_reg[4] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(inc_cnt),
        .D(p_0_in[4]),
        .Q(\inc_cnt_reg_n_0_[4] ),
        .R(\stable_pass_cnt_reg[0]_0 ));
  FDRE \inc_cnt_reg[5] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(inc_cnt),
        .D(p_0_in[5]),
        .Q(\inc_cnt_reg_n_0_[5] ),
        .R(\stable_pass_cnt_reg[0]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \init_dec_cnt[0]_i_1 
       (.I0(init_dec_cnt_reg[0]),
        .O(init_dec_cnt0[0]));
  (* SOFT_HLUTNM = "soft_lutpair285" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \init_dec_cnt[1]_i_1 
       (.I0(init_dec_cnt_reg[0]),
        .I1(init_dec_cnt_reg[1]),
        .O(\init_dec_cnt[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair285" *) 
  LUT3 #(
    .INIT(8'hE1)) 
    \init_dec_cnt[2]_i_1 
       (.I0(init_dec_cnt_reg[0]),
        .I1(init_dec_cnt_reg[1]),
        .I2(init_dec_cnt_reg[2]),
        .O(init_dec_cnt0[2]));
  (* SOFT_HLUTNM = "soft_lutpair265" *) 
  LUT4 #(
    .INIT(16'hFE01)) 
    \init_dec_cnt[3]_i_1 
       (.I0(init_dec_cnt_reg[2]),
        .I1(init_dec_cnt_reg[1]),
        .I2(init_dec_cnt_reg[0]),
        .I3(init_dec_cnt_reg[3]),
        .O(init_dec_cnt0[3]));
  (* SOFT_HLUTNM = "soft_lutpair265" *) 
  LUT5 #(
    .INIT(32'hFFFE0001)) 
    \init_dec_cnt[4]_i_1 
       (.I0(init_dec_cnt_reg[3]),
        .I1(init_dec_cnt_reg[0]),
        .I2(init_dec_cnt_reg[1]),
        .I3(init_dec_cnt_reg[2]),
        .I4(init_dec_cnt_reg[4]),
        .O(init_dec_cnt0[4]));
  LUT6 #(
    .INIT(64'h0000000000008000)) 
    \init_dec_cnt[5]_i_1 
       (.I0(\FSM_sequential_fine_adj_state_r[3]_i_4_n_0 ),
        .I1(fine_adj_state_r[0]),
        .I2(fine_adj_state_r[3]),
        .I3(fine_adj_state_r[1]),
        .I4(fine_adj_state_r[2]),
        .I5(\init_dec_cnt[5]_i_3_n_0 ),
        .O(init_dec_cnt));
  LUT6 #(
    .INIT(64'hFFFFFFFE00000001)) 
    \init_dec_cnt[5]_i_2 
       (.I0(init_dec_cnt_reg[4]),
        .I1(init_dec_cnt_reg[2]),
        .I2(init_dec_cnt_reg[1]),
        .I3(init_dec_cnt_reg[0]),
        .I4(init_dec_cnt_reg[3]),
        .I5(init_dec_cnt_reg[5]),
        .O(init_dec_cnt0[5]));
  (* SOFT_HLUTNM = "soft_lutpair276" *) 
  LUT3 #(
    .INIT(8'hFB)) 
    \init_dec_cnt[5]_i_3 
       (.I0(fine_adjust_lane_cnt[0]),
        .I1(fine_adjust_lane_cnt[1]),
        .I2(fine_adjust_lane_cnt[2]),
        .O(\init_dec_cnt[5]_i_3_n_0 ));
  FDSE \init_dec_cnt_reg[0] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(init_dec_cnt),
        .D(init_dec_cnt0[0]),
        .Q(init_dec_cnt_reg[0]),
        .S(\init_dec_cnt_reg[4]_0 ));
  FDSE \init_dec_cnt_reg[1] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(init_dec_cnt),
        .D(\init_dec_cnt[1]_i_1_n_0 ),
        .Q(init_dec_cnt_reg[1]),
        .S(\init_dec_cnt_reg[4]_0 ));
  FDSE \init_dec_cnt_reg[2] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(init_dec_cnt),
        .D(init_dec_cnt0[2]),
        .Q(init_dec_cnt_reg[2]),
        .S(\init_dec_cnt_reg[4]_0 ));
  FDSE \init_dec_cnt_reg[3] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(init_dec_cnt),
        .D(init_dec_cnt0[3]),
        .Q(init_dec_cnt_reg[3]),
        .S(\init_dec_cnt_reg[4]_0 ));
  FDSE \init_dec_cnt_reg[4] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(init_dec_cnt),
        .D(init_dec_cnt0[4]),
        .Q(init_dec_cnt_reg[4]),
        .S(\init_dec_cnt_reg[4]_0 ));
  FDRE \init_dec_cnt_reg[5] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(init_dec_cnt),
        .D(init_dec_cnt0[5]),
        .Q(init_dec_cnt_reg[5]),
        .R(\init_dec_cnt_reg[4]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair251" *) 
  LUT4 #(
    .INIT(16'hCCDC)) 
    init_dec_done_i_1
       (.I0(\FSM_sequential_fine_adj_state_r[3]_i_4_n_0 ),
        .I1(init_dec_done_reg_n_0),
        .I2(fine_adj_state_r[2]),
        .I3(\FSM_sequential_fine_adj_state_r[0]_i_2_n_0 ),
        .O(init_dec_done_i_1_n_0));
  FDRE init_dec_done_reg
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(init_dec_done_i_1_n_0),
        .Q(init_dec_done_reg_n_0),
        .R(\pi_dqs_found_any_bank_reg[0]_0 [1]));
  FDRE init_dqsfound_done_r1_reg
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(rd_data_offset_cal_done),
        .Q(init_dqsfound_done_r1_reg_n_0),
        .R(1'b0));
  FDRE init_dqsfound_done_r2_reg
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(init_dqsfound_done_r1_reg_n_0),
        .Q(init_dqsfound_done_r2),
        .R(1'b0));
  (* srl_name = "\u_mig_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/dqsfind_calib_left.u_ddr_phy_dqs_found_cal_hr/init_dqsfound_done_r4_reg_srl2 " *) 
  SRL16E init_dqsfound_done_r4_reg_srl2
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(init_dqsfound_done_r5_reg_0),
        .D(init_dqsfound_done_r2),
        .Q(init_dqsfound_done_r4_reg_srl2_n_0));
  FDRE init_dqsfound_done_r5_reg
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(init_dqsfound_done_r4_reg_srl2_n_0),
        .Q(init_dqsfound_done_r5),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h00000100)) 
    init_dqsfound_done_r_i_1
       (.I0(\pi_rst_stg1_cal_r_reg_n_0_[0] ),
        .I1(init_dqsfound_done_r_reg_0),
        .I2(\pi_rst_stg1_cal_r_reg_n_0_[1] ),
        .I3(init_dqsfound_done_r_i_2_n_0),
        .I4(\pi_rst_stg1_cal_r_reg_n_0_[2] ),
        .O(init_dqsfound_done_r_i_1_n_0));
  LUT6 #(
    .INIT(64'h1FFFFFFF10000000)) 
    init_dqsfound_done_r_i_2
       (.I0(\rnk_cnt_r_reg_n_0_[0] ),
        .I1(\rnk_cnt_r_reg_n_0_[1] ),
        .I2(pi_dqs_found_all_bank[2]),
        .I3(pi_dqs_found_all_bank[1]),
        .I4(pi_dqs_found_all_bank[0]),
        .I5(rd_data_offset_cal_done),
        .O(init_dqsfound_done_r_i_2_n_0));
  FDRE init_dqsfound_done_r_reg
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(init_dqsfound_done_r_i_1_n_0),
        .Q(rd_data_offset_cal_done),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hFE)) 
    \init_state_r[0]_i_24 
       (.I0(pi_dqs_found_rank_done),
        .I1(\init_state_r[0]_i_10 ),
        .I2(dqs_found_done_r_reg_0),
        .O(rank_done_r_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair286" *) 
  LUT2 #(
    .INIT(4'h7)) 
    \init_state_r[2]_i_28 
       (.I0(dqs_found_done_r_reg_0),
        .I1(\init_state_r[2]_i_10 ),
        .O(dqs_found_done_r_reg_2));
  LUT4 #(
    .INIT(16'h8000)) 
    \pi_dqs_found_all_bank[0]_i_1 
       (.I0(pi_dqs_found_lanes_r3[0]),
        .I1(pi_dqs_found_lanes_r3[1]),
        .I2(pi_dqs_found_lanes_r3[2]),
        .I3(pi_dqs_found_lanes_r3[3]),
        .O(p_8_out[0]));
  LUT4 #(
    .INIT(16'h8000)) 
    \pi_dqs_found_all_bank[2]_i_1 
       (.I0(pi_dqs_found_lanes_r3[8]),
        .I1(pi_dqs_found_lanes_r3[9]),
        .I2(pi_dqs_found_lanes_r3[10]),
        .I3(pi_dqs_found_lanes_r3[11]),
        .O(p_8_out[2]));
  FDRE \pi_dqs_found_all_bank_r_reg[0] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(pi_dqs_found_all_bank[0]),
        .Q(pi_dqs_found_all_bank_r[0]),
        .R(1'b0));
  FDRE \pi_dqs_found_all_bank_r_reg[1] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(pi_dqs_found_all_bank[1]),
        .Q(pi_dqs_found_all_bank_r[1]),
        .R(1'b0));
  FDRE \pi_dqs_found_all_bank_r_reg[2] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(pi_dqs_found_all_bank[2]),
        .Q(pi_dqs_found_all_bank_r[2]),
        .R(1'b0));
  FDRE \pi_dqs_found_all_bank_reg[0] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(dqs_found_start_r_reg_0),
        .D(p_8_out[0]),
        .Q(pi_dqs_found_all_bank[0]),
        .R(\pi_dqs_found_any_bank_reg[0]_0 [1]));
  FDRE \pi_dqs_found_all_bank_reg[1] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(dqs_found_start_r_reg_0),
        .D(dqs_found_start_r_reg_0),
        .Q(pi_dqs_found_all_bank[1]),
        .R(\pi_dqs_found_any_bank_reg[0]_0 [1]));
  FDRE \pi_dqs_found_all_bank_reg[2] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(dqs_found_start_r_reg_0),
        .D(p_8_out[2]),
        .Q(pi_dqs_found_all_bank[2]),
        .R(\pi_dqs_found_any_bank_reg[0]_0 [1]));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \pi_dqs_found_any_bank[0]_i_1 
       (.I0(pi_dqs_found_lanes_r3[0]),
        .I1(pi_dqs_found_lanes_r3[1]),
        .I2(pi_dqs_found_lanes_r3[3]),
        .I3(pi_dqs_found_lanes_r3[2]),
        .O(\pi_dqs_found_any_bank[0]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \pi_dqs_found_any_bank[2]_i_1 
       (.I0(pi_dqs_found_lanes_r3[8]),
        .I1(pi_dqs_found_lanes_r3[11]),
        .I2(pi_dqs_found_lanes_r3[9]),
        .I3(pi_dqs_found_lanes_r3[10]),
        .O(\pi_dqs_found_any_bank[2]_i_1_n_0 ));
  FDRE \pi_dqs_found_any_bank_r_reg[0] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(pi_dqs_found_any_bank[0]),
        .Q(\pi_dqs_found_any_bank_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \pi_dqs_found_any_bank_r_reg[2] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(pi_dqs_found_any_bank[2]),
        .Q(p_0_in62_in),
        .R(1'b0));
  FDRE \pi_dqs_found_any_bank_reg[0] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(dqs_found_start_r_reg_0),
        .D(\pi_dqs_found_any_bank[0]_i_1_n_0 ),
        .Q(pi_dqs_found_any_bank[0]),
        .R(\pi_dqs_found_any_bank_reg[0]_0 [1]));
  FDRE \pi_dqs_found_any_bank_reg[2] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(dqs_found_start_r_reg_0),
        .D(\pi_dqs_found_any_bank[2]_i_1_n_0 ),
        .Q(pi_dqs_found_any_bank[2]),
        .R(\pi_dqs_found_any_bank_reg[0]_0 [1]));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r1_reg[0] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(in0[0]),
        .Q(pi_dqs_found_lanes_r1[0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r1_reg[10] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(in0[6]),
        .Q(pi_dqs_found_lanes_r1[10]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r1_reg[11] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(in0[7]),
        .Q(pi_dqs_found_lanes_r1[11]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r1_reg[1] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(in0[1]),
        .Q(pi_dqs_found_lanes_r1[1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r1_reg[2] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(in0[2]),
        .Q(pi_dqs_found_lanes_r1[2]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r1_reg[3] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(in0[3]),
        .Q(pi_dqs_found_lanes_r1[3]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r1_reg[4] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(n_0_3),
        .Q(pi_dqs_found_lanes_r1[4]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r1_reg[5] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(n_0_2),
        .Q(pi_dqs_found_lanes_r1[5]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r1_reg[6] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(n_0_1),
        .Q(pi_dqs_found_lanes_r1[6]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r1_reg[7] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(n_0_0),
        .Q(pi_dqs_found_lanes_r1[7]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r1_reg[8] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(in0[4]),
        .Q(pi_dqs_found_lanes_r1[8]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r1_reg[9] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(in0[5]),
        .Q(pi_dqs_found_lanes_r1[9]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r2_reg[0] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(pi_dqs_found_lanes_r1[0]),
        .Q(pi_dqs_found_lanes_r2[0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r2_reg[10] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(pi_dqs_found_lanes_r1[10]),
        .Q(pi_dqs_found_lanes_r2[10]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r2_reg[11] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(pi_dqs_found_lanes_r1[11]),
        .Q(pi_dqs_found_lanes_r2[11]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r2_reg[1] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(pi_dqs_found_lanes_r1[1]),
        .Q(pi_dqs_found_lanes_r2[1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r2_reg[2] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(pi_dqs_found_lanes_r1[2]),
        .Q(pi_dqs_found_lanes_r2[2]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r2_reg[3] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(pi_dqs_found_lanes_r1[3]),
        .Q(pi_dqs_found_lanes_r2[3]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r2_reg[4] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(pi_dqs_found_lanes_r1[4]),
        .Q(pi_dqs_found_lanes_r2[4]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r2_reg[5] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(pi_dqs_found_lanes_r1[5]),
        .Q(pi_dqs_found_lanes_r2[5]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r2_reg[6] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(pi_dqs_found_lanes_r1[6]),
        .Q(pi_dqs_found_lanes_r2[6]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r2_reg[7] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(pi_dqs_found_lanes_r1[7]),
        .Q(pi_dqs_found_lanes_r2[7]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r2_reg[8] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(pi_dqs_found_lanes_r1[8]),
        .Q(pi_dqs_found_lanes_r2[8]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r2_reg[9] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(pi_dqs_found_lanes_r1[9]),
        .Q(pi_dqs_found_lanes_r2[9]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r3_reg[0] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(pi_dqs_found_lanes_r2[0]),
        .Q(pi_dqs_found_lanes_r3[0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r3_reg[10] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(pi_dqs_found_lanes_r2[10]),
        .Q(pi_dqs_found_lanes_r3[10]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r3_reg[11] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(pi_dqs_found_lanes_r2[11]),
        .Q(pi_dqs_found_lanes_r3[11]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r3_reg[1] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(pi_dqs_found_lanes_r2[1]),
        .Q(pi_dqs_found_lanes_r3[1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r3_reg[2] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(pi_dqs_found_lanes_r2[2]),
        .Q(pi_dqs_found_lanes_r3[2]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r3_reg[3] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(pi_dqs_found_lanes_r2[3]),
        .Q(pi_dqs_found_lanes_r3[3]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r3_reg[4] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(pi_dqs_found_lanes_r2[4]),
        .Q(pi_dqs_found_lanes_r3[4]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r3_reg[5] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(pi_dqs_found_lanes_r2[5]),
        .Q(pi_dqs_found_lanes_r3[5]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r3_reg[6] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(pi_dqs_found_lanes_r2[6]),
        .Q(pi_dqs_found_lanes_r3[6]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r3_reg[7] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(pi_dqs_found_lanes_r2[7]),
        .Q(pi_dqs_found_lanes_r3[7]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r3_reg[8] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(pi_dqs_found_lanes_r2[8]),
        .Q(pi_dqs_found_lanes_r3[8]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \pi_dqs_found_lanes_r3_reg[9] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(pi_dqs_found_lanes_r2[9]),
        .Q(pi_dqs_found_lanes_r3[9]),
        .R(1'b0));
  LUT2 #(
    .INIT(4'hE)) 
    \pi_rst_stg1_cal[0]_i_1 
       (.I0(\pi_rst_stg1_cal_r_reg_n_0_[0] ),
        .I1(rst_dqs_find),
        .O(\pi_rst_stg1_cal[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair293" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \pi_rst_stg1_cal[1]_i_1 
       (.I0(\pi_rst_stg1_cal_r_reg_n_0_[1] ),
        .I1(rst_dqs_find),
        .O(\pi_rst_stg1_cal[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair293" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \pi_rst_stg1_cal[2]_i_1 
       (.I0(\pi_rst_stg1_cal_r_reg_n_0_[2] ),
        .I1(rst_dqs_find),
        .O(\pi_rst_stg1_cal[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h000000000000FFA8)) 
    \pi_rst_stg1_cal_r1[0]_i_1 
       (.I0(\pi_rst_stg1_cal_r1_reg_n_0_[0] ),
        .I1(\pi_dqs_found_any_bank_r_reg_n_0_[0] ),
        .I2(pi_dqs_found_all_bank[0]),
        .I3(\pi_rst_stg1_cal_r_reg_n_0_[0] ),
        .I4(init_dqsfound_done_r_reg_0),
        .I5(fine_adjust_reg_0),
        .O(\pi_rst_stg1_cal_r1[0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h000000F8)) 
    \pi_rst_stg1_cal_r1[1]_i_1 
       (.I0(p_0_in22_in),
        .I1(pi_dqs_found_all_bank[1]),
        .I2(\pi_rst_stg1_cal_r_reg_n_0_[1] ),
        .I3(init_dqsfound_done_r_reg_0),
        .I4(fine_adjust_reg_0),
        .O(\pi_rst_stg1_cal_r1[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h000000000000FFA8)) 
    \pi_rst_stg1_cal_r1[2]_i_1 
       (.I0(p_0_in17_in),
        .I1(p_0_in62_in),
        .I2(pi_dqs_found_all_bank[2]),
        .I3(\pi_rst_stg1_cal_r_reg_n_0_[2] ),
        .I4(init_dqsfound_done_r_reg_0),
        .I5(fine_adjust_reg_0),
        .O(\pi_rst_stg1_cal_r1[2]_i_1_n_0 ));
  FDRE \pi_rst_stg1_cal_r1_reg[0] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(\pi_rst_stg1_cal_r1[0]_i_1_n_0 ),
        .Q(\pi_rst_stg1_cal_r1_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \pi_rst_stg1_cal_r1_reg[1] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(\pi_rst_stg1_cal_r1[1]_i_1_n_0 ),
        .Q(p_0_in22_in),
        .R(1'b0));
  FDRE \pi_rst_stg1_cal_r1_reg[2] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(\pi_rst_stg1_cal_r1[2]_i_1_n_0 ),
        .Q(p_0_in17_in),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000011111110)) 
    \pi_rst_stg1_cal_r[0]_i_1 
       (.I0(fine_adjust_reg_0),
        .I1(init_dqsfound_done_r_reg_0),
        .I2(\pi_rst_stg1_cal_r[0]_i_2_n_0 ),
        .I3(\rd_byte_data_offset[0][5]_i_4_n_0 ),
        .I4(\pi_rst_stg1_cal_r_reg_n_0_[0] ),
        .I5(\pi_rst_stg1_cal_r1_reg_n_0_[0] ),
        .O(\pi_rst_stg1_cal_r[0]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h4F44)) 
    \pi_rst_stg1_cal_r[0]_i_2 
       (.I0(dqs_found_start_r),
        .I1(dqs_found_start_r_reg_0),
        .I2(pi_dqs_found_all_bank[0]),
        .I3(\pi_dqs_found_any_bank_r_reg_n_0_[0] ),
        .O(\pi_rst_stg1_cal_r[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAAAAA08)) 
    \pi_rst_stg1_cal_r[1]_i_1 
       (.I0(\pi_rst_stg1_cal_r_reg[1]_0 ),
        .I1(dqs_found_start_r_reg_0),
        .I2(dqs_found_start_r),
        .I3(\rd_byte_data_offset[0][11]_i_4_n_0 ),
        .I4(\pi_rst_stg1_cal_r_reg_n_0_[1] ),
        .I5(p_0_in22_in),
        .O(\pi_rst_stg1_cal_r[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000011111110)) 
    \pi_rst_stg1_cal_r[2]_i_1 
       (.I0(fine_adjust_reg_0),
        .I1(init_dqsfound_done_r_reg_0),
        .I2(\pi_rst_stg1_cal_r[2]_i_2_n_0 ),
        .I3(\rd_byte_data_offset[0][17]_i_4_n_0 ),
        .I4(\pi_rst_stg1_cal_r_reg_n_0_[2] ),
        .I5(p_0_in17_in),
        .O(\pi_rst_stg1_cal_r[2]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h4F44)) 
    \pi_rst_stg1_cal_r[2]_i_2 
       (.I0(dqs_found_start_r),
        .I1(dqs_found_start_r_reg_0),
        .I2(pi_dqs_found_all_bank[2]),
        .I3(p_0_in62_in),
        .O(\pi_rst_stg1_cal_r[2]_i_2_n_0 ));
  FDRE \pi_rst_stg1_cal_r_reg[0] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(\pi_rst_stg1_cal_r[0]_i_1_n_0 ),
        .Q(\pi_rst_stg1_cal_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \pi_rst_stg1_cal_r_reg[1] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(\pi_rst_stg1_cal_r[1]_i_1_n_0 ),
        .Q(\pi_rst_stg1_cal_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \pi_rst_stg1_cal_r_reg[2] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(\pi_rst_stg1_cal_r[2]_i_1_n_0 ),
        .Q(\pi_rst_stg1_cal_r_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \pi_rst_stg1_cal_reg[0] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(\pi_rst_stg1_cal[0]_i_1_n_0 ),
        .Q(\pi_rst_stg1_cal_reg[2]_0 [0]),
        .R(\pi_dqs_found_any_bank_reg[0]_0 [0]));
  FDRE \pi_rst_stg1_cal_reg[1] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(\pi_rst_stg1_cal[1]_i_1_n_0 ),
        .Q(\pi_rst_stg1_cal_reg[2]_0 [1]),
        .R(\pi_dqs_found_any_bank_reg[0]_0 [0]));
  FDRE \pi_rst_stg1_cal_reg[2] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(\pi_rst_stg1_cal[2]_i_1_n_0 ),
        .Q(\pi_rst_stg1_cal_reg[2]_0 [2]),
        .R(\pi_dqs_found_any_bank_reg[0]_0 [0]));
  FDRE rank_done_r1_reg
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(pi_dqs_found_rank_done),
        .Q(rank_done_r1),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair258" *) 
  LUT5 #(
    .INIT(32'h00005551)) 
    rank_done_r_i_1
       (.I0(init_dqsfound_done_r_reg_0),
        .I1(rd_data_offset_cal_done),
        .I2(\rnk_cnt_r_reg_n_0_[1] ),
        .I3(\rnk_cnt_r_reg_n_0_[0] ),
        .I4(rank_done_r_i_2_n_0),
        .O(rank_done_r_i_1_n_0));
  LUT6 #(
    .INIT(64'hFF7F7F7F7F7F7F7F)) 
    rank_done_r_i_2
       (.I0(pi_dqs_found_all_bank[0]),
        .I1(pi_dqs_found_all_bank[1]),
        .I2(pi_dqs_found_all_bank[2]),
        .I3(pi_dqs_found_all_bank_r[2]),
        .I4(pi_dqs_found_all_bank_r[1]),
        .I5(pi_dqs_found_all_bank_r[0]),
        .O(rank_done_r_i_2_n_0));
  FDRE rank_done_r_reg
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(rank_done_r_i_1_n_0),
        .Q(pi_dqs_found_rank_done),
        .R(1'b0));
  LUT2 #(
    .INIT(4'h2)) 
    \rank_final_loop[0].bank_final_loop[0].final_data_offset[0][5]_i_1 
       (.I0(rd_data_offset_cal_done),
        .I1(init_dqsfound_done_r1_reg_n_0),
        .O(p_22_out));
  (* SOFT_HLUTNM = "soft_lutpair282" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][0]_i_1 
       (.I0(\rd_byte_data_offset_reg_n_0_[0][0] ),
        .O(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair273" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][1]_i_1 
       (.I0(\rd_byte_data_offset_reg_n_0_[0][0] ),
        .I1(\rd_byte_data_offset_reg_n_0_[0][1] ),
        .O(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][1]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'hA9)) 
    \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][2]_i_1 
       (.I0(\rd_byte_data_offset_reg_n_0_[0][2] ),
        .I1(\rd_byte_data_offset_reg_n_0_[0][0] ),
        .I2(\rd_byte_data_offset_reg_n_0_[0][1] ),
        .O(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair263" *) 
  LUT4 #(
    .INIT(16'hAAA9)) 
    \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][3]_i_1 
       (.I0(Q),
        .I1(\rd_byte_data_offset_reg_n_0_[0][2] ),
        .I2(\rd_byte_data_offset_reg_n_0_[0][1] ),
        .I3(\rd_byte_data_offset_reg_n_0_[0][0] ),
        .O(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair263" *) 
  LUT5 #(
    .INIT(32'hAAAAAAA9)) 
    \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][4]_i_1 
       (.I0(\rd_byte_data_offset_reg_n_0_[0][4] ),
        .I1(Q),
        .I2(\rd_byte_data_offset_reg_n_0_[0][0] ),
        .I3(\rd_byte_data_offset_reg_n_0_[0][1] ),
        .I4(\rd_byte_data_offset_reg_n_0_[0][2] ),
        .O(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][4]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'h04)) 
    \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_1 
       (.I0(init_dqsfound_done_r1_reg_n_0),
        .I1(rd_data_offset_cal_done),
        .I2(init_dqsfound_done_r_reg_0),
        .O(final_data_offset_mc));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAAAA9)) 
    \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_2 
       (.I0(\rd_byte_data_offset_reg_n_0_[0][5] ),
        .I1(\rd_byte_data_offset_reg_n_0_[0][4] ),
        .I2(\rd_byte_data_offset_reg_n_0_[0][2] ),
        .I3(\rd_byte_data_offset_reg_n_0_[0][1] ),
        .I4(\rd_byte_data_offset_reg_n_0_[0][0] ),
        .I5(Q),
        .O(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_2_n_0 ));
  FDRE \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(final_data_offset_mc),
        .D(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][0]_i_1_n_0 ),
        .Q(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]_0 [0]),
        .R(1'b0));
  FDRE \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][1] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(final_data_offset_mc),
        .D(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][1]_i_1_n_0 ),
        .Q(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]_0 [1]),
        .R(1'b0));
  FDRE \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][2] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(final_data_offset_mc),
        .D(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][2]_i_1_n_0 ),
        .Q(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]_0 [2]),
        .R(1'b0));
  FDRE \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][3] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(final_data_offset_mc),
        .D(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][3]_i_1_n_0 ),
        .Q(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]_0 [3]),
        .R(1'b0));
  FDRE \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][4] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(final_data_offset_mc),
        .D(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][4]_i_1_n_0 ),
        .Q(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]_0 [4]),
        .R(1'b0));
  FDRE \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(final_data_offset_mc),
        .D(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][5]_i_2_n_0 ),
        .Q(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5]_0 [5]),
        .R(1'b0));
  FDRE \rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][0] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(p_22_out),
        .D(\rd_byte_data_offset_reg_n_0_[0][0] ),
        .Q(rd_data_offset_ranks_0[0]),
        .R(\pi_dqs_found_any_bank_reg[0]_0 [1]));
  FDRE \rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][1] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(p_22_out),
        .D(\rd_byte_data_offset_reg_n_0_[0][1] ),
        .Q(rd_data_offset_ranks_0[1]),
        .R(\pi_dqs_found_any_bank_reg[0]_0 [1]));
  FDRE \rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][2] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(p_22_out),
        .D(\rd_byte_data_offset_reg_n_0_[0][2] ),
        .Q(rd_data_offset_ranks_0[2]),
        .R(\pi_dqs_found_any_bank_reg[0]_0 [1]));
  FDRE \rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(p_22_out),
        .D(Q),
        .Q(\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 ),
        .R(\pi_dqs_found_any_bank_reg[0]_0 [1]));
  FDRE \rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][4] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(p_22_out),
        .D(\rd_byte_data_offset_reg_n_0_[0][4] ),
        .Q(rd_data_offset_ranks_0[4]),
        .R(\pi_dqs_found_any_bank_reg[0]_0 [1]));
  FDRE \rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][5] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(p_22_out),
        .D(\rd_byte_data_offset_reg_n_0_[0][5] ),
        .Q(rd_data_offset_ranks_0[5]),
        .R(\pi_dqs_found_any_bank_reg[0]_0 [1]));
  LUT3 #(
    .INIT(8'h8A)) 
    \rank_final_loop[0].bank_final_loop[1].final_data_offset[0][11]_i_1 
       (.I0(init_dqsfound_done_r5),
        .I1(init_dqsfound_done_r1_reg_n_0),
        .I2(rd_data_offset_cal_done),
        .O(final_data_offset));
  LUT4 #(
    .INIT(16'h00D0)) 
    \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][11]_i_1 
       (.I0(rd_data_offset_cal_done),
        .I1(init_dqsfound_done_r1_reg_n_0),
        .I2(init_dqsfound_done_r5),
        .I3(init_dqsfound_done_r_reg_0),
        .O(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][11]_i_1_n_0 ));
  FDRE \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][10] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][11]_i_1_n_0 ),
        .D(\rank_final_loop[0].final_do_max_reg[0]_45 [4]),
        .Q(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11]_0 [4]),
        .R(1'b0));
  FDRE \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][11]_i_1_n_0 ),
        .D(\rank_final_loop[0].final_do_max_reg[0]_45 [5]),
        .Q(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11]_0 [5]),
        .R(1'b0));
  FDRE \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][11]_i_1_n_0 ),
        .D(\rank_final_loop[0].final_do_max_reg[0]_45 [0]),
        .Q(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11]_0 [0]),
        .R(1'b0));
  FDRE \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][7] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][11]_i_1_n_0 ),
        .D(\rank_final_loop[0].final_do_max_reg[0]_45 [1]),
        .Q(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11]_0 [1]),
        .R(1'b0));
  FDRE \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][8] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][11]_i_1_n_0 ),
        .D(\rank_final_loop[0].final_do_max_reg[0]_45 [2]),
        .Q(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11]_0 [2]),
        .R(1'b0));
  FDRE \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][9] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc[0][11]_i_1_n_0 ),
        .D(\rank_final_loop[0].final_do_max_reg[0]_45 [3]),
        .Q(\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11]_0 [3]),
        .R(1'b0));
  FDRE \rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][10] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(final_data_offset),
        .D(\rank_final_loop[0].final_do_max_reg[0]_45 [4]),
        .Q(rd_data_offset_ranks_1[4]),
        .R(\pi_dqs_found_any_bank_reg[0]_0 [1]));
  FDRE \rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][11] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(final_data_offset),
        .D(\rank_final_loop[0].final_do_max_reg[0]_45 [5]),
        .Q(rd_data_offset_ranks_1[5]),
        .R(\pi_dqs_found_any_bank_reg[0]_0 [1]));
  FDRE \rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][6] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(final_data_offset),
        .D(\rank_final_loop[0].final_do_max_reg[0]_45 [0]),
        .Q(rd_data_offset_ranks_1[0]),
        .R(\pi_dqs_found_any_bank_reg[0]_0 [1]));
  FDRE \rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][7] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(final_data_offset),
        .D(\rank_final_loop[0].final_do_max_reg[0]_45 [1]),
        .Q(rd_data_offset_ranks_1[1]),
        .R(\pi_dqs_found_any_bank_reg[0]_0 [1]));
  FDRE \rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][8] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(final_data_offset),
        .D(\rank_final_loop[0].final_do_max_reg[0]_45 [2]),
        .Q(rd_data_offset_ranks_1[2]),
        .R(\pi_dqs_found_any_bank_reg[0]_0 [1]));
  FDRE \rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(final_data_offset),
        .D(\rank_final_loop[0].final_do_max_reg[0]_45 [3]),
        .Q(\rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9]_0 ),
        .R(\pi_dqs_found_any_bank_reg[0]_0 [1]));
  (* SOFT_HLUTNM = "soft_lutpair283" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][12]_i_1 
       (.I0(\rd_byte_data_offset_reg_n_0_[0][12] ),
        .O(\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][12]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair274" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][13]_i_1 
       (.I0(\rd_byte_data_offset_reg_n_0_[0][12] ),
        .I1(\rd_byte_data_offset_reg_n_0_[0][13] ),
        .O(\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][13]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'hA9)) 
    \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][14]_i_1 
       (.I0(\rd_byte_data_offset_reg_n_0_[0][14] ),
        .I1(\rd_byte_data_offset_reg_n_0_[0][12] ),
        .I2(\rd_byte_data_offset_reg_n_0_[0][13] ),
        .O(\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][14]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair264" *) 
  LUT4 #(
    .INIT(16'hAAA9)) 
    \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][15]_i_1 
       (.I0(\rd_byte_data_offset_reg[0][15]_0 ),
        .I1(\rd_byte_data_offset_reg_n_0_[0][14] ),
        .I2(\rd_byte_data_offset_reg_n_0_[0][13] ),
        .I3(\rd_byte_data_offset_reg_n_0_[0][12] ),
        .O(\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][15]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair264" *) 
  LUT5 #(
    .INIT(32'hAAAAAAA9)) 
    \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][16]_i_1 
       (.I0(\rd_byte_data_offset_reg_n_0_[0][16] ),
        .I1(\rd_byte_data_offset_reg[0][15]_0 ),
        .I2(\rd_byte_data_offset_reg_n_0_[0][12] ),
        .I3(\rd_byte_data_offset_reg_n_0_[0][13] ),
        .I4(\rd_byte_data_offset_reg_n_0_[0][14] ),
        .O(\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][16]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAAAA9)) 
    \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][17]_i_1 
       (.I0(\rd_byte_data_offset_reg_n_0_[0][17] ),
        .I1(\rd_byte_data_offset_reg_n_0_[0][16] ),
        .I2(\rd_byte_data_offset_reg_n_0_[0][14] ),
        .I3(\rd_byte_data_offset_reg_n_0_[0][13] ),
        .I4(\rd_byte_data_offset_reg_n_0_[0][12] ),
        .I5(\rd_byte_data_offset_reg[0][15]_0 ),
        .O(\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][17]_i_1_n_0 ));
  FDRE \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][12] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(final_data_offset_mc),
        .D(\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][12]_i_1_n_0 ),
        .Q(\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17]_0 [0]),
        .R(1'b0));
  FDRE \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][13] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(final_data_offset_mc),
        .D(\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][13]_i_1_n_0 ),
        .Q(\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17]_0 [1]),
        .R(1'b0));
  FDRE \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][14] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(final_data_offset_mc),
        .D(\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][14]_i_1_n_0 ),
        .Q(\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17]_0 [2]),
        .R(1'b0));
  FDRE \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][15] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(final_data_offset_mc),
        .D(\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][15]_i_1_n_0 ),
        .Q(\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17]_0 [3]),
        .R(1'b0));
  FDRE \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][16] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(final_data_offset_mc),
        .D(\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][16]_i_1_n_0 ),
        .Q(\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17]_0 [4]),
        .R(1'b0));
  FDRE \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(final_data_offset_mc),
        .D(\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][17]_i_1_n_0 ),
        .Q(\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17]_0 [5]),
        .R(1'b0));
  FDRE \rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][12] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(p_22_out),
        .D(\rd_byte_data_offset_reg_n_0_[0][12] ),
        .Q(rd_data_offset_ranks_2[0]),
        .R(\pi_dqs_found_any_bank_reg[0]_0 [0]));
  FDRE \rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][13] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(p_22_out),
        .D(\rd_byte_data_offset_reg_n_0_[0][13] ),
        .Q(rd_data_offset_ranks_2[1]),
        .R(\pi_dqs_found_any_bank_reg[0]_0 [0]));
  FDRE \rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][14] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(p_22_out),
        .D(\rd_byte_data_offset_reg_n_0_[0][14] ),
        .Q(rd_data_offset_ranks_2[2]),
        .R(\pi_dqs_found_any_bank_reg[0]_0 [0]));
  FDRE \rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][15] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(p_22_out),
        .D(\rd_byte_data_offset_reg[0][15]_0 ),
        .Q(\rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][15]_0 ),
        .R(\pi_dqs_found_any_bank_reg[0]_0 [0]));
  FDRE \rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][16] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(p_22_out),
        .D(\rd_byte_data_offset_reg_n_0_[0][16] ),
        .Q(rd_data_offset_ranks_2[4]),
        .R(\pi_dqs_found_any_bank_reg[0]_0 [0]));
  FDRE \rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][17] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(p_22_out),
        .D(\rd_byte_data_offset_reg_n_0_[0][17] ),
        .Q(rd_data_offset_ranks_2[5]),
        .R(\pi_dqs_found_any_bank_reg[0]_0 [1]));
  (* SOFT_HLUTNM = "soft_lutpair292" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \rank_final_loop[0].final_do_index[0][0]_i_1 
       (.I0(\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ),
        .O(\rank_final_loop[0].final_do_index[0][0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair292" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rank_final_loop[0].final_do_index[0][1]_i_1 
       (.I0(\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ),
        .I1(\rank_final_loop[0].final_do_index_reg_n_0_[0][1] ),
        .O(\rank_final_loop[0].final_do_index[0][1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair291" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \rank_final_loop[0].final_do_index[0][2]_i_1 
       (.I0(\rank_final_loop[0].final_do_index_reg_n_0_[0][2] ),
        .I1(\rank_final_loop[0].final_do_index_reg_n_0_[0][1] ),
        .I2(\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ),
        .O(\rank_final_loop[0].final_do_index[0][2]_i_1_n_0 ));
  FDRE \rank_final_loop[0].final_do_index_reg[0][0] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(\rank_final_loop[0].final_do_index[0][0]_i_1_n_0 ),
        .Q(\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ),
        .R(\pi_dqs_found_any_bank_reg[0]_0 [1]));
  FDRE \rank_final_loop[0].final_do_index_reg[0][1] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(\rank_final_loop[0].final_do_index[0][1]_i_1_n_0 ),
        .Q(\rank_final_loop[0].final_do_index_reg_n_0_[0][1] ),
        .R(\pi_dqs_found_any_bank_reg[0]_0 [1]));
  FDRE \rank_final_loop[0].final_do_index_reg[0][2] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(\rank_final_loop[0].final_do_index[0][2]_i_1_n_0 ),
        .Q(\rank_final_loop[0].final_do_index_reg_n_0_[0][2] ),
        .R(\pi_dqs_found_any_bank_reg[0]_0 [1]));
  LUT6 #(
    .INIT(64'hFCFFF4F4FCFFF7F7)) 
    \rank_final_loop[0].final_do_max[0][0]_i_1 
       (.I0(rd_data_offset_ranks_1[0]),
        .I1(\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ),
        .I2(\rank_final_loop[0].final_do_index_reg_n_0_[0][2] ),
        .I3(rd_data_offset_ranks_2[0]),
        .I4(\rank_final_loop[0].final_do_index_reg_n_0_[0][1] ),
        .I5(rd_data_offset_ranks_0[0]),
        .O(\rank_final_loop[0].final_do_max[0][0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair281" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \rank_final_loop[0].final_do_max[0][1]_i_1 
       (.I0(\rank_final_loop[0].final_do_max[0][0]_i_1_n_0 ),
        .I1(\rank_final_loop[0].final_do_max[0][5]_i_8_n_0 ),
        .O(\rank_final_loop[0].final_do_max[0][1]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'h95)) 
    \rank_final_loop[0].final_do_max[0][2]_i_1 
       (.I0(\rank_final_loop[0].final_do_max[0][5]_i_9_n_0 ),
        .I1(\rank_final_loop[0].final_do_max[0][0]_i_1_n_0 ),
        .I2(\rank_final_loop[0].final_do_max[0][5]_i_8_n_0 ),
        .O(\rank_final_loop[0].final_do_max[0][2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair260" *) 
  LUT4 #(
    .INIT(16'h9555)) 
    \rank_final_loop[0].final_do_max[0][3]_i_1 
       (.I0(\rank_final_loop[0].final_do_max[0][5]_i_7_n_0 ),
        .I1(\rank_final_loop[0].final_do_max[0][5]_i_9_n_0 ),
        .I2(\rank_final_loop[0].final_do_max[0][5]_i_8_n_0 ),
        .I3(\rank_final_loop[0].final_do_max[0][0]_i_1_n_0 ),
        .O(\rank_final_loop[0].final_do_max[0][3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair260" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \rank_final_loop[0].final_do_max[0][4]_i_1 
       (.I0(\rank_final_loop[0].final_do_max[0][5]_i_9_n_0 ),
        .I1(\rank_final_loop[0].final_do_max[0][5]_i_8_n_0 ),
        .I2(\rank_final_loop[0].final_do_max[0][0]_i_1_n_0 ),
        .I3(\rank_final_loop[0].final_do_max[0][5]_i_7_n_0 ),
        .I4(\rank_final_loop[0].final_do_max[0][5]_i_3_n_0 ),
        .O(\rank_final_loop[0].final_do_max[0][4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000F4F4FF)) 
    \rank_final_loop[0].final_do_max[0][5]_i_1 
       (.I0(\rank_final_loop[0].final_do_max_reg[0]_45 [4]),
        .I1(\rank_final_loop[0].final_do_max[0][5]_i_3_n_0 ),
        .I2(\rank_final_loop[0].final_do_max[0][5]_i_4_n_0 ),
        .I3(\rank_final_loop[0].final_do_max_reg[0]_45 [5]),
        .I4(\rank_final_loop[0].final_do_max[0][5]_i_5_n_0 ),
        .I5(\rank_final_loop[0].final_do_max[0][5]_i_6_n_0 ),
        .O(\rank_final_loop[0].final_do_max[0][5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair281" *) 
  LUT4 #(
    .INIT(16'h011F)) 
    \rank_final_loop[0].final_do_max[0][5]_i_10 
       (.I0(\rank_final_loop[0].final_do_max_reg[0]_45 [0]),
        .I1(\rank_final_loop[0].final_do_max[0][0]_i_1_n_0 ),
        .I2(\rank_final_loop[0].final_do_max[0][5]_i_8_n_0 ),
        .I3(\rank_final_loop[0].final_do_max_reg[0]_45 [1]),
        .O(\rank_final_loop[0].final_do_max[0][5]_i_10_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \rank_final_loop[0].final_do_max[0][5]_i_11 
       (.I0(\rank_final_loop[0].final_do_max_reg[0]_45 [4]),
        .I1(\rank_final_loop[0].final_do_max[0][5]_i_3_n_0 ),
        .O(\rank_final_loop[0].final_do_max[0][5]_i_11_n_0 ));
  LUT6 #(
    .INIT(64'h40000000BFFFFFFF)) 
    \rank_final_loop[0].final_do_max[0][5]_i_2 
       (.I0(\rank_final_loop[0].final_do_max[0][5]_i_3_n_0 ),
        .I1(\rank_final_loop[0].final_do_max[0][5]_i_7_n_0 ),
        .I2(\rank_final_loop[0].final_do_max[0][0]_i_1_n_0 ),
        .I3(\rank_final_loop[0].final_do_max[0][5]_i_8_n_0 ),
        .I4(\rank_final_loop[0].final_do_max[0][5]_i_9_n_0 ),
        .I5(\rank_final_loop[0].final_do_max[0][5]_i_5_n_0 ),
        .O(\rank_final_loop[0].final_do_max[0][5]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h03000B0B03000808)) 
    \rank_final_loop[0].final_do_max[0][5]_i_3 
       (.I0(rd_data_offset_ranks_1[4]),
        .I1(\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ),
        .I2(\rank_final_loop[0].final_do_index_reg_n_0_[0][2] ),
        .I3(rd_data_offset_ranks_2[4]),
        .I4(\rank_final_loop[0].final_do_index_reg_n_0_[0][1] ),
        .I5(rd_data_offset_ranks_0[4]),
        .O(\rank_final_loop[0].final_do_max[0][5]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h00000071007100FF)) 
    \rank_final_loop[0].final_do_max[0][5]_i_4 
       (.I0(\rank_final_loop[0].final_do_max[0][5]_i_9_n_0 ),
        .I1(\rank_final_loop[0].final_do_max_reg[0]_45 [2]),
        .I2(\rank_final_loop[0].final_do_max[0][5]_i_10_n_0 ),
        .I3(\rank_final_loop[0].final_do_max[0][5]_i_11_n_0 ),
        .I4(\rank_final_loop[0].final_do_max_reg[0]_45 [3]),
        .I5(\rank_final_loop[0].final_do_max[0][5]_i_7_n_0 ),
        .O(\rank_final_loop[0].final_do_max[0][5]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFCFFF4F4FCFFF7F7)) 
    \rank_final_loop[0].final_do_max[0][5]_i_5 
       (.I0(rd_data_offset_ranks_1[5]),
        .I1(\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ),
        .I2(\rank_final_loop[0].final_do_index_reg_n_0_[0][2] ),
        .I3(rd_data_offset_ranks_2[5]),
        .I4(\rank_final_loop[0].final_do_index_reg_n_0_[0][1] ),
        .I5(rd_data_offset_ranks_0[5]),
        .O(\rank_final_loop[0].final_do_max[0][5]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair291" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \rank_final_loop[0].final_do_max[0][5]_i_6 
       (.I0(\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ),
        .I1(\rank_final_loop[0].final_do_index_reg_n_0_[0][2] ),
        .O(\rank_final_loop[0].final_do_max[0][5]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hFCFCDCDFFFFFDCDF)) 
    \rank_final_loop[0].final_do_max[0][5]_i_7 
       (.I0(\rank_final_loop[0].bank_final_loop[1].final_data_offset_reg[0][9]_0 ),
        .I1(\rank_final_loop[0].final_do_index_reg_n_0_[0][2] ),
        .I2(\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ),
        .I3(\rank_final_loop[0].bank_final_loop[0].final_data_offset_reg[0][3]_0 ),
        .I4(\rank_final_loop[0].final_do_index_reg_n_0_[0][1] ),
        .I5(\rank_final_loop[0].bank_final_loop[2].final_data_offset_reg[0][15]_0 ),
        .O(\rank_final_loop[0].final_do_max[0][5]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hFCFFF4F4FCFFF7F7)) 
    \rank_final_loop[0].final_do_max[0][5]_i_8 
       (.I0(rd_data_offset_ranks_1[1]),
        .I1(\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ),
        .I2(\rank_final_loop[0].final_do_index_reg_n_0_[0][2] ),
        .I3(rd_data_offset_ranks_2[1]),
        .I4(\rank_final_loop[0].final_do_index_reg_n_0_[0][1] ),
        .I5(rd_data_offset_ranks_0[1]),
        .O(\rank_final_loop[0].final_do_max[0][5]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hFCFFF4F4FCFFF7F7)) 
    \rank_final_loop[0].final_do_max[0][5]_i_9 
       (.I0(rd_data_offset_ranks_1[2]),
        .I1(\rank_final_loop[0].final_do_index_reg_n_0_[0][0] ),
        .I2(\rank_final_loop[0].final_do_index_reg_n_0_[0][2] ),
        .I3(rd_data_offset_ranks_2[2]),
        .I4(\rank_final_loop[0].final_do_index_reg_n_0_[0][1] ),
        .I5(rd_data_offset_ranks_0[2]),
        .O(\rank_final_loop[0].final_do_max[0][5]_i_9_n_0 ));
  FDRE \rank_final_loop[0].final_do_max_reg[0][0] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(\rank_final_loop[0].final_do_max[0][5]_i_1_n_0 ),
        .D(\rank_final_loop[0].final_do_max[0][0]_i_1_n_0 ),
        .Q(\rank_final_loop[0].final_do_max_reg[0]_45 [0]),
        .R(\pi_dqs_found_any_bank_reg[0]_0 [0]));
  FDRE \rank_final_loop[0].final_do_max_reg[0][1] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(\rank_final_loop[0].final_do_max[0][5]_i_1_n_0 ),
        .D(\rank_final_loop[0].final_do_max[0][1]_i_1_n_0 ),
        .Q(\rank_final_loop[0].final_do_max_reg[0]_45 [1]),
        .R(\pi_dqs_found_any_bank_reg[0]_0 [0]));
  FDRE \rank_final_loop[0].final_do_max_reg[0][2] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(\rank_final_loop[0].final_do_max[0][5]_i_1_n_0 ),
        .D(\rank_final_loop[0].final_do_max[0][2]_i_1_n_0 ),
        .Q(\rank_final_loop[0].final_do_max_reg[0]_45 [2]),
        .R(\pi_dqs_found_any_bank_reg[0]_0 [0]));
  FDRE \rank_final_loop[0].final_do_max_reg[0][3] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(\rank_final_loop[0].final_do_max[0][5]_i_1_n_0 ),
        .D(\rank_final_loop[0].final_do_max[0][3]_i_1_n_0 ),
        .Q(\rank_final_loop[0].final_do_max_reg[0]_45 [3]),
        .R(\pi_dqs_found_any_bank_reg[0]_0 [0]));
  FDRE \rank_final_loop[0].final_do_max_reg[0][4] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(\rank_final_loop[0].final_do_max[0][5]_i_1_n_0 ),
        .D(\rank_final_loop[0].final_do_max[0][4]_i_1_n_0 ),
        .Q(\rank_final_loop[0].final_do_max_reg[0]_45 [4]),
        .R(\pi_dqs_found_any_bank_reg[0]_0 [0]));
  FDRE \rank_final_loop[0].final_do_max_reg[0][5] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(\rank_final_loop[0].final_do_max[0][5]_i_1_n_0 ),
        .D(\rank_final_loop[0].final_do_max[0][5]_i_2_n_0 ),
        .Q(\rank_final_loop[0].final_do_max_reg[0]_45 [5]),
        .R(\pi_dqs_found_any_bank_reg[0]_0 [0]));
  (* SOFT_HLUTNM = "soft_lutpair254" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \rd_byte_data_offset[0][10]_i_1 
       (.I0(\rd_byte_data_offset_reg_n_0_[0][10] ),
        .I1(\rd_byte_data_offset_reg[0][9]_0 ),
        .I2(\rd_byte_data_offset_reg_n_0_[0][8] ),
        .I3(\rd_byte_data_offset_reg_n_0_[0][7] ),
        .I4(\rd_byte_data_offset_reg_n_0_[0][6] ),
        .O(p_1_in[4]));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAFFAE)) 
    \rd_byte_data_offset[0][11]_i_1 
       (.I0(init_dqsfound_done_r_reg_0),
        .I1(rank_done_r1),
        .I2(rd_data_offset_cal_done),
        .I3(\rd_byte_data_offset[0][11]_i_4_n_0 ),
        .I4(\rnk_cnt_r_reg_n_0_[0] ),
        .I5(\rnk_cnt_r_reg_n_0_[1] ),
        .O(\rd_byte_data_offset[0][11]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \rd_byte_data_offset[0][11]_i_2 
       (.I0(\rd_byte_data_offset[0][11]_i_4_n_0 ),
        .I1(rank_done_r1),
        .I2(pi_dqs_found_all_bank[1]),
        .I3(rd_data_offset_cal_done),
        .I4(fine_adjust_reg_0),
        .I5(\rd_byte_data_offset[0][11]_i_5_n_0 ),
        .O(\rd_byte_data_offset[0][11]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAAAAAA)) 
    \rd_byte_data_offset[0][11]_i_3 
       (.I0(\rd_byte_data_offset_reg_n_0_[0][11] ),
        .I1(\rd_byte_data_offset_reg_n_0_[0][6] ),
        .I2(\rd_byte_data_offset_reg_n_0_[0][7] ),
        .I3(\rd_byte_data_offset_reg_n_0_[0][8] ),
        .I4(\rd_byte_data_offset_reg[0][9]_0 ),
        .I5(\rd_byte_data_offset_reg_n_0_[0][10] ),
        .O(p_1_in[5]));
  LUT6 #(
    .INIT(64'hFFFFFEEEAAAAAAAA)) 
    \rd_byte_data_offset[0][11]_i_4 
       (.I0(\rd_byte_data_offset_reg_n_0_[0][11] ),
        .I1(\rd_byte_data_offset_reg[0][9]_0 ),
        .I2(\rd_byte_data_offset_reg_n_0_[0][6] ),
        .I3(\rd_byte_data_offset_reg_n_0_[0][7] ),
        .I4(\rd_byte_data_offset_reg_n_0_[0][8] ),
        .I5(\rd_byte_data_offset_reg_n_0_[0][10] ),
        .O(\rd_byte_data_offset[0][11]_i_4_n_0 ));
  LUT4 #(
    .INIT(16'hFDFF)) 
    \rd_byte_data_offset[0][11]_i_5 
       (.I0(\FSM_sequential_fine_adj_state_r[0]_i_6_n_0 ),
        .I1(\rnk_cnt_r_reg_n_0_[0] ),
        .I2(\rnk_cnt_r_reg_n_0_[1] ),
        .I3(dqs_found_start_r),
        .O(\rd_byte_data_offset[0][11]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair275" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rd_byte_data_offset[0][13]_i_1 
       (.I0(\rd_byte_data_offset_reg_n_0_[0][13] ),
        .I1(\rd_byte_data_offset_reg_n_0_[0][12] ),
        .O(\rd_byte_data_offset[0][13]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair283" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \rd_byte_data_offset[0][14]_i_1 
       (.I0(\rd_byte_data_offset_reg_n_0_[0][14] ),
        .I1(\rd_byte_data_offset_reg_n_0_[0][12] ),
        .I2(\rd_byte_data_offset_reg_n_0_[0][13] ),
        .O(p_1_in__0[2]));
  (* SOFT_HLUTNM = "soft_lutpair266" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \rd_byte_data_offset[0][15]_i_1 
       (.I0(\rd_byte_data_offset_reg[0][15]_0 ),
        .I1(\rd_byte_data_offset_reg_n_0_[0][13] ),
        .I2(\rd_byte_data_offset_reg_n_0_[0][12] ),
        .I3(\rd_byte_data_offset_reg_n_0_[0][14] ),
        .O(p_1_in__0[3]));
  (* SOFT_HLUTNM = "soft_lutpair266" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \rd_byte_data_offset[0][16]_i_1 
       (.I0(\rd_byte_data_offset_reg_n_0_[0][16] ),
        .I1(\rd_byte_data_offset_reg[0][15]_0 ),
        .I2(\rd_byte_data_offset_reg_n_0_[0][14] ),
        .I3(\rd_byte_data_offset_reg_n_0_[0][12] ),
        .I4(\rd_byte_data_offset_reg_n_0_[0][13] ),
        .O(p_1_in__0[4]));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAFFAE)) 
    \rd_byte_data_offset[0][17]_i_1 
       (.I0(init_dqsfound_done_r_reg_0),
        .I1(rank_done_r1),
        .I2(rd_data_offset_cal_done),
        .I3(\rd_byte_data_offset[0][17]_i_4_n_0 ),
        .I4(\rnk_cnt_r_reg_n_0_[0] ),
        .I5(\rnk_cnt_r_reg_n_0_[1] ),
        .O(\rd_byte_data_offset[0][17]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \rd_byte_data_offset[0][17]_i_2 
       (.I0(\rd_byte_data_offset[0][17]_i_4_n_0 ),
        .I1(rank_done_r1),
        .I2(pi_dqs_found_all_bank[2]),
        .I3(rd_data_offset_cal_done),
        .I4(fine_adjust_reg_0),
        .I5(\rd_byte_data_offset[0][11]_i_5_n_0 ),
        .O(\rd_byte_data_offset[0][17]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAAAAAA)) 
    \rd_byte_data_offset[0][17]_i_3 
       (.I0(\rd_byte_data_offset_reg_n_0_[0][17] ),
        .I1(\rd_byte_data_offset_reg_n_0_[0][13] ),
        .I2(\rd_byte_data_offset_reg_n_0_[0][12] ),
        .I3(\rd_byte_data_offset_reg_n_0_[0][14] ),
        .I4(\rd_byte_data_offset_reg[0][15]_0 ),
        .I5(\rd_byte_data_offset_reg_n_0_[0][16] ),
        .O(p_1_in__0[5]));
  LUT6 #(
    .INIT(64'hFFFFFEEEAAAAAAAA)) 
    \rd_byte_data_offset[0][17]_i_4 
       (.I0(\rd_byte_data_offset_reg_n_0_[0][17] ),
        .I1(\rd_byte_data_offset_reg[0][15]_0 ),
        .I2(\rd_byte_data_offset_reg_n_0_[0][13] ),
        .I3(\rd_byte_data_offset_reg_n_0_[0][12] ),
        .I4(\rd_byte_data_offset_reg_n_0_[0][14] ),
        .I5(\rd_byte_data_offset_reg_n_0_[0][16] ),
        .O(\rd_byte_data_offset[0][17]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair278" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rd_byte_data_offset[0][1]_i_1 
       (.I0(\rd_byte_data_offset_reg_n_0_[0][1] ),
        .I1(\rd_byte_data_offset_reg_n_0_[0][0] ),
        .O(\rd_byte_data_offset[0][1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair282" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \rd_byte_data_offset[0][2]_i_1 
       (.I0(\rd_byte_data_offset_reg_n_0_[0][2] ),
        .I1(\rd_byte_data_offset_reg_n_0_[0][0] ),
        .I2(\rd_byte_data_offset_reg_n_0_[0][1] ),
        .O(p_1_in__1[2]));
  (* SOFT_HLUTNM = "soft_lutpair259" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \rd_byte_data_offset[0][3]_i_1 
       (.I0(Q),
        .I1(\rd_byte_data_offset_reg_n_0_[0][1] ),
        .I2(\rd_byte_data_offset_reg_n_0_[0][0] ),
        .I3(\rd_byte_data_offset_reg_n_0_[0][2] ),
        .O(p_1_in__1[3]));
  (* SOFT_HLUTNM = "soft_lutpair259" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \rd_byte_data_offset[0][4]_i_1 
       (.I0(\rd_byte_data_offset_reg_n_0_[0][4] ),
        .I1(Q),
        .I2(\rd_byte_data_offset_reg_n_0_[0][2] ),
        .I3(\rd_byte_data_offset_reg_n_0_[0][0] ),
        .I4(\rd_byte_data_offset_reg_n_0_[0][1] ),
        .O(p_1_in__1[4]));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAFFAE)) 
    \rd_byte_data_offset[0][5]_i_1 
       (.I0(init_dqsfound_done_r_reg_0),
        .I1(rank_done_r1),
        .I2(rd_data_offset_cal_done),
        .I3(\rd_byte_data_offset[0][5]_i_4_n_0 ),
        .I4(\rnk_cnt_r_reg_n_0_[0] ),
        .I5(\rnk_cnt_r_reg_n_0_[1] ),
        .O(\rd_byte_data_offset[0][5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \rd_byte_data_offset[0][5]_i_2 
       (.I0(\rd_byte_data_offset[0][5]_i_4_n_0 ),
        .I1(rank_done_r1),
        .I2(pi_dqs_found_all_bank[0]),
        .I3(rd_data_offset_cal_done),
        .I4(fine_adjust_reg_0),
        .I5(\rd_byte_data_offset[0][11]_i_5_n_0 ),
        .O(rd_byte_data_offset));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAAAAAA)) 
    \rd_byte_data_offset[0][5]_i_3 
       (.I0(\rd_byte_data_offset_reg_n_0_[0][5] ),
        .I1(\rd_byte_data_offset_reg_n_0_[0][1] ),
        .I2(\rd_byte_data_offset_reg_n_0_[0][0] ),
        .I3(\rd_byte_data_offset_reg_n_0_[0][2] ),
        .I4(Q),
        .I5(\rd_byte_data_offset_reg_n_0_[0][4] ),
        .O(p_1_in__1[5]));
  LUT6 #(
    .INIT(64'hFFFFFEEEAAAAAAAA)) 
    \rd_byte_data_offset[0][5]_i_4 
       (.I0(\rd_byte_data_offset_reg_n_0_[0][5] ),
        .I1(Q),
        .I2(\rd_byte_data_offset_reg_n_0_[0][1] ),
        .I3(\rd_byte_data_offset_reg_n_0_[0][0] ),
        .I4(\rd_byte_data_offset_reg_n_0_[0][2] ),
        .I5(\rd_byte_data_offset_reg_n_0_[0][4] ),
        .O(\rd_byte_data_offset[0][5]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \rd_byte_data_offset[0][6]_i_1 
       (.I0(\rd_byte_data_offset_reg_n_0_[0][6] ),
        .O(p_1_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair272" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rd_byte_data_offset[0][7]_i_1 
       (.I0(\rd_byte_data_offset_reg_n_0_[0][6] ),
        .I1(\rd_byte_data_offset_reg_n_0_[0][7] ),
        .O(p_1_in[1]));
  LUT3 #(
    .INIT(8'h6A)) 
    \rd_byte_data_offset[0][8]_i_1 
       (.I0(\rd_byte_data_offset_reg_n_0_[0][8] ),
        .I1(\rd_byte_data_offset_reg_n_0_[0][7] ),
        .I2(\rd_byte_data_offset_reg_n_0_[0][6] ),
        .O(p_1_in[2]));
  (* SOFT_HLUTNM = "soft_lutpair254" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \rd_byte_data_offset[0][9]_i_1 
       (.I0(\rd_byte_data_offset_reg[0][9]_0 ),
        .I1(\rd_byte_data_offset_reg_n_0_[0][6] ),
        .I2(\rd_byte_data_offset_reg_n_0_[0][7] ),
        .I3(\rd_byte_data_offset_reg_n_0_[0][8] ),
        .O(p_1_in[3]));
  FDRE \rd_byte_data_offset_reg[0][0] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(rd_byte_data_offset),
        .D(\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc[0][0]_i_1_n_0 ),
        .Q(\rd_byte_data_offset_reg_n_0_[0][0] ),
        .R(\rd_byte_data_offset[0][5]_i_1_n_0 ));
  FDRE \rd_byte_data_offset_reg[0][10] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(\rd_byte_data_offset[0][11]_i_2_n_0 ),
        .D(p_1_in[4]),
        .Q(\rd_byte_data_offset_reg_n_0_[0][10] ),
        .R(\rd_byte_data_offset[0][11]_i_1_n_0 ));
  FDRE \rd_byte_data_offset_reg[0][11] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(\rd_byte_data_offset[0][11]_i_2_n_0 ),
        .D(p_1_in[5]),
        .Q(\rd_byte_data_offset_reg_n_0_[0][11] ),
        .R(\rd_byte_data_offset[0][11]_i_1_n_0 ));
  FDRE \rd_byte_data_offset_reg[0][12] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(\rd_byte_data_offset[0][17]_i_2_n_0 ),
        .D(\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc[0][12]_i_1_n_0 ),
        .Q(\rd_byte_data_offset_reg_n_0_[0][12] ),
        .R(\rd_byte_data_offset[0][17]_i_1_n_0 ));
  FDRE \rd_byte_data_offset_reg[0][13] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(\rd_byte_data_offset[0][17]_i_2_n_0 ),
        .D(\rd_byte_data_offset[0][13]_i_1_n_0 ),
        .Q(\rd_byte_data_offset_reg_n_0_[0][13] ),
        .R(\rd_byte_data_offset[0][17]_i_1_n_0 ));
  FDSE \rd_byte_data_offset_reg[0][14] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(\rd_byte_data_offset[0][17]_i_2_n_0 ),
        .D(p_1_in__0[2]),
        .Q(\rd_byte_data_offset_reg_n_0_[0][14] ),
        .S(\rd_byte_data_offset[0][17]_i_1_n_0 ));
  FDRE \rd_byte_data_offset_reg[0][15] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(\rd_byte_data_offset[0][17]_i_2_n_0 ),
        .D(p_1_in__0[3]),
        .Q(\rd_byte_data_offset_reg[0][15]_0 ),
        .R(\rd_byte_data_offset[0][17]_i_1_n_0 ));
  FDRE \rd_byte_data_offset_reg[0][16] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(\rd_byte_data_offset[0][17]_i_2_n_0 ),
        .D(p_1_in__0[4]),
        .Q(\rd_byte_data_offset_reg_n_0_[0][16] ),
        .R(\rd_byte_data_offset[0][17]_i_1_n_0 ));
  FDRE \rd_byte_data_offset_reg[0][17] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(\rd_byte_data_offset[0][17]_i_2_n_0 ),
        .D(p_1_in__0[5]),
        .Q(\rd_byte_data_offset_reg_n_0_[0][17] ),
        .R(\rd_byte_data_offset[0][17]_i_1_n_0 ));
  FDRE \rd_byte_data_offset_reg[0][1] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(rd_byte_data_offset),
        .D(\rd_byte_data_offset[0][1]_i_1_n_0 ),
        .Q(\rd_byte_data_offset_reg_n_0_[0][1] ),
        .R(\rd_byte_data_offset[0][5]_i_1_n_0 ));
  FDSE \rd_byte_data_offset_reg[0][2] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(rd_byte_data_offset),
        .D(p_1_in__1[2]),
        .Q(\rd_byte_data_offset_reg_n_0_[0][2] ),
        .S(\rd_byte_data_offset[0][5]_i_1_n_0 ));
  FDRE \rd_byte_data_offset_reg[0][3] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(rd_byte_data_offset),
        .D(p_1_in__1[3]),
        .Q(Q),
        .R(\rd_byte_data_offset[0][5]_i_1_n_0 ));
  FDRE \rd_byte_data_offset_reg[0][4] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(rd_byte_data_offset),
        .D(p_1_in__1[4]),
        .Q(\rd_byte_data_offset_reg_n_0_[0][4] ),
        .R(\rd_byte_data_offset[0][5]_i_1_n_0 ));
  FDRE \rd_byte_data_offset_reg[0][5] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(rd_byte_data_offset),
        .D(p_1_in__1[5]),
        .Q(\rd_byte_data_offset_reg_n_0_[0][5] ),
        .R(\rd_byte_data_offset[0][5]_i_1_n_0 ));
  FDRE \rd_byte_data_offset_reg[0][6] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(\rd_byte_data_offset[0][11]_i_2_n_0 ),
        .D(p_1_in[0]),
        .Q(\rd_byte_data_offset_reg_n_0_[0][6] ),
        .R(\rd_byte_data_offset[0][11]_i_1_n_0 ));
  FDRE \rd_byte_data_offset_reg[0][7] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(\rd_byte_data_offset[0][11]_i_2_n_0 ),
        .D(p_1_in[1]),
        .Q(\rd_byte_data_offset_reg_n_0_[0][7] ),
        .R(\rd_byte_data_offset[0][11]_i_1_n_0 ));
  FDSE \rd_byte_data_offset_reg[0][8] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(\rd_byte_data_offset[0][11]_i_2_n_0 ),
        .D(p_1_in[2]),
        .Q(\rd_byte_data_offset_reg_n_0_[0][8] ),
        .S(\rd_byte_data_offset[0][11]_i_1_n_0 ));
  FDRE \rd_byte_data_offset_reg[0][9] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(\rd_byte_data_offset[0][11]_i_2_n_0 ),
        .D(p_1_in[3]),
        .Q(\rd_byte_data_offset_reg[0][9]_0 ),
        .R(\rd_byte_data_offset[0][11]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair270" *) 
  LUT3 #(
    .INIT(8'hD2)) 
    \rnk_cnt_r[0]_i_1 
       (.I0(pi_dqs_found_rank_done),
        .I1(rd_data_offset_cal_done),
        .I2(\rnk_cnt_r_reg_n_0_[0] ),
        .O(\rnk_cnt_r[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair270" *) 
  LUT4 #(
    .INIT(16'hF708)) 
    \rnk_cnt_r[1]_i_1 
       (.I0(\rnk_cnt_r_reg_n_0_[0] ),
        .I1(pi_dqs_found_rank_done),
        .I2(rd_data_offset_cal_done),
        .I3(\rnk_cnt_r_reg_n_0_[1] ),
        .O(\rnk_cnt_r[1]_i_1_n_0 ));
  FDRE \rnk_cnt_r_reg[0] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(\rnk_cnt_r[0]_i_1_n_0 ),
        .Q(\rnk_cnt_r_reg_n_0_[0] ),
        .R(\pi_dqs_found_any_bank_reg[0]_0 [1]));
  FDRE \rnk_cnt_r_reg[1] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(\rnk_cnt_r[1]_i_1_n_0 ),
        .Q(\rnk_cnt_r_reg_n_0_[1] ),
        .R(\pi_dqs_found_any_bank_reg[0]_0 [1]));
  LUT6 #(
    .INIT(64'h80AAFFFF80AA0000)) 
    rst_dqs_find_i_1
       (.I0(rst_dqs_find_i_2_n_0),
        .I1(fine_adj_state_r[1]),
        .I2(prech_done),
        .I3(fine_adj_state_r[0]),
        .I4(rst_dqs_find_i_3_n_0),
        .I5(rst_dqs_find),
        .O(rst_dqs_find_i_1_n_0));
  LUT6 #(
    .INIT(64'hFEEEFEFFEEEEEEEE)) 
    rst_dqs_find_i_2
       (.I0(rst_dqs_find_i_4_n_0),
        .I1(fine_adj_state_r[2]),
        .I2(\FSM_sequential_fine_adj_state_r[1]_i_14_n_0 ),
        .I3(\FSM_sequential_fine_adj_state_r[1]_i_5_n_0 ),
        .I4(\first_fail_taps[5]_i_5_n_0 ),
        .I5(fine_adj_state_r[3]),
        .O(rst_dqs_find_i_2_n_0));
  LUT6 #(
    .INIT(64'h008000800A8A0282)) 
    rst_dqs_find_i_3
       (.I0(rst_dqs_find_i_5_n_0),
        .I1(fine_adj_state_r[1]),
        .I2(fine_adj_state_r[3]),
        .I3(rst_dqs_find_i_6_n_0),
        .I4(p_1_in30_in),
        .I5(fine_adj_state_r[2]),
        .O(rst_dqs_find_i_3_n_0));
  LUT2 #(
    .INIT(4'h2)) 
    rst_dqs_find_i_4
       (.I0(init_dqsfound_done_r5),
        .I1(fine_adj_state_r[1]),
        .O(rst_dqs_find_i_4_n_0));
  LUT6 #(
    .INIT(64'h88FFFFF88888FFF8)) 
    rst_dqs_find_i_5
       (.I0(prech_done),
        .I1(fine_adj_state_r[2]),
        .I2(init_dqsfound_done_r5),
        .I3(fine_adj_state_r[1]),
        .I4(fine_adj_state_r[0]),
        .I5(\FSM_sequential_fine_adj_state_r[3]_i_6_n_0 ),
        .O(rst_dqs_find_i_5_n_0));
  LUT6 #(
    .INIT(64'h00000000FFFFFFAB)) 
    rst_dqs_find_i_6
       (.I0(\dec_cnt[5]_i_6_n_0 ),
        .I1(first_fail_detect_reg_n_0),
        .I2(\FSM_sequential_fine_adj_state_r[1]_i_14_n_0 ),
        .I3(\FSM_sequential_fine_adj_state_r[1]_i_5_n_0 ),
        .I4(\first_fail_taps[5]_i_5_n_0 ),
        .I5(rst_dqs_find_i_7_n_0),
        .O(rst_dqs_find_i_6_n_0));
  LUT5 #(
    .INIT(32'hEAAAAAAA)) 
    rst_dqs_find_i_7
       (.I0(fine_adj_state_r[2]),
        .I1(p_1_in30_in),
        .I2(detect_pi_found_dqs),
        .I3(\FSM_sequential_fine_adj_state_r[1]_i_14_n_0 ),
        .I4(\FSM_sequential_fine_adj_state_r[2]_i_3_n_0 ),
        .O(rst_dqs_find_i_7_n_0));
  FDRE rst_dqs_find_r1_reg
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(rst_dqs_find),
        .Q(rst_dqs_find_r1),
        .R(1'b0));
  FDRE rst_dqs_find_r2_reg
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(rst_dqs_find_r1),
        .Q(rst_dqs_find_r2),
        .R(1'b0));
  FDRE rst_dqs_find_reg
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(1'b1),
        .D(rst_dqs_find_i_1_n_0),
        .Q(rst_dqs_find),
        .R(\pi_dqs_found_any_bank_reg[0]_0 [1]));
  (* SOFT_HLUTNM = "soft_lutpair255" *) 
  LUT4 #(
    .INIT(16'h0080)) 
    \stable_pass_cnt[0]_i_1 
       (.I0(pi_dqs_found_all_bank[2]),
        .I1(pi_dqs_found_all_bank[1]),
        .I2(pi_dqs_found_all_bank[0]),
        .I3(\stable_pass_cnt_reg_n_0_[0] ),
        .O(p_0_in__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair255" *) 
  LUT5 #(
    .INIT(32'h00808000)) 
    \stable_pass_cnt[1]_i_1 
       (.I0(pi_dqs_found_all_bank[2]),
        .I1(pi_dqs_found_all_bank[1]),
        .I2(pi_dqs_found_all_bank[0]),
        .I3(stable_pass_cnt_reg[1]),
        .I4(\stable_pass_cnt_reg_n_0_[0] ),
        .O(p_0_in__0[1]));
  (* SOFT_HLUTNM = "soft_lutpair256" *) 
  LUT4 #(
    .INIT(16'h2A80)) 
    \stable_pass_cnt[2]_i_1 
       (.I0(\FSM_sequential_fine_adj_state_r[1]_i_5_n_0 ),
        .I1(\stable_pass_cnt_reg_n_0_[0] ),
        .I2(stable_pass_cnt_reg[1]),
        .I3(stable_pass_cnt_reg[2]),
        .O(p_0_in__0[2]));
  (* SOFT_HLUTNM = "soft_lutpair256" *) 
  LUT5 #(
    .INIT(32'h2AAA8000)) 
    \stable_pass_cnt[3]_i_1 
       (.I0(\FSM_sequential_fine_adj_state_r[1]_i_5_n_0 ),
        .I1(stable_pass_cnt_reg[1]),
        .I2(\stable_pass_cnt_reg_n_0_[0] ),
        .I3(stable_pass_cnt_reg[2]),
        .I4(stable_pass_cnt_reg[3]),
        .O(p_0_in__0[3]));
  LUT6 #(
    .INIT(64'h2AAAAAAA80000000)) 
    \stable_pass_cnt[4]_i_1 
       (.I0(\FSM_sequential_fine_adj_state_r[1]_i_5_n_0 ),
        .I1(stable_pass_cnt_reg[1]),
        .I2(\stable_pass_cnt_reg_n_0_[0] ),
        .I3(stable_pass_cnt_reg[3]),
        .I4(stable_pass_cnt_reg[2]),
        .I5(stable_pass_cnt_reg[4]),
        .O(p_0_in__0[4]));
  LUT5 #(
    .INIT(32'h00000800)) 
    \stable_pass_cnt[5]_i_1 
       (.I0(detect_pi_found_dqs),
        .I1(fine_adj_state_r[3]),
        .I2(fine_adj_state_r[2]),
        .I3(fine_adj_state_r[1]),
        .I4(fine_adj_state_r[0]),
        .O(stable_pass_cnt));
  LUT6 #(
    .INIT(64'h2AAAAAAA80000000)) 
    \stable_pass_cnt[5]_i_2 
       (.I0(\FSM_sequential_fine_adj_state_r[1]_i_5_n_0 ),
        .I1(stable_pass_cnt_reg[2]),
        .I2(stable_pass_cnt_reg[3]),
        .I3(\stable_pass_cnt[5]_i_3_n_0 ),
        .I4(stable_pass_cnt_reg[4]),
        .I5(stable_pass_cnt_reg[5]),
        .O(p_0_in__0[5]));
  LUT2 #(
    .INIT(4'h8)) 
    \stable_pass_cnt[5]_i_3 
       (.I0(\stable_pass_cnt_reg_n_0_[0] ),
        .I1(stable_pass_cnt_reg[1]),
        .O(\stable_pass_cnt[5]_i_3_n_0 ));
  FDRE \stable_pass_cnt_reg[0] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(stable_pass_cnt),
        .D(p_0_in__0[0]),
        .Q(\stable_pass_cnt_reg_n_0_[0] ),
        .R(\stable_pass_cnt_reg[0]_0 ));
  FDRE \stable_pass_cnt_reg[1] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(stable_pass_cnt),
        .D(p_0_in__0[1]),
        .Q(stable_pass_cnt_reg[1]),
        .R(\stable_pass_cnt_reg[0]_0 ));
  FDRE \stable_pass_cnt_reg[2] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(stable_pass_cnt),
        .D(p_0_in__0[2]),
        .Q(stable_pass_cnt_reg[2]),
        .R(\stable_pass_cnt_reg[0]_0 ));
  FDRE \stable_pass_cnt_reg[3] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(stable_pass_cnt),
        .D(p_0_in__0[3]),
        .Q(stable_pass_cnt_reg[3]),
        .R(\stable_pass_cnt_reg[0]_0 ));
  FDRE \stable_pass_cnt_reg[4] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(stable_pass_cnt),
        .D(p_0_in__0[4]),
        .Q(stable_pass_cnt_reg[4]),
        .R(\stable_pass_cnt_reg[0]_0 ));
  FDRE \stable_pass_cnt_reg[5] 
       (.C(init_dqsfound_done_r5_reg_0),
        .CE(stable_pass_cnt),
        .D(p_0_in__0[5]),
        .Q(stable_pass_cnt_reg[5]),
        .R(\stable_pass_cnt_reg[0]_0 ));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_phy_init" *) 
module mig_mig_7series_v4_2_ddr_phy_init
   (prech_done,
    wrlvl_done_r1,
    prbs_rdlvl_done_pulse_reg_0,
    prech_req_posedge_r_reg_0,
    pi_calib_done,
    complex_ocal_reset_rd_addr,
    wl_sm_start,
    wrcal_rd_wait,
    wrcal_sanity_chk,
    detect_pi_found_dqs,
    calib_complete,
    pi_dqs_found_done_r1,
    complex_act_start,
    \one_rank.stg1_wr_done_reg_0 ,
    wrlvl_final_if_rst,
    wr_lvl_start_reg_0,
    rdlvl_stg1_start_reg_0,
    phy_write_calib,
    phy_read_calib,
    first_rdlvl_pat_r,
    first_wrcal_pat_r,
    D,
    Q,
    d_in,
    phy_dout,
    init_complete_r1_timing_reg_0,
    D6,
    D8,
    \gen_no_mirror.div_clk_loop[0].phy_address_reg[2]_0 ,
    D5,
    D4,
    D7,
    D9,
    D1,
    \gen_no_mirror.div_clk_loop[0].phy_address_reg[8]_0 ,
    \gen_no_mirror.div_clk_loop[0].phy_address_reg[9]_0 ,
    D3,
    \gen_no_mirror.div_clk_loop[0].phy_bank_reg[0]_0 ,
    \gen_no_mirror.div_clk_loop[0].phy_bank_reg[1]_0 ,
    \write_buffer.wr_buf_out_data_reg[448] ,
    D2,
    \write_buffer.wr_buf_out_data_reg[450] ,
    \write_buffer.wr_buf_out_data_reg[451] ,
    \write_buffer.wr_buf_out_data_reg[452] ,
    \write_buffer.wr_buf_out_data_reg[453] ,
    \write_buffer.wr_buf_out_data_reg[454] ,
    \write_buffer.wr_buf_out_data_reg[455] ,
    \write_buffer.wr_buf_out_data_reg[456] ,
    \write_buffer.wr_buf_out_data_reg[457] ,
    \write_buffer.wr_buf_out_data_reg[458] ,
    \write_buffer.wr_buf_out_data_reg[459] ,
    \write_buffer.wr_buf_out_data_reg[460] ,
    \write_buffer.wr_buf_out_data_reg[461] ,
    \write_buffer.wr_buf_out_data_reg[462] ,
    \write_buffer.wr_buf_out_data_reg[463] ,
    \write_buffer.wr_buf_out_data_reg[464] ,
    \write_buffer.wr_buf_out_data_reg[465] ,
    \write_buffer.wr_buf_out_data_reg[466] ,
    \write_buffer.wr_buf_out_data_reg[467] ,
    \write_buffer.wr_buf_out_data_reg[468] ,
    \write_buffer.wr_buf_out_data_reg[469] ,
    \write_buffer.wr_buf_out_data_reg[470] ,
    \write_buffer.wr_buf_out_data_reg[471] ,
    \write_buffer.wr_buf_out_data_reg[472] ,
    \write_buffer.wr_buf_out_data_reg[473] ,
    \write_buffer.wr_buf_out_data_reg[474] ,
    \write_buffer.wr_buf_out_data_reg[475] ,
    \write_buffer.wr_buf_out_data_reg[476] ,
    \write_buffer.wr_buf_out_data_reg[477] ,
    \write_buffer.wr_buf_out_data_reg[478] ,
    \write_buffer.wr_buf_out_data_reg[479] ,
    \write_buffer.wr_buf_out_data_reg[480] ,
    \write_buffer.wr_buf_out_data_reg[481] ,
    \write_buffer.wr_buf_out_data_reg[482] ,
    \write_buffer.wr_buf_out_data_reg[483] ,
    \write_buffer.wr_buf_out_data_reg[484] ,
    \write_buffer.wr_buf_out_data_reg[485] ,
    \write_buffer.wr_buf_out_data_reg[486] ,
    \write_buffer.wr_buf_out_data_reg[487] ,
    \write_buffer.wr_buf_out_data_reg[488] ,
    \write_buffer.wr_buf_out_data_reg[489] ,
    \write_buffer.wr_buf_out_data_reg[490] ,
    \write_buffer.wr_buf_out_data_reg[491] ,
    \write_buffer.wr_buf_out_data_reg[492] ,
    \write_buffer.wr_buf_out_data_reg[493] ,
    \write_buffer.wr_buf_out_data_reg[494] ,
    \write_buffer.wr_buf_out_data_reg[495] ,
    \write_buffer.wr_buf_out_data_reg[496] ,
    \write_buffer.wr_buf_out_data_reg[497] ,
    \write_buffer.wr_buf_out_data_reg[498] ,
    \write_buffer.wr_buf_out_data_reg[499] ,
    \write_buffer.wr_buf_out_data_reg[500] ,
    \write_buffer.wr_buf_out_data_reg[501] ,
    \write_buffer.wr_buf_out_data_reg[502] ,
    \write_buffer.wr_buf_out_data_reg[503] ,
    \write_buffer.wr_buf_out_data_reg[504] ,
    \write_buffer.wr_buf_out_data_reg[505] ,
    \write_buffer.wr_buf_out_data_reg[506] ,
    \write_buffer.wr_buf_out_data_reg[507] ,
    \write_buffer.wr_buf_out_data_reg[508] ,
    \write_buffer.wr_buf_out_data_reg[509] ,
    \write_buffer.wr_buf_out_data_reg[510] ,
    \write_buffer.wr_buf_out_data_reg[511] ,
    \cmd_pipe_plus.mc_ras_n_reg[1] ,
    \cmd_pipe_plus.mc_cas_n_reg[1] ,
    \cmd_pipe_plus.mc_odt_reg[0] ,
    \cmd_pipe_plus.mc_cke_reg[3] ,
    \cmd_pipe_plus.mc_we_n_reg[1] ,
    app_rd_data_valid,
    \read_fifo.tail_r_reg[0] ,
    wl_sm_start_reg_0,
    mux_rd_valid_r0,
    prbs_rdlvl_start_reg_0,
    prbs_rdlvl_start_reg_1,
    stg1_wr_done,
    \init_state_r_reg[4]_0 ,
    \init_state_r_reg[4]_1 ,
    rdlvl_stg1_start_int_reg_0,
    E,
    prbs_rdlvl_done_reg,
    \rd_addr_reg[1] ,
    prbs_rdlvl_done_reg_0,
    SR,
    phy_data_wr_en,
    phy_cmd_wr_en,
    mux_reset_n,
    \cmd_pipe_plus.mc_cke_reg[3]_0 ,
    wrcal_start_reg_0,
    pi_dqs_found_start_reg_0,
    mpr_rdlvl_start_reg_0,
    \calib_seq_reg[1]_0 ,
    \cmd_pipe_plus.mc_data_offset_1_reg[5] ,
    \cmd_pipe_plus.mc_data_offset_2_reg[5] ,
    \write_buffer.wr_buf_out_data_reg[455]_0 ,
    \write_buffer.wr_buf_out_data_reg[463]_0 ,
    \write_buffer.wr_buf_out_data_reg[471]_0 ,
    \write_buffer.wr_buf_out_data_reg[479]_0 ,
    \write_buffer.wr_buf_out_data_reg[487]_0 ,
    \write_buffer.wr_buf_out_data_reg[495]_0 ,
    \write_buffer.wr_buf_out_data_reg[503]_0 ,
    \write_buffer.wr_buf_out_data_reg[511]_0 ,
    \rdlvl_start_dly0_r_reg[14]_0 ,
    pi_phase_locked_all_r1_reg_0,
    \victim_sel_reg[0]_0 ,
    wrlvl_done_r_reg_0,
    prbs_last_byte_done,
    wrlvl_rank_done,
    prbs_rdlvl_done_pulse0,
    \en_cnt_div4.enable_wrlvl_cnt_reg[2]_0 ,
    reset_rd_addr0,
    prech_req,
    wrcal_resume_w,
    complex_oclkdelay_calib_done_r1_reg_0,
    rdlvl_last_byte_done,
    pi_dqs_found_done_r1_reg_0,
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 ,
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[510]_0 ,
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[506]_0 ,
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[125]_0 ,
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[121]_0 ,
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[61]_0 ,
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57]_0 ,
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[508]_0 ,
    prbs_out,
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187]_0 ,
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[445]_0 ,
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[441]_0 ,
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[380]_0 ,
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[376]_0 ,
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[319]_0 ,
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[315]_0 ,
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[255]_0 ,
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[253]_0 ,
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[251]_0 ,
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[249]_0 ,
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[188]_0 ,
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[184]_0 ,
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[190]_0 ,
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[186]_0 ,
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[124]_0 ,
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[120]_0 ,
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0 ,
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[507]_0 ,
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[446]_0 ,
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[442]_0 ,
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[382]_0 ,
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[378]_0 ,
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[509]_0 ,
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[505]_0 ,
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[316]_0 ,
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[312]_0 ,
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[252]_0 ,
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[248]_0 ,
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[62]_0 ,
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[58]_0 ,
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[447]_0 ,
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[444]_0 ,
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[443]_0 ,
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[440]_0 ,
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[381]_0 ,
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[377]_0 ,
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[191]_0 ,
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187]_1 ,
    \rd_addr_reg[7] ,
    prbs_rdlvl_done_r1,
    \init_state_r[0]_i_4_0 ,
    \complex_num_writes_reg[1]_0 ,
    pi_dqs_found_rank_done,
    complex_pi_incdec_done,
    rdlvl_stg1_done_r1,
    write_calib_reg_0,
    wrlvl_byte_redo,
    \phy_ctl_wd_i1_reg[0] ,
    mem_reg_0_15_36_41,
    if_empty,
    mc_address,
    phy_ctl_wr_i1_reg,
    mem_out,
    out_fifo,
    out_fifo_0,
    out_fifo_1,
    mc_ras_n,
    out_fifo_2,
    mc_bank,
    mem_reg_0_15_78_79,
    out_fifo_3,
    out_fifo_4,
    out_fifo_5,
    out_fifo_6,
    out_fifo_7,
    out_fifo_8,
    out_fifo_9,
    out_fifo_10,
    out_fifo_11,
    out_fifo_12,
    out_fifo_13,
    out_fifo_14,
    out_fifo_15,
    out_fifo_16,
    out_fifo_17,
    out_fifo_18,
    out_fifo_19,
    out_fifo_20,
    out_fifo_21,
    out_fifo_22,
    out_fifo_23,
    out_fifo_24,
    out_fifo_25,
    out_fifo_26,
    out_fifo_27,
    out_fifo_28,
    mc_cas_n,
    out_fifo_29,
    out_fifo_30,
    mc_odt,
    out_fifo_31,
    mc_cke,
    mc_we_n,
    app_rd_data_valid_0,
    \read_fifo.tail_r ,
    wr_level_done_r5,
    prbs_rdlvl_start_r,
    \calib_data_offset_0_reg[3]_0 ,
    init_dqsfound_done_r2,
    \calib_data_offset_0_reg[3]_1 ,
    \calib_data_offset_1_reg[3]_0 ,
    \calib_data_offset_1_reg[3]_1 ,
    \calib_data_offset_2_reg[3]_0 ,
    \calib_data_offset_2_reg[3]_1 ,
    ddr3_lm_done_r_reg_0,
    ck_addr_cmd_delay_done,
    \calib_seq_reg[0]_0 ,
    \gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0 ,
    rdlvl_pi_incdec,
    prbs_rdlvl_start_reg_2,
    \rd_addr_reg[7]_0 ,
    done_dqs_tap_inc,
    \stg1_wr_rd_cnt_reg[3]_0 ,
    prech_req_posedge_r_reg_1,
    dqs_found_prech_req,
    rdlvl_stg1_rank_done,
    rdlvl_prech_req,
    wrcal_prech_req,
    \init_state_r[2]_i_4_0 ,
    \init_state_r[0]_i_14_0 ,
    num_samples_done_r,
    \init_state_r[4]_i_17_0 ,
    \row_cnt_victim_rotate.complex_row_cnt_reg[6]_0 ,
    \init_state_r[1]_i_6_0 ,
    \init_state_r[2]_i_3_0 ,
    reset_rd_addr,
    \row_cnt_victim_rotate.complex_row_cnt_reg[1]_0 ,
    \row_cnt_victim_rotate.complex_row_cnt_reg[2]_0 ,
    \row_cnt_victim_rotate.complex_row_cnt_reg[3]_0 ,
    \init_state_r[4]_i_10_0 ,
    \init_state_r[3]_i_4_0 ,
    \init_state_r[0]_i_4_1 ,
    \samples_cnt_r_reg[11] ,
    \rd_addr_reg[3] ,
    mc_wrdata_en,
    \en_cnt_div4.enable_wrlvl_cnt_reg[4]_0 ,
    \calib_data_offset_0_reg[5]_0 ,
    \calib_data_offset_0_reg[4]_0 ,
    \calib_data_offset_0_reg[2]_0 ,
    \calib_data_offset_0_reg[1]_0 ,
    \calib_data_offset_0_reg[0]_0 ,
    \calib_data_offset_1_reg[5]_0 ,
    \calib_data_offset_1_reg[4]_0 ,
    \calib_data_offset_1_reg[2]_0 ,
    \calib_data_offset_1_reg[1]_0 ,
    \calib_data_offset_1_reg[0]_0 ,
    \calib_data_offset_2_reg[5]_0 ,
    \calib_data_offset_2_reg[4]_0 ,
    \calib_data_offset_2_reg[2]_0 ,
    \calib_data_offset_2_reg[1]_0 ,
    \calib_data_offset_2_reg[0]_0 ,
    \cnt_pwron_ce_r_reg[0]_0 ,
    \data_offset_1_i1_reg[0] ,
    \data_offset_1_i1_reg[1] ,
    \data_offset_1_i1_reg[2] ,
    mc_data_offset_1,
    \data_offset_1_i1_reg[4] ,
    \data_offset_1_i1_reg[5] ,
    \data_offset_2_i1_reg[0] ,
    \data_offset_2_i1_reg[1] ,
    \data_offset_2_i1_reg[2] ,
    mc_data_offset_2,
    \data_offset_2_i1_reg[4] ,
    \data_offset_2_i1_reg[5] ,
    mc_cmd,
    \phy_ctl_wd_i1_reg[17] ,
    \phy_ctl_wd_i1_reg[18] ,
    \phy_ctl_wd_i1_reg[19] ,
    mc_data_offset,
    \phy_ctl_wd_i1_reg[21] ,
    \phy_ctl_wd_i1_reg[22] ,
    mem_reg_0_15_48_53,
    mem_reg_0_15_54_59,
    mem_reg_0_15_66_71,
    mem_reg_0_15_72_77,
    mem_reg_0_15_18_23,
    mem_reg_0_15_18_23_0,
    mem_reg_0_15_36_41_0,
    mem_reg_0_15_36_41_1,
    mem_reg_0_15_54_59_0,
    mem_reg_0_15_78_79_0);
  output prech_done;
  output wrlvl_done_r1;
  output prbs_rdlvl_done_pulse_reg_0;
  output prech_req_posedge_r_reg_0;
  output pi_calib_done;
  output complex_ocal_reset_rd_addr;
  output wl_sm_start;
  output wrcal_rd_wait;
  output wrcal_sanity_chk;
  output detect_pi_found_dqs;
  output calib_complete;
  output pi_dqs_found_done_r1;
  output complex_act_start;
  output \one_rank.stg1_wr_done_reg_0 ;
  output wrlvl_final_if_rst;
  output wr_lvl_start_reg_0;
  output rdlvl_stg1_start_reg_0;
  output phy_write_calib;
  output phy_read_calib;
  output first_rdlvl_pat_r;
  output first_wrcal_pat_r;
  output [7:0]D;
  output [0:0]Q;
  output [35:0]d_in;
  output [23:0]phy_dout;
  output init_complete_r1_timing_reg_0;
  output [7:0]D6;
  output [3:0]D8;
  output [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[2]_0 ;
  output [3:0]D5;
  output [3:0]D4;
  output [3:0]D7;
  output [3:0]D9;
  output [3:0]D1;
  output [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[8]_0 ;
  output [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[9]_0 ;
  output [3:0]D3;
  output [3:0]\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0]_0 ;
  output [7:0]\gen_no_mirror.div_clk_loop[0].phy_bank_reg[1]_0 ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[448] ;
  output [7:0]D2;
  output [7:0]\write_buffer.wr_buf_out_data_reg[450] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[451] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[452] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[453] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[454] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[455] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[456] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[457] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[458] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[459] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[460] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[461] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[462] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[463] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[464] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[465] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[466] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[467] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[468] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[469] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[470] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[471] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[472] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[473] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[474] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[475] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[476] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[477] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[478] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[479] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[480] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[481] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[482] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[483] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[484] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[485] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[486] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[487] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[488] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[489] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[490] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[491] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[492] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[493] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[494] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[495] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[496] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[497] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[498] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[499] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[500] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[501] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[502] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[503] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[504] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[505] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[506] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[507] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[508] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[509] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[510] ;
  output [7:0]\write_buffer.wr_buf_out_data_reg[511] ;
  output [1:0]\cmd_pipe_plus.mc_ras_n_reg[1] ;
  output [0:0]\cmd_pipe_plus.mc_cas_n_reg[1] ;
  output [3:0]\cmd_pipe_plus.mc_odt_reg[0] ;
  output [3:0]\cmd_pipe_plus.mc_cke_reg[3] ;
  output [0:0]\cmd_pipe_plus.mc_we_n_reg[1] ;
  output app_rd_data_valid;
  output \read_fifo.tail_r_reg[0] ;
  output wl_sm_start_reg_0;
  output mux_rd_valid_r0;
  output prbs_rdlvl_start_reg_0;
  output prbs_rdlvl_start_reg_1;
  output stg1_wr_done;
  output \init_state_r_reg[4]_0 ;
  output \init_state_r_reg[4]_1 ;
  output rdlvl_stg1_start_int_reg_0;
  output [0:0]E;
  output [0:0]prbs_rdlvl_done_reg;
  output \rd_addr_reg[1] ;
  output prbs_rdlvl_done_reg_0;
  output [0:0]SR;
  output phy_data_wr_en;
  output phy_cmd_wr_en;
  output mux_reset_n;
  output [5:0]\cmd_pipe_plus.mc_cke_reg[3]_0 ;
  output wrcal_start_reg_0;
  output pi_dqs_found_start_reg_0;
  output mpr_rdlvl_start_reg_0;
  output [10:0]\calib_seq_reg[1]_0 ;
  output [5:0]\cmd_pipe_plus.mc_data_offset_1_reg[5] ;
  output [5:0]\cmd_pipe_plus.mc_data_offset_2_reg[5] ;
  output [63:0]\write_buffer.wr_buf_out_data_reg[455]_0 ;
  output [63:0]\write_buffer.wr_buf_out_data_reg[463]_0 ;
  output [63:0]\write_buffer.wr_buf_out_data_reg[471]_0 ;
  output [63:0]\write_buffer.wr_buf_out_data_reg[479]_0 ;
  output [63:0]\write_buffer.wr_buf_out_data_reg[487]_0 ;
  output [63:0]\write_buffer.wr_buf_out_data_reg[495]_0 ;
  output [63:0]\write_buffer.wr_buf_out_data_reg[503]_0 ;
  output [63:0]\write_buffer.wr_buf_out_data_reg[511]_0 ;
  input \rdlvl_start_dly0_r_reg[14]_0 ;
  input pi_phase_locked_all_r1_reg_0;
  input [0:0]\victim_sel_reg[0]_0 ;
  input wrlvl_done_r_reg_0;
  input prbs_last_byte_done;
  input wrlvl_rank_done;
  input prbs_rdlvl_done_pulse0;
  input \en_cnt_div4.enable_wrlvl_cnt_reg[2]_0 ;
  input reset_rd_addr0;
  input prech_req;
  input wrcal_resume_w;
  input complex_oclkdelay_calib_done_r1_reg_0;
  input rdlvl_last_byte_done;
  input pi_dqs_found_done_r1_reg_0;
  input [0:0]\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 ;
  input \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[510]_0 ;
  input \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[506]_0 ;
  input \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[125]_0 ;
  input \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[121]_0 ;
  input \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[61]_0 ;
  input \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57]_0 ;
  input \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[508]_0 ;
  input [19:0]prbs_out;
  input \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187]_0 ;
  input \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[445]_0 ;
  input \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[441]_0 ;
  input \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[380]_0 ;
  input \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[376]_0 ;
  input \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[319]_0 ;
  input \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[315]_0 ;
  input \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[255]_0 ;
  input \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[253]_0 ;
  input \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[251]_0 ;
  input \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[249]_0 ;
  input \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[188]_0 ;
  input \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[184]_0 ;
  input \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[190]_0 ;
  input \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[186]_0 ;
  input \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[124]_0 ;
  input \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[120]_0 ;
  input \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0 ;
  input \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[507]_0 ;
  input \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[446]_0 ;
  input \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[442]_0 ;
  input \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[382]_0 ;
  input \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[378]_0 ;
  input \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[509]_0 ;
  input \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[505]_0 ;
  input \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[316]_0 ;
  input \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[312]_0 ;
  input \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[252]_0 ;
  input \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[248]_0 ;
  input \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[62]_0 ;
  input \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[58]_0 ;
  input \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[447]_0 ;
  input \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[444]_0 ;
  input \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[443]_0 ;
  input \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[440]_0 ;
  input \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[381]_0 ;
  input \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[377]_0 ;
  input \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[191]_0 ;
  input \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187]_1 ;
  input \rd_addr_reg[7] ;
  input prbs_rdlvl_done_r1;
  input \init_state_r[0]_i_4_0 ;
  input \complex_num_writes_reg[1]_0 ;
  input pi_dqs_found_rank_done;
  input complex_pi_incdec_done;
  input rdlvl_stg1_done_r1;
  input write_calib_reg_0;
  input wrlvl_byte_redo;
  input \phy_ctl_wd_i1_reg[0] ;
  input mem_reg_0_15_36_41;
  input if_empty;
  input [34:0]mc_address;
  input phy_ctl_wr_i1_reg;
  input [35:0]mem_out;
  input out_fifo;
  input [23:0]out_fifo_0;
  input out_fifo_1;
  input [0:0]mc_ras_n;
  input out_fifo_2;
  input [8:0]mc_bank;
  input [511:0]mem_reg_0_15_78_79;
  input [63:0]out_fifo_3;
  input out_fifo_4;
  input [63:0]out_fifo_5;
  input out_fifo_6;
  input [63:0]out_fifo_7;
  input out_fifo_8;
  input [63:0]out_fifo_9;
  input out_fifo_10;
  input out_fifo_11;
  input [63:0]out_fifo_12;
  input out_fifo_13;
  input [63:0]out_fifo_14;
  input out_fifo_15;
  input [63:0]out_fifo_16;
  input out_fifo_17;
  input [63:0]out_fifo_18;
  input out_fifo_19;
  input out_fifo_20;
  input out_fifo_21;
  input out_fifo_22;
  input out_fifo_23;
  input out_fifo_24;
  input out_fifo_25;
  input out_fifo_26;
  input out_fifo_27;
  input out_fifo_28;
  input [0:0]mc_cas_n;
  input [11:0]out_fifo_29;
  input out_fifo_30;
  input [0:0]mc_odt;
  input out_fifo_31;
  input [0:0]mc_cke;
  input [0:0]mc_we_n;
  input [0:0]app_rd_data_valid_0;
  input [0:0]\read_fifo.tail_r ;
  input wr_level_done_r5;
  input prbs_rdlvl_start_r;
  input [0:0]\calib_data_offset_0_reg[3]_0 ;
  input init_dqsfound_done_r2;
  input [0:0]\calib_data_offset_0_reg[3]_1 ;
  input [0:0]\calib_data_offset_1_reg[3]_0 ;
  input [0:0]\calib_data_offset_1_reg[3]_1 ;
  input [0:0]\calib_data_offset_2_reg[3]_0 ;
  input [0:0]\calib_data_offset_2_reg[3]_1 ;
  input ddr3_lm_done_r_reg_0;
  input ck_addr_cmd_delay_done;
  input [0:0]\calib_seq_reg[0]_0 ;
  input \gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0 ;
  input rdlvl_pi_incdec;
  input prbs_rdlvl_start_reg_2;
  input \rd_addr_reg[7]_0 ;
  input done_dqs_tap_inc;
  input \stg1_wr_rd_cnt_reg[3]_0 ;
  input prech_req_posedge_r_reg_1;
  input dqs_found_prech_req;
  input rdlvl_stg1_rank_done;
  input rdlvl_prech_req;
  input wrcal_prech_req;
  input \init_state_r[2]_i_4_0 ;
  input \init_state_r[0]_i_14_0 ;
  input num_samples_done_r;
  input \init_state_r[4]_i_17_0 ;
  input \row_cnt_victim_rotate.complex_row_cnt_reg[6]_0 ;
  input \init_state_r[1]_i_6_0 ;
  input \init_state_r[2]_i_3_0 ;
  input reset_rd_addr;
  input \row_cnt_victim_rotate.complex_row_cnt_reg[1]_0 ;
  input \row_cnt_victim_rotate.complex_row_cnt_reg[2]_0 ;
  input \row_cnt_victim_rotate.complex_row_cnt_reg[3]_0 ;
  input \init_state_r[4]_i_10_0 ;
  input \init_state_r[3]_i_4_0 ;
  input \init_state_r[0]_i_4_1 ;
  input \samples_cnt_r_reg[11] ;
  input [0:0]\rd_addr_reg[3] ;
  input mc_wrdata_en;
  input \en_cnt_div4.enable_wrlvl_cnt_reg[4]_0 ;
  input \calib_data_offset_0_reg[5]_0 ;
  input \calib_data_offset_0_reg[4]_0 ;
  input \calib_data_offset_0_reg[2]_0 ;
  input \calib_data_offset_0_reg[1]_0 ;
  input \calib_data_offset_0_reg[0]_0 ;
  input \calib_data_offset_1_reg[5]_0 ;
  input \calib_data_offset_1_reg[4]_0 ;
  input \calib_data_offset_1_reg[2]_0 ;
  input \calib_data_offset_1_reg[1]_0 ;
  input \calib_data_offset_1_reg[0]_0 ;
  input \calib_data_offset_2_reg[5]_0 ;
  input \calib_data_offset_2_reg[4]_0 ;
  input \calib_data_offset_2_reg[2]_0 ;
  input \calib_data_offset_2_reg[1]_0 ;
  input \calib_data_offset_2_reg[0]_0 ;
  input \cnt_pwron_ce_r_reg[0]_0 ;
  input \data_offset_1_i1_reg[0] ;
  input \data_offset_1_i1_reg[1] ;
  input \data_offset_1_i1_reg[2] ;
  input [0:0]mc_data_offset_1;
  input \data_offset_1_i1_reg[4] ;
  input \data_offset_1_i1_reg[5] ;
  input \data_offset_2_i1_reg[0] ;
  input \data_offset_2_i1_reg[1] ;
  input \data_offset_2_i1_reg[2] ;
  input [0:0]mc_data_offset_2;
  input \data_offset_2_i1_reg[4] ;
  input \data_offset_2_i1_reg[5] ;
  input [1:0]mc_cmd;
  input \phy_ctl_wd_i1_reg[17] ;
  input \phy_ctl_wd_i1_reg[18] ;
  input \phy_ctl_wd_i1_reg[19] ;
  input [0:0]mc_data_offset;
  input \phy_ctl_wd_i1_reg[21] ;
  input \phy_ctl_wd_i1_reg[22] ;
  input mem_reg_0_15_48_53;
  input mem_reg_0_15_54_59;
  input mem_reg_0_15_66_71;
  input mem_reg_0_15_72_77;
  input mem_reg_0_15_18_23;
  input mem_reg_0_15_18_23_0;
  input mem_reg_0_15_36_41_0;
  input mem_reg_0_15_36_41_1;
  input mem_reg_0_15_54_59_0;
  input mem_reg_0_15_78_79_0;

  wire [7:0]D;
  wire [3:0]D1;
  wire [7:0]D2;
  wire [3:0]D3;
  wire [3:0]D4;
  wire [3:0]D5;
  wire [7:0]D6;
  wire [3:0]D7;
  wire [3:0]D8;
  wire [3:0]D9;
  wire \DDR3_1rank.phy_int_cs_n[1]_i_10_n_0 ;
  wire \DDR3_1rank.phy_int_cs_n[1]_i_1_n_0 ;
  wire \DDR3_1rank.phy_int_cs_n[1]_i_2_n_0 ;
  wire \DDR3_1rank.phy_int_cs_n[1]_i_3_n_0 ;
  wire \DDR3_1rank.phy_int_cs_n[1]_i_4_n_0 ;
  wire \DDR3_1rank.phy_int_cs_n[1]_i_5_n_0 ;
  wire \DDR3_1rank.phy_int_cs_n[1]_i_6_n_0 ;
  wire \DDR3_1rank.phy_int_cs_n[1]_i_7_n_0 ;
  wire \DDR3_1rank.phy_int_cs_n[1]_i_8_n_0 ;
  wire \DDR3_1rank.phy_int_cs_n[1]_i_9_n_0 ;
  wire [0:0]E;
  wire [0:0]Q;
  wire [0:0]SR;
  wire [12:0]address_w;
  wire app_rd_data_valid;
  wire [0:0]app_rd_data_valid_0;
  wire \back_to_back_reads_4_1.num_reads[0]_i_1_n_0 ;
  wire \back_to_back_reads_4_1.num_reads[1]_i_1_n_0 ;
  wire [2:0]bank_w;
  wire burst_addr_r_i_1_n_0;
  wire burst_addr_r_i_2_n_0;
  wire burst_addr_r_i_3_n_0;
  wire [3:3]calib_cke;
  wire [2:0]calib_cmd;
  wire \calib_cmd[0]_i_1_n_0 ;
  wire \calib_cmd[1]_i_1_n_0 ;
  wire \calib_cmd[2]_i_1_n_0 ;
  wire \calib_cmd[2]_i_2_n_0 ;
  wire \calib_cmd[2]_i_3_n_0 ;
  wire \calib_cmd[2]_i_4_n_0 ;
  wire \calib_cmd[2]_i_5_n_0 ;
  wire calib_cmd_wren;
  wire calib_complete;
  wire [5:0]calib_data_offset_0;
  wire \calib_data_offset_0[3]_i_1_n_0 ;
  wire \calib_data_offset_0[3]_i_2_n_0 ;
  wire \calib_data_offset_0[5]_i_1_n_0 ;
  wire \calib_data_offset_0_reg[0]_0 ;
  wire \calib_data_offset_0_reg[1]_0 ;
  wire \calib_data_offset_0_reg[2]_0 ;
  wire [0:0]\calib_data_offset_0_reg[3]_0 ;
  wire [0:0]\calib_data_offset_0_reg[3]_1 ;
  wire \calib_data_offset_0_reg[4]_0 ;
  wire \calib_data_offset_0_reg[5]_0 ;
  wire [5:0]calib_data_offset_1;
  wire \calib_data_offset_1[3]_i_1_n_0 ;
  wire \calib_data_offset_1[3]_i_2_n_0 ;
  wire \calib_data_offset_1_reg[0]_0 ;
  wire \calib_data_offset_1_reg[1]_0 ;
  wire \calib_data_offset_1_reg[2]_0 ;
  wire [0:0]\calib_data_offset_1_reg[3]_0 ;
  wire [0:0]\calib_data_offset_1_reg[3]_1 ;
  wire \calib_data_offset_1_reg[4]_0 ;
  wire \calib_data_offset_1_reg[5]_0 ;
  wire [5:0]calib_data_offset_2;
  wire \calib_data_offset_2[3]_i_1_n_0 ;
  wire \calib_data_offset_2[3]_i_2_n_0 ;
  wire \calib_data_offset_2_reg[0]_0 ;
  wire \calib_data_offset_2_reg[1]_0 ;
  wire \calib_data_offset_2_reg[2]_0 ;
  wire [0:0]\calib_data_offset_2_reg[3]_0 ;
  wire [0:0]\calib_data_offset_2_reg[3]_1 ;
  wire \calib_data_offset_2_reg[4]_0 ;
  wire \calib_data_offset_2_reg[5]_0 ;
  wire [0:0]calib_odt;
  wire \calib_odt[0]_i_1_n_0 ;
  wire \calib_odt[0]_i_2_n_0 ;
  wire \calib_odt[0]_i_3_n_0 ;
  wire \calib_seq[0]_i_1_n_0 ;
  wire \calib_seq[1]_i_1_n_0 ;
  wire [0:0]\calib_seq_reg[0]_0 ;
  wire [10:0]\calib_seq_reg[1]_0 ;
  wire calib_wrdata_en;
  wire calib_wrdata_en_i_2_n_0;
  wire ck_addr_cmd_delay_done;
  wire clear;
  wire [0:0]\cmd_pipe_plus.mc_cas_n_reg[1] ;
  wire [3:0]\cmd_pipe_plus.mc_cke_reg[3] ;
  wire [5:0]\cmd_pipe_plus.mc_cke_reg[3]_0 ;
  wire [5:0]\cmd_pipe_plus.mc_data_offset_1_reg[5] ;
  wire [5:0]\cmd_pipe_plus.mc_data_offset_2_reg[5] ;
  wire [3:0]\cmd_pipe_plus.mc_odt_reg[0] ;
  wire [1:0]\cmd_pipe_plus.mc_ras_n_reg[1] ;
  wire [0:0]\cmd_pipe_plus.mc_we_n_reg[1] ;
  wire cnt_cmd_done_m7_r;
  wire cnt_cmd_done_m7_r_i_1_n_0;
  wire cnt_cmd_done_m7_r_i_2_n_0;
  wire cnt_cmd_done_r;
  wire cnt_cmd_done_r_i_1_n_0;
  wire \cnt_cmd_r[0]_i_1_n_0 ;
  wire \cnt_cmd_r[1]_i_1_n_0 ;
  wire \cnt_cmd_r[2]_i_1_n_0 ;
  wire \cnt_cmd_r[3]_i_1_n_0 ;
  wire \cnt_cmd_r[4]_i_1_n_0 ;
  wire \cnt_cmd_r[5]_i_1_n_0 ;
  wire \cnt_cmd_r[6]_i_1_n_0 ;
  wire \cnt_cmd_r[6]_i_2_n_0 ;
  wire \cnt_cmd_r[6]_i_3_n_0 ;
  wire \cnt_cmd_r[6]_i_4_n_0 ;
  wire \cnt_cmd_r_reg_n_0_[0] ;
  wire \cnt_cmd_r_reg_n_0_[1] ;
  wire \cnt_cmd_r_reg_n_0_[2] ;
  wire \cnt_cmd_r_reg_n_0_[3] ;
  wire \cnt_cmd_r_reg_n_0_[4] ;
  wire \cnt_cmd_r_reg_n_0_[5] ;
  wire \cnt_cmd_r_reg_n_0_[6] ;
  wire cnt_dllk_zqinit_done_r;
  wire cnt_dllk_zqinit_done_r_i_1_n_0;
  wire \cnt_dllk_zqinit_r[7]_i_1_n_0 ;
  wire [7:0]cnt_dllk_zqinit_r_reg;
  wire cnt_init_af_done_r;
  wire cnt_init_af_done_r_i_1_n_0;
  wire [1:0]cnt_init_af_r;
  wire \cnt_init_af_r[0]_i_1_n_0 ;
  wire \cnt_init_af_r[1]_i_1_n_0 ;
  wire cnt_init_mr_done_r;
  wire cnt_init_mr_done_r_i_1_n_0;
  wire [1:0]cnt_init_mr_r;
  wire cnt_init_mr_r1;
  wire \cnt_init_mr_r[0]_i_1_n_0 ;
  wire \cnt_init_mr_r[0]_i_2_n_0 ;
  wire \cnt_init_mr_r[0]_i_3_n_0 ;
  wire \cnt_init_mr_r[1]_i_1_n_0 ;
  wire \cnt_init_mr_r[1]_i_2_n_0 ;
  wire [9:0]cnt_pwron_ce_r_reg;
  wire \cnt_pwron_ce_r_reg[0]_0 ;
  wire cnt_pwron_cke_done_r;
  wire cnt_pwron_cke_done_r_i_1_n_0;
  wire cnt_pwron_cke_done_r_i_2_n_0;
  wire cnt_pwron_cke_done_r_i_3_n_0;
  wire \cnt_pwron_r[8]_i_2_n_0 ;
  wire [8:0]cnt_pwron_r_reg;
  wire cnt_pwron_reset_done_r;
  wire cnt_pwron_reset_done_r_i_1_n_0;
  wire cnt_pwron_reset_done_r_i_2_n_0;
  wire cnt_txpr_done_r;
  wire cnt_txpr_done_r_i_1_n_0;
  wire cnt_txpr_done_r_i_2_n_0;
  wire \cnt_txpr_r[7]_i_3_n_0 ;
  wire [7:0]cnt_txpr_r_reg;
  wire complex_act_start;
  wire complex_act_start0;
  wire complex_act_start_i_2_n_0;
  wire complex_address0;
  wire \complex_address[9]_i_2_n_0 ;
  wire \complex_address[9]_i_3_n_0 ;
  wire \complex_address_reg_n_0_[0] ;
  wire \complex_address_reg_n_0_[1] ;
  wire \complex_address_reg_n_0_[2] ;
  wire \complex_address_reg_n_0_[3] ;
  wire \complex_address_reg_n_0_[4] ;
  wire \complex_address_reg_n_0_[5] ;
  wire \complex_address_reg_n_0_[6] ;
  wire \complex_address_reg_n_0_[7] ;
  wire \complex_address_reg_n_0_[8] ;
  wire \complex_address_reg_n_0_[9] ;
  wire complex_byte_rd_done;
  wire complex_byte_rd_done_i_1_n_0;
  wire complex_byte_rd_done_i_2_n_0;
  wire \complex_num_reads[0]_i_1_n_0 ;
  wire \complex_num_reads[1]_i_1_n_0 ;
  wire \complex_num_reads[1]_i_2_n_0 ;
  wire \complex_num_reads[2]_i_1_n_0 ;
  wire \complex_num_reads[2]_i_2_n_0 ;
  wire \complex_num_reads[2]_i_3_n_0 ;
  wire \complex_num_reads[2]_i_4_n_0 ;
  wire \complex_num_reads[2]_i_5_n_0 ;
  wire \complex_num_reads[2]_i_6_n_0 ;
  wire \complex_num_reads[3]_i_1_n_0 ;
  wire \complex_num_reads[3]_i_2_n_0 ;
  wire \complex_num_reads[3]_i_3_n_0 ;
  wire \complex_num_reads[3]_i_4_n_0 ;
  wire \complex_num_reads[3]_i_5_n_0 ;
  wire \complex_num_reads[3]_i_6_n_0 ;
  wire \complex_num_reads[3]_i_7_n_0 ;
  wire [3:0]complex_num_reads_dec;
  wire \complex_num_reads_dec[0]_i_1_n_0 ;
  wire \complex_num_reads_dec[1]_i_1_n_0 ;
  wire \complex_num_reads_dec[2]_i_1_n_0 ;
  wire \complex_num_reads_dec[3]_i_1_n_0 ;
  wire \complex_num_reads_dec[3]_i_2_n_0 ;
  wire \complex_num_reads_dec[3]_i_3_n_0 ;
  wire \complex_num_reads_dec[3]_i_4_n_0 ;
  wire \complex_num_reads_reg_n_0_[0] ;
  wire \complex_num_reads_reg_n_0_[1] ;
  wire \complex_num_reads_reg_n_0_[2] ;
  wire \complex_num_reads_reg_n_0_[3] ;
  wire \complex_num_writes[0]_i_1_n_0 ;
  wire \complex_num_writes[0]_i_2_n_0 ;
  wire \complex_num_writes[1]_i_1_n_0 ;
  wire \complex_num_writes[1]_i_2_n_0 ;
  wire \complex_num_writes[2]_i_1_n_0 ;
  wire \complex_num_writes[2]_i_2_n_0 ;
  wire \complex_num_writes[2]_i_3_n_0 ;
  wire \complex_num_writes[2]_i_4_n_0 ;
  wire \complex_num_writes[2]_i_5_n_0 ;
  wire \complex_num_writes[2]_i_7_n_0 ;
  wire \complex_num_writes[2]_i_8_n_0 ;
  wire \complex_num_writes[2]_i_9_n_0 ;
  wire \complex_num_writes[3]_i_1_n_0 ;
  wire \complex_num_writes[3]_i_2_n_0 ;
  wire \complex_num_writes[3]_i_3_n_0 ;
  wire \complex_num_writes[3]_i_4_n_0 ;
  wire \complex_num_writes[4]_i_10_n_0 ;
  wire \complex_num_writes[4]_i_11_n_0 ;
  wire \complex_num_writes[4]_i_12_n_0 ;
  wire \complex_num_writes[4]_i_13_n_0 ;
  wire \complex_num_writes[4]_i_14_n_0 ;
  wire \complex_num_writes[4]_i_15_n_0 ;
  wire \complex_num_writes[4]_i_16_n_0 ;
  wire \complex_num_writes[4]_i_1_n_0 ;
  wire \complex_num_writes[4]_i_2_n_0 ;
  wire \complex_num_writes[4]_i_3_n_0 ;
  wire \complex_num_writes[4]_i_4_n_0 ;
  wire \complex_num_writes[4]_i_5_n_0 ;
  wire \complex_num_writes[4]_i_6_n_0 ;
  wire \complex_num_writes[4]_i_7_n_0 ;
  wire \complex_num_writes[4]_i_8_n_0 ;
  wire \complex_num_writes[4]_i_9_n_0 ;
  wire [4:0]complex_num_writes_dec;
  wire \complex_num_writes_dec[0]_i_1_n_0 ;
  wire \complex_num_writes_dec[1]_i_1_n_0 ;
  wire \complex_num_writes_dec[2]_i_1_n_0 ;
  wire \complex_num_writes_dec[3]_i_1_n_0 ;
  wire \complex_num_writes_dec[4]_i_2_n_0 ;
  wire \complex_num_writes_dec[4]_i_3_n_0 ;
  wire \complex_num_writes_dec[4]_i_4_n_0 ;
  wire \complex_num_writes_dec[4]_i_5_n_0 ;
  wire \complex_num_writes_reg[1]_0 ;
  wire \complex_num_writes_reg_n_0_[0] ;
  wire \complex_num_writes_reg_n_0_[1] ;
  wire \complex_num_writes_reg_n_0_[2] ;
  wire \complex_num_writes_reg_n_0_[3] ;
  wire \complex_num_writes_reg_n_0_[4] ;
  wire complex_ocal_odt_ext;
  wire complex_ocal_odt_ext_i_1_n_0;
  wire complex_ocal_odt_ext_i_2_n_0;
  wire complex_ocal_odt_ext_i_3_n_0;
  wire complex_ocal_reset_rd_addr;
  wire complex_ocal_reset_rd_addr0;
  wire complex_ocal_reset_rd_addr_i_2_n_0;
  wire complex_ocal_reset_rd_addr_i_3_n_0;
  wire complex_ocal_wr_start;
  wire complex_ocal_wr_start_i_1_n_0;
  wire complex_oclkdelay_calib_done_r1;
  wire complex_oclkdelay_calib_done_r1_reg_0;
  wire complex_oclkdelay_calib_start_int;
  wire complex_oclkdelay_calib_start_int_i_1_n_0;
  wire complex_oclkdelay_calib_start_int_i_2_n_0;
  wire complex_oclkdelay_calib_start_r1;
  wire complex_odt_ext;
  wire complex_odt_ext_i_1_n_0;
  wire complex_pi_incdec_done;
  wire complex_row0_rd_done;
  wire complex_row0_rd_done1;
  wire complex_row0_rd_done_i_1_n_0;
  wire complex_row0_rd_done_i_2_n_0;
  wire complex_row0_wr_done;
  wire complex_row0_wr_done0;
  wire [2:0]complex_row1_rd_cnt;
  wire \complex_row1_rd_cnt[0]_i_1_n_0 ;
  wire \complex_row1_rd_cnt[1]_i_1_n_0 ;
  wire \complex_row1_rd_cnt[2]_i_1_n_0 ;
  wire complex_row1_rd_done;
  wire complex_row1_rd_done_i_1_n_0;
  wire complex_row1_rd_done_i_2_n_0;
  wire complex_row1_rd_done_r1;
  wire complex_row1_wr_done;
  wire complex_row_cnt;
  wire complex_row_cnt_ocal;
  wire complex_row_cnt_ocal0;
  wire \complex_row_cnt_ocal[3]_i_4_n_0 ;
  wire \complex_row_cnt_ocal[3]_i_5_n_0 ;
  wire \complex_row_cnt_ocal[3]_i_6_n_0 ;
  wire [3:0]complex_row_cnt_ocal_reg;
  wire complex_sample_cnt_inc;
  wire complex_sample_cnt_inc0;
  wire complex_sample_cnt_inc_i_2_n_0;
  wire complex_sample_cnt_inc_i_3_n_0;
  wire complex_sample_cnt_inc_r1;
  wire complex_sample_cnt_inc_r2;
  wire \complex_wait_cnt[3]_i_1_n_0 ;
  wire \complex_wait_cnt[3]_i_3_n_0 ;
  wire [3:0]complex_wait_cnt_reg;
  wire complex_wr_done;
  wire [35:0]d_in;
  wire \data_offset_1_i1_reg[0] ;
  wire \data_offset_1_i1_reg[1] ;
  wire \data_offset_1_i1_reg[2] ;
  wire \data_offset_1_i1_reg[4] ;
  wire \data_offset_1_i1_reg[5] ;
  wire \data_offset_2_i1_reg[0] ;
  wire \data_offset_2_i1_reg[1] ;
  wire \data_offset_2_i1_reg[2] ;
  wire \data_offset_2_i1_reg[4] ;
  wire \data_offset_2_i1_reg[5] ;
  wire ddr2_pre_flag_r_i_1_n_0;
  wire ddr2_pre_flag_r_i_2_n_0;
  wire ddr2_pre_flag_r_reg_n_0;
  wire ddr2_refresh_flag_r;
  wire ddr2_refresh_flag_r_i_1_n_0;
  wire ddr2_refresh_flag_r_i_2_n_0;
  wire ddr2_refresh_flag_r_i_3_n_0;
  wire ddr3_lm_done_r;
  wire ddr3_lm_done_r_i_1_n_0;
  wire ddr3_lm_done_r_reg_0;
  wire detect_pi_found_dqs;
  wire detect_pi_found_dqs0;
  wire detect_pi_found_dqs_i_2_n_0;
  wire done_dqs_tap_inc;
  wire [1:0]dqs_asrt_cnt;
  wire \dqs_asrt_cnt[0]_i_1_n_0 ;
  wire \dqs_asrt_cnt[1]_i_1_n_0 ;
  wire dqs_found_prech_req;
  wire \en_cnt_div4.enable_wrlvl_cnt[0]_i_1_n_0 ;
  wire \en_cnt_div4.enable_wrlvl_cnt[1]_i_1_n_0 ;
  wire \en_cnt_div4.enable_wrlvl_cnt[2]_i_1_n_0 ;
  wire \en_cnt_div4.enable_wrlvl_cnt[3]_i_1_n_0 ;
  wire \en_cnt_div4.enable_wrlvl_cnt[4]_i_1_n_0 ;
  wire \en_cnt_div4.enable_wrlvl_cnt_reg[2]_0 ;
  wire \en_cnt_div4.enable_wrlvl_cnt_reg[4]_0 ;
  wire \en_cnt_div4.wrlvl_odt_i_1_n_0 ;
  wire \en_cnt_div4.wrlvl_odt_i_2_n_0 ;
  wire [4:0]enable_wrlvl_cnt;
  wire enable_wrlvl_cnt0;
  wire first_rdlvl_pat_r;
  wire first_rdlvl_pat_r_i_1_n_0;
  wire first_wrcal_pat_r;
  wire first_wrcal_pat_r_i_1_n_0;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_2_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_3_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_4_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_3_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_5_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_6_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_2_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_3_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_4_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_5_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_2_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_3_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_4_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_5_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_6_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_2_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_3_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_2_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_3_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_4_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_2_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_3_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_4_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_5_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_6_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_10_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_2_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_3_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_4_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_5_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_6_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_7_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_8_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_9_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_10_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_11_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_12_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_13_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_2_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_3_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_4_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_5_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_6_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_8_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_2_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_3_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_12_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_13_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_15_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_16_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_17_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_2_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_5_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_6_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0 ;
  wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[2]_0 ;
  wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[8]_0 ;
  wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_address_reg[9]_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10] ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12] ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ;
  wire \gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9] ;
  wire \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_2_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_3_n_0 ;
  wire \gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_2_n_0 ;
  wire [3:0]\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0]_0 ;
  wire [7:0]\gen_no_mirror.div_clk_loop[0].phy_bank_reg[1]_0 ;
  wire \gen_rnk[0].mr1_r_reg_n_0_[0][1] ;
  wire if_empty;
  wire init_complete_r1;
  (* RTL_KEEP = "true" *) wire init_complete_r1_timing;
  wire init_complete_r1_timing_reg_0;
  wire init_complete_r2;
  wire init_complete_r_i_1_n_0;
  wire init_complete_r_reg_n_0;
  (* RTL_KEEP = "true" *) wire init_complete_r_timing;
  wire init_complete_r_timing_i_1_n_0;
  wire init_dqsfound_done_r2;
  wire init_next_state1100_out;
  wire [6:6]init_state_r;
  wire [6:0]init_state_r1;
  wire \init_state_r[0]_i_10_n_0 ;
  wire \init_state_r[0]_i_11_n_0 ;
  wire \init_state_r[0]_i_12_n_0 ;
  wire \init_state_r[0]_i_13_n_0 ;
  wire \init_state_r[0]_i_14_0 ;
  wire \init_state_r[0]_i_14_n_0 ;
  wire \init_state_r[0]_i_15_n_0 ;
  wire \init_state_r[0]_i_16_n_0 ;
  wire \init_state_r[0]_i_17_n_0 ;
  wire \init_state_r[0]_i_18_n_0 ;
  wire \init_state_r[0]_i_19_n_0 ;
  wire \init_state_r[0]_i_1_n_0 ;
  wire \init_state_r[0]_i_20_n_0 ;
  wire \init_state_r[0]_i_21_n_0 ;
  wire \init_state_r[0]_i_22_n_0 ;
  wire \init_state_r[0]_i_23_n_0 ;
  wire \init_state_r[0]_i_25_n_0 ;
  wire \init_state_r[0]_i_26_n_0 ;
  wire \init_state_r[0]_i_27_n_0 ;
  wire \init_state_r[0]_i_28_n_0 ;
  wire \init_state_r[0]_i_29_n_0 ;
  wire \init_state_r[0]_i_2_n_0 ;
  wire \init_state_r[0]_i_30_n_0 ;
  wire \init_state_r[0]_i_31_n_0 ;
  wire \init_state_r[0]_i_32_n_0 ;
  wire \init_state_r[0]_i_3_n_0 ;
  wire \init_state_r[0]_i_4_0 ;
  wire \init_state_r[0]_i_4_1 ;
  wire \init_state_r[0]_i_4_n_0 ;
  wire \init_state_r[0]_i_5_n_0 ;
  wire \init_state_r[0]_i_6_n_0 ;
  wire \init_state_r[0]_i_7_n_0 ;
  wire \init_state_r[0]_i_8_n_0 ;
  wire \init_state_r[0]_i_9_n_0 ;
  wire \init_state_r[1]_i_10_n_0 ;
  wire \init_state_r[1]_i_11_n_0 ;
  wire \init_state_r[1]_i_12_n_0 ;
  wire \init_state_r[1]_i_13_n_0 ;
  wire \init_state_r[1]_i_14_n_0 ;
  wire \init_state_r[1]_i_15_n_0 ;
  wire \init_state_r[1]_i_16_n_0 ;
  wire \init_state_r[1]_i_17_n_0 ;
  wire \init_state_r[1]_i_18_n_0 ;
  wire \init_state_r[1]_i_19_n_0 ;
  wire \init_state_r[1]_i_1_n_0 ;
  wire \init_state_r[1]_i_20_n_0 ;
  wire \init_state_r[1]_i_21_n_0 ;
  wire \init_state_r[1]_i_22_n_0 ;
  wire \init_state_r[1]_i_23_n_0 ;
  wire \init_state_r[1]_i_24_n_0 ;
  wire \init_state_r[1]_i_25_n_0 ;
  wire \init_state_r[1]_i_26_n_0 ;
  wire \init_state_r[1]_i_27_n_0 ;
  wire \init_state_r[1]_i_29_n_0 ;
  wire \init_state_r[1]_i_2_n_0 ;
  wire \init_state_r[1]_i_30_n_0 ;
  wire \init_state_r[1]_i_31_n_0 ;
  wire \init_state_r[1]_i_32_n_0 ;
  wire \init_state_r[1]_i_34_n_0 ;
  wire \init_state_r[1]_i_3_n_0 ;
  wire \init_state_r[1]_i_4_n_0 ;
  wire \init_state_r[1]_i_5_n_0 ;
  wire \init_state_r[1]_i_6_0 ;
  wire \init_state_r[1]_i_6_n_0 ;
  wire \init_state_r[1]_i_7_n_0 ;
  wire \init_state_r[1]_i_8_n_0 ;
  wire \init_state_r[1]_i_9_n_0 ;
  wire \init_state_r[2]_i_10_n_0 ;
  wire \init_state_r[2]_i_11_n_0 ;
  wire \init_state_r[2]_i_12_n_0 ;
  wire \init_state_r[2]_i_13_n_0 ;
  wire \init_state_r[2]_i_14_n_0 ;
  wire \init_state_r[2]_i_15_n_0 ;
  wire \init_state_r[2]_i_16_n_0 ;
  wire \init_state_r[2]_i_17_n_0 ;
  wire \init_state_r[2]_i_18_n_0 ;
  wire \init_state_r[2]_i_19_n_0 ;
  wire \init_state_r[2]_i_1_n_0 ;
  wire \init_state_r[2]_i_20_n_0 ;
  wire \init_state_r[2]_i_21_n_0 ;
  wire \init_state_r[2]_i_22_n_0 ;
  wire \init_state_r[2]_i_23_n_0 ;
  wire \init_state_r[2]_i_24_n_0 ;
  wire \init_state_r[2]_i_25_n_0 ;
  wire \init_state_r[2]_i_26_n_0 ;
  wire \init_state_r[2]_i_29_n_0 ;
  wire \init_state_r[2]_i_2_n_0 ;
  wire \init_state_r[2]_i_30_n_0 ;
  wire \init_state_r[2]_i_31_n_0 ;
  wire \init_state_r[2]_i_32_n_0 ;
  wire \init_state_r[2]_i_33_n_0 ;
  wire \init_state_r[2]_i_34_n_0 ;
  wire \init_state_r[2]_i_36_n_0 ;
  wire \init_state_r[2]_i_38_n_0 ;
  wire \init_state_r[2]_i_39_n_0 ;
  wire \init_state_r[2]_i_3_0 ;
  wire \init_state_r[2]_i_3_n_0 ;
  wire \init_state_r[2]_i_40_n_0 ;
  wire \init_state_r[2]_i_41_n_0 ;
  wire \init_state_r[2]_i_42_n_0 ;
  wire \init_state_r[2]_i_43_n_0 ;
  wire \init_state_r[2]_i_44_n_0 ;
  wire \init_state_r[2]_i_45_n_0 ;
  wire \init_state_r[2]_i_4_0 ;
  wire \init_state_r[2]_i_4_n_0 ;
  wire \init_state_r[2]_i_5_n_0 ;
  wire \init_state_r[2]_i_6_n_0 ;
  wire \init_state_r[2]_i_7_n_0 ;
  wire \init_state_r[2]_i_8_n_0 ;
  wire \init_state_r[2]_i_9_n_0 ;
  wire \init_state_r[3]_i_10_n_0 ;
  wire \init_state_r[3]_i_11_n_0 ;
  wire \init_state_r[3]_i_12_n_0 ;
  wire \init_state_r[3]_i_13_n_0 ;
  wire \init_state_r[3]_i_14_n_0 ;
  wire \init_state_r[3]_i_15_n_0 ;
  wire \init_state_r[3]_i_16_n_0 ;
  wire \init_state_r[3]_i_17_n_0 ;
  wire \init_state_r[3]_i_18_n_0 ;
  wire \init_state_r[3]_i_19_n_0 ;
  wire \init_state_r[3]_i_1_n_0 ;
  wire \init_state_r[3]_i_20_n_0 ;
  wire \init_state_r[3]_i_21_n_0 ;
  wire \init_state_r[3]_i_22_n_0 ;
  wire \init_state_r[3]_i_24_n_0 ;
  wire \init_state_r[3]_i_2_n_0 ;
  wire \init_state_r[3]_i_3_n_0 ;
  wire \init_state_r[3]_i_4_0 ;
  wire \init_state_r[3]_i_4_n_0 ;
  wire \init_state_r[3]_i_5_n_0 ;
  wire \init_state_r[3]_i_6_n_0 ;
  wire \init_state_r[3]_i_7_n_0 ;
  wire \init_state_r[3]_i_8_n_0 ;
  wire \init_state_r[3]_i_9_n_0 ;
  wire \init_state_r[4]_i_10_0 ;
  wire \init_state_r[4]_i_10_n_0 ;
  wire \init_state_r[4]_i_11_n_0 ;
  wire \init_state_r[4]_i_12_n_0 ;
  wire \init_state_r[4]_i_13_n_0 ;
  wire \init_state_r[4]_i_14_n_0 ;
  wire \init_state_r[4]_i_15_n_0 ;
  wire \init_state_r[4]_i_16_n_0 ;
  wire \init_state_r[4]_i_17_0 ;
  wire \init_state_r[4]_i_17_n_0 ;
  wire \init_state_r[4]_i_18_n_0 ;
  wire \init_state_r[4]_i_19_n_0 ;
  wire \init_state_r[4]_i_1_n_0 ;
  wire \init_state_r[4]_i_20_n_0 ;
  wire \init_state_r[4]_i_21_n_0 ;
  wire \init_state_r[4]_i_22_n_0 ;
  wire \init_state_r[4]_i_23_n_0 ;
  wire \init_state_r[4]_i_24_n_0 ;
  wire \init_state_r[4]_i_25_n_0 ;
  wire \init_state_r[4]_i_26_n_0 ;
  wire \init_state_r[4]_i_27_n_0 ;
  wire \init_state_r[4]_i_2_n_0 ;
  wire \init_state_r[4]_i_3_n_0 ;
  wire \init_state_r[4]_i_4_n_0 ;
  wire \init_state_r[4]_i_5_n_0 ;
  wire \init_state_r[4]_i_6_n_0 ;
  wire \init_state_r[4]_i_7_n_0 ;
  wire \init_state_r[4]_i_8_n_0 ;
  wire \init_state_r[4]_i_9_n_0 ;
  wire \init_state_r[5]_i_10_n_0 ;
  wire \init_state_r[5]_i_11_n_0 ;
  wire \init_state_r[5]_i_12_n_0 ;
  wire \init_state_r[5]_i_13_n_0 ;
  wire \init_state_r[5]_i_14_n_0 ;
  wire \init_state_r[5]_i_15_n_0 ;
  wire \init_state_r[5]_i_16_n_0 ;
  wire \init_state_r[5]_i_17_n_0 ;
  wire \init_state_r[5]_i_18_n_0 ;
  wire \init_state_r[5]_i_19_n_0 ;
  wire \init_state_r[5]_i_1_n_0 ;
  wire \init_state_r[5]_i_20_n_0 ;
  wire \init_state_r[5]_i_21_n_0 ;
  wire \init_state_r[5]_i_22_n_0 ;
  wire \init_state_r[5]_i_23_n_0 ;
  wire \init_state_r[5]_i_24_n_0 ;
  wire \init_state_r[5]_i_25_n_0 ;
  wire \init_state_r[5]_i_26_n_0 ;
  wire \init_state_r[5]_i_27_n_0 ;
  wire \init_state_r[5]_i_28_n_0 ;
  wire \init_state_r[5]_i_29_n_0 ;
  wire \init_state_r[5]_i_2_n_0 ;
  wire \init_state_r[5]_i_30_n_0 ;
  wire \init_state_r[5]_i_31_n_0 ;
  wire \init_state_r[5]_i_32_n_0 ;
  wire \init_state_r[5]_i_33_n_0 ;
  wire \init_state_r[5]_i_34_n_0 ;
  wire \init_state_r[5]_i_35_n_0 ;
  wire \init_state_r[5]_i_36_n_0 ;
  wire \init_state_r[5]_i_37_n_0 ;
  wire \init_state_r[5]_i_38_n_0 ;
  wire \init_state_r[5]_i_39_n_0 ;
  wire \init_state_r[5]_i_3_n_0 ;
  wire \init_state_r[5]_i_40_n_0 ;
  wire \init_state_r[5]_i_41_n_0 ;
  wire \init_state_r[5]_i_42_n_0 ;
  wire \init_state_r[5]_i_43_n_0 ;
  wire \init_state_r[5]_i_44_n_0 ;
  wire \init_state_r[5]_i_45_n_0 ;
  wire \init_state_r[5]_i_46_n_0 ;
  wire \init_state_r[5]_i_47_n_0 ;
  wire \init_state_r[5]_i_48_n_0 ;
  wire \init_state_r[5]_i_49_n_0 ;
  wire \init_state_r[5]_i_4_n_0 ;
  wire \init_state_r[5]_i_50_n_0 ;
  wire \init_state_r[5]_i_5_n_0 ;
  wire \init_state_r[5]_i_6_n_0 ;
  wire \init_state_r[5]_i_7_n_0 ;
  wire \init_state_r[5]_i_8_n_0 ;
  wire \init_state_r[5]_i_9_n_0 ;
  wire \init_state_r[6]_i_10_n_0 ;
  wire \init_state_r[6]_i_11_n_0 ;
  wire \init_state_r[6]_i_12_n_0 ;
  wire \init_state_r[6]_i_13_n_0 ;
  wire \init_state_r[6]_i_14_n_0 ;
  wire \init_state_r[6]_i_15_n_0 ;
  wire \init_state_r[6]_i_16_n_0 ;
  wire \init_state_r[6]_i_17_n_0 ;
  wire \init_state_r[6]_i_18_n_0 ;
  wire \init_state_r[6]_i_19_n_0 ;
  wire \init_state_r[6]_i_1_n_0 ;
  wire \init_state_r[6]_i_20_n_0 ;
  wire \init_state_r[6]_i_21_n_0 ;
  wire \init_state_r[6]_i_22_n_0 ;
  wire \init_state_r[6]_i_23_n_0 ;
  wire \init_state_r[6]_i_24_n_0 ;
  wire \init_state_r[6]_i_25_n_0 ;
  wire \init_state_r[6]_i_26_n_0 ;
  wire \init_state_r[6]_i_2_n_0 ;
  wire \init_state_r[6]_i_3_n_0 ;
  wire \init_state_r[6]_i_4_n_0 ;
  wire \init_state_r[6]_i_5_n_0 ;
  wire \init_state_r[6]_i_6_n_0 ;
  wire \init_state_r[6]_i_7_n_0 ;
  wire \init_state_r[6]_i_8_n_0 ;
  wire \init_state_r[6]_i_9_n_0 ;
  wire \init_state_r_reg[4]_0 ;
  wire \init_state_r_reg[4]_1 ;
  wire \init_state_r_reg_n_0_[1] ;
  wire \init_state_r_reg_n_0_[2] ;
  wire \init_state_r_reg_n_0_[3] ;
  wire \init_state_r_reg_n_0_[4] ;
  wire \init_state_r_reg_n_0_[5] ;
  wire [34:0]mc_address;
  wire [8:0]mc_bank;
  wire [0:0]mc_cas_n;
  wire [0:0]mc_cke;
  wire [1:0]mc_cmd;
  wire [0:0]mc_data_offset;
  wire [0:0]mc_data_offset_1;
  wire [0:0]mc_data_offset_2;
  wire [0:0]mc_odt;
  wire [0:0]mc_ras_n;
  wire [0:0]mc_we_n;
  wire mc_wrdata_en;
  wire mem_init_done_r;
  wire mem_init_done_r_i_1_n_0;
  wire mem_init_done_r_i_2_n_0;
  wire [35:0]mem_out;
  wire mem_reg_0_15_18_23;
  wire mem_reg_0_15_18_23_0;
  wire mem_reg_0_15_36_41;
  wire mem_reg_0_15_36_41_0;
  wire mem_reg_0_15_36_41_1;
  wire mem_reg_0_15_48_53;
  wire mem_reg_0_15_54_59;
  wire mem_reg_0_15_54_59_0;
  wire mem_reg_0_15_66_71;
  wire mem_reg_0_15_72_77;
  wire [511:0]mem_reg_0_15_78_79;
  wire mem_reg_0_15_78_79_0;
  wire mpr_rdlvl_start_i_1_n_0;
  wire mpr_rdlvl_start_i_2_n_0;
  wire mpr_rdlvl_start_reg_0;
  wire mux_rd_valid_r0;
  wire mux_reset_n;
  wire [1:0]num_reads;
  wire num_refresh0;
  wire \num_refresh[3]_i_1_n_0 ;
  wire \num_refresh[3]_i_4_n_0 ;
  wire \num_refresh[3]_i_5_n_0 ;
  wire \num_refresh[3]_i_6_n_0 ;
  wire [3:0]num_refresh_reg;
  wire num_samples_done_r;
  wire \ocal_act_wait_cnt[3]_i_1_n_0 ;
  wire \ocal_act_wait_cnt[3]_i_3_n_0 ;
  wire [3:0]ocal_act_wait_cnt_reg;
  wire [3:2]oclk_wr_cnt0;
  wire \oclk_wr_cnt[0]_i_1_n_0 ;
  wire \oclk_wr_cnt[1]_i_1_n_0 ;
  wire \oclk_wr_cnt[3]_i_1_n_0 ;
  wire \oclk_wr_cnt[3]_i_4_n_0 ;
  wire [3:0]oclk_wr_cnt_reg;
  wire \odd_cwl.phy_cas_n[1]_i_1_n_0 ;
  wire \odd_cwl.phy_cas_n[1]_i_2_n_0 ;
  wire \odd_cwl.phy_cas_n[1]_i_3_n_0 ;
  wire \odd_cwl.phy_cas_n[1]_i_4_n_0 ;
  wire \odd_cwl.phy_ras_n[1]_i_1_n_0 ;
  wire \odd_cwl.phy_we_n[1]_i_1_n_0 ;
  wire \one_rank.stg1_wr_done_i_1_n_0 ;
  wire \one_rank.stg1_wr_done_reg_0 ;
  wire \one_rank_complex.complex_wr_done_i_1_n_0 ;
  wire \one_rank_complex.complex_wr_done_i_2_n_0 ;
  wire \one_rank_complex.complex_wr_done_i_3_n_0 ;
  wire \one_rank_complex.complex_wr_done_i_4_n_0 ;
  wire out_fifo;
  wire [23:0]out_fifo_0;
  wire out_fifo_1;
  wire out_fifo_10;
  wire out_fifo_11;
  wire [63:0]out_fifo_12;
  wire out_fifo_13;
  wire [63:0]out_fifo_14;
  wire out_fifo_15;
  wire [63:0]out_fifo_16;
  wire out_fifo_17;
  wire [63:0]out_fifo_18;
  wire out_fifo_19;
  wire out_fifo_2;
  wire out_fifo_20;
  wire out_fifo_21;
  wire out_fifo_22;
  wire out_fifo_23;
  wire out_fifo_24;
  wire out_fifo_25;
  wire out_fifo_26;
  wire out_fifo_27;
  wire out_fifo_28;
  wire [11:0]out_fifo_29;
  wire [63:0]out_fifo_3;
  wire out_fifo_30;
  wire out_fifo_31;
  wire out_fifo_4;
  wire [63:0]out_fifo_5;
  wire out_fifo_6;
  wire [63:0]out_fifo_7;
  wire out_fifo_8;
  wire [63:0]out_fifo_9;
  wire p_0_in0_in;
  wire [9:0]p_0_in__0;
  wire [8:0]p_0_in__1;
  wire [7:0]p_0_in__2;
  wire [3:0]p_0_in__3;
  wire [7:0]p_0_in__4;
  wire [3:0]p_0_in__5;
  wire [3:0]p_0_in__6;
  wire [3:0]p_0_in__7;
  wire [3:0]p_0_in__8;
  wire p_115_in;
  wire [3:3]p_17_in;
  wire p_81_in;
  wire [11:9]phy_bank;
  wire [1:1]phy_cas_n;
  wire phy_cmd_wr_en;
  wire [1:1]phy_cs_n;
  wire \phy_ctl_wd_i1_reg[0] ;
  wire \phy_ctl_wd_i1_reg[17] ;
  wire \phy_ctl_wd_i1_reg[18] ;
  wire \phy_ctl_wd_i1_reg[19] ;
  wire \phy_ctl_wd_i1_reg[21] ;
  wire \phy_ctl_wd_i1_reg[22] ;
  wire phy_ctl_wr_i1_reg;
  wire phy_data_wr_en;
  wire [23:0]phy_dout;
  wire [1:1]phy_ras_n;
  wire phy_read_calib;
  wire phy_reset_n;
  wire [1:1]phy_we_n;
  wire [511:56]phy_wrdata;
  wire phy_wrdata_en;
  wire phy_write_calib;
  wire pi_calib_done;
  wire pi_calib_done_r;
  wire pi_calib_done_r_i_1_n_0;
  wire pi_calib_rank_done_r;
  wire pi_dqs_found_done_r1;
  wire pi_dqs_found_done_r1_reg_0;
  wire pi_dqs_found_rank_done;
  wire pi_dqs_found_start_i_1_n_0;
  wire pi_dqs_found_start_i_2_n_0;
  wire pi_dqs_found_start_reg_0;
  (* async_reg = "true" *) wire pi_phase_locked_all_r1;
  wire pi_phase_locked_all_r1_reg_0;
  (* async_reg = "true" *) wire pi_phase_locked_all_r2;
  (* async_reg = "true" *) wire pi_phase_locked_all_r3;
  (* async_reg = "true" *) wire pi_phase_locked_all_r4;
  wire prbs_gen_clk_en;
  wire prbs_gen_clk_en0;
  wire prbs_gen_clk_en_i_1_n_0;
  wire prbs_gen_clk_en_i_3_n_0;
  wire prbs_gen_clk_en_i_4_n_0;
  wire prbs_gen_clk_en_i_5_n_0;
  wire prbs_gen_oclk_clk_en;
  wire prbs_gen_oclk_clk_en_i_10_n_0;
  wire prbs_gen_oclk_clk_en_i_11_n_0;
  wire prbs_gen_oclk_clk_en_i_12_n_0;
  wire prbs_gen_oclk_clk_en_i_1_n_0;
  wire prbs_gen_oclk_clk_en_i_2_n_0;
  wire prbs_gen_oclk_clk_en_i_3_n_0;
  wire prbs_gen_oclk_clk_en_i_4_n_0;
  wire prbs_gen_oclk_clk_en_i_5_n_0;
  wire prbs_gen_oclk_clk_en_i_6_n_0;
  wire prbs_gen_oclk_clk_en_i_7_n_0;
  wire prbs_gen_oclk_clk_en_i_8_n_0;
  wire prbs_gen_oclk_clk_en_i_9_n_0;
  wire prbs_last_byte_done;
  wire prbs_last_byte_done_r;
  wire [19:0]prbs_out;
  wire prbs_rdlvl_done_pulse0;
  wire prbs_rdlvl_done_pulse_reg_0;
  wire prbs_rdlvl_done_r1;
  wire [0:0]prbs_rdlvl_done_reg;
  wire prbs_rdlvl_done_reg_0;
  wire prbs_rdlvl_start_i_1_n_0;
  wire prbs_rdlvl_start_i_2_n_0;
  wire prbs_rdlvl_start_i_3_n_0;
  wire prbs_rdlvl_start_r;
  wire prbs_rdlvl_start_reg_0;
  wire prbs_rdlvl_start_reg_1;
  wire prbs_rdlvl_start_reg_2;
  wire prech_done;
  wire \prech_done_dly_r_reg[15]_srl16_n_0 ;
  wire prech_done_pre;
  wire prech_pending_r;
  wire prech_pending_r_i_1_n_0;
  wire prech_pending_r_i_2_n_0;
  wire prech_pending_r_i_3_n_0;
  wire prech_pending_r_i_4_n_0;
  wire prech_pending_r_i_5_n_0;
  wire prech_pending_r_i_6_n_0;
  wire prech_req;
  wire prech_req_posedge_r0;
  wire prech_req_posedge_r_reg_0;
  wire prech_req_posedge_r_reg_1;
  wire prech_req_r;
  wire pwron_ce_r;
  wire pwron_ce_r_i_1_n_0;
  wire pwron_ce_r_i_2_n_0;
  wire \rd_addr_reg[1] ;
  wire [0:0]\rd_addr_reg[3] ;
  wire \rd_addr_reg[7] ;
  wire \rd_addr_reg[7]_0 ;
  wire rdlvl_last_byte_done;
  wire rdlvl_last_byte_done_r;
  wire rdlvl_pi_incdec;
  wire rdlvl_prech_req;
  wire [14:14]rdlvl_start_dly0_r;
  wire \rdlvl_start_dly0_r_reg[13]_srl14_n_0 ;
  wire \rdlvl_start_dly0_r_reg[14]_0 ;
  wire rdlvl_start_pre;
  wire rdlvl_start_pre_i_1_n_0;
  wire rdlvl_stg1_done_r1;
  wire rdlvl_stg1_rank_done;
  wire rdlvl_stg1_start_i_1_n_0;
  wire rdlvl_stg1_start_i_2_n_0;
  wire rdlvl_stg1_start_int;
  wire rdlvl_stg1_start_int_i_1_n_0;
  wire rdlvl_stg1_start_int_i_2_n_0;
  wire rdlvl_stg1_start_int_reg_0;
  wire rdlvl_stg1_start_reg_0;
  wire read_calib_i_1_n_0;
  wire [0:0]\read_fifo.tail_r ;
  wire \read_fifo.tail_r_reg[0] ;
  wire reg_ctrl_cnt_r;
  wire \reg_ctrl_cnt_r[3]_i_1_n_0 ;
  wire [3:0]reg_ctrl_cnt_r_reg;
  wire reset_rd_addr;
  wire reset_rd_addr0;
  wire reset_rd_addr_r1;
  wire \row_cnt_victim_rotate.complex_row_cnt[0]_i_1_n_0 ;
  wire \row_cnt_victim_rotate.complex_row_cnt[1]_i_1_n_0 ;
  wire \row_cnt_victim_rotate.complex_row_cnt[2]_i_1_n_0 ;
  wire \row_cnt_victim_rotate.complex_row_cnt[3]_i_1_n_0 ;
  wire \row_cnt_victim_rotate.complex_row_cnt[3]_i_2_n_0 ;
  wire \row_cnt_victim_rotate.complex_row_cnt[4]_i_1_n_0 ;
  wire \row_cnt_victim_rotate.complex_row_cnt[4]_i_3_n_0 ;
  wire \row_cnt_victim_rotate.complex_row_cnt[4]_i_4_n_0 ;
  wire \row_cnt_victim_rotate.complex_row_cnt[4]_i_5_n_0 ;
  wire \row_cnt_victim_rotate.complex_row_cnt[4]_i_6_n_0 ;
  wire \row_cnt_victim_rotate.complex_row_cnt[4]_i_7_n_0 ;
  wire \row_cnt_victim_rotate.complex_row_cnt[4]_i_8_n_0 ;
  wire \row_cnt_victim_rotate.complex_row_cnt[4]_i_9_n_0 ;
  wire \row_cnt_victim_rotate.complex_row_cnt[5]_i_1_n_0 ;
  wire \row_cnt_victim_rotate.complex_row_cnt[5]_i_2_n_0 ;
  wire \row_cnt_victim_rotate.complex_row_cnt[6]_i_1_n_0 ;
  wire \row_cnt_victim_rotate.complex_row_cnt[7]_i_1_n_0 ;
  wire \row_cnt_victim_rotate.complex_row_cnt[7]_i_2_n_0 ;
  wire \row_cnt_victim_rotate.complex_row_cnt[7]_i_3_n_0 ;
  wire \row_cnt_victim_rotate.complex_row_cnt_reg[1]_0 ;
  wire \row_cnt_victim_rotate.complex_row_cnt_reg[2]_0 ;
  wire \row_cnt_victim_rotate.complex_row_cnt_reg[3]_0 ;
  wire \row_cnt_victim_rotate.complex_row_cnt_reg[6]_0 ;
  wire \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] ;
  wire \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1] ;
  wire \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2] ;
  wire \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3] ;
  wire \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4] ;
  wire \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5] ;
  wire \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6] ;
  wire \row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[7] ;
  wire \samples_cnt_r_reg[11] ;
  wire stg1_wr_done;
  wire \stg1_wr_rd_cnt[0]_i_1_n_0 ;
  wire \stg1_wr_rd_cnt[1]_i_1_n_0 ;
  wire \stg1_wr_rd_cnt[2]_i_1_n_0 ;
  wire \stg1_wr_rd_cnt[3]_i_1_n_0 ;
  wire \stg1_wr_rd_cnt[3]_i_2_n_0 ;
  wire \stg1_wr_rd_cnt[4]_i_1_n_0 ;
  wire \stg1_wr_rd_cnt[4]_i_3_n_0 ;
  wire \stg1_wr_rd_cnt[4]_i_4_n_0 ;
  wire \stg1_wr_rd_cnt[5]_i_1_n_0 ;
  wire \stg1_wr_rd_cnt[5]_i_2_n_0 ;
  wire \stg1_wr_rd_cnt[6]_i_1_n_0 ;
  wire \stg1_wr_rd_cnt[6]_i_2_n_0 ;
  wire \stg1_wr_rd_cnt[7]_i_1_n_0 ;
  wire \stg1_wr_rd_cnt[8]_i_1_n_0 ;
  wire \stg1_wr_rd_cnt[8]_i_2_n_0 ;
  wire \stg1_wr_rd_cnt[8]_i_3_n_0 ;
  wire \stg1_wr_rd_cnt[8]_i_4_n_0 ;
  wire \stg1_wr_rd_cnt[8]_i_5_n_0 ;
  wire \stg1_wr_rd_cnt[8]_i_6_n_0 ;
  wire \stg1_wr_rd_cnt_reg[3]_0 ;
  wire \stg1_wr_rd_cnt_reg_n_0_[0] ;
  wire \stg1_wr_rd_cnt_reg_n_0_[1] ;
  wire \stg1_wr_rd_cnt_reg_n_0_[2] ;
  wire \stg1_wr_rd_cnt_reg_n_0_[3] ;
  wire \stg1_wr_rd_cnt_reg_n_0_[4] ;
  wire \stg1_wr_rd_cnt_reg_n_0_[5] ;
  wire \stg1_wr_rd_cnt_reg_n_0_[6] ;
  wire \stg1_wr_rd_cnt_reg_n_0_[7] ;
  wire \stg1_wr_rd_cnt_reg_n_0_[8] ;
  wire \victim_sel[0]_i_1_n_0 ;
  wire \victim_sel[0]_i_2_n_0 ;
  wire \victim_sel[1]_i_1_n_0 ;
  wire \victim_sel[1]_i_2_n_0 ;
  wire \victim_sel[2]_i_1_n_0 ;
  wire \victim_sel[2]_i_2_n_0 ;
  wire \victim_sel[2]_i_3_n_0 ;
  wire \victim_sel[2]_i_4_n_0 ;
  wire [0:0]\victim_sel_reg[0]_0 ;
  wire \victim_sel_reg_n_0_[0] ;
  wire \victim_sel_reg_n_0_[1] ;
  wire \victim_sel_reg_n_0_[2] ;
  wire wl_sm_start;
  wire wl_sm_start_reg_0;
  wire \wr_done_victim_rotate.complex_row0_wr_done_i_1_n_0 ;
  wire \wr_done_victim_rotate.complex_row0_wr_done_i_3_n_0 ;
  wire \wr_done_victim_rotate.complex_row1_wr_done_i_1_n_0 ;
  wire wr_level_done_r5;
  wire wr_level_dqs_asrt;
  wire wr_level_dqs_asrt_i_1_n_0;
  wire wr_level_dqs_asrt_r1;
  wire wr_lvl_start_i_1_n_0;
  wire wr_lvl_start_reg_0;
  wire wr_victim_inc;
  wire wr_victim_inc0;
  wire wr_victim_inc_i_2_n_0;
  wire wr_victim_inc_i_3_n_0;
  wire [2:0]wr_victim_sel;
  wire \wr_victim_sel[0]_i_1_n_0 ;
  wire \wr_victim_sel[1]_i_1_n_0 ;
  wire \wr_victim_sel[2]_i_1_n_0 ;
  wire \wr_victim_sel[2]_i_3_n_0 ;
  wire [2:0]wr_victim_sel_ocal;
  wire \wr_victim_sel_ocal[0]_i_1_n_0 ;
  wire \wr_victim_sel_ocal[1]_i_1_n_0 ;
  wire \wr_victim_sel_ocal[2]_i_1_n_0 ;
  wire \wr_victim_sel_ocal[2]_i_2_n_0 ;
  wire wrcal_final_chk;
  wire wrcal_final_chk_i_1_n_0;
  wire wrcal_final_chk_i_2_n_0;
  wire wrcal_prech_req;
  wire wrcal_rd_wait;
  wire wrcal_rd_wait_i_1_n_0;
  wire wrcal_reads;
  wire wrcal_reads05_out;
  wire \wrcal_reads[0]_i_1_n_0 ;
  wire \wrcal_reads[1]_i_1_n_0 ;
  wire \wrcal_reads[2]_i_1_n_0 ;
  wire \wrcal_reads[3]_i_1_n_0 ;
  wire \wrcal_reads[4]_i_1_n_0 ;
  wire \wrcal_reads[5]_i_1_n_0 ;
  wire \wrcal_reads[6]_i_1_n_0 ;
  wire \wrcal_reads[7]_i_10_n_0 ;
  wire \wrcal_reads[7]_i_2_n_0 ;
  wire \wrcal_reads[7]_i_3_n_0 ;
  wire \wrcal_reads[7]_i_4_n_0 ;
  wire \wrcal_reads[7]_i_5_n_0 ;
  wire \wrcal_reads[7]_i_6_n_0 ;
  wire \wrcal_reads[7]_i_7_n_0 ;
  wire \wrcal_reads[7]_i_8_n_0 ;
  wire \wrcal_reads_reg_n_0_[0] ;
  wire \wrcal_reads_reg_n_0_[1] ;
  wire \wrcal_reads_reg_n_0_[2] ;
  wire \wrcal_reads_reg_n_0_[3] ;
  wire \wrcal_reads_reg_n_0_[4] ;
  wire \wrcal_reads_reg_n_0_[5] ;
  wire \wrcal_reads_reg_n_0_[6] ;
  wire \wrcal_reads_reg_n_0_[7] ;
  wire wrcal_resume_r;
  wire wrcal_resume_w;
  wire wrcal_sanity_chk;
  wire [5:5]wrcal_start_dly_r;
  wire \wrcal_start_dly_r_reg[4]_srl5_n_0 ;
  wire wrcal_start_i_1_n_0;
  wire wrcal_start_pre;
  wire wrcal_start_reg_0;
  wire [3:2]wrcal_wr_cnt0;
  wire \wrcal_wr_cnt[0]_i_1_n_0 ;
  wire \wrcal_wr_cnt[1]_i_1_n_0 ;
  wire \wrcal_wr_cnt[3]_i_1_n_0 ;
  wire \wrcal_wr_cnt[3]_i_2_n_0 ;
  wire \wrcal_wr_cnt[3]_i_4_n_0 ;
  wire [3:0]wrcal_wr_cnt_reg;
  wire \wrdq_div1_4to1_wrcal_first.phy_wrdata[190]_i_1_n_0 ;
  wire \wrdq_div1_4to1_wrcal_first.phy_wrdata[511]_i_1_n_0 ;
  wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[120]_0 ;
  wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[121]_0 ;
  wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[124]_0 ;
  wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[125]_0 ;
  wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[184]_0 ;
  wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[186]_0 ;
  wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187]_0 ;
  wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187]_1 ;
  wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[188]_0 ;
  wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[190]_0 ;
  wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[191]_0 ;
  wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[248]_0 ;
  wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[249]_0 ;
  wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[251]_0 ;
  wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[252]_0 ;
  wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[253]_0 ;
  wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[255]_0 ;
  wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[312]_0 ;
  wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[315]_0 ;
  wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[316]_0 ;
  wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[319]_0 ;
  wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[376]_0 ;
  wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[377]_0 ;
  wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[378]_0 ;
  wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[380]_0 ;
  wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[381]_0 ;
  wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[382]_0 ;
  wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[440]_0 ;
  wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[441]_0 ;
  wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[442]_0 ;
  wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[443]_0 ;
  wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[444]_0 ;
  wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[445]_0 ;
  wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[446]_0 ;
  wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[447]_0 ;
  wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[505]_0 ;
  wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[506]_0 ;
  wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[507]_0 ;
  wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[508]_0 ;
  wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[509]_0 ;
  wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[510]_0 ;
  wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0 ;
  wire [0:0]\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 ;
  wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57]_0 ;
  wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[58]_0 ;
  wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[61]_0 ;
  wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[62]_0 ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[448] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[450] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[451] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[452] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[453] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[454] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[455] ;
  wire [63:0]\write_buffer.wr_buf_out_data_reg[455]_0 ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[456] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[457] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[458] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[459] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[460] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[461] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[462] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[463] ;
  wire [63:0]\write_buffer.wr_buf_out_data_reg[463]_0 ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[464] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[465] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[466] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[467] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[468] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[469] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[470] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[471] ;
  wire [63:0]\write_buffer.wr_buf_out_data_reg[471]_0 ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[472] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[473] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[474] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[475] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[476] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[477] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[478] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[479] ;
  wire [63:0]\write_buffer.wr_buf_out_data_reg[479]_0 ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[480] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[481] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[482] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[483] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[484] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[485] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[486] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[487] ;
  wire [63:0]\write_buffer.wr_buf_out_data_reg[487]_0 ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[488] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[489] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[490] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[491] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[492] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[493] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[494] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[495] ;
  wire [63:0]\write_buffer.wr_buf_out_data_reg[495]_0 ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[496] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[497] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[498] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[499] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[500] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[501] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[502] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[503] ;
  wire [63:0]\write_buffer.wr_buf_out_data_reg[503]_0 ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[504] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[505] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[506] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[507] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[508] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[509] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[510] ;
  wire [7:0]\write_buffer.wr_buf_out_data_reg[511] ;
  wire [63:0]\write_buffer.wr_buf_out_data_reg[511]_0 ;
  wire write_calib_i_1_n_0;
  wire write_calib_i_2_n_0;
  wire write_calib_reg_0;
  wire wrlvl_active;
  wire wrlvl_active_i_1_n_0;
  wire wrlvl_active_r1;
  wire wrlvl_byte_redo;
  wire wrlvl_done_r;
  wire wrlvl_done_r1;
  wire wrlvl_done_r_reg_0;
  wire wrlvl_final_if_rst;
  wire wrlvl_final_if_rst_i_1_n_0;
  wire wrlvl_final_if_rst_i_2_n_0;
  wire wrlvl_final_if_rst_i_3_n_0;
  wire wrlvl_odt;
  wire wrlvl_odt_ctl;
  wire wrlvl_odt_ctl_i_1_n_0;
  wire wrlvl_odt_ctl_i_2_n_0;
  wire wrlvl_rank_done;
  wire wrlvl_rank_done_r1;
  wire wrlvl_rank_done_r6_reg_srl5_n_0;
  wire wrlvl_rank_done_r7;

  LUT6 #(
    .INIT(64'h00000000AAAB0000)) 
    \DDR3_1rank.phy_int_cs_n[1]_i_1 
       (.I0(\DDR3_1rank.phy_int_cs_n[1]_i_2_n_0 ),
        .I1(Q),
        .I2(\init_state_r_reg_n_0_[1] ),
        .I3(prbs_rdlvl_start_i_3_n_0),
        .I4(\DDR3_1rank.phy_int_cs_n[1]_i_3_n_0 ),
        .I5(\cnt_dllk_zqinit_r[7]_i_1_n_0 ),
        .O(\DDR3_1rank.phy_int_cs_n[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair425" *) 
  LUT5 #(
    .INIT(32'hFFFFDFFF)) 
    \DDR3_1rank.phy_int_cs_n[1]_i_10 
       (.I0(\init_state_r_reg_n_0_[4] ),
        .I1(init_state_r),
        .I2(\init_state_r_reg_n_0_[5] ),
        .I3(\init_state_r_reg_n_0_[2] ),
        .I4(\init_state_r_reg_n_0_[3] ),
        .O(\DDR3_1rank.phy_int_cs_n[1]_i_10_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair486" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \DDR3_1rank.phy_int_cs_n[1]_i_2 
       (.I0(phy_wrdata_en),
        .I1(\calib_cmd[2]_i_3_n_0 ),
        .O(\DDR3_1rank.phy_int_cs_n[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000400000000)) 
    \DDR3_1rank.phy_int_cs_n[1]_i_3 
       (.I0(\DDR3_1rank.phy_int_cs_n[1]_i_4_n_0 ),
        .I1(\num_refresh[3]_i_4_n_0 ),
        .I2(\DDR3_1rank.phy_int_cs_n[1]_i_5_n_0 ),
        .I3(complex_row1_rd_done_i_2_n_0),
        .I4(\DDR3_1rank.phy_int_cs_n[1]_i_6_n_0 ),
        .I5(\DDR3_1rank.phy_int_cs_n[1]_i_7_n_0 ),
        .O(\DDR3_1rank.phy_int_cs_n[1]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hBAAAFAAABFAAFFAA)) 
    \DDR3_1rank.phy_int_cs_n[1]_i_4 
       (.I0(\DDR3_1rank.phy_int_cs_n[1]_i_8_n_0 ),
        .I1(complex_oclkdelay_calib_start_int_i_2_n_0),
        .I2(Q),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(\DDR3_1rank.phy_int_cs_n[1]_i_9_n_0 ),
        .I5(\DDR3_1rank.phy_int_cs_n[1]_i_10_n_0 ),
        .O(\DDR3_1rank.phy_int_cs_n[1]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h0000000300020000)) 
    \DDR3_1rank.phy_int_cs_n[1]_i_5 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(Q),
        .I2(\init_state_r[3]_i_6_n_0 ),
        .I3(\init_state_r_reg_n_0_[4] ),
        .I4(\init_state_r_reg_n_0_[2] ),
        .I5(\init_state_r_reg_n_0_[3] ),
        .O(\DDR3_1rank.phy_int_cs_n[1]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h0000000040000000)) 
    \DDR3_1rank.phy_int_cs_n[1]_i_6 
       (.I0(init_state_r),
        .I1(\init_state_r_reg_n_0_[5] ),
        .I2(\init_state_r_reg_n_0_[2] ),
        .I3(\init_state_r_reg_n_0_[4] ),
        .I4(\init_state_r_reg_n_0_[3] ),
        .I5(prbs_rdlvl_start_i_2_n_0),
        .O(\DDR3_1rank.phy_int_cs_n[1]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h5151515151511151)) 
    \DDR3_1rank.phy_int_cs_n[1]_i_7 
       (.I0(\cnt_init_mr_r[1]_i_2_n_0 ),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(mpr_rdlvl_start_i_2_n_0),
        .I3(Q),
        .I4(\wrcal_reads[7]_i_7_n_0 ),
        .I5(\wrcal_reads[7]_i_4_n_0 ),
        .O(\DDR3_1rank.phy_int_cs_n[1]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h4004000000000000)) 
    \DDR3_1rank.phy_int_cs_n[1]_i_8 
       (.I0(\init_state_r[3]_i_6_n_0 ),
        .I1(\init_state_r_reg_n_0_[3] ),
        .I2(\init_state_r_reg_n_0_[1] ),
        .I3(\init_state_r_reg_n_0_[2] ),
        .I4(\init_state_r_reg_n_0_[4] ),
        .I5(Q),
        .O(\DDR3_1rank.phy_int_cs_n[1]_i_8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair423" *) 
  LUT5 #(
    .INIT(32'hFFEFFFFF)) 
    \DDR3_1rank.phy_int_cs_n[1]_i_9 
       (.I0(\init_state_r_reg_n_0_[5] ),
        .I1(init_state_r),
        .I2(\init_state_r_reg_n_0_[4] ),
        .I3(\init_state_r_reg_n_0_[3] ),
        .I4(\init_state_r_reg_n_0_[2] ),
        .O(\DDR3_1rank.phy_int_cs_n[1]_i_9_n_0 ));
  FDSE \DDR3_1rank.phy_int_cs_n_reg[1] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\DDR3_1rank.phy_int_cs_n[1]_i_1_n_0 ),
        .Q(phy_cs_n),
        .S(\victim_sel_reg[0]_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \FSM_sequential_wl_state_r[0]_i_13 
       (.I0(wl_sm_start),
        .I1(wr_level_done_r5),
        .O(wl_sm_start_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair532" *) 
  LUT2 #(
    .INIT(4'h2)) 
    app_rd_data_valid_INST_0
       (.I0(init_complete_r1_timing_reg_0),
        .I1(app_rd_data_valid_0),
        .O(app_rd_data_valid));
  LUT2 #(
    .INIT(4'h2)) 
    app_rd_data_valid_INST_0_i_1
       (.I0(init_complete_r1_timing),
        .I1(if_empty),
        .O(init_complete_r1_timing_reg_0));
  LUT5 #(
    .INIT(32'h00000023)) 
    \back_to_back_reads_4_1.num_reads[0]_i_1 
       (.I0(num_reads[1]),
        .I1(num_reads[0]),
        .I2(pi_dqs_found_start_i_2_n_0),
        .I3(\init_state_r_reg[4]_1 ),
        .I4(write_calib_reg_0),
        .O(\back_to_back_reads_4_1.num_reads[0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00000089)) 
    \back_to_back_reads_4_1.num_reads[1]_i_1 
       (.I0(num_reads[1]),
        .I1(num_reads[0]),
        .I2(pi_dqs_found_start_i_2_n_0),
        .I3(\init_state_r_reg[4]_1 ),
        .I4(\rd_addr_reg[7] ),
        .O(\back_to_back_reads_4_1.num_reads[1]_i_1_n_0 ));
  FDRE \back_to_back_reads_4_1.num_reads_reg[0] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\back_to_back_reads_4_1.num_reads[0]_i_1_n_0 ),
        .Q(num_reads[0]),
        .R(1'b0));
  FDRE \back_to_back_reads_4_1.num_reads_reg[1] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\back_to_back_reads_4_1.num_reads[1]_i_1_n_0 ),
        .Q(num_reads[1]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h000000000000EEEF)) 
    burst_addr_r_i_1
       (.I0(burst_addr_r_i_2_n_0),
        .I1(burst_addr_r_i_3_n_0),
        .I2(p_17_in),
        .I3(\DDR3_1rank.phy_int_cs_n[1]_i_2_n_0 ),
        .I4(ddr3_lm_done_r_reg_0),
        .I5(\rd_addr_reg[7] ),
        .O(burst_addr_r_i_1_n_0));
  LUT6 #(
    .INIT(64'h0100000004000000)) 
    burst_addr_r_i_2
       (.I0(\cnt_init_mr_r[0]_i_2_n_0 ),
        .I1(\init_state_r_reg_n_0_[4] ),
        .I2(init_state_r),
        .I3(\init_state_r_reg_n_0_[5] ),
        .I4(Q),
        .I5(\init_state_r_reg_n_0_[1] ),
        .O(burst_addr_r_i_2_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFF10000313)) 
    burst_addr_r_i_3
       (.I0(Q),
        .I1(\wrcal_reads[7]_i_7_n_0 ),
        .I2(\init_state_r_reg_n_0_[1] ),
        .I3(\init_state_r_reg_n_0_[2] ),
        .I4(\init_state_r_reg_n_0_[3] ),
        .I5(p_0_in0_in),
        .O(burst_addr_r_i_3_n_0));
  FDRE burst_addr_r_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(burst_addr_r_i_1_n_0),
        .Q(p_17_in),
        .R(1'b0));
  FDRE \calib_cke_reg[0] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(cnt_pwron_cke_done_r),
        .Q(calib_cke),
        .R(\victim_sel_reg[0]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair510" *) 
  LUT2 #(
    .INIT(4'hD)) 
    \calib_cmd[0]_i_1 
       (.I0(\calib_cmd[2]_i_2_n_0 ),
        .I1(\calib_cmd[2]_i_3_n_0 ),
        .O(\calib_cmd[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair531" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \calib_cmd[1]_i_1 
       (.I0(\calib_cmd[2]_i_3_n_0 ),
        .I1(\calib_cmd[2]_i_2_n_0 ),
        .O(\calib_cmd[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair531" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \calib_cmd[2]_i_1 
       (.I0(\calib_cmd[2]_i_2_n_0 ),
        .I1(\calib_cmd[2]_i_3_n_0 ),
        .O(\calib_cmd[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair455" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \calib_cmd[2]_i_2 
       (.I0(wr_level_dqs_asrt),
        .I1(phy_wrdata_en),
        .O(\calib_cmd[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFF45FFFF)) 
    \calib_cmd[2]_i_3 
       (.I0(rdlvl_pi_incdec),
        .I1(\calib_cmd[2]_i_4_n_0 ),
        .I2(rdlvl_stg1_start_i_2_n_0),
        .I3(\calib_cmd[2]_i_5_n_0 ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_8_n_0 ),
        .I5(burst_addr_r_i_2_n_0),
        .O(\calib_cmd[2]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0000000001000000)) 
    \calib_cmd[2]_i_4 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(init_state_r),
        .I2(\init_state_r_reg_n_0_[4] ),
        .I3(\init_state_r_reg_n_0_[5] ),
        .I4(Q),
        .I5(\init_state_r[4]_i_4_n_0 ),
        .O(\calib_cmd[2]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000020400)) 
    \calib_cmd[2]_i_5 
       (.I0(\init_state_r_reg_n_0_[2] ),
        .I1(\init_state_r_reg_n_0_[3] ),
        .I2(complex_act_start_i_2_n_0),
        .I3(\init_state_r_reg_n_0_[4] ),
        .I4(\init_state_r_reg_n_0_[1] ),
        .I5(Q),
        .O(\calib_cmd[2]_i_5_n_0 ));
  FDRE \calib_cmd_reg[0] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\calib_cmd[0]_i_1_n_0 ),
        .Q(calib_cmd[0]),
        .R(1'b0));
  FDRE \calib_cmd_reg[1] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\calib_cmd[1]_i_1_n_0 ),
        .Q(calib_cmd[1]),
        .R(1'b0));
  FDRE \calib_cmd_reg[2] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\calib_cmd[2]_i_1_n_0 ),
        .Q(calib_cmd[2]),
        .R(1'b0));
  LUT2 #(
    .INIT(4'h8)) 
    calib_ctl_wren_i_1
       (.I0(cnt_pwron_cke_done_r),
        .I1(\calib_seq_reg[0]_0 ),
        .O(p_115_in));
  FDRE calib_ctl_wren_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(p_115_in),
        .Q(calib_cmd_wren),
        .R(\en_cnt_div4.enable_wrlvl_cnt_reg[2]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair506" *) 
  LUT3 #(
    .INIT(8'hD0)) 
    \calib_data_offset_0[3]_i_1 
       (.I0(\calib_cmd[2]_i_2_n_0 ),
        .I1(\calib_cmd[2]_i_3_n_0 ),
        .I2(\calib_data_offset_0[3]_i_2_n_0 ),
        .O(\calib_data_offset_0[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hA0A2A080FFFFFFFF)) 
    \calib_data_offset_0[3]_i_2 
       (.I0(pi_calib_done),
        .I1(pi_dqs_found_done_r1),
        .I2(\calib_data_offset_0_reg[3]_0 ),
        .I3(init_dqsfound_done_r2),
        .I4(\calib_data_offset_0_reg[3]_1 ),
        .I5(\calib_cmd[2]_i_2_n_0 ),
        .O(\calib_data_offset_0[3]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'h7F)) 
    \calib_data_offset_0[5]_i_1 
       (.I0(\calib_cmd[2]_i_3_n_0 ),
        .I1(\calib_cmd[2]_i_2_n_0 ),
        .I2(pi_calib_done),
        .O(\calib_data_offset_0[5]_i_1_n_0 ));
  FDRE \calib_data_offset_0_reg[0] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\calib_data_offset_0_reg[0]_0 ),
        .Q(calib_data_offset_0[0]),
        .R(\calib_data_offset_0[5]_i_1_n_0 ));
  FDRE \calib_data_offset_0_reg[1] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\calib_data_offset_0_reg[1]_0 ),
        .Q(calib_data_offset_0[1]),
        .R(\calib_data_offset_0[5]_i_1_n_0 ));
  FDRE \calib_data_offset_0_reg[2] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\calib_data_offset_0_reg[2]_0 ),
        .Q(calib_data_offset_0[2]),
        .R(\calib_data_offset_0[5]_i_1_n_0 ));
  FDRE \calib_data_offset_0_reg[3] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\calib_data_offset_0[3]_i_1_n_0 ),
        .Q(calib_data_offset_0[3]),
        .R(1'b0));
  FDRE \calib_data_offset_0_reg[4] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\calib_data_offset_0_reg[4]_0 ),
        .Q(calib_data_offset_0[4]),
        .R(\calib_data_offset_0[5]_i_1_n_0 ));
  FDRE \calib_data_offset_0_reg[5] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\calib_data_offset_0_reg[5]_0 ),
        .Q(calib_data_offset_0[5]),
        .R(\calib_data_offset_0[5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair510" *) 
  LUT3 #(
    .INIT(8'hD0)) 
    \calib_data_offset_1[3]_i_1 
       (.I0(\calib_cmd[2]_i_2_n_0 ),
        .I1(\calib_cmd[2]_i_3_n_0 ),
        .I2(\calib_data_offset_1[3]_i_2_n_0 ),
        .O(\calib_data_offset_1[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hA0A2A080FFFFFFFF)) 
    \calib_data_offset_1[3]_i_2 
       (.I0(pi_calib_done),
        .I1(pi_dqs_found_done_r1),
        .I2(\calib_data_offset_1_reg[3]_0 ),
        .I3(init_dqsfound_done_r2),
        .I4(\calib_data_offset_1_reg[3]_1 ),
        .I5(\calib_cmd[2]_i_2_n_0 ),
        .O(\calib_data_offset_1[3]_i_2_n_0 ));
  FDRE \calib_data_offset_1_reg[0] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\calib_data_offset_1_reg[0]_0 ),
        .Q(calib_data_offset_1[0]),
        .R(\calib_data_offset_0[5]_i_1_n_0 ));
  FDRE \calib_data_offset_1_reg[1] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\calib_data_offset_1_reg[1]_0 ),
        .Q(calib_data_offset_1[1]),
        .R(\calib_data_offset_0[5]_i_1_n_0 ));
  FDRE \calib_data_offset_1_reg[2] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\calib_data_offset_1_reg[2]_0 ),
        .Q(calib_data_offset_1[2]),
        .R(\calib_data_offset_0[5]_i_1_n_0 ));
  FDRE \calib_data_offset_1_reg[3] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\calib_data_offset_1[3]_i_1_n_0 ),
        .Q(calib_data_offset_1[3]),
        .R(1'b0));
  FDRE \calib_data_offset_1_reg[4] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\calib_data_offset_1_reg[4]_0 ),
        .Q(calib_data_offset_1[4]),
        .R(\calib_data_offset_0[5]_i_1_n_0 ));
  FDRE \calib_data_offset_1_reg[5] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\calib_data_offset_1_reg[5]_0 ),
        .Q(calib_data_offset_1[5]),
        .R(\calib_data_offset_0[5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair506" *) 
  LUT3 #(
    .INIT(8'hD0)) 
    \calib_data_offset_2[3]_i_1 
       (.I0(\calib_cmd[2]_i_2_n_0 ),
        .I1(\calib_cmd[2]_i_3_n_0 ),
        .I2(\calib_data_offset_2[3]_i_2_n_0 ),
        .O(\calib_data_offset_2[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hA0A2A080FFFFFFFF)) 
    \calib_data_offset_2[3]_i_2 
       (.I0(pi_calib_done),
        .I1(pi_dqs_found_done_r1),
        .I2(\calib_data_offset_2_reg[3]_0 ),
        .I3(init_dqsfound_done_r2),
        .I4(\calib_data_offset_2_reg[3]_1 ),
        .I5(\calib_cmd[2]_i_2_n_0 ),
        .O(\calib_data_offset_2[3]_i_2_n_0 ));
  FDRE \calib_data_offset_2_reg[0] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\calib_data_offset_2_reg[0]_0 ),
        .Q(calib_data_offset_2[0]),
        .R(\calib_data_offset_0[5]_i_1_n_0 ));
  FDRE \calib_data_offset_2_reg[1] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\calib_data_offset_2_reg[1]_0 ),
        .Q(calib_data_offset_2[1]),
        .R(\calib_data_offset_0[5]_i_1_n_0 ));
  FDRE \calib_data_offset_2_reg[2] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\calib_data_offset_2_reg[2]_0 ),
        .Q(calib_data_offset_2[2]),
        .R(\calib_data_offset_0[5]_i_1_n_0 ));
  FDRE \calib_data_offset_2_reg[3] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\calib_data_offset_2[3]_i_1_n_0 ),
        .Q(calib_data_offset_2[3]),
        .R(1'b0));
  FDRE \calib_data_offset_2_reg[4] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\calib_data_offset_2_reg[4]_0 ),
        .Q(calib_data_offset_2[4]),
        .R(\calib_data_offset_0[5]_i_1_n_0 ));
  FDRE \calib_data_offset_2_reg[5] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\calib_data_offset_2_reg[5]_0 ),
        .Q(calib_data_offset_2[5]),
        .R(\calib_data_offset_0[5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair455" *) 
  LUT4 #(
    .INIT(16'h00E0)) 
    \calib_odt[0]_i_1 
       (.I0(\calib_odt[0]_i_2_n_0 ),
        .I1(phy_wrdata_en),
        .I2(\gen_rnk[0].mr1_r_reg_n_0_[0][1] ),
        .I3(write_calib_reg_0),
        .O(\calib_odt[0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \calib_odt[0]_i_2 
       (.I0(stg1_wr_done),
        .I1(complex_ocal_odt_ext),
        .I2(complex_odt_ext),
        .I3(\complex_address[9]_i_3_n_0 ),
        .I4(\calib_odt[0]_i_3_n_0 ),
        .O(\calib_odt[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hC0005500C00055FF)) 
    \calib_odt[0]_i_3 
       (.I0(calib_wrdata_en_i_2_n_0),
        .I1(\odd_cwl.phy_cas_n[1]_i_4_n_0 ),
        .I2(wrlvl_odt),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(Q),
        .I5(complex_ocal_odt_ext_i_3_n_0),
        .O(\calib_odt[0]_i_3_n_0 ));
  FDRE \calib_odt_reg[0] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\calib_odt[0]_i_1_n_0 ),
        .Q(calib_odt),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair450" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \calib_seq[0]_i_1 
       (.I0(cnt_pwron_cke_done_r),
        .I1(\calib_seq_reg[0]_0 ),
        .I2(\calib_seq_reg[1]_0 [9]),
        .O(\calib_seq[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair450" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \calib_seq[1]_i_1 
       (.I0(\calib_seq_reg[1]_0 [9]),
        .I1(cnt_pwron_cke_done_r),
        .I2(\calib_seq_reg[0]_0 ),
        .I3(\calib_seq_reg[1]_0 [10]),
        .O(\calib_seq[1]_i_1_n_0 ));
  FDRE \calib_seq_reg[0] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\calib_seq[0]_i_1_n_0 ),
        .Q(\calib_seq_reg[1]_0 [9]),
        .R(\victim_sel_reg[0]_0 ));
  FDRE \calib_seq_reg[1] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\calib_seq[1]_i_1_n_0 ),
        .Q(\calib_seq_reg[1]_0 [10]),
        .R(\victim_sel_reg[0]_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFCCCFCCDD)) 
    calib_wrdata_en_i_1
       (.I0(prbs_rdlvl_start_i_3_n_0),
        .I1(p_0_in0_in),
        .I2(calib_wrdata_en_i_2_n_0),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(Q),
        .I5(\stg1_wr_rd_cnt[8]_i_5_n_0 ),
        .O(phy_wrdata_en));
  (* SOFT_HLUTNM = "soft_lutpair388" *) 
  LUT5 #(
    .INIT(32'hFFFFFEFF)) 
    calib_wrdata_en_i_2
       (.I0(\init_state_r_reg_n_0_[2] ),
        .I1(\init_state_r_reg_n_0_[3] ),
        .I2(init_state_r),
        .I3(\init_state_r_reg_n_0_[5] ),
        .I4(\init_state_r_reg_n_0_[4] ),
        .O(calib_wrdata_en_i_2_n_0));
  FDRE calib_wrdata_en_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(phy_wrdata_en),
        .Q(calib_wrdata_en),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000800000)) 
    cnt_cmd_done_m7_r_i_1
       (.I0(\cnt_cmd_r_reg_n_0_[5] ),
        .I1(\cnt_cmd_r_reg_n_0_[4] ),
        .I2(\cnt_cmd_r_reg_n_0_[3] ),
        .I3(\cnt_cmd_r_reg_n_0_[2] ),
        .I4(\cnt_cmd_r_reg_n_0_[6] ),
        .I5(cnt_cmd_done_m7_r_i_2_n_0),
        .O(cnt_cmd_done_m7_r_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair518" *) 
  LUT2 #(
    .INIT(4'hE)) 
    cnt_cmd_done_m7_r_i_2
       (.I0(\cnt_cmd_r_reg_n_0_[1] ),
        .I1(\cnt_cmd_r_reg_n_0_[0] ),
        .O(cnt_cmd_done_m7_r_i_2_n_0));
  FDRE cnt_cmd_done_m7_r_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(cnt_cmd_done_m7_r_i_1_n_0),
        .Q(cnt_cmd_done_m7_r),
        .R(1'b0));
  LUT2 #(
    .INIT(4'h8)) 
    cnt_cmd_done_r_i_1
       (.I0(\cnt_cmd_r[6]_i_4_n_0 ),
        .I1(\cnt_cmd_r_reg_n_0_[6] ),
        .O(cnt_cmd_done_r_i_1_n_0));
  FDRE cnt_cmd_done_r_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(cnt_cmd_done_r_i_1_n_0),
        .Q(cnt_cmd_done_r),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair520" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \cnt_cmd_r[0]_i_1 
       (.I0(\cnt_cmd_r_reg_n_0_[0] ),
        .O(\cnt_cmd_r[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair520" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cnt_cmd_r[1]_i_1 
       (.I0(\cnt_cmd_r_reg_n_0_[0] ),
        .I1(\cnt_cmd_r_reg_n_0_[1] ),
        .O(\cnt_cmd_r[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair518" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \cnt_cmd_r[2]_i_1 
       (.I0(\cnt_cmd_r_reg_n_0_[2] ),
        .I1(\cnt_cmd_r_reg_n_0_[0] ),
        .I2(\cnt_cmd_r_reg_n_0_[1] ),
        .O(\cnt_cmd_r[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair424" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \cnt_cmd_r[3]_i_1 
       (.I0(\cnt_cmd_r_reg_n_0_[3] ),
        .I1(\cnt_cmd_r_reg_n_0_[2] ),
        .I2(\cnt_cmd_r_reg_n_0_[1] ),
        .I3(\cnt_cmd_r_reg_n_0_[0] ),
        .O(\cnt_cmd_r[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair424" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \cnt_cmd_r[4]_i_1 
       (.I0(\cnt_cmd_r_reg_n_0_[4] ),
        .I1(\cnt_cmd_r_reg_n_0_[3] ),
        .I2(\cnt_cmd_r_reg_n_0_[0] ),
        .I3(\cnt_cmd_r_reg_n_0_[1] ),
        .I4(\cnt_cmd_r_reg_n_0_[2] ),
        .O(\cnt_cmd_r[4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAAAAAA)) 
    \cnt_cmd_r[5]_i_1 
       (.I0(\cnt_cmd_r_reg_n_0_[5] ),
        .I1(\cnt_cmd_r_reg_n_0_[2] ),
        .I2(\cnt_cmd_r_reg_n_0_[1] ),
        .I3(\cnt_cmd_r_reg_n_0_[0] ),
        .I4(\cnt_cmd_r_reg_n_0_[3] ),
        .I5(\cnt_cmd_r_reg_n_0_[4] ),
        .O(\cnt_cmd_r[5]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \cnt_cmd_r[6]_i_1 
       (.I0(init_state_r),
        .I1(\cnt_cmd_r[6]_i_3_n_0 ),
        .O(\cnt_cmd_r[6]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \cnt_cmd_r[6]_i_2 
       (.I0(\cnt_cmd_r_reg_n_0_[6] ),
        .I1(\cnt_cmd_r[6]_i_4_n_0 ),
        .O(\cnt_cmd_r[6]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFD7B8C3F9C7EDC7)) 
    \cnt_cmd_r[6]_i_3 
       (.I0(\init_state_r_reg_n_0_[3] ),
        .I1(Q),
        .I2(\init_state_r_reg_n_0_[5] ),
        .I3(\init_state_r_reg_n_0_[4] ),
        .I4(\init_state_r_reg_n_0_[2] ),
        .I5(\init_state_r_reg_n_0_[1] ),
        .O(\cnt_cmd_r[6]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \cnt_cmd_r[6]_i_4 
       (.I0(\cnt_cmd_r_reg_n_0_[3] ),
        .I1(\cnt_cmd_r_reg_n_0_[0] ),
        .I2(\cnt_cmd_r_reg_n_0_[1] ),
        .I3(\cnt_cmd_r_reg_n_0_[2] ),
        .I4(\cnt_cmd_r_reg_n_0_[4] ),
        .I5(\cnt_cmd_r_reg_n_0_[5] ),
        .O(\cnt_cmd_r[6]_i_4_n_0 ));
  FDRE \cnt_cmd_r_reg[0] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\cnt_cmd_r[0]_i_1_n_0 ),
        .Q(\cnt_cmd_r_reg_n_0_[0] ),
        .R(\cnt_cmd_r[6]_i_1_n_0 ));
  FDRE \cnt_cmd_r_reg[1] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\cnt_cmd_r[1]_i_1_n_0 ),
        .Q(\cnt_cmd_r_reg_n_0_[1] ),
        .R(\cnt_cmd_r[6]_i_1_n_0 ));
  FDRE \cnt_cmd_r_reg[2] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\cnt_cmd_r[2]_i_1_n_0 ),
        .Q(\cnt_cmd_r_reg_n_0_[2] ),
        .R(\cnt_cmd_r[6]_i_1_n_0 ));
  FDRE \cnt_cmd_r_reg[3] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\cnt_cmd_r[3]_i_1_n_0 ),
        .Q(\cnt_cmd_r_reg_n_0_[3] ),
        .R(\cnt_cmd_r[6]_i_1_n_0 ));
  FDRE \cnt_cmd_r_reg[4] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\cnt_cmd_r[4]_i_1_n_0 ),
        .Q(\cnt_cmd_r_reg_n_0_[4] ),
        .R(\cnt_cmd_r[6]_i_1_n_0 ));
  FDRE \cnt_cmd_r_reg[5] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\cnt_cmd_r[5]_i_1_n_0 ),
        .Q(\cnt_cmd_r_reg_n_0_[5] ),
        .R(\cnt_cmd_r[6]_i_1_n_0 ));
  FDRE \cnt_cmd_r_reg[6] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\cnt_cmd_r[6]_i_2_n_0 ),
        .Q(\cnt_cmd_r_reg_n_0_[6] ),
        .R(\cnt_cmd_r[6]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair471" *) 
  LUT4 #(
    .INIT(16'hEAAA)) 
    cnt_dllk_zqinit_done_r_i_1
       (.I0(cnt_dllk_zqinit_done_r),
        .I1(cnt_dllk_zqinit_r_reg[6]),
        .I2(mem_init_done_r_i_2_n_0),
        .I3(cnt_dllk_zqinit_r_reg[7]),
        .O(cnt_dllk_zqinit_done_r_i_1_n_0));
  FDRE cnt_dllk_zqinit_done_r_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(cnt_dllk_zqinit_done_r_i_1_n_0),
        .Q(cnt_dllk_zqinit_done_r),
        .R(\cnt_dllk_zqinit_r[7]_i_1_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \cnt_dllk_zqinit_r[0]_i_1 
       (.I0(cnt_dllk_zqinit_r_reg[0]),
        .O(p_0_in__4[0]));
  (* SOFT_HLUTNM = "soft_lutpair519" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cnt_dllk_zqinit_r[1]_i_1 
       (.I0(cnt_dllk_zqinit_r_reg[1]),
        .I1(cnt_dllk_zqinit_r_reg[0]),
        .O(p_0_in__4[1]));
  (* SOFT_HLUTNM = "soft_lutpair519" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \cnt_dllk_zqinit_r[2]_i_1 
       (.I0(cnt_dllk_zqinit_r_reg[2]),
        .I1(cnt_dllk_zqinit_r_reg[0]),
        .I2(cnt_dllk_zqinit_r_reg[1]),
        .O(p_0_in__4[2]));
  (* SOFT_HLUTNM = "soft_lutpair419" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \cnt_dllk_zqinit_r[3]_i_1 
       (.I0(cnt_dllk_zqinit_r_reg[3]),
        .I1(cnt_dllk_zqinit_r_reg[1]),
        .I2(cnt_dllk_zqinit_r_reg[0]),
        .I3(cnt_dllk_zqinit_r_reg[2]),
        .O(p_0_in__4[3]));
  (* SOFT_HLUTNM = "soft_lutpair419" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \cnt_dllk_zqinit_r[4]_i_1 
       (.I0(cnt_dllk_zqinit_r_reg[4]),
        .I1(cnt_dllk_zqinit_r_reg[2]),
        .I2(cnt_dllk_zqinit_r_reg[0]),
        .I3(cnt_dllk_zqinit_r_reg[1]),
        .I4(cnt_dllk_zqinit_r_reg[3]),
        .O(p_0_in__4[4]));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAAAAAA)) 
    \cnt_dllk_zqinit_r[5]_i_1 
       (.I0(cnt_dllk_zqinit_r_reg[5]),
        .I1(cnt_dllk_zqinit_r_reg[3]),
        .I2(cnt_dllk_zqinit_r_reg[1]),
        .I3(cnt_dllk_zqinit_r_reg[0]),
        .I4(cnt_dllk_zqinit_r_reg[2]),
        .I5(cnt_dllk_zqinit_r_reg[4]),
        .O(p_0_in__4[5]));
  LUT2 #(
    .INIT(4'h6)) 
    \cnt_dllk_zqinit_r[6]_i_1 
       (.I0(cnt_dllk_zqinit_r_reg[6]),
        .I1(mem_init_done_r_i_2_n_0),
        .O(p_0_in__4[6]));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \cnt_dllk_zqinit_r[7]_i_1 
       (.I0(\wrcal_reads[7]_i_4_n_0 ),
        .I1(\init_state_r_reg_n_0_[4] ),
        .I2(\init_state_r_reg_n_0_[5] ),
        .I3(init_state_r),
        .I4(Q),
        .I5(\init_state_r_reg_n_0_[1] ),
        .O(\cnt_dllk_zqinit_r[7]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair471" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \cnt_dllk_zqinit_r[7]_i_2 
       (.I0(cnt_dllk_zqinit_r_reg[7]),
        .I1(mem_init_done_r_i_2_n_0),
        .I2(cnt_dllk_zqinit_r_reg[6]),
        .O(p_0_in__4[7]));
  FDRE \cnt_dllk_zqinit_r_reg[0] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(p_0_in__4[0]),
        .Q(cnt_dllk_zqinit_r_reg[0]),
        .R(\cnt_dllk_zqinit_r[7]_i_1_n_0 ));
  FDRE \cnt_dllk_zqinit_r_reg[1] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(p_0_in__4[1]),
        .Q(cnt_dllk_zqinit_r_reg[1]),
        .R(\cnt_dllk_zqinit_r[7]_i_1_n_0 ));
  FDRE \cnt_dllk_zqinit_r_reg[2] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(p_0_in__4[2]),
        .Q(cnt_dllk_zqinit_r_reg[2]),
        .R(\cnt_dllk_zqinit_r[7]_i_1_n_0 ));
  FDRE \cnt_dllk_zqinit_r_reg[3] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(p_0_in__4[3]),
        .Q(cnt_dllk_zqinit_r_reg[3]),
        .R(\cnt_dllk_zqinit_r[7]_i_1_n_0 ));
  FDRE \cnt_dllk_zqinit_r_reg[4] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(p_0_in__4[4]),
        .Q(cnt_dllk_zqinit_r_reg[4]),
        .R(\cnt_dllk_zqinit_r[7]_i_1_n_0 ));
  FDRE \cnt_dllk_zqinit_r_reg[5] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(p_0_in__4[5]),
        .Q(cnt_dllk_zqinit_r_reg[5]),
        .R(\cnt_dllk_zqinit_r[7]_i_1_n_0 ));
  FDRE \cnt_dllk_zqinit_r_reg[6] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(p_0_in__4[6]),
        .Q(cnt_dllk_zqinit_r_reg[6]),
        .R(\cnt_dllk_zqinit_r[7]_i_1_n_0 ));
  FDRE \cnt_dllk_zqinit_r_reg[7] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(p_0_in__4[7]),
        .Q(cnt_dllk_zqinit_r_reg[7]),
        .R(\cnt_dllk_zqinit_r[7]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair392" *) 
  LUT5 #(
    .INIT(32'h0000E222)) 
    cnt_init_af_done_r_i_1
       (.I0(cnt_init_af_done_r),
        .I1(cnt_init_mr_r1),
        .I2(cnt_init_af_r[1]),
        .I3(cnt_init_af_r[0]),
        .I4(\reg_ctrl_cnt_r[3]_i_1_n_0 ),
        .O(cnt_init_af_done_r_i_1_n_0));
  FDRE cnt_init_af_done_r_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(cnt_init_af_done_r_i_1_n_0),
        .Q(cnt_init_af_done_r),
        .R(1'b0));
  LUT3 #(
    .INIT(8'h06)) 
    \cnt_init_af_r[0]_i_1 
       (.I0(cnt_init_af_r[0]),
        .I1(cnt_init_mr_r1),
        .I2(\reg_ctrl_cnt_r[3]_i_1_n_0 ),
        .O(\cnt_init_af_r[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair392" *) 
  LUT4 #(
    .INIT(16'h006A)) 
    \cnt_init_af_r[1]_i_1 
       (.I0(cnt_init_af_r[1]),
        .I1(cnt_init_mr_r1),
        .I2(cnt_init_af_r[0]),
        .I3(\reg_ctrl_cnt_r[3]_i_1_n_0 ),
        .O(\cnt_init_af_r[1]_i_1_n_0 ));
  FDRE \cnt_init_af_r_reg[0] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\cnt_init_af_r[0]_i_1_n_0 ),
        .Q(cnt_init_af_r[0]),
        .R(1'b0));
  FDRE \cnt_init_af_r_reg[1] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\cnt_init_af_r[1]_i_1_n_0 ),
        .Q(cnt_init_af_r[1]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h000000000000E222)) 
    cnt_init_mr_done_r_i_1
       (.I0(cnt_init_mr_done_r),
        .I1(\cnt_init_mr_r[1]_i_2_n_0 ),
        .I2(cnt_init_mr_r[1]),
        .I3(cnt_init_mr_r[0]),
        .I4(\reg_ctrl_cnt_r[3]_i_1_n_0 ),
        .I5(cnt_init_mr_r1),
        .O(cnt_init_mr_done_r_i_1_n_0));
  FDRE cnt_init_mr_done_r_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(cnt_init_mr_done_r_i_1_n_0),
        .Q(cnt_init_mr_done_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h00000000AA9AAA8A)) 
    \cnt_init_mr_r[0]_i_1 
       (.I0(cnt_init_mr_r[0]),
        .I1(\cnt_init_mr_r[0]_i_2_n_0 ),
        .I2(\cnt_init_mr_r[0]_i_3_n_0 ),
        .I3(Q),
        .I4(\init_state_r_reg_n_0_[1] ),
        .I5(cnt_init_mr_r1),
        .O(\cnt_init_mr_r[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair522" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \cnt_init_mr_r[0]_i_2 
       (.I0(\init_state_r_reg_n_0_[3] ),
        .I1(\init_state_r_reg_n_0_[2] ),
        .O(\cnt_init_mr_r[0]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair488" *) 
  LUT3 #(
    .INIT(8'h01)) 
    \cnt_init_mr_r[0]_i_3 
       (.I0(\init_state_r_reg_n_0_[4] ),
        .I1(\init_state_r_reg_n_0_[5] ),
        .I2(init_state_r),
        .O(\cnt_init_mr_r[0]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'h0000006A)) 
    \cnt_init_mr_r[1]_i_1 
       (.I0(cnt_init_mr_r[1]),
        .I1(\cnt_init_mr_r[1]_i_2_n_0 ),
        .I2(cnt_init_mr_r[0]),
        .I3(\reg_ctrl_cnt_r[3]_i_1_n_0 ),
        .I4(cnt_init_mr_r1),
        .O(\cnt_init_mr_r[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000100000000)) 
    \cnt_init_mr_r[1]_i_2 
       (.I0(\init_state_r_reg_n_0_[3] ),
        .I1(\init_state_r_reg_n_0_[2] ),
        .I2(\init_state_r_reg_n_0_[4] ),
        .I3(\init_state_r_reg_n_0_[5] ),
        .I4(init_state_r),
        .I5(detect_pi_found_dqs_i_2_n_0),
        .O(\cnt_init_mr_r[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000001000000)) 
    \cnt_init_mr_r[1]_i_3 
       (.I0(\init_state_r_reg_n_0_[5] ),
        .I1(init_state_r),
        .I2(\init_state_r[4]_i_4_n_0 ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ),
        .I4(\init_state_r_reg_n_0_[4] ),
        .I5(mem_init_done_r),
        .O(cnt_init_mr_r1));
  FDRE \cnt_init_mr_r_reg[0] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\cnt_init_mr_r[0]_i_1_n_0 ),
        .Q(cnt_init_mr_r[0]),
        .R(1'b0));
  FDRE \cnt_init_mr_r_reg[1] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\cnt_init_mr_r[1]_i_1_n_0 ),
        .Q(cnt_init_mr_r[1]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \cnt_pwron_ce_r[0]_i_1 
       (.I0(cnt_pwron_ce_r_reg[0]),
        .O(p_0_in__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair502" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cnt_pwron_ce_r[1]_i_1 
       (.I0(cnt_pwron_ce_r_reg[1]),
        .I1(cnt_pwron_ce_r_reg[0]),
        .O(p_0_in__0[1]));
  (* SOFT_HLUTNM = "soft_lutpair502" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \cnt_pwron_ce_r[2]_i_1 
       (.I0(cnt_pwron_ce_r_reg[2]),
        .I1(cnt_pwron_ce_r_reg[0]),
        .I2(cnt_pwron_ce_r_reg[1]),
        .O(p_0_in__0[2]));
  (* SOFT_HLUTNM = "soft_lutpair435" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \cnt_pwron_ce_r[3]_i_1 
       (.I0(cnt_pwron_ce_r_reg[3]),
        .I1(cnt_pwron_ce_r_reg[1]),
        .I2(cnt_pwron_ce_r_reg[0]),
        .I3(cnt_pwron_ce_r_reg[2]),
        .O(p_0_in__0[3]));
  (* SOFT_HLUTNM = "soft_lutpair435" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \cnt_pwron_ce_r[4]_i_1 
       (.I0(cnt_pwron_ce_r_reg[4]),
        .I1(cnt_pwron_ce_r_reg[2]),
        .I2(cnt_pwron_ce_r_reg[0]),
        .I3(cnt_pwron_ce_r_reg[1]),
        .I4(cnt_pwron_ce_r_reg[3]),
        .O(p_0_in__0[4]));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAAAAAA)) 
    \cnt_pwron_ce_r[5]_i_1 
       (.I0(cnt_pwron_ce_r_reg[5]),
        .I1(cnt_pwron_ce_r_reg[3]),
        .I2(cnt_pwron_ce_r_reg[1]),
        .I3(cnt_pwron_ce_r_reg[0]),
        .I4(cnt_pwron_ce_r_reg[2]),
        .I5(cnt_pwron_ce_r_reg[4]),
        .O(p_0_in__0[5]));
  (* SOFT_HLUTNM = "soft_lutpair507" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cnt_pwron_ce_r[6]_i_1 
       (.I0(cnt_pwron_ce_r_reg[6]),
        .I1(pwron_ce_r_i_2_n_0),
        .O(p_0_in__0[6]));
  (* SOFT_HLUTNM = "soft_lutpair507" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \cnt_pwron_ce_r[7]_i_1 
       (.I0(cnt_pwron_ce_r_reg[7]),
        .I1(pwron_ce_r_i_2_n_0),
        .I2(cnt_pwron_ce_r_reg[6]),
        .O(p_0_in__0[7]));
  (* SOFT_HLUTNM = "soft_lutpair433" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \cnt_pwron_ce_r[8]_i_1 
       (.I0(cnt_pwron_ce_r_reg[8]),
        .I1(cnt_pwron_ce_r_reg[6]),
        .I2(pwron_ce_r_i_2_n_0),
        .I3(cnt_pwron_ce_r_reg[7]),
        .O(p_0_in__0[8]));
  (* SOFT_HLUTNM = "soft_lutpair433" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \cnt_pwron_ce_r[9]_i_1 
       (.I0(cnt_pwron_ce_r_reg[9]),
        .I1(cnt_pwron_ce_r_reg[7]),
        .I2(pwron_ce_r_i_2_n_0),
        .I3(cnt_pwron_ce_r_reg[6]),
        .I4(cnt_pwron_ce_r_reg[8]),
        .O(p_0_in__0[9]));
  FDRE \cnt_pwron_ce_r_reg[0] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(p_0_in__0[0]),
        .Q(cnt_pwron_ce_r_reg[0]),
        .R(\cnt_pwron_ce_r_reg[0]_0 ));
  FDRE \cnt_pwron_ce_r_reg[1] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(p_0_in__0[1]),
        .Q(cnt_pwron_ce_r_reg[1]),
        .R(\cnt_pwron_ce_r_reg[0]_0 ));
  FDRE \cnt_pwron_ce_r_reg[2] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(p_0_in__0[2]),
        .Q(cnt_pwron_ce_r_reg[2]),
        .R(\cnt_pwron_ce_r_reg[0]_0 ));
  FDRE \cnt_pwron_ce_r_reg[3] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(p_0_in__0[3]),
        .Q(cnt_pwron_ce_r_reg[3]),
        .R(\cnt_pwron_ce_r_reg[0]_0 ));
  FDRE \cnt_pwron_ce_r_reg[4] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(p_0_in__0[4]),
        .Q(cnt_pwron_ce_r_reg[4]),
        .R(\cnt_pwron_ce_r_reg[0]_0 ));
  FDRE \cnt_pwron_ce_r_reg[5] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(p_0_in__0[5]),
        .Q(cnt_pwron_ce_r_reg[5]),
        .R(\cnt_pwron_ce_r_reg[0]_0 ));
  FDRE \cnt_pwron_ce_r_reg[6] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(p_0_in__0[6]),
        .Q(cnt_pwron_ce_r_reg[6]),
        .R(\cnt_pwron_ce_r_reg[0]_0 ));
  FDRE \cnt_pwron_ce_r_reg[7] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(p_0_in__0[7]),
        .Q(cnt_pwron_ce_r_reg[7]),
        .R(\cnt_pwron_ce_r_reg[0]_0 ));
  FDRE \cnt_pwron_ce_r_reg[8] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(p_0_in__0[8]),
        .Q(cnt_pwron_ce_r_reg[8]),
        .R(\cnt_pwron_ce_r_reg[0]_0 ));
  FDRE \cnt_pwron_ce_r_reg[9] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(p_0_in__0[9]),
        .Q(cnt_pwron_ce_r_reg[9]),
        .R(\cnt_pwron_ce_r_reg[0]_0 ));
  LUT5 #(
    .INIT(32'h0000BA00)) 
    cnt_pwron_cke_done_r_i_1
       (.I0(cnt_pwron_cke_done_r),
        .I1(cnt_pwron_cke_done_r_i_2_n_0),
        .I2(cnt_pwron_cke_done_r_i_3_n_0),
        .I3(\calib_seq_reg[0]_0 ),
        .I4(\rd_addr_reg[7] ),
        .O(cnt_pwron_cke_done_r_i_1_n_0));
  LUT6 #(
    .INIT(64'hFFFFEFFFFFFFFFFF)) 
    cnt_pwron_cke_done_r_i_2
       (.I0(cnt_pwron_r_reg[8]),
        .I1(cnt_pwron_r_reg[7]),
        .I2(cnt_pwron_r_reg[2]),
        .I3(cnt_pwron_r_reg[6]),
        .I4(cnt_pwron_r_reg[4]),
        .I5(cnt_pwron_r_reg[1]),
        .O(cnt_pwron_cke_done_r_i_2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair498" *) 
  LUT3 #(
    .INIT(8'h01)) 
    cnt_pwron_cke_done_r_i_3
       (.I0(cnt_pwron_r_reg[5]),
        .I1(cnt_pwron_r_reg[0]),
        .I2(cnt_pwron_r_reg[3]),
        .O(cnt_pwron_cke_done_r_i_3_n_0));
  FDRE cnt_pwron_cke_done_r_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(cnt_pwron_cke_done_r_i_1_n_0),
        .Q(cnt_pwron_cke_done_r),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair526" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \cnt_pwron_r[0]_i_1 
       (.I0(cnt_pwron_r_reg[0]),
        .O(p_0_in__1[0]));
  (* SOFT_HLUTNM = "soft_lutpair526" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cnt_pwron_r[1]_i_1 
       (.I0(cnt_pwron_r_reg[1]),
        .I1(cnt_pwron_r_reg[0]),
        .O(p_0_in__1[1]));
  (* SOFT_HLUTNM = "soft_lutpair498" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \cnt_pwron_r[2]_i_1 
       (.I0(cnt_pwron_r_reg[2]),
        .I1(cnt_pwron_r_reg[0]),
        .I2(cnt_pwron_r_reg[1]),
        .O(p_0_in__1[2]));
  (* SOFT_HLUTNM = "soft_lutpair428" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \cnt_pwron_r[3]_i_1 
       (.I0(cnt_pwron_r_reg[3]),
        .I1(cnt_pwron_r_reg[1]),
        .I2(cnt_pwron_r_reg[0]),
        .I3(cnt_pwron_r_reg[2]),
        .O(p_0_in__1[3]));
  (* SOFT_HLUTNM = "soft_lutpair428" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \cnt_pwron_r[4]_i_1 
       (.I0(cnt_pwron_r_reg[4]),
        .I1(cnt_pwron_r_reg[2]),
        .I2(cnt_pwron_r_reg[0]),
        .I3(cnt_pwron_r_reg[1]),
        .I4(cnt_pwron_r_reg[3]),
        .O(p_0_in__1[4]));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAAAAAA)) 
    \cnt_pwron_r[5]_i_1 
       (.I0(cnt_pwron_r_reg[5]),
        .I1(cnt_pwron_r_reg[3]),
        .I2(cnt_pwron_r_reg[1]),
        .I3(cnt_pwron_r_reg[0]),
        .I4(cnt_pwron_r_reg[2]),
        .I5(cnt_pwron_r_reg[4]),
        .O(p_0_in__1[5]));
  LUT2 #(
    .INIT(4'h6)) 
    \cnt_pwron_r[6]_i_1 
       (.I0(cnt_pwron_r_reg[6]),
        .I1(\cnt_pwron_r[8]_i_2_n_0 ),
        .O(p_0_in__1[6]));
  (* SOFT_HLUTNM = "soft_lutpair464" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \cnt_pwron_r[7]_i_1 
       (.I0(cnt_pwron_r_reg[7]),
        .I1(\cnt_pwron_r[8]_i_2_n_0 ),
        .I2(cnt_pwron_r_reg[6]),
        .O(p_0_in__1[7]));
  (* SOFT_HLUTNM = "soft_lutpair464" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \cnt_pwron_r[8]_i_1 
       (.I0(cnt_pwron_r_reg[8]),
        .I1(cnt_pwron_r_reg[6]),
        .I2(\cnt_pwron_r[8]_i_2_n_0 ),
        .I3(cnt_pwron_r_reg[7]),
        .O(p_0_in__1[8]));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \cnt_pwron_r[8]_i_2 
       (.I0(cnt_pwron_r_reg[3]),
        .I1(cnt_pwron_r_reg[1]),
        .I2(cnt_pwron_r_reg[0]),
        .I3(cnt_pwron_r_reg[2]),
        .I4(cnt_pwron_r_reg[4]),
        .I5(cnt_pwron_r_reg[5]),
        .O(\cnt_pwron_r[8]_i_2_n_0 ));
  FDRE \cnt_pwron_r_reg[0] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(pwron_ce_r),
        .D(p_0_in__1[0]),
        .Q(cnt_pwron_r_reg[0]),
        .R(\cnt_pwron_ce_r_reg[0]_0 ));
  FDRE \cnt_pwron_r_reg[1] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(pwron_ce_r),
        .D(p_0_in__1[1]),
        .Q(cnt_pwron_r_reg[1]),
        .R(\cnt_pwron_ce_r_reg[0]_0 ));
  FDRE \cnt_pwron_r_reg[2] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(pwron_ce_r),
        .D(p_0_in__1[2]),
        .Q(cnt_pwron_r_reg[2]),
        .R(\cnt_pwron_ce_r_reg[0]_0 ));
  FDRE \cnt_pwron_r_reg[3] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(pwron_ce_r),
        .D(p_0_in__1[3]),
        .Q(cnt_pwron_r_reg[3]),
        .R(\cnt_pwron_ce_r_reg[0]_0 ));
  FDRE \cnt_pwron_r_reg[4] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(pwron_ce_r),
        .D(p_0_in__1[4]),
        .Q(cnt_pwron_r_reg[4]),
        .R(\cnt_pwron_ce_r_reg[0]_0 ));
  FDRE \cnt_pwron_r_reg[5] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(pwron_ce_r),
        .D(p_0_in__1[5]),
        .Q(cnt_pwron_r_reg[5]),
        .R(\cnt_pwron_ce_r_reg[0]_0 ));
  FDRE \cnt_pwron_r_reg[6] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(pwron_ce_r),
        .D(p_0_in__1[6]),
        .Q(cnt_pwron_r_reg[6]),
        .R(\cnt_pwron_ce_r_reg[0]_0 ));
  FDRE \cnt_pwron_r_reg[7] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(pwron_ce_r),
        .D(p_0_in__1[7]),
        .Q(cnt_pwron_r_reg[7]),
        .R(\cnt_pwron_ce_r_reg[0]_0 ));
  FDRE \cnt_pwron_r_reg[8] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(pwron_ce_r),
        .D(p_0_in__1[8]),
        .Q(cnt_pwron_r_reg[8]),
        .R(\cnt_pwron_ce_r_reg[0]_0 ));
  LUT5 #(
    .INIT(32'h0000F200)) 
    cnt_pwron_reset_done_r_i_1
       (.I0(cnt_pwron_cke_done_r_i_3_n_0),
        .I1(cnt_pwron_reset_done_r_i_2_n_0),
        .I2(cnt_pwron_reset_done_r),
        .I3(\calib_seq_reg[0]_0 ),
        .I4(\rd_addr_reg[7] ),
        .O(cnt_pwron_reset_done_r_i_1_n_0));
  LUT6 #(
    .INIT(64'hFFFFFEFFFFFFFFFF)) 
    cnt_pwron_reset_done_r_i_2
       (.I0(cnt_pwron_r_reg[8]),
        .I1(cnt_pwron_r_reg[7]),
        .I2(cnt_pwron_r_reg[1]),
        .I3(cnt_pwron_r_reg[2]),
        .I4(cnt_pwron_r_reg[6]),
        .I5(cnt_pwron_r_reg[4]),
        .O(cnt_pwron_reset_done_r_i_2_n_0));
  FDRE cnt_pwron_reset_done_r_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(cnt_pwron_reset_done_r_i_1_n_0),
        .Q(cnt_pwron_reset_done_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAABAA)) 
    cnt_txpr_done_r_i_1
       (.I0(cnt_txpr_done_r),
        .I1(cnt_txpr_done_r_i_2_n_0),
        .I2(cnt_txpr_r_reg[7]),
        .I3(cnt_txpr_r_reg[4]),
        .I4(cnt_txpr_r_reg[6]),
        .I5(cnt_txpr_r_reg[3]),
        .O(cnt_txpr_done_r_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair472" *) 
  LUT4 #(
    .INIT(16'hFFDF)) 
    cnt_txpr_done_r_i_2
       (.I0(cnt_txpr_r_reg[1]),
        .I1(cnt_txpr_r_reg[0]),
        .I2(cnt_txpr_r_reg[2]),
        .I3(cnt_txpr_r_reg[5]),
        .O(cnt_txpr_done_r_i_2_n_0));
  FDRE cnt_txpr_done_r_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(cnt_txpr_done_r_i_1_n_0),
        .Q(cnt_txpr_done_r),
        .R(clear));
  (* SOFT_HLUTNM = "soft_lutpair527" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \cnt_txpr_r[0]_i_1 
       (.I0(cnt_txpr_r_reg[0]),
        .O(p_0_in__2[0]));
  (* SOFT_HLUTNM = "soft_lutpair527" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cnt_txpr_r[1]_i_1 
       (.I0(cnt_txpr_r_reg[1]),
        .I1(cnt_txpr_r_reg[0]),
        .O(p_0_in__2[1]));
  (* SOFT_HLUTNM = "soft_lutpair472" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \cnt_txpr_r[2]_i_1 
       (.I0(cnt_txpr_r_reg[2]),
        .I1(cnt_txpr_r_reg[0]),
        .I2(cnt_txpr_r_reg[1]),
        .O(p_0_in__2[2]));
  (* SOFT_HLUTNM = "soft_lutpair420" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \cnt_txpr_r[3]_i_1 
       (.I0(cnt_txpr_r_reg[3]),
        .I1(cnt_txpr_r_reg[1]),
        .I2(cnt_txpr_r_reg[0]),
        .I3(cnt_txpr_r_reg[2]),
        .O(p_0_in__2[3]));
  (* SOFT_HLUTNM = "soft_lutpair420" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \cnt_txpr_r[4]_i_1 
       (.I0(cnt_txpr_r_reg[4]),
        .I1(cnt_txpr_r_reg[2]),
        .I2(cnt_txpr_r_reg[0]),
        .I3(cnt_txpr_r_reg[1]),
        .I4(cnt_txpr_r_reg[3]),
        .O(p_0_in__2[4]));
  LUT6 #(
    .INIT(64'h6AAAAAAAAAAAAAAA)) 
    \cnt_txpr_r[5]_i_1 
       (.I0(cnt_txpr_r_reg[5]),
        .I1(cnt_txpr_r_reg[3]),
        .I2(cnt_txpr_r_reg[1]),
        .I3(cnt_txpr_r_reg[0]),
        .I4(cnt_txpr_r_reg[2]),
        .I5(cnt_txpr_r_reg[4]),
        .O(p_0_in__2[5]));
  (* SOFT_HLUTNM = "soft_lutpair512" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cnt_txpr_r[6]_i_1 
       (.I0(cnt_txpr_r_reg[6]),
        .I1(\cnt_txpr_r[7]_i_3_n_0 ),
        .O(p_0_in__2[6]));
  LUT1 #(
    .INIT(2'h1)) 
    \cnt_txpr_r[7]_i_1 
       (.I0(cnt_pwron_cke_done_r),
        .O(clear));
  (* SOFT_HLUTNM = "soft_lutpair512" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \cnt_txpr_r[7]_i_2 
       (.I0(cnt_txpr_r_reg[7]),
        .I1(\cnt_txpr_r[7]_i_3_n_0 ),
        .I2(cnt_txpr_r_reg[6]),
        .O(p_0_in__2[7]));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \cnt_txpr_r[7]_i_3 
       (.I0(cnt_txpr_r_reg[5]),
        .I1(cnt_txpr_r_reg[3]),
        .I2(cnt_txpr_r_reg[1]),
        .I3(cnt_txpr_r_reg[0]),
        .I4(cnt_txpr_r_reg[2]),
        .I5(cnt_txpr_r_reg[4]),
        .O(\cnt_txpr_r[7]_i_3_n_0 ));
  FDRE \cnt_txpr_r_reg[0] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(p_0_in__2[0]),
        .Q(cnt_txpr_r_reg[0]),
        .R(clear));
  FDRE \cnt_txpr_r_reg[1] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(p_0_in__2[1]),
        .Q(cnt_txpr_r_reg[1]),
        .R(clear));
  FDRE \cnt_txpr_r_reg[2] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(p_0_in__2[2]),
        .Q(cnt_txpr_r_reg[2]),
        .R(clear));
  FDRE \cnt_txpr_r_reg[3] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(p_0_in__2[3]),
        .Q(cnt_txpr_r_reg[3]),
        .R(clear));
  FDRE \cnt_txpr_r_reg[4] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(p_0_in__2[4]),
        .Q(cnt_txpr_r_reg[4]),
        .R(clear));
  FDRE \cnt_txpr_r_reg[5] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(p_0_in__2[5]),
        .Q(cnt_txpr_r_reg[5]),
        .R(clear));
  FDRE \cnt_txpr_r_reg[6] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(p_0_in__2[6]),
        .Q(cnt_txpr_r_reg[6]),
        .R(clear));
  FDRE \cnt_txpr_r_reg[7] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(p_0_in__2[7]),
        .Q(cnt_txpr_r_reg[7]),
        .R(clear));
  LUT6 #(
    .INIT(64'h00FF000002020000)) 
    complex_act_start_i_1
       (.I0(\init_state_r_reg_n_0_[4] ),
        .I1(complex_act_start_i_2_n_0),
        .I2(\wrcal_reads[7]_i_4_n_0 ),
        .I3(prbs_rdlvl_start_i_3_n_0),
        .I4(\init_state_r_reg_n_0_[1] ),
        .I5(Q),
        .O(complex_act_start0));
  (* SOFT_HLUTNM = "soft_lutpair476" *) 
  LUT2 #(
    .INIT(4'hB)) 
    complex_act_start_i_2
       (.I0(init_state_r),
        .I1(\init_state_r_reg_n_0_[5] ),
        .O(complex_act_start_i_2_n_0));
  FDRE complex_act_start_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(complex_act_start0),
        .Q(complex_act_start),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFF10FF10101000)) 
    \complex_address[9]_i_1 
       (.I0(complex_oclkdelay_calib_start_int_i_2_n_0),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(Q),
        .I3(init_state_r1[2]),
        .I4(\complex_address[9]_i_2_n_0 ),
        .I5(\complex_address[9]_i_3_n_0 ),
        .O(complex_address0));
  LUT6 #(
    .INIT(64'hFFFFFFFFBFFFFFFF)) 
    \complex_address[9]_i_2 
       (.I0(init_state_r1[6]),
        .I1(init_state_r1[5]),
        .I2(init_state_r1[4]),
        .I3(init_state_r1[3]),
        .I4(init_state_r1[0]),
        .I5(init_state_r1[1]),
        .O(\complex_address[9]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0080000000000000)) 
    \complex_address[9]_i_3 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ),
        .I1(\init_state_r_reg_n_0_[2] ),
        .I2(\init_state_r_reg_n_0_[5] ),
        .I3(init_state_r),
        .I4(\init_state_r_reg_n_0_[4] ),
        .I5(\init_state_r_reg_n_0_[3] ),
        .O(\complex_address[9]_i_3_n_0 ));
  FDRE \complex_address_reg[0] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(complex_address0),
        .D(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ),
        .Q(\complex_address_reg_n_0_[0] ),
        .R(\en_cnt_div4.enable_wrlvl_cnt_reg[2]_0 ));
  FDRE \complex_address_reg[1] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(complex_address0),
        .D(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ),
        .Q(\complex_address_reg_n_0_[1] ),
        .R(\en_cnt_div4.enable_wrlvl_cnt_reg[2]_0 ));
  FDRE \complex_address_reg[2] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(complex_address0),
        .D(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ),
        .Q(\complex_address_reg_n_0_[2] ),
        .R(\en_cnt_div4.enable_wrlvl_cnt_reg[2]_0 ));
  FDRE \complex_address_reg[3] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(complex_address0),
        .D(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),
        .Q(\complex_address_reg_n_0_[3] ),
        .R(\en_cnt_div4.enable_wrlvl_cnt_reg[2]_0 ));
  FDRE \complex_address_reg[4] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(complex_address0),
        .D(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ),
        .Q(\complex_address_reg_n_0_[4] ),
        .R(\en_cnt_div4.enable_wrlvl_cnt_reg[2]_0 ));
  FDRE \complex_address_reg[5] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(complex_address0),
        .D(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ),
        .Q(\complex_address_reg_n_0_[5] ),
        .R(\en_cnt_div4.enable_wrlvl_cnt_reg[2]_0 ));
  FDRE \complex_address_reg[6] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(complex_address0),
        .D(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ),
        .Q(\complex_address_reg_n_0_[6] ),
        .R(\en_cnt_div4.enable_wrlvl_cnt_reg[2]_0 ));
  FDRE \complex_address_reg[7] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(complex_address0),
        .D(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ),
        .Q(\complex_address_reg_n_0_[7] ),
        .R(\en_cnt_div4.enable_wrlvl_cnt_reg[2]_0 ));
  FDRE \complex_address_reg[8] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(complex_address0),
        .D(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ),
        .Q(\complex_address_reg_n_0_[8] ),
        .R(\en_cnt_div4.enable_wrlvl_cnt_reg[2]_0 ));
  FDRE \complex_address_reg[9] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(complex_address0),
        .D(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9] ),
        .Q(\complex_address_reg_n_0_[9] ),
        .R(\en_cnt_div4.enable_wrlvl_cnt_reg[2]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair391" *) 
  LUT5 #(
    .INIT(32'h00001110)) 
    complex_byte_rd_done_i_1
       (.I0(write_calib_reg_0),
        .I1(prbs_rdlvl_done_pulse_reg_0),
        .I2(complex_byte_rd_done_i_2_n_0),
        .I3(complex_byte_rd_done),
        .I4(\stg1_wr_rd_cnt[8]_i_5_n_0 ),
        .O(complex_byte_rd_done_i_1_n_0));
  LUT6 #(
    .INIT(64'h0000800000000000)) 
    complex_byte_rd_done_i_2
       (.I0(complex_row1_rd_cnt[1]),
        .I1(complex_row1_rd_cnt[0]),
        .I2(complex_row1_rd_cnt[2]),
        .I3(complex_row1_rd_done),
        .I4(complex_row1_rd_done_r1),
        .I5(complex_oclkdelay_calib_done_r1_reg_0),
        .O(complex_byte_rd_done_i_2_n_0));
  FDRE complex_byte_rd_done_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(complex_byte_rd_done_i_1_n_0),
        .Q(complex_byte_rd_done),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hFFFF26EE)) 
    \complex_num_reads[0]_i_1 
       (.I0(\complex_num_reads_reg_n_0_[0] ),
        .I1(\complex_num_reads[3]_i_2_n_0 ),
        .I2(\complex_num_writes[4]_i_6_n_0 ),
        .I3(\complex_num_reads[2]_i_3_n_0 ),
        .I4(\complex_num_reads[3]_i_4_n_0 ),
        .O(\complex_num_reads[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0222FE2200000000)) 
    \complex_num_reads[1]_i_1 
       (.I0(\complex_num_reads_reg_n_0_[1] ),
        .I1(\complex_num_reads[2]_i_5_n_0 ),
        .I2(\complex_num_writes[2]_i_5_n_0 ),
        .I3(\complex_num_reads[2]_i_3_n_0 ),
        .I4(\complex_num_reads[1]_i_2_n_0 ),
        .I5(\complex_num_reads[2]_i_2_n_0 ),
        .O(\complex_num_reads[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair458" *) 
  LUT4 #(
    .INIT(16'hA88A)) 
    \complex_num_reads[1]_i_2 
       (.I0(\complex_num_writes[4]_i_7_n_0 ),
        .I1(\complex_num_writes[4]_i_6_n_0 ),
        .I2(\complex_num_reads_reg_n_0_[1] ),
        .I3(\complex_num_reads_reg_n_0_[0] ),
        .O(\complex_num_reads[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0022000008AA0800)) 
    \complex_num_reads[2]_i_1 
       (.I0(\complex_num_reads[2]_i_2_n_0 ),
        .I1(\complex_num_reads[2]_i_3_n_0 ),
        .I2(\complex_num_reads[2]_i_4_n_0 ),
        .I3(\complex_num_reads[2]_i_5_n_0 ),
        .I4(\complex_num_reads_reg_n_0_[2] ),
        .I5(\complex_num_writes[2]_i_5_n_0 ),
        .O(\complex_num_reads[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0015555555555555)) 
    \complex_num_reads[2]_i_2 
       (.I0(\rd_addr_reg[7] ),
        .I1(\complex_num_reads_reg_n_0_[2] ),
        .I2(\complex_num_reads_reg_n_0_[1] ),
        .I3(\complex_num_reads_reg_n_0_[3] ),
        .I4(\complex_num_writes[4]_i_12_n_0 ),
        .I5(\complex_num_reads[2]_i_3_n_0 ),
        .O(\complex_num_reads[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000004000)) 
    \complex_num_reads[2]_i_3 
       (.I0(\complex_num_reads[2]_i_6_n_0 ),
        .I1(complex_wait_cnt_reg[2]),
        .I2(complex_wait_cnt_reg[3]),
        .I3(complex_wait_cnt_reg[1]),
        .I4(complex_wait_cnt_reg[0]),
        .I5(complex_row0_rd_done),
        .O(\complex_num_reads[2]_i_3_n_0 ));
  LUT4 #(
    .INIT(16'h802A)) 
    \complex_num_reads[2]_i_4 
       (.I0(\complex_num_writes[2]_i_8_n_0 ),
        .I1(\complex_num_reads_reg_n_0_[1] ),
        .I2(\complex_num_reads_reg_n_0_[0] ),
        .I3(\complex_num_reads_reg_n_0_[2] ),
        .O(\complex_num_reads[2]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair477" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \complex_num_reads[2]_i_5 
       (.I0(\complex_num_reads[2]_i_3_n_0 ),
        .I1(\complex_num_reads[3]_i_7_n_0 ),
        .I2(\complex_num_reads[3]_i_2_n_0 ),
        .O(\complex_num_reads[2]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFFDFFFFFFFFFFFFF)) 
    \complex_num_reads[2]_i_6 
       (.I0(\init_state_r_reg_n_0_[5] ),
        .I1(init_state_r),
        .I2(\init_state_r_reg_n_0_[4] ),
        .I3(\init_state_r_reg_n_0_[2] ),
        .I4(\init_state_r_reg_n_0_[3] ),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ),
        .O(\complex_num_reads[2]_i_6_n_0 ));
  LUT4 #(
    .INIT(16'h00E2)) 
    \complex_num_reads[3]_i_1 
       (.I0(\complex_num_reads_reg_n_0_[3] ),
        .I1(\complex_num_reads[3]_i_2_n_0 ),
        .I2(\complex_num_reads[3]_i_3_n_0 ),
        .I3(\complex_num_reads[3]_i_4_n_0 ),
        .O(\complex_num_reads[3]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h0EFEFEFE)) 
    \complex_num_reads[3]_i_2 
       (.I0(\complex_num_writes[3]_i_4_n_0 ),
        .I1(stg1_wr_done),
        .I2(\complex_num_reads[2]_i_3_n_0 ),
        .I3(\complex_num_reads[3]_i_5_n_0 ),
        .I4(\complex_num_reads[3]_i_6_n_0 ),
        .O(\complex_num_reads[3]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h8AA8A8A8A8A8A8A8)) 
    \complex_num_reads[3]_i_3 
       (.I0(\complex_num_reads[2]_i_3_n_0 ),
        .I1(\complex_num_writes[4]_i_6_n_0 ),
        .I2(\complex_num_reads_reg_n_0_[3] ),
        .I3(\complex_num_reads_reg_n_0_[2] ),
        .I4(\complex_num_reads_reg_n_0_[1] ),
        .I5(\complex_num_reads_reg_n_0_[0] ),
        .O(\complex_num_reads[3]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair477" *) 
  LUT4 #(
    .INIT(16'hF5D5)) 
    \complex_num_reads[3]_i_4 
       (.I0(\complex_num_reads[2]_i_2_n_0 ),
        .I1(\complex_num_reads[3]_i_7_n_0 ),
        .I2(\complex_num_reads[2]_i_3_n_0 ),
        .I3(\complex_num_writes[2]_i_5_n_0 ),
        .O(\complex_num_reads[3]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'h55554440)) 
    \complex_num_reads[3]_i_5 
       (.I0(\complex_num_writes[4]_i_12_n_0 ),
        .I1(\complex_num_reads_reg_n_0_[2] ),
        .I2(\complex_num_reads_reg_n_0_[0] ),
        .I3(\complex_num_reads_reg_n_0_[1] ),
        .I4(\complex_num_reads_reg_n_0_[3] ),
        .O(\complex_num_reads[3]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hBABABAAABAAAAAAA)) 
    \complex_num_reads[3]_i_6 
       (.I0(\complex_num_writes[4]_i_10_n_0 ),
        .I1(\complex_num_writes[4]_i_6_n_0 ),
        .I2(\complex_num_reads_reg_n_0_[3] ),
        .I3(\complex_num_reads_reg_n_0_[2] ),
        .I4(\complex_num_reads_reg_n_0_[1] ),
        .I5(\complex_num_writes[4]_i_13_n_0 ),
        .O(\complex_num_reads[3]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000080)) 
    \complex_num_reads[3]_i_7 
       (.I0(\complex_num_writes[2]_i_9_n_0 ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[3] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[0] ),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[2] ),
        .I4(\stg1_wr_rd_cnt_reg_n_0_[5] ),
        .I5(\stg1_wr_rd_cnt_reg_n_0_[4] ),
        .O(\complex_num_reads[3]_i_7_n_0 ));
  LUT3 #(
    .INIT(8'h74)) 
    \complex_num_reads_dec[0]_i_1 
       (.I0(complex_num_reads_dec[0]),
        .I1(\complex_num_reads_dec[3]_i_3_n_0 ),
        .I2(\complex_num_reads_reg_n_0_[0] ),
        .O(\complex_num_reads_dec[0]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h9F90)) 
    \complex_num_reads_dec[1]_i_1 
       (.I0(complex_num_reads_dec[1]),
        .I1(complex_num_reads_dec[0]),
        .I2(\complex_num_reads_dec[3]_i_3_n_0 ),
        .I3(\complex_num_reads_reg_n_0_[1] ),
        .O(\complex_num_reads_dec[1]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hA9FFA900)) 
    \complex_num_reads_dec[2]_i_1 
       (.I0(complex_num_reads_dec[2]),
        .I1(complex_num_reads_dec[0]),
        .I2(complex_num_reads_dec[1]),
        .I3(\complex_num_reads_dec[3]_i_3_n_0 ),
        .I4(\complex_num_reads_reg_n_0_[2] ),
        .O(\complex_num_reads_dec[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hDDDDDDDDDDDDDDD5)) 
    \complex_num_reads_dec[3]_i_1 
       (.I0(\complex_num_reads_dec[3]_i_3_n_0 ),
        .I1(\stg1_wr_rd_cnt[8]_i_4_n_0 ),
        .I2(complex_num_reads_dec[2]),
        .I3(complex_num_reads_dec[1]),
        .I4(complex_num_reads_dec[0]),
        .I5(complex_num_reads_dec[3]),
        .O(\complex_num_reads_dec[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAAA9FFFFAAA90000)) 
    \complex_num_reads_dec[3]_i_2 
       (.I0(complex_num_reads_dec[3]),
        .I1(complex_num_reads_dec[2]),
        .I2(complex_num_reads_dec[1]),
        .I3(complex_num_reads_dec[0]),
        .I4(\complex_num_reads_dec[3]_i_3_n_0 ),
        .I5(\complex_num_reads_reg_n_0_[3] ),
        .O(\complex_num_reads_dec[3]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h5555555554555555)) 
    \complex_num_reads_dec[3]_i_3 
       (.I0(\complex_num_reads_dec[3]_i_4_n_0 ),
        .I1(complex_oclkdelay_calib_start_int_i_2_n_0),
        .I2(\init_state_r_reg_n_0_[1] ),
        .I3(Q),
        .I4(\init_state_r[5]_i_13_n_0 ),
        .I5(complex_row0_rd_done),
        .O(\complex_num_reads_dec[3]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF00000020)) 
    \complex_num_reads_dec[3]_i_4 
       (.I0(\init_state_r_reg_n_0_[4] ),
        .I1(init_state_r),
        .I2(\init_state_r_reg_n_0_[5] ),
        .I3(\wrcal_reads[7]_i_4_n_0 ),
        .I4(prbs_rdlvl_start_i_2_n_0),
        .I5(stg1_wr_done),
        .O(\complex_num_reads_dec[3]_i_4_n_0 ));
  FDSE \complex_num_reads_dec_reg[0] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\complex_num_reads_dec[3]_i_1_n_0 ),
        .D(\complex_num_reads_dec[0]_i_1_n_0 ),
        .Q(complex_num_reads_dec[0]),
        .S(\en_cnt_div4.enable_wrlvl_cnt_reg[2]_0 ));
  FDRE \complex_num_reads_dec_reg[1] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\complex_num_reads_dec[3]_i_1_n_0 ),
        .D(\complex_num_reads_dec[1]_i_1_n_0 ),
        .Q(complex_num_reads_dec[1]),
        .R(\en_cnt_div4.enable_wrlvl_cnt_reg[2]_0 ));
  FDRE \complex_num_reads_dec_reg[2] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\complex_num_reads_dec[3]_i_1_n_0 ),
        .D(\complex_num_reads_dec[2]_i_1_n_0 ),
        .Q(complex_num_reads_dec[2]),
        .R(\en_cnt_div4.enable_wrlvl_cnt_reg[2]_0 ));
  FDRE \complex_num_reads_dec_reg[3] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\complex_num_reads_dec[3]_i_1_n_0 ),
        .D(\complex_num_reads_dec[3]_i_2_n_0 ),
        .Q(complex_num_reads_dec[3]),
        .R(\en_cnt_div4.enable_wrlvl_cnt_reg[2]_0 ));
  FDRE \complex_num_reads_reg[0] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\complex_num_reads[0]_i_1_n_0 ),
        .Q(\complex_num_reads_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \complex_num_reads_reg[1] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\complex_num_reads[1]_i_1_n_0 ),
        .Q(\complex_num_reads_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \complex_num_reads_reg[2] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\complex_num_reads[2]_i_1_n_0 ),
        .Q(\complex_num_reads_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \complex_num_reads_reg[3] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\complex_num_reads[3]_i_1_n_0 ),
        .Q(\complex_num_reads_reg_n_0_[3] ),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h22622E6EFFFFFFFF)) 
    \complex_num_writes[0]_i_1 
       (.I0(\complex_num_writes_reg_n_0_[0] ),
        .I1(\complex_num_writes[3]_i_2_n_0 ),
        .I2(\complex_num_writes[4]_i_5_n_0 ),
        .I3(\complex_num_writes[4]_i_6_n_0 ),
        .I4(\complex_num_writes[0]_i_2_n_0 ),
        .I5(\complex_num_writes[4]_i_2_n_0 ),
        .O(\complex_num_writes[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000800)) 
    \complex_num_writes[0]_i_2 
       (.I0(complex_row0_wr_done),
        .I1(\init_state_r_reg_n_0_[4] ),
        .I2(init_state_r),
        .I3(\init_state_r_reg_n_0_[5] ),
        .I4(\wrcal_reads[7]_i_4_n_0 ),
        .I5(prbs_rdlvl_start_i_2_n_0),
        .O(\complex_num_writes[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFEEE022200000000)) 
    \complex_num_writes[1]_i_1 
       (.I0(\complex_num_writes_reg_n_0_[1] ),
        .I1(\complex_num_writes[2]_i_4_n_0 ),
        .I2(\complex_num_writes[4]_i_5_n_0 ),
        .I3(\complex_num_writes[2]_i_5_n_0 ),
        .I4(\complex_num_writes[1]_i_2_n_0 ),
        .I5(\complex_num_writes[2]_i_2_n_0 ),
        .O(\complex_num_writes[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hCECECEEECEEECECE)) 
    \complex_num_writes[1]_i_2 
       (.I0(\complex_num_writes[4]_i_5_n_0 ),
        .I1(\complex_num_writes[0]_i_2_n_0 ),
        .I2(\complex_num_writes[4]_i_7_n_0 ),
        .I3(\complex_num_writes[4]_i_6_n_0 ),
        .I4(\complex_num_writes_reg_n_0_[0] ),
        .I5(\complex_num_writes_reg_n_0_[1] ),
        .O(\complex_num_writes[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h00008A808A808A80)) 
    \complex_num_writes[2]_i_1 
       (.I0(\complex_num_writes[2]_i_2_n_0 ),
        .I1(\complex_num_writes[2]_i_3_n_0 ),
        .I2(\complex_num_writes[2]_i_4_n_0 ),
        .I3(\complex_num_writes_reg_n_0_[2] ),
        .I4(\complex_num_writes[4]_i_5_n_0 ),
        .I5(\complex_num_writes[2]_i_5_n_0 ),
        .O(\complex_num_writes[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0222AAAAAAAAAAAA)) 
    \complex_num_writes[2]_i_2 
       (.I0(\complex_num_writes_reg[1]_0 ),
        .I1(\complex_num_writes[2]_i_7_n_0 ),
        .I2(\complex_num_writes_reg_n_0_[2] ),
        .I3(\complex_num_writes_reg_n_0_[1] ),
        .I4(\complex_num_writes[4]_i_12_n_0 ),
        .I5(\complex_num_writes[4]_i_5_n_0 ),
        .O(\complex_num_writes[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hBFFFFBBBAAAAAAAA)) 
    \complex_num_writes[2]_i_3 
       (.I0(\complex_num_writes[0]_i_2_n_0 ),
        .I1(\complex_num_writes[2]_i_8_n_0 ),
        .I2(\complex_num_writes_reg_n_0_[1] ),
        .I3(\complex_num_writes_reg_n_0_[0] ),
        .I4(\complex_num_writes_reg_n_0_[2] ),
        .I5(\complex_num_writes[4]_i_5_n_0 ),
        .O(\complex_num_writes[2]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair487" *) 
  LUT3 #(
    .INIT(8'hBA)) 
    \complex_num_writes[2]_i_4 
       (.I0(\complex_num_writes[4]_i_4_n_0 ),
        .I1(\complex_num_writes[2]_i_8_n_0 ),
        .I2(\complex_num_writes[4]_i_5_n_0 ),
        .O(\complex_num_writes[2]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000008000)) 
    \complex_num_writes[2]_i_5 
       (.I0(\complex_num_writes[2]_i_9_n_0 ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[4] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[2] ),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[0] ),
        .I4(\stg1_wr_rd_cnt_reg_n_0_[5] ),
        .I5(\stg1_wr_rd_cnt_reg_n_0_[3] ),
        .O(\complex_num_writes[2]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair415" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \complex_num_writes[2]_i_7 
       (.I0(\complex_num_writes_reg_n_0_[3] ),
        .I1(\complex_num_writes_reg_n_0_[4] ),
        .O(\complex_num_writes[2]_i_7_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair458" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \complex_num_writes[2]_i_8 
       (.I0(\complex_num_reads[3]_i_7_n_0 ),
        .I1(\complex_num_writes[4]_i_6_n_0 ),
        .O(\complex_num_writes[2]_i_8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair453" *) 
  LUT4 #(
    .INIT(16'h0004)) 
    \complex_num_writes[2]_i_9 
       (.I0(\stg1_wr_rd_cnt_reg_n_0_[1] ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[6] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[7] ),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[8] ),
        .O(\complex_num_writes[2]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hEEE2E2E200000000)) 
    \complex_num_writes[3]_i_1 
       (.I0(\complex_num_writes_reg_n_0_[3] ),
        .I1(\complex_num_writes[3]_i_2_n_0 ),
        .I2(\complex_num_writes[3]_i_3_n_0 ),
        .I3(complex_row0_wr_done),
        .I4(\complex_num_writes[3]_i_4_n_0 ),
        .I5(\complex_num_writes[4]_i_2_n_0 ),
        .O(\complex_num_writes[3]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'hF8)) 
    \complex_num_writes[3]_i_2 
       (.I0(\complex_num_writes[4]_i_6_n_0 ),
        .I1(\complex_num_writes[4]_i_5_n_0 ),
        .I2(\complex_num_writes[4]_i_4_n_0 ),
        .O(\complex_num_writes[3]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h8AA8A8A8A8A8A8A8)) 
    \complex_num_writes[3]_i_3 
       (.I0(\complex_num_writes[4]_i_5_n_0 ),
        .I1(\complex_num_writes[4]_i_6_n_0 ),
        .I2(\complex_num_writes_reg_n_0_[3] ),
        .I3(\complex_num_writes_reg_n_0_[1] ),
        .I4(\complex_num_writes_reg_n_0_[0] ),
        .I5(\complex_num_writes_reg_n_0_[2] ),
        .O(\complex_num_writes[3]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0000100000000000)) 
    \complex_num_writes[3]_i_4 
       (.I0(prbs_rdlvl_start_i_2_n_0),
        .I1(\init_state_r_reg_n_0_[3] ),
        .I2(\init_state_r_reg_n_0_[2] ),
        .I3(\init_state_r_reg_n_0_[5] ),
        .I4(init_state_r),
        .I5(\init_state_r_reg_n_0_[4] ),
        .O(\complex_num_writes[3]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h00008A808A808A80)) 
    \complex_num_writes[4]_i_1 
       (.I0(\complex_num_writes[4]_i_2_n_0 ),
        .I1(\complex_num_writes[4]_i_3_n_0 ),
        .I2(\complex_num_writes[4]_i_4_n_0 ),
        .I3(\complex_num_writes_reg_n_0_[4] ),
        .I4(\complex_num_writes[4]_i_5_n_0 ),
        .I5(\complex_num_writes[4]_i_6_n_0 ),
        .O(\complex_num_writes[4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF8880AAAA)) 
    \complex_num_writes[4]_i_10 
       (.I0(\stg1_wr_rd_cnt_reg_n_0_[6] ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[3] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[2] ),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[1] ),
        .I4(\complex_num_writes[4]_i_14_n_0 ),
        .I5(\complex_num_writes[4]_i_15_n_0 ),
        .O(\complex_num_writes[4]_i_10_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair439" *) 
  LUT5 #(
    .INIT(32'hFFFEEEEE)) 
    \complex_num_writes[4]_i_11 
       (.I0(\complex_num_writes_reg_n_0_[4] ),
        .I1(\complex_num_writes_reg_n_0_[3] ),
        .I2(\complex_num_writes_reg_n_0_[1] ),
        .I3(\complex_num_writes_reg_n_0_[0] ),
        .I4(\complex_num_writes_reg_n_0_[2] ),
        .O(\complex_num_writes[4]_i_11_n_0 ));
  LUT3 #(
    .INIT(8'hFE)) 
    \complex_num_writes[4]_i_12 
       (.I0(\stg1_wr_rd_cnt_reg_n_0_[8] ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[7] ),
        .I2(\complex_num_writes[4]_i_16_n_0 ),
        .O(\complex_num_writes[4]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFA8)) 
    \complex_num_writes[4]_i_13 
       (.I0(\stg1_wr_rd_cnt_reg_n_0_[5] ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[3] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[4] ),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[6] ),
        .I4(\stg1_wr_rd_cnt_reg_n_0_[8] ),
        .I5(\stg1_wr_rd_cnt_reg_n_0_[7] ),
        .O(\complex_num_writes[4]_i_13_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair481" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \complex_num_writes[4]_i_14 
       (.I0(\stg1_wr_rd_cnt_reg_n_0_[5] ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[4] ),
        .O(\complex_num_writes[4]_i_14_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair386" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \complex_num_writes[4]_i_15 
       (.I0(\stg1_wr_rd_cnt_reg_n_0_[7] ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[8] ),
        .O(\complex_num_writes[4]_i_15_n_0 ));
  LUT6 #(
    .INIT(64'hC8C8C8C0C8C0C8C0)) 
    \complex_num_writes[4]_i_16 
       (.I0(\stg1_wr_rd_cnt_reg_n_0_[4] ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[6] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[5] ),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[3] ),
        .I4(\stg1_wr_rd_cnt_reg_n_0_[1] ),
        .I5(\stg1_wr_rd_cnt_reg_n_0_[2] ),
        .O(\complex_num_writes[4]_i_16_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair487" *) 
  LUT3 #(
    .INIT(8'h8A)) 
    \complex_num_writes[4]_i_2 
       (.I0(\complex_num_writes[2]_i_2_n_0 ),
        .I1(\complex_num_writes[4]_i_7_n_0 ),
        .I2(\complex_num_writes[4]_i_5_n_0 ),
        .O(\complex_num_writes[4]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hC0EAEAC0EAC0EAC0)) 
    \complex_num_writes[4]_i_3 
       (.I0(\complex_num_writes[4]_i_5_n_0 ),
        .I1(complex_row0_wr_done),
        .I2(\complex_num_writes[3]_i_4_n_0 ),
        .I3(\complex_num_writes_reg_n_0_[4] ),
        .I4(\complex_num_writes[4]_i_8_n_0 ),
        .I5(\complex_num_writes_reg_n_0_[3] ),
        .O(\complex_num_writes[4]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFABFBAAAAAAAA)) 
    \complex_num_writes[4]_i_4 
       (.I0(\complex_num_writes[3]_i_4_n_0 ),
        .I1(\complex_num_writes[4]_i_9_n_0 ),
        .I2(\complex_num_writes[4]_i_10_n_0 ),
        .I3(\complex_num_writes[4]_i_11_n_0 ),
        .I4(\complex_num_writes[4]_i_12_n_0 ),
        .I5(\complex_num_writes[4]_i_5_n_0 ),
        .O(\complex_num_writes[4]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000800000)) 
    \complex_num_writes[4]_i_5 
       (.I0(complex_wait_cnt_reg[2]),
        .I1(complex_wait_cnt_reg[3]),
        .I2(complex_wait_cnt_reg[1]),
        .I3(complex_wait_cnt_reg[0]),
        .I4(\complex_address[9]_i_3_n_0 ),
        .I5(complex_row0_wr_done),
        .O(\complex_num_writes[4]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair385" *) 
  LUT5 #(
    .INIT(32'h40000000)) 
    \complex_num_writes[4]_i_6 
       (.I0(complex_sample_cnt_inc_i_3_n_0),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[5] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[0] ),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[1] ),
        .I4(\stg1_wr_rd_cnt_reg_n_0_[2] ),
        .O(\complex_num_writes[4]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hEFFFFFDFFFFFFFFF)) 
    \complex_num_writes[4]_i_7 
       (.I0(\stg1_wr_rd_cnt_reg_n_0_[3] ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[5] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[0] ),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[2] ),
        .I4(\stg1_wr_rd_cnt_reg_n_0_[4] ),
        .I5(\complex_num_writes[2]_i_9_n_0 ),
        .O(\complex_num_writes[4]_i_7_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair439" *) 
  LUT3 #(
    .INIT(8'h80)) 
    \complex_num_writes[4]_i_8 
       (.I0(\complex_num_writes_reg_n_0_[2] ),
        .I1(\complex_num_writes_reg_n_0_[0] ),
        .I2(\complex_num_writes_reg_n_0_[1] ),
        .O(\complex_num_writes[4]_i_8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair415" *) 
  LUT5 #(
    .INIT(32'hFEAAEAAA)) 
    \complex_num_writes[4]_i_9 
       (.I0(\complex_num_writes_reg_n_0_[4] ),
        .I1(\complex_num_writes_reg_n_0_[1] ),
        .I2(\complex_num_writes_reg_n_0_[2] ),
        .I3(\complex_num_writes_reg_n_0_[3] ),
        .I4(\complex_num_writes[4]_i_13_n_0 ),
        .O(\complex_num_writes[4]_i_9_n_0 ));
  LUT3 #(
    .INIT(8'h74)) 
    \complex_num_writes_dec[0]_i_1 
       (.I0(complex_num_writes_dec[0]),
        .I1(\complex_num_writes_dec[4]_i_4_n_0 ),
        .I2(\complex_num_writes_reg_n_0_[0] ),
        .O(\complex_num_writes_dec[0]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h9F90)) 
    \complex_num_writes_dec[1]_i_1 
       (.I0(complex_num_writes_dec[1]),
        .I1(complex_num_writes_dec[0]),
        .I2(\complex_num_writes_dec[4]_i_4_n_0 ),
        .I3(\complex_num_writes_reg_n_0_[1] ),
        .O(\complex_num_writes_dec[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair390" *) 
  LUT5 #(
    .INIT(32'hA9FFA900)) 
    \complex_num_writes_dec[2]_i_1 
       (.I0(complex_num_writes_dec[2]),
        .I1(complex_num_writes_dec[0]),
        .I2(complex_num_writes_dec[1]),
        .I3(\complex_num_writes_dec[4]_i_4_n_0 ),
        .I4(\complex_num_writes_reg_n_0_[2] ),
        .O(\complex_num_writes_dec[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAAA9FFFFAAA90000)) 
    \complex_num_writes_dec[3]_i_1 
       (.I0(complex_num_writes_dec[3]),
        .I1(complex_num_writes_dec[2]),
        .I2(complex_num_writes_dec[1]),
        .I3(complex_num_writes_dec[0]),
        .I4(\complex_num_writes_dec[4]_i_4_n_0 ),
        .I5(\complex_num_writes_reg_n_0_[3] ),
        .O(\complex_num_writes_dec[3]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \complex_num_writes_dec[4]_i_1 
       (.I0(prbs_rdlvl_done_pulse_reg_0),
        .I1(write_calib_reg_0),
        .O(complex_row0_rd_done1));
  LUT5 #(
    .INIT(32'hFDFF5555)) 
    \complex_num_writes_dec[4]_i_2 
       (.I0(\complex_num_writes_dec[4]_i_4_n_0 ),
        .I1(complex_num_writes_dec[4]),
        .I2(complex_num_writes_dec[3]),
        .I3(\complex_num_writes_dec[4]_i_5_n_0 ),
        .I4(\stg1_wr_rd_cnt[8]_i_5_n_0 ),
        .O(\complex_num_writes_dec[4]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h9AFF9A00)) 
    \complex_num_writes_dec[4]_i_3 
       (.I0(complex_num_writes_dec[4]),
        .I1(complex_num_writes_dec[3]),
        .I2(\complex_num_writes_dec[4]_i_5_n_0 ),
        .I3(\complex_num_writes_dec[4]_i_4_n_0 ),
        .I4(\complex_num_writes_reg_n_0_[4] ),
        .O(\complex_num_writes_dec[4]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'h000000DF)) 
    \complex_num_writes_dec[4]_i_4 
       (.I0(\init_state_r[5]_i_13_n_0 ),
        .I1(complex_row0_rd_done),
        .I2(\complex_address[9]_i_3_n_0 ),
        .I3(stg1_wr_done),
        .I4(\complex_num_writes[3]_i_4_n_0 ),
        .O(\complex_num_writes_dec[4]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair390" *) 
  LUT3 #(
    .INIT(8'h01)) 
    \complex_num_writes_dec[4]_i_5 
       (.I0(complex_num_writes_dec[0]),
        .I1(complex_num_writes_dec[1]),
        .I2(complex_num_writes_dec[2]),
        .O(\complex_num_writes_dec[4]_i_5_n_0 ));
  FDSE \complex_num_writes_dec_reg[0] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\complex_num_writes_dec[4]_i_2_n_0 ),
        .D(\complex_num_writes_dec[0]_i_1_n_0 ),
        .Q(complex_num_writes_dec[0]),
        .S(complex_row0_rd_done1));
  FDRE \complex_num_writes_dec_reg[1] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\complex_num_writes_dec[4]_i_2_n_0 ),
        .D(\complex_num_writes_dec[1]_i_1_n_0 ),
        .Q(complex_num_writes_dec[1]),
        .R(complex_row0_rd_done1));
  FDRE \complex_num_writes_dec_reg[2] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\complex_num_writes_dec[4]_i_2_n_0 ),
        .D(\complex_num_writes_dec[2]_i_1_n_0 ),
        .Q(complex_num_writes_dec[2]),
        .R(complex_row0_rd_done1));
  FDRE \complex_num_writes_dec_reg[3] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\complex_num_writes_dec[4]_i_2_n_0 ),
        .D(\complex_num_writes_dec[3]_i_1_n_0 ),
        .Q(complex_num_writes_dec[3]),
        .R(complex_row0_rd_done1));
  FDRE \complex_num_writes_dec_reg[4] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\complex_num_writes_dec[4]_i_2_n_0 ),
        .D(\complex_num_writes_dec[4]_i_3_n_0 ),
        .Q(complex_num_writes_dec[4]),
        .R(complex_row0_rd_done1));
  FDRE \complex_num_writes_reg[0] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\complex_num_writes[0]_i_1_n_0 ),
        .Q(\complex_num_writes_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \complex_num_writes_reg[1] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\complex_num_writes[1]_i_1_n_0 ),
        .Q(\complex_num_writes_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \complex_num_writes_reg[2] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\complex_num_writes[2]_i_1_n_0 ),
        .Q(\complex_num_writes_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \complex_num_writes_reg[3] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\complex_num_writes[3]_i_1_n_0 ),
        .Q(\complex_num_writes_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \complex_num_writes_reg[4] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\complex_num_writes[4]_i_1_n_0 ),
        .Q(\complex_num_writes_reg_n_0_[4] ),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h00000000FFFFFFDF)) 
    complex_ocal_odt_ext_i_1
       (.I0(cnt_cmd_done_m7_r),
        .I1(prbs_rdlvl_start_i_2_n_0),
        .I2(\init_state_r_reg_n_0_[4] ),
        .I3(\init_state_r[3]_i_6_n_0 ),
        .I4(\cnt_init_mr_r[0]_i_2_n_0 ),
        .I5(complex_ocal_odt_ext_i_2_n_0),
        .O(complex_ocal_odt_ext_i_1_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFF1100FFF0)) 
    complex_ocal_odt_ext_i_2
       (.I0(complex_ocal_odt_ext_i_3_n_0),
        .I1(Q),
        .I2(prbs_rdlvl_start_i_3_n_0),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(complex_ocal_odt_ext),
        .I5(write_calib_reg_0),
        .O(complex_ocal_odt_ext_i_2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair423" *) 
  LUT5 #(
    .INIT(32'hFFEFFFFF)) 
    complex_ocal_odt_ext_i_3
       (.I0(\init_state_r_reg_n_0_[2] ),
        .I1(\init_state_r_reg_n_0_[3] ),
        .I2(\init_state_r_reg_n_0_[4] ),
        .I3(init_state_r),
        .I4(\init_state_r_reg_n_0_[5] ),
        .O(complex_ocal_odt_ext_i_3_n_0));
  FDRE complex_ocal_odt_ext_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(complex_ocal_odt_ext_i_1_n_0),
        .Q(complex_ocal_odt_ext),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h44444F4444444444)) 
    complex_ocal_reset_rd_addr_i_1
       (.I0(prbs_last_byte_done_r),
        .I1(prbs_last_byte_done),
        .I2(complex_ocal_reset_rd_addr_i_2_n_0),
        .I3(complex_wait_cnt_reg[3]),
        .I4(complex_wait_cnt_reg[2]),
        .I5(complex_ocal_reset_rd_addr_i_3_n_0),
        .O(complex_ocal_reset_rd_addr0));
  (* SOFT_HLUTNM = "soft_lutpair530" *) 
  LUT2 #(
    .INIT(4'hB)) 
    complex_ocal_reset_rd_addr_i_2
       (.I0(complex_wait_cnt_reg[1]),
        .I1(complex_wait_cnt_reg[0]),
        .O(complex_ocal_reset_rd_addr_i_2_n_0));
  LUT6 #(
    .INIT(64'h0080000000000000)) 
    complex_ocal_reset_rd_addr_i_3
       (.I0(\wrcal_reads[7]_i_5_n_0 ),
        .I1(\init_state_r_reg_n_0_[2] ),
        .I2(\init_state_r_reg_n_0_[5] ),
        .I3(init_state_r),
        .I4(\init_state_r_reg_n_0_[4] ),
        .I5(\init_state_r_reg_n_0_[3] ),
        .O(complex_ocal_reset_rd_addr_i_3_n_0));
  FDRE complex_ocal_reset_rd_addr_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(complex_ocal_reset_rd_addr0),
        .Q(complex_ocal_reset_rd_addr),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair490" *) 
  LUT2 #(
    .INIT(4'hE)) 
    complex_ocal_wr_start_i_1
       (.I0(complex_ocal_reset_rd_addr),
        .I1(complex_ocal_wr_start),
        .O(complex_ocal_wr_start_i_1_n_0));
  FDRE complex_ocal_wr_start_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(complex_ocal_wr_start_i_1_n_0),
        .Q(complex_ocal_wr_start),
        .R(\victim_sel_reg[0]_0 ));
  FDRE complex_oclkdelay_calib_done_r1_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(complex_oclkdelay_calib_done_r1_reg_0),
        .Q(complex_oclkdelay_calib_done_r1),
        .R(\victim_sel_reg[0]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair440" *) 
  LUT5 #(
    .INIT(32'hFFFF1000)) 
    complex_oclkdelay_calib_start_int_i_1
       (.I0(complex_oclkdelay_calib_start_int_i_2_n_0),
        .I1(Q),
        .I2(\init_state_r_reg_n_0_[1] ),
        .I3(prbs_last_byte_done_r),
        .I4(complex_oclkdelay_calib_start_int),
        .O(complex_oclkdelay_calib_start_int_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair408" *) 
  LUT5 #(
    .INIT(32'hFFDFFFFF)) 
    complex_oclkdelay_calib_start_int_i_2
       (.I0(\init_state_r_reg_n_0_[3] ),
        .I1(\init_state_r_reg_n_0_[2] ),
        .I2(\init_state_r_reg_n_0_[4] ),
        .I3(init_state_r),
        .I4(\init_state_r_reg_n_0_[5] ),
        .O(complex_oclkdelay_calib_start_int_i_2_n_0));
  FDRE complex_oclkdelay_calib_start_int_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(complex_oclkdelay_calib_start_int_i_1_n_0),
        .Q(complex_oclkdelay_calib_start_int),
        .R(\victim_sel_reg[0]_0 ));
  FDRE complex_oclkdelay_calib_start_r1_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(complex_oclkdelay_calib_start_int),
        .Q(complex_oclkdelay_calib_start_r1),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000055551000)) 
    complex_odt_ext_i_1
       (.I0(write_calib_reg_0),
        .I1(complex_sample_cnt_inc_i_2_n_0),
        .I2(rdlvl_stg1_done_r1),
        .I3(\stg1_wr_rd_cnt[8]_i_5_n_0 ),
        .I4(complex_odt_ext),
        .I5(complex_row1_rd_done_i_2_n_0),
        .O(complex_odt_ext_i_1_n_0));
  FDRE complex_odt_ext_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(complex_odt_ext_i_1_n_0),
        .Q(complex_odt_ext),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair461" *) 
  LUT4 #(
    .INIT(16'h0010)) 
    complex_row0_rd_done_i_1
       (.I0(prbs_rdlvl_done_pulse_reg_0),
        .I1(write_calib_reg_0),
        .I2(complex_row0_rd_done_i_2_n_0),
        .I3(complex_sample_cnt_inc),
        .O(complex_row0_rd_done_i_1_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFF0000E000)) 
    complex_row0_rd_done_i_2
       (.I0(prbs_rdlvl_start_reg_0),
        .I1(complex_oclkdelay_calib_start_int),
        .I2(complex_row1_wr_done),
        .I3(complex_row0_wr_done),
        .I4(wr_victim_inc_i_2_n_0),
        .I5(complex_row0_rd_done),
        .O(complex_row0_rd_done_i_2_n_0));
  FDRE complex_row0_rd_done_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(complex_row0_rd_done_i_1_n_0),
        .Q(complex_row0_rd_done),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h0000009A)) 
    \complex_row1_rd_cnt[0]_i_1 
       (.I0(complex_row1_rd_cnt[0]),
        .I1(complex_row1_rd_done_r1),
        .I2(complex_row1_rd_done),
        .I3(\rd_addr_reg[7] ),
        .I4(prbs_rdlvl_done_pulse_reg_0),
        .O(\complex_row1_rd_cnt[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000009AAA)) 
    \complex_row1_rd_cnt[1]_i_1 
       (.I0(complex_row1_rd_cnt[1]),
        .I1(complex_row1_rd_done_r1),
        .I2(complex_row1_rd_done),
        .I3(complex_row1_rd_cnt[0]),
        .I4(\rd_addr_reg[7] ),
        .I5(prbs_rdlvl_done_pulse_reg_0),
        .O(\complex_row1_rd_cnt[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h000000009AAAAAAA)) 
    \complex_row1_rd_cnt[2]_i_1 
       (.I0(complex_row1_rd_cnt[2]),
        .I1(complex_row1_rd_done_r1),
        .I2(complex_row1_rd_done),
        .I3(complex_row1_rd_cnt[1]),
        .I4(complex_row1_rd_cnt[0]),
        .I5(complex_row0_rd_done1),
        .O(\complex_row1_rd_cnt[2]_i_1_n_0 ));
  FDRE \complex_row1_rd_cnt_reg[0] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\complex_row1_rd_cnt[0]_i_1_n_0 ),
        .Q(complex_row1_rd_cnt[0]),
        .R(1'b0));
  FDRE \complex_row1_rd_cnt_reg[1] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\complex_row1_rd_cnt[1]_i_1_n_0 ),
        .Q(complex_row1_rd_cnt[1]),
        .R(1'b0));
  FDRE \complex_row1_rd_cnt_reg[2] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\complex_row1_rd_cnt[2]_i_1_n_0 ),
        .Q(complex_row1_rd_cnt[2]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000011110100)) 
    complex_row1_rd_done_i_1
       (.I0(write_calib_reg_0),
        .I1(prbs_rdlvl_done_pulse_reg_0),
        .I2(wr_victim_inc_i_2_n_0),
        .I3(complex_row0_rd_done),
        .I4(complex_row1_rd_done),
        .I5(complex_row1_rd_done_i_2_n_0),
        .O(complex_row1_rd_done_i_1_n_0));
  LUT6 #(
    .INIT(64'h0000000000000020)) 
    complex_row1_rd_done_i_2
       (.I0(\init_state_r_reg_n_0_[4] ),
        .I1(\init_state_r_reg_n_0_[3] ),
        .I2(\init_state_r_reg_n_0_[2] ),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(Q),
        .I5(init_state_r),
        .O(complex_row1_rd_done_i_2_n_0));
  FDRE complex_row1_rd_done_r1_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(complex_row1_rd_done),
        .Q(complex_row1_rd_done_r1),
        .R(1'b0));
  FDRE complex_row1_rd_done_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(complex_row1_rd_done_i_1_n_0),
        .Q(complex_row1_rd_done),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \complex_row_cnt_ocal[0]_i_1 
       (.I0(complex_row_cnt_ocal_reg[0]),
        .O(p_0_in__6[0]));
  (* SOFT_HLUTNM = "soft_lutpair500" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \complex_row_cnt_ocal[1]_i_1 
       (.I0(complex_row_cnt_ocal_reg[1]),
        .I1(complex_row_cnt_ocal_reg[0]),
        .O(p_0_in__6[1]));
  (* SOFT_HLUTNM = "soft_lutpair500" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \complex_row_cnt_ocal[2]_i_1 
       (.I0(complex_row_cnt_ocal_reg[2]),
        .I1(complex_row_cnt_ocal_reg[0]),
        .I2(complex_row_cnt_ocal_reg[1]),
        .O(p_0_in__6[2]));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFF8F)) 
    \complex_row_cnt_ocal[3]_i_1 
       (.I0(wr_victim_inc),
        .I1(\complex_row_cnt_ocal[3]_i_4_n_0 ),
        .I2(rdlvl_stg1_done_r1),
        .I3(complex_byte_rd_done),
        .I4(prbs_rdlvl_done_pulse_reg_0),
        .I5(write_calib_reg_0),
        .O(complex_row_cnt_ocal0));
  LUT6 #(
    .INIT(64'h00000000FFF80000)) 
    \complex_row_cnt_ocal[3]_i_2 
       (.I0(\complex_row_cnt_ocal[3]_i_5_n_0 ),
        .I1(\complex_row_cnt_ocal[3]_i_6_n_0 ),
        .I2(wr_victim_inc),
        .I3(complex_sample_cnt_inc_r2),
        .I4(complex_oclkdelay_calib_done_r1_reg_0),
        .I5(\complex_row_cnt_ocal[3]_i_4_n_0 ),
        .O(complex_row_cnt_ocal));
  (* SOFT_HLUTNM = "soft_lutpair451" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \complex_row_cnt_ocal[3]_i_3 
       (.I0(complex_row_cnt_ocal_reg[3]),
        .I1(complex_row_cnt_ocal_reg[1]),
        .I2(complex_row_cnt_ocal_reg[0]),
        .I3(complex_row_cnt_ocal_reg[2]),
        .O(p_0_in__6[3]));
  (* SOFT_HLUTNM = "soft_lutpair451" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \complex_row_cnt_ocal[3]_i_4 
       (.I0(complex_row_cnt_ocal_reg[3]),
        .I1(complex_row_cnt_ocal_reg[1]),
        .I2(complex_row_cnt_ocal_reg[0]),
        .I3(complex_row_cnt_ocal_reg[2]),
        .O(\complex_row_cnt_ocal[3]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h1000000000000000)) 
    \complex_row_cnt_ocal[3]_i_5 
       (.I0(wr_victim_inc_i_3_n_0),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[0] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[1] ),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[3] ),
        .I4(\stg1_wr_rd_cnt_reg_n_0_[2] ),
        .I5(\stg1_wr_rd_cnt_reg_n_0_[4] ),
        .O(\complex_row_cnt_ocal[3]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h0000010000000000)) 
    \complex_row_cnt_ocal[3]_i_6 
       (.I0(Q),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(\wrcal_reads[7]_i_4_n_0 ),
        .I3(\init_state_r_reg_n_0_[5] ),
        .I4(init_state_r),
        .I5(\init_state_r_reg_n_0_[4] ),
        .O(\complex_row_cnt_ocal[3]_i_6_n_0 ));
  FDRE \complex_row_cnt_ocal_reg[0] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(complex_row_cnt_ocal),
        .D(p_0_in__6[0]),
        .Q(complex_row_cnt_ocal_reg[0]),
        .R(complex_row_cnt_ocal0));
  FDRE \complex_row_cnt_ocal_reg[1] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(complex_row_cnt_ocal),
        .D(p_0_in__6[1]),
        .Q(complex_row_cnt_ocal_reg[1]),
        .R(complex_row_cnt_ocal0));
  FDRE \complex_row_cnt_ocal_reg[2] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(complex_row_cnt_ocal),
        .D(p_0_in__6[2]),
        .Q(complex_row_cnt_ocal_reg[2]),
        .R(complex_row_cnt_ocal0));
  FDRE \complex_row_cnt_ocal_reg[3] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(complex_row_cnt_ocal),
        .D(p_0_in__6[3]),
        .Q(complex_row_cnt_ocal_reg[3]),
        .R(complex_row_cnt_ocal0));
  LUT2 #(
    .INIT(4'h2)) 
    complex_sample_cnt_inc_i_1
       (.I0(complex_row1_rd_done),
        .I1(complex_sample_cnt_inc_i_2_n_0),
        .O(complex_sample_cnt_inc0));
  (* SOFT_HLUTNM = "soft_lutpair385" *) 
  LUT5 #(
    .INIT(32'hFFFFFFFB)) 
    complex_sample_cnt_inc_i_2
       (.I0(\stg1_wr_rd_cnt_reg_n_0_[2] ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[0] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[1] ),
        .I3(complex_sample_cnt_inc_i_3_n_0),
        .I4(\stg1_wr_rd_cnt_reg_n_0_[5] ),
        .O(complex_sample_cnt_inc_i_2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair386" *) 
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    complex_sample_cnt_inc_i_3
       (.I0(\stg1_wr_rd_cnt_reg_n_0_[7] ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[8] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[6] ),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[4] ),
        .I4(\stg1_wr_rd_cnt_reg_n_0_[3] ),
        .O(complex_sample_cnt_inc_i_3_n_0));
  FDRE complex_sample_cnt_inc_r1_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(complex_sample_cnt_inc),
        .Q(complex_sample_cnt_inc_r1),
        .R(1'b0));
  FDRE complex_sample_cnt_inc_r2_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(complex_sample_cnt_inc_r1),
        .Q(complex_sample_cnt_inc_r2),
        .R(1'b0));
  FDRE complex_sample_cnt_inc_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(complex_sample_cnt_inc0),
        .Q(complex_sample_cnt_inc),
        .R(\victim_sel_reg[0]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \complex_wait_cnt[0]_i_1 
       (.I0(complex_wait_cnt_reg[0]),
        .O(p_0_in__7[0]));
  (* SOFT_HLUTNM = "soft_lutpair530" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \complex_wait_cnt[1]_i_1 
       (.I0(complex_wait_cnt_reg[1]),
        .I1(complex_wait_cnt_reg[0]),
        .O(p_0_in__7[1]));
  (* SOFT_HLUTNM = "soft_lutpair437" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \complex_wait_cnt[2]_i_1 
       (.I0(complex_wait_cnt_reg[1]),
        .I1(complex_wait_cnt_reg[0]),
        .I2(complex_wait_cnt_reg[2]),
        .O(p_0_in__7[2]));
  LUT6 #(
    .INIT(64'hFFFFFFFFEAAAAAAA)) 
    \complex_wait_cnt[3]_i_1 
       (.I0(\complex_wait_cnt[3]_i_3_n_0 ),
        .I1(complex_wait_cnt_reg[0]),
        .I2(complex_wait_cnt_reg[1]),
        .I3(complex_wait_cnt_reg[2]),
        .I4(complex_wait_cnt_reg[3]),
        .I5(\rd_addr_reg[7] ),
        .O(\complex_wait_cnt[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair422" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \complex_wait_cnt[3]_i_2 
       (.I0(complex_wait_cnt_reg[3]),
        .I1(complex_wait_cnt_reg[1]),
        .I2(complex_wait_cnt_reg[0]),
        .I3(complex_wait_cnt_reg[2]),
        .O(p_0_in__7[3]));
  LUT6 #(
    .INIT(64'hFFDFDDDFFDFFDFFF)) 
    \complex_wait_cnt[3]_i_3 
       (.I0(\init_state_r_reg_n_0_[4] ),
        .I1(complex_act_start_i_2_n_0),
        .I2(\init_state_r_reg_n_0_[2] ),
        .I3(\init_state_r_reg_n_0_[3] ),
        .I4(\init_state_r_reg_n_0_[1] ),
        .I5(Q),
        .O(\complex_wait_cnt[3]_i_3_n_0 ));
  FDRE \complex_wait_cnt_reg[0] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(p_0_in__7[0]),
        .Q(complex_wait_cnt_reg[0]),
        .R(\complex_wait_cnt[3]_i_1_n_0 ));
  FDRE \complex_wait_cnt_reg[1] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(p_0_in__7[1]),
        .Q(complex_wait_cnt_reg[1]),
        .R(\complex_wait_cnt[3]_i_1_n_0 ));
  FDRE \complex_wait_cnt_reg[2] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(p_0_in__7[2]),
        .Q(complex_wait_cnt_reg[2]),
        .R(\complex_wait_cnt[3]_i_1_n_0 ));
  FDRE \complex_wait_cnt_reg[3] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(p_0_in__7[3]),
        .Q(complex_wait_cnt_reg[3]),
        .R(\complex_wait_cnt[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair496" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_offset_1_i1[0]_i_1 
       (.I0(\data_offset_1_i1_reg[0] ),
        .I1(phy_ctl_wr_i1_reg),
        .I2(calib_data_offset_1[0]),
        .O(\cmd_pipe_plus.mc_data_offset_1_reg[5] [0]));
  (* SOFT_HLUTNM = "soft_lutpair497" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_offset_1_i1[1]_i_1 
       (.I0(\data_offset_1_i1_reg[1] ),
        .I1(phy_ctl_wr_i1_reg),
        .I2(calib_data_offset_1[1]),
        .O(\cmd_pipe_plus.mc_data_offset_1_reg[5] [1]));
  (* SOFT_HLUTNM = "soft_lutpair499" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_offset_1_i1[2]_i_1 
       (.I0(\data_offset_1_i1_reg[2] ),
        .I1(phy_ctl_wr_i1_reg),
        .I2(calib_data_offset_1[2]),
        .O(\cmd_pipe_plus.mc_data_offset_1_reg[5] [2]));
  (* SOFT_HLUTNM = "soft_lutpair501" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_offset_1_i1[3]_i_1 
       (.I0(mc_data_offset_1),
        .I1(phy_ctl_wr_i1_reg),
        .I2(calib_data_offset_1[3]),
        .O(\cmd_pipe_plus.mc_data_offset_1_reg[5] [3]));
  (* SOFT_HLUTNM = "soft_lutpair501" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_offset_1_i1[4]_i_1 
       (.I0(\data_offset_1_i1_reg[4] ),
        .I1(phy_ctl_wr_i1_reg),
        .I2(calib_data_offset_1[4]),
        .O(\cmd_pipe_plus.mc_data_offset_1_reg[5] [4]));
  (* SOFT_HLUTNM = "soft_lutpair497" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_offset_1_i1[5]_i_1 
       (.I0(\data_offset_1_i1_reg[5] ),
        .I1(phy_ctl_wr_i1_reg),
        .I2(calib_data_offset_1[5]),
        .O(\cmd_pipe_plus.mc_data_offset_1_reg[5] [5]));
  (* SOFT_HLUTNM = "soft_lutpair496" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_offset_2_i1[0]_i_1 
       (.I0(\data_offset_2_i1_reg[0] ),
        .I1(phy_ctl_wr_i1_reg),
        .I2(calib_data_offset_2[0]),
        .O(\cmd_pipe_plus.mc_data_offset_2_reg[5] [0]));
  (* SOFT_HLUTNM = "soft_lutpair499" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_offset_2_i1[1]_i_1 
       (.I0(\data_offset_2_i1_reg[1] ),
        .I1(phy_ctl_wr_i1_reg),
        .I2(calib_data_offset_2[1]),
        .O(\cmd_pipe_plus.mc_data_offset_2_reg[5] [1]));
  (* SOFT_HLUTNM = "soft_lutpair508" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_offset_2_i1[2]_i_1 
       (.I0(\data_offset_2_i1_reg[2] ),
        .I1(phy_ctl_wr_i1_reg),
        .I2(calib_data_offset_2[2]),
        .O(\cmd_pipe_plus.mc_data_offset_2_reg[5] [2]));
  (* SOFT_HLUTNM = "soft_lutpair508" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_offset_2_i1[3]_i_1 
       (.I0(mc_data_offset_2),
        .I1(phy_ctl_wr_i1_reg),
        .I2(calib_data_offset_2[3]),
        .O(\cmd_pipe_plus.mc_data_offset_2_reg[5] [3]));
  (* SOFT_HLUTNM = "soft_lutpair516" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_offset_2_i1[4]_i_1 
       (.I0(\data_offset_2_i1_reg[4] ),
        .I1(phy_ctl_wr_i1_reg),
        .I2(calib_data_offset_2[4]),
        .O(\cmd_pipe_plus.mc_data_offset_2_reg[5] [4]));
  (* SOFT_HLUTNM = "soft_lutpair516" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \data_offset_2_i1[5]_i_1 
       (.I0(\data_offset_2_i1_reg[5] ),
        .I1(phy_ctl_wr_i1_reg),
        .I2(calib_data_offset_2[5]),
        .O(\cmd_pipe_plus.mc_data_offset_2_reg[5] [5]));
  LUT6 #(
    .INIT(64'h2222222222F02222)) 
    ddr2_pre_flag_r_i_1
       (.I0(ddr2_pre_flag_r_reg_n_0),
        .I1(ddr2_pre_flag_r_i_2_n_0),
        .I2(\init_state_r_reg_n_0_[1] ),
        .I3(Q),
        .I4(\cnt_init_mr_r[0]_i_3_n_0 ),
        .I5(\cnt_init_mr_r[0]_i_2_n_0 ),
        .O(ddr2_pre_flag_r_i_1_n_0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    ddr2_pre_flag_r_i_2
       (.I0(ddr2_refresh_flag_r_i_3_n_0),
        .I1(Q),
        .I2(\init_state_r_reg_n_0_[1] ),
        .I3(cnt_cmd_done_r),
        .I4(ddr2_refresh_flag_r),
        .I5(cnt_init_mr_done_r),
        .O(ddr2_pre_flag_r_i_2_n_0));
  FDRE ddr2_pre_flag_r_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(ddr2_pre_flag_r_i_1_n_0),
        .Q(ddr2_pre_flag_r_reg_n_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000FF8CFFCCFFCC)) 
    ddr2_refresh_flag_r_i_1
       (.I0(ddr2_refresh_flag_r_i_2_n_0),
        .I1(ddr2_refresh_flag_r),
        .I2(cnt_init_mr_done_r),
        .I3(cnt_init_mr_r1),
        .I4(\wrcal_reads[7]_i_5_n_0 ),
        .I5(ddr2_refresh_flag_r_i_3_n_0),
        .O(ddr2_refresh_flag_r_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair463" *) 
  LUT3 #(
    .INIT(8'h7F)) 
    ddr2_refresh_flag_r_i_2
       (.I0(Q),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(cnt_cmd_done_r),
        .O(ddr2_refresh_flag_r_i_2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair427" *) 
  LUT5 #(
    .INIT(32'h00000001)) 
    ddr2_refresh_flag_r_i_3
       (.I0(init_state_r),
        .I1(\init_state_r_reg_n_0_[5] ),
        .I2(\init_state_r_reg_n_0_[4] ),
        .I3(\init_state_r_reg_n_0_[2] ),
        .I4(\init_state_r_reg_n_0_[3] ),
        .O(ddr2_refresh_flag_r_i_3_n_0));
  FDRE ddr2_refresh_flag_r_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(ddr2_refresh_flag_r_i_1_n_0),
        .Q(ddr2_refresh_flag_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF00000004)) 
    ddr3_lm_done_r_i_1
       (.I0(prbs_rdlvl_start_i_2_n_0),
        .I1(ddr3_lm_done_r_reg_0),
        .I2(\init_state_r[3]_i_6_n_0 ),
        .I3(\init_state_r_reg_n_0_[4] ),
        .I4(\cnt_init_mr_r[0]_i_2_n_0 ),
        .I5(ddr3_lm_done_r),
        .O(ddr3_lm_done_r_i_1_n_0));
  FDRE ddr3_lm_done_r_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(ddr3_lm_done_r_i_1_n_0),
        .Q(ddr3_lm_done_r),
        .R(\en_cnt_div4.enable_wrlvl_cnt_reg[2]_0 ));
  LUT6 #(
    .INIT(64'h0000000010000000)) 
    detect_pi_found_dqs_i_1
       (.I0(\cnt_init_mr_r[0]_i_2_n_0 ),
        .I1(\init_state_r[3]_i_6_n_0 ),
        .I2(\init_state_r_reg_n_0_[4] ),
        .I3(detect_pi_found_dqs_i_2_n_0),
        .I4(\cnt_cmd_r[6]_i_4_n_0 ),
        .I5(\cnt_cmd_r_reg_n_0_[6] ),
        .O(detect_pi_found_dqs0));
  (* SOFT_HLUTNM = "soft_lutpair440" *) 
  LUT2 #(
    .INIT(4'h2)) 
    detect_pi_found_dqs_i_2
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(Q),
        .O(detect_pi_found_dqs_i_2_n_0));
  FDRE detect_pi_found_dqs_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(detect_pi_found_dqs0),
        .Q(detect_pi_found_dqs),
        .R(\en_cnt_div4.enable_wrlvl_cnt_reg[2]_0 ));
  LUT6 #(
    .INIT(64'h00000000DADA00DA)) 
    \dqs_asrt_cnt[0]_i_1 
       (.I0(dqs_asrt_cnt[0]),
        .I1(dqs_asrt_cnt[1]),
        .I2(wr_level_dqs_asrt),
        .I3(wrlvl_done_r),
        .I4(wrlvl_done_r1),
        .I5(\rd_addr_reg[7] ),
        .O(\dqs_asrt_cnt[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000ECEC00EC)) 
    \dqs_asrt_cnt[1]_i_1 
       (.I0(dqs_asrt_cnt[0]),
        .I1(dqs_asrt_cnt[1]),
        .I2(wr_level_dqs_asrt),
        .I3(wrlvl_done_r),
        .I4(wrlvl_done_r1),
        .I5(\rd_addr_reg[7] ),
        .O(\dqs_asrt_cnt[1]_i_1_n_0 ));
  FDRE \dqs_asrt_cnt_reg[0] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\dqs_asrt_cnt[0]_i_1_n_0 ),
        .Q(dqs_asrt_cnt[0]),
        .R(1'b0));
  FDRE \dqs_asrt_cnt_reg[1] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\dqs_asrt_cnt[1]_i_1_n_0 ),
        .Q(dqs_asrt_cnt[1]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000033333332)) 
    \en_cnt_div4.enable_wrlvl_cnt[0]_i_1 
       (.I0(enable_wrlvl_cnt[1]),
        .I1(enable_wrlvl_cnt[0]),
        .I2(enable_wrlvl_cnt[3]),
        .I3(enable_wrlvl_cnt[2]),
        .I4(enable_wrlvl_cnt[4]),
        .I5(\en_cnt_div4.enable_wrlvl_cnt_reg[4]_0 ),
        .O(\en_cnt_div4.enable_wrlvl_cnt[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000099999998)) 
    \en_cnt_div4.enable_wrlvl_cnt[1]_i_1 
       (.I0(enable_wrlvl_cnt[1]),
        .I1(enable_wrlvl_cnt[0]),
        .I2(enable_wrlvl_cnt[3]),
        .I3(enable_wrlvl_cnt[2]),
        .I4(enable_wrlvl_cnt[4]),
        .I5(\en_cnt_div4.enable_wrlvl_cnt_reg[4]_0 ),
        .O(\en_cnt_div4.enable_wrlvl_cnt[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFEE11EE10)) 
    \en_cnt_div4.enable_wrlvl_cnt[2]_i_1 
       (.I0(enable_wrlvl_cnt[1]),
        .I1(enable_wrlvl_cnt[0]),
        .I2(enable_wrlvl_cnt[3]),
        .I3(enable_wrlvl_cnt[2]),
        .I4(enable_wrlvl_cnt[4]),
        .I5(\init_state_r_reg[4]_0 ),
        .O(\en_cnt_div4.enable_wrlvl_cnt[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFF0E1F0E0)) 
    \en_cnt_div4.enable_wrlvl_cnt[3]_i_1 
       (.I0(enable_wrlvl_cnt[1]),
        .I1(enable_wrlvl_cnt[0]),
        .I2(enable_wrlvl_cnt[3]),
        .I3(enable_wrlvl_cnt[2]),
        .I4(enable_wrlvl_cnt[4]),
        .I5(\init_state_r_reg[4]_0 ),
        .O(\en_cnt_div4.enable_wrlvl_cnt[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0002FFFF00020002)) 
    \en_cnt_div4.enable_wrlvl_cnt[3]_i_2 
       (.I0(detect_pi_found_dqs_i_2_n_0),
        .I1(\init_state_r[3]_i_6_n_0 ),
        .I2(\init_state_r_reg_n_0_[4] ),
        .I3(\wrcal_reads[7]_i_4_n_0 ),
        .I4(enable_wrlvl_cnt0),
        .I5(wrlvl_odt),
        .O(\init_state_r_reg[4]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair434" *) 
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \en_cnt_div4.enable_wrlvl_cnt[3]_i_3 
       (.I0(enable_wrlvl_cnt[4]),
        .I1(enable_wrlvl_cnt[2]),
        .I2(enable_wrlvl_cnt[3]),
        .I3(enable_wrlvl_cnt[0]),
        .I4(enable_wrlvl_cnt[1]),
        .O(enable_wrlvl_cnt0));
  LUT6 #(
    .INIT(64'h00000000FFFE0000)) 
    \en_cnt_div4.enable_wrlvl_cnt[4]_i_1 
       (.I0(enable_wrlvl_cnt[1]),
        .I1(enable_wrlvl_cnt[0]),
        .I2(enable_wrlvl_cnt[3]),
        .I3(enable_wrlvl_cnt[2]),
        .I4(enable_wrlvl_cnt[4]),
        .I5(\en_cnt_div4.enable_wrlvl_cnt_reg[4]_0 ),
        .O(\en_cnt_div4.enable_wrlvl_cnt[4]_i_1_n_0 ));
  FDRE \en_cnt_div4.enable_wrlvl_cnt_reg[0] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\en_cnt_div4.enable_wrlvl_cnt[0]_i_1_n_0 ),
        .Q(enable_wrlvl_cnt[0]),
        .R(1'b0));
  FDRE \en_cnt_div4.enable_wrlvl_cnt_reg[1] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\en_cnt_div4.enable_wrlvl_cnt[1]_i_1_n_0 ),
        .Q(enable_wrlvl_cnt[1]),
        .R(1'b0));
  FDRE \en_cnt_div4.enable_wrlvl_cnt_reg[2] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\en_cnt_div4.enable_wrlvl_cnt[2]_i_1_n_0 ),
        .Q(enable_wrlvl_cnt[2]),
        .R(\en_cnt_div4.enable_wrlvl_cnt_reg[2]_0 ));
  FDRE \en_cnt_div4.enable_wrlvl_cnt_reg[3] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\en_cnt_div4.enable_wrlvl_cnt[3]_i_1_n_0 ),
        .Q(enable_wrlvl_cnt[3]),
        .R(\en_cnt_div4.enable_wrlvl_cnt_reg[2]_0 ));
  FDRE \en_cnt_div4.enable_wrlvl_cnt_reg[4] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\en_cnt_div4.enable_wrlvl_cnt[4]_i_1_n_0 ),
        .Q(enable_wrlvl_cnt[4]),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h0054)) 
    \en_cnt_div4.wrlvl_odt_i_1 
       (.I0(write_calib_reg_0),
        .I1(\en_cnt_div4.wrlvl_odt_i_2_n_0 ),
        .I2(wrlvl_odt),
        .I3(wrlvl_odt_ctl),
        .O(\en_cnt_div4.wrlvl_odt_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair434" *) 
  LUT5 #(
    .INIT(32'h00000100)) 
    \en_cnt_div4.wrlvl_odt_i_2 
       (.I0(enable_wrlvl_cnt[2]),
        .I1(enable_wrlvl_cnt[3]),
        .I2(enable_wrlvl_cnt[4]),
        .I3(enable_wrlvl_cnt[0]),
        .I4(enable_wrlvl_cnt[1]),
        .O(\en_cnt_div4.wrlvl_odt_i_2_n_0 ));
  FDRE \en_cnt_div4.wrlvl_odt_reg 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\en_cnt_div4.wrlvl_odt_i_1_n_0 ),
        .Q(wrlvl_odt),
        .R(1'b0));
  LUT4 #(
    .INIT(16'hFFF4)) 
    first_rdlvl_pat_r_i_1
       (.I0(\stg1_wr_rd_cnt[8]_i_5_n_0 ),
        .I1(first_rdlvl_pat_r),
        .I2(rdlvl_stg1_rank_done),
        .I3(write_calib_reg_0),
        .O(first_rdlvl_pat_r_i_1_n_0));
  FDRE first_rdlvl_pat_r_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(first_rdlvl_pat_r_i_1_n_0),
        .Q(first_rdlvl_pat_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFEFAAAB)) 
    first_wrcal_pat_r_i_1
       (.I0(write_calib_reg_0),
        .I1(calib_wrdata_en_i_2_n_0),
        .I2(Q),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(first_wrcal_pat_r),
        .I5(wrcal_resume_w),
        .O(first_wrcal_pat_r_i_1_n_0));
  FDRE first_wrcal_pat_r_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(first_wrcal_pat_r_i_1_n_0),
        .Q(first_wrcal_pat_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFEAAAAAAAAA)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_1 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_2_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_3_n_0 ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_4_n_0 ),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_5_n_0 ),
        .O(address_w[0]));
  (* SOFT_HLUTNM = "soft_lutpair476" *) 
  LUT4 #(
    .INIT(16'h0200)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_2 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_5_n_0 ),
        .I1(init_state_r),
        .I2(reg_ctrl_cnt_r_reg[3]),
        .I3(reg_ctrl_cnt_r_reg[0]),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h080808AA)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_3 
       (.I0(\complex_address_reg_n_0_[0] ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_6_n_0 ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10_n_0 ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair467" *) 
  LUT4 #(
    .INIT(16'h00E2)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[0]_i_4 
       (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] ),
        .I1(complex_oclkdelay_calib_done_r1_reg_0),
        .I2(complex_row_cnt_ocal_reg[0]),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_8_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[0]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h44444000FFFFFFFF)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_1 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_3_n_0 ),
        .I2(cnt_init_mr_r[0]),
        .I3(cnt_init_mr_r[1]),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0 ),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_5_n_0 ),
        .O(address_w[10]));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF7FEF)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2 
       (.I0(\init_state_r_reg_n_0_[4] ),
        .I1(Q),
        .I2(\init_state_r_reg_n_0_[1] ),
        .I3(\init_state_r_reg_n_0_[3] ),
        .I4(\init_state_r_reg_n_0_[2] ),
        .I5(\init_state_r_reg_n_0_[5] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair489" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_3 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_6_n_0 ),
        .I1(init_state_r),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFEFFFFFFF6FE)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_5 
       (.I0(Q),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(\wrcal_reads[7]_i_4_n_0 ),
        .I3(\init_state_r_reg_n_0_[4] ),
        .I4(init_state_r),
        .I5(\init_state_r_reg_n_0_[5] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h0000000040070000)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[10]_i_6 
       (.I0(\init_state_r_reg_n_0_[3] ),
        .I1(\init_state_r_reg_n_0_[2] ),
        .I2(\init_state_r_reg_n_0_[5] ),
        .I3(Q),
        .I4(\init_state_r_reg_n_0_[1] ),
        .I5(\init_state_r_reg_n_0_[4] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h0000001000400000)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[12]_i_1 
       (.I0(\init_state_r_reg_n_0_[3] ),
        .I1(\init_state_r_reg_n_0_[2] ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ),
        .I3(init_state_r),
        .I4(\init_state_r_reg_n_0_[5] ),
        .I5(\init_state_r_reg_n_0_[4] ),
        .O(address_w[12]));
  (* SOFT_HLUTNM = "soft_lutpair456" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2 
       (.I0(Q),
        .I1(\init_state_r_reg_n_0_[1] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hEAFFFFFFAAAAAAAA)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_1 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_2_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_3_n_0 ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_4_n_0 ),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_2_n_0 ),
        .O(address_w[1]));
  (* SOFT_HLUTNM = "soft_lutpair416" *) 
  LUT5 #(
    .INIT(32'h00405555)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_2 
       (.I0(init_state_r),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_5_n_0 ),
        .I2(reg_ctrl_cnt_r_reg[1]),
        .I3(reg_ctrl_cnt_r_reg[3]),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_9_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hDDD0FFFF)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_3 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_6_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10_n_0 ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9_n_0 ),
        .I4(\complex_address_reg_n_0_[1] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair465" *) 
  LUT4 #(
    .INIT(16'hABFB)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_4 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_8_n_0 ),
        .I1(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1] ),
        .I2(complex_oclkdelay_calib_done_r1_reg_0),
        .I3(complex_row_cnt_ocal_reg[1]),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h1000000000000000)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[1]_i_5 
       (.I0(\init_state_r_reg_n_0_[5] ),
        .I1(\init_state_r_reg_n_0_[2] ),
        .I2(\init_state_r_reg_n_0_[3] ),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(Q),
        .I5(\init_state_r_reg_n_0_[4] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[1]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF8FFF0000)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_1 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_2_n_0 ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_3_n_0 ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_5_n_0 ),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_4_n_0 ),
        .O(address_w[2]));
  LUT5 #(
    .INIT(32'hDDD0FFFF)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_2 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_6_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10_n_0 ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9_n_0 ),
        .I4(\complex_address_reg_n_0_[2] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair474" *) 
  LUT4 #(
    .INIT(16'hABFB)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_3 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_8_n_0 ),
        .I1(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2] ),
        .I2(complex_oclkdelay_calib_done_r1_reg_0),
        .I3(complex_row_cnt_ocal_reg[2]),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hBABBBABABABABABA)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_4 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_6_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_5_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_3_n_0 ),
        .I3(reg_ctrl_cnt_r_reg[1]),
        .I4(reg_ctrl_cnt_r_reg[2]),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_6_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFDFFFFFFBFFFFFFF)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_5 
       (.I0(\init_state_r_reg_n_0_[3] ),
        .I1(\init_state_r_reg_n_0_[2] ),
        .I2(\init_state_r_reg_n_0_[5] ),
        .I3(Q),
        .I4(\init_state_r_reg_n_0_[1] ),
        .I5(\init_state_r_reg_n_0_[4] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair416" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[2]_i_6 
       (.I0(init_state_r),
        .I1(reg_ctrl_cnt_r_reg[3]),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[2]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h8A888A888A88AAAA)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_1 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_5_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_2_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3_n_0 ),
        .I4(\complex_address_reg_n_0_[3] ),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4_n_0 ),
        .O(address_w[3]));
  LUT6 #(
    .INIT(64'h00000000EEE222E2)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_2 
       (.I0(p_17_in),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_8_n_0 ),
        .I2(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3] ),
        .I3(complex_oclkdelay_calib_done_r1_reg_0),
        .I4(complex_row_cnt_ocal_reg[3]),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_3_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFEAA)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[3]_i_3 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0 ),
        .I1(\stg1_wr_rd_cnt[8]_i_5_n_0 ),
        .I2(\stg1_wr_rd_cnt[8]_i_4_n_0 ),
        .I3(complex_oclkdelay_calib_done_r1_reg_0),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_10_n_0 ),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_11_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[3]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h20AA2020AAAAAAAA)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_1 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_5_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_2_n_0 ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_3_n_0 ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3_n_0 ),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_4_n_0 ),
        .O(address_w[4]));
  LUT2 #(
    .INIT(4'h6)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_2 
       (.I0(\complex_address_reg_n_0_[4] ),
        .I1(\complex_address_reg_n_0_[3] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair462" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_3 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair465" *) 
  LUT3 #(
    .INIT(8'hEF)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[4]_i_4 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_8_n_0 ),
        .I1(complex_oclkdelay_calib_done_r1_reg_0),
        .I2(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[4]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFEAAAAAAAAA)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_1 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_2_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_3_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3_n_0 ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_4_n_0 ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_5_n_0 ),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_5_n_0 ),
        .O(address_w[5]));
  LUT6 #(
    .INIT(64'h000000000000EA00)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_2 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0 ),
        .I1(cnt_init_mr_r[1]),
        .I2(cnt_init_mr_r[0]),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_6_n_0 ),
        .I4(init_state_r),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_2_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair468" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_3 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0000222F222F0000)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_4 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_6_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10_n_0 ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9_n_0 ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_6_n_0 ),
        .I5(\complex_address_reg_n_0_[5] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair467" *) 
  LUT3 #(
    .INIT(8'h02)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_5 
       (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5] ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_8_n_0 ),
        .I2(complex_oclkdelay_calib_done_r1_reg_0),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair484" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[5]_i_6 
       (.I0(\complex_address_reg_n_0_[4] ),
        .I1(\complex_address_reg_n_0_[3] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[5]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFF5D0000)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_1 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_2_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_3_n_0 ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_4_n_0 ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_5_n_0 ),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_6_n_0 ),
        .O(address_w[6]));
  (* SOFT_HLUTNM = "soft_lutpair413" *) 
  LUT3 #(
    .INIT(8'hA8)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_10 
       (.I0(complex_oclkdelay_calib_done_r1_reg_0),
        .I1(\stg1_wr_rd_cnt[8]_i_4_n_0 ),
        .I2(\stg1_wr_rd_cnt[8]_i_5_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFDDD0DDD0FFFF)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_2 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_6_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10_n_0 ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9_n_0 ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_7_n_0 ),
        .I5(\complex_address_reg_n_0_[6] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair468" *) 
  LUT4 #(
    .INIT(16'h9555)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_3 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair474" *) 
  LUT3 #(
    .INIT(8'h02)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_4 
       (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6] ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_8_n_0 ),
        .I2(complex_oclkdelay_calib_done_r1_reg_0),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair489" *) 
  LUT3 #(
    .INIT(8'h8A)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_5 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_2_n_0 ),
        .I1(init_state_r),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_6_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair485" *) 
  LUT3 #(
    .INIT(8'h04)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_6 
       (.I0(init_state_r),
        .I1(\gen_rnk[0].mr1_r_reg_n_0_[0][1] ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_9_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair484" *) 
  LUT3 #(
    .INIT(8'h80)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_7 
       (.I0(\complex_address_reg_n_0_[3] ),
        .I1(\complex_address_reg_n_0_[4] ),
        .I2(\complex_address_reg_n_0_[5] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFF4FFFFFFFF)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_8 
       (.I0(calib_wrdata_en_i_2_n_0),
        .I1(Q),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_10_n_0 ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_10_n_0 ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0 ),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_8_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hDDDDD9DD77777777)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[6]_i_9 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_6_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0 ),
        .I3(cnt_init_mr_r[1]),
        .I4(cnt_init_mr_r[0]),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_6_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[6]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'h20AA2020AAAAAAAA)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_1 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_2_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_3_n_0 ),
        .I2(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[7] ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_4_n_0 ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3_n_0 ),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_5_n_0 ),
        .O(address_w[7]));
  LUT6 #(
    .INIT(64'hCCCCCCCCCCCFDDDD)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_10 
       (.I0(prbs_rdlvl_start_i_3_n_0),
        .I1(p_0_in0_in),
        .I2(\cnt_init_mr_r[0]_i_2_n_0 ),
        .I3(\init_state_r[6]_i_2_n_0 ),
        .I4(Q),
        .I5(\init_state_r_reg_n_0_[1] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000020)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_11 
       (.I0(Q),
        .I1(\init_state_r_reg_n_0_[4] ),
        .I2(\init_state_r_reg_n_0_[5] ),
        .I3(init_state_r),
        .I4(\init_state_r_reg_n_0_[3] ),
        .I5(\init_state_r_reg_n_0_[2] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_11_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair414" *) 
  LUT5 #(
    .INIT(32'h95555555)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_12 
       (.I0(\complex_address_reg_n_0_[7] ),
        .I1(\complex_address_reg_n_0_[6] ),
        .I2(\complex_address_reg_n_0_[3] ),
        .I3(\complex_address_reg_n_0_[4] ),
        .I4(\complex_address_reg_n_0_[5] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'h0000002000000000)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_13 
       (.I0(detect_pi_found_dqs_i_2_n_0),
        .I1(\init_state_r_reg_n_0_[4] ),
        .I2(\init_state_r_reg_n_0_[5] ),
        .I3(init_state_r),
        .I4(\init_state_r_reg_n_0_[3] ),
        .I5(\init_state_r_reg_n_0_[2] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_13_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair452" *) 
  LUT4 #(
    .INIT(16'hAA08)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_2 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_5_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_6_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7_n_0 ),
        .I3(init_state_r),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFFFD)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_3 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_8_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0 ),
        .I2(complex_oclkdelay_calib_done_r1_reg_0),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_10_n_0 ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_11_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair432" *) 
  LUT5 #(
    .INIT(32'h95555555)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_4 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FEAAFEFE)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_5 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_12_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10_n_0 ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_6_n_0 ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7_n_0 ),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_3_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hF9FDFFFFDFFFFEFF)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_6 
       (.I0(\init_state_r_reg_n_0_[5] ),
        .I1(\init_state_r_reg_n_0_[4] ),
        .I2(\init_state_r_reg_n_0_[2] ),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(Q),
        .I5(\init_state_r_reg_n_0_[3] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h1000000000001110)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7 
       (.I0(\init_state_r_reg_n_0_[5] ),
        .I1(\init_state_r_reg_n_0_[2] ),
        .I2(\init_state_r_reg_n_0_[3] ),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(Q),
        .I5(\init_state_r_reg_n_0_[4] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFBFFFDFF)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_8 
       (.I0(\init_state_r_reg_n_0_[4] ),
        .I1(\init_state_r_reg_n_0_[5] ),
        .I2(init_state_r),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ),
        .I4(\init_state_r_reg_n_0_[2] ),
        .I5(\init_state_r_reg_n_0_[3] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair413" *) 
  LUT5 #(
    .INIT(32'h55555545)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9 
       (.I0(complex_oclkdelay_calib_done_r1_reg_0),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_13_n_0 ),
        .I2(rdlvl_stg1_start_i_2_n_0),
        .I3(\stg1_wr_rd_cnt[8]_i_5_n_0 ),
        .I4(\stg1_wr_rd_cnt[8]_i_4_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hFF60FF60FF60FFFF)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_1 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_2_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3_n_0 ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_2_n_0 ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4_n_0 ),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_3_n_0 ),
        .O(address_w[8]));
  LUT6 #(
    .INIT(64'h0080808080808080)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_2 
       (.I0(\cnt_init_mr_r[1]_i_2_n_0 ),
        .I1(cnt_init_mr_r[0]),
        .I2(cnt_init_mr_r[1]),
        .I3(pi_dqs_found_done_r1_reg_0),
        .I4(prbs_rdlvl_start_reg_2),
        .I5(complex_oclkdelay_calib_done_r1_reg_0),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h9555555555555555)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[8]_i_3 
       (.I0(\complex_address_reg_n_0_[8] ),
        .I1(\complex_address_reg_n_0_[7] ),
        .I2(\complex_address_reg_n_0_[5] ),
        .I3(\complex_address_reg_n_0_[4] ),
        .I4(\complex_address_reg_n_0_[3] ),
        .I5(\complex_address_reg_n_0_[6] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[8]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h6A00FFFF6A006A00)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_1 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9] ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_2_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3_n_0 ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4_n_0 ),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_5_n_0 ),
        .O(address_w[9]));
  (* SOFT_HLUTNM = "soft_lutpair473" *) 
  LUT3 #(
    .INIT(8'h4F)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0 ),
        .I1(init_state_r1[3]),
        .I2(\stg1_wr_rd_cnt[8]_i_5_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFF7)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11 
       (.I0(init_state_r1[2]),
        .I1(init_state_r1[1]),
        .I2(init_state_r1[5]),
        .I3(init_state_r1[0]),
        .I4(init_state_r1[4]),
        .I5(init_state_r1[6]),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair414" *) 
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_12 
       (.I0(\complex_address_reg_n_0_[6] ),
        .I1(\complex_address_reg_n_0_[3] ),
        .I2(\complex_address_reg_n_0_[4] ),
        .I3(\complex_address_reg_n_0_[5] ),
        .I4(\complex_address_reg_n_0_[7] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_12_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair473" *) 
  LUT4 #(
    .INIT(16'h5504)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_13 
       (.I0(complex_row0_rd_done),
        .I1(init_state_r1[3]),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0 ),
        .I3(\one_rank.stg1_wr_done_reg_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'h0000008000000000)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14 
       (.I0(\stg1_wr_rd_cnt_reg_n_0_[1] ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[0] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[5] ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_17_n_0 ),
        .I4(\complex_num_writes[4]_i_15_n_0 ),
        .I5(\stg1_wr_rd_cnt_reg_n_0_[6] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000100)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_15 
       (.I0(complex_sample_cnt_inc_i_3_n_0),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[5] ),
        .I2(prbs_rdlvl_start_reg_2),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[2] ),
        .I4(\stg1_wr_rd_cnt_reg_n_0_[1] ),
        .I5(\stg1_wr_rd_cnt_reg_n_0_[0] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_15_n_0 ));
  LUT6 #(
    .INIT(64'h4444444444444044)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_16 
       (.I0(calib_wrdata_en_i_2_n_0),
        .I1(Q),
        .I2(wrcal_wr_cnt_reg[3]),
        .I3(wrcal_wr_cnt_reg[2]),
        .I4(wrcal_wr_cnt_reg[0]),
        .I5(wrcal_wr_cnt_reg[1]),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_16_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair481" *) 
  LUT3 #(
    .INIT(8'h7F)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_17 
       (.I0(\stg1_wr_rd_cnt_reg_n_0_[4] ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[2] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[3] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_17_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair432" *) 
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_2 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hF1FFF1F1)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_6_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9_n_0 ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_10_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hBAFF0000BAFFBAFF)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0 ),
        .I2(init_state_r1[3]),
        .I3(\stg1_wr_rd_cnt[8]_i_5_n_0 ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_6_n_0 ),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_4_n_0 ));
  LUT3 #(
    .INIT(8'h6A)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_5 
       (.I0(\complex_address_reg_n_0_[9] ),
        .I1(\complex_address_reg_n_0_[8] ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_12_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_5_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFF5D)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_6 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_9_n_0 ),
        .I1(\row_cnt_victim_rotate.complex_row_cnt[4]_i_9_n_0 ),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_13_n_0 ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14_n_0 ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_15_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_6_n_0 ));
  LUT4 #(
    .INIT(16'hA8AA)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7 
       (.I0(\stg1_wr_rd_cnt[8]_i_4_n_0 ),
        .I1(init_state_r1[1]),
        .I2(init_state_r1[2]),
        .I3(prbs_gen_oclk_clk_en_i_11_n_0),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFEF0000)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8 
       (.I0(oclk_wr_cnt_reg[1]),
        .I1(oclk_wr_cnt_reg[0]),
        .I2(oclk_wr_cnt_reg[2]),
        .I3(oclk_wr_cnt_reg[3]),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[7]_i_10_n_0 ),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_16_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hFF57FFFFFF57FF57)) 
    \gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9 
       (.I0(complex_oclkdelay_calib_done_r1_reg_0),
        .I1(\stg1_wr_rd_cnt[8]_i_4_n_0 ),
        .I2(\stg1_wr_rd_cnt[8]_i_5_n_0 ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_14_n_0 ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_13_n_0 ),
        .I5(\complex_row_cnt_ocal[3]_i_5_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_9_n_0 ));
  FDRE \gen_no_mirror.div_clk_loop[0].phy_address_reg[0] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(address_w[0]),
        .Q(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \gen_no_mirror.div_clk_loop[0].phy_address_reg[10] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(address_w[10]),
        .Q(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10] ),
        .R(1'b0));
  FDRE \gen_no_mirror.div_clk_loop[0].phy_address_reg[12] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(address_w[12]),
        .Q(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12] ),
        .R(1'b0));
  FDRE \gen_no_mirror.div_clk_loop[0].phy_address_reg[1] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(address_w[1]),
        .Q(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \gen_no_mirror.div_clk_loop[0].phy_address_reg[2] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(address_w[2]),
        .Q(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \gen_no_mirror.div_clk_loop[0].phy_address_reg[3] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(address_w[3]),
        .Q(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \gen_no_mirror.div_clk_loop[0].phy_address_reg[4] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(address_w[4]),
        .Q(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \gen_no_mirror.div_clk_loop[0].phy_address_reg[5] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(address_w[5]),
        .Q(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \gen_no_mirror.div_clk_loop[0].phy_address_reg[6] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(address_w[6]),
        .Q(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \gen_no_mirror.div_clk_loop[0].phy_address_reg[7] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(address_w[7]),
        .Q(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ),
        .R(1'b0));
  FDRE \gen_no_mirror.div_clk_loop[0].phy_address_reg[8] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(address_w[8]),
        .Q(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ),
        .R(1'b0));
  FDRE \gen_no_mirror.div_clk_loop[0].phy_address_reg[9] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(address_w[9]),
        .Q(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9] ),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h000000000000AA08)) 
    \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_1 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_2_n_0 ),
        .I1(\init_state_r_reg_n_0_[3] ),
        .I2(\init_state_r_reg_n_0_[2] ),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(\init_state_r_reg_n_0_[4] ),
        .I5(init_state_r),
        .O(bank_w[0]));
  LUT6 #(
    .INIT(64'h4007800740078003)) 
    \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_2 
       (.I0(\init_state_r_reg_n_0_[3] ),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(\init_state_r_reg_n_0_[5] ),
        .I3(Q),
        .I4(\init_state_r_reg_n_0_[2] ),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_3_n_0 ),
        .O(\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h06666666)) 
    \gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_3 
       (.I0(cnt_init_mr_r[1]),
        .I1(cnt_init_mr_r[0]),
        .I2(complex_oclkdelay_calib_done_r1_reg_0),
        .I3(prbs_rdlvl_start_reg_2),
        .I4(pi_dqs_found_done_r1_reg_0),
        .O(\gen_no_mirror.div_clk_loop[0].phy_bank[0]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair466" *) 
  LUT4 #(
    .INIT(16'h0020)) 
    \gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_1 
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_2_n_0 ),
        .I1(\init_state_r_reg_n_0_[4] ),
        .I2(\init_state_r_reg_n_0_[1] ),
        .I3(init_state_r),
        .O(bank_w[1]));
  LUT6 #(
    .INIT(64'h0980098009800981)) 
    \gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_2 
       (.I0(Q),
        .I1(\init_state_r_reg_n_0_[5] ),
        .I2(\init_state_r_reg_n_0_[2] ),
        .I3(\init_state_r_reg_n_0_[3] ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0 ),
        .I5(cnt_init_mr_r[1]),
        .O(\gen_no_mirror.div_clk_loop[0].phy_bank[1]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h0800)) 
    \gen_no_mirror.div_clk_loop[0].phy_bank[2]_i_1 
       (.I0(reg_ctrl_cnt_r),
        .I1(reg_ctrl_cnt_r_reg[2]),
        .I2(reg_ctrl_cnt_r_reg[3]),
        .I3(reg_ctrl_cnt_r_reg[1]),
        .O(bank_w[2]));
  FDRE \gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(bank_w[0]),
        .Q(phy_bank[9]),
        .R(1'b0));
  FDRE \gen_no_mirror.div_clk_loop[0].phy_bank_reg[1] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(bank_w[1]),
        .Q(phy_bank[10]),
        .R(1'b0));
  FDRE \gen_no_mirror.div_clk_loop[0].phy_bank_reg[2] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(bank_w[2]),
        .Q(phy_bank[11]),
        .R(1'b0));
  LUT2 #(
    .INIT(4'hE)) 
    \gen_reset_obuf.u_reset_obuf_i_1 
       (.I0(phy_ctl_wr_i1_reg),
        .I1(phy_reset_n),
        .O(mux_reset_n));
  FDRE \gen_rnk[0].mr1_r_reg[0][1] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(1'b1),
        .Q(\gen_rnk[0].mr1_r_reg_n_0_[0][1] ),
        .R(\en_cnt_div4.enable_wrlvl_cnt_reg[2]_0 ));
  FDRE init_calib_complete_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(init_complete_r2),
        .Q(calib_complete),
        .R(\en_cnt_div4.enable_wrlvl_cnt_reg[2]_0 ));
  FDRE init_complete_r1_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(init_complete_r_reg_n_0),
        .Q(init_complete_r1),
        .R(\en_cnt_div4.enable_wrlvl_cnt_reg[2]_0 ));
  (* KEEP = "yes" *) 
  FDRE init_complete_r1_timing_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(init_complete_r_timing),
        .Q(init_complete_r1_timing),
        .R(\en_cnt_div4.enable_wrlvl_cnt_reg[2]_0 ));
  FDRE init_complete_r2_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(init_complete_r1),
        .Q(init_complete_r2),
        .R(\victim_sel_reg[0]_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF00000020)) 
    init_complete_r_i_1
       (.I0(detect_pi_found_dqs_i_2_n_0),
        .I1(\wrcal_reads[7]_i_4_n_0 ),
        .I2(\init_state_r_reg_n_0_[4] ),
        .I3(init_state_r),
        .I4(\init_state_r_reg_n_0_[5] ),
        .I5(init_complete_r_reg_n_0),
        .O(init_complete_r_i_1_n_0));
  FDRE init_complete_r_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(init_complete_r_i_1_n_0),
        .Q(init_complete_r_reg_n_0),
        .R(\victim_sel_reg[0]_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF00000020)) 
    init_complete_r_timing_i_1
       (.I0(detect_pi_found_dqs_i_2_n_0),
        .I1(\wrcal_reads[7]_i_4_n_0 ),
        .I2(\init_state_r_reg_n_0_[4] ),
        .I3(init_state_r),
        .I4(\init_state_r_reg_n_0_[5] ),
        .I5(init_complete_r_timing),
        .O(init_complete_r_timing_i_1_n_0));
  (* KEEP = "yes" *) 
  FDRE init_complete_r_timing_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(init_complete_r_timing_i_1_n_0),
        .Q(init_complete_r_timing),
        .R(\victim_sel_reg[0]_0 ));
  FDRE \init_state_r1_reg[0] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(Q),
        .Q(init_state_r1[0]),
        .R(\victim_sel_reg[0]_0 ));
  FDRE \init_state_r1_reg[1] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\init_state_r_reg_n_0_[1] ),
        .Q(init_state_r1[1]),
        .R(\victim_sel_reg[0]_0 ));
  FDRE \init_state_r1_reg[2] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\init_state_r_reg_n_0_[2] ),
        .Q(init_state_r1[2]),
        .R(\victim_sel_reg[0]_0 ));
  FDRE \init_state_r1_reg[3] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\init_state_r_reg_n_0_[3] ),
        .Q(init_state_r1[3]),
        .R(\victim_sel_reg[0]_0 ));
  FDRE \init_state_r1_reg[4] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\init_state_r_reg_n_0_[4] ),
        .Q(init_state_r1[4]),
        .R(\victim_sel_reg[0]_0 ));
  FDRE \init_state_r1_reg[5] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\init_state_r_reg_n_0_[5] ),
        .Q(init_state_r1[5]),
        .R(\victim_sel_reg[0]_0 ));
  FDRE \init_state_r1_reg[6] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(init_state_r),
        .Q(init_state_r1[6]),
        .R(\victim_sel_reg[0]_0 ));
  LUT6 #(
    .INIT(64'hAAFEAAFEFFFFAAFE)) 
    \init_state_r[0]_i_1 
       (.I0(\init_state_r[0]_i_2_n_0 ),
        .I1(\init_state_r[0]_i_3_n_0 ),
        .I2(\init_state_r[0]_i_4_n_0 ),
        .I3(\init_state_r[0]_i_5_n_0 ),
        .I4(\init_state_r[0]_i_6_n_0 ),
        .I5(\init_state_r[0]_i_7_n_0 ),
        .O(\init_state_r[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0FFF0FF0BB00BB00)) 
    \init_state_r[0]_i_10 
       (.I0(num_reads[1]),
        .I1(num_reads[0]),
        .I2(cnt_cmd_done_r),
        .I3(Q),
        .I4(\init_state_r[0]_i_4_1 ),
        .I5(\init_state_r_reg_n_0_[1] ),
        .O(\init_state_r[0]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000001101)) 
    \init_state_r[0]_i_11 
       (.I0(Q),
        .I1(rdlvl_stg1_rank_done),
        .I2(prbs_rdlvl_start_reg_2),
        .I3(rdlvl_stg1_done_r1),
        .I4(prbs_rdlvl_done_pulse0),
        .I5(prech_req_posedge_r_reg_0),
        .O(\init_state_r[0]_i_11_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF55151515)) 
    \init_state_r[0]_i_12 
       (.I0(\init_state_r[4]_i_4_n_0 ),
        .I1(Q),
        .I2(cnt_cmd_done_r),
        .I3(wrlvl_done_r1),
        .I4(\init_state_r_reg_n_0_[1] ),
        .I5(\init_state_r[0]_i_25_n_0 ),
        .O(\init_state_r[0]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'h0455155504440444)) 
    \init_state_r[0]_i_13 
       (.I0(\cnt_init_mr_r[0]_i_2_n_0 ),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(cnt_cmd_done_r),
        .I3(Q),
        .I4(cnt_txpr_done_r),
        .I5(\init_state_r[0]_i_26_n_0 ),
        .O(\init_state_r[0]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'h8A8AA000AA8AA000)) 
    \init_state_r[0]_i_14 
       (.I0(\init_state_r[0]_i_27_n_0 ),
        .I1(reset_rd_addr_r1),
        .I2(Q),
        .I3(cnt_cmd_done_r),
        .I4(\init_state_r_reg_n_0_[1] ),
        .I5(rdlvl_stg1_done_r1),
        .O(\init_state_r[0]_i_14_n_0 ));
  LUT6 #(
    .INIT(64'hFF7FFF7FFF7F7F7F)) 
    \init_state_r[0]_i_15 
       (.I0(\init_state_r_reg_n_0_[3] ),
        .I1(\init_state_r_reg_n_0_[2] ),
        .I2(detect_pi_found_dqs_i_2_n_0),
        .I3(\init_state_r[2]_i_8_n_0 ),
        .I4(rdlvl_stg1_done_r1),
        .I5(complex_sample_cnt_inc_i_2_n_0),
        .O(\init_state_r[0]_i_15_n_0 ));
  LUT6 #(
    .INIT(64'hFF450055FF45FF55)) 
    \init_state_r[0]_i_16 
       (.I0(\init_state_r[6]_i_11_n_0 ),
        .I1(\init_state_r[5]_i_13_n_0 ),
        .I2(complex_sample_cnt_inc_i_2_n_0),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(Q),
        .I5(prbs_rdlvl_done_pulse0),
        .O(\init_state_r[0]_i_16_n_0 ));
  LUT6 #(
    .INIT(64'h0000F355FF55FF55)) 
    \init_state_r[0]_i_17 
       (.I0(Q),
        .I1(complex_row1_wr_done),
        .I2(\one_rank.stg1_wr_done_reg_0 ),
        .I3(\init_state_r[5]_i_13_n_0 ),
        .I4(\init_state_r[3]_i_21_n_0 ),
        .I5(\init_state_r[0]_i_28_n_0 ),
        .O(\init_state_r[0]_i_17_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF04FF04FF04FF)) 
    \init_state_r[0]_i_18 
       (.I0(\cnt_init_mr_r[0]_i_2_n_0 ),
        .I1(\init_state_r[0]_i_29_n_0 ),
        .I2(\init_state_r[2]_i_29_n_0 ),
        .I3(\init_state_r_reg_n_0_[4] ),
        .I4(\init_state_r[0]_i_30_n_0 ),
        .I5(complex_oclkdelay_calib_done_r1_reg_0),
        .O(\init_state_r[0]_i_18_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF00F7)) 
    \init_state_r[0]_i_19 
       (.I0(complex_sample_cnt_inc_i_2_n_0),
        .I1(Q),
        .I2(\init_state_r[5]_i_13_n_0 ),
        .I3(\init_state_r[6]_i_15_n_0 ),
        .I4(rdlvl_stg1_start_int_i_2_n_0),
        .I5(\init_state_r_reg_n_0_[1] ),
        .O(\init_state_r[0]_i_19_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair429" *) 
  LUT5 #(
    .INIT(32'hF0F000D0)) 
    \init_state_r[0]_i_2 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(\ocal_act_wait_cnt[3]_i_3_n_0 ),
        .I2(init_state_r),
        .I3(\init_state_r_reg_n_0_[2] ),
        .I4(Q),
        .O(\init_state_r[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFBB30FFFF0000)) 
    \init_state_r[0]_i_20 
       (.I0(\init_state_r[5]_i_35_n_0 ),
        .I1(Q),
        .I2(cnt_cmd_done_r),
        .I3(\init_state_r_reg_n_0_[2] ),
        .I4(\init_state_r_reg_n_0_[4] ),
        .I5(\init_state_r_reg_n_0_[3] ),
        .O(\init_state_r[0]_i_20_n_0 ));
  LUT6 #(
    .INIT(64'h00000000747400FF)) 
    \init_state_r[0]_i_21 
       (.I0(p_17_in),
        .I1(Q),
        .I2(cnt_cmd_done_r),
        .I3(\init_state_r[0]_i_31_n_0 ),
        .I4(\init_state_r_reg_n_0_[1] ),
        .I5(\cnt_init_mr_r[0]_i_2_n_0 ),
        .O(\init_state_r[0]_i_21_n_0 ));
  LUT6 #(
    .INIT(64'h0F00020F0F0F020F)) 
    \init_state_r[0]_i_22 
       (.I0(\wrcal_reads_reg_n_0_[0] ),
        .I1(\wrcal_reads[7]_i_6_n_0 ),
        .I2(\init_state_r[2]_i_45_n_0 ),
        .I3(Q),
        .I4(\init_state_r_reg_n_0_[1] ),
        .I5(init_next_state1100_out),
        .O(\init_state_r[0]_i_22_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair417" *) 
  LUT4 #(
    .INIT(16'hFFEF)) 
    \init_state_r[0]_i_23 
       (.I0(reg_ctrl_cnt_r_reg[0]),
        .I1(reg_ctrl_cnt_r_reg[1]),
        .I2(reg_ctrl_cnt_r_reg[3]),
        .I3(reg_ctrl_cnt_r_reg[2]),
        .O(\init_state_r[0]_i_23_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAABBFFAFFF)) 
    \init_state_r[0]_i_25 
       (.I0(\init_state_r_reg_n_0_[4] ),
        .I1(wrlvl_rank_done_r7),
        .I2(cnt_dllk_zqinit_done_r),
        .I3(Q),
        .I4(\init_state_r_reg_n_0_[1] ),
        .I5(\wrcal_reads[7]_i_4_n_0 ),
        .O(\init_state_r[0]_i_25_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair399" *) 
  LUT4 #(
    .INIT(16'hEAAA)) 
    \init_state_r[0]_i_26 
       (.I0(Q),
        .I1(\calib_seq_reg[0]_0 ),
        .I2(cnt_pwron_cke_done_r),
        .I3(ck_addr_cmd_delay_done),
        .O(\init_state_r[0]_i_26_n_0 ));
  LUT6 #(
    .INIT(64'hBBFBFFFFBBFBBBFB)) 
    \init_state_r[0]_i_27 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(pi_calib_done),
        .I2(pi_dqs_found_done_r1_reg_0),
        .I3(ddr3_lm_done_r_reg_0),
        .I4(\init_state_r[0]_i_32_n_0 ),
        .I5(\init_state_r[0]_i_14_0 ),
        .O(\init_state_r[0]_i_27_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFC8F8FFFF)) 
    \init_state_r[0]_i_28 
       (.I0(prbs_last_byte_done_r),
        .I1(\init_state_r[5]_i_13_n_0 ),
        .I2(complex_oclkdelay_calib_done_r1_reg_0),
        .I3(prbs_rdlvl_done_r1),
        .I4(Q),
        .I5(\init_state_r_reg_n_0_[1] ),
        .O(\init_state_r[0]_i_28_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair521" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \init_state_r[0]_i_29 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(cnt_cmd_done_r),
        .O(\init_state_r[0]_i_29_n_0 ));
  LUT6 #(
    .INIT(64'h0100000011101010)) 
    \init_state_r[0]_i_3 
       (.I0(\init_state_r[4]_i_4_n_0 ),
        .I1(Q),
        .I2(\init_state_r_reg_n_0_[1] ),
        .I3(ddr2_pre_flag_r_reg_n_0),
        .I4(cnt_cmd_done_r),
        .I5(\init_state_r[4]_i_10_n_0 ),
        .O(\init_state_r[0]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair442" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \init_state_r[0]_i_30 
       (.I0(Q),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(\init_state_r_reg_n_0_[2] ),
        .I3(\init_state_r_reg_n_0_[3] ),
        .O(\init_state_r[0]_i_30_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAABABB)) 
    \init_state_r[0]_i_31 
       (.I0(\init_state_r[5]_i_30_n_0 ),
        .I1(Q),
        .I2(wrcal_prech_req),
        .I3(cnt_cmd_done_r),
        .I4(ddr3_lm_done_r_reg_0),
        .I5(prech_req_posedge_r_reg_0),
        .O(\init_state_r[0]_i_31_n_0 ));
  LUT6 #(
    .INIT(64'hFFEEFFEEFFEEAA08)) 
    \init_state_r[0]_i_32 
       (.I0(\one_rank.stg1_wr_done_reg_0 ),
        .I1(complex_oclkdelay_calib_done_r1_reg_0),
        .I2(rdlvl_stg1_start_int),
        .I3(prbs_last_byte_done),
        .I4(prbs_rdlvl_start_reg_2),
        .I5(rdlvl_last_byte_done),
        .O(\init_state_r[0]_i_32_n_0 ));
  LUT6 #(
    .INIT(64'hEFEEEFEFEFEEEFEE)) 
    \init_state_r[0]_i_4 
       (.I0(\init_state_r[0]_i_8_n_0 ),
        .I1(\init_state_r[0]_i_9_n_0 ),
        .I2(\cnt_init_mr_r[0]_i_2_n_0 ),
        .I3(\init_state_r[0]_i_10_n_0 ),
        .I4(\init_state_r[0]_i_11_n_0 ),
        .I5(\wrcal_reads[7]_i_5_n_0 ),
        .O(\init_state_r[0]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hABABABAAAAAAAAAA)) 
    \init_state_r[0]_i_5 
       (.I0(\init_state_r[3]_i_6_n_0 ),
        .I1(\init_state_r[0]_i_12_n_0 ),
        .I2(\init_state_r[0]_i_13_n_0 ),
        .I3(\init_state_r[0]_i_14_n_0 ),
        .I4(rdlvl_stg1_start_int_i_2_n_0),
        .I5(\init_state_r[0]_i_15_n_0 ),
        .O(\init_state_r[0]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0350FFFFFFFF)) 
    \init_state_r[0]_i_6 
       (.I0(\init_state_r[0]_i_16_n_0 ),
        .I1(\init_state_r[0]_i_17_n_0 ),
        .I2(\init_state_r_reg_n_0_[3] ),
        .I3(\init_state_r_reg_n_0_[2] ),
        .I4(\init_state_r[0]_i_18_n_0 ),
        .I5(\init_state_r[0]_i_19_n_0 ),
        .O(\init_state_r[0]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hDDDFDDDFDDDFDDDD)) 
    \init_state_r[0]_i_7 
       (.I0(\init_state_r_reg_n_0_[5] ),
        .I1(init_state_r),
        .I2(\init_state_r[0]_i_20_n_0 ),
        .I3(\init_state_r[0]_i_21_n_0 ),
        .I4(\wrcal_reads[7]_i_4_n_0 ),
        .I5(\init_state_r[0]_i_22_n_0 ),
        .O(\init_state_r[0]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h0001111111111111)) 
    \init_state_r[0]_i_8 
       (.I0(\wrcal_reads[7]_i_4_n_0 ),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(\init_state_r[0]_i_4_0 ),
        .I3(\init_state_r[4]_i_24_n_0 ),
        .I4(Q),
        .I5(cnt_cmd_done_r),
        .O(\init_state_r[0]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'h555F555D555D555D)) 
    \init_state_r[0]_i_9 
       (.I0(\init_state_r_reg_n_0_[4] ),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(rdlvl_stg1_start_int_i_2_n_0),
        .I3(Q),
        .I4(cnt_cmd_done_r),
        .I5(\init_state_r[0]_i_23_n_0 ),
        .O(\init_state_r[0]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hAAFEAAFEAAFEFFFF)) 
    \init_state_r[1]_i_1 
       (.I0(\init_state_r[1]_i_2_n_0 ),
        .I1(\init_state_r[1]_i_3_n_0 ),
        .I2(\init_state_r[1]_i_4_n_0 ),
        .I3(\init_state_r[1]_i_5_n_0 ),
        .I4(\init_state_r[1]_i_6_n_0 ),
        .I5(\init_state_r[1]_i_7_n_0 ),
        .O(\init_state_r[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000EEFEFEFE)) 
    \init_state_r[1]_i_10 
       (.I0(\init_state_r[2]_i_42_n_0 ),
        .I1(\init_state_r[1]_i_22_n_0 ),
        .I2(\init_state_r_reg_n_0_[1] ),
        .I3(\init_state_r[2]_i_43_n_0 ),
        .I4(\init_state_r[5]_i_27_n_0 ),
        .I5(\init_state_r[1]_i_23_n_0 ),
        .O(\init_state_r[1]_i_10_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair401" *) 
  LUT5 #(
    .INIT(32'hAAAAAAAB)) 
    \init_state_r[1]_i_11 
       (.I0(\init_state_r_reg_n_0_[4] ),
        .I1(\init_state_r[5]_i_32_n_0 ),
        .I2(\init_state_r_reg_n_0_[1] ),
        .I3(\init_state_r_reg_n_0_[2] ),
        .I4(\init_state_r_reg_n_0_[3] ),
        .O(\init_state_r[1]_i_11_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAA8AAAAAAAAAA)) 
    \init_state_r[1]_i_12 
       (.I0(\init_state_r[1]_i_24_n_0 ),
        .I1(wrcal_wr_cnt_reg[3]),
        .I2(wrcal_wr_cnt_reg[2]),
        .I3(wrcal_wr_cnt_reg[0]),
        .I4(wrcal_wr_cnt_reg[1]),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ),
        .O(\init_state_r[1]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hC0C3FAFF00C3FAFF)) 
    \init_state_r[1]_i_13 
       (.I0(\init_state_r[1]_i_25_n_0 ),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(Q),
        .I3(\init_state_r_reg_n_0_[2] ),
        .I4(\init_state_r_reg_n_0_[3] ),
        .I5(\init_state_r[3]_i_20_n_0 ),
        .O(\init_state_r[1]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'h0000000055555DDD)) 
    \init_state_r[1]_i_14 
       (.I0(detect_pi_found_dqs_i_2_n_0),
        .I1(\init_state_r[1]_i_26_n_0 ),
        .I2(\init_state_r[2]_i_38_n_0 ),
        .I3(\init_state_r[2]_i_39_n_0 ),
        .I4(\init_state_r[4]_i_22_n_0 ),
        .I5(\init_state_r[1]_i_27_n_0 ),
        .O(\init_state_r[1]_i_14_n_0 ));
  LUT6 #(
    .INIT(64'hFABFFAFFFABFFABF)) 
    \init_state_r[1]_i_15 
       (.I0(\wrcal_reads[7]_i_4_n_0 ),
        .I1(cnt_cmd_done_r),
        .I2(Q),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(\init_state_r[0]_i_4_0 ),
        .I5(\init_state_r[2]_i_4_0 ),
        .O(\init_state_r[1]_i_15_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFEF000000)) 
    \init_state_r[1]_i_16 
       (.I0(prech_req_posedge_r_reg_0),
        .I1(prbs_rdlvl_done_pulse0),
        .I2(\init_state_r[1]_i_6_0 ),
        .I3(\init_state_r[6]_i_24_n_0 ),
        .I4(\init_state_r[1]_i_29_n_0 ),
        .I5(\init_state_r[1]_i_30_n_0 ),
        .O(\init_state_r[1]_i_16_n_0 ));
  LUT6 #(
    .INIT(64'h5554000055555555)) 
    \init_state_r[1]_i_17 
       (.I0(\cnt_init_mr_r[0]_i_2_n_0 ),
        .I1(pi_dqs_found_done_r1_reg_0),
        .I2(prech_req_posedge_r_reg_0),
        .I3(pi_dqs_found_rank_done),
        .I4(detect_pi_found_dqs_i_2_n_0),
        .I5(\init_state_r[1]_i_31_n_0 ),
        .O(\init_state_r[1]_i_17_n_0 ));
  LUT6 #(
    .INIT(64'h8000000088888888)) 
    \init_state_r[1]_i_18 
       (.I0(cnt_cmd_done_r),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ),
        .I2(\init_state_r[1]_i_32_n_0 ),
        .I3(\init_state_r[0]_i_14_0 ),
        .I4(ddr3_lm_done_r_reg_0),
        .I5(pi_calib_done),
        .O(\init_state_r[1]_i_18_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair403" *) 
  LUT5 #(
    .INIT(32'hAAAA88A0)) 
    \init_state_r[1]_i_19 
       (.I0(\init_state_r[5]_i_46_n_0 ),
        .I1(rdlvl_stg1_done_r1),
        .I2(\init_state_r_reg_n_0_[1] ),
        .I3(cnt_cmd_done_r),
        .I4(reset_rd_addr_r1),
        .O(\init_state_r[1]_i_19_n_0 ));
  LUT6 #(
    .INIT(64'h88882000AAAAAAAA)) 
    \init_state_r[1]_i_2 
       (.I0(init_state_r),
        .I1(\init_state_r_reg_n_0_[2] ),
        .I2(prech_req_posedge_r_reg_0),
        .I3(Q),
        .I4(\init_state_r_reg_n_0_[1] ),
        .I5(\init_state_r[5]_i_28_n_0 ),
        .O(\init_state_r[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF0040)) 
    \init_state_r[1]_i_20 
       (.I0(\wrcal_reads[7]_i_4_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ),
        .I2(cnt_dllk_zqinit_done_r),
        .I3(mem_init_done_r),
        .I4(\init_state_r_reg_n_0_[4] ),
        .I5(\init_state_r[1]_i_34_n_0 ),
        .O(\init_state_r[1]_i_20_n_0 ));
  LUT6 #(
    .INIT(64'h0555404055554040)) 
    \init_state_r[1]_i_21 
       (.I0(\cnt_init_mr_r[0]_i_2_n_0 ),
        .I1(cnt_txpr_done_r),
        .I2(Q),
        .I3(cnt_cmd_done_r),
        .I4(\init_state_r_reg_n_0_[1] ),
        .I5(\init_state_r[2]_i_31_n_0 ),
        .O(\init_state_r[1]_i_21_n_0 ));
  LUT6 #(
    .INIT(64'h0000800000000000)) 
    \init_state_r[1]_i_22 
       (.I0(complex_wait_cnt_reg[3]),
        .I1(complex_wait_cnt_reg[2]),
        .I2(complex_wait_cnt_reg[1]),
        .I3(complex_wait_cnt_reg[0]),
        .I4(\init_state_r_reg_n_0_[1] ),
        .I5(Q),
        .O(\init_state_r[1]_i_22_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair396" *) 
  LUT5 #(
    .INIT(32'hBAABAAAB)) 
    \init_state_r[1]_i_23 
       (.I0(\init_state_r_reg_n_0_[3] ),
        .I1(\init_state_r_reg_n_0_[2] ),
        .I2(Q),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(cnt_cmd_done_r),
        .O(\init_state_r[1]_i_23_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair480" *) 
  LUT3 #(
    .INIT(8'h8F)) 
    \init_state_r[1]_i_24 
       (.I0(p_17_in),
        .I1(Q),
        .I2(\init_state_r_reg_n_0_[1] ),
        .O(\init_state_r[1]_i_24_n_0 ));
  LUT6 #(
    .INIT(64'h000000000001FF01)) 
    \init_state_r[1]_i_25 
       (.I0(wrlvl_byte_redo),
        .I1(prech_req_posedge_r_reg_0),
        .I2(ddr3_lm_done_r_reg_0),
        .I3(wrcal_resume_r),
        .I4(wrcal_final_chk),
        .I5(\init_state_r_reg_n_0_[1] ),
        .O(\init_state_r[1]_i_25_n_0 ));
  LUT6 #(
    .INIT(64'hF0FFF0FFFFFFF8FF)) 
    \init_state_r[1]_i_26 
       (.I0(prbs_last_byte_done_r),
        .I1(mem_init_done_r),
        .I2(ddr3_lm_done_r_reg_0),
        .I3(pi_dqs_found_done_r1_reg_0),
        .I4(prbs_rdlvl_start_reg_2),
        .I5(complex_oclkdelay_calib_done_r1_reg_0),
        .O(\init_state_r[1]_i_26_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair444" *) 
  LUT4 #(
    .INIT(16'h2232)) 
    \init_state_r[1]_i_27 
       (.I0(Q),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(cnt_cmd_done_r),
        .I3(ddr2_pre_flag_r_reg_n_0),
        .O(\init_state_r[1]_i_27_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair480" *) 
  LUT3 #(
    .INIT(8'h4F)) 
    \init_state_r[1]_i_29 
       (.I0(num_reads[1]),
        .I1(num_reads[0]),
        .I2(Q),
        .O(\init_state_r[1]_i_29_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF00F1FFFF)) 
    \init_state_r[1]_i_3 
       (.I0(\init_state_r[1]_i_8_n_0 ),
        .I1(complex_sample_cnt_inc_i_2_n_0),
        .I2(\init_state_r[1]_i_9_n_0 ),
        .I3(\init_state_r[4]_i_4_n_0 ),
        .I4(\init_state_r_reg_n_0_[4] ),
        .I5(\init_state_r[1]_i_10_n_0 ),
        .O(\init_state_r[1]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h3E000000FFFFFFFF)) 
    \init_state_r[1]_i_30 
       (.I0(cnt_cmd_done_r),
        .I1(Q),
        .I2(\init_state_r_reg_n_0_[1] ),
        .I3(\init_state_r_reg_n_0_[2] ),
        .I4(\init_state_r_reg_n_0_[3] ),
        .I5(\init_state_r_reg_n_0_[4] ),
        .O(\init_state_r[1]_i_30_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair403" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \init_state_r[1]_i_31 
       (.I0(cnt_cmd_done_r),
        .I1(\init_state_r_reg_n_0_[1] ),
        .O(\init_state_r[1]_i_31_n_0 ));
  LUT6 #(
    .INIT(64'hCCDDFFFF051D051D)) 
    \init_state_r[1]_i_32 
       (.I0(\one_rank.stg1_wr_done_reg_0 ),
        .I1(prbs_rdlvl_start_reg_2),
        .I2(prbs_last_byte_done),
        .I3(rdlvl_last_byte_done),
        .I4(rdlvl_stg1_start_int),
        .I5(complex_oclkdelay_calib_done_r1_reg_0),
        .O(\init_state_r[1]_i_32_n_0 ));
  LUT6 #(
    .INIT(64'h0000FCCC44CC0000)) 
    \init_state_r[1]_i_34 
       (.I0(wrlvl_rank_done_r7),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(cnt_cmd_done_r),
        .I3(Q),
        .I4(\init_state_r_reg_n_0_[2] ),
        .I5(\init_state_r_reg_n_0_[3] ),
        .O(\init_state_r[1]_i_34_n_0 ));
  LUT6 #(
    .INIT(64'h8080888088888888)) 
    \init_state_r[1]_i_4 
       (.I0(\init_state_r_reg_n_0_[2] ),
        .I1(\init_state_r_reg_n_0_[3] ),
        .I2(\init_state_r[5]_i_13_n_0 ),
        .I3(Q),
        .I4(complex_sample_cnt_inc_i_2_n_0),
        .I5(\init_state_r[5]_i_12_n_0 ),
        .O(\init_state_r[1]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hDFDFDFDDDDDDDDDD)) 
    \init_state_r[1]_i_5 
       (.I0(\init_state_r_reg_n_0_[5] ),
        .I1(init_state_r),
        .I2(\init_state_r[1]_i_11_n_0 ),
        .I3(\init_state_r[1]_i_12_n_0 ),
        .I4(\cnt_init_mr_r[0]_i_2_n_0 ),
        .I5(\init_state_r[1]_i_13_n_0 ),
        .O(\init_state_r[1]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAFEAA)) 
    \init_state_r[1]_i_6 
       (.I0(\init_state_r[3]_i_6_n_0 ),
        .I1(\init_state_r[4]_i_4_n_0 ),
        .I2(\init_state_r[1]_i_14_n_0 ),
        .I3(\init_state_r[1]_i_15_n_0 ),
        .I4(\init_state_r[1]_i_16_n_0 ),
        .I5(\init_state_r[1]_i_17_n_0 ),
        .O(\init_state_r[1]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h00000000000000F2)) 
    \init_state_r[1]_i_7 
       (.I0(\init_state_r[6]_i_20_n_0 ),
        .I1(\init_state_r[1]_i_18_n_0 ),
        .I2(rdlvl_stg1_start_int_i_2_n_0),
        .I3(\init_state_r[1]_i_19_n_0 ),
        .I4(\init_state_r[1]_i_20_n_0 ),
        .I5(\init_state_r[1]_i_21_n_0 ),
        .O(\init_state_r[1]_i_7_n_0 ));
  LUT5 #(
    .INIT(32'hAAAAAAAB)) 
    \init_state_r[1]_i_8 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(\init_state_r[6]_i_22_n_0 ),
        .I2(complex_row0_rd_done),
        .I3(complex_num_reads_dec[3]),
        .I4(complex_num_reads_dec[2]),
        .O(\init_state_r[1]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'h0030BABA00FFBABA)) 
    \init_state_r[1]_i_9 
       (.I0(prech_req_posedge_r_reg_0),
        .I1(prbs_rdlvl_done_r1),
        .I2(complex_oclkdelay_calib_done_r1_reg_0),
        .I3(Q),
        .I4(\init_state_r_reg_n_0_[1] ),
        .I5(\init_state_r[5]_i_13_n_0 ),
        .O(\init_state_r[1]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hAEAEAEAEFFAEFFFF)) 
    \init_state_r[2]_i_1 
       (.I0(\init_state_r[2]_i_2_n_0 ),
        .I1(\init_state_r[2]_i_3_n_0 ),
        .I2(\init_state_r[2]_i_4_n_0 ),
        .I3(\init_state_r[2]_i_5_n_0 ),
        .I4(\init_state_r[2]_i_6_n_0 ),
        .I5(\init_state_r[2]_i_7_n_0 ),
        .O(\init_state_r[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF00001FFF)) 
    \init_state_r[2]_i_10 
       (.I0(rdlvl_stg1_start_int_reg_0),
        .I1(\init_state_r[2]_i_3_0 ),
        .I2(\init_state_r[2]_i_29_n_0 ),
        .I3(pi_calib_done),
        .I4(\init_state_r_reg_n_0_[1] ),
        .I5(\init_state_r[2]_i_30_n_0 ),
        .O(\init_state_r[2]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hFFF8FFF8FFF8FFFF)) 
    \init_state_r[2]_i_11 
       (.I0(\init_state_r[2]_i_31_n_0 ),
        .I1(\init_state_r[2]_i_32_n_0 ),
        .I2(\init_state_r_reg_n_0_[4] ),
        .I3(\init_state_r[2]_i_33_n_0 ),
        .I4(\wrcal_reads[7]_i_4_n_0 ),
        .I5(\init_state_r[2]_i_34_n_0 ),
        .O(\init_state_r[2]_i_11_n_0 ));
  LUT6 #(
    .INIT(64'h67000000FFFFFFFF)) 
    \init_state_r[2]_i_12 
       (.I0(Q),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(cnt_cmd_done_r),
        .I3(\init_state_r_reg_n_0_[2] ),
        .I4(\init_state_r_reg_n_0_[3] ),
        .I5(\init_state_r_reg_n_0_[4] ),
        .O(\init_state_r[2]_i_12_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair405" *) 
  LUT5 #(
    .INIT(32'hBAAAAAAA)) 
    \init_state_r[2]_i_13 
       (.I0(\init_state_r_reg_n_0_[3] ),
        .I1(\init_state_r_reg_n_0_[2] ),
        .I2(\init_state_r_reg_n_0_[1] ),
        .I3(Q),
        .I4(cnt_cmd_done_r),
        .O(\init_state_r[2]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'h77777777FF7F7777)) 
    \init_state_r[2]_i_14 
       (.I0(prbs_rdlvl_start_i_2_n_0),
        .I1(\init_state_r_reg_n_0_[2] ),
        .I2(ddr3_lm_done_r),
        .I3(\init_state_r[2]_i_4_0 ),
        .I4(\init_state_r[2]_i_29_n_0 ),
        .I5(\init_state_r[0]_i_4_0 ),
        .O(\init_state_r[2]_i_14_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FFFFF474)) 
    \init_state_r[2]_i_15 
       (.I0(\init_state_r[2]_i_36_n_0 ),
        .I1(\init_state_r[4]_i_10_0 ),
        .I2(\init_state_r[2]_i_38_n_0 ),
        .I3(\init_state_r[2]_i_39_n_0 ),
        .I4(\init_state_r[2]_i_40_n_0 ),
        .I5(\init_state_r[2]_i_41_n_0 ),
        .O(\init_state_r[2]_i_15_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair443" *) 
  LUT4 #(
    .INIT(16'hAA2A)) 
    \init_state_r[2]_i_16 
       (.I0(\init_state_r_reg_n_0_[3] ),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(Q),
        .I3(\init_state_r_reg_n_0_[2] ),
        .O(\init_state_r[2]_i_16_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF7500FFFFFFFF)) 
    \init_state_r[2]_i_17 
       (.I0(\init_state_r[5]_i_13_n_0 ),
        .I1(prbs_rdlvl_done_r1),
        .I2(complex_oclkdelay_calib_done_r1_reg_0),
        .I3(detect_pi_found_dqs_i_2_n_0),
        .I4(\init_state_r_reg_n_0_[2] ),
        .I5(\init_state_r_reg_n_0_[3] ),
        .O(\init_state_r[2]_i_17_n_0 ));
  LUT6 #(
    .INIT(64'h0000FFDFFFDFFFDF)) 
    \init_state_r[2]_i_18 
       (.I0(\init_state_r[5]_i_48_n_0 ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[1] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[0] ),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[2] ),
        .I4(Q),
        .I5(\init_state_r[5]_i_13_n_0 ),
        .O(\init_state_r[2]_i_18_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF10111010)) 
    \init_state_r[2]_i_19 
       (.I0(\init_state_r_reg_n_0_[3] ),
        .I1(\init_state_r[2]_i_42_n_0 ),
        .I2(\init_state_r[5]_i_41_n_0 ),
        .I3(\init_state_r[2]_i_43_n_0 ),
        .I4(\init_state_r[5]_i_27_n_0 ),
        .I5(\init_state_r[2]_i_44_n_0 ),
        .O(\init_state_r[2]_i_19_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair430" *) 
  LUT5 #(
    .INIT(32'hAAAA8000)) 
    \init_state_r[2]_i_2 
       (.I0(init_state_r),
        .I1(complex_pi_incdec_done),
        .I2(Q),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(\init_state_r_reg_n_0_[2] ),
        .O(\init_state_r[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFDFFFFF00000000)) 
    \init_state_r[2]_i_20 
       (.I0(Q),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[2] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[0] ),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[1] ),
        .I4(\init_state_r[5]_i_48_n_0 ),
        .I5(\init_state_r[5]_i_12_n_0 ),
        .O(\init_state_r[2]_i_20_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair448" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \init_state_r[2]_i_21 
       (.I0(Q),
        .I1(complex_oclkdelay_calib_done_r1_reg_0),
        .O(\init_state_r[2]_i_21_n_0 ));
  LUT6 #(
    .INIT(64'hEFEEEEEEEEEEEEEE)) 
    \init_state_r[2]_i_22 
       (.I0(\init_state_r_reg_n_0_[3] ),
        .I1(\init_state_r_reg_n_0_[4] ),
        .I2(\init_state_r_reg_n_0_[2] ),
        .I3(Q),
        .I4(\init_state_r_reg_n_0_[1] ),
        .I5(p_17_in),
        .O(\init_state_r[2]_i_22_n_0 ));
  LUT6 #(
    .INIT(64'hFFAAFFFFBAAAFFFF)) 
    \init_state_r[2]_i_23 
       (.I0(\init_state_r[2]_i_45_n_0 ),
        .I1(pi_phase_locked_all_r4),
        .I2(pi_phase_locked_all_r3),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(\init_state_r_reg_n_0_[2] ),
        .I5(Q),
        .O(\init_state_r[2]_i_23_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair404" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \init_state_r[2]_i_24 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(\init_state_r_reg_n_0_[2] ),
        .O(\init_state_r[2]_i_24_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair431" *) 
  LUT5 #(
    .INIT(32'h0004FFFF)) 
    \init_state_r[2]_i_25 
       (.I0(oclk_wr_cnt_reg[1]),
        .I1(oclk_wr_cnt_reg[0]),
        .I2(oclk_wr_cnt_reg[2]),
        .I3(oclk_wr_cnt_reg[3]),
        .I4(Q),
        .O(\init_state_r[2]_i_25_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF5FD5F555)) 
    \init_state_r[2]_i_26 
       (.I0(\init_state_r_reg_n_0_[3] ),
        .I1(cnt_cmd_done_r),
        .I2(\init_state_r_reg_n_0_[1] ),
        .I3(Q),
        .I4(\init_state_r_reg_n_0_[2] ),
        .I5(\init_state_r_reg_n_0_[4] ),
        .O(\init_state_r[2]_i_26_n_0 ));
  LUT6 #(
    .INIT(64'hDDDF0003DCDC0000)) 
    \init_state_r[2]_i_27 
       (.I0(rdlvl_stg1_start_int),
        .I1(prbs_rdlvl_start_reg_2),
        .I2(rdlvl_last_byte_done),
        .I3(prbs_last_byte_done),
        .I4(complex_oclkdelay_calib_done_r1_reg_0),
        .I5(\one_rank.stg1_wr_done_reg_0 ),
        .O(rdlvl_stg1_start_int_reg_0));
  LUT2 #(
    .INIT(4'h8)) 
    \init_state_r[2]_i_29 
       (.I0(Q),
        .I1(cnt_cmd_done_r),
        .O(\init_state_r[2]_i_29_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF0000FF0D)) 
    \init_state_r[2]_i_3 
       (.I0(\init_state_r[2]_i_8_n_0 ),
        .I1(\init_state_r[2]_i_9_n_0 ),
        .I2(Q),
        .I3(\init_state_r[2]_i_10_n_0 ),
        .I4(rdlvl_stg1_start_int_i_2_n_0),
        .I5(\init_state_r[2]_i_11_n_0 ),
        .O(\init_state_r[2]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair444" *) 
  LUT4 #(
    .INIT(16'h0040)) 
    \init_state_r[2]_i_30 
       (.I0(cnt_cmd_done_r),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(Q),
        .I3(reset_rd_addr_r1),
        .O(\init_state_r[2]_i_30_n_0 ));
  LUT5 #(
    .INIT(32'hFBBBBBBB)) 
    \init_state_r[2]_i_31 
       (.I0(cnt_init_mr_done_r),
        .I1(cnt_cmd_done_r),
        .I2(pi_dqs_found_done_r1_reg_0),
        .I3(prbs_rdlvl_start_reg_2),
        .I4(complex_oclkdelay_calib_done_r1_reg_0),
        .O(\init_state_r[2]_i_31_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair396" *) 
  LUT5 #(
    .INIT(32'h10000000)) 
    \init_state_r[2]_i_32 
       (.I0(\init_state_r_reg_n_0_[2] ),
        .I1(\init_state_r_reg_n_0_[3] ),
        .I2(cnt_cmd_done_r),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(Q),
        .O(\init_state_r[2]_i_32_n_0 ));
  LUT6 #(
    .INIT(64'h0000400000000000)) 
    \init_state_r[2]_i_33 
       (.I0(wrlvl_done_r1),
        .I1(cnt_cmd_done_r),
        .I2(\init_state_r_reg_n_0_[1] ),
        .I3(Q),
        .I4(\init_state_r_reg_n_0_[2] ),
        .I5(\init_state_r_reg_n_0_[3] ),
        .O(\init_state_r[2]_i_33_n_0 ));
  LUT6 #(
    .INIT(64'h808A8080808A8A8A)) 
    \init_state_r[2]_i_34 
       (.I0(Q),
        .I1(wrlvl_rank_done_r7),
        .I2(\init_state_r_reg_n_0_[1] ),
        .I3(mem_init_done_r),
        .I4(cnt_dllk_zqinit_done_r),
        .I5(\init_state_r_reg_n_0_[2] ),
        .O(\init_state_r[2]_i_34_n_0 ));
  LUT6 #(
    .INIT(64'h20FFFFFF2020FF00)) 
    \init_state_r[2]_i_36 
       (.I0(prbs_last_byte_done_r),
        .I1(complex_oclkdelay_calib_done_r1_reg_0),
        .I2(pi_dqs_found_done_r1_reg_0),
        .I3(ddr3_lm_done_r_reg_0),
        .I4(mem_init_done_r),
        .I5(wrlvl_byte_redo),
        .O(\init_state_r[2]_i_36_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair460" *) 
  LUT4 #(
    .INIT(16'h0010)) 
    \init_state_r[2]_i_38 
       (.I0(num_refresh_reg[0]),
        .I1(num_refresh_reg[1]),
        .I2(num_refresh_reg[3]),
        .I3(num_refresh_reg[2]),
        .O(\init_state_r[2]_i_38_n_0 ));
  LUT4 #(
    .INIT(16'h2000)) 
    \init_state_r[2]_i_39 
       (.I0(pi_dqs_found_done_r1_reg_0),
        .I1(complex_oclkdelay_calib_done_r1_reg_0),
        .I2(prbs_last_byte_done_r),
        .I3(mem_init_done_r),
        .O(\init_state_r[2]_i_39_n_0 ));
  LUT6 #(
    .INIT(64'hABAABBBBABAAABAA)) 
    \init_state_r[2]_i_4 
       (.I0(\init_state_r[3]_i_6_n_0 ),
        .I1(\init_state_r[2]_i_12_n_0 ),
        .I2(\init_state_r[2]_i_13_n_0 ),
        .I3(\init_state_r[2]_i_14_n_0 ),
        .I4(\init_state_r[2]_i_15_n_0 ),
        .I5(\init_state_r[2]_i_16_n_0 ),
        .O(\init_state_r[2]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair436" *) 
  LUT3 #(
    .INIT(8'h04)) 
    \init_state_r[2]_i_40 
       (.I0(wrlvl_done_r1),
        .I1(pi_dqs_found_done_r1_reg_0),
        .I2(wrlvl_byte_redo),
        .O(\init_state_r[2]_i_40_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair404" *) 
  LUT5 #(
    .INIT(32'hDFDFFFDF)) 
    \init_state_r[2]_i_41 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(\init_state_r_reg_n_0_[2] ),
        .I2(cnt_cmd_done_r),
        .I3(cnt_init_af_done_r),
        .I4(mem_init_done_r),
        .O(\init_state_r[2]_i_41_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair395" *) 
  LUT5 #(
    .INIT(32'h0020FFFF)) 
    \init_state_r[2]_i_42 
       (.I0(complex_oclkdelay_calib_done_r1_reg_0),
        .I1(prbs_rdlvl_done_r1),
        .I2(Q),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(\init_state_r_reg_n_0_[2] ),
        .O(\init_state_r[2]_i_42_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair397" *) 
  LUT5 #(
    .INIT(32'h80000000)) 
    \init_state_r[2]_i_43 
       (.I0(complex_wait_cnt_reg[3]),
        .I1(complex_wait_cnt_reg[2]),
        .I2(complex_wait_cnt_reg[1]),
        .I3(complex_wait_cnt_reg[0]),
        .I4(\one_rank.stg1_wr_done_reg_0 ),
        .O(\init_state_r[2]_i_43_n_0 ));
  LUT6 #(
    .INIT(64'h00000080FFFFFFFF)) 
    \init_state_r[2]_i_44 
       (.I0(Q),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(cnt_cmd_done_r),
        .I3(\init_state_r_reg_n_0_[3] ),
        .I4(\init_state_r_reg_n_0_[2] ),
        .I5(\init_state_r_reg_n_0_[4] ),
        .O(\init_state_r[2]_i_44_n_0 ));
  LUT6 #(
    .INIT(64'h1111111111111110)) 
    \init_state_r[2]_i_45 
       (.I0(Q),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(wrlvl_byte_redo),
        .I3(prech_req_posedge_r_reg_0),
        .I4(ddr3_lm_done_r_reg_0),
        .I5(wrcal_resume_r),
        .O(\init_state_r[2]_i_45_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF45444444)) 
    \init_state_r[2]_i_5 
       (.I0(\init_state_r[2]_i_17_n_0 ),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(\init_state_r[6]_i_11_n_0 ),
        .I3(\init_state_r_reg_n_0_[2] ),
        .I4(\init_state_r[2]_i_18_n_0 ),
        .I5(\init_state_r[2]_i_19_n_0 ),
        .O(\init_state_r[2]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair412" *) 
  LUT5 #(
    .INIT(32'h7F5F7F7F)) 
    \init_state_r[2]_i_6 
       (.I0(\init_state_r_reg_n_0_[3] ),
        .I1(\init_state_r[2]_i_20_n_0 ),
        .I2(\init_state_r_reg_n_0_[2] ),
        .I3(\init_state_r[2]_i_21_n_0 ),
        .I4(\init_state_r_reg_n_0_[1] ),
        .O(\init_state_r[2]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF4444FF4F)) 
    \init_state_r[2]_i_7 
       (.I0(\init_state_r[2]_i_22_n_0 ),
        .I1(\init_state_r[2]_i_23_n_0 ),
        .I2(\init_state_r[2]_i_24_n_0 ),
        .I3(\init_state_r[2]_i_25_n_0 ),
        .I4(\init_state_r[2]_i_26_n_0 ),
        .I5(complex_act_start_i_2_n_0),
        .O(\init_state_r[2]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFBFFFFFFFFFF)) 
    \init_state_r[2]_i_8 
       (.I0(prbs_gen_oclk_clk_en_i_9_n_0),
        .I1(rdlvl_stg1_done_r1),
        .I2(complex_row0_wr_done),
        .I3(complex_oclkdelay_calib_done_r1_reg_0),
        .I4(complex_num_writes_dec[1]),
        .I5(complex_num_writes_dec[0]),
        .O(\init_state_r[2]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFEFFFFFFFFFF)) 
    \init_state_r[2]_i_9 
       (.I0(\stg1_wr_rd_cnt_reg_n_0_[5] ),
        .I1(complex_sample_cnt_inc_i_3_n_0),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[1] ),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[0] ),
        .I4(\stg1_wr_rd_cnt_reg_n_0_[2] ),
        .I5(rdlvl_stg1_done_r1),
        .O(\init_state_r[2]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hEEEEEEEEFFFFEEEF)) 
    \init_state_r[3]_i_1 
       (.I0(\init_state_r[3]_i_2_n_0 ),
        .I1(\init_state_r[3]_i_3_n_0 ),
        .I2(\init_state_r[3]_i_4_n_0 ),
        .I3(\init_state_r_reg_n_0_[4] ),
        .I4(\init_state_r[3]_i_5_n_0 ),
        .I5(\init_state_r[3]_i_6_n_0 ),
        .O(\init_state_r[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h000A3333AAAABBBB)) 
    \init_state_r[3]_i_10 
       (.I0(\init_state_r[3]_i_21_n_0 ),
        .I1(\init_state_r_reg_n_0_[3] ),
        .I2(complex_oclkdelay_calib_done_r1_reg_0),
        .I3(prbs_last_byte_done_r),
        .I4(\init_state_r[5]_i_13_n_0 ),
        .I5(\init_state_r[3]_i_22_n_0 ),
        .O(\init_state_r[3]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'h00000000000C040C)) 
    \init_state_r[3]_i_11 
       (.I0(\init_state_r[5]_i_13_n_0 ),
        .I1(\init_state_r_reg_n_0_[3] ),
        .I2(\init_state_r_reg_n_0_[2] ),
        .I3(detect_pi_found_dqs_i_2_n_0),
        .I4(prbs_rdlvl_done_pulse0),
        .I5(\init_state_r[5]_i_42_n_0 ),
        .O(\init_state_r[3]_i_11_n_0 ));
  LUT6 #(
    .INIT(64'h000000F0DDDDFFFF)) 
    \init_state_r[3]_i_12 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(\init_state_r[2]_i_21_n_0 ),
        .I2(\init_state_r[5]_i_14_n_0 ),
        .I3(\init_state_r[5]_i_13_n_0 ),
        .I4(\init_state_r_reg_n_0_[3] ),
        .I5(\init_state_r[5]_i_12_n_0 ),
        .O(\init_state_r[3]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'h0BFB000000000000)) 
    \init_state_r[3]_i_13 
       (.I0(\init_state_r[3]_i_4_0 ),
        .I1(pi_calib_done),
        .I2(\init_state_r_reg_n_0_[1] ),
        .I3(reset_rd_addr_r1),
        .I4(Q),
        .I5(cnt_cmd_done_r),
        .O(\init_state_r[3]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'h0F0F3F0F4F7F7F7F)) 
    \init_state_r[3]_i_14 
       (.I0(wrlvl_rank_done_r7),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(Q),
        .I3(cnt_dllk_zqinit_done_r),
        .I4(mem_init_done_r),
        .I5(\init_state_r_reg_n_0_[3] ),
        .O(\init_state_r[3]_i_14_n_0 ));
  LUT6 #(
    .INIT(64'hAA88AA8CAA88EE8C)) 
    \init_state_r[3]_i_15 
       (.I0(\init_state_r_reg_n_0_[2] ),
        .I1(cnt_cmd_done_r),
        .I2(ddr2_pre_flag_r_reg_n_0),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(Q),
        .I5(\init_state_r[3]_i_24_n_0 ),
        .O(\init_state_r[3]_i_15_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair488" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \init_state_r[3]_i_16 
       (.I0(\init_state_r_reg_n_0_[4] ),
        .I1(\init_state_r_reg_n_0_[3] ),
        .O(\init_state_r[3]_i_16_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair522" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \init_state_r[3]_i_17 
       (.I0(\init_state_r_reg_n_0_[4] ),
        .I1(\init_state_r_reg_n_0_[2] ),
        .O(\init_state_r[3]_i_17_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair521" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \init_state_r[3]_i_18 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(\init_state_r_reg_n_0_[3] ),
        .O(\init_state_r[3]_i_18_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFF04FF00FF00)) 
    \init_state_r[3]_i_19 
       (.I0(\init_state_r[4]_i_24_n_0 ),
        .I1(cnt_cmd_done_r),
        .I2(\init_state_r[0]_i_4_0 ),
        .I3(\init_state_r_reg_n_0_[3] ),
        .I4(\init_state_r_reg_n_0_[1] ),
        .I5(Q),
        .O(\init_state_r[3]_i_19_n_0 ));
  LUT5 #(
    .INIT(32'hF4444444)) 
    \init_state_r[3]_i_2 
       (.I0(\init_state_r[3]_i_7_n_0 ),
        .I1(\init_state_r[3]_i_8_n_0 ),
        .I2(\init_state_r_reg_n_0_[3] ),
        .I3(init_state_r),
        .I4(\init_state_r[3]_i_9_n_0 ),
        .O(\init_state_r[3]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair406" *) 
  LUT4 #(
    .INIT(16'h0010)) 
    \init_state_r[3]_i_20 
       (.I0(oclk_wr_cnt_reg[3]),
        .I1(oclk_wr_cnt_reg[2]),
        .I2(oclk_wr_cnt_reg[0]),
        .I3(oclk_wr_cnt_reg[1]),
        .O(\init_state_r[3]_i_20_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair398" *) 
  LUT3 #(
    .INIT(8'hBF)) 
    \init_state_r[3]_i_21 
       (.I0(prech_req_posedge_r_reg_0),
        .I1(Q),
        .I2(\init_state_r_reg_n_0_[1] ),
        .O(\init_state_r[3]_i_21_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair395" *) 
  LUT4 #(
    .INIT(16'h4044)) 
    \init_state_r[3]_i_22 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(Q),
        .I2(prbs_rdlvl_done_r1),
        .I3(complex_oclkdelay_calib_done_r1_reg_0),
        .O(\init_state_r[3]_i_22_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair436" *) 
  LUT5 #(
    .INIT(32'hFB00FBFB)) 
    \init_state_r[3]_i_24 
       (.I0(wrlvl_byte_redo),
        .I1(pi_dqs_found_done_r1_reg_0),
        .I2(wrlvl_done_r1),
        .I3(mem_init_done_r),
        .I4(cnt_init_af_done_r),
        .O(\init_state_r[3]_i_24_n_0 ));
  LUT6 #(
    .INIT(64'h5555010055555100)) 
    \init_state_r[3]_i_3 
       (.I0(\init_state_r[6]_i_2_n_0 ),
        .I1(\init_state_r[3]_i_10_n_0 ),
        .I2(\init_state_r_reg_n_0_[3] ),
        .I3(\init_state_r_reg_n_0_[2] ),
        .I4(\init_state_r[3]_i_11_n_0 ),
        .I5(\init_state_r[3]_i_12_n_0 ),
        .O(\init_state_r[3]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h8F838F83BFB38F83)) 
    \init_state_r[3]_i_4 
       (.I0(\init_state_r[3]_i_13_n_0 ),
        .I1(\init_state_r_reg_n_0_[2] ),
        .I2(\init_state_r_reg_n_0_[3] ),
        .I3(\init_state_r[3]_i_14_n_0 ),
        .I4(cnt_cmd_done_r),
        .I5(prbs_rdlvl_start_i_2_n_0),
        .O(\init_state_r[3]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h44444F4444444444)) 
    \init_state_r[3]_i_5 
       (.I0(\init_state_r[3]_i_15_n_0 ),
        .I1(\init_state_r[3]_i_16_n_0 ),
        .I2(\init_state_r[4]_i_13_n_0 ),
        .I3(\init_state_r[3]_i_17_n_0 ),
        .I4(\init_state_r[3]_i_18_n_0 ),
        .I5(\init_state_r[3]_i_19_n_0 ),
        .O(\init_state_r[3]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair452" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \init_state_r[3]_i_6 
       (.I0(init_state_r),
        .I1(\init_state_r_reg_n_0_[5] ),
        .O(\init_state_r[3]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h883F000000000000)) 
    \init_state_r[3]_i_7 
       (.I0(\init_state_r[3]_i_20_n_0 ),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(cnt_cmd_done_r),
        .I3(Q),
        .I4(\init_state_r_reg_n_0_[3] ),
        .I5(\init_state_r_reg_n_0_[2] ),
        .O(\init_state_r[3]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h000000000000EF80)) 
    \init_state_r[3]_i_8 
       (.I0(Q),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(\init_state_r_reg_n_0_[2] ),
        .I3(\init_state_r_reg_n_0_[3] ),
        .I4(\init_state_r_reg_n_0_[4] ),
        .I5(complex_act_start_i_2_n_0),
        .O(\init_state_r[3]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hF1F1F5F5F1FFF5F5)) 
    \init_state_r[3]_i_9 
       (.I0(\init_state_r[5]_i_28_n_0 ),
        .I1(complex_pi_incdec_done),
        .I2(\init_state_r_reg_n_0_[2] ),
        .I3(prech_req_posedge_r_reg_0),
        .I4(Q),
        .I5(\init_state_r_reg_n_0_[1] ),
        .O(\init_state_r[3]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF5501)) 
    \init_state_r[4]_i_1 
       (.I0(\init_state_r[4]_i_2_n_0 ),
        .I1(\init_state_r[4]_i_3_n_0 ),
        .I2(\init_state_r[4]_i_4_n_0 ),
        .I3(\init_state_r[4]_i_5_n_0 ),
        .I4(\init_state_r[4]_i_6_n_0 ),
        .I5(\init_state_r[4]_i_7_n_0 ),
        .O(\init_state_r[4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hEEAEEEEEEEEEEEEE)) 
    \init_state_r[4]_i_10 
       (.I0(\init_state_r[4]_i_22_n_0 ),
        .I1(\init_state_r[4]_i_23_n_0 ),
        .I2(pi_dqs_found_done_r1_reg_0),
        .I3(complex_oclkdelay_calib_done_r1_reg_0),
        .I4(prbs_last_byte_done_r),
        .I5(mem_init_done_r),
        .O(\init_state_r[4]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'h5455105554555455)) 
    \init_state_r[4]_i_11 
       (.I0(\wrcal_reads[7]_i_4_n_0 ),
        .I1(cnt_cmd_done_r),
        .I2(\init_state_r_reg_n_0_[4] ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ),
        .I4(\init_state_r[0]_i_4_0 ),
        .I5(\init_state_r[4]_i_24_n_0 ),
        .O(\init_state_r[4]_i_11_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair443" *) 
  LUT4 #(
    .INIT(16'h7000)) 
    \init_state_r[4]_i_12 
       (.I0(Q),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(\init_state_r_reg_n_0_[2] ),
        .I3(\init_state_r_reg_n_0_[3] ),
        .O(\init_state_r[4]_i_12_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair417" *) 
  LUT5 #(
    .INIT(32'h00000010)) 
    \init_state_r[4]_i_13 
       (.I0(Q),
        .I1(reg_ctrl_cnt_r_reg[2]),
        .I2(reg_ctrl_cnt_r_reg[3]),
        .I3(reg_ctrl_cnt_r_reg[1]),
        .I4(reg_ctrl_cnt_r_reg[0]),
        .O(\init_state_r[4]_i_13_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair482" *) 
  LUT3 #(
    .INIT(8'h1F)) 
    \init_state_r[4]_i_14 
       (.I0(\init_state_r_reg_n_0_[2] ),
        .I1(\init_state_r_reg_n_0_[3] ),
        .I2(\init_state_r_reg_n_0_[4] ),
        .O(\init_state_r[4]_i_14_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0FFF4FFF4FFF)) 
    \init_state_r[4]_i_15 
       (.I0(\init_state_r[4]_i_25_n_0 ),
        .I1(\init_state_r[4]_i_26_n_0 ),
        .I2(\init_state_r_reg_n_0_[4] ),
        .I3(\init_state_r_reg_n_0_[2] ),
        .I4(detect_pi_found_dqs_i_2_n_0),
        .I5(\init_state_r_reg_n_0_[3] ),
        .O(\init_state_r[4]_i_15_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair387" *) 
  LUT5 #(
    .INIT(32'hBA00FF00)) 
    \init_state_r[4]_i_16 
       (.I0(prech_req_posedge_r_reg_0),
        .I1(complex_oclkdelay_calib_done_r1),
        .I2(complex_oclkdelay_calib_done_r1_reg_0),
        .I3(Q),
        .I4(complex_sample_cnt_inc_i_2_n_0),
        .O(\init_state_r[4]_i_16_n_0 ));
  LUT6 #(
    .INIT(64'hDDDFDDDFDDDFDDDD)) 
    \init_state_r[4]_i_17 
       (.I0(\init_state_r_reg_n_0_[5] ),
        .I1(init_state_r),
        .I2(\init_state_r[3]_i_7_n_0 ),
        .I3(\init_state_r[1]_i_11_n_0 ),
        .I4(\wrcal_reads[7]_i_4_n_0 ),
        .I5(\init_state_r[4]_i_27_n_0 ),
        .O(\init_state_r[4]_i_17_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair421" *) 
  LUT5 #(
    .INIT(32'h0000C0A0)) 
    \init_state_r[4]_i_18 
       (.I0(prech_req_posedge_r_reg_0),
        .I1(complex_pi_incdec_done),
        .I2(Q),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(\init_state_r_reg_n_0_[2] ),
        .O(\init_state_r[4]_i_18_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair438" *) 
  LUT4 #(
    .INIT(16'h3F7F)) 
    \init_state_r[4]_i_19 
       (.I0(cnt_cmd_done_r),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(Q),
        .I3(\init_state_r_reg_n_0_[4] ),
        .O(\init_state_r[4]_i_19_n_0 ));
  LUT6 #(
    .INIT(64'hEEEFEEEFEEEFEEEE)) 
    \init_state_r[4]_i_2 
       (.I0(\init_state_r_reg_n_0_[5] ),
        .I1(init_state_r),
        .I2(\init_state_r_reg_n_0_[4] ),
        .I3(\init_state_r[4]_i_8_n_0 ),
        .I4(rdlvl_stg1_start_int_i_2_n_0),
        .I5(\init_state_r[4]_i_9_n_0 ),
        .O(\init_state_r[4]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hB000A000F000E000)) 
    \init_state_r[4]_i_20 
       (.I0(reset_rd_addr_r1),
        .I1(cnt_cmd_done_r),
        .I2(\init_state_r_reg_n_0_[1] ),
        .I3(Q),
        .I4(\init_state_r_reg_n_0_[4] ),
        .I5(rdlvl_stg1_done_r1),
        .O(\init_state_r[4]_i_20_n_0 ));
  LUT6 #(
    .INIT(64'h0000000080CC0000)) 
    \init_state_r[4]_i_21 
       (.I0(rdlvl_stg1_start_int_reg_0),
        .I1(\init_state_r[2]_i_29_n_0 ),
        .I2(ddr3_lm_done_r_reg_0),
        .I3(pi_dqs_found_done_r1_reg_0),
        .I4(pi_calib_done),
        .I5(\init_state_r_reg_n_0_[1] ),
        .O(\init_state_r[4]_i_21_n_0 ));
  LUT6 #(
    .INIT(64'h04FF04FFFFFF04FF)) 
    \init_state_r[4]_i_22 
       (.I0(wrlvl_byte_redo),
        .I1(pi_dqs_found_done_r1_reg_0),
        .I2(wrlvl_done_r1),
        .I3(cnt_cmd_done_r),
        .I4(cnt_init_af_done_r),
        .I5(mem_init_done_r),
        .O(\init_state_r[4]_i_22_n_0 ));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \init_state_r[4]_i_23 
       (.I0(mem_init_done_r),
        .I1(ddr3_lm_done_r_reg_0),
        .I2(wrlvl_byte_redo),
        .I3(\init_state_r[4]_i_10_0 ),
        .I4(\init_state_r[2]_i_38_n_0 ),
        .O(\init_state_r[4]_i_23_n_0 ));
  LUT6 #(
    .INIT(64'h4000000000000000)) 
    \init_state_r[4]_i_24 
       (.I0(ddr3_lm_done_r),
        .I1(prbs_rdlvl_start_reg_2),
        .I2(complex_oclkdelay_calib_done_r1_reg_0),
        .I3(wrlvl_done_r1),
        .I4(pi_dqs_found_done_r1_reg_0),
        .I5(ddr3_lm_done_r_reg_0),
        .O(\init_state_r[4]_i_24_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair447" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \init_state_r[4]_i_25 
       (.I0(Q),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(num_samples_done_r),
        .I3(prbs_rdlvl_start_reg_0),
        .O(\init_state_r[4]_i_25_n_0 ));
  LUT6 #(
    .INIT(64'hFDFDFDFCFDFDFD0C)) 
    \init_state_r[4]_i_26 
       (.I0(\init_state_r[3]_i_22_n_0 ),
        .I1(\init_state_r_reg_n_0_[4] ),
        .I2(\init_state_r[5]_i_13_n_0 ),
        .I3(prbs_rdlvl_start_i_2_n_0),
        .I4(prech_req_posedge_r_reg_0),
        .I5(\one_rank.stg1_wr_done_reg_0 ),
        .O(\init_state_r[4]_i_26_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFF0FBBBB)) 
    \init_state_r[4]_i_27 
       (.I0(wrcal_resume_r),
        .I1(\init_state_r[4]_i_17_0 ),
        .I2(pi_phase_locked_all_r3),
        .I3(pi_phase_locked_all_r4),
        .I4(\init_state_r_reg_n_0_[1] ),
        .I5(Q),
        .O(\init_state_r[4]_i_27_n_0 ));
  LUT6 #(
    .INIT(64'h4051000040515151)) 
    \init_state_r[4]_i_3 
       (.I0(Q),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(\init_state_r[4]_i_10_n_0 ),
        .I3(ddr2_pre_flag_r_reg_n_0),
        .I4(cnt_cmd_done_r),
        .I5(\init_state_r_reg_n_0_[4] ),
        .O(\init_state_r[4]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair529" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \init_state_r[4]_i_4 
       (.I0(\init_state_r_reg_n_0_[2] ),
        .I1(\init_state_r_reg_n_0_[3] ),
        .O(\init_state_r[4]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFEAEEEEEE)) 
    \init_state_r[4]_i_5 
       (.I0(\init_state_r[4]_i_11_n_0 ),
        .I1(\init_state_r[4]_i_12_n_0 ),
        .I2(\init_state_r_reg_n_0_[1] ),
        .I3(cnt_cmd_done_r),
        .I4(\init_state_r[4]_i_13_n_0 ),
        .I5(\init_state_r[4]_i_14_n_0 ),
        .O(\init_state_r[4]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h00000000ABAAABAB)) 
    \init_state_r[4]_i_6 
       (.I0(\init_state_r[4]_i_15_n_0 ),
        .I1(rdlvl_stg1_start_int_i_2_n_0),
        .I2(\init_state_r_reg_n_0_[1] ),
        .I3(\init_state_r[4]_i_16_n_0 ),
        .I4(\init_state_r[5]_i_13_n_0 ),
        .I5(\init_state_r[4]_i_17_n_0 ),
        .O(\init_state_r[4]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hA8A8A888A8A8A8A8)) 
    \init_state_r[4]_i_7 
       (.I0(init_state_r),
        .I1(\init_state_r[4]_i_18_n_0 ),
        .I2(\init_state_r_reg_n_0_[4] ),
        .I3(\init_state_r_reg_n_0_[2] ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ),
        .I5(\init_state_r[5]_i_28_n_0 ),
        .O(\init_state_r[4]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h0000000031332033)) 
    \init_state_r[4]_i_8 
       (.I0(\init_state_r_reg_n_0_[3] ),
        .I1(\init_state_r_reg_n_0_[2] ),
        .I2(wrlvl_done_r1),
        .I3(cnt_cmd_done_r),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address_reg[10]_0 ),
        .I5(\init_state_r[4]_i_19_n_0 ),
        .O(\init_state_r[4]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'h000000000000DD5D)) 
    \init_state_r[4]_i_9 
       (.I0(detect_pi_found_dqs_i_2_n_0),
        .I1(\init_state_r[2]_i_8_n_0 ),
        .I2(rdlvl_stg1_done_r1),
        .I3(complex_sample_cnt_inc_i_2_n_0),
        .I4(\init_state_r[4]_i_20_n_0 ),
        .I5(\init_state_r[4]_i_21_n_0 ),
        .O(\init_state_r[4]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF5554)) 
    \init_state_r[5]_i_1 
       (.I0(\init_state_r[5]_i_2_n_0 ),
        .I1(\init_state_r[5]_i_3_n_0 ),
        .I2(\init_state_r[5]_i_4_n_0 ),
        .I3(\init_state_r[5]_i_5_n_0 ),
        .I4(\init_state_r[5]_i_6_n_0 ),
        .I5(\init_state_r[5]_i_7_n_0 ),
        .O(\init_state_r[5]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFA20000)) 
    \init_state_r[5]_i_10 
       (.I0(\init_state_r_reg_n_0_[5] ),
        .I1(pi_phase_locked_all_r3),
        .I2(pi_phase_locked_all_r4),
        .I3(Q),
        .I4(\init_state_r_reg_n_0_[1] ),
        .O(\init_state_r[5]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFD00)) 
    \init_state_r[5]_i_11 
       (.I0(\wrcal_reads_reg_n_0_[0] ),
        .I1(\init_state_r[5]_i_37_n_0 ),
        .I2(\init_state_r[5]_i_38_n_0 ),
        .I3(\init_state_r[5]_i_39_n_0 ),
        .I4(\init_state_r[5]_i_40_n_0 ),
        .I5(\init_state_r_reg_n_0_[1] ),
        .O(\init_state_r[5]_i_11_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair398" *) 
  LUT5 #(
    .INIT(32'h10115555)) 
    \init_state_r[5]_i_12 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(prech_req_posedge_r_reg_0),
        .I2(complex_oclkdelay_calib_done_r1),
        .I3(complex_oclkdelay_calib_done_r1_reg_0),
        .I4(Q),
        .O(\init_state_r[5]_i_12_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair397" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \init_state_r[5]_i_13 
       (.I0(complex_wait_cnt_reg[0]),
        .I1(complex_wait_cnt_reg[1]),
        .I2(complex_wait_cnt_reg[2]),
        .I3(complex_wait_cnt_reg[3]),
        .O(\init_state_r[5]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFEFFFFFFFFFF)) 
    \init_state_r[5]_i_14 
       (.I0(\stg1_wr_rd_cnt_reg_n_0_[5] ),
        .I1(complex_sample_cnt_inc_i_3_n_0),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[1] ),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[0] ),
        .I4(\stg1_wr_rd_cnt_reg_n_0_[2] ),
        .I5(Q),
        .O(\init_state_r[5]_i_14_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair448" *) 
  LUT4 #(
    .INIT(16'hEFFF)) 
    \init_state_r[5]_i_15 
       (.I0(complex_oclkdelay_calib_done_r1_reg_0),
        .I1(Q),
        .I2(\init_state_r_reg_n_0_[5] ),
        .I3(\init_state_r_reg_n_0_[1] ),
        .O(\init_state_r[5]_i_15_n_0 ));
  LUT6 #(
    .INIT(64'h0004000444440004)) 
    \init_state_r[5]_i_16 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(Q),
        .I2(\init_state_r_reg_n_0_[5] ),
        .I3(\init_state_r[5]_i_13_n_0 ),
        .I4(complex_oclkdelay_calib_done_r1_reg_0),
        .I5(prbs_rdlvl_done_r1),
        .O(\init_state_r[5]_i_16_n_0 ));
  LUT6 #(
    .INIT(64'hCFCCCCCCCECCCECC)) 
    \init_state_r[5]_i_17 
       (.I0(\init_state_r_reg_n_0_[5] ),
        .I1(\init_state_r[5]_i_41_n_0 ),
        .I2(prech_req_posedge_r_reg_0),
        .I3(Q),
        .I4(\one_rank.stg1_wr_done_reg_0 ),
        .I5(\init_state_r[5]_i_13_n_0 ),
        .O(\init_state_r[5]_i_17_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair438" *) 
  LUT5 #(
    .INIT(32'hAA002A02)) 
    \init_state_r[5]_i_18 
       (.I0(\init_state_r_reg_n_0_[4] ),
        .I1(\init_state_r_reg_n_0_[5] ),
        .I2(Q),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(cnt_cmd_done_r),
        .O(\init_state_r[5]_i_18_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair469" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \init_state_r[5]_i_19 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(\init_state_r_reg_n_0_[5] ),
        .O(\init_state_r[5]_i_19_n_0 ));
  LUT6 #(
    .INIT(64'hABAAABABABAAABAA)) 
    \init_state_r[5]_i_2 
       (.I0(complex_act_start_i_2_n_0),
        .I1(\init_state_r[5]_i_8_n_0 ),
        .I2(\init_state_r[5]_i_9_n_0 ),
        .I3(\wrcal_reads[7]_i_4_n_0 ),
        .I4(\init_state_r[5]_i_10_n_0 ),
        .I5(\init_state_r[5]_i_11_n_0 ),
        .O(\init_state_r[5]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000100000000)) 
    \init_state_r[5]_i_20 
       (.I0(complex_num_reads_dec[2]),
        .I1(complex_num_reads_dec[3]),
        .I2(complex_row0_rd_done),
        .I3(\init_state_r[2]_i_21_n_0 ),
        .I4(complex_num_reads_dec[1]),
        .I5(complex_num_reads_dec[0]),
        .O(\init_state_r[5]_i_20_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFAB00)) 
    \init_state_r[5]_i_21 
       (.I0(prbs_rdlvl_done_pulse0),
        .I1(\init_state_r[5]_i_13_n_0 ),
        .I2(\init_state_r_reg_n_0_[5] ),
        .I3(detect_pi_found_dqs_i_2_n_0),
        .I4(\init_state_r[5]_i_42_n_0 ),
        .I5(\init_state_r[4]_i_4_n_0 ),
        .O(\init_state_r[5]_i_21_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FFFFF4FF)) 
    \init_state_r[5]_i_22 
       (.I0(\init_state_r[5]_i_43_n_0 ),
        .I1(\init_state_r[5]_i_44_n_0 ),
        .I2(\init_state_r[5]_i_45_n_0 ),
        .I3(\init_state_r_reg_n_0_[4] ),
        .I4(\init_state_r[5]_i_46_n_0 ),
        .I5(\init_state_r[3]_i_6_n_0 ),
        .O(\init_state_r[5]_i_22_n_0 ));
  LUT6 #(
    .INIT(64'hFFBAAAAABABAAAAA)) 
    \init_state_r[5]_i_23 
       (.I0(\init_state_r[5]_i_47_n_0 ),
        .I1(cnt_cmd_done_r),
        .I2(\init_state_r_reg_n_0_[5] ),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(Q),
        .I5(reset_rd_addr_r1),
        .O(\init_state_r[5]_i_23_n_0 ));
  LUT6 #(
    .INIT(64'hDFDFDF00FFFFFFFF)) 
    \init_state_r[5]_i_24 
       (.I0(\init_state_r[5]_i_48_n_0 ),
        .I1(\init_state_r[5]_i_49_n_0 ),
        .I2(rdlvl_stg1_done_r1),
        .I3(prbs_gen_oclk_clk_en_i_9_n_0),
        .I4(\init_state_r[6]_i_26_n_0 ),
        .I5(detect_pi_found_dqs_i_2_n_0),
        .O(\init_state_r[5]_i_24_n_0 ));
  LUT6 #(
    .INIT(64'hFFBBBFBBFFFFBFFF)) 
    \init_state_r[5]_i_25 
       (.I0(\cnt_init_mr_r[0]_i_2_n_0 ),
        .I1(\init_state_r_reg_n_0_[5] ),
        .I2(Q),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(cnt_cmd_done_r),
        .I5(\init_state_r[6]_i_25_n_0 ),
        .O(\init_state_r[5]_i_25_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF040004F0)) 
    \init_state_r[5]_i_26 
       (.I0(\init_state_r[5]_i_50_n_0 ),
        .I1(\init_state_r_reg_n_0_[5] ),
        .I2(\init_state_r_reg_n_0_[3] ),
        .I3(\init_state_r_reg_n_0_[2] ),
        .I4(\init_state_r[5]_i_43_n_0 ),
        .I5(\init_state_r_reg_n_0_[4] ),
        .O(\init_state_r[5]_i_26_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair411" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \init_state_r[5]_i_27 
       (.I0(Q),
        .I1(prech_req_posedge_r_reg_0),
        .O(\init_state_r[5]_i_27_n_0 ));
  LUT6 #(
    .INIT(64'h40000000FFFFFFFF)) 
    \init_state_r[5]_i_28 
       (.I0(Q),
        .I1(ocal_act_wait_cnt_reg[3]),
        .I2(ocal_act_wait_cnt_reg[2]),
        .I3(ocal_act_wait_cnt_reg[1]),
        .I4(ocal_act_wait_cnt_reg[0]),
        .I5(\init_state_r_reg_n_0_[1] ),
        .O(\init_state_r[5]_i_28_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair421" *) 
  LUT4 #(
    .INIT(16'hBFFF)) 
    \init_state_r[5]_i_29 
       (.I0(\init_state_r_reg_n_0_[2] ),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(Q),
        .I3(complex_pi_incdec_done),
        .O(\init_state_r[5]_i_29_n_0 ));
  LUT6 #(
    .INIT(64'h0400444455555555)) 
    \init_state_r[5]_i_3 
       (.I0(rdlvl_stg1_start_int_i_2_n_0),
        .I1(\init_state_r[5]_i_12_n_0 ),
        .I2(\init_state_r[5]_i_13_n_0 ),
        .I3(\init_state_r_reg_n_0_[5] ),
        .I4(\init_state_r[5]_i_14_n_0 ),
        .I5(\init_state_r[5]_i_15_n_0 ),
        .O(\init_state_r[5]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair407" *) 
  LUT5 #(
    .INIT(32'h00000020)) 
    \init_state_r[5]_i_30 
       (.I0(Q),
        .I1(wrcal_wr_cnt_reg[1]),
        .I2(wrcal_wr_cnt_reg[0]),
        .I3(wrcal_wr_cnt_reg[2]),
        .I4(wrcal_wr_cnt_reg[3]),
        .O(\init_state_r[5]_i_30_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair463" *) 
  LUT4 #(
    .INIT(16'hAABA)) 
    \init_state_r[5]_i_31 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(wrcal_prech_req),
        .I2(cnt_cmd_done_r),
        .I3(Q),
        .O(\init_state_r[5]_i_31_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair411" *) 
  LUT5 #(
    .INIT(32'hFFFF11F1)) 
    \init_state_r[5]_i_32 
       (.I0(prech_req_posedge_r_reg_0),
        .I1(ddr3_lm_done_r_reg_0),
        .I2(cnt_cmd_done_r),
        .I3(wrcal_prech_req),
        .I4(Q),
        .O(\init_state_r[5]_i_32_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair410" *) 
  LUT5 #(
    .INIT(32'h00103010)) 
    \init_state_r[5]_i_33 
       (.I0(cnt_cmd_done_r),
        .I1(\init_state_r_reg_n_0_[5] ),
        .I2(\init_state_r_reg_n_0_[1] ),
        .I3(Q),
        .I4(p_17_in),
        .O(\init_state_r[5]_i_33_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair410" *) 
  LUT3 #(
    .INIT(8'hF8)) 
    \init_state_r[5]_i_34 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(cnt_cmd_done_r),
        .I2(Q),
        .O(\init_state_r[5]_i_34_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair406" *) 
  LUT5 #(
    .INIT(32'hAAAAAA8A)) 
    \init_state_r[5]_i_35 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(oclk_wr_cnt_reg[1]),
        .I2(oclk_wr_cnt_reg[0]),
        .I3(oclk_wr_cnt_reg[2]),
        .I4(oclk_wr_cnt_reg[3]),
        .O(\init_state_r[5]_i_35_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAFFFEAAAAAAAA)) 
    \init_state_r[5]_i_36 
       (.I0(\init_state_r_reg_n_0_[4] ),
        .I1(cnt_cmd_done_r),
        .I2(Q),
        .I3(\init_state_r_reg_n_0_[5] ),
        .I4(\init_state_r_reg_n_0_[2] ),
        .I5(\init_state_r_reg_n_0_[3] ),
        .O(\init_state_r[5]_i_36_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair449" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    \init_state_r[5]_i_37 
       (.I0(\wrcal_reads_reg_n_0_[5] ),
        .I1(\wrcal_reads_reg_n_0_[6] ),
        .I2(\wrcal_reads_reg_n_0_[1] ),
        .I3(\wrcal_reads_reg_n_0_[3] ),
        .O(\init_state_r[5]_i_37_n_0 ));
  LUT3 #(
    .INIT(8'hFE)) 
    \init_state_r[5]_i_38 
       (.I0(\wrcal_reads_reg_n_0_[4] ),
        .I1(\wrcal_reads_reg_n_0_[2] ),
        .I2(\wrcal_reads_reg_n_0_[7] ),
        .O(\init_state_r[5]_i_38_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair483" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \init_state_r[5]_i_39 
       (.I0(Q),
        .I1(\init_state_r_reg_n_0_[5] ),
        .O(\init_state_r[5]_i_39_n_0 ));
  LUT6 #(
    .INIT(64'h0000440F0F0F4F0F)) 
    \init_state_r[5]_i_4 
       (.I0(\init_state_r[5]_i_16_n_0 ),
        .I1(\init_state_r[5]_i_17_n_0 ),
        .I2(\init_state_r[5]_i_18_n_0 ),
        .I3(\init_state_r_reg_n_0_[2] ),
        .I4(\init_state_r_reg_n_0_[3] ),
        .I5(\init_state_r_reg_n_0_[4] ),
        .O(\init_state_r[5]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h000000000000FFFD)) 
    \init_state_r[5]_i_40 
       (.I0(\init_state_r_reg_n_0_[5] ),
        .I1(wrlvl_byte_redo),
        .I2(prech_req_posedge_r_reg_0),
        .I3(ddr3_lm_done_r_reg_0),
        .I4(wrcal_resume_r),
        .I5(Q),
        .O(\init_state_r[5]_i_40_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair447" *) 
  LUT4 #(
    .INIT(16'h15FF)) 
    \init_state_r[5]_i_41 
       (.I0(Q),
        .I1(prbs_rdlvl_start_reg_0),
        .I2(num_samples_done_r),
        .I3(\init_state_r_reg_n_0_[1] ),
        .O(\init_state_r[5]_i_41_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair400" *) 
  LUT4 #(
    .INIT(16'h00F2)) 
    \init_state_r[5]_i_42 
       (.I0(complex_oclkdelay_calib_done_r1_reg_0),
        .I1(prbs_rdlvl_done_r1),
        .I2(prech_req_posedge_r_reg_0),
        .I3(\init_state_r_reg_n_0_[1] ),
        .O(\init_state_r[5]_i_42_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair483" *) 
  LUT3 #(
    .INIT(8'hBF)) 
    \init_state_r[5]_i_43 
       (.I0(cnt_cmd_done_r),
        .I1(\init_state_r_reg_n_0_[5] ),
        .I2(Q),
        .O(\init_state_r[5]_i_43_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair412" *) 
  LUT3 #(
    .INIT(8'h04)) 
    \init_state_r[5]_i_44 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(\init_state_r_reg_n_0_[2] ),
        .I2(\init_state_r_reg_n_0_[3] ),
        .O(\init_state_r[5]_i_44_n_0 ));
  LUT6 #(
    .INIT(64'h0000020002000200)) 
    \init_state_r[5]_i_45 
       (.I0(\init_state_r_reg_n_0_[5] ),
        .I1(Q),
        .I2(cnt_cmd_done_r),
        .I3(\init_state_r_reg_n_0_[3] ),
        .I4(\init_state_r_reg_n_0_[1] ),
        .I5(\init_state_r_reg_n_0_[2] ),
        .O(\init_state_r[5]_i_45_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair442" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \init_state_r[5]_i_46 
       (.I0(\init_state_r_reg_n_0_[2] ),
        .I1(Q),
        .I2(\init_state_r_reg_n_0_[3] ),
        .I3(\init_state_r_reg_n_0_[1] ),
        .O(\init_state_r[5]_i_46_n_0 ));
  LUT6 #(
    .INIT(64'h0008000808080008)) 
    \init_state_r[5]_i_47 
       (.I0(cnt_cmd_done_r),
        .I1(Q),
        .I2(\init_state_r_reg_n_0_[1] ),
        .I3(pi_calib_done),
        .I4(pi_dqs_found_done_r1_reg_0),
        .I5(ddr3_lm_done_r_reg_0),
        .O(\init_state_r[5]_i_47_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \init_state_r[5]_i_48 
       (.I0(\stg1_wr_rd_cnt_reg_n_0_[5] ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[3] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[4] ),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[6] ),
        .I4(\stg1_wr_rd_cnt_reg_n_0_[8] ),
        .I5(\stg1_wr_rd_cnt_reg_n_0_[7] ),
        .O(\init_state_r[5]_i_48_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair475" *) 
  LUT3 #(
    .INIT(8'hFB)) 
    \init_state_r[5]_i_49 
       (.I0(\stg1_wr_rd_cnt_reg_n_0_[1] ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[0] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[2] ),
        .O(\init_state_r[5]_i_49_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FFEFEFEF)) 
    \init_state_r[5]_i_5 
       (.I0(\init_state_r[5]_i_19_n_0 ),
        .I1(\init_state_r[5]_i_20_n_0 ),
        .I2(complex_sample_cnt_inc_i_2_n_0),
        .I3(Q),
        .I4(\init_state_r[5]_i_13_n_0 ),
        .I5(\init_state_r[5]_i_21_n_0 ),
        .O(\init_state_r[5]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair445" *) 
  LUT4 #(
    .INIT(16'hAFCF)) 
    \init_state_r[5]_i_50 
       (.I0(wrlvl_rank_done_r7),
        .I1(cnt_dllk_zqinit_done_r),
        .I2(Q),
        .I3(\init_state_r_reg_n_0_[1] ),
        .O(\init_state_r[5]_i_50_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAA2022AAAA)) 
    \init_state_r[5]_i_6 
       (.I0(\init_state_r[5]_i_22_n_0 ),
        .I1(rdlvl_stg1_start_int_i_2_n_0),
        .I2(\init_state_r[5]_i_23_n_0 ),
        .I3(\init_state_r[5]_i_24_n_0 ),
        .I4(\init_state_r[5]_i_25_n_0 ),
        .I5(\init_state_r[5]_i_26_n_0 ),
        .O(\init_state_r[5]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h88808888AAAAAAAA)) 
    \init_state_r[5]_i_7 
       (.I0(init_state_r),
        .I1(\init_state_r_reg_n_0_[5] ),
        .I2(\init_state_r_reg_n_0_[2] ),
        .I3(\init_state_r[5]_i_27_n_0 ),
        .I4(\init_state_r[5]_i_28_n_0 ),
        .I5(\init_state_r[5]_i_29_n_0 ),
        .O(\init_state_r[5]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h000000000000FEEE)) 
    \init_state_r[5]_i_8 
       (.I0(\init_state_r[5]_i_30_n_0 ),
        .I1(\init_state_r[5]_i_31_n_0 ),
        .I2(\init_state_r[5]_i_32_n_0 ),
        .I3(\init_state_r_reg_n_0_[5] ),
        .I4(\init_state_r[5]_i_33_n_0 ),
        .I5(\cnt_init_mr_r[0]_i_2_n_0 ),
        .O(\init_state_r[5]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF40444444)) 
    \init_state_r[5]_i_9 
       (.I0(rdlvl_stg1_start_int_i_2_n_0),
        .I1(\init_state_r[5]_i_34_n_0 ),
        .I2(\init_state_r_reg_n_0_[5] ),
        .I3(Q),
        .I4(\init_state_r[5]_i_35_n_0 ),
        .I5(\init_state_r[5]_i_36_n_0 ),
        .O(\init_state_r[5]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF5455)) 
    \init_state_r[6]_i_1 
       (.I0(\init_state_r[6]_i_2_n_0 ),
        .I1(\init_state_r[6]_i_3_n_0 ),
        .I2(\init_state_r[6]_i_4_n_0 ),
        .I3(\init_state_r[6]_i_5_n_0 ),
        .I4(\init_state_r[6]_i_6_n_0 ),
        .I5(\init_state_r[6]_i_7_n_0 ),
        .O(\init_state_r[6]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0040004000000040)) 
    \init_state_r[6]_i_10 
       (.I0(\init_state_r[5]_i_13_n_0 ),
        .I1(init_state_r),
        .I2(\init_state_r_reg_n_0_[1] ),
        .I3(Q),
        .I4(complex_oclkdelay_calib_done_r1_reg_0),
        .I5(prbs_rdlvl_done_r1),
        .O(\init_state_r[6]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF0001)) 
    \init_state_r[6]_i_11 
       (.I0(\init_state_r[6]_i_22_n_0 ),
        .I1(complex_row0_rd_done),
        .I2(complex_num_reads_dec[3]),
        .I3(complex_num_reads_dec[2]),
        .I4(prbs_rdlvl_done_pulse0),
        .I5(prech_req_posedge_r_reg_0),
        .O(\init_state_r[6]_i_11_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair429" *) 
  LUT3 #(
    .INIT(8'hAB)) 
    \init_state_r[6]_i_12 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(init_state_r),
        .I2(Q),
        .O(\init_state_r[6]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'h80000000AAAAAAAA)) 
    \init_state_r[6]_i_13 
       (.I0(Q),
        .I1(complex_wait_cnt_reg[0]),
        .I2(complex_wait_cnt_reg[1]),
        .I3(complex_wait_cnt_reg[2]),
        .I4(complex_wait_cnt_reg[3]),
        .I5(init_state_r),
        .O(\init_state_r[6]_i_13_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair437" *) 
  LUT5 #(
    .INIT(32'h2AAAAAAA)) 
    \init_state_r[6]_i_14 
       (.I0(init_state_r),
        .I1(complex_wait_cnt_reg[3]),
        .I2(complex_wait_cnt_reg[2]),
        .I3(complex_wait_cnt_reg[1]),
        .I4(complex_wait_cnt_reg[0]),
        .O(\init_state_r[6]_i_14_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair387" *) 
  LUT4 #(
    .INIT(16'hAA08)) 
    \init_state_r[6]_i_15 
       (.I0(Q),
        .I1(complex_oclkdelay_calib_done_r1_reg_0),
        .I2(complex_oclkdelay_calib_done_r1),
        .I3(prech_req_posedge_r_reg_0),
        .O(\init_state_r[6]_i_15_n_0 ));
  LUT6 #(
    .INIT(64'h77777777FF7F7777)) 
    \init_state_r[6]_i_16 
       (.I0(\init_state_r_reg_n_0_[2] ),
        .I1(\init_state_r_reg_n_0_[3] ),
        .I2(init_state_r),
        .I3(complex_oclkdelay_calib_done_r1_reg_0),
        .I4(\init_state_r_reg_n_0_[1] ),
        .I5(Q),
        .O(\init_state_r[6]_i_16_n_0 ));
  LUT6 #(
    .INIT(64'hFF1F1F1F11111111)) 
    \init_state_r[6]_i_17 
       (.I0(\init_state_r[6]_i_9_n_0 ),
        .I1(prbs_rdlvl_start_i_2_n_0),
        .I2(\init_state_r[6]_i_23_n_0 ),
        .I3(\init_state_r[6]_i_24_n_0 ),
        .I4(\init_state_r[6]_i_25_n_0 ),
        .I5(init_state_r),
        .O(\init_state_r[6]_i_17_n_0 ));
  LUT6 #(
    .INIT(64'h00000000D8000000)) 
    \init_state_r[6]_i_18 
       (.I0(cnt_cmd_done_r),
        .I1(rdlvl_stg1_done_r1),
        .I2(init_state_r),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(Q),
        .I5(reset_rd_addr_r1),
        .O(\init_state_r[6]_i_18_n_0 ));
  LUT6 #(
    .INIT(64'h5555555555575555)) 
    \init_state_r[6]_i_19 
       (.I0(init_state_r),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[5] ),
        .I2(complex_sample_cnt_inc_i_3_n_0),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[1] ),
        .I4(\stg1_wr_rd_cnt_reg_n_0_[0] ),
        .I5(\stg1_wr_rd_cnt_reg_n_0_[2] ),
        .O(\init_state_r[6]_i_19_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair485" *) 
  LUT3 #(
    .INIT(8'hDF)) 
    \init_state_r[6]_i_2 
       (.I0(\init_state_r_reg_n_0_[5] ),
        .I1(init_state_r),
        .I2(\init_state_r_reg_n_0_[4] ),
        .O(\init_state_r[6]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hBBBBBBBBBBBBBBBF)) 
    \init_state_r[6]_i_20 
       (.I0(Q),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(\init_state_r[6]_i_26_n_0 ),
        .I3(complex_num_writes_dec[2]),
        .I4(complex_num_writes_dec[4]),
        .I5(complex_num_writes_dec[3]),
        .O(\init_state_r[6]_i_20_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair400" *) 
  LUT5 #(
    .INIT(32'hAAFF0CFF)) 
    \init_state_r[6]_i_21 
       (.I0(prech_req_posedge_r_reg_0),
        .I1(complex_oclkdelay_calib_done_r1_reg_0),
        .I2(prbs_rdlvl_done_r1),
        .I3(Q),
        .I4(\init_state_r_reg_n_0_[1] ),
        .O(\init_state_r[6]_i_21_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair456" *) 
  LUT4 #(
    .INIT(16'hFFFD)) 
    \init_state_r[6]_i_22 
       (.I0(complex_num_reads_dec[0]),
        .I1(complex_num_reads_dec[1]),
        .I2(complex_oclkdelay_calib_done_r1_reg_0),
        .I3(Q),
        .O(\init_state_r[6]_i_22_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair405" *) 
  LUT5 #(
    .INIT(32'hFFFFD5FF)) 
    \init_state_r[6]_i_23 
       (.I0(\init_state_r_reg_n_0_[3] ),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(\init_state_r_reg_n_0_[2] ),
        .I3(Q),
        .I4(cnt_cmd_done_r),
        .O(\init_state_r[6]_i_23_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair401" *) 
  LUT3 #(
    .INIT(8'h01)) 
    \init_state_r[6]_i_24 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(\init_state_r_reg_n_0_[2] ),
        .I2(\init_state_r_reg_n_0_[3] ),
        .O(\init_state_r[6]_i_24_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair399" *) 
  LUT5 #(
    .INIT(32'h007FFF7F)) 
    \init_state_r[6]_i_25 
       (.I0(ck_addr_cmd_delay_done),
        .I1(cnt_pwron_cke_done_r),
        .I2(\calib_seq_reg[0]_0 ),
        .I3(Q),
        .I4(cnt_txpr_done_r),
        .O(\init_state_r[6]_i_25_n_0 ));
  LUT5 #(
    .INIT(32'hFFDFFFFF)) 
    \init_state_r[6]_i_26 
       (.I0(complex_num_writes_dec[0]),
        .I1(complex_num_writes_dec[1]),
        .I2(complex_oclkdelay_calib_done_r1_reg_0),
        .I3(complex_row0_wr_done),
        .I4(rdlvl_stg1_done_r1),
        .O(\init_state_r[6]_i_26_n_0 ));
  LUT6 #(
    .INIT(64'h1F1F1F1FFF1F1FFF)) 
    \init_state_r[6]_i_3 
       (.I0(\init_state_r[6]_i_8_n_0 ),
        .I1(\wrcal_reads[7]_i_4_n_0 ),
        .I2(\init_state_r_reg_n_0_[4] ),
        .I3(Q),
        .I4(\init_state_r_reg_n_0_[1] ),
        .I5(\init_state_r[6]_i_9_n_0 ),
        .O(\init_state_r[6]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h4444444544444444)) 
    \init_state_r[6]_i_4 
       (.I0(\init_state_r[4]_i_4_n_0 ),
        .I1(\init_state_r[6]_i_10_n_0 ),
        .I2(\init_state_r[6]_i_11_n_0 ),
        .I3(\init_state_r[6]_i_12_n_0 ),
        .I4(\init_state_r[6]_i_13_n_0 ),
        .I5(complex_sample_cnt_inc_i_2_n_0),
        .O(\init_state_r[6]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF0000FF75)) 
    \init_state_r[6]_i_5 
       (.I0(\init_state_r[6]_i_14_n_0 ),
        .I1(complex_sample_cnt_inc_i_2_n_0),
        .I2(Q),
        .I3(\init_state_r[6]_i_15_n_0 ),
        .I4(\init_state_r_reg_n_0_[1] ),
        .I5(\init_state_r[6]_i_16_n_0 ),
        .O(\init_state_r[6]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h8A888A888A888A8A)) 
    \init_state_r[6]_i_6 
       (.I0(\cnt_init_mr_r[0]_i_3_n_0 ),
        .I1(\init_state_r[6]_i_17_n_0 ),
        .I2(rdlvl_stg1_start_int_i_2_n_0),
        .I3(\init_state_r[6]_i_18_n_0 ),
        .I4(\init_state_r[6]_i_19_n_0 ),
        .I5(\init_state_r[6]_i_20_n_0 ),
        .O(\init_state_r[6]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h88AAA8AA8AAAAAAA)) 
    \init_state_r[6]_i_7 
       (.I0(init_state_r),
        .I1(\init_state_r_reg_n_0_[2] ),
        .I2(\init_state_r_reg_n_0_[1] ),
        .I3(Q),
        .I4(complex_pi_incdec_done),
        .I5(prech_req_posedge_r_reg_0),
        .O(\init_state_r[6]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h00FDFDFDFDFDFDFD)) 
    \init_state_r[6]_i_8 
       (.I0(init_state_r),
        .I1(\init_state_r[5]_i_13_n_0 ),
        .I2(\init_state_r[6]_i_21_n_0 ),
        .I3(prbs_rdlvl_start_reg_0),
        .I4(num_samples_done_r),
        .I5(detect_pi_found_dqs_i_2_n_0),
        .O(\init_state_r[6]_i_8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair446" *) 
  LUT4 #(
    .INIT(16'hFEFF)) 
    \init_state_r[6]_i_9 
       (.I0(\init_state_r_reg_n_0_[2] ),
        .I1(\init_state_r_reg_n_0_[3] ),
        .I2(cnt_cmd_done_r),
        .I3(init_state_r),
        .O(\init_state_r[6]_i_9_n_0 ));
  FDRE \init_state_r_reg[0] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\init_state_r[0]_i_1_n_0 ),
        .Q(Q),
        .R(\victim_sel_reg[0]_0 ));
  FDRE \init_state_r_reg[1] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\init_state_r[1]_i_1_n_0 ),
        .Q(\init_state_r_reg_n_0_[1] ),
        .R(\victim_sel_reg[0]_0 ));
  FDRE \init_state_r_reg[2] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\init_state_r[2]_i_1_n_0 ),
        .Q(\init_state_r_reg_n_0_[2] ),
        .R(\victim_sel_reg[0]_0 ));
  FDRE \init_state_r_reg[3] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\init_state_r[3]_i_1_n_0 ),
        .Q(\init_state_r_reg_n_0_[3] ),
        .R(\victim_sel_reg[0]_0 ));
  FDRE \init_state_r_reg[4] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\init_state_r[4]_i_1_n_0 ),
        .Q(\init_state_r_reg_n_0_[4] ),
        .R(\victim_sel_reg[0]_0 ));
  FDRE \init_state_r_reg[5] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\init_state_r[5]_i_1_n_0 ),
        .Q(\init_state_r_reg_n_0_[5] ),
        .R(\victim_sel_reg[0]_0 ));
  FDRE \init_state_r_reg[6] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\init_state_r[6]_i_1_n_0 ),
        .Q(init_state_r),
        .R(\victim_sel_reg[0]_0 ));
  LUT5 #(
    .INIT(32'hFFFF4000)) 
    mem_init_done_r_i_1
       (.I0(cnt_dllk_zqinit_done_r),
        .I1(cnt_dllk_zqinit_r_reg[7]),
        .I2(mem_init_done_r_i_2_n_0),
        .I3(cnt_dllk_zqinit_r_reg[6]),
        .I4(mem_init_done_r),
        .O(mem_init_done_r_i_1_n_0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    mem_init_done_r_i_2
       (.I0(cnt_dllk_zqinit_r_reg[5]),
        .I1(cnt_dllk_zqinit_r_reg[3]),
        .I2(cnt_dllk_zqinit_r_reg[1]),
        .I3(cnt_dllk_zqinit_r_reg[0]),
        .I4(cnt_dllk_zqinit_r_reg[2]),
        .I5(cnt_dllk_zqinit_r_reg[4]),
        .O(mem_init_done_r_i_2_n_0));
  FDRE mem_init_done_r_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(mem_init_done_r_i_1_n_0),
        .Q(mem_init_done_r),
        .R(\victim_sel_reg[0]_0 ));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_12_17_i_1__0
       (.I0(mem_reg_0_15_78_79[320]),
        .I1(phy_wrdata[376]),
        .I2(mem_reg_0_15_18_23_0),
        .O(\write_buffer.wr_buf_out_data_reg[455]_0 [5]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_12_17_i_1__1
       (.I0(mem_reg_0_15_78_79[352]),
        .I1(phy_wrdata[376]),
        .I2(mem_reg_0_15_36_41_0),
        .O(\write_buffer.wr_buf_out_data_reg[487]_0 [5]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_12_17_i_1__2
       (.I0(mc_odt),
        .I1(phy_ctl_wr_i1_reg),
        .I2(calib_odt),
        .O(\cmd_pipe_plus.mc_cke_reg[3]_0 [0]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_12_17_i_2
       (.I0(mem_reg_0_15_78_79[256]),
        .I1(phy_wrdata[312]),
        .I2(mem_reg_0_15_18_23),
        .O(\write_buffer.wr_buf_out_data_reg[455]_0 [4]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_12_17_i_2__0
       (.I0(mem_reg_0_15_78_79[288]),
        .I1(phy_wrdata[312]),
        .I2(mem_reg_0_15_18_23_0),
        .O(\write_buffer.wr_buf_out_data_reg[487]_0 [4]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_12_17_i_3
       (.I0(mem_reg_0_15_78_79[448]),
        .I1(phy_wrdata[504]),
        .I2(mem_reg_0_15_54_59_0),
        .O(\write_buffer.wr_buf_out_data_reg[455]_0 [7]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_12_17_i_3__0
       (.I0(mem_reg_0_15_78_79[480]),
        .I1(phy_wrdata[504]),
        .I2(mem_reg_0_15_78_79_0),
        .O(\write_buffer.wr_buf_out_data_reg[487]_0 [7]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_12_17_i_4
       (.I0(mem_reg_0_15_78_79[384]),
        .I1(phy_wrdata[440]),
        .I2(mem_reg_0_15_36_41_1),
        .O(\write_buffer.wr_buf_out_data_reg[455]_0 [6]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_12_17_i_4__0
       (.I0(mem_reg_0_15_78_79[416]),
        .I1(phy_wrdata[440]),
        .I2(mem_reg_0_15_36_41_1),
        .O(\write_buffer.wr_buf_out_data_reg[487]_0 [6]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_12_17_i_5
       (.I0(mem_reg_0_15_78_79[65]),
        .I1(phy_wrdata[121]),
        .I2(mem_reg_0_15_48_53),
        .O(\write_buffer.wr_buf_out_data_reg[455]_0 [9]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_12_17_i_5__0
       (.I0(mem_reg_0_15_78_79[72]),
        .I1(phy_wrdata[120]),
        .I2(mem_reg_0_15_48_53),
        .O(\write_buffer.wr_buf_out_data_reg[463]_0 [1]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_12_17_i_5__1
       (.I0(mem_reg_0_15_78_79[80]),
        .I1(phy_wrdata[120]),
        .I2(mem_reg_0_15_54_59),
        .O(\write_buffer.wr_buf_out_data_reg[471]_0 [1]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_12_17_i_5__2
       (.I0(mem_reg_0_15_78_79[88]),
        .I1(phy_wrdata[120]),
        .I2(mem_reg_0_15_54_59),
        .O(\write_buffer.wr_buf_out_data_reg[479]_0 [1]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_12_17_i_5__3
       (.I0(mem_reg_0_15_78_79[97]),
        .I1(phy_wrdata[121]),
        .I2(mem_reg_0_15_54_59),
        .O(\write_buffer.wr_buf_out_data_reg[487]_0 [9]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_12_17_i_5__4
       (.I0(mem_reg_0_15_78_79[104]),
        .I1(phy_wrdata[120]),
        .I2(mem_reg_0_15_54_59),
        .O(\write_buffer.wr_buf_out_data_reg[495]_0 [1]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_12_17_i_5__5
       (.I0(mem_reg_0_15_78_79[112]),
        .I1(phy_wrdata[120]),
        .I2(mem_reg_0_15_54_59),
        .O(\write_buffer.wr_buf_out_data_reg[503]_0 [1]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_12_17_i_5__6
       (.I0(mem_reg_0_15_78_79[120]),
        .I1(phy_wrdata[120]),
        .I2(mem_reg_0_15_54_59),
        .O(\write_buffer.wr_buf_out_data_reg[511]_0 [1]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_12_17_i_6
       (.I0(mem_reg_0_15_78_79[1]),
        .I1(phy_wrdata[57]),
        .I2(mem_reg_0_15_36_41),
        .O(\write_buffer.wr_buf_out_data_reg[455]_0 [8]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_12_17_i_6__0
       (.I0(mem_reg_0_15_78_79[8]),
        .I1(phy_wrdata[56]),
        .I2(mem_reg_0_15_36_41),
        .O(\write_buffer.wr_buf_out_data_reg[463]_0 [0]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_12_17_i_6__1
       (.I0(mem_reg_0_15_78_79[16]),
        .I1(phy_wrdata[56]),
        .I2(mem_reg_0_15_36_41),
        .O(\write_buffer.wr_buf_out_data_reg[471]_0 [0]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_12_17_i_6__2
       (.I0(mem_reg_0_15_78_79[24]),
        .I1(phy_wrdata[56]),
        .I2(mem_reg_0_15_36_41),
        .O(\write_buffer.wr_buf_out_data_reg[479]_0 [0]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_12_17_i_6__3
       (.I0(mem_reg_0_15_78_79[33]),
        .I1(phy_wrdata[57]),
        .I2(mem_reg_0_15_48_53),
        .O(\write_buffer.wr_buf_out_data_reg[487]_0 [8]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_12_17_i_6__4
       (.I0(mem_reg_0_15_78_79[40]),
        .I1(phy_wrdata[56]),
        .I2(mem_reg_0_15_48_53),
        .O(\write_buffer.wr_buf_out_data_reg[495]_0 [0]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_12_17_i_6__5
       (.I0(mem_reg_0_15_78_79[48]),
        .I1(phy_wrdata[56]),
        .I2(mem_reg_0_15_48_53),
        .O(\write_buffer.wr_buf_out_data_reg[503]_0 [0]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_12_17_i_6__6
       (.I0(mem_reg_0_15_78_79[56]),
        .I1(phy_wrdata[56]),
        .I2(mem_reg_0_15_48_53),
        .O(\write_buffer.wr_buf_out_data_reg[511]_0 [0]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_18_23_i_1
       (.I0(mem_reg_0_15_78_79[193]),
        .I1(phy_wrdata[249]),
        .I2(mem_reg_0_15_72_77),
        .O(\write_buffer.wr_buf_out_data_reg[455]_0 [11]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_18_23_i_1__0
       (.I0(mem_reg_0_15_78_79[200]),
        .I1(phy_wrdata[248]),
        .I2(mem_reg_0_15_72_77),
        .O(\write_buffer.wr_buf_out_data_reg[463]_0 [3]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_18_23_i_1__1
       (.I0(mem_reg_0_15_78_79[208]),
        .I1(phy_wrdata[248]),
        .I2(mem_reg_0_15_72_77),
        .O(\write_buffer.wr_buf_out_data_reg[471]_0 [3]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_18_23_i_1__2
       (.I0(mem_reg_0_15_78_79[216]),
        .I1(phy_wrdata[248]),
        .I2(mem_reg_0_15_72_77),
        .O(\write_buffer.wr_buf_out_data_reg[479]_0 [3]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_18_23_i_1__3
       (.I0(mem_reg_0_15_78_79[225]),
        .I1(phy_wrdata[249]),
        .I2(mem_reg_0_15_18_23),
        .O(\write_buffer.wr_buf_out_data_reg[487]_0 [11]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_18_23_i_1__4
       (.I0(mem_reg_0_15_78_79[232]),
        .I1(phy_wrdata[248]),
        .I2(mem_reg_0_15_18_23),
        .O(\write_buffer.wr_buf_out_data_reg[495]_0 [3]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_18_23_i_1__5
       (.I0(mem_reg_0_15_78_79[240]),
        .I1(phy_wrdata[248]),
        .I2(mem_reg_0_15_18_23),
        .O(\write_buffer.wr_buf_out_data_reg[503]_0 [3]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_18_23_i_1__6
       (.I0(mem_reg_0_15_78_79[248]),
        .I1(phy_wrdata[248]),
        .I2(mem_reg_0_15_18_23),
        .O(\write_buffer.wr_buf_out_data_reg[511]_0 [3]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_18_23_i_2
       (.I0(mem_reg_0_15_78_79[129]),
        .I1(phy_wrdata[185]),
        .I2(mem_reg_0_15_66_71),
        .O(\write_buffer.wr_buf_out_data_reg[455]_0 [10]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_18_23_i_2__0
       (.I0(mem_reg_0_15_78_79[136]),
        .I1(phy_wrdata[184]),
        .I2(mem_reg_0_15_66_71),
        .O(\write_buffer.wr_buf_out_data_reg[463]_0 [2]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_18_23_i_2__1
       (.I0(mem_reg_0_15_78_79[144]),
        .I1(phy_wrdata[184]),
        .I2(mem_reg_0_15_66_71),
        .O(\write_buffer.wr_buf_out_data_reg[471]_0 [2]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_18_23_i_2__2
       (.I0(mem_reg_0_15_78_79[152]),
        .I1(phy_wrdata[184]),
        .I2(mem_reg_0_15_66_71),
        .O(\write_buffer.wr_buf_out_data_reg[479]_0 [2]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_18_23_i_2__3
       (.I0(mem_reg_0_15_78_79[161]),
        .I1(phy_wrdata[185]),
        .I2(mem_reg_0_15_66_71),
        .O(\write_buffer.wr_buf_out_data_reg[487]_0 [10]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_18_23_i_2__4
       (.I0(mem_reg_0_15_78_79[168]),
        .I1(phy_wrdata[184]),
        .I2(mem_reg_0_15_66_71),
        .O(\write_buffer.wr_buf_out_data_reg[495]_0 [2]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_18_23_i_2__5
       (.I0(mem_reg_0_15_78_79[176]),
        .I1(phy_wrdata[184]),
        .I2(mem_reg_0_15_72_77),
        .O(\write_buffer.wr_buf_out_data_reg[503]_0 [2]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_18_23_i_2__6
       (.I0(mem_reg_0_15_78_79[184]),
        .I1(phy_wrdata[184]),
        .I2(mem_reg_0_15_72_77),
        .O(\write_buffer.wr_buf_out_data_reg[511]_0 [2]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_18_23_i_3
       (.I0(mem_reg_0_15_78_79[321]),
        .I1(phy_wrdata[377]),
        .I2(mem_reg_0_15_18_23_0),
        .O(\write_buffer.wr_buf_out_data_reg[455]_0 [13]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_18_23_i_3__0
       (.I0(mem_reg_0_15_78_79[328]),
        .I1(phy_wrdata[376]),
        .I2(mem_reg_0_15_36_41_0),
        .O(\write_buffer.wr_buf_out_data_reg[463]_0 [5]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_18_23_i_3__1
       (.I0(mem_reg_0_15_78_79[336]),
        .I1(phy_wrdata[376]),
        .I2(mem_reg_0_15_36_41_0),
        .O(\write_buffer.wr_buf_out_data_reg[471]_0 [5]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_18_23_i_3__2
       (.I0(mem_reg_0_15_78_79[344]),
        .I1(phy_wrdata[376]),
        .I2(mem_reg_0_15_36_41_0),
        .O(\write_buffer.wr_buf_out_data_reg[479]_0 [5]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_18_23_i_3__3
       (.I0(mem_reg_0_15_78_79[353]),
        .I1(phy_wrdata[377]),
        .I2(mem_reg_0_15_36_41_0),
        .O(\write_buffer.wr_buf_out_data_reg[487]_0 [13]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_18_23_i_3__4
       (.I0(mem_reg_0_15_78_79[360]),
        .I1(phy_wrdata[376]),
        .I2(mem_reg_0_15_36_41_0),
        .O(\write_buffer.wr_buf_out_data_reg[495]_0 [5]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_18_23_i_3__5
       (.I0(mem_reg_0_15_78_79[368]),
        .I1(phy_wrdata[376]),
        .I2(mem_reg_0_15_36_41_0),
        .O(\write_buffer.wr_buf_out_data_reg[503]_0 [5]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_18_23_i_3__6
       (.I0(mem_reg_0_15_78_79[376]),
        .I1(phy_wrdata[376]),
        .I2(mem_reg_0_15_36_41_1),
        .O(\write_buffer.wr_buf_out_data_reg[511]_0 [5]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_18_23_i_4
       (.I0(mem_reg_0_15_78_79[257]),
        .I1(phy_wrdata[313]),
        .I2(mem_reg_0_15_18_23),
        .O(\write_buffer.wr_buf_out_data_reg[455]_0 [12]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_18_23_i_4__0
       (.I0(mem_reg_0_15_78_79[264]),
        .I1(phy_wrdata[312]),
        .I2(mem_reg_0_15_18_23),
        .O(\write_buffer.wr_buf_out_data_reg[463]_0 [4]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_18_23_i_4__1
       (.I0(mem_reg_0_15_78_79[272]),
        .I1(phy_wrdata[312]),
        .I2(mem_reg_0_15_18_23),
        .O(\write_buffer.wr_buf_out_data_reg[471]_0 [4]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_18_23_i_4__2
       (.I0(mem_reg_0_15_78_79[280]),
        .I1(phy_wrdata[312]),
        .I2(mem_reg_0_15_18_23_0),
        .O(\write_buffer.wr_buf_out_data_reg[479]_0 [4]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_18_23_i_4__3
       (.I0(mem_reg_0_15_78_79[289]),
        .I1(phy_wrdata[313]),
        .I2(mem_reg_0_15_18_23_0),
        .O(\write_buffer.wr_buf_out_data_reg[487]_0 [12]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_18_23_i_4__4
       (.I0(mem_reg_0_15_78_79[296]),
        .I1(phy_wrdata[312]),
        .I2(mem_reg_0_15_18_23_0),
        .O(\write_buffer.wr_buf_out_data_reg[495]_0 [4]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_18_23_i_4__5
       (.I0(mem_reg_0_15_78_79[304]),
        .I1(phy_wrdata[312]),
        .I2(mem_reg_0_15_18_23_0),
        .O(\write_buffer.wr_buf_out_data_reg[503]_0 [4]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_18_23_i_4__6
       (.I0(mem_reg_0_15_78_79[312]),
        .I1(phy_wrdata[312]),
        .I2(mem_reg_0_15_18_23_0),
        .O(\write_buffer.wr_buf_out_data_reg[511]_0 [4]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_18_23_i_5
       (.I0(mem_reg_0_15_78_79[449]),
        .I1(phy_wrdata[505]),
        .I2(mem_reg_0_15_54_59_0),
        .O(\write_buffer.wr_buf_out_data_reg[455]_0 [15]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_18_23_i_5__0
       (.I0(mem_reg_0_15_78_79[456]),
        .I1(phy_wrdata[504]),
        .I2(mem_reg_0_15_54_59_0),
        .O(\write_buffer.wr_buf_out_data_reg[463]_0 [7]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_18_23_i_5__1
       (.I0(mem_reg_0_15_78_79[464]),
        .I1(phy_wrdata[504]),
        .I2(mem_reg_0_15_54_59_0),
        .O(\write_buffer.wr_buf_out_data_reg[471]_0 [7]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_18_23_i_5__2
       (.I0(mem_reg_0_15_78_79[472]),
        .I1(phy_wrdata[504]),
        .I2(mem_reg_0_15_78_79_0),
        .O(\write_buffer.wr_buf_out_data_reg[479]_0 [7]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_18_23_i_5__3
       (.I0(mem_reg_0_15_78_79[481]),
        .I1(phy_wrdata[505]),
        .I2(mem_reg_0_15_78_79_0),
        .O(\write_buffer.wr_buf_out_data_reg[487]_0 [15]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_18_23_i_5__4
       (.I0(mem_reg_0_15_78_79[488]),
        .I1(phy_wrdata[504]),
        .I2(mem_reg_0_15_78_79_0),
        .O(\write_buffer.wr_buf_out_data_reg[495]_0 [7]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_18_23_i_5__5
       (.I0(mem_reg_0_15_78_79[496]),
        .I1(phy_wrdata[504]),
        .I2(mem_reg_0_15_78_79_0),
        .O(\write_buffer.wr_buf_out_data_reg[503]_0 [7]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_18_23_i_5__6
       (.I0(mem_reg_0_15_78_79[504]),
        .I1(phy_wrdata[504]),
        .I2(mem_reg_0_15_78_79_0),
        .O(\write_buffer.wr_buf_out_data_reg[511]_0 [7]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_18_23_i_6
       (.I0(mem_reg_0_15_78_79[385]),
        .I1(phy_wrdata[441]),
        .I2(mem_reg_0_15_36_41_1),
        .O(\write_buffer.wr_buf_out_data_reg[455]_0 [14]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_18_23_i_6__0
       (.I0(mem_reg_0_15_78_79[392]),
        .I1(phy_wrdata[440]),
        .I2(mem_reg_0_15_36_41_1),
        .O(\write_buffer.wr_buf_out_data_reg[463]_0 [6]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_18_23_i_6__1
       (.I0(mem_reg_0_15_78_79[400]),
        .I1(phy_wrdata[440]),
        .I2(mem_reg_0_15_36_41_1),
        .O(\write_buffer.wr_buf_out_data_reg[471]_0 [6]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_18_23_i_6__2
       (.I0(mem_reg_0_15_78_79[408]),
        .I1(phy_wrdata[440]),
        .I2(mem_reg_0_15_36_41_1),
        .O(\write_buffer.wr_buf_out_data_reg[479]_0 [6]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_18_23_i_6__3
       (.I0(mem_reg_0_15_78_79[417]),
        .I1(phy_wrdata[441]),
        .I2(mem_reg_0_15_36_41_1),
        .O(\write_buffer.wr_buf_out_data_reg[487]_0 [14]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_18_23_i_6__4
       (.I0(mem_reg_0_15_78_79[424]),
        .I1(phy_wrdata[440]),
        .I2(mem_reg_0_15_54_59_0),
        .O(\write_buffer.wr_buf_out_data_reg[495]_0 [6]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_18_23_i_6__5
       (.I0(mem_reg_0_15_78_79[432]),
        .I1(phy_wrdata[440]),
        .I2(mem_reg_0_15_54_59_0),
        .O(\write_buffer.wr_buf_out_data_reg[503]_0 [6]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_18_23_i_6__6
       (.I0(mem_reg_0_15_78_79[440]),
        .I1(phy_wrdata[440]),
        .I2(mem_reg_0_15_54_59_0),
        .O(\write_buffer.wr_buf_out_data_reg[511]_0 [6]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_24_29_i_1
       (.I0(mc_address[22]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10] ),
        .I2(\phy_ctl_wd_i1_reg[0] ),
        .O(d_in[5]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_24_29_i_1__0
       (.I0(mem_reg_0_15_78_79[66]),
        .I1(phy_wrdata[122]),
        .I2(mem_reg_0_15_48_53),
        .O(\write_buffer.wr_buf_out_data_reg[455]_0 [17]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_24_29_i_1__1
       (.I0(mem_reg_0_15_78_79[73]),
        .I1(phy_wrdata[121]),
        .I2(mem_reg_0_15_48_53),
        .O(\write_buffer.wr_buf_out_data_reg[463]_0 [9]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_24_29_i_1__2
       (.I0(mem_reg_0_15_78_79[81]),
        .I1(phy_wrdata[121]),
        .I2(mem_reg_0_15_54_59),
        .O(\write_buffer.wr_buf_out_data_reg[471]_0 [9]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_24_29_i_1__3
       (.I0(mem_reg_0_15_78_79[89]),
        .I1(phy_wrdata[121]),
        .I2(mem_reg_0_15_54_59),
        .O(\write_buffer.wr_buf_out_data_reg[479]_0 [9]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_24_29_i_1__4
       (.I0(mem_reg_0_15_78_79[98]),
        .I1(phy_wrdata[122]),
        .I2(mem_reg_0_15_54_59),
        .O(\write_buffer.wr_buf_out_data_reg[487]_0 [17]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_24_29_i_1__5
       (.I0(mem_reg_0_15_78_79[105]),
        .I1(phy_wrdata[121]),
        .I2(mem_reg_0_15_54_59),
        .O(\write_buffer.wr_buf_out_data_reg[495]_0 [9]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_24_29_i_1__6
       (.I0(mem_reg_0_15_78_79[113]),
        .I1(phy_wrdata[121]),
        .I2(mem_reg_0_15_54_59),
        .O(\write_buffer.wr_buf_out_data_reg[503]_0 [9]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_24_29_i_1__7
       (.I0(mem_reg_0_15_78_79[121]),
        .I1(phy_wrdata[121]),
        .I2(mem_reg_0_15_54_59),
        .O(\write_buffer.wr_buf_out_data_reg[511]_0 [9]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_24_29_i_2
       (.I0(mc_address[10]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10] ),
        .I2(\phy_ctl_wd_i1_reg[0] ),
        .O(d_in[4]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_24_29_i_2__0
       (.I0(mem_reg_0_15_78_79[2]),
        .I1(phy_wrdata[58]),
        .I2(mem_reg_0_15_36_41),
        .O(\write_buffer.wr_buf_out_data_reg[455]_0 [16]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_24_29_i_2__1
       (.I0(mem_reg_0_15_78_79[9]),
        .I1(phy_wrdata[57]),
        .I2(mem_reg_0_15_36_41),
        .O(\write_buffer.wr_buf_out_data_reg[463]_0 [8]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_24_29_i_2__2
       (.I0(mem_reg_0_15_78_79[17]),
        .I1(phy_wrdata[57]),
        .I2(mem_reg_0_15_36_41),
        .O(\write_buffer.wr_buf_out_data_reg[471]_0 [8]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_24_29_i_2__3
       (.I0(mem_reg_0_15_78_79[25]),
        .I1(phy_wrdata[57]),
        .I2(mem_reg_0_15_36_41),
        .O(\write_buffer.wr_buf_out_data_reg[479]_0 [8]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_24_29_i_2__4
       (.I0(mem_reg_0_15_78_79[34]),
        .I1(phy_wrdata[58]),
        .I2(mem_reg_0_15_48_53),
        .O(\write_buffer.wr_buf_out_data_reg[487]_0 [16]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_24_29_i_2__5
       (.I0(mem_reg_0_15_78_79[41]),
        .I1(phy_wrdata[57]),
        .I2(mem_reg_0_15_48_53),
        .O(\write_buffer.wr_buf_out_data_reg[495]_0 [8]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_24_29_i_2__6
       (.I0(mem_reg_0_15_78_79[49]),
        .I1(phy_wrdata[57]),
        .I2(mem_reg_0_15_48_53),
        .O(\write_buffer.wr_buf_out_data_reg[503]_0 [8]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_24_29_i_2__7
       (.I0(mem_reg_0_15_78_79[57]),
        .I1(phy_wrdata[57]),
        .I2(mem_reg_0_15_48_53),
        .O(\write_buffer.wr_buf_out_data_reg[511]_0 [8]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_24_29_i_3
       (.I0(mem_reg_0_15_78_79[194]),
        .I1(phy_wrdata[250]),
        .I2(mem_reg_0_15_72_77),
        .O(\write_buffer.wr_buf_out_data_reg[455]_0 [19]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_24_29_i_3__0
       (.I0(mem_reg_0_15_78_79[201]),
        .I1(phy_wrdata[249]),
        .I2(mem_reg_0_15_72_77),
        .O(\write_buffer.wr_buf_out_data_reg[463]_0 [11]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_24_29_i_3__1
       (.I0(mem_reg_0_15_78_79[209]),
        .I1(phy_wrdata[249]),
        .I2(mem_reg_0_15_72_77),
        .O(\write_buffer.wr_buf_out_data_reg[471]_0 [11]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_24_29_i_3__2
       (.I0(mem_reg_0_15_78_79[217]),
        .I1(phy_wrdata[249]),
        .I2(mem_reg_0_15_72_77),
        .O(\write_buffer.wr_buf_out_data_reg[479]_0 [11]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_24_29_i_3__3
       (.I0(mem_reg_0_15_78_79[226]),
        .I1(phy_wrdata[250]),
        .I2(mem_reg_0_15_18_23),
        .O(\write_buffer.wr_buf_out_data_reg[487]_0 [19]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_24_29_i_3__4
       (.I0(mem_reg_0_15_78_79[233]),
        .I1(phy_wrdata[249]),
        .I2(mem_reg_0_15_18_23),
        .O(\write_buffer.wr_buf_out_data_reg[495]_0 [11]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_24_29_i_3__5
       (.I0(mem_reg_0_15_78_79[241]),
        .I1(phy_wrdata[249]),
        .I2(mem_reg_0_15_18_23),
        .O(\write_buffer.wr_buf_out_data_reg[503]_0 [11]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_24_29_i_3__6
       (.I0(mem_reg_0_15_78_79[249]),
        .I1(phy_wrdata[249]),
        .I2(mem_reg_0_15_18_23),
        .O(\write_buffer.wr_buf_out_data_reg[511]_0 [11]));
  LUT2 #(
    .INIT(4'hE)) 
    mem_reg_0_15_24_29_i_3__7
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10] ),
        .I1(mem_reg_0_15_36_41),
        .O(d_in[7]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_24_29_i_4
       (.I0(mc_address[33]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10] ),
        .I2(\phy_ctl_wd_i1_reg[0] ),
        .O(d_in[6]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_24_29_i_4__0
       (.I0(mem_reg_0_15_78_79[130]),
        .I1(phy_wrdata[186]),
        .I2(mem_reg_0_15_66_71),
        .O(\write_buffer.wr_buf_out_data_reg[455]_0 [18]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_24_29_i_4__1
       (.I0(mem_reg_0_15_78_79[137]),
        .I1(phy_wrdata[185]),
        .I2(mem_reg_0_15_66_71),
        .O(\write_buffer.wr_buf_out_data_reg[463]_0 [10]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_24_29_i_4__2
       (.I0(mem_reg_0_15_78_79[145]),
        .I1(phy_wrdata[185]),
        .I2(mem_reg_0_15_66_71),
        .O(\write_buffer.wr_buf_out_data_reg[471]_0 [10]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_24_29_i_4__3
       (.I0(mem_reg_0_15_78_79[153]),
        .I1(phy_wrdata[185]),
        .I2(mem_reg_0_15_66_71),
        .O(\write_buffer.wr_buf_out_data_reg[479]_0 [10]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_24_29_i_4__4
       (.I0(mem_reg_0_15_78_79[162]),
        .I1(phy_wrdata[186]),
        .I2(mem_reg_0_15_66_71),
        .O(\write_buffer.wr_buf_out_data_reg[487]_0 [18]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_24_29_i_4__5
       (.I0(mem_reg_0_15_78_79[169]),
        .I1(phy_wrdata[185]),
        .I2(mem_reg_0_15_66_71),
        .O(\write_buffer.wr_buf_out_data_reg[495]_0 [10]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_24_29_i_4__6
       (.I0(mem_reg_0_15_78_79[177]),
        .I1(phy_wrdata[185]),
        .I2(mem_reg_0_15_72_77),
        .O(\write_buffer.wr_buf_out_data_reg[503]_0 [10]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_24_29_i_4__7
       (.I0(mem_reg_0_15_78_79[185]),
        .I1(phy_wrdata[185]),
        .I2(mem_reg_0_15_72_77),
        .O(\write_buffer.wr_buf_out_data_reg[511]_0 [10]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_24_29_i_5
       (.I0(mem_reg_0_15_78_79[322]),
        .I1(phy_wrdata[378]),
        .I2(mem_reg_0_15_36_41_0),
        .O(\write_buffer.wr_buf_out_data_reg[455]_0 [21]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_24_29_i_5__0
       (.I0(mem_reg_0_15_78_79[329]),
        .I1(phy_wrdata[377]),
        .I2(mem_reg_0_15_36_41_0),
        .O(\write_buffer.wr_buf_out_data_reg[463]_0 [13]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_24_29_i_5__1
       (.I0(mem_reg_0_15_78_79[337]),
        .I1(phy_wrdata[377]),
        .I2(mem_reg_0_15_36_41_0),
        .O(\write_buffer.wr_buf_out_data_reg[471]_0 [13]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_24_29_i_5__2
       (.I0(mem_reg_0_15_78_79[345]),
        .I1(phy_wrdata[377]),
        .I2(mem_reg_0_15_36_41_0),
        .O(\write_buffer.wr_buf_out_data_reg[479]_0 [13]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_24_29_i_5__3
       (.I0(mem_reg_0_15_78_79[354]),
        .I1(phy_wrdata[378]),
        .I2(mem_reg_0_15_36_41_0),
        .O(\write_buffer.wr_buf_out_data_reg[487]_0 [21]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_24_29_i_5__4
       (.I0(mem_reg_0_15_78_79[361]),
        .I1(phy_wrdata[377]),
        .I2(mem_reg_0_15_36_41_0),
        .O(\write_buffer.wr_buf_out_data_reg[495]_0 [13]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_24_29_i_5__5
       (.I0(mem_reg_0_15_78_79[369]),
        .I1(phy_wrdata[377]),
        .I2(mem_reg_0_15_36_41_0),
        .O(\write_buffer.wr_buf_out_data_reg[503]_0 [13]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_24_29_i_5__6
       (.I0(mem_reg_0_15_78_79[377]),
        .I1(phy_wrdata[377]),
        .I2(mem_reg_0_15_36_41_1),
        .O(\write_buffer.wr_buf_out_data_reg[511]_0 [13]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_24_29_i_6
       (.I0(mem_reg_0_15_78_79[258]),
        .I1(phy_wrdata[314]),
        .I2(mem_reg_0_15_18_23),
        .O(\write_buffer.wr_buf_out_data_reg[455]_0 [20]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_24_29_i_6__0
       (.I0(mem_reg_0_15_78_79[265]),
        .I1(phy_wrdata[313]),
        .I2(mem_reg_0_15_18_23),
        .O(\write_buffer.wr_buf_out_data_reg[463]_0 [12]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_24_29_i_6__1
       (.I0(mem_reg_0_15_78_79[273]),
        .I1(phy_wrdata[313]),
        .I2(mem_reg_0_15_18_23_0),
        .O(\write_buffer.wr_buf_out_data_reg[471]_0 [12]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_24_29_i_6__2
       (.I0(mem_reg_0_15_78_79[281]),
        .I1(phy_wrdata[313]),
        .I2(mem_reg_0_15_18_23_0),
        .O(\write_buffer.wr_buf_out_data_reg[479]_0 [12]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_24_29_i_6__3
       (.I0(mem_reg_0_15_78_79[290]),
        .I1(phy_wrdata[314]),
        .I2(mem_reg_0_15_18_23_0),
        .O(\write_buffer.wr_buf_out_data_reg[487]_0 [20]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_24_29_i_6__4
       (.I0(mem_reg_0_15_78_79[297]),
        .I1(phy_wrdata[313]),
        .I2(mem_reg_0_15_18_23_0),
        .O(\write_buffer.wr_buf_out_data_reg[495]_0 [12]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_24_29_i_6__5
       (.I0(mem_reg_0_15_78_79[305]),
        .I1(phy_wrdata[313]),
        .I2(mem_reg_0_15_18_23_0),
        .O(\write_buffer.wr_buf_out_data_reg[503]_0 [12]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_24_29_i_6__6
       (.I0(mem_reg_0_15_78_79[313]),
        .I1(phy_wrdata[313]),
        .I2(mem_reg_0_15_18_23_0),
        .O(\write_buffer.wr_buf_out_data_reg[511]_0 [12]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_30_35_i_1
       (.I0(mc_address[16]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ),
        .I2(\phy_ctl_wd_i1_reg[0] ),
        .O(d_in[9]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_30_35_i_1__0
       (.I0(mc_address[20]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ),
        .I2(\phy_ctl_wd_i1_reg[0] ),
        .O(phy_dout[1]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_30_35_i_1__1
       (.I0(mem_reg_0_15_78_79[450]),
        .I1(phy_wrdata[506]),
        .I2(mem_reg_0_15_54_59_0),
        .O(\write_buffer.wr_buf_out_data_reg[455]_0 [23]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_30_35_i_1__2
       (.I0(mem_reg_0_15_78_79[457]),
        .I1(phy_wrdata[505]),
        .I2(mem_reg_0_15_54_59_0),
        .O(\write_buffer.wr_buf_out_data_reg[463]_0 [15]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_30_35_i_1__3
       (.I0(mem_reg_0_15_78_79[465]),
        .I1(phy_wrdata[505]),
        .I2(mem_reg_0_15_54_59_0),
        .O(\write_buffer.wr_buf_out_data_reg[471]_0 [15]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_30_35_i_1__4
       (.I0(mem_reg_0_15_78_79[473]),
        .I1(phy_wrdata[505]),
        .I2(mem_reg_0_15_78_79_0),
        .O(\write_buffer.wr_buf_out_data_reg[479]_0 [15]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_30_35_i_1__5
       (.I0(mem_reg_0_15_78_79[482]),
        .I1(phy_wrdata[506]),
        .I2(mem_reg_0_15_78_79_0),
        .O(\write_buffer.wr_buf_out_data_reg[487]_0 [23]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_30_35_i_1__6
       (.I0(mem_reg_0_15_78_79[489]),
        .I1(phy_wrdata[505]),
        .I2(mem_reg_0_15_78_79_0),
        .O(\write_buffer.wr_buf_out_data_reg[495]_0 [15]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_30_35_i_1__7
       (.I0(mem_reg_0_15_78_79[497]),
        .I1(phy_wrdata[505]),
        .I2(mem_reg_0_15_78_79_0),
        .O(\write_buffer.wr_buf_out_data_reg[503]_0 [15]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_30_35_i_1__8
       (.I0(mem_reg_0_15_78_79[505]),
        .I1(phy_wrdata[505]),
        .I2(mem_reg_0_15_78_79_0),
        .O(\write_buffer.wr_buf_out_data_reg[511]_0 [15]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_30_35_i_1__9
       (.I0(mc_cas_n),
        .I1(phy_ctl_wr_i1_reg),
        .I2(phy_cs_n),
        .O(\cmd_pipe_plus.mc_cke_reg[3]_0 [1]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_30_35_i_2
       (.I0(mc_address[4]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ),
        .I2(\phy_ctl_wd_i1_reg[0] ),
        .O(d_in[8]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_30_35_i_2__0
       (.I0(mc_address[8]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ),
        .I2(\phy_ctl_wd_i1_reg[0] ),
        .O(phy_dout[0]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_30_35_i_2__1
       (.I0(mem_reg_0_15_78_79[386]),
        .I1(phy_wrdata[442]),
        .I2(mem_reg_0_15_36_41_1),
        .O(\write_buffer.wr_buf_out_data_reg[455]_0 [22]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_30_35_i_2__2
       (.I0(mem_reg_0_15_78_79[393]),
        .I1(phy_wrdata[441]),
        .I2(mem_reg_0_15_36_41_1),
        .O(\write_buffer.wr_buf_out_data_reg[463]_0 [14]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_30_35_i_2__3
       (.I0(mem_reg_0_15_78_79[401]),
        .I1(phy_wrdata[441]),
        .I2(mem_reg_0_15_36_41_1),
        .O(\write_buffer.wr_buf_out_data_reg[471]_0 [14]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_30_35_i_2__4
       (.I0(mem_reg_0_15_78_79[409]),
        .I1(phy_wrdata[441]),
        .I2(mem_reg_0_15_36_41_1),
        .O(\write_buffer.wr_buf_out_data_reg[479]_0 [14]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_30_35_i_2__5
       (.I0(mem_reg_0_15_78_79[418]),
        .I1(phy_wrdata[442]),
        .I2(mem_reg_0_15_36_41_1),
        .O(\write_buffer.wr_buf_out_data_reg[487]_0 [22]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_30_35_i_2__6
       (.I0(mem_reg_0_15_78_79[425]),
        .I1(phy_wrdata[441]),
        .I2(mem_reg_0_15_54_59_0),
        .O(\write_buffer.wr_buf_out_data_reg[495]_0 [14]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_30_35_i_2__7
       (.I0(mem_reg_0_15_78_79[433]),
        .I1(phy_wrdata[441]),
        .I2(mem_reg_0_15_54_59_0),
        .O(\write_buffer.wr_buf_out_data_reg[503]_0 [14]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_30_35_i_2__8
       (.I0(mem_reg_0_15_78_79[441]),
        .I1(phy_wrdata[441]),
        .I2(mem_reg_0_15_54_59_0),
        .O(\write_buffer.wr_buf_out_data_reg[511]_0 [14]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_30_35_i_3
       (.I0(mem_reg_0_15_78_79[67]),
        .I1(phy_wrdata[123]),
        .I2(mem_reg_0_15_48_53),
        .O(\write_buffer.wr_buf_out_data_reg[455]_0 [25]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_30_35_i_3__0
       (.I0(mem_reg_0_15_78_79[74]),
        .I1(phy_wrdata[122]),
        .I2(mem_reg_0_15_48_53),
        .O(\write_buffer.wr_buf_out_data_reg[463]_0 [17]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_30_35_i_3__1
       (.I0(mem_reg_0_15_78_79[82]),
        .I1(phy_wrdata[122]),
        .I2(mem_reg_0_15_54_59),
        .O(\write_buffer.wr_buf_out_data_reg[471]_0 [17]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_30_35_i_3__2
       (.I0(mem_reg_0_15_78_79[90]),
        .I1(phy_wrdata[122]),
        .I2(mem_reg_0_15_54_59),
        .O(\write_buffer.wr_buf_out_data_reg[479]_0 [17]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_30_35_i_3__3
       (.I0(mem_reg_0_15_78_79[99]),
        .I1(phy_wrdata[123]),
        .I2(mem_reg_0_15_54_59),
        .O(\write_buffer.wr_buf_out_data_reg[487]_0 [25]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_30_35_i_3__4
       (.I0(mem_reg_0_15_78_79[106]),
        .I1(phy_wrdata[122]),
        .I2(mem_reg_0_15_54_59),
        .O(\write_buffer.wr_buf_out_data_reg[495]_0 [17]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_30_35_i_3__5
       (.I0(mem_reg_0_15_78_79[114]),
        .I1(phy_wrdata[122]),
        .I2(mem_reg_0_15_54_59),
        .O(\write_buffer.wr_buf_out_data_reg[503]_0 [17]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_30_35_i_3__6
       (.I0(mem_reg_0_15_78_79[122]),
        .I1(phy_wrdata[122]),
        .I2(mem_reg_0_15_54_59),
        .O(\write_buffer.wr_buf_out_data_reg[511]_0 [17]));
  LUT2 #(
    .INIT(4'hE)) 
    mem_reg_0_15_30_35_i_3__7
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ),
        .I1(mem_reg_0_15_36_41),
        .O(d_in[11]));
  LUT2 #(
    .INIT(4'hE)) 
    mem_reg_0_15_30_35_i_3__8
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ),
        .I1(mem_reg_0_15_36_41),
        .O(phy_dout[3]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_30_35_i_4
       (.I0(mc_address[27]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ),
        .I2(\phy_ctl_wd_i1_reg[0] ),
        .O(d_in[10]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_30_35_i_4__0
       (.I0(mc_address[31]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ),
        .I2(\phy_ctl_wd_i1_reg[0] ),
        .O(phy_dout[2]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_30_35_i_4__1
       (.I0(mem_reg_0_15_78_79[3]),
        .I1(phy_wrdata[59]),
        .I2(mem_reg_0_15_36_41),
        .O(\write_buffer.wr_buf_out_data_reg[455]_0 [24]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_30_35_i_4__2
       (.I0(mem_reg_0_15_78_79[10]),
        .I1(phy_wrdata[58]),
        .I2(mem_reg_0_15_36_41),
        .O(\write_buffer.wr_buf_out_data_reg[463]_0 [16]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_30_35_i_4__3
       (.I0(mem_reg_0_15_78_79[18]),
        .I1(phy_wrdata[58]),
        .I2(mem_reg_0_15_36_41),
        .O(\write_buffer.wr_buf_out_data_reg[471]_0 [16]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_30_35_i_4__4
       (.I0(mem_reg_0_15_78_79[26]),
        .I1(phy_wrdata[58]),
        .I2(mem_reg_0_15_36_41),
        .O(\write_buffer.wr_buf_out_data_reg[479]_0 [16]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_30_35_i_4__5
       (.I0(mem_reg_0_15_78_79[35]),
        .I1(phy_wrdata[59]),
        .I2(mem_reg_0_15_48_53),
        .O(\write_buffer.wr_buf_out_data_reg[487]_0 [24]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_30_35_i_4__6
       (.I0(mem_reg_0_15_78_79[42]),
        .I1(phy_wrdata[58]),
        .I2(mem_reg_0_15_48_53),
        .O(\write_buffer.wr_buf_out_data_reg[495]_0 [16]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_30_35_i_4__7
       (.I0(mem_reg_0_15_78_79[50]),
        .I1(phy_wrdata[58]),
        .I2(mem_reg_0_15_48_53),
        .O(\write_buffer.wr_buf_out_data_reg[503]_0 [16]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_30_35_i_4__8
       (.I0(mem_reg_0_15_78_79[58]),
        .I1(phy_wrdata[58]),
        .I2(mem_reg_0_15_48_53),
        .O(\write_buffer.wr_buf_out_data_reg[511]_0 [16]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_30_35_i_5
       (.I0(mem_reg_0_15_78_79[195]),
        .I1(phy_wrdata[251]),
        .I2(mem_reg_0_15_72_77),
        .O(\write_buffer.wr_buf_out_data_reg[455]_0 [27]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_30_35_i_5__0
       (.I0(mem_reg_0_15_78_79[202]),
        .I1(phy_wrdata[250]),
        .I2(mem_reg_0_15_72_77),
        .O(\write_buffer.wr_buf_out_data_reg[463]_0 [19]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_30_35_i_5__1
       (.I0(mem_reg_0_15_78_79[210]),
        .I1(phy_wrdata[250]),
        .I2(mem_reg_0_15_72_77),
        .O(\write_buffer.wr_buf_out_data_reg[471]_0 [19]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_30_35_i_5__2
       (.I0(mem_reg_0_15_78_79[218]),
        .I1(phy_wrdata[250]),
        .I2(mem_reg_0_15_72_77),
        .O(\write_buffer.wr_buf_out_data_reg[479]_0 [19]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_30_35_i_5__3
       (.I0(mem_reg_0_15_78_79[227]),
        .I1(phy_wrdata[251]),
        .I2(mem_reg_0_15_18_23),
        .O(\write_buffer.wr_buf_out_data_reg[487]_0 [27]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_30_35_i_5__4
       (.I0(mem_reg_0_15_78_79[234]),
        .I1(phy_wrdata[250]),
        .I2(mem_reg_0_15_18_23),
        .O(\write_buffer.wr_buf_out_data_reg[495]_0 [19]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_30_35_i_5__5
       (.I0(mem_reg_0_15_78_79[242]),
        .I1(phy_wrdata[250]),
        .I2(mem_reg_0_15_18_23),
        .O(\write_buffer.wr_buf_out_data_reg[503]_0 [19]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_30_35_i_5__6
       (.I0(mem_reg_0_15_78_79[250]),
        .I1(phy_wrdata[250]),
        .I2(mem_reg_0_15_18_23),
        .O(\write_buffer.wr_buf_out_data_reg[511]_0 [19]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_30_35_i_6
       (.I0(mem_reg_0_15_78_79[131]),
        .I1(phy_wrdata[187]),
        .I2(mem_reg_0_15_66_71),
        .O(\write_buffer.wr_buf_out_data_reg[455]_0 [26]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_30_35_i_6__0
       (.I0(mem_reg_0_15_78_79[138]),
        .I1(phy_wrdata[186]),
        .I2(mem_reg_0_15_66_71),
        .O(\write_buffer.wr_buf_out_data_reg[463]_0 [18]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_30_35_i_6__1
       (.I0(mem_reg_0_15_78_79[146]),
        .I1(phy_wrdata[186]),
        .I2(mem_reg_0_15_66_71),
        .O(\write_buffer.wr_buf_out_data_reg[471]_0 [18]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_30_35_i_6__2
       (.I0(mem_reg_0_15_78_79[154]),
        .I1(phy_wrdata[186]),
        .I2(mem_reg_0_15_66_71),
        .O(\write_buffer.wr_buf_out_data_reg[479]_0 [18]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_30_35_i_6__3
       (.I0(mem_reg_0_15_78_79[163]),
        .I1(phy_wrdata[187]),
        .I2(mem_reg_0_15_66_71),
        .O(\write_buffer.wr_buf_out_data_reg[487]_0 [26]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_30_35_i_6__4
       (.I0(mem_reg_0_15_78_79[170]),
        .I1(phy_wrdata[186]),
        .I2(mem_reg_0_15_66_71),
        .O(\write_buffer.wr_buf_out_data_reg[495]_0 [18]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_30_35_i_6__5
       (.I0(mem_reg_0_15_78_79[178]),
        .I1(phy_wrdata[186]),
        .I2(mem_reg_0_15_72_77),
        .O(\write_buffer.wr_buf_out_data_reg[503]_0 [18]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_30_35_i_6__6
       (.I0(mem_reg_0_15_78_79[186]),
        .I1(phy_wrdata[186]),
        .I2(mem_reg_0_15_72_77),
        .O(\write_buffer.wr_buf_out_data_reg[511]_0 [18]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_36_41_i_1
       (.I0(mc_bank[5]),
        .I1(phy_bank[11]),
        .I2(mem_reg_0_15_36_41),
        .O(phy_dout[5]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_36_41_i_1__0
       (.I0(mem_reg_0_15_78_79[323]),
        .I1(phy_wrdata[379]),
        .I2(mem_reg_0_15_36_41_0),
        .O(\write_buffer.wr_buf_out_data_reg[455]_0 [29]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_36_41_i_1__1
       (.I0(mem_reg_0_15_78_79[330]),
        .I1(phy_wrdata[378]),
        .I2(mem_reg_0_15_36_41_0),
        .O(\write_buffer.wr_buf_out_data_reg[463]_0 [21]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_36_41_i_1__2
       (.I0(mem_reg_0_15_78_79[338]),
        .I1(phy_wrdata[378]),
        .I2(mem_reg_0_15_36_41_0),
        .O(\write_buffer.wr_buf_out_data_reg[471]_0 [21]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_36_41_i_1__3
       (.I0(mem_reg_0_15_78_79[346]),
        .I1(phy_wrdata[378]),
        .I2(mem_reg_0_15_36_41_0),
        .O(\write_buffer.wr_buf_out_data_reg[479]_0 [21]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_36_41_i_1__4
       (.I0(mem_reg_0_15_78_79[355]),
        .I1(phy_wrdata[379]),
        .I2(mem_reg_0_15_36_41_0),
        .O(\write_buffer.wr_buf_out_data_reg[487]_0 [29]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_36_41_i_1__5
       (.I0(mem_reg_0_15_78_79[362]),
        .I1(phy_wrdata[378]),
        .I2(mem_reg_0_15_36_41_0),
        .O(\write_buffer.wr_buf_out_data_reg[495]_0 [21]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_36_41_i_1__6
       (.I0(mem_reg_0_15_78_79[370]),
        .I1(phy_wrdata[378]),
        .I2(mem_reg_0_15_36_41_0),
        .O(\write_buffer.wr_buf_out_data_reg[503]_0 [21]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_36_41_i_1__7
       (.I0(mem_reg_0_15_78_79[378]),
        .I1(phy_wrdata[378]),
        .I2(mem_reg_0_15_36_41_1),
        .O(\write_buffer.wr_buf_out_data_reg[511]_0 [21]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_36_41_i_1__8
       (.I0(mc_cas_n),
        .I1(phy_ctl_wr_i1_reg),
        .I2(phy_cas_n),
        .O(\cmd_pipe_plus.mc_cke_reg[3]_0 [2]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_36_41_i_2
       (.I0(mc_bank[2]),
        .I1(phy_bank[11]),
        .I2(mem_reg_0_15_36_41),
        .O(phy_dout[4]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_36_41_i_2__0
       (.I0(mem_reg_0_15_78_79[259]),
        .I1(phy_wrdata[315]),
        .I2(mem_reg_0_15_18_23),
        .O(\write_buffer.wr_buf_out_data_reg[455]_0 [28]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_36_41_i_2__1
       (.I0(mem_reg_0_15_78_79[266]),
        .I1(phy_wrdata[314]),
        .I2(mem_reg_0_15_18_23),
        .O(\write_buffer.wr_buf_out_data_reg[463]_0 [20]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_36_41_i_2__2
       (.I0(mem_reg_0_15_78_79[274]),
        .I1(phy_wrdata[314]),
        .I2(mem_reg_0_15_18_23_0),
        .O(\write_buffer.wr_buf_out_data_reg[471]_0 [20]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_36_41_i_2__3
       (.I0(mem_reg_0_15_78_79[282]),
        .I1(phy_wrdata[314]),
        .I2(mem_reg_0_15_18_23_0),
        .O(\write_buffer.wr_buf_out_data_reg[479]_0 [20]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_36_41_i_2__4
       (.I0(mem_reg_0_15_78_79[291]),
        .I1(phy_wrdata[315]),
        .I2(mem_reg_0_15_18_23_0),
        .O(\write_buffer.wr_buf_out_data_reg[487]_0 [28]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_36_41_i_2__5
       (.I0(mem_reg_0_15_78_79[298]),
        .I1(phy_wrdata[314]),
        .I2(mem_reg_0_15_18_23_0),
        .O(\write_buffer.wr_buf_out_data_reg[495]_0 [20]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_36_41_i_2__6
       (.I0(mem_reg_0_15_78_79[306]),
        .I1(phy_wrdata[314]),
        .I2(mem_reg_0_15_18_23_0),
        .O(\write_buffer.wr_buf_out_data_reg[503]_0 [20]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_36_41_i_2__7
       (.I0(mem_reg_0_15_78_79[314]),
        .I1(phy_wrdata[314]),
        .I2(mem_reg_0_15_18_23_0),
        .O(\write_buffer.wr_buf_out_data_reg[511]_0 [20]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_36_41_i_3
       (.I0(mem_reg_0_15_78_79[451]),
        .I1(phy_wrdata[507]),
        .I2(mem_reg_0_15_54_59_0),
        .O(\write_buffer.wr_buf_out_data_reg[455]_0 [31]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_36_41_i_3__0
       (.I0(mem_reg_0_15_78_79[458]),
        .I1(phy_wrdata[506]),
        .I2(mem_reg_0_15_54_59_0),
        .O(\write_buffer.wr_buf_out_data_reg[463]_0 [23]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_36_41_i_3__1
       (.I0(mem_reg_0_15_78_79[466]),
        .I1(phy_wrdata[506]),
        .I2(mem_reg_0_15_54_59_0),
        .O(\write_buffer.wr_buf_out_data_reg[471]_0 [23]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_36_41_i_3__2
       (.I0(mem_reg_0_15_78_79[474]),
        .I1(phy_wrdata[506]),
        .I2(mem_reg_0_15_78_79_0),
        .O(\write_buffer.wr_buf_out_data_reg[479]_0 [23]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_36_41_i_3__3
       (.I0(mem_reg_0_15_78_79[483]),
        .I1(phy_wrdata[507]),
        .I2(mem_reg_0_15_78_79_0),
        .O(\write_buffer.wr_buf_out_data_reg[487]_0 [31]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_36_41_i_3__4
       (.I0(mem_reg_0_15_78_79[490]),
        .I1(phy_wrdata[506]),
        .I2(mem_reg_0_15_78_79_0),
        .O(\write_buffer.wr_buf_out_data_reg[495]_0 [23]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_36_41_i_3__5
       (.I0(mem_reg_0_15_78_79[498]),
        .I1(phy_wrdata[506]),
        .I2(mem_reg_0_15_78_79_0),
        .O(\write_buffer.wr_buf_out_data_reg[503]_0 [23]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_36_41_i_3__6
       (.I0(mem_reg_0_15_78_79[506]),
        .I1(phy_wrdata[506]),
        .I2(mem_reg_0_15_78_79_0),
        .O(\write_buffer.wr_buf_out_data_reg[511]_0 [23]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_36_41_i_4
       (.I0(mem_reg_0_15_78_79[387]),
        .I1(phy_wrdata[443]),
        .I2(mem_reg_0_15_36_41_1),
        .O(\write_buffer.wr_buf_out_data_reg[455]_0 [30]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_36_41_i_4__0
       (.I0(mem_reg_0_15_78_79[394]),
        .I1(phy_wrdata[442]),
        .I2(mem_reg_0_15_36_41_1),
        .O(\write_buffer.wr_buf_out_data_reg[463]_0 [22]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_36_41_i_4__1
       (.I0(mem_reg_0_15_78_79[402]),
        .I1(phy_wrdata[442]),
        .I2(mem_reg_0_15_36_41_1),
        .O(\write_buffer.wr_buf_out_data_reg[471]_0 [22]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_36_41_i_4__2
       (.I0(mem_reg_0_15_78_79[410]),
        .I1(phy_wrdata[442]),
        .I2(mem_reg_0_15_36_41_1),
        .O(\write_buffer.wr_buf_out_data_reg[479]_0 [22]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_36_41_i_4__3
       (.I0(mem_reg_0_15_78_79[419]),
        .I1(phy_wrdata[443]),
        .I2(mem_reg_0_15_36_41_1),
        .O(\write_buffer.wr_buf_out_data_reg[487]_0 [30]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_36_41_i_4__4
       (.I0(mem_reg_0_15_78_79[426]),
        .I1(phy_wrdata[442]),
        .I2(mem_reg_0_15_54_59_0),
        .O(\write_buffer.wr_buf_out_data_reg[495]_0 [22]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_36_41_i_4__5
       (.I0(mem_reg_0_15_78_79[434]),
        .I1(phy_wrdata[442]),
        .I2(mem_reg_0_15_54_59_0),
        .O(\write_buffer.wr_buf_out_data_reg[503]_0 [22]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_36_41_i_4__6
       (.I0(mem_reg_0_15_78_79[442]),
        .I1(phy_wrdata[442]),
        .I2(mem_reg_0_15_54_59_0),
        .O(\write_buffer.wr_buf_out_data_reg[511]_0 [22]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_36_41_i_5
       (.I0(mem_reg_0_15_78_79[68]),
        .I1(phy_wrdata[124]),
        .I2(mem_reg_0_15_48_53),
        .O(\write_buffer.wr_buf_out_data_reg[455]_0 [33]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_36_41_i_5__0
       (.I0(mem_reg_0_15_78_79[75]),
        .I1(phy_wrdata[123]),
        .I2(mem_reg_0_15_48_53),
        .O(\write_buffer.wr_buf_out_data_reg[463]_0 [25]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_36_41_i_5__1
       (.I0(mem_reg_0_15_78_79[83]),
        .I1(phy_wrdata[123]),
        .I2(mem_reg_0_15_54_59),
        .O(\write_buffer.wr_buf_out_data_reg[471]_0 [25]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_36_41_i_5__2
       (.I0(mem_reg_0_15_78_79[91]),
        .I1(phy_wrdata[123]),
        .I2(mem_reg_0_15_54_59),
        .O(\write_buffer.wr_buf_out_data_reg[479]_0 [25]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_36_41_i_5__3
       (.I0(mem_reg_0_15_78_79[100]),
        .I1(phy_wrdata[124]),
        .I2(mem_reg_0_15_54_59),
        .O(\write_buffer.wr_buf_out_data_reg[487]_0 [33]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_36_41_i_5__4
       (.I0(mem_reg_0_15_78_79[107]),
        .I1(phy_wrdata[123]),
        .I2(mem_reg_0_15_54_59),
        .O(\write_buffer.wr_buf_out_data_reg[495]_0 [25]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_36_41_i_5__5
       (.I0(mem_reg_0_15_78_79[115]),
        .I1(phy_wrdata[123]),
        .I2(mem_reg_0_15_54_59),
        .O(\write_buffer.wr_buf_out_data_reg[503]_0 [25]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_36_41_i_5__6
       (.I0(mem_reg_0_15_78_79[123]),
        .I1(phy_wrdata[123]),
        .I2(mem_reg_0_15_54_59),
        .O(\write_buffer.wr_buf_out_data_reg[511]_0 [25]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_36_41_i_6
       (.I0(mem_reg_0_15_78_79[4]),
        .I1(phy_wrdata[60]),
        .I2(mem_reg_0_15_36_41),
        .O(\write_buffer.wr_buf_out_data_reg[455]_0 [32]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_36_41_i_6__0
       (.I0(mem_reg_0_15_78_79[11]),
        .I1(phy_wrdata[59]),
        .I2(mem_reg_0_15_36_41),
        .O(\write_buffer.wr_buf_out_data_reg[463]_0 [24]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_36_41_i_6__1
       (.I0(mem_reg_0_15_78_79[19]),
        .I1(phy_wrdata[59]),
        .I2(mem_reg_0_15_36_41),
        .O(\write_buffer.wr_buf_out_data_reg[471]_0 [24]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_36_41_i_6__2
       (.I0(mem_reg_0_15_78_79[27]),
        .I1(phy_wrdata[59]),
        .I2(mem_reg_0_15_36_41),
        .O(\write_buffer.wr_buf_out_data_reg[479]_0 [24]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_36_41_i_6__3
       (.I0(mem_reg_0_15_78_79[36]),
        .I1(phy_wrdata[60]),
        .I2(mem_reg_0_15_48_53),
        .O(\write_buffer.wr_buf_out_data_reg[487]_0 [32]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_36_41_i_6__4
       (.I0(mem_reg_0_15_78_79[43]),
        .I1(phy_wrdata[59]),
        .I2(mem_reg_0_15_48_53),
        .O(\write_buffer.wr_buf_out_data_reg[495]_0 [24]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_36_41_i_6__5
       (.I0(mem_reg_0_15_78_79[51]),
        .I1(phy_wrdata[59]),
        .I2(mem_reg_0_15_48_53),
        .O(\write_buffer.wr_buf_out_data_reg[503]_0 [24]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_36_41_i_6__6
       (.I0(mem_reg_0_15_78_79[59]),
        .I1(phy_wrdata[59]),
        .I2(mem_reg_0_15_48_53),
        .O(\write_buffer.wr_buf_out_data_reg[511]_0 [24]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_42_47_i_1
       (.I0(mem_reg_0_15_78_79[196]),
        .I1(phy_wrdata[252]),
        .I2(mem_reg_0_15_72_77),
        .O(\write_buffer.wr_buf_out_data_reg[455]_0 [35]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_42_47_i_1__0
       (.I0(mem_reg_0_15_78_79[203]),
        .I1(phy_wrdata[251]),
        .I2(mem_reg_0_15_72_77),
        .O(\write_buffer.wr_buf_out_data_reg[463]_0 [27]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_42_47_i_1__1
       (.I0(mem_reg_0_15_78_79[211]),
        .I1(phy_wrdata[251]),
        .I2(mem_reg_0_15_72_77),
        .O(\write_buffer.wr_buf_out_data_reg[471]_0 [27]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_42_47_i_1__2
       (.I0(mem_reg_0_15_78_79[219]),
        .I1(phy_wrdata[251]),
        .I2(mem_reg_0_15_72_77),
        .O(\write_buffer.wr_buf_out_data_reg[479]_0 [27]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_42_47_i_1__3
       (.I0(mem_reg_0_15_78_79[228]),
        .I1(phy_wrdata[252]),
        .I2(mem_reg_0_15_18_23),
        .O(\write_buffer.wr_buf_out_data_reg[487]_0 [35]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_42_47_i_1__4
       (.I0(mem_reg_0_15_78_79[235]),
        .I1(phy_wrdata[251]),
        .I2(mem_reg_0_15_18_23),
        .O(\write_buffer.wr_buf_out_data_reg[495]_0 [27]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_42_47_i_1__5
       (.I0(mem_reg_0_15_78_79[243]),
        .I1(phy_wrdata[251]),
        .I2(mem_reg_0_15_18_23),
        .O(\write_buffer.wr_buf_out_data_reg[503]_0 [27]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_42_47_i_1__6
       (.I0(mem_reg_0_15_78_79[251]),
        .I1(phy_wrdata[251]),
        .I2(mem_reg_0_15_18_23),
        .O(\write_buffer.wr_buf_out_data_reg[511]_0 [27]));
  LUT2 #(
    .INIT(4'hE)) 
    mem_reg_0_15_42_47_i_1__7
       (.I0(phy_bank[11]),
        .I1(mem_reg_0_15_36_41),
        .O(phy_dout[7]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_42_47_i_2
       (.I0(mc_address[15]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),
        .I2(\phy_ctl_wd_i1_reg[0] ),
        .O(d_in[13]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_42_47_i_2__0
       (.I0(mc_bank[8]),
        .I1(phy_bank[11]),
        .I2(mem_reg_0_15_36_41),
        .O(phy_dout[6]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_42_47_i_2__1
       (.I0(mem_reg_0_15_78_79[132]),
        .I1(phy_wrdata[188]),
        .I2(mem_reg_0_15_66_71),
        .O(\write_buffer.wr_buf_out_data_reg[455]_0 [34]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_42_47_i_2__2
       (.I0(mem_reg_0_15_78_79[139]),
        .I1(phy_wrdata[187]),
        .I2(mem_reg_0_15_66_71),
        .O(\write_buffer.wr_buf_out_data_reg[463]_0 [26]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_42_47_i_2__3
       (.I0(mem_reg_0_15_78_79[147]),
        .I1(phy_wrdata[187]),
        .I2(mem_reg_0_15_66_71),
        .O(\write_buffer.wr_buf_out_data_reg[471]_0 [26]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_42_47_i_2__4
       (.I0(mem_reg_0_15_78_79[155]),
        .I1(phy_wrdata[187]),
        .I2(mem_reg_0_15_66_71),
        .O(\write_buffer.wr_buf_out_data_reg[479]_0 [26]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_42_47_i_2__5
       (.I0(mem_reg_0_15_78_79[164]),
        .I1(phy_wrdata[188]),
        .I2(mem_reg_0_15_66_71),
        .O(\write_buffer.wr_buf_out_data_reg[487]_0 [34]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_42_47_i_2__6
       (.I0(mem_reg_0_15_78_79[171]),
        .I1(phy_wrdata[187]),
        .I2(mem_reg_0_15_66_71),
        .O(\write_buffer.wr_buf_out_data_reg[495]_0 [26]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_42_47_i_2__7
       (.I0(mem_reg_0_15_78_79[179]),
        .I1(phy_wrdata[187]),
        .I2(mem_reg_0_15_72_77),
        .O(\write_buffer.wr_buf_out_data_reg[503]_0 [26]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_42_47_i_2__8
       (.I0(mem_reg_0_15_78_79[187]),
        .I1(phy_wrdata[187]),
        .I2(mem_reg_0_15_72_77),
        .O(\write_buffer.wr_buf_out_data_reg[511]_0 [26]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_42_47_i_2__9
       (.I0(mc_ras_n),
        .I1(phy_ctl_wr_i1_reg),
        .I2(phy_ras_n),
        .O(\cmd_pipe_plus.mc_cke_reg[3]_0 [3]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_42_47_i_3
       (.I0(mc_address[3]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),
        .I2(\phy_ctl_wd_i1_reg[0] ),
        .O(d_in[12]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_42_47_i_3__0
       (.I0(mc_bank[4]),
        .I1(phy_bank[10]),
        .I2(mem_reg_0_15_36_41),
        .O(phy_dout[9]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_42_47_i_3__1
       (.I0(mem_reg_0_15_78_79[324]),
        .I1(phy_wrdata[380]),
        .I2(mem_reg_0_15_36_41_0),
        .O(\write_buffer.wr_buf_out_data_reg[455]_0 [37]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_42_47_i_3__2
       (.I0(mem_reg_0_15_78_79[331]),
        .I1(phy_wrdata[379]),
        .I2(mem_reg_0_15_36_41_0),
        .O(\write_buffer.wr_buf_out_data_reg[463]_0 [29]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_42_47_i_3__3
       (.I0(mem_reg_0_15_78_79[339]),
        .I1(phy_wrdata[379]),
        .I2(mem_reg_0_15_36_41_0),
        .O(\write_buffer.wr_buf_out_data_reg[471]_0 [29]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_42_47_i_3__4
       (.I0(mem_reg_0_15_78_79[347]),
        .I1(phy_wrdata[379]),
        .I2(mem_reg_0_15_36_41_0),
        .O(\write_buffer.wr_buf_out_data_reg[479]_0 [29]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_42_47_i_3__5
       (.I0(mem_reg_0_15_78_79[356]),
        .I1(phy_wrdata[380]),
        .I2(mem_reg_0_15_36_41_0),
        .O(\write_buffer.wr_buf_out_data_reg[487]_0 [37]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_42_47_i_3__6
       (.I0(mem_reg_0_15_78_79[363]),
        .I1(phy_wrdata[379]),
        .I2(mem_reg_0_15_36_41_0),
        .O(\write_buffer.wr_buf_out_data_reg[495]_0 [29]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_42_47_i_3__7
       (.I0(mem_reg_0_15_78_79[371]),
        .I1(phy_wrdata[379]),
        .I2(mem_reg_0_15_36_41_1),
        .O(\write_buffer.wr_buf_out_data_reg[503]_0 [29]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_42_47_i_3__8
       (.I0(mem_reg_0_15_78_79[379]),
        .I1(phy_wrdata[379]),
        .I2(mem_reg_0_15_36_41_1),
        .O(\write_buffer.wr_buf_out_data_reg[511]_0 [29]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_42_47_i_4
       (.I0(mc_bank[1]),
        .I1(phy_bank[10]),
        .I2(mem_reg_0_15_36_41),
        .O(phy_dout[8]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_42_47_i_4__0
       (.I0(mem_reg_0_15_78_79[260]),
        .I1(phy_wrdata[316]),
        .I2(mem_reg_0_15_18_23),
        .O(\write_buffer.wr_buf_out_data_reg[455]_0 [36]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_42_47_i_4__1
       (.I0(mem_reg_0_15_78_79[267]),
        .I1(phy_wrdata[315]),
        .I2(mem_reg_0_15_18_23),
        .O(\write_buffer.wr_buf_out_data_reg[463]_0 [28]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_42_47_i_4__2
       (.I0(mem_reg_0_15_78_79[275]),
        .I1(phy_wrdata[315]),
        .I2(mem_reg_0_15_18_23_0),
        .O(\write_buffer.wr_buf_out_data_reg[471]_0 [28]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_42_47_i_4__3
       (.I0(mem_reg_0_15_78_79[283]),
        .I1(phy_wrdata[315]),
        .I2(mem_reg_0_15_18_23_0),
        .O(\write_buffer.wr_buf_out_data_reg[479]_0 [28]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_42_47_i_4__4
       (.I0(mem_reg_0_15_78_79[292]),
        .I1(phy_wrdata[316]),
        .I2(mem_reg_0_15_18_23_0),
        .O(\write_buffer.wr_buf_out_data_reg[487]_0 [36]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_42_47_i_4__5
       (.I0(mem_reg_0_15_78_79[299]),
        .I1(phy_wrdata[315]),
        .I2(mem_reg_0_15_18_23_0),
        .O(\write_buffer.wr_buf_out_data_reg[495]_0 [28]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_42_47_i_4__6
       (.I0(mem_reg_0_15_78_79[307]),
        .I1(phy_wrdata[315]),
        .I2(mem_reg_0_15_18_23_0),
        .O(\write_buffer.wr_buf_out_data_reg[503]_0 [28]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_42_47_i_4__7
       (.I0(mem_reg_0_15_78_79[315]),
        .I1(phy_wrdata[315]),
        .I2(mem_reg_0_15_18_23_0),
        .O(\write_buffer.wr_buf_out_data_reg[511]_0 [28]));
  LUT2 #(
    .INIT(4'hE)) 
    mem_reg_0_15_42_47_i_4__8
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),
        .I1(\phy_ctl_wd_i1_reg[0] ),
        .O(d_in[15]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_42_47_i_5
       (.I0(mc_address[26]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),
        .I2(\phy_ctl_wd_i1_reg[0] ),
        .O(d_in[14]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_42_47_i_5__0
       (.I0(mem_reg_0_15_78_79[452]),
        .I1(phy_wrdata[508]),
        .I2(mem_reg_0_15_54_59_0),
        .O(\write_buffer.wr_buf_out_data_reg[455]_0 [39]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_42_47_i_5__1
       (.I0(mem_reg_0_15_78_79[459]),
        .I1(phy_wrdata[507]),
        .I2(mem_reg_0_15_54_59_0),
        .O(\write_buffer.wr_buf_out_data_reg[463]_0 [31]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_42_47_i_5__2
       (.I0(mem_reg_0_15_78_79[467]),
        .I1(phy_wrdata[507]),
        .I2(mem_reg_0_15_54_59_0),
        .O(\write_buffer.wr_buf_out_data_reg[471]_0 [31]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_42_47_i_5__3
       (.I0(mem_reg_0_15_78_79[475]),
        .I1(phy_wrdata[507]),
        .I2(mem_reg_0_15_78_79_0),
        .O(\write_buffer.wr_buf_out_data_reg[479]_0 [31]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_42_47_i_5__4
       (.I0(mem_reg_0_15_78_79[484]),
        .I1(phy_wrdata[508]),
        .I2(mem_reg_0_15_78_79_0),
        .O(\write_buffer.wr_buf_out_data_reg[487]_0 [39]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_42_47_i_5__5
       (.I0(mem_reg_0_15_78_79[491]),
        .I1(phy_wrdata[507]),
        .I2(mem_reg_0_15_78_79_0),
        .O(\write_buffer.wr_buf_out_data_reg[495]_0 [31]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_42_47_i_5__6
       (.I0(mem_reg_0_15_78_79[499]),
        .I1(phy_wrdata[507]),
        .I2(mem_reg_0_15_78_79_0),
        .O(\write_buffer.wr_buf_out_data_reg[503]_0 [31]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_42_47_i_5__7
       (.I0(mem_reg_0_15_78_79[507]),
        .I1(phy_wrdata[507]),
        .I2(mem_reg_0_15_78_79_0),
        .O(\write_buffer.wr_buf_out_data_reg[511]_0 [31]));
  LUT2 #(
    .INIT(4'hE)) 
    mem_reg_0_15_42_47_i_5__8
       (.I0(phy_bank[10]),
        .I1(mem_reg_0_15_36_41),
        .O(phy_dout[11]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_42_47_i_6
       (.I0(mc_bank[7]),
        .I1(phy_bank[10]),
        .I2(mem_reg_0_15_36_41),
        .O(phy_dout[10]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_42_47_i_6__0
       (.I0(mem_reg_0_15_78_79[388]),
        .I1(phy_wrdata[444]),
        .I2(mem_reg_0_15_36_41_1),
        .O(\write_buffer.wr_buf_out_data_reg[455]_0 [38]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_42_47_i_6__1
       (.I0(mem_reg_0_15_78_79[395]),
        .I1(phy_wrdata[443]),
        .I2(mem_reg_0_15_36_41_1),
        .O(\write_buffer.wr_buf_out_data_reg[463]_0 [30]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_42_47_i_6__2
       (.I0(mem_reg_0_15_78_79[403]),
        .I1(phy_wrdata[443]),
        .I2(mem_reg_0_15_36_41_1),
        .O(\write_buffer.wr_buf_out_data_reg[471]_0 [30]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_42_47_i_6__3
       (.I0(mem_reg_0_15_78_79[411]),
        .I1(phy_wrdata[443]),
        .I2(mem_reg_0_15_36_41_1),
        .O(\write_buffer.wr_buf_out_data_reg[479]_0 [30]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_42_47_i_6__4
       (.I0(mem_reg_0_15_78_79[420]),
        .I1(phy_wrdata[444]),
        .I2(mem_reg_0_15_54_59_0),
        .O(\write_buffer.wr_buf_out_data_reg[487]_0 [38]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_42_47_i_6__5
       (.I0(mem_reg_0_15_78_79[427]),
        .I1(phy_wrdata[443]),
        .I2(mem_reg_0_15_54_59_0),
        .O(\write_buffer.wr_buf_out_data_reg[495]_0 [30]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_42_47_i_6__6
       (.I0(mem_reg_0_15_78_79[435]),
        .I1(phy_wrdata[443]),
        .I2(mem_reg_0_15_54_59_0),
        .O(\write_buffer.wr_buf_out_data_reg[503]_0 [30]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_42_47_i_6__7
       (.I0(mem_reg_0_15_78_79[443]),
        .I1(phy_wrdata[443]),
        .I2(mem_reg_0_15_54_59_0),
        .O(\write_buffer.wr_buf_out_data_reg[511]_0 [30]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_48_53_i_1
       (.I0(mc_ras_n),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12] ),
        .I2(\phy_ctl_wd_i1_reg[0] ),
        .O(d_in[17]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_48_53_i_1__0
       (.I0(mc_bank[3]),
        .I1(phy_bank[9]),
        .I2(mem_reg_0_15_36_41),
        .O(phy_dout[13]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_48_53_i_1__1
       (.I0(mem_reg_0_15_78_79[69]),
        .I1(phy_wrdata[125]),
        .I2(mem_reg_0_15_48_53),
        .O(\write_buffer.wr_buf_out_data_reg[455]_0 [41]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_48_53_i_1__2
       (.I0(mem_reg_0_15_78_79[76]),
        .I1(phy_wrdata[124]),
        .I2(mem_reg_0_15_48_53),
        .O(\write_buffer.wr_buf_out_data_reg[463]_0 [33]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_48_53_i_1__3
       (.I0(mem_reg_0_15_78_79[84]),
        .I1(phy_wrdata[124]),
        .I2(mem_reg_0_15_54_59),
        .O(\write_buffer.wr_buf_out_data_reg[471]_0 [33]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_48_53_i_1__4
       (.I0(mem_reg_0_15_78_79[92]),
        .I1(phy_wrdata[124]),
        .I2(mem_reg_0_15_54_59),
        .O(\write_buffer.wr_buf_out_data_reg[479]_0 [33]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_48_53_i_1__5
       (.I0(mem_reg_0_15_78_79[101]),
        .I1(phy_wrdata[125]),
        .I2(mem_reg_0_15_54_59),
        .O(\write_buffer.wr_buf_out_data_reg[487]_0 [41]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_48_53_i_1__6
       (.I0(mem_reg_0_15_78_79[108]),
        .I1(phy_wrdata[124]),
        .I2(mem_reg_0_15_54_59),
        .O(\write_buffer.wr_buf_out_data_reg[495]_0 [33]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_48_53_i_1__7
       (.I0(mem_reg_0_15_78_79[116]),
        .I1(phy_wrdata[124]),
        .I2(mem_reg_0_15_54_59),
        .O(\write_buffer.wr_buf_out_data_reg[503]_0 [33]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_48_53_i_1__8
       (.I0(mem_reg_0_15_78_79[124]),
        .I1(phy_wrdata[124]),
        .I2(mem_reg_0_15_54_59),
        .O(\write_buffer.wr_buf_out_data_reg[511]_0 [33]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_48_53_i_1__9
       (.I0(mc_we_n),
        .I1(phy_ctl_wr_i1_reg),
        .I2(phy_we_n),
        .O(\cmd_pipe_plus.mc_cke_reg[3]_0 [4]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_48_53_i_2
       (.I0(mc_address[11]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12] ),
        .I2(\phy_ctl_wd_i1_reg[0] ),
        .O(d_in[16]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_48_53_i_2__0
       (.I0(mc_bank[0]),
        .I1(phy_bank[9]),
        .I2(mem_reg_0_15_36_41),
        .O(phy_dout[12]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_48_53_i_2__1
       (.I0(mem_reg_0_15_78_79[5]),
        .I1(phy_wrdata[61]),
        .I2(mem_reg_0_15_36_41),
        .O(\write_buffer.wr_buf_out_data_reg[455]_0 [40]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_48_53_i_2__2
       (.I0(mem_reg_0_15_78_79[12]),
        .I1(phy_wrdata[60]),
        .I2(mem_reg_0_15_36_41),
        .O(\write_buffer.wr_buf_out_data_reg[463]_0 [32]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_48_53_i_2__3
       (.I0(mem_reg_0_15_78_79[20]),
        .I1(phy_wrdata[60]),
        .I2(mem_reg_0_15_36_41),
        .O(\write_buffer.wr_buf_out_data_reg[471]_0 [32]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_48_53_i_2__4
       (.I0(mem_reg_0_15_78_79[28]),
        .I1(phy_wrdata[60]),
        .I2(mem_reg_0_15_48_53),
        .O(\write_buffer.wr_buf_out_data_reg[479]_0 [32]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_48_53_i_2__5
       (.I0(mem_reg_0_15_78_79[37]),
        .I1(phy_wrdata[61]),
        .I2(mem_reg_0_15_48_53),
        .O(\write_buffer.wr_buf_out_data_reg[487]_0 [40]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_48_53_i_2__6
       (.I0(mem_reg_0_15_78_79[44]),
        .I1(phy_wrdata[60]),
        .I2(mem_reg_0_15_48_53),
        .O(\write_buffer.wr_buf_out_data_reg[495]_0 [32]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_48_53_i_2__7
       (.I0(mem_reg_0_15_78_79[52]),
        .I1(phy_wrdata[60]),
        .I2(mem_reg_0_15_48_53),
        .O(\write_buffer.wr_buf_out_data_reg[503]_0 [32]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_48_53_i_2__8
       (.I0(mem_reg_0_15_78_79[60]),
        .I1(phy_wrdata[60]),
        .I2(mem_reg_0_15_48_53),
        .O(\write_buffer.wr_buf_out_data_reg[511]_0 [32]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_48_53_i_3
       (.I0(mem_reg_0_15_78_79[197]),
        .I1(phy_wrdata[253]),
        .I2(mem_reg_0_15_72_77),
        .O(\write_buffer.wr_buf_out_data_reg[455]_0 [43]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_48_53_i_3__0
       (.I0(mem_reg_0_15_78_79[204]),
        .I1(phy_wrdata[252]),
        .I2(mem_reg_0_15_72_77),
        .O(\write_buffer.wr_buf_out_data_reg[463]_0 [35]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_48_53_i_3__1
       (.I0(mem_reg_0_15_78_79[212]),
        .I1(phy_wrdata[252]),
        .I2(mem_reg_0_15_72_77),
        .O(\write_buffer.wr_buf_out_data_reg[471]_0 [35]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_48_53_i_3__2
       (.I0(mem_reg_0_15_78_79[220]),
        .I1(phy_wrdata[252]),
        .I2(mem_reg_0_15_72_77),
        .O(\write_buffer.wr_buf_out_data_reg[479]_0 [35]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_48_53_i_3__3
       (.I0(mem_reg_0_15_78_79[229]),
        .I1(phy_wrdata[253]),
        .I2(mem_reg_0_15_18_23),
        .O(\write_buffer.wr_buf_out_data_reg[487]_0 [43]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_48_53_i_3__4
       (.I0(mem_reg_0_15_78_79[236]),
        .I1(phy_wrdata[252]),
        .I2(mem_reg_0_15_18_23),
        .O(\write_buffer.wr_buf_out_data_reg[495]_0 [35]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_48_53_i_3__5
       (.I0(mem_reg_0_15_78_79[244]),
        .I1(phy_wrdata[252]),
        .I2(mem_reg_0_15_18_23),
        .O(\write_buffer.wr_buf_out_data_reg[503]_0 [35]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_48_53_i_3__6
       (.I0(mem_reg_0_15_78_79[252]),
        .I1(phy_wrdata[252]),
        .I2(mem_reg_0_15_18_23),
        .O(\write_buffer.wr_buf_out_data_reg[511]_0 [35]));
  LUT2 #(
    .INIT(4'hE)) 
    mem_reg_0_15_48_53_i_3__7
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12] ),
        .I1(mem_reg_0_15_36_41),
        .O(d_in[19]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_48_53_i_4
       (.I0(mc_address[34]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12] ),
        .I2(\phy_ctl_wd_i1_reg[0] ),
        .O(d_in[18]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_48_53_i_4__0
       (.I0(mem_reg_0_15_78_79[133]),
        .I1(phy_wrdata[189]),
        .I2(mem_reg_0_15_66_71),
        .O(\write_buffer.wr_buf_out_data_reg[455]_0 [42]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_48_53_i_4__1
       (.I0(mem_reg_0_15_78_79[140]),
        .I1(phy_wrdata[188]),
        .I2(mem_reg_0_15_66_71),
        .O(\write_buffer.wr_buf_out_data_reg[463]_0 [34]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_48_53_i_4__2
       (.I0(mem_reg_0_15_78_79[148]),
        .I1(phy_wrdata[188]),
        .I2(mem_reg_0_15_66_71),
        .O(\write_buffer.wr_buf_out_data_reg[471]_0 [34]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_48_53_i_4__3
       (.I0(mem_reg_0_15_78_79[156]),
        .I1(phy_wrdata[188]),
        .I2(mem_reg_0_15_66_71),
        .O(\write_buffer.wr_buf_out_data_reg[479]_0 [34]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_48_53_i_4__4
       (.I0(mem_reg_0_15_78_79[165]),
        .I1(phy_wrdata[189]),
        .I2(mem_reg_0_15_66_71),
        .O(\write_buffer.wr_buf_out_data_reg[487]_0 [42]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_48_53_i_4__5
       (.I0(mem_reg_0_15_78_79[172]),
        .I1(phy_wrdata[188]),
        .I2(mem_reg_0_15_66_71),
        .O(\write_buffer.wr_buf_out_data_reg[495]_0 [34]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_48_53_i_4__6
       (.I0(mem_reg_0_15_78_79[180]),
        .I1(phy_wrdata[188]),
        .I2(mem_reg_0_15_72_77),
        .O(\write_buffer.wr_buf_out_data_reg[503]_0 [34]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_48_53_i_4__7
       (.I0(mem_reg_0_15_78_79[188]),
        .I1(phy_wrdata[188]),
        .I2(mem_reg_0_15_72_77),
        .O(\write_buffer.wr_buf_out_data_reg[511]_0 [34]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_48_53_i_5
       (.I0(mc_address[12]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ),
        .I2(\phy_ctl_wd_i1_reg[0] ),
        .O(d_in[21]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_48_53_i_5__0
       (.I0(mem_reg_0_15_78_79[325]),
        .I1(phy_wrdata[381]),
        .I2(mem_reg_0_15_36_41_0),
        .O(\write_buffer.wr_buf_out_data_reg[455]_0 [45]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_48_53_i_5__1
       (.I0(mem_reg_0_15_78_79[332]),
        .I1(phy_wrdata[380]),
        .I2(mem_reg_0_15_36_41_0),
        .O(\write_buffer.wr_buf_out_data_reg[463]_0 [37]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_48_53_i_5__2
       (.I0(mem_reg_0_15_78_79[340]),
        .I1(phy_wrdata[380]),
        .I2(mem_reg_0_15_36_41_0),
        .O(\write_buffer.wr_buf_out_data_reg[471]_0 [37]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_48_53_i_5__3
       (.I0(mem_reg_0_15_78_79[348]),
        .I1(phy_wrdata[380]),
        .I2(mem_reg_0_15_36_41_0),
        .O(\write_buffer.wr_buf_out_data_reg[479]_0 [37]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_48_53_i_5__4
       (.I0(mem_reg_0_15_78_79[357]),
        .I1(phy_wrdata[381]),
        .I2(mem_reg_0_15_36_41_0),
        .O(\write_buffer.wr_buf_out_data_reg[487]_0 [45]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_48_53_i_5__5
       (.I0(mem_reg_0_15_78_79[364]),
        .I1(phy_wrdata[380]),
        .I2(mem_reg_0_15_36_41_0),
        .O(\write_buffer.wr_buf_out_data_reg[495]_0 [37]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_48_53_i_5__6
       (.I0(mem_reg_0_15_78_79[372]),
        .I1(phy_wrdata[380]),
        .I2(mem_reg_0_15_36_41_1),
        .O(\write_buffer.wr_buf_out_data_reg[503]_0 [37]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_48_53_i_5__7
       (.I0(mem_reg_0_15_78_79[380]),
        .I1(phy_wrdata[380]),
        .I2(mem_reg_0_15_36_41_1),
        .O(\write_buffer.wr_buf_out_data_reg[511]_0 [37]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_48_53_i_6
       (.I0(mc_address[0]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ),
        .I2(\phy_ctl_wd_i1_reg[0] ),
        .O(d_in[20]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_48_53_i_6__0
       (.I0(mem_reg_0_15_78_79[261]),
        .I1(phy_wrdata[317]),
        .I2(mem_reg_0_15_18_23),
        .O(\write_buffer.wr_buf_out_data_reg[455]_0 [44]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_48_53_i_6__1
       (.I0(mem_reg_0_15_78_79[268]),
        .I1(phy_wrdata[316]),
        .I2(mem_reg_0_15_18_23),
        .O(\write_buffer.wr_buf_out_data_reg[463]_0 [36]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_48_53_i_6__2
       (.I0(mem_reg_0_15_78_79[276]),
        .I1(phy_wrdata[316]),
        .I2(mem_reg_0_15_18_23_0),
        .O(\write_buffer.wr_buf_out_data_reg[471]_0 [36]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_48_53_i_6__3
       (.I0(mem_reg_0_15_78_79[284]),
        .I1(phy_wrdata[316]),
        .I2(mem_reg_0_15_18_23_0),
        .O(\write_buffer.wr_buf_out_data_reg[479]_0 [36]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_48_53_i_6__4
       (.I0(mem_reg_0_15_78_79[293]),
        .I1(phy_wrdata[317]),
        .I2(mem_reg_0_15_18_23_0),
        .O(\write_buffer.wr_buf_out_data_reg[487]_0 [44]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_48_53_i_6__5
       (.I0(mem_reg_0_15_78_79[300]),
        .I1(phy_wrdata[316]),
        .I2(mem_reg_0_15_18_23_0),
        .O(\write_buffer.wr_buf_out_data_reg[495]_0 [36]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_48_53_i_6__6
       (.I0(mem_reg_0_15_78_79[308]),
        .I1(phy_wrdata[316]),
        .I2(mem_reg_0_15_18_23_0),
        .O(\write_buffer.wr_buf_out_data_reg[503]_0 [36]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_48_53_i_6__7
       (.I0(mem_reg_0_15_78_79[316]),
        .I1(phy_wrdata[316]),
        .I2(mem_reg_0_15_18_23_0),
        .O(\write_buffer.wr_buf_out_data_reg[511]_0 [36]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_54_59_i_1
       (.I0(mem_reg_0_15_78_79[453]),
        .I1(phy_wrdata[509]),
        .I2(mem_reg_0_15_54_59_0),
        .O(\write_buffer.wr_buf_out_data_reg[455]_0 [47]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_54_59_i_1__0
       (.I0(mem_reg_0_15_78_79[460]),
        .I1(phy_wrdata[508]),
        .I2(mem_reg_0_15_54_59_0),
        .O(\write_buffer.wr_buf_out_data_reg[463]_0 [39]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_54_59_i_1__1
       (.I0(mem_reg_0_15_78_79[468]),
        .I1(phy_wrdata[508]),
        .I2(mem_reg_0_15_54_59_0),
        .O(\write_buffer.wr_buf_out_data_reg[471]_0 [39]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_54_59_i_1__2
       (.I0(mem_reg_0_15_78_79[476]),
        .I1(phy_wrdata[508]),
        .I2(mem_reg_0_15_78_79_0),
        .O(\write_buffer.wr_buf_out_data_reg[479]_0 [39]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_54_59_i_1__3
       (.I0(mem_reg_0_15_78_79[485]),
        .I1(phy_wrdata[509]),
        .I2(mem_reg_0_15_78_79_0),
        .O(\write_buffer.wr_buf_out_data_reg[487]_0 [47]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_54_59_i_1__4
       (.I0(mem_reg_0_15_78_79[492]),
        .I1(phy_wrdata[508]),
        .I2(mem_reg_0_15_78_79_0),
        .O(\write_buffer.wr_buf_out_data_reg[495]_0 [39]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_54_59_i_1__5
       (.I0(mem_reg_0_15_78_79[500]),
        .I1(phy_wrdata[508]),
        .I2(mem_reg_0_15_78_79_0),
        .O(\write_buffer.wr_buf_out_data_reg[503]_0 [39]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_54_59_i_1__6
       (.I0(mem_reg_0_15_78_79[508]),
        .I1(phy_wrdata[508]),
        .I2(mem_reg_0_15_78_79_0),
        .O(\write_buffer.wr_buf_out_data_reg[511]_0 [39]));
  LUT2 #(
    .INIT(4'hE)) 
    mem_reg_0_15_54_59_i_1__7
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ),
        .I1(\phy_ctl_wd_i1_reg[0] ),
        .O(d_in[23]));
  LUT2 #(
    .INIT(4'hE)) 
    mem_reg_0_15_54_59_i_1__8
       (.I0(phy_bank[9]),
        .I1(mem_reg_0_15_36_41),
        .O(phy_dout[15]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_54_59_i_2
       (.I0(mc_address[23]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ),
        .I2(\phy_ctl_wd_i1_reg[0] ),
        .O(d_in[22]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_54_59_i_2__0
       (.I0(mc_bank[6]),
        .I1(phy_bank[9]),
        .I2(mem_reg_0_15_36_41),
        .O(phy_dout[14]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_54_59_i_2__1
       (.I0(mem_reg_0_15_78_79[389]),
        .I1(phy_wrdata[445]),
        .I2(mem_reg_0_15_36_41_1),
        .O(\write_buffer.wr_buf_out_data_reg[455]_0 [46]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_54_59_i_2__2
       (.I0(mem_reg_0_15_78_79[396]),
        .I1(phy_wrdata[444]),
        .I2(mem_reg_0_15_36_41_1),
        .O(\write_buffer.wr_buf_out_data_reg[463]_0 [38]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_54_59_i_2__3
       (.I0(mem_reg_0_15_78_79[404]),
        .I1(phy_wrdata[444]),
        .I2(mem_reg_0_15_36_41_1),
        .O(\write_buffer.wr_buf_out_data_reg[471]_0 [38]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_54_59_i_2__4
       (.I0(mem_reg_0_15_78_79[412]),
        .I1(phy_wrdata[444]),
        .I2(mem_reg_0_15_36_41_1),
        .O(\write_buffer.wr_buf_out_data_reg[479]_0 [38]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_54_59_i_2__5
       (.I0(mem_reg_0_15_78_79[421]),
        .I1(phy_wrdata[445]),
        .I2(mem_reg_0_15_54_59_0),
        .O(\write_buffer.wr_buf_out_data_reg[487]_0 [46]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_54_59_i_2__6
       (.I0(mem_reg_0_15_78_79[428]),
        .I1(phy_wrdata[444]),
        .I2(mem_reg_0_15_54_59_0),
        .O(\write_buffer.wr_buf_out_data_reg[495]_0 [38]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_54_59_i_2__7
       (.I0(mem_reg_0_15_78_79[436]),
        .I1(phy_wrdata[444]),
        .I2(mem_reg_0_15_54_59_0),
        .O(\write_buffer.wr_buf_out_data_reg[503]_0 [38]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_54_59_i_2__8
       (.I0(mem_reg_0_15_78_79[444]),
        .I1(phy_wrdata[444]),
        .I2(mem_reg_0_15_54_59_0),
        .O(\write_buffer.wr_buf_out_data_reg[511]_0 [38]));
  LUT3 #(
    .INIT(8'hB8)) 
    mem_reg_0_15_54_59_i_2__9
       (.I0(mc_cke),
        .I1(phy_ctl_wr_i1_reg),
        .I2(calib_cke),
        .O(\cmd_pipe_plus.mc_cke_reg[3]_0 [5]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_54_59_i_3
       (.I0(mc_address[17]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ),
        .I2(\phy_ctl_wd_i1_reg[0] ),
        .O(d_in[25]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_54_59_i_3__0
       (.I0(mem_reg_0_15_78_79[70]),
        .I1(phy_wrdata[126]),
        .I2(mem_reg_0_15_48_53),
        .O(\write_buffer.wr_buf_out_data_reg[455]_0 [49]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_54_59_i_3__1
       (.I0(mem_reg_0_15_78_79[77]),
        .I1(phy_wrdata[125]),
        .I2(mem_reg_0_15_54_59),
        .O(\write_buffer.wr_buf_out_data_reg[463]_0 [41]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_54_59_i_3__2
       (.I0(mem_reg_0_15_78_79[85]),
        .I1(phy_wrdata[125]),
        .I2(mem_reg_0_15_54_59),
        .O(\write_buffer.wr_buf_out_data_reg[471]_0 [41]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_54_59_i_3__3
       (.I0(mem_reg_0_15_78_79[93]),
        .I1(phy_wrdata[125]),
        .I2(mem_reg_0_15_54_59),
        .O(\write_buffer.wr_buf_out_data_reg[479]_0 [41]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_54_59_i_3__4
       (.I0(mem_reg_0_15_78_79[102]),
        .I1(phy_wrdata[126]),
        .I2(mem_reg_0_15_54_59),
        .O(\write_buffer.wr_buf_out_data_reg[487]_0 [49]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_54_59_i_3__5
       (.I0(mem_reg_0_15_78_79[109]),
        .I1(phy_wrdata[125]),
        .I2(mem_reg_0_15_54_59),
        .O(\write_buffer.wr_buf_out_data_reg[495]_0 [41]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_54_59_i_3__6
       (.I0(mem_reg_0_15_78_79[117]),
        .I1(phy_wrdata[125]),
        .I2(mem_reg_0_15_54_59),
        .O(\write_buffer.wr_buf_out_data_reg[503]_0 [41]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_54_59_i_3__7
       (.I0(mem_reg_0_15_78_79[125]),
        .I1(phy_wrdata[125]),
        .I2(mem_reg_0_15_54_59),
        .O(\write_buffer.wr_buf_out_data_reg[511]_0 [41]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_54_59_i_4
       (.I0(mc_address[5]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ),
        .I2(\phy_ctl_wd_i1_reg[0] ),
        .O(d_in[24]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_54_59_i_4__0
       (.I0(mem_reg_0_15_78_79[6]),
        .I1(phy_wrdata[62]),
        .I2(mem_reg_0_15_36_41),
        .O(\write_buffer.wr_buf_out_data_reg[455]_0 [48]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_54_59_i_4__1
       (.I0(mem_reg_0_15_78_79[13]),
        .I1(phy_wrdata[61]),
        .I2(mem_reg_0_15_36_41),
        .O(\write_buffer.wr_buf_out_data_reg[463]_0 [40]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_54_59_i_4__2
       (.I0(mem_reg_0_15_78_79[21]),
        .I1(phy_wrdata[61]),
        .I2(mem_reg_0_15_36_41),
        .O(\write_buffer.wr_buf_out_data_reg[471]_0 [40]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_54_59_i_4__3
       (.I0(mem_reg_0_15_78_79[29]),
        .I1(phy_wrdata[61]),
        .I2(mem_reg_0_15_48_53),
        .O(\write_buffer.wr_buf_out_data_reg[479]_0 [40]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_54_59_i_4__4
       (.I0(mem_reg_0_15_78_79[38]),
        .I1(phy_wrdata[62]),
        .I2(mem_reg_0_15_48_53),
        .O(\write_buffer.wr_buf_out_data_reg[487]_0 [48]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_54_59_i_4__5
       (.I0(mem_reg_0_15_78_79[45]),
        .I1(phy_wrdata[61]),
        .I2(mem_reg_0_15_48_53),
        .O(\write_buffer.wr_buf_out_data_reg[495]_0 [40]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_54_59_i_4__6
       (.I0(mem_reg_0_15_78_79[53]),
        .I1(phy_wrdata[61]),
        .I2(mem_reg_0_15_48_53),
        .O(\write_buffer.wr_buf_out_data_reg[503]_0 [40]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_54_59_i_4__7
       (.I0(mem_reg_0_15_78_79[61]),
        .I1(phy_wrdata[61]),
        .I2(mem_reg_0_15_48_53),
        .O(\write_buffer.wr_buf_out_data_reg[511]_0 [40]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_54_59_i_5
       (.I0(mem_reg_0_15_78_79[198]),
        .I1(phy_wrdata[254]),
        .I2(mem_reg_0_15_72_77),
        .O(\write_buffer.wr_buf_out_data_reg[455]_0 [51]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_54_59_i_5__0
       (.I0(mem_reg_0_15_78_79[205]),
        .I1(phy_wrdata[253]),
        .I2(mem_reg_0_15_72_77),
        .O(\write_buffer.wr_buf_out_data_reg[463]_0 [43]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_54_59_i_5__1
       (.I0(mem_reg_0_15_78_79[213]),
        .I1(phy_wrdata[253]),
        .I2(mem_reg_0_15_72_77),
        .O(\write_buffer.wr_buf_out_data_reg[471]_0 [43]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_54_59_i_5__2
       (.I0(mem_reg_0_15_78_79[221]),
        .I1(phy_wrdata[253]),
        .I2(mem_reg_0_15_72_77),
        .O(\write_buffer.wr_buf_out_data_reg[479]_0 [43]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_54_59_i_5__3
       (.I0(mem_reg_0_15_78_79[230]),
        .I1(phy_wrdata[254]),
        .I2(mem_reg_0_15_18_23),
        .O(\write_buffer.wr_buf_out_data_reg[487]_0 [51]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_54_59_i_5__4
       (.I0(mem_reg_0_15_78_79[237]),
        .I1(phy_wrdata[253]),
        .I2(mem_reg_0_15_18_23),
        .O(\write_buffer.wr_buf_out_data_reg[495]_0 [43]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_54_59_i_5__5
       (.I0(mem_reg_0_15_78_79[245]),
        .I1(phy_wrdata[253]),
        .I2(mem_reg_0_15_18_23),
        .O(\write_buffer.wr_buf_out_data_reg[503]_0 [43]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_54_59_i_5__6
       (.I0(mem_reg_0_15_78_79[253]),
        .I1(phy_wrdata[253]),
        .I2(mem_reg_0_15_18_23),
        .O(\write_buffer.wr_buf_out_data_reg[511]_0 [43]));
  LUT2 #(
    .INIT(4'hE)) 
    mem_reg_0_15_54_59_i_5__7
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ),
        .I1(mem_reg_0_15_36_41),
        .O(d_in[27]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_54_59_i_6
       (.I0(mc_address[28]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ),
        .I2(\phy_ctl_wd_i1_reg[0] ),
        .O(d_in[26]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_54_59_i_6__0
       (.I0(mem_reg_0_15_78_79[134]),
        .I1(phy_wrdata[190]),
        .I2(mem_reg_0_15_66_71),
        .O(\write_buffer.wr_buf_out_data_reg[455]_0 [50]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_54_59_i_6__1
       (.I0(mem_reg_0_15_78_79[141]),
        .I1(phy_wrdata[189]),
        .I2(mem_reg_0_15_66_71),
        .O(\write_buffer.wr_buf_out_data_reg[463]_0 [42]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_54_59_i_6__2
       (.I0(mem_reg_0_15_78_79[149]),
        .I1(phy_wrdata[189]),
        .I2(mem_reg_0_15_66_71),
        .O(\write_buffer.wr_buf_out_data_reg[471]_0 [42]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_54_59_i_6__3
       (.I0(mem_reg_0_15_78_79[157]),
        .I1(phy_wrdata[189]),
        .I2(mem_reg_0_15_66_71),
        .O(\write_buffer.wr_buf_out_data_reg[479]_0 [42]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_54_59_i_6__4
       (.I0(mem_reg_0_15_78_79[166]),
        .I1(phy_wrdata[190]),
        .I2(mem_reg_0_15_66_71),
        .O(\write_buffer.wr_buf_out_data_reg[487]_0 [50]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_54_59_i_6__5
       (.I0(mem_reg_0_15_78_79[173]),
        .I1(phy_wrdata[189]),
        .I2(mem_reg_0_15_66_71),
        .O(\write_buffer.wr_buf_out_data_reg[495]_0 [42]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_54_59_i_6__6
       (.I0(mem_reg_0_15_78_79[181]),
        .I1(phy_wrdata[189]),
        .I2(mem_reg_0_15_72_77),
        .O(\write_buffer.wr_buf_out_data_reg[503]_0 [42]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_54_59_i_6__7
       (.I0(mem_reg_0_15_78_79[189]),
        .I1(phy_wrdata[189]),
        .I2(mem_reg_0_15_72_77),
        .O(\write_buffer.wr_buf_out_data_reg[511]_0 [42]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_60_65_i_1
       (.I0(mc_address[13]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ),
        .I2(\phy_ctl_wd_i1_reg[0] ),
        .O(d_in[29]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_60_65_i_1__0
       (.I0(mc_address[14]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ),
        .I2(\phy_ctl_wd_i1_reg[0] ),
        .O(phy_dout[17]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_60_65_i_1__1
       (.I0(mem_reg_0_15_78_79[326]),
        .I1(phy_wrdata[382]),
        .I2(mem_reg_0_15_36_41_0),
        .O(\write_buffer.wr_buf_out_data_reg[455]_0 [53]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_60_65_i_1__2
       (.I0(mem_reg_0_15_78_79[333]),
        .I1(phy_wrdata[381]),
        .I2(mem_reg_0_15_36_41_0),
        .O(\write_buffer.wr_buf_out_data_reg[463]_0 [45]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_60_65_i_1__3
       (.I0(mem_reg_0_15_78_79[341]),
        .I1(phy_wrdata[381]),
        .I2(mem_reg_0_15_36_41_0),
        .O(\write_buffer.wr_buf_out_data_reg[471]_0 [45]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_60_65_i_1__4
       (.I0(mem_reg_0_15_78_79[349]),
        .I1(phy_wrdata[381]),
        .I2(mem_reg_0_15_36_41_0),
        .O(\write_buffer.wr_buf_out_data_reg[479]_0 [45]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_60_65_i_1__5
       (.I0(mem_reg_0_15_78_79[358]),
        .I1(phy_wrdata[382]),
        .I2(mem_reg_0_15_36_41_0),
        .O(\write_buffer.wr_buf_out_data_reg[487]_0 [53]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_60_65_i_1__6
       (.I0(mem_reg_0_15_78_79[365]),
        .I1(phy_wrdata[381]),
        .I2(mem_reg_0_15_36_41_0),
        .O(\write_buffer.wr_buf_out_data_reg[495]_0 [45]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_60_65_i_1__7
       (.I0(mem_reg_0_15_78_79[373]),
        .I1(phy_wrdata[381]),
        .I2(mem_reg_0_15_36_41_1),
        .O(\write_buffer.wr_buf_out_data_reg[503]_0 [45]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_60_65_i_1__8
       (.I0(mem_reg_0_15_78_79[381]),
        .I1(phy_wrdata[381]),
        .I2(mem_reg_0_15_36_41_1),
        .O(\write_buffer.wr_buf_out_data_reg[511]_0 [45]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_60_65_i_2
       (.I0(mc_address[1]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ),
        .I2(\phy_ctl_wd_i1_reg[0] ),
        .O(d_in[28]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_60_65_i_2__0
       (.I0(mc_address[2]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ),
        .I2(\phy_ctl_wd_i1_reg[0] ),
        .O(phy_dout[16]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_60_65_i_2__1
       (.I0(mem_reg_0_15_78_79[262]),
        .I1(phy_wrdata[318]),
        .I2(mem_reg_0_15_18_23),
        .O(\write_buffer.wr_buf_out_data_reg[455]_0 [52]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_60_65_i_2__2
       (.I0(mem_reg_0_15_78_79[269]),
        .I1(phy_wrdata[317]),
        .I2(mem_reg_0_15_18_23),
        .O(\write_buffer.wr_buf_out_data_reg[463]_0 [44]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_60_65_i_2__3
       (.I0(mem_reg_0_15_78_79[277]),
        .I1(phy_wrdata[317]),
        .I2(mem_reg_0_15_18_23_0),
        .O(\write_buffer.wr_buf_out_data_reg[471]_0 [44]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_60_65_i_2__4
       (.I0(mem_reg_0_15_78_79[285]),
        .I1(phy_wrdata[317]),
        .I2(mem_reg_0_15_18_23_0),
        .O(\write_buffer.wr_buf_out_data_reg[479]_0 [44]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_60_65_i_2__5
       (.I0(mem_reg_0_15_78_79[294]),
        .I1(phy_wrdata[318]),
        .I2(mem_reg_0_15_18_23_0),
        .O(\write_buffer.wr_buf_out_data_reg[487]_0 [52]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_60_65_i_2__6
       (.I0(mem_reg_0_15_78_79[301]),
        .I1(phy_wrdata[317]),
        .I2(mem_reg_0_15_18_23_0),
        .O(\write_buffer.wr_buf_out_data_reg[495]_0 [44]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_60_65_i_2__7
       (.I0(mem_reg_0_15_78_79[309]),
        .I1(phy_wrdata[317]),
        .I2(mem_reg_0_15_18_23_0),
        .O(\write_buffer.wr_buf_out_data_reg[503]_0 [44]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_60_65_i_2__8
       (.I0(mem_reg_0_15_78_79[317]),
        .I1(phy_wrdata[317]),
        .I2(mem_reg_0_15_18_23_0),
        .O(\write_buffer.wr_buf_out_data_reg[511]_0 [44]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_60_65_i_3
       (.I0(mem_reg_0_15_78_79[454]),
        .I1(phy_wrdata[510]),
        .I2(mem_reg_0_15_54_59_0),
        .O(\write_buffer.wr_buf_out_data_reg[455]_0 [55]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_60_65_i_3__0
       (.I0(mem_reg_0_15_78_79[461]),
        .I1(phy_wrdata[509]),
        .I2(mem_reg_0_15_54_59_0),
        .O(\write_buffer.wr_buf_out_data_reg[463]_0 [47]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_60_65_i_3__1
       (.I0(mem_reg_0_15_78_79[469]),
        .I1(phy_wrdata[509]),
        .I2(mem_reg_0_15_78_79_0),
        .O(\write_buffer.wr_buf_out_data_reg[471]_0 [47]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_60_65_i_3__2
       (.I0(mem_reg_0_15_78_79[477]),
        .I1(phy_wrdata[509]),
        .I2(mem_reg_0_15_78_79_0),
        .O(\write_buffer.wr_buf_out_data_reg[479]_0 [47]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_60_65_i_3__3
       (.I0(mem_reg_0_15_78_79[486]),
        .I1(phy_wrdata[510]),
        .I2(mem_reg_0_15_78_79_0),
        .O(\write_buffer.wr_buf_out_data_reg[487]_0 [55]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_60_65_i_3__4
       (.I0(mem_reg_0_15_78_79[493]),
        .I1(phy_wrdata[509]),
        .I2(mem_reg_0_15_78_79_0),
        .O(\write_buffer.wr_buf_out_data_reg[495]_0 [47]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_60_65_i_3__5
       (.I0(mem_reg_0_15_78_79[501]),
        .I1(phy_wrdata[509]),
        .I2(mem_reg_0_15_78_79_0),
        .O(\write_buffer.wr_buf_out_data_reg[503]_0 [47]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_60_65_i_3__6
       (.I0(mem_reg_0_15_78_79[509]),
        .I1(phy_wrdata[509]),
        .I2(mem_reg_0_15_78_79_0),
        .O(\write_buffer.wr_buf_out_data_reg[511]_0 [47]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_60_65_i_4
       (.I0(mem_reg_0_15_78_79[390]),
        .I1(phy_wrdata[446]),
        .I2(mem_reg_0_15_36_41_1),
        .O(\write_buffer.wr_buf_out_data_reg[455]_0 [54]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_60_65_i_4__0
       (.I0(mem_reg_0_15_78_79[397]),
        .I1(phy_wrdata[445]),
        .I2(mem_reg_0_15_36_41_1),
        .O(\write_buffer.wr_buf_out_data_reg[463]_0 [46]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_60_65_i_4__1
       (.I0(mem_reg_0_15_78_79[405]),
        .I1(phy_wrdata[445]),
        .I2(mem_reg_0_15_36_41_1),
        .O(\write_buffer.wr_buf_out_data_reg[471]_0 [46]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_60_65_i_4__2
       (.I0(mem_reg_0_15_78_79[413]),
        .I1(phy_wrdata[445]),
        .I2(mem_reg_0_15_36_41_1),
        .O(\write_buffer.wr_buf_out_data_reg[479]_0 [46]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_60_65_i_4__3
       (.I0(mem_reg_0_15_78_79[422]),
        .I1(phy_wrdata[446]),
        .I2(mem_reg_0_15_54_59_0),
        .O(\write_buffer.wr_buf_out_data_reg[487]_0 [54]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_60_65_i_4__4
       (.I0(mem_reg_0_15_78_79[429]),
        .I1(phy_wrdata[445]),
        .I2(mem_reg_0_15_54_59_0),
        .O(\write_buffer.wr_buf_out_data_reg[495]_0 [46]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_60_65_i_4__5
       (.I0(mem_reg_0_15_78_79[437]),
        .I1(phy_wrdata[445]),
        .I2(mem_reg_0_15_54_59_0),
        .O(\write_buffer.wr_buf_out_data_reg[503]_0 [46]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_60_65_i_4__6
       (.I0(mem_reg_0_15_78_79[445]),
        .I1(phy_wrdata[445]),
        .I2(mem_reg_0_15_54_59_0),
        .O(\write_buffer.wr_buf_out_data_reg[511]_0 [46]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_60_65_i_5
       (.I0(mem_reg_0_15_78_79[78]),
        .I1(phy_wrdata[126]),
        .I2(mem_reg_0_15_54_59),
        .O(\write_buffer.wr_buf_out_data_reg[463]_0 [49]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_60_65_i_5__0
       (.I0(mem_reg_0_15_78_79[86]),
        .I1(phy_wrdata[126]),
        .I2(mem_reg_0_15_54_59),
        .O(\write_buffer.wr_buf_out_data_reg[471]_0 [49]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_60_65_i_5__1
       (.I0(mem_reg_0_15_78_79[94]),
        .I1(phy_wrdata[126]),
        .I2(mem_reg_0_15_54_59),
        .O(\write_buffer.wr_buf_out_data_reg[479]_0 [49]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_60_65_i_5__2
       (.I0(mem_reg_0_15_78_79[110]),
        .I1(phy_wrdata[126]),
        .I2(mem_reg_0_15_54_59),
        .O(\write_buffer.wr_buf_out_data_reg[495]_0 [49]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_60_65_i_5__3
       (.I0(mem_reg_0_15_78_79[118]),
        .I1(phy_wrdata[126]),
        .I2(mem_reg_0_15_54_59),
        .O(\write_buffer.wr_buf_out_data_reg[503]_0 [49]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_60_65_i_5__4
       (.I0(mem_reg_0_15_78_79[126]),
        .I1(phy_wrdata[126]),
        .I2(mem_reg_0_15_66_71),
        .O(\write_buffer.wr_buf_out_data_reg[511]_0 [49]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_60_65_i_6
       (.I0(mem_reg_0_15_78_79[14]),
        .I1(phy_wrdata[62]),
        .I2(mem_reg_0_15_36_41),
        .O(\write_buffer.wr_buf_out_data_reg[463]_0 [48]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_60_65_i_6__0
       (.I0(mem_reg_0_15_78_79[22]),
        .I1(phy_wrdata[62]),
        .I2(mem_reg_0_15_36_41),
        .O(\write_buffer.wr_buf_out_data_reg[471]_0 [48]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_60_65_i_6__1
       (.I0(mem_reg_0_15_78_79[30]),
        .I1(phy_wrdata[62]),
        .I2(mem_reg_0_15_48_53),
        .O(\write_buffer.wr_buf_out_data_reg[479]_0 [48]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_60_65_i_6__2
       (.I0(mem_reg_0_15_78_79[46]),
        .I1(phy_wrdata[62]),
        .I2(mem_reg_0_15_48_53),
        .O(\write_buffer.wr_buf_out_data_reg[495]_0 [48]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_60_65_i_6__3
       (.I0(mem_reg_0_15_78_79[54]),
        .I1(phy_wrdata[62]),
        .I2(mem_reg_0_15_48_53),
        .O(\write_buffer.wr_buf_out_data_reg[503]_0 [48]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_60_65_i_6__4
       (.I0(mem_reg_0_15_78_79[62]),
        .I1(phy_wrdata[62]),
        .I2(mem_reg_0_15_48_53),
        .O(\write_buffer.wr_buf_out_data_reg[511]_0 [48]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_66_71_i_1
       (.I0(mem_reg_0_15_78_79[206]),
        .I1(phy_wrdata[254]),
        .I2(mem_reg_0_15_72_77),
        .O(\write_buffer.wr_buf_out_data_reg[463]_0 [51]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_66_71_i_1__0
       (.I0(mem_reg_0_15_78_79[214]),
        .I1(phy_wrdata[254]),
        .I2(mem_reg_0_15_72_77),
        .O(\write_buffer.wr_buf_out_data_reg[471]_0 [51]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_66_71_i_1__1
       (.I0(mem_reg_0_15_78_79[222]),
        .I1(phy_wrdata[254]),
        .I2(mem_reg_0_15_72_77),
        .O(\write_buffer.wr_buf_out_data_reg[479]_0 [51]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_66_71_i_1__2
       (.I0(mem_reg_0_15_78_79[238]),
        .I1(phy_wrdata[254]),
        .I2(mem_reg_0_15_18_23),
        .O(\write_buffer.wr_buf_out_data_reg[495]_0 [51]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_66_71_i_1__3
       (.I0(mem_reg_0_15_78_79[246]),
        .I1(phy_wrdata[254]),
        .I2(mem_reg_0_15_18_23),
        .O(\write_buffer.wr_buf_out_data_reg[503]_0 [51]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_66_71_i_1__4
       (.I0(mem_reg_0_15_78_79[254]),
        .I1(phy_wrdata[254]),
        .I2(mem_reg_0_15_18_23),
        .O(\write_buffer.wr_buf_out_data_reg[511]_0 [51]));
  LUT2 #(
    .INIT(4'hE)) 
    mem_reg_0_15_66_71_i_1__5
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ),
        .I1(\phy_ctl_wd_i1_reg[0] ),
        .O(d_in[31]));
  LUT2 #(
    .INIT(4'hE)) 
    mem_reg_0_15_66_71_i_1__6
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ),
        .I1(\phy_ctl_wd_i1_reg[0] ),
        .O(phy_dout[19]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_66_71_i_2
       (.I0(mc_address[24]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ),
        .I2(\phy_ctl_wd_i1_reg[0] ),
        .O(d_in[30]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_66_71_i_2__0
       (.I0(mc_address[25]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ),
        .I2(\phy_ctl_wd_i1_reg[0] ),
        .O(phy_dout[18]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_66_71_i_2__1
       (.I0(mem_reg_0_15_78_79[142]),
        .I1(phy_wrdata[190]),
        .I2(mem_reg_0_15_66_71),
        .O(\write_buffer.wr_buf_out_data_reg[463]_0 [50]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_66_71_i_2__2
       (.I0(mem_reg_0_15_78_79[150]),
        .I1(phy_wrdata[190]),
        .I2(mem_reg_0_15_66_71),
        .O(\write_buffer.wr_buf_out_data_reg[471]_0 [50]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_66_71_i_2__3
       (.I0(mem_reg_0_15_78_79[158]),
        .I1(phy_wrdata[190]),
        .I2(mem_reg_0_15_66_71),
        .O(\write_buffer.wr_buf_out_data_reg[479]_0 [50]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_66_71_i_2__4
       (.I0(mem_reg_0_15_78_79[174]),
        .I1(phy_wrdata[190]),
        .I2(mem_reg_0_15_66_71),
        .O(\write_buffer.wr_buf_out_data_reg[495]_0 [50]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_66_71_i_2__5
       (.I0(mem_reg_0_15_78_79[182]),
        .I1(phy_wrdata[190]),
        .I2(mem_reg_0_15_72_77),
        .O(\write_buffer.wr_buf_out_data_reg[503]_0 [50]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_66_71_i_2__6
       (.I0(mem_reg_0_15_78_79[190]),
        .I1(phy_wrdata[190]),
        .I2(mem_reg_0_15_72_77),
        .O(\write_buffer.wr_buf_out_data_reg[511]_0 [50]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_66_71_i_3
       (.I0(mem_reg_0_15_78_79[334]),
        .I1(phy_wrdata[382]),
        .I2(mem_reg_0_15_36_41_0),
        .O(\write_buffer.wr_buf_out_data_reg[463]_0 [53]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_66_71_i_3__0
       (.I0(mem_reg_0_15_78_79[342]),
        .I1(phy_wrdata[382]),
        .I2(mem_reg_0_15_36_41_0),
        .O(\write_buffer.wr_buf_out_data_reg[471]_0 [53]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_66_71_i_3__1
       (.I0(mem_reg_0_15_78_79[350]),
        .I1(phy_wrdata[382]),
        .I2(mem_reg_0_15_36_41_0),
        .O(\write_buffer.wr_buf_out_data_reg[479]_0 [53]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_66_71_i_3__2
       (.I0(mem_reg_0_15_78_79[366]),
        .I1(phy_wrdata[382]),
        .I2(mem_reg_0_15_36_41_0),
        .O(\write_buffer.wr_buf_out_data_reg[495]_0 [53]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_66_71_i_3__3
       (.I0(mem_reg_0_15_78_79[374]),
        .I1(phy_wrdata[382]),
        .I2(mem_reg_0_15_36_41_1),
        .O(\write_buffer.wr_buf_out_data_reg[503]_0 [53]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_66_71_i_3__4
       (.I0(mem_reg_0_15_78_79[382]),
        .I1(phy_wrdata[382]),
        .I2(mem_reg_0_15_36_41_1),
        .O(\write_buffer.wr_buf_out_data_reg[511]_0 [53]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_66_71_i_4
       (.I0(mem_reg_0_15_78_79[270]),
        .I1(phy_wrdata[318]),
        .I2(mem_reg_0_15_18_23),
        .O(\write_buffer.wr_buf_out_data_reg[463]_0 [52]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_66_71_i_4__0
       (.I0(mem_reg_0_15_78_79[278]),
        .I1(phy_wrdata[318]),
        .I2(mem_reg_0_15_18_23_0),
        .O(\write_buffer.wr_buf_out_data_reg[471]_0 [52]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_66_71_i_4__1
       (.I0(mem_reg_0_15_78_79[286]),
        .I1(phy_wrdata[318]),
        .I2(mem_reg_0_15_18_23_0),
        .O(\write_buffer.wr_buf_out_data_reg[479]_0 [52]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_66_71_i_4__2
       (.I0(mem_reg_0_15_78_79[302]),
        .I1(phy_wrdata[318]),
        .I2(mem_reg_0_15_18_23_0),
        .O(\write_buffer.wr_buf_out_data_reg[495]_0 [52]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_66_71_i_4__3
       (.I0(mem_reg_0_15_78_79[310]),
        .I1(phy_wrdata[318]),
        .I2(mem_reg_0_15_18_23_0),
        .O(\write_buffer.wr_buf_out_data_reg[503]_0 [52]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_66_71_i_4__4
       (.I0(mem_reg_0_15_78_79[318]),
        .I1(phy_wrdata[318]),
        .I2(mem_reg_0_15_18_23_0),
        .O(\write_buffer.wr_buf_out_data_reg[511]_0 [52]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_66_71_i_5
       (.I0(mem_reg_0_15_78_79[462]),
        .I1(phy_wrdata[510]),
        .I2(mem_reg_0_15_54_59_0),
        .O(\write_buffer.wr_buf_out_data_reg[463]_0 [55]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_66_71_i_5__0
       (.I0(mem_reg_0_15_78_79[470]),
        .I1(phy_wrdata[510]),
        .I2(mem_reg_0_15_78_79_0),
        .O(\write_buffer.wr_buf_out_data_reg[471]_0 [55]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_66_71_i_5__1
       (.I0(mem_reg_0_15_78_79[478]),
        .I1(phy_wrdata[510]),
        .I2(mem_reg_0_15_78_79_0),
        .O(\write_buffer.wr_buf_out_data_reg[479]_0 [55]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_66_71_i_5__2
       (.I0(mem_reg_0_15_78_79[494]),
        .I1(phy_wrdata[510]),
        .I2(mem_reg_0_15_78_79_0),
        .O(\write_buffer.wr_buf_out_data_reg[495]_0 [55]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_66_71_i_5__3
       (.I0(mem_reg_0_15_78_79[502]),
        .I1(phy_wrdata[510]),
        .I2(mem_reg_0_15_78_79_0),
        .O(\write_buffer.wr_buf_out_data_reg[503]_0 [55]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_66_71_i_5__4
       (.I0(mem_reg_0_15_78_79[510]),
        .I1(phy_wrdata[510]),
        .I2(mem_reg_0_15_78_79_0),
        .O(\write_buffer.wr_buf_out_data_reg[511]_0 [55]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_66_71_i_6
       (.I0(mem_reg_0_15_78_79[398]),
        .I1(phy_wrdata[446]),
        .I2(mem_reg_0_15_36_41_1),
        .O(\write_buffer.wr_buf_out_data_reg[463]_0 [54]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_66_71_i_6__0
       (.I0(mem_reg_0_15_78_79[406]),
        .I1(phy_wrdata[446]),
        .I2(mem_reg_0_15_36_41_1),
        .O(\write_buffer.wr_buf_out_data_reg[471]_0 [54]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_66_71_i_6__1
       (.I0(mem_reg_0_15_78_79[414]),
        .I1(phy_wrdata[446]),
        .I2(mem_reg_0_15_36_41_1),
        .O(\write_buffer.wr_buf_out_data_reg[479]_0 [54]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_66_71_i_6__2
       (.I0(mem_reg_0_15_78_79[430]),
        .I1(phy_wrdata[446]),
        .I2(mem_reg_0_15_54_59_0),
        .O(\write_buffer.wr_buf_out_data_reg[495]_0 [54]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_66_71_i_6__3
       (.I0(mem_reg_0_15_78_79[438]),
        .I1(phy_wrdata[446]),
        .I2(mem_reg_0_15_54_59_0),
        .O(\write_buffer.wr_buf_out_data_reg[503]_0 [54]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_66_71_i_6__4
       (.I0(mem_reg_0_15_78_79[446]),
        .I1(phy_wrdata[446]),
        .I2(mem_reg_0_15_54_59_0),
        .O(\write_buffer.wr_buf_out_data_reg[511]_0 [54]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_6_11_i_1
       (.I0(mc_address[19]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ),
        .I2(\phy_ctl_wd_i1_reg[0] ),
        .O(d_in[1]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_6_11_i_2
       (.I0(mc_address[7]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ),
        .I2(\phy_ctl_wd_i1_reg[0] ),
        .O(d_in[0]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_6_11_i_3
       (.I0(mem_reg_0_15_78_79[64]),
        .I1(phy_wrdata[120]),
        .I2(mem_reg_0_15_48_53),
        .O(\write_buffer.wr_buf_out_data_reg[455]_0 [1]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_6_11_i_3__0
       (.I0(mem_reg_0_15_78_79[96]),
        .I1(phy_wrdata[120]),
        .I2(mem_reg_0_15_54_59),
        .O(\write_buffer.wr_buf_out_data_reg[487]_0 [1]));
  LUT2 #(
    .INIT(4'hE)) 
    mem_reg_0_15_6_11_i_3__1
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ),
        .I1(mem_reg_0_15_36_41),
        .O(d_in[3]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_6_11_i_4
       (.I0(mc_address[30]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ),
        .I2(\phy_ctl_wd_i1_reg[0] ),
        .O(d_in[2]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_6_11_i_4__0
       (.I0(mem_reg_0_15_78_79[0]),
        .I1(phy_wrdata[56]),
        .I2(mem_reg_0_15_36_41),
        .O(\write_buffer.wr_buf_out_data_reg[455]_0 [0]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_6_11_i_4__1
       (.I0(mem_reg_0_15_78_79[32]),
        .I1(phy_wrdata[56]),
        .I2(mem_reg_0_15_48_53),
        .O(\write_buffer.wr_buf_out_data_reg[487]_0 [0]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_6_11_i_5
       (.I0(mem_reg_0_15_78_79[192]),
        .I1(phy_wrdata[248]),
        .I2(mem_reg_0_15_72_77),
        .O(\write_buffer.wr_buf_out_data_reg[455]_0 [3]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_6_11_i_5__0
       (.I0(mem_reg_0_15_78_79[224]),
        .I1(phy_wrdata[248]),
        .I2(mem_reg_0_15_18_23),
        .O(\write_buffer.wr_buf_out_data_reg[487]_0 [3]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_6_11_i_6
       (.I0(mem_reg_0_15_78_79[128]),
        .I1(phy_wrdata[184]),
        .I2(mem_reg_0_15_66_71),
        .O(\write_buffer.wr_buf_out_data_reg[455]_0 [2]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_6_11_i_6__0
       (.I0(mem_reg_0_15_78_79[160]),
        .I1(phy_wrdata[184]),
        .I2(mem_reg_0_15_66_71),
        .O(\write_buffer.wr_buf_out_data_reg[487]_0 [2]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_72_77_i_1
       (.I0(mc_address[18]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ),
        .I2(\phy_ctl_wd_i1_reg[0] ),
        .O(phy_dout[21]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_72_77_i_1__0
       (.I0(mc_address[21]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9] ),
        .I2(\phy_ctl_wd_i1_reg[0] ),
        .O(d_in[33]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_72_77_i_1__1
       (.I0(mem_reg_0_15_78_79[71]),
        .I1(phy_wrdata[127]),
        .I2(mem_reg_0_15_48_53),
        .O(\write_buffer.wr_buf_out_data_reg[455]_0 [57]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_72_77_i_1__2
       (.I0(mem_reg_0_15_78_79[79]),
        .I1(phy_wrdata[127]),
        .I2(mem_reg_0_15_54_59),
        .O(\write_buffer.wr_buf_out_data_reg[463]_0 [57]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_72_77_i_1__3
       (.I0(mem_reg_0_15_78_79[87]),
        .I1(phy_wrdata[127]),
        .I2(mem_reg_0_15_54_59),
        .O(\write_buffer.wr_buf_out_data_reg[471]_0 [57]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_72_77_i_1__4
       (.I0(mem_reg_0_15_78_79[95]),
        .I1(phy_wrdata[127]),
        .I2(mem_reg_0_15_54_59),
        .O(\write_buffer.wr_buf_out_data_reg[479]_0 [57]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_72_77_i_1__5
       (.I0(mem_reg_0_15_78_79[103]),
        .I1(phy_wrdata[127]),
        .I2(mem_reg_0_15_54_59),
        .O(\write_buffer.wr_buf_out_data_reg[487]_0 [57]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_72_77_i_1__6
       (.I0(mem_reg_0_15_78_79[111]),
        .I1(phy_wrdata[127]),
        .I2(mem_reg_0_15_54_59),
        .O(\write_buffer.wr_buf_out_data_reg[495]_0 [57]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_72_77_i_1__7
       (.I0(mem_reg_0_15_78_79[119]),
        .I1(phy_wrdata[127]),
        .I2(mem_reg_0_15_54_59),
        .O(\write_buffer.wr_buf_out_data_reg[503]_0 [57]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_72_77_i_1__8
       (.I0(mem_reg_0_15_78_79[127]),
        .I1(phy_wrdata[127]),
        .I2(mem_reg_0_15_66_71),
        .O(\write_buffer.wr_buf_out_data_reg[511]_0 [57]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_72_77_i_2
       (.I0(mc_address[6]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ),
        .I2(\phy_ctl_wd_i1_reg[0] ),
        .O(phy_dout[20]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_72_77_i_2__0
       (.I0(mc_address[9]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9] ),
        .I2(\phy_ctl_wd_i1_reg[0] ),
        .O(d_in[32]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_72_77_i_2__1
       (.I0(mem_reg_0_15_78_79[7]),
        .I1(phy_wrdata[63]),
        .I2(mem_reg_0_15_36_41),
        .O(\write_buffer.wr_buf_out_data_reg[455]_0 [56]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_72_77_i_2__2
       (.I0(mem_reg_0_15_78_79[15]),
        .I1(phy_wrdata[63]),
        .I2(mem_reg_0_15_36_41),
        .O(\write_buffer.wr_buf_out_data_reg[463]_0 [56]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_72_77_i_2__3
       (.I0(mem_reg_0_15_78_79[23]),
        .I1(phy_wrdata[63]),
        .I2(mem_reg_0_15_36_41),
        .O(\write_buffer.wr_buf_out_data_reg[471]_0 [56]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_72_77_i_2__4
       (.I0(mem_reg_0_15_78_79[31]),
        .I1(phy_wrdata[63]),
        .I2(mem_reg_0_15_48_53),
        .O(\write_buffer.wr_buf_out_data_reg[479]_0 [56]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_72_77_i_2__5
       (.I0(mem_reg_0_15_78_79[39]),
        .I1(phy_wrdata[63]),
        .I2(mem_reg_0_15_48_53),
        .O(\write_buffer.wr_buf_out_data_reg[487]_0 [56]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_72_77_i_2__6
       (.I0(mem_reg_0_15_78_79[47]),
        .I1(phy_wrdata[63]),
        .I2(mem_reg_0_15_48_53),
        .O(\write_buffer.wr_buf_out_data_reg[495]_0 [56]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_72_77_i_2__7
       (.I0(mem_reg_0_15_78_79[55]),
        .I1(phy_wrdata[63]),
        .I2(mem_reg_0_15_48_53),
        .O(\write_buffer.wr_buf_out_data_reg[503]_0 [56]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_72_77_i_2__8
       (.I0(mem_reg_0_15_78_79[63]),
        .I1(phy_wrdata[63]),
        .I2(mem_reg_0_15_48_53),
        .O(\write_buffer.wr_buf_out_data_reg[511]_0 [56]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_72_77_i_3
       (.I0(mem_reg_0_15_78_79[199]),
        .I1(phy_wrdata[255]),
        .I2(mem_reg_0_15_72_77),
        .O(\write_buffer.wr_buf_out_data_reg[455]_0 [59]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_72_77_i_3__0
       (.I0(mem_reg_0_15_78_79[207]),
        .I1(phy_wrdata[255]),
        .I2(mem_reg_0_15_72_77),
        .O(\write_buffer.wr_buf_out_data_reg[463]_0 [59]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_72_77_i_3__1
       (.I0(mem_reg_0_15_78_79[215]),
        .I1(phy_wrdata[255]),
        .I2(mem_reg_0_15_72_77),
        .O(\write_buffer.wr_buf_out_data_reg[471]_0 [59]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_72_77_i_3__2
       (.I0(mem_reg_0_15_78_79[223]),
        .I1(phy_wrdata[255]),
        .I2(mem_reg_0_15_72_77),
        .O(\write_buffer.wr_buf_out_data_reg[479]_0 [59]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_72_77_i_3__3
       (.I0(mem_reg_0_15_78_79[231]),
        .I1(phy_wrdata[255]),
        .I2(mem_reg_0_15_18_23),
        .O(\write_buffer.wr_buf_out_data_reg[487]_0 [59]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_72_77_i_3__4
       (.I0(mem_reg_0_15_78_79[239]),
        .I1(phy_wrdata[255]),
        .I2(mem_reg_0_15_18_23),
        .O(\write_buffer.wr_buf_out_data_reg[495]_0 [59]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_72_77_i_3__5
       (.I0(mem_reg_0_15_78_79[247]),
        .I1(phy_wrdata[255]),
        .I2(mem_reg_0_15_18_23),
        .O(\write_buffer.wr_buf_out_data_reg[503]_0 [59]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_72_77_i_3__6
       (.I0(mem_reg_0_15_78_79[255]),
        .I1(phy_wrdata[255]),
        .I2(mem_reg_0_15_18_23),
        .O(\write_buffer.wr_buf_out_data_reg[511]_0 [59]));
  LUT2 #(
    .INIT(4'hE)) 
    mem_reg_0_15_72_77_i_3__7
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ),
        .I1(mem_reg_0_15_36_41),
        .O(phy_dout[23]));
  LUT2 #(
    .INIT(4'hE)) 
    mem_reg_0_15_72_77_i_3__8
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9] ),
        .I1(mem_reg_0_15_36_41),
        .O(d_in[35]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_72_77_i_4
       (.I0(mc_address[29]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ),
        .I2(\phy_ctl_wd_i1_reg[0] ),
        .O(phy_dout[22]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_72_77_i_4__0
       (.I0(mc_address[32]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9] ),
        .I2(\phy_ctl_wd_i1_reg[0] ),
        .O(d_in[34]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_72_77_i_4__1
       (.I0(mem_reg_0_15_78_79[135]),
        .I1(phy_wrdata[191]),
        .I2(mem_reg_0_15_66_71),
        .O(\write_buffer.wr_buf_out_data_reg[455]_0 [58]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_72_77_i_4__2
       (.I0(mem_reg_0_15_78_79[143]),
        .I1(phy_wrdata[191]),
        .I2(mem_reg_0_15_66_71),
        .O(\write_buffer.wr_buf_out_data_reg[463]_0 [58]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_72_77_i_4__3
       (.I0(mem_reg_0_15_78_79[151]),
        .I1(phy_wrdata[191]),
        .I2(mem_reg_0_15_66_71),
        .O(\write_buffer.wr_buf_out_data_reg[471]_0 [58]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_72_77_i_4__4
       (.I0(mem_reg_0_15_78_79[159]),
        .I1(phy_wrdata[191]),
        .I2(mem_reg_0_15_66_71),
        .O(\write_buffer.wr_buf_out_data_reg[479]_0 [58]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_72_77_i_4__5
       (.I0(mem_reg_0_15_78_79[167]),
        .I1(phy_wrdata[191]),
        .I2(mem_reg_0_15_66_71),
        .O(\write_buffer.wr_buf_out_data_reg[487]_0 [58]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_72_77_i_4__6
       (.I0(mem_reg_0_15_78_79[175]),
        .I1(phy_wrdata[191]),
        .I2(mem_reg_0_15_72_77),
        .O(\write_buffer.wr_buf_out_data_reg[495]_0 [58]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_72_77_i_4__7
       (.I0(mem_reg_0_15_78_79[183]),
        .I1(phy_wrdata[191]),
        .I2(mem_reg_0_15_72_77),
        .O(\write_buffer.wr_buf_out_data_reg[503]_0 [58]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_72_77_i_4__8
       (.I0(mem_reg_0_15_78_79[191]),
        .I1(phy_wrdata[191]),
        .I2(mem_reg_0_15_72_77),
        .O(\write_buffer.wr_buf_out_data_reg[511]_0 [58]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_72_77_i_5
       (.I0(mem_reg_0_15_78_79[327]),
        .I1(phy_wrdata[383]),
        .I2(mem_reg_0_15_36_41_0),
        .O(\write_buffer.wr_buf_out_data_reg[455]_0 [61]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_72_77_i_5__0
       (.I0(mem_reg_0_15_78_79[335]),
        .I1(phy_wrdata[383]),
        .I2(mem_reg_0_15_36_41_0),
        .O(\write_buffer.wr_buf_out_data_reg[463]_0 [61]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_72_77_i_5__1
       (.I0(mem_reg_0_15_78_79[343]),
        .I1(phy_wrdata[383]),
        .I2(mem_reg_0_15_36_41_0),
        .O(\write_buffer.wr_buf_out_data_reg[471]_0 [61]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_72_77_i_5__2
       (.I0(mem_reg_0_15_78_79[351]),
        .I1(phy_wrdata[383]),
        .I2(mem_reg_0_15_36_41_0),
        .O(\write_buffer.wr_buf_out_data_reg[479]_0 [61]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_72_77_i_5__3
       (.I0(mem_reg_0_15_78_79[359]),
        .I1(phy_wrdata[383]),
        .I2(mem_reg_0_15_36_41_0),
        .O(\write_buffer.wr_buf_out_data_reg[487]_0 [61]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_72_77_i_5__4
       (.I0(mem_reg_0_15_78_79[367]),
        .I1(phy_wrdata[383]),
        .I2(mem_reg_0_15_36_41_0),
        .O(\write_buffer.wr_buf_out_data_reg[495]_0 [61]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_72_77_i_5__5
       (.I0(mem_reg_0_15_78_79[375]),
        .I1(phy_wrdata[383]),
        .I2(mem_reg_0_15_36_41_1),
        .O(\write_buffer.wr_buf_out_data_reg[503]_0 [61]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_72_77_i_5__6
       (.I0(mem_reg_0_15_78_79[383]),
        .I1(phy_wrdata[383]),
        .I2(mem_reg_0_15_36_41_1),
        .O(\write_buffer.wr_buf_out_data_reg[511]_0 [61]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_72_77_i_6
       (.I0(mem_reg_0_15_78_79[263]),
        .I1(phy_wrdata[319]),
        .I2(mem_reg_0_15_18_23),
        .O(\write_buffer.wr_buf_out_data_reg[455]_0 [60]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_72_77_i_6__0
       (.I0(mem_reg_0_15_78_79[271]),
        .I1(phy_wrdata[319]),
        .I2(mem_reg_0_15_18_23),
        .O(\write_buffer.wr_buf_out_data_reg[463]_0 [60]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_72_77_i_6__1
       (.I0(mem_reg_0_15_78_79[279]),
        .I1(phy_wrdata[319]),
        .I2(mem_reg_0_15_18_23_0),
        .O(\write_buffer.wr_buf_out_data_reg[471]_0 [60]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_72_77_i_6__2
       (.I0(mem_reg_0_15_78_79[287]),
        .I1(phy_wrdata[319]),
        .I2(mem_reg_0_15_18_23_0),
        .O(\write_buffer.wr_buf_out_data_reg[479]_0 [60]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_72_77_i_6__3
       (.I0(mem_reg_0_15_78_79[295]),
        .I1(phy_wrdata[319]),
        .I2(mem_reg_0_15_18_23_0),
        .O(\write_buffer.wr_buf_out_data_reg[487]_0 [60]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_72_77_i_6__4
       (.I0(mem_reg_0_15_78_79[303]),
        .I1(phy_wrdata[319]),
        .I2(mem_reg_0_15_18_23_0),
        .O(\write_buffer.wr_buf_out_data_reg[495]_0 [60]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_72_77_i_6__5
       (.I0(mem_reg_0_15_78_79[311]),
        .I1(phy_wrdata[319]),
        .I2(mem_reg_0_15_18_23_0),
        .O(\write_buffer.wr_buf_out_data_reg[503]_0 [60]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_72_77_i_6__6
       (.I0(mem_reg_0_15_78_79[319]),
        .I1(phy_wrdata[319]),
        .I2(mem_reg_0_15_18_23_0),
        .O(\write_buffer.wr_buf_out_data_reg[511]_0 [60]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_78_79_i_1
       (.I0(mem_reg_0_15_78_79[455]),
        .I1(phy_wrdata[511]),
        .I2(mem_reg_0_15_54_59_0),
        .O(\write_buffer.wr_buf_out_data_reg[455]_0 [63]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_78_79_i_1__0
       (.I0(mem_reg_0_15_78_79[463]),
        .I1(phy_wrdata[511]),
        .I2(mem_reg_0_15_54_59_0),
        .O(\write_buffer.wr_buf_out_data_reg[463]_0 [63]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_78_79_i_1__1
       (.I0(mem_reg_0_15_78_79[471]),
        .I1(phy_wrdata[511]),
        .I2(mem_reg_0_15_78_79_0),
        .O(\write_buffer.wr_buf_out_data_reg[471]_0 [63]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_78_79_i_1__2
       (.I0(mem_reg_0_15_78_79[479]),
        .I1(phy_wrdata[511]),
        .I2(mem_reg_0_15_78_79_0),
        .O(\write_buffer.wr_buf_out_data_reg[479]_0 [63]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_78_79_i_1__3
       (.I0(mem_reg_0_15_78_79[487]),
        .I1(phy_wrdata[511]),
        .I2(mem_reg_0_15_78_79_0),
        .O(\write_buffer.wr_buf_out_data_reg[487]_0 [63]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_78_79_i_1__4
       (.I0(mem_reg_0_15_78_79[495]),
        .I1(phy_wrdata[511]),
        .I2(mem_reg_0_15_78_79_0),
        .O(\write_buffer.wr_buf_out_data_reg[495]_0 [63]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_78_79_i_1__5
       (.I0(mem_reg_0_15_78_79[503]),
        .I1(phy_wrdata[511]),
        .I2(mem_reg_0_15_78_79_0),
        .O(\write_buffer.wr_buf_out_data_reg[503]_0 [63]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_78_79_i_1__6
       (.I0(mem_reg_0_15_78_79[511]),
        .I1(phy_wrdata[511]),
        .I2(mem_reg_0_15_78_79_0),
        .O(\write_buffer.wr_buf_out_data_reg[511]_0 [63]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_78_79_i_2
       (.I0(mem_reg_0_15_78_79[391]),
        .I1(phy_wrdata[447]),
        .I2(mem_reg_0_15_36_41_1),
        .O(\write_buffer.wr_buf_out_data_reg[455]_0 [62]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_78_79_i_2__0
       (.I0(mem_reg_0_15_78_79[399]),
        .I1(phy_wrdata[447]),
        .I2(mem_reg_0_15_36_41_1),
        .O(\write_buffer.wr_buf_out_data_reg[463]_0 [62]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_78_79_i_2__1
       (.I0(mem_reg_0_15_78_79[407]),
        .I1(phy_wrdata[447]),
        .I2(mem_reg_0_15_36_41_1),
        .O(\write_buffer.wr_buf_out_data_reg[471]_0 [62]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_78_79_i_2__2
       (.I0(mem_reg_0_15_78_79[415]),
        .I1(phy_wrdata[447]),
        .I2(mem_reg_0_15_36_41_1),
        .O(\write_buffer.wr_buf_out_data_reg[479]_0 [62]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_78_79_i_2__3
       (.I0(mem_reg_0_15_78_79[423]),
        .I1(phy_wrdata[447]),
        .I2(mem_reg_0_15_54_59_0),
        .O(\write_buffer.wr_buf_out_data_reg[487]_0 [62]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_78_79_i_2__4
       (.I0(mem_reg_0_15_78_79[431]),
        .I1(phy_wrdata[447]),
        .I2(mem_reg_0_15_54_59_0),
        .O(\write_buffer.wr_buf_out_data_reg[495]_0 [62]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_78_79_i_2__5
       (.I0(mem_reg_0_15_78_79[439]),
        .I1(phy_wrdata[447]),
        .I2(mem_reg_0_15_54_59_0),
        .O(\write_buffer.wr_buf_out_data_reg[503]_0 [62]));
  LUT3 #(
    .INIT(8'hAC)) 
    mem_reg_0_15_78_79_i_2__6
       (.I0(mem_reg_0_15_78_79[447]),
        .I1(phy_wrdata[447]),
        .I2(mem_reg_0_15_54_59_0),
        .O(\write_buffer.wr_buf_out_data_reg[511]_0 [62]));
  (* SOFT_HLUTNM = "soft_lutpair469" *) 
  LUT4 #(
    .INIT(16'hFF02)) 
    mpr_rdlvl_start_i_1
       (.I0(pi_dqs_found_done_r1_reg_0),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(mpr_rdlvl_start_i_2_n_0),
        .I3(mpr_rdlvl_start_reg_0),
        .O(mpr_rdlvl_start_i_1_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFDFFF)) 
    mpr_rdlvl_start_i_2
       (.I0(\init_state_r_reg_n_0_[3] ),
        .I1(\init_state_r_reg_n_0_[2] ),
        .I2(Q),
        .I3(\init_state_r_reg_n_0_[5] ),
        .I4(\init_state_r_reg_n_0_[4] ),
        .I5(init_state_r),
        .O(mpr_rdlvl_start_i_2_n_0));
  FDRE mpr_rdlvl_start_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(mpr_rdlvl_start_i_1_n_0),
        .Q(mpr_rdlvl_start_reg_0),
        .R(\victim_sel_reg[0]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair525" *) 
  LUT2 #(
    .INIT(4'h2)) 
    mux_rd_valid_r_i_1
       (.I0(prbs_rdlvl_start_reg_0),
        .I1(if_empty),
        .O(mux_rd_valid_r0));
  (* SOFT_HLUTNM = "soft_lutpair525" *) 
  LUT2 #(
    .INIT(4'h2)) 
    new_cnt_dqs_r_i_2
       (.I0(prbs_rdlvl_start_reg_0),
        .I1(prbs_rdlvl_start_r),
        .O(prbs_rdlvl_start_reg_1));
  LUT1 #(
    .INIT(2'h1)) 
    \num_refresh[0]_i_1 
       (.I0(num_refresh_reg[0]),
        .O(p_0_in__5[0]));
  (* SOFT_HLUTNM = "soft_lutpair513" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \num_refresh[1]_i_1 
       (.I0(num_refresh_reg[1]),
        .I1(num_refresh_reg[0]),
        .O(p_0_in__5[1]));
  (* SOFT_HLUTNM = "soft_lutpair513" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \num_refresh[2]_i_1 
       (.I0(num_refresh_reg[2]),
        .I1(num_refresh_reg[0]),
        .I2(num_refresh_reg[1]),
        .O(p_0_in__5[2]));
  LUT5 #(
    .INIT(32'hFFFFDFDD)) 
    \num_refresh[3]_i_1 
       (.I0(\num_refresh[3]_i_4_n_0 ),
        .I1(\rd_addr_reg[7] ),
        .I2(complex_oclkdelay_calib_start_int_i_2_n_0),
        .I3(\init_state_r_reg_n_0_[1] ),
        .I4(\num_refresh[3]_i_5_n_0 ),
        .O(\num_refresh[3]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h0A8AAA8A)) 
    \num_refresh[3]_i_2 
       (.I0(\num_refresh[3]_i_6_n_0 ),
        .I1(ddr3_lm_done_r_reg_0),
        .I2(pi_dqs_found_done_r1_reg_0),
        .I3(prbs_rdlvl_start_reg_2),
        .I4(complex_oclkdelay_calib_done_r1_reg_0),
        .O(num_refresh0));
  (* SOFT_HLUTNM = "soft_lutpair460" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \num_refresh[3]_i_3 
       (.I0(num_refresh_reg[3]),
        .I1(num_refresh_reg[1]),
        .I2(num_refresh_reg[0]),
        .I3(num_refresh_reg[2]),
        .O(p_0_in__5[3]));
  LUT6 #(
    .INIT(64'hFFFFFFEFFFFFFFFE)) 
    \num_refresh[3]_i_4 
       (.I0(rdlvl_stg1_start_int_i_2_n_0),
        .I1(init_state_r),
        .I2(\init_state_r_reg_n_0_[5] ),
        .I3(\init_state_r_reg_n_0_[4] ),
        .I4(\init_state_r_reg_n_0_[1] ),
        .I5(Q),
        .O(\num_refresh[3]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h0000000041000000)) 
    \num_refresh[3]_i_5 
       (.I0(prbs_rdlvl_start_i_2_n_0),
        .I1(\init_state_r_reg_n_0_[3] ),
        .I2(\init_state_r_reg_n_0_[4] ),
        .I3(\init_state_r_reg_n_0_[2] ),
        .I4(\init_state_r_reg_n_0_[5] ),
        .I5(init_state_r),
        .O(\num_refresh[3]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000800)) 
    \num_refresh[3]_i_6 
       (.I0(\init_state_r_reg_n_0_[4] ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ),
        .I2(\init_state_r_reg_n_0_[2] ),
        .I3(\init_state_r_reg_n_0_[3] ),
        .I4(init_state_r),
        .I5(\init_state_r_reg_n_0_[5] ),
        .O(\num_refresh[3]_i_6_n_0 ));
  FDRE \num_refresh_reg[0] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(num_refresh0),
        .D(p_0_in__5[0]),
        .Q(num_refresh_reg[0]),
        .R(\num_refresh[3]_i_1_n_0 ));
  FDRE \num_refresh_reg[1] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(num_refresh0),
        .D(p_0_in__5[1]),
        .Q(num_refresh_reg[1]),
        .R(\num_refresh[3]_i_1_n_0 ));
  FDRE \num_refresh_reg[2] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(num_refresh0),
        .D(p_0_in__5[2]),
        .Q(num_refresh_reg[2]),
        .R(\num_refresh[3]_i_1_n_0 ));
  FDRE \num_refresh_reg[3] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(num_refresh0),
        .D(p_0_in__5[3]),
        .Q(num_refresh_reg[3]),
        .R(\num_refresh[3]_i_1_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \ocal_act_wait_cnt[0]_i_1 
       (.I0(ocal_act_wait_cnt_reg[0]),
        .O(p_0_in__8[0]));
  (* SOFT_HLUTNM = "soft_lutpair495" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \ocal_act_wait_cnt[1]_i_1 
       (.I0(ocal_act_wait_cnt_reg[1]),
        .I1(ocal_act_wait_cnt_reg[0]),
        .O(p_0_in__8[1]));
  (* SOFT_HLUTNM = "soft_lutpair495" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \ocal_act_wait_cnt[2]_i_1 
       (.I0(ocal_act_wait_cnt_reg[2]),
        .I1(ocal_act_wait_cnt_reg[1]),
        .I2(ocal_act_wait_cnt_reg[0]),
        .O(p_0_in__8[2]));
  LUT5 #(
    .INIT(32'hFFFFFFFD)) 
    \ocal_act_wait_cnt[3]_i_1 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(Q),
        .I2(\ocal_act_wait_cnt[3]_i_3_n_0 ),
        .I3(prbs_rdlvl_start_i_3_n_0),
        .I4(write_calib_reg_0),
        .O(\ocal_act_wait_cnt[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair457" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \ocal_act_wait_cnt[3]_i_2 
       (.I0(ocal_act_wait_cnt_reg[0]),
        .I1(ocal_act_wait_cnt_reg[1]),
        .I2(ocal_act_wait_cnt_reg[2]),
        .I3(ocal_act_wait_cnt_reg[3]),
        .O(p_0_in__8[3]));
  (* SOFT_HLUTNM = "soft_lutpair457" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \ocal_act_wait_cnt[3]_i_3 
       (.I0(ocal_act_wait_cnt_reg[3]),
        .I1(ocal_act_wait_cnt_reg[2]),
        .I2(ocal_act_wait_cnt_reg[1]),
        .I3(ocal_act_wait_cnt_reg[0]),
        .O(\ocal_act_wait_cnt[3]_i_3_n_0 ));
  FDRE \ocal_act_wait_cnt_reg[0] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(p_0_in__8[0]),
        .Q(ocal_act_wait_cnt_reg[0]),
        .R(\ocal_act_wait_cnt[3]_i_1_n_0 ));
  FDRE \ocal_act_wait_cnt_reg[1] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(p_0_in__8[1]),
        .Q(ocal_act_wait_cnt_reg[1]),
        .R(\ocal_act_wait_cnt[3]_i_1_n_0 ));
  FDRE \ocal_act_wait_cnt_reg[2] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(p_0_in__8[2]),
        .Q(ocal_act_wait_cnt_reg[2]),
        .R(\ocal_act_wait_cnt[3]_i_1_n_0 ));
  FDRE \ocal_act_wait_cnt_reg[3] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(p_0_in__8[3]),
        .Q(ocal_act_wait_cnt_reg[3]),
        .R(\ocal_act_wait_cnt[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair523" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \oclk_wr_cnt[0]_i_1 
       (.I0(oclk_wr_cnt_reg[0]),
        .O(\oclk_wr_cnt[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair523" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \oclk_wr_cnt[1]_i_1 
       (.I0(oclk_wr_cnt_reg[0]),
        .I1(oclk_wr_cnt_reg[1]),
        .O(\oclk_wr_cnt[1]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'hA9)) 
    \oclk_wr_cnt[2]_i_1 
       (.I0(oclk_wr_cnt_reg[2]),
        .I1(oclk_wr_cnt_reg[1]),
        .I2(oclk_wr_cnt_reg[0]),
        .O(oclk_wr_cnt0[2]));
  LUT6 #(
    .INIT(64'hFFFFFFFFAAAAAAAB)) 
    \oclk_wr_cnt[3]_i_1 
       (.I0(\oclk_wr_cnt[3]_i_4_n_0 ),
        .I1(oclk_wr_cnt_reg[1]),
        .I2(oclk_wr_cnt_reg[0]),
        .I3(oclk_wr_cnt_reg[3]),
        .I4(oclk_wr_cnt_reg[2]),
        .I5(write_calib_reg_0),
        .O(\oclk_wr_cnt[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000002000000)) 
    \oclk_wr_cnt[3]_i_2 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(init_state_r),
        .I2(\init_state_r_reg_n_0_[4] ),
        .I3(\init_state_r_reg_n_0_[5] ),
        .I4(Q),
        .I5(rdlvl_stg1_start_int_i_2_n_0),
        .O(p_0_in0_in));
  (* SOFT_HLUTNM = "soft_lutpair431" *) 
  LUT4 #(
    .INIT(16'hAAA9)) 
    \oclk_wr_cnt[3]_i_3 
       (.I0(oclk_wr_cnt_reg[3]),
        .I1(oclk_wr_cnt_reg[2]),
        .I2(oclk_wr_cnt_reg[0]),
        .I3(oclk_wr_cnt_reg[1]),
        .O(oclk_wr_cnt0[3]));
  LUT6 #(
    .INIT(64'h0000000000000800)) 
    \oclk_wr_cnt[3]_i_4 
       (.I0(\wrcal_reads[7]_i_5_n_0 ),
        .I1(\init_state_r_reg_n_0_[5] ),
        .I2(init_state_r),
        .I3(\init_state_r_reg_n_0_[4] ),
        .I4(\init_state_r_reg_n_0_[3] ),
        .I5(\init_state_r_reg_n_0_[2] ),
        .O(\oclk_wr_cnt[3]_i_4_n_0 ));
  FDRE \oclk_wr_cnt_reg[0] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(p_0_in0_in),
        .D(\oclk_wr_cnt[0]_i_1_n_0 ),
        .Q(oclk_wr_cnt_reg[0]),
        .R(\oclk_wr_cnt[3]_i_1_n_0 ));
  FDRE \oclk_wr_cnt_reg[1] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(p_0_in0_in),
        .D(\oclk_wr_cnt[1]_i_1_n_0 ),
        .Q(oclk_wr_cnt_reg[1]),
        .R(\oclk_wr_cnt[3]_i_1_n_0 ));
  FDSE \oclk_wr_cnt_reg[2] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(p_0_in0_in),
        .D(oclk_wr_cnt0[2]),
        .Q(oclk_wr_cnt_reg[2]),
        .S(\oclk_wr_cnt[3]_i_1_n_0 ));
  FDRE \oclk_wr_cnt_reg[3] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(p_0_in0_in),
        .D(oclk_wr_cnt0[3]),
        .Q(oclk_wr_cnt_reg[3]),
        .R(\oclk_wr_cnt[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h8888888888880888)) 
    \odd_cwl.phy_cas_n[1]_i_1 
       (.I0(\DDR3_1rank.phy_int_cs_n[1]_i_2_n_0 ),
        .I1(\odd_cwl.phy_cas_n[1]_i_2_n_0 ),
        .I2(\init_state_r_reg_n_0_[4] ),
        .I3(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ),
        .I4(\init_state_r[4]_i_4_n_0 ),
        .I5(\init_state_r[3]_i_6_n_0 ),
        .O(\odd_cwl.phy_cas_n[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h2A0AAA022AAAAA22)) 
    \odd_cwl.phy_cas_n[1]_i_2 
       (.I0(\DDR3_1rank.phy_int_cs_n[1]_i_7_n_0 ),
        .I1(\odd_cwl.phy_cas_n[1]_i_3_n_0 ),
        .I2(\init_state_r_reg_n_0_[1] ),
        .I3(Q),
        .I4(\init_state_r_reg_n_0_[4] ),
        .I5(\odd_cwl.phy_cas_n[1]_i_4_n_0 ),
        .O(\odd_cwl.phy_cas_n[1]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair446" *) 
  LUT4 #(
    .INIT(16'h0010)) 
    \odd_cwl.phy_cas_n[1]_i_3 
       (.I0(\init_state_r_reg_n_0_[5] ),
        .I1(init_state_r),
        .I2(\init_state_r_reg_n_0_[3] ),
        .I3(\init_state_r_reg_n_0_[2] ),
        .O(\odd_cwl.phy_cas_n[1]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair408" *) 
  LUT5 #(
    .INIT(32'h00000100)) 
    \odd_cwl.phy_cas_n[1]_i_4 
       (.I0(init_state_r),
        .I1(\init_state_r_reg_n_0_[5] ),
        .I2(\init_state_r_reg_n_0_[4] ),
        .I3(\init_state_r_reg_n_0_[2] ),
        .I4(\init_state_r_reg_n_0_[3] ),
        .O(\odd_cwl.phy_cas_n[1]_i_4_n_0 ));
  FDRE \odd_cwl.phy_cas_n_reg[1] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\odd_cwl.phy_cas_n[1]_i_1_n_0 ),
        .Q(phy_cas_n),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAAAA2)) 
    \odd_cwl.phy_ras_n[1]_i_1 
       (.I0(\DDR3_1rank.phy_int_cs_n[1]_i_3_n_0 ),
        .I1(\init_state_r_reg_n_0_[4] ),
        .I2(prbs_rdlvl_start_i_2_n_0),
        .I3(\init_state_r_reg_n_0_[5] ),
        .I4(init_state_r),
        .I5(\init_state_r[4]_i_4_n_0 ),
        .O(\odd_cwl.phy_ras_n[1]_i_1_n_0 ));
  FDRE \odd_cwl.phy_ras_n_reg[1] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\odd_cwl.phy_ras_n[1]_i_1_n_0 ),
        .Q(phy_ras_n),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair486" *) 
  LUT3 #(
    .INIT(8'h08)) 
    \odd_cwl.phy_we_n[1]_i_1 
       (.I0(\odd_cwl.phy_cas_n[1]_i_2_n_0 ),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[10]_i_5_n_0 ),
        .I2(phy_wrdata_en),
        .O(\odd_cwl.phy_we_n[1]_i_1_n_0 ));
  FDRE \odd_cwl.phy_we_n_reg[1] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\odd_cwl.phy_we_n[1]_i_1_n_0 ),
        .Q(phy_we_n),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0001000100010000)) 
    \one_rank.stg1_wr_done_i_1 
       (.I0(\reg_ctrl_cnt_r[3]_i_1_n_0 ),
        .I1(rdlvl_last_byte_done),
        .I2(prbs_rdlvl_done_pulse_reg_0),
        .I3(complex_byte_rd_done),
        .I4(stg1_wr_done),
        .I5(\one_rank.stg1_wr_done_reg_0 ),
        .O(\one_rank.stg1_wr_done_i_1_n_0 ));
  FDRE \one_rank.stg1_wr_done_reg 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\one_rank.stg1_wr_done_i_1_n_0 ),
        .Q(\one_rank.stg1_wr_done_reg_0 ),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h0000002A)) 
    \one_rank_complex.complex_wr_done_i_1 
       (.I0(\one_rank_complex.complex_wr_done_i_2_n_0 ),
        .I1(complex_oclkdelay_calib_done_r1_reg_0),
        .I2(\stg1_wr_rd_cnt[8]_i_5_n_0 ),
        .I3(rdlvl_last_byte_done),
        .I4(\reg_ctrl_cnt_r[3]_i_1_n_0 ),
        .O(\one_rank_complex.complex_wr_done_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000551055105510)) 
    \one_rank_complex.complex_wr_done_i_2 
       (.I0(prbs_rdlvl_done_pulse_reg_0),
        .I1(\one_rank_complex.complex_wr_done_i_3_n_0 ),
        .I2(\one_rank_complex.complex_wr_done_i_4_n_0 ),
        .I3(complex_wr_done),
        .I4(\victim_sel[2]_i_4_n_0 ),
        .I5(complex_byte_rd_done),
        .O(\one_rank_complex.complex_wr_done_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFDFFFFFFFFFDFFF)) 
    \one_rank_complex.complex_wr_done_i_3 
       (.I0(\init_state_r_reg_n_0_[4] ),
        .I1(complex_act_start_i_2_n_0),
        .I2(\init_state_r_reg_n_0_[2] ),
        .I3(\init_state_r_reg_n_0_[3] ),
        .I4(\init_state_r_reg_n_0_[1] ),
        .I5(Q),
        .O(\one_rank_complex.complex_wr_done_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair422" *) 
  LUT5 #(
    .INIT(32'h00800000)) 
    \one_rank_complex.complex_wr_done_i_4 
       (.I0(complex_wait_cnt_reg[2]),
        .I1(complex_wait_cnt_reg[3]),
        .I2(complex_row1_wr_done),
        .I3(complex_wait_cnt_reg[1]),
        .I4(complex_wait_cnt_reg[0]),
        .O(\one_rank_complex.complex_wr_done_i_4_n_0 ));
  FDRE \one_rank_complex.complex_wr_done_reg 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\one_rank_complex.complex_wr_done_i_1_n_0 ),
        .Q(complex_wr_done),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_10__2
       (.I0(mem_reg_0_15_78_79[448]),
        .I1(phy_wrdata[504]),
        .I2(out_fifo_27),
        .I3(out_fifo_3[7]),
        .I4(out_fifo_4),
        .O(\write_buffer.wr_buf_out_data_reg[448] [7]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_10__3
       (.I0(mem_reg_0_15_78_79[480]),
        .I1(phy_wrdata[504]),
        .I2(out_fifo_28),
        .I3(out_fifo_12[7]),
        .I4(out_fifo_13),
        .O(\write_buffer.wr_buf_out_data_reg[480] [7]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_11__2
       (.I0(mem_reg_0_15_78_79[384]),
        .I1(phy_wrdata[440]),
        .I2(out_fifo_26),
        .I3(out_fifo_3[6]),
        .I4(out_fifo_4),
        .O(\write_buffer.wr_buf_out_data_reg[448] [6]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_11__3
       (.I0(mem_reg_0_15_78_79[416]),
        .I1(phy_wrdata[440]),
        .I2(out_fifo_26),
        .I3(out_fifo_12[6]),
        .I4(out_fifo_13),
        .O(\write_buffer.wr_buf_out_data_reg[480] [6]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_12__2
       (.I0(mem_reg_0_15_78_79[320]),
        .I1(phy_wrdata[376]),
        .I2(out_fifo_24),
        .I3(out_fifo_3[5]),
        .I4(out_fifo_4),
        .O(\write_buffer.wr_buf_out_data_reg[448] [5]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_12__3
       (.I0(mem_reg_0_15_78_79[352]),
        .I1(phy_wrdata[376]),
        .I2(out_fifo_25),
        .I3(out_fifo_12[5]),
        .I4(out_fifo_13),
        .O(\write_buffer.wr_buf_out_data_reg[480] [5]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_13__2
       (.I0(mem_reg_0_15_78_79[256]),
        .I1(phy_wrdata[312]),
        .I2(out_fifo_23),
        .I3(out_fifo_3[4]),
        .I4(out_fifo_4),
        .O(\write_buffer.wr_buf_out_data_reg[448] [4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_13__3
       (.I0(mem_reg_0_15_78_79[288]),
        .I1(phy_wrdata[312]),
        .I2(out_fifo_24),
        .I3(out_fifo_12[4]),
        .I4(out_fifo_13),
        .O(\write_buffer.wr_buf_out_data_reg[480] [4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_14__0
       (.I0(mem_reg_0_15_78_79[192]),
        .I1(phy_wrdata[248]),
        .I2(out_fifo_22),
        .I3(out_fifo_3[3]),
        .I4(out_fifo_4),
        .O(\write_buffer.wr_buf_out_data_reg[448] [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_14__1
       (.I0(mem_reg_0_15_78_79[224]),
        .I1(phy_wrdata[248]),
        .I2(out_fifo_23),
        .I3(out_fifo_12[3]),
        .I4(out_fifo_13),
        .O(\write_buffer.wr_buf_out_data_reg[480] [3]));
  LUT4 #(
    .INIT(16'hEEF0)) 
    out_fifo_i_14__2
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ),
        .I1(out_fifo_31),
        .I2(mem_out[3]),
        .I3(out_fifo),
        .O(D1[3]));
  LUT4 #(
    .INIT(16'hEEF0)) 
    out_fifo_i_14__3
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ),
        .I1(out_fifo_31),
        .I2(out_fifo_0[3]),
        .I3(out_fifo_1),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[8]_0 [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_15__0
       (.I0(mc_address[30]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ),
        .I2(out_fifo_2),
        .I3(mem_out[2]),
        .I4(out_fifo),
        .O(D1[2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_15__1
       (.I0(mc_address[31]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ),
        .I2(out_fifo_2),
        .I3(out_fifo_0[2]),
        .I4(out_fifo_1),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[8]_0 [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_15__2
       (.I0(mem_reg_0_15_78_79[128]),
        .I1(phy_wrdata[184]),
        .I2(out_fifo_21),
        .I3(out_fifo_3[2]),
        .I4(out_fifo_4),
        .O(\write_buffer.wr_buf_out_data_reg[448] [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_15__3
       (.I0(mem_reg_0_15_78_79[160]),
        .I1(phy_wrdata[184]),
        .I2(out_fifo_21),
        .I3(out_fifo_12[2]),
        .I4(out_fifo_13),
        .O(\write_buffer.wr_buf_out_data_reg[480] [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_16
       (.I0(mc_address[19]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ),
        .I2(phy_ctl_wr_i1_reg),
        .I3(mem_out[1]),
        .I4(out_fifo),
        .O(D1[1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_16__0
       (.I0(mc_address[20]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ),
        .I2(phy_ctl_wr_i1_reg),
        .I3(out_fifo_0[1]),
        .I4(out_fifo_1),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[8]_0 [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_16__1
       (.I0(mem_reg_0_15_78_79[64]),
        .I1(phy_wrdata[120]),
        .I2(out_fifo_11),
        .I3(out_fifo_3[1]),
        .I4(out_fifo_4),
        .O(\write_buffer.wr_buf_out_data_reg[448] [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_16__2
       (.I0(mem_reg_0_15_78_79[96]),
        .I1(phy_wrdata[120]),
        .I2(out_fifo_20),
        .I3(out_fifo_12[1]),
        .I4(out_fifo_13),
        .O(\write_buffer.wr_buf_out_data_reg[480] [1]));
  LUT5 #(
    .INIT(32'hB8B8FF00)) 
    out_fifo_i_16__3
       (.I0(mc_odt),
        .I1(out_fifo_31),
        .I2(calib_odt),
        .I3(out_fifo_29[3]),
        .I4(out_fifo_30),
        .O(\cmd_pipe_plus.mc_odt_reg[0] [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_17
       (.I0(mc_address[7]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[7] ),
        .I2(phy_ctl_wr_i1_reg),
        .I3(mem_out[0]),
        .I4(out_fifo),
        .O(D1[0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_17__0
       (.I0(mc_address[8]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[8] ),
        .I2(phy_ctl_wr_i1_reg),
        .I3(out_fifo_0[0]),
        .I4(out_fifo_1),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[8]_0 [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_17__1
       (.I0(mem_reg_0_15_78_79[0]),
        .I1(phy_wrdata[56]),
        .I2(out_fifo_2),
        .I3(out_fifo_3[0]),
        .I4(out_fifo_4),
        .O(\write_buffer.wr_buf_out_data_reg[448] [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_17__2
       (.I0(mem_reg_0_15_78_79[32]),
        .I1(phy_wrdata[56]),
        .I2(out_fifo_11),
        .I3(out_fifo_12[0]),
        .I4(out_fifo_13),
        .O(\write_buffer.wr_buf_out_data_reg[480] [0]));
  LUT5 #(
    .INIT(32'hB8B8FF00)) 
    out_fifo_i_17__3
       (.I0(mc_odt),
        .I1(out_fifo_31),
        .I2(calib_odt),
        .I3(out_fifo_29[2]),
        .I4(out_fifo_30),
        .O(\cmd_pipe_plus.mc_odt_reg[0] [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_18__0
       (.I0(mem_reg_0_15_78_79[449]),
        .I1(phy_wrdata[505]),
        .I2(out_fifo_27),
        .I3(out_fifo_3[15]),
        .I4(out_fifo_4),
        .O(D2[7]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_18__1
       (.I0(mem_reg_0_15_78_79[456]),
        .I1(phy_wrdata[504]),
        .I2(out_fifo_27),
        .I3(out_fifo_5[7]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[456] [7]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_18__2
       (.I0(mem_reg_0_15_78_79[464]),
        .I1(phy_wrdata[504]),
        .I2(out_fifo_27),
        .I3(out_fifo_7[7]),
        .I4(out_fifo_8),
        .O(\write_buffer.wr_buf_out_data_reg[464] [7]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_18__3
       (.I0(mem_reg_0_15_78_79[472]),
        .I1(phy_wrdata[504]),
        .I2(out_fifo_28),
        .I3(out_fifo_9[7]),
        .I4(out_fifo_10),
        .O(\write_buffer.wr_buf_out_data_reg[472] [7]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_18__4
       (.I0(mem_reg_0_15_78_79[481]),
        .I1(phy_wrdata[505]),
        .I2(out_fifo_28),
        .I3(out_fifo_12[15]),
        .I4(out_fifo_13),
        .O(\write_buffer.wr_buf_out_data_reg[481] [7]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_18__5
       (.I0(mem_reg_0_15_78_79[488]),
        .I1(phy_wrdata[504]),
        .I2(out_fifo_28),
        .I3(out_fifo_14[7]),
        .I4(out_fifo_15),
        .O(\write_buffer.wr_buf_out_data_reg[488] [7]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_18__6
       (.I0(mem_reg_0_15_78_79[496]),
        .I1(phy_wrdata[504]),
        .I2(out_fifo_28),
        .I3(out_fifo_16[7]),
        .I4(out_fifo_17),
        .O(\write_buffer.wr_buf_out_data_reg[496] [7]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_18__7
       (.I0(mem_reg_0_15_78_79[504]),
        .I1(phy_wrdata[504]),
        .I2(out_fifo_28),
        .I3(out_fifo_18[7]),
        .I4(out_fifo_19),
        .O(\write_buffer.wr_buf_out_data_reg[504] [7]));
  LUT5 #(
    .INIT(32'hB8B8FF00)) 
    out_fifo_i_18__8
       (.I0(mc_odt),
        .I1(out_fifo_28),
        .I2(calib_odt),
        .I3(out_fifo_29[1]),
        .I4(out_fifo_30),
        .O(\cmd_pipe_plus.mc_odt_reg[0] [1]));
  LUT4 #(
    .INIT(16'hEEF0)) 
    out_fifo_i_18__9
       (.I0(phy_bank[10]),
        .I1(out_fifo_31),
        .I2(out_fifo_0[11]),
        .I3(out_fifo_1),
        .O(\gen_no_mirror.div_clk_loop[0].phy_bank_reg[1]_0 [7]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_19__0
       (.I0(mc_bank[7]),
        .I1(phy_bank[10]),
        .I2(out_fifo_2),
        .I3(out_fifo_0[10]),
        .I4(out_fifo_1),
        .O(\gen_no_mirror.div_clk_loop[0].phy_bank_reg[1]_0 [6]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_19__1
       (.I0(mem_reg_0_15_78_79[385]),
        .I1(phy_wrdata[441]),
        .I2(out_fifo_26),
        .I3(out_fifo_3[14]),
        .I4(out_fifo_4),
        .O(D2[6]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_19__2
       (.I0(mem_reg_0_15_78_79[392]),
        .I1(phy_wrdata[440]),
        .I2(out_fifo_26),
        .I3(out_fifo_5[6]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[456] [6]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_19__3
       (.I0(mem_reg_0_15_78_79[400]),
        .I1(phy_wrdata[440]),
        .I2(out_fifo_26),
        .I3(out_fifo_7[6]),
        .I4(out_fifo_8),
        .O(\write_buffer.wr_buf_out_data_reg[464] [6]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_19__4
       (.I0(mem_reg_0_15_78_79[408]),
        .I1(phy_wrdata[440]),
        .I2(out_fifo_26),
        .I3(out_fifo_9[6]),
        .I4(out_fifo_10),
        .O(\write_buffer.wr_buf_out_data_reg[472] [6]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_19__5
       (.I0(mem_reg_0_15_78_79[417]),
        .I1(phy_wrdata[441]),
        .I2(out_fifo_26),
        .I3(out_fifo_12[14]),
        .I4(out_fifo_13),
        .O(\write_buffer.wr_buf_out_data_reg[481] [6]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_19__6
       (.I0(mem_reg_0_15_78_79[424]),
        .I1(phy_wrdata[440]),
        .I2(out_fifo_27),
        .I3(out_fifo_14[6]),
        .I4(out_fifo_15),
        .O(\write_buffer.wr_buf_out_data_reg[488] [6]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_19__7
       (.I0(mem_reg_0_15_78_79[432]),
        .I1(phy_wrdata[440]),
        .I2(out_fifo_27),
        .I3(out_fifo_16[6]),
        .I4(out_fifo_17),
        .O(\write_buffer.wr_buf_out_data_reg[496] [6]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_19__8
       (.I0(mem_reg_0_15_78_79[440]),
        .I1(phy_wrdata[440]),
        .I2(out_fifo_27),
        .I3(out_fifo_18[6]),
        .I4(out_fifo_19),
        .O(\write_buffer.wr_buf_out_data_reg[504] [6]));
  LUT5 #(
    .INIT(32'hB8B8FF00)) 
    out_fifo_i_19__9
       (.I0(mc_odt),
        .I1(out_fifo_28),
        .I2(calib_odt),
        .I3(out_fifo_29[0]),
        .I4(out_fifo_30),
        .O(\cmd_pipe_plus.mc_odt_reg[0] [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_20__1
       (.I0(mc_bank[4]),
        .I1(phy_bank[10]),
        .I2(out_fifo_2),
        .I3(out_fifo_0[9]),
        .I4(out_fifo_1),
        .O(\gen_no_mirror.div_clk_loop[0].phy_bank_reg[1]_0 [5]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_20__2
       (.I0(mem_reg_0_15_78_79[321]),
        .I1(phy_wrdata[377]),
        .I2(out_fifo_25),
        .I3(out_fifo_3[13]),
        .I4(out_fifo_4),
        .O(D2[5]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_20__3
       (.I0(mem_reg_0_15_78_79[328]),
        .I1(phy_wrdata[376]),
        .I2(out_fifo_25),
        .I3(out_fifo_5[5]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[456] [5]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_20__4
       (.I0(mem_reg_0_15_78_79[336]),
        .I1(phy_wrdata[376]),
        .I2(out_fifo_25),
        .I3(out_fifo_7[5]),
        .I4(out_fifo_8),
        .O(\write_buffer.wr_buf_out_data_reg[464] [5]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_20__5
       (.I0(mem_reg_0_15_78_79[344]),
        .I1(phy_wrdata[376]),
        .I2(out_fifo_25),
        .I3(out_fifo_9[5]),
        .I4(out_fifo_10),
        .O(\write_buffer.wr_buf_out_data_reg[472] [5]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_20__6
       (.I0(mem_reg_0_15_78_79[353]),
        .I1(phy_wrdata[377]),
        .I2(out_fifo_25),
        .I3(out_fifo_12[13]),
        .I4(out_fifo_13),
        .O(\write_buffer.wr_buf_out_data_reg[481] [5]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_20__7
       (.I0(mem_reg_0_15_78_79[360]),
        .I1(phy_wrdata[376]),
        .I2(out_fifo_25),
        .I3(out_fifo_14[5]),
        .I4(out_fifo_15),
        .O(\write_buffer.wr_buf_out_data_reg[488] [5]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_20__8
       (.I0(mem_reg_0_15_78_79[368]),
        .I1(phy_wrdata[376]),
        .I2(out_fifo_25),
        .I3(out_fifo_16[5]),
        .I4(out_fifo_17),
        .O(\write_buffer.wr_buf_out_data_reg[496] [5]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_20__9
       (.I0(mem_reg_0_15_78_79[376]),
        .I1(phy_wrdata[376]),
        .I2(out_fifo_26),
        .I3(out_fifo_18[5]),
        .I4(out_fifo_19),
        .O(\write_buffer.wr_buf_out_data_reg[504] [5]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_21__1
       (.I0(mc_bank[1]),
        .I1(phy_bank[10]),
        .I2(out_fifo_2),
        .I3(out_fifo_0[8]),
        .I4(out_fifo_1),
        .O(\gen_no_mirror.div_clk_loop[0].phy_bank_reg[1]_0 [4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_21__2
       (.I0(mem_reg_0_15_78_79[257]),
        .I1(phy_wrdata[313]),
        .I2(out_fifo_23),
        .I3(out_fifo_3[12]),
        .I4(out_fifo_4),
        .O(D2[4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_21__3
       (.I0(mem_reg_0_15_78_79[264]),
        .I1(phy_wrdata[312]),
        .I2(out_fifo_23),
        .I3(out_fifo_5[4]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[456] [4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_21__4
       (.I0(mem_reg_0_15_78_79[272]),
        .I1(phy_wrdata[312]),
        .I2(out_fifo_24),
        .I3(out_fifo_7[4]),
        .I4(out_fifo_8),
        .O(\write_buffer.wr_buf_out_data_reg[464] [4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_21__5
       (.I0(mem_reg_0_15_78_79[280]),
        .I1(phy_wrdata[312]),
        .I2(out_fifo_24),
        .I3(out_fifo_9[4]),
        .I4(out_fifo_10),
        .O(\write_buffer.wr_buf_out_data_reg[472] [4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_21__6
       (.I0(mem_reg_0_15_78_79[289]),
        .I1(phy_wrdata[313]),
        .I2(out_fifo_24),
        .I3(out_fifo_12[12]),
        .I4(out_fifo_13),
        .O(\write_buffer.wr_buf_out_data_reg[481] [4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_21__7
       (.I0(mem_reg_0_15_78_79[296]),
        .I1(phy_wrdata[312]),
        .I2(out_fifo_24),
        .I3(out_fifo_14[4]),
        .I4(out_fifo_15),
        .O(\write_buffer.wr_buf_out_data_reg[488] [4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_21__8
       (.I0(mem_reg_0_15_78_79[304]),
        .I1(phy_wrdata[312]),
        .I2(out_fifo_24),
        .I3(out_fifo_16[4]),
        .I4(out_fifo_17),
        .O(\write_buffer.wr_buf_out_data_reg[496] [4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_21__9
       (.I0(mem_reg_0_15_78_79[312]),
        .I1(phy_wrdata[312]),
        .I2(out_fifo_24),
        .I3(out_fifo_18[4]),
        .I4(out_fifo_19),
        .O(\write_buffer.wr_buf_out_data_reg[504] [4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_22__0
       (.I0(mem_reg_0_15_78_79[193]),
        .I1(phy_wrdata[249]),
        .I2(out_fifo_22),
        .I3(out_fifo_3[11]),
        .I4(out_fifo_4),
        .O(D2[3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_22__1
       (.I0(mem_reg_0_15_78_79[200]),
        .I1(phy_wrdata[248]),
        .I2(out_fifo_22),
        .I3(out_fifo_5[3]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[456] [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_22__2
       (.I0(mem_reg_0_15_78_79[208]),
        .I1(phy_wrdata[248]),
        .I2(out_fifo_22),
        .I3(out_fifo_7[3]),
        .I4(out_fifo_8),
        .O(\write_buffer.wr_buf_out_data_reg[464] [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_22__3
       (.I0(mem_reg_0_15_78_79[216]),
        .I1(phy_wrdata[248]),
        .I2(out_fifo_22),
        .I3(out_fifo_9[3]),
        .I4(out_fifo_10),
        .O(\write_buffer.wr_buf_out_data_reg[472] [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_22__4
       (.I0(mem_reg_0_15_78_79[225]),
        .I1(phy_wrdata[249]),
        .I2(out_fifo_23),
        .I3(out_fifo_12[11]),
        .I4(out_fifo_13),
        .O(\write_buffer.wr_buf_out_data_reg[481] [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_22__5
       (.I0(mem_reg_0_15_78_79[232]),
        .I1(phy_wrdata[248]),
        .I2(out_fifo_23),
        .I3(out_fifo_14[3]),
        .I4(out_fifo_15),
        .O(\write_buffer.wr_buf_out_data_reg[488] [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_22__6
       (.I0(mem_reg_0_15_78_79[240]),
        .I1(phy_wrdata[248]),
        .I2(out_fifo_23),
        .I3(out_fifo_16[3]),
        .I4(out_fifo_17),
        .O(\write_buffer.wr_buf_out_data_reg[496] [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_22__7
       (.I0(mem_reg_0_15_78_79[248]),
        .I1(phy_wrdata[248]),
        .I2(out_fifo_23),
        .I3(out_fifo_18[3]),
        .I4(out_fifo_19),
        .O(\write_buffer.wr_buf_out_data_reg[504] [3]));
  LUT4 #(
    .INIT(16'hEEF0)) 
    out_fifo_i_22__8
       (.I0(phy_bank[11]),
        .I1(out_fifo_31),
        .I2(out_fifo_0[7]),
        .I3(out_fifo_1),
        .O(\gen_no_mirror.div_clk_loop[0].phy_bank_reg[1]_0 [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_23__0
       (.I0(mc_bank[8]),
        .I1(phy_bank[11]),
        .I2(out_fifo_2),
        .I3(out_fifo_0[6]),
        .I4(out_fifo_1),
        .O(\gen_no_mirror.div_clk_loop[0].phy_bank_reg[1]_0 [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_23__1
       (.I0(mem_reg_0_15_78_79[129]),
        .I1(phy_wrdata[185]),
        .I2(out_fifo_21),
        .I3(out_fifo_3[10]),
        .I4(out_fifo_4),
        .O(D2[2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_23__2
       (.I0(mem_reg_0_15_78_79[136]),
        .I1(phy_wrdata[184]),
        .I2(out_fifo_21),
        .I3(out_fifo_5[2]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[456] [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_23__3
       (.I0(mem_reg_0_15_78_79[144]),
        .I1(phy_wrdata[184]),
        .I2(out_fifo_21),
        .I3(out_fifo_7[2]),
        .I4(out_fifo_8),
        .O(\write_buffer.wr_buf_out_data_reg[464] [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_23__4
       (.I0(mem_reg_0_15_78_79[152]),
        .I1(phy_wrdata[184]),
        .I2(out_fifo_21),
        .I3(out_fifo_9[2]),
        .I4(out_fifo_10),
        .O(\write_buffer.wr_buf_out_data_reg[472] [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_23__5
       (.I0(mem_reg_0_15_78_79[161]),
        .I1(phy_wrdata[185]),
        .I2(out_fifo_21),
        .I3(out_fifo_12[10]),
        .I4(out_fifo_13),
        .O(\write_buffer.wr_buf_out_data_reg[481] [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_23__6
       (.I0(mem_reg_0_15_78_79[168]),
        .I1(phy_wrdata[184]),
        .I2(out_fifo_21),
        .I3(out_fifo_14[2]),
        .I4(out_fifo_15),
        .O(\write_buffer.wr_buf_out_data_reg[488] [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_23__7
       (.I0(mem_reg_0_15_78_79[176]),
        .I1(phy_wrdata[184]),
        .I2(out_fifo_22),
        .I3(out_fifo_16[2]),
        .I4(out_fifo_17),
        .O(\write_buffer.wr_buf_out_data_reg[496] [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_23__8
       (.I0(mem_reg_0_15_78_79[184]),
        .I1(phy_wrdata[184]),
        .I2(out_fifo_22),
        .I3(out_fifo_18[2]),
        .I4(out_fifo_19),
        .O(\write_buffer.wr_buf_out_data_reg[504] [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_24__1
       (.I0(mc_bank[5]),
        .I1(phy_bank[11]),
        .I2(out_fifo_2),
        .I3(out_fifo_0[5]),
        .I4(out_fifo_1),
        .O(\gen_no_mirror.div_clk_loop[0].phy_bank_reg[1]_0 [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_24__2
       (.I0(mem_reg_0_15_78_79[65]),
        .I1(phy_wrdata[121]),
        .I2(out_fifo_11),
        .I3(out_fifo_3[9]),
        .I4(out_fifo_4),
        .O(D2[1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_24__3
       (.I0(mem_reg_0_15_78_79[72]),
        .I1(phy_wrdata[120]),
        .I2(out_fifo_11),
        .I3(out_fifo_5[1]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[456] [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_24__4
       (.I0(mem_reg_0_15_78_79[80]),
        .I1(phy_wrdata[120]),
        .I2(out_fifo_20),
        .I3(out_fifo_7[1]),
        .I4(out_fifo_8),
        .O(\write_buffer.wr_buf_out_data_reg[464] [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_24__5
       (.I0(mem_reg_0_15_78_79[88]),
        .I1(phy_wrdata[120]),
        .I2(out_fifo_20),
        .I3(out_fifo_9[1]),
        .I4(out_fifo_10),
        .O(\write_buffer.wr_buf_out_data_reg[472] [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_24__6
       (.I0(mem_reg_0_15_78_79[97]),
        .I1(phy_wrdata[121]),
        .I2(out_fifo_20),
        .I3(out_fifo_12[9]),
        .I4(out_fifo_13),
        .O(\write_buffer.wr_buf_out_data_reg[481] [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_24__7
       (.I0(mem_reg_0_15_78_79[104]),
        .I1(phy_wrdata[120]),
        .I2(out_fifo_20),
        .I3(out_fifo_14[1]),
        .I4(out_fifo_15),
        .O(\write_buffer.wr_buf_out_data_reg[488] [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_24__8
       (.I0(mem_reg_0_15_78_79[112]),
        .I1(phy_wrdata[120]),
        .I2(out_fifo_20),
        .I3(out_fifo_16[1]),
        .I4(out_fifo_17),
        .O(\write_buffer.wr_buf_out_data_reg[496] [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_24__9
       (.I0(mem_reg_0_15_78_79[120]),
        .I1(phy_wrdata[120]),
        .I2(out_fifo_20),
        .I3(out_fifo_18[1]),
        .I4(out_fifo_19),
        .O(\write_buffer.wr_buf_out_data_reg[504] [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_25__0
       (.I0(mc_bank[2]),
        .I1(phy_bank[11]),
        .I2(out_fifo_2),
        .I3(out_fifo_0[4]),
        .I4(out_fifo_1),
        .O(\gen_no_mirror.div_clk_loop[0].phy_bank_reg[1]_0 [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_25__1
       (.I0(mem_reg_0_15_78_79[1]),
        .I1(phy_wrdata[57]),
        .I2(out_fifo_2),
        .I3(out_fifo_3[8]),
        .I4(out_fifo_4),
        .O(D2[0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_25__2
       (.I0(mem_reg_0_15_78_79[8]),
        .I1(phy_wrdata[56]),
        .I2(out_fifo_2),
        .I3(out_fifo_5[0]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[456] [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_25__3
       (.I0(mem_reg_0_15_78_79[16]),
        .I1(phy_wrdata[56]),
        .I2(out_fifo_2),
        .I3(out_fifo_7[0]),
        .I4(out_fifo_8),
        .O(\write_buffer.wr_buf_out_data_reg[464] [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_25__4
       (.I0(mem_reg_0_15_78_79[24]),
        .I1(phy_wrdata[56]),
        .I2(out_fifo_2),
        .I3(out_fifo_9[0]),
        .I4(out_fifo_10),
        .O(\write_buffer.wr_buf_out_data_reg[472] [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_25__5
       (.I0(mem_reg_0_15_78_79[33]),
        .I1(phy_wrdata[57]),
        .I2(out_fifo_11),
        .I3(out_fifo_12[8]),
        .I4(out_fifo_13),
        .O(\write_buffer.wr_buf_out_data_reg[481] [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_25__6
       (.I0(mem_reg_0_15_78_79[40]),
        .I1(phy_wrdata[56]),
        .I2(out_fifo_11),
        .I3(out_fifo_14[0]),
        .I4(out_fifo_15),
        .O(\write_buffer.wr_buf_out_data_reg[488] [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_25__7
       (.I0(mem_reg_0_15_78_79[48]),
        .I1(phy_wrdata[56]),
        .I2(out_fifo_11),
        .I3(out_fifo_16[0]),
        .I4(out_fifo_17),
        .O(\write_buffer.wr_buf_out_data_reg[496] [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_25__8
       (.I0(mem_reg_0_15_78_79[56]),
        .I1(phy_wrdata[56]),
        .I2(out_fifo_11),
        .I3(out_fifo_18[0]),
        .I4(out_fifo_19),
        .O(\write_buffer.wr_buf_out_data_reg[504] [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_26__1
       (.I0(mem_reg_0_15_78_79[450]),
        .I1(phy_wrdata[506]),
        .I2(out_fifo_27),
        .I3(out_fifo_3[23]),
        .I4(out_fifo_4),
        .O(\write_buffer.wr_buf_out_data_reg[450] [7]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_26__2
       (.I0(mem_reg_0_15_78_79[457]),
        .I1(phy_wrdata[505]),
        .I2(out_fifo_27),
        .I3(out_fifo_5[15]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[457] [7]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_26__3
       (.I0(mem_reg_0_15_78_79[465]),
        .I1(phy_wrdata[505]),
        .I2(out_fifo_27),
        .I3(out_fifo_7[15]),
        .I4(out_fifo_8),
        .O(\write_buffer.wr_buf_out_data_reg[465] [7]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_26__4
       (.I0(mem_reg_0_15_78_79[473]),
        .I1(phy_wrdata[505]),
        .I2(out_fifo_28),
        .I3(out_fifo_9[15]),
        .I4(out_fifo_10),
        .O(\write_buffer.wr_buf_out_data_reg[473] [7]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_26__5
       (.I0(mem_reg_0_15_78_79[482]),
        .I1(phy_wrdata[506]),
        .I2(out_fifo_28),
        .I3(out_fifo_12[23]),
        .I4(out_fifo_13),
        .O(\write_buffer.wr_buf_out_data_reg[482] [7]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_26__6
       (.I0(mem_reg_0_15_78_79[489]),
        .I1(phy_wrdata[505]),
        .I2(out_fifo_28),
        .I3(out_fifo_14[15]),
        .I4(out_fifo_15),
        .O(\write_buffer.wr_buf_out_data_reg[489] [7]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_26__7
       (.I0(mem_reg_0_15_78_79[497]),
        .I1(phy_wrdata[505]),
        .I2(out_fifo_28),
        .I3(out_fifo_16[15]),
        .I4(out_fifo_17),
        .O(\write_buffer.wr_buf_out_data_reg[497] [7]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_26__8
       (.I0(mem_reg_0_15_78_79[505]),
        .I1(phy_wrdata[505]),
        .I2(out_fifo_28),
        .I3(out_fifo_18[15]),
        .I4(out_fifo_19),
        .O(\write_buffer.wr_buf_out_data_reg[505] [7]));
  LUT4 #(
    .INIT(16'hEEF0)) 
    out_fifo_i_26__9
       (.I0(phy_bank[9]),
        .I1(out_fifo_31),
        .I2(out_fifo_0[15]),
        .I3(out_fifo_1),
        .O(\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0]_0 [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_27__0
       (.I0(mc_bank[6]),
        .I1(phy_bank[9]),
        .I2(out_fifo_2),
        .I3(out_fifo_0[14]),
        .I4(out_fifo_1),
        .O(\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0]_0 [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_27__1
       (.I0(mem_reg_0_15_78_79[386]),
        .I1(phy_wrdata[442]),
        .I2(out_fifo_26),
        .I3(out_fifo_3[22]),
        .I4(out_fifo_4),
        .O(\write_buffer.wr_buf_out_data_reg[450] [6]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_27__2
       (.I0(mem_reg_0_15_78_79[393]),
        .I1(phy_wrdata[441]),
        .I2(out_fifo_26),
        .I3(out_fifo_5[14]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[457] [6]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_27__3
       (.I0(mem_reg_0_15_78_79[401]),
        .I1(phy_wrdata[441]),
        .I2(out_fifo_26),
        .I3(out_fifo_7[14]),
        .I4(out_fifo_8),
        .O(\write_buffer.wr_buf_out_data_reg[465] [6]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_27__4
       (.I0(mem_reg_0_15_78_79[409]),
        .I1(phy_wrdata[441]),
        .I2(out_fifo_26),
        .I3(out_fifo_9[14]),
        .I4(out_fifo_10),
        .O(\write_buffer.wr_buf_out_data_reg[473] [6]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_27__5
       (.I0(mem_reg_0_15_78_79[418]),
        .I1(phy_wrdata[442]),
        .I2(out_fifo_26),
        .I3(out_fifo_12[22]),
        .I4(out_fifo_13),
        .O(\write_buffer.wr_buf_out_data_reg[482] [6]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_27__6
       (.I0(mem_reg_0_15_78_79[425]),
        .I1(phy_wrdata[441]),
        .I2(out_fifo_27),
        .I3(out_fifo_14[14]),
        .I4(out_fifo_15),
        .O(\write_buffer.wr_buf_out_data_reg[489] [6]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_27__7
       (.I0(mem_reg_0_15_78_79[433]),
        .I1(phy_wrdata[441]),
        .I2(out_fifo_27),
        .I3(out_fifo_16[14]),
        .I4(out_fifo_17),
        .O(\write_buffer.wr_buf_out_data_reg[497] [6]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_27__8
       (.I0(mem_reg_0_15_78_79[441]),
        .I1(phy_wrdata[441]),
        .I2(out_fifo_27),
        .I3(out_fifo_18[14]),
        .I4(out_fifo_19),
        .O(\write_buffer.wr_buf_out_data_reg[505] [6]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_28__0
       (.I0(mc_bank[3]),
        .I1(phy_bank[9]),
        .I2(out_fifo_2),
        .I3(out_fifo_0[13]),
        .I4(out_fifo_1),
        .O(\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0]_0 [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_28__1
       (.I0(mem_reg_0_15_78_79[322]),
        .I1(phy_wrdata[378]),
        .I2(out_fifo_25),
        .I3(out_fifo_3[21]),
        .I4(out_fifo_4),
        .O(\write_buffer.wr_buf_out_data_reg[450] [5]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_28__2
       (.I0(mem_reg_0_15_78_79[329]),
        .I1(phy_wrdata[377]),
        .I2(out_fifo_25),
        .I3(out_fifo_5[13]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[457] [5]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_28__3
       (.I0(mem_reg_0_15_78_79[337]),
        .I1(phy_wrdata[377]),
        .I2(out_fifo_25),
        .I3(out_fifo_7[13]),
        .I4(out_fifo_8),
        .O(\write_buffer.wr_buf_out_data_reg[465] [5]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_28__4
       (.I0(mem_reg_0_15_78_79[345]),
        .I1(phy_wrdata[377]),
        .I2(out_fifo_25),
        .I3(out_fifo_9[13]),
        .I4(out_fifo_10),
        .O(\write_buffer.wr_buf_out_data_reg[473] [5]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_28__5
       (.I0(mem_reg_0_15_78_79[354]),
        .I1(phy_wrdata[378]),
        .I2(out_fifo_25),
        .I3(out_fifo_12[21]),
        .I4(out_fifo_13),
        .O(\write_buffer.wr_buf_out_data_reg[482] [5]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_28__6
       (.I0(mem_reg_0_15_78_79[361]),
        .I1(phy_wrdata[377]),
        .I2(out_fifo_25),
        .I3(out_fifo_14[13]),
        .I4(out_fifo_15),
        .O(\write_buffer.wr_buf_out_data_reg[489] [5]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_28__7
       (.I0(mem_reg_0_15_78_79[369]),
        .I1(phy_wrdata[377]),
        .I2(out_fifo_25),
        .I3(out_fifo_16[13]),
        .I4(out_fifo_17),
        .O(\write_buffer.wr_buf_out_data_reg[497] [5]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_28__8
       (.I0(mem_reg_0_15_78_79[377]),
        .I1(phy_wrdata[377]),
        .I2(out_fifo_26),
        .I3(out_fifo_18[13]),
        .I4(out_fifo_19),
        .O(\write_buffer.wr_buf_out_data_reg[505] [5]));
  LUT5 #(
    .INIT(32'hB8B8FF00)) 
    out_fifo_i_28__9
       (.I0(mc_cas_n),
        .I1(out_fifo_28),
        .I2(phy_cs_n),
        .I3(out_fifo_29[4]),
        .I4(out_fifo_30),
        .O(\cmd_pipe_plus.mc_cas_n_reg[1] ));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_29__0
       (.I0(mc_bank[0]),
        .I1(phy_bank[9]),
        .I2(out_fifo_2),
        .I3(out_fifo_0[12]),
        .I4(out_fifo_1),
        .O(\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0]_0 [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_29__1
       (.I0(mem_reg_0_15_78_79[258]),
        .I1(phy_wrdata[314]),
        .I2(out_fifo_23),
        .I3(out_fifo_3[20]),
        .I4(out_fifo_4),
        .O(\write_buffer.wr_buf_out_data_reg[450] [4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_29__2
       (.I0(mem_reg_0_15_78_79[265]),
        .I1(phy_wrdata[313]),
        .I2(out_fifo_23),
        .I3(out_fifo_5[12]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[457] [4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_29__3
       (.I0(mem_reg_0_15_78_79[273]),
        .I1(phy_wrdata[313]),
        .I2(out_fifo_24),
        .I3(out_fifo_7[12]),
        .I4(out_fifo_8),
        .O(\write_buffer.wr_buf_out_data_reg[465] [4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_29__4
       (.I0(mem_reg_0_15_78_79[281]),
        .I1(phy_wrdata[313]),
        .I2(out_fifo_24),
        .I3(out_fifo_9[12]),
        .I4(out_fifo_10),
        .O(\write_buffer.wr_buf_out_data_reg[473] [4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_29__5
       (.I0(mem_reg_0_15_78_79[290]),
        .I1(phy_wrdata[314]),
        .I2(out_fifo_24),
        .I3(out_fifo_12[20]),
        .I4(out_fifo_13),
        .O(\write_buffer.wr_buf_out_data_reg[482] [4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_29__6
       (.I0(mem_reg_0_15_78_79[297]),
        .I1(phy_wrdata[313]),
        .I2(out_fifo_24),
        .I3(out_fifo_14[12]),
        .I4(out_fifo_15),
        .O(\write_buffer.wr_buf_out_data_reg[489] [4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_29__7
       (.I0(mem_reg_0_15_78_79[305]),
        .I1(phy_wrdata[313]),
        .I2(out_fifo_24),
        .I3(out_fifo_16[12]),
        .I4(out_fifo_17),
        .O(\write_buffer.wr_buf_out_data_reg[497] [4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_29__8
       (.I0(mem_reg_0_15_78_79[313]),
        .I1(phy_wrdata[313]),
        .I2(out_fifo_24),
        .I3(out_fifo_18[12]),
        .I4(out_fifo_19),
        .O(\write_buffer.wr_buf_out_data_reg[505] [4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_30__1
       (.I0(mem_reg_0_15_78_79[194]),
        .I1(phy_wrdata[250]),
        .I2(out_fifo_22),
        .I3(out_fifo_3[19]),
        .I4(out_fifo_4),
        .O(\write_buffer.wr_buf_out_data_reg[450] [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_30__2
       (.I0(mem_reg_0_15_78_79[201]),
        .I1(phy_wrdata[249]),
        .I2(out_fifo_22),
        .I3(out_fifo_5[11]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[457] [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_30__3
       (.I0(mem_reg_0_15_78_79[209]),
        .I1(phy_wrdata[249]),
        .I2(out_fifo_22),
        .I3(out_fifo_7[11]),
        .I4(out_fifo_8),
        .O(\write_buffer.wr_buf_out_data_reg[465] [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_30__4
       (.I0(mem_reg_0_15_78_79[217]),
        .I1(phy_wrdata[249]),
        .I2(out_fifo_22),
        .I3(out_fifo_9[11]),
        .I4(out_fifo_10),
        .O(\write_buffer.wr_buf_out_data_reg[473] [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_30__5
       (.I0(mem_reg_0_15_78_79[226]),
        .I1(phy_wrdata[250]),
        .I2(out_fifo_23),
        .I3(out_fifo_12[19]),
        .I4(out_fifo_13),
        .O(\write_buffer.wr_buf_out_data_reg[482] [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_30__6
       (.I0(mem_reg_0_15_78_79[233]),
        .I1(phy_wrdata[249]),
        .I2(out_fifo_23),
        .I3(out_fifo_14[11]),
        .I4(out_fifo_15),
        .O(\write_buffer.wr_buf_out_data_reg[489] [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_30__7
       (.I0(mem_reg_0_15_78_79[241]),
        .I1(phy_wrdata[249]),
        .I2(out_fifo_23),
        .I3(out_fifo_16[11]),
        .I4(out_fifo_17),
        .O(\write_buffer.wr_buf_out_data_reg[497] [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_30__8
       (.I0(mem_reg_0_15_78_79[249]),
        .I1(phy_wrdata[249]),
        .I2(out_fifo_23),
        .I3(out_fifo_18[11]),
        .I4(out_fifo_19),
        .O(\write_buffer.wr_buf_out_data_reg[505] [3]));
  LUT4 #(
    .INIT(16'hEEF0)) 
    out_fifo_i_30__9
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10] ),
        .I1(out_fifo_31),
        .I2(mem_out[7]),
        .I3(out_fifo),
        .O(D3[3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_31__0
       (.I0(mc_address[33]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10] ),
        .I2(out_fifo_2),
        .I3(mem_out[6]),
        .I4(out_fifo),
        .O(D3[2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_31__1
       (.I0(mem_reg_0_15_78_79[130]),
        .I1(phy_wrdata[186]),
        .I2(out_fifo_21),
        .I3(out_fifo_3[18]),
        .I4(out_fifo_4),
        .O(\write_buffer.wr_buf_out_data_reg[450] [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_31__2
       (.I0(mem_reg_0_15_78_79[137]),
        .I1(phy_wrdata[185]),
        .I2(out_fifo_21),
        .I3(out_fifo_5[10]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[457] [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_31__3
       (.I0(mem_reg_0_15_78_79[145]),
        .I1(phy_wrdata[185]),
        .I2(out_fifo_21),
        .I3(out_fifo_7[10]),
        .I4(out_fifo_8),
        .O(\write_buffer.wr_buf_out_data_reg[465] [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_31__4
       (.I0(mem_reg_0_15_78_79[153]),
        .I1(phy_wrdata[185]),
        .I2(out_fifo_21),
        .I3(out_fifo_9[10]),
        .I4(out_fifo_10),
        .O(\write_buffer.wr_buf_out_data_reg[473] [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_31__5
       (.I0(mem_reg_0_15_78_79[162]),
        .I1(phy_wrdata[186]),
        .I2(out_fifo_21),
        .I3(out_fifo_12[18]),
        .I4(out_fifo_13),
        .O(\write_buffer.wr_buf_out_data_reg[482] [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_31__6
       (.I0(mem_reg_0_15_78_79[169]),
        .I1(phy_wrdata[185]),
        .I2(out_fifo_21),
        .I3(out_fifo_14[10]),
        .I4(out_fifo_15),
        .O(\write_buffer.wr_buf_out_data_reg[489] [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_31__7
       (.I0(mem_reg_0_15_78_79[177]),
        .I1(phy_wrdata[185]),
        .I2(out_fifo_22),
        .I3(out_fifo_16[10]),
        .I4(out_fifo_17),
        .O(\write_buffer.wr_buf_out_data_reg[497] [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_31__8
       (.I0(mem_reg_0_15_78_79[185]),
        .I1(phy_wrdata[185]),
        .I2(out_fifo_22),
        .I3(out_fifo_18[10]),
        .I4(out_fifo_19),
        .O(\write_buffer.wr_buf_out_data_reg[505] [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_32__0
       (.I0(mc_address[22]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10] ),
        .I2(phy_ctl_wr_i1_reg),
        .I3(mem_out[5]),
        .I4(out_fifo),
        .O(D3[1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_32__1
       (.I0(mem_reg_0_15_78_79[66]),
        .I1(phy_wrdata[122]),
        .I2(out_fifo_11),
        .I3(out_fifo_3[17]),
        .I4(out_fifo_4),
        .O(\write_buffer.wr_buf_out_data_reg[450] [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_32__2
       (.I0(mem_reg_0_15_78_79[73]),
        .I1(phy_wrdata[121]),
        .I2(out_fifo_11),
        .I3(out_fifo_5[9]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[457] [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_32__3
       (.I0(mem_reg_0_15_78_79[81]),
        .I1(phy_wrdata[121]),
        .I2(out_fifo_20),
        .I3(out_fifo_7[9]),
        .I4(out_fifo_8),
        .O(\write_buffer.wr_buf_out_data_reg[465] [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_32__4
       (.I0(mem_reg_0_15_78_79[89]),
        .I1(phy_wrdata[121]),
        .I2(out_fifo_20),
        .I3(out_fifo_9[9]),
        .I4(out_fifo_10),
        .O(\write_buffer.wr_buf_out_data_reg[473] [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_32__5
       (.I0(mem_reg_0_15_78_79[98]),
        .I1(phy_wrdata[122]),
        .I2(out_fifo_20),
        .I3(out_fifo_12[17]),
        .I4(out_fifo_13),
        .O(\write_buffer.wr_buf_out_data_reg[482] [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_32__6
       (.I0(mem_reg_0_15_78_79[105]),
        .I1(phy_wrdata[121]),
        .I2(out_fifo_20),
        .I3(out_fifo_14[9]),
        .I4(out_fifo_15),
        .O(\write_buffer.wr_buf_out_data_reg[489] [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_32__7
       (.I0(mem_reg_0_15_78_79[113]),
        .I1(phy_wrdata[121]),
        .I2(out_fifo_20),
        .I3(out_fifo_16[9]),
        .I4(out_fifo_17),
        .O(\write_buffer.wr_buf_out_data_reg[497] [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_32__8
       (.I0(mem_reg_0_15_78_79[121]),
        .I1(phy_wrdata[121]),
        .I2(out_fifo_20),
        .I3(out_fifo_18[9]),
        .I4(out_fifo_19),
        .O(\write_buffer.wr_buf_out_data_reg[505] [1]));
  LUT5 #(
    .INIT(32'hB8B8FF00)) 
    out_fifo_i_32__9
       (.I0(mc_ras_n),
        .I1(out_fifo_28),
        .I2(phy_ras_n),
        .I3(out_fifo_29[6]),
        .I4(out_fifo_30),
        .O(\cmd_pipe_plus.mc_ras_n_reg[1] [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_33__0
       (.I0(mc_address[10]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[10] ),
        .I2(phy_ctl_wr_i1_reg),
        .I3(mem_out[4]),
        .I4(out_fifo),
        .O(D3[0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_33__1
       (.I0(mem_reg_0_15_78_79[2]),
        .I1(phy_wrdata[58]),
        .I2(out_fifo_2),
        .I3(out_fifo_3[16]),
        .I4(out_fifo_4),
        .O(\write_buffer.wr_buf_out_data_reg[450] [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_33__2
       (.I0(mem_reg_0_15_78_79[9]),
        .I1(phy_wrdata[57]),
        .I2(out_fifo_2),
        .I3(out_fifo_5[8]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[457] [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_33__3
       (.I0(mem_reg_0_15_78_79[17]),
        .I1(phy_wrdata[57]),
        .I2(out_fifo_2),
        .I3(out_fifo_7[8]),
        .I4(out_fifo_8),
        .O(\write_buffer.wr_buf_out_data_reg[465] [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_33__4
       (.I0(mem_reg_0_15_78_79[25]),
        .I1(phy_wrdata[57]),
        .I2(out_fifo_2),
        .I3(out_fifo_9[8]),
        .I4(out_fifo_10),
        .O(\write_buffer.wr_buf_out_data_reg[473] [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_33__5
       (.I0(mem_reg_0_15_78_79[34]),
        .I1(phy_wrdata[58]),
        .I2(out_fifo_11),
        .I3(out_fifo_12[16]),
        .I4(out_fifo_13),
        .O(\write_buffer.wr_buf_out_data_reg[482] [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_33__6
       (.I0(mem_reg_0_15_78_79[41]),
        .I1(phy_wrdata[57]),
        .I2(out_fifo_11),
        .I3(out_fifo_14[8]),
        .I4(out_fifo_15),
        .O(\write_buffer.wr_buf_out_data_reg[489] [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_33__7
       (.I0(mem_reg_0_15_78_79[49]),
        .I1(phy_wrdata[57]),
        .I2(out_fifo_11),
        .I3(out_fifo_16[8]),
        .I4(out_fifo_17),
        .O(\write_buffer.wr_buf_out_data_reg[497] [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_33__8
       (.I0(mem_reg_0_15_78_79[57]),
        .I1(phy_wrdata[57]),
        .I2(out_fifo_11),
        .I3(out_fifo_18[8]),
        .I4(out_fifo_19),
        .O(\write_buffer.wr_buf_out_data_reg[505] [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_34__2
       (.I0(mem_reg_0_15_78_79[451]),
        .I1(phy_wrdata[507]),
        .I2(out_fifo_27),
        .I3(out_fifo_3[31]),
        .I4(out_fifo_4),
        .O(\write_buffer.wr_buf_out_data_reg[451] [7]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_34__3
       (.I0(mem_reg_0_15_78_79[458]),
        .I1(phy_wrdata[506]),
        .I2(out_fifo_27),
        .I3(out_fifo_5[23]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[458] [7]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_34__4
       (.I0(mem_reg_0_15_78_79[466]),
        .I1(phy_wrdata[506]),
        .I2(out_fifo_27),
        .I3(out_fifo_7[23]),
        .I4(out_fifo_8),
        .O(\write_buffer.wr_buf_out_data_reg[466] [7]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_34__5
       (.I0(mem_reg_0_15_78_79[474]),
        .I1(phy_wrdata[506]),
        .I2(out_fifo_28),
        .I3(out_fifo_9[23]),
        .I4(out_fifo_10),
        .O(\write_buffer.wr_buf_out_data_reg[474] [7]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_34__6
       (.I0(mem_reg_0_15_78_79[483]),
        .I1(phy_wrdata[507]),
        .I2(out_fifo_28),
        .I3(out_fifo_12[31]),
        .I4(out_fifo_13),
        .O(\write_buffer.wr_buf_out_data_reg[483] [7]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_34__7
       (.I0(mem_reg_0_15_78_79[490]),
        .I1(phy_wrdata[506]),
        .I2(out_fifo_28),
        .I3(out_fifo_14[23]),
        .I4(out_fifo_15),
        .O(\write_buffer.wr_buf_out_data_reg[490] [7]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_34__8
       (.I0(mem_reg_0_15_78_79[498]),
        .I1(phy_wrdata[506]),
        .I2(out_fifo_28),
        .I3(out_fifo_16[23]),
        .I4(out_fifo_17),
        .O(\write_buffer.wr_buf_out_data_reg[498] [7]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_34__9
       (.I0(mem_reg_0_15_78_79[506]),
        .I1(phy_wrdata[506]),
        .I2(out_fifo_28),
        .I3(out_fifo_18[23]),
        .I4(out_fifo_19),
        .O(\write_buffer.wr_buf_out_data_reg[506] [7]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_35__1
       (.I0(mem_reg_0_15_78_79[387]),
        .I1(phy_wrdata[443]),
        .I2(out_fifo_26),
        .I3(out_fifo_3[30]),
        .I4(out_fifo_4),
        .O(\write_buffer.wr_buf_out_data_reg[451] [6]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_35__2
       (.I0(mem_reg_0_15_78_79[394]),
        .I1(phy_wrdata[442]),
        .I2(out_fifo_26),
        .I3(out_fifo_5[22]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[458] [6]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_35__3
       (.I0(mem_reg_0_15_78_79[402]),
        .I1(phy_wrdata[442]),
        .I2(out_fifo_26),
        .I3(out_fifo_7[22]),
        .I4(out_fifo_8),
        .O(\write_buffer.wr_buf_out_data_reg[466] [6]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_35__4
       (.I0(mem_reg_0_15_78_79[410]),
        .I1(phy_wrdata[442]),
        .I2(out_fifo_26),
        .I3(out_fifo_9[22]),
        .I4(out_fifo_10),
        .O(\write_buffer.wr_buf_out_data_reg[474] [6]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_35__5
       (.I0(mem_reg_0_15_78_79[419]),
        .I1(phy_wrdata[443]),
        .I2(out_fifo_27),
        .I3(out_fifo_12[30]),
        .I4(out_fifo_13),
        .O(\write_buffer.wr_buf_out_data_reg[483] [6]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_35__6
       (.I0(mem_reg_0_15_78_79[426]),
        .I1(phy_wrdata[442]),
        .I2(out_fifo_27),
        .I3(out_fifo_14[22]),
        .I4(out_fifo_15),
        .O(\write_buffer.wr_buf_out_data_reg[490] [6]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_35__7
       (.I0(mem_reg_0_15_78_79[434]),
        .I1(phy_wrdata[442]),
        .I2(out_fifo_27),
        .I3(out_fifo_16[22]),
        .I4(out_fifo_17),
        .O(\write_buffer.wr_buf_out_data_reg[498] [6]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_35__8
       (.I0(mem_reg_0_15_78_79[442]),
        .I1(phy_wrdata[442]),
        .I2(out_fifo_27),
        .I3(out_fifo_18[22]),
        .I4(out_fifo_19),
        .O(\write_buffer.wr_buf_out_data_reg[506] [6]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_36__1
       (.I0(mem_reg_0_15_78_79[323]),
        .I1(phy_wrdata[379]),
        .I2(out_fifo_25),
        .I3(out_fifo_3[29]),
        .I4(out_fifo_4),
        .O(\write_buffer.wr_buf_out_data_reg[451] [5]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_36__2
       (.I0(mem_reg_0_15_78_79[330]),
        .I1(phy_wrdata[378]),
        .I2(out_fifo_25),
        .I3(out_fifo_5[21]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[458] [5]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_36__3
       (.I0(mem_reg_0_15_78_79[338]),
        .I1(phy_wrdata[378]),
        .I2(out_fifo_25),
        .I3(out_fifo_7[21]),
        .I4(out_fifo_8),
        .O(\write_buffer.wr_buf_out_data_reg[466] [5]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_36__4
       (.I0(mem_reg_0_15_78_79[346]),
        .I1(phy_wrdata[378]),
        .I2(out_fifo_25),
        .I3(out_fifo_9[21]),
        .I4(out_fifo_10),
        .O(\write_buffer.wr_buf_out_data_reg[474] [5]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_36__5
       (.I0(mem_reg_0_15_78_79[355]),
        .I1(phy_wrdata[379]),
        .I2(out_fifo_25),
        .I3(out_fifo_12[29]),
        .I4(out_fifo_13),
        .O(\write_buffer.wr_buf_out_data_reg[483] [5]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_36__6
       (.I0(mem_reg_0_15_78_79[362]),
        .I1(phy_wrdata[378]),
        .I2(out_fifo_25),
        .I3(out_fifo_14[21]),
        .I4(out_fifo_15),
        .O(\write_buffer.wr_buf_out_data_reg[490] [5]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_36__7
       (.I0(mem_reg_0_15_78_79[370]),
        .I1(phy_wrdata[378]),
        .I2(out_fifo_26),
        .I3(out_fifo_16[21]),
        .I4(out_fifo_17),
        .O(\write_buffer.wr_buf_out_data_reg[498] [5]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_36__8
       (.I0(mem_reg_0_15_78_79[378]),
        .I1(phy_wrdata[378]),
        .I2(out_fifo_26),
        .I3(out_fifo_18[21]),
        .I4(out_fifo_19),
        .O(\write_buffer.wr_buf_out_data_reg[506] [5]));
  LUT5 #(
    .INIT(32'hB8B8FF00)) 
    out_fifo_i_36__9
       (.I0(mc_cas_n),
        .I1(out_fifo_28),
        .I2(phy_cas_n),
        .I3(out_fifo_29[5]),
        .I4(out_fifo_30),
        .O(\cmd_pipe_plus.mc_ras_n_reg[1] [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_37__1
       (.I0(mem_reg_0_15_78_79[259]),
        .I1(phy_wrdata[315]),
        .I2(out_fifo_23),
        .I3(out_fifo_3[28]),
        .I4(out_fifo_4),
        .O(\write_buffer.wr_buf_out_data_reg[451] [4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_37__2
       (.I0(mem_reg_0_15_78_79[266]),
        .I1(phy_wrdata[314]),
        .I2(out_fifo_23),
        .I3(out_fifo_5[20]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[458] [4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_37__3
       (.I0(mem_reg_0_15_78_79[274]),
        .I1(phy_wrdata[314]),
        .I2(out_fifo_24),
        .I3(out_fifo_7[20]),
        .I4(out_fifo_8),
        .O(\write_buffer.wr_buf_out_data_reg[466] [4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_37__4
       (.I0(mem_reg_0_15_78_79[282]),
        .I1(phy_wrdata[314]),
        .I2(out_fifo_24),
        .I3(out_fifo_9[20]),
        .I4(out_fifo_10),
        .O(\write_buffer.wr_buf_out_data_reg[474] [4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_37__5
       (.I0(mem_reg_0_15_78_79[291]),
        .I1(phy_wrdata[315]),
        .I2(out_fifo_24),
        .I3(out_fifo_12[28]),
        .I4(out_fifo_13),
        .O(\write_buffer.wr_buf_out_data_reg[483] [4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_37__6
       (.I0(mem_reg_0_15_78_79[298]),
        .I1(phy_wrdata[314]),
        .I2(out_fifo_24),
        .I3(out_fifo_14[20]),
        .I4(out_fifo_15),
        .O(\write_buffer.wr_buf_out_data_reg[490] [4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_37__7
       (.I0(mem_reg_0_15_78_79[306]),
        .I1(phy_wrdata[314]),
        .I2(out_fifo_24),
        .I3(out_fifo_16[20]),
        .I4(out_fifo_17),
        .O(\write_buffer.wr_buf_out_data_reg[498] [4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_37__8
       (.I0(mem_reg_0_15_78_79[314]),
        .I1(phy_wrdata[314]),
        .I2(out_fifo_24),
        .I3(out_fifo_18[20]),
        .I4(out_fifo_19),
        .O(\write_buffer.wr_buf_out_data_reg[506] [4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_38__1
       (.I0(mem_reg_0_15_78_79[195]),
        .I1(phy_wrdata[251]),
        .I2(out_fifo_22),
        .I3(out_fifo_3[27]),
        .I4(out_fifo_4),
        .O(\write_buffer.wr_buf_out_data_reg[451] [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_38__2
       (.I0(mem_reg_0_15_78_79[202]),
        .I1(phy_wrdata[250]),
        .I2(out_fifo_22),
        .I3(out_fifo_5[19]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[458] [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_38__3
       (.I0(mem_reg_0_15_78_79[210]),
        .I1(phy_wrdata[250]),
        .I2(out_fifo_22),
        .I3(out_fifo_7[19]),
        .I4(out_fifo_8),
        .O(\write_buffer.wr_buf_out_data_reg[466] [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_38__4
       (.I0(mem_reg_0_15_78_79[218]),
        .I1(phy_wrdata[250]),
        .I2(out_fifo_22),
        .I3(out_fifo_9[19]),
        .I4(out_fifo_10),
        .O(\write_buffer.wr_buf_out_data_reg[474] [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_38__5
       (.I0(mem_reg_0_15_78_79[227]),
        .I1(phy_wrdata[251]),
        .I2(out_fifo_23),
        .I3(out_fifo_12[27]),
        .I4(out_fifo_13),
        .O(\write_buffer.wr_buf_out_data_reg[483] [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_38__6
       (.I0(mem_reg_0_15_78_79[234]),
        .I1(phy_wrdata[250]),
        .I2(out_fifo_23),
        .I3(out_fifo_14[19]),
        .I4(out_fifo_15),
        .O(\write_buffer.wr_buf_out_data_reg[490] [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_38__7
       (.I0(mem_reg_0_15_78_79[242]),
        .I1(phy_wrdata[250]),
        .I2(out_fifo_23),
        .I3(out_fifo_16[19]),
        .I4(out_fifo_17),
        .O(\write_buffer.wr_buf_out_data_reg[498] [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_38__8
       (.I0(mem_reg_0_15_78_79[250]),
        .I1(phy_wrdata[250]),
        .I2(out_fifo_23),
        .I3(out_fifo_18[19]),
        .I4(out_fifo_19),
        .O(\write_buffer.wr_buf_out_data_reg[506] [3]));
  (* SOFT_HLUTNM = "soft_lutpair462" *) 
  LUT4 #(
    .INIT(16'hEEF0)) 
    out_fifo_i_38__9
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ),
        .I1(out_fifo_31),
        .I2(mem_out[11]),
        .I3(out_fifo),
        .O(D4[3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_39__0
       (.I0(mc_address[27]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ),
        .I2(out_fifo_2),
        .I3(mem_out[10]),
        .I4(out_fifo),
        .O(D4[2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_39__1
       (.I0(mem_reg_0_15_78_79[131]),
        .I1(phy_wrdata[187]),
        .I2(out_fifo_21),
        .I3(out_fifo_3[26]),
        .I4(out_fifo_4),
        .O(\write_buffer.wr_buf_out_data_reg[451] [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_39__2
       (.I0(mem_reg_0_15_78_79[138]),
        .I1(phy_wrdata[186]),
        .I2(out_fifo_21),
        .I3(out_fifo_5[18]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[458] [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_39__3
       (.I0(mem_reg_0_15_78_79[146]),
        .I1(phy_wrdata[186]),
        .I2(out_fifo_21),
        .I3(out_fifo_7[18]),
        .I4(out_fifo_8),
        .O(\write_buffer.wr_buf_out_data_reg[466] [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_39__4
       (.I0(mem_reg_0_15_78_79[154]),
        .I1(phy_wrdata[186]),
        .I2(out_fifo_21),
        .I3(out_fifo_9[18]),
        .I4(out_fifo_10),
        .O(\write_buffer.wr_buf_out_data_reg[474] [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_39__5
       (.I0(mem_reg_0_15_78_79[163]),
        .I1(phy_wrdata[187]),
        .I2(out_fifo_21),
        .I3(out_fifo_12[26]),
        .I4(out_fifo_13),
        .O(\write_buffer.wr_buf_out_data_reg[483] [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_39__6
       (.I0(mem_reg_0_15_78_79[170]),
        .I1(phy_wrdata[186]),
        .I2(out_fifo_21),
        .I3(out_fifo_14[18]),
        .I4(out_fifo_15),
        .O(\write_buffer.wr_buf_out_data_reg[490] [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_39__7
       (.I0(mem_reg_0_15_78_79[178]),
        .I1(phy_wrdata[186]),
        .I2(out_fifo_22),
        .I3(out_fifo_16[18]),
        .I4(out_fifo_17),
        .O(\write_buffer.wr_buf_out_data_reg[498] [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_39__8
       (.I0(mem_reg_0_15_78_79[186]),
        .I1(phy_wrdata[186]),
        .I2(out_fifo_22),
        .I3(out_fifo_18[18]),
        .I4(out_fifo_19),
        .O(\write_buffer.wr_buf_out_data_reg[506] [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_40__0
       (.I0(mc_address[16]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ),
        .I2(phy_ctl_wr_i1_reg),
        .I3(mem_out[9]),
        .I4(out_fifo),
        .O(D4[1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_40__1
       (.I0(mem_reg_0_15_78_79[67]),
        .I1(phy_wrdata[123]),
        .I2(out_fifo_11),
        .I3(out_fifo_3[25]),
        .I4(out_fifo_4),
        .O(\write_buffer.wr_buf_out_data_reg[451] [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_40__2
       (.I0(mem_reg_0_15_78_79[74]),
        .I1(phy_wrdata[122]),
        .I2(out_fifo_11),
        .I3(out_fifo_5[17]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[458] [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_40__3
       (.I0(mem_reg_0_15_78_79[82]),
        .I1(phy_wrdata[122]),
        .I2(out_fifo_20),
        .I3(out_fifo_7[17]),
        .I4(out_fifo_8),
        .O(\write_buffer.wr_buf_out_data_reg[466] [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_40__4
       (.I0(mem_reg_0_15_78_79[90]),
        .I1(phy_wrdata[122]),
        .I2(out_fifo_20),
        .I3(out_fifo_9[17]),
        .I4(out_fifo_10),
        .O(\write_buffer.wr_buf_out_data_reg[474] [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_40__5
       (.I0(mem_reg_0_15_78_79[99]),
        .I1(phy_wrdata[123]),
        .I2(out_fifo_20),
        .I3(out_fifo_12[25]),
        .I4(out_fifo_13),
        .O(\write_buffer.wr_buf_out_data_reg[483] [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_40__6
       (.I0(mem_reg_0_15_78_79[106]),
        .I1(phy_wrdata[122]),
        .I2(out_fifo_20),
        .I3(out_fifo_14[17]),
        .I4(out_fifo_15),
        .O(\write_buffer.wr_buf_out_data_reg[490] [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_40__7
       (.I0(mem_reg_0_15_78_79[114]),
        .I1(phy_wrdata[122]),
        .I2(out_fifo_20),
        .I3(out_fifo_16[17]),
        .I4(out_fifo_17),
        .O(\write_buffer.wr_buf_out_data_reg[498] [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_40__8
       (.I0(mem_reg_0_15_78_79[122]),
        .I1(phy_wrdata[122]),
        .I2(out_fifo_20),
        .I3(out_fifo_18[17]),
        .I4(out_fifo_19),
        .O(\write_buffer.wr_buf_out_data_reg[506] [1]));
  LUT5 #(
    .INIT(32'hB8B8FF00)) 
    out_fifo_i_40__9
       (.I0(mc_we_n),
        .I1(out_fifo_31),
        .I2(phy_we_n),
        .I3(out_fifo_29[7]),
        .I4(out_fifo_30),
        .O(\cmd_pipe_plus.mc_we_n_reg[1] ));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_41__0
       (.I0(mc_address[4]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[4] ),
        .I2(phy_ctl_wr_i1_reg),
        .I3(mem_out[8]),
        .I4(out_fifo),
        .O(D4[0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_41__1
       (.I0(mem_reg_0_15_78_79[3]),
        .I1(phy_wrdata[59]),
        .I2(out_fifo_2),
        .I3(out_fifo_3[24]),
        .I4(out_fifo_4),
        .O(\write_buffer.wr_buf_out_data_reg[451] [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_41__2
       (.I0(mem_reg_0_15_78_79[10]),
        .I1(phy_wrdata[58]),
        .I2(out_fifo_2),
        .I3(out_fifo_5[16]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[458] [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_41__3
       (.I0(mem_reg_0_15_78_79[18]),
        .I1(phy_wrdata[58]),
        .I2(out_fifo_2),
        .I3(out_fifo_7[16]),
        .I4(out_fifo_8),
        .O(\write_buffer.wr_buf_out_data_reg[466] [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_41__4
       (.I0(mem_reg_0_15_78_79[26]),
        .I1(phy_wrdata[58]),
        .I2(out_fifo_2),
        .I3(out_fifo_9[16]),
        .I4(out_fifo_10),
        .O(\write_buffer.wr_buf_out_data_reg[474] [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_41__5
       (.I0(mem_reg_0_15_78_79[35]),
        .I1(phy_wrdata[59]),
        .I2(out_fifo_11),
        .I3(out_fifo_12[24]),
        .I4(out_fifo_13),
        .O(\write_buffer.wr_buf_out_data_reg[483] [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_41__6
       (.I0(mem_reg_0_15_78_79[42]),
        .I1(phy_wrdata[58]),
        .I2(out_fifo_11),
        .I3(out_fifo_14[16]),
        .I4(out_fifo_15),
        .O(\write_buffer.wr_buf_out_data_reg[490] [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_41__7
       (.I0(mem_reg_0_15_78_79[50]),
        .I1(phy_wrdata[58]),
        .I2(out_fifo_11),
        .I3(out_fifo_16[16]),
        .I4(out_fifo_17),
        .O(\write_buffer.wr_buf_out_data_reg[498] [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_41__8
       (.I0(mem_reg_0_15_78_79[58]),
        .I1(phy_wrdata[58]),
        .I2(out_fifo_11),
        .I3(out_fifo_18[16]),
        .I4(out_fifo_19),
        .O(\write_buffer.wr_buf_out_data_reg[506] [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_42__1
       (.I0(mem_reg_0_15_78_79[452]),
        .I1(phy_wrdata[508]),
        .I2(out_fifo_27),
        .I3(out_fifo_3[39]),
        .I4(out_fifo_4),
        .O(\write_buffer.wr_buf_out_data_reg[452] [7]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_42__2
       (.I0(mem_reg_0_15_78_79[459]),
        .I1(phy_wrdata[507]),
        .I2(out_fifo_27),
        .I3(out_fifo_5[31]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[459] [7]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_42__3
       (.I0(mem_reg_0_15_78_79[467]),
        .I1(phy_wrdata[507]),
        .I2(out_fifo_27),
        .I3(out_fifo_7[31]),
        .I4(out_fifo_8),
        .O(\write_buffer.wr_buf_out_data_reg[467] [7]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_42__4
       (.I0(mem_reg_0_15_78_79[475]),
        .I1(phy_wrdata[507]),
        .I2(out_fifo_28),
        .I3(out_fifo_9[31]),
        .I4(out_fifo_10),
        .O(\write_buffer.wr_buf_out_data_reg[475] [7]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_42__5
       (.I0(mem_reg_0_15_78_79[484]),
        .I1(phy_wrdata[508]),
        .I2(out_fifo_28),
        .I3(out_fifo_12[39]),
        .I4(out_fifo_13),
        .O(\write_buffer.wr_buf_out_data_reg[484] [7]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_42__6
       (.I0(mem_reg_0_15_78_79[491]),
        .I1(phy_wrdata[507]),
        .I2(out_fifo_28),
        .I3(out_fifo_14[31]),
        .I4(out_fifo_15),
        .O(\write_buffer.wr_buf_out_data_reg[491] [7]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_42__7
       (.I0(mem_reg_0_15_78_79[499]),
        .I1(phy_wrdata[507]),
        .I2(out_fifo_28),
        .I3(out_fifo_16[31]),
        .I4(out_fifo_17),
        .O(\write_buffer.wr_buf_out_data_reg[499] [7]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_42__8
       (.I0(mem_reg_0_15_78_79[507]),
        .I1(phy_wrdata[507]),
        .I2(out_fifo_28),
        .I3(out_fifo_18[31]),
        .I4(out_fifo_19),
        .O(\write_buffer.wr_buf_out_data_reg[507] [7]));
  LUT4 #(
    .INIT(16'hEEF0)) 
    out_fifo_i_42__9
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),
        .I1(out_fifo_31),
        .I2(mem_out[15]),
        .I3(out_fifo),
        .O(D5[3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_43__1
       (.I0(mc_address[26]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),
        .I2(out_fifo_2),
        .I3(mem_out[14]),
        .I4(out_fifo),
        .O(D5[2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_43__2
       (.I0(mem_reg_0_15_78_79[388]),
        .I1(phy_wrdata[444]),
        .I2(out_fifo_26),
        .I3(out_fifo_3[38]),
        .I4(out_fifo_4),
        .O(\write_buffer.wr_buf_out_data_reg[452] [6]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_43__3
       (.I0(mem_reg_0_15_78_79[395]),
        .I1(phy_wrdata[443]),
        .I2(out_fifo_26),
        .I3(out_fifo_5[30]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[459] [6]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_43__4
       (.I0(mem_reg_0_15_78_79[403]),
        .I1(phy_wrdata[443]),
        .I2(out_fifo_26),
        .I3(out_fifo_7[30]),
        .I4(out_fifo_8),
        .O(\write_buffer.wr_buf_out_data_reg[467] [6]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_43__5
       (.I0(mem_reg_0_15_78_79[411]),
        .I1(phy_wrdata[443]),
        .I2(out_fifo_26),
        .I3(out_fifo_9[30]),
        .I4(out_fifo_10),
        .O(\write_buffer.wr_buf_out_data_reg[475] [6]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_43__6
       (.I0(mem_reg_0_15_78_79[420]),
        .I1(phy_wrdata[444]),
        .I2(out_fifo_27),
        .I3(out_fifo_12[38]),
        .I4(out_fifo_13),
        .O(\write_buffer.wr_buf_out_data_reg[484] [6]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_43__7
       (.I0(mem_reg_0_15_78_79[427]),
        .I1(phy_wrdata[443]),
        .I2(out_fifo_27),
        .I3(out_fifo_14[30]),
        .I4(out_fifo_15),
        .O(\write_buffer.wr_buf_out_data_reg[491] [6]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_43__8
       (.I0(mem_reg_0_15_78_79[435]),
        .I1(phy_wrdata[443]),
        .I2(out_fifo_27),
        .I3(out_fifo_16[30]),
        .I4(out_fifo_17),
        .O(\write_buffer.wr_buf_out_data_reg[499] [6]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_43__9
       (.I0(mem_reg_0_15_78_79[443]),
        .I1(phy_wrdata[443]),
        .I2(out_fifo_27),
        .I3(out_fifo_18[30]),
        .I4(out_fifo_19),
        .O(\write_buffer.wr_buf_out_data_reg[507] [6]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_44__1
       (.I0(mc_address[15]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),
        .I2(phy_ctl_wr_i1_reg),
        .I3(mem_out[13]),
        .I4(out_fifo),
        .O(D5[1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_44__2
       (.I0(mem_reg_0_15_78_79[324]),
        .I1(phy_wrdata[380]),
        .I2(out_fifo_25),
        .I3(out_fifo_3[37]),
        .I4(out_fifo_4),
        .O(\write_buffer.wr_buf_out_data_reg[452] [5]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_44__3
       (.I0(mem_reg_0_15_78_79[331]),
        .I1(phy_wrdata[379]),
        .I2(out_fifo_25),
        .I3(out_fifo_5[29]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[459] [5]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_44__4
       (.I0(mem_reg_0_15_78_79[339]),
        .I1(phy_wrdata[379]),
        .I2(out_fifo_25),
        .I3(out_fifo_7[29]),
        .I4(out_fifo_8),
        .O(\write_buffer.wr_buf_out_data_reg[467] [5]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_44__5
       (.I0(mem_reg_0_15_78_79[347]),
        .I1(phy_wrdata[379]),
        .I2(out_fifo_25),
        .I3(out_fifo_9[29]),
        .I4(out_fifo_10),
        .O(\write_buffer.wr_buf_out_data_reg[475] [5]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_44__6
       (.I0(mem_reg_0_15_78_79[356]),
        .I1(phy_wrdata[380]),
        .I2(out_fifo_25),
        .I3(out_fifo_12[37]),
        .I4(out_fifo_13),
        .O(\write_buffer.wr_buf_out_data_reg[484] [5]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_44__7
       (.I0(mem_reg_0_15_78_79[363]),
        .I1(phy_wrdata[379]),
        .I2(out_fifo_25),
        .I3(out_fifo_14[29]),
        .I4(out_fifo_15),
        .O(\write_buffer.wr_buf_out_data_reg[491] [5]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_44__8
       (.I0(mem_reg_0_15_78_79[371]),
        .I1(phy_wrdata[379]),
        .I2(out_fifo_26),
        .I3(out_fifo_16[29]),
        .I4(out_fifo_17),
        .O(\write_buffer.wr_buf_out_data_reg[499] [5]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_44__9
       (.I0(mem_reg_0_15_78_79[379]),
        .I1(phy_wrdata[379]),
        .I2(out_fifo_26),
        .I3(out_fifo_18[29]),
        .I4(out_fifo_19),
        .O(\write_buffer.wr_buf_out_data_reg[507] [5]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_45__1
       (.I0(mc_address[3]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[3] ),
        .I2(phy_ctl_wr_i1_reg),
        .I3(mem_out[12]),
        .I4(out_fifo),
        .O(D5[0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_45__2
       (.I0(mem_reg_0_15_78_79[260]),
        .I1(phy_wrdata[316]),
        .I2(out_fifo_23),
        .I3(out_fifo_3[36]),
        .I4(out_fifo_4),
        .O(\write_buffer.wr_buf_out_data_reg[452] [4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_45__3
       (.I0(mem_reg_0_15_78_79[267]),
        .I1(phy_wrdata[315]),
        .I2(out_fifo_23),
        .I3(out_fifo_5[28]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[459] [4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_45__4
       (.I0(mem_reg_0_15_78_79[275]),
        .I1(phy_wrdata[315]),
        .I2(out_fifo_24),
        .I3(out_fifo_7[28]),
        .I4(out_fifo_8),
        .O(\write_buffer.wr_buf_out_data_reg[467] [4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_45__5
       (.I0(mem_reg_0_15_78_79[283]),
        .I1(phy_wrdata[315]),
        .I2(out_fifo_24),
        .I3(out_fifo_9[28]),
        .I4(out_fifo_10),
        .O(\write_buffer.wr_buf_out_data_reg[475] [4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_45__6
       (.I0(mem_reg_0_15_78_79[292]),
        .I1(phy_wrdata[316]),
        .I2(out_fifo_24),
        .I3(out_fifo_12[36]),
        .I4(out_fifo_13),
        .O(\write_buffer.wr_buf_out_data_reg[484] [4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_45__7
       (.I0(mem_reg_0_15_78_79[299]),
        .I1(phy_wrdata[315]),
        .I2(out_fifo_24),
        .I3(out_fifo_14[28]),
        .I4(out_fifo_15),
        .O(\write_buffer.wr_buf_out_data_reg[491] [4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_45__8
       (.I0(mem_reg_0_15_78_79[307]),
        .I1(phy_wrdata[315]),
        .I2(out_fifo_24),
        .I3(out_fifo_16[28]),
        .I4(out_fifo_17),
        .O(\write_buffer.wr_buf_out_data_reg[499] [4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_45__9
       (.I0(mem_reg_0_15_78_79[315]),
        .I1(phy_wrdata[315]),
        .I2(out_fifo_24),
        .I3(out_fifo_18[28]),
        .I4(out_fifo_19),
        .O(\write_buffer.wr_buf_out_data_reg[507] [4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_46
       (.I0(mem_reg_0_15_78_79[196]),
        .I1(phy_wrdata[252]),
        .I2(out_fifo_22),
        .I3(out_fifo_3[35]),
        .I4(out_fifo_4),
        .O(\write_buffer.wr_buf_out_data_reg[452] [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_46__0
       (.I0(mem_reg_0_15_78_79[203]),
        .I1(phy_wrdata[251]),
        .I2(out_fifo_22),
        .I3(out_fifo_5[27]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[459] [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_46__1
       (.I0(mem_reg_0_15_78_79[211]),
        .I1(phy_wrdata[251]),
        .I2(out_fifo_22),
        .I3(out_fifo_7[27]),
        .I4(out_fifo_8),
        .O(\write_buffer.wr_buf_out_data_reg[467] [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_46__2
       (.I0(mem_reg_0_15_78_79[219]),
        .I1(phy_wrdata[251]),
        .I2(out_fifo_22),
        .I3(out_fifo_9[27]),
        .I4(out_fifo_10),
        .O(\write_buffer.wr_buf_out_data_reg[475] [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_46__3
       (.I0(mem_reg_0_15_78_79[228]),
        .I1(phy_wrdata[252]),
        .I2(out_fifo_23),
        .I3(out_fifo_12[35]),
        .I4(out_fifo_13),
        .O(\write_buffer.wr_buf_out_data_reg[484] [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_46__4
       (.I0(mem_reg_0_15_78_79[235]),
        .I1(phy_wrdata[251]),
        .I2(out_fifo_23),
        .I3(out_fifo_14[27]),
        .I4(out_fifo_15),
        .O(\write_buffer.wr_buf_out_data_reg[491] [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_46__5
       (.I0(mem_reg_0_15_78_79[243]),
        .I1(phy_wrdata[251]),
        .I2(out_fifo_23),
        .I3(out_fifo_16[27]),
        .I4(out_fifo_17),
        .O(\write_buffer.wr_buf_out_data_reg[499] [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_46__6
       (.I0(mem_reg_0_15_78_79[251]),
        .I1(phy_wrdata[251]),
        .I2(out_fifo_23),
        .I3(out_fifo_18[27]),
        .I4(out_fifo_19),
        .O(\write_buffer.wr_buf_out_data_reg[507] [3]));
  LUT5 #(
    .INIT(32'hB8B8FF00)) 
    out_fifo_i_46__7
       (.I0(mc_cke),
        .I1(out_fifo_31),
        .I2(calib_cke),
        .I3(out_fifo_29[11]),
        .I4(out_fifo_30),
        .O(\cmd_pipe_plus.mc_cke_reg[3] [3]));
  LUT4 #(
    .INIT(16'hEEF0)) 
    out_fifo_i_46__8
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ),
        .I1(out_fifo_31),
        .I2(out_fifo_0[19]),
        .I3(out_fifo_1),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[2]_0 [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_47
       (.I0(mc_address[25]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ),
        .I2(out_fifo_2),
        .I3(out_fifo_0[18]),
        .I4(out_fifo_1),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[2]_0 [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_47__0
       (.I0(mem_reg_0_15_78_79[132]),
        .I1(phy_wrdata[188]),
        .I2(out_fifo_21),
        .I3(out_fifo_3[34]),
        .I4(out_fifo_4),
        .O(\write_buffer.wr_buf_out_data_reg[452] [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_47__1
       (.I0(mem_reg_0_15_78_79[139]),
        .I1(phy_wrdata[187]),
        .I2(out_fifo_21),
        .I3(out_fifo_5[26]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[459] [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_47__2
       (.I0(mem_reg_0_15_78_79[147]),
        .I1(phy_wrdata[187]),
        .I2(out_fifo_21),
        .I3(out_fifo_7[26]),
        .I4(out_fifo_8),
        .O(\write_buffer.wr_buf_out_data_reg[467] [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_47__3
       (.I0(mem_reg_0_15_78_79[155]),
        .I1(phy_wrdata[187]),
        .I2(out_fifo_21),
        .I3(out_fifo_9[26]),
        .I4(out_fifo_10),
        .O(\write_buffer.wr_buf_out_data_reg[475] [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_47__4
       (.I0(mem_reg_0_15_78_79[164]),
        .I1(phy_wrdata[188]),
        .I2(out_fifo_21),
        .I3(out_fifo_12[34]),
        .I4(out_fifo_13),
        .O(\write_buffer.wr_buf_out_data_reg[484] [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_47__5
       (.I0(mem_reg_0_15_78_79[171]),
        .I1(phy_wrdata[187]),
        .I2(out_fifo_21),
        .I3(out_fifo_14[26]),
        .I4(out_fifo_15),
        .O(\write_buffer.wr_buf_out_data_reg[491] [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_47__6
       (.I0(mem_reg_0_15_78_79[179]),
        .I1(phy_wrdata[187]),
        .I2(out_fifo_22),
        .I3(out_fifo_16[26]),
        .I4(out_fifo_17),
        .O(\write_buffer.wr_buf_out_data_reg[499] [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_47__7
       (.I0(mem_reg_0_15_78_79[187]),
        .I1(phy_wrdata[187]),
        .I2(out_fifo_22),
        .I3(out_fifo_18[26]),
        .I4(out_fifo_19),
        .O(\write_buffer.wr_buf_out_data_reg[507] [2]));
  LUT5 #(
    .INIT(32'hB8B8FF00)) 
    out_fifo_i_47__8
       (.I0(mc_cke),
        .I1(out_fifo_31),
        .I2(calib_cke),
        .I3(out_fifo_29[10]),
        .I4(out_fifo_30),
        .O(\cmd_pipe_plus.mc_cke_reg[3] [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_48
       (.I0(mc_address[14]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ),
        .I2(phy_ctl_wr_i1_reg),
        .I3(out_fifo_0[17]),
        .I4(out_fifo_1),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[2]_0 [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_48__1
       (.I0(mem_reg_0_15_78_79[68]),
        .I1(phy_wrdata[124]),
        .I2(out_fifo_11),
        .I3(out_fifo_3[33]),
        .I4(out_fifo_4),
        .O(\write_buffer.wr_buf_out_data_reg[452] [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_48__2
       (.I0(mem_reg_0_15_78_79[75]),
        .I1(phy_wrdata[123]),
        .I2(out_fifo_11),
        .I3(out_fifo_5[25]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[459] [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_48__3
       (.I0(mem_reg_0_15_78_79[83]),
        .I1(phy_wrdata[123]),
        .I2(out_fifo_20),
        .I3(out_fifo_7[25]),
        .I4(out_fifo_8),
        .O(\write_buffer.wr_buf_out_data_reg[467] [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_48__4
       (.I0(mem_reg_0_15_78_79[91]),
        .I1(phy_wrdata[123]),
        .I2(out_fifo_20),
        .I3(out_fifo_9[25]),
        .I4(out_fifo_10),
        .O(\write_buffer.wr_buf_out_data_reg[475] [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_48__5
       (.I0(mem_reg_0_15_78_79[100]),
        .I1(phy_wrdata[124]),
        .I2(out_fifo_20),
        .I3(out_fifo_12[33]),
        .I4(out_fifo_13),
        .O(\write_buffer.wr_buf_out_data_reg[484] [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_48__6
       (.I0(mem_reg_0_15_78_79[107]),
        .I1(phy_wrdata[123]),
        .I2(out_fifo_20),
        .I3(out_fifo_14[25]),
        .I4(out_fifo_15),
        .O(\write_buffer.wr_buf_out_data_reg[491] [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_48__7
       (.I0(mem_reg_0_15_78_79[115]),
        .I1(phy_wrdata[123]),
        .I2(out_fifo_20),
        .I3(out_fifo_16[25]),
        .I4(out_fifo_17),
        .O(\write_buffer.wr_buf_out_data_reg[499] [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_48__8
       (.I0(mem_reg_0_15_78_79[123]),
        .I1(phy_wrdata[123]),
        .I2(out_fifo_20),
        .I3(out_fifo_18[25]),
        .I4(out_fifo_19),
        .O(\write_buffer.wr_buf_out_data_reg[507] [1]));
  LUT5 #(
    .INIT(32'hB8B8FF00)) 
    out_fifo_i_48__9
       (.I0(mc_cke),
        .I1(out_fifo_31),
        .I2(calib_cke),
        .I3(out_fifo_29[9]),
        .I4(out_fifo_30),
        .O(\cmd_pipe_plus.mc_cke_reg[3] [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_49
       (.I0(mc_address[2]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[2] ),
        .I2(phy_ctl_wr_i1_reg),
        .I3(out_fifo_0[16]),
        .I4(out_fifo_1),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[2]_0 [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_49__0
       (.I0(mem_reg_0_15_78_79[4]),
        .I1(phy_wrdata[60]),
        .I2(out_fifo_2),
        .I3(out_fifo_3[32]),
        .I4(out_fifo_4),
        .O(\write_buffer.wr_buf_out_data_reg[452] [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_49__1
       (.I0(mem_reg_0_15_78_79[11]),
        .I1(phy_wrdata[59]),
        .I2(out_fifo_2),
        .I3(out_fifo_5[24]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[459] [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_49__2
       (.I0(mem_reg_0_15_78_79[19]),
        .I1(phy_wrdata[59]),
        .I2(out_fifo_2),
        .I3(out_fifo_7[24]),
        .I4(out_fifo_8),
        .O(\write_buffer.wr_buf_out_data_reg[467] [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_49__3
       (.I0(mem_reg_0_15_78_79[27]),
        .I1(phy_wrdata[59]),
        .I2(out_fifo_11),
        .I3(out_fifo_9[24]),
        .I4(out_fifo_10),
        .O(\write_buffer.wr_buf_out_data_reg[475] [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_49__4
       (.I0(mem_reg_0_15_78_79[36]),
        .I1(phy_wrdata[60]),
        .I2(out_fifo_11),
        .I3(out_fifo_12[32]),
        .I4(out_fifo_13),
        .O(\write_buffer.wr_buf_out_data_reg[484] [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_49__5
       (.I0(mem_reg_0_15_78_79[43]),
        .I1(phy_wrdata[59]),
        .I2(out_fifo_11),
        .I3(out_fifo_14[24]),
        .I4(out_fifo_15),
        .O(\write_buffer.wr_buf_out_data_reg[491] [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_49__6
       (.I0(mem_reg_0_15_78_79[51]),
        .I1(phy_wrdata[59]),
        .I2(out_fifo_11),
        .I3(out_fifo_16[24]),
        .I4(out_fifo_17),
        .O(\write_buffer.wr_buf_out_data_reg[499] [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_49__7
       (.I0(mem_reg_0_15_78_79[59]),
        .I1(phy_wrdata[59]),
        .I2(out_fifo_11),
        .I3(out_fifo_18[24]),
        .I4(out_fifo_19),
        .O(\write_buffer.wr_buf_out_data_reg[507] [0]));
  LUT5 #(
    .INIT(32'hB8B8FF00)) 
    out_fifo_i_49__8
       (.I0(mc_cke),
        .I1(out_fifo_31),
        .I2(calib_cke),
        .I3(out_fifo_29[8]),
        .I4(out_fifo_30),
        .O(\cmd_pipe_plus.mc_cke_reg[3] [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_50__0
       (.I0(mem_reg_0_15_78_79[453]),
        .I1(phy_wrdata[509]),
        .I2(out_fifo_27),
        .I3(out_fifo_3[47]),
        .I4(out_fifo_4),
        .O(\write_buffer.wr_buf_out_data_reg[453] [7]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_50__1
       (.I0(mem_reg_0_15_78_79[460]),
        .I1(phy_wrdata[508]),
        .I2(out_fifo_27),
        .I3(out_fifo_5[39]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[460] [7]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_50__2
       (.I0(mem_reg_0_15_78_79[468]),
        .I1(phy_wrdata[508]),
        .I2(out_fifo_28),
        .I3(out_fifo_7[39]),
        .I4(out_fifo_8),
        .O(\write_buffer.wr_buf_out_data_reg[468] [7]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_50__3
       (.I0(mem_reg_0_15_78_79[476]),
        .I1(phy_wrdata[508]),
        .I2(out_fifo_28),
        .I3(out_fifo_9[39]),
        .I4(out_fifo_10),
        .O(\write_buffer.wr_buf_out_data_reg[476] [7]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_50__4
       (.I0(mem_reg_0_15_78_79[485]),
        .I1(phy_wrdata[509]),
        .I2(out_fifo_28),
        .I3(out_fifo_12[47]),
        .I4(out_fifo_13),
        .O(\write_buffer.wr_buf_out_data_reg[485] [7]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_50__5
       (.I0(mem_reg_0_15_78_79[492]),
        .I1(phy_wrdata[508]),
        .I2(out_fifo_28),
        .I3(out_fifo_14[39]),
        .I4(out_fifo_15),
        .O(\write_buffer.wr_buf_out_data_reg[492] [7]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_50__6
       (.I0(mem_reg_0_15_78_79[500]),
        .I1(phy_wrdata[508]),
        .I2(out_fifo_28),
        .I3(out_fifo_16[39]),
        .I4(out_fifo_17),
        .O(\write_buffer.wr_buf_out_data_reg[500] [7]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_50__7
       (.I0(mem_reg_0_15_78_79[508]),
        .I1(phy_wrdata[508]),
        .I2(out_fifo_28),
        .I3(out_fifo_18[39]),
        .I4(out_fifo_19),
        .O(\write_buffer.wr_buf_out_data_reg[508] [7]));
  LUT4 #(
    .INIT(16'hEEF0)) 
    out_fifo_i_50__8
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ),
        .I1(out_fifo_31),
        .I2(mem_out[23]),
        .I3(out_fifo),
        .O(D6[7]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_51__0
       (.I0(mc_address[23]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ),
        .I2(phy_ctl_wr_i1_reg),
        .I3(mem_out[22]),
        .I4(out_fifo),
        .O(D6[6]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_51__1
       (.I0(mem_reg_0_15_78_79[389]),
        .I1(phy_wrdata[445]),
        .I2(out_fifo_26),
        .I3(out_fifo_3[46]),
        .I4(out_fifo_4),
        .O(\write_buffer.wr_buf_out_data_reg[453] [6]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_51__2
       (.I0(mem_reg_0_15_78_79[396]),
        .I1(phy_wrdata[444]),
        .I2(out_fifo_26),
        .I3(out_fifo_5[38]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[460] [6]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_51__3
       (.I0(mem_reg_0_15_78_79[404]),
        .I1(phy_wrdata[444]),
        .I2(out_fifo_26),
        .I3(out_fifo_7[38]),
        .I4(out_fifo_8),
        .O(\write_buffer.wr_buf_out_data_reg[468] [6]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_51__4
       (.I0(mem_reg_0_15_78_79[412]),
        .I1(phy_wrdata[444]),
        .I2(out_fifo_26),
        .I3(out_fifo_9[38]),
        .I4(out_fifo_10),
        .O(\write_buffer.wr_buf_out_data_reg[476] [6]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_51__5
       (.I0(mem_reg_0_15_78_79[421]),
        .I1(phy_wrdata[445]),
        .I2(out_fifo_27),
        .I3(out_fifo_12[46]),
        .I4(out_fifo_13),
        .O(\write_buffer.wr_buf_out_data_reg[485] [6]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_51__6
       (.I0(mem_reg_0_15_78_79[428]),
        .I1(phy_wrdata[444]),
        .I2(out_fifo_27),
        .I3(out_fifo_14[38]),
        .I4(out_fifo_15),
        .O(\write_buffer.wr_buf_out_data_reg[492] [6]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_51__7
       (.I0(mem_reg_0_15_78_79[436]),
        .I1(phy_wrdata[444]),
        .I2(out_fifo_27),
        .I3(out_fifo_16[38]),
        .I4(out_fifo_17),
        .O(\write_buffer.wr_buf_out_data_reg[500] [6]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_51__8
       (.I0(mem_reg_0_15_78_79[444]),
        .I1(phy_wrdata[444]),
        .I2(out_fifo_27),
        .I3(out_fifo_18[38]),
        .I4(out_fifo_19),
        .O(\write_buffer.wr_buf_out_data_reg[508] [6]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_52
       (.I0(mc_address[12]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ),
        .I2(phy_ctl_wr_i1_reg),
        .I3(mem_out[21]),
        .I4(out_fifo),
        .O(D6[5]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_52__0
       (.I0(mem_reg_0_15_78_79[325]),
        .I1(phy_wrdata[381]),
        .I2(out_fifo_25),
        .I3(out_fifo_3[45]),
        .I4(out_fifo_4),
        .O(\write_buffer.wr_buf_out_data_reg[453] [5]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_52__1
       (.I0(mem_reg_0_15_78_79[332]),
        .I1(phy_wrdata[380]),
        .I2(out_fifo_25),
        .I3(out_fifo_5[37]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[460] [5]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_52__2
       (.I0(mem_reg_0_15_78_79[340]),
        .I1(phy_wrdata[380]),
        .I2(out_fifo_25),
        .I3(out_fifo_7[37]),
        .I4(out_fifo_8),
        .O(\write_buffer.wr_buf_out_data_reg[468] [5]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_52__3
       (.I0(mem_reg_0_15_78_79[348]),
        .I1(phy_wrdata[380]),
        .I2(out_fifo_25),
        .I3(out_fifo_9[37]),
        .I4(out_fifo_10),
        .O(\write_buffer.wr_buf_out_data_reg[476] [5]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_52__4
       (.I0(mem_reg_0_15_78_79[357]),
        .I1(phy_wrdata[381]),
        .I2(out_fifo_25),
        .I3(out_fifo_12[45]),
        .I4(out_fifo_13),
        .O(\write_buffer.wr_buf_out_data_reg[485] [5]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_52__5
       (.I0(mem_reg_0_15_78_79[364]),
        .I1(phy_wrdata[380]),
        .I2(out_fifo_25),
        .I3(out_fifo_14[37]),
        .I4(out_fifo_15),
        .O(\write_buffer.wr_buf_out_data_reg[492] [5]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_52__6
       (.I0(mem_reg_0_15_78_79[372]),
        .I1(phy_wrdata[380]),
        .I2(out_fifo_26),
        .I3(out_fifo_16[37]),
        .I4(out_fifo_17),
        .O(\write_buffer.wr_buf_out_data_reg[500] [5]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_52__7
       (.I0(mem_reg_0_15_78_79[380]),
        .I1(phy_wrdata[380]),
        .I2(out_fifo_26),
        .I3(out_fifo_18[37]),
        .I4(out_fifo_19),
        .O(\write_buffer.wr_buf_out_data_reg[508] [5]));
  LUT4 #(
    .INIT(16'hEEF0)) 
    out_fifo_i_52__8
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ),
        .I1(out_fifo_31),
        .I2(out_fifo_0[23]),
        .I3(out_fifo_1),
        .O(D9[3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_53
       (.I0(mc_address[0]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[0] ),
        .I2(phy_ctl_wr_i1_reg),
        .I3(mem_out[20]),
        .I4(out_fifo),
        .O(D6[4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_53__0
       (.I0(mc_address[29]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ),
        .I2(out_fifo_2),
        .I3(out_fifo_0[22]),
        .I4(out_fifo_1),
        .O(D9[2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_53__1
       (.I0(mem_reg_0_15_78_79[261]),
        .I1(phy_wrdata[317]),
        .I2(out_fifo_23),
        .I3(out_fifo_3[44]),
        .I4(out_fifo_4),
        .O(\write_buffer.wr_buf_out_data_reg[453] [4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_53__2
       (.I0(mem_reg_0_15_78_79[268]),
        .I1(phy_wrdata[316]),
        .I2(out_fifo_23),
        .I3(out_fifo_5[36]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[460] [4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_53__3
       (.I0(mem_reg_0_15_78_79[276]),
        .I1(phy_wrdata[316]),
        .I2(out_fifo_24),
        .I3(out_fifo_7[36]),
        .I4(out_fifo_8),
        .O(\write_buffer.wr_buf_out_data_reg[468] [4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_53__4
       (.I0(mem_reg_0_15_78_79[284]),
        .I1(phy_wrdata[316]),
        .I2(out_fifo_24),
        .I3(out_fifo_9[36]),
        .I4(out_fifo_10),
        .O(\write_buffer.wr_buf_out_data_reg[476] [4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_53__5
       (.I0(mem_reg_0_15_78_79[293]),
        .I1(phy_wrdata[317]),
        .I2(out_fifo_24),
        .I3(out_fifo_12[44]),
        .I4(out_fifo_13),
        .O(\write_buffer.wr_buf_out_data_reg[485] [4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_53__6
       (.I0(mem_reg_0_15_78_79[300]),
        .I1(phy_wrdata[316]),
        .I2(out_fifo_24),
        .I3(out_fifo_14[36]),
        .I4(out_fifo_15),
        .O(\write_buffer.wr_buf_out_data_reg[492] [4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_53__7
       (.I0(mem_reg_0_15_78_79[308]),
        .I1(phy_wrdata[316]),
        .I2(out_fifo_24),
        .I3(out_fifo_16[36]),
        .I4(out_fifo_17),
        .O(\write_buffer.wr_buf_out_data_reg[500] [4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_53__8
       (.I0(mem_reg_0_15_78_79[316]),
        .I1(phy_wrdata[316]),
        .I2(out_fifo_24),
        .I3(out_fifo_18[36]),
        .I4(out_fifo_19),
        .O(\write_buffer.wr_buf_out_data_reg[508] [4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_54
       (.I0(mc_address[18]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ),
        .I2(phy_ctl_wr_i1_reg),
        .I3(out_fifo_0[21]),
        .I4(out_fifo_1),
        .O(D9[1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_54__0
       (.I0(mem_reg_0_15_78_79[197]),
        .I1(phy_wrdata[253]),
        .I2(out_fifo_22),
        .I3(out_fifo_3[43]),
        .I4(out_fifo_4),
        .O(\write_buffer.wr_buf_out_data_reg[453] [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_54__1
       (.I0(mem_reg_0_15_78_79[204]),
        .I1(phy_wrdata[252]),
        .I2(out_fifo_22),
        .I3(out_fifo_5[35]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[460] [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_54__2
       (.I0(mem_reg_0_15_78_79[212]),
        .I1(phy_wrdata[252]),
        .I2(out_fifo_22),
        .I3(out_fifo_7[35]),
        .I4(out_fifo_8),
        .O(\write_buffer.wr_buf_out_data_reg[468] [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_54__3
       (.I0(mem_reg_0_15_78_79[220]),
        .I1(phy_wrdata[252]),
        .I2(out_fifo_22),
        .I3(out_fifo_9[35]),
        .I4(out_fifo_10),
        .O(\write_buffer.wr_buf_out_data_reg[476] [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_54__4
       (.I0(mem_reg_0_15_78_79[229]),
        .I1(phy_wrdata[253]),
        .I2(out_fifo_23),
        .I3(out_fifo_12[43]),
        .I4(out_fifo_13),
        .O(\write_buffer.wr_buf_out_data_reg[485] [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_54__5
       (.I0(mem_reg_0_15_78_79[236]),
        .I1(phy_wrdata[252]),
        .I2(out_fifo_23),
        .I3(out_fifo_14[35]),
        .I4(out_fifo_15),
        .O(\write_buffer.wr_buf_out_data_reg[492] [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_54__6
       (.I0(mem_reg_0_15_78_79[244]),
        .I1(phy_wrdata[252]),
        .I2(out_fifo_23),
        .I3(out_fifo_16[35]),
        .I4(out_fifo_17),
        .O(\write_buffer.wr_buf_out_data_reg[500] [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_54__7
       (.I0(mem_reg_0_15_78_79[252]),
        .I1(phy_wrdata[252]),
        .I2(out_fifo_23),
        .I3(out_fifo_18[35]),
        .I4(out_fifo_19),
        .O(\write_buffer.wr_buf_out_data_reg[508] [3]));
  LUT4 #(
    .INIT(16'hEEF0)) 
    out_fifo_i_54__8
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12] ),
        .I1(out_fifo_31),
        .I2(mem_out[19]),
        .I3(out_fifo),
        .O(D6[3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_55
       (.I0(mc_address[6]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[6] ),
        .I2(phy_ctl_wr_i1_reg),
        .I3(out_fifo_0[20]),
        .I4(out_fifo_1),
        .O(D9[0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_55__0
       (.I0(mc_address[34]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12] ),
        .I2(out_fifo_2),
        .I3(mem_out[18]),
        .I4(out_fifo),
        .O(D6[2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_55__1
       (.I0(mem_reg_0_15_78_79[133]),
        .I1(phy_wrdata[189]),
        .I2(out_fifo_21),
        .I3(out_fifo_3[42]),
        .I4(out_fifo_4),
        .O(\write_buffer.wr_buf_out_data_reg[453] [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_55__2
       (.I0(mem_reg_0_15_78_79[140]),
        .I1(phy_wrdata[188]),
        .I2(out_fifo_21),
        .I3(out_fifo_5[34]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[460] [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_55__3
       (.I0(mem_reg_0_15_78_79[148]),
        .I1(phy_wrdata[188]),
        .I2(out_fifo_21),
        .I3(out_fifo_7[34]),
        .I4(out_fifo_8),
        .O(\write_buffer.wr_buf_out_data_reg[468] [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_55__4
       (.I0(mem_reg_0_15_78_79[156]),
        .I1(phy_wrdata[188]),
        .I2(out_fifo_21),
        .I3(out_fifo_9[34]),
        .I4(out_fifo_10),
        .O(\write_buffer.wr_buf_out_data_reg[476] [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_55__5
       (.I0(mem_reg_0_15_78_79[165]),
        .I1(phy_wrdata[189]),
        .I2(out_fifo_21),
        .I3(out_fifo_12[42]),
        .I4(out_fifo_13),
        .O(\write_buffer.wr_buf_out_data_reg[485] [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_55__6
       (.I0(mem_reg_0_15_78_79[172]),
        .I1(phy_wrdata[188]),
        .I2(out_fifo_21),
        .I3(out_fifo_14[34]),
        .I4(out_fifo_15),
        .O(\write_buffer.wr_buf_out_data_reg[492] [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_55__7
       (.I0(mem_reg_0_15_78_79[180]),
        .I1(phy_wrdata[188]),
        .I2(out_fifo_22),
        .I3(out_fifo_16[34]),
        .I4(out_fifo_17),
        .O(\write_buffer.wr_buf_out_data_reg[500] [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_55__8
       (.I0(mem_reg_0_15_78_79[188]),
        .I1(phy_wrdata[188]),
        .I2(out_fifo_22),
        .I3(out_fifo_18[34]),
        .I4(out_fifo_19),
        .O(\write_buffer.wr_buf_out_data_reg[508] [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_56
       (.I0(mc_ras_n),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12] ),
        .I2(phy_ctl_wr_i1_reg),
        .I3(mem_out[17]),
        .I4(out_fifo),
        .O(D6[1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_56__0
       (.I0(mem_reg_0_15_78_79[69]),
        .I1(phy_wrdata[125]),
        .I2(out_fifo_11),
        .I3(out_fifo_3[41]),
        .I4(out_fifo_4),
        .O(\write_buffer.wr_buf_out_data_reg[453] [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_56__1
       (.I0(mem_reg_0_15_78_79[76]),
        .I1(phy_wrdata[124]),
        .I2(out_fifo_20),
        .I3(out_fifo_5[33]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[460] [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_56__2
       (.I0(mem_reg_0_15_78_79[84]),
        .I1(phy_wrdata[124]),
        .I2(out_fifo_20),
        .I3(out_fifo_7[33]),
        .I4(out_fifo_8),
        .O(\write_buffer.wr_buf_out_data_reg[468] [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_56__3
       (.I0(mem_reg_0_15_78_79[92]),
        .I1(phy_wrdata[124]),
        .I2(out_fifo_20),
        .I3(out_fifo_9[33]),
        .I4(out_fifo_10),
        .O(\write_buffer.wr_buf_out_data_reg[476] [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_56__4
       (.I0(mem_reg_0_15_78_79[101]),
        .I1(phy_wrdata[125]),
        .I2(out_fifo_20),
        .I3(out_fifo_12[41]),
        .I4(out_fifo_13),
        .O(\write_buffer.wr_buf_out_data_reg[485] [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_56__5
       (.I0(mem_reg_0_15_78_79[108]),
        .I1(phy_wrdata[124]),
        .I2(out_fifo_20),
        .I3(out_fifo_14[33]),
        .I4(out_fifo_15),
        .O(\write_buffer.wr_buf_out_data_reg[492] [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_56__6
       (.I0(mem_reg_0_15_78_79[116]),
        .I1(phy_wrdata[124]),
        .I2(out_fifo_20),
        .I3(out_fifo_16[33]),
        .I4(out_fifo_17),
        .O(\write_buffer.wr_buf_out_data_reg[500] [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_56__7
       (.I0(mem_reg_0_15_78_79[124]),
        .I1(phy_wrdata[124]),
        .I2(out_fifo_20),
        .I3(out_fifo_18[33]),
        .I4(out_fifo_19),
        .O(\write_buffer.wr_buf_out_data_reg[508] [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_57
       (.I0(mc_address[11]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[12] ),
        .I2(phy_ctl_wr_i1_reg),
        .I3(mem_out[16]),
        .I4(out_fifo),
        .O(D6[0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_57__0
       (.I0(mem_reg_0_15_78_79[5]),
        .I1(phy_wrdata[61]),
        .I2(out_fifo_2),
        .I3(out_fifo_3[40]),
        .I4(out_fifo_4),
        .O(\write_buffer.wr_buf_out_data_reg[453] [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_57__1
       (.I0(mem_reg_0_15_78_79[12]),
        .I1(phy_wrdata[60]),
        .I2(out_fifo_2),
        .I3(out_fifo_5[32]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[460] [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_57__2
       (.I0(mem_reg_0_15_78_79[20]),
        .I1(phy_wrdata[60]),
        .I2(out_fifo_2),
        .I3(out_fifo_7[32]),
        .I4(out_fifo_8),
        .O(\write_buffer.wr_buf_out_data_reg[468] [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_57__3
       (.I0(mem_reg_0_15_78_79[28]),
        .I1(phy_wrdata[60]),
        .I2(out_fifo_11),
        .I3(out_fifo_9[32]),
        .I4(out_fifo_10),
        .O(\write_buffer.wr_buf_out_data_reg[476] [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_57__4
       (.I0(mem_reg_0_15_78_79[37]),
        .I1(phy_wrdata[61]),
        .I2(out_fifo_11),
        .I3(out_fifo_12[40]),
        .I4(out_fifo_13),
        .O(\write_buffer.wr_buf_out_data_reg[485] [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_57__5
       (.I0(mem_reg_0_15_78_79[44]),
        .I1(phy_wrdata[60]),
        .I2(out_fifo_11),
        .I3(out_fifo_14[32]),
        .I4(out_fifo_15),
        .O(\write_buffer.wr_buf_out_data_reg[492] [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_57__6
       (.I0(mem_reg_0_15_78_79[52]),
        .I1(phy_wrdata[60]),
        .I2(out_fifo_11),
        .I3(out_fifo_16[32]),
        .I4(out_fifo_17),
        .O(\write_buffer.wr_buf_out_data_reg[500] [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_57__7
       (.I0(mem_reg_0_15_78_79[60]),
        .I1(phy_wrdata[60]),
        .I2(out_fifo_11),
        .I3(out_fifo_18[32]),
        .I4(out_fifo_19),
        .O(\write_buffer.wr_buf_out_data_reg[508] [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_58__0
       (.I0(mem_reg_0_15_78_79[454]),
        .I1(phy_wrdata[510]),
        .I2(out_fifo_27),
        .I3(out_fifo_3[55]),
        .I4(out_fifo_4),
        .O(\write_buffer.wr_buf_out_data_reg[454] [7]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_58__1
       (.I0(mem_reg_0_15_78_79[461]),
        .I1(phy_wrdata[509]),
        .I2(out_fifo_27),
        .I3(out_fifo_5[47]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[461] [7]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_58__2
       (.I0(mem_reg_0_15_78_79[469]),
        .I1(phy_wrdata[509]),
        .I2(out_fifo_28),
        .I3(out_fifo_7[47]),
        .I4(out_fifo_8),
        .O(\write_buffer.wr_buf_out_data_reg[469] [7]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_58__3
       (.I0(mem_reg_0_15_78_79[477]),
        .I1(phy_wrdata[509]),
        .I2(out_fifo_28),
        .I3(out_fifo_9[47]),
        .I4(out_fifo_10),
        .O(\write_buffer.wr_buf_out_data_reg[477] [7]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_58__4
       (.I0(mem_reg_0_15_78_79[486]),
        .I1(phy_wrdata[510]),
        .I2(out_fifo_28),
        .I3(out_fifo_12[55]),
        .I4(out_fifo_13),
        .O(\write_buffer.wr_buf_out_data_reg[486] [7]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_58__5
       (.I0(mem_reg_0_15_78_79[493]),
        .I1(phy_wrdata[509]),
        .I2(out_fifo_28),
        .I3(out_fifo_14[47]),
        .I4(out_fifo_15),
        .O(\write_buffer.wr_buf_out_data_reg[493] [7]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_58__6
       (.I0(mem_reg_0_15_78_79[501]),
        .I1(phy_wrdata[509]),
        .I2(out_fifo_28),
        .I3(out_fifo_16[47]),
        .I4(out_fifo_17),
        .O(\write_buffer.wr_buf_out_data_reg[501] [7]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_58__7
       (.I0(mem_reg_0_15_78_79[509]),
        .I1(phy_wrdata[509]),
        .I2(out_fifo_28),
        .I3(out_fifo_18[47]),
        .I4(out_fifo_19),
        .O(\write_buffer.wr_buf_out_data_reg[509] [7]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_59__0
       (.I0(mem_reg_0_15_78_79[390]),
        .I1(phy_wrdata[446]),
        .I2(out_fifo_26),
        .I3(out_fifo_3[54]),
        .I4(out_fifo_4),
        .O(\write_buffer.wr_buf_out_data_reg[454] [6]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_59__1
       (.I0(mem_reg_0_15_78_79[397]),
        .I1(phy_wrdata[445]),
        .I2(out_fifo_26),
        .I3(out_fifo_5[46]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[461] [6]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_59__2
       (.I0(mem_reg_0_15_78_79[405]),
        .I1(phy_wrdata[445]),
        .I2(out_fifo_26),
        .I3(out_fifo_7[46]),
        .I4(out_fifo_8),
        .O(\write_buffer.wr_buf_out_data_reg[469] [6]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_59__3
       (.I0(mem_reg_0_15_78_79[413]),
        .I1(phy_wrdata[445]),
        .I2(out_fifo_26),
        .I3(out_fifo_9[46]),
        .I4(out_fifo_10),
        .O(\write_buffer.wr_buf_out_data_reg[477] [6]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_59__4
       (.I0(mem_reg_0_15_78_79[422]),
        .I1(phy_wrdata[446]),
        .I2(out_fifo_27),
        .I3(out_fifo_12[54]),
        .I4(out_fifo_13),
        .O(\write_buffer.wr_buf_out_data_reg[486] [6]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_59__5
       (.I0(mem_reg_0_15_78_79[429]),
        .I1(phy_wrdata[445]),
        .I2(out_fifo_27),
        .I3(out_fifo_14[46]),
        .I4(out_fifo_15),
        .O(\write_buffer.wr_buf_out_data_reg[493] [6]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_59__6
       (.I0(mem_reg_0_15_78_79[437]),
        .I1(phy_wrdata[445]),
        .I2(out_fifo_27),
        .I3(out_fifo_16[46]),
        .I4(out_fifo_17),
        .O(\write_buffer.wr_buf_out_data_reg[501] [6]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_59__7
       (.I0(mem_reg_0_15_78_79[445]),
        .I1(phy_wrdata[445]),
        .I2(out_fifo_27),
        .I3(out_fifo_18[46]),
        .I4(out_fifo_19),
        .O(\write_buffer.wr_buf_out_data_reg[509] [6]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_60__0
       (.I0(mem_reg_0_15_78_79[326]),
        .I1(phy_wrdata[382]),
        .I2(out_fifo_25),
        .I3(out_fifo_3[53]),
        .I4(out_fifo_4),
        .O(\write_buffer.wr_buf_out_data_reg[454] [5]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_60__1
       (.I0(mem_reg_0_15_78_79[333]),
        .I1(phy_wrdata[381]),
        .I2(out_fifo_25),
        .I3(out_fifo_5[45]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[461] [5]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_60__2
       (.I0(mem_reg_0_15_78_79[341]),
        .I1(phy_wrdata[381]),
        .I2(out_fifo_25),
        .I3(out_fifo_7[45]),
        .I4(out_fifo_8),
        .O(\write_buffer.wr_buf_out_data_reg[469] [5]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_60__3
       (.I0(mem_reg_0_15_78_79[349]),
        .I1(phy_wrdata[381]),
        .I2(out_fifo_25),
        .I3(out_fifo_9[45]),
        .I4(out_fifo_10),
        .O(\write_buffer.wr_buf_out_data_reg[477] [5]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_60__4
       (.I0(mem_reg_0_15_78_79[358]),
        .I1(phy_wrdata[382]),
        .I2(out_fifo_25),
        .I3(out_fifo_12[53]),
        .I4(out_fifo_13),
        .O(\write_buffer.wr_buf_out_data_reg[486] [5]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_60__5
       (.I0(mem_reg_0_15_78_79[365]),
        .I1(phy_wrdata[381]),
        .I2(out_fifo_25),
        .I3(out_fifo_14[45]),
        .I4(out_fifo_15),
        .O(\write_buffer.wr_buf_out_data_reg[493] [5]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_60__6
       (.I0(mem_reg_0_15_78_79[373]),
        .I1(phy_wrdata[381]),
        .I2(out_fifo_26),
        .I3(out_fifo_16[45]),
        .I4(out_fifo_17),
        .O(\write_buffer.wr_buf_out_data_reg[501] [5]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_60__7
       (.I0(mem_reg_0_15_78_79[381]),
        .I1(phy_wrdata[381]),
        .I2(out_fifo_26),
        .I3(out_fifo_18[45]),
        .I4(out_fifo_19),
        .O(\write_buffer.wr_buf_out_data_reg[509] [5]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_61__0
       (.I0(mem_reg_0_15_78_79[262]),
        .I1(phy_wrdata[318]),
        .I2(out_fifo_23),
        .I3(out_fifo_3[52]),
        .I4(out_fifo_4),
        .O(\write_buffer.wr_buf_out_data_reg[454] [4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_61__1
       (.I0(mem_reg_0_15_78_79[269]),
        .I1(phy_wrdata[317]),
        .I2(out_fifo_23),
        .I3(out_fifo_5[44]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[461] [4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_61__2
       (.I0(mem_reg_0_15_78_79[277]),
        .I1(phy_wrdata[317]),
        .I2(out_fifo_24),
        .I3(out_fifo_7[44]),
        .I4(out_fifo_8),
        .O(\write_buffer.wr_buf_out_data_reg[469] [4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_61__3
       (.I0(mem_reg_0_15_78_79[285]),
        .I1(phy_wrdata[317]),
        .I2(out_fifo_24),
        .I3(out_fifo_9[44]),
        .I4(out_fifo_10),
        .O(\write_buffer.wr_buf_out_data_reg[477] [4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_61__4
       (.I0(mem_reg_0_15_78_79[294]),
        .I1(phy_wrdata[318]),
        .I2(out_fifo_24),
        .I3(out_fifo_12[52]),
        .I4(out_fifo_13),
        .O(\write_buffer.wr_buf_out_data_reg[486] [4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_61__5
       (.I0(mem_reg_0_15_78_79[301]),
        .I1(phy_wrdata[317]),
        .I2(out_fifo_24),
        .I3(out_fifo_14[44]),
        .I4(out_fifo_15),
        .O(\write_buffer.wr_buf_out_data_reg[493] [4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_61__6
       (.I0(mem_reg_0_15_78_79[309]),
        .I1(phy_wrdata[317]),
        .I2(out_fifo_24),
        .I3(out_fifo_16[44]),
        .I4(out_fifo_17),
        .O(\write_buffer.wr_buf_out_data_reg[501] [4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_61__7
       (.I0(mem_reg_0_15_78_79[317]),
        .I1(phy_wrdata[317]),
        .I2(out_fifo_24),
        .I3(out_fifo_18[44]),
        .I4(out_fifo_19),
        .O(\write_buffer.wr_buf_out_data_reg[509] [4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_62
       (.I0(mem_reg_0_15_78_79[198]),
        .I1(phy_wrdata[254]),
        .I2(out_fifo_22),
        .I3(out_fifo_3[51]),
        .I4(out_fifo_4),
        .O(\write_buffer.wr_buf_out_data_reg[454] [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_62__0
       (.I0(mem_reg_0_15_78_79[205]),
        .I1(phy_wrdata[253]),
        .I2(out_fifo_22),
        .I3(out_fifo_5[43]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[461] [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_62__1
       (.I0(mem_reg_0_15_78_79[213]),
        .I1(phy_wrdata[253]),
        .I2(out_fifo_22),
        .I3(out_fifo_7[43]),
        .I4(out_fifo_8),
        .O(\write_buffer.wr_buf_out_data_reg[469] [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_62__2
       (.I0(mem_reg_0_15_78_79[221]),
        .I1(phy_wrdata[253]),
        .I2(out_fifo_22),
        .I3(out_fifo_9[43]),
        .I4(out_fifo_10),
        .O(\write_buffer.wr_buf_out_data_reg[477] [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_62__3
       (.I0(mem_reg_0_15_78_79[230]),
        .I1(phy_wrdata[254]),
        .I2(out_fifo_23),
        .I3(out_fifo_12[51]),
        .I4(out_fifo_13),
        .O(\write_buffer.wr_buf_out_data_reg[486] [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_62__4
       (.I0(mem_reg_0_15_78_79[237]),
        .I1(phy_wrdata[253]),
        .I2(out_fifo_23),
        .I3(out_fifo_14[43]),
        .I4(out_fifo_15),
        .O(\write_buffer.wr_buf_out_data_reg[493] [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_62__5
       (.I0(mem_reg_0_15_78_79[245]),
        .I1(phy_wrdata[253]),
        .I2(out_fifo_23),
        .I3(out_fifo_16[43]),
        .I4(out_fifo_17),
        .O(\write_buffer.wr_buf_out_data_reg[501] [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_62__6
       (.I0(mem_reg_0_15_78_79[253]),
        .I1(phy_wrdata[253]),
        .I2(out_fifo_23),
        .I3(out_fifo_18[43]),
        .I4(out_fifo_19),
        .O(\write_buffer.wr_buf_out_data_reg[509] [3]));
  LUT4 #(
    .INIT(16'hEEF0)) 
    out_fifo_i_62__7
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ),
        .I1(out_fifo_31),
        .I2(mem_out[27]),
        .I3(out_fifo),
        .O(D7[3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_63
       (.I0(mc_address[28]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ),
        .I2(out_fifo_2),
        .I3(mem_out[26]),
        .I4(out_fifo),
        .O(D7[2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_63__0
       (.I0(mem_reg_0_15_78_79[134]),
        .I1(phy_wrdata[190]),
        .I2(out_fifo_21),
        .I3(out_fifo_3[50]),
        .I4(out_fifo_4),
        .O(\write_buffer.wr_buf_out_data_reg[454] [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_63__1
       (.I0(mem_reg_0_15_78_79[141]),
        .I1(phy_wrdata[189]),
        .I2(out_fifo_21),
        .I3(out_fifo_5[42]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[461] [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_63__2
       (.I0(mem_reg_0_15_78_79[149]),
        .I1(phy_wrdata[189]),
        .I2(out_fifo_21),
        .I3(out_fifo_7[42]),
        .I4(out_fifo_8),
        .O(\write_buffer.wr_buf_out_data_reg[469] [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_63__3
       (.I0(mem_reg_0_15_78_79[157]),
        .I1(phy_wrdata[189]),
        .I2(out_fifo_21),
        .I3(out_fifo_9[42]),
        .I4(out_fifo_10),
        .O(\write_buffer.wr_buf_out_data_reg[477] [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_63__4
       (.I0(mem_reg_0_15_78_79[166]),
        .I1(phy_wrdata[190]),
        .I2(out_fifo_21),
        .I3(out_fifo_12[50]),
        .I4(out_fifo_13),
        .O(\write_buffer.wr_buf_out_data_reg[486] [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_63__5
       (.I0(mem_reg_0_15_78_79[173]),
        .I1(phy_wrdata[189]),
        .I2(out_fifo_21),
        .I3(out_fifo_14[42]),
        .I4(out_fifo_15),
        .O(\write_buffer.wr_buf_out_data_reg[493] [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_63__6
       (.I0(mem_reg_0_15_78_79[181]),
        .I1(phy_wrdata[189]),
        .I2(out_fifo_22),
        .I3(out_fifo_16[42]),
        .I4(out_fifo_17),
        .O(\write_buffer.wr_buf_out_data_reg[501] [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_63__7
       (.I0(mem_reg_0_15_78_79[189]),
        .I1(phy_wrdata[189]),
        .I2(out_fifo_22),
        .I3(out_fifo_18[42]),
        .I4(out_fifo_19),
        .O(\write_buffer.wr_buf_out_data_reg[509] [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_64
       (.I0(mc_address[17]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ),
        .I2(phy_ctl_wr_i1_reg),
        .I3(mem_out[25]),
        .I4(out_fifo),
        .O(D7[1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_64__0
       (.I0(mem_reg_0_15_78_79[70]),
        .I1(phy_wrdata[126]),
        .I2(out_fifo_11),
        .I3(out_fifo_3[49]),
        .I4(out_fifo_4),
        .O(\write_buffer.wr_buf_out_data_reg[454] [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_64__1
       (.I0(mem_reg_0_15_78_79[77]),
        .I1(phy_wrdata[125]),
        .I2(out_fifo_20),
        .I3(out_fifo_5[41]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[461] [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_64__2
       (.I0(mem_reg_0_15_78_79[85]),
        .I1(phy_wrdata[125]),
        .I2(out_fifo_20),
        .I3(out_fifo_7[41]),
        .I4(out_fifo_8),
        .O(\write_buffer.wr_buf_out_data_reg[469] [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_64__3
       (.I0(mem_reg_0_15_78_79[93]),
        .I1(phy_wrdata[125]),
        .I2(out_fifo_20),
        .I3(out_fifo_9[41]),
        .I4(out_fifo_10),
        .O(\write_buffer.wr_buf_out_data_reg[477] [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_64__4
       (.I0(mem_reg_0_15_78_79[102]),
        .I1(phy_wrdata[126]),
        .I2(out_fifo_20),
        .I3(out_fifo_12[49]),
        .I4(out_fifo_13),
        .O(\write_buffer.wr_buf_out_data_reg[486] [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_64__5
       (.I0(mem_reg_0_15_78_79[109]),
        .I1(phy_wrdata[125]),
        .I2(out_fifo_20),
        .I3(out_fifo_14[41]),
        .I4(out_fifo_15),
        .O(\write_buffer.wr_buf_out_data_reg[493] [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_64__6
       (.I0(mem_reg_0_15_78_79[117]),
        .I1(phy_wrdata[125]),
        .I2(out_fifo_20),
        .I3(out_fifo_16[41]),
        .I4(out_fifo_17),
        .O(\write_buffer.wr_buf_out_data_reg[501] [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_64__7
       (.I0(mem_reg_0_15_78_79[125]),
        .I1(phy_wrdata[125]),
        .I2(out_fifo_21),
        .I3(out_fifo_18[41]),
        .I4(out_fifo_19),
        .O(\write_buffer.wr_buf_out_data_reg[509] [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_65
       (.I0(mc_address[5]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[5] ),
        .I2(phy_ctl_wr_i1_reg),
        .I3(mem_out[24]),
        .I4(out_fifo),
        .O(D7[0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_65__0
       (.I0(mem_reg_0_15_78_79[6]),
        .I1(phy_wrdata[62]),
        .I2(out_fifo_2),
        .I3(out_fifo_3[48]),
        .I4(out_fifo_4),
        .O(\write_buffer.wr_buf_out_data_reg[454] [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_65__1
       (.I0(mem_reg_0_15_78_79[13]),
        .I1(phy_wrdata[61]),
        .I2(out_fifo_2),
        .I3(out_fifo_5[40]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[461] [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_65__2
       (.I0(mem_reg_0_15_78_79[21]),
        .I1(phy_wrdata[61]),
        .I2(out_fifo_2),
        .I3(out_fifo_7[40]),
        .I4(out_fifo_8),
        .O(\write_buffer.wr_buf_out_data_reg[469] [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_65__3
       (.I0(mem_reg_0_15_78_79[29]),
        .I1(phy_wrdata[61]),
        .I2(out_fifo_11),
        .I3(out_fifo_9[40]),
        .I4(out_fifo_10),
        .O(\write_buffer.wr_buf_out_data_reg[477] [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_65__4
       (.I0(mem_reg_0_15_78_79[38]),
        .I1(phy_wrdata[62]),
        .I2(out_fifo_11),
        .I3(out_fifo_12[48]),
        .I4(out_fifo_13),
        .O(\write_buffer.wr_buf_out_data_reg[486] [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_65__5
       (.I0(mem_reg_0_15_78_79[45]),
        .I1(phy_wrdata[61]),
        .I2(out_fifo_11),
        .I3(out_fifo_14[40]),
        .I4(out_fifo_15),
        .O(\write_buffer.wr_buf_out_data_reg[493] [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_65__6
       (.I0(mem_reg_0_15_78_79[53]),
        .I1(phy_wrdata[61]),
        .I2(out_fifo_11),
        .I3(out_fifo_16[40]),
        .I4(out_fifo_17),
        .O(\write_buffer.wr_buf_out_data_reg[501] [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_65__7
       (.I0(mem_reg_0_15_78_79[61]),
        .I1(phy_wrdata[61]),
        .I2(out_fifo_11),
        .I3(out_fifo_18[40]),
        .I4(out_fifo_19),
        .O(\write_buffer.wr_buf_out_data_reg[509] [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_66__2
       (.I0(mem_reg_0_15_78_79[462]),
        .I1(phy_wrdata[510]),
        .I2(out_fifo_27),
        .I3(out_fifo_5[55]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[462] [7]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_66__3
       (.I0(mem_reg_0_15_78_79[470]),
        .I1(phy_wrdata[510]),
        .I2(out_fifo_28),
        .I3(out_fifo_7[55]),
        .I4(out_fifo_8),
        .O(\write_buffer.wr_buf_out_data_reg[470] [7]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_66__4
       (.I0(mem_reg_0_15_78_79[478]),
        .I1(phy_wrdata[510]),
        .I2(out_fifo_28),
        .I3(out_fifo_9[55]),
        .I4(out_fifo_10),
        .O(\write_buffer.wr_buf_out_data_reg[478] [7]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_66__5
       (.I0(mem_reg_0_15_78_79[494]),
        .I1(phy_wrdata[510]),
        .I2(out_fifo_28),
        .I3(out_fifo_14[55]),
        .I4(out_fifo_15),
        .O(\write_buffer.wr_buf_out_data_reg[494] [7]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_66__6
       (.I0(mem_reg_0_15_78_79[502]),
        .I1(phy_wrdata[510]),
        .I2(out_fifo_28),
        .I3(out_fifo_16[55]),
        .I4(out_fifo_17),
        .O(\write_buffer.wr_buf_out_data_reg[502] [7]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_66__7
       (.I0(mem_reg_0_15_78_79[510]),
        .I1(phy_wrdata[510]),
        .I2(out_fifo_28),
        .I3(out_fifo_18[55]),
        .I4(out_fifo_19),
        .O(\write_buffer.wr_buf_out_data_reg[510] [7]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_67__2
       (.I0(mem_reg_0_15_78_79[398]),
        .I1(phy_wrdata[446]),
        .I2(out_fifo_26),
        .I3(out_fifo_5[54]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[462] [6]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_67__3
       (.I0(mem_reg_0_15_78_79[406]),
        .I1(phy_wrdata[446]),
        .I2(out_fifo_26),
        .I3(out_fifo_7[54]),
        .I4(out_fifo_8),
        .O(\write_buffer.wr_buf_out_data_reg[470] [6]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_67__4
       (.I0(mem_reg_0_15_78_79[414]),
        .I1(phy_wrdata[446]),
        .I2(out_fifo_26),
        .I3(out_fifo_9[54]),
        .I4(out_fifo_10),
        .O(\write_buffer.wr_buf_out_data_reg[478] [6]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_67__5
       (.I0(mem_reg_0_15_78_79[430]),
        .I1(phy_wrdata[446]),
        .I2(out_fifo_27),
        .I3(out_fifo_14[54]),
        .I4(out_fifo_15),
        .O(\write_buffer.wr_buf_out_data_reg[494] [6]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_67__6
       (.I0(mem_reg_0_15_78_79[438]),
        .I1(phy_wrdata[446]),
        .I2(out_fifo_27),
        .I3(out_fifo_16[54]),
        .I4(out_fifo_17),
        .O(\write_buffer.wr_buf_out_data_reg[502] [6]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_67__7
       (.I0(mem_reg_0_15_78_79[446]),
        .I1(phy_wrdata[446]),
        .I2(out_fifo_27),
        .I3(out_fifo_18[54]),
        .I4(out_fifo_19),
        .O(\write_buffer.wr_buf_out_data_reg[510] [6]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_68__2
       (.I0(mem_reg_0_15_78_79[334]),
        .I1(phy_wrdata[382]),
        .I2(out_fifo_25),
        .I3(out_fifo_5[53]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[462] [5]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_68__3
       (.I0(mem_reg_0_15_78_79[342]),
        .I1(phy_wrdata[382]),
        .I2(out_fifo_25),
        .I3(out_fifo_7[53]),
        .I4(out_fifo_8),
        .O(\write_buffer.wr_buf_out_data_reg[470] [5]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_68__4
       (.I0(mem_reg_0_15_78_79[350]),
        .I1(phy_wrdata[382]),
        .I2(out_fifo_25),
        .I3(out_fifo_9[53]),
        .I4(out_fifo_10),
        .O(\write_buffer.wr_buf_out_data_reg[478] [5]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_68__5
       (.I0(mem_reg_0_15_78_79[366]),
        .I1(phy_wrdata[382]),
        .I2(out_fifo_25),
        .I3(out_fifo_14[53]),
        .I4(out_fifo_15),
        .O(\write_buffer.wr_buf_out_data_reg[494] [5]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_68__6
       (.I0(mem_reg_0_15_78_79[374]),
        .I1(phy_wrdata[382]),
        .I2(out_fifo_26),
        .I3(out_fifo_16[53]),
        .I4(out_fifo_17),
        .O(\write_buffer.wr_buf_out_data_reg[502] [5]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_68__7
       (.I0(mem_reg_0_15_78_79[382]),
        .I1(phy_wrdata[382]),
        .I2(out_fifo_26),
        .I3(out_fifo_18[53]),
        .I4(out_fifo_19),
        .O(\write_buffer.wr_buf_out_data_reg[510] [5]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_69__2
       (.I0(mem_reg_0_15_78_79[270]),
        .I1(phy_wrdata[318]),
        .I2(out_fifo_23),
        .I3(out_fifo_5[52]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[462] [4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_69__3
       (.I0(mem_reg_0_15_78_79[278]),
        .I1(phy_wrdata[318]),
        .I2(out_fifo_24),
        .I3(out_fifo_7[52]),
        .I4(out_fifo_8),
        .O(\write_buffer.wr_buf_out_data_reg[470] [4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_69__4
       (.I0(mem_reg_0_15_78_79[286]),
        .I1(phy_wrdata[318]),
        .I2(out_fifo_24),
        .I3(out_fifo_9[52]),
        .I4(out_fifo_10),
        .O(\write_buffer.wr_buf_out_data_reg[478] [4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_69__5
       (.I0(mem_reg_0_15_78_79[302]),
        .I1(phy_wrdata[318]),
        .I2(out_fifo_24),
        .I3(out_fifo_14[52]),
        .I4(out_fifo_15),
        .O(\write_buffer.wr_buf_out_data_reg[494] [4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_69__6
       (.I0(mem_reg_0_15_78_79[310]),
        .I1(phy_wrdata[318]),
        .I2(out_fifo_24),
        .I3(out_fifo_16[52]),
        .I4(out_fifo_17),
        .O(\write_buffer.wr_buf_out_data_reg[502] [4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_69__7
       (.I0(mem_reg_0_15_78_79[318]),
        .I1(phy_wrdata[318]),
        .I2(out_fifo_24),
        .I3(out_fifo_18[52]),
        .I4(out_fifo_19),
        .O(\write_buffer.wr_buf_out_data_reg[510] [4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_70__1
       (.I0(mem_reg_0_15_78_79[206]),
        .I1(phy_wrdata[254]),
        .I2(out_fifo_22),
        .I3(out_fifo_5[51]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[462] [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_70__2
       (.I0(mem_reg_0_15_78_79[214]),
        .I1(phy_wrdata[254]),
        .I2(out_fifo_22),
        .I3(out_fifo_7[51]),
        .I4(out_fifo_8),
        .O(\write_buffer.wr_buf_out_data_reg[470] [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_70__3
       (.I0(mem_reg_0_15_78_79[222]),
        .I1(phy_wrdata[254]),
        .I2(out_fifo_22),
        .I3(out_fifo_9[51]),
        .I4(out_fifo_10),
        .O(\write_buffer.wr_buf_out_data_reg[478] [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_70__4
       (.I0(mem_reg_0_15_78_79[238]),
        .I1(phy_wrdata[254]),
        .I2(out_fifo_23),
        .I3(out_fifo_14[51]),
        .I4(out_fifo_15),
        .O(\write_buffer.wr_buf_out_data_reg[494] [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_70__5
       (.I0(mem_reg_0_15_78_79[246]),
        .I1(phy_wrdata[254]),
        .I2(out_fifo_23),
        .I3(out_fifo_16[51]),
        .I4(out_fifo_17),
        .O(\write_buffer.wr_buf_out_data_reg[502] [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_70__6
       (.I0(mem_reg_0_15_78_79[254]),
        .I1(phy_wrdata[254]),
        .I2(out_fifo_23),
        .I3(out_fifo_18[51]),
        .I4(out_fifo_19),
        .O(\write_buffer.wr_buf_out_data_reg[510] [3]));
  LUT4 #(
    .INIT(16'hEEF0)) 
    out_fifo_i_70__7
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ),
        .I1(out_fifo_31),
        .I2(mem_out[31]),
        .I3(out_fifo),
        .O(D8[3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_71__1
       (.I0(mc_address[24]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ),
        .I2(out_fifo_2),
        .I3(mem_out[30]),
        .I4(out_fifo),
        .O(D8[2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_71__2
       (.I0(mem_reg_0_15_78_79[142]),
        .I1(phy_wrdata[190]),
        .I2(out_fifo_21),
        .I3(out_fifo_5[50]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[462] [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_71__3
       (.I0(mem_reg_0_15_78_79[150]),
        .I1(phy_wrdata[190]),
        .I2(out_fifo_21),
        .I3(out_fifo_7[50]),
        .I4(out_fifo_8),
        .O(\write_buffer.wr_buf_out_data_reg[470] [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_71__4
       (.I0(mem_reg_0_15_78_79[158]),
        .I1(phy_wrdata[190]),
        .I2(out_fifo_21),
        .I3(out_fifo_9[50]),
        .I4(out_fifo_10),
        .O(\write_buffer.wr_buf_out_data_reg[478] [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_71__5
       (.I0(mem_reg_0_15_78_79[174]),
        .I1(phy_wrdata[190]),
        .I2(out_fifo_22),
        .I3(out_fifo_14[50]),
        .I4(out_fifo_15),
        .O(\write_buffer.wr_buf_out_data_reg[494] [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_71__6
       (.I0(mem_reg_0_15_78_79[182]),
        .I1(phy_wrdata[190]),
        .I2(out_fifo_22),
        .I3(out_fifo_16[50]),
        .I4(out_fifo_17),
        .O(\write_buffer.wr_buf_out_data_reg[502] [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_71__7
       (.I0(mem_reg_0_15_78_79[190]),
        .I1(phy_wrdata[190]),
        .I2(out_fifo_22),
        .I3(out_fifo_18[50]),
        .I4(out_fifo_19),
        .O(\write_buffer.wr_buf_out_data_reg[510] [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_72__1
       (.I0(mc_address[13]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ),
        .I2(phy_ctl_wr_i1_reg),
        .I3(mem_out[29]),
        .I4(out_fifo),
        .O(D8[1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_72__2
       (.I0(mem_reg_0_15_78_79[78]),
        .I1(phy_wrdata[126]),
        .I2(out_fifo_20),
        .I3(out_fifo_5[49]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[462] [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_72__3
       (.I0(mem_reg_0_15_78_79[86]),
        .I1(phy_wrdata[126]),
        .I2(out_fifo_20),
        .I3(out_fifo_7[49]),
        .I4(out_fifo_8),
        .O(\write_buffer.wr_buf_out_data_reg[470] [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_72__4
       (.I0(mem_reg_0_15_78_79[94]),
        .I1(phy_wrdata[126]),
        .I2(out_fifo_20),
        .I3(out_fifo_9[49]),
        .I4(out_fifo_10),
        .O(\write_buffer.wr_buf_out_data_reg[478] [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_72__5
       (.I0(mem_reg_0_15_78_79[110]),
        .I1(phy_wrdata[126]),
        .I2(out_fifo_20),
        .I3(out_fifo_14[49]),
        .I4(out_fifo_15),
        .O(\write_buffer.wr_buf_out_data_reg[494] [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_72__6
       (.I0(mem_reg_0_15_78_79[118]),
        .I1(phy_wrdata[126]),
        .I2(out_fifo_20),
        .I3(out_fifo_16[49]),
        .I4(out_fifo_17),
        .O(\write_buffer.wr_buf_out_data_reg[502] [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_72__7
       (.I0(mem_reg_0_15_78_79[126]),
        .I1(phy_wrdata[126]),
        .I2(out_fifo_21),
        .I3(out_fifo_18[49]),
        .I4(out_fifo_19),
        .O(\write_buffer.wr_buf_out_data_reg[510] [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_73__1
       (.I0(mc_address[1]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[1] ),
        .I2(phy_ctl_wr_i1_reg),
        .I3(mem_out[28]),
        .I4(out_fifo),
        .O(D8[0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_73__2
       (.I0(mem_reg_0_15_78_79[14]),
        .I1(phy_wrdata[62]),
        .I2(out_fifo_2),
        .I3(out_fifo_5[48]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[462] [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_73__3
       (.I0(mem_reg_0_15_78_79[22]),
        .I1(phy_wrdata[62]),
        .I2(out_fifo_2),
        .I3(out_fifo_7[48]),
        .I4(out_fifo_8),
        .O(\write_buffer.wr_buf_out_data_reg[470] [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_73__4
       (.I0(mem_reg_0_15_78_79[30]),
        .I1(phy_wrdata[62]),
        .I2(out_fifo_11),
        .I3(out_fifo_9[48]),
        .I4(out_fifo_10),
        .O(\write_buffer.wr_buf_out_data_reg[478] [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_73__5
       (.I0(mem_reg_0_15_78_79[46]),
        .I1(phy_wrdata[62]),
        .I2(out_fifo_11),
        .I3(out_fifo_14[48]),
        .I4(out_fifo_15),
        .O(\write_buffer.wr_buf_out_data_reg[494] [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_73__6
       (.I0(mem_reg_0_15_78_79[54]),
        .I1(phy_wrdata[62]),
        .I2(out_fifo_11),
        .I3(out_fifo_16[48]),
        .I4(out_fifo_17),
        .O(\write_buffer.wr_buf_out_data_reg[502] [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_73__7
       (.I0(mem_reg_0_15_78_79[62]),
        .I1(phy_wrdata[62]),
        .I2(out_fifo_11),
        .I3(out_fifo_18[48]),
        .I4(out_fifo_19),
        .O(\write_buffer.wr_buf_out_data_reg[510] [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_74__0
       (.I0(mem_reg_0_15_78_79[455]),
        .I1(phy_wrdata[511]),
        .I2(out_fifo_27),
        .I3(out_fifo_3[63]),
        .I4(out_fifo_4),
        .O(\write_buffer.wr_buf_out_data_reg[455] [7]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_74__1
       (.I0(mem_reg_0_15_78_79[463]),
        .I1(phy_wrdata[511]),
        .I2(out_fifo_27),
        .I3(out_fifo_5[63]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[463] [7]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_74__2
       (.I0(mem_reg_0_15_78_79[471]),
        .I1(phy_wrdata[511]),
        .I2(out_fifo_28),
        .I3(out_fifo_7[63]),
        .I4(out_fifo_8),
        .O(\write_buffer.wr_buf_out_data_reg[471] [7]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_74__3
       (.I0(mem_reg_0_15_78_79[479]),
        .I1(phy_wrdata[511]),
        .I2(out_fifo_28),
        .I3(out_fifo_9[63]),
        .I4(out_fifo_10),
        .O(\write_buffer.wr_buf_out_data_reg[479] [7]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_74__4
       (.I0(mem_reg_0_15_78_79[487]),
        .I1(phy_wrdata[511]),
        .I2(out_fifo_28),
        .I3(out_fifo_12[63]),
        .I4(out_fifo_13),
        .O(\write_buffer.wr_buf_out_data_reg[487] [7]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_74__5
       (.I0(mem_reg_0_15_78_79[495]),
        .I1(phy_wrdata[511]),
        .I2(out_fifo_28),
        .I3(out_fifo_14[63]),
        .I4(out_fifo_15),
        .O(\write_buffer.wr_buf_out_data_reg[495] [7]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_74__6
       (.I0(mem_reg_0_15_78_79[503]),
        .I1(phy_wrdata[511]),
        .I2(out_fifo_28),
        .I3(out_fifo_16[63]),
        .I4(out_fifo_17),
        .O(\write_buffer.wr_buf_out_data_reg[503] [7]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_74__7
       (.I0(mem_reg_0_15_78_79[511]),
        .I1(phy_wrdata[511]),
        .I2(out_fifo_28),
        .I3(out_fifo_18[63]),
        .I4(out_fifo_19),
        .O(\write_buffer.wr_buf_out_data_reg[511] [7]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_75__0
       (.I0(mem_reg_0_15_78_79[391]),
        .I1(phy_wrdata[447]),
        .I2(out_fifo_26),
        .I3(out_fifo_3[62]),
        .I4(out_fifo_4),
        .O(\write_buffer.wr_buf_out_data_reg[455] [6]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_75__1
       (.I0(mem_reg_0_15_78_79[399]),
        .I1(phy_wrdata[447]),
        .I2(out_fifo_26),
        .I3(out_fifo_5[62]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[463] [6]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_75__2
       (.I0(mem_reg_0_15_78_79[407]),
        .I1(phy_wrdata[447]),
        .I2(out_fifo_26),
        .I3(out_fifo_7[62]),
        .I4(out_fifo_8),
        .O(\write_buffer.wr_buf_out_data_reg[471] [6]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_75__3
       (.I0(mem_reg_0_15_78_79[415]),
        .I1(phy_wrdata[447]),
        .I2(out_fifo_26),
        .I3(out_fifo_9[62]),
        .I4(out_fifo_10),
        .O(\write_buffer.wr_buf_out_data_reg[479] [6]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_75__4
       (.I0(mem_reg_0_15_78_79[423]),
        .I1(phy_wrdata[447]),
        .I2(out_fifo_27),
        .I3(out_fifo_12[62]),
        .I4(out_fifo_13),
        .O(\write_buffer.wr_buf_out_data_reg[487] [6]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_75__5
       (.I0(mem_reg_0_15_78_79[431]),
        .I1(phy_wrdata[447]),
        .I2(out_fifo_27),
        .I3(out_fifo_14[62]),
        .I4(out_fifo_15),
        .O(\write_buffer.wr_buf_out_data_reg[495] [6]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_75__6
       (.I0(mem_reg_0_15_78_79[439]),
        .I1(phy_wrdata[447]),
        .I2(out_fifo_27),
        .I3(out_fifo_16[62]),
        .I4(out_fifo_17),
        .O(\write_buffer.wr_buf_out_data_reg[503] [6]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_75__7
       (.I0(mem_reg_0_15_78_79[447]),
        .I1(phy_wrdata[447]),
        .I2(out_fifo_27),
        .I3(out_fifo_18[62]),
        .I4(out_fifo_19),
        .O(\write_buffer.wr_buf_out_data_reg[511] [6]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_76
       (.I0(mem_reg_0_15_78_79[327]),
        .I1(phy_wrdata[383]),
        .I2(out_fifo_25),
        .I3(out_fifo_3[61]),
        .I4(out_fifo_4),
        .O(\write_buffer.wr_buf_out_data_reg[455] [5]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_76__0
       (.I0(mem_reg_0_15_78_79[335]),
        .I1(phy_wrdata[383]),
        .I2(out_fifo_25),
        .I3(out_fifo_5[61]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[463] [5]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_76__1
       (.I0(mem_reg_0_15_78_79[343]),
        .I1(phy_wrdata[383]),
        .I2(out_fifo_25),
        .I3(out_fifo_7[61]),
        .I4(out_fifo_8),
        .O(\write_buffer.wr_buf_out_data_reg[471] [5]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_76__2
       (.I0(mem_reg_0_15_78_79[351]),
        .I1(phy_wrdata[383]),
        .I2(out_fifo_25),
        .I3(out_fifo_9[61]),
        .I4(out_fifo_10),
        .O(\write_buffer.wr_buf_out_data_reg[479] [5]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_76__3
       (.I0(mem_reg_0_15_78_79[359]),
        .I1(phy_wrdata[383]),
        .I2(out_fifo_25),
        .I3(out_fifo_12[61]),
        .I4(out_fifo_13),
        .O(\write_buffer.wr_buf_out_data_reg[487] [5]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_76__4
       (.I0(mem_reg_0_15_78_79[367]),
        .I1(phy_wrdata[383]),
        .I2(out_fifo_25),
        .I3(out_fifo_14[61]),
        .I4(out_fifo_15),
        .O(\write_buffer.wr_buf_out_data_reg[495] [5]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_76__5
       (.I0(mem_reg_0_15_78_79[375]),
        .I1(phy_wrdata[383]),
        .I2(out_fifo_26),
        .I3(out_fifo_16[61]),
        .I4(out_fifo_17),
        .O(\write_buffer.wr_buf_out_data_reg[503] [5]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_76__6
       (.I0(mem_reg_0_15_78_79[383]),
        .I1(phy_wrdata[383]),
        .I2(out_fifo_26),
        .I3(out_fifo_18[61]),
        .I4(out_fifo_19),
        .O(\write_buffer.wr_buf_out_data_reg[511] [5]));
  LUT4 #(
    .INIT(16'hEEF0)) 
    out_fifo_i_76__7
       (.I0(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9] ),
        .I1(out_fifo_31),
        .I2(mem_out[35]),
        .I3(out_fifo),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[9]_0 [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_77
       (.I0(mc_address[32]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9] ),
        .I2(out_fifo_2),
        .I3(mem_out[34]),
        .I4(out_fifo),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[9]_0 [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_77__0
       (.I0(mem_reg_0_15_78_79[263]),
        .I1(phy_wrdata[319]),
        .I2(out_fifo_23),
        .I3(out_fifo_3[60]),
        .I4(out_fifo_4),
        .O(\write_buffer.wr_buf_out_data_reg[455] [4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_77__1
       (.I0(mem_reg_0_15_78_79[271]),
        .I1(phy_wrdata[319]),
        .I2(out_fifo_23),
        .I3(out_fifo_5[60]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[463] [4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_77__2
       (.I0(mem_reg_0_15_78_79[279]),
        .I1(phy_wrdata[319]),
        .I2(out_fifo_24),
        .I3(out_fifo_7[60]),
        .I4(out_fifo_8),
        .O(\write_buffer.wr_buf_out_data_reg[471] [4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_77__3
       (.I0(mem_reg_0_15_78_79[287]),
        .I1(phy_wrdata[319]),
        .I2(out_fifo_24),
        .I3(out_fifo_9[60]),
        .I4(out_fifo_10),
        .O(\write_buffer.wr_buf_out_data_reg[479] [4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_77__4
       (.I0(mem_reg_0_15_78_79[295]),
        .I1(phy_wrdata[319]),
        .I2(out_fifo_24),
        .I3(out_fifo_12[60]),
        .I4(out_fifo_13),
        .O(\write_buffer.wr_buf_out_data_reg[487] [4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_77__5
       (.I0(mem_reg_0_15_78_79[303]),
        .I1(phy_wrdata[319]),
        .I2(out_fifo_24),
        .I3(out_fifo_14[60]),
        .I4(out_fifo_15),
        .O(\write_buffer.wr_buf_out_data_reg[495] [4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_77__6
       (.I0(mem_reg_0_15_78_79[311]),
        .I1(phy_wrdata[319]),
        .I2(out_fifo_24),
        .I3(out_fifo_16[60]),
        .I4(out_fifo_17),
        .O(\write_buffer.wr_buf_out_data_reg[503] [4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_77__7
       (.I0(mem_reg_0_15_78_79[319]),
        .I1(phy_wrdata[319]),
        .I2(out_fifo_24),
        .I3(out_fifo_18[60]),
        .I4(out_fifo_19),
        .O(\write_buffer.wr_buf_out_data_reg[511] [4]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_78
       (.I0(mc_address[21]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9] ),
        .I2(phy_ctl_wr_i1_reg),
        .I3(mem_out[33]),
        .I4(out_fifo),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[9]_0 [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_78__0
       (.I0(mem_reg_0_15_78_79[199]),
        .I1(phy_wrdata[255]),
        .I2(out_fifo_22),
        .I3(out_fifo_3[59]),
        .I4(out_fifo_4),
        .O(\write_buffer.wr_buf_out_data_reg[455] [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_78__1
       (.I0(mem_reg_0_15_78_79[207]),
        .I1(phy_wrdata[255]),
        .I2(out_fifo_22),
        .I3(out_fifo_5[59]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[463] [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_78__2
       (.I0(mem_reg_0_15_78_79[215]),
        .I1(phy_wrdata[255]),
        .I2(out_fifo_22),
        .I3(out_fifo_7[59]),
        .I4(out_fifo_8),
        .O(\write_buffer.wr_buf_out_data_reg[471] [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_78__3
       (.I0(mem_reg_0_15_78_79[223]),
        .I1(phy_wrdata[255]),
        .I2(out_fifo_23),
        .I3(out_fifo_9[59]),
        .I4(out_fifo_10),
        .O(\write_buffer.wr_buf_out_data_reg[479] [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_78__4
       (.I0(mem_reg_0_15_78_79[231]),
        .I1(phy_wrdata[255]),
        .I2(out_fifo_23),
        .I3(out_fifo_12[59]),
        .I4(out_fifo_13),
        .O(\write_buffer.wr_buf_out_data_reg[487] [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_78__5
       (.I0(mem_reg_0_15_78_79[239]),
        .I1(phy_wrdata[255]),
        .I2(out_fifo_23),
        .I3(out_fifo_14[59]),
        .I4(out_fifo_15),
        .O(\write_buffer.wr_buf_out_data_reg[495] [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_78__6
       (.I0(mem_reg_0_15_78_79[247]),
        .I1(phy_wrdata[255]),
        .I2(out_fifo_23),
        .I3(out_fifo_16[59]),
        .I4(out_fifo_17),
        .O(\write_buffer.wr_buf_out_data_reg[503] [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_78__7
       (.I0(mem_reg_0_15_78_79[255]),
        .I1(phy_wrdata[255]),
        .I2(out_fifo_23),
        .I3(out_fifo_18[59]),
        .I4(out_fifo_19),
        .O(\write_buffer.wr_buf_out_data_reg[511] [3]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_79
       (.I0(mc_address[9]),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address_reg_n_0_[9] ),
        .I2(phy_ctl_wr_i1_reg),
        .I3(mem_out[32]),
        .I4(out_fifo),
        .O(\gen_no_mirror.div_clk_loop[0].phy_address_reg[9]_0 [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_79__0
       (.I0(mem_reg_0_15_78_79[135]),
        .I1(phy_wrdata[191]),
        .I2(out_fifo_21),
        .I3(out_fifo_3[58]),
        .I4(out_fifo_4),
        .O(\write_buffer.wr_buf_out_data_reg[455] [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_79__1
       (.I0(mem_reg_0_15_78_79[143]),
        .I1(phy_wrdata[191]),
        .I2(out_fifo_21),
        .I3(out_fifo_5[58]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[463] [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_79__2
       (.I0(mem_reg_0_15_78_79[151]),
        .I1(phy_wrdata[191]),
        .I2(out_fifo_21),
        .I3(out_fifo_7[58]),
        .I4(out_fifo_8),
        .O(\write_buffer.wr_buf_out_data_reg[471] [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_79__3
       (.I0(mem_reg_0_15_78_79[159]),
        .I1(phy_wrdata[191]),
        .I2(out_fifo_21),
        .I3(out_fifo_9[58]),
        .I4(out_fifo_10),
        .O(\write_buffer.wr_buf_out_data_reg[479] [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_79__4
       (.I0(mem_reg_0_15_78_79[167]),
        .I1(phy_wrdata[191]),
        .I2(out_fifo_21),
        .I3(out_fifo_12[58]),
        .I4(out_fifo_13),
        .O(\write_buffer.wr_buf_out_data_reg[487] [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_79__5
       (.I0(mem_reg_0_15_78_79[175]),
        .I1(phy_wrdata[191]),
        .I2(out_fifo_22),
        .I3(out_fifo_14[58]),
        .I4(out_fifo_15),
        .O(\write_buffer.wr_buf_out_data_reg[495] [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_79__6
       (.I0(mem_reg_0_15_78_79[183]),
        .I1(phy_wrdata[191]),
        .I2(out_fifo_22),
        .I3(out_fifo_16[58]),
        .I4(out_fifo_17),
        .O(\write_buffer.wr_buf_out_data_reg[503] [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_79__7
       (.I0(mem_reg_0_15_78_79[191]),
        .I1(phy_wrdata[191]),
        .I2(out_fifo_22),
        .I3(out_fifo_18[58]),
        .I4(out_fifo_19),
        .O(\write_buffer.wr_buf_out_data_reg[511] [2]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_80
       (.I0(mem_reg_0_15_78_79[71]),
        .I1(phy_wrdata[127]),
        .I2(out_fifo_11),
        .I3(out_fifo_3[57]),
        .I4(out_fifo_4),
        .O(\write_buffer.wr_buf_out_data_reg[455] [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_80__0
       (.I0(mem_reg_0_15_78_79[79]),
        .I1(phy_wrdata[127]),
        .I2(out_fifo_20),
        .I3(out_fifo_5[57]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[463] [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_80__1
       (.I0(mem_reg_0_15_78_79[87]),
        .I1(phy_wrdata[127]),
        .I2(out_fifo_20),
        .I3(out_fifo_7[57]),
        .I4(out_fifo_8),
        .O(\write_buffer.wr_buf_out_data_reg[471] [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_80__2
       (.I0(mem_reg_0_15_78_79[95]),
        .I1(phy_wrdata[127]),
        .I2(out_fifo_20),
        .I3(out_fifo_9[57]),
        .I4(out_fifo_10),
        .O(\write_buffer.wr_buf_out_data_reg[479] [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_80__3
       (.I0(mem_reg_0_15_78_79[103]),
        .I1(phy_wrdata[127]),
        .I2(out_fifo_20),
        .I3(out_fifo_12[57]),
        .I4(out_fifo_13),
        .O(\write_buffer.wr_buf_out_data_reg[487] [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_80__4
       (.I0(mem_reg_0_15_78_79[111]),
        .I1(phy_wrdata[127]),
        .I2(out_fifo_20),
        .I3(out_fifo_14[57]),
        .I4(out_fifo_15),
        .O(\write_buffer.wr_buf_out_data_reg[495] [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_80__5
       (.I0(mem_reg_0_15_78_79[119]),
        .I1(phy_wrdata[127]),
        .I2(out_fifo_20),
        .I3(out_fifo_16[57]),
        .I4(out_fifo_17),
        .O(\write_buffer.wr_buf_out_data_reg[503] [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_80__6
       (.I0(mem_reg_0_15_78_79[127]),
        .I1(phy_wrdata[127]),
        .I2(out_fifo_21),
        .I3(out_fifo_18[57]),
        .I4(out_fifo_19),
        .O(\write_buffer.wr_buf_out_data_reg[511] [1]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_81
       (.I0(mem_reg_0_15_78_79[7]),
        .I1(phy_wrdata[63]),
        .I2(out_fifo_2),
        .I3(out_fifo_3[56]),
        .I4(out_fifo_4),
        .O(\write_buffer.wr_buf_out_data_reg[455] [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_81__0
       (.I0(mem_reg_0_15_78_79[15]),
        .I1(phy_wrdata[63]),
        .I2(out_fifo_2),
        .I3(out_fifo_5[56]),
        .I4(out_fifo_6),
        .O(\write_buffer.wr_buf_out_data_reg[463] [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_81__1
       (.I0(mem_reg_0_15_78_79[23]),
        .I1(phy_wrdata[63]),
        .I2(out_fifo_2),
        .I3(out_fifo_7[56]),
        .I4(out_fifo_8),
        .O(\write_buffer.wr_buf_out_data_reg[471] [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_81__2
       (.I0(mem_reg_0_15_78_79[31]),
        .I1(phy_wrdata[63]),
        .I2(out_fifo_11),
        .I3(out_fifo_9[56]),
        .I4(out_fifo_10),
        .O(\write_buffer.wr_buf_out_data_reg[479] [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_81__3
       (.I0(mem_reg_0_15_78_79[39]),
        .I1(phy_wrdata[63]),
        .I2(out_fifo_11),
        .I3(out_fifo_12[56]),
        .I4(out_fifo_13),
        .O(\write_buffer.wr_buf_out_data_reg[487] [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_81__4
       (.I0(mem_reg_0_15_78_79[47]),
        .I1(phy_wrdata[63]),
        .I2(out_fifo_11),
        .I3(out_fifo_14[56]),
        .I4(out_fifo_15),
        .O(\write_buffer.wr_buf_out_data_reg[495] [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_81__5
       (.I0(mem_reg_0_15_78_79[55]),
        .I1(phy_wrdata[63]),
        .I2(out_fifo_11),
        .I3(out_fifo_16[56]),
        .I4(out_fifo_17),
        .O(\write_buffer.wr_buf_out_data_reg[503] [0]));
  LUT5 #(
    .INIT(32'hACACFF00)) 
    out_fifo_i_81__6
       (.I0(mem_reg_0_15_78_79[63]),
        .I1(phy_wrdata[63]),
        .I2(out_fifo_11),
        .I3(out_fifo_18[56]),
        .I4(out_fifo_19),
        .O(\write_buffer.wr_buf_out_data_reg[511] [0]));
  (* SOFT_HLUTNM = "soft_lutpair509" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \phy_ctl_wd_i1[0]_i_1 
       (.I0(mc_cmd[0]),
        .I1(calib_cmd[0]),
        .I2(\phy_ctl_wd_i1_reg[0] ),
        .O(\calib_seq_reg[1]_0 [0]));
  (* SOFT_HLUTNM = "soft_lutpair511" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \phy_ctl_wd_i1[17]_i_1 
       (.I0(\phy_ctl_wd_i1_reg[17] ),
        .I1(calib_data_offset_0[0]),
        .I2(\phy_ctl_wd_i1_reg[0] ),
        .O(\calib_seq_reg[1]_0 [3]));
  (* SOFT_HLUTNM = "soft_lutpair515" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \phy_ctl_wd_i1[18]_i_1 
       (.I0(\phy_ctl_wd_i1_reg[18] ),
        .I1(calib_data_offset_0[1]),
        .I2(\phy_ctl_wd_i1_reg[0] ),
        .O(\calib_seq_reg[1]_0 [4]));
  (* SOFT_HLUTNM = "soft_lutpair517" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \phy_ctl_wd_i1[19]_i_1 
       (.I0(\phy_ctl_wd_i1_reg[19] ),
        .I1(calib_data_offset_0[2]),
        .I2(\phy_ctl_wd_i1_reg[0] ),
        .O(\calib_seq_reg[1]_0 [5]));
  (* SOFT_HLUTNM = "soft_lutpair509" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \phy_ctl_wd_i1[1]_i_1 
       (.I0(mc_cmd[1]),
        .I1(calib_cmd[1]),
        .I2(\phy_ctl_wd_i1_reg[0] ),
        .O(\calib_seq_reg[1]_0 [1]));
  LUT3 #(
    .INIT(8'hAC)) 
    \phy_ctl_wd_i1[20]_i_1 
       (.I0(mc_data_offset),
        .I1(calib_data_offset_0[3]),
        .I2(\phy_ctl_wd_i1_reg[0] ),
        .O(\calib_seq_reg[1]_0 [6]));
  (* SOFT_HLUTNM = "soft_lutpair517" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \phy_ctl_wd_i1[21]_i_1 
       (.I0(\phy_ctl_wd_i1_reg[21] ),
        .I1(calib_data_offset_0[4]),
        .I2(\phy_ctl_wd_i1_reg[0] ),
        .O(\calib_seq_reg[1]_0 [7]));
  (* SOFT_HLUTNM = "soft_lutpair515" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \phy_ctl_wd_i1[22]_i_1 
       (.I0(\phy_ctl_wd_i1_reg[22] ),
        .I1(calib_data_offset_0[5]),
        .I2(\phy_ctl_wd_i1_reg[0] ),
        .O(\calib_seq_reg[1]_0 [8]));
  (* SOFT_HLUTNM = "soft_lutpair511" *) 
  LUT3 #(
    .INIT(8'hAC)) 
    \phy_ctl_wd_i1[2]_i_1 
       (.I0(mc_cas_n),
        .I1(calib_cmd[2]),
        .I2(\phy_ctl_wd_i1_reg[0] ),
        .O(\calib_seq_reg[1]_0 [2]));
  FDCE phy_reset_n_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .CLR(\en_cnt_div4.enable_wrlvl_cnt_reg[2]_0 ),
        .D(cnt_pwron_reset_done_r),
        .Q(phy_reset_n));
  FDRE pi_calib_done_r1_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(pi_calib_done_r),
        .Q(pi_calib_done),
        .R(1'b0));
  LUT2 #(
    .INIT(4'hE)) 
    pi_calib_done_r_i_1
       (.I0(pi_calib_rank_done_r),
        .I1(pi_calib_done_r),
        .O(pi_calib_done_r_i_1_n_0));
  FDRE pi_calib_done_r_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(pi_calib_done_r_i_1_n_0),
        .Q(pi_calib_done_r),
        .R(\en_cnt_div4.enable_wrlvl_cnt_reg[2]_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    pi_calib_rank_done_r_i_1
       (.I0(pi_phase_locked_all_r3),
        .I1(pi_phase_locked_all_r4),
        .O(init_next_state1100_out));
  FDRE pi_calib_rank_done_r_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(init_next_state1100_out),
        .Q(pi_calib_rank_done_r),
        .R(\victim_sel_reg[0]_0 ));
  FDRE pi_dqs_found_done_r1_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(pi_dqs_found_done_r1_reg_0),
        .Q(pi_dqs_found_done_r1),
        .R(\en_cnt_div4.enable_wrlvl_cnt_reg[2]_0 ));
  LUT5 #(
    .INIT(32'h000000AB)) 
    pi_dqs_found_start_i_1
       (.I0(pi_dqs_found_start_reg_0),
        .I1(pi_dqs_found_done_r1_reg_0),
        .I2(pi_dqs_found_start_i_2_n_0),
        .I3(wrlvl_byte_redo),
        .I4(\rd_addr_reg[7] ),
        .O(pi_dqs_found_start_i_1_n_0));
  LUT6 #(
    .INIT(64'hFFFEFFFFFFFFFFFF)) 
    pi_dqs_found_start_i_2
       (.I0(\init_state_r_reg_n_0_[3] ),
        .I1(\init_state_r_reg_n_0_[2] ),
        .I2(init_state_r),
        .I3(\init_state_r_reg_n_0_[5] ),
        .I4(\init_state_r_reg_n_0_[4] ),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ),
        .O(pi_dqs_found_start_i_2_n_0));
  FDRE pi_dqs_found_start_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(pi_dqs_found_start_i_1_n_0),
        .Q(pi_dqs_found_start_reg_0),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE pi_phase_locked_all_r1_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(pi_phase_locked_all_r1_reg_0),
        .Q(pi_phase_locked_all_r1),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE pi_phase_locked_all_r2_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(pi_phase_locked_all_r1),
        .Q(pi_phase_locked_all_r2),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE pi_phase_locked_all_r3_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(pi_phase_locked_all_r2),
        .Q(pi_phase_locked_all_r3),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE pi_phase_locked_all_r4_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(pi_phase_locked_all_r3),
        .Q(pi_phase_locked_all_r4),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h000000000E0E0E00)) 
    prbs_gen_clk_en_i_1
       (.I0(\one_rank.stg1_wr_done_reg_0 ),
        .I1(wr_victim_inc_i_2_n_0),
        .I2(\rd_addr_reg[7] ),
        .I3(prbs_gen_clk_en0),
        .I4(prbs_gen_clk_en),
        .I5(complex_oclkdelay_calib_done_r1_reg_0),
        .O(prbs_gen_clk_en_i_1_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFF444444F4)) 
    prbs_gen_clk_en_i_2
       (.I0(prbs_gen_clk_en_i_3_n_0),
        .I1(rdlvl_stg1_done_r1),
        .I2(prbs_rdlvl_start_reg_0),
        .I3(prbs_gen_clk_en_i_4_n_0),
        .I4(prbs_rdlvl_start_i_2_n_0),
        .I5(\stg1_wr_rd_cnt[8]_i_4_n_0 ),
        .O(prbs_gen_clk_en0));
  LUT6 #(
    .INIT(64'h00D0D0D0D0D0D0D0)) 
    prbs_gen_clk_en_i_3
       (.I0(\complex_num_writes[3]_i_4_n_0 ),
        .I1(prbs_gen_clk_en_i_5_n_0),
        .I2(\rd_addr_reg[7]_0 ),
        .I3(\cnt_cmd_r[6]_i_4_n_0 ),
        .I4(\cnt_cmd_r_reg_n_0_[6] ),
        .I5(\stg1_wr_rd_cnt[4]_i_4_n_0 ),
        .O(prbs_gen_clk_en_i_3_n_0));
  (* SOFT_HLUTNM = "soft_lutpair425" *) 
  LUT5 #(
    .INIT(32'hFFFEFFFF)) 
    prbs_gen_clk_en_i_4
       (.I0(\init_state_r_reg_n_0_[3] ),
        .I1(\init_state_r_reg_n_0_[2] ),
        .I2(init_state_r),
        .I3(\init_state_r_reg_n_0_[5] ),
        .I4(\init_state_r_reg_n_0_[4] ),
        .O(prbs_gen_clk_en_i_4_n_0));
  (* SOFT_HLUTNM = "soft_lutpair402" *) 
  LUT4 #(
    .INIT(16'hFF7F)) 
    prbs_gen_clk_en_i_5
       (.I0(complex_wait_cnt_reg[2]),
        .I1(complex_wait_cnt_reg[3]),
        .I2(complex_wait_cnt_reg[1]),
        .I3(complex_wait_cnt_reg[0]),
        .O(prbs_gen_clk_en_i_5_n_0));
  FDRE prbs_gen_clk_en_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(prbs_gen_clk_en_i_1_n_0),
        .Q(prbs_gen_clk_en),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000000080)) 
    prbs_gen_oclk_clk_en_i_1
       (.I0(prbs_gen_oclk_clk_en_i_2_n_0),
        .I1(complex_ocal_wr_start),
        .I2(prbs_gen_oclk_clk_en_i_3_n_0),
        .I3(prbs_gen_oclk_clk_en_i_4_n_0),
        .I4(prbs_gen_oclk_clk_en_i_5_n_0),
        .I5(prbs_gen_oclk_clk_en_i_6_n_0),
        .O(prbs_gen_oclk_clk_en_i_1_n_0));
  LUT6 #(
    .INIT(64'h0000080000000000)) 
    prbs_gen_oclk_clk_en_i_10
       (.I0(complex_byte_rd_done),
        .I1(\init_state_r_reg_n_0_[4] ),
        .I2(init_state_r),
        .I3(\init_state_r_reg_n_0_[5] ),
        .I4(\wrcal_reads[7]_i_4_n_0 ),
        .I5(detect_pi_found_dqs_i_2_n_0),
        .O(prbs_gen_oclk_clk_en_i_10_n_0));
  LUT5 #(
    .INIT(32'h10000000)) 
    prbs_gen_oclk_clk_en_i_11
       (.I0(init_state_r1[0]),
        .I1(init_state_r1[6]),
        .I2(init_state_r1[5]),
        .I3(init_state_r1[4]),
        .I4(init_state_r1[3]),
        .O(prbs_gen_oclk_clk_en_i_11_n_0));
  (* SOFT_HLUTNM = "soft_lutpair427" *) 
  LUT5 #(
    .INIT(32'hF7FFFFFF)) 
    prbs_gen_oclk_clk_en_i_12
       (.I0(\init_state_r_reg_n_0_[3] ),
        .I1(\init_state_r_reg_n_0_[4] ),
        .I2(init_state_r),
        .I3(\init_state_r_reg_n_0_[5] ),
        .I4(\init_state_r_reg_n_0_[2] ),
        .O(prbs_gen_oclk_clk_en_i_12_n_0));
  (* SOFT_HLUTNM = "soft_lutpair494" *) 
  LUT3 #(
    .INIT(8'h54)) 
    prbs_gen_oclk_clk_en_i_2
       (.I0(write_calib_reg_0),
        .I1(wr_victim_inc_i_2_n_0),
        .I2(\one_rank.stg1_wr_done_reg_0 ),
        .O(prbs_gen_oclk_clk_en_i_2_n_0));
  LUT6 #(
    .INIT(64'h00000000EEEFEEEE)) 
    prbs_gen_oclk_clk_en_i_3
       (.I0(prbs_gen_oclk_clk_en),
        .I1(prbs_gen_oclk_clk_en_i_7_n_0),
        .I2(\one_rank.stg1_wr_done_reg_0 ),
        .I3(complex_row1_wr_done),
        .I4(prbs_gen_oclk_clk_en_i_8_n_0),
        .I5(complex_oclkdelay_calib_done_r1_reg_0),
        .O(prbs_gen_oclk_clk_en_i_3_n_0));
  LUT6 #(
    .INIT(64'h0000000000000008)) 
    prbs_gen_oclk_clk_en_i_4
       (.I0(\init_state_r[5]_i_13_n_0 ),
        .I1(\complex_num_writes_reg_n_0_[0] ),
        .I2(\complex_num_writes_reg_n_0_[1] ),
        .I3(\complex_num_writes_reg_n_0_[2] ),
        .I4(\complex_num_writes_reg_n_0_[3] ),
        .I5(\complex_num_writes_reg_n_0_[4] ),
        .O(prbs_gen_oclk_clk_en_i_4_n_0));
  LUT6 #(
    .INIT(64'h11111F1111111111)) 
    prbs_gen_oclk_clk_en_i_5
       (.I0(complex_oclkdelay_calib_start_int_i_2_n_0),
        .I1(prbs_rdlvl_start_i_2_n_0),
        .I2(prbs_gen_oclk_clk_en_i_9_n_0),
        .I3(complex_num_writes_dec[1]),
        .I4(complex_num_writes_dec[0]),
        .I5(\stg1_wr_rd_cnt[8]_i_5_n_0 ),
        .O(prbs_gen_oclk_clk_en_i_5_n_0));
  LUT6 #(
    .INIT(64'hEAAAAAAAEAAAEAAA)) 
    prbs_gen_oclk_clk_en_i_6
       (.I0(prbs_gen_oclk_clk_en_i_10_n_0),
        .I1(init_state_r1[2]),
        .I2(init_state_r1[1]),
        .I3(prbs_gen_oclk_clk_en_i_11_n_0),
        .I4(prbs_gen_oclk_clk_en_i_12_n_0),
        .I5(detect_pi_found_dqs_i_2_n_0),
        .O(prbs_gen_oclk_clk_en_i_6_n_0));
  LUT6 #(
    .INIT(64'hCFCCCFCCFFFFEFEE)) 
    prbs_gen_oclk_clk_en_i_7
       (.I0(\complex_address[9]_i_3_n_0 ),
        .I1(\stg1_wr_rd_cnt[8]_i_4_n_0 ),
        .I2(\rd_addr_reg[7]_0 ),
        .I3(prbs_rdlvl_done_r1),
        .I4(complex_ocal_reset_rd_addr_i_3_n_0),
        .I5(prbs_gen_clk_en_i_5_n_0),
        .O(prbs_gen_oclk_clk_en_i_7_n_0));
  (* SOFT_HLUTNM = "soft_lutpair402" *) 
  LUT5 #(
    .INIT(32'h20000000)) 
    prbs_gen_oclk_clk_en_i_8
       (.I0(\complex_num_writes[3]_i_4_n_0 ),
        .I1(complex_wait_cnt_reg[0]),
        .I2(complex_wait_cnt_reg[1]),
        .I3(complex_wait_cnt_reg[3]),
        .I4(complex_wait_cnt_reg[2]),
        .O(prbs_gen_oclk_clk_en_i_8_n_0));
  LUT3 #(
    .INIT(8'hFE)) 
    prbs_gen_oclk_clk_en_i_9
       (.I0(complex_num_writes_dec[2]),
        .I1(complex_num_writes_dec[4]),
        .I2(complex_num_writes_dec[3]),
        .O(prbs_gen_oclk_clk_en_i_9_n_0));
  FDRE prbs_gen_oclk_clk_en_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(prbs_gen_oclk_clk_en_i_1_n_0),
        .Q(prbs_gen_oclk_clk_en),
        .R(1'b0));
  FDRE prbs_last_byte_done_r_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(prbs_last_byte_done),
        .Q(prbs_last_byte_done_r),
        .R(1'b0));
  FDRE prbs_rdlvl_done_pulse_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(prbs_rdlvl_done_pulse0),
        .Q(prbs_rdlvl_done_pulse_reg_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF00000020)) 
    prbs_rdlvl_start_i_1
       (.I0(pi_dqs_found_done_r1_reg_0),
        .I1(complex_oclkdelay_calib_done_r1_reg_0),
        .I2(prbs_rdlvl_start_reg_2),
        .I3(prbs_rdlvl_start_i_2_n_0),
        .I4(prbs_rdlvl_start_i_3_n_0),
        .I5(prbs_rdlvl_start_reg_0),
        .O(prbs_rdlvl_start_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair445" *) 
  LUT2 #(
    .INIT(4'h7)) 
    prbs_rdlvl_start_i_2
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(Q),
        .O(prbs_rdlvl_start_i_2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair388" *) 
  LUT5 #(
    .INIT(32'hFFFEFFFF)) 
    prbs_rdlvl_start_i_3
       (.I0(\init_state_r_reg_n_0_[4] ),
        .I1(\init_state_r_reg_n_0_[3] ),
        .I2(\init_state_r_reg_n_0_[2] ),
        .I3(\init_state_r_reg_n_0_[5] ),
        .I4(init_state_r),
        .O(prbs_rdlvl_start_i_3_n_0));
  FDRE prbs_rdlvl_start_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(prbs_rdlvl_start_i_1_n_0),
        .Q(prbs_rdlvl_start_reg_0),
        .R(\victim_sel_reg[0]_0 ));
  (* srl_bus_name = "\u_mig_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/prech_done_dly_r_reg " *) 
  (* srl_name = "\u_mig_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/prech_done_dly_r_reg[15]_srl16 " *) 
  SRL16E \prech_done_dly_r_reg[15]_srl16 
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b1),
        .A3(1'b1),
        .CE(1'b1),
        .CLK(\rdlvl_start_dly0_r_reg[14]_0 ),
        .D(prech_done_pre),
        .Q(\prech_done_dly_r_reg[15]_srl16_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair478" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \prech_done_dly_r_reg[15]_srl16_i_1 
       (.I0(prech_pending_r_i_2_n_0),
        .I1(prech_req_posedge_r_reg_0),
        .O(prech_done_pre));
  FDRE prech_done_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\prech_done_dly_r_reg[15]_srl16_n_0 ),
        .Q(prech_done),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair478" *) 
  LUT3 #(
    .INIT(8'hBA)) 
    prech_pending_r_i_1
       (.I0(prech_req_posedge_r_reg_0),
        .I1(prech_pending_r_i_2_n_0),
        .I2(prech_pending_r),
        .O(prech_pending_r_i_1_n_0));
  LUT6 #(
    .INIT(64'hAAAAA800AAAAAAAA)) 
    prech_pending_r_i_2
       (.I0(prech_pending_r),
        .I1(\complex_row_cnt_ocal[3]_i_6_n_0 ),
        .I2(prech_pending_r_i_3_n_0),
        .I3(prbs_last_byte_done_r),
        .I4(prech_pending_r_i_4_n_0),
        .I5(prech_pending_r_i_5_n_0),
        .O(prech_pending_r_i_2_n_0));
  LUT6 #(
    .INIT(64'h0000000000000008)) 
    prech_pending_r_i_3
       (.I0(cnt_cmd_done_r),
        .I1(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ),
        .I2(\init_state_r_reg_n_0_[4] ),
        .I3(\init_state_r_reg_n_0_[5] ),
        .I4(init_state_r),
        .I5(rdlvl_stg1_start_int_i_2_n_0),
        .O(prech_pending_r_i_3_n_0));
  LUT5 #(
    .INIT(32'hFFFFF8FF)) 
    prech_pending_r_i_4
       (.I0(\stg1_wr_rd_cnt[4]_i_4_n_0 ),
        .I1(dqs_found_prech_req),
        .I2(stg1_wr_done),
        .I3(rdlvl_stg1_start_i_2_n_0),
        .I4(\num_refresh[3]_i_5_n_0 ),
        .O(prech_pending_r_i_4_n_0));
  LUT6 #(
    .INIT(64'hDDD0DDDDDDDDDDDD)) 
    prech_pending_r_i_5
       (.I0(cnt_cmd_done_r),
        .I1(prech_pending_r_i_6_n_0),
        .I2(complex_oclkdelay_calib_start_int_i_2_n_0),
        .I3(Q),
        .I4(\init_state_r_reg_n_0_[1] ),
        .I5(complex_oclkdelay_calib_start_r1),
        .O(prech_pending_r_i_5_n_0));
  LUT6 #(
    .INIT(64'h0000CCFDCCFDCCFD)) 
    prech_pending_r_i_6
       (.I0(\wrcal_reads[7]_i_5_n_0 ),
        .I1(\wrcal_reads[7]_i_7_n_0 ),
        .I2(\cnt_init_mr_r[0]_i_2_n_0 ),
        .I3(\init_state_r[0]_i_30_n_0 ),
        .I4(\stg1_wr_rd_cnt[4]_i_4_n_0 ),
        .I5(rdlvl_last_byte_done_r),
        .O(prech_pending_r_i_6_n_0));
  FDRE prech_pending_r_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(prech_pending_r_i_1_n_0),
        .Q(prech_pending_r),
        .R(\en_cnt_div4.enable_wrlvl_cnt_reg[2]_0 ));
  LUT6 #(
    .INIT(64'h5555555455545554)) 
    prech_req_posedge_r_i_1
       (.I0(prech_req_r),
        .I1(rdlvl_prech_req),
        .I2(wrcal_prech_req),
        .I3(prech_req_posedge_r_reg_1),
        .I4(dqs_found_prech_req),
        .I5(\init_state_r_reg[4]_1 ),
        .O(prech_req_posedge_r0));
  LUT6 #(
    .INIT(64'h0000000000000008)) 
    prech_req_posedge_r_i_2
       (.I0(detect_pi_found_dqs_i_2_n_0),
        .I1(\init_state_r_reg_n_0_[4] ),
        .I2(\init_state_r_reg_n_0_[5] ),
        .I3(init_state_r),
        .I4(\init_state_r_reg_n_0_[2] ),
        .I5(\init_state_r_reg_n_0_[3] ),
        .O(\init_state_r_reg[4]_1 ));
  FDRE prech_req_posedge_r_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(prech_req_posedge_r0),
        .Q(prech_req_posedge_r_reg_0),
        .R(\victim_sel_reg[0]_0 ));
  FDRE prech_req_r_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(prech_req),
        .Q(prech_req_r),
        .R(\victim_sel_reg[0]_0 ));
  LUT5 #(
    .INIT(32'h80000000)) 
    pwron_ce_r_i_1
       (.I0(cnt_pwron_ce_r_reg[9]),
        .I1(cnt_pwron_ce_r_reg[7]),
        .I2(pwron_ce_r_i_2_n_0),
        .I3(cnt_pwron_ce_r_reg[6]),
        .I4(cnt_pwron_ce_r_reg[8]),
        .O(pwron_ce_r_i_1_n_0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    pwron_ce_r_i_2
       (.I0(cnt_pwron_ce_r_reg[5]),
        .I1(cnt_pwron_ce_r_reg[3]),
        .I2(cnt_pwron_ce_r_reg[1]),
        .I3(cnt_pwron_ce_r_reg[0]),
        .I4(cnt_pwron_ce_r_reg[2]),
        .I5(cnt_pwron_ce_r_reg[4]),
        .O(pwron_ce_r_i_2_n_0));
  FDRE pwron_ce_r_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(pwron_ce_r_i_1_n_0),
        .Q(pwron_ce_r),
        .R(\victim_sel_reg[0]_0 ));
  LUT5 #(
    .INIT(32'hFF575757)) 
    \rd_addr[2]_i_3 
       (.I0(complex_oclkdelay_calib_done_r1_reg_0),
        .I1(prbs_gen_clk_en),
        .I2(prbs_gen_oclk_clk_en),
        .I3(complex_wr_done),
        .I4(\rd_addr_reg[7]_0 ),
        .O(prbs_rdlvl_done_reg_0));
  LUT6 #(
    .INIT(64'hBFBFBFAAAAAAAAAA)) 
    \rd_addr[3]_i_3 
       (.I0(\rd_addr_reg[3] ),
        .I1(\rd_addr_reg[7]_0 ),
        .I2(complex_wr_done),
        .I3(prbs_gen_oclk_clk_en),
        .I4(prbs_gen_clk_en),
        .I5(complex_oclkdelay_calib_done_r1_reg_0),
        .O(\rd_addr_reg[1] ));
  (* SOFT_HLUTNM = "soft_lutpair490" *) 
  LUT3 #(
    .INIT(8'hFE)) 
    \rd_addr[7]_i_1 
       (.I0(\rd_addr_reg[7] ),
        .I1(complex_ocal_reset_rd_addr),
        .I2(reset_rd_addr),
        .O(SR));
  LUT6 #(
    .INIT(64'h0BFF0BFF0BFF0000)) 
    \rd_addr[7]_i_2 
       (.I0(complex_oclkdelay_calib_done_r1_reg_0),
        .I1(prbs_rdlvl_start_reg_0),
        .I2(complex_wr_done),
        .I3(\rd_addr_reg[7]_0 ),
        .I4(prbs_gen_clk_en),
        .I5(prbs_gen_oclk_clk_en),
        .O(prbs_rdlvl_done_reg));
  FDRE rdlvl_last_byte_done_r_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(rdlvl_last_byte_done),
        .Q(rdlvl_last_byte_done_r),
        .R(1'b0));
  (* srl_bus_name = "\u_mig_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/rdlvl_start_dly0_r_reg " *) 
  (* srl_name = "\u_mig_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/rdlvl_start_dly0_r_reg[13]_srl14 " *) 
  SRL16E \rdlvl_start_dly0_r_reg[13]_srl14 
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b1),
        .A3(1'b1),
        .CE(1'b1),
        .CLK(\rdlvl_start_dly0_r_reg[14]_0 ),
        .D(rdlvl_start_pre),
        .Q(\rdlvl_start_dly0_r_reg[13]_srl14_n_0 ));
  FDRE \rdlvl_start_dly0_r_reg[14] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\rdlvl_start_dly0_r_reg[13]_srl14_n_0 ),
        .Q(rdlvl_start_dly0_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFF00080000)) 
    rdlvl_start_pre_i_1
       (.I0(pi_dqs_found_done_r1_reg_0),
        .I1(\wrcal_reads[7]_i_5_n_0 ),
        .I2(\cnt_init_mr_r[0]_i_2_n_0 ),
        .I3(\init_state_r[3]_i_6_n_0 ),
        .I4(\init_state_r_reg_n_0_[4] ),
        .I5(rdlvl_start_pre),
        .O(rdlvl_start_pre_i_1_n_0));
  FDRE rdlvl_start_pre_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(rdlvl_start_pre_i_1_n_0),
        .Q(rdlvl_start_pre),
        .R(\en_cnt_div4.enable_wrlvl_cnt_reg[2]_0 ));
  LUT4 #(
    .INIT(16'hFB08)) 
    rdlvl_stg1_start_i_1
       (.I0(rdlvl_start_dly0_r),
        .I1(pi_dqs_found_done_r1_reg_0),
        .I2(rdlvl_stg1_start_i_2_n_0),
        .I3(rdlvl_stg1_start_reg_0),
        .O(rdlvl_stg1_start_i_1_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFDFFFFFFFF)) 
    rdlvl_stg1_start_i_2
       (.I0(\init_state_r_reg_n_0_[4] ),
        .I1(\init_state_r_reg_n_0_[5] ),
        .I2(init_state_r),
        .I3(\init_state_r_reg_n_0_[2] ),
        .I4(\init_state_r_reg_n_0_[3] ),
        .I5(\wrcal_reads[7]_i_5_n_0 ),
        .O(rdlvl_stg1_start_i_2_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFF00008000)) 
    rdlvl_stg1_start_int_i_1
       (.I0(pi_dqs_found_done_r1_reg_0),
        .I1(cnt_cmd_done_r),
        .I2(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ),
        .I3(\cnt_init_mr_r[0]_i_3_n_0 ),
        .I4(rdlvl_stg1_start_int_i_2_n_0),
        .I5(rdlvl_stg1_start_int),
        .O(rdlvl_stg1_start_int_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair482" *) 
  LUT2 #(
    .INIT(4'h7)) 
    rdlvl_stg1_start_int_i_2
       (.I0(\init_state_r_reg_n_0_[3] ),
        .I1(\init_state_r_reg_n_0_[2] ),
        .O(rdlvl_stg1_start_int_i_2_n_0));
  FDRE rdlvl_stg1_start_int_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(rdlvl_stg1_start_int_i_1_n_0),
        .Q(rdlvl_stg1_start_int),
        .R(\en_cnt_div4.enable_wrlvl_cnt_reg[2]_0 ));
  FDRE rdlvl_stg1_start_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(rdlvl_stg1_start_i_1_n_0),
        .Q(rdlvl_stg1_start_reg_0),
        .R(\victim_sel_reg[0]_0 ));
  LUT6 #(
    .INIT(64'h0000000055550100)) 
    read_calib_i_1
       (.I0(write_calib_reg_0),
        .I1(\wrcal_reads[7]_i_4_n_0 ),
        .I2(\wrcal_reads[7]_i_7_n_0 ),
        .I3(detect_pi_found_dqs_i_2_n_0),
        .I4(phy_read_calib),
        .I5(pi_calib_done),
        .O(read_calib_i_1_n_0));
  FDRE read_calib_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(read_calib_i_1_n_0),
        .Q(phy_read_calib),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair532" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \read_fifo.tail_r[0]_i_1 
       (.I0(init_complete_r1_timing_reg_0),
        .I1(\read_fifo.tail_r ),
        .O(\read_fifo.tail_r_reg[0] ));
  (* SOFT_HLUTNM = "soft_lutpair528" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \reg_ctrl_cnt_r[0]_i_1 
       (.I0(reg_ctrl_cnt_r_reg[0]),
        .O(p_0_in__3[0]));
  (* SOFT_HLUTNM = "soft_lutpair528" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \reg_ctrl_cnt_r[1]_i_1 
       (.I0(reg_ctrl_cnt_r_reg[1]),
        .I1(reg_ctrl_cnt_r_reg[0]),
        .O(p_0_in__3[1]));
  (* SOFT_HLUTNM = "soft_lutpair459" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \reg_ctrl_cnt_r[2]_i_1 
       (.I0(reg_ctrl_cnt_r_reg[2]),
        .I1(reg_ctrl_cnt_r_reg[0]),
        .I2(reg_ctrl_cnt_r_reg[1]),
        .O(p_0_in__3[2]));
  LUT6 #(
    .INIT(64'h0000000100000000)) 
    \reg_ctrl_cnt_r[3]_i_1 
       (.I0(\init_state_r_reg_n_0_[3] ),
        .I1(\init_state_r_reg_n_0_[2] ),
        .I2(\init_state_r_reg_n_0_[4] ),
        .I3(\init_state_r_reg_n_0_[5] ),
        .I4(init_state_r),
        .I5(\wrcal_reads[7]_i_5_n_0 ),
        .O(\reg_ctrl_cnt_r[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000400000000)) 
    \reg_ctrl_cnt_r[3]_i_2 
       (.I0(\init_state_r_reg_n_0_[2] ),
        .I1(\init_state_r_reg_n_0_[3] ),
        .I2(init_state_r),
        .I3(\init_state_r_reg_n_0_[5] ),
        .I4(prbs_rdlvl_start_i_2_n_0),
        .I5(\init_state_r_reg_n_0_[4] ),
        .O(reg_ctrl_cnt_r));
  (* SOFT_HLUTNM = "soft_lutpair459" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \reg_ctrl_cnt_r[3]_i_3 
       (.I0(reg_ctrl_cnt_r_reg[3]),
        .I1(reg_ctrl_cnt_r_reg[1]),
        .I2(reg_ctrl_cnt_r_reg[0]),
        .I3(reg_ctrl_cnt_r_reg[2]),
        .O(p_0_in__3[3]));
  FDRE \reg_ctrl_cnt_r_reg[0] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(reg_ctrl_cnt_r),
        .D(p_0_in__3[0]),
        .Q(reg_ctrl_cnt_r_reg[0]),
        .R(\reg_ctrl_cnt_r[3]_i_1_n_0 ));
  FDRE \reg_ctrl_cnt_r_reg[1] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(reg_ctrl_cnt_r),
        .D(p_0_in__3[1]),
        .Q(reg_ctrl_cnt_r_reg[1]),
        .R(\reg_ctrl_cnt_r[3]_i_1_n_0 ));
  FDRE \reg_ctrl_cnt_r_reg[2] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(reg_ctrl_cnt_r),
        .D(p_0_in__3[2]),
        .Q(reg_ctrl_cnt_r_reg[2]),
        .R(\reg_ctrl_cnt_r[3]_i_1_n_0 ));
  FDRE \reg_ctrl_cnt_r_reg[3] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(reg_ctrl_cnt_r),
        .D(p_0_in__3[3]),
        .Q(reg_ctrl_cnt_r_reg[3]),
        .R(\reg_ctrl_cnt_r[3]_i_1_n_0 ));
  FDRE reset_rd_addr_r1_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(reset_rd_addr0),
        .Q(reset_rd_addr_r1),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair426" *) 
  LUT5 #(
    .INIT(32'h55550455)) 
    \row_cnt_victim_rotate.complex_row_cnt[0]_i_1 
       (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] ),
        .I1(\row_cnt_victim_rotate.complex_row_cnt[4]_i_5_n_0 ),
        .I2(\one_rank.stg1_wr_done_reg_0 ),
        .I3(complex_sample_cnt_inc_r2),
        .I4(\row_cnt_victim_rotate.complex_row_cnt_reg[6]_0 ),
        .O(\row_cnt_victim_rotate.complex_row_cnt[0]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h8BB8)) 
    \row_cnt_victim_rotate.complex_row_cnt[1]_i_1 
       (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg[1]_0 ),
        .I1(\row_cnt_victim_rotate.complex_row_cnt[3]_i_2_n_0 ),
        .I2(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1] ),
        .I3(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] ),
        .O(\row_cnt_victim_rotate.complex_row_cnt[1]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h8BB8B8B8)) 
    \row_cnt_victim_rotate.complex_row_cnt[2]_i_1 
       (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg[2]_0 ),
        .I1(\row_cnt_victim_rotate.complex_row_cnt[3]_i_2_n_0 ),
        .I2(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2] ),
        .I3(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] ),
        .I4(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1] ),
        .O(\row_cnt_victim_rotate.complex_row_cnt[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h8BB8B8B8B8B8B8B8)) 
    \row_cnt_victim_rotate.complex_row_cnt[3]_i_1 
       (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg[3]_0 ),
        .I1(\row_cnt_victim_rotate.complex_row_cnt[3]_i_2_n_0 ),
        .I2(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3] ),
        .I3(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1] ),
        .I4(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] ),
        .I5(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2] ),
        .O(\row_cnt_victim_rotate.complex_row_cnt[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair426" *) 
  LUT4 #(
    .INIT(16'h4044)) 
    \row_cnt_victim_rotate.complex_row_cnt[3]_i_2 
       (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg[6]_0 ),
        .I1(complex_sample_cnt_inc_r2),
        .I2(\one_rank.stg1_wr_done_reg_0 ),
        .I3(\row_cnt_victim_rotate.complex_row_cnt[4]_i_5_n_0 ),
        .O(\row_cnt_victim_rotate.complex_row_cnt[3]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hEFEFEEEFAAAAAAAA)) 
    \row_cnt_victim_rotate.complex_row_cnt[4]_i_1 
       (.I0(\row_cnt_victim_rotate.complex_row_cnt[4]_i_4_n_0 ),
        .I1(reset_rd_addr_r1),
        .I2(\row_cnt_victim_rotate.complex_row_cnt[4]_i_5_n_0 ),
        .I3(complex_sample_cnt_inc_r2),
        .I4(\row_cnt_victim_rotate.complex_row_cnt_reg[6]_0 ),
        .I5(\row_cnt_victim_rotate.complex_row_cnt[4]_i_6_n_0 ),
        .O(\row_cnt_victim_rotate.complex_row_cnt[4]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'h0E)) 
    \row_cnt_victim_rotate.complex_row_cnt[4]_i_2 
       (.I0(\row_cnt_victim_rotate.complex_row_cnt[4]_i_5_n_0 ),
        .I1(\one_rank.stg1_wr_done_reg_0 ),
        .I2(\row_cnt_victim_rotate.complex_row_cnt[4]_i_7_n_0 ),
        .O(complex_row_cnt));
  LUT6 #(
    .INIT(64'h1555555540000000)) 
    \row_cnt_victim_rotate.complex_row_cnt[4]_i_3 
       (.I0(\row_cnt_victim_rotate.complex_row_cnt[4]_i_8_n_0 ),
        .I1(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3] ),
        .I2(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1] ),
        .I3(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] ),
        .I4(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2] ),
        .I5(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4] ),
        .O(\row_cnt_victim_rotate.complex_row_cnt[4]_i_3_n_0 ));
  LUT3 #(
    .INIT(8'hFB)) 
    \row_cnt_victim_rotate.complex_row_cnt[4]_i_4 
       (.I0(p_81_in),
        .I1(rdlvl_stg1_done_r1),
        .I2(complex_oclkdelay_calib_done_r1_reg_0),
        .O(\row_cnt_victim_rotate.complex_row_cnt[4]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'h00000001)) 
    \row_cnt_victim_rotate.complex_row_cnt[4]_i_5 
       (.I0(\row_cnt_victim_rotate.complex_row_cnt[5]_i_2_n_0 ),
        .I1(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6] ),
        .I2(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5] ),
        .I3(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4] ),
        .I4(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[7] ),
        .O(\row_cnt_victim_rotate.complex_row_cnt[4]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \row_cnt_victim_rotate.complex_row_cnt[4]_i_6 
       (.I0(\one_rank.stg1_wr_done_reg_0 ),
        .I1(\row_cnt_victim_rotate.complex_row_cnt[4]_i_7_n_0 ),
        .O(\row_cnt_victim_rotate.complex_row_cnt[4]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h0000000100010001)) 
    \row_cnt_victim_rotate.complex_row_cnt[4]_i_7 
       (.I0(reset_rd_addr_r1),
        .I1(\row_cnt_victim_rotate.complex_row_cnt_reg[6]_0 ),
        .I2(wr_victim_inc),
        .I3(complex_sample_cnt_inc_r2),
        .I4(\complex_row_cnt_ocal[3]_i_6_n_0 ),
        .I5(\row_cnt_victim_rotate.complex_row_cnt[4]_i_9_n_0 ),
        .O(\row_cnt_victim_rotate.complex_row_cnt[4]_i_7_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \row_cnt_victim_rotate.complex_row_cnt[4]_i_8 
       (.I0(complex_sample_cnt_inc_r2),
        .I1(\row_cnt_victim_rotate.complex_row_cnt_reg[6]_0 ),
        .O(\row_cnt_victim_rotate.complex_row_cnt[4]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'h0000000004000000)) 
    \row_cnt_victim_rotate.complex_row_cnt[4]_i_9 
       (.I0(\stg1_wr_rd_cnt_reg_n_0_[3] ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[1] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[0] ),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[4] ),
        .I4(\stg1_wr_rd_cnt_reg_n_0_[2] ),
        .I5(wr_victim_inc_i_3_n_0),
        .O(\row_cnt_victim_rotate.complex_row_cnt[4]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'h0000000022226AAA)) 
    \row_cnt_victim_rotate.complex_row_cnt[5]_i_1 
       (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5] ),
        .I1(complex_row_cnt),
        .I2(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4] ),
        .I3(\row_cnt_victim_rotate.complex_row_cnt[5]_i_2_n_0 ),
        .I4(\row_cnt_victim_rotate.complex_row_cnt[4]_i_8_n_0 ),
        .I5(\row_cnt_victim_rotate.complex_row_cnt[7]_i_3_n_0 ),
        .O(\row_cnt_victim_rotate.complex_row_cnt[5]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h8000)) 
    \row_cnt_victim_rotate.complex_row_cnt[5]_i_2 
       (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3] ),
        .I1(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1] ),
        .I2(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] ),
        .I3(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2] ),
        .O(\row_cnt_victim_rotate.complex_row_cnt[5]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h000000006626AA2A)) 
    \row_cnt_victim_rotate.complex_row_cnt[6]_i_1 
       (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6] ),
        .I1(complex_row_cnt),
        .I2(complex_sample_cnt_inc_r2),
        .I3(\row_cnt_victim_rotate.complex_row_cnt_reg[6]_0 ),
        .I4(\row_cnt_victim_rotate.complex_row_cnt[7]_i_2_n_0 ),
        .I5(\row_cnt_victim_rotate.complex_row_cnt[7]_i_3_n_0 ),
        .O(\row_cnt_victim_rotate.complex_row_cnt[6]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000022226AAA)) 
    \row_cnt_victim_rotate.complex_row_cnt[7]_i_1 
       (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[7] ),
        .I1(complex_row_cnt),
        .I2(\row_cnt_victim_rotate.complex_row_cnt[7]_i_2_n_0 ),
        .I3(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6] ),
        .I4(\row_cnt_victim_rotate.complex_row_cnt[4]_i_8_n_0 ),
        .I5(\row_cnt_victim_rotate.complex_row_cnt[7]_i_3_n_0 ),
        .O(\row_cnt_victim_rotate.complex_row_cnt[7]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \row_cnt_victim_rotate.complex_row_cnt[7]_i_2 
       (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4] ),
        .I1(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3] ),
        .I2(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1] ),
        .I3(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] ),
        .I4(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2] ),
        .I5(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5] ),
        .O(\row_cnt_victim_rotate.complex_row_cnt[7]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFF5D0000)) 
    \row_cnt_victim_rotate.complex_row_cnt[7]_i_3 
       (.I0(\row_cnt_victim_rotate.complex_row_cnt[4]_i_5_n_0 ),
        .I1(complex_sample_cnt_inc_r2),
        .I2(\row_cnt_victim_rotate.complex_row_cnt_reg[6]_0 ),
        .I3(reset_rd_addr_r1),
        .I4(\row_cnt_victim_rotate.complex_row_cnt[4]_i_6_n_0 ),
        .I5(\row_cnt_victim_rotate.complex_row_cnt[4]_i_4_n_0 ),
        .O(\row_cnt_victim_rotate.complex_row_cnt[7]_i_3_n_0 ));
  FDRE \row_cnt_victim_rotate.complex_row_cnt_reg[0] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(complex_row_cnt),
        .D(\row_cnt_victim_rotate.complex_row_cnt[0]_i_1_n_0 ),
        .Q(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] ),
        .R(\row_cnt_victim_rotate.complex_row_cnt[4]_i_1_n_0 ));
  FDRE \row_cnt_victim_rotate.complex_row_cnt_reg[1] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(complex_row_cnt),
        .D(\row_cnt_victim_rotate.complex_row_cnt[1]_i_1_n_0 ),
        .Q(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1] ),
        .R(\row_cnt_victim_rotate.complex_row_cnt[4]_i_1_n_0 ));
  FDRE \row_cnt_victim_rotate.complex_row_cnt_reg[2] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(complex_row_cnt),
        .D(\row_cnt_victim_rotate.complex_row_cnt[2]_i_1_n_0 ),
        .Q(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2] ),
        .R(\row_cnt_victim_rotate.complex_row_cnt[4]_i_1_n_0 ));
  FDRE \row_cnt_victim_rotate.complex_row_cnt_reg[3] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(complex_row_cnt),
        .D(\row_cnt_victim_rotate.complex_row_cnt[3]_i_1_n_0 ),
        .Q(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3] ),
        .R(\row_cnt_victim_rotate.complex_row_cnt[4]_i_1_n_0 ));
  FDRE \row_cnt_victim_rotate.complex_row_cnt_reg[4] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(complex_row_cnt),
        .D(\row_cnt_victim_rotate.complex_row_cnt[4]_i_3_n_0 ),
        .Q(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4] ),
        .R(\row_cnt_victim_rotate.complex_row_cnt[4]_i_1_n_0 ));
  FDRE \row_cnt_victim_rotate.complex_row_cnt_reg[5] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\row_cnt_victim_rotate.complex_row_cnt[5]_i_1_n_0 ),
        .Q(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \row_cnt_victim_rotate.complex_row_cnt_reg[6] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\row_cnt_victim_rotate.complex_row_cnt[6]_i_1_n_0 ),
        .Q(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \row_cnt_victim_rotate.complex_row_cnt_reg[7] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\row_cnt_victim_rotate.complex_row_cnt[7]_i_1_n_0 ),
        .Q(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[7] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair461" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \samples_cnt_r[11]_i_1 
       (.I0(complex_sample_cnt_inc),
        .I1(\samples_cnt_r_reg[11] ),
        .O(E));
  (* SOFT_HLUTNM = "soft_lutpair470" *) 
  LUT3 #(
    .INIT(8'hBA)) 
    \stg1_wr_rd_cnt[0]_i_1 
       (.I0(\stg1_wr_rd_cnt[6]_i_2_n_0 ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[0] ),
        .I2(\stg1_wr_rd_cnt[8]_i_3_n_0 ),
        .O(\stg1_wr_rd_cnt[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0D00000D0D0D0D0D)) 
    \stg1_wr_rd_cnt[1]_i_1 
       (.I0(stg1_wr_done),
        .I1(prbs_rdlvl_start_reg_2),
        .I2(write_calib_reg_0),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[1] ),
        .I4(\stg1_wr_rd_cnt_reg_n_0_[0] ),
        .I5(\stg1_wr_rd_cnt[4]_i_3_n_0 ),
        .O(\stg1_wr_rd_cnt[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h1000000000000000)) 
    \stg1_wr_rd_cnt[1]_i_2 
       (.I0(\init_state_r[3]_i_6_n_0 ),
        .I1(\init_state_r_reg_n_0_[4] ),
        .I2(\init_state_r_reg_n_0_[1] ),
        .I3(\init_state_r_reg_n_0_[3] ),
        .I4(Q),
        .I5(\init_state_r_reg_n_0_[2] ),
        .O(stg1_wr_done));
  (* SOFT_HLUTNM = "soft_lutpair475" *) 
  LUT4 #(
    .INIT(16'hFD57)) 
    \stg1_wr_rd_cnt[2]_i_1 
       (.I0(\stg1_wr_rd_cnt[8]_i_3_n_0 ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[1] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[0] ),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[2] ),
        .O(\stg1_wr_rd_cnt[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h008AAA8AAA8A008A)) 
    \stg1_wr_rd_cnt[3]_i_1 
       (.I0(\stg1_wr_rd_cnt_reg[3]_0 ),
        .I1(complex_oclkdelay_calib_done_r1_reg_0),
        .I2(\stg1_wr_rd_cnt[3]_i_2_n_0 ),
        .I3(\stg1_wr_rd_cnt[4]_i_3_n_0 ),
        .I4(\stg1_wr_rd_cnt[5]_i_2_n_0 ),
        .I5(\stg1_wr_rd_cnt_reg_n_0_[3] ),
        .O(\stg1_wr_rd_cnt[3]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00002F00)) 
    \stg1_wr_rd_cnt[3]_i_2 
       (.I0(complex_row0_rd_done),
        .I1(complex_row1_rd_done),
        .I2(complex_row1_wr_done),
        .I3(complex_row0_wr_done),
        .I4(wr_victim_inc),
        .O(\stg1_wr_rd_cnt[3]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h8288AAAA)) 
    \stg1_wr_rd_cnt[4]_i_1 
       (.I0(\stg1_wr_rd_cnt_reg[3]_0 ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[4] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[3] ),
        .I3(\stg1_wr_rd_cnt[5]_i_2_n_0 ),
        .I4(\stg1_wr_rd_cnt[4]_i_3_n_0 ),
        .O(\stg1_wr_rd_cnt[4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00020202)) 
    \stg1_wr_rd_cnt[4]_i_3 
       (.I0(complex_sample_cnt_inc_i_2_n_0),
        .I1(rdlvl_last_byte_done),
        .I2(complex_ocal_reset_rd_addr_i_3_n_0),
        .I3(prech_req_posedge_r_reg_1),
        .I4(\stg1_wr_rd_cnt[4]_i_4_n_0 ),
        .O(\stg1_wr_rd_cnt[4]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000004)) 
    \stg1_wr_rd_cnt[4]_i_4 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(Q),
        .I2(\init_state_r_reg_n_0_[4] ),
        .I3(\init_state_r_reg_n_0_[5] ),
        .I4(init_state_r),
        .I5(rdlvl_stg1_start_int_i_2_n_0),
        .O(\stg1_wr_rd_cnt[4]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hEEEBEEEEAAAAAAAA)) 
    \stg1_wr_rd_cnt[5]_i_1 
       (.I0(\stg1_wr_rd_cnt[6]_i_2_n_0 ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[5] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[3] ),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[4] ),
        .I4(\stg1_wr_rd_cnt[5]_i_2_n_0 ),
        .I5(\stg1_wr_rd_cnt[8]_i_3_n_0 ),
        .O(\stg1_wr_rd_cnt[5]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'h01)) 
    \stg1_wr_rd_cnt[5]_i_2 
       (.I0(\stg1_wr_rd_cnt_reg_n_0_[2] ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[0] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[1] ),
        .O(\stg1_wr_rd_cnt[5]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair470" *) 
  LUT4 #(
    .INIT(16'hFF60)) 
    \stg1_wr_rd_cnt[6]_i_1 
       (.I0(\stg1_wr_rd_cnt_reg_n_0_[6] ),
        .I1(\stg1_wr_rd_cnt[8]_i_6_n_0 ),
        .I2(\stg1_wr_rd_cnt[8]_i_3_n_0 ),
        .I3(\stg1_wr_rd_cnt[6]_i_2_n_0 ),
        .O(\stg1_wr_rd_cnt[6]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair389" *) 
  LUT5 #(
    .INIT(32'h00001011)) 
    \stg1_wr_rd_cnt[6]_i_2 
       (.I0(\stg1_wr_rd_cnt[3]_i_2_n_0 ),
        .I1(write_calib_reg_0),
        .I2(prbs_rdlvl_start_reg_2),
        .I3(stg1_wr_done),
        .I4(\stg1_wr_rd_cnt[4]_i_3_n_0 ),
        .O(\stg1_wr_rd_cnt[6]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair409" *) 
  LUT4 #(
    .INIT(16'hA208)) 
    \stg1_wr_rd_cnt[7]_i_1 
       (.I0(\stg1_wr_rd_cnt[8]_i_3_n_0 ),
        .I1(\stg1_wr_rd_cnt[8]_i_6_n_0 ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[6] ),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[7] ),
        .O(\stg1_wr_rd_cnt[7]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFFD5)) 
    \stg1_wr_rd_cnt[8]_i_1 
       (.I0(\stg1_wr_rd_cnt[8]_i_3_n_0 ),
        .I1(\stg1_wr_rd_cnt[8]_i_4_n_0 ),
        .I2(prbs_rdlvl_start_reg_2),
        .I3(\stg1_wr_rd_cnt[8]_i_5_n_0 ),
        .O(\stg1_wr_rd_cnt[8]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair409" *) 
  LUT5 #(
    .INIT(32'hA8AA0200)) 
    \stg1_wr_rd_cnt[8]_i_2 
       (.I0(\stg1_wr_rd_cnt[8]_i_3_n_0 ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[7] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[6] ),
        .I3(\stg1_wr_rd_cnt[8]_i_6_n_0 ),
        .I4(\stg1_wr_rd_cnt_reg_n_0_[8] ),
        .O(\stg1_wr_rd_cnt[8]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair389" *) 
  LUT4 #(
    .INIT(16'h00A2)) 
    \stg1_wr_rd_cnt[8]_i_3 
       (.I0(\stg1_wr_rd_cnt[4]_i_3_n_0 ),
        .I1(stg1_wr_done),
        .I2(prbs_rdlvl_start_reg_2),
        .I3(write_calib_reg_0),
        .O(\stg1_wr_rd_cnt[8]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0000080000000000)) 
    \stg1_wr_rd_cnt[8]_i_4 
       (.I0(\wrcal_reads[7]_i_5_n_0 ),
        .I1(\init_state_r_reg_n_0_[5] ),
        .I2(init_state_r),
        .I3(\init_state_r_reg_n_0_[4] ),
        .I4(\init_state_r_reg_n_0_[2] ),
        .I5(\init_state_r_reg_n_0_[3] ),
        .O(\stg1_wr_rd_cnt[8]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h0100000000000000)) 
    \stg1_wr_rd_cnt[8]_i_5 
       (.I0(init_state_r),
        .I1(\init_state_r_reg_n_0_[5] ),
        .I2(\init_state_r_reg_n_0_[4] ),
        .I3(\init_state_r_reg_n_0_[3] ),
        .I4(\init_state_r_reg_n_0_[2] ),
        .I5(detect_pi_found_dqs_i_2_n_0),
        .O(\stg1_wr_rd_cnt[8]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \stg1_wr_rd_cnt[8]_i_6 
       (.I0(\stg1_wr_rd_cnt_reg_n_0_[4] ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[5] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[3] ),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[2] ),
        .I4(\stg1_wr_rd_cnt_reg_n_0_[0] ),
        .I5(\stg1_wr_rd_cnt_reg_n_0_[1] ),
        .O(\stg1_wr_rd_cnt[8]_i_6_n_0 ));
  FDRE \stg1_wr_rd_cnt_reg[0] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\stg1_wr_rd_cnt[8]_i_1_n_0 ),
        .D(\stg1_wr_rd_cnt[0]_i_1_n_0 ),
        .Q(\stg1_wr_rd_cnt_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \stg1_wr_rd_cnt_reg[1] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\stg1_wr_rd_cnt[8]_i_1_n_0 ),
        .D(\stg1_wr_rd_cnt[1]_i_1_n_0 ),
        .Q(\stg1_wr_rd_cnt_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \stg1_wr_rd_cnt_reg[2] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\stg1_wr_rd_cnt[8]_i_1_n_0 ),
        .D(\stg1_wr_rd_cnt[2]_i_1_n_0 ),
        .Q(\stg1_wr_rd_cnt_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \stg1_wr_rd_cnt_reg[3] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\stg1_wr_rd_cnt[8]_i_1_n_0 ),
        .D(\stg1_wr_rd_cnt[3]_i_1_n_0 ),
        .Q(\stg1_wr_rd_cnt_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \stg1_wr_rd_cnt_reg[4] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\stg1_wr_rd_cnt[8]_i_1_n_0 ),
        .D(\stg1_wr_rd_cnt[4]_i_1_n_0 ),
        .Q(\stg1_wr_rd_cnt_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \stg1_wr_rd_cnt_reg[5] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\stg1_wr_rd_cnt[8]_i_1_n_0 ),
        .D(\stg1_wr_rd_cnt[5]_i_1_n_0 ),
        .Q(\stg1_wr_rd_cnt_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \stg1_wr_rd_cnt_reg[6] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\stg1_wr_rd_cnt[8]_i_1_n_0 ),
        .D(\stg1_wr_rd_cnt[6]_i_1_n_0 ),
        .Q(\stg1_wr_rd_cnt_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \stg1_wr_rd_cnt_reg[7] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\stg1_wr_rd_cnt[8]_i_1_n_0 ),
        .D(\stg1_wr_rd_cnt[7]_i_1_n_0 ),
        .Q(\stg1_wr_rd_cnt_reg_n_0_[7] ),
        .R(1'b0));
  FDRE \stg1_wr_rd_cnt_reg[8] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\stg1_wr_rd_cnt[8]_i_1_n_0 ),
        .D(\stg1_wr_rd_cnt[8]_i_2_n_0 ),
        .Q(\stg1_wr_rd_cnt_reg_n_0_[8] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair491" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \victim_sel[0]_i_1 
       (.I0(\victim_sel[0]_i_2_n_0 ),
        .I1(\victim_sel[2]_i_3_n_0 ),
        .I2(\victim_sel_reg_n_0_[0] ),
        .O(\victim_sel[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h3A3F0A0F3A300A00)) 
    \victim_sel[0]_i_2 
       (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg[1]_0 ),
        .I1(complex_wr_done),
        .I2(complex_oclkdelay_calib_done_r1_reg_0),
        .I3(\one_rank.stg1_wr_done_reg_0 ),
        .I4(wr_victim_sel_ocal[0]),
        .I5(wr_victim_sel[0]),
        .O(\victim_sel[0]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair492" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \victim_sel[1]_i_1 
       (.I0(\victim_sel[1]_i_2_n_0 ),
        .I1(\victim_sel[2]_i_3_n_0 ),
        .I2(\victim_sel_reg_n_0_[1] ),
        .O(\victim_sel[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h3A3F0A0F3A300A00)) 
    \victim_sel[1]_i_2 
       (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg[2]_0 ),
        .I1(complex_wr_done),
        .I2(complex_oclkdelay_calib_done_r1_reg_0),
        .I3(\one_rank.stg1_wr_done_reg_0 ),
        .I4(wr_victim_sel_ocal[1]),
        .I5(wr_victim_sel[1]),
        .O(\victim_sel[1]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair491" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \victim_sel[2]_i_1 
       (.I0(\victim_sel[2]_i_2_n_0 ),
        .I1(\victim_sel[2]_i_3_n_0 ),
        .I2(\victim_sel_reg_n_0_[2] ),
        .O(\victim_sel[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h3A3F0A0F3A300A00)) 
    \victim_sel[2]_i_2 
       (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg[3]_0 ),
        .I1(complex_wr_done),
        .I2(complex_oclkdelay_calib_done_r1_reg_0),
        .I3(\one_rank.stg1_wr_done_reg_0 ),
        .I4(wr_victim_sel_ocal[2]),
        .I5(wr_victim_sel[2]),
        .O(\victim_sel[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFBABF)) 
    \victim_sel[2]_i_3 
       (.I0(\victim_sel[2]_i_4_n_0 ),
        .I1(complex_wr_done),
        .I2(complex_oclkdelay_calib_done_r1_reg_0),
        .I3(\one_rank.stg1_wr_done_reg_0 ),
        .I4(reset_rd_addr),
        .I5(complex_ocal_reset_rd_addr),
        .O(\victim_sel[2]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0000200000000000)) 
    \victim_sel[2]_i_4 
       (.I0(detect_pi_found_dqs_i_2_n_0),
        .I1(\init_state_r_reg_n_0_[3] ),
        .I2(\init_state_r_reg_n_0_[2] ),
        .I3(\init_state_r_reg_n_0_[5] ),
        .I4(init_state_r),
        .I5(\init_state_r_reg_n_0_[4] ),
        .O(\victim_sel[2]_i_4_n_0 ));
  FDRE \victim_sel_reg[0] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\victim_sel[0]_i_1_n_0 ),
        .Q(\victim_sel_reg_n_0_[0] ),
        .R(\victim_sel_reg[0]_0 ));
  FDRE \victim_sel_reg[1] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\victim_sel[1]_i_1_n_0 ),
        .Q(\victim_sel_reg_n_0_[1] ),
        .R(\victim_sel_reg[0]_0 ));
  FDRE \victim_sel_reg[2] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\victim_sel[2]_i_1_n_0 ),
        .Q(\victim_sel_reg_n_0_[2] ),
        .R(\victim_sel_reg[0]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair492" *) 
  LUT3 #(
    .INIT(8'h01)) 
    \victim_sel_rotate.sel[56]_i_1 
       (.I0(\victim_sel_reg_n_0_[2] ),
        .I1(\victim_sel_reg_n_0_[0] ),
        .I2(\victim_sel_reg_n_0_[1] ),
        .O(D[0]));
  (* SOFT_HLUTNM = "soft_lutpair504" *) 
  LUT3 #(
    .INIT(8'h02)) 
    \victim_sel_rotate.sel[57]_i_1 
       (.I0(\victim_sel_reg_n_0_[0] ),
        .I1(\victim_sel_reg_n_0_[2] ),
        .I2(\victim_sel_reg_n_0_[1] ),
        .O(D[1]));
  (* SOFT_HLUTNM = "soft_lutpair505" *) 
  LUT3 #(
    .INIT(8'h02)) 
    \victim_sel_rotate.sel[58]_i_1 
       (.I0(\victim_sel_reg_n_0_[1] ),
        .I1(\victim_sel_reg_n_0_[2] ),
        .I2(\victim_sel_reg_n_0_[0] ),
        .O(D[2]));
  LUT3 #(
    .INIT(8'h40)) 
    \victim_sel_rotate.sel[59]_i_1 
       (.I0(\victim_sel_reg_n_0_[2] ),
        .I1(\victim_sel_reg_n_0_[0] ),
        .I2(\victim_sel_reg_n_0_[1] ),
        .O(D[3]));
  (* SOFT_HLUTNM = "soft_lutpair505" *) 
  LUT3 #(
    .INIT(8'h02)) 
    \victim_sel_rotate.sel[60]_i_1 
       (.I0(\victim_sel_reg_n_0_[2] ),
        .I1(\victim_sel_reg_n_0_[0] ),
        .I2(\victim_sel_reg_n_0_[1] ),
        .O(D[4]));
  (* SOFT_HLUTNM = "soft_lutpair503" *) 
  LUT3 #(
    .INIT(8'h08)) 
    \victim_sel_rotate.sel[61]_i_1 
       (.I0(\victim_sel_reg_n_0_[0] ),
        .I1(\victim_sel_reg_n_0_[2] ),
        .I2(\victim_sel_reg_n_0_[1] ),
        .O(D[5]));
  (* SOFT_HLUTNM = "soft_lutpair504" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \victim_sel_rotate.sel[62]_i_1 
       (.I0(\victim_sel_reg_n_0_[0] ),
        .I1(\victim_sel_reg_n_0_[2] ),
        .I2(\victim_sel_reg_n_0_[1] ),
        .O(D[6]));
  (* SOFT_HLUTNM = "soft_lutpair503" *) 
  LUT3 #(
    .INIT(8'h80)) 
    \victim_sel_rotate.sel[63]_i_1 
       (.I0(\victim_sel_reg_n_0_[1] ),
        .I1(\victim_sel_reg_n_0_[0] ),
        .I2(\victim_sel_reg_n_0_[2] ),
        .O(D[7]));
  FDRE wl_sm_start_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(wr_level_dqs_asrt_r1),
        .Q(wl_sm_start),
        .R(\en_cnt_div4.enable_wrlvl_cnt_reg[2]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair454" *) 
  LUT4 #(
    .INIT(16'h00AE)) 
    \wr_done_victim_rotate.complex_row0_wr_done_i_1 
       (.I0(complex_row0_wr_done),
        .I1(rdlvl_stg1_done_r1),
        .I2(wr_victim_inc_i_2_n_0),
        .I3(complex_row0_wr_done0),
        .O(\wr_done_victim_rotate.complex_row0_wr_done_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF0011F011)) 
    \wr_done_victim_rotate.complex_row0_wr_done_i_2 
       (.I0(\row_cnt_victim_rotate.complex_row_cnt[5]_i_2_n_0 ),
        .I1(\wr_victim_sel[2]_i_3_n_0 ),
        .I2(wr_victim_inc),
        .I3(complex_oclkdelay_calib_done_r1_reg_0),
        .I4(\complex_row_cnt_ocal[3]_i_4_n_0 ),
        .I5(\wr_done_victim_rotate.complex_row0_wr_done_i_3_n_0 ),
        .O(complex_row0_wr_done0));
  (* SOFT_HLUTNM = "soft_lutpair391" *) 
  LUT3 #(
    .INIT(8'hFE)) 
    \wr_done_victim_rotate.complex_row0_wr_done_i_3 
       (.I0(complex_byte_rd_done),
        .I1(prbs_rdlvl_done_pulse_reg_0),
        .I2(write_calib_reg_0),
        .O(\wr_done_victim_rotate.complex_row0_wr_done_i_3_n_0 ));
  FDRE \wr_done_victim_rotate.complex_row0_wr_done_reg 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\wr_done_victim_rotate.complex_row0_wr_done_i_1_n_0 ),
        .Q(complex_row0_wr_done),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair454" *) 
  LUT4 #(
    .INIT(16'h00AE)) 
    \wr_done_victim_rotate.complex_row1_wr_done_i_1 
       (.I0(complex_row1_wr_done),
        .I1(complex_row0_wr_done),
        .I2(wr_victim_inc_i_2_n_0),
        .I3(complex_row0_wr_done0),
        .O(\wr_done_victim_rotate.complex_row1_wr_done_i_1_n_0 ));
  FDRE \wr_done_victim_rotate.complex_row1_wr_done_reg 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\wr_done_victim_rotate.complex_row1_wr_done_i_1_n_0 ),
        .Q(complex_row1_wr_done),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h00A8)) 
    wr_level_dqs_asrt_i_1
       (.I0(\en_cnt_div4.wrlvl_odt_i_2_n_0 ),
        .I1(wrlvl_active_r1),
        .I2(wr_level_dqs_asrt),
        .I3(write_calib_reg_0),
        .O(wr_level_dqs_asrt_i_1_n_0));
  FDRE wr_level_dqs_asrt_r1_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(wr_level_dqs_asrt),
        .Q(wr_level_dqs_asrt_r1),
        .R(1'b0));
  FDRE wr_level_dqs_asrt_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(wr_level_dqs_asrt_i_1_n_0),
        .Q(wr_level_dqs_asrt),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h0000EA00)) 
    wr_lvl_start_i_1
       (.I0(wr_lvl_start_reg_0),
        .I1(dqs_asrt_cnt[0]),
        .I2(dqs_asrt_cnt[1]),
        .I3(wrlvl_active),
        .I4(write_calib_reg_0),
        .O(wr_lvl_start_i_1_n_0));
  FDRE wr_lvl_start_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(wr_lvl_start_i_1_n_0),
        .Q(wr_lvl_start_reg_0),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair493" *) 
  LUT2 #(
    .INIT(4'hE)) 
    wr_ptr0_i_1
       (.I0(phy_ctl_wr_i1_reg),
        .I1(calib_cmd_wren),
        .O(phy_cmd_wr_en));
  (* SOFT_HLUTNM = "soft_lutpair493" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \wr_ptr[3]_i_3 
       (.I0(mc_wrdata_en),
        .I1(phy_ctl_wr_i1_reg),
        .I2(calib_wrdata_en),
        .O(phy_data_wr_en));
  (* SOFT_HLUTNM = "soft_lutpair494" *) 
  LUT3 #(
    .INIT(8'h04)) 
    wr_victim_inc_i_1
       (.I0(wr_victim_inc_i_2_n_0),
        .I1(complex_row0_wr_done),
        .I2(\one_rank.stg1_wr_done_reg_0 ),
        .O(wr_victim_inc0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFEF)) 
    wr_victim_inc_i_2
       (.I0(wr_victim_inc_i_3_n_0),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[0] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[1] ),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[3] ),
        .I4(\stg1_wr_rd_cnt_reg_n_0_[4] ),
        .I5(\stg1_wr_rd_cnt_reg_n_0_[2] ),
        .O(wr_victim_inc_i_2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair453" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    wr_victim_inc_i_3
       (.I0(\stg1_wr_rd_cnt_reg_n_0_[5] ),
        .I1(\stg1_wr_rd_cnt_reg_n_0_[7] ),
        .I2(\stg1_wr_rd_cnt_reg_n_0_[8] ),
        .I3(\stg1_wr_rd_cnt_reg_n_0_[6] ),
        .O(wr_victim_inc_i_3_n_0));
  FDRE wr_victim_inc_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(wr_victim_inc0),
        .Q(wr_victim_inc),
        .R(\en_cnt_div4.enable_wrlvl_cnt_reg[2]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair418" *) 
  LUT4 #(
    .INIT(16'h006A)) 
    \wr_victim_sel[0]_i_1 
       (.I0(wr_victim_sel[0]),
        .I1(wr_victim_inc),
        .I2(rdlvl_stg1_done_r1),
        .I3(p_81_in),
        .O(\wr_victim_sel[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair418" *) 
  LUT5 #(
    .INIT(32'h00006AAA)) 
    \wr_victim_sel[1]_i_1 
       (.I0(wr_victim_sel[1]),
        .I1(wr_victim_inc),
        .I2(rdlvl_stg1_done_r1),
        .I3(wr_victim_sel[0]),
        .I4(p_81_in),
        .O(\wr_victim_sel[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h000000006AAAAAAA)) 
    \wr_victim_sel[2]_i_1 
       (.I0(wr_victim_sel[2]),
        .I1(wr_victim_inc),
        .I2(rdlvl_stg1_done_r1),
        .I3(wr_victim_sel[1]),
        .I4(wr_victim_sel[0]),
        .I5(p_81_in),
        .O(\wr_victim_sel[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hBAAAAAAAAAAAAAAA)) 
    \wr_victim_sel[2]_i_2 
       (.I0(write_calib_reg_0),
        .I1(\wr_victim_sel[2]_i_3_n_0 ),
        .I2(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[3] ),
        .I3(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[1] ),
        .I4(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[0] ),
        .I5(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[2] ),
        .O(p_81_in));
  LUT5 #(
    .INIT(32'hFFFEFFFF)) 
    \wr_victim_sel[2]_i_3 
       (.I0(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[6] ),
        .I1(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[5] ),
        .I2(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[4] ),
        .I3(\row_cnt_victim_rotate.complex_row_cnt_reg_n_0_[7] ),
        .I4(wr_victim_inc),
        .O(\wr_victim_sel[2]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair441" *) 
  LUT4 #(
    .INIT(16'h006A)) 
    \wr_victim_sel_ocal[0]_i_1 
       (.I0(wr_victim_sel_ocal[0]),
        .I1(wr_victim_inc),
        .I2(complex_oclkdelay_calib_done_r1_reg_0),
        .I3(\wr_victim_sel_ocal[2]_i_2_n_0 ),
        .O(\wr_victim_sel_ocal[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair441" *) 
  LUT5 #(
    .INIT(32'h00006AAA)) 
    \wr_victim_sel_ocal[1]_i_1 
       (.I0(wr_victim_sel_ocal[1]),
        .I1(wr_victim_inc),
        .I2(complex_oclkdelay_calib_done_r1_reg_0),
        .I3(wr_victim_sel_ocal[0]),
        .I4(\wr_victim_sel_ocal[2]_i_2_n_0 ),
        .O(\wr_victim_sel_ocal[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h000000006AAAAAAA)) 
    \wr_victim_sel_ocal[2]_i_1 
       (.I0(wr_victim_sel_ocal[2]),
        .I1(wr_victim_inc),
        .I2(complex_oclkdelay_calib_done_r1_reg_0),
        .I3(wr_victim_sel_ocal[1]),
        .I4(wr_victim_sel_ocal[0]),
        .I5(\wr_victim_sel_ocal[2]_i_2_n_0 ),
        .O(\wr_victim_sel_ocal[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hEAAAAAAAAAAAAAAA)) 
    \wr_victim_sel_ocal[2]_i_2 
       (.I0(write_calib_reg_0),
        .I1(wr_victim_inc),
        .I2(complex_row_cnt_ocal_reg[3]),
        .I3(complex_row_cnt_ocal_reg[1]),
        .I4(complex_row_cnt_ocal_reg[0]),
        .I5(complex_row_cnt_ocal_reg[2]),
        .O(\wr_victim_sel_ocal[2]_i_2_n_0 ));
  FDRE \wr_victim_sel_ocal_reg[0] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\wr_victim_sel_ocal[0]_i_1_n_0 ),
        .Q(wr_victim_sel_ocal[0]),
        .R(1'b0));
  FDRE \wr_victim_sel_ocal_reg[1] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\wr_victim_sel_ocal[1]_i_1_n_0 ),
        .Q(wr_victim_sel_ocal[1]),
        .R(1'b0));
  FDRE \wr_victim_sel_ocal_reg[2] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\wr_victim_sel_ocal[2]_i_1_n_0 ),
        .Q(wr_victim_sel_ocal[2]),
        .R(1'b0));
  FDRE \wr_victim_sel_reg[0] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\wr_victim_sel[0]_i_1_n_0 ),
        .Q(wr_victim_sel[0]),
        .R(1'b0));
  FDRE \wr_victim_sel_reg[1] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\wr_victim_sel[1]_i_1_n_0 ),
        .Q(wr_victim_sel[1]),
        .R(1'b0));
  FDRE \wr_victim_sel_reg[2] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\wr_victim_sel[2]_i_1_n_0 ),
        .Q(wr_victim_sel[2]),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hFFFF4000)) 
    wrcal_final_chk_i_1
       (.I0(wrcal_final_chk_i_2_n_0),
        .I1(\init_state_r[4]_i_1_n_0 ),
        .I2(\init_state_r[0]_i_1_n_0 ),
        .I3(\init_state_r[3]_i_1_n_0 ),
        .I4(wrcal_final_chk),
        .O(wrcal_final_chk_i_1_n_0));
  LUT5 #(
    .INIT(32'hFFFFDFFF)) 
    wrcal_final_chk_i_2
       (.I0(ddr3_lm_done_r_reg_0),
        .I1(\init_state_r[6]_i_1_n_0 ),
        .I2(\init_state_r[1]_i_1_n_0 ),
        .I3(\init_state_r[2]_i_1_n_0 ),
        .I4(\init_state_r[5]_i_1_n_0 ),
        .O(wrcal_final_chk_i_2_n_0));
  FDRE wrcal_final_chk_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(wrcal_final_chk_i_1_n_0),
        .Q(wrcal_final_chk),
        .R(\victim_sel_reg[0]_0 ));
  LUT6 #(
    .INIT(64'h0000000000000100)) 
    wrcal_rd_wait_i_1
       (.I0(Q),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(\init_state_r_reg_n_0_[4] ),
        .I3(\init_state_r_reg_n_0_[5] ),
        .I4(init_state_r),
        .I5(\wrcal_reads[7]_i_4_n_0 ),
        .O(wrcal_rd_wait_i_1_n_0));
  FDRE wrcal_rd_wait_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(wrcal_rd_wait_i_1_n_0),
        .Q(wrcal_rd_wait),
        .R(\victim_sel_reg[0]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair479" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \wrcal_reads[0]_i_1 
       (.I0(wrcal_reads),
        .I1(\wrcal_reads_reg_n_0_[0] ),
        .O(\wrcal_reads[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair479" *) 
  LUT3 #(
    .INIT(8'hF9)) 
    \wrcal_reads[1]_i_1 
       (.I0(\wrcal_reads_reg_n_0_[0] ),
        .I1(\wrcal_reads_reg_n_0_[1] ),
        .I2(wrcal_reads),
        .O(\wrcal_reads[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair394" *) 
  LUT4 #(
    .INIT(16'hFFE1)) 
    \wrcal_reads[2]_i_1 
       (.I0(\wrcal_reads_reg_n_0_[1] ),
        .I1(\wrcal_reads_reg_n_0_[0] ),
        .I2(\wrcal_reads_reg_n_0_[2] ),
        .I3(wrcal_reads),
        .O(\wrcal_reads[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair394" *) 
  LUT5 #(
    .INIT(32'hFFFFFE01)) 
    \wrcal_reads[3]_i_1 
       (.I0(\wrcal_reads_reg_n_0_[0] ),
        .I1(\wrcal_reads_reg_n_0_[1] ),
        .I2(\wrcal_reads_reg_n_0_[2] ),
        .I3(\wrcal_reads_reg_n_0_[3] ),
        .I4(wrcal_reads),
        .O(\wrcal_reads[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFE0001)) 
    \wrcal_reads[4]_i_1 
       (.I0(\wrcal_reads_reg_n_0_[2] ),
        .I1(\wrcal_reads_reg_n_0_[1] ),
        .I2(\wrcal_reads_reg_n_0_[0] ),
        .I3(\wrcal_reads_reg_n_0_[3] ),
        .I4(\wrcal_reads_reg_n_0_[4] ),
        .I5(wrcal_reads),
        .O(\wrcal_reads[4]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'hF6)) 
    \wrcal_reads[5]_i_1 
       (.I0(\wrcal_reads[7]_i_8_n_0 ),
        .I1(\wrcal_reads_reg_n_0_[5] ),
        .I2(wrcal_reads),
        .O(\wrcal_reads[5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair393" *) 
  LUT4 #(
    .INIT(16'hFFD2)) 
    \wrcal_reads[6]_i_1 
       (.I0(\wrcal_reads[7]_i_8_n_0 ),
        .I1(\wrcal_reads_reg_n_0_[5] ),
        .I2(\wrcal_reads_reg_n_0_[6] ),
        .I3(wrcal_reads),
        .O(\wrcal_reads[6]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAABAAAAAAAAAA)) 
    \wrcal_reads[7]_i_1 
       (.I0(write_calib_reg_0),
        .I1(\wrcal_reads[7]_i_4_n_0 ),
        .I2(init_state_r),
        .I3(\init_state_r_reg_n_0_[5] ),
        .I4(\init_state_r_reg_n_0_[4] ),
        .I5(\wrcal_reads[7]_i_5_n_0 ),
        .O(wrcal_reads05_out));
  (* SOFT_HLUTNM = "soft_lutpair449" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \wrcal_reads[7]_i_10 
       (.I0(\wrcal_reads_reg_n_0_[6] ),
        .I1(\wrcal_reads_reg_n_0_[5] ),
        .O(\wrcal_reads[7]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hEEEEEEEEEEEEEFEE)) 
    \wrcal_reads[7]_i_2 
       (.I0(\wrcal_reads_reg_n_0_[0] ),
        .I1(\wrcal_reads[7]_i_6_n_0 ),
        .I2(\wrcal_reads[7]_i_4_n_0 ),
        .I3(Q),
        .I4(\init_state_r_reg_n_0_[1] ),
        .I5(\wrcal_reads[7]_i_7_n_0 ),
        .O(\wrcal_reads[7]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair393" *) 
  LUT5 #(
    .INIT(32'hFFFFFD02)) 
    \wrcal_reads[7]_i_3 
       (.I0(\wrcal_reads[7]_i_8_n_0 ),
        .I1(\wrcal_reads_reg_n_0_[5] ),
        .I2(\wrcal_reads_reg_n_0_[6] ),
        .I3(\wrcal_reads_reg_n_0_[7] ),
        .I4(wrcal_reads),
        .O(\wrcal_reads[7]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair529" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \wrcal_reads[7]_i_4 
       (.I0(\init_state_r_reg_n_0_[3] ),
        .I1(\init_state_r_reg_n_0_[2] ),
        .O(\wrcal_reads[7]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair430" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \wrcal_reads[7]_i_5 
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(Q),
        .O(\wrcal_reads[7]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \wrcal_reads[7]_i_6 
       (.I0(\wrcal_reads_reg_n_0_[7] ),
        .I1(\wrcal_reads_reg_n_0_[2] ),
        .I2(\wrcal_reads_reg_n_0_[4] ),
        .I3(\wrcal_reads_reg_n_0_[3] ),
        .I4(\wrcal_reads_reg_n_0_[1] ),
        .I5(\wrcal_reads[7]_i_10_n_0 ),
        .O(\wrcal_reads[7]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair466" *) 
  LUT3 #(
    .INIT(8'hFB)) 
    \wrcal_reads[7]_i_7 
       (.I0(\init_state_r_reg_n_0_[4] ),
        .I1(\init_state_r_reg_n_0_[5] ),
        .I2(init_state_r),
        .O(\wrcal_reads[7]_i_7_n_0 ));
  LUT5 #(
    .INIT(32'h00000001)) 
    \wrcal_reads[7]_i_8 
       (.I0(\wrcal_reads_reg_n_0_[3] ),
        .I1(\wrcal_reads_reg_n_0_[0] ),
        .I2(\wrcal_reads_reg_n_0_[1] ),
        .I3(\wrcal_reads_reg_n_0_[2] ),
        .I4(\wrcal_reads_reg_n_0_[4] ),
        .O(\wrcal_reads[7]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000010)) 
    \wrcal_reads[7]_i_9 
       (.I0(\wrcal_reads[7]_i_7_n_0 ),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(Q),
        .I3(\wrcal_reads[7]_i_4_n_0 ),
        .I4(\wrcal_reads[7]_i_6_n_0 ),
        .I5(\wrcal_reads_reg_n_0_[0] ),
        .O(wrcal_reads));
  FDRE \wrcal_reads_reg[0] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrcal_reads[7]_i_2_n_0 ),
        .D(\wrcal_reads[0]_i_1_n_0 ),
        .Q(\wrcal_reads_reg_n_0_[0] ),
        .R(wrcal_reads05_out));
  FDRE \wrcal_reads_reg[1] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrcal_reads[7]_i_2_n_0 ),
        .D(\wrcal_reads[1]_i_1_n_0 ),
        .Q(\wrcal_reads_reg_n_0_[1] ),
        .R(wrcal_reads05_out));
  FDRE \wrcal_reads_reg[2] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrcal_reads[7]_i_2_n_0 ),
        .D(\wrcal_reads[2]_i_1_n_0 ),
        .Q(\wrcal_reads_reg_n_0_[2] ),
        .R(wrcal_reads05_out));
  FDRE \wrcal_reads_reg[3] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrcal_reads[7]_i_2_n_0 ),
        .D(\wrcal_reads[3]_i_1_n_0 ),
        .Q(\wrcal_reads_reg_n_0_[3] ),
        .R(wrcal_reads05_out));
  FDRE \wrcal_reads_reg[4] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrcal_reads[7]_i_2_n_0 ),
        .D(\wrcal_reads[4]_i_1_n_0 ),
        .Q(\wrcal_reads_reg_n_0_[4] ),
        .R(wrcal_reads05_out));
  FDRE \wrcal_reads_reg[5] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrcal_reads[7]_i_2_n_0 ),
        .D(\wrcal_reads[5]_i_1_n_0 ),
        .Q(\wrcal_reads_reg_n_0_[5] ),
        .R(wrcal_reads05_out));
  FDRE \wrcal_reads_reg[6] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrcal_reads[7]_i_2_n_0 ),
        .D(\wrcal_reads[6]_i_1_n_0 ),
        .Q(\wrcal_reads_reg_n_0_[6] ),
        .R(wrcal_reads05_out));
  FDRE \wrcal_reads_reg[7] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrcal_reads[7]_i_2_n_0 ),
        .D(\wrcal_reads[7]_i_3_n_0 ),
        .Q(\wrcal_reads_reg_n_0_[7] ),
        .R(wrcal_reads05_out));
  FDRE wrcal_resume_r_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(wrcal_resume_w),
        .Q(wrcal_resume_r),
        .R(1'b0));
  FDRE wrcal_sanity_chk_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(wrcal_final_chk),
        .Q(wrcal_sanity_chk),
        .R(1'b0));
  (* srl_bus_name = "\u_mig_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrcal_start_dly_r_reg " *) 
  (* srl_name = "\u_mig_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrcal_start_dly_r_reg[4]_srl5 " *) 
  SRL16E \wrcal_start_dly_r_reg[4]_srl5 
       (.A0(1'b0),
        .A1(1'b0),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(\rdlvl_start_dly0_r_reg[14]_0 ),
        .D(wrcal_start_pre),
        .Q(\wrcal_start_dly_r_reg[4]_srl5_n_0 ));
  LUT6 #(
    .INIT(64'h0000000001001000)) 
    \wrcal_start_dly_r_reg[4]_srl5_i_1 
       (.I0(\init_state_r_reg_n_0_[4] ),
        .I1(complex_act_start_i_2_n_0),
        .I2(\init_state_r_reg_n_0_[1] ),
        .I3(Q),
        .I4(\init_state_r_reg_n_0_[2] ),
        .I5(\init_state_r_reg_n_0_[3] ),
        .O(wrcal_start_pre));
  FDRE \wrcal_start_dly_r_reg[5] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(\wrcal_start_dly_r_reg[4]_srl5_n_0 ),
        .Q(wrcal_start_dly_r),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h000E)) 
    wrcal_start_i_1
       (.I0(wrcal_start_reg_0),
        .I1(wrcal_start_dly_r),
        .I2(wrlvl_byte_redo),
        .I3(\rd_addr_reg[7] ),
        .O(wrcal_start_i_1_n_0));
  FDRE wrcal_start_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(wrcal_start_i_1_n_0),
        .Q(wrcal_start_reg_0),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair524" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \wrcal_wr_cnt[0]_i_1 
       (.I0(wrcal_wr_cnt_reg[0]),
        .O(\wrcal_wr_cnt[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair524" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \wrcal_wr_cnt[1]_i_1 
       (.I0(wrcal_wr_cnt_reg[0]),
        .I1(wrcal_wr_cnt_reg[1]),
        .O(\wrcal_wr_cnt[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair514" *) 
  LUT3 #(
    .INIT(8'hA9)) 
    \wrcal_wr_cnt[2]_i_1 
       (.I0(wrcal_wr_cnt_reg[2]),
        .I1(wrcal_wr_cnt_reg[1]),
        .I2(wrcal_wr_cnt_reg[0]),
        .O(wrcal_wr_cnt0[2]));
  LUT6 #(
    .INIT(64'hFFFFFFFF444444F4)) 
    \wrcal_wr_cnt[3]_i_1 
       (.I0(calib_wrdata_en_i_2_n_0),
        .I1(detect_pi_found_dqs_i_2_n_0),
        .I2(\wrcal_wr_cnt[3]_i_4_n_0 ),
        .I3(wrcal_wr_cnt_reg[3]),
        .I4(wrcal_wr_cnt_reg[2]),
        .I5(write_calib_reg_0),
        .O(\wrcal_wr_cnt[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000100000)) 
    \wrcal_wr_cnt[3]_i_2 
       (.I0(\cnt_init_mr_r[0]_i_2_n_0 ),
        .I1(init_state_r),
        .I2(\init_state_r_reg_n_0_[5] ),
        .I3(\init_state_r_reg_n_0_[4] ),
        .I4(Q),
        .I5(\init_state_r_reg_n_0_[1] ),
        .O(\wrcal_wr_cnt[3]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair407" *) 
  LUT4 #(
    .INIT(16'hAAA9)) 
    \wrcal_wr_cnt[3]_i_3 
       (.I0(wrcal_wr_cnt_reg[3]),
        .I1(wrcal_wr_cnt_reg[2]),
        .I2(wrcal_wr_cnt_reg[0]),
        .I3(wrcal_wr_cnt_reg[1]),
        .O(wrcal_wr_cnt0[3]));
  (* SOFT_HLUTNM = "soft_lutpair514" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \wrcal_wr_cnt[3]_i_4 
       (.I0(wrcal_wr_cnt_reg[0]),
        .I1(wrcal_wr_cnt_reg[1]),
        .O(\wrcal_wr_cnt[3]_i_4_n_0 ));
  FDRE \wrcal_wr_cnt_reg[0] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrcal_wr_cnt[3]_i_2_n_0 ),
        .D(\wrcal_wr_cnt[0]_i_1_n_0 ),
        .Q(wrcal_wr_cnt_reg[0]),
        .R(\wrcal_wr_cnt[3]_i_1_n_0 ));
  FDRE \wrcal_wr_cnt_reg[1] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrcal_wr_cnt[3]_i_2_n_0 ),
        .D(\wrcal_wr_cnt[1]_i_1_n_0 ),
        .Q(wrcal_wr_cnt_reg[1]),
        .R(\wrcal_wr_cnt[3]_i_1_n_0 ));
  FDSE \wrcal_wr_cnt_reg[2] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrcal_wr_cnt[3]_i_2_n_0 ),
        .D(wrcal_wr_cnt0[2]),
        .Q(wrcal_wr_cnt_reg[2]),
        .S(\wrcal_wr_cnt[3]_i_1_n_0 ));
  FDRE \wrcal_wr_cnt_reg[3] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrcal_wr_cnt[3]_i_2_n_0 ),
        .D(wrcal_wr_cnt0[3]),
        .Q(wrcal_wr_cnt_reg[3]),
        .R(\wrcal_wr_cnt[3]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \wrdq_div1_4to1_wrcal_first.phy_wrdata[190]_i_1 
       (.I0(first_wrcal_pat_r),
        .I1(ddr3_lm_done_r_reg_0),
        .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata[190]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    \wrdq_div1_4to1_wrcal_first.phy_wrdata[511]_i_1 
       (.I0(first_wrcal_pat_r),
        .I1(ddr3_lm_done_r_reg_0),
        .O(\wrdq_div1_4to1_wrcal_first.phy_wrdata[511]_i_1_n_0 ));
  FDRE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[120] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 ),
        .D(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[120]_0 ),
        .Q(phy_wrdata[120]),
        .R(\wrdq_div1_4to1_wrcal_first.phy_wrdata[190]_i_1_n_0 ));
  FDRE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[121] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 ),
        .D(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[121]_0 ),
        .Q(phy_wrdata[121]),
        .R(1'b0));
  FDRE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[122] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 ),
        .D(prbs_out[4]),
        .Q(phy_wrdata[122]),
        .R(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[508]_0 ));
  FDRE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[123] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 ),
        .D(prbs_out[5]),
        .Q(phy_wrdata[123]),
        .R(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[508]_0 ));
  FDRE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[124] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 ),
        .D(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[124]_0 ),
        .Q(phy_wrdata[124]),
        .R(\wrdq_div1_4to1_wrcal_first.phy_wrdata[190]_i_1_n_0 ));
  FDRE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[125] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 ),
        .D(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[125]_0 ),
        .Q(phy_wrdata[125]),
        .R(1'b0));
  FDRE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[126] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 ),
        .D(prbs_out[6]),
        .Q(phy_wrdata[126]),
        .R(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[508]_0 ));
  FDRE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[127] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 ),
        .D(prbs_out[7]),
        .Q(phy_wrdata[127]),
        .R(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[508]_0 ));
  FDRE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[184] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 ),
        .D(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[184]_0 ),
        .Q(phy_wrdata[184]),
        .R(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187]_0 ));
  FDSE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[185] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 ),
        .D(prbs_out[8]),
        .Q(phy_wrdata[185]),
        .S(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[508]_0 ));
  FDRE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[186] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 ),
        .D(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[186]_0 ),
        .Q(phy_wrdata[186]),
        .R(\wrdq_div1_4to1_wrcal_first.phy_wrdata[190]_i_1_n_0 ));
  FDSE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 ),
        .D(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187]_1 ),
        .Q(phy_wrdata[187]),
        .S(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187]_0 ));
  FDRE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[188] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 ),
        .D(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[188]_0 ),
        .Q(phy_wrdata[188]),
        .R(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187]_0 ));
  FDSE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[189] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 ),
        .D(prbs_out[9]),
        .Q(phy_wrdata[189]),
        .S(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[508]_0 ));
  FDRE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[190] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 ),
        .D(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[190]_0 ),
        .Q(phy_wrdata[190]),
        .R(\wrdq_div1_4to1_wrcal_first.phy_wrdata[190]_i_1_n_0 ));
  FDSE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[191] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 ),
        .D(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[191]_0 ),
        .Q(phy_wrdata[191]),
        .S(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187]_0 ));
  FDSE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[248] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 ),
        .D(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[248]_0 ),
        .Q(phy_wrdata[248]),
        .S(\wrdq_div1_4to1_wrcal_first.phy_wrdata[190]_i_1_n_0 ));
  FDRE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[249] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 ),
        .D(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[249]_0 ),
        .Q(phy_wrdata[249]),
        .R(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187]_0 ));
  FDSE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[250] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 ),
        .D(prbs_out[10]),
        .Q(phy_wrdata[250]),
        .S(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[508]_0 ));
  FDRE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[251] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 ),
        .D(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[251]_0 ),
        .Q(phy_wrdata[251]),
        .R(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187]_0 ));
  FDSE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[252] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 ),
        .D(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[252]_0 ),
        .Q(phy_wrdata[252]),
        .S(\wrdq_div1_4to1_wrcal_first.phy_wrdata[190]_i_1_n_0 ));
  FDRE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[253] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 ),
        .D(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[253]_0 ),
        .Q(phy_wrdata[253]),
        .R(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187]_0 ));
  FDSE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[254] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 ),
        .D(prbs_out[11]),
        .Q(phy_wrdata[254]),
        .S(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[508]_0 ));
  FDRE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[255] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 ),
        .D(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[255]_0 ),
        .Q(phy_wrdata[255]),
        .R(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187]_0 ));
  FDSE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[312] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 ),
        .D(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[312]_0 ),
        .Q(phy_wrdata[312]),
        .S(\wrdq_div1_4to1_wrcal_first.phy_wrdata[190]_i_1_n_0 ));
  FDRE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[313] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 ),
        .D(prbs_out[12]),
        .Q(phy_wrdata[313]),
        .R(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[508]_0 ));
  FDSE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[314] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 ),
        .D(prbs_out[13]),
        .Q(phy_wrdata[314]),
        .S(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[508]_0 ));
  FDRE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[315] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 ),
        .D(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[315]_0 ),
        .Q(phy_wrdata[315]),
        .R(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187]_0 ));
  FDSE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[316] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 ),
        .D(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[316]_0 ),
        .Q(phy_wrdata[316]),
        .S(\wrdq_div1_4to1_wrcal_first.phy_wrdata[190]_i_1_n_0 ));
  FDRE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[317] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 ),
        .D(prbs_out[14]),
        .Q(phy_wrdata[317]),
        .R(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[508]_0 ));
  FDSE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[318] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 ),
        .D(prbs_out[15]),
        .Q(phy_wrdata[318]),
        .S(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[508]_0 ));
  FDRE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[319] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 ),
        .D(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[319]_0 ),
        .Q(phy_wrdata[319]),
        .R(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187]_0 ));
  FDRE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[376] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 ),
        .D(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[376]_0 ),
        .Q(phy_wrdata[376]),
        .R(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187]_0 ));
  FDSE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[377] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 ),
        .D(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[377]_0 ),
        .Q(phy_wrdata[377]),
        .S(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187]_0 ));
  FDSE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[378] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 ),
        .D(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[378]_0 ),
        .Q(phy_wrdata[378]),
        .S(\wrdq_div1_4to1_wrcal_first.phy_wrdata[511]_i_1_n_0 ));
  FDSE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[379] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 ),
        .D(prbs_out[16]),
        .Q(phy_wrdata[379]),
        .S(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[508]_0 ));
  FDRE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[380] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 ),
        .D(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[380]_0 ),
        .Q(phy_wrdata[380]),
        .R(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187]_0 ));
  FDSE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[381] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 ),
        .D(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[381]_0 ),
        .Q(phy_wrdata[381]),
        .S(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187]_0 ));
  FDSE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[382] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 ),
        .D(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[382]_0 ),
        .Q(phy_wrdata[382]),
        .S(\wrdq_div1_4to1_wrcal_first.phy_wrdata[511]_i_1_n_0 ));
  FDSE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[383] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 ),
        .D(prbs_out[17]),
        .Q(phy_wrdata[383]),
        .S(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[508]_0 ));
  FDSE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[440] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 ),
        .D(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[440]_0 ),
        .Q(phy_wrdata[440]),
        .S(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187]_0 ));
  FDRE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[441] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 ),
        .D(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[441]_0 ),
        .Q(phy_wrdata[441]),
        .R(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187]_0 ));
  FDSE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[442] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 ),
        .D(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[442]_0 ),
        .Q(phy_wrdata[442]),
        .S(\wrdq_div1_4to1_wrcal_first.phy_wrdata[511]_i_1_n_0 ));
  FDSE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[443] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 ),
        .D(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[443]_0 ),
        .Q(phy_wrdata[443]),
        .S(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187]_0 ));
  FDSE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[444] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 ),
        .D(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[444]_0 ),
        .Q(phy_wrdata[444]),
        .S(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187]_0 ));
  FDRE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[445] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 ),
        .D(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[445]_0 ),
        .Q(phy_wrdata[445]),
        .R(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187]_0 ));
  FDSE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[446] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 ),
        .D(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[446]_0 ),
        .Q(phy_wrdata[446]),
        .S(\wrdq_div1_4to1_wrcal_first.phy_wrdata[511]_i_1_n_0 ));
  FDSE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[447] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 ),
        .D(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[447]_0 ),
        .Q(phy_wrdata[447]),
        .S(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[187]_0 ));
  FDRE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[504] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 ),
        .D(prbs_out[18]),
        .Q(phy_wrdata[504]),
        .R(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[508]_0 ));
  FDSE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[505] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 ),
        .D(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[505]_0 ),
        .Q(phy_wrdata[505]),
        .S(\wrdq_div1_4to1_wrcal_first.phy_wrdata[190]_i_1_n_0 ));
  FDRE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[506] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 ),
        .D(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[506]_0 ),
        .Q(phy_wrdata[506]),
        .R(1'b0));
  FDSE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[507] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 ),
        .D(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[507]_0 ),
        .Q(phy_wrdata[507]),
        .S(\wrdq_div1_4to1_wrcal_first.phy_wrdata[511]_i_1_n_0 ));
  FDRE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[508] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 ),
        .D(prbs_out[19]),
        .Q(phy_wrdata[508]),
        .R(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[508]_0 ));
  FDSE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[509] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 ),
        .D(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[509]_0 ),
        .Q(phy_wrdata[509]),
        .S(\wrdq_div1_4to1_wrcal_first.phy_wrdata[190]_i_1_n_0 ));
  FDRE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[510] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 ),
        .D(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[510]_0 ),
        .Q(phy_wrdata[510]),
        .R(1'b0));
  FDSE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 ),
        .D(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0 ),
        .Q(phy_wrdata[511]),
        .S(\wrdq_div1_4to1_wrcal_first.phy_wrdata[511]_i_1_n_0 ));
  FDSE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 ),
        .D(prbs_out[0]),
        .Q(phy_wrdata[56]),
        .S(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[508]_0 ));
  FDRE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 ),
        .D(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[57]_0 ),
        .Q(phy_wrdata[57]),
        .R(1'b0));
  FDSE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[58] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 ),
        .D(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[58]_0 ),
        .Q(phy_wrdata[58]),
        .S(\wrdq_div1_4to1_wrcal_first.phy_wrdata[190]_i_1_n_0 ));
  FDSE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[59] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 ),
        .D(prbs_out[1]),
        .Q(phy_wrdata[59]),
        .S(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[508]_0 ));
  FDSE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[60] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 ),
        .D(prbs_out[2]),
        .Q(phy_wrdata[60]),
        .S(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[508]_0 ));
  FDRE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[61] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 ),
        .D(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[61]_0 ),
        .Q(phy_wrdata[61]),
        .R(1'b0));
  FDSE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[62] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 ),
        .D(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[62]_0 ),
        .Q(phy_wrdata[62]),
        .S(\wrdq_div1_4to1_wrcal_first.phy_wrdata[190]_i_1_n_0 ));
  FDSE \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[63] 
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 ),
        .D(prbs_out[3]),
        .Q(phy_wrdata[63]),
        .S(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[508]_0 ));
  LUT6 #(
    .INIT(64'h000000007F7F7F00)) 
    write_calib_i_1
       (.I0(done_dqs_tap_inc),
        .I1(\init_state_r_reg_n_0_[1] ),
        .I2(write_calib_i_2_n_0),
        .I3(wrlvl_active_r1),
        .I4(phy_write_calib),
        .I5(write_calib_reg_0),
        .O(write_calib_i_1_n_0));
  LUT6 #(
    .INIT(64'h0000000000000004)) 
    write_calib_i_2
       (.I0(\init_state_r_reg_n_0_[2] ),
        .I1(\init_state_r_reg_n_0_[3] ),
        .I2(init_state_r),
        .I3(\init_state_r_reg_n_0_[5] ),
        .I4(Q),
        .I5(\init_state_r_reg_n_0_[4] ),
        .O(write_calib_i_2_n_0));
  FDRE write_calib_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(write_calib_i_1_n_0),
        .Q(phy_write_calib),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000005540)) 
    wrlvl_active_i_1
       (.I0(done_dqs_tap_inc),
        .I1(wrlvl_odt),
        .I2(\en_cnt_div4.wrlvl_odt_i_2_n_0 ),
        .I3(wrlvl_active),
        .I4(wrlvl_rank_done),
        .I5(write_calib_reg_0),
        .O(wrlvl_active_i_1_n_0));
  FDRE wrlvl_active_r1_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(wrlvl_active),
        .Q(wrlvl_active_r1),
        .R(1'b0));
  FDRE wrlvl_active_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(wrlvl_active_i_1_n_0),
        .Q(wrlvl_active),
        .R(1'b0));
  FDRE wrlvl_done_r1_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(wrlvl_done_r),
        .Q(wrlvl_done_r1),
        .R(1'b0));
  FDRE wrlvl_done_r_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(wrlvl_done_r_reg_0),
        .Q(wrlvl_done_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000020202220)) 
    wrlvl_final_if_rst_i_1
       (.I0(wrlvl_final_if_rst_i_2_n_0),
        .I1(write_calib_reg_0),
        .I2(wrlvl_final_if_rst),
        .I3(wrlvl_done_r),
        .I4(wrlvl_final_if_rst_i_3_n_0),
        .I5(\num_refresh[3]_i_6_n_0 ),
        .O(wrlvl_final_if_rst_i_1_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFBFFFFFFFF)) 
    wrlvl_final_if_rst_i_2
       (.I0(\init_state_r_reg_n_0_[4] ),
        .I1(\init_state_r_reg_n_0_[5] ),
        .I2(init_state_r),
        .I3(\init_state_r_reg_n_0_[3] ),
        .I4(\init_state_r_reg_n_0_[2] ),
        .I5(\gen_no_mirror.div_clk_loop[0].phy_address[12]_i_2_n_0 ),
        .O(wrlvl_final_if_rst_i_2_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFD)) 
    wrlvl_final_if_rst_i_3
       (.I0(\init_state_r_reg_n_0_[1] ),
        .I1(\init_state_r_reg_n_0_[4] ),
        .I2(Q),
        .I3(\init_state_r_reg_n_0_[5] ),
        .I4(init_state_r),
        .I5(\init_state_r[4]_i_4_n_0 ),
        .O(wrlvl_final_if_rst_i_3_n_0));
  FDRE wrlvl_final_if_rst_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(wrlvl_final_if_rst_i_1_n_0),
        .Q(wrlvl_final_if_rst),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h0000AA20)) 
    wrlvl_odt_ctl_i_1
       (.I0(wrlvl_odt_ctl_i_2_n_0),
        .I1(wrlvl_rank_done_r1),
        .I2(wrlvl_rank_done),
        .I3(wrlvl_odt_ctl),
        .I4(write_calib_reg_0),
        .O(wrlvl_odt_ctl_i_1_n_0));
  LUT6 #(
    .INIT(64'hFFFDFFFDFFFDFFFF)) 
    wrlvl_odt_ctl_i_2
       (.I0(detect_pi_found_dqs_i_2_n_0),
        .I1(\init_state_r[3]_i_6_n_0 ),
        .I2(\init_state_r_reg_n_0_[4] ),
        .I3(\wrcal_reads[7]_i_4_n_0 ),
        .I4(\gen_no_mirror.div_clk_loop[0].phy_address[9]_i_11_n_0 ),
        .I5(init_state_r1[3]),
        .O(wrlvl_odt_ctl_i_2_n_0));
  FDRE wrlvl_odt_ctl_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(wrlvl_odt_ctl_i_1_n_0),
        .Q(wrlvl_odt_ctl),
        .R(1'b0));
  FDRE wrlvl_rank_done_r1_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(wrlvl_rank_done),
        .Q(wrlvl_rank_done_r1),
        .R(1'b0));
  (* srl_name = "\u_mig_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/wrlvl_rank_done_r6_reg_srl5 " *) 
  SRL16E wrlvl_rank_done_r6_reg_srl5
       (.A0(1'b0),
        .A1(1'b0),
        .A2(1'b1),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(\rdlvl_start_dly0_r_reg[14]_0 ),
        .D(wrlvl_rank_done_r1),
        .Q(wrlvl_rank_done_r6_reg_srl5_n_0));
  FDRE wrlvl_rank_done_r7_reg
       (.C(\rdlvl_start_dly0_r_reg[14]_0 ),
        .CE(1'b1),
        .D(wrlvl_rank_done_r6_reg_srl5_n_0),
        .Q(wrlvl_rank_done_r7),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_phy_prbs_rdlvl" *) 
module mig_mig_7series_v4_2_ddr_phy_prbs_rdlvl
   (prbs_rdlvl_start_r,
    complex_victim_inc_reg_0,
    prbs_rdlvl_prech_req_reg_0,
    prbs_pi_stg2_f_en,
    prbs_pi_stg2_f_incdec,
    new_cnt_dqs_r_reg_0,
    num_samples_done_r,
    prbs_rdlvl_done_reg_0,
    prbs_last_byte_done,
    reset_rd_addr,
    complex_pi_incdec_done,
    \samples_cnt_r_reg[11]_0 ,
    D,
    \rd_victim_sel_reg[2]_0 ,
    \rd_victim_sel_reg[0]_0 ,
    \rd_victim_sel_reg[1]_0 ,
    prbs_rdlvl_done_pulse0,
    prbs_rdlvl_done_reg_1,
    dqs_found_done_r_reg,
    reset_rd_addr0,
    \prbs_dqs_cnt_r_reg[0]_0 ,
    \prbs_dqs_cnt_r_reg[1]_0 ,
    \prbs_dqs_cnt_r_reg[2]_0 ,
    \prbs_dqs_cnt_r_reg[3]_0 ,
    reset_if_r9_reg,
    \rd_mux_sel_r_reg[2]_0 ,
    prbs_rdlvl_start_r_reg_0,
    \bit_cnt_reg[7]_0 ,
    mux_rd_valid_r0,
    \samples_cnt_r_reg[0]_0 ,
    prbs_out,
    \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]_0 ,
    \gen_mux_rd[1].mux_rd_rise0_r1_reg[1]_0 ,
    \gen_mux_rd[2].mux_rd_rise0_r1_reg[2]_0 ,
    \gen_mux_rd[3].mux_rd_rise0_r1_reg[3]_0 ,
    \gen_mux_rd[4].mux_rd_rise0_r1_reg[4]_0 ,
    \gen_mux_rd[5].mux_rd_rise0_r1_reg[5]_0 ,
    \gen_mux_rd[6].mux_rd_rise0_r1_reg[6]_0 ,
    \gen_mux_rd[7].mux_rd_rise0_r1_reg[7]_0 ,
    \gen_mux_rd[0].mux_rd_fall0_r1_reg[0]_0 ,
    \gen_mux_rd[1].mux_rd_fall0_r1_reg[1]_0 ,
    \gen_mux_rd[2].mux_rd_fall0_r1_reg[2]_0 ,
    \gen_mux_rd[3].mux_rd_fall0_r1_reg[3]_0 ,
    \gen_mux_rd[4].mux_rd_fall0_r1_reg[4]_0 ,
    \gen_mux_rd[5].mux_rd_fall0_r1_reg[5]_0 ,
    \gen_mux_rd[6].mux_rd_fall0_r1_reg[6]_0 ,
    \gen_mux_rd[7].mux_rd_fall0_r1_reg[7]_0 ,
    \gen_mux_rd[0].mux_rd_rise1_r1_reg[0]_0 ,
    \gen_mux_rd[1].mux_rd_rise1_r1_reg[1]_0 ,
    \gen_mux_rd[2].mux_rd_rise1_r1_reg[2]_0 ,
    \gen_mux_rd[3].mux_rd_rise1_r1_reg[3]_0 ,
    \gen_mux_rd[4].mux_rd_rise1_r1_reg[4]_0 ,
    \gen_mux_rd[5].mux_rd_rise1_r1_reg[5]_0 ,
    \gen_mux_rd[6].mux_rd_rise1_r1_reg[6]_0 ,
    \gen_mux_rd[7].mux_rd_rise1_r1_reg[7]_0 ,
    \gen_mux_rd[0].mux_rd_fall1_r1_reg[0]_0 ,
    \gen_mux_rd[1].mux_rd_fall1_r1_reg[1]_0 ,
    \gen_mux_rd[2].mux_rd_fall1_r1_reg[2]_0 ,
    \gen_mux_rd[3].mux_rd_fall1_r1_reg[3]_0 ,
    \gen_mux_rd[4].mux_rd_fall1_r1_reg[4]_0 ,
    \gen_mux_rd[5].mux_rd_fall1_r1_reg[5]_0 ,
    \gen_mux_rd[6].mux_rd_fall1_r1_reg[6]_0 ,
    \gen_mux_rd[7].mux_rd_fall1_r1_reg[7]_0 ,
    \gen_mux_rd[0].mux_rd_rise2_r1_reg[0]_0 ,
    \gen_mux_rd[1].mux_rd_rise2_r1_reg[1]_0 ,
    \gen_mux_rd[2].mux_rd_rise2_r1_reg[2]_0 ,
    \gen_mux_rd[3].mux_rd_rise2_r1_reg[3]_0 ,
    \gen_mux_rd[4].mux_rd_rise2_r1_reg[4]_0 ,
    \gen_mux_rd[5].mux_rd_rise2_r1_reg[5]_0 ,
    \gen_mux_rd[6].mux_rd_rise2_r1_reg[6]_0 ,
    \gen_mux_rd[7].mux_rd_rise2_r1_reg[7]_0 ,
    \gen_mux_rd[0].mux_rd_fall2_r1_reg[0]_0 ,
    \gen_mux_rd[1].mux_rd_fall2_r1_reg[1]_0 ,
    \gen_mux_rd[2].mux_rd_fall2_r1_reg[2]_0 ,
    \gen_mux_rd[3].mux_rd_fall2_r1_reg[3]_0 ,
    \gen_mux_rd[4].mux_rd_fall2_r1_reg[4]_0 ,
    \gen_mux_rd[5].mux_rd_fall2_r1_reg[5]_0 ,
    \gen_mux_rd[6].mux_rd_fall2_r1_reg[6]_0 ,
    \gen_mux_rd[7].mux_rd_fall2_r1_reg[7]_0 ,
    \gen_mux_rd[0].mux_rd_rise3_r1_reg[0]_0 ,
    \gen_mux_rd[1].mux_rd_rise3_r1_reg[1]_0 ,
    \gen_mux_rd[2].mux_rd_rise3_r1_reg[2]_0 ,
    \gen_mux_rd[3].mux_rd_rise3_r1_reg[3]_0 ,
    \gen_mux_rd[4].mux_rd_rise3_r1_reg[4]_0 ,
    \gen_mux_rd[5].mux_rd_rise3_r1_reg[5]_0 ,
    \gen_mux_rd[6].mux_rd_rise3_r1_reg[6]_0 ,
    \gen_mux_rd[7].mux_rd_rise3_r1_reg[7]_0 ,
    \gen_mux_rd[0].mux_rd_fall3_r1_reg[0]_0 ,
    \gen_mux_rd[1].mux_rd_fall3_r1_reg[1]_0 ,
    \gen_mux_rd[2].mux_rd_fall3_r1_reg[2]_0 ,
    \gen_mux_rd[3].mux_rd_fall3_r1_reg[3]_0 ,
    \gen_mux_rd[4].mux_rd_fall3_r1_reg[4]_0 ,
    \gen_mux_rd[5].mux_rd_fall3_r1_reg[5]_0 ,
    \gen_mux_rd[6].mux_rd_fall3_r1_reg[6]_0 ,
    \gen_mux_rd[7].mux_rd_fall3_r1_reg[7]_0 ,
    \prbs_dec_tap_cnt_reg[0]_0 ,
    \match_flag_and_reg[7]_0 ,
    no_err_win_detected_reg_0,
    prbs_found_2nd_edge_r_reg_0,
    new_cnt_dqs_r_reg_1,
    \rd_victim_sel_reg[2]_1 ,
    prech_done,
    \cmp_err_4to1.compare_err_f3_reg_0 ,
    complex_act_start,
    prbs_rdlvl_done_r1,
    \gen_byte_sel_div2.byte_sel_cnt_reg[0] ,
    \init_state_r[0]_i_27 ,
    \gen_byte_sel_div2.byte_sel_cnt_reg[0]_0 ,
    rdlvl_last_byte_done,
    \init_state_r[0]_i_27_0 ,
    complex_ocal_reset_rd_addr,
    rdlvl_stg1_done_r1,
    reset_if,
    Q,
    reset_if_r9,
    reset_if_reg,
    E,
    \prbs_dqs_cnt_r_reg[0]_1 ,
    \rdlvl_cpt_tap_cnt_reg[5]_0 ,
    \rdlvl_cpt_tap_cnt_reg[5]_1 ,
    \rdlvl_cpt_tap_cnt_reg[5]_2 ,
    \rdlvl_cpt_tap_cnt_reg[5]_3 );
  output prbs_rdlvl_start_r;
  output complex_victim_inc_reg_0;
  output prbs_rdlvl_prech_req_reg_0;
  output prbs_pi_stg2_f_en;
  output prbs_pi_stg2_f_incdec;
  output new_cnt_dqs_r_reg_0;
  output num_samples_done_r;
  output prbs_rdlvl_done_reg_0;
  output prbs_last_byte_done;
  output reset_rd_addr;
  output complex_pi_incdec_done;
  output \samples_cnt_r_reg[11]_0 ;
  output [5:0]D;
  output \rd_victim_sel_reg[2]_0 ;
  output \rd_victim_sel_reg[0]_0 ;
  output \rd_victim_sel_reg[1]_0 ;
  output prbs_rdlvl_done_pulse0;
  output prbs_rdlvl_done_reg_1;
  output dqs_found_done_r_reg;
  output reset_rd_addr0;
  output \prbs_dqs_cnt_r_reg[0]_0 ;
  output \prbs_dqs_cnt_r_reg[1]_0 ;
  output \prbs_dqs_cnt_r_reg[2]_0 ;
  output \prbs_dqs_cnt_r_reg[3]_0 ;
  output reset_if_r9_reg;
  output [2:0]\rd_mux_sel_r_reg[2]_0 ;
  input prbs_rdlvl_start_r_reg_0;
  input \bit_cnt_reg[7]_0 ;
  input mux_rd_valid_r0;
  input \samples_cnt_r_reg[0]_0 ;
  input [63:0]prbs_out;
  input \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]_0 ;
  input \gen_mux_rd[1].mux_rd_rise0_r1_reg[1]_0 ;
  input \gen_mux_rd[2].mux_rd_rise0_r1_reg[2]_0 ;
  input \gen_mux_rd[3].mux_rd_rise0_r1_reg[3]_0 ;
  input \gen_mux_rd[4].mux_rd_rise0_r1_reg[4]_0 ;
  input \gen_mux_rd[5].mux_rd_rise0_r1_reg[5]_0 ;
  input \gen_mux_rd[6].mux_rd_rise0_r1_reg[6]_0 ;
  input \gen_mux_rd[7].mux_rd_rise0_r1_reg[7]_0 ;
  input \gen_mux_rd[0].mux_rd_fall0_r1_reg[0]_0 ;
  input \gen_mux_rd[1].mux_rd_fall0_r1_reg[1]_0 ;
  input \gen_mux_rd[2].mux_rd_fall0_r1_reg[2]_0 ;
  input \gen_mux_rd[3].mux_rd_fall0_r1_reg[3]_0 ;
  input \gen_mux_rd[4].mux_rd_fall0_r1_reg[4]_0 ;
  input \gen_mux_rd[5].mux_rd_fall0_r1_reg[5]_0 ;
  input \gen_mux_rd[6].mux_rd_fall0_r1_reg[6]_0 ;
  input \gen_mux_rd[7].mux_rd_fall0_r1_reg[7]_0 ;
  input \gen_mux_rd[0].mux_rd_rise1_r1_reg[0]_0 ;
  input \gen_mux_rd[1].mux_rd_rise1_r1_reg[1]_0 ;
  input \gen_mux_rd[2].mux_rd_rise1_r1_reg[2]_0 ;
  input \gen_mux_rd[3].mux_rd_rise1_r1_reg[3]_0 ;
  input \gen_mux_rd[4].mux_rd_rise1_r1_reg[4]_0 ;
  input \gen_mux_rd[5].mux_rd_rise1_r1_reg[5]_0 ;
  input \gen_mux_rd[6].mux_rd_rise1_r1_reg[6]_0 ;
  input \gen_mux_rd[7].mux_rd_rise1_r1_reg[7]_0 ;
  input \gen_mux_rd[0].mux_rd_fall1_r1_reg[0]_0 ;
  input \gen_mux_rd[1].mux_rd_fall1_r1_reg[1]_0 ;
  input \gen_mux_rd[2].mux_rd_fall1_r1_reg[2]_0 ;
  input \gen_mux_rd[3].mux_rd_fall1_r1_reg[3]_0 ;
  input \gen_mux_rd[4].mux_rd_fall1_r1_reg[4]_0 ;
  input \gen_mux_rd[5].mux_rd_fall1_r1_reg[5]_0 ;
  input \gen_mux_rd[6].mux_rd_fall1_r1_reg[6]_0 ;
  input \gen_mux_rd[7].mux_rd_fall1_r1_reg[7]_0 ;
  input \gen_mux_rd[0].mux_rd_rise2_r1_reg[0]_0 ;
  input \gen_mux_rd[1].mux_rd_rise2_r1_reg[1]_0 ;
  input \gen_mux_rd[2].mux_rd_rise2_r1_reg[2]_0 ;
  input \gen_mux_rd[3].mux_rd_rise2_r1_reg[3]_0 ;
  input \gen_mux_rd[4].mux_rd_rise2_r1_reg[4]_0 ;
  input \gen_mux_rd[5].mux_rd_rise2_r1_reg[5]_0 ;
  input \gen_mux_rd[6].mux_rd_rise2_r1_reg[6]_0 ;
  input \gen_mux_rd[7].mux_rd_rise2_r1_reg[7]_0 ;
  input \gen_mux_rd[0].mux_rd_fall2_r1_reg[0]_0 ;
  input \gen_mux_rd[1].mux_rd_fall2_r1_reg[1]_0 ;
  input \gen_mux_rd[2].mux_rd_fall2_r1_reg[2]_0 ;
  input \gen_mux_rd[3].mux_rd_fall2_r1_reg[3]_0 ;
  input \gen_mux_rd[4].mux_rd_fall2_r1_reg[4]_0 ;
  input \gen_mux_rd[5].mux_rd_fall2_r1_reg[5]_0 ;
  input \gen_mux_rd[6].mux_rd_fall2_r1_reg[6]_0 ;
  input \gen_mux_rd[7].mux_rd_fall2_r1_reg[7]_0 ;
  input \gen_mux_rd[0].mux_rd_rise3_r1_reg[0]_0 ;
  input \gen_mux_rd[1].mux_rd_rise3_r1_reg[1]_0 ;
  input \gen_mux_rd[2].mux_rd_rise3_r1_reg[2]_0 ;
  input \gen_mux_rd[3].mux_rd_rise3_r1_reg[3]_0 ;
  input \gen_mux_rd[4].mux_rd_rise3_r1_reg[4]_0 ;
  input \gen_mux_rd[5].mux_rd_rise3_r1_reg[5]_0 ;
  input \gen_mux_rd[6].mux_rd_rise3_r1_reg[6]_0 ;
  input \gen_mux_rd[7].mux_rd_rise3_r1_reg[7]_0 ;
  input \gen_mux_rd[0].mux_rd_fall3_r1_reg[0]_0 ;
  input \gen_mux_rd[1].mux_rd_fall3_r1_reg[1]_0 ;
  input \gen_mux_rd[2].mux_rd_fall3_r1_reg[2]_0 ;
  input \gen_mux_rd[3].mux_rd_fall3_r1_reg[3]_0 ;
  input \gen_mux_rd[4].mux_rd_fall3_r1_reg[4]_0 ;
  input \gen_mux_rd[5].mux_rd_fall3_r1_reg[5]_0 ;
  input \gen_mux_rd[6].mux_rd_fall3_r1_reg[6]_0 ;
  input \gen_mux_rd[7].mux_rd_fall3_r1_reg[7]_0 ;
  input [0:0]\prbs_dec_tap_cnt_reg[0]_0 ;
  input \match_flag_and_reg[7]_0 ;
  input no_err_win_detected_reg_0;
  input prbs_found_2nd_edge_r_reg_0;
  input new_cnt_dqs_r_reg_1;
  input \rd_victim_sel_reg[2]_1 ;
  input prech_done;
  input \cmp_err_4to1.compare_err_f3_reg_0 ;
  input complex_act_start;
  input prbs_rdlvl_done_r1;
  input \gen_byte_sel_div2.byte_sel_cnt_reg[0] ;
  input \init_state_r[0]_i_27 ;
  input \gen_byte_sel_div2.byte_sel_cnt_reg[0]_0 ;
  input rdlvl_last_byte_done;
  input \init_state_r[0]_i_27_0 ;
  input complex_ocal_reset_rd_addr;
  input rdlvl_stg1_done_r1;
  input reset_if;
  input [3:0]Q;
  input reset_if_r9;
  input reset_if_reg;
  input [0:0]E;
  input \prbs_dqs_cnt_r_reg[0]_1 ;
  input \rdlvl_cpt_tap_cnt_reg[5]_0 ;
  input [5:0]\rdlvl_cpt_tap_cnt_reg[5]_1 ;
  input \rdlvl_cpt_tap_cnt_reg[5]_2 ;
  input [5:0]\rdlvl_cpt_tap_cnt_reg[5]_3 ;

  wire [5:0]D;
  wire [0:0]E;
  wire [3:0]Q;
  wire bit_cnt0;
  wire \bit_cnt[7]_i_1_n_0 ;
  wire \bit_cnt[7]_i_3_n_0 ;
  wire \bit_cnt_reg[7]_0 ;
  wire \bit_cnt_reg_n_0_[0] ;
  wire \bit_cnt_reg_n_0_[1] ;
  wire \bit_cnt_reg_n_0_[2] ;
  wire \bit_cnt_reg_n_0_[3] ;
  wire \cmp_err_4to1.compare_err_f0_i_2_n_0 ;
  wire \cmp_err_4to1.compare_err_f0_i_3_n_0 ;
  wire \cmp_err_4to1.compare_err_f0_reg_n_0 ;
  wire \cmp_err_4to1.compare_err_f1_i_2_n_0 ;
  wire \cmp_err_4to1.compare_err_f1_i_3_n_0 ;
  wire \cmp_err_4to1.compare_err_f1_reg_n_0 ;
  wire \cmp_err_4to1.compare_err_f2_i_2_n_0 ;
  wire \cmp_err_4to1.compare_err_f2_i_3_n_0 ;
  wire \cmp_err_4to1.compare_err_f2_reg_n_0 ;
  wire \cmp_err_4to1.compare_err_f3_i_2_n_0 ;
  wire \cmp_err_4to1.compare_err_f3_i_3_n_0 ;
  wire \cmp_err_4to1.compare_err_f3_reg_0 ;
  wire \cmp_err_4to1.compare_err_f3_reg_n_0 ;
  wire \cmp_err_4to1.compare_err_i_4_n_0 ;
  wire \cmp_err_4to1.compare_err_r0_i_2_n_0 ;
  wire \cmp_err_4to1.compare_err_r0_i_3_n_0 ;
  wire \cmp_err_4to1.compare_err_r0_reg_n_0 ;
  wire \cmp_err_4to1.compare_err_r1_i_2_n_0 ;
  wire \cmp_err_4to1.compare_err_r1_i_3_n_0 ;
  wire \cmp_err_4to1.compare_err_r1_reg_n_0 ;
  wire \cmp_err_4to1.compare_err_r2_i_2_n_0 ;
  wire \cmp_err_4to1.compare_err_r2_i_3_n_0 ;
  wire \cmp_err_4to1.compare_err_r2_reg_n_0 ;
  wire \cmp_err_4to1.compare_err_r3_i_2_n_0 ;
  wire \cmp_err_4to1.compare_err_r3_i_3_n_0 ;
  wire \cmp_err_4to1.compare_err_r3_reg_n_0 ;
  wire \cmp_err_4to1.compare_err_reg_n_0 ;
  wire \cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_3_n_0 ;
  wire \cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_4_n_0 ;
  wire \cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_5_n_0 ;
  wire \cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_6_n_0 ;
  wire \cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_7_n_0 ;
  wire \cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_2_n_0 ;
  wire \cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_3_n_0 ;
  wire \cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_4_n_0 ;
  wire \cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_2_n_0 ;
  wire \cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_3_n_0 ;
  wire \cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_4_n_0 ;
  wire \cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_2_n_0 ;
  wire \cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_3_n_0 ;
  wire \cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_4_n_0 ;
  wire \cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_2_n_0 ;
  wire \cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_3_n_0 ;
  wire \cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_4_n_0 ;
  wire \cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_2_n_0 ;
  wire \cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_3_n_0 ;
  wire \cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_4_n_0 ;
  wire \cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_2_n_0 ;
  wire \cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_3_n_0 ;
  wire \cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_4_n_0 ;
  wire \cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_2_n_0 ;
  wire \cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_3_n_0 ;
  wire \cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_4_n_0 ;
  wire cnt_wait_state;
  wire cnt_wait_state_i_1_n_0;
  wire compare_err0;
  wire compare_err086_out;
  wire compare_err_f00;
  wire compare_err_f10;
  wire compare_err_f20;
  wire compare_err_f30;
  wire compare_err_latch_i_1_n_0;
  wire compare_err_latch_reg_n_0;
  wire [7:0]compare_err_pb;
  wire compare_err_pb_and_i_1_n_0;
  wire compare_err_pb_and_i_2_n_0;
  wire compare_err_pb_and_i_3_n_0;
  wire compare_err_pb_and_reg_n_0;
  wire compare_err_pb_or_i_1_n_0;
  wire compare_err_pb_or_i_2_n_0;
  wire compare_err_pb_or_i_3_n_0;
  wire compare_err_r00;
  wire compare_err_r10;
  wire compare_err_r20;
  wire compare_err_r30;
  wire complex_act_start;
  wire complex_ocal_reset_rd_addr;
  wire complex_pi_incdec_done;
  wire complex_pi_incdec_done_i_1_n_0;
  wire complex_pi_incdec_done_i_2_n_0;
  wire complex_pi_incdec_done_i_3_n_0;
  wire complex_pi_incdec_done_i_4_n_0;
  wire complex_pi_incdec_done_i_5_n_0;
  wire complex_pi_incdec_done_i_6_n_0;
  wire complex_pi_incdec_done_i_7_n_0;
  wire complex_pi_incdec_done_i_8_n_0;
  wire complex_victim_inc;
  wire complex_victim_inc_reg_0;
  wire [11:1]data0;
  wire dqs_found_done_r_reg;
  wire edge_det_error_i_1_n_0;
  wire edge_det_error_i_2_n_0;
  wire edge_det_error_i_3_n_0;
  wire edge_det_error_i_4_n_0;
  wire edge_det_error_i_5_n_0;
  wire edge_det_error_i_6_n_0;
  wire edge_det_error_i_7_n_0;
  wire edge_det_error_reg_n_0;
  wire err_chk_invalid;
  wire err_chk_invalid_i_1_n_0;
  wire fine_inc_stage_i_1_n_0;
  wire fine_inc_stage_reg_n_0;
  wire fine_pi_dec_cnt;
  wire \fine_pi_dec_cnt[0]_i_1_n_0 ;
  wire \fine_pi_dec_cnt[0]_i_2_n_0 ;
  wire \fine_pi_dec_cnt[0]_i_3_n_0 ;
  wire \fine_pi_dec_cnt[1]_i_1_n_0 ;
  wire \fine_pi_dec_cnt[1]_i_2_n_0 ;
  wire \fine_pi_dec_cnt[1]_i_3_n_0 ;
  wire \fine_pi_dec_cnt[2]_i_1_n_0 ;
  wire \fine_pi_dec_cnt[2]_i_2_n_0 ;
  wire \fine_pi_dec_cnt[3]_i_10_n_0 ;
  wire \fine_pi_dec_cnt[3]_i_11_n_0 ;
  wire \fine_pi_dec_cnt[3]_i_12_n_0 ;
  wire \fine_pi_dec_cnt[3]_i_1_n_0 ;
  wire \fine_pi_dec_cnt[3]_i_2_n_0 ;
  wire \fine_pi_dec_cnt[3]_i_3_n_0 ;
  wire \fine_pi_dec_cnt[3]_i_4_n_0 ;
  wire \fine_pi_dec_cnt[3]_i_5_n_0 ;
  wire \fine_pi_dec_cnt[3]_i_6_n_0 ;
  wire \fine_pi_dec_cnt[3]_i_8_n_0 ;
  wire \fine_pi_dec_cnt[3]_i_9_n_0 ;
  wire \fine_pi_dec_cnt[4]_i_1_n_0 ;
  wire \fine_pi_dec_cnt[4]_i_2_n_0 ;
  wire \fine_pi_dec_cnt[4]_i_3_n_0 ;
  wire \fine_pi_dec_cnt[4]_i_4_n_0 ;
  wire \fine_pi_dec_cnt[5]_i_11_n_0 ;
  wire \fine_pi_dec_cnt[5]_i_12_n_0 ;
  wire \fine_pi_dec_cnt[5]_i_13_n_0 ;
  wire \fine_pi_dec_cnt[5]_i_14_n_0 ;
  wire \fine_pi_dec_cnt[5]_i_2_n_0 ;
  wire \fine_pi_dec_cnt[5]_i_3_n_0 ;
  wire \fine_pi_dec_cnt[5]_i_4_n_0 ;
  wire \fine_pi_dec_cnt[5]_i_5_n_0 ;
  wire \fine_pi_dec_cnt[5]_i_6_n_0 ;
  wire \fine_pi_dec_cnt[5]_i_7_n_0 ;
  wire \fine_pi_dec_cnt[5]_i_8_n_0 ;
  wire \fine_pi_dec_cnt[5]_i_9_n_0 ;
  wire \fine_pi_dec_cnt_reg[3]_i_7_n_0 ;
  wire \fine_pi_dec_cnt_reg[3]_i_7_n_1 ;
  wire \fine_pi_dec_cnt_reg[3]_i_7_n_2 ;
  wire \fine_pi_dec_cnt_reg[3]_i_7_n_3 ;
  wire \fine_pi_dec_cnt_reg[3]_i_7_n_4 ;
  wire \fine_pi_dec_cnt_reg[3]_i_7_n_5 ;
  wire \fine_pi_dec_cnt_reg[3]_i_7_n_6 ;
  wire \fine_pi_dec_cnt_reg[3]_i_7_n_7 ;
  wire \fine_pi_dec_cnt_reg[5]_i_10_n_1 ;
  wire \fine_pi_dec_cnt_reg[5]_i_10_n_3 ;
  wire \fine_pi_dec_cnt_reg[5]_i_10_n_6 ;
  wire \fine_pi_dec_cnt_reg[5]_i_10_n_7 ;
  wire \fine_pi_dec_cnt_reg_n_0_[0] ;
  wire \fine_pi_dec_cnt_reg_n_0_[1] ;
  wire \fine_pi_dec_cnt_reg_n_0_[2] ;
  wire \fine_pi_dec_cnt_reg_n_0_[3] ;
  wire \fine_pi_dec_cnt_reg_n_0_[4] ;
  wire \fine_pi_dec_cnt_reg_n_0_[5] ;
  wire \gen_byte_sel_div2.byte_sel_cnt_reg[0] ;
  wire \gen_byte_sel_div2.byte_sel_cnt_reg[0]_0 ;
  wire \gen_mux_div4.gen_rd_4[1].mux_rd_fall0_r2_reg ;
  wire \gen_mux_div4.gen_rd_4[1].mux_rd_fall1_r2_reg ;
  wire \gen_mux_div4.gen_rd_4[1].mux_rd_fall2_r2_reg ;
  wire \gen_mux_div4.gen_rd_4[1].mux_rd_fall3_r2_reg ;
  wire \gen_mux_div4.gen_rd_4[1].mux_rd_rise0_r2_reg ;
  wire \gen_mux_div4.gen_rd_4[1].mux_rd_rise1_r2_reg ;
  wire \gen_mux_div4.gen_rd_4[1].mux_rd_rise2_r2_reg ;
  wire \gen_mux_div4.gen_rd_4[1].mux_rd_rise3_r2_reg ;
  wire \gen_mux_div4.gen_rd_4[2].mux_rd_fall0_r2_reg ;
  wire \gen_mux_div4.gen_rd_4[2].mux_rd_fall1_r2_reg ;
  wire \gen_mux_div4.gen_rd_4[2].mux_rd_fall2_r2_reg ;
  wire \gen_mux_div4.gen_rd_4[2].mux_rd_fall3_r2_reg ;
  wire \gen_mux_div4.gen_rd_4[2].mux_rd_rise0_r2_reg ;
  wire \gen_mux_div4.gen_rd_4[2].mux_rd_rise1_r2_reg ;
  wire \gen_mux_div4.gen_rd_4[2].mux_rd_rise2_r2_reg ;
  wire \gen_mux_div4.gen_rd_4[2].mux_rd_rise3_r2_reg ;
  wire \gen_mux_div4.gen_rd_4[3].mux_rd_fall0_r2_reg ;
  wire \gen_mux_div4.gen_rd_4[3].mux_rd_fall1_r2_reg ;
  wire \gen_mux_div4.gen_rd_4[3].mux_rd_fall2_r2_reg ;
  wire \gen_mux_div4.gen_rd_4[3].mux_rd_fall3_r2_reg ;
  wire \gen_mux_div4.gen_rd_4[3].mux_rd_rise0_r2_reg ;
  wire \gen_mux_div4.gen_rd_4[3].mux_rd_rise1_r2_reg ;
  wire \gen_mux_div4.gen_rd_4[3].mux_rd_rise2_r2_reg ;
  wire \gen_mux_div4.gen_rd_4[3].mux_rd_rise3_r2_reg ;
  wire \gen_mux_div4.gen_rd_4[4].mux_rd_fall0_r2_reg ;
  wire \gen_mux_div4.gen_rd_4[4].mux_rd_fall1_r2_reg ;
  wire \gen_mux_div4.gen_rd_4[4].mux_rd_fall2_r2_reg ;
  wire \gen_mux_div4.gen_rd_4[4].mux_rd_fall3_r2_reg ;
  wire \gen_mux_div4.gen_rd_4[4].mux_rd_rise0_r2_reg ;
  wire \gen_mux_div4.gen_rd_4[4].mux_rd_rise1_r2_reg ;
  wire \gen_mux_div4.gen_rd_4[4].mux_rd_rise2_r2_reg ;
  wire \gen_mux_div4.gen_rd_4[4].mux_rd_rise3_r2_reg ;
  wire \gen_mux_div4.gen_rd_4[5].mux_rd_fall0_r2_reg ;
  wire \gen_mux_div4.gen_rd_4[5].mux_rd_fall1_r2_reg ;
  wire \gen_mux_div4.gen_rd_4[5].mux_rd_fall2_r2_reg ;
  wire \gen_mux_div4.gen_rd_4[5].mux_rd_fall3_r2_reg ;
  wire \gen_mux_div4.gen_rd_4[5].mux_rd_rise0_r2_reg ;
  wire \gen_mux_div4.gen_rd_4[5].mux_rd_rise1_r2_reg ;
  wire \gen_mux_div4.gen_rd_4[5].mux_rd_rise2_r2_reg ;
  wire \gen_mux_div4.gen_rd_4[5].mux_rd_rise3_r2_reg ;
  wire \gen_mux_div4.gen_rd_4[6].mux_rd_fall0_r2_reg ;
  wire \gen_mux_div4.gen_rd_4[6].mux_rd_fall1_r2_reg ;
  wire \gen_mux_div4.gen_rd_4[6].mux_rd_fall2_r2_reg ;
  wire \gen_mux_div4.gen_rd_4[6].mux_rd_fall3_r2_reg ;
  wire \gen_mux_div4.gen_rd_4[6].mux_rd_rise0_r2_reg ;
  wire \gen_mux_div4.gen_rd_4[6].mux_rd_rise1_r2_reg ;
  wire \gen_mux_div4.gen_rd_4[6].mux_rd_rise2_r2_reg ;
  wire \gen_mux_div4.gen_rd_4[6].mux_rd_rise3_r2_reg ;
  wire \gen_mux_div4.gen_rd_4[7].mux_rd_fall0_r2_reg ;
  wire \gen_mux_div4.gen_rd_4[7].mux_rd_fall1_r2_reg ;
  wire \gen_mux_div4.gen_rd_4[7].mux_rd_fall2_r2_reg ;
  wire \gen_mux_div4.gen_rd_4[7].mux_rd_fall3_r2_reg ;
  wire \gen_mux_div4.gen_rd_4[7].mux_rd_rise0_r2_reg ;
  wire \gen_mux_div4.gen_rd_4[7].mux_rd_rise1_r2_reg ;
  wire \gen_mux_div4.gen_rd_4[7].mux_rd_rise2_r2_reg ;
  wire \gen_mux_div4.gen_rd_4[7].mux_rd_rise3_r2_reg ;
  wire \gen_mux_rd[0].mux_rd_fall0_r1_reg[0]_0 ;
  wire \gen_mux_rd[0].mux_rd_fall1_r1_reg[0]_0 ;
  wire \gen_mux_rd[0].mux_rd_fall2_r1_reg[0]_0 ;
  wire \gen_mux_rd[0].mux_rd_fall3_r1_reg[0]_0 ;
  wire \gen_mux_rd[0].mux_rd_rise0_r1_reg[0]_0 ;
  wire \gen_mux_rd[0].mux_rd_rise1_r1_reg[0]_0 ;
  wire \gen_mux_rd[0].mux_rd_rise2_r1_reg[0]_0 ;
  wire \gen_mux_rd[0].mux_rd_rise3_r1_reg[0]_0 ;
  wire \gen_mux_rd[1].mux_rd_fall0_r1_reg ;
  wire \gen_mux_rd[1].mux_rd_fall0_r1_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_fall1_r1_reg ;
  wire \gen_mux_rd[1].mux_rd_fall1_r1_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_fall2_r1_reg ;
  wire \gen_mux_rd[1].mux_rd_fall2_r1_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_fall3_r1_reg ;
  wire \gen_mux_rd[1].mux_rd_fall3_r1_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_rise0_r1_reg ;
  wire \gen_mux_rd[1].mux_rd_rise0_r1_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_rise1_r1_reg ;
  wire \gen_mux_rd[1].mux_rd_rise1_r1_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_rise2_r1_reg ;
  wire \gen_mux_rd[1].mux_rd_rise2_r1_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_rise3_r1_reg ;
  wire \gen_mux_rd[1].mux_rd_rise3_r1_reg[1]_0 ;
  wire \gen_mux_rd[2].mux_rd_fall0_r1_reg ;
  wire \gen_mux_rd[2].mux_rd_fall0_r1_reg[2]_0 ;
  wire \gen_mux_rd[2].mux_rd_fall1_r1_reg ;
  wire \gen_mux_rd[2].mux_rd_fall1_r1_reg[2]_0 ;
  wire \gen_mux_rd[2].mux_rd_fall2_r1_reg ;
  wire \gen_mux_rd[2].mux_rd_fall2_r1_reg[2]_0 ;
  wire \gen_mux_rd[2].mux_rd_fall3_r1_reg ;
  wire \gen_mux_rd[2].mux_rd_fall3_r1_reg[2]_0 ;
  wire \gen_mux_rd[2].mux_rd_rise0_r1_reg ;
  wire \gen_mux_rd[2].mux_rd_rise0_r1_reg[2]_0 ;
  wire \gen_mux_rd[2].mux_rd_rise1_r1_reg ;
  wire \gen_mux_rd[2].mux_rd_rise1_r1_reg[2]_0 ;
  wire \gen_mux_rd[2].mux_rd_rise2_r1_reg ;
  wire \gen_mux_rd[2].mux_rd_rise2_r1_reg[2]_0 ;
  wire \gen_mux_rd[2].mux_rd_rise3_r1_reg ;
  wire \gen_mux_rd[2].mux_rd_rise3_r1_reg[2]_0 ;
  wire \gen_mux_rd[3].mux_rd_fall0_r1_reg ;
  wire \gen_mux_rd[3].mux_rd_fall0_r1_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_fall1_r1_reg ;
  wire \gen_mux_rd[3].mux_rd_fall1_r1_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_fall2_r1_reg ;
  wire \gen_mux_rd[3].mux_rd_fall2_r1_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_fall3_r1_reg ;
  wire \gen_mux_rd[3].mux_rd_fall3_r1_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_rise0_r1_reg ;
  wire \gen_mux_rd[3].mux_rd_rise0_r1_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_rise1_r1_reg ;
  wire \gen_mux_rd[3].mux_rd_rise1_r1_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_rise2_r1_reg ;
  wire \gen_mux_rd[3].mux_rd_rise2_r1_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_rise3_r1_reg ;
  wire \gen_mux_rd[3].mux_rd_rise3_r1_reg[3]_0 ;
  wire \gen_mux_rd[4].mux_rd_fall0_r1_reg ;
  wire \gen_mux_rd[4].mux_rd_fall0_r1_reg[4]_0 ;
  wire \gen_mux_rd[4].mux_rd_fall1_r1_reg ;
  wire \gen_mux_rd[4].mux_rd_fall1_r1_reg[4]_0 ;
  wire \gen_mux_rd[4].mux_rd_fall2_r1_reg ;
  wire \gen_mux_rd[4].mux_rd_fall2_r1_reg[4]_0 ;
  wire \gen_mux_rd[4].mux_rd_fall3_r1_reg ;
  wire \gen_mux_rd[4].mux_rd_fall3_r1_reg[4]_0 ;
  wire \gen_mux_rd[4].mux_rd_rise0_r1_reg ;
  wire \gen_mux_rd[4].mux_rd_rise0_r1_reg[4]_0 ;
  wire \gen_mux_rd[4].mux_rd_rise1_r1_reg ;
  wire \gen_mux_rd[4].mux_rd_rise1_r1_reg[4]_0 ;
  wire \gen_mux_rd[4].mux_rd_rise2_r1_reg ;
  wire \gen_mux_rd[4].mux_rd_rise2_r1_reg[4]_0 ;
  wire \gen_mux_rd[4].mux_rd_rise3_r1_reg ;
  wire \gen_mux_rd[4].mux_rd_rise3_r1_reg[4]_0 ;
  wire \gen_mux_rd[5].mux_rd_fall0_r1_reg ;
  wire \gen_mux_rd[5].mux_rd_fall0_r1_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_fall1_r1_reg ;
  wire \gen_mux_rd[5].mux_rd_fall1_r1_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_fall2_r1_reg ;
  wire \gen_mux_rd[5].mux_rd_fall2_r1_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_fall3_r1_reg ;
  wire \gen_mux_rd[5].mux_rd_fall3_r1_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_rise0_r1_reg ;
  wire \gen_mux_rd[5].mux_rd_rise0_r1_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_rise1_r1_reg ;
  wire \gen_mux_rd[5].mux_rd_rise1_r1_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_rise2_r1_reg ;
  wire \gen_mux_rd[5].mux_rd_rise2_r1_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_rise3_r1_reg ;
  wire \gen_mux_rd[5].mux_rd_rise3_r1_reg[5]_0 ;
  wire \gen_mux_rd[6].mux_rd_fall0_r1_reg ;
  wire \gen_mux_rd[6].mux_rd_fall0_r1_reg[6]_0 ;
  wire \gen_mux_rd[6].mux_rd_fall1_r1_reg ;
  wire \gen_mux_rd[6].mux_rd_fall1_r1_reg[6]_0 ;
  wire \gen_mux_rd[6].mux_rd_fall2_r1_reg ;
  wire \gen_mux_rd[6].mux_rd_fall2_r1_reg[6]_0 ;
  wire \gen_mux_rd[6].mux_rd_fall3_r1_reg ;
  wire \gen_mux_rd[6].mux_rd_fall3_r1_reg[6]_0 ;
  wire \gen_mux_rd[6].mux_rd_rise0_r1_reg ;
  wire \gen_mux_rd[6].mux_rd_rise0_r1_reg[6]_0 ;
  wire \gen_mux_rd[6].mux_rd_rise1_r1_reg ;
  wire \gen_mux_rd[6].mux_rd_rise1_r1_reg[6]_0 ;
  wire \gen_mux_rd[6].mux_rd_rise2_r1_reg ;
  wire \gen_mux_rd[6].mux_rd_rise2_r1_reg[6]_0 ;
  wire \gen_mux_rd[6].mux_rd_rise3_r1_reg ;
  wire \gen_mux_rd[6].mux_rd_rise3_r1_reg[6]_0 ;
  wire \gen_mux_rd[7].mux_rd_fall0_r1_reg ;
  wire \gen_mux_rd[7].mux_rd_fall0_r1_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_fall1_r1_reg ;
  wire \gen_mux_rd[7].mux_rd_fall1_r1_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_fall2_r1_reg ;
  wire \gen_mux_rd[7].mux_rd_fall2_r1_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_fall3_r1_reg ;
  wire \gen_mux_rd[7].mux_rd_fall3_r1_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_rise0_r1_reg ;
  wire \gen_mux_rd[7].mux_rd_rise0_r1_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_rise1_r1_reg ;
  wire \gen_mux_rd[7].mux_rd_rise1_r1_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_rise2_r1_reg ;
  wire \gen_mux_rd[7].mux_rd_rise2_r1_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_rise3_r1_reg ;
  wire \gen_mux_rd[7].mux_rd_rise3_r1_reg[7]_0 ;
  wire \genblk7[0].compare_err_pb_latch_r[0]_i_1_n_0 ;
  wire \genblk7[0].compare_err_pb_latch_r[0]_i_2_n_0 ;
  wire \genblk7[0].compare_err_pb_latch_r_reg_n_0_[0] ;
  wire \genblk7[1].compare_err_pb_latch_r[1]_i_1_n_0 ;
  wire \genblk7[1].compare_err_pb_latch_r_reg_n_0_[1] ;
  wire \genblk7[2].compare_err_pb_latch_r[2]_i_1_n_0 ;
  wire \genblk7[2].compare_err_pb_latch_r_reg_n_0_[2] ;
  wire \genblk7[3].compare_err_pb_latch_r[3]_i_1_n_0 ;
  wire \genblk7[3].compare_err_pb_latch_r_reg_n_0_[3] ;
  wire \genblk7[4].compare_err_pb_latch_r[4]_i_1_n_0 ;
  wire \genblk7[4].compare_err_pb_latch_r_reg_n_0_[4] ;
  wire \genblk7[5].compare_err_pb_latch_r[5]_i_1_n_0 ;
  wire \genblk7[5].compare_err_pb_latch_r_reg_n_0_[5] ;
  wire \genblk7[6].compare_err_pb_latch_r[6]_i_1_n_0 ;
  wire \genblk7[6].compare_err_pb_latch_r_reg_n_0_[6] ;
  wire \genblk7[7].compare_err_pb_latch_r[7]_i_1_n_0 ;
  wire \genblk7[7].compare_err_pb_latch_r_reg_n_0_[7] ;
  wire \genblk8[0].left_edge_updated[0]_i_1_n_0 ;
  wire \genblk8[0].left_edge_updated[0]_i_2_n_0 ;
  wire \genblk8[0].match_flag_pb[7]_i_1_n_0 ;
  wire \genblk8[0].right_edge_found_pb[0]_i_1_n_0 ;
  wire \genblk8[0].right_edge_found_pb[0]_i_2_n_0 ;
  wire \genblk8[0].right_edge_found_pb[0]_i_3_n_0 ;
  wire \genblk8[0].right_edge_found_pb[0]_i_4_n_0 ;
  wire \genblk8[0].right_edge_found_pb[0]_i_5_n_0 ;
  wire \genblk8[0].right_edge_found_pb[0]_i_6_n_0 ;
  wire \genblk8[0].right_edge_found_pb_reg_n_0_[0] ;
  wire \genblk8[1].left_edge_updated[1]_i_1_n_0 ;
  wire \genblk8[1].right_edge_found_pb[1]_i_1_n_0 ;
  wire \genblk8[1].right_edge_found_pb[1]_i_2_n_0 ;
  wire \genblk8[1].right_edge_found_pb[1]_i_3_n_0 ;
  wire \genblk8[1].right_edge_found_pb[1]_i_4_n_0 ;
  wire \genblk8[1].right_edge_found_pb_reg_n_0_[1] ;
  wire \genblk8[2].left_edge_updated[2]_i_1_n_0 ;
  wire \genblk8[2].right_edge_found_pb[2]_i_1_n_0 ;
  wire \genblk8[2].right_edge_found_pb[2]_i_2_n_0 ;
  wire \genblk8[2].right_edge_found_pb[2]_i_3_n_0 ;
  wire \genblk8[2].right_edge_found_pb[2]_i_4_n_0 ;
  wire \genblk8[2].right_edge_found_pb_reg_n_0_[2] ;
  wire \genblk8[3].left_edge_updated[3]_i_1_n_0 ;
  wire \genblk8[3].left_edge_updated[3]_i_2_n_0 ;
  wire \genblk8[3].right_edge_found_pb[3]_i_1_n_0 ;
  wire \genblk8[3].right_edge_found_pb[3]_i_2_n_0 ;
  wire \genblk8[3].right_edge_found_pb[3]_i_3_n_0 ;
  wire \genblk8[3].right_edge_found_pb[3]_i_4_n_0 ;
  wire \genblk8[3].right_edge_found_pb[3]_i_5_n_0 ;
  wire \genblk8[3].right_edge_found_pb_reg_n_0_[3] ;
  wire \genblk8[4].left_edge_updated[4]_i_1_n_0 ;
  wire \genblk8[4].left_edge_updated[4]_i_2_n_0 ;
  wire \genblk8[4].right_edge_found_pb[4]_i_1_n_0 ;
  wire \genblk8[4].right_edge_found_pb[4]_i_2_n_0 ;
  wire \genblk8[4].right_edge_found_pb[4]_i_3_n_0 ;
  wire \genblk8[4].right_edge_found_pb[4]_i_4_n_0 ;
  wire \genblk8[4].right_edge_found_pb[4]_i_5_n_0 ;
  wire \genblk8[4].right_edge_found_pb_reg_n_0_[4] ;
  wire \genblk8[5].left_edge_updated[5]_i_1_n_0 ;
  wire \genblk8[5].left_edge_updated[5]_i_2_n_0 ;
  wire \genblk8[5].right_edge_found_pb[5]_i_1_n_0 ;
  wire \genblk8[5].right_edge_found_pb[5]_i_2_n_0 ;
  wire \genblk8[5].right_edge_found_pb[5]_i_3_n_0 ;
  wire \genblk8[5].right_edge_found_pb[5]_i_4_n_0 ;
  wire \genblk8[5].right_edge_found_pb[5]_i_5_n_0 ;
  wire \genblk8[5].right_edge_found_pb_reg_n_0_[5] ;
  wire \genblk8[6].left_edge_updated[6]_i_1_n_0 ;
  wire \genblk8[6].left_edge_updated[6]_i_2_n_0 ;
  wire \genblk8[6].right_edge_found_pb[6]_i_1_n_0 ;
  wire \genblk8[6].right_edge_found_pb[6]_i_2_n_0 ;
  wire \genblk8[6].right_edge_found_pb[6]_i_3_n_0 ;
  wire \genblk8[6].right_edge_found_pb[6]_i_4_n_0 ;
  wire \genblk8[6].right_edge_found_pb[6]_i_5_n_0 ;
  wire \genblk8[6].right_edge_found_pb_reg_n_0_[6] ;
  wire \genblk8[7].left_edge_updated[7]_i_1_n_0 ;
  wire \genblk8[7].right_edge_found_pb[7]_i_1_n_0 ;
  wire \genblk8[7].right_edge_found_pb[7]_i_2_n_0 ;
  wire \genblk8[7].right_edge_found_pb[7]_i_3_n_0 ;
  wire \genblk8[7].right_edge_found_pb[7]_i_4_n_0 ;
  wire \genblk8[7].right_edge_found_pb_reg_n_0_[7] ;
  wire \init_state_r[0]_i_27 ;
  wire \init_state_r[0]_i_27_0 ;
  wire \largest_left_edge[0]_i_1_n_0 ;
  wire \largest_left_edge[1]_i_1_n_0 ;
  wire \largest_left_edge[2]_i_1_n_0 ;
  wire \largest_left_edge[3]_i_1_n_0 ;
  wire \largest_left_edge[4]_i_1_n_0 ;
  wire \largest_left_edge[5]_i_1_n_0 ;
  wire \largest_left_edge[5]_i_2_n_0 ;
  wire \largest_left_edge[5]_i_3_n_0 ;
  wire \largest_left_edge[5]_i_4_n_0 ;
  wire \largest_left_edge[5]_i_5_n_0 ;
  wire \largest_left_edge_reg_n_0_[0] ;
  wire \largest_left_edge_reg_n_0_[1] ;
  wire \largest_left_edge_reg_n_0_[2] ;
  wire \largest_left_edge_reg_n_0_[3] ;
  wire \largest_left_edge_reg_n_0_[4] ;
  wire \largest_left_edge_reg_n_0_[5] ;
  wire left_edge_found_pb85_out;
  wire [7:0]left_edge_updated;
  wire match_flag_and;
  wire \match_flag_and[0]_i_1_n_0 ;
  wire \match_flag_and[1]_i_1_n_0 ;
  wire \match_flag_and[2]_i_1_n_0 ;
  wire \match_flag_and[3]_i_1_n_0 ;
  wire \match_flag_and[4]_i_1_n_0 ;
  wire \match_flag_and[5]_i_1_n_0 ;
  wire \match_flag_and[6]_i_1_n_0 ;
  wire \match_flag_and[7]_i_2_n_0 ;
  wire \match_flag_and_reg[7]_0 ;
  wire \match_flag_and_reg_n_0_[0] ;
  wire \match_flag_and_reg_n_0_[1] ;
  wire \match_flag_and_reg_n_0_[2] ;
  wire \match_flag_and_reg_n_0_[3] ;
  wire \match_flag_and_reg_n_0_[4] ;
  wire \match_flag_and_reg_n_0_[5] ;
  wire \match_flag_and_reg_n_0_[6] ;
  wire \match_flag_and_reg_n_0_[7] ;
  wire \match_flag_or[0]_i_1_n_0 ;
  wire \match_flag_or[1]_i_1_n_0 ;
  wire \match_flag_or[2]_i_1_n_0 ;
  wire \match_flag_or[3]_i_1_n_0 ;
  wire \match_flag_or[4]_i_1_n_0 ;
  wire \match_flag_or[5]_i_1_n_0 ;
  wire \match_flag_or[6]_i_1_n_0 ;
  wire [63:0]match_flag_pb;
  wire mux_rd_fall0_r1;
  wire mux_rd_fall0_r2;
  wire mux_rd_fall1_r1;
  wire mux_rd_fall1_r2;
  wire mux_rd_fall2_r1;
  wire mux_rd_fall2_r2;
  wire mux_rd_fall3_r1;
  wire mux_rd_fall3_r2;
  wire mux_rd_rise0_r1;
  wire mux_rd_rise0_r2;
  wire mux_rd_rise1_r1;
  wire mux_rd_rise1_r2;
  wire mux_rd_rise2_r1;
  wire mux_rd_rise2_r2;
  wire mux_rd_rise3_r1;
  wire mux_rd_rise3_r2;
  wire mux_rd_valid_r;
  wire mux_rd_valid_r0;
  wire new_cnt_dqs_r_i_1_n_0;
  wire new_cnt_dqs_r_i_3_n_0;
  wire new_cnt_dqs_r_i_4_n_0;
  wire new_cnt_dqs_r_reg_0;
  wire new_cnt_dqs_r_reg_1;
  wire no_err_win_detected_i_1_n_0;
  wire no_err_win_detected_i_2_n_0;
  wire no_err_win_detected_latch_i_1_n_0;
  wire no_err_win_detected_latch_i_2_n_0;
  wire no_err_win_detected_latch_i_3_n_0;
  wire no_err_win_detected_latch_reg_n_0;
  wire no_err_win_detected_reg_0;
  wire no_err_win_detected_reg_n_0;
  wire num_samples_done_ind_i_1_n_0;
  wire num_samples_done_ind_reg_n_0;
  wire num_samples_done_r;
  wire [3:0]p_0_in;
  wire [7:0]p_0_in166_in;
  wire [7:0]p_0_in169_in;
  wire [7:0]p_0_in172_in;
  wire [7:0]p_0_in175_in;
  wire [7:0]p_0_in178_in;
  wire [7:0]p_0_in181_in;
  wire [7:0]p_0_in184_in;
  wire [7:0]p_0_in187_in;
  wire [7:0]p_0_in__0;
  wire p_10_out;
  wire p_154_out;
  wire p_19_out;
  wire [7:0]p_1_in167_in;
  wire [7:0]p_1_in170_in;
  wire [7:0]p_1_in173_in;
  wire [7:0]p_1_in176_in;
  wire [7:0]p_1_in179_in;
  wire [7:0]p_1_in182_in;
  wire [7:0]p_1_in185_in;
  wire [7:0]p_1_in188_in;
  wire p_28_out;
  wire p_37_out;
  wire p_46_out;
  wire p_55_out;
  wire p_64_out;
  wire p_66_out;
  wire p_75_out;
  wire pi_en_stg2_f_timing;
  wire pi_stg2_f_incdec_timing;
  wire pi_stg2_f_incdec_timing_i_1__0_n_0;
  wire \prbs_1st_edge_taps_r[1]_i_1_n_0 ;
  wire \prbs_1st_edge_taps_r[2]_i_1_n_0 ;
  wire \prbs_1st_edge_taps_r[3]_i_1_n_0 ;
  wire \prbs_1st_edge_taps_r[4]_i_1_n_0 ;
  wire \prbs_1st_edge_taps_r[5]_i_1_n_0 ;
  wire \prbs_1st_edge_taps_r[5]_i_2_n_0 ;
  wire \prbs_1st_edge_taps_r[5]_i_3_n_0 ;
  wire \prbs_1st_edge_taps_r_reg_n_0_[0] ;
  wire \prbs_1st_edge_taps_r_reg_n_0_[1] ;
  wire \prbs_1st_edge_taps_r_reg_n_0_[2] ;
  wire \prbs_1st_edge_taps_r_reg_n_0_[3] ;
  wire \prbs_1st_edge_taps_r_reg_n_0_[4] ;
  wire \prbs_1st_edge_taps_r_reg_n_0_[5] ;
  wire [5:0]prbs_2nd_edge_taps_r;
  wire \prbs_2nd_edge_taps_r[0]_i_1_n_0 ;
  wire \prbs_2nd_edge_taps_r[1]_i_1_n_0 ;
  wire \prbs_2nd_edge_taps_r[2]_i_1_n_0 ;
  wire \prbs_2nd_edge_taps_r[3]_i_1_n_0 ;
  wire \prbs_2nd_edge_taps_r[4]_i_1_n_0 ;
  wire \prbs_2nd_edge_taps_r[5]_i_1_n_0 ;
  wire \prbs_2nd_edge_taps_r[5]_i_2_n_0 ;
  wire \prbs_2nd_edge_taps_r[5]_i_3_n_0 ;
  wire \prbs_2nd_edge_taps_r[5]_i_4_n_0 ;
  wire \prbs_2nd_edge_taps_r[5]_i_5_n_0 ;
  wire [5:0]prbs_dec_tap_cnt;
  wire [5:1]prbs_dec_tap_cnt10_out;
  wire [5:1]prbs_dec_tap_cnt2;
  wire \prbs_dec_tap_cnt[0]_i_1_n_0 ;
  wire \prbs_dec_tap_cnt[0]_i_2_n_0 ;
  wire \prbs_dec_tap_cnt[1]_i_1_n_0 ;
  wire \prbs_dec_tap_cnt[1]_i_2_n_0 ;
  wire \prbs_dec_tap_cnt[2]_i_1_n_0 ;
  wire \prbs_dec_tap_cnt[2]_i_2_n_0 ;
  wire \prbs_dec_tap_cnt[2]_i_3_n_0 ;
  wire \prbs_dec_tap_cnt[2]_i_5_n_0 ;
  wire \prbs_dec_tap_cnt[2]_i_6_n_0 ;
  wire \prbs_dec_tap_cnt[2]_i_7_n_0 ;
  wire \prbs_dec_tap_cnt[2]_i_8_n_0 ;
  wire \prbs_dec_tap_cnt[3]_i_1_n_0 ;
  wire \prbs_dec_tap_cnt[3]_i_2_n_0 ;
  wire \prbs_dec_tap_cnt[3]_i_3_n_0 ;
  wire \prbs_dec_tap_cnt[3]_i_4_n_0 ;
  wire \prbs_dec_tap_cnt[4]_i_1_n_0 ;
  wire \prbs_dec_tap_cnt[4]_i_2_n_0 ;
  wire \prbs_dec_tap_cnt[4]_i_3_n_0 ;
  wire \prbs_dec_tap_cnt[4]_i_4_n_0 ;
  wire \prbs_dec_tap_cnt[4]_i_6_n_0 ;
  wire \prbs_dec_tap_cnt[4]_i_7_n_0 ;
  wire \prbs_dec_tap_cnt[5]_i_10_n_0 ;
  wire \prbs_dec_tap_cnt[5]_i_11_n_0 ;
  wire \prbs_dec_tap_cnt[5]_i_12_n_0 ;
  wire \prbs_dec_tap_cnt[5]_i_13_n_0 ;
  wire \prbs_dec_tap_cnt[5]_i_1_n_0 ;
  wire \prbs_dec_tap_cnt[5]_i_2_n_0 ;
  wire \prbs_dec_tap_cnt[5]_i_3_n_0 ;
  wire \prbs_dec_tap_cnt[5]_i_4_n_0 ;
  wire \prbs_dec_tap_cnt[5]_i_5_n_0 ;
  wire \prbs_dec_tap_cnt[5]_i_8_n_0 ;
  wire \prbs_dec_tap_cnt[5]_i_9_n_0 ;
  wire [0:0]\prbs_dec_tap_cnt_reg[0]_0 ;
  wire \prbs_dec_tap_cnt_reg[2]_i_4_n_0 ;
  wire \prbs_dec_tap_cnt_reg[2]_i_4_n_1 ;
  wire \prbs_dec_tap_cnt_reg[2]_i_4_n_2 ;
  wire \prbs_dec_tap_cnt_reg[2]_i_4_n_3 ;
  wire \prbs_dec_tap_cnt_reg[4]_i_5_n_3 ;
  wire \prbs_dec_tap_cnt_reg[5]_i_6_n_1 ;
  wire \prbs_dec_tap_cnt_reg[5]_i_6_n_3 ;
  wire \prbs_dec_tap_cnt_reg[5]_i_7_n_0 ;
  wire \prbs_dec_tap_cnt_reg[5]_i_7_n_1 ;
  wire \prbs_dec_tap_cnt_reg[5]_i_7_n_2 ;
  wire \prbs_dec_tap_cnt_reg[5]_i_7_n_3 ;
  wire \prbs_dqs_cnt_r[0]_i_1_n_0 ;
  wire \prbs_dqs_cnt_r[1]_i_1_n_0 ;
  wire \prbs_dqs_cnt_r[2]_i_1_n_0 ;
  wire \prbs_dqs_cnt_r[3]_i_1_n_0 ;
  wire \prbs_dqs_cnt_r[3]_i_2_n_0 ;
  wire \prbs_dqs_cnt_r[3]_i_3_n_0 ;
  wire \prbs_dqs_cnt_r[3]_i_4_n_0 ;
  wire \prbs_dqs_cnt_r_reg[0]_0 ;
  wire \prbs_dqs_cnt_r_reg[0]_1 ;
  wire \prbs_dqs_cnt_r_reg[1]_0 ;
  wire \prbs_dqs_cnt_r_reg[2]_0 ;
  wire \prbs_dqs_cnt_r_reg[3]_0 ;
  wire \prbs_dqs_cnt_r_reg_n_0_[0] ;
  wire \prbs_dqs_cnt_r_reg_n_0_[1] ;
  wire \prbs_dqs_cnt_r_reg_n_0_[2] ;
  wire \prbs_dqs_cnt_r_reg_n_0_[3] ;
  wire \prbs_dqs_tap_cnt_r[0]_i_1_n_0 ;
  wire \prbs_dqs_tap_cnt_r[1]_i_1_n_0 ;
  wire \prbs_dqs_tap_cnt_r[2]_i_1_n_0 ;
  wire \prbs_dqs_tap_cnt_r[3]_i_1_n_0 ;
  wire \prbs_dqs_tap_cnt_r[3]_i_2_n_0 ;
  wire \prbs_dqs_tap_cnt_r[4]_i_1_n_0 ;
  wire \prbs_dqs_tap_cnt_r[4]_i_2_n_0 ;
  wire \prbs_dqs_tap_cnt_r[5]_i_1_n_0 ;
  wire \prbs_dqs_tap_cnt_r[5]_i_2_n_0 ;
  wire \prbs_dqs_tap_cnt_r[5]_i_3_n_0 ;
  wire \prbs_dqs_tap_cnt_r[5]_i_4_n_0 ;
  wire \prbs_dqs_tap_cnt_r_reg_n_0_[0] ;
  wire \prbs_dqs_tap_cnt_r_reg_n_0_[1] ;
  wire \prbs_dqs_tap_cnt_r_reg_n_0_[2] ;
  wire \prbs_dqs_tap_cnt_r_reg_n_0_[3] ;
  wire \prbs_dqs_tap_cnt_r_reg_n_0_[4] ;
  wire \prbs_dqs_tap_cnt_r_reg_n_0_[5] ;
  wire prbs_dqs_tap_limit_r;
  wire prbs_dqs_tap_limit_r_i_1_n_0;
  wire prbs_dqs_tap_limit_r_i_2_n_0;
  wire prbs_found_1st_edge_r_i_1_n_0;
  wire prbs_found_1st_edge_r_reg_n_0;
  wire prbs_found_2nd_edge_r_i_1_n_0;
  wire prbs_found_2nd_edge_r_reg_0;
  wire prbs_found_2nd_edge_r_reg_n_0;
  wire prbs_inc_tap_cnt;
  wire \prbs_inc_tap_cnt[0]_i_1_n_0 ;
  wire \prbs_inc_tap_cnt[1]_i_1_n_0 ;
  wire \prbs_inc_tap_cnt[1]_i_2_n_0 ;
  wire \prbs_inc_tap_cnt[2]_i_1_n_0 ;
  wire \prbs_inc_tap_cnt[2]_i_2_n_0 ;
  wire \prbs_inc_tap_cnt[2]_i_3_n_0 ;
  wire \prbs_inc_tap_cnt[3]_i_1_n_0 ;
  wire \prbs_inc_tap_cnt[3]_i_2_n_0 ;
  wire \prbs_inc_tap_cnt[3]_i_3_n_0 ;
  wire \prbs_inc_tap_cnt[4]_i_1_n_0 ;
  wire \prbs_inc_tap_cnt[5]_i_10_n_0 ;
  wire \prbs_inc_tap_cnt[5]_i_11_n_0 ;
  wire \prbs_inc_tap_cnt[5]_i_12_n_0 ;
  wire \prbs_inc_tap_cnt[5]_i_2_n_0 ;
  wire \prbs_inc_tap_cnt[5]_i_3_n_0 ;
  wire \prbs_inc_tap_cnt[5]_i_4_n_0 ;
  wire \prbs_inc_tap_cnt[5]_i_5_n_0 ;
  wire \prbs_inc_tap_cnt[5]_i_6_n_0 ;
  wire \prbs_inc_tap_cnt[5]_i_7_n_0 ;
  wire \prbs_inc_tap_cnt[5]_i_8_n_0 ;
  wire \prbs_inc_tap_cnt[5]_i_9_n_0 ;
  wire \prbs_inc_tap_cnt_reg_n_0_[0] ;
  wire \prbs_inc_tap_cnt_reg_n_0_[1] ;
  wire \prbs_inc_tap_cnt_reg_n_0_[2] ;
  wire \prbs_inc_tap_cnt_reg_n_0_[3] ;
  wire \prbs_inc_tap_cnt_reg_n_0_[4] ;
  wire \prbs_inc_tap_cnt_reg_n_0_[5] ;
  wire prbs_last_byte_done;
  wire prbs_last_byte_done_i_1_n_0;
  wire prbs_last_byte_done_i_2_n_0;
  wire [63:0]prbs_out;
  wire prbs_pi_stg2_f_en;
  wire prbs_pi_stg2_f_incdec;
  wire prbs_prech_req_r;
  wire prbs_prech_req_r_i_1_n_0;
  wire prbs_rdlvl_done_i_1_n_0;
  wire prbs_rdlvl_done_pulse0;
  wire prbs_rdlvl_done_r1;
  wire prbs_rdlvl_done_reg_0;
  wire prbs_rdlvl_done_reg_1;
  wire prbs_rdlvl_prech_req_reg_0;
  wire prbs_rdlvl_start_r;
  wire prbs_rdlvl_start_r_reg_0;
  wire [4:0]prbs_state_r;
  wire \prbs_state_r[0]_i_1_n_0 ;
  wire \prbs_state_r[0]_i_2_n_0 ;
  wire \prbs_state_r[0]_i_3_n_0 ;
  wire \prbs_state_r[0]_i_4_n_0 ;
  wire \prbs_state_r[0]_i_5_n_0 ;
  wire \prbs_state_r[1]_i_1_n_0 ;
  wire \prbs_state_r[1]_i_2_n_0 ;
  wire \prbs_state_r[1]_i_3_n_0 ;
  wire \prbs_state_r[1]_i_4_n_0 ;
  wire \prbs_state_r[1]_i_5_n_0 ;
  wire \prbs_state_r[1]_i_6_n_0 ;
  wire \prbs_state_r[2]_i_1_n_0 ;
  wire \prbs_state_r[2]_i_2_n_0 ;
  wire \prbs_state_r[2]_i_3_n_0 ;
  wire \prbs_state_r[2]_i_4_n_0 ;
  wire \prbs_state_r[2]_i_5_n_0 ;
  wire \prbs_state_r[3]_i_1_n_0 ;
  wire \prbs_state_r[3]_i_2_n_0 ;
  wire \prbs_state_r[3]_i_3_n_0 ;
  wire \prbs_state_r[3]_i_4_n_0 ;
  wire \prbs_state_r[3]_i_5_n_0 ;
  wire \prbs_state_r[3]_i_6_n_0 ;
  wire \prbs_state_r[4]_i_10_n_0 ;
  wire \prbs_state_r[4]_i_11_n_0 ;
  wire \prbs_state_r[4]_i_12_n_0 ;
  wire \prbs_state_r[4]_i_1_n_0 ;
  wire \prbs_state_r[4]_i_2_n_0 ;
  wire \prbs_state_r[4]_i_3_n_0 ;
  wire \prbs_state_r[4]_i_4_n_0 ;
  wire \prbs_state_r[4]_i_5_n_0 ;
  wire \prbs_state_r[4]_i_6_n_0 ;
  wire \prbs_state_r[4]_i_7_n_0 ;
  wire \prbs_state_r[4]_i_8_n_0 ;
  wire \prbs_state_r[4]_i_9_n_0 ;
  wire prbs_tap_en_r;
  wire prbs_tap_en_r_i_1_n_0;
  wire prbs_tap_en_r_reg_n_0;
  wire prbs_tap_inc_r;
  wire prbs_tap_inc_r_i_1_n_0;
  wire prbs_tap_inc_r_i_3_n_0;
  wire prbs_tap_inc_r_i_4_n_0;
  wire prech_done;
  wire [2:0]\rd_mux_sel_r_reg[2]_0 ;
  wire rd_valid_r1;
  wire rd_valid_r2_reg_n_0;
  wire \rd_victim_sel[0]_i_1_n_0 ;
  wire \rd_victim_sel[1]_i_1_n_0 ;
  wire \rd_victim_sel[2]_i_1_n_0 ;
  wire \rd_victim_sel_reg[0]_0 ;
  wire \rd_victim_sel_reg[1]_0 ;
  wire \rd_victim_sel_reg[2]_0 ;
  wire \rd_victim_sel_reg[2]_1 ;
  wire [5:0]rdlvl_cpt_tap_cnt;
  wire \rdlvl_cpt_tap_cnt_reg[5]_0 ;
  wire [5:0]\rdlvl_cpt_tap_cnt_reg[5]_1 ;
  wire \rdlvl_cpt_tap_cnt_reg[5]_2 ;
  wire [5:0]\rdlvl_cpt_tap_cnt_reg[5]_3 ;
  wire rdlvl_last_byte_done;
  wire rdlvl_stg1_done_r1;
  wire reset_if;
  wire reset_if_i_2_n_0;
  wire reset_if_r9;
  wire reset_if_r9_reg;
  wire reset_if_reg;
  wire reset_rd_addr;
  wire reset_rd_addr0;
  wire reset_rd_addr_i_1_n_0;
  wire right_edge_found_i_1_n_0;
  wire right_edge_found_i_2_n_0;
  wire right_edge_found_i_3_n_0;
  wire right_edge_found_i_4_n_0;
  wire right_edge_found_i_5_n_0;
  wire right_edge_found_reg_n_0;
  wire \samples_cnt_r[0]_i_1_n_0 ;
  wire \samples_cnt_r[0]_i_2_n_0 ;
  wire \samples_cnt_r[0]_i_3_n_0 ;
  wire \samples_cnt_r[10]_i_1_n_0 ;
  wire \samples_cnt_r[11]_i_2_n_0 ;
  wire \samples_cnt_r[1]_i_1_n_0 ;
  wire \samples_cnt_r[2]_i_1_n_0 ;
  wire \samples_cnt_r[3]_i_1_n_0 ;
  wire \samples_cnt_r[4]_i_1_n_0 ;
  wire \samples_cnt_r[5]_i_1_n_0 ;
  wire \samples_cnt_r[6]_i_1_n_0 ;
  wire \samples_cnt_r[7]_i_1_n_0 ;
  wire \samples_cnt_r[8]_i_1_n_0 ;
  wire \samples_cnt_r[9]_i_1_n_0 ;
  wire \samples_cnt_r_reg[0]_0 ;
  wire \samples_cnt_r_reg[11]_0 ;
  wire \samples_cnt_r_reg[11]_i_4_n_2 ;
  wire \samples_cnt_r_reg[11]_i_4_n_3 ;
  wire \samples_cnt_r_reg[4]_i_2_n_0 ;
  wire \samples_cnt_r_reg[4]_i_2_n_1 ;
  wire \samples_cnt_r_reg[4]_i_2_n_2 ;
  wire \samples_cnt_r_reg[4]_i_2_n_3 ;
  wire \samples_cnt_r_reg[8]_i_2_n_0 ;
  wire \samples_cnt_r_reg[8]_i_2_n_1 ;
  wire \samples_cnt_r_reg[8]_i_2_n_2 ;
  wire \samples_cnt_r_reg[8]_i_2_n_3 ;
  wire \samples_cnt_r_reg_n_0_[0] ;
  wire \samples_cnt_r_reg_n_0_[10] ;
  wire \samples_cnt_r_reg_n_0_[11] ;
  wire \samples_cnt_r_reg_n_0_[1] ;
  wire \samples_cnt_r_reg_n_0_[2] ;
  wire \samples_cnt_r_reg_n_0_[3] ;
  wire \samples_cnt_r_reg_n_0_[4] ;
  wire \samples_cnt_r_reg_n_0_[5] ;
  wire \samples_cnt_r_reg_n_0_[6] ;
  wire \samples_cnt_r_reg_n_0_[7] ;
  wire \samples_cnt_r_reg_n_0_[8] ;
  wire \samples_cnt_r_reg_n_0_[9] ;
  wire [7:0]sel0;
  wire smallest_right_edge;
  wire \smallest_right_edge[0]_i_1_n_0 ;
  wire \smallest_right_edge[1]_i_1_n_0 ;
  wire \smallest_right_edge[2]_i_1_n_0 ;
  wire \smallest_right_edge[3]_i_1_n_0 ;
  wire \smallest_right_edge[4]_i_1_n_0 ;
  wire \smallest_right_edge[5]_i_10_n_0 ;
  wire \smallest_right_edge[5]_i_2_n_0 ;
  wire \smallest_right_edge[5]_i_3_n_0 ;
  wire \smallest_right_edge[5]_i_4_n_0 ;
  wire \smallest_right_edge[5]_i_5_n_0 ;
  wire \smallest_right_edge[5]_i_6_n_0 ;
  wire \smallest_right_edge[5]_i_7_n_0 ;
  wire \smallest_right_edge[5]_i_8_n_0 ;
  wire \smallest_right_edge[5]_i_9_n_0 ;
  wire \smallest_right_edge_reg_n_0_[0] ;
  wire \smallest_right_edge_reg_n_0_[1] ;
  wire \smallest_right_edge_reg_n_0_[2] ;
  wire \smallest_right_edge_reg_n_0_[3] ;
  wire \smallest_right_edge_reg_n_0_[4] ;
  wire \smallest_right_edge_reg_n_0_[5] ;
  wire \stage_cnt[0]_i_1_n_0 ;
  wire \stage_cnt[0]_i_2_n_0 ;
  wire \stage_cnt[1]_i_1_n_0 ;
  wire \stage_cnt[1]_i_2_n_0 ;
  wire \stage_cnt_reg_n_0_[0] ;
  wire \stage_cnt_reg_n_0_[1] ;
  wire \victim_not_fixed.num_samples_done_r_i_1_n_0 ;
  wire \victim_not_fixed.num_samples_done_r_i_2_n_0 ;
  wire wait_state_cnt_en_r;
  wire wait_state_cnt_en_r0;
  wire \wait_state_cnt_r[3]_i_1_n_0 ;
  wire [3:0]wait_state_cnt_r_reg;
  wire [3:1]\NLW_fine_pi_dec_cnt_reg[5]_i_10_CO_UNCONNECTED ;
  wire [3:2]\NLW_fine_pi_dec_cnt_reg[5]_i_10_O_UNCONNECTED ;
  wire [0:0]\NLW_prbs_dec_tap_cnt_reg[2]_i_4_O_UNCONNECTED ;
  wire [3:1]\NLW_prbs_dec_tap_cnt_reg[4]_i_5_CO_UNCONNECTED ;
  wire [3:2]\NLW_prbs_dec_tap_cnt_reg[4]_i_5_O_UNCONNECTED ;
  wire [3:1]\NLW_prbs_dec_tap_cnt_reg[5]_i_6_CO_UNCONNECTED ;
  wire [3:2]\NLW_prbs_dec_tap_cnt_reg[5]_i_6_O_UNCONNECTED ;
  wire [0:0]\NLW_prbs_dec_tap_cnt_reg[5]_i_7_O_UNCONNECTED ;
  wire [3:2]\NLW_samples_cnt_r_reg[11]_i_4_CO_UNCONNECTED ;
  wire [3:3]\NLW_samples_cnt_r_reg[11]_i_4_O_UNCONNECTED ;

  (* SOFT_HLUTNM = "soft_lutpair78" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \bit_cnt[0]_i_1 
       (.I0(\bit_cnt_reg_n_0_[0] ),
        .O(p_0_in__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair78" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \bit_cnt[1]_i_1 
       (.I0(\bit_cnt_reg_n_0_[0] ),
        .I1(\bit_cnt_reg_n_0_[1] ),
        .O(p_0_in__0[1]));
  (* SOFT_HLUTNM = "soft_lutpair71" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \bit_cnt[2]_i_1 
       (.I0(\bit_cnt_reg_n_0_[2] ),
        .I1(\bit_cnt_reg_n_0_[1] ),
        .I2(\bit_cnt_reg_n_0_[0] ),
        .O(p_0_in__0[2]));
  (* SOFT_HLUTNM = "soft_lutpair71" *) 
  LUT3 #(
    .INIT(8'h80)) 
    \bit_cnt[3]_i_1 
       (.I0(\bit_cnt_reg_n_0_[2] ),
        .I1(\bit_cnt_reg_n_0_[0] ),
        .I2(\bit_cnt_reg_n_0_[1] ),
        .O(p_0_in__0[3]));
  LUT6 #(
    .INIT(64'hFFFFFFFF00000002)) 
    \bit_cnt[7]_i_1 
       (.I0(prbs_state_r[0]),
        .I1(prbs_state_r[3]),
        .I2(prbs_state_r[2]),
        .I3(prbs_state_r[1]),
        .I4(prbs_state_r[4]),
        .I5(\rd_victim_sel_reg[2]_1 ),
        .O(\bit_cnt[7]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000100000000)) 
    \bit_cnt[7]_i_2 
       (.I0(p_0_in__0[6]),
        .I1(p_0_in__0[7]),
        .I2(\stage_cnt_reg_n_0_[1] ),
        .I3(\stage_cnt_reg_n_0_[0] ),
        .I4(\bit_cnt_reg_n_0_[3] ),
        .I5(\bit_cnt[7]_i_3_n_0 ),
        .O(bit_cnt0));
  (* SOFT_HLUTNM = "soft_lutpair14" *) 
  LUT5 #(
    .INIT(32'h00080000)) 
    \bit_cnt[7]_i_3 
       (.I0(prbs_state_r[4]),
        .I1(prbs_state_r[0]),
        .I2(prbs_state_r[3]),
        .I3(prbs_state_r[2]),
        .I4(prbs_state_r[1]),
        .O(\bit_cnt[7]_i_3_n_0 ));
  FDRE \bit_cnt_reg[0] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(bit_cnt0),
        .D(p_0_in__0[0]),
        .Q(\bit_cnt_reg_n_0_[0] ),
        .R(\bit_cnt[7]_i_1_n_0 ));
  FDRE \bit_cnt_reg[1] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(bit_cnt0),
        .D(p_0_in__0[1]),
        .Q(\bit_cnt_reg_n_0_[1] ),
        .R(\bit_cnt[7]_i_1_n_0 ));
  FDRE \bit_cnt_reg[2] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(bit_cnt0),
        .D(p_0_in__0[2]),
        .Q(\bit_cnt_reg_n_0_[2] ),
        .R(\bit_cnt[7]_i_1_n_0 ));
  FDRE \bit_cnt_reg[3] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(bit_cnt0),
        .D(p_0_in__0[3]),
        .Q(\bit_cnt_reg_n_0_[3] ),
        .R(\bit_cnt[7]_i_1_n_0 ));
  FDRE \bit_cnt_reg[6] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(bit_cnt0),
        .D(p_0_in__0[6]),
        .Q(p_0_in__0[6]),
        .R(\bit_cnt[7]_i_1_n_0 ));
  FDRE \bit_cnt_reg[7] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(bit_cnt0),
        .D(p_0_in__0[7]),
        .Q(p_0_in__0[7]),
        .R(\bit_cnt[7]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF6FF6)) 
    \cmp_err_4to1.compare_err_f0_i_1 
       (.I0(p_0_in184_in[7]),
        .I1(p_1_in185_in[7]),
        .I2(p_0_in184_in[6]),
        .I3(p_1_in185_in[6]),
        .I4(\cmp_err_4to1.compare_err_f0_i_2_n_0 ),
        .I5(\cmp_err_4to1.compare_err_f0_i_3_n_0 ),
        .O(compare_err_f00));
  LUT6 #(
    .INIT(64'h6FF6FFFFFFFF6FF6)) 
    \cmp_err_4to1.compare_err_f0_i_2 
       (.I0(p_1_in185_in[3]),
        .I1(p_0_in184_in[3]),
        .I2(p_0_in184_in[5]),
        .I3(p_1_in185_in[5]),
        .I4(p_0_in184_in[4]),
        .I5(p_1_in185_in[4]),
        .O(\cmp_err_4to1.compare_err_f0_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h6FF6FFFFFFFF6FF6)) 
    \cmp_err_4to1.compare_err_f0_i_3 
       (.I0(p_1_in185_in[0]),
        .I1(p_0_in184_in[0]),
        .I2(p_0_in184_in[2]),
        .I3(p_1_in185_in[2]),
        .I4(p_0_in184_in[1]),
        .I5(p_1_in185_in[1]),
        .O(\cmp_err_4to1.compare_err_f0_i_3_n_0 ));
  FDRE \cmp_err_4to1.compare_err_f0_reg 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(rd_valid_r2_reg_n_0),
        .D(compare_err_f00),
        .Q(\cmp_err_4to1.compare_err_f0_reg_n_0 ),
        .R(compare_err0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF6FF6)) 
    \cmp_err_4to1.compare_err_f1_i_1 
       (.I0(p_0_in178_in[7]),
        .I1(p_1_in179_in[7]),
        .I2(p_0_in178_in[6]),
        .I3(p_1_in179_in[6]),
        .I4(\cmp_err_4to1.compare_err_f1_i_2_n_0 ),
        .I5(\cmp_err_4to1.compare_err_f1_i_3_n_0 ),
        .O(compare_err_f10));
  LUT6 #(
    .INIT(64'h6FF6FFFFFFFF6FF6)) 
    \cmp_err_4to1.compare_err_f1_i_2 
       (.I0(p_1_in179_in[3]),
        .I1(p_0_in178_in[3]),
        .I2(p_0_in178_in[5]),
        .I3(p_1_in179_in[5]),
        .I4(p_0_in178_in[4]),
        .I5(p_1_in179_in[4]),
        .O(\cmp_err_4to1.compare_err_f1_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h6FF6FFFFFFFF6FF6)) 
    \cmp_err_4to1.compare_err_f1_i_3 
       (.I0(p_1_in179_in[0]),
        .I1(p_0_in178_in[0]),
        .I2(p_0_in178_in[2]),
        .I3(p_1_in179_in[2]),
        .I4(p_0_in178_in[1]),
        .I5(p_1_in179_in[1]),
        .O(\cmp_err_4to1.compare_err_f1_i_3_n_0 ));
  FDRE \cmp_err_4to1.compare_err_f1_reg 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(rd_valid_r2_reg_n_0),
        .D(compare_err_f10),
        .Q(\cmp_err_4to1.compare_err_f1_reg_n_0 ),
        .R(compare_err0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF6FF6)) 
    \cmp_err_4to1.compare_err_f2_i_1 
       (.I0(p_0_in172_in[7]),
        .I1(p_1_in173_in[7]),
        .I2(p_0_in172_in[6]),
        .I3(p_1_in173_in[6]),
        .I4(\cmp_err_4to1.compare_err_f2_i_2_n_0 ),
        .I5(\cmp_err_4to1.compare_err_f2_i_3_n_0 ),
        .O(compare_err_f20));
  LUT6 #(
    .INIT(64'h6FF6FFFFFFFF6FF6)) 
    \cmp_err_4to1.compare_err_f2_i_2 
       (.I0(p_1_in173_in[3]),
        .I1(p_0_in172_in[3]),
        .I2(p_0_in172_in[5]),
        .I3(p_1_in173_in[5]),
        .I4(p_0_in172_in[4]),
        .I5(p_1_in173_in[4]),
        .O(\cmp_err_4to1.compare_err_f2_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h6FF6FFFFFFFF6FF6)) 
    \cmp_err_4to1.compare_err_f2_i_3 
       (.I0(p_1_in173_in[0]),
        .I1(p_0_in172_in[0]),
        .I2(p_0_in172_in[2]),
        .I3(p_1_in173_in[2]),
        .I4(p_0_in172_in[1]),
        .I5(p_1_in173_in[1]),
        .O(\cmp_err_4to1.compare_err_f2_i_3_n_0 ));
  FDRE \cmp_err_4to1.compare_err_f2_reg 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(rd_valid_r2_reg_n_0),
        .D(compare_err_f20),
        .Q(\cmp_err_4to1.compare_err_f2_reg_n_0 ),
        .R(compare_err0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF6FF6)) 
    \cmp_err_4to1.compare_err_f3_i_1 
       (.I0(p_0_in166_in[7]),
        .I1(p_1_in167_in[7]),
        .I2(p_0_in166_in[6]),
        .I3(p_1_in167_in[6]),
        .I4(\cmp_err_4to1.compare_err_f3_i_2_n_0 ),
        .I5(\cmp_err_4to1.compare_err_f3_i_3_n_0 ),
        .O(compare_err_f30));
  LUT6 #(
    .INIT(64'h6FF6FFFFFFFF6FF6)) 
    \cmp_err_4to1.compare_err_f3_i_2 
       (.I0(p_1_in167_in[3]),
        .I1(p_0_in166_in[3]),
        .I2(p_0_in166_in[5]),
        .I3(p_1_in167_in[5]),
        .I4(p_0_in166_in[4]),
        .I5(p_1_in167_in[4]),
        .O(\cmp_err_4to1.compare_err_f3_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h6FF6FFFFFFFF6FF6)) 
    \cmp_err_4to1.compare_err_f3_i_3 
       (.I0(p_1_in167_in[0]),
        .I1(p_0_in166_in[0]),
        .I2(p_0_in166_in[2]),
        .I3(p_1_in167_in[2]),
        .I4(p_0_in166_in[1]),
        .I5(p_1_in167_in[1]),
        .O(\cmp_err_4to1.compare_err_f3_i_3_n_0 ));
  FDRE \cmp_err_4to1.compare_err_f3_reg 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(rd_valid_r2_reg_n_0),
        .D(compare_err_f30),
        .Q(\cmp_err_4to1.compare_err_f3_reg_n_0 ),
        .R(compare_err0));
  LUT6 #(
    .INIT(64'hAAAAAAAAAABABAAA)) 
    \cmp_err_4to1.compare_err_i_1 
       (.I0(\cmp_err_4to1.compare_err_f3_reg_0 ),
        .I1(prbs_state_r[4]),
        .I2(prbs_state_r[0]),
        .I3(prbs_state_r[2]),
        .I4(prbs_state_r[1]),
        .I5(prbs_state_r[3]),
        .O(compare_err0));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \cmp_err_4to1.compare_err_i_2 
       (.I0(\cmp_err_4to1.compare_err_r1_reg_n_0 ),
        .I1(\cmp_err_4to1.compare_err_f1_reg_n_0 ),
        .I2(\cmp_err_4to1.compare_err_f3_reg_n_0 ),
        .I3(\cmp_err_4to1.compare_err_f0_reg_n_0 ),
        .I4(\cmp_err_4to1.compare_err_i_4_n_0 ),
        .O(compare_err086_out));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \cmp_err_4to1.compare_err_i_4 
       (.I0(\cmp_err_4to1.compare_err_r0_reg_n_0 ),
        .I1(\cmp_err_4to1.compare_err_f2_reg_n_0 ),
        .I2(\cmp_err_4to1.compare_err_r3_reg_n_0 ),
        .I3(\cmp_err_4to1.compare_err_r2_reg_n_0 ),
        .O(\cmp_err_4to1.compare_err_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF6FF6)) 
    \cmp_err_4to1.compare_err_r0_i_1 
       (.I0(p_0_in187_in[7]),
        .I1(p_1_in188_in[7]),
        .I2(p_0_in187_in[6]),
        .I3(p_1_in188_in[6]),
        .I4(\cmp_err_4to1.compare_err_r0_i_2_n_0 ),
        .I5(\cmp_err_4to1.compare_err_r0_i_3_n_0 ),
        .O(compare_err_r00));
  LUT6 #(
    .INIT(64'h6FF6FFFFFFFF6FF6)) 
    \cmp_err_4to1.compare_err_r0_i_2 
       (.I0(p_1_in188_in[3]),
        .I1(p_0_in187_in[3]),
        .I2(p_0_in187_in[5]),
        .I3(p_1_in188_in[5]),
        .I4(p_0_in187_in[4]),
        .I5(p_1_in188_in[4]),
        .O(\cmp_err_4to1.compare_err_r0_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h6FF6FFFFFFFF6FF6)) 
    \cmp_err_4to1.compare_err_r0_i_3 
       (.I0(p_1_in188_in[0]),
        .I1(p_0_in187_in[0]),
        .I2(p_0_in187_in[2]),
        .I3(p_1_in188_in[2]),
        .I4(p_0_in187_in[1]),
        .I5(p_1_in188_in[1]),
        .O(\cmp_err_4to1.compare_err_r0_i_3_n_0 ));
  FDRE \cmp_err_4to1.compare_err_r0_reg 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(rd_valid_r2_reg_n_0),
        .D(compare_err_r00),
        .Q(\cmp_err_4to1.compare_err_r0_reg_n_0 ),
        .R(compare_err0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF6FF6)) 
    \cmp_err_4to1.compare_err_r1_i_1 
       (.I0(p_0_in181_in[7]),
        .I1(p_1_in182_in[7]),
        .I2(p_0_in181_in[6]),
        .I3(p_1_in182_in[6]),
        .I4(\cmp_err_4to1.compare_err_r1_i_2_n_0 ),
        .I5(\cmp_err_4to1.compare_err_r1_i_3_n_0 ),
        .O(compare_err_r10));
  LUT6 #(
    .INIT(64'h6FF6FFFFFFFF6FF6)) 
    \cmp_err_4to1.compare_err_r1_i_2 
       (.I0(p_1_in182_in[3]),
        .I1(p_0_in181_in[3]),
        .I2(p_0_in181_in[5]),
        .I3(p_1_in182_in[5]),
        .I4(p_0_in181_in[4]),
        .I5(p_1_in182_in[4]),
        .O(\cmp_err_4to1.compare_err_r1_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h6FF6FFFFFFFF6FF6)) 
    \cmp_err_4to1.compare_err_r1_i_3 
       (.I0(p_1_in182_in[0]),
        .I1(p_0_in181_in[0]),
        .I2(p_0_in181_in[2]),
        .I3(p_1_in182_in[2]),
        .I4(p_0_in181_in[1]),
        .I5(p_1_in182_in[1]),
        .O(\cmp_err_4to1.compare_err_r1_i_3_n_0 ));
  FDRE \cmp_err_4to1.compare_err_r1_reg 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(rd_valid_r2_reg_n_0),
        .D(compare_err_r10),
        .Q(\cmp_err_4to1.compare_err_r1_reg_n_0 ),
        .R(compare_err0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF6FF6)) 
    \cmp_err_4to1.compare_err_r2_i_1 
       (.I0(p_0_in175_in[7]),
        .I1(p_1_in176_in[7]),
        .I2(p_0_in175_in[6]),
        .I3(p_1_in176_in[6]),
        .I4(\cmp_err_4to1.compare_err_r2_i_2_n_0 ),
        .I5(\cmp_err_4to1.compare_err_r2_i_3_n_0 ),
        .O(compare_err_r20));
  LUT6 #(
    .INIT(64'h6FF6FFFFFFFF6FF6)) 
    \cmp_err_4to1.compare_err_r2_i_2 
       (.I0(p_1_in176_in[3]),
        .I1(p_0_in175_in[3]),
        .I2(p_0_in175_in[5]),
        .I3(p_1_in176_in[5]),
        .I4(p_0_in175_in[4]),
        .I5(p_1_in176_in[4]),
        .O(\cmp_err_4to1.compare_err_r2_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h6FF6FFFFFFFF6FF6)) 
    \cmp_err_4to1.compare_err_r2_i_3 
       (.I0(p_1_in176_in[0]),
        .I1(p_0_in175_in[0]),
        .I2(p_0_in175_in[2]),
        .I3(p_1_in176_in[2]),
        .I4(p_0_in175_in[1]),
        .I5(p_1_in176_in[1]),
        .O(\cmp_err_4to1.compare_err_r2_i_3_n_0 ));
  FDRE \cmp_err_4to1.compare_err_r2_reg 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(rd_valid_r2_reg_n_0),
        .D(compare_err_r20),
        .Q(\cmp_err_4to1.compare_err_r2_reg_n_0 ),
        .R(compare_err0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF6FF6)) 
    \cmp_err_4to1.compare_err_r3_i_1 
       (.I0(p_0_in169_in[7]),
        .I1(p_1_in170_in[7]),
        .I2(p_0_in169_in[6]),
        .I3(p_1_in170_in[6]),
        .I4(\cmp_err_4to1.compare_err_r3_i_2_n_0 ),
        .I5(\cmp_err_4to1.compare_err_r3_i_3_n_0 ),
        .O(compare_err_r30));
  LUT6 #(
    .INIT(64'h6FF6FFFFFFFF6FF6)) 
    \cmp_err_4to1.compare_err_r3_i_2 
       (.I0(p_1_in170_in[3]),
        .I1(p_0_in169_in[3]),
        .I2(p_0_in169_in[5]),
        .I3(p_1_in170_in[5]),
        .I4(p_0_in169_in[4]),
        .I5(p_1_in170_in[4]),
        .O(\cmp_err_4to1.compare_err_r3_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h6FF6FFFFFFFF6FF6)) 
    \cmp_err_4to1.compare_err_r3_i_3 
       (.I0(p_1_in170_in[0]),
        .I1(p_0_in169_in[0]),
        .I2(p_0_in169_in[2]),
        .I3(p_1_in170_in[2]),
        .I4(p_0_in169_in[1]),
        .I5(p_1_in170_in[1]),
        .O(\cmp_err_4to1.compare_err_r3_i_3_n_0 ));
  FDRE \cmp_err_4to1.compare_err_r3_reg 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(rd_valid_r2_reg_n_0),
        .D(compare_err_r30),
        .Q(\cmp_err_4to1.compare_err_r3_reg_n_0 ),
        .R(compare_err0));
  FDRE \cmp_err_4to1.compare_err_reg 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(rd_valid_r2_reg_n_0),
        .D(compare_err086_out),
        .Q(\cmp_err_4to1.compare_err_reg_n_0 ),
        .R(compare_err0));
  LUT6 #(
    .INIT(64'hFEFEFEFEFEFFFEFE)) 
    \cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_1 
       (.I0(\rd_victim_sel_reg[2]_1 ),
        .I1(new_cnt_dqs_r_reg_0),
        .I2(\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_3_n_0 ),
        .I3(\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_4_n_0 ),
        .I4(err_chk_invalid),
        .I5(prbs_state_r[0]),
        .O(p_66_out));
  LUT6 #(
    .INIT(64'hFFFFFFFFBEFFFFBE)) 
    \cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_2 
       (.I0(\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_5_n_0 ),
        .I1(p_1_in188_in[0]),
        .I2(p_0_in187_in[0]),
        .I3(p_1_in167_in[0]),
        .I4(p_0_in166_in[0]),
        .I5(\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_6_n_0 ),
        .O(p_75_out));
  (* SOFT_HLUTNM = "soft_lutpair41" *) 
  LUT4 #(
    .INIT(16'h0800)) 
    \cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_3 
       (.I0(prbs_state_r[2]),
        .I1(prbs_state_r[0]),
        .I2(prbs_state_r[4]),
        .I3(prbs_state_r[3]),
        .O(\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair54" *) 
  LUT4 #(
    .INIT(16'hF7EF)) 
    \cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_4 
       (.I0(prbs_state_r[1]),
        .I1(prbs_state_r[2]),
        .I2(prbs_state_r[4]),
        .I3(prbs_state_r[3]),
        .O(\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_4_n_0 ));
  LUT4 #(
    .INIT(16'h6FF6)) 
    \cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_5 
       (.I0(p_1_in176_in[0]),
        .I1(p_0_in175_in[0]),
        .I2(p_1_in179_in[0]),
        .I3(p_0_in178_in[0]),
        .O(\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_5_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF6FF6)) 
    \cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_6 
       (.I0(p_0_in184_in[0]),
        .I1(p_1_in185_in[0]),
        .I2(p_0_in181_in[0]),
        .I3(p_1_in182_in[0]),
        .I4(\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_7_n_0 ),
        .O(\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_6_n_0 ));
  LUT4 #(
    .INIT(16'h6FF6)) 
    \cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_7 
       (.I0(p_1_in173_in[0]),
        .I1(p_0_in172_in[0]),
        .I2(p_1_in170_in[0]),
        .I3(p_0_in169_in[0]),
        .O(\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_7_n_0 ));
  FDRE \cmp_err_pb_4to1.(null)[0].compare_err_pb_reg[0] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(rd_valid_r2_reg_n_0),
        .D(p_75_out),
        .Q(compare_err_pb[0]),
        .R(p_66_out));
  LUT6 #(
    .INIT(64'hFFFFFFFFBEFFFFBE)) 
    \cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_1 
       (.I0(\cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_2_n_0 ),
        .I1(p_1_in188_in[1]),
        .I2(p_0_in187_in[1]),
        .I3(p_1_in167_in[1]),
        .I4(p_0_in166_in[1]),
        .I5(\cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_3_n_0 ),
        .O(p_64_out));
  LUT4 #(
    .INIT(16'h6FF6)) 
    \cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_2 
       (.I0(p_1_in170_in[1]),
        .I1(p_0_in169_in[1]),
        .I2(p_1_in173_in[1]),
        .I3(p_0_in172_in[1]),
        .O(\cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF6FF6)) 
    \cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_3 
       (.I0(p_0_in178_in[1]),
        .I1(p_1_in179_in[1]),
        .I2(p_0_in175_in[1]),
        .I3(p_1_in176_in[1]),
        .I4(\cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_4_n_0 ),
        .O(\cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_3_n_0 ));
  LUT4 #(
    .INIT(16'h6FF6)) 
    \cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_4 
       (.I0(p_1_in182_in[1]),
        .I1(p_0_in181_in[1]),
        .I2(p_1_in185_in[1]),
        .I3(p_0_in184_in[1]),
        .O(\cmp_err_pb_4to1.(null)[1].compare_err_pb[1]_i_4_n_0 ));
  FDRE \cmp_err_pb_4to1.(null)[1].compare_err_pb_reg[1] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(rd_valid_r2_reg_n_0),
        .D(p_64_out),
        .Q(compare_err_pb[1]),
        .R(p_66_out));
  LUT6 #(
    .INIT(64'hFFFFFFFFBEFFFFBE)) 
    \cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_1 
       (.I0(\cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_2_n_0 ),
        .I1(p_1_in170_in[2]),
        .I2(p_0_in169_in[2]),
        .I3(p_1_in188_in[2]),
        .I4(p_0_in187_in[2]),
        .I5(\cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_3_n_0 ),
        .O(p_55_out));
  LUT4 #(
    .INIT(16'h6FF6)) 
    \cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_2 
       (.I0(p_1_in167_in[2]),
        .I1(p_0_in166_in[2]),
        .I2(p_1_in173_in[2]),
        .I3(p_0_in172_in[2]),
        .O(\cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF6FF6)) 
    \cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_3 
       (.I0(p_0_in178_in[2]),
        .I1(p_1_in179_in[2]),
        .I2(p_0_in175_in[2]),
        .I3(p_1_in176_in[2]),
        .I4(\cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_4_n_0 ),
        .O(\cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_3_n_0 ));
  LUT4 #(
    .INIT(16'h6FF6)) 
    \cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_4 
       (.I0(p_1_in182_in[2]),
        .I1(p_0_in181_in[2]),
        .I2(p_1_in185_in[2]),
        .I3(p_0_in184_in[2]),
        .O(\cmp_err_pb_4to1.(null)[2].compare_err_pb[2]_i_4_n_0 ));
  FDRE \cmp_err_pb_4to1.(null)[2].compare_err_pb_reg[2] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(rd_valid_r2_reg_n_0),
        .D(p_55_out),
        .Q(compare_err_pb[2]),
        .R(p_66_out));
  LUT6 #(
    .INIT(64'hFFFFFFFFBEFFFFBE)) 
    \cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_1 
       (.I0(\cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_2_n_0 ),
        .I1(p_1_in188_in[3]),
        .I2(p_0_in187_in[3]),
        .I3(p_1_in167_in[3]),
        .I4(p_0_in166_in[3]),
        .I5(\cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_3_n_0 ),
        .O(p_46_out));
  LUT4 #(
    .INIT(16'h6FF6)) 
    \cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_2 
       (.I0(p_1_in170_in[3]),
        .I1(p_0_in169_in[3]),
        .I2(p_1_in173_in[3]),
        .I3(p_0_in172_in[3]),
        .O(\cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF6FF6)) 
    \cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_3 
       (.I0(p_0_in178_in[3]),
        .I1(p_1_in179_in[3]),
        .I2(p_0_in175_in[3]),
        .I3(p_1_in176_in[3]),
        .I4(\cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_4_n_0 ),
        .O(\cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_3_n_0 ));
  LUT4 #(
    .INIT(16'h6FF6)) 
    \cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_4 
       (.I0(p_1_in182_in[3]),
        .I1(p_0_in181_in[3]),
        .I2(p_1_in185_in[3]),
        .I3(p_0_in184_in[3]),
        .O(\cmp_err_pb_4to1.(null)[3].compare_err_pb[3]_i_4_n_0 ));
  FDRE \cmp_err_pb_4to1.(null)[3].compare_err_pb_reg[3] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(rd_valid_r2_reg_n_0),
        .D(p_46_out),
        .Q(compare_err_pb[3]),
        .R(p_66_out));
  LUT6 #(
    .INIT(64'hFFFFFFFFBEFFFFBE)) 
    \cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_1 
       (.I0(\cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_2_n_0 ),
        .I1(p_1_in188_in[4]),
        .I2(p_0_in187_in[4]),
        .I3(p_1_in167_in[4]),
        .I4(p_0_in166_in[4]),
        .I5(\cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_3_n_0 ),
        .O(p_37_out));
  LUT4 #(
    .INIT(16'h6FF6)) 
    \cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_2 
       (.I0(p_1_in170_in[4]),
        .I1(p_0_in169_in[4]),
        .I2(p_1_in173_in[4]),
        .I3(p_0_in172_in[4]),
        .O(\cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF6FF6)) 
    \cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_3 
       (.I0(p_0_in178_in[4]),
        .I1(p_1_in179_in[4]),
        .I2(p_0_in175_in[4]),
        .I3(p_1_in176_in[4]),
        .I4(\cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_4_n_0 ),
        .O(\cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_3_n_0 ));
  LUT4 #(
    .INIT(16'h6FF6)) 
    \cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_4 
       (.I0(p_1_in182_in[4]),
        .I1(p_0_in181_in[4]),
        .I2(p_1_in185_in[4]),
        .I3(p_0_in184_in[4]),
        .O(\cmp_err_pb_4to1.(null)[4].compare_err_pb[4]_i_4_n_0 ));
  FDRE \cmp_err_pb_4to1.(null)[4].compare_err_pb_reg[4] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(rd_valid_r2_reg_n_0),
        .D(p_37_out),
        .Q(compare_err_pb[4]),
        .R(p_66_out));
  LUT6 #(
    .INIT(64'hFFFFFFFFBEFFFFBE)) 
    \cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_1 
       (.I0(\cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_2_n_0 ),
        .I1(p_1_in173_in[5]),
        .I2(p_0_in172_in[5]),
        .I3(p_1_in188_in[5]),
        .I4(p_0_in187_in[5]),
        .I5(\cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_3_n_0 ),
        .O(p_28_out));
  LUT4 #(
    .INIT(16'h6FF6)) 
    \cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_2 
       (.I0(p_1_in167_in[5]),
        .I1(p_0_in166_in[5]),
        .I2(p_1_in170_in[5]),
        .I3(p_0_in169_in[5]),
        .O(\cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF6FF6)) 
    \cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_3 
       (.I0(p_0_in178_in[5]),
        .I1(p_1_in179_in[5]),
        .I2(p_0_in175_in[5]),
        .I3(p_1_in176_in[5]),
        .I4(\cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_4_n_0 ),
        .O(\cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_3_n_0 ));
  LUT4 #(
    .INIT(16'h6FF6)) 
    \cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_4 
       (.I0(p_1_in182_in[5]),
        .I1(p_0_in181_in[5]),
        .I2(p_1_in185_in[5]),
        .I3(p_0_in184_in[5]),
        .O(\cmp_err_pb_4to1.(null)[5].compare_err_pb[5]_i_4_n_0 ));
  FDRE \cmp_err_pb_4to1.(null)[5].compare_err_pb_reg[5] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(rd_valid_r2_reg_n_0),
        .D(p_28_out),
        .Q(compare_err_pb[5]),
        .R(p_66_out));
  LUT6 #(
    .INIT(64'hFFFFFFFFBEFFFFBE)) 
    \cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_1 
       (.I0(\cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_2_n_0 ),
        .I1(p_1_in188_in[6]),
        .I2(p_0_in187_in[6]),
        .I3(p_1_in176_in[6]),
        .I4(p_0_in175_in[6]),
        .I5(\cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_3_n_0 ),
        .O(p_19_out));
  LUT4 #(
    .INIT(16'h6FF6)) 
    \cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_2 
       (.I0(p_1_in185_in[6]),
        .I1(p_0_in184_in[6]),
        .I2(p_1_in182_in[6]),
        .I3(p_0_in181_in[6]),
        .O(\cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF6FF6)) 
    \cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_3 
       (.I0(p_0_in169_in[6]),
        .I1(p_1_in170_in[6]),
        .I2(p_0_in166_in[6]),
        .I3(p_1_in167_in[6]),
        .I4(\cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_4_n_0 ),
        .O(\cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_3_n_0 ));
  LUT4 #(
    .INIT(16'h6FF6)) 
    \cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_4 
       (.I0(p_1_in173_in[6]),
        .I1(p_0_in172_in[6]),
        .I2(p_1_in179_in[6]),
        .I3(p_0_in178_in[6]),
        .O(\cmp_err_pb_4to1.(null)[6].compare_err_pb[6]_i_4_n_0 ));
  FDRE \cmp_err_pb_4to1.(null)[6].compare_err_pb_reg[6] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(rd_valid_r2_reg_n_0),
        .D(p_19_out),
        .Q(compare_err_pb[6]),
        .R(p_66_out));
  LUT6 #(
    .INIT(64'hFFFFFFFFBEFFFFBE)) 
    \cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_1 
       (.I0(\cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_2_n_0 ),
        .I1(p_1_in188_in[7]),
        .I2(p_0_in187_in[7]),
        .I3(p_1_in167_in[7]),
        .I4(p_0_in166_in[7]),
        .I5(\cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_3_n_0 ),
        .O(p_10_out));
  LUT4 #(
    .INIT(16'h6FF6)) 
    \cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_2 
       (.I0(p_1_in173_in[7]),
        .I1(p_0_in172_in[7]),
        .I2(p_1_in176_in[7]),
        .I3(p_0_in175_in[7]),
        .O(\cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF6FF6)) 
    \cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_3 
       (.I0(p_0_in169_in[7]),
        .I1(p_1_in170_in[7]),
        .I2(p_0_in184_in[7]),
        .I3(p_1_in185_in[7]),
        .I4(\cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_4_n_0 ),
        .O(\cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_3_n_0 ));
  LUT4 #(
    .INIT(16'h6FF6)) 
    \cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_4 
       (.I0(p_1_in182_in[7]),
        .I1(p_0_in181_in[7]),
        .I2(p_1_in179_in[7]),
        .I3(p_0_in178_in[7]),
        .O(\cmp_err_pb_4to1.(null)[7].compare_err_pb[7]_i_4_n_0 ));
  FDRE \cmp_err_pb_4to1.(null)[7].compare_err_pb_reg[7] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(rd_valid_r2_reg_n_0),
        .D(p_10_out),
        .Q(compare_err_pb[7]),
        .R(p_66_out));
  (* SOFT_HLUTNM = "soft_lutpair22" *) 
  LUT5 #(
    .INIT(32'h80000000)) 
    cnt_wait_state_i_1
       (.I0(wait_state_cnt_r_reg[3]),
        .I1(wait_state_cnt_en_r),
        .I2(wait_state_cnt_r_reg[0]),
        .I3(wait_state_cnt_r_reg[1]),
        .I4(wait_state_cnt_r_reg[2]),
        .O(cnt_wait_state_i_1_n_0));
  FDRE cnt_wait_state_reg
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(cnt_wait_state_i_1_n_0),
        .Q(cnt_wait_state),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000003000000020)) 
    compare_err_latch_i_1
       (.I0(\cmp_err_4to1.compare_err_reg_n_0 ),
        .I1(prbs_state_r[0]),
        .I2(\prbs_state_r[3]_i_4_n_0 ),
        .I3(prbs_state_r[4]),
        .I4(prbs_state_r[3]),
        .I5(compare_err_latch_reg_n_0),
        .O(compare_err_latch_i_1_n_0));
  FDRE compare_err_latch_reg
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(compare_err_latch_i_1_n_0),
        .Q(compare_err_latch_reg_n_0),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h000000AB)) 
    compare_err_pb_and_i_1
       (.I0(compare_err_pb_and_reg_n_0),
        .I1(compare_err_pb_and_i_2_n_0),
        .I2(compare_err_pb_and_i_3_n_0),
        .I3(\rd_victim_sel_reg[2]_1 ),
        .I4(\genblk7[0].compare_err_pb_latch_r[0]_i_1_n_0 ),
        .O(compare_err_pb_and_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair66" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    compare_err_pb_and_i_2
       (.I0(compare_err_pb[1]),
        .I1(compare_err_pb[0]),
        .I2(compare_err_pb[3]),
        .I3(compare_err_pb[2]),
        .O(compare_err_pb_and_i_2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair63" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    compare_err_pb_and_i_3
       (.I0(compare_err_pb[5]),
        .I1(compare_err_pb[4]),
        .I2(compare_err_pb[7]),
        .I3(compare_err_pb[6]),
        .O(compare_err_pb_and_i_3_n_0));
  FDRE compare_err_pb_and_reg
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(compare_err_pb_and_i_1_n_0),
        .Q(compare_err_pb_and_reg_n_0),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h000000FE)) 
    compare_err_pb_or_i_1
       (.I0(sel0[0]),
        .I1(compare_err_pb_or_i_2_n_0),
        .I2(compare_err_pb_or_i_3_n_0),
        .I3(\rd_victim_sel_reg[2]_1 ),
        .I4(\genblk7[0].compare_err_pb_latch_r[0]_i_1_n_0 ),
        .O(compare_err_pb_or_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair66" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    compare_err_pb_or_i_2
       (.I0(compare_err_pb[1]),
        .I1(compare_err_pb[0]),
        .I2(compare_err_pb[3]),
        .I3(compare_err_pb[2]),
        .O(compare_err_pb_or_i_2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair63" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    compare_err_pb_or_i_3
       (.I0(compare_err_pb[5]),
        .I1(compare_err_pb[4]),
        .I2(compare_err_pb[7]),
        .I3(compare_err_pb[6]),
        .O(compare_err_pb_or_i_3_n_0));
  FDRE compare_err_pb_or_reg
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(compare_err_pb_or_i_1_n_0),
        .Q(sel0[0]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hAAAAAABFAAAAAA80)) 
    complex_pi_incdec_done_i_1
       (.I0(complex_pi_incdec_done_i_2_n_0),
        .I1(complex_pi_incdec_done_i_3_n_0),
        .I2(complex_pi_incdec_done_i_4_n_0),
        .I3(complex_pi_incdec_done_i_5_n_0),
        .I4(complex_pi_incdec_done_i_6_n_0),
        .I5(complex_pi_incdec_done),
        .O(complex_pi_incdec_done_i_1_n_0));
  LUT6 #(
    .INIT(64'hA0A2A2A2A0AEA2A2)) 
    complex_pi_incdec_done_i_2
       (.I0(cnt_wait_state),
        .I1(prbs_state_r[1]),
        .I2(prbs_state_r[2]),
        .I3(prbs_state_r[4]),
        .I4(prbs_state_r[0]),
        .I5(prbs_state_r[3]),
        .O(complex_pi_incdec_done_i_2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair18" *) 
  LUT2 #(
    .INIT(4'h2)) 
    complex_pi_incdec_done_i_3
       (.I0(prbs_state_r[1]),
        .I1(prbs_state_r[4]),
        .O(complex_pi_incdec_done_i_3_n_0));
  LUT6 #(
    .INIT(64'h0A5A0A0A15150505)) 
    complex_pi_incdec_done_i_4
       (.I0(prbs_state_r[0]),
        .I1(\prbs_state_r[2]_i_5_n_0 ),
        .I2(prbs_state_r[2]),
        .I3(\fine_pi_dec_cnt[5]_i_4_n_0 ),
        .I4(cnt_wait_state),
        .I5(prbs_state_r[3]),
        .O(complex_pi_incdec_done_i_4_n_0));
  LUT6 #(
    .INIT(64'h0000080000000000)) 
    complex_pi_incdec_done_i_5
       (.I0(\prbs_dec_tap_cnt[5]_i_3_n_0 ),
        .I1(prbs_state_r[2]),
        .I2(prbs_state_r[0]),
        .I3(cnt_wait_state),
        .I4(prbs_state_r[4]),
        .I5(complex_pi_incdec_done_i_7_n_0),
        .O(complex_pi_incdec_done_i_5_n_0));
  LUT6 #(
    .INIT(64'h000001000000FFFF)) 
    complex_pi_incdec_done_i_6
       (.I0(\prbs_state_r[3]_i_6_n_0 ),
        .I1(prbs_state_r[4]),
        .I2(prbs_state_r[3]),
        .I3(prbs_state_r[1]),
        .I4(prbs_state_r[2]),
        .I5(complex_pi_incdec_done_i_8_n_0),
        .O(complex_pi_incdec_done_i_6_n_0));
  (* SOFT_HLUTNM = "soft_lutpair21" *) 
  LUT2 #(
    .INIT(4'h1)) 
    complex_pi_incdec_done_i_7
       (.I0(prbs_state_r[3]),
        .I1(prbs_state_r[1]),
        .O(complex_pi_incdec_done_i_7_n_0));
  LUT6 #(
    .INIT(64'hEEEEEEEEEEEFEFFF)) 
    complex_pi_incdec_done_i_8
       (.I0(prbs_state_r[3]),
        .I1(prbs_state_r[1]),
        .I2(prbs_state_r[4]),
        .I3(cnt_wait_state),
        .I4(prbs_state_r[0]),
        .I5(prbs_state_r[2]),
        .O(complex_pi_incdec_done_i_8_n_0));
  FDRE complex_pi_incdec_done_reg
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(complex_pi_incdec_done_i_1_n_0),
        .Q(complex_pi_incdec_done),
        .R(\match_flag_and_reg[7]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    complex_victim_inc_i_1
       (.I0(\samples_cnt_r_reg[11]_0 ),
        .O(complex_victim_inc));
  FDRE complex_victim_inc_reg
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(complex_victim_inc),
        .Q(complex_victim_inc_reg_0),
        .R(\samples_cnt_r_reg[0]_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFB3000000)) 
    edge_det_error_i_1
       (.I0(edge_det_error_i_2_n_0),
        .I1(prbs_found_1st_edge_r_reg_n_0),
        .I2(prbs_found_2nd_edge_r_reg_n_0),
        .I3(edge_det_error_i_3_n_0),
        .I4(edge_det_error_i_4_n_0),
        .I5(edge_det_error_reg_n_0),
        .O(edge_det_error_i_1_n_0));
  LUT5 #(
    .INIT(32'hB2BB2222)) 
    edge_det_error_i_2
       (.I0(\prbs_1st_edge_taps_r_reg_n_0_[5] ),
        .I1(prbs_2nd_edge_taps_r[5]),
        .I2(\prbs_1st_edge_taps_r_reg_n_0_[4] ),
        .I3(prbs_2nd_edge_taps_r[4]),
        .I4(edge_det_error_i_5_n_0),
        .O(edge_det_error_i_2_n_0));
  LUT2 #(
    .INIT(4'h1)) 
    edge_det_error_i_3
       (.I0(prbs_state_r[3]),
        .I1(prbs_state_r[4]),
        .O(edge_det_error_i_3_n_0));
  (* SOFT_HLUTNM = "soft_lutpair28" *) 
  LUT3 #(
    .INIT(8'h80)) 
    edge_det_error_i_4
       (.I0(prbs_state_r[2]),
        .I1(prbs_state_r[1]),
        .I2(prbs_state_r[0]),
        .O(edge_det_error_i_4_n_0));
  LUT6 #(
    .INIT(64'h22F2FFFF22F222F2)) 
    edge_det_error_i_5
       (.I0(edge_det_error_i_6_n_0),
        .I1(edge_det_error_i_7_n_0),
        .I2(\prbs_1st_edge_taps_r_reg_n_0_[4] ),
        .I3(prbs_2nd_edge_taps_r[4]),
        .I4(prbs_2nd_edge_taps_r[3]),
        .I5(\prbs_1st_edge_taps_r_reg_n_0_[3] ),
        .O(edge_det_error_i_5_n_0));
  LUT6 #(
    .INIT(64'hD0FDD0FDFFFFD0FD)) 
    edge_det_error_i_6
       (.I0(prbs_2nd_edge_taps_r[0]),
        .I1(\prbs_1st_edge_taps_r_reg_n_0_[0] ),
        .I2(\prbs_1st_edge_taps_r_reg_n_0_[1] ),
        .I3(prbs_2nd_edge_taps_r[1]),
        .I4(\prbs_1st_edge_taps_r_reg_n_0_[2] ),
        .I5(prbs_2nd_edge_taps_r[2]),
        .O(edge_det_error_i_6_n_0));
  LUT4 #(
    .INIT(16'h4F44)) 
    edge_det_error_i_7
       (.I0(\prbs_1st_edge_taps_r_reg_n_0_[3] ),
        .I1(prbs_2nd_edge_taps_r[3]),
        .I2(\prbs_1st_edge_taps_r_reg_n_0_[2] ),
        .I3(prbs_2nd_edge_taps_r[2]),
        .O(edge_det_error_i_7_n_0));
  FDRE edge_det_error_reg
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(edge_det_error_i_1_n_0),
        .Q(edge_det_error_reg_n_0),
        .R(\samples_cnt_r_reg[0]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair22" *) 
  LUT3 #(
    .INIT(8'h7F)) 
    err_chk_invalid_i_1
       (.I0(wait_state_cnt_r_reg[3]),
        .I1(wait_state_cnt_r_reg[2]),
        .I2(wait_state_cnt_r_reg[1]),
        .O(err_chk_invalid_i_1_n_0));
  FDRE err_chk_invalid_reg
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(err_chk_invalid_i_1_n_0),
        .Q(err_chk_invalid),
        .R(1'b0));
  LUT2 #(
    .INIT(4'h7)) 
    fine_inc_stage_i_1
       (.I0(\stage_cnt_reg_n_0_[0] ),
        .I1(\stage_cnt_reg_n_0_[1] ),
        .O(fine_inc_stage_i_1_n_0));
  FDSE fine_inc_stage_reg
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(fine_inc_stage_i_1_n_0),
        .Q(fine_inc_stage_reg_n_0),
        .S(\prbs_dec_tap_cnt_reg[0]_0 ));
  LUT6 #(
    .INIT(64'h00CA003AFFCAFF3A)) 
    \fine_pi_dec_cnt[0]_i_1 
       (.I0(D[0]),
        .I1(\fine_pi_dec_cnt[0]_i_2_n_0 ),
        .I2(prbs_state_r[1]),
        .I3(prbs_state_r[2]),
        .I4(\fine_pi_dec_cnt[0]_i_3_n_0 ),
        .I5(\fine_pi_dec_cnt_reg_n_0_[0] ),
        .O(\fine_pi_dec_cnt[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair40" *) 
  LUT3 #(
    .INIT(8'hFB)) 
    \fine_pi_dec_cnt[0]_i_2 
       (.I0(\fine_pi_dec_cnt_reg[3]_i_7_n_6 ),
        .I1(\stage_cnt_reg_n_0_[1] ),
        .I2(\stage_cnt_reg_n_0_[0] ),
        .O(\fine_pi_dec_cnt[0]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair27" *) 
  LUT4 #(
    .INIT(16'hFB04)) 
    \fine_pi_dec_cnt[0]_i_3 
       (.I0(\stage_cnt_reg_n_0_[0] ),
        .I1(\stage_cnt_reg_n_0_[1] ),
        .I2(\fine_pi_dec_cnt_reg[3]_i_7_n_7 ),
        .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),
        .O(\fine_pi_dec_cnt[0]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair60" *) 
  LUT4 #(
    .INIT(16'hE22E)) 
    \fine_pi_dec_cnt[1]_i_1 
       (.I0(\fine_pi_dec_cnt[1]_i_2_n_0 ),
        .I1(prbs_state_r[2]),
        .I2(\fine_pi_dec_cnt_reg_n_0_[0] ),
        .I3(\fine_pi_dec_cnt_reg_n_0_[1] ),
        .O(\fine_pi_dec_cnt[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hCCC3333CAAAAAAAA)) 
    \fine_pi_dec_cnt[1]_i_2 
       (.I0(D[1]),
        .I1(\fine_pi_dec_cnt[1]_i_3_n_0 ),
        .I2(\fine_pi_dec_cnt[5]_i_11_n_0 ),
        .I3(\fine_pi_dec_cnt_reg[3]_i_7_n_5 ),
        .I4(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),
        .I5(prbs_state_r[1]),
        .O(\fine_pi_dec_cnt[1]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair27" *) 
  LUT5 #(
    .INIT(32'hFBF3FFFB)) 
    \fine_pi_dec_cnt[1]_i_3 
       (.I0(\fine_pi_dec_cnt_reg[3]_i_7_n_6 ),
        .I1(\stage_cnt_reg_n_0_[1] ),
        .I2(\stage_cnt_reg_n_0_[0] ),
        .I3(\fine_pi_dec_cnt_reg[3]_i_7_n_7 ),
        .I4(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),
        .O(\fine_pi_dec_cnt[1]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair19" *) 
  LUT5 #(
    .INIT(32'hFCAA03AA)) 
    \fine_pi_dec_cnt[2]_i_1 
       (.I0(\fine_pi_dec_cnt[2]_i_2_n_0 ),
        .I1(\fine_pi_dec_cnt_reg_n_0_[0] ),
        .I2(\fine_pi_dec_cnt_reg_n_0_[1] ),
        .I3(prbs_state_r[2]),
        .I4(\fine_pi_dec_cnt_reg_n_0_[2] ),
        .O(\fine_pi_dec_cnt[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hCCC3333CAAAAAAAA)) 
    \fine_pi_dec_cnt[2]_i_2 
       (.I0(D[2]),
        .I1(\fine_pi_dec_cnt[3]_i_8_n_0 ),
        .I2(\fine_pi_dec_cnt[5]_i_11_n_0 ),
        .I3(\fine_pi_dec_cnt_reg[3]_i_7_n_4 ),
        .I4(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),
        .I5(prbs_state_r[1]),
        .O(\fine_pi_dec_cnt[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFAAEAAABA)) 
    \fine_pi_dec_cnt[3]_i_1 
       (.I0(\fine_pi_dec_cnt[3]_i_2_n_0 ),
        .I1(\fine_pi_dec_cnt[3]_i_3_n_0 ),
        .I2(prbs_state_r[1]),
        .I3(prbs_state_r[2]),
        .I4(\fine_pi_dec_cnt[3]_i_4_n_0 ),
        .I5(\fine_pi_dec_cnt[3]_i_5_n_0 ),
        .O(\fine_pi_dec_cnt[3]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \fine_pi_dec_cnt[3]_i_10 
       (.I0(\smallest_right_edge_reg_n_0_[2] ),
        .I1(\largest_left_edge_reg_n_0_[2] ),
        .O(\fine_pi_dec_cnt[3]_i_10_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \fine_pi_dec_cnt[3]_i_11 
       (.I0(\smallest_right_edge_reg_n_0_[1] ),
        .I1(\largest_left_edge_reg_n_0_[1] ),
        .O(\fine_pi_dec_cnt[3]_i_11_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \fine_pi_dec_cnt[3]_i_12 
       (.I0(\smallest_right_edge_reg_n_0_[0] ),
        .I1(\largest_left_edge_reg_n_0_[0] ),
        .O(\fine_pi_dec_cnt[3]_i_12_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair16" *) 
  LUT5 #(
    .INIT(32'h880F8800)) 
    \fine_pi_dec_cnt[3]_i_2 
       (.I0(\fine_pi_dec_cnt[3]_i_6_n_0 ),
        .I1(\fine_pi_dec_cnt_reg_n_0_[3] ),
        .I2(prbs_state_r[1]),
        .I3(prbs_state_r[2]),
        .I4(D[3]),
        .O(\fine_pi_dec_cnt[3]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h04FB40BF04FB04FB)) 
    \fine_pi_dec_cnt[3]_i_3 
       (.I0(\stage_cnt_reg_n_0_[0] ),
        .I1(\stage_cnt_reg_n_0_[1] ),
        .I2(\fine_pi_dec_cnt_reg[5]_i_10_n_7 ),
        .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[3] ),
        .I4(\fine_pi_dec_cnt_reg[3]_i_7_n_4 ),
        .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),
        .O(\fine_pi_dec_cnt[3]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair33" *) 
  LUT5 #(
    .INIT(32'h55450010)) 
    \fine_pi_dec_cnt[3]_i_4 
       (.I0(\fine_pi_dec_cnt[3]_i_8_n_0 ),
        .I1(\stage_cnt_reg_n_0_[0] ),
        .I2(\stage_cnt_reg_n_0_[1] ),
        .I3(\fine_pi_dec_cnt_reg[3]_i_7_n_4 ),
        .I4(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),
        .O(\fine_pi_dec_cnt[3]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair37" *) 
  LUT5 #(
    .INIT(32'h00000004)) 
    \fine_pi_dec_cnt[3]_i_5 
       (.I0(\fine_pi_dec_cnt_reg_n_0_[3] ),
        .I1(prbs_state_r[2]),
        .I2(\fine_pi_dec_cnt_reg_n_0_[0] ),
        .I3(\fine_pi_dec_cnt_reg_n_0_[1] ),
        .I4(\fine_pi_dec_cnt_reg_n_0_[2] ),
        .O(\fine_pi_dec_cnt[3]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair19" *) 
  LUT3 #(
    .INIT(8'hFE)) 
    \fine_pi_dec_cnt[3]_i_6 
       (.I0(\fine_pi_dec_cnt_reg_n_0_[2] ),
        .I1(\fine_pi_dec_cnt_reg_n_0_[1] ),
        .I2(\fine_pi_dec_cnt_reg_n_0_[0] ),
        .O(\fine_pi_dec_cnt[3]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hECFECCCCFFFFECFE)) 
    \fine_pi_dec_cnt[3]_i_8 
       (.I0(\fine_pi_dec_cnt_reg[3]_i_7_n_6 ),
        .I1(\fine_pi_dec_cnt[5]_i_11_n_0 ),
        .I2(\fine_pi_dec_cnt_reg[3]_i_7_n_7 ),
        .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),
        .I4(\fine_pi_dec_cnt_reg[3]_i_7_n_5 ),
        .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),
        .O(\fine_pi_dec_cnt[3]_i_8_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \fine_pi_dec_cnt[3]_i_9 
       (.I0(\smallest_right_edge_reg_n_0_[3] ),
        .I1(\largest_left_edge_reg_n_0_[3] ),
        .O(\fine_pi_dec_cnt[3]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hEAAEEAAEFBBFEAAE)) 
    \fine_pi_dec_cnt[4]_i_1 
       (.I0(\fine_pi_dec_cnt[4]_i_2_n_0 ),
        .I1(prbs_state_r[2]),
        .I2(\fine_pi_dec_cnt[4]_i_3_n_0 ),
        .I3(\fine_pi_dec_cnt_reg_n_0_[4] ),
        .I4(D[4]),
        .I5(prbs_state_r[1]),
        .O(\fine_pi_dec_cnt[4]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair52" *) 
  LUT4 #(
    .INIT(16'h2002)) 
    \fine_pi_dec_cnt[4]_i_2 
       (.I0(prbs_state_r[1]),
        .I1(prbs_state_r[2]),
        .I2(\fine_pi_dec_cnt[4]_i_4_n_0 ),
        .I3(\fine_pi_dec_cnt[5]_i_9_n_0 ),
        .O(\fine_pi_dec_cnt[4]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair37" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    \fine_pi_dec_cnt[4]_i_3 
       (.I0(\fine_pi_dec_cnt_reg_n_0_[3] ),
        .I1(\fine_pi_dec_cnt_reg_n_0_[0] ),
        .I2(\fine_pi_dec_cnt_reg_n_0_[1] ),
        .I3(\fine_pi_dec_cnt_reg_n_0_[2] ),
        .O(\fine_pi_dec_cnt[4]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h5565556555955565)) 
    \fine_pi_dec_cnt[4]_i_4 
       (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),
        .I1(\fine_pi_dec_cnt_reg[5]_i_10_n_6 ),
        .I2(\stage_cnt_reg_n_0_[1] ),
        .I3(\stage_cnt_reg_n_0_[0] ),
        .I4(\fine_pi_dec_cnt_reg[5]_i_10_n_7 ),
        .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[3] ),
        .O(\fine_pi_dec_cnt[4]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFBAAAAAAEAAAAAAA)) 
    \fine_pi_dec_cnt[5]_i_1 
       (.I0(\fine_pi_dec_cnt[5]_i_3_n_0 ),
        .I1(prbs_state_r[2]),
        .I2(\fine_pi_dec_cnt[5]_i_4_n_0 ),
        .I3(\fine_pi_dec_cnt[5]_i_5_n_0 ),
        .I4(\prbs_state_r[0]_i_2_n_0 ),
        .I5(cnt_wait_state),
        .O(fine_pi_dec_cnt));
  (* SOFT_HLUTNM = "soft_lutpair33" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \fine_pi_dec_cnt[5]_i_11 
       (.I0(\stage_cnt_reg_n_0_[0] ),
        .I1(\stage_cnt_reg_n_0_[1] ),
        .O(\fine_pi_dec_cnt[5]_i_11_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair40" *) 
  LUT4 #(
    .INIT(16'h0B00)) 
    \fine_pi_dec_cnt[5]_i_12 
       (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[3] ),
        .I1(\fine_pi_dec_cnt_reg[5]_i_10_n_7 ),
        .I2(\stage_cnt_reg_n_0_[0] ),
        .I3(\stage_cnt_reg_n_0_[1] ),
        .O(\fine_pi_dec_cnt[5]_i_12_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \fine_pi_dec_cnt[5]_i_13 
       (.I0(\smallest_right_edge_reg_n_0_[5] ),
        .I1(\largest_left_edge_reg_n_0_[5] ),
        .O(\fine_pi_dec_cnt[5]_i_13_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \fine_pi_dec_cnt[5]_i_14 
       (.I0(\smallest_right_edge_reg_n_0_[4] ),
        .I1(\largest_left_edge_reg_n_0_[4] ),
        .O(\fine_pi_dec_cnt[5]_i_14_n_0 ));
  LUT6 #(
    .INIT(64'h88BBBB88B8B8B8B8)) 
    \fine_pi_dec_cnt[5]_i_2 
       (.I0(\fine_pi_dec_cnt[5]_i_6_n_0 ),
        .I1(prbs_state_r[2]),
        .I2(D[5]),
        .I3(\fine_pi_dec_cnt[5]_i_7_n_0 ),
        .I4(\fine_pi_dec_cnt[5]_i_8_n_0 ),
        .I5(prbs_state_r[1]),
        .O(\fine_pi_dec_cnt[5]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h000C000000000002)) 
    \fine_pi_dec_cnt[5]_i_3 
       (.I0(new_cnt_dqs_r_reg_1),
        .I1(prbs_state_r[1]),
        .I2(prbs_state_r[2]),
        .I3(prbs_state_r[3]),
        .I4(prbs_state_r[0]),
        .I5(prbs_state_r[4]),
        .O(\fine_pi_dec_cnt[5]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \fine_pi_dec_cnt[5]_i_4 
       (.I0(\fine_pi_dec_cnt_reg_n_0_[3] ),
        .I1(\fine_pi_dec_cnt_reg_n_0_[0] ),
        .I2(\fine_pi_dec_cnt_reg_n_0_[1] ),
        .I3(\fine_pi_dec_cnt_reg_n_0_[2] ),
        .I4(\fine_pi_dec_cnt_reg_n_0_[4] ),
        .I5(\fine_pi_dec_cnt_reg_n_0_[5] ),
        .O(\fine_pi_dec_cnt[5]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair43" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \fine_pi_dec_cnt[5]_i_5 
       (.I0(prbs_state_r[3]),
        .I1(prbs_state_r[4]),
        .O(\fine_pi_dec_cnt[5]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAAAA9)) 
    \fine_pi_dec_cnt[5]_i_6 
       (.I0(\fine_pi_dec_cnt_reg_n_0_[5] ),
        .I1(\fine_pi_dec_cnt_reg_n_0_[4] ),
        .I2(\fine_pi_dec_cnt_reg_n_0_[2] ),
        .I3(\fine_pi_dec_cnt_reg_n_0_[1] ),
        .I4(\fine_pi_dec_cnt_reg_n_0_[0] ),
        .I5(\fine_pi_dec_cnt_reg_n_0_[3] ),
        .O(\fine_pi_dec_cnt[5]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hAA8AAA200020008A)) 
    \fine_pi_dec_cnt[5]_i_7 
       (.I0(\fine_pi_dec_cnt[5]_i_9_n_0 ),
        .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[3] ),
        .I2(\fine_pi_dec_cnt_reg[5]_i_10_n_7 ),
        .I3(\fine_pi_dec_cnt[5]_i_11_n_0 ),
        .I4(\fine_pi_dec_cnt_reg[5]_i_10_n_6 ),
        .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),
        .O(\fine_pi_dec_cnt[5]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h3936C9C9C9C9C6C9)) 
    \fine_pi_dec_cnt[5]_i_8 
       (.I0(\fine_pi_dec_cnt_reg[5]_i_10_n_1 ),
        .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),
        .I2(\fine_pi_dec_cnt[5]_i_11_n_0 ),
        .I3(\fine_pi_dec_cnt_reg[5]_i_10_n_6 ),
        .I4(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),
        .I5(\fine_pi_dec_cnt[5]_i_12_n_0 ),
        .O(\fine_pi_dec_cnt[5]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'h006600F6A0F6A0FF)) 
    \fine_pi_dec_cnt[5]_i_9 
       (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[3] ),
        .I1(\fine_pi_dec_cnt_reg[5]_i_10_n_7 ),
        .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),
        .I3(\fine_pi_dec_cnt[5]_i_11_n_0 ),
        .I4(\fine_pi_dec_cnt_reg[3]_i_7_n_4 ),
        .I5(\fine_pi_dec_cnt[3]_i_8_n_0 ),
        .O(\fine_pi_dec_cnt[5]_i_9_n_0 ));
  FDRE \fine_pi_dec_cnt_reg[0] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(fine_pi_dec_cnt),
        .D(\fine_pi_dec_cnt[0]_i_1_n_0 ),
        .Q(\fine_pi_dec_cnt_reg_n_0_[0] ),
        .R(\samples_cnt_r_reg[0]_0 ));
  FDRE \fine_pi_dec_cnt_reg[1] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(fine_pi_dec_cnt),
        .D(\fine_pi_dec_cnt[1]_i_1_n_0 ),
        .Q(\fine_pi_dec_cnt_reg_n_0_[1] ),
        .R(\samples_cnt_r_reg[0]_0 ));
  FDRE \fine_pi_dec_cnt_reg[2] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(fine_pi_dec_cnt),
        .D(\fine_pi_dec_cnt[2]_i_1_n_0 ),
        .Q(\fine_pi_dec_cnt_reg_n_0_[2] ),
        .R(\samples_cnt_r_reg[0]_0 ));
  FDRE \fine_pi_dec_cnt_reg[3] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(fine_pi_dec_cnt),
        .D(\fine_pi_dec_cnt[3]_i_1_n_0 ),
        .Q(\fine_pi_dec_cnt_reg_n_0_[3] ),
        .R(\samples_cnt_r_reg[0]_0 ));
  CARRY4 \fine_pi_dec_cnt_reg[3]_i_7 
       (.CI(1'b0),
        .CO({\fine_pi_dec_cnt_reg[3]_i_7_n_0 ,\fine_pi_dec_cnt_reg[3]_i_7_n_1 ,\fine_pi_dec_cnt_reg[3]_i_7_n_2 ,\fine_pi_dec_cnt_reg[3]_i_7_n_3 }),
        .CYINIT(1'b0),
        .DI({\smallest_right_edge_reg_n_0_[3] ,\smallest_right_edge_reg_n_0_[2] ,\smallest_right_edge_reg_n_0_[1] ,\smallest_right_edge_reg_n_0_[0] }),
        .O({\fine_pi_dec_cnt_reg[3]_i_7_n_4 ,\fine_pi_dec_cnt_reg[3]_i_7_n_5 ,\fine_pi_dec_cnt_reg[3]_i_7_n_6 ,\fine_pi_dec_cnt_reg[3]_i_7_n_7 }),
        .S({\fine_pi_dec_cnt[3]_i_9_n_0 ,\fine_pi_dec_cnt[3]_i_10_n_0 ,\fine_pi_dec_cnt[3]_i_11_n_0 ,\fine_pi_dec_cnt[3]_i_12_n_0 }));
  FDRE \fine_pi_dec_cnt_reg[4] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(fine_pi_dec_cnt),
        .D(\fine_pi_dec_cnt[4]_i_1_n_0 ),
        .Q(\fine_pi_dec_cnt_reg_n_0_[4] ),
        .R(\samples_cnt_r_reg[0]_0 ));
  FDRE \fine_pi_dec_cnt_reg[5] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(fine_pi_dec_cnt),
        .D(\fine_pi_dec_cnt[5]_i_2_n_0 ),
        .Q(\fine_pi_dec_cnt_reg_n_0_[5] ),
        .R(\samples_cnt_r_reg[0]_0 ));
  CARRY4 \fine_pi_dec_cnt_reg[5]_i_10 
       (.CI(\fine_pi_dec_cnt_reg[3]_i_7_n_0 ),
        .CO({\NLW_fine_pi_dec_cnt_reg[5]_i_10_CO_UNCONNECTED [3],\fine_pi_dec_cnt_reg[5]_i_10_n_1 ,\NLW_fine_pi_dec_cnt_reg[5]_i_10_CO_UNCONNECTED [1],\fine_pi_dec_cnt_reg[5]_i_10_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,\smallest_right_edge_reg_n_0_[5] ,\smallest_right_edge_reg_n_0_[4] }),
        .O({\NLW_fine_pi_dec_cnt_reg[5]_i_10_O_UNCONNECTED [3:2],\fine_pi_dec_cnt_reg[5]_i_10_n_6 ,\fine_pi_dec_cnt_reg[5]_i_10_n_7 }),
        .S({1'b0,1'b1,\fine_pi_dec_cnt[5]_i_13_n_0 ,\fine_pi_dec_cnt[5]_i_14_n_0 }));
  (* SOFT_HLUTNM = "soft_lutpair34" *) 
  LUT5 #(
    .INIT(32'h0808FB08)) 
    \gen_byte_sel_div2.byte_sel_cnt[0]_i_2 
       (.I0(\prbs_dqs_cnt_r_reg_n_0_[0] ),
        .I1(\gen_byte_sel_div2.byte_sel_cnt_reg[0] ),
        .I2(prbs_rdlvl_done_reg_0),
        .I3(Q[0]),
        .I4(\gen_byte_sel_div2.byte_sel_cnt_reg[0]_0 ),
        .O(\prbs_dqs_cnt_r_reg[0]_0 ));
  LUT5 #(
    .INIT(32'h0808FB08)) 
    \gen_byte_sel_div2.byte_sel_cnt[1]_i_2 
       (.I0(\prbs_dqs_cnt_r_reg_n_0_[1] ),
        .I1(\gen_byte_sel_div2.byte_sel_cnt_reg[0] ),
        .I2(prbs_rdlvl_done_reg_0),
        .I3(Q[1]),
        .I4(\gen_byte_sel_div2.byte_sel_cnt_reg[0]_0 ),
        .O(\prbs_dqs_cnt_r_reg[1]_0 ));
  LUT5 #(
    .INIT(32'h0808FB08)) 
    \gen_byte_sel_div2.byte_sel_cnt[2]_i_2 
       (.I0(\prbs_dqs_cnt_r_reg_n_0_[2] ),
        .I1(\gen_byte_sel_div2.byte_sel_cnt_reg[0] ),
        .I2(prbs_rdlvl_done_reg_0),
        .I3(Q[2]),
        .I4(\gen_byte_sel_div2.byte_sel_cnt_reg[0]_0 ),
        .O(\prbs_dqs_cnt_r_reg[2]_0 ));
  LUT5 #(
    .INIT(32'h0808FB08)) 
    \gen_byte_sel_div2.byte_sel_cnt[3]_i_5 
       (.I0(\prbs_dqs_cnt_r_reg_n_0_[3] ),
        .I1(\gen_byte_sel_div2.byte_sel_cnt_reg[0] ),
        .I2(prbs_rdlvl_done_reg_0),
        .I3(Q[3]),
        .I4(\gen_byte_sel_div2.byte_sel_cnt_reg[0]_0 ),
        .O(\prbs_dqs_cnt_r_reg[3]_0 ));
  FDRE \gen_mux_div4.gen_rd_4[0].mux_rd_fall0_r2_reg[0] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(mux_rd_valid_r),
        .D(mux_rd_fall0_r1),
        .Q(mux_rd_fall0_r2),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[0].mux_rd_fall0_r3_reg[0] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(mux_rd_fall0_r2),
        .Q(p_1_in185_in[0]),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[0].mux_rd_fall1_r2_reg[0] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(mux_rd_valid_r),
        .D(mux_rd_fall1_r1),
        .Q(mux_rd_fall1_r2),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[0].mux_rd_fall1_r3_reg[0] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(mux_rd_fall1_r2),
        .Q(p_1_in179_in[0]),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[0].mux_rd_fall2_r2_reg[0] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(mux_rd_valid_r),
        .D(mux_rd_fall2_r1),
        .Q(mux_rd_fall2_r2),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[0].mux_rd_fall2_r3_reg[0] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(mux_rd_fall2_r2),
        .Q(p_1_in173_in[0]),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[0].mux_rd_fall3_r2_reg[0] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(mux_rd_valid_r),
        .D(mux_rd_fall3_r1),
        .Q(mux_rd_fall3_r2),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[0].mux_rd_fall3_r3_reg[0] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(mux_rd_fall3_r2),
        .Q(p_1_in167_in[0]),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[0].mux_rd_rise0_r2_reg[0] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(mux_rd_valid_r),
        .D(mux_rd_rise0_r1),
        .Q(mux_rd_rise0_r2),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[0].mux_rd_rise0_r3_reg[0] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(mux_rd_rise0_r2),
        .Q(p_1_in188_in[0]),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[0].mux_rd_rise1_r2_reg[0] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(mux_rd_valid_r),
        .D(mux_rd_rise1_r1),
        .Q(mux_rd_rise1_r2),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[0].mux_rd_rise1_r3_reg[0] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(mux_rd_rise1_r2),
        .Q(p_1_in182_in[0]),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[0].mux_rd_rise2_r2_reg[0] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(mux_rd_valid_r),
        .D(mux_rd_rise2_r1),
        .Q(mux_rd_rise2_r2),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[0].mux_rd_rise2_r3_reg[0] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(mux_rd_rise2_r2),
        .Q(p_1_in176_in[0]),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[0].mux_rd_rise3_r2_reg[0] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(mux_rd_valid_r),
        .D(mux_rd_rise3_r1),
        .Q(mux_rd_rise3_r2),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[0].mux_rd_rise3_r3_reg[0] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(mux_rd_rise3_r2),
        .Q(p_1_in170_in[0]),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[1].mux_rd_fall0_r2_reg[1] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(mux_rd_valid_r),
        .D(\gen_mux_rd[1].mux_rd_fall0_r1_reg ),
        .Q(\gen_mux_div4.gen_rd_4[1].mux_rd_fall0_r2_reg ),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[1].mux_rd_fall0_r3_reg[1] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_div4.gen_rd_4[1].mux_rd_fall0_r2_reg ),
        .Q(p_1_in185_in[1]),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[1].mux_rd_fall1_r2_reg[1] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(mux_rd_valid_r),
        .D(\gen_mux_rd[1].mux_rd_fall1_r1_reg ),
        .Q(\gen_mux_div4.gen_rd_4[1].mux_rd_fall1_r2_reg ),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[1].mux_rd_fall1_r3_reg[1] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_div4.gen_rd_4[1].mux_rd_fall1_r2_reg ),
        .Q(p_1_in179_in[1]),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[1].mux_rd_fall2_r2_reg[1] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(mux_rd_valid_r),
        .D(\gen_mux_rd[1].mux_rd_fall2_r1_reg ),
        .Q(\gen_mux_div4.gen_rd_4[1].mux_rd_fall2_r2_reg ),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[1].mux_rd_fall2_r3_reg[1] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_div4.gen_rd_4[1].mux_rd_fall2_r2_reg ),
        .Q(p_1_in173_in[1]),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[1].mux_rd_fall3_r2_reg[1] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(mux_rd_valid_r),
        .D(\gen_mux_rd[1].mux_rd_fall3_r1_reg ),
        .Q(\gen_mux_div4.gen_rd_4[1].mux_rd_fall3_r2_reg ),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[1].mux_rd_fall3_r3_reg[1] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_div4.gen_rd_4[1].mux_rd_fall3_r2_reg ),
        .Q(p_1_in167_in[1]),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[1].mux_rd_rise0_r2_reg[1] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(mux_rd_valid_r),
        .D(\gen_mux_rd[1].mux_rd_rise0_r1_reg ),
        .Q(\gen_mux_div4.gen_rd_4[1].mux_rd_rise0_r2_reg ),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[1].mux_rd_rise0_r3_reg[1] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_div4.gen_rd_4[1].mux_rd_rise0_r2_reg ),
        .Q(p_1_in188_in[1]),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[1].mux_rd_rise1_r2_reg[1] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(mux_rd_valid_r),
        .D(\gen_mux_rd[1].mux_rd_rise1_r1_reg ),
        .Q(\gen_mux_div4.gen_rd_4[1].mux_rd_rise1_r2_reg ),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[1].mux_rd_rise1_r3_reg[1] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_div4.gen_rd_4[1].mux_rd_rise1_r2_reg ),
        .Q(p_1_in182_in[1]),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[1].mux_rd_rise2_r2_reg[1] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(mux_rd_valid_r),
        .D(\gen_mux_rd[1].mux_rd_rise2_r1_reg ),
        .Q(\gen_mux_div4.gen_rd_4[1].mux_rd_rise2_r2_reg ),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[1].mux_rd_rise2_r3_reg[1] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_div4.gen_rd_4[1].mux_rd_rise2_r2_reg ),
        .Q(p_1_in176_in[1]),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[1].mux_rd_rise3_r2_reg[1] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(mux_rd_valid_r),
        .D(\gen_mux_rd[1].mux_rd_rise3_r1_reg ),
        .Q(\gen_mux_div4.gen_rd_4[1].mux_rd_rise3_r2_reg ),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[1].mux_rd_rise3_r3_reg[1] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_div4.gen_rd_4[1].mux_rd_rise3_r2_reg ),
        .Q(p_1_in170_in[1]),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[2].mux_rd_fall0_r2_reg[2] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(mux_rd_valid_r),
        .D(\gen_mux_rd[2].mux_rd_fall0_r1_reg ),
        .Q(\gen_mux_div4.gen_rd_4[2].mux_rd_fall0_r2_reg ),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[2].mux_rd_fall0_r3_reg[2] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_div4.gen_rd_4[2].mux_rd_fall0_r2_reg ),
        .Q(p_1_in185_in[2]),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[2].mux_rd_fall1_r2_reg[2] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(mux_rd_valid_r),
        .D(\gen_mux_rd[2].mux_rd_fall1_r1_reg ),
        .Q(\gen_mux_div4.gen_rd_4[2].mux_rd_fall1_r2_reg ),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[2].mux_rd_fall1_r3_reg[2] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_div4.gen_rd_4[2].mux_rd_fall1_r2_reg ),
        .Q(p_1_in179_in[2]),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[2].mux_rd_fall2_r2_reg[2] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(mux_rd_valid_r),
        .D(\gen_mux_rd[2].mux_rd_fall2_r1_reg ),
        .Q(\gen_mux_div4.gen_rd_4[2].mux_rd_fall2_r2_reg ),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[2].mux_rd_fall2_r3_reg[2] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_div4.gen_rd_4[2].mux_rd_fall2_r2_reg ),
        .Q(p_1_in173_in[2]),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[2].mux_rd_fall3_r2_reg[2] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(mux_rd_valid_r),
        .D(\gen_mux_rd[2].mux_rd_fall3_r1_reg ),
        .Q(\gen_mux_div4.gen_rd_4[2].mux_rd_fall3_r2_reg ),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[2].mux_rd_fall3_r3_reg[2] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_div4.gen_rd_4[2].mux_rd_fall3_r2_reg ),
        .Q(p_1_in167_in[2]),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[2].mux_rd_rise0_r2_reg[2] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(mux_rd_valid_r),
        .D(\gen_mux_rd[2].mux_rd_rise0_r1_reg ),
        .Q(\gen_mux_div4.gen_rd_4[2].mux_rd_rise0_r2_reg ),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[2].mux_rd_rise0_r3_reg[2] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_div4.gen_rd_4[2].mux_rd_rise0_r2_reg ),
        .Q(p_1_in188_in[2]),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[2].mux_rd_rise1_r2_reg[2] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(mux_rd_valid_r),
        .D(\gen_mux_rd[2].mux_rd_rise1_r1_reg ),
        .Q(\gen_mux_div4.gen_rd_4[2].mux_rd_rise1_r2_reg ),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[2].mux_rd_rise1_r3_reg[2] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_div4.gen_rd_4[2].mux_rd_rise1_r2_reg ),
        .Q(p_1_in182_in[2]),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[2].mux_rd_rise2_r2_reg[2] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(mux_rd_valid_r),
        .D(\gen_mux_rd[2].mux_rd_rise2_r1_reg ),
        .Q(\gen_mux_div4.gen_rd_4[2].mux_rd_rise2_r2_reg ),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[2].mux_rd_rise2_r3_reg[2] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_div4.gen_rd_4[2].mux_rd_rise2_r2_reg ),
        .Q(p_1_in176_in[2]),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[2].mux_rd_rise3_r2_reg[2] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(mux_rd_valid_r),
        .D(\gen_mux_rd[2].mux_rd_rise3_r1_reg ),
        .Q(\gen_mux_div4.gen_rd_4[2].mux_rd_rise3_r2_reg ),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[2].mux_rd_rise3_r3_reg[2] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_div4.gen_rd_4[2].mux_rd_rise3_r2_reg ),
        .Q(p_1_in170_in[2]),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[3].mux_rd_fall0_r2_reg[3] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(mux_rd_valid_r),
        .D(\gen_mux_rd[3].mux_rd_fall0_r1_reg ),
        .Q(\gen_mux_div4.gen_rd_4[3].mux_rd_fall0_r2_reg ),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[3].mux_rd_fall0_r3_reg[3] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_div4.gen_rd_4[3].mux_rd_fall0_r2_reg ),
        .Q(p_1_in185_in[3]),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[3].mux_rd_fall1_r2_reg[3] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(mux_rd_valid_r),
        .D(\gen_mux_rd[3].mux_rd_fall1_r1_reg ),
        .Q(\gen_mux_div4.gen_rd_4[3].mux_rd_fall1_r2_reg ),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[3].mux_rd_fall1_r3_reg[3] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_div4.gen_rd_4[3].mux_rd_fall1_r2_reg ),
        .Q(p_1_in179_in[3]),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[3].mux_rd_fall2_r2_reg[3] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(mux_rd_valid_r),
        .D(\gen_mux_rd[3].mux_rd_fall2_r1_reg ),
        .Q(\gen_mux_div4.gen_rd_4[3].mux_rd_fall2_r2_reg ),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[3].mux_rd_fall2_r3_reg[3] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_div4.gen_rd_4[3].mux_rd_fall2_r2_reg ),
        .Q(p_1_in173_in[3]),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[3].mux_rd_fall3_r2_reg[3] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(mux_rd_valid_r),
        .D(\gen_mux_rd[3].mux_rd_fall3_r1_reg ),
        .Q(\gen_mux_div4.gen_rd_4[3].mux_rd_fall3_r2_reg ),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[3].mux_rd_fall3_r3_reg[3] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_div4.gen_rd_4[3].mux_rd_fall3_r2_reg ),
        .Q(p_1_in167_in[3]),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[3].mux_rd_rise0_r2_reg[3] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(mux_rd_valid_r),
        .D(\gen_mux_rd[3].mux_rd_rise0_r1_reg ),
        .Q(\gen_mux_div4.gen_rd_4[3].mux_rd_rise0_r2_reg ),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[3].mux_rd_rise0_r3_reg[3] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_div4.gen_rd_4[3].mux_rd_rise0_r2_reg ),
        .Q(p_1_in188_in[3]),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[3].mux_rd_rise1_r2_reg[3] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(mux_rd_valid_r),
        .D(\gen_mux_rd[3].mux_rd_rise1_r1_reg ),
        .Q(\gen_mux_div4.gen_rd_4[3].mux_rd_rise1_r2_reg ),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[3].mux_rd_rise1_r3_reg[3] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_div4.gen_rd_4[3].mux_rd_rise1_r2_reg ),
        .Q(p_1_in182_in[3]),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[3].mux_rd_rise2_r2_reg[3] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(mux_rd_valid_r),
        .D(\gen_mux_rd[3].mux_rd_rise2_r1_reg ),
        .Q(\gen_mux_div4.gen_rd_4[3].mux_rd_rise2_r2_reg ),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[3].mux_rd_rise2_r3_reg[3] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_div4.gen_rd_4[3].mux_rd_rise2_r2_reg ),
        .Q(p_1_in176_in[3]),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[3].mux_rd_rise3_r2_reg[3] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(mux_rd_valid_r),
        .D(\gen_mux_rd[3].mux_rd_rise3_r1_reg ),
        .Q(\gen_mux_div4.gen_rd_4[3].mux_rd_rise3_r2_reg ),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[3].mux_rd_rise3_r3_reg[3] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_div4.gen_rd_4[3].mux_rd_rise3_r2_reg ),
        .Q(p_1_in170_in[3]),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[4].mux_rd_fall0_r2_reg[4] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(mux_rd_valid_r),
        .D(\gen_mux_rd[4].mux_rd_fall0_r1_reg ),
        .Q(\gen_mux_div4.gen_rd_4[4].mux_rd_fall0_r2_reg ),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[4].mux_rd_fall0_r3_reg[4] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_div4.gen_rd_4[4].mux_rd_fall0_r2_reg ),
        .Q(p_1_in185_in[4]),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[4].mux_rd_fall1_r2_reg[4] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(mux_rd_valid_r),
        .D(\gen_mux_rd[4].mux_rd_fall1_r1_reg ),
        .Q(\gen_mux_div4.gen_rd_4[4].mux_rd_fall1_r2_reg ),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[4].mux_rd_fall1_r3_reg[4] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_div4.gen_rd_4[4].mux_rd_fall1_r2_reg ),
        .Q(p_1_in179_in[4]),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[4].mux_rd_fall2_r2_reg[4] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(mux_rd_valid_r),
        .D(\gen_mux_rd[4].mux_rd_fall2_r1_reg ),
        .Q(\gen_mux_div4.gen_rd_4[4].mux_rd_fall2_r2_reg ),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[4].mux_rd_fall2_r3_reg[4] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_div4.gen_rd_4[4].mux_rd_fall2_r2_reg ),
        .Q(p_1_in173_in[4]),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[4].mux_rd_fall3_r2_reg[4] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(mux_rd_valid_r),
        .D(\gen_mux_rd[4].mux_rd_fall3_r1_reg ),
        .Q(\gen_mux_div4.gen_rd_4[4].mux_rd_fall3_r2_reg ),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[4].mux_rd_fall3_r3_reg[4] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_div4.gen_rd_4[4].mux_rd_fall3_r2_reg ),
        .Q(p_1_in167_in[4]),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[4].mux_rd_rise0_r2_reg[4] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(mux_rd_valid_r),
        .D(\gen_mux_rd[4].mux_rd_rise0_r1_reg ),
        .Q(\gen_mux_div4.gen_rd_4[4].mux_rd_rise0_r2_reg ),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[4].mux_rd_rise0_r3_reg[4] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_div4.gen_rd_4[4].mux_rd_rise0_r2_reg ),
        .Q(p_1_in188_in[4]),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[4].mux_rd_rise1_r2_reg[4] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(mux_rd_valid_r),
        .D(\gen_mux_rd[4].mux_rd_rise1_r1_reg ),
        .Q(\gen_mux_div4.gen_rd_4[4].mux_rd_rise1_r2_reg ),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[4].mux_rd_rise1_r3_reg[4] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_div4.gen_rd_4[4].mux_rd_rise1_r2_reg ),
        .Q(p_1_in182_in[4]),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[4].mux_rd_rise2_r2_reg[4] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(mux_rd_valid_r),
        .D(\gen_mux_rd[4].mux_rd_rise2_r1_reg ),
        .Q(\gen_mux_div4.gen_rd_4[4].mux_rd_rise2_r2_reg ),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[4].mux_rd_rise2_r3_reg[4] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_div4.gen_rd_4[4].mux_rd_rise2_r2_reg ),
        .Q(p_1_in176_in[4]),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[4].mux_rd_rise3_r2_reg[4] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(mux_rd_valid_r),
        .D(\gen_mux_rd[4].mux_rd_rise3_r1_reg ),
        .Q(\gen_mux_div4.gen_rd_4[4].mux_rd_rise3_r2_reg ),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[4].mux_rd_rise3_r3_reg[4] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_div4.gen_rd_4[4].mux_rd_rise3_r2_reg ),
        .Q(p_1_in170_in[4]),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[5].mux_rd_fall0_r2_reg[5] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(mux_rd_valid_r),
        .D(\gen_mux_rd[5].mux_rd_fall0_r1_reg ),
        .Q(\gen_mux_div4.gen_rd_4[5].mux_rd_fall0_r2_reg ),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[5].mux_rd_fall0_r3_reg[5] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_div4.gen_rd_4[5].mux_rd_fall0_r2_reg ),
        .Q(p_1_in185_in[5]),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[5].mux_rd_fall1_r2_reg[5] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(mux_rd_valid_r),
        .D(\gen_mux_rd[5].mux_rd_fall1_r1_reg ),
        .Q(\gen_mux_div4.gen_rd_4[5].mux_rd_fall1_r2_reg ),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[5].mux_rd_fall1_r3_reg[5] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_div4.gen_rd_4[5].mux_rd_fall1_r2_reg ),
        .Q(p_1_in179_in[5]),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[5].mux_rd_fall2_r2_reg[5] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(mux_rd_valid_r),
        .D(\gen_mux_rd[5].mux_rd_fall2_r1_reg ),
        .Q(\gen_mux_div4.gen_rd_4[5].mux_rd_fall2_r2_reg ),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[5].mux_rd_fall2_r3_reg[5] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_div4.gen_rd_4[5].mux_rd_fall2_r2_reg ),
        .Q(p_1_in173_in[5]),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[5].mux_rd_fall3_r2_reg[5] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(mux_rd_valid_r),
        .D(\gen_mux_rd[5].mux_rd_fall3_r1_reg ),
        .Q(\gen_mux_div4.gen_rd_4[5].mux_rd_fall3_r2_reg ),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[5].mux_rd_fall3_r3_reg[5] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_div4.gen_rd_4[5].mux_rd_fall3_r2_reg ),
        .Q(p_1_in167_in[5]),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[5].mux_rd_rise0_r2_reg[5] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(mux_rd_valid_r),
        .D(\gen_mux_rd[5].mux_rd_rise0_r1_reg ),
        .Q(\gen_mux_div4.gen_rd_4[5].mux_rd_rise0_r2_reg ),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[5].mux_rd_rise0_r3_reg[5] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_div4.gen_rd_4[5].mux_rd_rise0_r2_reg ),
        .Q(p_1_in188_in[5]),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[5].mux_rd_rise1_r2_reg[5] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(mux_rd_valid_r),
        .D(\gen_mux_rd[5].mux_rd_rise1_r1_reg ),
        .Q(\gen_mux_div4.gen_rd_4[5].mux_rd_rise1_r2_reg ),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[5].mux_rd_rise1_r3_reg[5] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_div4.gen_rd_4[5].mux_rd_rise1_r2_reg ),
        .Q(p_1_in182_in[5]),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[5].mux_rd_rise2_r2_reg[5] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(mux_rd_valid_r),
        .D(\gen_mux_rd[5].mux_rd_rise2_r1_reg ),
        .Q(\gen_mux_div4.gen_rd_4[5].mux_rd_rise2_r2_reg ),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[5].mux_rd_rise2_r3_reg[5] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_div4.gen_rd_4[5].mux_rd_rise2_r2_reg ),
        .Q(p_1_in176_in[5]),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[5].mux_rd_rise3_r2_reg[5] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(mux_rd_valid_r),
        .D(\gen_mux_rd[5].mux_rd_rise3_r1_reg ),
        .Q(\gen_mux_div4.gen_rd_4[5].mux_rd_rise3_r2_reg ),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[5].mux_rd_rise3_r3_reg[5] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_div4.gen_rd_4[5].mux_rd_rise3_r2_reg ),
        .Q(p_1_in170_in[5]),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[6].mux_rd_fall0_r2_reg[6] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(mux_rd_valid_r),
        .D(\gen_mux_rd[6].mux_rd_fall0_r1_reg ),
        .Q(\gen_mux_div4.gen_rd_4[6].mux_rd_fall0_r2_reg ),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[6].mux_rd_fall0_r3_reg[6] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_div4.gen_rd_4[6].mux_rd_fall0_r2_reg ),
        .Q(p_1_in185_in[6]),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[6].mux_rd_fall1_r2_reg[6] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(mux_rd_valid_r),
        .D(\gen_mux_rd[6].mux_rd_fall1_r1_reg ),
        .Q(\gen_mux_div4.gen_rd_4[6].mux_rd_fall1_r2_reg ),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[6].mux_rd_fall1_r3_reg[6] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_div4.gen_rd_4[6].mux_rd_fall1_r2_reg ),
        .Q(p_1_in179_in[6]),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[6].mux_rd_fall2_r2_reg[6] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(mux_rd_valid_r),
        .D(\gen_mux_rd[6].mux_rd_fall2_r1_reg ),
        .Q(\gen_mux_div4.gen_rd_4[6].mux_rd_fall2_r2_reg ),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[6].mux_rd_fall2_r3_reg[6] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_div4.gen_rd_4[6].mux_rd_fall2_r2_reg ),
        .Q(p_1_in173_in[6]),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[6].mux_rd_fall3_r2_reg[6] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(mux_rd_valid_r),
        .D(\gen_mux_rd[6].mux_rd_fall3_r1_reg ),
        .Q(\gen_mux_div4.gen_rd_4[6].mux_rd_fall3_r2_reg ),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[6].mux_rd_fall3_r3_reg[6] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_div4.gen_rd_4[6].mux_rd_fall3_r2_reg ),
        .Q(p_1_in167_in[6]),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[6].mux_rd_rise0_r2_reg[6] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(mux_rd_valid_r),
        .D(\gen_mux_rd[6].mux_rd_rise0_r1_reg ),
        .Q(\gen_mux_div4.gen_rd_4[6].mux_rd_rise0_r2_reg ),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[6].mux_rd_rise0_r3_reg[6] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_div4.gen_rd_4[6].mux_rd_rise0_r2_reg ),
        .Q(p_1_in188_in[6]),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[6].mux_rd_rise1_r2_reg[6] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(mux_rd_valid_r),
        .D(\gen_mux_rd[6].mux_rd_rise1_r1_reg ),
        .Q(\gen_mux_div4.gen_rd_4[6].mux_rd_rise1_r2_reg ),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[6].mux_rd_rise1_r3_reg[6] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_div4.gen_rd_4[6].mux_rd_rise1_r2_reg ),
        .Q(p_1_in182_in[6]),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[6].mux_rd_rise2_r2_reg[6] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(mux_rd_valid_r),
        .D(\gen_mux_rd[6].mux_rd_rise2_r1_reg ),
        .Q(\gen_mux_div4.gen_rd_4[6].mux_rd_rise2_r2_reg ),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[6].mux_rd_rise2_r3_reg[6] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_div4.gen_rd_4[6].mux_rd_rise2_r2_reg ),
        .Q(p_1_in176_in[6]),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[6].mux_rd_rise3_r2_reg[6] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(mux_rd_valid_r),
        .D(\gen_mux_rd[6].mux_rd_rise3_r1_reg ),
        .Q(\gen_mux_div4.gen_rd_4[6].mux_rd_rise3_r2_reg ),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[6].mux_rd_rise3_r3_reg[6] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_div4.gen_rd_4[6].mux_rd_rise3_r2_reg ),
        .Q(p_1_in170_in[6]),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[7].mux_rd_fall0_r2_reg[7] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(mux_rd_valid_r),
        .D(\gen_mux_rd[7].mux_rd_fall0_r1_reg ),
        .Q(\gen_mux_div4.gen_rd_4[7].mux_rd_fall0_r2_reg ),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[7].mux_rd_fall0_r3_reg[7] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_div4.gen_rd_4[7].mux_rd_fall0_r2_reg ),
        .Q(p_1_in185_in[7]),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[7].mux_rd_fall1_r2_reg[7] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(mux_rd_valid_r),
        .D(\gen_mux_rd[7].mux_rd_fall1_r1_reg ),
        .Q(\gen_mux_div4.gen_rd_4[7].mux_rd_fall1_r2_reg ),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[7].mux_rd_fall1_r3_reg[7] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_div4.gen_rd_4[7].mux_rd_fall1_r2_reg ),
        .Q(p_1_in179_in[7]),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[7].mux_rd_fall2_r2_reg[7] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(mux_rd_valid_r),
        .D(\gen_mux_rd[7].mux_rd_fall2_r1_reg ),
        .Q(\gen_mux_div4.gen_rd_4[7].mux_rd_fall2_r2_reg ),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[7].mux_rd_fall2_r3_reg[7] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_div4.gen_rd_4[7].mux_rd_fall2_r2_reg ),
        .Q(p_1_in173_in[7]),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[7].mux_rd_fall3_r2_reg[7] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(mux_rd_valid_r),
        .D(\gen_mux_rd[7].mux_rd_fall3_r1_reg ),
        .Q(\gen_mux_div4.gen_rd_4[7].mux_rd_fall3_r2_reg ),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[7].mux_rd_fall3_r3_reg[7] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_div4.gen_rd_4[7].mux_rd_fall3_r2_reg ),
        .Q(p_1_in167_in[7]),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[7].mux_rd_rise0_r2_reg[7] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(mux_rd_valid_r),
        .D(\gen_mux_rd[7].mux_rd_rise0_r1_reg ),
        .Q(\gen_mux_div4.gen_rd_4[7].mux_rd_rise0_r2_reg ),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[7].mux_rd_rise0_r3_reg[7] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_div4.gen_rd_4[7].mux_rd_rise0_r2_reg ),
        .Q(p_1_in188_in[7]),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[7].mux_rd_rise1_r2_reg[7] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(mux_rd_valid_r),
        .D(\gen_mux_rd[7].mux_rd_rise1_r1_reg ),
        .Q(\gen_mux_div4.gen_rd_4[7].mux_rd_rise1_r2_reg ),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[7].mux_rd_rise1_r3_reg[7] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_div4.gen_rd_4[7].mux_rd_rise1_r2_reg ),
        .Q(p_1_in182_in[7]),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[7].mux_rd_rise2_r2_reg[7] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(mux_rd_valid_r),
        .D(\gen_mux_rd[7].mux_rd_rise2_r1_reg ),
        .Q(\gen_mux_div4.gen_rd_4[7].mux_rd_rise2_r2_reg ),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[7].mux_rd_rise2_r3_reg[7] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_div4.gen_rd_4[7].mux_rd_rise2_r2_reg ),
        .Q(p_1_in176_in[7]),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[7].mux_rd_rise3_r2_reg[7] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(mux_rd_valid_r),
        .D(\gen_mux_rd[7].mux_rd_rise3_r1_reg ),
        .Q(\gen_mux_div4.gen_rd_4[7].mux_rd_rise3_r2_reg ),
        .R(1'b0));
  FDRE \gen_mux_div4.gen_rd_4[7].mux_rd_rise3_r3_reg[7] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_div4.gen_rd_4[7].mux_rd_rise3_r2_reg ),
        .Q(p_1_in170_in[7]),
        .R(1'b0));
  FDRE \gen_mux_rd[0].compare_data_fall0_r1_reg[0] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_out[8]),
        .Q(p_0_in184_in[0]),
        .R(1'b0));
  FDRE \gen_mux_rd[0].compare_data_fall1_r1_reg[0] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_out[24]),
        .Q(p_0_in178_in[0]),
        .R(1'b0));
  FDRE \gen_mux_rd[0].compare_data_fall2_r1_reg[0] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_out[40]),
        .Q(p_0_in172_in[0]),
        .R(1'b0));
  FDRE \gen_mux_rd[0].compare_data_fall3_r1_reg[0] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_out[56]),
        .Q(p_0_in166_in[0]),
        .R(1'b0));
  FDRE \gen_mux_rd[0].compare_data_rise0_r1_reg[0] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_out[0]),
        .Q(p_0_in187_in[0]),
        .R(1'b0));
  FDRE \gen_mux_rd[0].compare_data_rise1_r1_reg[0] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_out[16]),
        .Q(p_0_in181_in[0]),
        .R(1'b0));
  FDRE \gen_mux_rd[0].compare_data_rise2_r1_reg[0] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_out[32]),
        .Q(p_0_in175_in[0]),
        .R(1'b0));
  FDRE \gen_mux_rd[0].compare_data_rise3_r1_reg[0] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_out[48]),
        .Q(p_0_in169_in[0]),
        .R(1'b0));
  FDRE \gen_mux_rd[0].mux_rd_fall0_r1_reg[0] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_rd[0].mux_rd_fall0_r1_reg[0]_0 ),
        .Q(mux_rd_fall0_r1),
        .R(1'b0));
  FDRE \gen_mux_rd[0].mux_rd_fall1_r1_reg[0] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_rd[0].mux_rd_fall1_r1_reg[0]_0 ),
        .Q(mux_rd_fall1_r1),
        .R(1'b0));
  FDRE \gen_mux_rd[0].mux_rd_fall2_r1_reg[0] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_rd[0].mux_rd_fall2_r1_reg[0]_0 ),
        .Q(mux_rd_fall2_r1),
        .R(1'b0));
  FDRE \gen_mux_rd[0].mux_rd_fall3_r1_reg[0] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_rd[0].mux_rd_fall3_r1_reg[0]_0 ),
        .Q(mux_rd_fall3_r1),
        .R(1'b0));
  FDRE \gen_mux_rd[0].mux_rd_rise0_r1_reg[0] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_rd[0].mux_rd_rise0_r1_reg[0]_0 ),
        .Q(mux_rd_rise0_r1),
        .R(1'b0));
  FDRE \gen_mux_rd[0].mux_rd_rise1_r1_reg[0] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_rd[0].mux_rd_rise1_r1_reg[0]_0 ),
        .Q(mux_rd_rise1_r1),
        .R(1'b0));
  FDRE \gen_mux_rd[0].mux_rd_rise2_r1_reg[0] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_rd[0].mux_rd_rise2_r1_reg[0]_0 ),
        .Q(mux_rd_rise2_r1),
        .R(1'b0));
  FDRE \gen_mux_rd[0].mux_rd_rise3_r1_reg[0] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_rd[0].mux_rd_rise3_r1_reg[0]_0 ),
        .Q(mux_rd_rise3_r1),
        .R(1'b0));
  FDRE \gen_mux_rd[1].compare_data_fall0_r1_reg[1] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_out[9]),
        .Q(p_0_in184_in[1]),
        .R(1'b0));
  FDRE \gen_mux_rd[1].compare_data_fall1_r1_reg[1] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_out[25]),
        .Q(p_0_in178_in[1]),
        .R(1'b0));
  FDRE \gen_mux_rd[1].compare_data_fall2_r1_reg[1] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_out[41]),
        .Q(p_0_in172_in[1]),
        .R(1'b0));
  FDRE \gen_mux_rd[1].compare_data_fall3_r1_reg[1] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_out[57]),
        .Q(p_0_in166_in[1]),
        .R(1'b0));
  FDRE \gen_mux_rd[1].compare_data_rise0_r1_reg[1] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_out[1]),
        .Q(p_0_in187_in[1]),
        .R(1'b0));
  FDRE \gen_mux_rd[1].compare_data_rise1_r1_reg[1] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_out[17]),
        .Q(p_0_in181_in[1]),
        .R(1'b0));
  FDRE \gen_mux_rd[1].compare_data_rise2_r1_reg[1] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_out[33]),
        .Q(p_0_in175_in[1]),
        .R(1'b0));
  FDRE \gen_mux_rd[1].compare_data_rise3_r1_reg[1] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_out[49]),
        .Q(p_0_in169_in[1]),
        .R(1'b0));
  FDRE \gen_mux_rd[1].mux_rd_fall0_r1_reg[1] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_rd[1].mux_rd_fall0_r1_reg[1]_0 ),
        .Q(\gen_mux_rd[1].mux_rd_fall0_r1_reg ),
        .R(1'b0));
  FDRE \gen_mux_rd[1].mux_rd_fall1_r1_reg[1] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_rd[1].mux_rd_fall1_r1_reg[1]_0 ),
        .Q(\gen_mux_rd[1].mux_rd_fall1_r1_reg ),
        .R(1'b0));
  FDRE \gen_mux_rd[1].mux_rd_fall2_r1_reg[1] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_rd[1].mux_rd_fall2_r1_reg[1]_0 ),
        .Q(\gen_mux_rd[1].mux_rd_fall2_r1_reg ),
        .R(1'b0));
  FDRE \gen_mux_rd[1].mux_rd_fall3_r1_reg[1] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_rd[1].mux_rd_fall3_r1_reg[1]_0 ),
        .Q(\gen_mux_rd[1].mux_rd_fall3_r1_reg ),
        .R(1'b0));
  FDRE \gen_mux_rd[1].mux_rd_rise0_r1_reg[1] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_rd[1].mux_rd_rise0_r1_reg[1]_0 ),
        .Q(\gen_mux_rd[1].mux_rd_rise0_r1_reg ),
        .R(1'b0));
  FDRE \gen_mux_rd[1].mux_rd_rise1_r1_reg[1] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_rd[1].mux_rd_rise1_r1_reg[1]_0 ),
        .Q(\gen_mux_rd[1].mux_rd_rise1_r1_reg ),
        .R(1'b0));
  FDRE \gen_mux_rd[1].mux_rd_rise2_r1_reg[1] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_rd[1].mux_rd_rise2_r1_reg[1]_0 ),
        .Q(\gen_mux_rd[1].mux_rd_rise2_r1_reg ),
        .R(1'b0));
  FDRE \gen_mux_rd[1].mux_rd_rise3_r1_reg[1] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_rd[1].mux_rd_rise3_r1_reg[1]_0 ),
        .Q(\gen_mux_rd[1].mux_rd_rise3_r1_reg ),
        .R(1'b0));
  FDRE \gen_mux_rd[2].compare_data_fall0_r1_reg[2] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_out[10]),
        .Q(p_0_in184_in[2]),
        .R(1'b0));
  FDRE \gen_mux_rd[2].compare_data_fall1_r1_reg[2] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_out[26]),
        .Q(p_0_in178_in[2]),
        .R(1'b0));
  FDRE \gen_mux_rd[2].compare_data_fall2_r1_reg[2] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_out[42]),
        .Q(p_0_in172_in[2]),
        .R(1'b0));
  FDRE \gen_mux_rd[2].compare_data_fall3_r1_reg[2] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_out[58]),
        .Q(p_0_in166_in[2]),
        .R(1'b0));
  FDRE \gen_mux_rd[2].compare_data_rise0_r1_reg[2] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_out[2]),
        .Q(p_0_in187_in[2]),
        .R(1'b0));
  FDRE \gen_mux_rd[2].compare_data_rise1_r1_reg[2] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_out[18]),
        .Q(p_0_in181_in[2]),
        .R(1'b0));
  FDRE \gen_mux_rd[2].compare_data_rise2_r1_reg[2] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_out[34]),
        .Q(p_0_in175_in[2]),
        .R(1'b0));
  FDRE \gen_mux_rd[2].compare_data_rise3_r1_reg[2] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_out[50]),
        .Q(p_0_in169_in[2]),
        .R(1'b0));
  FDRE \gen_mux_rd[2].mux_rd_fall0_r1_reg[2] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_rd[2].mux_rd_fall0_r1_reg[2]_0 ),
        .Q(\gen_mux_rd[2].mux_rd_fall0_r1_reg ),
        .R(1'b0));
  FDRE \gen_mux_rd[2].mux_rd_fall1_r1_reg[2] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_rd[2].mux_rd_fall1_r1_reg[2]_0 ),
        .Q(\gen_mux_rd[2].mux_rd_fall1_r1_reg ),
        .R(1'b0));
  FDRE \gen_mux_rd[2].mux_rd_fall2_r1_reg[2] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_rd[2].mux_rd_fall2_r1_reg[2]_0 ),
        .Q(\gen_mux_rd[2].mux_rd_fall2_r1_reg ),
        .R(1'b0));
  FDRE \gen_mux_rd[2].mux_rd_fall3_r1_reg[2] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_rd[2].mux_rd_fall3_r1_reg[2]_0 ),
        .Q(\gen_mux_rd[2].mux_rd_fall3_r1_reg ),
        .R(1'b0));
  FDRE \gen_mux_rd[2].mux_rd_rise0_r1_reg[2] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_rd[2].mux_rd_rise0_r1_reg[2]_0 ),
        .Q(\gen_mux_rd[2].mux_rd_rise0_r1_reg ),
        .R(1'b0));
  FDRE \gen_mux_rd[2].mux_rd_rise1_r1_reg[2] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_rd[2].mux_rd_rise1_r1_reg[2]_0 ),
        .Q(\gen_mux_rd[2].mux_rd_rise1_r1_reg ),
        .R(1'b0));
  FDRE \gen_mux_rd[2].mux_rd_rise2_r1_reg[2] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_rd[2].mux_rd_rise2_r1_reg[2]_0 ),
        .Q(\gen_mux_rd[2].mux_rd_rise2_r1_reg ),
        .R(1'b0));
  FDRE \gen_mux_rd[2].mux_rd_rise3_r1_reg[2] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_rd[2].mux_rd_rise3_r1_reg[2]_0 ),
        .Q(\gen_mux_rd[2].mux_rd_rise3_r1_reg ),
        .R(1'b0));
  FDRE \gen_mux_rd[3].compare_data_fall0_r1_reg[3] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_out[11]),
        .Q(p_0_in184_in[3]),
        .R(1'b0));
  FDRE \gen_mux_rd[3].compare_data_fall1_r1_reg[3] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_out[27]),
        .Q(p_0_in178_in[3]),
        .R(1'b0));
  FDRE \gen_mux_rd[3].compare_data_fall2_r1_reg[3] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_out[43]),
        .Q(p_0_in172_in[3]),
        .R(1'b0));
  FDRE \gen_mux_rd[3].compare_data_fall3_r1_reg[3] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_out[59]),
        .Q(p_0_in166_in[3]),
        .R(1'b0));
  FDRE \gen_mux_rd[3].compare_data_rise0_r1_reg[3] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_out[3]),
        .Q(p_0_in187_in[3]),
        .R(1'b0));
  FDRE \gen_mux_rd[3].compare_data_rise1_r1_reg[3] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_out[19]),
        .Q(p_0_in181_in[3]),
        .R(1'b0));
  FDRE \gen_mux_rd[3].compare_data_rise2_r1_reg[3] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_out[35]),
        .Q(p_0_in175_in[3]),
        .R(1'b0));
  FDRE \gen_mux_rd[3].compare_data_rise3_r1_reg[3] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_out[51]),
        .Q(p_0_in169_in[3]),
        .R(1'b0));
  FDRE \gen_mux_rd[3].mux_rd_fall0_r1_reg[3] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_rd[3].mux_rd_fall0_r1_reg[3]_0 ),
        .Q(\gen_mux_rd[3].mux_rd_fall0_r1_reg ),
        .R(1'b0));
  FDRE \gen_mux_rd[3].mux_rd_fall1_r1_reg[3] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_rd[3].mux_rd_fall1_r1_reg[3]_0 ),
        .Q(\gen_mux_rd[3].mux_rd_fall1_r1_reg ),
        .R(1'b0));
  FDRE \gen_mux_rd[3].mux_rd_fall2_r1_reg[3] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_rd[3].mux_rd_fall2_r1_reg[3]_0 ),
        .Q(\gen_mux_rd[3].mux_rd_fall2_r1_reg ),
        .R(1'b0));
  FDRE \gen_mux_rd[3].mux_rd_fall3_r1_reg[3] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_rd[3].mux_rd_fall3_r1_reg[3]_0 ),
        .Q(\gen_mux_rd[3].mux_rd_fall3_r1_reg ),
        .R(1'b0));
  FDRE \gen_mux_rd[3].mux_rd_rise0_r1_reg[3] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_rd[3].mux_rd_rise0_r1_reg[3]_0 ),
        .Q(\gen_mux_rd[3].mux_rd_rise0_r1_reg ),
        .R(1'b0));
  FDRE \gen_mux_rd[3].mux_rd_rise1_r1_reg[3] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_rd[3].mux_rd_rise1_r1_reg[3]_0 ),
        .Q(\gen_mux_rd[3].mux_rd_rise1_r1_reg ),
        .R(1'b0));
  FDRE \gen_mux_rd[3].mux_rd_rise2_r1_reg[3] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_rd[3].mux_rd_rise2_r1_reg[3]_0 ),
        .Q(\gen_mux_rd[3].mux_rd_rise2_r1_reg ),
        .R(1'b0));
  FDRE \gen_mux_rd[3].mux_rd_rise3_r1_reg[3] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_rd[3].mux_rd_rise3_r1_reg[3]_0 ),
        .Q(\gen_mux_rd[3].mux_rd_rise3_r1_reg ),
        .R(1'b0));
  FDRE \gen_mux_rd[4].compare_data_fall0_r1_reg[4] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_out[12]),
        .Q(p_0_in184_in[4]),
        .R(1'b0));
  FDRE \gen_mux_rd[4].compare_data_fall1_r1_reg[4] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_out[28]),
        .Q(p_0_in178_in[4]),
        .R(1'b0));
  FDRE \gen_mux_rd[4].compare_data_fall2_r1_reg[4] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_out[44]),
        .Q(p_0_in172_in[4]),
        .R(1'b0));
  FDRE \gen_mux_rd[4].compare_data_fall3_r1_reg[4] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_out[60]),
        .Q(p_0_in166_in[4]),
        .R(1'b0));
  FDRE \gen_mux_rd[4].compare_data_rise0_r1_reg[4] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_out[4]),
        .Q(p_0_in187_in[4]),
        .R(1'b0));
  FDRE \gen_mux_rd[4].compare_data_rise1_r1_reg[4] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_out[20]),
        .Q(p_0_in181_in[4]),
        .R(1'b0));
  FDRE \gen_mux_rd[4].compare_data_rise2_r1_reg[4] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_out[36]),
        .Q(p_0_in175_in[4]),
        .R(1'b0));
  FDRE \gen_mux_rd[4].compare_data_rise3_r1_reg[4] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_out[52]),
        .Q(p_0_in169_in[4]),
        .R(1'b0));
  FDRE \gen_mux_rd[4].mux_rd_fall0_r1_reg[4] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_rd[4].mux_rd_fall0_r1_reg[4]_0 ),
        .Q(\gen_mux_rd[4].mux_rd_fall0_r1_reg ),
        .R(1'b0));
  FDRE \gen_mux_rd[4].mux_rd_fall1_r1_reg[4] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_rd[4].mux_rd_fall1_r1_reg[4]_0 ),
        .Q(\gen_mux_rd[4].mux_rd_fall1_r1_reg ),
        .R(1'b0));
  FDRE \gen_mux_rd[4].mux_rd_fall2_r1_reg[4] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_rd[4].mux_rd_fall2_r1_reg[4]_0 ),
        .Q(\gen_mux_rd[4].mux_rd_fall2_r1_reg ),
        .R(1'b0));
  FDRE \gen_mux_rd[4].mux_rd_fall3_r1_reg[4] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_rd[4].mux_rd_fall3_r1_reg[4]_0 ),
        .Q(\gen_mux_rd[4].mux_rd_fall3_r1_reg ),
        .R(1'b0));
  FDRE \gen_mux_rd[4].mux_rd_rise0_r1_reg[4] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_rd[4].mux_rd_rise0_r1_reg[4]_0 ),
        .Q(\gen_mux_rd[4].mux_rd_rise0_r1_reg ),
        .R(1'b0));
  FDRE \gen_mux_rd[4].mux_rd_rise1_r1_reg[4] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_rd[4].mux_rd_rise1_r1_reg[4]_0 ),
        .Q(\gen_mux_rd[4].mux_rd_rise1_r1_reg ),
        .R(1'b0));
  FDRE \gen_mux_rd[4].mux_rd_rise2_r1_reg[4] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_rd[4].mux_rd_rise2_r1_reg[4]_0 ),
        .Q(\gen_mux_rd[4].mux_rd_rise2_r1_reg ),
        .R(1'b0));
  FDRE \gen_mux_rd[4].mux_rd_rise3_r1_reg[4] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_rd[4].mux_rd_rise3_r1_reg[4]_0 ),
        .Q(\gen_mux_rd[4].mux_rd_rise3_r1_reg ),
        .R(1'b0));
  FDRE \gen_mux_rd[5].compare_data_fall0_r1_reg[5] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_out[13]),
        .Q(p_0_in184_in[5]),
        .R(1'b0));
  FDRE \gen_mux_rd[5].compare_data_fall1_r1_reg[5] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_out[29]),
        .Q(p_0_in178_in[5]),
        .R(1'b0));
  FDRE \gen_mux_rd[5].compare_data_fall2_r1_reg[5] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_out[45]),
        .Q(p_0_in172_in[5]),
        .R(1'b0));
  FDRE \gen_mux_rd[5].compare_data_fall3_r1_reg[5] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_out[61]),
        .Q(p_0_in166_in[5]),
        .R(1'b0));
  FDRE \gen_mux_rd[5].compare_data_rise0_r1_reg[5] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_out[5]),
        .Q(p_0_in187_in[5]),
        .R(1'b0));
  FDRE \gen_mux_rd[5].compare_data_rise1_r1_reg[5] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_out[21]),
        .Q(p_0_in181_in[5]),
        .R(1'b0));
  FDRE \gen_mux_rd[5].compare_data_rise2_r1_reg[5] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_out[37]),
        .Q(p_0_in175_in[5]),
        .R(1'b0));
  FDRE \gen_mux_rd[5].compare_data_rise3_r1_reg[5] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_out[53]),
        .Q(p_0_in169_in[5]),
        .R(1'b0));
  FDRE \gen_mux_rd[5].mux_rd_fall0_r1_reg[5] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_rd[5].mux_rd_fall0_r1_reg[5]_0 ),
        .Q(\gen_mux_rd[5].mux_rd_fall0_r1_reg ),
        .R(1'b0));
  FDRE \gen_mux_rd[5].mux_rd_fall1_r1_reg[5] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_rd[5].mux_rd_fall1_r1_reg[5]_0 ),
        .Q(\gen_mux_rd[5].mux_rd_fall1_r1_reg ),
        .R(1'b0));
  FDRE \gen_mux_rd[5].mux_rd_fall2_r1_reg[5] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_rd[5].mux_rd_fall2_r1_reg[5]_0 ),
        .Q(\gen_mux_rd[5].mux_rd_fall2_r1_reg ),
        .R(1'b0));
  FDRE \gen_mux_rd[5].mux_rd_fall3_r1_reg[5] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_rd[5].mux_rd_fall3_r1_reg[5]_0 ),
        .Q(\gen_mux_rd[5].mux_rd_fall3_r1_reg ),
        .R(1'b0));
  FDRE \gen_mux_rd[5].mux_rd_rise0_r1_reg[5] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_rd[5].mux_rd_rise0_r1_reg[5]_0 ),
        .Q(\gen_mux_rd[5].mux_rd_rise0_r1_reg ),
        .R(1'b0));
  FDRE \gen_mux_rd[5].mux_rd_rise1_r1_reg[5] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_rd[5].mux_rd_rise1_r1_reg[5]_0 ),
        .Q(\gen_mux_rd[5].mux_rd_rise1_r1_reg ),
        .R(1'b0));
  FDRE \gen_mux_rd[5].mux_rd_rise2_r1_reg[5] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_rd[5].mux_rd_rise2_r1_reg[5]_0 ),
        .Q(\gen_mux_rd[5].mux_rd_rise2_r1_reg ),
        .R(1'b0));
  FDRE \gen_mux_rd[5].mux_rd_rise3_r1_reg[5] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_rd[5].mux_rd_rise3_r1_reg[5]_0 ),
        .Q(\gen_mux_rd[5].mux_rd_rise3_r1_reg ),
        .R(1'b0));
  FDRE \gen_mux_rd[6].compare_data_fall0_r1_reg[6] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_out[14]),
        .Q(p_0_in184_in[6]),
        .R(1'b0));
  FDRE \gen_mux_rd[6].compare_data_fall1_r1_reg[6] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_out[30]),
        .Q(p_0_in178_in[6]),
        .R(1'b0));
  FDRE \gen_mux_rd[6].compare_data_fall2_r1_reg[6] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_out[46]),
        .Q(p_0_in172_in[6]),
        .R(1'b0));
  FDRE \gen_mux_rd[6].compare_data_fall3_r1_reg[6] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_out[62]),
        .Q(p_0_in166_in[6]),
        .R(1'b0));
  FDRE \gen_mux_rd[6].compare_data_rise0_r1_reg[6] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_out[6]),
        .Q(p_0_in187_in[6]),
        .R(1'b0));
  FDRE \gen_mux_rd[6].compare_data_rise1_r1_reg[6] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_out[22]),
        .Q(p_0_in181_in[6]),
        .R(1'b0));
  FDRE \gen_mux_rd[6].compare_data_rise2_r1_reg[6] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_out[38]),
        .Q(p_0_in175_in[6]),
        .R(1'b0));
  FDRE \gen_mux_rd[6].compare_data_rise3_r1_reg[6] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_out[54]),
        .Q(p_0_in169_in[6]),
        .R(1'b0));
  FDRE \gen_mux_rd[6].mux_rd_fall0_r1_reg[6] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_rd[6].mux_rd_fall0_r1_reg[6]_0 ),
        .Q(\gen_mux_rd[6].mux_rd_fall0_r1_reg ),
        .R(1'b0));
  FDRE \gen_mux_rd[6].mux_rd_fall1_r1_reg[6] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_rd[6].mux_rd_fall1_r1_reg[6]_0 ),
        .Q(\gen_mux_rd[6].mux_rd_fall1_r1_reg ),
        .R(1'b0));
  FDRE \gen_mux_rd[6].mux_rd_fall2_r1_reg[6] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_rd[6].mux_rd_fall2_r1_reg[6]_0 ),
        .Q(\gen_mux_rd[6].mux_rd_fall2_r1_reg ),
        .R(1'b0));
  FDRE \gen_mux_rd[6].mux_rd_fall3_r1_reg[6] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_rd[6].mux_rd_fall3_r1_reg[6]_0 ),
        .Q(\gen_mux_rd[6].mux_rd_fall3_r1_reg ),
        .R(1'b0));
  FDRE \gen_mux_rd[6].mux_rd_rise0_r1_reg[6] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_rd[6].mux_rd_rise0_r1_reg[6]_0 ),
        .Q(\gen_mux_rd[6].mux_rd_rise0_r1_reg ),
        .R(1'b0));
  FDRE \gen_mux_rd[6].mux_rd_rise1_r1_reg[6] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_rd[6].mux_rd_rise1_r1_reg[6]_0 ),
        .Q(\gen_mux_rd[6].mux_rd_rise1_r1_reg ),
        .R(1'b0));
  FDRE \gen_mux_rd[6].mux_rd_rise2_r1_reg[6] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_rd[6].mux_rd_rise2_r1_reg[6]_0 ),
        .Q(\gen_mux_rd[6].mux_rd_rise2_r1_reg ),
        .R(1'b0));
  FDRE \gen_mux_rd[6].mux_rd_rise3_r1_reg[6] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_rd[6].mux_rd_rise3_r1_reg[6]_0 ),
        .Q(\gen_mux_rd[6].mux_rd_rise3_r1_reg ),
        .R(1'b0));
  FDRE \gen_mux_rd[7].compare_data_fall0_r1_reg[7] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_out[15]),
        .Q(p_0_in184_in[7]),
        .R(1'b0));
  FDRE \gen_mux_rd[7].compare_data_fall1_r1_reg[7] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_out[31]),
        .Q(p_0_in178_in[7]),
        .R(1'b0));
  FDRE \gen_mux_rd[7].compare_data_fall2_r1_reg[7] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_out[47]),
        .Q(p_0_in172_in[7]),
        .R(1'b0));
  FDRE \gen_mux_rd[7].compare_data_fall3_r1_reg[7] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_out[63]),
        .Q(p_0_in166_in[7]),
        .R(1'b0));
  FDRE \gen_mux_rd[7].compare_data_rise0_r1_reg[7] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_out[7]),
        .Q(p_0_in187_in[7]),
        .R(1'b0));
  FDRE \gen_mux_rd[7].compare_data_rise1_r1_reg[7] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_out[23]),
        .Q(p_0_in181_in[7]),
        .R(1'b0));
  FDRE \gen_mux_rd[7].compare_data_rise2_r1_reg[7] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_out[39]),
        .Q(p_0_in175_in[7]),
        .R(1'b0));
  FDRE \gen_mux_rd[7].compare_data_rise3_r1_reg[7] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_out[55]),
        .Q(p_0_in169_in[7]),
        .R(1'b0));
  FDRE \gen_mux_rd[7].mux_rd_fall0_r1_reg[7] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_rd[7].mux_rd_fall0_r1_reg[7]_0 ),
        .Q(\gen_mux_rd[7].mux_rd_fall0_r1_reg ),
        .R(1'b0));
  FDRE \gen_mux_rd[7].mux_rd_fall1_r1_reg[7] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_rd[7].mux_rd_fall1_r1_reg[7]_0 ),
        .Q(\gen_mux_rd[7].mux_rd_fall1_r1_reg ),
        .R(1'b0));
  FDRE \gen_mux_rd[7].mux_rd_fall2_r1_reg[7] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_rd[7].mux_rd_fall2_r1_reg[7]_0 ),
        .Q(\gen_mux_rd[7].mux_rd_fall2_r1_reg ),
        .R(1'b0));
  FDRE \gen_mux_rd[7].mux_rd_fall3_r1_reg[7] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_rd[7].mux_rd_fall3_r1_reg[7]_0 ),
        .Q(\gen_mux_rd[7].mux_rd_fall3_r1_reg ),
        .R(1'b0));
  FDRE \gen_mux_rd[7].mux_rd_rise0_r1_reg[7] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_rd[7].mux_rd_rise0_r1_reg[7]_0 ),
        .Q(\gen_mux_rd[7].mux_rd_rise0_r1_reg ),
        .R(1'b0));
  FDRE \gen_mux_rd[7].mux_rd_rise1_r1_reg[7] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_rd[7].mux_rd_rise1_r1_reg[7]_0 ),
        .Q(\gen_mux_rd[7].mux_rd_rise1_r1_reg ),
        .R(1'b0));
  FDRE \gen_mux_rd[7].mux_rd_rise2_r1_reg[7] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_rd[7].mux_rd_rise2_r1_reg[7]_0 ),
        .Q(\gen_mux_rd[7].mux_rd_rise2_r1_reg ),
        .R(1'b0));
  FDRE \gen_mux_rd[7].mux_rd_rise3_r1_reg[7] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\gen_mux_rd[7].mux_rd_rise3_r1_reg[7]_0 ),
        .Q(\gen_mux_rd[7].mux_rd_rise3_r1_reg ),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h00F0002000000100)) 
    \genblk7[0].compare_err_pb_latch_r[0]_i_1 
       (.I0(prbs_state_r[1]),
        .I1(cnt_wait_state),
        .I2(prbs_state_r[3]),
        .I3(prbs_state_r[4]),
        .I4(prbs_state_r[0]),
        .I5(prbs_state_r[2]),
        .O(\genblk7[0].compare_err_pb_latch_r[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair39" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \genblk7[0].compare_err_pb_latch_r[0]_i_2 
       (.I0(compare_err_pb[0]),
        .I1(\genblk7[0].compare_err_pb_latch_r_reg_n_0_[0] ),
        .O(\genblk7[0].compare_err_pb_latch_r[0]_i_2_n_0 ));
  FDRE \genblk7[0].compare_err_pb_latch_r_reg[0] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\genblk7[0].compare_err_pb_latch_r[0]_i_2_n_0 ),
        .Q(\genblk7[0].compare_err_pb_latch_r_reg_n_0_[0] ),
        .R(\genblk7[0].compare_err_pb_latch_r[0]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \genblk7[1].compare_err_pb_latch_r[1]_i_1 
       (.I0(compare_err_pb[1]),
        .I1(\genblk7[1].compare_err_pb_latch_r_reg_n_0_[1] ),
        .O(\genblk7[1].compare_err_pb_latch_r[1]_i_1_n_0 ));
  FDRE \genblk7[1].compare_err_pb_latch_r_reg[1] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\genblk7[1].compare_err_pb_latch_r[1]_i_1_n_0 ),
        .Q(\genblk7[1].compare_err_pb_latch_r_reg_n_0_[1] ),
        .R(\genblk7[0].compare_err_pb_latch_r[0]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \genblk7[2].compare_err_pb_latch_r[2]_i_1 
       (.I0(compare_err_pb[2]),
        .I1(\genblk7[2].compare_err_pb_latch_r_reg_n_0_[2] ),
        .O(\genblk7[2].compare_err_pb_latch_r[2]_i_1_n_0 ));
  FDRE \genblk7[2].compare_err_pb_latch_r_reg[2] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\genblk7[2].compare_err_pb_latch_r[2]_i_1_n_0 ),
        .Q(\genblk7[2].compare_err_pb_latch_r_reg_n_0_[2] ),
        .R(\genblk7[0].compare_err_pb_latch_r[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair47" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \genblk7[3].compare_err_pb_latch_r[3]_i_1 
       (.I0(compare_err_pb[3]),
        .I1(\genblk7[3].compare_err_pb_latch_r_reg_n_0_[3] ),
        .O(\genblk7[3].compare_err_pb_latch_r[3]_i_1_n_0 ));
  FDRE \genblk7[3].compare_err_pb_latch_r_reg[3] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\genblk7[3].compare_err_pb_latch_r[3]_i_1_n_0 ),
        .Q(\genblk7[3].compare_err_pb_latch_r_reg_n_0_[3] ),
        .R(\genblk7[0].compare_err_pb_latch_r[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair53" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \genblk7[4].compare_err_pb_latch_r[4]_i_1 
       (.I0(compare_err_pb[4]),
        .I1(\genblk7[4].compare_err_pb_latch_r_reg_n_0_[4] ),
        .O(\genblk7[4].compare_err_pb_latch_r[4]_i_1_n_0 ));
  FDRE \genblk7[4].compare_err_pb_latch_r_reg[4] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\genblk7[4].compare_err_pb_latch_r[4]_i_1_n_0 ),
        .Q(\genblk7[4].compare_err_pb_latch_r_reg_n_0_[4] ),
        .R(\genblk7[0].compare_err_pb_latch_r[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair61" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \genblk7[5].compare_err_pb_latch_r[5]_i_1 
       (.I0(compare_err_pb[5]),
        .I1(\genblk7[5].compare_err_pb_latch_r_reg_n_0_[5] ),
        .O(\genblk7[5].compare_err_pb_latch_r[5]_i_1_n_0 ));
  FDRE \genblk7[5].compare_err_pb_latch_r_reg[5] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\genblk7[5].compare_err_pb_latch_r[5]_i_1_n_0 ),
        .Q(\genblk7[5].compare_err_pb_latch_r_reg_n_0_[5] ),
        .R(\genblk7[0].compare_err_pb_latch_r[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair62" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \genblk7[6].compare_err_pb_latch_r[6]_i_1 
       (.I0(compare_err_pb[6]),
        .I1(\genblk7[6].compare_err_pb_latch_r_reg_n_0_[6] ),
        .O(\genblk7[6].compare_err_pb_latch_r[6]_i_1_n_0 ));
  FDRE \genblk7[6].compare_err_pb_latch_r_reg[6] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\genblk7[6].compare_err_pb_latch_r[6]_i_1_n_0 ),
        .Q(\genblk7[6].compare_err_pb_latch_r_reg_n_0_[6] ),
        .R(\genblk7[0].compare_err_pb_latch_r[0]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \genblk7[7].compare_err_pb_latch_r[7]_i_1 
       (.I0(compare_err_pb[7]),
        .I1(\genblk7[7].compare_err_pb_latch_r_reg_n_0_[7] ),
        .O(\genblk7[7].compare_err_pb_latch_r[7]_i_1_n_0 ));
  FDRE \genblk7[7].compare_err_pb_latch_r_reg[7] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\genblk7[7].compare_err_pb_latch_r[7]_i_1_n_0 ),
        .Q(\genblk7[7].compare_err_pb_latch_r_reg_n_0_[7] ),
        .R(\genblk7[0].compare_err_pb_latch_r[0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h88BF8880)) 
    \genblk8[0].left_edge_updated[0]_i_1 
       (.I0(\genblk8[0].left_edge_updated[0]_i_2_n_0 ),
        .I1(p_154_out),
        .I2(\genblk8[0].right_edge_found_pb[0]_i_3_n_0 ),
        .I3(\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_3_n_0 ),
        .I4(left_edge_updated[0]),
        .O(\genblk8[0].left_edge_updated[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000100)) 
    \genblk8[0].left_edge_updated[0]_i_2 
       (.I0(match_flag_pb[3]),
        .I1(match_flag_pb[2]),
        .I2(match_flag_pb[0]),
        .I3(match_flag_pb[7]),
        .I4(\genblk7[0].compare_err_pb_latch_r_reg_n_0_[0] ),
        .I5(\genblk8[0].right_edge_found_pb[0]_i_5_n_0 ),
        .O(\genblk8[0].left_edge_updated[0]_i_2_n_0 ));
  FDRE \genblk8[0].left_edge_updated_reg[0] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\genblk8[0].left_edge_updated[0]_i_1_n_0 ),
        .Q(left_edge_updated[0]),
        .R(\bit_cnt[7]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAAEABAAAA)) 
    \genblk8[0].match_flag_pb[7]_i_1 
       (.I0(\rd_victim_sel_reg[2]_1 ),
        .I1(prbs_state_r[3]),
        .I2(prbs_state_r[1]),
        .I3(prbs_state_r[2]),
        .I4(prbs_state_r[0]),
        .I5(prbs_state_r[4]),
        .O(\genblk8[0].match_flag_pb[7]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000800000000)) 
    \genblk8[0].match_flag_pb[7]_i_2 
       (.I0(prbs_state_r[0]),
        .I1(num_samples_done_r),
        .I2(prbs_state_r[1]),
        .I3(prbs_state_r[3]),
        .I4(prbs_state_r[2]),
        .I5(prbs_state_r[4]),
        .O(p_154_out));
  FDSE \genblk8[0].match_flag_pb_reg[0] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(p_154_out),
        .D(\genblk7[0].compare_err_pb_latch_r_reg_n_0_[0] ),
        .Q(match_flag_pb[0]),
        .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 ));
  FDSE \genblk8[0].match_flag_pb_reg[1] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(p_154_out),
        .D(match_flag_pb[0]),
        .Q(match_flag_pb[1]),
        .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 ));
  FDSE \genblk8[0].match_flag_pb_reg[2] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(p_154_out),
        .D(match_flag_pb[1]),
        .Q(match_flag_pb[2]),
        .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 ));
  FDSE \genblk8[0].match_flag_pb_reg[3] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(p_154_out),
        .D(match_flag_pb[2]),
        .Q(match_flag_pb[3]),
        .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 ));
  FDSE \genblk8[0].match_flag_pb_reg[4] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(p_154_out),
        .D(match_flag_pb[3]),
        .Q(match_flag_pb[4]),
        .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 ));
  FDSE \genblk8[0].match_flag_pb_reg[5] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(p_154_out),
        .D(match_flag_pb[4]),
        .Q(match_flag_pb[5]),
        .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 ));
  FDSE \genblk8[0].match_flag_pb_reg[6] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(p_154_out),
        .D(match_flag_pb[5]),
        .Q(match_flag_pb[6]),
        .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 ));
  FDSE \genblk8[0].match_flag_pb_reg[7] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(p_154_out),
        .D(match_flag_pb[6]),
        .Q(match_flag_pb[7]),
        .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h1F001F00AAAABFAA)) 
    \genblk8[0].right_edge_found_pb[0]_i_1 
       (.I0(\genblk8[0].right_edge_found_pb_reg_n_0_[0] ),
        .I1(prbs_dqs_tap_limit_r_i_2_n_0),
        .I2(\genblk8[0].right_edge_found_pb[0]_i_2_n_0 ),
        .I3(p_154_out),
        .I4(\genblk8[0].right_edge_found_pb[0]_i_3_n_0 ),
        .I5(\genblk8[0].right_edge_found_pb[0]_i_4_n_0 ),
        .O(\genblk8[0].right_edge_found_pb[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFEFFFF)) 
    \genblk8[0].right_edge_found_pb[0]_i_2 
       (.I0(\genblk8[0].right_edge_found_pb[0]_i_5_n_0 ),
        .I1(match_flag_pb[3]),
        .I2(match_flag_pb[2]),
        .I3(match_flag_pb[0]),
        .I4(\genblk7[0].compare_err_pb_latch_r_reg_n_0_[0] ),
        .I5(match_flag_pb[7]),
        .O(\genblk8[0].right_edge_found_pb[0]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair39" *) 
  LUT4 #(
    .INIT(16'h0002)) 
    \genblk8[0].right_edge_found_pb[0]_i_3 
       (.I0(\genblk8[0].right_edge_found_pb[0]_i_6_n_0 ),
        .I1(\genblk7[0].compare_err_pb_latch_r_reg_n_0_[0] ),
        .I2(match_flag_pb[0]),
        .I3(match_flag_pb[1]),
        .O(\genblk8[0].right_edge_found_pb[0]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair14" *) 
  LUT5 #(
    .INIT(32'h00400000)) 
    \genblk8[0].right_edge_found_pb[0]_i_4 
       (.I0(prbs_state_r[4]),
        .I1(prbs_state_r[0]),
        .I2(prbs_state_r[2]),
        .I3(prbs_state_r[1]),
        .I4(prbs_state_r[3]),
        .O(\genblk8[0].right_edge_found_pb[0]_i_4_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \genblk8[0].right_edge_found_pb[0]_i_5 
       (.I0(match_flag_pb[6]),
        .I1(match_flag_pb[4]),
        .I2(match_flag_pb[1]),
        .I3(match_flag_pb[5]),
        .O(\genblk8[0].right_edge_found_pb[0]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h0000000100000000)) 
    \genblk8[0].right_edge_found_pb[0]_i_6 
       (.I0(match_flag_pb[2]),
        .I1(match_flag_pb[3]),
        .I2(match_flag_pb[4]),
        .I3(match_flag_pb[5]),
        .I4(match_flag_pb[6]),
        .I5(match_flag_pb[7]),
        .O(\genblk8[0].right_edge_found_pb[0]_i_6_n_0 ));
  FDRE \genblk8[0].right_edge_found_pb_reg[0] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\genblk8[0].right_edge_found_pb[0]_i_1_n_0 ),
        .Q(\genblk8[0].right_edge_found_pb_reg_n_0_[0] ),
        .R(\bit_cnt[7]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h8F88)) 
    \genblk8[1].left_edge_updated[1]_i_1 
       (.I0(p_154_out),
        .I1(\genblk8[1].right_edge_found_pb[1]_i_3_n_0 ),
        .I2(\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_3_n_0 ),
        .I3(left_edge_updated[1]),
        .O(\genblk8[1].left_edge_updated[1]_i_1_n_0 ));
  FDRE \genblk8[1].left_edge_updated_reg[1] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\genblk8[1].left_edge_updated[1]_i_1_n_0 ),
        .Q(left_edge_updated[1]),
        .R(\bit_cnt[7]_i_1_n_0 ));
  FDSE \genblk8[1].match_flag_pb_reg[10] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(p_154_out),
        .D(match_flag_pb[9]),
        .Q(match_flag_pb[10]),
        .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 ));
  FDSE \genblk8[1].match_flag_pb_reg[11] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(p_154_out),
        .D(match_flag_pb[10]),
        .Q(match_flag_pb[11]),
        .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 ));
  FDSE \genblk8[1].match_flag_pb_reg[12] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(p_154_out),
        .D(match_flag_pb[11]),
        .Q(match_flag_pb[12]),
        .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 ));
  FDSE \genblk8[1].match_flag_pb_reg[13] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(p_154_out),
        .D(match_flag_pb[12]),
        .Q(match_flag_pb[13]),
        .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 ));
  FDSE \genblk8[1].match_flag_pb_reg[14] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(p_154_out),
        .D(match_flag_pb[13]),
        .Q(match_flag_pb[14]),
        .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 ));
  FDSE \genblk8[1].match_flag_pb_reg[15] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(p_154_out),
        .D(match_flag_pb[14]),
        .Q(match_flag_pb[15]),
        .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 ));
  FDSE \genblk8[1].match_flag_pb_reg[8] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(p_154_out),
        .D(\genblk7[1].compare_err_pb_latch_r_reg_n_0_[1] ),
        .Q(match_flag_pb[8]),
        .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 ));
  FDSE \genblk8[1].match_flag_pb_reg[9] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(p_154_out),
        .D(match_flag_pb[8]),
        .Q(match_flag_pb[9]),
        .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h1F001F00AAAABFAA)) 
    \genblk8[1].right_edge_found_pb[1]_i_1 
       (.I0(\genblk8[1].right_edge_found_pb_reg_n_0_[1] ),
        .I1(prbs_dqs_tap_limit_r_i_2_n_0),
        .I2(\genblk8[1].right_edge_found_pb[1]_i_2_n_0 ),
        .I3(p_154_out),
        .I4(\genblk8[1].right_edge_found_pb[1]_i_3_n_0 ),
        .I5(\genblk8[0].right_edge_found_pb[0]_i_4_n_0 ),
        .O(\genblk8[1].right_edge_found_pb[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFEFFFF)) 
    \genblk8[1].right_edge_found_pb[1]_i_2 
       (.I0(\genblk8[1].right_edge_found_pb[1]_i_4_n_0 ),
        .I1(match_flag_pb[11]),
        .I2(match_flag_pb[10]),
        .I3(match_flag_pb[8]),
        .I4(\genblk7[1].compare_err_pb_latch_r_reg_n_0_[1] ),
        .I5(match_flag_pb[15]),
        .O(\genblk8[1].right_edge_found_pb[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000100)) 
    \genblk8[1].right_edge_found_pb[1]_i_3 
       (.I0(match_flag_pb[11]),
        .I1(match_flag_pb[10]),
        .I2(match_flag_pb[8]),
        .I3(match_flag_pb[15]),
        .I4(\genblk7[1].compare_err_pb_latch_r_reg_n_0_[1] ),
        .I5(\genblk8[1].right_edge_found_pb[1]_i_4_n_0 ),
        .O(\genblk8[1].right_edge_found_pb[1]_i_3_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \genblk8[1].right_edge_found_pb[1]_i_4 
       (.I0(match_flag_pb[14]),
        .I1(match_flag_pb[12]),
        .I2(match_flag_pb[9]),
        .I3(match_flag_pb[13]),
        .O(\genblk8[1].right_edge_found_pb[1]_i_4_n_0 ));
  FDRE \genblk8[1].right_edge_found_pb_reg[1] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\genblk8[1].right_edge_found_pb[1]_i_1_n_0 ),
        .Q(\genblk8[1].right_edge_found_pb_reg_n_0_[1] ),
        .R(\bit_cnt[7]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFBFFFFFFAAAAAAAA)) 
    \genblk8[2].left_edge_updated[2]_i_1 
       (.I0(left_edge_found_pb85_out),
        .I1(prbs_state_r[3]),
        .I2(prbs_state_r[4]),
        .I3(prbs_state_r[0]),
        .I4(prbs_state_r[2]),
        .I5(left_edge_updated[2]),
        .O(\genblk8[2].left_edge_updated[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000200)) 
    \genblk8[2].left_edge_updated[2]_i_2 
       (.I0(p_154_out),
        .I1(match_flag_pb[16]),
        .I2(match_flag_pb[17]),
        .I3(match_flag_pb[23]),
        .I4(\genblk7[2].compare_err_pb_latch_r_reg_n_0_[2] ),
        .I5(\genblk8[2].right_edge_found_pb[2]_i_4_n_0 ),
        .O(left_edge_found_pb85_out));
  FDRE \genblk8[2].left_edge_updated_reg[2] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\genblk8[2].left_edge_updated[2]_i_1_n_0 ),
        .Q(left_edge_updated[2]),
        .R(\bit_cnt[7]_i_1_n_0 ));
  FDSE \genblk8[2].match_flag_pb_reg[16] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(p_154_out),
        .D(\genblk7[2].compare_err_pb_latch_r_reg_n_0_[2] ),
        .Q(match_flag_pb[16]),
        .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 ));
  FDSE \genblk8[2].match_flag_pb_reg[17] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(p_154_out),
        .D(match_flag_pb[16]),
        .Q(match_flag_pb[17]),
        .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 ));
  FDSE \genblk8[2].match_flag_pb_reg[18] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(p_154_out),
        .D(match_flag_pb[17]),
        .Q(match_flag_pb[18]),
        .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 ));
  FDSE \genblk8[2].match_flag_pb_reg[19] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(p_154_out),
        .D(match_flag_pb[18]),
        .Q(match_flag_pb[19]),
        .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 ));
  FDSE \genblk8[2].match_flag_pb_reg[20] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(p_154_out),
        .D(match_flag_pb[19]),
        .Q(match_flag_pb[20]),
        .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 ));
  FDSE \genblk8[2].match_flag_pb_reg[21] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(p_154_out),
        .D(match_flag_pb[20]),
        .Q(match_flag_pb[21]),
        .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 ));
  FDSE \genblk8[2].match_flag_pb_reg[22] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(p_154_out),
        .D(match_flag_pb[21]),
        .Q(match_flag_pb[22]),
        .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 ));
  FDSE \genblk8[2].match_flag_pb_reg[23] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(p_154_out),
        .D(match_flag_pb[22]),
        .Q(match_flag_pb[23]),
        .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h1F1F0000BFAAAAAA)) 
    \genblk8[2].right_edge_found_pb[2]_i_1 
       (.I0(\genblk8[2].right_edge_found_pb_reg_n_0_[2] ),
        .I1(prbs_dqs_tap_limit_r_i_2_n_0),
        .I2(\genblk8[2].right_edge_found_pb[2]_i_2_n_0 ),
        .I3(\genblk8[2].right_edge_found_pb[2]_i_3_n_0 ),
        .I4(p_154_out),
        .I5(\genblk8[0].right_edge_found_pb[0]_i_4_n_0 ),
        .O(\genblk8[2].right_edge_found_pb[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair24" *) 
  LUT5 #(
    .INIT(32'hFFFFFFEF)) 
    \genblk8[2].right_edge_found_pb[2]_i_2 
       (.I0(\genblk8[2].right_edge_found_pb[2]_i_4_n_0 ),
        .I1(match_flag_pb[23]),
        .I2(\genblk7[2].compare_err_pb_latch_r_reg_n_0_[2] ),
        .I3(match_flag_pb[17]),
        .I4(match_flag_pb[16]),
        .O(\genblk8[2].right_edge_found_pb[2]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair24" *) 
  LUT5 #(
    .INIT(32'hFFFFFFEF)) 
    \genblk8[2].right_edge_found_pb[2]_i_3 
       (.I0(\genblk8[2].right_edge_found_pb[2]_i_4_n_0 ),
        .I1(\genblk7[2].compare_err_pb_latch_r_reg_n_0_[2] ),
        .I2(match_flag_pb[23]),
        .I3(match_flag_pb[17]),
        .I4(match_flag_pb[16]),
        .O(\genblk8[2].right_edge_found_pb[2]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \genblk8[2].right_edge_found_pb[2]_i_4 
       (.I0(match_flag_pb[22]),
        .I1(match_flag_pb[18]),
        .I2(match_flag_pb[19]),
        .I3(match_flag_pb[21]),
        .I4(match_flag_pb[20]),
        .O(\genblk8[2].right_edge_found_pb[2]_i_4_n_0 ));
  FDRE \genblk8[2].right_edge_found_pb_reg[2] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\genblk8[2].right_edge_found_pb[2]_i_1_n_0 ),
        .Q(\genblk8[2].right_edge_found_pb_reg_n_0_[2] ),
        .R(\bit_cnt[7]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h88BF8880)) 
    \genblk8[3].left_edge_updated[3]_i_1 
       (.I0(\genblk8[3].left_edge_updated[3]_i_2_n_0 ),
        .I1(p_154_out),
        .I2(\genblk8[3].right_edge_found_pb[3]_i_3_n_0 ),
        .I3(\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_3_n_0 ),
        .I4(left_edge_updated[3]),
        .O(\genblk8[3].left_edge_updated[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000100)) 
    \genblk8[3].left_edge_updated[3]_i_2 
       (.I0(match_flag_pb[27]),
        .I1(match_flag_pb[26]),
        .I2(match_flag_pb[24]),
        .I3(match_flag_pb[31]),
        .I4(\genblk7[3].compare_err_pb_latch_r_reg_n_0_[3] ),
        .I5(\genblk8[3].right_edge_found_pb[3]_i_4_n_0 ),
        .O(\genblk8[3].left_edge_updated[3]_i_2_n_0 ));
  FDRE \genblk8[3].left_edge_updated_reg[3] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\genblk8[3].left_edge_updated[3]_i_1_n_0 ),
        .Q(left_edge_updated[3]),
        .R(\bit_cnt[7]_i_1_n_0 ));
  FDSE \genblk8[3].match_flag_pb_reg[24] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(p_154_out),
        .D(\genblk7[3].compare_err_pb_latch_r_reg_n_0_[3] ),
        .Q(match_flag_pb[24]),
        .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 ));
  FDSE \genblk8[3].match_flag_pb_reg[25] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(p_154_out),
        .D(match_flag_pb[24]),
        .Q(match_flag_pb[25]),
        .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 ));
  FDSE \genblk8[3].match_flag_pb_reg[26] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(p_154_out),
        .D(match_flag_pb[25]),
        .Q(match_flag_pb[26]),
        .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 ));
  FDSE \genblk8[3].match_flag_pb_reg[27] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(p_154_out),
        .D(match_flag_pb[26]),
        .Q(match_flag_pb[27]),
        .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 ));
  FDSE \genblk8[3].match_flag_pb_reg[28] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(p_154_out),
        .D(match_flag_pb[27]),
        .Q(match_flag_pb[28]),
        .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 ));
  FDSE \genblk8[3].match_flag_pb_reg[29] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(p_154_out),
        .D(match_flag_pb[28]),
        .Q(match_flag_pb[29]),
        .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 ));
  FDSE \genblk8[3].match_flag_pb_reg[30] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(p_154_out),
        .D(match_flag_pb[29]),
        .Q(match_flag_pb[30]),
        .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 ));
  FDSE \genblk8[3].match_flag_pb_reg[31] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(p_154_out),
        .D(match_flag_pb[30]),
        .Q(match_flag_pb[31]),
        .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h1F001F00AAAABFAA)) 
    \genblk8[3].right_edge_found_pb[3]_i_1 
       (.I0(\genblk8[3].right_edge_found_pb_reg_n_0_[3] ),
        .I1(prbs_dqs_tap_limit_r_i_2_n_0),
        .I2(\genblk8[3].right_edge_found_pb[3]_i_2_n_0 ),
        .I3(p_154_out),
        .I4(\genblk8[3].right_edge_found_pb[3]_i_3_n_0 ),
        .I5(\genblk8[0].right_edge_found_pb[0]_i_4_n_0 ),
        .O(\genblk8[3].right_edge_found_pb[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFEFFFF)) 
    \genblk8[3].right_edge_found_pb[3]_i_2 
       (.I0(\genblk8[3].right_edge_found_pb[3]_i_4_n_0 ),
        .I1(match_flag_pb[27]),
        .I2(match_flag_pb[26]),
        .I3(match_flag_pb[24]),
        .I4(\genblk7[3].compare_err_pb_latch_r_reg_n_0_[3] ),
        .I5(match_flag_pb[31]),
        .O(\genblk8[3].right_edge_found_pb[3]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair47" *) 
  LUT4 #(
    .INIT(16'h0002)) 
    \genblk8[3].right_edge_found_pb[3]_i_3 
       (.I0(\genblk8[3].right_edge_found_pb[3]_i_5_n_0 ),
        .I1(\genblk7[3].compare_err_pb_latch_r_reg_n_0_[3] ),
        .I2(match_flag_pb[24]),
        .I3(match_flag_pb[25]),
        .O(\genblk8[3].right_edge_found_pb[3]_i_3_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \genblk8[3].right_edge_found_pb[3]_i_4 
       (.I0(match_flag_pb[30]),
        .I1(match_flag_pb[28]),
        .I2(match_flag_pb[25]),
        .I3(match_flag_pb[29]),
        .O(\genblk8[3].right_edge_found_pb[3]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h0000000100000000)) 
    \genblk8[3].right_edge_found_pb[3]_i_5 
       (.I0(match_flag_pb[26]),
        .I1(match_flag_pb[27]),
        .I2(match_flag_pb[28]),
        .I3(match_flag_pb[29]),
        .I4(match_flag_pb[30]),
        .I5(match_flag_pb[31]),
        .O(\genblk8[3].right_edge_found_pb[3]_i_5_n_0 ));
  FDRE \genblk8[3].right_edge_found_pb_reg[3] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\genblk8[3].right_edge_found_pb[3]_i_1_n_0 ),
        .Q(\genblk8[3].right_edge_found_pb_reg_n_0_[3] ),
        .R(\bit_cnt[7]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h88BF8880)) 
    \genblk8[4].left_edge_updated[4]_i_1 
       (.I0(\genblk8[4].left_edge_updated[4]_i_2_n_0 ),
        .I1(p_154_out),
        .I2(\genblk8[4].right_edge_found_pb[4]_i_3_n_0 ),
        .I3(\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_3_n_0 ),
        .I4(left_edge_updated[4]),
        .O(\genblk8[4].left_edge_updated[4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000100)) 
    \genblk8[4].left_edge_updated[4]_i_2 
       (.I0(match_flag_pb[35]),
        .I1(match_flag_pb[34]),
        .I2(match_flag_pb[32]),
        .I3(match_flag_pb[39]),
        .I4(\genblk7[4].compare_err_pb_latch_r_reg_n_0_[4] ),
        .I5(\genblk8[4].right_edge_found_pb[4]_i_4_n_0 ),
        .O(\genblk8[4].left_edge_updated[4]_i_2_n_0 ));
  FDRE \genblk8[4].left_edge_updated_reg[4] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\genblk8[4].left_edge_updated[4]_i_1_n_0 ),
        .Q(left_edge_updated[4]),
        .R(\bit_cnt[7]_i_1_n_0 ));
  FDSE \genblk8[4].match_flag_pb_reg[32] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(p_154_out),
        .D(\genblk7[4].compare_err_pb_latch_r_reg_n_0_[4] ),
        .Q(match_flag_pb[32]),
        .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 ));
  FDSE \genblk8[4].match_flag_pb_reg[33] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(p_154_out),
        .D(match_flag_pb[32]),
        .Q(match_flag_pb[33]),
        .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 ));
  FDSE \genblk8[4].match_flag_pb_reg[34] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(p_154_out),
        .D(match_flag_pb[33]),
        .Q(match_flag_pb[34]),
        .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 ));
  FDSE \genblk8[4].match_flag_pb_reg[35] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(p_154_out),
        .D(match_flag_pb[34]),
        .Q(match_flag_pb[35]),
        .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 ));
  FDSE \genblk8[4].match_flag_pb_reg[36] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(p_154_out),
        .D(match_flag_pb[35]),
        .Q(match_flag_pb[36]),
        .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 ));
  FDSE \genblk8[4].match_flag_pb_reg[37] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(p_154_out),
        .D(match_flag_pb[36]),
        .Q(match_flag_pb[37]),
        .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 ));
  FDSE \genblk8[4].match_flag_pb_reg[38] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(p_154_out),
        .D(match_flag_pb[37]),
        .Q(match_flag_pb[38]),
        .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 ));
  FDSE \genblk8[4].match_flag_pb_reg[39] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(p_154_out),
        .D(match_flag_pb[38]),
        .Q(match_flag_pb[39]),
        .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h1F001F00AAAABFAA)) 
    \genblk8[4].right_edge_found_pb[4]_i_1 
       (.I0(\genblk8[4].right_edge_found_pb_reg_n_0_[4] ),
        .I1(prbs_dqs_tap_limit_r_i_2_n_0),
        .I2(\genblk8[4].right_edge_found_pb[4]_i_2_n_0 ),
        .I3(p_154_out),
        .I4(\genblk8[4].right_edge_found_pb[4]_i_3_n_0 ),
        .I5(\genblk8[0].right_edge_found_pb[0]_i_4_n_0 ),
        .O(\genblk8[4].right_edge_found_pb[4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFEFFFF)) 
    \genblk8[4].right_edge_found_pb[4]_i_2 
       (.I0(\genblk8[4].right_edge_found_pb[4]_i_4_n_0 ),
        .I1(match_flag_pb[35]),
        .I2(match_flag_pb[34]),
        .I3(match_flag_pb[32]),
        .I4(\genblk7[4].compare_err_pb_latch_r_reg_n_0_[4] ),
        .I5(match_flag_pb[39]),
        .O(\genblk8[4].right_edge_found_pb[4]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair53" *) 
  LUT4 #(
    .INIT(16'h0002)) 
    \genblk8[4].right_edge_found_pb[4]_i_3 
       (.I0(\genblk8[4].right_edge_found_pb[4]_i_5_n_0 ),
        .I1(\genblk7[4].compare_err_pb_latch_r_reg_n_0_[4] ),
        .I2(match_flag_pb[32]),
        .I3(match_flag_pb[33]),
        .O(\genblk8[4].right_edge_found_pb[4]_i_3_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \genblk8[4].right_edge_found_pb[4]_i_4 
       (.I0(match_flag_pb[38]),
        .I1(match_flag_pb[36]),
        .I2(match_flag_pb[33]),
        .I3(match_flag_pb[37]),
        .O(\genblk8[4].right_edge_found_pb[4]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h0000000100000000)) 
    \genblk8[4].right_edge_found_pb[4]_i_5 
       (.I0(match_flag_pb[34]),
        .I1(match_flag_pb[35]),
        .I2(match_flag_pb[36]),
        .I3(match_flag_pb[37]),
        .I4(match_flag_pb[38]),
        .I5(match_flag_pb[39]),
        .O(\genblk8[4].right_edge_found_pb[4]_i_5_n_0 ));
  FDRE \genblk8[4].right_edge_found_pb_reg[4] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\genblk8[4].right_edge_found_pb[4]_i_1_n_0 ),
        .Q(\genblk8[4].right_edge_found_pb_reg_n_0_[4] ),
        .R(\bit_cnt[7]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h88BF8880)) 
    \genblk8[5].left_edge_updated[5]_i_1 
       (.I0(\genblk8[5].left_edge_updated[5]_i_2_n_0 ),
        .I1(p_154_out),
        .I2(\genblk8[5].right_edge_found_pb[5]_i_3_n_0 ),
        .I3(\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_3_n_0 ),
        .I4(left_edge_updated[5]),
        .O(\genblk8[5].left_edge_updated[5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000100)) 
    \genblk8[5].left_edge_updated[5]_i_2 
       (.I0(match_flag_pb[43]),
        .I1(match_flag_pb[42]),
        .I2(match_flag_pb[40]),
        .I3(match_flag_pb[47]),
        .I4(\genblk7[5].compare_err_pb_latch_r_reg_n_0_[5] ),
        .I5(\genblk8[5].right_edge_found_pb[5]_i_4_n_0 ),
        .O(\genblk8[5].left_edge_updated[5]_i_2_n_0 ));
  FDRE \genblk8[5].left_edge_updated_reg[5] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\genblk8[5].left_edge_updated[5]_i_1_n_0 ),
        .Q(left_edge_updated[5]),
        .R(\bit_cnt[7]_i_1_n_0 ));
  FDSE \genblk8[5].match_flag_pb_reg[40] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(p_154_out),
        .D(\genblk7[5].compare_err_pb_latch_r_reg_n_0_[5] ),
        .Q(match_flag_pb[40]),
        .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 ));
  FDSE \genblk8[5].match_flag_pb_reg[41] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(p_154_out),
        .D(match_flag_pb[40]),
        .Q(match_flag_pb[41]),
        .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 ));
  FDSE \genblk8[5].match_flag_pb_reg[42] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(p_154_out),
        .D(match_flag_pb[41]),
        .Q(match_flag_pb[42]),
        .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 ));
  FDSE \genblk8[5].match_flag_pb_reg[43] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(p_154_out),
        .D(match_flag_pb[42]),
        .Q(match_flag_pb[43]),
        .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 ));
  FDSE \genblk8[5].match_flag_pb_reg[44] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(p_154_out),
        .D(match_flag_pb[43]),
        .Q(match_flag_pb[44]),
        .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 ));
  FDSE \genblk8[5].match_flag_pb_reg[45] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(p_154_out),
        .D(match_flag_pb[44]),
        .Q(match_flag_pb[45]),
        .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 ));
  FDSE \genblk8[5].match_flag_pb_reg[46] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(p_154_out),
        .D(match_flag_pb[45]),
        .Q(match_flag_pb[46]),
        .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 ));
  FDSE \genblk8[5].match_flag_pb_reg[47] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(p_154_out),
        .D(match_flag_pb[46]),
        .Q(match_flag_pb[47]),
        .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h1F001F00AAAABFAA)) 
    \genblk8[5].right_edge_found_pb[5]_i_1 
       (.I0(\genblk8[5].right_edge_found_pb_reg_n_0_[5] ),
        .I1(prbs_dqs_tap_limit_r_i_2_n_0),
        .I2(\genblk8[5].right_edge_found_pb[5]_i_2_n_0 ),
        .I3(p_154_out),
        .I4(\genblk8[5].right_edge_found_pb[5]_i_3_n_0 ),
        .I5(\genblk8[0].right_edge_found_pb[0]_i_4_n_0 ),
        .O(\genblk8[5].right_edge_found_pb[5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFEFFFF)) 
    \genblk8[5].right_edge_found_pb[5]_i_2 
       (.I0(\genblk8[5].right_edge_found_pb[5]_i_4_n_0 ),
        .I1(match_flag_pb[43]),
        .I2(match_flag_pb[42]),
        .I3(match_flag_pb[40]),
        .I4(\genblk7[5].compare_err_pb_latch_r_reg_n_0_[5] ),
        .I5(match_flag_pb[47]),
        .O(\genblk8[5].right_edge_found_pb[5]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair61" *) 
  LUT4 #(
    .INIT(16'h0002)) 
    \genblk8[5].right_edge_found_pb[5]_i_3 
       (.I0(\genblk8[5].right_edge_found_pb[5]_i_5_n_0 ),
        .I1(\genblk7[5].compare_err_pb_latch_r_reg_n_0_[5] ),
        .I2(match_flag_pb[40]),
        .I3(match_flag_pb[41]),
        .O(\genblk8[5].right_edge_found_pb[5]_i_3_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \genblk8[5].right_edge_found_pb[5]_i_4 
       (.I0(match_flag_pb[46]),
        .I1(match_flag_pb[44]),
        .I2(match_flag_pb[41]),
        .I3(match_flag_pb[45]),
        .O(\genblk8[5].right_edge_found_pb[5]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h0000000100000000)) 
    \genblk8[5].right_edge_found_pb[5]_i_5 
       (.I0(match_flag_pb[42]),
        .I1(match_flag_pb[43]),
        .I2(match_flag_pb[44]),
        .I3(match_flag_pb[45]),
        .I4(match_flag_pb[46]),
        .I5(match_flag_pb[47]),
        .O(\genblk8[5].right_edge_found_pb[5]_i_5_n_0 ));
  FDRE \genblk8[5].right_edge_found_pb_reg[5] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\genblk8[5].right_edge_found_pb[5]_i_1_n_0 ),
        .Q(\genblk8[5].right_edge_found_pb_reg_n_0_[5] ),
        .R(\bit_cnt[7]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h88BF8880)) 
    \genblk8[6].left_edge_updated[6]_i_1 
       (.I0(\genblk8[6].left_edge_updated[6]_i_2_n_0 ),
        .I1(p_154_out),
        .I2(\genblk8[6].right_edge_found_pb[6]_i_3_n_0 ),
        .I3(\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_3_n_0 ),
        .I4(left_edge_updated[6]),
        .O(\genblk8[6].left_edge_updated[6]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000100)) 
    \genblk8[6].left_edge_updated[6]_i_2 
       (.I0(match_flag_pb[51]),
        .I1(match_flag_pb[50]),
        .I2(match_flag_pb[48]),
        .I3(match_flag_pb[55]),
        .I4(\genblk7[6].compare_err_pb_latch_r_reg_n_0_[6] ),
        .I5(\genblk8[6].right_edge_found_pb[6]_i_4_n_0 ),
        .O(\genblk8[6].left_edge_updated[6]_i_2_n_0 ));
  FDRE \genblk8[6].left_edge_updated_reg[6] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\genblk8[6].left_edge_updated[6]_i_1_n_0 ),
        .Q(left_edge_updated[6]),
        .R(\bit_cnt[7]_i_1_n_0 ));
  FDSE \genblk8[6].match_flag_pb_reg[48] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(p_154_out),
        .D(\genblk7[6].compare_err_pb_latch_r_reg_n_0_[6] ),
        .Q(match_flag_pb[48]),
        .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 ));
  FDSE \genblk8[6].match_flag_pb_reg[49] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(p_154_out),
        .D(match_flag_pb[48]),
        .Q(match_flag_pb[49]),
        .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 ));
  FDSE \genblk8[6].match_flag_pb_reg[50] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(p_154_out),
        .D(match_flag_pb[49]),
        .Q(match_flag_pb[50]),
        .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 ));
  FDSE \genblk8[6].match_flag_pb_reg[51] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(p_154_out),
        .D(match_flag_pb[50]),
        .Q(match_flag_pb[51]),
        .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 ));
  FDSE \genblk8[6].match_flag_pb_reg[52] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(p_154_out),
        .D(match_flag_pb[51]),
        .Q(match_flag_pb[52]),
        .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 ));
  FDSE \genblk8[6].match_flag_pb_reg[53] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(p_154_out),
        .D(match_flag_pb[52]),
        .Q(match_flag_pb[53]),
        .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 ));
  FDSE \genblk8[6].match_flag_pb_reg[54] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(p_154_out),
        .D(match_flag_pb[53]),
        .Q(match_flag_pb[54]),
        .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 ));
  FDSE \genblk8[6].match_flag_pb_reg[55] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(p_154_out),
        .D(match_flag_pb[54]),
        .Q(match_flag_pb[55]),
        .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h1F001F00AAAABFAA)) 
    \genblk8[6].right_edge_found_pb[6]_i_1 
       (.I0(\genblk8[6].right_edge_found_pb_reg_n_0_[6] ),
        .I1(prbs_dqs_tap_limit_r_i_2_n_0),
        .I2(\genblk8[6].right_edge_found_pb[6]_i_2_n_0 ),
        .I3(p_154_out),
        .I4(\genblk8[6].right_edge_found_pb[6]_i_3_n_0 ),
        .I5(\genblk8[0].right_edge_found_pb[0]_i_4_n_0 ),
        .O(\genblk8[6].right_edge_found_pb[6]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFEFFFF)) 
    \genblk8[6].right_edge_found_pb[6]_i_2 
       (.I0(\genblk8[6].right_edge_found_pb[6]_i_4_n_0 ),
        .I1(match_flag_pb[51]),
        .I2(match_flag_pb[50]),
        .I3(match_flag_pb[48]),
        .I4(\genblk7[6].compare_err_pb_latch_r_reg_n_0_[6] ),
        .I5(match_flag_pb[55]),
        .O(\genblk8[6].right_edge_found_pb[6]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair62" *) 
  LUT4 #(
    .INIT(16'h0002)) 
    \genblk8[6].right_edge_found_pb[6]_i_3 
       (.I0(\genblk8[6].right_edge_found_pb[6]_i_5_n_0 ),
        .I1(\genblk7[6].compare_err_pb_latch_r_reg_n_0_[6] ),
        .I2(match_flag_pb[48]),
        .I3(match_flag_pb[49]),
        .O(\genblk8[6].right_edge_found_pb[6]_i_3_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \genblk8[6].right_edge_found_pb[6]_i_4 
       (.I0(match_flag_pb[54]),
        .I1(match_flag_pb[52]),
        .I2(match_flag_pb[49]),
        .I3(match_flag_pb[53]),
        .O(\genblk8[6].right_edge_found_pb[6]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h0000000100000000)) 
    \genblk8[6].right_edge_found_pb[6]_i_5 
       (.I0(match_flag_pb[50]),
        .I1(match_flag_pb[51]),
        .I2(match_flag_pb[52]),
        .I3(match_flag_pb[53]),
        .I4(match_flag_pb[54]),
        .I5(match_flag_pb[55]),
        .O(\genblk8[6].right_edge_found_pb[6]_i_5_n_0 ));
  FDRE \genblk8[6].right_edge_found_pb_reg[6] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\genblk8[6].right_edge_found_pb[6]_i_1_n_0 ),
        .Q(\genblk8[6].right_edge_found_pb_reg_n_0_[6] ),
        .R(\bit_cnt[7]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h8F88)) 
    \genblk8[7].left_edge_updated[7]_i_1 
       (.I0(p_154_out),
        .I1(\genblk8[7].right_edge_found_pb[7]_i_3_n_0 ),
        .I2(\cmp_err_pb_4to1.(null)[0].compare_err_pb[0]_i_3_n_0 ),
        .I3(left_edge_updated[7]),
        .O(\genblk8[7].left_edge_updated[7]_i_1_n_0 ));
  FDRE \genblk8[7].left_edge_updated_reg[7] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\genblk8[7].left_edge_updated[7]_i_1_n_0 ),
        .Q(left_edge_updated[7]),
        .R(\bit_cnt[7]_i_1_n_0 ));
  FDSE \genblk8[7].match_flag_pb_reg[56] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(p_154_out),
        .D(\genblk7[7].compare_err_pb_latch_r_reg_n_0_[7] ),
        .Q(match_flag_pb[56]),
        .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 ));
  FDSE \genblk8[7].match_flag_pb_reg[57] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(p_154_out),
        .D(match_flag_pb[56]),
        .Q(match_flag_pb[57]),
        .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 ));
  FDSE \genblk8[7].match_flag_pb_reg[58] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(p_154_out),
        .D(match_flag_pb[57]),
        .Q(match_flag_pb[58]),
        .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 ));
  FDSE \genblk8[7].match_flag_pb_reg[59] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(p_154_out),
        .D(match_flag_pb[58]),
        .Q(match_flag_pb[59]),
        .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 ));
  FDSE \genblk8[7].match_flag_pb_reg[60] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(p_154_out),
        .D(match_flag_pb[59]),
        .Q(match_flag_pb[60]),
        .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 ));
  FDSE \genblk8[7].match_flag_pb_reg[61] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(p_154_out),
        .D(match_flag_pb[60]),
        .Q(match_flag_pb[61]),
        .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 ));
  FDSE \genblk8[7].match_flag_pb_reg[62] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(p_154_out),
        .D(match_flag_pb[61]),
        .Q(match_flag_pb[62]),
        .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 ));
  FDSE \genblk8[7].match_flag_pb_reg[63] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(p_154_out),
        .D(match_flag_pb[62]),
        .Q(match_flag_pb[63]),
        .S(\genblk8[0].match_flag_pb[7]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hCD00CD00AAAAEFAA)) 
    \genblk8[7].right_edge_found_pb[7]_i_1 
       (.I0(\genblk8[7].right_edge_found_pb_reg_n_0_[7] ),
        .I1(\genblk8[7].right_edge_found_pb[7]_i_2_n_0 ),
        .I2(prbs_dqs_tap_limit_r_i_2_n_0),
        .I3(p_154_out),
        .I4(\genblk8[7].right_edge_found_pb[7]_i_3_n_0 ),
        .I5(\genblk8[0].right_edge_found_pb[0]_i_4_n_0 ),
        .O(\genblk8[7].right_edge_found_pb[7]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000100)) 
    \genblk8[7].right_edge_found_pb[7]_i_2 
       (.I0(match_flag_pb[59]),
        .I1(match_flag_pb[58]),
        .I2(match_flag_pb[56]),
        .I3(\genblk7[7].compare_err_pb_latch_r_reg_n_0_[7] ),
        .I4(match_flag_pb[63]),
        .I5(\genblk8[7].right_edge_found_pb[7]_i_4_n_0 ),
        .O(\genblk8[7].right_edge_found_pb[7]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000100)) 
    \genblk8[7].right_edge_found_pb[7]_i_3 
       (.I0(match_flag_pb[59]),
        .I1(match_flag_pb[58]),
        .I2(match_flag_pb[56]),
        .I3(match_flag_pb[63]),
        .I4(\genblk7[7].compare_err_pb_latch_r_reg_n_0_[7] ),
        .I5(\genblk8[7].right_edge_found_pb[7]_i_4_n_0 ),
        .O(\genblk8[7].right_edge_found_pb[7]_i_3_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \genblk8[7].right_edge_found_pb[7]_i_4 
       (.I0(match_flag_pb[62]),
        .I1(match_flag_pb[60]),
        .I2(match_flag_pb[57]),
        .I3(match_flag_pb[61]),
        .O(\genblk8[7].right_edge_found_pb[7]_i_4_n_0 ));
  FDRE \genblk8[7].right_edge_found_pb_reg[7] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\genblk8[7].right_edge_found_pb[7]_i_1_n_0 ),
        .Q(\genblk8[7].right_edge_found_pb_reg_n_0_[7] ),
        .R(\bit_cnt[7]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hAAAAAA8A)) 
    \init_state_r[1]_i_33 
       (.I0(\init_state_r[0]_i_27 ),
        .I1(prbs_last_byte_done),
        .I2(rdlvl_last_byte_done),
        .I3(prbs_rdlvl_done_reg_0),
        .I4(\init_state_r[0]_i_27_0 ),
        .O(dqs_found_done_r_reg));
  LUT4 #(
    .INIT(16'h80B0)) 
    \init_state_r[2]_i_37 
       (.I0(prbs_rdlvl_done_reg_0),
        .I1(\gen_byte_sel_div2.byte_sel_cnt_reg[0] ),
        .I2(\init_state_r[0]_i_27 ),
        .I3(\gen_byte_sel_div2.byte_sel_cnt_reg[0]_0 ),
        .O(prbs_rdlvl_done_reg_1));
  (* SOFT_HLUTNM = "soft_lutpair70" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \largest_left_edge[0]_i_1 
       (.I0(prbs_state_r[2]),
        .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),
        .O(\largest_left_edge[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair70" *) 
  LUT3 #(
    .INIT(8'h60)) 
    \largest_left_edge[1]_i_1 
       (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),
        .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),
        .I2(prbs_state_r[2]),
        .O(\largest_left_edge[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair65" *) 
  LUT4 #(
    .INIT(16'h6A00)) 
    \largest_left_edge[2]_i_1 
       (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),
        .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),
        .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),
        .I3(prbs_state_r[2]),
        .O(\largest_left_edge[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair31" *) 
  LUT5 #(
    .INIT(32'h82222222)) 
    \largest_left_edge[3]_i_1 
       (.I0(prbs_state_r[2]),
        .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[3] ),
        .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),
        .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),
        .I4(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),
        .O(\largest_left_edge[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFF800000007F0000)) 
    \largest_left_edge[4]_i_1 
       (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),
        .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),
        .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),
        .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[3] ),
        .I4(prbs_state_r[2]),
        .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),
        .O(\largest_left_edge[4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0080001000000010)) 
    \largest_left_edge[5]_i_1 
       (.I0(prbs_state_r[0]),
        .I1(prbs_state_r[1]),
        .I2(prbs_state_r[3]),
        .I3(prbs_state_r[4]),
        .I4(prbs_state_r[2]),
        .I5(\largest_left_edge[5]_i_3_n_0 ),
        .O(\largest_left_edge[5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair46" *) 
  LUT4 #(
    .INIT(16'hD020)) 
    \largest_left_edge[5]_i_2 
       (.I0(\largest_left_edge[5]_i_4_n_0 ),
        .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),
        .I2(prbs_state_r[2]),
        .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),
        .O(\largest_left_edge[5]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h5555555555555551)) 
    \largest_left_edge[5]_i_3 
       (.I0(no_err_win_detected_latch_reg_n_0),
        .I1(\largest_left_edge[5]_i_5_n_0 ),
        .I2(left_edge_updated[7]),
        .I3(left_edge_updated[6]),
        .I4(left_edge_updated[5]),
        .I5(left_edge_updated[4]),
        .O(\largest_left_edge[5]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair38" *) 
  LUT4 #(
    .INIT(16'h007F)) 
    \largest_left_edge[5]_i_4 
       (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),
        .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),
        .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),
        .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[3] ),
        .O(\largest_left_edge[5]_i_4_n_0 ));
  LUT4 #(
    .INIT(16'h0001)) 
    \largest_left_edge[5]_i_5 
       (.I0(left_edge_updated[1]),
        .I1(left_edge_updated[0]),
        .I2(left_edge_updated[3]),
        .I3(left_edge_updated[2]),
        .O(\largest_left_edge[5]_i_5_n_0 ));
  FDRE \largest_left_edge_reg[0] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(\largest_left_edge[5]_i_1_n_0 ),
        .D(\largest_left_edge[0]_i_1_n_0 ),
        .Q(\largest_left_edge_reg_n_0_[0] ),
        .R(\samples_cnt_r_reg[0]_0 ));
  FDRE \largest_left_edge_reg[1] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(\largest_left_edge[5]_i_1_n_0 ),
        .D(\largest_left_edge[1]_i_1_n_0 ),
        .Q(\largest_left_edge_reg_n_0_[1] ),
        .R(\samples_cnt_r_reg[0]_0 ));
  FDRE \largest_left_edge_reg[2] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(\largest_left_edge[5]_i_1_n_0 ),
        .D(\largest_left_edge[2]_i_1_n_0 ),
        .Q(\largest_left_edge_reg_n_0_[2] ),
        .R(\samples_cnt_r_reg[0]_0 ));
  FDRE \largest_left_edge_reg[3] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(\largest_left_edge[5]_i_1_n_0 ),
        .D(\largest_left_edge[3]_i_1_n_0 ),
        .Q(\largest_left_edge_reg_n_0_[3] ),
        .R(\samples_cnt_r_reg[0]_0 ));
  FDRE \largest_left_edge_reg[4] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(\largest_left_edge[5]_i_1_n_0 ),
        .D(\largest_left_edge[4]_i_1_n_0 ),
        .Q(\largest_left_edge_reg_n_0_[4] ),
        .R(\samples_cnt_r_reg[0]_0 ));
  FDRE \largest_left_edge_reg[5] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(\largest_left_edge[5]_i_1_n_0 ),
        .D(\largest_left_edge[5]_i_2_n_0 ),
        .Q(\largest_left_edge_reg_n_0_[5] ),
        .R(\samples_cnt_r_reg[0]_0 ));
  LUT5 #(
    .INIT(32'hFFF3BBBB)) 
    \match_flag_and[0]_i_1 
       (.I0(compare_err_pb_and_reg_n_0),
        .I1(prbs_state_r[4]),
        .I2(num_samples_done_ind_reg_n_0),
        .I3(num_samples_done_r),
        .I4(prbs_state_r[1]),
        .O(\match_flag_and[0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFF3BBBB)) 
    \match_flag_and[1]_i_1 
       (.I0(\match_flag_and_reg_n_0_[0] ),
        .I1(prbs_state_r[4]),
        .I2(num_samples_done_ind_reg_n_0),
        .I3(num_samples_done_r),
        .I4(prbs_state_r[1]),
        .O(\match_flag_and[1]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFF3BBBB)) 
    \match_flag_and[2]_i_1 
       (.I0(\match_flag_and_reg_n_0_[1] ),
        .I1(prbs_state_r[4]),
        .I2(num_samples_done_ind_reg_n_0),
        .I3(num_samples_done_r),
        .I4(prbs_state_r[1]),
        .O(\match_flag_and[2]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFF3BBBB)) 
    \match_flag_and[3]_i_1 
       (.I0(\match_flag_and_reg_n_0_[2] ),
        .I1(prbs_state_r[4]),
        .I2(num_samples_done_ind_reg_n_0),
        .I3(num_samples_done_r),
        .I4(prbs_state_r[1]),
        .O(\match_flag_and[3]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFF3BBBB)) 
    \match_flag_and[4]_i_1 
       (.I0(\match_flag_and_reg_n_0_[3] ),
        .I1(prbs_state_r[4]),
        .I2(num_samples_done_ind_reg_n_0),
        .I3(num_samples_done_r),
        .I4(prbs_state_r[1]),
        .O(\match_flag_and[4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFF3BBBB)) 
    \match_flag_and[5]_i_1 
       (.I0(\match_flag_and_reg_n_0_[4] ),
        .I1(prbs_state_r[4]),
        .I2(num_samples_done_ind_reg_n_0),
        .I3(num_samples_done_r),
        .I4(prbs_state_r[1]),
        .O(\match_flag_and[5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair18" *) 
  LUT5 #(
    .INIT(32'hFFF3BBBB)) 
    \match_flag_and[6]_i_1 
       (.I0(\match_flag_and_reg_n_0_[5] ),
        .I1(prbs_state_r[4]),
        .I2(num_samples_done_ind_reg_n_0),
        .I3(num_samples_done_r),
        .I4(prbs_state_r[1]),
        .O(\match_flag_and[6]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h020C020C02040004)) 
    \match_flag_and[7]_i_1 
       (.I0(prbs_state_r[4]),
        .I1(prbs_state_r[0]),
        .I2(\prbs_state_r[4]_i_5_n_0 ),
        .I3(prbs_state_r[1]),
        .I4(num_samples_done_ind_reg_n_0),
        .I5(num_samples_done_r),
        .O(match_flag_and));
  LUT5 #(
    .INIT(32'hFFF3BBBB)) 
    \match_flag_and[7]_i_2 
       (.I0(\match_flag_and_reg_n_0_[6] ),
        .I1(prbs_state_r[4]),
        .I2(num_samples_done_ind_reg_n_0),
        .I3(num_samples_done_r),
        .I4(prbs_state_r[1]),
        .O(\match_flag_and[7]_i_2_n_0 ));
  FDSE \match_flag_and_reg[0] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(match_flag_and),
        .D(\match_flag_and[0]_i_1_n_0 ),
        .Q(\match_flag_and_reg_n_0_[0] ),
        .S(\match_flag_and_reg[7]_0 ));
  FDSE \match_flag_and_reg[1] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(match_flag_and),
        .D(\match_flag_and[1]_i_1_n_0 ),
        .Q(\match_flag_and_reg_n_0_[1] ),
        .S(\match_flag_and_reg[7]_0 ));
  FDSE \match_flag_and_reg[2] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(match_flag_and),
        .D(\match_flag_and[2]_i_1_n_0 ),
        .Q(\match_flag_and_reg_n_0_[2] ),
        .S(\match_flag_and_reg[7]_0 ));
  FDSE \match_flag_and_reg[3] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(match_flag_and),
        .D(\match_flag_and[3]_i_1_n_0 ),
        .Q(\match_flag_and_reg_n_0_[3] ),
        .S(\match_flag_and_reg[7]_0 ));
  FDSE \match_flag_and_reg[4] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(match_flag_and),
        .D(\match_flag_and[4]_i_1_n_0 ),
        .Q(\match_flag_and_reg_n_0_[4] ),
        .S(\match_flag_and_reg[7]_0 ));
  FDSE \match_flag_and_reg[5] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(match_flag_and),
        .D(\match_flag_and[5]_i_1_n_0 ),
        .Q(\match_flag_and_reg_n_0_[5] ),
        .S(\match_flag_and_reg[7]_0 ));
  FDSE \match_flag_and_reg[6] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(match_flag_and),
        .D(\match_flag_and[6]_i_1_n_0 ),
        .Q(\match_flag_and_reg_n_0_[6] ),
        .S(\match_flag_and_reg[7]_0 ));
  FDSE \match_flag_and_reg[7] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(match_flag_and),
        .D(\match_flag_and[7]_i_2_n_0 ),
        .Q(\match_flag_and_reg_n_0_[7] ),
        .S(\match_flag_and_reg[7]_0 ));
  LUT5 #(
    .INIT(32'hFFF3BBBB)) 
    \match_flag_or[0]_i_1 
       (.I0(sel0[0]),
        .I1(prbs_state_r[4]),
        .I2(num_samples_done_ind_reg_n_0),
        .I3(num_samples_done_r),
        .I4(prbs_state_r[1]),
        .O(\match_flag_or[0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFF3BBBB)) 
    \match_flag_or[1]_i_1 
       (.I0(sel0[1]),
        .I1(prbs_state_r[4]),
        .I2(num_samples_done_ind_reg_n_0),
        .I3(num_samples_done_r),
        .I4(prbs_state_r[1]),
        .O(\match_flag_or[1]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFF3BBBB)) 
    \match_flag_or[2]_i_1 
       (.I0(sel0[2]),
        .I1(prbs_state_r[4]),
        .I2(num_samples_done_ind_reg_n_0),
        .I3(num_samples_done_r),
        .I4(prbs_state_r[1]),
        .O(\match_flag_or[2]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFF3BBBB)) 
    \match_flag_or[3]_i_1 
       (.I0(sel0[3]),
        .I1(prbs_state_r[4]),
        .I2(num_samples_done_ind_reg_n_0),
        .I3(num_samples_done_r),
        .I4(prbs_state_r[1]),
        .O(\match_flag_or[3]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFF3BBBB)) 
    \match_flag_or[4]_i_1 
       (.I0(sel0[4]),
        .I1(prbs_state_r[4]),
        .I2(num_samples_done_ind_reg_n_0),
        .I3(num_samples_done_r),
        .I4(prbs_state_r[1]),
        .O(\match_flag_or[4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFF3BBBB)) 
    \match_flag_or[5]_i_1 
       (.I0(sel0[5]),
        .I1(prbs_state_r[4]),
        .I2(num_samples_done_ind_reg_n_0),
        .I3(num_samples_done_r),
        .I4(prbs_state_r[1]),
        .O(\match_flag_or[5]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFF3BBBB)) 
    \match_flag_or[6]_i_1 
       (.I0(sel0[6]),
        .I1(prbs_state_r[4]),
        .I2(num_samples_done_ind_reg_n_0),
        .I3(num_samples_done_r),
        .I4(prbs_state_r[1]),
        .O(\match_flag_or[6]_i_1_n_0 ));
  FDSE \match_flag_or_reg[0] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(match_flag_and),
        .D(\match_flag_or[0]_i_1_n_0 ),
        .Q(sel0[1]),
        .S(\prbs_dec_tap_cnt_reg[0]_0 ));
  FDSE \match_flag_or_reg[1] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(match_flag_and),
        .D(\match_flag_or[1]_i_1_n_0 ),
        .Q(sel0[2]),
        .S(\prbs_dec_tap_cnt_reg[0]_0 ));
  FDSE \match_flag_or_reg[2] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(match_flag_and),
        .D(\match_flag_or[2]_i_1_n_0 ),
        .Q(sel0[3]),
        .S(\prbs_dec_tap_cnt_reg[0]_0 ));
  FDSE \match_flag_or_reg[3] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(match_flag_and),
        .D(\match_flag_or[3]_i_1_n_0 ),
        .Q(sel0[4]),
        .S(\prbs_dec_tap_cnt_reg[0]_0 ));
  FDSE \match_flag_or_reg[4] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(match_flag_and),
        .D(\match_flag_or[4]_i_1_n_0 ),
        .Q(sel0[5]),
        .S(\prbs_dec_tap_cnt_reg[0]_0 ));
  FDSE \match_flag_or_reg[5] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(match_flag_and),
        .D(\match_flag_or[5]_i_1_n_0 ),
        .Q(sel0[6]),
        .S(\prbs_dec_tap_cnt_reg[0]_0 ));
  FDSE \match_flag_or_reg[6] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(match_flag_and),
        .D(\match_flag_or[6]_i_1_n_0 ),
        .Q(sel0[7]),
        .S(\prbs_dec_tap_cnt_reg[0]_0 ));
  FDRE mux_rd_valid_r_reg
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(mux_rd_valid_r0),
        .Q(mux_rd_valid_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hAA0CFFFFAA0C0000)) 
    new_cnt_dqs_r_i_1
       (.I0(prech_done),
        .I1(new_cnt_dqs_r_reg_1),
        .I2(prbs_state_r[0]),
        .I3(prbs_state_r[3]),
        .I4(new_cnt_dqs_r_i_3_n_0),
        .I5(new_cnt_dqs_r_reg_0),
        .O(new_cnt_dqs_r_i_1_n_0));
  LUT6 #(
    .INIT(64'hAAAAAAAAFAEAAAEA)) 
    new_cnt_dqs_r_i_3
       (.I0(\prbs_dqs_cnt_r[3]_i_1_n_0 ),
        .I1(new_cnt_dqs_r_reg_1),
        .I2(new_cnt_dqs_r_i_4_n_0),
        .I3(prbs_state_r[0]),
        .I4(cnt_wait_state),
        .I5(prbs_state_r[3]),
        .O(new_cnt_dqs_r_i_3_n_0));
  (* SOFT_HLUTNM = "soft_lutpair52" *) 
  LUT3 #(
    .INIT(8'h01)) 
    new_cnt_dqs_r_i_4
       (.I0(prbs_state_r[2]),
        .I1(prbs_state_r[1]),
        .I2(prbs_state_r[4]),
        .O(new_cnt_dqs_r_i_4_n_0));
  FDRE new_cnt_dqs_r_reg
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(new_cnt_dqs_r_i_1_n_0),
        .Q(new_cnt_dqs_r_reg_0),
        .R(\prbs_dec_tap_cnt_reg[0]_0 ));
  LUT5 #(
    .INIT(32'h00000002)) 
    no_err_win_detected_i_1
       (.I0(no_err_win_detected_i_2_n_0),
        .I1(sel0[2]),
        .I2(sel0[3]),
        .I3(sel0[0]),
        .I4(sel0[1]),
        .O(no_err_win_detected_i_1_n_0));
  LUT6 #(
    .INIT(64'h0000000100000000)) 
    no_err_win_detected_i_2
       (.I0(sel0[4]),
        .I1(sel0[5]),
        .I2(sel0[6]),
        .I3(sel0[7]),
        .I4(prbs_state_r[1]),
        .I5(prbs_state_r[4]),
        .O(no_err_win_detected_i_2_n_0));
  LUT5 #(
    .INIT(32'h888F8880)) 
    no_err_win_detected_latch_i_1
       (.I0(no_err_win_detected_reg_n_0),
        .I1(prbs_state_r[3]),
        .I2(no_err_win_detected_latch_i_2_n_0),
        .I3(no_err_win_detected_latch_i_3_n_0),
        .I4(no_err_win_detected_latch_reg_n_0),
        .O(no_err_win_detected_latch_i_1_n_0));
  LUT6 #(
    .INIT(64'h0000800200000000)) 
    no_err_win_detected_latch_i_2
       (.I0(no_err_win_detected_reg_n_0),
        .I1(prbs_state_r[3]),
        .I2(prbs_state_r[1]),
        .I3(prbs_state_r[2]),
        .I4(prbs_state_r[4]),
        .I5(prbs_state_r[0]),
        .O(no_err_win_detected_latch_i_2_n_0));
  LUT6 #(
    .INIT(64'h000000E0000F0000)) 
    no_err_win_detected_latch_i_3
       (.I0(num_samples_done_r),
        .I1(num_samples_done_ind_reg_n_0),
        .I2(prbs_state_r[1]),
        .I3(\prbs_state_r[4]_i_5_n_0 ),
        .I4(prbs_state_r[0]),
        .I5(prbs_state_r[4]),
        .O(no_err_win_detected_latch_i_3_n_0));
  FDRE no_err_win_detected_latch_reg
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(no_err_win_detected_latch_i_1_n_0),
        .Q(no_err_win_detected_latch_reg_n_0),
        .R(\prbs_dec_tap_cnt_reg[0]_0 ));
  FDRE no_err_win_detected_reg
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(match_flag_and),
        .D(no_err_win_detected_i_1_n_0),
        .Q(no_err_win_detected_reg_n_0),
        .R(no_err_win_detected_reg_0));
  LUT6 #(
    .INIT(64'hF0F0F0F0B2B0F0F0)) 
    num_samples_done_ind_i_1
       (.I0(prbs_state_r[0]),
        .I1(prbs_state_r[1]),
        .I2(num_samples_done_ind_reg_n_0),
        .I3(num_samples_done_r),
        .I4(prbs_state_r[4]),
        .I5(\prbs_state_r[4]_i_5_n_0 ),
        .O(num_samples_done_ind_i_1_n_0));
  FDRE num_samples_done_ind_reg
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(num_samples_done_ind_i_1_n_0),
        .Q(num_samples_done_ind_reg_n_0),
        .R(\samples_cnt_r_reg[0]_0 ));
  FDRE pi_en_stg2_f_reg
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(pi_en_stg2_f_timing),
        .Q(prbs_pi_stg2_f_en),
        .R(1'b0));
  FDRE pi_en_stg2_f_timing_reg
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_tap_en_r_reg_n_0),
        .Q(pi_en_stg2_f_timing),
        .R(\match_flag_and_reg[7]_0 ));
  FDRE pi_stg2_f_incdec_reg
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(pi_stg2_f_incdec_timing),
        .Q(prbs_pi_stg2_f_incdec),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair67" *) 
  LUT3 #(
    .INIT(8'h40)) 
    pi_stg2_f_incdec_timing_i_1__0
       (.I0(\rd_victim_sel_reg[2]_1 ),
        .I1(prbs_tap_inc_r),
        .I2(prbs_tap_en_r_reg_n_0),
        .O(pi_stg2_f_incdec_timing_i_1__0_n_0));
  FDRE pi_stg2_f_incdec_timing_reg
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(pi_stg2_f_incdec_timing_i_1__0_n_0),
        .Q(pi_stg2_f_incdec_timing),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair69" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \prbs_1st_edge_taps_r[1]_i_1 
       (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),
        .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),
        .O(\prbs_1st_edge_taps_r[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair69" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \prbs_1st_edge_taps_r[2]_i_1 
       (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),
        .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),
        .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),
        .O(\prbs_1st_edge_taps_r[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair31" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \prbs_1st_edge_taps_r[3]_i_1 
       (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),
        .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),
        .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),
        .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[3] ),
        .O(\prbs_1st_edge_taps_r[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair17" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \prbs_1st_edge_taps_r[4]_i_1 
       (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[3] ),
        .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),
        .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),
        .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),
        .I4(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),
        .O(\prbs_1st_edge_taps_r[4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h4C005D00)) 
    \prbs_1st_edge_taps_r[5]_i_1 
       (.I0(prbs_found_1st_edge_r_reg_n_0),
        .I1(prbs_state_r[3]),
        .I2(prbs_state_r[1]),
        .I3(\prbs_2nd_edge_taps_r[5]_i_4_n_0 ),
        .I4(compare_err_latch_reg_n_0),
        .O(\prbs_1st_edge_taps_r[5]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h5D00)) 
    \prbs_1st_edge_taps_r[5]_i_2 
       (.I0(prbs_found_1st_edge_r_reg_n_0),
        .I1(prbs_state_r[3]),
        .I2(prbs_state_r[1]),
        .I3(\prbs_2nd_edge_taps_r[5]_i_4_n_0 ),
        .O(\prbs_1st_edge_taps_r[5]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \prbs_1st_edge_taps_r[5]_i_3 
       (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),
        .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),
        .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),
        .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),
        .I4(\prbs_dqs_tap_cnt_r_reg_n_0_[3] ),
        .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),
        .O(\prbs_1st_edge_taps_r[5]_i_3_n_0 ));
  FDRE \prbs_1st_edge_taps_r_reg[0] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(\prbs_1st_edge_taps_r[5]_i_2_n_0 ),
        .D(\prbs_2nd_edge_taps_r[0]_i_1_n_0 ),
        .Q(\prbs_1st_edge_taps_r_reg_n_0_[0] ),
        .R(\prbs_1st_edge_taps_r[5]_i_1_n_0 ));
  FDRE \prbs_1st_edge_taps_r_reg[1] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(\prbs_1st_edge_taps_r[5]_i_2_n_0 ),
        .D(\prbs_1st_edge_taps_r[1]_i_1_n_0 ),
        .Q(\prbs_1st_edge_taps_r_reg_n_0_[1] ),
        .R(\prbs_1st_edge_taps_r[5]_i_1_n_0 ));
  FDRE \prbs_1st_edge_taps_r_reg[2] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(\prbs_1st_edge_taps_r[5]_i_2_n_0 ),
        .D(\prbs_1st_edge_taps_r[2]_i_1_n_0 ),
        .Q(\prbs_1st_edge_taps_r_reg_n_0_[2] ),
        .R(\prbs_1st_edge_taps_r[5]_i_1_n_0 ));
  FDRE \prbs_1st_edge_taps_r_reg[3] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(\prbs_1st_edge_taps_r[5]_i_2_n_0 ),
        .D(\prbs_1st_edge_taps_r[3]_i_1_n_0 ),
        .Q(\prbs_1st_edge_taps_r_reg_n_0_[3] ),
        .R(\prbs_1st_edge_taps_r[5]_i_1_n_0 ));
  FDRE \prbs_1st_edge_taps_r_reg[4] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(\prbs_1st_edge_taps_r[5]_i_2_n_0 ),
        .D(\prbs_1st_edge_taps_r[4]_i_1_n_0 ),
        .Q(\prbs_1st_edge_taps_r_reg_n_0_[4] ),
        .R(\prbs_1st_edge_taps_r[5]_i_1_n_0 ));
  FDRE \prbs_1st_edge_taps_r_reg[5] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(\prbs_1st_edge_taps_r[5]_i_2_n_0 ),
        .D(\prbs_1st_edge_taps_r[5]_i_3_n_0 ),
        .Q(\prbs_1st_edge_taps_r_reg_n_0_[5] ),
        .R(\prbs_1st_edge_taps_r[5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair36" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \prbs_2nd_edge_taps_r[0]_i_1 
       (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),
        .O(\prbs_2nd_edge_taps_r[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair73" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \prbs_2nd_edge_taps_r[1]_i_1 
       (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),
        .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),
        .O(\prbs_2nd_edge_taps_r[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair73" *) 
  LUT3 #(
    .INIT(8'hE1)) 
    \prbs_2nd_edge_taps_r[2]_i_1 
       (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),
        .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),
        .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),
        .O(\prbs_2nd_edge_taps_r[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair49" *) 
  LUT4 #(
    .INIT(16'hFE01)) 
    \prbs_2nd_edge_taps_r[3]_i_1 
       (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),
        .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),
        .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),
        .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[3] ),
        .O(\prbs_2nd_edge_taps_r[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair17" *) 
  LUT5 #(
    .INIT(32'hFFFE0001)) 
    \prbs_2nd_edge_taps_r[4]_i_1 
       (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[3] ),
        .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),
        .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),
        .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),
        .I4(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),
        .O(\prbs_2nd_edge_taps_r[4]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h8C00)) 
    \prbs_2nd_edge_taps_r[5]_i_1 
       (.I0(prbs_found_1st_edge_r_reg_n_0),
        .I1(prbs_state_r[3]),
        .I2(prbs_state_r[1]),
        .I3(\prbs_2nd_edge_taps_r[5]_i_4_n_0 ),
        .O(\prbs_2nd_edge_taps_r[5]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hAE00)) 
    \prbs_2nd_edge_taps_r[5]_i_2 
       (.I0(prbs_found_1st_edge_r_reg_n_0),
        .I1(prbs_state_r[3]),
        .I2(prbs_state_r[1]),
        .I3(\prbs_2nd_edge_taps_r[5]_i_4_n_0 ),
        .O(\prbs_2nd_edge_taps_r[5]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFE00000001)) 
    \prbs_2nd_edge_taps_r[5]_i_3 
       (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),
        .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),
        .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),
        .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),
        .I4(\prbs_dqs_tap_cnt_r_reg_n_0_[3] ),
        .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),
        .O(\prbs_2nd_edge_taps_r[5]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0002FF0000000000)) 
    \prbs_2nd_edge_taps_r[5]_i_4 
       (.I0(num_samples_done_r),
        .I1(prbs_dqs_tap_limit_r),
        .I2(\prbs_inc_tap_cnt[5]_i_4_n_0 ),
        .I3(prbs_state_r[3]),
        .I4(prbs_state_r[1]),
        .I5(\prbs_2nd_edge_taps_r[5]_i_5_n_0 ),
        .O(\prbs_2nd_edge_taps_r[5]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair68" *) 
  LUT3 #(
    .INIT(8'h01)) 
    \prbs_2nd_edge_taps_r[5]_i_5 
       (.I0(prbs_state_r[2]),
        .I1(prbs_state_r[4]),
        .I2(prbs_state_r[0]),
        .O(\prbs_2nd_edge_taps_r[5]_i_5_n_0 ));
  FDRE \prbs_2nd_edge_taps_r_reg[0] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(\prbs_2nd_edge_taps_r[5]_i_2_n_0 ),
        .D(\prbs_2nd_edge_taps_r[0]_i_1_n_0 ),
        .Q(prbs_2nd_edge_taps_r[0]),
        .R(\prbs_2nd_edge_taps_r[5]_i_1_n_0 ));
  FDRE \prbs_2nd_edge_taps_r_reg[1] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(\prbs_2nd_edge_taps_r[5]_i_2_n_0 ),
        .D(\prbs_2nd_edge_taps_r[1]_i_1_n_0 ),
        .Q(prbs_2nd_edge_taps_r[1]),
        .R(\prbs_2nd_edge_taps_r[5]_i_1_n_0 ));
  FDRE \prbs_2nd_edge_taps_r_reg[2] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(\prbs_2nd_edge_taps_r[5]_i_2_n_0 ),
        .D(\prbs_2nd_edge_taps_r[2]_i_1_n_0 ),
        .Q(prbs_2nd_edge_taps_r[2]),
        .R(\prbs_2nd_edge_taps_r[5]_i_1_n_0 ));
  FDRE \prbs_2nd_edge_taps_r_reg[3] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(\prbs_2nd_edge_taps_r[5]_i_2_n_0 ),
        .D(\prbs_2nd_edge_taps_r[3]_i_1_n_0 ),
        .Q(prbs_2nd_edge_taps_r[3]),
        .R(\prbs_2nd_edge_taps_r[5]_i_1_n_0 ));
  FDRE \prbs_2nd_edge_taps_r_reg[4] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(\prbs_2nd_edge_taps_r[5]_i_2_n_0 ),
        .D(\prbs_2nd_edge_taps_r[4]_i_1_n_0 ),
        .Q(prbs_2nd_edge_taps_r[4]),
        .R(\prbs_2nd_edge_taps_r[5]_i_1_n_0 ));
  FDRE \prbs_2nd_edge_taps_r_reg[5] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(\prbs_2nd_edge_taps_r[5]_i_2_n_0 ),
        .D(\prbs_2nd_edge_taps_r[5]_i_3_n_0 ),
        .Q(prbs_2nd_edge_taps_r[5]),
        .R(\prbs_2nd_edge_taps_r[5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair59" *) 
  LUT3 #(
    .INIT(8'h8B)) 
    \prbs_dec_tap_cnt[0]_i_1 
       (.I0(\prbs_dec_tap_cnt[0]_i_2_n_0 ),
        .I1(prbs_state_r[2]),
        .I2(prbs_dec_tap_cnt[0]),
        .O(\prbs_dec_tap_cnt[0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h72FF7200)) 
    \prbs_dec_tap_cnt[0]_i_2 
       (.I0(prbs_found_2nd_edge_r_reg_n_0),
        .I1(prbs_dec_tap_cnt2[1]),
        .I2(prbs_dec_tap_cnt10_out[1]),
        .I3(prbs_found_1st_edge_r_reg_n_0),
        .I4(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),
        .O(\prbs_dec_tap_cnt[0]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair59" *) 
  LUT4 #(
    .INIT(16'hF909)) 
    \prbs_dec_tap_cnt[1]_i_1 
       (.I0(prbs_dec_tap_cnt[1]),
        .I1(prbs_dec_tap_cnt[0]),
        .I2(prbs_state_r[2]),
        .I3(\prbs_dec_tap_cnt[1]_i_2_n_0 ),
        .O(\prbs_dec_tap_cnt[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h66FFF0F06600F0F0)) 
    \prbs_dec_tap_cnt[1]_i_2 
       (.I0(prbs_dec_tap_cnt2[2]),
        .I1(prbs_dec_tap_cnt2[1]),
        .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),
        .I3(prbs_found_2nd_edge_r_reg_n_0),
        .I4(prbs_found_1st_edge_r_reg_n_0),
        .I5(prbs_dec_tap_cnt10_out[2]),
        .O(\prbs_dec_tap_cnt[1]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair29" *) 
  LUT5 #(
    .INIT(32'hFFE100E1)) 
    \prbs_dec_tap_cnt[2]_i_1 
       (.I0(prbs_dec_tap_cnt[0]),
        .I1(prbs_dec_tap_cnt[1]),
        .I2(prbs_dec_tap_cnt[2]),
        .I3(prbs_state_r[2]),
        .I4(\prbs_dec_tap_cnt[2]_i_2_n_0 ),
        .O(\prbs_dec_tap_cnt[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h66FFF0F06600F0F0)) 
    \prbs_dec_tap_cnt[2]_i_2 
       (.I0(\prbs_dec_tap_cnt[2]_i_3_n_0 ),
        .I1(prbs_dec_tap_cnt2[3]),
        .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[3] ),
        .I3(prbs_found_2nd_edge_r_reg_n_0),
        .I4(prbs_found_1st_edge_r_reg_n_0),
        .I5(prbs_dec_tap_cnt10_out[3]),
        .O(\prbs_dec_tap_cnt[2]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \prbs_dec_tap_cnt[2]_i_3 
       (.I0(prbs_dec_tap_cnt2[1]),
        .I1(prbs_dec_tap_cnt2[2]),
        .O(\prbs_dec_tap_cnt[2]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \prbs_dec_tap_cnt[2]_i_5 
       (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[3] ),
        .I1(\prbs_1st_edge_taps_r_reg_n_0_[3] ),
        .O(\prbs_dec_tap_cnt[2]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \prbs_dec_tap_cnt[2]_i_6 
       (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),
        .I1(\prbs_1st_edge_taps_r_reg_n_0_[2] ),
        .O(\prbs_dec_tap_cnt[2]_i_6_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \prbs_dec_tap_cnt[2]_i_7 
       (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),
        .I1(\prbs_1st_edge_taps_r_reg_n_0_[1] ),
        .O(\prbs_dec_tap_cnt[2]_i_7_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \prbs_dec_tap_cnt[2]_i_8 
       (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),
        .I1(\prbs_1st_edge_taps_r_reg_n_0_[0] ),
        .O(\prbs_dec_tap_cnt[2]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hCCCCCCC88888888C)) 
    \prbs_dec_tap_cnt[3]_i_1 
       (.I0(prbs_state_r[2]),
        .I1(\prbs_dec_tap_cnt[3]_i_2_n_0 ),
        .I2(prbs_dec_tap_cnt[0]),
        .I3(prbs_dec_tap_cnt[1]),
        .I4(prbs_dec_tap_cnt[2]),
        .I5(prbs_dec_tap_cnt[3]),
        .O(\prbs_dec_tap_cnt[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hBAFAEAFABAAAEAAA)) 
    \prbs_dec_tap_cnt[3]_i_2 
       (.I0(\prbs_dec_tap_cnt[3]_i_3_n_0 ),
        .I1(prbs_dec_tap_cnt2[4]),
        .I2(prbs_found_1st_edge_r_reg_n_0),
        .I3(prbs_found_2nd_edge_r_reg_n_0),
        .I4(\prbs_dec_tap_cnt[3]_i_4_n_0 ),
        .I5(prbs_dec_tap_cnt10_out[4]),
        .O(\prbs_dec_tap_cnt[3]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair46" *) 
  LUT3 #(
    .INIT(8'h4F)) 
    \prbs_dec_tap_cnt[3]_i_3 
       (.I0(prbs_found_1st_edge_r_reg_n_0),
        .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),
        .I2(prbs_state_r[2]),
        .O(\prbs_dec_tap_cnt[3]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair45" *) 
  LUT3 #(
    .INIT(8'h80)) 
    \prbs_dec_tap_cnt[3]_i_4 
       (.I0(prbs_dec_tap_cnt2[3]),
        .I1(prbs_dec_tap_cnt2[2]),
        .I2(prbs_dec_tap_cnt2[1]),
        .O(\prbs_dec_tap_cnt[3]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFAAA90000AAA9)) 
    \prbs_dec_tap_cnt[4]_i_1 
       (.I0(prbs_dec_tap_cnt[4]),
        .I1(\prbs_dec_tap_cnt[4]_i_2_n_0 ),
        .I2(prbs_dec_tap_cnt[2]),
        .I3(prbs_dec_tap_cnt[3]),
        .I4(prbs_state_r[2]),
        .I5(\prbs_dec_tap_cnt[4]_i_3_n_0 ),
        .O(\prbs_dec_tap_cnt[4]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair29" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \prbs_dec_tap_cnt[4]_i_2 
       (.I0(prbs_dec_tap_cnt[0]),
        .I1(prbs_dec_tap_cnt[1]),
        .O(\prbs_dec_tap_cnt[4]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h66FFF0F06600F0F0)) 
    \prbs_dec_tap_cnt[4]_i_3 
       (.I0(prbs_dec_tap_cnt2[5]),
        .I1(\prbs_dec_tap_cnt[4]_i_4_n_0 ),
        .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),
        .I3(prbs_found_2nd_edge_r_reg_n_0),
        .I4(prbs_found_1st_edge_r_reg_n_0),
        .I5(prbs_dec_tap_cnt10_out[5]),
        .O(\prbs_dec_tap_cnt[4]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair45" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \prbs_dec_tap_cnt[4]_i_4 
       (.I0(prbs_dec_tap_cnt2[1]),
        .I1(prbs_dec_tap_cnt2[2]),
        .I2(prbs_dec_tap_cnt2[3]),
        .I3(prbs_dec_tap_cnt2[4]),
        .O(\prbs_dec_tap_cnt[4]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \prbs_dec_tap_cnt[4]_i_6 
       (.I0(\prbs_1st_edge_taps_r_reg_n_0_[5] ),
        .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),
        .O(\prbs_dec_tap_cnt[4]_i_6_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \prbs_dec_tap_cnt[4]_i_7 
       (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),
        .I1(\prbs_1st_edge_taps_r_reg_n_0_[4] ),
        .O(\prbs_dec_tap_cnt[4]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h000000C000000040)) 
    \prbs_dec_tap_cnt[5]_i_1 
       (.I0(\prbs_dec_tap_cnt[5]_i_3_n_0 ),
        .I1(prbs_state_r[0]),
        .I2(prbs_state_r[1]),
        .I3(prbs_state_r[4]),
        .I4(prbs_state_r[3]),
        .I5(prbs_state_r[2]),
        .O(\prbs_dec_tap_cnt[5]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \prbs_dec_tap_cnt[5]_i_10 
       (.I0(prbs_2nd_edge_taps_r[3]),
        .I1(\prbs_1st_edge_taps_r_reg_n_0_[3] ),
        .O(\prbs_dec_tap_cnt[5]_i_10_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \prbs_dec_tap_cnt[5]_i_11 
       (.I0(prbs_2nd_edge_taps_r[2]),
        .I1(\prbs_1st_edge_taps_r_reg_n_0_[2] ),
        .O(\prbs_dec_tap_cnt[5]_i_11_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \prbs_dec_tap_cnt[5]_i_12 
       (.I0(prbs_2nd_edge_taps_r[1]),
        .I1(\prbs_1st_edge_taps_r_reg_n_0_[1] ),
        .O(\prbs_dec_tap_cnt[5]_i_12_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \prbs_dec_tap_cnt[5]_i_13 
       (.I0(prbs_2nd_edge_taps_r[0]),
        .I1(\prbs_1st_edge_taps_r_reg_n_0_[0] ),
        .O(\prbs_dec_tap_cnt[5]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'hF000000066666666)) 
    \prbs_dec_tap_cnt[5]_i_2 
       (.I0(prbs_dec_tap_cnt[5]),
        .I1(\prbs_dec_tap_cnt[5]_i_4_n_0 ),
        .I2(\prbs_dec_tap_cnt[5]_i_5_n_0 ),
        .I3(prbs_found_2nd_edge_r_reg_n_0),
        .I4(prbs_found_1st_edge_r_reg_n_0),
        .I5(prbs_state_r[2]),
        .O(\prbs_dec_tap_cnt[5]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \prbs_dec_tap_cnt[5]_i_3 
       (.I0(prbs_dec_tap_cnt[4]),
        .I1(prbs_dec_tap_cnt[3]),
        .I2(prbs_dec_tap_cnt[2]),
        .I3(prbs_dec_tap_cnt[1]),
        .I4(prbs_dec_tap_cnt[0]),
        .I5(prbs_dec_tap_cnt[5]),
        .O(\prbs_dec_tap_cnt[5]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'h00000001)) 
    \prbs_dec_tap_cnt[5]_i_4 
       (.I0(prbs_dec_tap_cnt[0]),
        .I1(prbs_dec_tap_cnt[1]),
        .I2(prbs_dec_tap_cnt[2]),
        .I3(prbs_dec_tap_cnt[3]),
        .I4(prbs_dec_tap_cnt[4]),
        .O(\prbs_dec_tap_cnt[5]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h9555555555555555)) 
    \prbs_dec_tap_cnt[5]_i_5 
       (.I0(\prbs_dec_tap_cnt_reg[5]_i_6_n_1 ),
        .I1(prbs_dec_tap_cnt2[5]),
        .I2(prbs_dec_tap_cnt2[1]),
        .I3(prbs_dec_tap_cnt2[2]),
        .I4(prbs_dec_tap_cnt2[3]),
        .I5(prbs_dec_tap_cnt2[4]),
        .O(\prbs_dec_tap_cnt[5]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \prbs_dec_tap_cnt[5]_i_8 
       (.I0(prbs_2nd_edge_taps_r[5]),
        .I1(\prbs_1st_edge_taps_r_reg_n_0_[5] ),
        .O(\prbs_dec_tap_cnt[5]_i_8_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \prbs_dec_tap_cnt[5]_i_9 
       (.I0(prbs_2nd_edge_taps_r[4]),
        .I1(\prbs_1st_edge_taps_r_reg_n_0_[4] ),
        .O(\prbs_dec_tap_cnt[5]_i_9_n_0 ));
  FDRE \prbs_dec_tap_cnt_reg[0] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(\prbs_dec_tap_cnt[5]_i_1_n_0 ),
        .D(\prbs_dec_tap_cnt[0]_i_1_n_0 ),
        .Q(prbs_dec_tap_cnt[0]),
        .R(\prbs_dec_tap_cnt_reg[0]_0 ));
  FDRE \prbs_dec_tap_cnt_reg[1] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(\prbs_dec_tap_cnt[5]_i_1_n_0 ),
        .D(\prbs_dec_tap_cnt[1]_i_1_n_0 ),
        .Q(prbs_dec_tap_cnt[1]),
        .R(\prbs_dec_tap_cnt_reg[0]_0 ));
  FDRE \prbs_dec_tap_cnt_reg[2] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(\prbs_dec_tap_cnt[5]_i_1_n_0 ),
        .D(\prbs_dec_tap_cnt[2]_i_1_n_0 ),
        .Q(prbs_dec_tap_cnt[2]),
        .R(\prbs_dec_tap_cnt_reg[0]_0 ));
  CARRY4 \prbs_dec_tap_cnt_reg[2]_i_4 
       (.CI(1'b0),
        .CO({\prbs_dec_tap_cnt_reg[2]_i_4_n_0 ,\prbs_dec_tap_cnt_reg[2]_i_4_n_1 ,\prbs_dec_tap_cnt_reg[2]_i_4_n_2 ,\prbs_dec_tap_cnt_reg[2]_i_4_n_3 }),
        .CYINIT(1'b1),
        .DI({\prbs_dqs_tap_cnt_r_reg_n_0_[3] ,\prbs_dqs_tap_cnt_r_reg_n_0_[2] ,\prbs_dqs_tap_cnt_r_reg_n_0_[1] ,\prbs_dqs_tap_cnt_r_reg_n_0_[0] }),
        .O({prbs_dec_tap_cnt10_out[3:1],\NLW_prbs_dec_tap_cnt_reg[2]_i_4_O_UNCONNECTED [0]}),
        .S({\prbs_dec_tap_cnt[2]_i_5_n_0 ,\prbs_dec_tap_cnt[2]_i_6_n_0 ,\prbs_dec_tap_cnt[2]_i_7_n_0 ,\prbs_dec_tap_cnt[2]_i_8_n_0 }));
  FDRE \prbs_dec_tap_cnt_reg[3] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(\prbs_dec_tap_cnt[5]_i_1_n_0 ),
        .D(\prbs_dec_tap_cnt[3]_i_1_n_0 ),
        .Q(prbs_dec_tap_cnt[3]),
        .R(\prbs_dec_tap_cnt_reg[0]_0 ));
  FDRE \prbs_dec_tap_cnt_reg[4] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(\prbs_dec_tap_cnt[5]_i_1_n_0 ),
        .D(\prbs_dec_tap_cnt[4]_i_1_n_0 ),
        .Q(prbs_dec_tap_cnt[4]),
        .R(\prbs_dec_tap_cnt_reg[0]_0 ));
  CARRY4 \prbs_dec_tap_cnt_reg[4]_i_5 
       (.CI(\prbs_dec_tap_cnt_reg[2]_i_4_n_0 ),
        .CO({\NLW_prbs_dec_tap_cnt_reg[4]_i_5_CO_UNCONNECTED [3:1],\prbs_dec_tap_cnt_reg[4]_i_5_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,\prbs_dqs_tap_cnt_r_reg_n_0_[4] }),
        .O({\NLW_prbs_dec_tap_cnt_reg[4]_i_5_O_UNCONNECTED [3:2],prbs_dec_tap_cnt10_out[5:4]}),
        .S({1'b0,1'b0,\prbs_dec_tap_cnt[4]_i_6_n_0 ,\prbs_dec_tap_cnt[4]_i_7_n_0 }));
  FDRE \prbs_dec_tap_cnt_reg[5] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(\prbs_dec_tap_cnt[5]_i_1_n_0 ),
        .D(\prbs_dec_tap_cnt[5]_i_2_n_0 ),
        .Q(prbs_dec_tap_cnt[5]),
        .R(\prbs_dec_tap_cnt_reg[0]_0 ));
  CARRY4 \prbs_dec_tap_cnt_reg[5]_i_6 
       (.CI(\prbs_dec_tap_cnt_reg[5]_i_7_n_0 ),
        .CO({\NLW_prbs_dec_tap_cnt_reg[5]_i_6_CO_UNCONNECTED [3],\prbs_dec_tap_cnt_reg[5]_i_6_n_1 ,\NLW_prbs_dec_tap_cnt_reg[5]_i_6_CO_UNCONNECTED [1],\prbs_dec_tap_cnt_reg[5]_i_6_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,prbs_2nd_edge_taps_r[5:4]}),
        .O({\NLW_prbs_dec_tap_cnt_reg[5]_i_6_O_UNCONNECTED [3:2],prbs_dec_tap_cnt2[5:4]}),
        .S({1'b0,1'b1,\prbs_dec_tap_cnt[5]_i_8_n_0 ,\prbs_dec_tap_cnt[5]_i_9_n_0 }));
  CARRY4 \prbs_dec_tap_cnt_reg[5]_i_7 
       (.CI(1'b0),
        .CO({\prbs_dec_tap_cnt_reg[5]_i_7_n_0 ,\prbs_dec_tap_cnt_reg[5]_i_7_n_1 ,\prbs_dec_tap_cnt_reg[5]_i_7_n_2 ,\prbs_dec_tap_cnt_reg[5]_i_7_n_3 }),
        .CYINIT(1'b1),
        .DI(prbs_2nd_edge_taps_r[3:0]),
        .O({prbs_dec_tap_cnt2[3:1],\NLW_prbs_dec_tap_cnt_reg[5]_i_7_O_UNCONNECTED [0]}),
        .S({\prbs_dec_tap_cnt[5]_i_10_n_0 ,\prbs_dec_tap_cnt[5]_i_11_n_0 ,\prbs_dec_tap_cnt[5]_i_12_n_0 ,\prbs_dec_tap_cnt[5]_i_13_n_0 }));
  (* SOFT_HLUTNM = "soft_lutpair34" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \prbs_dqs_cnt_r[0]_i_1 
       (.I0(\prbs_dqs_cnt_r_reg_n_0_[0] ),
        .O(\prbs_dqs_cnt_r[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair74" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \prbs_dqs_cnt_r[1]_i_1 
       (.I0(\prbs_dqs_cnt_r_reg_n_0_[0] ),
        .I1(\prbs_dqs_cnt_r_reg_n_0_[1] ),
        .O(\prbs_dqs_cnt_r[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair74" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \prbs_dqs_cnt_r[2]_i_1 
       (.I0(\prbs_dqs_cnt_r_reg_n_0_[2] ),
        .I1(\prbs_dqs_cnt_r_reg_n_0_[1] ),
        .I2(\prbs_dqs_cnt_r_reg_n_0_[0] ),
        .O(\prbs_dqs_cnt_r[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0200000000000000)) 
    \prbs_dqs_cnt_r[3]_i_1 
       (.I0(\prbs_dqs_cnt_r[3]_i_3_n_0 ),
        .I1(prbs_state_r[4]),
        .I2(prbs_state_r[0]),
        .I3(prbs_state_r[3]),
        .I4(prech_done),
        .I5(\prbs_dqs_cnt_r[3]_i_4_n_0 ),
        .O(\prbs_dqs_cnt_r[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair48" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \prbs_dqs_cnt_r[3]_i_2 
       (.I0(\prbs_dqs_cnt_r_reg_n_0_[3] ),
        .I1(\prbs_dqs_cnt_r_reg_n_0_[0] ),
        .I2(\prbs_dqs_cnt_r_reg_n_0_[1] ),
        .I3(\prbs_dqs_cnt_r_reg_n_0_[2] ),
        .O(\prbs_dqs_cnt_r[3]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair16" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \prbs_dqs_cnt_r[3]_i_3 
       (.I0(prbs_state_r[1]),
        .I1(prbs_state_r[2]),
        .O(\prbs_dqs_cnt_r[3]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair48" *) 
  LUT4 #(
    .INIT(16'h1555)) 
    \prbs_dqs_cnt_r[3]_i_4 
       (.I0(\prbs_dqs_cnt_r_reg_n_0_[3] ),
        .I1(\prbs_dqs_cnt_r_reg_n_0_[0] ),
        .I2(\prbs_dqs_cnt_r_reg_n_0_[1] ),
        .I3(\prbs_dqs_cnt_r_reg_n_0_[2] ),
        .O(\prbs_dqs_cnt_r[3]_i_4_n_0 ));
  FDRE \prbs_dqs_cnt_r_reg[0] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(\prbs_dqs_cnt_r[3]_i_1_n_0 ),
        .D(\prbs_dqs_cnt_r[0]_i_1_n_0 ),
        .Q(\prbs_dqs_cnt_r_reg_n_0_[0] ),
        .R(\prbs_dqs_cnt_r_reg[0]_1 ));
  FDRE \prbs_dqs_cnt_r_reg[1] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(\prbs_dqs_cnt_r[3]_i_1_n_0 ),
        .D(\prbs_dqs_cnt_r[1]_i_1_n_0 ),
        .Q(\prbs_dqs_cnt_r_reg_n_0_[1] ),
        .R(\prbs_dqs_cnt_r_reg[0]_1 ));
  FDRE \prbs_dqs_cnt_r_reg[2] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(\prbs_dqs_cnt_r[3]_i_1_n_0 ),
        .D(\prbs_dqs_cnt_r[2]_i_1_n_0 ),
        .Q(\prbs_dqs_cnt_r_reg_n_0_[2] ),
        .R(\prbs_dqs_cnt_r_reg[0]_1 ));
  FDRE \prbs_dqs_cnt_r_reg[3] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(\prbs_dqs_cnt_r[3]_i_1_n_0 ),
        .D(\prbs_dqs_cnt_r[3]_i_2_n_0 ),
        .Q(\prbs_dqs_cnt_r_reg_n_0_[3] ),
        .R(\prbs_dqs_cnt_r_reg[0]_1 ));
  LUT3 #(
    .INIT(8'h8B)) 
    \prbs_dqs_tap_cnt_r[0]_i_1 
       (.I0(D[0]),
        .I1(new_cnt_dqs_r_reg_0),
        .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),
        .O(\prbs_dqs_tap_cnt_r[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair36" *) 
  LUT5 #(
    .INIT(32'hFF690069)) 
    \prbs_dqs_tap_cnt_r[1]_i_1 
       (.I0(prbs_tap_inc_r),
        .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),
        .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),
        .I3(new_cnt_dqs_r_reg_0),
        .I4(D[1]),
        .O(\prbs_dqs_tap_cnt_r[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF7E8100007E81)) 
    \prbs_dqs_tap_cnt_r[2]_i_1 
       (.I0(prbs_tap_inc_r),
        .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),
        .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),
        .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),
        .I4(new_cnt_dqs_r_reg_0),
        .I5(D[2]),
        .O(\prbs_dqs_tap_cnt_r[2]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFB100B1)) 
    \prbs_dqs_tap_cnt_r[3]_i_1 
       (.I0(prbs_tap_inc_r),
        .I1(\prbs_dqs_tap_cnt_r[3]_i_2_n_0 ),
        .I2(\prbs_1st_edge_taps_r[3]_i_1_n_0 ),
        .I3(new_cnt_dqs_r_reg_0),
        .I4(D[3]),
        .O(\prbs_dqs_tap_cnt_r[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair49" *) 
  LUT4 #(
    .INIT(16'h5556)) 
    \prbs_dqs_tap_cnt_r[3]_i_2 
       (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[3] ),
        .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),
        .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),
        .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),
        .O(\prbs_dqs_tap_cnt_r[3]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFFB100B1)) 
    \prbs_dqs_tap_cnt_r[4]_i_1 
       (.I0(prbs_tap_inc_r),
        .I1(\prbs_dqs_tap_cnt_r[4]_i_2_n_0 ),
        .I2(\prbs_1st_edge_taps_r[4]_i_1_n_0 ),
        .I3(new_cnt_dqs_r_reg_0),
        .I4(D[4]),
        .O(\prbs_dqs_tap_cnt_r[4]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair38" *) 
  LUT5 #(
    .INIT(32'h55555556)) 
    \prbs_dqs_tap_cnt_r[4]_i_2 
       (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),
        .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),
        .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),
        .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),
        .I4(\prbs_dqs_tap_cnt_r_reg_n_0_[3] ),
        .O(\prbs_dqs_tap_cnt_r[4]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hFEAA)) 
    \prbs_dqs_tap_cnt_r[5]_i_1 
       (.I0(new_cnt_dqs_r_reg_0),
        .I1(prbs_tap_inc_r),
        .I2(\prbs_dqs_tap_cnt_r[5]_i_3_n_0 ),
        .I3(prbs_tap_en_r_reg_n_0),
        .O(\prbs_dqs_tap_cnt_r[5]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFB100B1)) 
    \prbs_dqs_tap_cnt_r[5]_i_2 
       (.I0(prbs_tap_inc_r),
        .I1(\prbs_dqs_tap_cnt_r[5]_i_4_n_0 ),
        .I2(\prbs_1st_edge_taps_r[5]_i_3_n_0 ),
        .I3(new_cnt_dqs_r_reg_0),
        .I4(D[5]),
        .O(\prbs_dqs_tap_cnt_r[5]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \prbs_dqs_tap_cnt_r[5]_i_3 
       (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),
        .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[3] ),
        .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),
        .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),
        .I4(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),
        .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),
        .O(\prbs_dqs_tap_cnt_r[5]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h5555555555555556)) 
    \prbs_dqs_tap_cnt_r[5]_i_4 
       (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),
        .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[3] ),
        .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),
        .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),
        .I4(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),
        .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),
        .O(\prbs_dqs_tap_cnt_r[5]_i_4_n_0 ));
  FDRE \prbs_dqs_tap_cnt_r_reg[0] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(\prbs_dqs_tap_cnt_r[5]_i_1_n_0 ),
        .D(\prbs_dqs_tap_cnt_r[0]_i_1_n_0 ),
        .Q(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),
        .R(\samples_cnt_r_reg[0]_0 ));
  FDRE \prbs_dqs_tap_cnt_r_reg[1] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(\prbs_dqs_tap_cnt_r[5]_i_1_n_0 ),
        .D(\prbs_dqs_tap_cnt_r[1]_i_1_n_0 ),
        .Q(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),
        .R(\samples_cnt_r_reg[0]_0 ));
  FDRE \prbs_dqs_tap_cnt_r_reg[2] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(\prbs_dqs_tap_cnt_r[5]_i_1_n_0 ),
        .D(\prbs_dqs_tap_cnt_r[2]_i_1_n_0 ),
        .Q(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),
        .R(\samples_cnt_r_reg[0]_0 ));
  FDRE \prbs_dqs_tap_cnt_r_reg[3] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(\prbs_dqs_tap_cnt_r[5]_i_1_n_0 ),
        .D(\prbs_dqs_tap_cnt_r[3]_i_1_n_0 ),
        .Q(\prbs_dqs_tap_cnt_r_reg_n_0_[3] ),
        .R(\samples_cnt_r_reg[0]_0 ));
  FDRE \prbs_dqs_tap_cnt_r_reg[4] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(\prbs_dqs_tap_cnt_r[5]_i_1_n_0 ),
        .D(\prbs_dqs_tap_cnt_r[4]_i_1_n_0 ),
        .Q(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),
        .R(\samples_cnt_r_reg[0]_0 ));
  FDRE \prbs_dqs_tap_cnt_r_reg[5] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(\prbs_dqs_tap_cnt_r[5]_i_1_n_0 ),
        .D(\prbs_dqs_tap_cnt_r[5]_i_2_n_0 ),
        .Q(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),
        .R(\samples_cnt_r_reg[0]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair67" *) 
  LUT3 #(
    .INIT(8'h01)) 
    prbs_dqs_tap_limit_r_i_1
       (.I0(prbs_dqs_tap_limit_r_i_2_n_0),
        .I1(new_cnt_dqs_r_reg_0),
        .I2(\rd_victim_sel_reg[2]_1 ),
        .O(prbs_dqs_tap_limit_r_i_1_n_0));
  LUT6 #(
    .INIT(64'h7FFFFFFFFFFFFFFF)) 
    prbs_dqs_tap_limit_r_i_2
       (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),
        .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),
        .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),
        .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),
        .I4(\prbs_dqs_tap_cnt_r_reg_n_0_[3] ),
        .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),
        .O(prbs_dqs_tap_limit_r_i_2_n_0));
  FDRE prbs_dqs_tap_limit_r_reg
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_dqs_tap_limit_r_i_1_n_0),
        .Q(prbs_dqs_tap_limit_r),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair50" *) 
  LUT4 #(
    .INIT(16'h1F10)) 
    prbs_found_1st_edge_r_i_1
       (.I0(\prbs_inc_tap_cnt[5]_i_4_n_0 ),
        .I1(prbs_state_r[3]),
        .I2(\prbs_2nd_edge_taps_r[5]_i_4_n_0 ),
        .I3(prbs_found_1st_edge_r_reg_n_0),
        .O(prbs_found_1st_edge_r_i_1_n_0));
  FDRE prbs_found_1st_edge_r_reg
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_found_1st_edge_r_i_1_n_0),
        .Q(prbs_found_1st_edge_r_reg_n_0),
        .R(\prbs_dec_tap_cnt_reg[0]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair21" *) 
  LUT5 #(
    .INIT(32'h73FF2200)) 
    prbs_found_2nd_edge_r_i_1
       (.I0(prbs_found_1st_edge_r_reg_n_0),
        .I1(prbs_state_r[3]),
        .I2(prbs_state_r[1]),
        .I3(\prbs_2nd_edge_taps_r[5]_i_4_n_0 ),
        .I4(prbs_found_2nd_edge_r_reg_n_0),
        .O(prbs_found_2nd_edge_r_i_1_n_0));
  FDRE prbs_found_2nd_edge_r_reg
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_found_2nd_edge_r_i_1_n_0),
        .Q(prbs_found_2nd_edge_r_reg_n_0),
        .R(prbs_found_2nd_edge_r_reg_0));
  LUT4 #(
    .INIT(16'h06F6)) 
    \prbs_inc_tap_cnt[0]_i_1 
       (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),
        .I1(rdlvl_cpt_tap_cnt[0]),
        .I2(prbs_state_r[2]),
        .I3(\prbs_inc_tap_cnt_reg_n_0_[0] ),
        .O(\prbs_inc_tap_cnt[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair23" *) 
  LUT5 #(
    .INIT(32'hB8BB4744)) 
    \prbs_inc_tap_cnt[1]_i_1 
       (.I0(\prbs_inc_tap_cnt_reg_n_0_[0] ),
        .I1(prbs_state_r[2]),
        .I2(rdlvl_cpt_tap_cnt[0]),
        .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),
        .I4(\prbs_inc_tap_cnt[1]_i_2_n_0 ),
        .O(\prbs_inc_tap_cnt[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair42" *) 
  LUT4 #(
    .INIT(16'hF606)) 
    \prbs_inc_tap_cnt[1]_i_2 
       (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),
        .I1(rdlvl_cpt_tap_cnt[1]),
        .I2(prbs_state_r[2]),
        .I3(\prbs_inc_tap_cnt_reg_n_0_[1] ),
        .O(\prbs_inc_tap_cnt[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h656A6A659A95959A)) 
    \prbs_inc_tap_cnt[2]_i_1 
       (.I0(\prbs_inc_tap_cnt[2]_i_2_n_0 ),
        .I1(\prbs_inc_tap_cnt_reg_n_0_[2] ),
        .I2(prbs_state_r[2]),
        .I3(rdlvl_cpt_tap_cnt[2]),
        .I4(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),
        .I5(\prbs_inc_tap_cnt[2]_i_3_n_0 ),
        .O(\prbs_inc_tap_cnt[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair23" *) 
  LUT5 #(
    .INIT(32'h00004744)) 
    \prbs_inc_tap_cnt[2]_i_2 
       (.I0(\prbs_inc_tap_cnt_reg_n_0_[0] ),
        .I1(prbs_state_r[2]),
        .I2(rdlvl_cpt_tap_cnt[0]),
        .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),
        .I4(\prbs_inc_tap_cnt[1]_i_2_n_0 ),
        .O(\prbs_inc_tap_cnt[2]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair42" *) 
  LUT3 #(
    .INIT(8'hF4)) 
    \prbs_inc_tap_cnt[2]_i_3 
       (.I0(rdlvl_cpt_tap_cnt[1]),
        .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),
        .I2(prbs_state_r[2]),
        .O(\prbs_inc_tap_cnt[2]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAA9655965569AA69)) 
    \prbs_inc_tap_cnt[3]_i_1 
       (.I0(\prbs_inc_tap_cnt[3]_i_2_n_0 ),
        .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[3] ),
        .I2(rdlvl_cpt_tap_cnt[3]),
        .I3(prbs_state_r[2]),
        .I4(\prbs_inc_tap_cnt_reg_n_0_[3] ),
        .I5(\prbs_inc_tap_cnt[3]_i_3_n_0 ),
        .O(\prbs_inc_tap_cnt[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hEFEAEAEF8A80808A)) 
    \prbs_inc_tap_cnt[3]_i_2 
       (.I0(\prbs_inc_tap_cnt[2]_i_2_n_0 ),
        .I1(\prbs_inc_tap_cnt_reg_n_0_[2] ),
        .I2(prbs_state_r[2]),
        .I3(rdlvl_cpt_tap_cnt[2]),
        .I4(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),
        .I5(\prbs_inc_tap_cnt[2]_i_3_n_0 ),
        .O(\prbs_inc_tap_cnt[3]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair57" *) 
  LUT4 #(
    .INIT(16'hFD0D)) 
    \prbs_inc_tap_cnt[3]_i_3 
       (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),
        .I1(rdlvl_cpt_tap_cnt[2]),
        .I2(prbs_state_r[2]),
        .I3(\prbs_inc_tap_cnt_reg_n_0_[2] ),
        .O(\prbs_inc_tap_cnt[3]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAA9655965569AA69)) 
    \prbs_inc_tap_cnt[4]_i_1 
       (.I0(\prbs_inc_tap_cnt[5]_i_6_n_0 ),
        .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),
        .I2(rdlvl_cpt_tap_cnt[4]),
        .I3(prbs_state_r[2]),
        .I4(\prbs_inc_tap_cnt_reg_n_0_[4] ),
        .I5(\prbs_inc_tap_cnt[5]_i_7_n_0 ),
        .O(\prbs_inc_tap_cnt[4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAAAAE)) 
    \prbs_inc_tap_cnt[5]_i_1 
       (.I0(\prbs_inc_tap_cnt[5]_i_3_n_0 ),
        .I1(num_samples_done_r),
        .I2(prbs_dqs_tap_limit_r),
        .I3(\prbs_inc_tap_cnt[5]_i_4_n_0 ),
        .I4(\prbs_inc_tap_cnt[5]_i_5_n_0 ),
        .I5(prbs_found_1st_edge_r_reg_n_0),
        .O(prbs_inc_tap_cnt));
  (* SOFT_HLUTNM = "soft_lutpair65" *) 
  LUT3 #(
    .INIT(8'hFE)) 
    \prbs_inc_tap_cnt[5]_i_10 
       (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),
        .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),
        .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),
        .O(\prbs_inc_tap_cnt[5]_i_10_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair56" *) 
  LUT4 #(
    .INIT(16'hF909)) 
    \prbs_inc_tap_cnt[5]_i_11 
       (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[3] ),
        .I1(rdlvl_cpt_tap_cnt[3]),
        .I2(prbs_state_r[2]),
        .I3(\prbs_inc_tap_cnt_reg_n_0_[3] ),
        .O(\prbs_inc_tap_cnt[5]_i_11_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair57" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \prbs_inc_tap_cnt[5]_i_12 
       (.I0(\prbs_inc_tap_cnt_reg_n_0_[2] ),
        .I1(prbs_state_r[2]),
        .I2(rdlvl_cpt_tap_cnt[2]),
        .O(\prbs_inc_tap_cnt[5]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hB4B4B42DD2D2D2B4)) 
    \prbs_inc_tap_cnt[5]_i_2 
       (.I0(\prbs_inc_tap_cnt[5]_i_6_n_0 ),
        .I1(\prbs_inc_tap_cnt[5]_i_7_n_0 ),
        .I2(\prbs_inc_tap_cnt[5]_i_8_n_0 ),
        .I3(prbs_state_r[2]),
        .I4(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),
        .I5(\prbs_inc_tap_cnt[5]_i_9_n_0 ),
        .O(\prbs_inc_tap_cnt[5]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0002000000000000)) 
    \prbs_inc_tap_cnt[5]_i_3 
       (.I0(prbs_state_r[0]),
        .I1(prbs_state_r[1]),
        .I2(prbs_state_r[4]),
        .I3(prbs_state_r[3]),
        .I4(prbs_state_r[2]),
        .I5(\prbs_state_r[2]_i_5_n_0 ),
        .O(\prbs_inc_tap_cnt[5]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'h0000FFFE)) 
    \prbs_inc_tap_cnt[5]_i_4 
       (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),
        .I1(\prbs_inc_tap_cnt[5]_i_10_n_0 ),
        .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[3] ),
        .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),
        .I4(compare_err_latch_reg_n_0),
        .O(\prbs_inc_tap_cnt[5]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair20" *) 
  LUT5 #(
    .INIT(32'hFFFFFFFB)) 
    \prbs_inc_tap_cnt[5]_i_5 
       (.I0(prbs_state_r[0]),
        .I1(prbs_state_r[1]),
        .I2(prbs_state_r[2]),
        .I3(prbs_state_r[4]),
        .I4(prbs_state_r[3]),
        .O(\prbs_inc_tap_cnt[5]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hA8EAA8EAA8EA80A8)) 
    \prbs_inc_tap_cnt[5]_i_6 
       (.I0(\prbs_inc_tap_cnt[5]_i_11_n_0 ),
        .I1(\prbs_inc_tap_cnt[2]_i_3_n_0 ),
        .I2(\prbs_inc_tap_cnt[2]_i_2_n_0 ),
        .I3(\prbs_inc_tap_cnt[5]_i_12_n_0 ),
        .I4(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),
        .I5(prbs_state_r[2]),
        .O(\prbs_inc_tap_cnt[5]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair56" *) 
  LUT4 #(
    .INIT(16'hFD0D)) 
    \prbs_inc_tap_cnt[5]_i_7 
       (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[3] ),
        .I1(rdlvl_cpt_tap_cnt[3]),
        .I2(prbs_state_r[2]),
        .I3(\prbs_inc_tap_cnt_reg_n_0_[3] ),
        .O(\prbs_inc_tap_cnt[5]_i_7_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair55" *) 
  LUT4 #(
    .INIT(16'hF909)) 
    \prbs_inc_tap_cnt[5]_i_8 
       (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),
        .I1(rdlvl_cpt_tap_cnt[5]),
        .I2(prbs_state_r[2]),
        .I3(\prbs_inc_tap_cnt_reg_n_0_[5] ),
        .O(\prbs_inc_tap_cnt[5]_i_8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair68" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \prbs_inc_tap_cnt[5]_i_9 
       (.I0(\prbs_inc_tap_cnt_reg_n_0_[4] ),
        .I1(prbs_state_r[2]),
        .I2(rdlvl_cpt_tap_cnt[4]),
        .O(\prbs_inc_tap_cnt[5]_i_9_n_0 ));
  FDRE \prbs_inc_tap_cnt_reg[0] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(prbs_inc_tap_cnt),
        .D(\prbs_inc_tap_cnt[0]_i_1_n_0 ),
        .Q(\prbs_inc_tap_cnt_reg_n_0_[0] ),
        .R(\match_flag_and_reg[7]_0 ));
  FDRE \prbs_inc_tap_cnt_reg[1] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(prbs_inc_tap_cnt),
        .D(\prbs_inc_tap_cnt[1]_i_1_n_0 ),
        .Q(\prbs_inc_tap_cnt_reg_n_0_[1] ),
        .R(\match_flag_and_reg[7]_0 ));
  FDRE \prbs_inc_tap_cnt_reg[2] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(prbs_inc_tap_cnt),
        .D(\prbs_inc_tap_cnt[2]_i_1_n_0 ),
        .Q(\prbs_inc_tap_cnt_reg_n_0_[2] ),
        .R(\match_flag_and_reg[7]_0 ));
  FDRE \prbs_inc_tap_cnt_reg[3] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(prbs_inc_tap_cnt),
        .D(\prbs_inc_tap_cnt[3]_i_1_n_0 ),
        .Q(\prbs_inc_tap_cnt_reg_n_0_[3] ),
        .R(\match_flag_and_reg[7]_0 ));
  FDRE \prbs_inc_tap_cnt_reg[4] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(prbs_inc_tap_cnt),
        .D(\prbs_inc_tap_cnt[4]_i_1_n_0 ),
        .Q(\prbs_inc_tap_cnt_reg_n_0_[4] ),
        .R(\match_flag_and_reg[7]_0 ));
  FDRE \prbs_inc_tap_cnt_reg[5] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(prbs_inc_tap_cnt),
        .D(\prbs_inc_tap_cnt[5]_i_2_n_0 ),
        .Q(\prbs_inc_tap_cnt_reg_n_0_[5] ),
        .R(\match_flag_and_reg[7]_0 ));
  LUT6 #(
    .INIT(64'hFC3CFFFF00040000)) 
    prbs_last_byte_done_i_1
       (.I0(\prbs_dqs_cnt_r[3]_i_4_n_0 ),
        .I1(prbs_state_r[3]),
        .I2(prbs_state_r[1]),
        .I3(prbs_state_r[0]),
        .I4(prbs_last_byte_done_i_2_n_0),
        .I5(prbs_last_byte_done),
        .O(prbs_last_byte_done_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair60" *) 
  LUT2 #(
    .INIT(4'h1)) 
    prbs_last_byte_done_i_2
       (.I0(prbs_state_r[4]),
        .I1(prbs_state_r[2]),
        .O(prbs_last_byte_done_i_2_n_0));
  FDRE prbs_last_byte_done_reg
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_last_byte_done_i_1_n_0),
        .Q(prbs_last_byte_done),
        .R(\prbs_dec_tap_cnt_reg[0]_0 ));
  LUT6 #(
    .INIT(64'hCFFFDF0F00001000)) 
    prbs_prech_req_r_i_1
       (.I0(prech_done),
        .I1(prbs_state_r[0]),
        .I2(prbs_last_byte_done_i_2_n_0),
        .I3(prbs_state_r[3]),
        .I4(prbs_state_r[1]),
        .I5(prbs_prech_req_r),
        .O(prbs_prech_req_r_i_1_n_0));
  FDRE prbs_prech_req_r_reg
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_prech_req_r_i_1_n_0),
        .Q(prbs_prech_req_r),
        .R(\match_flag_and_reg[7]_0 ));
  LUT6 #(
    .INIT(64'hFFDFFFFF00100000)) 
    prbs_rdlvl_done_i_1
       (.I0(edge_det_error_reg_n_0),
        .I1(prbs_state_r[4]),
        .I2(prbs_state_r[3]),
        .I3(prbs_state_r[0]),
        .I4(\prbs_state_r[3]_i_4_n_0 ),
        .I5(prbs_rdlvl_done_reg_0),
        .O(prbs_rdlvl_done_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair35" *) 
  LUT2 #(
    .INIT(4'h2)) 
    prbs_rdlvl_done_pulse_i_1
       (.I0(prbs_rdlvl_done_reg_0),
        .I1(prbs_rdlvl_done_r1),
        .O(prbs_rdlvl_done_pulse0));
  (* MAX_FANOUT = "100" *) 
  FDRE prbs_rdlvl_done_reg
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_rdlvl_done_i_1_n_0),
        .Q(prbs_rdlvl_done_reg_0),
        .R(\samples_cnt_r_reg[0]_0 ));
  FDRE prbs_rdlvl_prech_req_reg
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_prech_req_r),
        .Q(prbs_rdlvl_prech_req_reg_0),
        .R(\prbs_dec_tap_cnt_reg[0]_0 ));
  FDRE prbs_rdlvl_start_r_reg
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_rdlvl_start_r_reg_0),
        .Q(prbs_rdlvl_start_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h8AFF8AFF8AFF8A8A)) 
    \prbs_state_r[0]_i_1 
       (.I0(prbs_state_r[4]),
        .I1(prbs_state_r[2]),
        .I2(\prbs_state_r[0]_i_2_n_0 ),
        .I3(\prbs_state_r[0]_i_3_n_0 ),
        .I4(\prbs_state_r[0]_i_4_n_0 ),
        .I5(\prbs_state_r[0]_i_5_n_0 ),
        .O(\prbs_state_r[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair44" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \prbs_state_r[0]_i_2 
       (.I0(prbs_state_r[0]),
        .I1(prbs_state_r[1]),
        .O(\prbs_state_r[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFAFA10000)) 
    \prbs_state_r[0]_i_3 
       (.I0(prbs_state_r[0]),
        .I1(\prbs_dqs_cnt_r[3]_i_4_n_0 ),
        .I2(prbs_state_r[2]),
        .I3(prbs_state_r[1]),
        .I4(prbs_state_r[3]),
        .I5(prbs_state_r[4]),
        .O(\prbs_state_r[0]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000DE0000)) 
    \prbs_state_r[0]_i_4 
       (.I0(prbs_found_1st_edge_r_reg_n_0),
        .I1(prbs_dqs_tap_limit_r),
        .I2(\prbs_inc_tap_cnt[5]_i_4_n_0 ),
        .I3(prbs_state_r[2]),
        .I4(prbs_state_r[1]),
        .I5(prbs_state_r[0]),
        .O(\prbs_state_r[0]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFC0C0FFFFC707)) 
    \prbs_state_r[0]_i_5 
       (.I0(\prbs_dec_tap_cnt[5]_i_3_n_0 ),
        .I1(prbs_state_r[2]),
        .I2(prbs_state_r[1]),
        .I3(\prbs_state_r[2]_i_5_n_0 ),
        .I4(\prbs_state_r[1]_i_4_n_0 ),
        .I5(prbs_state_r[0]),
        .O(\prbs_state_r[0]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF55101010)) 
    \prbs_state_r[1]_i_1 
       (.I0(prbs_state_r[4]),
        .I1(\prbs_state_r[1]_i_2_n_0 ),
        .I2(\prbs_state_r[1]_i_3_n_0 ),
        .I3(\prbs_state_r[1]_i_4_n_0 ),
        .I4(\prbs_state_r[1]_i_5_n_0 ),
        .I5(\prbs_state_r[1]_i_6_n_0 ),
        .O(\prbs_state_r[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFEFCFC30307575)) 
    \prbs_state_r[1]_i_2 
       (.I0(prbs_state_r[0]),
        .I1(prbs_state_r[4]),
        .I2(prbs_state_r[3]),
        .I3(\prbs_state_r[2]_i_5_n_0 ),
        .I4(prbs_state_r[1]),
        .I5(prbs_state_r[2]),
        .O(\prbs_state_r[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF5054FFFFFFFF)) 
    \prbs_state_r[1]_i_3 
       (.I0(prbs_state_r[0]),
        .I1(prbs_found_1st_edge_r_reg_n_0),
        .I2(prbs_dqs_tap_limit_r),
        .I3(\prbs_inc_tap_cnt[5]_i_4_n_0 ),
        .I4(prbs_state_r[2]),
        .I5(prbs_state_r[1]),
        .O(\prbs_state_r[1]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair26" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \prbs_state_r[1]_i_4 
       (.I0(prbs_state_r[2]),
        .I1(prbs_state_r[4]),
        .I2(prbs_state_r[3]),
        .O(\prbs_state_r[1]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h5500551155005F11)) 
    \prbs_state_r[1]_i_5 
       (.I0(prbs_state_r[1]),
        .I1(\prbs_dqs_cnt_r[3]_i_4_n_0 ),
        .I2(\fine_pi_dec_cnt[5]_i_4_n_0 ),
        .I3(prbs_state_r[2]),
        .I4(prbs_state_r[0]),
        .I5(fine_inc_stage_reg_n_0),
        .O(\prbs_state_r[1]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair15" *) 
  LUT5 #(
    .INIT(32'hCC620000)) 
    \prbs_state_r[1]_i_6 
       (.I0(prbs_state_r[1]),
        .I1(prbs_state_r[0]),
        .I2(\smallest_right_edge[5]_i_3_n_0 ),
        .I3(prbs_state_r[2]),
        .I4(prbs_state_r[4]),
        .O(\prbs_state_r[1]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair25" *) 
  LUT5 #(
    .INIT(32'hFFFFFF10)) 
    \prbs_state_r[2]_i_1 
       (.I0(prbs_state_r[4]),
        .I1(prbs_state_r[3]),
        .I2(\prbs_state_r[2]_i_2_n_0 ),
        .I3(\prbs_state_r[2]_i_3_n_0 ),
        .I4(\prbs_state_r[2]_i_4_n_0 ),
        .O(\prbs_state_r[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hEEFCCC00EE30CC00)) 
    \prbs_state_r[2]_i_2 
       (.I0(\prbs_state_r[2]_i_5_n_0 ),
        .I1(prbs_state_r[0]),
        .I2(\prbs_state_r[4]_i_12_n_0 ),
        .I3(prbs_state_r[2]),
        .I4(prbs_state_r[1]),
        .I5(\prbs_state_r[3]_i_6_n_0 ),
        .O(\prbs_state_r[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0040444444440000)) 
    \prbs_state_r[2]_i_3 
       (.I0(prbs_state_r[4]),
        .I1(prbs_state_r[3]),
        .I2(\fine_pi_dec_cnt[5]_i_4_n_0 ),
        .I3(prbs_state_r[0]),
        .I4(prbs_state_r[2]),
        .I5(prbs_state_r[1]),
        .O(\prbs_state_r[2]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair15" *) 
  LUT5 #(
    .INIT(32'h62660000)) 
    \prbs_state_r[2]_i_4 
       (.I0(prbs_state_r[2]),
        .I1(prbs_state_r[0]),
        .I2(prbs_state_r[1]),
        .I3(\smallest_right_edge[5]_i_3_n_0 ),
        .I4(prbs_state_r[4]),
        .O(\prbs_state_r[2]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \prbs_state_r[2]_i_5 
       (.I0(\prbs_inc_tap_cnt_reg_n_0_[1] ),
        .I1(\prbs_inc_tap_cnt_reg_n_0_[2] ),
        .I2(\prbs_inc_tap_cnt_reg_n_0_[0] ),
        .I3(\prbs_inc_tap_cnt_reg_n_0_[5] ),
        .I4(\prbs_inc_tap_cnt_reg_n_0_[4] ),
        .I5(\prbs_inc_tap_cnt_reg_n_0_[3] ),
        .O(\prbs_state_r[2]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h000000000E00FFFF)) 
    \prbs_state_r[3]_i_1 
       (.I0(\prbs_state_r[3]_i_2_n_0 ),
        .I1(\prbs_state_r[3]_i_3_n_0 ),
        .I2(prbs_state_r[3]),
        .I3(\prbs_state_r[3]_i_4_n_0 ),
        .I4(\prbs_state_r[3]_i_5_n_0 ),
        .I5(prbs_state_r[4]),
        .O(\prbs_state_r[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair51" *) 
  LUT4 #(
    .INIT(16'h00DC)) 
    \prbs_state_r[3]_i_2 
       (.I0(\prbs_inc_tap_cnt[5]_i_4_n_0 ),
        .I1(prbs_dqs_tap_limit_r),
        .I2(prbs_found_1st_edge_r_reg_n_0),
        .I3(prbs_state_r[0]),
        .O(\prbs_state_r[3]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair51" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \prbs_state_r[3]_i_3 
       (.I0(prbs_state_r[0]),
        .I1(\prbs_state_r[3]_i_6_n_0 ),
        .O(\prbs_state_r[3]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair54" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \prbs_state_r[3]_i_4 
       (.I0(prbs_state_r[1]),
        .I1(prbs_state_r[2]),
        .O(\prbs_state_r[3]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFF0F4FFF0FFF0F0F)) 
    \prbs_state_r[3]_i_5 
       (.I0(\fine_pi_dec_cnt[5]_i_4_n_0 ),
        .I1(fine_inc_stage_reg_n_0),
        .I2(\prbs_state_r[1]_i_4_n_0 ),
        .I3(prbs_state_r[1]),
        .I4(prbs_state_r[0]),
        .I5(prbs_state_r[2]),
        .O(\prbs_state_r[3]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFEFF)) 
    \prbs_state_r[3]_i_6 
       (.I0(prbs_dec_tap_cnt[4]),
        .I1(prbs_dec_tap_cnt[5]),
        .I2(prbs_dec_tap_cnt[1]),
        .I3(prbs_dec_tap_cnt[0]),
        .I4(prbs_dec_tap_cnt[3]),
        .I5(prbs_dec_tap_cnt[2]),
        .O(\prbs_state_r[3]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFCCCECFCE)) 
    \prbs_state_r[4]_i_1 
       (.I0(\prbs_state_r[4]_i_3_n_0 ),
        .I1(\prbs_state_r[4]_i_4_n_0 ),
        .I2(\prbs_state_r[4]_i_5_n_0 ),
        .I3(prbs_state_r[4]),
        .I4(\prbs_state_r[4]_i_6_n_0 ),
        .I5(\prbs_state_r[4]_i_7_n_0 ),
        .O(\prbs_state_r[4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFAFFFAA0FCA0A0)) 
    \prbs_state_r[4]_i_10 
       (.I0(cnt_wait_state),
        .I1(prech_done),
        .I2(prbs_state_r[2]),
        .I3(prbs_state_r[1]),
        .I4(prbs_state_r[3]),
        .I5(prbs_state_r[0]),
        .O(\prbs_state_r[4]_i_10_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair25" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \prbs_state_r[4]_i_11 
       (.I0(prbs_state_r[3]),
        .I1(prbs_state_r[4]),
        .O(\prbs_state_r[4]_i_11_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair50" *) 
  LUT3 #(
    .INIT(8'h31)) 
    \prbs_state_r[4]_i_12 
       (.I0(prbs_found_1st_edge_r_reg_n_0),
        .I1(prbs_dqs_tap_limit_r),
        .I2(\prbs_inc_tap_cnt[5]_i_4_n_0 ),
        .O(\prbs_state_r[4]_i_12_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair26" *) 
  LUT5 #(
    .INIT(32'h2A2A082A)) 
    \prbs_state_r[4]_i_2 
       (.I0(\prbs_state_r[4]_i_8_n_0 ),
        .I1(prbs_state_r[4]),
        .I2(prbs_state_r[2]),
        .I3(prbs_state_r[3]),
        .I4(\prbs_state_r[4]_i_9_n_0 ),
        .O(\prbs_state_r[4]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair44" *) 
  LUT4 #(
    .INIT(16'h0004)) 
    \prbs_state_r[4]_i_3 
       (.I0(prbs_rdlvl_start_r),
        .I1(prbs_rdlvl_start_r_reg_0),
        .I2(prbs_state_r[0]),
        .I3(prbs_state_r[1]),
        .O(\prbs_state_r[4]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0000FFFF00000008)) 
    \prbs_state_r[4]_i_4 
       (.I0(num_samples_done_r),
        .I1(prbs_state_r[1]),
        .I2(prbs_state_r[2]),
        .I3(prbs_state_r[3]),
        .I4(prbs_state_r[4]),
        .I5(\prbs_state_r[4]_i_10_n_0 ),
        .O(\prbs_state_r[4]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair55" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \prbs_state_r[4]_i_5 
       (.I0(prbs_state_r[3]),
        .I1(prbs_state_r[2]),
        .O(\prbs_state_r[4]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h3300000F3355FF0F)) 
    \prbs_state_r[4]_i_6 
       (.I0(num_samples_done_ind_reg_n_0),
        .I1(\stage_cnt[0]_i_2_n_0 ),
        .I2(cnt_wait_state),
        .I3(prbs_state_r[0]),
        .I4(prbs_state_r[1]),
        .I5(num_samples_done_r),
        .O(\prbs_state_r[4]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h0000000800080008)) 
    \prbs_state_r[4]_i_7 
       (.I0(complex_act_start),
        .I1(prbs_state_r[2]),
        .I2(prbs_state_r[1]),
        .I3(\prbs_state_r[4]_i_11_n_0 ),
        .I4(prbs_state_r[0]),
        .I5(edge_det_error_reg_n_0),
        .O(\prbs_state_r[4]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hFFEEEEEEEEFEEEEE)) 
    \prbs_state_r[4]_i_8 
       (.I0(prbs_state_r[3]),
        .I1(prbs_state_r[4]),
        .I2(\prbs_state_r[4]_i_12_n_0 ),
        .I3(prbs_state_r[2]),
        .I4(prbs_state_r[1]),
        .I5(prbs_state_r[0]),
        .O(\prbs_state_r[4]_i_8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair28" *) 
  LUT5 #(
    .INIT(32'hF4000000)) 
    \prbs_state_r[4]_i_9 
       (.I0(\fine_pi_dec_cnt[5]_i_4_n_0 ),
        .I1(fine_inc_stage_reg_n_0),
        .I2(prbs_state_r[0]),
        .I3(prbs_state_r[1]),
        .I4(prbs_state_r[2]),
        .O(\prbs_state_r[4]_i_9_n_0 ));
  FDRE \prbs_state_r_reg[0] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(\prbs_state_r[4]_i_1_n_0 ),
        .D(\prbs_state_r[0]_i_1_n_0 ),
        .Q(prbs_state_r[0]),
        .R(\samples_cnt_r_reg[0]_0 ));
  FDRE \prbs_state_r_reg[1] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(\prbs_state_r[4]_i_1_n_0 ),
        .D(\prbs_state_r[1]_i_1_n_0 ),
        .Q(prbs_state_r[1]),
        .R(\samples_cnt_r_reg[0]_0 ));
  FDRE \prbs_state_r_reg[2] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(\prbs_state_r[4]_i_1_n_0 ),
        .D(\prbs_state_r[2]_i_1_n_0 ),
        .Q(prbs_state_r[2]),
        .R(\samples_cnt_r_reg[0]_0 ));
  FDRE \prbs_state_r_reg[3] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(\prbs_state_r[4]_i_1_n_0 ),
        .D(\prbs_state_r[3]_i_1_n_0 ),
        .Q(prbs_state_r[3]),
        .R(\samples_cnt_r_reg[0]_0 ));
  FDRE \prbs_state_r_reg[4] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(\prbs_state_r[4]_i_1_n_0 ),
        .D(\prbs_state_r[4]_i_2_n_0 ),
        .Q(prbs_state_r[4]),
        .R(\samples_cnt_r_reg[0]_0 ));
  LUT6 #(
    .INIT(64'hFD00FFFFFD000000)) 
    prbs_tap_en_r_i_1
       (.I0(prbs_state_r[3]),
        .I1(prbs_state_r[1]),
        .I2(\fine_pi_dec_cnt[5]_i_4_n_0 ),
        .I3(prbs_state_r[0]),
        .I4(prbs_tap_en_r),
        .I5(prbs_tap_en_r_reg_n_0),
        .O(prbs_tap_en_r_i_1_n_0));
  FDRE prbs_tap_en_r_reg
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_tap_en_r_i_1_n_0),
        .Q(prbs_tap_en_r_reg_n_0),
        .R(\prbs_dec_tap_cnt_reg[0]_0 ));
  LUT6 #(
    .INIT(64'h8088FFFF80880000)) 
    prbs_tap_inc_r_i_1
       (.I0(prbs_state_r[2]),
        .I1(prbs_state_r[0]),
        .I2(prbs_state_r[1]),
        .I3(prbs_state_r[3]),
        .I4(prbs_tap_en_r),
        .I5(prbs_tap_inc_r),
        .O(prbs_tap_inc_r_i_1_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFF00001006)) 
    prbs_tap_inc_r_i_2
       (.I0(prbs_state_r[3]),
        .I1(prbs_state_r[4]),
        .I2(prbs_state_r[1]),
        .I3(prbs_state_r[0]),
        .I4(prbs_state_r[2]),
        .I5(prbs_tap_inc_r_i_3_n_0),
        .O(prbs_tap_en_r));
  LUT6 #(
    .INIT(64'h000000005BFB0BBB)) 
    prbs_tap_inc_r_i_3
       (.I0(prbs_state_r[1]),
        .I1(prbs_state_r[3]),
        .I2(prbs_state_r[0]),
        .I3(prbs_dqs_tap_limit_r),
        .I4(\fine_pi_dec_cnt[5]_i_4_n_0 ),
        .I5(prbs_tap_inc_r_i_4_n_0),
        .O(prbs_tap_inc_r_i_3_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFF4440FFFF)) 
    prbs_tap_inc_r_i_4
       (.I0(prbs_state_r[3]),
        .I1(prbs_state_r[0]),
        .I2(prbs_dqs_tap_limit_r),
        .I3(prbs_state_r[1]),
        .I4(prbs_state_r[2]),
        .I5(prbs_state_r[4]),
        .O(prbs_tap_inc_r_i_4_n_0));
  FDRE prbs_tap_inc_r_reg
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(prbs_tap_inc_r_i_1_n_0),
        .Q(prbs_tap_inc_r),
        .R(\samples_cnt_r_reg[0]_0 ));
  FDRE \rd_mux_sel_r_reg[0] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\prbs_dqs_cnt_r_reg_n_0_[0] ),
        .Q(\rd_mux_sel_r_reg[2]_0 [0]),
        .R(1'b0));
  FDRE \rd_mux_sel_r_reg[1] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\prbs_dqs_cnt_r_reg_n_0_[1] ),
        .Q(\rd_mux_sel_r_reg[2]_0 [1]),
        .R(1'b0));
  FDRE \rd_mux_sel_r_reg[2] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\prbs_dqs_cnt_r_reg_n_0_[2] ),
        .Q(\rd_mux_sel_r_reg[2]_0 [2]),
        .R(1'b0));
  FDRE rd_valid_r1_reg
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(mux_rd_valid_r),
        .Q(rd_valid_r1),
        .R(1'b0));
  FDRE rd_valid_r2_reg
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(rd_valid_r1),
        .Q(rd_valid_r2_reg_n_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h000000000000E5A5)) 
    \rd_victim_sel[0]_i_1 
       (.I0(\samples_cnt_r_reg[11]_0 ),
        .I1(\rd_victim_sel_reg[1]_0 ),
        .I2(\rd_victim_sel_reg[0]_0 ),
        .I3(\rd_victim_sel_reg[2]_0 ),
        .I4(num_samples_done_r),
        .I5(\rd_victim_sel_reg[2]_1 ),
        .O(\rd_victim_sel[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h000000000000DC9C)) 
    \rd_victim_sel[1]_i_1 
       (.I0(\samples_cnt_r_reg[11]_0 ),
        .I1(\rd_victim_sel_reg[1]_0 ),
        .I2(\rd_victim_sel_reg[0]_0 ),
        .I3(\rd_victim_sel_reg[2]_0 ),
        .I4(num_samples_done_r),
        .I5(\rd_victim_sel_reg[2]_1 ),
        .O(\rd_victim_sel[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h000000000000FF40)) 
    \rd_victim_sel[2]_i_1 
       (.I0(\samples_cnt_r_reg[11]_0 ),
        .I1(\rd_victim_sel_reg[1]_0 ),
        .I2(\rd_victim_sel_reg[0]_0 ),
        .I3(\rd_victim_sel_reg[2]_0 ),
        .I4(num_samples_done_r),
        .I5(\rd_victim_sel_reg[2]_1 ),
        .O(\rd_victim_sel[2]_i_1_n_0 ));
  FDRE \rd_victim_sel_reg[0] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\rd_victim_sel[0]_i_1_n_0 ),
        .Q(\rd_victim_sel_reg[0]_0 ),
        .R(1'b0));
  FDRE \rd_victim_sel_reg[1] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\rd_victim_sel[1]_i_1_n_0 ),
        .Q(\rd_victim_sel_reg[1]_0 ),
        .R(1'b0));
  FDRE \rd_victim_sel_reg[2] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\rd_victim_sel[2]_i_1_n_0 ),
        .Q(\rd_victim_sel_reg[2]_0 ),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h4540)) 
    \rdlvl_cpt_tap_cnt[0]_i_1 
       (.I0(\rdlvl_cpt_tap_cnt_reg[5]_0 ),
        .I1(\rdlvl_cpt_tap_cnt_reg[5]_1 [0]),
        .I2(\rdlvl_cpt_tap_cnt_reg[5]_2 ),
        .I3(\rdlvl_cpt_tap_cnt_reg[5]_3 [0]),
        .O(D[0]));
  LUT4 #(
    .INIT(16'h4540)) 
    \rdlvl_cpt_tap_cnt[1]_i_1 
       (.I0(\rdlvl_cpt_tap_cnt_reg[5]_0 ),
        .I1(\rdlvl_cpt_tap_cnt_reg[5]_1 [1]),
        .I2(\rdlvl_cpt_tap_cnt_reg[5]_2 ),
        .I3(\rdlvl_cpt_tap_cnt_reg[5]_3 [1]),
        .O(D[1]));
  LUT4 #(
    .INIT(16'h4540)) 
    \rdlvl_cpt_tap_cnt[2]_i_1 
       (.I0(\rdlvl_cpt_tap_cnt_reg[5]_0 ),
        .I1(\rdlvl_cpt_tap_cnt_reg[5]_1 [2]),
        .I2(\rdlvl_cpt_tap_cnt_reg[5]_2 ),
        .I3(\rdlvl_cpt_tap_cnt_reg[5]_3 [2]),
        .O(D[2]));
  LUT4 #(
    .INIT(16'h4540)) 
    \rdlvl_cpt_tap_cnt[3]_i_1 
       (.I0(\rdlvl_cpt_tap_cnt_reg[5]_0 ),
        .I1(\rdlvl_cpt_tap_cnt_reg[5]_1 [3]),
        .I2(\rdlvl_cpt_tap_cnt_reg[5]_2 ),
        .I3(\rdlvl_cpt_tap_cnt_reg[5]_3 [3]),
        .O(D[3]));
  LUT4 #(
    .INIT(16'h4540)) 
    \rdlvl_cpt_tap_cnt[4]_i_1 
       (.I0(\rdlvl_cpt_tap_cnt_reg[5]_0 ),
        .I1(\rdlvl_cpt_tap_cnt_reg[5]_1 [4]),
        .I2(\rdlvl_cpt_tap_cnt_reg[5]_2 ),
        .I3(\rdlvl_cpt_tap_cnt_reg[5]_3 [4]),
        .O(D[4]));
  LUT4 #(
    .INIT(16'h4540)) 
    \rdlvl_cpt_tap_cnt[5]_i_1 
       (.I0(\rdlvl_cpt_tap_cnt_reg[5]_0 ),
        .I1(\rdlvl_cpt_tap_cnt_reg[5]_1 [5]),
        .I2(\rdlvl_cpt_tap_cnt_reg[5]_2 ),
        .I3(\rdlvl_cpt_tap_cnt_reg[5]_3 [5]),
        .O(D[5]));
  FDRE \rdlvl_cpt_tap_cnt_reg[0] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(new_cnt_dqs_r_reg_0),
        .D(D[0]),
        .Q(rdlvl_cpt_tap_cnt[0]),
        .R(\prbs_dec_tap_cnt_reg[0]_0 ));
  FDRE \rdlvl_cpt_tap_cnt_reg[1] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(new_cnt_dqs_r_reg_0),
        .D(D[1]),
        .Q(rdlvl_cpt_tap_cnt[1]),
        .R(\prbs_dec_tap_cnt_reg[0]_0 ));
  FDRE \rdlvl_cpt_tap_cnt_reg[2] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(new_cnt_dqs_r_reg_0),
        .D(D[2]),
        .Q(rdlvl_cpt_tap_cnt[2]),
        .R(\prbs_dec_tap_cnt_reg[0]_0 ));
  FDRE \rdlvl_cpt_tap_cnt_reg[3] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(new_cnt_dqs_r_reg_0),
        .D(D[3]),
        .Q(rdlvl_cpt_tap_cnt[3]),
        .R(\prbs_dec_tap_cnt_reg[0]_0 ));
  FDRE \rdlvl_cpt_tap_cnt_reg[4] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(new_cnt_dqs_r_reg_0),
        .D(D[4]),
        .Q(rdlvl_cpt_tap_cnt[4]),
        .R(\prbs_dec_tap_cnt_reg[0]_0 ));
  FDRE \rdlvl_cpt_tap_cnt_reg[5] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(new_cnt_dqs_r_reg_0),
        .D(D[5]),
        .Q(rdlvl_cpt_tap_cnt[5]),
        .R(\prbs_dec_tap_cnt_reg[0]_0 ));
  LUT3 #(
    .INIT(8'h02)) 
    reset_if_i_1
       (.I0(reset_if_i_2_n_0),
        .I1(reset_if_r9),
        .I2(reset_if_reg),
        .O(reset_if_r9_reg));
  (* SOFT_HLUTNM = "soft_lutpair35" *) 
  LUT5 #(
    .INIT(32'hFFFF22F2)) 
    reset_if_i_2
       (.I0(prbs_rdlvl_done_reg_0),
        .I1(prbs_rdlvl_done_r1),
        .I2(\gen_byte_sel_div2.byte_sel_cnt_reg[0] ),
        .I3(rdlvl_stg1_done_r1),
        .I4(reset_if),
        .O(reset_if_i_2_n_0));
  LUT6 #(
    .INIT(64'hFFFDFEFF00010000)) 
    reset_rd_addr_i_1
       (.I0(prbs_state_r[1]),
        .I1(prbs_state_r[4]),
        .I2(prbs_state_r[2]),
        .I3(prbs_state_r[0]),
        .I4(prbs_state_r[3]),
        .I5(reset_rd_addr),
        .O(reset_rd_addr_i_1_n_0));
  LUT2 #(
    .INIT(4'hE)) 
    reset_rd_addr_r1_i_1
       (.I0(reset_rd_addr),
        .I1(complex_ocal_reset_rd_addr),
        .O(reset_rd_addr0));
  FDRE reset_rd_addr_reg
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(reset_rd_addr_i_1_n_0),
        .Q(reset_rd_addr),
        .R(\match_flag_and_reg[7]_0 ));
  LUT6 #(
    .INIT(64'h10FFFFFF10000000)) 
    right_edge_found_i_1
       (.I0(prbs_state_r[4]),
        .I1(no_err_win_detected_reg_n_0),
        .I2(right_edge_found_i_2_n_0),
        .I3(right_edge_found_i_3_n_0),
        .I4(right_edge_found_i_4_n_0),
        .I5(right_edge_found_reg_n_0),
        .O(right_edge_found_i_1_n_0));
  LUT6 #(
    .INIT(64'h5555555555555551)) 
    right_edge_found_i_2
       (.I0(right_edge_found_reg_n_0),
        .I1(right_edge_found_i_5_n_0),
        .I2(\genblk8[7].right_edge_found_pb_reg_n_0_[7] ),
        .I3(\genblk8[6].right_edge_found_pb_reg_n_0_[6] ),
        .I4(\genblk8[5].right_edge_found_pb_reg_n_0_[5] ),
        .I5(\genblk8[4].right_edge_found_pb_reg_n_0_[4] ),
        .O(right_edge_found_i_2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair41" *) 
  LUT4 #(
    .INIT(16'h8100)) 
    right_edge_found_i_3
       (.I0(prbs_state_r[2]),
        .I1(prbs_state_r[3]),
        .I2(prbs_state_r[0]),
        .I3(prbs_state_r[1]),
        .O(right_edge_found_i_3_n_0));
  LUT6 #(
    .INIT(64'h0000EEEEFFF00000)) 
    right_edge_found_i_4
       (.I0(num_samples_done_ind_reg_n_0),
        .I1(num_samples_done_r),
        .I2(no_err_win_detected_reg_n_0),
        .I3(right_edge_found_i_2_n_0),
        .I4(prbs_state_r[3]),
        .I5(prbs_state_r[4]),
        .O(right_edge_found_i_4_n_0));
  (* SOFT_HLUTNM = "soft_lutpair58" *) 
  LUT4 #(
    .INIT(16'h0001)) 
    right_edge_found_i_5
       (.I0(\genblk8[1].right_edge_found_pb_reg_n_0_[1] ),
        .I1(\genblk8[0].right_edge_found_pb_reg_n_0_[0] ),
        .I2(\genblk8[3].right_edge_found_pb_reg_n_0_[3] ),
        .I3(\genblk8[2].right_edge_found_pb_reg_n_0_[2] ),
        .O(right_edge_found_i_5_n_0));
  FDRE right_edge_found_reg
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(right_edge_found_i_1_n_0),
        .Q(right_edge_found_reg_n_0),
        .R(\samples_cnt_r_reg[0]_0 ));
  LUT6 #(
    .INIT(64'h00000000FFFFFFFE)) 
    \samples_cnt_r[0]_i_1 
       (.I0(\samples_cnt_r_reg_n_0_[11] ),
        .I1(\samples_cnt_r_reg_n_0_[10] ),
        .I2(\samples_cnt_r_reg_n_0_[1] ),
        .I3(\samples_cnt_r[0]_i_2_n_0 ),
        .I4(\samples_cnt_r[0]_i_3_n_0 ),
        .I5(\samples_cnt_r_reg_n_0_[0] ),
        .O(\samples_cnt_r[0]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \samples_cnt_r[0]_i_2 
       (.I0(\samples_cnt_r_reg_n_0_[7] ),
        .I1(\samples_cnt_r_reg_n_0_[6] ),
        .I2(\samples_cnt_r_reg_n_0_[9] ),
        .I3(\samples_cnt_r_reg_n_0_[8] ),
        .O(\samples_cnt_r[0]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hFFF7)) 
    \samples_cnt_r[0]_i_3 
       (.I0(\samples_cnt_r_reg_n_0_[3] ),
        .I1(\samples_cnt_r_reg_n_0_[2] ),
        .I2(\samples_cnt_r_reg_n_0_[5] ),
        .I3(\samples_cnt_r_reg_n_0_[4] ),
        .O(\samples_cnt_r[0]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair75" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \samples_cnt_r[10]_i_1 
       (.I0(\samples_cnt_r_reg[11]_0 ),
        .I1(data0[10]),
        .O(\samples_cnt_r[10]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair76" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \samples_cnt_r[11]_i_2 
       (.I0(\samples_cnt_r_reg[11]_0 ),
        .I1(data0[11]),
        .O(\samples_cnt_r[11]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \samples_cnt_r[11]_i_3 
       (.I0(\samples_cnt_r_reg_n_0_[11] ),
        .I1(\samples_cnt_r_reg_n_0_[10] ),
        .I2(\samples_cnt_r_reg_n_0_[1] ),
        .I3(\samples_cnt_r[0]_i_2_n_0 ),
        .I4(\samples_cnt_r[0]_i_3_n_0 ),
        .I5(\samples_cnt_r_reg_n_0_[0] ),
        .O(\samples_cnt_r_reg[11]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair75" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \samples_cnt_r[1]_i_1 
       (.I0(\samples_cnt_r_reg[11]_0 ),
        .I1(data0[1]),
        .O(\samples_cnt_r[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair77" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \samples_cnt_r[2]_i_1 
       (.I0(\samples_cnt_r_reg[11]_0 ),
        .I1(data0[2]),
        .O(\samples_cnt_r[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair76" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \samples_cnt_r[3]_i_1 
       (.I0(\samples_cnt_r_reg[11]_0 ),
        .I1(data0[3]),
        .O(\samples_cnt_r[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair79" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \samples_cnt_r[4]_i_1 
       (.I0(\samples_cnt_r_reg[11]_0 ),
        .I1(data0[4]),
        .O(\samples_cnt_r[4]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair81" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \samples_cnt_r[5]_i_1 
       (.I0(\samples_cnt_r_reg[11]_0 ),
        .I1(data0[5]),
        .O(\samples_cnt_r[5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair79" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \samples_cnt_r[6]_i_1 
       (.I0(\samples_cnt_r_reg[11]_0 ),
        .I1(data0[6]),
        .O(\samples_cnt_r[6]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \samples_cnt_r[7]_i_1 
       (.I0(\samples_cnt_r_reg[11]_0 ),
        .I1(data0[7]),
        .O(\samples_cnt_r[7]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair81" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \samples_cnt_r[8]_i_1 
       (.I0(\samples_cnt_r_reg[11]_0 ),
        .I1(data0[8]),
        .O(\samples_cnt_r[8]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair77" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \samples_cnt_r[9]_i_1 
       (.I0(\samples_cnt_r_reg[11]_0 ),
        .I1(data0[9]),
        .O(\samples_cnt_r[9]_i_1_n_0 ));
  FDRE \samples_cnt_r_reg[0] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(E),
        .D(\samples_cnt_r[0]_i_1_n_0 ),
        .Q(\samples_cnt_r_reg_n_0_[0] ),
        .R(\samples_cnt_r_reg[0]_0 ));
  FDRE \samples_cnt_r_reg[10] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(E),
        .D(\samples_cnt_r[10]_i_1_n_0 ),
        .Q(\samples_cnt_r_reg_n_0_[10] ),
        .R(\samples_cnt_r_reg[0]_0 ));
  FDRE \samples_cnt_r_reg[11] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(E),
        .D(\samples_cnt_r[11]_i_2_n_0 ),
        .Q(\samples_cnt_r_reg_n_0_[11] ),
        .R(\samples_cnt_r_reg[0]_0 ));
  CARRY4 \samples_cnt_r_reg[11]_i_4 
       (.CI(\samples_cnt_r_reg[8]_i_2_n_0 ),
        .CO({\NLW_samples_cnt_r_reg[11]_i_4_CO_UNCONNECTED [3:2],\samples_cnt_r_reg[11]_i_4_n_2 ,\samples_cnt_r_reg[11]_i_4_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\NLW_samples_cnt_r_reg[11]_i_4_O_UNCONNECTED [3],data0[11:9]}),
        .S({1'b0,\samples_cnt_r_reg_n_0_[11] ,\samples_cnt_r_reg_n_0_[10] ,\samples_cnt_r_reg_n_0_[9] }));
  FDRE \samples_cnt_r_reg[1] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(E),
        .D(\samples_cnt_r[1]_i_1_n_0 ),
        .Q(\samples_cnt_r_reg_n_0_[1] ),
        .R(\samples_cnt_r_reg[0]_0 ));
  FDRE \samples_cnt_r_reg[2] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(E),
        .D(\samples_cnt_r[2]_i_1_n_0 ),
        .Q(\samples_cnt_r_reg_n_0_[2] ),
        .R(\samples_cnt_r_reg[0]_0 ));
  FDRE \samples_cnt_r_reg[3] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(E),
        .D(\samples_cnt_r[3]_i_1_n_0 ),
        .Q(\samples_cnt_r_reg_n_0_[3] ),
        .R(\samples_cnt_r_reg[0]_0 ));
  FDRE \samples_cnt_r_reg[4] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(E),
        .D(\samples_cnt_r[4]_i_1_n_0 ),
        .Q(\samples_cnt_r_reg_n_0_[4] ),
        .R(\samples_cnt_r_reg[0]_0 ));
  CARRY4 \samples_cnt_r_reg[4]_i_2 
       (.CI(1'b0),
        .CO({\samples_cnt_r_reg[4]_i_2_n_0 ,\samples_cnt_r_reg[4]_i_2_n_1 ,\samples_cnt_r_reg[4]_i_2_n_2 ,\samples_cnt_r_reg[4]_i_2_n_3 }),
        .CYINIT(\samples_cnt_r_reg_n_0_[0] ),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(data0[4:1]),
        .S({\samples_cnt_r_reg_n_0_[4] ,\samples_cnt_r_reg_n_0_[3] ,\samples_cnt_r_reg_n_0_[2] ,\samples_cnt_r_reg_n_0_[1] }));
  FDRE \samples_cnt_r_reg[5] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(E),
        .D(\samples_cnt_r[5]_i_1_n_0 ),
        .Q(\samples_cnt_r_reg_n_0_[5] ),
        .R(\samples_cnt_r_reg[0]_0 ));
  FDRE \samples_cnt_r_reg[6] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(E),
        .D(\samples_cnt_r[6]_i_1_n_0 ),
        .Q(\samples_cnt_r_reg_n_0_[6] ),
        .R(\samples_cnt_r_reg[0]_0 ));
  FDRE \samples_cnt_r_reg[7] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(E),
        .D(\samples_cnt_r[7]_i_1_n_0 ),
        .Q(\samples_cnt_r_reg_n_0_[7] ),
        .R(\samples_cnt_r_reg[0]_0 ));
  FDRE \samples_cnt_r_reg[8] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(E),
        .D(\samples_cnt_r[8]_i_1_n_0 ),
        .Q(\samples_cnt_r_reg_n_0_[8] ),
        .R(\samples_cnt_r_reg[0]_0 ));
  CARRY4 \samples_cnt_r_reg[8]_i_2 
       (.CI(\samples_cnt_r_reg[4]_i_2_n_0 ),
        .CO({\samples_cnt_r_reg[8]_i_2_n_0 ,\samples_cnt_r_reg[8]_i_2_n_1 ,\samples_cnt_r_reg[8]_i_2_n_2 ,\samples_cnt_r_reg[8]_i_2_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O(data0[8:5]),
        .S({\samples_cnt_r_reg_n_0_[8] ,\samples_cnt_r_reg_n_0_[7] ,\samples_cnt_r_reg_n_0_[6] ,\samples_cnt_r_reg_n_0_[5] }));
  FDRE \samples_cnt_r_reg[9] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(E),
        .D(\samples_cnt_r[9]_i_1_n_0 ),
        .Q(\samples_cnt_r_reg_n_0_[9] ),
        .R(\samples_cnt_r_reg[0]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair72" *) 
  LUT2 #(
    .INIT(4'h7)) 
    \smallest_right_edge[0]_i_1 
       (.I0(prbs_state_r[0]),
        .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),
        .O(\smallest_right_edge[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair72" *) 
  LUT3 #(
    .INIT(8'hD7)) 
    \smallest_right_edge[1]_i_1 
       (.I0(prbs_state_r[0]),
        .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),
        .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),
        .O(\smallest_right_edge[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair32" *) 
  LUT4 #(
    .INIT(16'hFD57)) 
    \smallest_right_edge[2]_i_1 
       (.I0(prbs_state_r[0]),
        .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),
        .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),
        .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),
        .O(\smallest_right_edge[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair32" *) 
  LUT5 #(
    .INIT(32'hFFFD5557)) 
    \smallest_right_edge[3]_i_1 
       (.I0(prbs_state_r[0]),
        .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),
        .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),
        .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),
        .I4(\prbs_dqs_tap_cnt_r_reg_n_0_[3] ),
        .O(\smallest_right_edge[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFD55555557)) 
    \smallest_right_edge[4]_i_1 
       (.I0(prbs_state_r[0]),
        .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[3] ),
        .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),
        .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),
        .I4(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),
        .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),
        .O(\smallest_right_edge[4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFF0020200000)) 
    \smallest_right_edge[5]_i_1 
       (.I0(\smallest_right_edge[5]_i_3_n_0 ),
        .I1(right_edge_found_reg_n_0),
        .I2(num_samples_done_r),
        .I3(\smallest_right_edge[5]_i_4_n_0 ),
        .I4(\smallest_right_edge[5]_i_5_n_0 ),
        .I5(\smallest_right_edge[5]_i_6_n_0 ),
        .O(smallest_right_edge));
  (* SOFT_HLUTNM = "soft_lutpair58" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \smallest_right_edge[5]_i_10 
       (.I0(\genblk8[1].right_edge_found_pb_reg_n_0_[1] ),
        .I1(\genblk8[0].right_edge_found_pb_reg_n_0_[0] ),
        .I2(\genblk8[3].right_edge_found_pb_reg_n_0_[3] ),
        .I3(\genblk8[2].right_edge_found_pb_reg_n_0_[2] ),
        .O(\smallest_right_edge[5]_i_10_n_0 ));
  LUT2 #(
    .INIT(4'h7)) 
    \smallest_right_edge[5]_i_2 
       (.I0(prbs_state_r[0]),
        .I1(\prbs_dqs_tap_cnt_r[5]_i_4_n_0 ),
        .O(\smallest_right_edge[5]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAAAEA)) 
    \smallest_right_edge[5]_i_3 
       (.I0(\smallest_right_edge[5]_i_7_n_0 ),
        .I1(\smallest_right_edge[5]_i_8_n_0 ),
        .I2(\smallest_right_edge[5]_i_9_n_0 ),
        .I3(\match_flag_and_reg_n_0_[0] ),
        .I4(\match_flag_and_reg_n_0_[1] ),
        .I5(\match_flag_and_reg_n_0_[2] ),
        .O(\smallest_right_edge[5]_i_3_n_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \smallest_right_edge[5]_i_4 
       (.I0(right_edge_found_i_2_n_0),
        .I1(no_err_win_detected_reg_n_0),
        .O(\smallest_right_edge[5]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair20" *) 
  LUT5 #(
    .INIT(32'h00011000)) 
    \smallest_right_edge[5]_i_5 
       (.I0(prbs_state_r[1]),
        .I1(prbs_state_r[2]),
        .I2(prbs_state_r[0]),
        .I3(prbs_state_r[4]),
        .I4(prbs_state_r[3]),
        .O(\smallest_right_edge[5]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair30" *) 
  LUT5 #(
    .INIT(32'h40000004)) 
    \smallest_right_edge[5]_i_6 
       (.I0(prbs_state_r[4]),
        .I1(prbs_state_r[3]),
        .I2(prbs_state_r[2]),
        .I3(prbs_state_r[1]),
        .I4(prbs_state_r[0]),
        .O(\smallest_right_edge[5]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \smallest_right_edge[5]_i_7 
       (.I0(\smallest_right_edge[5]_i_10_n_0 ),
        .I1(\genblk8[7].right_edge_found_pb_reg_n_0_[7] ),
        .I2(\genblk8[6].right_edge_found_pb_reg_n_0_[6] ),
        .I3(\genblk8[5].right_edge_found_pb_reg_n_0_[5] ),
        .I4(\genblk8[4].right_edge_found_pb_reg_n_0_[4] ),
        .I5(prbs_dqs_tap_limit_r),
        .O(\smallest_right_edge[5]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hFEFEFEFEFEFEFEEE)) 
    \smallest_right_edge[5]_i_8 
       (.I0(\prbs_dqs_tap_cnt_r_reg_n_0_[5] ),
        .I1(\prbs_dqs_tap_cnt_r_reg_n_0_[4] ),
        .I2(\prbs_dqs_tap_cnt_r_reg_n_0_[3] ),
        .I3(\prbs_dqs_tap_cnt_r_reg_n_0_[2] ),
        .I4(\prbs_dqs_tap_cnt_r_reg_n_0_[1] ),
        .I5(\prbs_dqs_tap_cnt_r_reg_n_0_[0] ),
        .O(\smallest_right_edge[5]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'h0000000100000000)) 
    \smallest_right_edge[5]_i_9 
       (.I0(\match_flag_and_reg_n_0_[3] ),
        .I1(\match_flag_and_reg_n_0_[4] ),
        .I2(\match_flag_and_reg_n_0_[5] ),
        .I3(\match_flag_and_reg_n_0_[6] ),
        .I4(\match_flag_and_reg_n_0_[7] ),
        .I5(compare_err_pb_and_reg_n_0),
        .O(\smallest_right_edge[5]_i_9_n_0 ));
  FDSE \smallest_right_edge_reg[0] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(smallest_right_edge),
        .D(\smallest_right_edge[0]_i_1_n_0 ),
        .Q(\smallest_right_edge_reg_n_0_[0] ),
        .S(\samples_cnt_r_reg[0]_0 ));
  FDSE \smallest_right_edge_reg[1] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(smallest_right_edge),
        .D(\smallest_right_edge[1]_i_1_n_0 ),
        .Q(\smallest_right_edge_reg_n_0_[1] ),
        .S(\samples_cnt_r_reg[0]_0 ));
  FDSE \smallest_right_edge_reg[2] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(smallest_right_edge),
        .D(\smallest_right_edge[2]_i_1_n_0 ),
        .Q(\smallest_right_edge_reg_n_0_[2] ),
        .S(\samples_cnt_r_reg[0]_0 ));
  FDSE \smallest_right_edge_reg[3] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(smallest_right_edge),
        .D(\smallest_right_edge[3]_i_1_n_0 ),
        .Q(\smallest_right_edge_reg_n_0_[3] ),
        .S(\samples_cnt_r_reg[0]_0 ));
  FDSE \smallest_right_edge_reg[4] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(smallest_right_edge),
        .D(\smallest_right_edge[4]_i_1_n_0 ),
        .Q(\smallest_right_edge_reg_n_0_[4] ),
        .S(\samples_cnt_r_reg[0]_0 ));
  FDSE \smallest_right_edge_reg[5] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(smallest_right_edge),
        .D(\smallest_right_edge[5]_i_2_n_0 ),
        .Q(\smallest_right_edge_reg_n_0_[5] ),
        .S(\samples_cnt_r_reg[0]_0 ));
  LUT6 #(
    .INIT(64'hDFFFFCFF20000000)) 
    \stage_cnt[0]_i_1 
       (.I0(\stage_cnt[0]_i_2_n_0 ),
        .I1(\prbs_state_r[4]_i_5_n_0 ),
        .I2(prbs_state_r[4]),
        .I3(prbs_state_r[0]),
        .I4(prbs_state_r[1]),
        .I5(\stage_cnt_reg_n_0_[0] ),
        .O(\stage_cnt[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000010)) 
    \stage_cnt[0]_i_2 
       (.I0(p_0_in__0[6]),
        .I1(p_0_in__0[7]),
        .I2(\bit_cnt_reg_n_0_[3] ),
        .I3(\bit_cnt_reg_n_0_[2] ),
        .I4(\bit_cnt_reg_n_0_[0] ),
        .I5(\bit_cnt_reg_n_0_[1] ),
        .O(\stage_cnt[0]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair43" *) 
  LUT4 #(
    .INIT(16'h2F80)) 
    \stage_cnt[1]_i_1 
       (.I0(prbs_state_r[4]),
        .I1(\stage_cnt_reg_n_0_[0] ),
        .I2(\stage_cnt[1]_i_2_n_0 ),
        .I3(\stage_cnt_reg_n_0_[1] ),
        .O(\stage_cnt[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0200000000030000)) 
    \stage_cnt[1]_i_2 
       (.I0(\stage_cnt[0]_i_2_n_0 ),
        .I1(prbs_state_r[2]),
        .I2(prbs_state_r[3]),
        .I3(prbs_state_r[4]),
        .I4(prbs_state_r[0]),
        .I5(prbs_state_r[1]),
        .O(\stage_cnt[1]_i_2_n_0 ));
  FDRE \stage_cnt_reg[0] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\stage_cnt[0]_i_1_n_0 ),
        .Q(\stage_cnt_reg_n_0_[0] ),
        .R(\samples_cnt_r_reg[0]_0 ));
  FDRE \stage_cnt_reg[1] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\stage_cnt[1]_i_1_n_0 ),
        .Q(\stage_cnt_reg_n_0_[1] ),
        .R(\samples_cnt_r_reg[0]_0 ));
  LUT6 #(
    .INIT(64'h8AAA8AAAAA8A8AAA)) 
    \victim_not_fixed.num_samples_done_r_i_1 
       (.I0(\victim_not_fixed.num_samples_done_r_i_2_n_0 ),
        .I1(prbs_state_r[4]),
        .I2(prbs_state_r[0]),
        .I3(prbs_state_r[2]),
        .I4(prbs_state_r[1]),
        .I5(prbs_state_r[3]),
        .O(\victim_not_fixed.num_samples_done_r_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AAAAEAAA)) 
    \victim_not_fixed.num_samples_done_r_i_2 
       (.I0(num_samples_done_r),
        .I1(\rd_victim_sel_reg[2]_0 ),
        .I2(\rd_victim_sel_reg[0]_0 ),
        .I3(\rd_victim_sel_reg[1]_0 ),
        .I4(\samples_cnt_r_reg[11]_0 ),
        .I5(\rd_victim_sel_reg[2]_1 ),
        .O(\victim_not_fixed.num_samples_done_r_i_2_n_0 ));
  FDRE \victim_not_fixed.num_samples_done_r_reg 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(\victim_not_fixed.num_samples_done_r_i_1_n_0 ),
        .Q(num_samples_done_r),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair30" *) 
  LUT5 #(
    .INIT(32'h0101081C)) 
    wait_state_cnt_en_r_i_1
       (.I0(prbs_state_r[1]),
        .I1(prbs_state_r[2]),
        .I2(prbs_state_r[4]),
        .I3(prbs_state_r[3]),
        .I4(prbs_state_r[0]),
        .O(wait_state_cnt_en_r0));
  FDRE wait_state_cnt_en_r_reg
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(wait_state_cnt_en_r0),
        .Q(wait_state_cnt_en_r),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair80" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \wait_state_cnt_r[0]_i_1 
       (.I0(wait_state_cnt_r_reg[0]),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair80" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \wait_state_cnt_r[1]_i_1 
       (.I0(wait_state_cnt_r_reg[0]),
        .I1(wait_state_cnt_r_reg[1]),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair64" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \wait_state_cnt_r[2]_i_1 
       (.I0(wait_state_cnt_r_reg[2]),
        .I1(wait_state_cnt_r_reg[1]),
        .I2(wait_state_cnt_r_reg[0]),
        .O(p_0_in[2]));
  LUT5 #(
    .INIT(32'h8000FFFF)) 
    \wait_state_cnt_r[3]_i_1 
       (.I0(wait_state_cnt_r_reg[3]),
        .I1(wait_state_cnt_r_reg[2]),
        .I2(wait_state_cnt_r_reg[1]),
        .I3(wait_state_cnt_r_reg[0]),
        .I4(wait_state_cnt_en_r),
        .O(\wait_state_cnt_r[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair64" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \wait_state_cnt_r[3]_i_2 
       (.I0(wait_state_cnt_r_reg[3]),
        .I1(wait_state_cnt_r_reg[0]),
        .I2(wait_state_cnt_r_reg[1]),
        .I3(wait_state_cnt_r_reg[2]),
        .O(p_0_in[3]));
  FDRE \wait_state_cnt_r_reg[0] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(wait_state_cnt_r_reg[0]),
        .R(\wait_state_cnt_r[3]_i_1_n_0 ));
  FDRE \wait_state_cnt_r_reg[1] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(wait_state_cnt_r_reg[1]),
        .R(\wait_state_cnt_r[3]_i_1_n_0 ));
  FDRE \wait_state_cnt_r_reg[2] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(wait_state_cnt_r_reg[2]),
        .R(\wait_state_cnt_r[3]_i_1_n_0 ));
  FDRE \wait_state_cnt_r_reg[3] 
       (.C(\bit_cnt_reg[7]_0 ),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(wait_state_cnt_r_reg[3]),
        .R(\wait_state_cnt_r[3]_i_1_n_0 ));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_phy_rdlvl" *) 
module mig_mig_7series_v4_2_ddr_phy_rdlvl
   (new_cnt_cpt_r_reg_0,
    samp_edge_cnt0_en_r,
    idelay_ce_int,
    idelay_inc_int,
    rdlvl_prech_req,
    pi_fine_dly_dec_done,
    rdlvl_pi_stg2_f_en,
    rdlvl_pi_stg2_f_incdec,
    pi_stg2_load_reg_0,
    pi_cnt_dec_reg_0,
    rdlvl_stg1_done_int_reg_0,
    rdlvl_stg1_rank_done,
    rdlvl_last_byte_done,
    rdlvl_pi_incdec,
    \rnk_cnt_r_reg[1]_0 ,
    \cal1_cnt_cpt_r_reg[2]_0 ,
    \rd_mux_sel_r_reg[2]_0 ,
    Q,
    rdlvl_stg1_done_int_reg_1,
    rdlvl_stg1_done_int_reg_2,
    p_1_in,
    \cal1_cnt_cpt_r_reg[2]_1 ,
    \cal1_cnt_cpt_r_reg[0]_0 ,
    \cal1_cnt_cpt_r_reg[0]_1 ,
    cal1_dq_idel_ce_reg_0,
    \rnk_cnt_r_reg[0]_0 ,
    cal1_dq_idel_ce_reg_1,
    cal1_dq_idel_ce_reg_2,
    prech_req,
    rdlvl_stg1_done_r1_reg,
    rdlvl_stg1_done_int_reg_3,
    \pi_stg2_reg_l_reg[5]_0 ,
    \rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 ,
    rdlvl_pi_incdec_reg_0,
    \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ,
    \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ,
    \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ,
    \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ,
    \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0 ,
    \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0 ,
    \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0 ,
    \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0 ,
    \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0 ,
    \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ,
    \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0 ,
    \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ,
    \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0 ,
    \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ,
    \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0 ,
    \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ,
    \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0 ,
    \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ,
    \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0 ,
    \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ,
    \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0 ,
    \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ,
    \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0 ,
    \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ,
    \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0 ,
    \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ,
    \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0 ,
    \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ,
    \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0 ,
    \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ,
    \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0 ,
    \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ,
    \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0 ,
    \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ,
    \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0 ,
    \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ,
    \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0 ,
    \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ,
    \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0 ,
    \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ,
    \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0 ,
    \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ,
    \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0 ,
    \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ,
    \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0 ,
    \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ,
    \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0 ,
    \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ,
    \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0 ,
    \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ,
    \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0 ,
    \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ,
    \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0 ,
    \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ,
    \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0 ,
    \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ,
    \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0 ,
    \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ,
    \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 ,
    \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ,
    \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0 ,
    \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ,
    \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0 ,
    \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ,
    mpr_rdlvl_start_r_reg_0,
    rdlvl_stg1_start_r_reg_0,
    E,
    dqs_po_dec_done,
    \samp_edge_cnt1_r_reg[0]_0 ,
    sr_valid_r_reg_0,
    SR,
    found_second_edge_r_reg_0,
    pi_stg2_f_incdec_timing_reg_0,
    \stg1_wr_rd_cnt_reg[3] ,
    stg1_wr_done,
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56] ,
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 ,
    \done_cnt_reg[2]_0 ,
    prech_done,
    D,
    wrcal_prech_req,
    prech_req_r_reg,
    dqs_found_prech_req,
    prech_req_r_reg_0,
    rdlvl_stg1_done_r1,
    \init_state_r[1]_i_16 ,
    \gen_byte_sel_div2.byte_sel_cnt_reg[3] ,
    \gen_byte_sel_div2.byte_sel_cnt_reg[3]_0 ,
    \gen_byte_sel_div2.byte_sel_cnt_reg[3]_1 ,
    \gen_byte_sel_div2.byte_sel_cnt_reg[2] ,
    \gen_byte_sel_div2.byte_sel_cnt_reg[2]_0 ,
    \gen_byte_sel_div2.byte_sel_cnt_reg[1] ,
    \gen_byte_sel_div2.byte_sel_cnt_reg[1]_0 ,
    \gen_byte_sel_div2.byte_sel_cnt_reg[0] ,
    \gen_byte_sel_div2.byte_sel_cnt_reg[0]_0 ,
    \idelay_tap_cnt_r_reg[0][0][4]_0 ,
    \idelay_tap_cnt_r_reg[0][1][4]_0 ,
    \idelay_tap_cnt_r_reg[0][2][4]_0 ,
    \idelay_tap_cnt_r_reg[0][3][4]_0 ,
    \idelay_tap_cnt_r_reg[0][4][4]_0 ,
    \idelay_tap_cnt_r_reg[0][5][4]_0 ,
    \idelay_tap_cnt_r_reg[0][6][4]_0 ,
    \idelay_tap_cnt_r_reg[0][7][4]_0 ,
    \tap_cnt_cpt_r_reg[5]_0 ,
    \cnt_shift_r_reg[0]_0 ,
    \wait_cnt_r_reg[0]_0 );
  output new_cnt_cpt_r_reg_0;
  output samp_edge_cnt0_en_r;
  output idelay_ce_int;
  output idelay_inc_int;
  output rdlvl_prech_req;
  output pi_fine_dly_dec_done;
  output rdlvl_pi_stg2_f_en;
  output rdlvl_pi_stg2_f_incdec;
  output pi_stg2_load_reg_0;
  output pi_cnt_dec_reg_0;
  output rdlvl_stg1_done_int_reg_0;
  output rdlvl_stg1_rank_done;
  output rdlvl_last_byte_done;
  output rdlvl_pi_incdec;
  output \rnk_cnt_r_reg[1]_0 ;
  output \cal1_cnt_cpt_r_reg[2]_0 ;
  output \rd_mux_sel_r_reg[2]_0 ;
  output [1:0]Q;
  output rdlvl_stg1_done_int_reg_1;
  output [0:0]rdlvl_stg1_done_int_reg_2;
  output p_1_in;
  output \cal1_cnt_cpt_r_reg[2]_1 ;
  output \cal1_cnt_cpt_r_reg[0]_0 ;
  output \cal1_cnt_cpt_r_reg[0]_1 ;
  output cal1_dq_idel_ce_reg_0;
  output \rnk_cnt_r_reg[0]_0 ;
  output cal1_dq_idel_ce_reg_1;
  output cal1_dq_idel_ce_reg_2;
  output prech_req;
  output rdlvl_stg1_done_r1_reg;
  output [3:0]rdlvl_stg1_done_int_reg_3;
  output [5:0]\pi_stg2_reg_l_reg[5]_0 ;
  input [1:0]\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 ;
  input rdlvl_pi_incdec_reg_0;
  input \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ;
  input \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ;
  input \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ;
  input \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ;
  input \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0 ;
  input \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0 ;
  input \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0 ;
  input \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0 ;
  input \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0 ;
  input \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ;
  input \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0 ;
  input \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ;
  input \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0 ;
  input \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ;
  input \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0 ;
  input \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ;
  input \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0 ;
  input \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ;
  input \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0 ;
  input \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ;
  input \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0 ;
  input \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ;
  input \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0 ;
  input \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ;
  input \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0 ;
  input \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ;
  input \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0 ;
  input \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ;
  input \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0 ;
  input \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ;
  input \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0 ;
  input \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ;
  input \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0 ;
  input \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ;
  input \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0 ;
  input \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ;
  input \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0 ;
  input \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ;
  input \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0 ;
  input \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ;
  input \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0 ;
  input \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ;
  input \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0 ;
  input \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ;
  input \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0 ;
  input \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ;
  input \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0 ;
  input \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ;
  input \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0 ;
  input \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ;
  input \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0 ;
  input \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ;
  input \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0 ;
  input \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ;
  input \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0 ;
  input \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ;
  input \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0 ;
  input \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ;
  input \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 ;
  input \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ;
  input \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0 ;
  input \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ;
  input \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0 ;
  input \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ;
  input mpr_rdlvl_start_r_reg_0;
  input rdlvl_stg1_start_r_reg_0;
  input [0:0]E;
  input dqs_po_dec_done;
  input \samp_edge_cnt1_r_reg[0]_0 ;
  input sr_valid_r_reg_0;
  input [1:0]SR;
  input found_second_edge_r_reg_0;
  input pi_stg2_f_incdec_timing_reg_0;
  input \stg1_wr_rd_cnt_reg[3] ;
  input stg1_wr_done;
  input \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56] ;
  input \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 ;
  input \done_cnt_reg[2]_0 ;
  input prech_done;
  input [5:0]D;
  input wrcal_prech_req;
  input prech_req_r_reg;
  input dqs_found_prech_req;
  input prech_req_r_reg_0;
  input rdlvl_stg1_done_r1;
  input [0:0]\init_state_r[1]_i_16 ;
  input \gen_byte_sel_div2.byte_sel_cnt_reg[3] ;
  input \gen_byte_sel_div2.byte_sel_cnt_reg[3]_0 ;
  input [0:0]\gen_byte_sel_div2.byte_sel_cnt_reg[3]_1 ;
  input \gen_byte_sel_div2.byte_sel_cnt_reg[2] ;
  input \gen_byte_sel_div2.byte_sel_cnt_reg[2]_0 ;
  input \gen_byte_sel_div2.byte_sel_cnt_reg[1] ;
  input \gen_byte_sel_div2.byte_sel_cnt_reg[1]_0 ;
  input \gen_byte_sel_div2.byte_sel_cnt_reg[0] ;
  input \gen_byte_sel_div2.byte_sel_cnt_reg[0]_0 ;
  input [0:0]\idelay_tap_cnt_r_reg[0][0][4]_0 ;
  input [0:0]\idelay_tap_cnt_r_reg[0][1][4]_0 ;
  input [0:0]\idelay_tap_cnt_r_reg[0][2][4]_0 ;
  input [0:0]\idelay_tap_cnt_r_reg[0][3][4]_0 ;
  input [0:0]\idelay_tap_cnt_r_reg[0][4][4]_0 ;
  input [0:0]\idelay_tap_cnt_r_reg[0][5][4]_0 ;
  input [0:0]\idelay_tap_cnt_r_reg[0][6][4]_0 ;
  input [0:0]\idelay_tap_cnt_r_reg[0][7][4]_0 ;
  input [0:0]\tap_cnt_cpt_r_reg[5]_0 ;
  input [0:0]\cnt_shift_r_reg[0]_0 ;
  input [0:0]\wait_cnt_r_reg[0]_0 ;

  wire [5:0]D;
  wire [0:0]E;
  wire \FSM_onehot_cal1_state_r[10]_i_1_n_0 ;
  wire \FSM_onehot_cal1_state_r[11]_i_1_n_0 ;
  wire \FSM_onehot_cal1_state_r[13]_i_1_n_0 ;
  wire \FSM_onehot_cal1_state_r[14]_i_1_n_0 ;
  wire \FSM_onehot_cal1_state_r[15]_i_1_n_0 ;
  wire \FSM_onehot_cal1_state_r[15]_i_2_n_0 ;
  wire \FSM_onehot_cal1_state_r[15]_i_3_n_0 ;
  wire \FSM_onehot_cal1_state_r[16]_i_1_n_0 ;
  wire \FSM_onehot_cal1_state_r[16]_i_2_n_0 ;
  wire \FSM_onehot_cal1_state_r[16]_i_3_n_0 ;
  wire \FSM_onehot_cal1_state_r[16]_i_4_n_0 ;
  wire \FSM_onehot_cal1_state_r[1]_i_1_n_0 ;
  wire \FSM_onehot_cal1_state_r[20]_i_1_n_0 ;
  wire \FSM_onehot_cal1_state_r[21]_i_1_n_0 ;
  wire \FSM_onehot_cal1_state_r[21]_i_2_n_0 ;
  wire \FSM_onehot_cal1_state_r[21]_i_3_n_0 ;
  wire \FSM_onehot_cal1_state_r[22]_i_1_n_0 ;
  wire \FSM_onehot_cal1_state_r[22]_i_2_n_0 ;
  wire \FSM_onehot_cal1_state_r[29]_i_1_n_0 ;
  wire \FSM_onehot_cal1_state_r[2]_i_1_n_0 ;
  wire \FSM_onehot_cal1_state_r[34]_i_10_n_0 ;
  wire \FSM_onehot_cal1_state_r[34]_i_11_n_0 ;
  wire \FSM_onehot_cal1_state_r[34]_i_12_n_0 ;
  wire \FSM_onehot_cal1_state_r[34]_i_13_n_0 ;
  wire \FSM_onehot_cal1_state_r[34]_i_1_n_0 ;
  wire \FSM_onehot_cal1_state_r[34]_i_2_n_0 ;
  wire \FSM_onehot_cal1_state_r[34]_i_3_n_0 ;
  wire \FSM_onehot_cal1_state_r[34]_i_4_n_0 ;
  wire \FSM_onehot_cal1_state_r[34]_i_5_n_0 ;
  wire \FSM_onehot_cal1_state_r[34]_i_6_n_0 ;
  wire \FSM_onehot_cal1_state_r[34]_i_8_n_0 ;
  wire \FSM_onehot_cal1_state_r[34]_i_9_n_0 ;
  wire \FSM_onehot_cal1_state_r[4]_i_1_n_0 ;
  wire \FSM_onehot_cal1_state_r[5]_i_1_n_0 ;
  wire \FSM_onehot_cal1_state_r[5]_i_2_n_0 ;
  wire \FSM_onehot_cal1_state_r[5]_i_3_n_0 ;
  wire \FSM_onehot_cal1_state_r[6]_i_1_n_0 ;
  wire \FSM_onehot_cal1_state_r[6]_i_2_n_0 ;
  wire \FSM_onehot_cal1_state_r[7]_i_1_n_0 ;
  wire \FSM_onehot_cal1_state_r[8]_i_1_n_0 ;
  wire \FSM_onehot_cal1_state_r[9]_i_1_n_0 ;
  wire \FSM_onehot_cal1_state_r_reg_n_0_[12] ;
  wire \FSM_onehot_cal1_state_r_reg_n_0_[15] ;
  wire \FSM_onehot_cal1_state_r_reg_n_0_[16] ;
  wire \FSM_onehot_cal1_state_r_reg_n_0_[1] ;
  wire \FSM_onehot_cal1_state_r_reg_n_0_[22] ;
  wire \FSM_onehot_cal1_state_r_reg_n_0_[29] ;
  wire \FSM_onehot_cal1_state_r_reg_n_0_[3] ;
  wire \FSM_onehot_cal1_state_r_reg_n_0_[7] ;
  wire \FSM_onehot_cal1_state_r_reg_n_0_[8] ;
  wire [1:0]Q;
  wire [1:0]SR;
  wire \cal1_cnt_cpt_r[0]_i_1_n_0 ;
  wire \cal1_cnt_cpt_r[1]_i_1_n_0 ;
  wire \cal1_cnt_cpt_r[2]_i_1_n_0 ;
  wire \cal1_cnt_cpt_r[2]_i_2_n_0 ;
  wire \cal1_cnt_cpt_r[2]_i_3_n_0 ;
  wire \cal1_cnt_cpt_r_reg[0]_0 ;
  wire \cal1_cnt_cpt_r_reg[0]_1 ;
  wire \cal1_cnt_cpt_r_reg[2]_0 ;
  wire \cal1_cnt_cpt_r_reg[2]_1 ;
  wire \cal1_cnt_cpt_r_reg_n_0_[0] ;
  wire \cal1_cnt_cpt_r_reg_n_0_[1] ;
  wire \cal1_cnt_cpt_r_reg_n_0_[2] ;
  wire cal1_dlyce_cpt_r;
  wire cal1_dlyce_cpt_r_reg_n_0;
  wire cal1_dlyinc_cpt_r;
  wire cal1_dlyinc_cpt_r_reg_n_0;
  wire cal1_dq_idel_ce;
  wire cal1_dq_idel_ce_reg_0;
  wire cal1_dq_idel_ce_reg_1;
  wire cal1_dq_idel_ce_reg_2;
  wire cal1_dq_idel_inc;
  wire cal1_prech_req_r;
  wire cal1_prech_req_r__0;
  wire \cal1_state_r1[0]_i_1_n_0 ;
  wire \cal1_state_r1[0]_i_2_n_0 ;
  wire \cal1_state_r1[0]_i_3_n_0 ;
  wire \cal1_state_r1[1]_i_1_n_0 ;
  wire \cal1_state_r1[1]_i_2_n_0 ;
  wire \cal1_state_r1[2]_i_1_n_0 ;
  wire \cal1_state_r1[2]_i_2_n_0 ;
  wire \cal1_state_r1[3]_i_1_n_0 ;
  wire \cal1_state_r1[3]_i_2_n_0 ;
  wire \cal1_state_r1[3]_i_3_n_0 ;
  wire \cal1_state_r1[4]_i_1_n_0 ;
  wire \cal1_state_r1[5]_i_1_n_0 ;
  wire \cal1_state_r1_reg_n_0_[0] ;
  wire \cal1_state_r1_reg_n_0_[1] ;
  wire \cal1_state_r1_reg_n_0_[2] ;
  wire \cal1_state_r1_reg_n_0_[3] ;
  wire \cal1_state_r1_reg_n_0_[4] ;
  wire \cal1_state_r1_reg_n_0_[5] ;
  wire cal1_wait_cnt_en_r;
  wire cal1_wait_cnt_en_r0;
  wire cal1_wait_cnt_en_r_i_2_n_0;
  wire cal1_wait_cnt_en_r_i_3_n_0;
  wire \cal1_wait_cnt_r[4]_i_1_n_0 ;
  wire [4:0]cal1_wait_cnt_r_reg;
  wire cal1_wait_r;
  wire cal1_wait_r_i_1_n_0;
  wire [5:0]cnt_idel_dec_cpt_r;
  wire [4:0]cnt_idel_dec_cpt_r1;
  wire \cnt_idel_dec_cpt_r[0]_i_2_n_0 ;
  wire \cnt_idel_dec_cpt_r[0]_i_3_n_0 ;
  wire \cnt_idel_dec_cpt_r[1]_i_2_n_0 ;
  wire \cnt_idel_dec_cpt_r[1]_i_3_n_0 ;
  wire \cnt_idel_dec_cpt_r[1]_i_4_n_0 ;
  wire \cnt_idel_dec_cpt_r[2]_i_11_n_0 ;
  wire \cnt_idel_dec_cpt_r[2]_i_12_n_0 ;
  wire \cnt_idel_dec_cpt_r[2]_i_13_n_0 ;
  wire \cnt_idel_dec_cpt_r[2]_i_14_n_0 ;
  wire \cnt_idel_dec_cpt_r[2]_i_15_n_0 ;
  wire \cnt_idel_dec_cpt_r[2]_i_3_n_0 ;
  wire \cnt_idel_dec_cpt_r[2]_i_4_n_0 ;
  wire \cnt_idel_dec_cpt_r[2]_i_5_n_0 ;
  wire \cnt_idel_dec_cpt_r[2]_i_6_n_0 ;
  wire \cnt_idel_dec_cpt_r[2]_i_7_n_0 ;
  wire \cnt_idel_dec_cpt_r[2]_i_8_n_0 ;
  wire \cnt_idel_dec_cpt_r[2]_i_9_n_0 ;
  wire \cnt_idel_dec_cpt_r[3]_i_2_n_0 ;
  wire \cnt_idel_dec_cpt_r[3]_i_3_n_0 ;
  wire \cnt_idel_dec_cpt_r[3]_i_4_n_0 ;
  wire \cnt_idel_dec_cpt_r[3]_i_5_n_0 ;
  wire \cnt_idel_dec_cpt_r[4]_i_10_n_0 ;
  wire \cnt_idel_dec_cpt_r[4]_i_11_n_0 ;
  wire \cnt_idel_dec_cpt_r[4]_i_12_n_0 ;
  wire \cnt_idel_dec_cpt_r[4]_i_13_n_0 ;
  wire \cnt_idel_dec_cpt_r[4]_i_14_n_0 ;
  wire \cnt_idel_dec_cpt_r[4]_i_3_n_0 ;
  wire \cnt_idel_dec_cpt_r[4]_i_4_n_0 ;
  wire \cnt_idel_dec_cpt_r[4]_i_5_n_0 ;
  wire \cnt_idel_dec_cpt_r[4]_i_6_n_0 ;
  wire \cnt_idel_dec_cpt_r[4]_i_7_n_0 ;
  wire \cnt_idel_dec_cpt_r[4]_i_9_n_0 ;
  wire \cnt_idel_dec_cpt_r[5]_i_1_n_0 ;
  wire \cnt_idel_dec_cpt_r[5]_i_3_n_0 ;
  wire \cnt_idel_dec_cpt_r[5]_i_4_n_0 ;
  wire \cnt_idel_dec_cpt_r[5]_i_5_n_0 ;
  wire \cnt_idel_dec_cpt_r[5]_i_6_n_0 ;
  wire \cnt_idel_dec_cpt_r_reg[2]_i_10_n_0 ;
  wire \cnt_idel_dec_cpt_r_reg[2]_i_10_n_1 ;
  wire \cnt_idel_dec_cpt_r_reg[2]_i_10_n_2 ;
  wire \cnt_idel_dec_cpt_r_reg[2]_i_10_n_3 ;
  wire \cnt_idel_dec_cpt_r_reg[2]_i_10_n_4 ;
  wire \cnt_idel_dec_cpt_r_reg[2]_i_10_n_5 ;
  wire \cnt_idel_dec_cpt_r_reg[2]_i_10_n_6 ;
  wire \cnt_idel_dec_cpt_r_reg[2]_i_2_n_0 ;
  wire \cnt_idel_dec_cpt_r_reg[2]_i_2_n_1 ;
  wire \cnt_idel_dec_cpt_r_reg[2]_i_2_n_2 ;
  wire \cnt_idel_dec_cpt_r_reg[2]_i_2_n_3 ;
  wire \cnt_idel_dec_cpt_r_reg[4]_i_2_n_1 ;
  wire \cnt_idel_dec_cpt_r_reg[4]_i_2_n_3 ;
  wire \cnt_idel_dec_cpt_r_reg[4]_i_8_n_3 ;
  wire \cnt_idel_dec_cpt_r_reg[4]_i_8_n_6 ;
  wire \cnt_idel_dec_cpt_r_reg[4]_i_8_n_7 ;
  wire \cnt_idel_dec_cpt_r_reg_n_0_[0] ;
  wire \cnt_idel_dec_cpt_r_reg_n_0_[1] ;
  wire \cnt_idel_dec_cpt_r_reg_n_0_[2] ;
  wire \cnt_idel_dec_cpt_r_reg_n_0_[3] ;
  wire \cnt_idel_dec_cpt_r_reg_n_0_[4] ;
  wire \cnt_idel_dec_cpt_r_reg_n_0_[5] ;
  wire [3:0]cnt_shift_r_reg;
  wire [0:0]\cnt_shift_r_reg[0]_0 ;
  wire detect_edge_done_r;
  wire detect_edge_done_r_i_1_n_0;
  wire detect_edge_done_r_i_2_n_0;
  wire [3:0]done_cnt;
  wire done_cnt1;
  wire \done_cnt[0]_i_1_n_0 ;
  wire \done_cnt[1]_i_1_n_0 ;
  wire \done_cnt[2]_i_1_n_0 ;
  wire \done_cnt[3]_i_1_n_0 ;
  wire \done_cnt_reg[2]_0 ;
  wire dqs_found_prech_req;
  wire dqs_po_dec_done;
  wire dqs_po_dec_done_r1;
  wire dqs_po_dec_done_r2;
  wire fine_dly_dec_done_r1;
  wire fine_dly_dec_done_r1_i_1_n_0;
  wire fine_dly_dec_done_r1_i_2_n_0;
  wire fine_dly_dec_done_r2;
  wire \first_edge_taps_r[5]_i_1_n_0 ;
  wire \first_edge_taps_r[5]_i_2_n_0 ;
  wire \first_edge_taps_r[5]_i_3_n_0 ;
  wire \first_edge_taps_r_reg_n_0_[0] ;
  wire \first_edge_taps_r_reg_n_0_[1] ;
  wire \first_edge_taps_r_reg_n_0_[2] ;
  wire \first_edge_taps_r_reg_n_0_[3] ;
  wire \first_edge_taps_r_reg_n_0_[4] ;
  wire \first_edge_taps_r_reg_n_0_[5] ;
  wire found_edge_r_i_1_n_0;
  wire found_edge_r_i_2_n_0;
  wire found_edge_r_reg_n_0;
  wire found_first_edge_r_i_1_n_0;
  wire found_first_edge_r_reg_n_0;
  wire found_second_edge_r_i_1_n_0;
  wire found_second_edge_r_reg_0;
  wire found_second_edge_r_reg_n_0;
  wire found_stable_eye_last_r;
  wire found_stable_eye_last_r_i_1_n_0;
  wire found_stable_eye_r_i_1_n_0;
  wire found_stable_eye_r_i_2_n_0;
  wire found_stable_eye_r_reg_n_0;
  wire \gen_byte_sel_div2.byte_sel_cnt_reg[0] ;
  wire \gen_byte_sel_div2.byte_sel_cnt_reg[0]_0 ;
  wire \gen_byte_sel_div2.byte_sel_cnt_reg[1] ;
  wire \gen_byte_sel_div2.byte_sel_cnt_reg[1]_0 ;
  wire \gen_byte_sel_div2.byte_sel_cnt_reg[2] ;
  wire \gen_byte_sel_div2.byte_sel_cnt_reg[2]_0 ;
  wire \gen_byte_sel_div2.byte_sel_cnt_reg[3] ;
  wire \gen_byte_sel_div2.byte_sel_cnt_reg[3]_0 ;
  wire [0:0]\gen_byte_sel_div2.byte_sel_cnt_reg[3]_1 ;
  wire \gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0 ;
  wire \gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0] ;
  wire \gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0 ;
  wire \gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0] ;
  wire \gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0 ;
  wire \gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0] ;
  wire \gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0 ;
  wire \gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0] ;
  wire \gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ;
  wire \gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0] ;
  wire \gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0 ;
  wire \gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0] ;
  wire \gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0 ;
  wire \gen_mux_rd[0].mux_rd_rise2_r_reg_n_0_[0] ;
  wire \gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0 ;
  wire \gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0] ;
  wire \gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_fall0_r_reg_n_0_[1] ;
  wire \gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_fall1_r_reg_n_0_[1] ;
  wire \gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_fall2_r_reg_n_0_[1] ;
  wire \gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_fall3_r_reg_n_0_[1] ;
  wire \gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_rise0_r_reg_n_0_[1] ;
  wire \gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_rise1_r_reg_n_0_[1] ;
  wire \gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_rise2_r_reg_n_0_[1] ;
  wire \gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ;
  wire \gen_mux_rd[1].mux_rd_rise3_r_reg_n_0_[1] ;
  wire \gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0 ;
  wire \gen_mux_rd[2].mux_rd_fall0_r_reg_n_0_[2] ;
  wire \gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0 ;
  wire \gen_mux_rd[2].mux_rd_fall1_r_reg_n_0_[2] ;
  wire \gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0 ;
  wire \gen_mux_rd[2].mux_rd_fall2_r_reg_n_0_[2] ;
  wire \gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 ;
  wire \gen_mux_rd[2].mux_rd_fall3_r_reg_n_0_[2] ;
  wire \gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ;
  wire \gen_mux_rd[2].mux_rd_rise0_r_reg_n_0_[2] ;
  wire \gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0 ;
  wire \gen_mux_rd[2].mux_rd_rise1_r_reg_n_0_[2] ;
  wire \gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0 ;
  wire \gen_mux_rd[2].mux_rd_rise2_r_reg_n_0_[2] ;
  wire \gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0 ;
  wire \gen_mux_rd[2].mux_rd_rise3_r_reg_n_0_[2] ;
  wire \gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_fall0_r_reg_n_0_[3] ;
  wire \gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_fall1_r_reg_n_0_[3] ;
  wire \gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_fall2_r_reg_n_0_[3] ;
  wire \gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_fall3_r_reg_n_0_[3] ;
  wire \gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_rise0_r_reg_n_0_[3] ;
  wire \gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_rise1_r_reg_n_0_[3] ;
  wire \gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_rise2_r_reg_n_0_[3] ;
  wire \gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ;
  wire \gen_mux_rd[3].mux_rd_rise3_r_reg_n_0_[3] ;
  wire \gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0 ;
  wire \gen_mux_rd[4].mux_rd_fall0_r_reg_n_0_[4] ;
  wire \gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0 ;
  wire \gen_mux_rd[4].mux_rd_fall1_r_reg_n_0_[4] ;
  wire \gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0 ;
  wire \gen_mux_rd[4].mux_rd_fall2_r_reg_n_0_[4] ;
  wire \gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0 ;
  wire \gen_mux_rd[4].mux_rd_fall3_r_reg_n_0_[4] ;
  wire \gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0 ;
  wire \gen_mux_rd[4].mux_rd_rise0_r_reg_n_0_[4] ;
  wire \gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0 ;
  wire \gen_mux_rd[4].mux_rd_rise1_r_reg_n_0_[4] ;
  wire \gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0 ;
  wire \gen_mux_rd[4].mux_rd_rise2_r_reg_n_0_[4] ;
  wire \gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0 ;
  wire \gen_mux_rd[4].mux_rd_rise3_r_reg_n_0_[4] ;
  wire \gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_fall0_r_reg_n_0_[5] ;
  wire \gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_fall1_r_reg_n_0_[5] ;
  wire \gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_fall2_r_reg_n_0_[5] ;
  wire \gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_fall3_r_reg_n_0_[5] ;
  wire \gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_rise0_r_reg_n_0_[5] ;
  wire \gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_rise1_r_reg_n_0_[5] ;
  wire \gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_rise2_r_reg_n_0_[5] ;
  wire \gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ;
  wire \gen_mux_rd[5].mux_rd_rise3_r_reg_n_0_[5] ;
  wire \gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0 ;
  wire \gen_mux_rd[6].mux_rd_fall0_r_reg_n_0_[6] ;
  wire \gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0 ;
  wire \gen_mux_rd[6].mux_rd_fall1_r_reg_n_0_[6] ;
  wire \gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0 ;
  wire \gen_mux_rd[6].mux_rd_fall2_r_reg_n_0_[6] ;
  wire \gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0 ;
  wire \gen_mux_rd[6].mux_rd_fall3_r_reg_n_0_[6] ;
  wire \gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0 ;
  wire \gen_mux_rd[6].mux_rd_rise0_r_reg_n_0_[6] ;
  wire \gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0 ;
  wire \gen_mux_rd[6].mux_rd_rise1_r_reg_n_0_[6] ;
  wire \gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0 ;
  wire \gen_mux_rd[6].mux_rd_rise2_r_reg_n_0_[6] ;
  wire \gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0 ;
  wire \gen_mux_rd[6].mux_rd_rise3_r_reg_n_0_[6] ;
  wire \gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_fall0_r_reg_n_0_[7] ;
  wire \gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_fall1_r_reg_n_0_[7] ;
  wire \gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_fall2_r_reg_n_0_[7] ;
  wire \gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_fall3_r_reg_n_0_[7] ;
  wire \gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_rise0_r_reg_n_0_[7] ;
  wire \gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_rise1_r_reg_n_0_[7] ;
  wire \gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_rise2_r_reg_n_0_[7] ;
  wire \gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ;
  wire \gen_mux_rd[7].mux_rd_rise3_r_reg_n_0_[7] ;
  wire \gen_old_sr_div4.gen_old_sr[0].old_sr_fall0_r_reg[0]_191 ;
  wire \gen_old_sr_div4.gen_old_sr[0].old_sr_fall1_r_reg[0]_207 ;
  wire \gen_old_sr_div4.gen_old_sr[0].old_sr_fall2_r_reg[0]_175 ;
  wire \gen_old_sr_div4.gen_old_sr[0].old_sr_fall3_r_reg[0]_183 ;
  wire \gen_old_sr_div4.gen_old_sr[0].old_sr_rise0_r_reg[0]_223 ;
  wire \gen_old_sr_div4.gen_old_sr[0].old_sr_rise1_r_reg[0]_199 ;
  wire \gen_old_sr_div4.gen_old_sr[0].old_sr_rise2_r_reg[0]_215 ;
  wire \gen_old_sr_div4.gen_old_sr[0].old_sr_rise3_r_reg[0]_231 ;
  wire \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall0_r_reg[0]_143 ;
  wire \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall1_r_reg[0]_119 ;
  wire \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall2_r_reg[0]_127 ;
  wire \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall3_r_reg[0]_151 ;
  wire \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise0_r_reg[0]_159 ;
  wire \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise1_r_reg[0]_111 ;
  wire \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise2_r_reg[0]_135 ;
  wire \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise3_r_reg[0]_167 ;
  wire \gen_old_sr_div4.gen_old_sr[1].old_sr_fall0_r_reg[1]_192 ;
  wire \gen_old_sr_div4.gen_old_sr[1].old_sr_fall1_r_reg[1]_208 ;
  wire \gen_old_sr_div4.gen_old_sr[1].old_sr_fall2_r_reg[1]_176 ;
  wire \gen_old_sr_div4.gen_old_sr[1].old_sr_fall3_r_reg[1]_184 ;
  wire \gen_old_sr_div4.gen_old_sr[1].old_sr_rise0_r_reg[1]_224 ;
  wire \gen_old_sr_div4.gen_old_sr[1].old_sr_rise1_r_reg[1]_200 ;
  wire \gen_old_sr_div4.gen_old_sr[1].old_sr_rise2_r_reg[1]_216 ;
  wire \gen_old_sr_div4.gen_old_sr[1].old_sr_rise3_r_reg[1]_232 ;
  wire \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall0_r_reg[1]_144 ;
  wire \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall1_r_reg[1]_120 ;
  wire \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall2_r_reg[1]_128 ;
  wire \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall3_r_reg[1]_152 ;
  wire \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise0_r_reg[1]_160 ;
  wire \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise1_r_reg[1]_112 ;
  wire \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise2_r_reg[1]_136 ;
  wire \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise3_r_reg[1]_168 ;
  wire \gen_old_sr_div4.gen_old_sr[2].old_sr_fall0_r_reg[2]_193 ;
  wire \gen_old_sr_div4.gen_old_sr[2].old_sr_fall1_r_reg[2]_209 ;
  wire \gen_old_sr_div4.gen_old_sr[2].old_sr_fall2_r_reg[2]_177 ;
  wire \gen_old_sr_div4.gen_old_sr[2].old_sr_fall3_r_reg[2]_185 ;
  wire \gen_old_sr_div4.gen_old_sr[2].old_sr_rise0_r_reg[2]_225 ;
  wire \gen_old_sr_div4.gen_old_sr[2].old_sr_rise1_r_reg[2]_201 ;
  wire \gen_old_sr_div4.gen_old_sr[2].old_sr_rise2_r_reg[2]_217 ;
  wire \gen_old_sr_div4.gen_old_sr[2].old_sr_rise3_r_reg[2]_233 ;
  wire \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall0_r_reg[2]_145 ;
  wire \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall1_r_reg[2]_121 ;
  wire \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall2_r_reg[2]_129 ;
  wire \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall3_r_reg[2]_153 ;
  wire \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise0_r_reg[2]_161 ;
  wire \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise1_r_reg[2]_113 ;
  wire \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise2_r_reg[2]_137 ;
  wire \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise3_r_reg[2]_169 ;
  wire \gen_old_sr_div4.gen_old_sr[3].old_sr_fall0_r_reg[3]_194 ;
  wire \gen_old_sr_div4.gen_old_sr[3].old_sr_fall1_r_reg[3]_210 ;
  wire \gen_old_sr_div4.gen_old_sr[3].old_sr_fall2_r_reg[3]_178 ;
  wire \gen_old_sr_div4.gen_old_sr[3].old_sr_fall3_r_reg[3]_186 ;
  wire \gen_old_sr_div4.gen_old_sr[3].old_sr_rise0_r_reg[3]_226 ;
  wire \gen_old_sr_div4.gen_old_sr[3].old_sr_rise1_r_reg[3]_202 ;
  wire \gen_old_sr_div4.gen_old_sr[3].old_sr_rise2_r_reg[3]_218 ;
  wire \gen_old_sr_div4.gen_old_sr[3].old_sr_rise3_r_reg[3]_234 ;
  wire \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall0_r_reg[3]_146 ;
  wire \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall1_r_reg[3]_122 ;
  wire \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall2_r_reg[3]_130 ;
  wire \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall3_r_reg[3]_154 ;
  wire \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise0_r_reg[3]_162 ;
  wire \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise1_r_reg[3]_114 ;
  wire \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise2_r_reg[3]_138 ;
  wire \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise3_r_reg[3]_170 ;
  wire \gen_old_sr_div4.gen_old_sr[4].old_sr_fall0_r_reg[4]_195 ;
  wire \gen_old_sr_div4.gen_old_sr[4].old_sr_fall1_r_reg[4]_211 ;
  wire \gen_old_sr_div4.gen_old_sr[4].old_sr_fall2_r_reg[4]_179 ;
  wire \gen_old_sr_div4.gen_old_sr[4].old_sr_fall3_r_reg[4]_187 ;
  wire \gen_old_sr_div4.gen_old_sr[4].old_sr_rise0_r_reg[4]_227 ;
  wire \gen_old_sr_div4.gen_old_sr[4].old_sr_rise1_r_reg[4]_203 ;
  wire \gen_old_sr_div4.gen_old_sr[4].old_sr_rise2_r_reg[4]_219 ;
  wire \gen_old_sr_div4.gen_old_sr[4].old_sr_rise3_r_reg[4]_235 ;
  wire \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall0_r_reg[4]_147 ;
  wire \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall1_r_reg[4]_123 ;
  wire \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall2_r_reg[4]_131 ;
  wire \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall3_r_reg[4]_155 ;
  wire \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise0_r_reg[4]_163 ;
  wire \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise1_r_reg[4]_115 ;
  wire \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise2_r_reg[4]_139 ;
  wire \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise3_r_reg[4]_171 ;
  wire \gen_old_sr_div4.gen_old_sr[5].old_sr_fall0_r_reg[5]_196 ;
  wire \gen_old_sr_div4.gen_old_sr[5].old_sr_fall1_r_reg[5]_212 ;
  wire \gen_old_sr_div4.gen_old_sr[5].old_sr_fall2_r_reg[5]_180 ;
  wire \gen_old_sr_div4.gen_old_sr[5].old_sr_fall3_r_reg[5]_188 ;
  wire \gen_old_sr_div4.gen_old_sr[5].old_sr_rise0_r_reg[5]_228 ;
  wire \gen_old_sr_div4.gen_old_sr[5].old_sr_rise1_r_reg[5]_204 ;
  wire \gen_old_sr_div4.gen_old_sr[5].old_sr_rise2_r_reg[5]_220 ;
  wire \gen_old_sr_div4.gen_old_sr[5].old_sr_rise3_r_reg[5]_236 ;
  wire \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall0_r_reg[5]_148 ;
  wire \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall1_r_reg[5]_124 ;
  wire \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall2_r_reg[5]_132 ;
  wire \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall3_r_reg[5]_156 ;
  wire \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise0_r_reg[5]_164 ;
  wire \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise1_r_reg[5]_116 ;
  wire \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise2_r_reg[5]_140 ;
  wire \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise3_r_reg[5]_172 ;
  wire \gen_old_sr_div4.gen_old_sr[6].old_sr_fall0_r_reg[6]_197 ;
  wire \gen_old_sr_div4.gen_old_sr[6].old_sr_fall1_r_reg[6]_213 ;
  wire \gen_old_sr_div4.gen_old_sr[6].old_sr_fall2_r_reg[6]_181 ;
  wire \gen_old_sr_div4.gen_old_sr[6].old_sr_fall3_r_reg[6]_189 ;
  wire \gen_old_sr_div4.gen_old_sr[6].old_sr_rise0_r_reg[6]_229 ;
  wire \gen_old_sr_div4.gen_old_sr[6].old_sr_rise1_r_reg[6]_205 ;
  wire \gen_old_sr_div4.gen_old_sr[6].old_sr_rise2_r_reg[6]_221 ;
  wire \gen_old_sr_div4.gen_old_sr[6].old_sr_rise3_r_reg[6]_237 ;
  wire \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall0_r_reg[6]_149 ;
  wire \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall1_r_reg[6]_125 ;
  wire \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall2_r_reg[6]_133 ;
  wire \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall3_r_reg[6]_157 ;
  wire \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise0_r_reg[6]_165 ;
  wire \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise1_r_reg[6]_117 ;
  wire \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise2_r_reg[6]_141 ;
  wire \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise3_r_reg[6]_173 ;
  wire \gen_old_sr_div4.gen_old_sr[7].old_sr_fall0_r_reg[7]_198 ;
  wire \gen_old_sr_div4.gen_old_sr[7].old_sr_fall1_r_reg[7]_214 ;
  wire \gen_old_sr_div4.gen_old_sr[7].old_sr_fall2_r_reg[7]_182 ;
  wire \gen_old_sr_div4.gen_old_sr[7].old_sr_fall3_r_reg[7]_190 ;
  wire \gen_old_sr_div4.gen_old_sr[7].old_sr_rise0_r_reg[7]_230 ;
  wire \gen_old_sr_div4.gen_old_sr[7].old_sr_rise1_r_reg[7]_206 ;
  wire \gen_old_sr_div4.gen_old_sr[7].old_sr_rise2_r_reg[7]_222 ;
  wire \gen_old_sr_div4.gen_old_sr[7].old_sr_rise3_r_reg[7]_238 ;
  wire \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall0_r_reg[7]_150 ;
  wire \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall1_r_reg[7]_126 ;
  wire \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall2_r_reg[7]_134 ;
  wire \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall3_r_reg[7]_158 ;
  wire \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise0_r_reg[7]_166 ;
  wire \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise1_r_reg[7]_118 ;
  wire \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise2_r_reg[7]_142 ;
  wire \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise3_r_reg[7]_174 ;
  wire \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall0_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r[0]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r[0]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r[0]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise2_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise3_r[0]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r[0]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r[0]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r[0]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[0].pat0_match_fall0_r[0]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[0].pat1_match_fall2_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r[1]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall2_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall3_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r[1]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r[1]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r[1]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r[1]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall1_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r[1]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r[1]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[1].pat0_match_rise1_r[1]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall1_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r[2]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r[2]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r[2]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r[2]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r[2]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise1_r[2]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise2_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r[2]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[2].pat0_match_fall1_r[2]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[2].pat1_match_fall3_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r[3]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r[3]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall3_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r[3]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise2_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise3_r[3]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r[3]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall2_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r[3]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r[3]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[3].pat0_match_rise2_r[3]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[3].pat1_match_rise0_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall0_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r[4]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r[4]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r[4]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise2_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise3_r[4]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r[4]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r[4]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r[4]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[4].pat0_match_fall0_r[4]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[4].pat1_match_fall2_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r[5]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall2_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall3_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r[5]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r[5]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r[5]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r[5]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall1_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r[5]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r[5]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[5].pat0_match_rise1_r[5]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall1_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r[6]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r[6]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r[6]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r[6]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r[6]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise1_r[6]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise2_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r[6]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[6].pat0_match_fall1_r[6]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[6].pat1_match_fall3_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r[7]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r[7]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall3_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r[7]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise2_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise3_r[7]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r[7]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall2_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r[7]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r[7]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[7].pat0_match_rise2_r[7]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[7].pat1_match_rise0_r_reg ;
  wire \gen_pat_match_div4.idel_pat0_data_match_r_i_2_n_0 ;
  wire \gen_pat_match_div4.idel_pat0_data_match_r_reg_n_0 ;
  wire \gen_pat_match_div4.idel_pat0_match_fall0_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.idel_pat0_match_fall1_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.idel_pat0_match_rise0_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.idel_pat0_match_rise1_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.idel_pat0_match_rise3_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.idel_pat1_data_match_r_i_2_n_0 ;
  wire \gen_pat_match_div4.idel_pat1_data_match_r_reg_n_0 ;
  wire \gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.idel_pat1_match_fall2_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.idel_pat1_match_fall3_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.idel_pat1_match_rise0_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.idel_pat1_match_rise1_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.idel_pat1_match_rise2_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.idel_pat1_match_rise3_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.pat0_data_match_r_i_2_n_0 ;
  wire \gen_pat_match_div4.pat0_data_match_r_reg_n_0 ;
  wire \gen_pat_match_div4.pat0_match_fall0_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.pat0_match_fall0_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.pat0_match_fall1_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.pat0_match_fall1_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.pat0_match_fall2_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.pat0_match_fall2_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.pat0_match_fall3_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.pat0_match_fall3_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.pat0_match_rise0_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.pat0_match_rise0_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.pat0_match_rise1_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.pat0_match_rise1_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.pat0_match_rise2_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.pat0_match_rise2_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.pat0_match_rise3_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.pat0_match_rise3_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.pat1_data_match_r_i_2_n_0 ;
  wire \gen_pat_match_div4.pat1_data_match_r_reg_n_0 ;
  wire \gen_pat_match_div4.pat1_match_fall0_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.pat1_match_fall0_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.pat1_match_fall1_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.pat1_match_fall1_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.pat1_match_fall2_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.pat1_match_fall2_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.pat1_match_fall3_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.pat1_match_fall3_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.pat1_match_rise0_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.pat1_match_rise0_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.pat1_match_rise1_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.pat1_match_rise1_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.pat1_match_rise2_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.pat1_match_rise2_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.pat1_match_rise3_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.pat1_match_rise3_and_r_i_2_n_0 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_95 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_71 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_79 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_55 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_47 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_87 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_63 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_103 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_96 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_72 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_80 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_56 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_48 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_88 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_64 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_104 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_97 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_73 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_81 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_57 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_49 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_89 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_65 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_105 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_98 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_74 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_82 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_58 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_50 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_90 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_66 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_106 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_99 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_75 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_83 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_59 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_51 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_91 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_67 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_107 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_100 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_76 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_84 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_60 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_52 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_92 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_68 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_108 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_101 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_77 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_85 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_61 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_53 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_93 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_69 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_109 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_102 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_78 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_86 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_62 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_54 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_94 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_70 ;
  wire \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_110 ;
  wire \gen_sr_match_div4.gen_sr_match[0].old_sr_diff_r_reg_n_0_[0] ;
  wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r[0]_inv_i_2_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r_reg[0]_inv_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r[0]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r_reg_n_0_[0] ;
  wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r[0]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r_reg_n_0_[0] ;
  wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r[0]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r_reg_n_0_[0] ;
  wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r[0]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r_reg_n_0_[0] ;
  wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r[0]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r_reg_n_0_[0] ;
  wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r[0]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r_reg_n_0_[0] ;
  wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r[0]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r_reg_n_0_[0] ;
  wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r[0]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r_reg_n_0_[0] ;
  wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg_n_0_[0] ;
  wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r[0]_inv_i_2_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r_reg[0]_inv_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r_reg_n_0_[0] ;
  wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r[0]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r_reg_n_0_[0] ;
  wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r[0]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r_reg_n_0_[0] ;
  wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r[0]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r_reg_n_0_[0] ;
  wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r[0]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r_reg_n_0_[0] ;
  wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r[0]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r_reg_n_0_[0] ;
  wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r[0]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r_reg_n_0_[0] ;
  wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r[0]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r_reg_n_0_[0] ;
  wire \gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r[1]_inv_i_2_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r_reg[1]_inv_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall0_r[1]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall1_r[1]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall2_r[1]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall3_r[1]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise0_r[1]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise1_r[1]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise2_r[1]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise3_r[1]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r[1]_inv_i_2_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r_reg[1]_inv_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall0_r[1]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall1_r[1]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall2_r[1]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall3_r[1]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise0_r[1]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise1_r[1]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise2_r[1]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise3_r[1]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r[2]_inv_i_2_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r_reg[2]_inv_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall0_r[2]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall1_r[2]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall2_r[2]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall3_r[2]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise0_r[2]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise1_r[2]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise2_r[2]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise3_r[2]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r[2]_inv_i_2_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r_reg[2]_inv_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall0_r[2]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall1_r[2]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall2_r[2]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall3_r[2]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise0_r[2]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise1_r[2]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise2_r[2]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise3_r[2]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r[3]_inv_i_2_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r_reg[3]_inv_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall0_r[3]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall1_r[3]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall2_r[3]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall3_r[3]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise0_r[3]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise1_r[3]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise2_r[3]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise3_r[3]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r[3]_inv_i_2_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r_reg[3]_inv_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall0_r[3]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall1_r[3]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall2_r[3]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall3_r[3]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise0_r[3]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise1_r[3]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise2_r[3]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise3_r[3]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r[4]_inv_i_2_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r_reg[4]_inv_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall0_r[4]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall1_r[4]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall2_r[4]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall3_r[4]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise0_r[4]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise1_r[4]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise2_r[4]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise3_r[4]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r[4]_inv_i_2_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r_reg[4]_inv_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall0_r[4]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall1_r[4]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall2_r[4]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall3_r[4]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise0_r[4]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise1_r[4]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise2_r[4]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise3_r[4]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r[5]_inv_i_2_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r_reg[5]_inv_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall0_r[5]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall1_r[5]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall2_r[5]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall3_r[5]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise0_r[5]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise1_r[5]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise2_r[5]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise3_r[5]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r[5]_inv_i_2_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r_reg[5]_inv_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall0_r[5]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall1_r[5]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall2_r[5]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall3_r[5]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise0_r[5]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise1_r[5]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise2_r[5]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise3_r[5]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r[6]_inv_i_2_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r_reg[6]_inv_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall0_r[6]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall1_r[6]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall2_r[6]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall3_r[6]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise0_r[6]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise1_r[6]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise2_r[6]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise3_r[6]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r[6]_inv_i_2_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r_reg[6]_inv_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall0_r[6]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall1_r[6]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall2_r[6]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall3_r[6]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise0_r[6]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise1_r[6]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise2_r[6]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise3_r[6]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[7].old_sr_diff_r_reg_n_0_[7] ;
  wire \gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r[7]_inv_i_2_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r_reg[7]_inv_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall0_r[7]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall1_r[7]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall2_r[7]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall2_r_reg_n_0_[7] ;
  wire \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall3_r[7]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise0_r[7]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r[7]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r_reg_n_0_[7] ;
  wire \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r[7]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r_reg_n_0_[7] ;
  wire \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r[7]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[7].prev_sr_diff_r_reg_n_0_[7] ;
  wire \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r[7]_inv_i_2_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r_reg[7]_inv_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall0_r[7]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall1_r[7]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall2_r[7]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall3_r[7]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise0_r[7]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise1_r[7]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise2_r[7]_i_1_n_0 ;
  wire \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise3_r[7]_i_1_n_0 ;
  wire \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0 ;
  wire \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_4_n_0 ;
  wire \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0 ;
  wire [4:0]\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_239 ;
  wire \gen_track_left_edge[0].pb_detect_edge_done_r[0]_i_1_n_0 ;
  wire \gen_track_left_edge[0].pb_found_edge_r[0]_i_1_n_0 ;
  wire \gen_track_left_edge[0].pb_found_edge_r[0]_i_2_n_0 ;
  wire \gen_track_left_edge[0].pb_found_edge_r_reg_n_0_[0] ;
  wire \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_1_n_0 ;
  wire \gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_1_n_0 ;
  wire \gen_track_left_edge[0].pb_last_tap_jitter_r_reg_n_0_[0] ;
  wire \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0 ;
  wire \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0 ;
  wire \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_4_n_0 ;
  wire \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_5_n_0 ;
  wire [4:0]\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_240 ;
  wire \gen_track_left_edge[1].pb_detect_edge_done_r[1]_i_1_n_0 ;
  wire \gen_track_left_edge[1].pb_found_edge_r[1]_i_1_n_0 ;
  wire \gen_track_left_edge[1].pb_found_edge_r[1]_i_2_n_0 ;
  wire \gen_track_left_edge[1].pb_found_edge_r_reg_n_0_[1] ;
  wire \gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_1_n_0 ;
  wire \gen_track_left_edge[1].pb_last_tap_jitter_r[1]_i_1_n_0 ;
  wire \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0 ;
  wire \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0 ;
  wire \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_4_n_0 ;
  wire \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_5_n_0 ;
  wire [4:0]\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_241 ;
  wire \gen_track_left_edge[2].pb_detect_edge_done_r[2]_i_1_n_0 ;
  wire \gen_track_left_edge[2].pb_found_edge_r[2]_i_1_n_0 ;
  wire \gen_track_left_edge[2].pb_found_edge_r[2]_i_2_n_0 ;
  wire \gen_track_left_edge[2].pb_found_edge_r_reg_n_0_[2] ;
  wire \gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_1_n_0 ;
  wire \gen_track_left_edge[2].pb_last_tap_jitter_r[2]_i_1_n_0 ;
  wire \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0 ;
  wire \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0 ;
  wire \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_4_n_0 ;
  wire \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_5_n_0 ;
  wire [4:0]\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_242 ;
  wire \gen_track_left_edge[3].pb_detect_edge_done_r[3]_i_1_n_0 ;
  wire \gen_track_left_edge[3].pb_found_edge_r[3]_i_1_n_0 ;
  wire \gen_track_left_edge[3].pb_found_edge_r[3]_i_2_n_0 ;
  wire \gen_track_left_edge[3].pb_found_edge_r_reg_n_0_[3] ;
  wire \gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_1_n_0 ;
  wire \gen_track_left_edge[3].pb_last_tap_jitter_r[3]_i_1_n_0 ;
  wire \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0 ;
  wire \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0 ;
  wire \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_4_n_0 ;
  wire \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_5_n_0 ;
  wire [4:0]\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_243 ;
  wire \gen_track_left_edge[4].pb_detect_edge_done_r[4]_i_1_n_0 ;
  wire \gen_track_left_edge[4].pb_found_edge_r[4]_i_1_n_0 ;
  wire \gen_track_left_edge[4].pb_found_edge_r[4]_i_2_n_0 ;
  wire \gen_track_left_edge[4].pb_found_edge_r_reg_n_0_[4] ;
  wire \gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_1_n_0 ;
  wire \gen_track_left_edge[4].pb_last_tap_jitter_r[4]_i_1_n_0 ;
  wire \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0 ;
  wire \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0 ;
  wire \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_4_n_0 ;
  wire \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_5_n_0 ;
  wire [4:0]\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_244 ;
  wire \gen_track_left_edge[5].pb_detect_edge_done_r[5]_i_1_n_0 ;
  wire \gen_track_left_edge[5].pb_found_edge_r[5]_i_1_n_0 ;
  wire \gen_track_left_edge[5].pb_found_edge_r[5]_i_2_n_0 ;
  wire \gen_track_left_edge[5].pb_found_edge_r_reg_n_0_[5] ;
  wire \gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_1_n_0 ;
  wire \gen_track_left_edge[5].pb_last_tap_jitter_r[5]_i_1_n_0 ;
  wire \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0 ;
  wire \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0 ;
  wire \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_4_n_0 ;
  wire \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_5_n_0 ;
  wire [4:0]\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_245 ;
  wire \gen_track_left_edge[6].pb_detect_edge_done_r[6]_i_1_n_0 ;
  wire \gen_track_left_edge[6].pb_found_edge_r[6]_i_1_n_0 ;
  wire \gen_track_left_edge[6].pb_found_edge_r[6]_i_2_n_0 ;
  wire \gen_track_left_edge[6].pb_found_edge_r_reg_n_0_[6] ;
  wire \gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_1_n_0 ;
  wire \gen_track_left_edge[6].pb_last_tap_jitter_r[6]_i_1_n_0 ;
  wire \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0 ;
  wire \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0 ;
  wire \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_4_n_0 ;
  wire \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_5_n_0 ;
  wire [4:0]\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_246 ;
  wire \gen_track_left_edge[7].pb_detect_edge_done_r[7]_i_1_n_0 ;
  wire \gen_track_left_edge[7].pb_found_edge_r[7]_i_1_n_0 ;
  wire \gen_track_left_edge[7].pb_found_edge_r[7]_i_2_n_0 ;
  wire \gen_track_left_edge[7].pb_found_edge_r_reg_n_0_[7] ;
  wire \gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_1_n_0 ;
  wire \gen_track_left_edge[7].pb_last_tap_jitter_r[7]_i_1_n_0 ;
  wire idel_adj_inc_i_1_n_0;
  wire idel_adj_inc_reg_n_0;
  wire [4:0]idel_dec_cnt;
  wire \idel_dec_cnt[3]_i_2_n_0 ;
  wire \idel_dec_cnt[4]_i_1_n_0 ;
  wire \idel_dec_cnt[4]_i_3_n_0 ;
  wire \idel_dec_cnt[4]_i_4_n_0 ;
  wire \idel_dec_cnt[4]_i_5_n_0 ;
  wire \idel_dec_cnt_reg_n_0_[0] ;
  wire \idel_dec_cnt_reg_n_0_[1] ;
  wire \idel_dec_cnt_reg_n_0_[2] ;
  wire \idel_dec_cnt_reg_n_0_[3] ;
  wire \idel_dec_cnt_reg_n_0_[4] ;
  wire idel_mpr_pat_detect_r;
  wire idel_pat0_data_match_r0;
  wire idel_pat0_match_fall0_and_r;
  wire idel_pat0_match_fall1_and_r;
  wire idel_pat0_match_fall2_and_r;
  wire idel_pat0_match_fall3_and_r;
  wire idel_pat0_match_rise0_and_r;
  wire idel_pat0_match_rise1_and_r;
  wire idel_pat0_match_rise2_and_r;
  wire idel_pat0_match_rise3_and_r;
  wire [7:0]idel_pat0_match_rise3_r;
  wire idel_pat1_data_match_r0;
  wire idel_pat1_match_fall0_and_r;
  wire idel_pat1_match_fall1_and_r;
  wire idel_pat1_match_fall2_and_r;
  wire idel_pat1_match_fall3_and_r;
  wire idel_pat1_match_rise0_and_r;
  wire idel_pat1_match_rise1_and_r;
  wire [7:0]idel_pat1_match_rise1_r;
  wire idel_pat1_match_rise2_and_r;
  wire idel_pat1_match_rise3_and_r;
  wire idel_pat_detect_valid_r_i_1_n_0;
  wire idel_pat_detect_valid_r_reg_n_0;
  wire idelay_ce_int;
  wire idelay_inc_int;
  wire [4:0]idelay_tap_cnt_r;
  wire \idelay_tap_cnt_r[0][0][0]_i_1_n_0 ;
  wire \idelay_tap_cnt_r[0][0][1]_i_1_n_0 ;
  wire \idelay_tap_cnt_r[0][0][2]_i_1_n_0 ;
  wire \idelay_tap_cnt_r[0][0][3]_i_1_n_0 ;
  wire \idelay_tap_cnt_r[0][0][3]_i_2_n_0 ;
  wire \idelay_tap_cnt_r[0][0][4]_i_2_n_0 ;
  wire \idelay_tap_cnt_r[0][0][4]_i_6_n_0 ;
  wire [0:0]\idelay_tap_cnt_r_reg[0][0][4]_0 ;
  wire [0:0]\idelay_tap_cnt_r_reg[0][1][4]_0 ;
  wire [0:0]\idelay_tap_cnt_r_reg[0][2][4]_0 ;
  wire [0:0]\idelay_tap_cnt_r_reg[0][3][4]_0 ;
  wire [0:0]\idelay_tap_cnt_r_reg[0][4][4]_0 ;
  wire [0:0]\idelay_tap_cnt_r_reg[0][5][4]_0 ;
  wire [0:0]\idelay_tap_cnt_r_reg[0][6][4]_0 ;
  wire [0:0]\idelay_tap_cnt_r_reg[0][7][4]_0 ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][0][0] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][0][1] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][0][2] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][0][3] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][0][4] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][1][0] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][1][1] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][1][2] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][1][3] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][1][4] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][2][0] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][2][1] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][2][2] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][2][3] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][2][4] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][3][0] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][3][1] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][3][2] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][3][3] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][3][4] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][4][0] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][4][1] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][4][2] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][4][3] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][4][4] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][5][0] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][5][1] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][5][2] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][5][3] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][5][4] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][6][0] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][6][1] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][6][2] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][6][3] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][6][4] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][7][0] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][7][1] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][7][2] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][7][3] ;
  wire \idelay_tap_cnt_r_reg_n_0_[0][7][4] ;
  wire [4:0]idelay_tap_cnt_slice_r;
  wire \idelay_tap_cnt_slice_r[0]_i_2_n_0 ;
  wire \idelay_tap_cnt_slice_r[0]_i_3_n_0 ;
  wire \idelay_tap_cnt_slice_r[1]_i_2_n_0 ;
  wire \idelay_tap_cnt_slice_r[1]_i_3_n_0 ;
  wire \idelay_tap_cnt_slice_r[2]_i_2_n_0 ;
  wire \idelay_tap_cnt_slice_r[2]_i_3_n_0 ;
  wire \idelay_tap_cnt_slice_r[3]_i_2_n_0 ;
  wire \idelay_tap_cnt_slice_r[3]_i_3_n_0 ;
  wire \idelay_tap_cnt_slice_r[4]_i_2_n_0 ;
  wire \idelay_tap_cnt_slice_r[4]_i_3_n_0 ;
  wire idelay_tap_limit_r_i_1_n_0;
  wire idelay_tap_limit_r_i_2_n_0;
  wire idelay_tap_limit_r_reg_n_0;
  wire inhibit_edge_detect_r;
  wire [0:0]\init_state_r[1]_i_16 ;
  wire \mpr_4to1.idel_mpr_pat_detect_r_i_1_n_0 ;
  wire \mpr_4to1.idel_mpr_pat_detect_r_i_2_n_0 ;
  wire \mpr_4to1.idel_mpr_pat_detect_r_i_3_n_0 ;
  wire \mpr_4to1.inhibit_edge_detect_r_i_1_n_0 ;
  wire \mpr_4to1.inhibit_edge_detect_r_i_2_n_0 ;
  wire \mpr_4to1.inhibit_edge_detect_r_i_3_n_0 ;
  wire \mpr_4to1.inhibit_edge_detect_r_i_4_n_0 ;
  wire \mpr_4to1.inhibit_edge_detect_r_i_5_n_0 ;
  wire \mpr_4to1.inhibit_edge_detect_r_i_6_n_0 ;
  wire \mpr_4to1.stable_idel_cnt[0]_i_1_n_0 ;
  wire \mpr_4to1.stable_idel_cnt[1]_i_1_n_0 ;
  wire \mpr_4to1.stable_idel_cnt[2]_i_1_n_0 ;
  wire \mpr_4to1.stable_idel_cnt[2]_i_4_n_0 ;
  wire \mpr_4to1.stable_idel_cnt[2]_i_5_n_0 ;
  wire \mpr_4to1.stable_idel_cnt[2]_i_6_n_0 ;
  wire \mpr_4to1.stable_idel_cnt[2]_i_7_n_0 ;
  wire \mpr_4to1.stable_idel_cnt_reg_n_0_[0] ;
  wire \mpr_4to1.stable_idel_cnt_reg_n_0_[1] ;
  wire \mpr_4to1.stable_idel_cnt_reg_n_0_[2] ;
  wire mpr_dec_cpt_r;
  wire mpr_dec_cpt_r_i_1_n_0;
  wire mpr_dec_cpt_r_reg_n_0;
  wire mpr_rd_fall0_prev_r;
  wire mpr_rd_fall1_prev_r;
  wire mpr_rd_fall2_prev_r;
  wire mpr_rd_fall3_prev_r;
  wire mpr_rd_rise0_prev_r;
  wire mpr_rd_rise0_prev_r0;
  wire mpr_rd_rise1_prev_r;
  wire mpr_rd_rise2_prev_r;
  wire mpr_rd_rise3_prev_r;
  wire mpr_rdlvl_start_r;
  wire mpr_rdlvl_start_r_reg_0;
  wire new_cnt_cpt_r;
  wire new_cnt_cpt_r_i_2_n_0;
  wire new_cnt_cpt_r_reg_0;
  wire p_0_in;
  wire p_0_in100_in;
  wire p_0_in103_in;
  wire p_0_in10_in;
  wire p_0_in135_in;
  wire p_0_in13_in;
  wire p_0_in157_in;
  wire p_0_in16_in;
  wire p_0_in182_in;
  wire p_0_in1_in;
  wire p_0_in207_in;
  wire p_0_in232_in;
  wire p_0_in257_in;
  wire p_0_in282_in;
  wire p_0_in307_in;
  wire p_0_in332_in;
  wire p_0_in357_in;
  wire p_0_in382_in;
  wire p_0_in407_in;
  wire p_0_in432_in;
  wire p_0_in457_in;
  wire p_0_in4_in;
  wire p_0_in541_in;
  wire p_0_in549_in;
  wire p_0_in7_in;
  wire p_0_in88_in;
  wire p_0_in91_in;
  wire p_0_in94_in;
  wire p_0_in97_in;
  wire [5:2]p_0_in__0;
  wire [4:0]p_0_in__1;
  wire [4:0]p_0_in__10;
  wire [3:0]p_0_in__2;
  wire [4:0]p_0_in__3;
  wire [4:0]p_0_in__4;
  wire [4:0]p_0_in__5;
  wire [4:0]p_0_in__6;
  wire [4:0]p_0_in__7;
  wire [4:0]p_0_in__8;
  wire [4:0]p_0_in__9;
  wire p_12_in;
  wire p_139_out;
  wire p_13_in;
  wire p_14_in;
  wire p_165_out;
  wire p_190_out;
  wire p_1_in;
  wire p_1_in11_in;
  wire p_1_in138_in;
  wire p_1_in14_in;
  wire p_1_in164_in;
  wire p_1_in17_in;
  wire p_1_in189_in;
  wire p_1_in214_in;
  wire p_1_in239_in;
  wire p_1_in264_in;
  wire p_1_in26_in;
  wire p_1_in289_in;
  wire p_1_in2_in;
  wire p_1_in314_in;
  wire p_1_in339_in;
  wire p_1_in364_in;
  wire p_1_in389_in;
  wire p_1_in414_in;
  wire p_1_in439_in;
  wire p_1_in464_in;
  wire p_1_in5_in;
  wire p_1_in8_in;
  wire p_215_out;
  wire p_240_out;
  wire p_265_out;
  wire p_27_in;
  wire p_290_out;
  wire p_2_in;
  wire p_2_in158_in;
  wire p_2_in183_in;
  wire p_2_in208_in;
  wire p_2_in233_in;
  wire p_2_in258_in;
  wire p_2_in283_in;
  wire p_2_in308_in;
  wire p_2_in333_in;
  wire p_2_in358_in;
  wire p_2_in383_in;
  wire p_2_in408_in;
  wire p_2_in433_in;
  wire p_2_in458_in;
  wire p_315_out;
  wire p_340_out;
  wire p_34_in;
  wire p_365_out;
  wire p_390_out;
  wire p_3_in136_in;
  wire p_3_in159_in;
  wire p_3_in184_in;
  wire p_3_in209_in;
  wire p_3_in234_in;
  wire p_3_in259_in;
  wire p_3_in284_in;
  wire p_3_in309_in;
  wire p_3_in334_in;
  wire p_3_in359_in;
  wire p_3_in384_in;
  wire p_3_in409_in;
  wire p_3_in434_in;
  wire p_3_in459_in;
  wire p_415_out;
  wire p_440_out;
  wire p_465_out;
  wire p_490_out;
  wire p_4_in160_in;
  wire p_4_in185_in;
  wire p_4_in210_in;
  wire p_4_in235_in;
  wire p_4_in260_in;
  wire p_4_in285_in;
  wire p_4_in310_in;
  wire p_4_in335_in;
  wire p_4_in360_in;
  wire p_4_in385_in;
  wire p_4_in410_in;
  wire p_4_in435_in;
  wire p_4_in460_in;
  wire p_515_out;
  wire p_5_in161_in;
  wire p_5_in186_in;
  wire p_5_in211_in;
  wire p_5_in236_in;
  wire p_5_in261_in;
  wire p_5_in286_in;
  wire p_5_in311_in;
  wire p_5_in336_in;
  wire p_5_in361_in;
  wire p_5_in386_in;
  wire p_5_in411_in;
  wire p_5_in436_in;
  wire p_5_in461_in;
  wire p_6_in137_in;
  wire p_6_in162_in;
  wire p_6_in187_in;
  wire p_6_in212_in;
  wire p_6_in237_in;
  wire p_6_in262_in;
  wire p_6_in287_in;
  wire p_6_in312_in;
  wire p_6_in337_in;
  wire p_6_in362_in;
  wire p_6_in387_in;
  wire p_6_in412_in;
  wire p_6_in437_in;
  wire p_6_in462_in;
  wire p_7_in;
  wire p_7_in163_in;
  wire p_7_in188_in;
  wire p_7_in213_in;
  wire p_7_in238_in;
  wire p_7_in263_in;
  wire p_7_in288_in;
  wire p_7_in313_in;
  wire p_7_in338_in;
  wire p_7_in363_in;
  wire p_7_in388_in;
  wire p_7_in413_in;
  wire p_7_in438_in;
  wire p_7_in463_in;
  wire p_8_in;
  wire p_9_in;
  wire pat0_data_match_r0;
  wire pat0_match_fall0_and_r;
  wire [7:0]pat0_match_fall0_r;
  wire pat0_match_fall1_and_r;
  wire [7:0]pat0_match_fall1_r;
  wire pat0_match_fall2_and_r;
  wire [7:0]pat0_match_fall2_r;
  wire pat0_match_fall3_and_r;
  wire [7:0]pat0_match_fall3_r;
  wire pat0_match_rise0_and_r;
  wire [7:0]pat0_match_rise0_r;
  wire pat0_match_rise1_and_r;
  wire [7:0]pat0_match_rise1_r;
  wire pat0_match_rise2_and_r;
  wire [7:0]pat0_match_rise2_r;
  wire pat0_match_rise3_and_r;
  wire [7:0]pat0_match_rise3_r;
  wire pat1_data_match_r0;
  wire pat1_match_fall0_and_r;
  wire pat1_match_fall1_and_r;
  wire pat1_match_fall2_and_r;
  wire pat1_match_fall3_and_r;
  wire pat1_match_rise0_and_r;
  wire pat1_match_rise1_and_r;
  wire pat1_match_rise2_and_r;
  wire pat1_match_rise3_and_r;
  wire pb_cnt_eye_size_r;
  wire pb_detect_edge;
  wire [7:0]pb_detect_edge_done_r;
  wire [7:0]pb_found_stable_eye_r;
  wire pi_cnt_dec_i_1_n_0;
  wire pi_cnt_dec_i_2_n_0;
  wire pi_cnt_dec_reg_0;
  wire pi_en_stg2_f_timing;
  wire pi_en_stg2_f_timing_i_1_n_0;
  wire pi_fine_dly_dec_done;
  wire [5:0]pi_rdval_cnt;
  wire \pi_rdval_cnt[0]_i_1_n_0 ;
  wire \pi_rdval_cnt[1]_i_1_n_0 ;
  wire \pi_rdval_cnt[2]_i_1_n_0 ;
  wire \pi_rdval_cnt[3]_i_1_n_0 ;
  wire \pi_rdval_cnt[3]_i_2_n_0 ;
  wire \pi_rdval_cnt[3]_i_3_n_0 ;
  wire \pi_rdval_cnt[4]_i_1_n_0 ;
  wire \pi_rdval_cnt[5]_i_1_n_0 ;
  wire \pi_rdval_cnt[5]_i_2_n_0 ;
  wire \pi_rdval_cnt[5]_i_3_n_0 ;
  wire \pi_rdval_cnt[5]_i_4_n_0 ;
  wire pi_stg2_f_incdec_timing;
  wire pi_stg2_f_incdec_timing_i_1_n_0;
  wire pi_stg2_f_incdec_timing_reg_0;
  wire pi_stg2_load_reg_0;
  wire pi_stg2_load_timing;
  wire pi_stg2_load_timing_i_1_n_0;
  wire [2:0]pi_stg2_rdlvl_cnt;
  wire [5:0]\pi_stg2_reg_l_reg[5]_0 ;
  wire [5:0]pi_stg2_reg_l_timing;
  wire \pi_stg2_reg_l_timing[0]_i_2_n_0 ;
  wire \pi_stg2_reg_l_timing[0]_i_3_n_0 ;
  wire \pi_stg2_reg_l_timing[1]_i_2_n_0 ;
  wire \pi_stg2_reg_l_timing[1]_i_3_n_0 ;
  wire \pi_stg2_reg_l_timing[2]_i_2_n_0 ;
  wire \pi_stg2_reg_l_timing[2]_i_3_n_0 ;
  wire \pi_stg2_reg_l_timing[3]_i_2_n_0 ;
  wire \pi_stg2_reg_l_timing[3]_i_3_n_0 ;
  wire \pi_stg2_reg_l_timing[4]_i_2_n_0 ;
  wire \pi_stg2_reg_l_timing[4]_i_3_n_0 ;
  wire \pi_stg2_reg_l_timing[5]_i_1_n_0 ;
  wire \pi_stg2_reg_l_timing[5]_i_3_n_0 ;
  wire \pi_stg2_reg_l_timing[5]_i_4_n_0 ;
  wire \pi_stg2_reg_l_timing[5]_i_5_n_0 ;
  wire prech_done;
  wire prech_req;
  wire prech_req_r_reg;
  wire prech_req_r_reg_0;
  wire \rd_mux_sel_r_reg[2]_0 ;
  wire \rd_mux_sel_r_reg_n_0_[2] ;
  wire [5:0]rdlvl_dqs_tap_cnt_r;
  wire \rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0 ;
  wire \rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0 ;
  wire \rdlvl_dqs_tap_cnt_r[0][1][5]_i_1_n_0 ;
  wire \rdlvl_dqs_tap_cnt_r[0][2][5]_i_1_n_0 ;
  wire \rdlvl_dqs_tap_cnt_r[0][3][5]_i_1_n_0 ;
  wire \rdlvl_dqs_tap_cnt_r[0][4][5]_i_1_n_0 ;
  wire \rdlvl_dqs_tap_cnt_r[0][5][5]_i_1_n_0 ;
  wire \rdlvl_dqs_tap_cnt_r[0][6][5]_i_1_n_0 ;
  wire \rdlvl_dqs_tap_cnt_r[0][7][5]_i_1_n_0 ;
  wire [1:0]\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][0] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][1] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][2] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][3] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][4] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][5] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][0] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][1] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][2] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][3] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][4] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][5] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][0] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][1] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][2] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][3] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][4] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][5] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][0] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][1] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][2] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][3] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][4] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][5] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][4][0] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][4][1] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][4][2] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][4][3] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][4][4] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][4][5] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][5][0] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][5][1] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][5][2] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][5][3] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][5][4] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][5][5] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][6][0] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][6][1] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][6][2] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][6][3] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][6][4] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][6][5] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][7][0] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][7][1] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][7][2] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][7][3] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][7][4] ;
  wire \rdlvl_dqs_tap_cnt_r_reg_n_0_[0][7][5] ;
  wire rdlvl_last_byte_done;
  wire rdlvl_last_byte_done_int_i_1_n_0;
  wire rdlvl_pi_incdec;
  wire rdlvl_pi_incdec_i_1_n_0;
  wire rdlvl_pi_incdec_i_2_n_0;
  wire rdlvl_pi_incdec_i_3_n_0;
  wire rdlvl_pi_incdec_i_4_n_0;
  wire rdlvl_pi_incdec_i_5_n_0;
  wire rdlvl_pi_incdec_reg_0;
  wire rdlvl_pi_stg2_f_en;
  wire rdlvl_pi_stg2_f_incdec;
  wire rdlvl_prech_req;
  wire rdlvl_rank_done_r_i_1_n_0;
  wire rdlvl_rank_done_r_i_2_n_0;
  wire rdlvl_rank_done_r_i_3_n_0;
  wire rdlvl_stg1_done_int;
  wire rdlvl_stg1_done_int_i_1_n_0;
  wire rdlvl_stg1_done_int_reg_0;
  wire rdlvl_stg1_done_int_reg_1;
  wire [0:0]rdlvl_stg1_done_int_reg_2;
  wire [3:0]rdlvl_stg1_done_int_reg_3;
  wire rdlvl_stg1_done_r1;
  wire rdlvl_stg1_done_r1_reg;
  wire rdlvl_stg1_rank_done;
  wire rdlvl_stg1_start_r;
  wire rdlvl_stg1_start_r_reg_0;
  wire [3:0]regl_dqs_cnt;
  wire \regl_dqs_cnt[0]_i_1_n_0 ;
  wire \regl_dqs_cnt[1]_i_1_n_0 ;
  wire \regl_dqs_cnt[2]_i_1_n_0 ;
  wire \regl_dqs_cnt[3]_i_1_n_0 ;
  wire [3:0]regl_dqs_cnt_r;
  wire [1:0]regl_rank_cnt;
  wire regl_rank_cnt0;
  wire \regl_rank_cnt[0]_i_1_n_0 ;
  wire \regl_rank_cnt[1]_i_1_n_0 ;
  wire \regl_rank_cnt[1]_i_3_n_0 ;
  wire [5:0]right_edge_taps_r;
  wire \right_edge_taps_r[5]_i_1_n_0 ;
  wire \right_edge_taps_r_reg_n_0_[0] ;
  wire \right_edge_taps_r_reg_n_0_[1] ;
  wire \right_edge_taps_r_reg_n_0_[2] ;
  wire \right_edge_taps_r_reg_n_0_[3] ;
  wire \right_edge_taps_r_reg_n_0_[4] ;
  wire \right_edge_taps_r_reg_n_0_[5] ;
  wire \rnk_cnt_r[0]_i_1__0_n_0 ;
  wire \rnk_cnt_r[1]_i_1__0_n_0 ;
  wire \rnk_cnt_r[1]_i_2_n_0 ;
  wire \rnk_cnt_r_reg[0]_0 ;
  wire \rnk_cnt_r_reg[1]_0 ;
  wire \rnk_cnt_r_reg_n_0_[0] ;
  wire \rnk_cnt_r_reg_n_0_[1] ;
  wire samp_cnt_done_r_i_1_n_0;
  wire samp_cnt_done_r_i_2_n_0;
  wire samp_cnt_done_r_i_3_n_0;
  wire samp_cnt_done_r_i_4_n_0;
  wire samp_cnt_done_r_reg_n_0;
  wire samp_edge_cnt0_en_r;
  wire \samp_edge_cnt0_r[0]_i_3_n_0 ;
  wire [11:0]samp_edge_cnt0_r_reg;
  wire \samp_edge_cnt0_r_reg[0]_i_2_n_0 ;
  wire \samp_edge_cnt0_r_reg[0]_i_2_n_1 ;
  wire \samp_edge_cnt0_r_reg[0]_i_2_n_2 ;
  wire \samp_edge_cnt0_r_reg[0]_i_2_n_3 ;
  wire \samp_edge_cnt0_r_reg[0]_i_2_n_4 ;
  wire \samp_edge_cnt0_r_reg[0]_i_2_n_5 ;
  wire \samp_edge_cnt0_r_reg[0]_i_2_n_6 ;
  wire \samp_edge_cnt0_r_reg[0]_i_2_n_7 ;
  wire \samp_edge_cnt0_r_reg[4]_i_1_n_0 ;
  wire \samp_edge_cnt0_r_reg[4]_i_1_n_1 ;
  wire \samp_edge_cnt0_r_reg[4]_i_1_n_2 ;
  wire \samp_edge_cnt0_r_reg[4]_i_1_n_3 ;
  wire \samp_edge_cnt0_r_reg[4]_i_1_n_4 ;
  wire \samp_edge_cnt0_r_reg[4]_i_1_n_5 ;
  wire \samp_edge_cnt0_r_reg[4]_i_1_n_6 ;
  wire \samp_edge_cnt0_r_reg[4]_i_1_n_7 ;
  wire \samp_edge_cnt0_r_reg[8]_i_1_n_1 ;
  wire \samp_edge_cnt0_r_reg[8]_i_1_n_2 ;
  wire \samp_edge_cnt0_r_reg[8]_i_1_n_3 ;
  wire \samp_edge_cnt0_r_reg[8]_i_1_n_4 ;
  wire \samp_edge_cnt0_r_reg[8]_i_1_n_5 ;
  wire \samp_edge_cnt0_r_reg[8]_i_1_n_6 ;
  wire \samp_edge_cnt0_r_reg[8]_i_1_n_7 ;
  wire samp_edge_cnt1_en_r;
  wire samp_edge_cnt1_en_r0;
  wire samp_edge_cnt1_en_r_i_2_n_0;
  wire samp_edge_cnt1_en_r_i_3_n_0;
  wire \samp_edge_cnt1_r[0]_i_2_n_0 ;
  wire [11:0]samp_edge_cnt1_r_reg;
  wire \samp_edge_cnt1_r_reg[0]_0 ;
  wire \samp_edge_cnt1_r_reg[0]_i_1_n_0 ;
  wire \samp_edge_cnt1_r_reg[0]_i_1_n_1 ;
  wire \samp_edge_cnt1_r_reg[0]_i_1_n_2 ;
  wire \samp_edge_cnt1_r_reg[0]_i_1_n_3 ;
  wire \samp_edge_cnt1_r_reg[0]_i_1_n_4 ;
  wire \samp_edge_cnt1_r_reg[0]_i_1_n_5 ;
  wire \samp_edge_cnt1_r_reg[0]_i_1_n_6 ;
  wire \samp_edge_cnt1_r_reg[0]_i_1_n_7 ;
  wire \samp_edge_cnt1_r_reg[4]_i_1_n_0 ;
  wire \samp_edge_cnt1_r_reg[4]_i_1_n_1 ;
  wire \samp_edge_cnt1_r_reg[4]_i_1_n_2 ;
  wire \samp_edge_cnt1_r_reg[4]_i_1_n_3 ;
  wire \samp_edge_cnt1_r_reg[4]_i_1_n_4 ;
  wire \samp_edge_cnt1_r_reg[4]_i_1_n_5 ;
  wire \samp_edge_cnt1_r_reg[4]_i_1_n_6 ;
  wire \samp_edge_cnt1_r_reg[4]_i_1_n_7 ;
  wire \samp_edge_cnt1_r_reg[8]_i_1_n_1 ;
  wire \samp_edge_cnt1_r_reg[8]_i_1_n_2 ;
  wire \samp_edge_cnt1_r_reg[8]_i_1_n_3 ;
  wire \samp_edge_cnt1_r_reg[8]_i_1_n_4 ;
  wire \samp_edge_cnt1_r_reg[8]_i_1_n_5 ;
  wire \samp_edge_cnt1_r_reg[8]_i_1_n_6 ;
  wire \samp_edge_cnt1_r_reg[8]_i_1_n_7 ;
  wire \second_edge_taps_r[1]_i_1_n_0 ;
  wire \second_edge_taps_r[2]_i_1_n_0 ;
  wire \second_edge_taps_r[3]_i_1_n_0 ;
  wire \second_edge_taps_r[4]_i_1_n_0 ;
  wire \second_edge_taps_r[5]_i_1_n_0 ;
  wire \second_edge_taps_r[5]_i_2_n_0 ;
  wire \second_edge_taps_r[5]_i_3_n_0 ;
  wire \second_edge_taps_r_reg_n_0_[0] ;
  wire \second_edge_taps_r_reg_n_0_[1] ;
  wire \second_edge_taps_r_reg_n_0_[2] ;
  wire \second_edge_taps_r_reg_n_0_[3] ;
  wire \second_edge_taps_r_reg_n_0_[4] ;
  wire \second_edge_taps_r_reg_n_0_[5] ;
  wire sr_valid_r1;
  wire sr_valid_r2;
  wire sr_valid_r_i_1_n_0;
  wire sr_valid_r_reg_0;
  wire sr_valid_r_reg_n_0;
  wire stable_idel_cnt;
  wire stable_idel_cnt0;
  wire stg1_wr_done;
  wire \stg1_wr_rd_cnt_reg[3] ;
  wire store_sr_r0;
  wire store_sr_r_i_1_n_0;
  wire store_sr_r_reg_n_0;
  wire store_sr_req_pulsed_r;
  wire store_sr_req_pulsed_r__0;
  wire store_sr_req_r;
  wire store_sr_req_r_i_2_n_0;
  wire store_sr_req_r_reg_n_0;
  wire tap_cnt_cpt_r;
  wire [0:0]tap_cnt_cpt_r0;
  wire \tap_cnt_cpt_r[1]_i_1_n_0 ;
  wire \tap_cnt_cpt_r[5]_i_4_n_0 ;
  wire \tap_cnt_cpt_r[5]_i_5_n_0 ;
  wire \tap_cnt_cpt_r[5]_i_6_n_0 ;
  wire [0:0]\tap_cnt_cpt_r_reg[5]_0 ;
  wire \tap_cnt_cpt_r_reg_n_0_[0] ;
  wire \tap_cnt_cpt_r_reg_n_0_[1] ;
  wire \tap_cnt_cpt_r_reg_n_0_[2] ;
  wire \tap_cnt_cpt_r_reg_n_0_[3] ;
  wire \tap_cnt_cpt_r_reg_n_0_[4] ;
  wire \tap_cnt_cpt_r_reg_n_0_[5] ;
  wire tap_limit_cpt_r;
  wire tap_limit_cpt_r_i_1_n_0;
  wire tap_limit_cpt_r_i_2_n_0;
  wire wait_cnt_r0;
  wire [3:0]wait_cnt_r0__0;
  wire \wait_cnt_r[1]_i_1__0_n_0 ;
  wire [3:0]wait_cnt_r_reg;
  wire [0:0]\wait_cnt_r_reg[0]_0 ;
  wire wrcal_prech_req;
  wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56] ;
  wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 ;
  wire [0:0]\NLW_cnt_idel_dec_cpt_r_reg[2]_i_10_O_UNCONNECTED ;
  wire [0:0]\NLW_cnt_idel_dec_cpt_r_reg[2]_i_2_O_UNCONNECTED ;
  wire [3:1]\NLW_cnt_idel_dec_cpt_r_reg[4]_i_2_CO_UNCONNECTED ;
  wire [3:2]\NLW_cnt_idel_dec_cpt_r_reg[4]_i_2_O_UNCONNECTED ;
  wire [3:1]\NLW_cnt_idel_dec_cpt_r_reg[4]_i_8_CO_UNCONNECTED ;
  wire [3:2]\NLW_cnt_idel_dec_cpt_r_reg[4]_i_8_O_UNCONNECTED ;
  wire [3:3]\NLW_samp_edge_cnt0_r_reg[8]_i_1_CO_UNCONNECTED ;
  wire [3:3]\NLW_samp_edge_cnt1_r_reg[8]_i_1_CO_UNCONNECTED ;

  (* SOFT_HLUTNM = "soft_lutpair104" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \FSM_onehot_cal1_state_r[10]_i_1 
       (.I0(p_1_in26_in),
        .I1(p_2_in),
        .O(\FSM_onehot_cal1_state_r[10]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair107" *) 
  LUT5 #(
    .INIT(32'h00002AAA)) 
    \FSM_onehot_cal1_state_r[11]_i_1 
       (.I0(store_sr_req_pulsed_r),
        .I1(found_edge_r_reg_n_0),
        .I2(found_stable_eye_last_r),
        .I3(found_first_edge_r_reg_n_0),
        .I4(tap_limit_cpt_r),
        .O(\FSM_onehot_cal1_state_r[11]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair117" *) 
  LUT4 #(
    .INIT(16'hFBAA)) 
    \FSM_onehot_cal1_state_r[13]_i_1 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[8] ),
        .I1(mpr_rdlvl_start_r_reg_0),
        .I2(mpr_rdlvl_start_r),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[7] ),
        .O(\FSM_onehot_cal1_state_r[13]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair128" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \FSM_onehot_cal1_state_r[14]_i_1 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[1] ),
        .I1(\FSM_onehot_cal1_state_r[16]_i_2_n_0 ),
        .O(\FSM_onehot_cal1_state_r[14]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'hBA)) 
    \FSM_onehot_cal1_state_r[15]_i_1 
       (.I0(\FSM_onehot_cal1_state_r[15]_i_2_n_0 ),
        .I1(\FSM_onehot_cal1_state_r[15]_i_3_n_0 ),
        .I2(p_12_in),
        .O(\FSM_onehot_cal1_state_r[15]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair132" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \FSM_onehot_cal1_state_r[15]_i_2 
       (.I0(\FSM_onehot_cal1_state_r[16]_i_3_n_0 ),
        .I1(mpr_dec_cpt_r_reg_n_0),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[1] ),
        .I3(\FSM_onehot_cal1_state_r[16]_i_2_n_0 ),
        .O(\FSM_onehot_cal1_state_r[15]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000002)) 
    \FSM_onehot_cal1_state_r[15]_i_3 
       (.I0(\pi_rdval_cnt[5]_i_3_n_0 ),
        .I1(\idel_dec_cnt_reg_n_0_[4] ),
        .I2(\idel_dec_cnt_reg_n_0_[2] ),
        .I3(\idel_dec_cnt_reg_n_0_[1] ),
        .I4(\idel_dec_cnt_reg_n_0_[0] ),
        .I5(\idel_dec_cnt_reg_n_0_[3] ),
        .O(\FSM_onehot_cal1_state_r[15]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF8000FF00)) 
    \FSM_onehot_cal1_state_r[16]_i_1 
       (.I0(\FSM_onehot_cal1_state_r[16]_i_2_n_0 ),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[1] ),
        .I2(\FSM_onehot_cal1_state_r[16]_i_3_n_0 ),
        .I3(mpr_dec_cpt_r_reg_n_0),
        .I4(\FSM_onehot_cal1_state_r[21]_i_2_n_0 ),
        .I5(\FSM_onehot_cal1_state_r[16]_i_4_n_0 ),
        .O(\FSM_onehot_cal1_state_r[16]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000100)) 
    \FSM_onehot_cal1_state_r[16]_i_2 
       (.I0(\cnt_idel_dec_cpt_r_reg_n_0_[4] ),
        .I1(\cnt_idel_dec_cpt_r_reg_n_0_[3] ),
        .I2(\cnt_idel_dec_cpt_r_reg_n_0_[5] ),
        .I3(\cnt_idel_dec_cpt_r_reg_n_0_[0] ),
        .I4(\cnt_idel_dec_cpt_r_reg_n_0_[2] ),
        .I5(\cnt_idel_dec_cpt_r_reg_n_0_[1] ),
        .O(\FSM_onehot_cal1_state_r[16]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair109" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \FSM_onehot_cal1_state_r[16]_i_3 
       (.I0(idelay_tap_cnt_r[0]),
        .I1(\mpr_4to1.inhibit_edge_detect_r_i_2_n_0 ),
        .O(\FSM_onehot_cal1_state_r[16]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair119" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \FSM_onehot_cal1_state_r[16]_i_4 
       (.I0(p_27_in),
        .I1(store_sr_req_r_i_2_n_0),
        .O(\FSM_onehot_cal1_state_r[16]_i_4_n_0 ));
  LUT3 #(
    .INIT(8'hFE)) 
    \FSM_onehot_cal1_state_r[1]_i_1 
       (.I0(mpr_dec_cpt_r),
        .I1(p_9_in),
        .I2(p_13_in),
        .O(\FSM_onehot_cal1_state_r[1]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'hBA)) 
    \FSM_onehot_cal1_state_r[20]_i_1 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[16] ),
        .I1(idel_adj_inc_reg_n_0),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[3] ),
        .O(\FSM_onehot_cal1_state_r[20]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFF1F1F1F1F1F1F1)) 
    \FSM_onehot_cal1_state_r[21]_i_1 
       (.I0(\FSM_onehot_cal1_state_r[21]_i_2_n_0 ),
        .I1(mpr_dec_cpt_r_reg_n_0),
        .I2(\FSM_onehot_cal1_state_r[21]_i_3_n_0 ),
        .I3(idel_mpr_pat_detect_r),
        .I4(p_0_in549_in),
        .I5(idel_pat_detect_valid_r_reg_n_0),
        .O(\FSM_onehot_cal1_state_r[21]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair130" *) 
  LUT2 #(
    .INIT(4'h7)) 
    \FSM_onehot_cal1_state_r[21]_i_2 
       (.I0(p_12_in),
        .I1(\FSM_onehot_cal1_state_r[15]_i_3_n_0 ),
        .O(\FSM_onehot_cal1_state_r[21]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFE0E0E0)) 
    \FSM_onehot_cal1_state_r[21]_i_3 
       (.I0(\gen_pat_match_div4.idel_pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.idel_pat0_data_match_r_reg_n_0 ),
        .I2(p_34_in),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[3] ),
        .I4(idel_adj_inc_reg_n_0),
        .I5(p_8_in),
        .O(\FSM_onehot_cal1_state_r[21]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h080808080808AA08)) 
    \FSM_onehot_cal1_state_r[22]_i_1 
       (.I0(idelay_tap_limit_r_reg_n_0),
        .I1(\FSM_onehot_cal1_state_r[22]_i_2_n_0 ),
        .I2(idel_mpr_pat_detect_r),
        .I3(p_34_in),
        .I4(\gen_pat_match_div4.idel_pat0_data_match_r_reg_n_0 ),
        .I5(\gen_pat_match_div4.idel_pat1_data_match_r_reg_n_0 ),
        .O(\FSM_onehot_cal1_state_r[22]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair110" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \FSM_onehot_cal1_state_r[22]_i_2 
       (.I0(idel_pat_detect_valid_r_reg_n_0),
        .I1(p_0_in549_in),
        .O(\FSM_onehot_cal1_state_r[22]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair107" *) 
  LUT5 #(
    .INIT(32'hAAAA8000)) 
    \FSM_onehot_cal1_state_r[29]_i_1 
       (.I0(store_sr_req_pulsed_r),
        .I1(found_edge_r_reg_n_0),
        .I2(found_stable_eye_last_r),
        .I3(found_first_edge_r_reg_n_0),
        .I4(tap_limit_cpt_r),
        .O(\FSM_onehot_cal1_state_r[29]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0404040404045504)) 
    \FSM_onehot_cal1_state_r[2]_i_1 
       (.I0(idelay_tap_limit_r_reg_n_0),
        .I1(\FSM_onehot_cal1_state_r[22]_i_2_n_0 ),
        .I2(idel_mpr_pat_detect_r),
        .I3(p_34_in),
        .I4(\gen_pat_match_div4.idel_pat0_data_match_r_reg_n_0 ),
        .I5(\gen_pat_match_div4.idel_pat1_data_match_r_reg_n_0 ),
        .O(\FSM_onehot_cal1_state_r[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFF7500)) 
    \FSM_onehot_cal1_state_r[34]_i_1 
       (.I0(\FSM_onehot_cal1_state_r[34]_i_3_n_0 ),
        .I1(\FSM_onehot_cal1_state_r[34]_i_4_n_0 ),
        .I2(detect_edge_done_r),
        .I3(\FSM_onehot_cal1_state_r[34]_i_5_n_0 ),
        .I4(\FSM_onehot_cal1_state_r[34]_i_6_n_0 ),
        .I5(mpr_dec_cpt_r),
        .O(\FSM_onehot_cal1_state_r[34]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF88F8)) 
    \FSM_onehot_cal1_state_r[34]_i_10 
       (.I0(prech_done),
        .I1(cal1_prech_req_r),
        .I2(p_27_in),
        .I3(cal1_wait_r),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[12] ),
        .O(\FSM_onehot_cal1_state_r[34]_i_10_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair128" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    \FSM_onehot_cal1_state_r[34]_i_11 
       (.I0(p_0_in549_in),
        .I1(p_0_in541_in),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[1] ),
        .I3(cal1_dq_idel_inc),
        .O(\FSM_onehot_cal1_state_r[34]_i_11_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000002)) 
    \FSM_onehot_cal1_state_r[34]_i_12 
       (.I0(\FSM_onehot_cal1_state_r[34]_i_4_n_0 ),
        .I1(p_9_in),
        .I2(p_0_in549_in),
        .I3(p_0_in541_in),
        .I4(\FSM_onehot_cal1_state_r[34]_i_13_n_0 ),
        .I5(\cal1_state_r1[2]_i_2_n_0 ),
        .O(\FSM_onehot_cal1_state_r[34]_i_12_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair112" *) 
  LUT3 #(
    .INIT(8'hFE)) 
    \FSM_onehot_cal1_state_r[34]_i_13 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[29] ),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[8] ),
        .I2(p_8_in),
        .O(\FSM_onehot_cal1_state_r[34]_i_13_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair123" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \FSM_onehot_cal1_state_r[34]_i_2 
       (.I0(p_0_in549_in),
        .I1(idel_pat_detect_valid_r_reg_n_0),
        .O(\FSM_onehot_cal1_state_r[34]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000100)) 
    \FSM_onehot_cal1_state_r[34]_i_3 
       (.I0(cal1_dq_idel_inc),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[1] ),
        .I2(\FSM_onehot_cal1_state_r[34]_i_8_n_0 ),
        .I3(cal1_wait_r),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[29] ),
        .I5(\FSM_onehot_cal1_state_r_reg_n_0_[15] ),
        .O(\FSM_onehot_cal1_state_r[34]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair82" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \FSM_onehot_cal1_state_r[34]_i_4 
       (.I0(p_34_in),
        .I1(store_sr_req_pulsed_r),
        .O(\FSM_onehot_cal1_state_r[34]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \FSM_onehot_cal1_state_r[34]_i_5 
       (.I0(\FSM_onehot_cal1_state_r[34]_i_9_n_0 ),
        .I1(p_14_in),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[3] ),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[15] ),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[16] ),
        .I5(p_13_in),
        .O(\FSM_onehot_cal1_state_r[34]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF40F04040)) 
    \FSM_onehot_cal1_state_r[34]_i_6 
       (.I0(mpr_rdlvl_start_r),
        .I1(mpr_rdlvl_start_r_reg_0),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[7] ),
        .I3(rdlvl_stg1_start_r),
        .I4(rdlvl_stg1_start_r_reg_0),
        .I5(\FSM_onehot_cal1_state_r[34]_i_10_n_0 ),
        .O(\FSM_onehot_cal1_state_r[34]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair102" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \FSM_onehot_cal1_state_r[34]_i_7 
       (.I0(p_27_in),
        .I1(store_sr_req_r_i_2_n_0),
        .O(mpr_dec_cpt_r));
  (* SOFT_HLUTNM = "soft_lutpair108" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \FSM_onehot_cal1_state_r[34]_i_8 
       (.I0(p_0_in541_in),
        .I1(p_0_in549_in),
        .O(\FSM_onehot_cal1_state_r[34]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FFFFFFFE)) 
    \FSM_onehot_cal1_state_r[34]_i_9 
       (.I0(cal1_wait_cnt_en_r_i_2_n_0),
        .I1(p_9_in),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[29] ),
        .I3(detect_edge_done_r),
        .I4(\FSM_onehot_cal1_state_r[34]_i_11_n_0 ),
        .I5(\FSM_onehot_cal1_state_r[34]_i_12_n_0 ),
        .O(\FSM_onehot_cal1_state_r[34]_i_9_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair132" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \FSM_onehot_cal1_state_r[4]_i_1 
       (.I0(mpr_dec_cpt_r_reg_n_0),
        .I1(\FSM_onehot_cal1_state_r[16]_i_2_n_0 ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[1] ),
        .O(\FSM_onehot_cal1_state_r[4]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair100" *) 
  LUT5 #(
    .INIT(32'h00000002)) 
    \FSM_onehot_cal1_state_r[5]_i_1 
       (.I0(p_0_in541_in),
        .I1(\FSM_onehot_cal1_state_r[5]_i_2_n_0 ),
        .I2(regl_rank_cnt[1]),
        .I3(regl_rank_cnt[0]),
        .I4(\FSM_onehot_cal1_state_r[5]_i_3_n_0 ),
        .O(\FSM_onehot_cal1_state_r[5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair97" *) 
  LUT4 #(
    .INIT(16'hFFFD)) 
    \FSM_onehot_cal1_state_r[5]_i_2 
       (.I0(done_cnt[0]),
        .I1(done_cnt[1]),
        .I2(done_cnt[3]),
        .I3(done_cnt[2]),
        .O(\FSM_onehot_cal1_state_r[5]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair88" *) 
  LUT4 #(
    .INIT(16'hBFFF)) 
    \FSM_onehot_cal1_state_r[5]_i_3 
       (.I0(regl_dqs_cnt[3]),
        .I1(regl_dqs_cnt[1]),
        .I2(regl_dqs_cnt[0]),
        .I3(regl_dqs_cnt[2]),
        .O(\FSM_onehot_cal1_state_r[5]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h44444444F4444444)) 
    \FSM_onehot_cal1_state_r[6]_i_1 
       (.I0(\FSM_onehot_cal1_state_r[6]_i_2_n_0 ),
        .I1(p_0_in541_in),
        .I2(cal1_prech_req_r),
        .I3(\cal1_cnt_cpt_r_reg_n_0_[1] ),
        .I4(\cal1_cnt_cpt_r_reg_n_0_[0] ),
        .I5(\cal1_cnt_cpt_r_reg[2]_1 ),
        .O(\FSM_onehot_cal1_state_r[6]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair100" *) 
  LUT4 #(
    .INIT(16'h0001)) 
    \FSM_onehot_cal1_state_r[6]_i_2 
       (.I0(\FSM_onehot_cal1_state_r[5]_i_3_n_0 ),
        .I1(regl_rank_cnt[0]),
        .I2(regl_rank_cnt[1]),
        .I3(\FSM_onehot_cal1_state_r[5]_i_2_n_0 ),
        .O(\FSM_onehot_cal1_state_r[6]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair218" *) 
  LUT3 #(
    .INIT(8'hFD)) 
    \FSM_onehot_cal1_state_r[6]_i_3 
       (.I0(\cal1_cnt_cpt_r_reg_n_0_[2] ),
        .I1(\rnk_cnt_r_reg_n_0_[0] ),
        .I2(\rnk_cnt_r_reg_n_0_[1] ),
        .O(\cal1_cnt_cpt_r_reg[2]_1 ));
  LUT6 #(
    .INIT(64'h8000800080000000)) 
    \FSM_onehot_cal1_state_r[7]_i_1 
       (.I0(cal1_prech_req_r),
        .I1(\cal1_cnt_cpt_r_reg_n_0_[1] ),
        .I2(\cal1_cnt_cpt_r_reg_n_0_[0] ),
        .I3(\cal1_cnt_cpt_r_reg_n_0_[2] ),
        .I4(\rnk_cnt_r_reg_n_0_[0] ),
        .I5(\rnk_cnt_r_reg_n_0_[1] ),
        .O(\FSM_onehot_cal1_state_r[7]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair121" *) 
  LUT4 #(
    .INIT(16'h2AAA)) 
    \FSM_onehot_cal1_state_r[8]_i_1 
       (.I0(cal1_prech_req_r),
        .I1(\cal1_cnt_cpt_r_reg_n_0_[2] ),
        .I2(\cal1_cnt_cpt_r_reg_n_0_[0] ),
        .I3(\cal1_cnt_cpt_r_reg_n_0_[1] ),
        .O(\FSM_onehot_cal1_state_r[8]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair210" *) 
  LUT3 #(
    .INIT(8'h40)) 
    \FSM_onehot_cal1_state_r[9]_i_1 
       (.I0(mpr_rdlvl_start_r),
        .I1(mpr_rdlvl_start_r_reg_0),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[7] ),
        .O(\FSM_onehot_cal1_state_r[9]_i_1_n_0 ));
  (* FSM_ENCODED_STATES = "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\FSM_onehot_cal1_state_r[34]_i_1_n_0 ),
        .D(\FSM_onehot_cal1_state_r_reg_n_0_[29] ),
        .Q(p_13_in),
        .R(SR[1]));
  (* FSM_ENCODED_STATES = "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[10] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\FSM_onehot_cal1_state_r[34]_i_1_n_0 ),
        .D(\FSM_onehot_cal1_state_r[10]_i_1_n_0 ),
        .Q(p_0_in549_in),
        .R(SR[1]));
  (* FSM_ENCODED_STATES = "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[11] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\FSM_onehot_cal1_state_r[34]_i_1_n_0 ),
        .D(\FSM_onehot_cal1_state_r[11]_i_1_n_0 ),
        .Q(p_14_in),
        .R(SR[1]));
  (* FSM_ENCODED_STATES = "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[12] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\FSM_onehot_cal1_state_r[34]_i_1_n_0 ),
        .D(p_14_in),
        .Q(\FSM_onehot_cal1_state_r_reg_n_0_[12] ),
        .R(SR[1]));
  (* FSM_ENCODED_STATES = "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[13] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\FSM_onehot_cal1_state_r[34]_i_1_n_0 ),
        .D(\FSM_onehot_cal1_state_r[13]_i_1_n_0 ),
        .Q(p_27_in),
        .R(SR[1]));
  (* FSM_ENCODED_STATES = "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[14] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\FSM_onehot_cal1_state_r[34]_i_1_n_0 ),
        .D(\FSM_onehot_cal1_state_r[14]_i_1_n_0 ),
        .Q(p_9_in),
        .R(SR[1]));
  (* FSM_ENCODED_STATES = "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[15] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\FSM_onehot_cal1_state_r[34]_i_1_n_0 ),
        .D(\FSM_onehot_cal1_state_r[15]_i_1_n_0 ),
        .Q(\FSM_onehot_cal1_state_r_reg_n_0_[15] ),
        .R(SR[1]));
  (* FSM_ENCODED_STATES = "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[16] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\FSM_onehot_cal1_state_r[34]_i_1_n_0 ),
        .D(\FSM_onehot_cal1_state_r[16]_i_1_n_0 ),
        .Q(\FSM_onehot_cal1_state_r_reg_n_0_[16] ),
        .R(SR[1]));
  (* FSM_ENCODED_STATES = "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\FSM_onehot_cal1_state_r[34]_i_1_n_0 ),
        .D(\FSM_onehot_cal1_state_r[1]_i_1_n_0 ),
        .Q(\FSM_onehot_cal1_state_r_reg_n_0_[1] ),
        .R(SR[1]));
  (* FSM_ENCODED_STATES = "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[20] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\FSM_onehot_cal1_state_r[34]_i_1_n_0 ),
        .D(\FSM_onehot_cal1_state_r[20]_i_1_n_0 ),
        .Q(p_34_in),
        .R(SR[1]));
  (* FSM_ENCODED_STATES = "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[21] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\FSM_onehot_cal1_state_r[34]_i_1_n_0 ),
        .D(\FSM_onehot_cal1_state_r[21]_i_1_n_0 ),
        .Q(store_sr_req_pulsed_r),
        .R(SR[1]));
  (* FSM_ENCODED_STATES = "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[22] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\FSM_onehot_cal1_state_r[34]_i_1_n_0 ),
        .D(\FSM_onehot_cal1_state_r[22]_i_1_n_0 ),
        .Q(\FSM_onehot_cal1_state_r_reg_n_0_[22] ),
        .R(SR[1]));
  (* FSM_ENCODED_STATES = "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[29] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\FSM_onehot_cal1_state_r[34]_i_1_n_0 ),
        .D(\FSM_onehot_cal1_state_r[29]_i_1_n_0 ),
        .Q(\FSM_onehot_cal1_state_r_reg_n_0_[29] ),
        .R(SR[1]));
  (* FSM_ENCODED_STATES = "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\FSM_onehot_cal1_state_r[34]_i_1_n_0 ),
        .D(\FSM_onehot_cal1_state_r[2]_i_1_n_0 ),
        .Q(cal1_dq_idel_inc),
        .R(SR[1]));
  (* FSM_ENCODED_STATES = "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[31] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\FSM_onehot_cal1_state_r[34]_i_1_n_0 ),
        .D(\FSM_onehot_cal1_state_r_reg_n_0_[12] ),
        .Q(p_8_in),
        .R(SR[1]));
  (* FSM_ENCODED_STATES = "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[32] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\FSM_onehot_cal1_state_r[34]_i_1_n_0 ),
        .D(\FSM_onehot_cal1_state_r_reg_n_0_[15] ),
        .Q(p_12_in),
        .R(SR[1]));
  (* FSM_ENCODED_STATES = "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[34] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\FSM_onehot_cal1_state_r[34]_i_1_n_0 ),
        .D(\FSM_onehot_cal1_state_r[34]_i_2_n_0 ),
        .Q(p_2_in),
        .R(SR[1]));
  (* FSM_ENCODED_STATES = "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\FSM_onehot_cal1_state_r[34]_i_1_n_0 ),
        .D(cal1_dq_idel_inc),
        .Q(\FSM_onehot_cal1_state_r_reg_n_0_[3] ),
        .R(SR[1]));
  (* FSM_ENCODED_STATES = "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\FSM_onehot_cal1_state_r[34]_i_1_n_0 ),
        .D(\FSM_onehot_cal1_state_r[4]_i_1_n_0 ),
        .Q(cal1_prech_req_r),
        .R(SR[1]));
  (* FSM_ENCODED_STATES = "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[5] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\FSM_onehot_cal1_state_r[34]_i_1_n_0 ),
        .D(\FSM_onehot_cal1_state_r[5]_i_1_n_0 ),
        .Q(rdlvl_stg1_done_int),
        .R(SR[1]));
  (* FSM_ENCODED_STATES = "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[6] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\FSM_onehot_cal1_state_r[34]_i_1_n_0 ),
        .D(\FSM_onehot_cal1_state_r[6]_i_1_n_0 ),
        .Q(p_0_in541_in),
        .R(SR[1]));
  (* FSM_ENCODED_STATES = "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000" *) 
  FDSE #(
    .INIT(1'b1)) 
    \FSM_onehot_cal1_state_r_reg[7] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\FSM_onehot_cal1_state_r[34]_i_1_n_0 ),
        .D(\FSM_onehot_cal1_state_r[7]_i_1_n_0 ),
        .Q(\FSM_onehot_cal1_state_r_reg_n_0_[7] ),
        .S(SR[1]));
  (* FSM_ENCODED_STATES = "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[8] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\FSM_onehot_cal1_state_r[34]_i_1_n_0 ),
        .D(\FSM_onehot_cal1_state_r[8]_i_1_n_0 ),
        .Q(\FSM_onehot_cal1_state_r_reg_n_0_[8] ),
        .R(SR[1]));
  (* FSM_ENCODED_STATES = "CAL1_STORE_FIRST_WAIT:00000000000000000010000000000000000,CAL1_NEW_DQS_WAIT:00000000000000000000010000000000000,CAL1_IDLE:00000000000000000000000000010000000,CAL1_REGL_LOAD:00000000000000000000000000001000000,CAL1_PB_INC_DQ:00000001000000000000000000000000000,CAL1_PB_DEC_CPT_WAIT:00000000100000000000000000000000000,CAL1_CENTER_WAIT:00000000000000000000000000000000001,CAL1_PB_DETECT_EDGE_DQ:00001000000000000000000000000000000,CAL1_PB_DEC_CPT:00000000001000000000000000000000000,CAL1_PB_DEC_CPT_LEFT_WAIT:01000000000000000000000000000000000,CAL1_PB_INC_DQ_WAIT:00000010000000000000000000000000000,CAL1_RD_STOP_FOR_PI_INC:00000000000000000000000100000000000,CAL1_DONE:00000000000000000000000000000100000,CAL1_PB_DEC_CPT_LEFT:00000000000100000000000000000000000,CAL1_NEW_DQS_PREWAIT:00000000000000000000000000100000000,CAL1_NEXT_DQS:00000000000000000000000000000010000,CAL1_IDEL_DEC_CPT_WAIT:00000000000000000000100000000000000,CAL1_IDEL_DEC_CPT:00000000000000000000000000000000010,CAL1_PB_INC_CPT_WAIT:00000000000000000100000000000000000,CAL1_PB_INC_CPT:00000000000000010000000000000000000,CAL1_CALC_IDEL:00000100000000000000000000000000000,CAL1_PB_DETECT_EDGE:00000000000000001000000000000000000,CAL1_DQ_IDEL_TAP_DEC_WAIT:00100000000000000000000000000000000,CAL1_IDEL_INC_CPT_WAIT:00010000000000000000000000000000000,CAL1_PB_STORE_FIRST_WAIT:00000000010000000000000000000000000,CAL1_DQ_IDEL_TAP_DEC:00000000000000000001000000000000000,CAL1_IDEL_INC_CPT:00000000000000000000001000000000000,CAL1_DQ_IDEL_TAP_INC_WAIT:00000000000000000000000000000001000,CAL1_DETECT_EDGE:00000000000001000000000000000000000,CAL1_DQ_IDEL_TAP_INC:00000000000000000000000000000000100,CAL1_MPR_PAT_DETECT:00000000000000000000000010000000000,CAL1_VALID_WAIT:10000000000000000000000000000000000,CAL1_MPR_NEW_DQS_WAIT:00000000000000000000000001000000000,CAL1_RDLVL_ERR:00000000000010000000000000000000000,CAL1_PAT_DETECT:00000000000000100000000000000000000" *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_cal1_state_r_reg[9] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\FSM_onehot_cal1_state_r[34]_i_1_n_0 ),
        .D(\FSM_onehot_cal1_state_r[9]_i_1_n_0 ),
        .Q(p_1_in26_in),
        .R(SR[1]));
  LUT6 #(
    .INIT(64'h0F4F50505A5A5050)) 
    \cal1_cnt_cpt_r[0]_i_1 
       (.I0(p_0_in541_in),
        .I1(\cal1_cnt_cpt_r_reg_n_0_[1] ),
        .I2(\cal1_cnt_cpt_r_reg_n_0_[0] ),
        .I3(\cal1_cnt_cpt_r_reg[2]_1 ),
        .I4(cal1_prech_req_r),
        .I5(prech_done),
        .O(\cal1_cnt_cpt_r[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h3C7C44446C6C4444)) 
    \cal1_cnt_cpt_r[1]_i_1 
       (.I0(p_0_in541_in),
        .I1(\cal1_cnt_cpt_r_reg_n_0_[1] ),
        .I2(\cal1_cnt_cpt_r_reg_n_0_[0] ),
        .I3(\cal1_cnt_cpt_r_reg[2]_1 ),
        .I4(cal1_prech_req_r),
        .I5(prech_done),
        .O(\cal1_cnt_cpt_r[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h73CC550077885500)) 
    \cal1_cnt_cpt_r[2]_i_1 
       (.I0(p_0_in541_in),
        .I1(\cal1_cnt_cpt_r[2]_i_2_n_0 ),
        .I2(\cal1_cnt_cpt_r[2]_i_3_n_0 ),
        .I3(\cal1_cnt_cpt_r_reg_n_0_[2] ),
        .I4(cal1_prech_req_r),
        .I5(prech_done),
        .O(\cal1_cnt_cpt_r[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair219" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \cal1_cnt_cpt_r[2]_i_2 
       (.I0(\cal1_cnt_cpt_r_reg_n_0_[0] ),
        .I1(\cal1_cnt_cpt_r_reg_n_0_[1] ),
        .O(\cal1_cnt_cpt_r[2]_i_2_n_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    \cal1_cnt_cpt_r[2]_i_3 
       (.I0(\rnk_cnt_r_reg_n_0_[1] ),
        .I1(\rnk_cnt_r_reg_n_0_[0] ),
        .O(\cal1_cnt_cpt_r[2]_i_3_n_0 ));
  FDRE \cal1_cnt_cpt_r_reg[0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\cal1_cnt_cpt_r[0]_i_1_n_0 ),
        .Q(\cal1_cnt_cpt_r_reg_n_0_[0] ),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 [1]));
  FDRE \cal1_cnt_cpt_r_reg[1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\cal1_cnt_cpt_r[1]_i_1_n_0 ),
        .Q(\cal1_cnt_cpt_r_reg_n_0_[1] ),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 [1]));
  FDRE \cal1_cnt_cpt_r_reg[2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\cal1_cnt_cpt_r[2]_i_1_n_0 ),
        .Q(\cal1_cnt_cpt_r_reg_n_0_[2] ),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 [1]));
  (* SOFT_HLUTNM = "soft_lutpair222" *) 
  LUT3 #(
    .INIT(8'hBA)) 
    cal1_dlyce_cpt_r_i_1
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[1] ),
        .I1(tap_limit_cpt_r),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[12] ),
        .O(cal1_dlyce_cpt_r));
  FDRE cal1_dlyce_cpt_r_reg
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(cal1_dlyce_cpt_r),
        .Q(cal1_dlyce_cpt_r_reg_n_0),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 [1]));
  (* SOFT_HLUTNM = "soft_lutpair222" *) 
  LUT2 #(
    .INIT(4'h2)) 
    cal1_dlyinc_cpt_r_i_1
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[12] ),
        .I1(tap_limit_cpt_r),
        .O(cal1_dlyinc_cpt_r));
  FDRE cal1_dlyinc_cpt_r_reg
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(cal1_dlyinc_cpt_r),
        .Q(cal1_dlyinc_cpt_r_reg_n_0),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 [1]));
  LUT2 #(
    .INIT(4'hE)) 
    cal1_dq_idel_ce_i_1
       (.I0(cal1_dq_idel_inc),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[15] ),
        .O(cal1_dq_idel_ce));
  FDRE cal1_dq_idel_ce_reg
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(cal1_dq_idel_ce),
        .Q(idelay_ce_int),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 [1]));
  FDRE cal1_dq_idel_inc_reg
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(cal1_dq_idel_inc),
        .Q(idelay_inc_int),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 [1]));
  FDRE cal1_prech_req_r_reg
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(cal1_prech_req_r),
        .Q(cal1_prech_req_r__0),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 [1]));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \cal1_state_r1[0]_i_1 
       (.I0(p_0_in541_in),
        .I1(rdlvl_stg1_done_int),
        .I2(\cal1_state_r1[0]_i_2_n_0 ),
        .I3(p_9_in),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[29] ),
        .I5(\cal1_state_r1[0]_i_3_n_0 ),
        .O(\cal1_state_r1[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair111" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \cal1_state_r1[0]_i_2 
       (.I0(p_34_in),
        .I1(p_0_in549_in),
        .O(\cal1_state_r1[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \cal1_state_r1[0]_i_3 
       (.I0(p_27_in),
        .I1(p_14_in),
        .I2(p_1_in26_in),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[3] ),
        .I4(p_12_in),
        .I5(\FSM_onehot_cal1_state_r_reg_n_0_[12] ),
        .O(\cal1_state_r1[0]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \cal1_state_r1[1]_i_1 
       (.I0(\cal1_state_r1[3]_i_3_n_0 ),
        .I1(\cal1_state_r1[1]_i_2_n_0 ),
        .I2(p_12_in),
        .I3(p_2_in),
        .I4(cal1_prech_req_r),
        .I5(\FSM_onehot_cal1_state_r_reg_n_0_[15] ),
        .O(\cal1_state_r1[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair111" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    \cal1_state_r1[1]_i_2 
       (.I0(p_13_in),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[16] ),
        .I2(p_0_in549_in),
        .I3(p_34_in),
        .O(\cal1_state_r1[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \cal1_state_r1[2]_i_1 
       (.I0(\cal1_state_r1[3]_i_2_n_0 ),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[3] ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[15] ),
        .I3(p_1_in26_in),
        .I4(rdlvl_stg1_done_int),
        .I5(\cal1_state_r1[2]_i_2_n_0 ),
        .O(\cal1_state_r1[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair130" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    \cal1_state_r1[2]_i_2 
       (.I0(p_12_in),
        .I1(p_2_in),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[1] ),
        .I3(cal1_dq_idel_inc),
        .O(\cal1_state_r1[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    \cal1_state_r1[3]_i_1 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[12] ),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[1] ),
        .I2(store_sr_req_pulsed_r),
        .I3(\FSM_onehot_cal1_state_r[10]_i_1_n_0 ),
        .I4(\cal1_state_r1[3]_i_2_n_0 ),
        .I5(\cal1_state_r1[3]_i_3_n_0 ),
        .O(\cal1_state_r1[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair108" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    \cal1_state_r1[3]_i_2 
       (.I0(cal1_prech_req_r),
        .I1(p_0_in549_in),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[22] ),
        .I3(p_9_in),
        .O(\cal1_state_r1[3]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair112" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    \cal1_state_r1[3]_i_3 
       (.I0(p_0_in541_in),
        .I1(rdlvl_stg1_done_int),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[29] ),
        .I3(p_8_in),
        .O(\cal1_state_r1[3]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair104" *) 
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \cal1_state_r1[4]_i_1 
       (.I0(p_2_in),
        .I1(p_1_in26_in),
        .I2(p_0_in541_in),
        .I3(p_0_in549_in),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[22] ),
        .O(\cal1_state_r1[4]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair206" *) 
  LUT3 #(
    .INIT(8'hFE)) 
    \cal1_state_r1[5]_i_1 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[8] ),
        .I1(p_14_in),
        .I2(p_13_in),
        .O(\cal1_state_r1[5]_i_1_n_0 ));
  FDRE \cal1_state_r1_reg[0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\cal1_state_r1[0]_i_1_n_0 ),
        .Q(\cal1_state_r1_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \cal1_state_r1_reg[1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\cal1_state_r1[1]_i_1_n_0 ),
        .Q(\cal1_state_r1_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \cal1_state_r1_reg[2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\cal1_state_r1[2]_i_1_n_0 ),
        .Q(\cal1_state_r1_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \cal1_state_r1_reg[3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\cal1_state_r1[3]_i_1_n_0 ),
        .Q(\cal1_state_r1_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \cal1_state_r1_reg[4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\cal1_state_r1[4]_i_1_n_0 ),
        .Q(\cal1_state_r1_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \cal1_state_r1_reg[5] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\cal1_state_r1[5]_i_1_n_0 ),
        .Q(\cal1_state_r1_reg_n_0_[5] ),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    cal1_wait_cnt_en_r_i_1
       (.I0(cal1_wait_cnt_en_r_i_2_n_0),
        .I1(p_9_in),
        .I2(p_13_in),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[3] ),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[16] ),
        .I5(cal1_wait_cnt_en_r_i_3_n_0),
        .O(cal1_wait_cnt_en_r0));
  (* SOFT_HLUTNM = "soft_lutpair129" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    cal1_wait_cnt_en_r_i_2
       (.I0(p_12_in),
        .I1(p_2_in),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[8] ),
        .I3(p_8_in),
        .O(cal1_wait_cnt_en_r_i_2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair206" *) 
  LUT3 #(
    .INIT(8'hFE)) 
    cal1_wait_cnt_en_r_i_3
       (.I0(p_1_in26_in),
        .I1(p_14_in),
        .I2(p_27_in),
        .O(cal1_wait_cnt_en_r_i_3_n_0));
  FDRE cal1_wait_cnt_en_r_reg
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(cal1_wait_cnt_en_r0),
        .Q(cal1_wait_cnt_en_r),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \cal1_wait_cnt_r[0]_i_1 
       (.I0(cal1_wait_cnt_r_reg[0]),
        .O(p_0_in__1[0]));
  (* SOFT_HLUTNM = "soft_lutpair220" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \cal1_wait_cnt_r[1]_i_1 
       (.I0(cal1_wait_cnt_r_reg[1]),
        .I1(cal1_wait_cnt_r_reg[0]),
        .O(p_0_in__1[1]));
  (* SOFT_HLUTNM = "soft_lutpair220" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \cal1_wait_cnt_r[2]_i_1 
       (.I0(cal1_wait_cnt_r_reg[2]),
        .I1(cal1_wait_cnt_r_reg[0]),
        .I2(cal1_wait_cnt_r_reg[1]),
        .O(p_0_in__1[2]));
  (* SOFT_HLUTNM = "soft_lutpair106" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \cal1_wait_cnt_r[3]_i_1 
       (.I0(cal1_wait_cnt_r_reg[3]),
        .I1(cal1_wait_cnt_r_reg[1]),
        .I2(cal1_wait_cnt_r_reg[0]),
        .I3(cal1_wait_cnt_r_reg[2]),
        .O(p_0_in__1[3]));
  LUT6 #(
    .INIT(64'h40000000FFFFFFFF)) 
    \cal1_wait_cnt_r[4]_i_1 
       (.I0(cal1_wait_cnt_r_reg[4]),
        .I1(cal1_wait_cnt_r_reg[3]),
        .I2(cal1_wait_cnt_r_reg[1]),
        .I3(cal1_wait_cnt_r_reg[0]),
        .I4(cal1_wait_cnt_r_reg[2]),
        .I5(cal1_wait_cnt_en_r),
        .O(\cal1_wait_cnt_r[4]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair106" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \cal1_wait_cnt_r[4]_i_2 
       (.I0(cal1_wait_cnt_r_reg[4]),
        .I1(cal1_wait_cnt_r_reg[2]),
        .I2(cal1_wait_cnt_r_reg[0]),
        .I3(cal1_wait_cnt_r_reg[1]),
        .I4(cal1_wait_cnt_r_reg[3]),
        .O(p_0_in__1[4]));
  FDRE \cal1_wait_cnt_r_reg[0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(p_0_in__1[0]),
        .Q(cal1_wait_cnt_r_reg[0]),
        .R(\cal1_wait_cnt_r[4]_i_1_n_0 ));
  FDRE \cal1_wait_cnt_r_reg[1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(p_0_in__1[1]),
        .Q(cal1_wait_cnt_r_reg[1]),
        .R(\cal1_wait_cnt_r[4]_i_1_n_0 ));
  FDRE \cal1_wait_cnt_r_reg[2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(p_0_in__1[2]),
        .Q(cal1_wait_cnt_r_reg[2]),
        .R(\cal1_wait_cnt_r[4]_i_1_n_0 ));
  FDRE \cal1_wait_cnt_r_reg[3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(p_0_in__1[3]),
        .Q(cal1_wait_cnt_r_reg[3]),
        .R(\cal1_wait_cnt_r[4]_i_1_n_0 ));
  FDRE \cal1_wait_cnt_r_reg[4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(p_0_in__1[4]),
        .Q(cal1_wait_cnt_r_reg[4]),
        .R(\cal1_wait_cnt_r[4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hDFFFFFFFFFFFFFFF)) 
    cal1_wait_r_i_1
       (.I0(cal1_wait_cnt_en_r),
        .I1(cal1_wait_cnt_r_reg[4]),
        .I2(cal1_wait_cnt_r_reg[3]),
        .I3(cal1_wait_cnt_r_reg[1]),
        .I4(cal1_wait_cnt_r_reg[0]),
        .I5(cal1_wait_cnt_r_reg[2]),
        .O(cal1_wait_r_i_1_n_0));
  FDRE cal1_wait_r_reg
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(cal1_wait_r_i_1_n_0),
        .Q(cal1_wait_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hFFFF7020)) 
    \cnt_idel_dec_cpt_r[0]_i_1 
       (.I0(found_second_edge_r_reg_n_0),
        .I1(cnt_idel_dec_cpt_r1[0]),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[29] ),
        .I3(\cnt_idel_dec_cpt_r[0]_i_2_n_0 ),
        .I4(\cnt_idel_dec_cpt_r[0]_i_3_n_0 ),
        .O(cnt_idel_dec_cpt_r[0]));
  LUT6 #(
    .INIT(64'hB800B8FFB8FFB800)) 
    \cnt_idel_dec_cpt_r[0]_i_2 
       (.I0(\cnt_idel_dec_cpt_r_reg[2]_i_10_n_6 ),
        .I1(found_first_edge_r_reg_n_0),
        .I2(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .I3(\cnt_idel_dec_cpt_r[4]_i_9_n_0 ),
        .I4(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .I5(\right_edge_taps_r_reg_n_0_[1] ),
        .O(\cnt_idel_dec_cpt_r[0]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair119" *) 
  LUT4 #(
    .INIT(16'h8F88)) 
    \cnt_idel_dec_cpt_r[0]_i_3 
       (.I0(D[0]),
        .I1(p_27_in),
        .I2(\cnt_idel_dec_cpt_r_reg_n_0_[0] ),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[1] ),
        .O(\cnt_idel_dec_cpt_r[0]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF28AA2800)) 
    \cnt_idel_dec_cpt_r[1]_i_1 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[29] ),
        .I1(cnt_idel_dec_cpt_r1[1]),
        .I2(cnt_idel_dec_cpt_r1[0]),
        .I3(found_second_edge_r_reg_n_0),
        .I4(\cnt_idel_dec_cpt_r[1]_i_2_n_0 ),
        .I5(\cnt_idel_dec_cpt_r[1]_i_3_n_0 ),
        .O(cnt_idel_dec_cpt_r[1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \cnt_idel_dec_cpt_r[1]_i_2 
       (.I0(\cnt_idel_dec_cpt_r_reg[2]_i_10_n_5 ),
        .I1(found_first_edge_r_reg_n_0),
        .I2(\tap_cnt_cpt_r_reg_n_0_[2] ),
        .I3(\cnt_idel_dec_cpt_r[4]_i_9_n_0 ),
        .I4(\cnt_idel_dec_cpt_r[1]_i_4_n_0 ),
        .O(\cnt_idel_dec_cpt_r[1]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hF88F8888)) 
    \cnt_idel_dec_cpt_r[1]_i_3 
       (.I0(D[1]),
        .I1(p_27_in),
        .I2(\cnt_idel_dec_cpt_r_reg_n_0_[1] ),
        .I3(\cnt_idel_dec_cpt_r_reg_n_0_[0] ),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[1] ),
        .O(\cnt_idel_dec_cpt_r[1]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair120" *) 
  LUT4 #(
    .INIT(16'h4BB4)) 
    \cnt_idel_dec_cpt_r[1]_i_4 
       (.I0(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .I1(\right_edge_taps_r_reg_n_0_[1] ),
        .I2(\right_edge_taps_r_reg_n_0_[2] ),
        .I3(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .O(\cnt_idel_dec_cpt_r[1]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF28AA2800)) 
    \cnt_idel_dec_cpt_r[2]_i_1 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[29] ),
        .I1(cnt_idel_dec_cpt_r1[2]),
        .I2(\cnt_idel_dec_cpt_r[2]_i_3_n_0 ),
        .I3(found_second_edge_r_reg_n_0),
        .I4(\cnt_idel_dec_cpt_r[2]_i_4_n_0 ),
        .I5(\cnt_idel_dec_cpt_r[2]_i_5_n_0 ),
        .O(cnt_idel_dec_cpt_r[2]));
  LUT6 #(
    .INIT(64'h2B22D4DDD4DD2B22)) 
    \cnt_idel_dec_cpt_r[2]_i_11 
       (.I0(\right_edge_taps_r_reg_n_0_[2] ),
        .I1(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .I2(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .I3(\right_edge_taps_r_reg_n_0_[1] ),
        .I4(\right_edge_taps_r_reg_n_0_[3] ),
        .I5(\tap_cnt_cpt_r_reg_n_0_[2] ),
        .O(\cnt_idel_dec_cpt_r[2]_i_11_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \cnt_idel_dec_cpt_r[2]_i_12 
       (.I0(\tap_cnt_cpt_r_reg_n_0_[3] ),
        .I1(\first_edge_taps_r_reg_n_0_[3] ),
        .O(\cnt_idel_dec_cpt_r[2]_i_12_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \cnt_idel_dec_cpt_r[2]_i_13 
       (.I0(\tap_cnt_cpt_r_reg_n_0_[2] ),
        .I1(\first_edge_taps_r_reg_n_0_[2] ),
        .O(\cnt_idel_dec_cpt_r[2]_i_13_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \cnt_idel_dec_cpt_r[2]_i_14 
       (.I0(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .I1(\first_edge_taps_r_reg_n_0_[1] ),
        .O(\cnt_idel_dec_cpt_r[2]_i_14_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \cnt_idel_dec_cpt_r[2]_i_15 
       (.I0(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .I1(\first_edge_taps_r_reg_n_0_[0] ),
        .O(\cnt_idel_dec_cpt_r[2]_i_15_n_0 ));
  LUT2 #(
    .INIT(4'h8)) 
    \cnt_idel_dec_cpt_r[2]_i_3 
       (.I0(cnt_idel_dec_cpt_r1[1]),
        .I1(cnt_idel_dec_cpt_r1[0]),
        .O(\cnt_idel_dec_cpt_r[2]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \cnt_idel_dec_cpt_r[2]_i_4 
       (.I0(\cnt_idel_dec_cpt_r_reg[2]_i_10_n_4 ),
        .I1(found_first_edge_r_reg_n_0),
        .I2(\tap_cnt_cpt_r_reg_n_0_[3] ),
        .I3(\cnt_idel_dec_cpt_r[4]_i_9_n_0 ),
        .I4(\cnt_idel_dec_cpt_r[2]_i_11_n_0 ),
        .O(\cnt_idel_dec_cpt_r[2]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hF888F888F88888F8)) 
    \cnt_idel_dec_cpt_r[2]_i_5 
       (.I0(D[2]),
        .I1(p_27_in),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[1] ),
        .I3(\cnt_idel_dec_cpt_r_reg_n_0_[2] ),
        .I4(\cnt_idel_dec_cpt_r_reg_n_0_[0] ),
        .I5(\cnt_idel_dec_cpt_r_reg_n_0_[1] ),
        .O(\cnt_idel_dec_cpt_r[2]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \cnt_idel_dec_cpt_r[2]_i_6 
       (.I0(\second_edge_taps_r_reg_n_0_[3] ),
        .I1(\first_edge_taps_r_reg_n_0_[3] ),
        .O(\cnt_idel_dec_cpt_r[2]_i_6_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \cnt_idel_dec_cpt_r[2]_i_7 
       (.I0(\second_edge_taps_r_reg_n_0_[2] ),
        .I1(\first_edge_taps_r_reg_n_0_[2] ),
        .O(\cnt_idel_dec_cpt_r[2]_i_7_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \cnt_idel_dec_cpt_r[2]_i_8 
       (.I0(\second_edge_taps_r_reg_n_0_[1] ),
        .I1(\first_edge_taps_r_reg_n_0_[1] ),
        .O(\cnt_idel_dec_cpt_r[2]_i_8_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \cnt_idel_dec_cpt_r[2]_i_9 
       (.I0(\second_edge_taps_r_reg_n_0_[0] ),
        .I1(\first_edge_taps_r_reg_n_0_[0] ),
        .O(\cnt_idel_dec_cpt_r[2]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF28AA2800)) 
    \cnt_idel_dec_cpt_r[3]_i_1 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[29] ),
        .I1(cnt_idel_dec_cpt_r1[3]),
        .I2(\cnt_idel_dec_cpt_r[3]_i_2_n_0 ),
        .I3(found_second_edge_r_reg_n_0),
        .I4(\cnt_idel_dec_cpt_r[3]_i_3_n_0 ),
        .I5(\cnt_idel_dec_cpt_r[3]_i_4_n_0 ),
        .O(cnt_idel_dec_cpt_r[3]));
  (* SOFT_HLUTNM = "soft_lutpair131" *) 
  LUT3 #(
    .INIT(8'h80)) 
    \cnt_idel_dec_cpt_r[3]_i_2 
       (.I0(cnt_idel_dec_cpt_r1[2]),
        .I1(cnt_idel_dec_cpt_r1[0]),
        .I2(cnt_idel_dec_cpt_r1[1]),
        .O(\cnt_idel_dec_cpt_r[3]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \cnt_idel_dec_cpt_r[3]_i_3 
       (.I0(\cnt_idel_dec_cpt_r_reg[4]_i_8_n_7 ),
        .I1(found_first_edge_r_reg_n_0),
        .I2(\tap_cnt_cpt_r_reg_n_0_[4] ),
        .I3(\cnt_idel_dec_cpt_r[4]_i_9_n_0 ),
        .I4(\cnt_idel_dec_cpt_r[3]_i_5_n_0 ),
        .O(\cnt_idel_dec_cpt_r[3]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'h8FF88888)) 
    \cnt_idel_dec_cpt_r[3]_i_4 
       (.I0(D[3]),
        .I1(p_27_in),
        .I2(\cnt_idel_dec_cpt_r_reg_n_0_[3] ),
        .I3(\cnt_idel_dec_cpt_r[4]_i_11_n_0 ),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[1] ),
        .O(\cnt_idel_dec_cpt_r[3]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair208" *) 
  LUT3 #(
    .INIT(8'h96)) 
    \cnt_idel_dec_cpt_r[3]_i_5 
       (.I0(\cnt_idel_dec_cpt_r[4]_i_14_n_0 ),
        .I1(\right_edge_taps_r_reg_n_0_[4] ),
        .I2(\tap_cnt_cpt_r_reg_n_0_[3] ),
        .O(\cnt_idel_dec_cpt_r[3]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF28AA2800)) 
    \cnt_idel_dec_cpt_r[4]_i_1 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[29] ),
        .I1(cnt_idel_dec_cpt_r1[4]),
        .I2(\cnt_idel_dec_cpt_r[4]_i_3_n_0 ),
        .I3(found_second_edge_r_reg_n_0),
        .I4(\cnt_idel_dec_cpt_r[4]_i_4_n_0 ),
        .I5(\cnt_idel_dec_cpt_r[4]_i_5_n_0 ),
        .O(cnt_idel_dec_cpt_r[4]));
  (* SOFT_HLUTNM = "soft_lutpair103" *) 
  LUT5 #(
    .INIT(32'hB24D4DB2)) 
    \cnt_idel_dec_cpt_r[4]_i_10 
       (.I0(\right_edge_taps_r_reg_n_0_[4] ),
        .I1(\tap_cnt_cpt_r_reg_n_0_[3] ),
        .I2(\cnt_idel_dec_cpt_r[4]_i_14_n_0 ),
        .I3(\right_edge_taps_r_reg_n_0_[5] ),
        .I4(\tap_cnt_cpt_r_reg_n_0_[4] ),
        .O(\cnt_idel_dec_cpt_r[4]_i_10_n_0 ));
  LUT3 #(
    .INIT(8'h01)) 
    \cnt_idel_dec_cpt_r[4]_i_11 
       (.I0(\cnt_idel_dec_cpt_r_reg_n_0_[0] ),
        .I1(\cnt_idel_dec_cpt_r_reg_n_0_[1] ),
        .I2(\cnt_idel_dec_cpt_r_reg_n_0_[2] ),
        .O(\cnt_idel_dec_cpt_r[4]_i_11_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \cnt_idel_dec_cpt_r[4]_i_12 
       (.I0(\tap_cnt_cpt_r_reg_n_0_[5] ),
        .I1(\first_edge_taps_r_reg_n_0_[5] ),
        .O(\cnt_idel_dec_cpt_r[4]_i_12_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \cnt_idel_dec_cpt_r[4]_i_13 
       (.I0(\tap_cnt_cpt_r_reg_n_0_[4] ),
        .I1(\first_edge_taps_r_reg_n_0_[4] ),
        .O(\cnt_idel_dec_cpt_r[4]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'h2B22FFFF00002B22)) 
    \cnt_idel_dec_cpt_r[4]_i_14 
       (.I0(\right_edge_taps_r_reg_n_0_[2] ),
        .I1(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .I2(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .I3(\right_edge_taps_r_reg_n_0_[1] ),
        .I4(\tap_cnt_cpt_r_reg_n_0_[2] ),
        .I5(\right_edge_taps_r_reg_n_0_[3] ),
        .O(\cnt_idel_dec_cpt_r[4]_i_14_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair131" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \cnt_idel_dec_cpt_r[4]_i_3 
       (.I0(cnt_idel_dec_cpt_r1[3]),
        .I1(cnt_idel_dec_cpt_r1[1]),
        .I2(cnt_idel_dec_cpt_r1[0]),
        .I3(cnt_idel_dec_cpt_r1[2]),
        .O(\cnt_idel_dec_cpt_r[4]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \cnt_idel_dec_cpt_r[4]_i_4 
       (.I0(\cnt_idel_dec_cpt_r_reg[4]_i_8_n_6 ),
        .I1(found_first_edge_r_reg_n_0),
        .I2(\tap_cnt_cpt_r_reg_n_0_[5] ),
        .I3(\cnt_idel_dec_cpt_r[4]_i_9_n_0 ),
        .I4(\cnt_idel_dec_cpt_r[4]_i_10_n_0 ),
        .O(\cnt_idel_dec_cpt_r[4]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hF8F88FF888888888)) 
    \cnt_idel_dec_cpt_r[4]_i_5 
       (.I0(D[4]),
        .I1(p_27_in),
        .I2(\cnt_idel_dec_cpt_r_reg_n_0_[4] ),
        .I3(\cnt_idel_dec_cpt_r[4]_i_11_n_0 ),
        .I4(\cnt_idel_dec_cpt_r_reg_n_0_[3] ),
        .I5(\FSM_onehot_cal1_state_r_reg_n_0_[1] ),
        .O(\cnt_idel_dec_cpt_r[4]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \cnt_idel_dec_cpt_r[4]_i_6 
       (.I0(\second_edge_taps_r_reg_n_0_[5] ),
        .I1(\first_edge_taps_r_reg_n_0_[5] ),
        .O(\cnt_idel_dec_cpt_r[4]_i_6_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \cnt_idel_dec_cpt_r[4]_i_7 
       (.I0(\second_edge_taps_r_reg_n_0_[4] ),
        .I1(\first_edge_taps_r_reg_n_0_[4] ),
        .O(\cnt_idel_dec_cpt_r[4]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \cnt_idel_dec_cpt_r[4]_i_9 
       (.I0(\right_edge_taps_r_reg_n_0_[5] ),
        .I1(\right_edge_taps_r_reg_n_0_[4] ),
        .I2(\right_edge_taps_r_reg_n_0_[1] ),
        .I3(\right_edge_taps_r_reg_n_0_[0] ),
        .I4(\right_edge_taps_r_reg_n_0_[2] ),
        .I5(\right_edge_taps_r_reg_n_0_[3] ),
        .O(\cnt_idel_dec_cpt_r[4]_i_9_n_0 ));
  LUT3 #(
    .INIT(8'hFE)) 
    \cnt_idel_dec_cpt_r[5]_i_1 
       (.I0(mpr_dec_cpt_r),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[1] ),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[29] ),
        .O(\cnt_idel_dec_cpt_r[5]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFAEAEAE)) 
    \cnt_idel_dec_cpt_r[5]_i_2 
       (.I0(\cnt_idel_dec_cpt_r[5]_i_3_n_0 ),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[1] ),
        .I2(\cnt_idel_dec_cpt_r[5]_i_4_n_0 ),
        .I3(p_27_in),
        .I4(D[5]),
        .O(cnt_idel_dec_cpt_r[5]));
  LUT6 #(
    .INIT(64'h8808080808888888)) 
    \cnt_idel_dec_cpt_r[5]_i_3 
       (.I0(\cnt_idel_dec_cpt_r[5]_i_5_n_0 ),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[29] ),
        .I2(found_second_edge_r_reg_n_0),
        .I3(cnt_idel_dec_cpt_r1[4]),
        .I4(\cnt_idel_dec_cpt_r[4]_i_3_n_0 ),
        .I5(\cnt_idel_dec_cpt_r_reg[4]_i_2_n_1 ),
        .O(\cnt_idel_dec_cpt_r[5]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h5555555555555556)) 
    \cnt_idel_dec_cpt_r[5]_i_4 
       (.I0(\cnt_idel_dec_cpt_r_reg_n_0_[5] ),
        .I1(\cnt_idel_dec_cpt_r_reg_n_0_[0] ),
        .I2(\cnt_idel_dec_cpt_r_reg_n_0_[1] ),
        .I3(\cnt_idel_dec_cpt_r_reg_n_0_[2] ),
        .I4(\cnt_idel_dec_cpt_r_reg_n_0_[3] ),
        .I5(\cnt_idel_dec_cpt_r_reg_n_0_[4] ),
        .O(\cnt_idel_dec_cpt_r[5]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAABEBBEEBE)) 
    \cnt_idel_dec_cpt_r[5]_i_5 
       (.I0(found_second_edge_r_reg_n_0),
        .I1(\tap_cnt_cpt_r_reg_n_0_[5] ),
        .I2(\right_edge_taps_r_reg_n_0_[5] ),
        .I3(\tap_cnt_cpt_r_reg_n_0_[4] ),
        .I4(\cnt_idel_dec_cpt_r[5]_i_6_n_0 ),
        .I5(\cnt_idel_dec_cpt_r[4]_i_9_n_0 ),
        .O(\cnt_idel_dec_cpt_r[5]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair103" *) 
  LUT3 #(
    .INIT(8'hB2)) 
    \cnt_idel_dec_cpt_r[5]_i_6 
       (.I0(\cnt_idel_dec_cpt_r[4]_i_14_n_0 ),
        .I1(\tap_cnt_cpt_r_reg_n_0_[3] ),
        .I2(\right_edge_taps_r_reg_n_0_[4] ),
        .O(\cnt_idel_dec_cpt_r[5]_i_6_n_0 ));
  FDRE \cnt_idel_dec_cpt_r_reg[0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\cnt_idel_dec_cpt_r[5]_i_1_n_0 ),
        .D(cnt_idel_dec_cpt_r[0]),
        .Q(\cnt_idel_dec_cpt_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \cnt_idel_dec_cpt_r_reg[1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\cnt_idel_dec_cpt_r[5]_i_1_n_0 ),
        .D(cnt_idel_dec_cpt_r[1]),
        .Q(\cnt_idel_dec_cpt_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \cnt_idel_dec_cpt_r_reg[2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\cnt_idel_dec_cpt_r[5]_i_1_n_0 ),
        .D(cnt_idel_dec_cpt_r[2]),
        .Q(\cnt_idel_dec_cpt_r_reg_n_0_[2] ),
        .R(1'b0));
  CARRY4 \cnt_idel_dec_cpt_r_reg[2]_i_10 
       (.CI(1'b0),
        .CO({\cnt_idel_dec_cpt_r_reg[2]_i_10_n_0 ,\cnt_idel_dec_cpt_r_reg[2]_i_10_n_1 ,\cnt_idel_dec_cpt_r_reg[2]_i_10_n_2 ,\cnt_idel_dec_cpt_r_reg[2]_i_10_n_3 }),
        .CYINIT(1'b1),
        .DI({\tap_cnt_cpt_r_reg_n_0_[3] ,\tap_cnt_cpt_r_reg_n_0_[2] ,\tap_cnt_cpt_r_reg_n_0_[1] ,\tap_cnt_cpt_r_reg_n_0_[0] }),
        .O({\cnt_idel_dec_cpt_r_reg[2]_i_10_n_4 ,\cnt_idel_dec_cpt_r_reg[2]_i_10_n_5 ,\cnt_idel_dec_cpt_r_reg[2]_i_10_n_6 ,\NLW_cnt_idel_dec_cpt_r_reg[2]_i_10_O_UNCONNECTED [0]}),
        .S({\cnt_idel_dec_cpt_r[2]_i_12_n_0 ,\cnt_idel_dec_cpt_r[2]_i_13_n_0 ,\cnt_idel_dec_cpt_r[2]_i_14_n_0 ,\cnt_idel_dec_cpt_r[2]_i_15_n_0 }));
  CARRY4 \cnt_idel_dec_cpt_r_reg[2]_i_2 
       (.CI(1'b0),
        .CO({\cnt_idel_dec_cpt_r_reg[2]_i_2_n_0 ,\cnt_idel_dec_cpt_r_reg[2]_i_2_n_1 ,\cnt_idel_dec_cpt_r_reg[2]_i_2_n_2 ,\cnt_idel_dec_cpt_r_reg[2]_i_2_n_3 }),
        .CYINIT(1'b1),
        .DI({\second_edge_taps_r_reg_n_0_[3] ,\second_edge_taps_r_reg_n_0_[2] ,\second_edge_taps_r_reg_n_0_[1] ,\second_edge_taps_r_reg_n_0_[0] }),
        .O({cnt_idel_dec_cpt_r1[2:0],\NLW_cnt_idel_dec_cpt_r_reg[2]_i_2_O_UNCONNECTED [0]}),
        .S({\cnt_idel_dec_cpt_r[2]_i_6_n_0 ,\cnt_idel_dec_cpt_r[2]_i_7_n_0 ,\cnt_idel_dec_cpt_r[2]_i_8_n_0 ,\cnt_idel_dec_cpt_r[2]_i_9_n_0 }));
  FDRE \cnt_idel_dec_cpt_r_reg[3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\cnt_idel_dec_cpt_r[5]_i_1_n_0 ),
        .D(cnt_idel_dec_cpt_r[3]),
        .Q(\cnt_idel_dec_cpt_r_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \cnt_idel_dec_cpt_r_reg[4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\cnt_idel_dec_cpt_r[5]_i_1_n_0 ),
        .D(cnt_idel_dec_cpt_r[4]),
        .Q(\cnt_idel_dec_cpt_r_reg_n_0_[4] ),
        .R(1'b0));
  CARRY4 \cnt_idel_dec_cpt_r_reg[4]_i_2 
       (.CI(\cnt_idel_dec_cpt_r_reg[2]_i_2_n_0 ),
        .CO({\NLW_cnt_idel_dec_cpt_r_reg[4]_i_2_CO_UNCONNECTED [3],\cnt_idel_dec_cpt_r_reg[4]_i_2_n_1 ,\NLW_cnt_idel_dec_cpt_r_reg[4]_i_2_CO_UNCONNECTED [1],\cnt_idel_dec_cpt_r_reg[4]_i_2_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,\second_edge_taps_r_reg_n_0_[5] ,\second_edge_taps_r_reg_n_0_[4] }),
        .O({\NLW_cnt_idel_dec_cpt_r_reg[4]_i_2_O_UNCONNECTED [3:2],cnt_idel_dec_cpt_r1[4:3]}),
        .S({1'b0,1'b1,\cnt_idel_dec_cpt_r[4]_i_6_n_0 ,\cnt_idel_dec_cpt_r[4]_i_7_n_0 }));
  CARRY4 \cnt_idel_dec_cpt_r_reg[4]_i_8 
       (.CI(\cnt_idel_dec_cpt_r_reg[2]_i_10_n_0 ),
        .CO({\NLW_cnt_idel_dec_cpt_r_reg[4]_i_8_CO_UNCONNECTED [3:1],\cnt_idel_dec_cpt_r_reg[4]_i_8_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,\tap_cnt_cpt_r_reg_n_0_[4] }),
        .O({\NLW_cnt_idel_dec_cpt_r_reg[4]_i_8_O_UNCONNECTED [3:2],\cnt_idel_dec_cpt_r_reg[4]_i_8_n_6 ,\cnt_idel_dec_cpt_r_reg[4]_i_8_n_7 }),
        .S({1'b0,1'b0,\cnt_idel_dec_cpt_r[4]_i_12_n_0 ,\cnt_idel_dec_cpt_r[4]_i_13_n_0 }));
  FDRE \cnt_idel_dec_cpt_r_reg[5] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\cnt_idel_dec_cpt_r[5]_i_1_n_0 ),
        .D(cnt_idel_dec_cpt_r[5]),
        .Q(\cnt_idel_dec_cpt_r_reg_n_0_[5] ),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h3332)) 
    \cnt_shift_r[0]_i_1 
       (.I0(cnt_shift_r_reg[1]),
        .I1(cnt_shift_r_reg[0]),
        .I2(cnt_shift_r_reg[2]),
        .I3(cnt_shift_r_reg[3]),
        .O(p_0_in__2[0]));
  LUT2 #(
    .INIT(4'h6)) 
    \cnt_shift_r[1]_i_1 
       (.I0(cnt_shift_r_reg[0]),
        .I1(cnt_shift_r_reg[1]),
        .O(p_0_in__2[1]));
  (* SOFT_HLUTNM = "soft_lutpair126" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \cnt_shift_r[2]_i_1 
       (.I0(cnt_shift_r_reg[2]),
        .I1(cnt_shift_r_reg[1]),
        .I2(cnt_shift_r_reg[0]),
        .O(p_0_in__2[2]));
  (* SOFT_HLUTNM = "soft_lutpair126" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \cnt_shift_r[3]_i_2 
       (.I0(cnt_shift_r_reg[3]),
        .I1(cnt_shift_r_reg[0]),
        .I2(cnt_shift_r_reg[1]),
        .I3(cnt_shift_r_reg[2]),
        .O(p_0_in__2[3]));
  FDSE \cnt_shift_r_reg[0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(E),
        .D(p_0_in__2[0]),
        .Q(cnt_shift_r_reg[0]),
        .S(\cnt_shift_r_reg[0]_0 ));
  FDRE \cnt_shift_r_reg[1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(E),
        .D(p_0_in__2[1]),
        .Q(cnt_shift_r_reg[1]),
        .R(\cnt_shift_r_reg[0]_0 ));
  FDRE \cnt_shift_r_reg[2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(E),
        .D(p_0_in__2[2]),
        .Q(cnt_shift_r_reg[2]),
        .R(\cnt_shift_r_reg[0]_0 ));
  FDRE \cnt_shift_r_reg[3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(E),
        .D(p_0_in__2[3]),
        .Q(cnt_shift_r_reg[3]),
        .R(\cnt_shift_r_reg[0]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair209" *) 
  LUT3 #(
    .INIT(8'hBF)) 
    \ctl_lane_cnt[2]_i_3 
       (.I0(\done_cnt_reg[2]_0 ),
        .I1(pi_fine_dly_dec_done),
        .I2(dqs_po_dec_done),
        .O(p_1_in));
  LUT5 #(
    .INIT(32'h00008000)) 
    detect_edge_done_r_i_1
       (.I0(pb_detect_edge_done_r[4]),
        .I1(pb_detect_edge_done_r[6]),
        .I2(pb_detect_edge_done_r[0]),
        .I3(pb_detect_edge_done_r[2]),
        .I4(detect_edge_done_r_i_2_n_0),
        .O(detect_edge_done_r_i_1_n_0));
  LUT4 #(
    .INIT(16'h7FFF)) 
    detect_edge_done_r_i_2
       (.I0(pb_detect_edge_done_r[3]),
        .I1(pb_detect_edge_done_r[1]),
        .I2(pb_detect_edge_done_r[7]),
        .I3(pb_detect_edge_done_r[5]),
        .O(detect_edge_done_r_i_2_n_0));
  FDRE detect_edge_done_r_reg
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(detect_edge_done_r_i_1_n_0),
        .Q(detect_edge_done_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000003332)) 
    \done_cnt[0]_i_1 
       (.I0(done_cnt[2]),
        .I1(done_cnt[0]),
        .I2(done_cnt[1]),
        .I3(done_cnt[3]),
        .I4(done_cnt1),
        .I5(\done_cnt_reg[2]_0 ),
        .O(\done_cnt[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair87" *) 
  LUT5 #(
    .INIT(32'hFAAFFAAE)) 
    \done_cnt[1]_i_1 
       (.I0(done_cnt1),
        .I1(done_cnt[3]),
        .I2(done_cnt[1]),
        .I3(done_cnt[0]),
        .I4(done_cnt[2]),
        .O(\done_cnt[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h000000000000A9A8)) 
    \done_cnt[2]_i_1 
       (.I0(done_cnt[2]),
        .I1(done_cnt[0]),
        .I2(done_cnt[1]),
        .I3(done_cnt[3]),
        .I4(done_cnt1),
        .I5(\done_cnt_reg[2]_0 ),
        .O(\done_cnt[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair87" *) 
  LUT5 #(
    .INIT(32'hEEEEEEEA)) 
    \done_cnt[3]_i_1 
       (.I0(done_cnt1),
        .I1(done_cnt[3]),
        .I2(done_cnt[1]),
        .I3(done_cnt[0]),
        .I4(done_cnt[2]),
        .O(\done_cnt[3]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h1F11)) 
    \done_cnt[3]_i_2 
       (.I0(\FSM_onehot_cal1_state_r[5]_i_2_n_0 ),
        .I1(rdlvl_stg1_done_int),
        .I2(\rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0 ),
        .I3(p_0_in541_in),
        .O(done_cnt1));
  FDRE \done_cnt_reg[0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\done_cnt[0]_i_1_n_0 ),
        .Q(done_cnt[0]),
        .R(1'b0));
  FDRE \done_cnt_reg[1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\done_cnt[1]_i_1_n_0 ),
        .Q(done_cnt[1]),
        .R(SR[0]));
  FDRE \done_cnt_reg[2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\done_cnt[2]_i_1_n_0 ),
        .Q(done_cnt[2]),
        .R(1'b0));
  FDRE \done_cnt_reg[3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\done_cnt[3]_i_1_n_0 ),
        .Q(done_cnt[3]),
        .R(SR[0]));
  FDRE dqs_po_dec_done_r1_reg
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(dqs_po_dec_done),
        .Q(dqs_po_dec_done_r1),
        .R(1'b0));
  FDRE dqs_po_dec_done_r2_reg
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(dqs_po_dec_done_r1),
        .Q(dqs_po_dec_done_r2),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hFFFFF222)) 
    fine_dly_dec_done_r1_i_1
       (.I0(pi_cnt_dec_reg_0),
        .I1(fine_dly_dec_done_r1_i_2_n_0),
        .I2(dqs_po_dec_done_r2),
        .I3(\pi_rdval_cnt[5]_i_3_n_0 ),
        .I4(fine_dly_dec_done_r1),
        .O(fine_dly_dec_done_r1_i_1_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFEFF)) 
    fine_dly_dec_done_r1_i_2
       (.I0(pi_rdval_cnt[2]),
        .I1(pi_rdval_cnt[3]),
        .I2(pi_rdval_cnt[1]),
        .I3(pi_rdval_cnt[0]),
        .I4(pi_rdval_cnt[4]),
        .I5(pi_rdval_cnt[5]),
        .O(fine_dly_dec_done_r1_i_2_n_0));
  FDRE fine_dly_dec_done_r1_reg
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(fine_dly_dec_done_r1_i_1_n_0),
        .Q(fine_dly_dec_done_r1),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 [1]));
  FDRE fine_dly_dec_done_r2_reg
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(fine_dly_dec_done_r1),
        .Q(fine_dly_dec_done_r2),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h0000BFAA)) 
    \first_edge_taps_r[5]_i_1 
       (.I0(cal1_prech_req_r),
        .I1(found_first_edge_r_reg_n_0),
        .I2(found_stable_eye_last_r),
        .I3(\first_edge_taps_r[5]_i_3_n_0 ),
        .I4(store_sr_req_pulsed_r),
        .O(\first_edge_taps_r[5]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hBFAA)) 
    \first_edge_taps_r[5]_i_2 
       (.I0(cal1_prech_req_r),
        .I1(found_first_edge_r_reg_n_0),
        .I2(found_stable_eye_last_r),
        .I3(\first_edge_taps_r[5]_i_3_n_0 ),
        .O(\first_edge_taps_r[5]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair125" *) 
  LUT4 #(
    .INIT(16'h0080)) 
    \first_edge_taps_r[5]_i_3 
       (.I0(found_edge_r_reg_n_0),
        .I1(store_sr_req_pulsed_r),
        .I2(detect_edge_done_r),
        .I3(tap_limit_cpt_r),
        .O(\first_edge_taps_r[5]_i_3_n_0 ));
  FDRE \first_edge_taps_r_reg[0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\first_edge_taps_r[5]_i_2_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .Q(\first_edge_taps_r_reg_n_0_[0] ),
        .R(\first_edge_taps_r[5]_i_1_n_0 ));
  FDRE \first_edge_taps_r_reg[1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\first_edge_taps_r[5]_i_2_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .Q(\first_edge_taps_r_reg_n_0_[1] ),
        .R(\first_edge_taps_r[5]_i_1_n_0 ));
  FDRE \first_edge_taps_r_reg[2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\first_edge_taps_r[5]_i_2_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[2] ),
        .Q(\first_edge_taps_r_reg_n_0_[2] ),
        .R(\first_edge_taps_r[5]_i_1_n_0 ));
  FDRE \first_edge_taps_r_reg[3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\first_edge_taps_r[5]_i_2_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[3] ),
        .Q(\first_edge_taps_r_reg_n_0_[3] ),
        .R(\first_edge_taps_r[5]_i_1_n_0 ));
  FDRE \first_edge_taps_r_reg[4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\first_edge_taps_r[5]_i_2_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[4] ),
        .Q(\first_edge_taps_r_reg_n_0_[4] ),
        .R(\first_edge_taps_r[5]_i_1_n_0 ));
  FDRE \first_edge_taps_r_reg[5] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\first_edge_taps_r[5]_i_2_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[5] ),
        .Q(\first_edge_taps_r_reg_n_0_[5] ),
        .R(\first_edge_taps_r[5]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    found_edge_r_i_1
       (.I0(\gen_track_left_edge[3].pb_found_edge_r_reg_n_0_[3] ),
        .I1(\gen_track_left_edge[6].pb_found_edge_r_reg_n_0_[6] ),
        .I2(\gen_track_left_edge[5].pb_found_edge_r_reg_n_0_[5] ),
        .I3(\gen_track_left_edge[7].pb_found_edge_r_reg_n_0_[7] ),
        .I4(found_edge_r_i_2_n_0),
        .O(found_edge_r_i_1_n_0));
  LUT4 #(
    .INIT(16'hFFFE)) 
    found_edge_r_i_2
       (.I0(\gen_track_left_edge[4].pb_found_edge_r_reg_n_0_[4] ),
        .I1(\gen_track_left_edge[0].pb_found_edge_r_reg_n_0_[0] ),
        .I2(\gen_track_left_edge[2].pb_found_edge_r_reg_n_0_[2] ),
        .I3(\gen_track_left_edge[1].pb_found_edge_r_reg_n_0_[1] ),
        .O(found_edge_r_i_2_n_0));
  FDRE found_edge_r_reg
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(found_edge_r_i_1_n_0),
        .Q(found_edge_r_reg_n_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFF555555BA000000)) 
    found_first_edge_r_i_1
       (.I0(cal1_prech_req_r),
        .I1(tap_limit_cpt_r),
        .I2(detect_edge_done_r),
        .I3(store_sr_req_pulsed_r),
        .I4(found_edge_r_reg_n_0),
        .I5(found_first_edge_r_reg_n_0),
        .O(found_first_edge_r_i_1_n_0));
  FDRE found_first_edge_r_reg
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(found_first_edge_r_i_1_n_0),
        .Q(found_first_edge_r_reg_n_0),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 [1]));
  LUT6 #(
    .INIT(64'hF5551555E0000000)) 
    found_second_edge_r_i_1
       (.I0(cal1_prech_req_r),
        .I1(\first_edge_taps_r[5]_i_3_n_0 ),
        .I2(found_first_edge_r_reg_n_0),
        .I3(found_stable_eye_last_r),
        .I4(store_sr_req_pulsed_r),
        .I5(found_second_edge_r_reg_n_0),
        .O(found_second_edge_r_i_1_n_0));
  FDRE found_second_edge_r_reg
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(found_second_edge_r_i_1_n_0),
        .Q(found_second_edge_r_reg_n_0),
        .R(found_second_edge_r_reg_0));
  LUT3 #(
    .INIT(8'hB8)) 
    found_stable_eye_last_r_i_1
       (.I0(found_stable_eye_r_reg_n_0),
        .I1(detect_edge_done_r),
        .I2(found_stable_eye_last_r),
        .O(found_stable_eye_last_r_i_1_n_0));
  FDRE found_stable_eye_last_r_reg
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(found_stable_eye_last_r_i_1_n_0),
        .Q(found_stable_eye_last_r),
        .R(\FSM_onehot_cal1_state_r_reg_n_0_[16] ));
  LUT5 #(
    .INIT(32'h00008000)) 
    found_stable_eye_r_i_1
       (.I0(pb_found_stable_eye_r[2]),
        .I1(pb_found_stable_eye_r[3]),
        .I2(pb_found_stable_eye_r[0]),
        .I3(pb_found_stable_eye_r[1]),
        .I4(found_stable_eye_r_i_2_n_0),
        .O(found_stable_eye_r_i_1_n_0));
  LUT4 #(
    .INIT(16'h7FFF)) 
    found_stable_eye_r_i_2
       (.I0(pb_found_stable_eye_r[5]),
        .I1(pb_found_stable_eye_r[4]),
        .I2(pb_found_stable_eye_r[7]),
        .I3(pb_found_stable_eye_r[6]),
        .O(found_stable_eye_r_i_2_n_0));
  FDRE found_stable_eye_r_reg
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(found_stable_eye_r_i_1_n_0),
        .Q(found_stable_eye_r_reg_n_0),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \gen_byte_sel_div2.byte_sel_cnt[0]_i_1 
       (.I0(\gen_byte_sel_div2.byte_sel_cnt_reg[0] ),
        .I1(rdlvl_stg1_done_int_reg_0),
        .I2(pi_stg2_rdlvl_cnt[0]),
        .I3(\gen_byte_sel_div2.byte_sel_cnt_reg[3]_0 ),
        .I4(\gen_byte_sel_div2.byte_sel_cnt_reg[0]_0 ),
        .O(rdlvl_stg1_done_int_reg_3[0]));
  (* SOFT_HLUTNM = "soft_lutpair219" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_byte_sel_div2.byte_sel_cnt[0]_i_3 
       (.I0(regl_dqs_cnt_r[0]),
        .I1(p_0_in541_in),
        .I2(\cal1_cnt_cpt_r_reg_n_0_[0] ),
        .O(pi_stg2_rdlvl_cnt[0]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \gen_byte_sel_div2.byte_sel_cnt[1]_i_1 
       (.I0(\gen_byte_sel_div2.byte_sel_cnt_reg[1] ),
        .I1(rdlvl_stg1_done_int_reg_0),
        .I2(pi_stg2_rdlvl_cnt[1]),
        .I3(\gen_byte_sel_div2.byte_sel_cnt_reg[3]_0 ),
        .I4(\gen_byte_sel_div2.byte_sel_cnt_reg[1]_0 ),
        .O(rdlvl_stg1_done_int_reg_3[1]));
  (* SOFT_HLUTNM = "soft_lutpair207" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_byte_sel_div2.byte_sel_cnt[1]_i_3 
       (.I0(regl_dqs_cnt_r[1]),
        .I1(p_0_in541_in),
        .I2(\cal1_cnt_cpt_r_reg_n_0_[1] ),
        .O(pi_stg2_rdlvl_cnt[1]));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    \gen_byte_sel_div2.byte_sel_cnt[2]_i_1 
       (.I0(\gen_byte_sel_div2.byte_sel_cnt_reg[2] ),
        .I1(rdlvl_stg1_done_int_reg_0),
        .I2(pi_stg2_rdlvl_cnt[2]),
        .I3(\gen_byte_sel_div2.byte_sel_cnt_reg[3]_0 ),
        .I4(\gen_byte_sel_div2.byte_sel_cnt_reg[2]_0 ),
        .O(rdlvl_stg1_done_int_reg_3[2]));
  (* SOFT_HLUTNM = "soft_lutpair207" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_byte_sel_div2.byte_sel_cnt[2]_i_3 
       (.I0(regl_dqs_cnt_r[2]),
        .I1(p_0_in541_in),
        .I2(\cal1_cnt_cpt_r_reg_n_0_[2] ),
        .O(pi_stg2_rdlvl_cnt[2]));
  LUT6 #(
    .INIT(64'hB888FFFFB8880000)) 
    \gen_byte_sel_div2.byte_sel_cnt[3]_i_3 
       (.I0(\gen_byte_sel_div2.byte_sel_cnt_reg[3] ),
        .I1(rdlvl_stg1_done_int_reg_0),
        .I2(p_0_in541_in),
        .I3(regl_dqs_cnt_r[3]),
        .I4(\gen_byte_sel_div2.byte_sel_cnt_reg[3]_0 ),
        .I5(\gen_byte_sel_div2.byte_sel_cnt_reg[3]_1 ),
        .O(rdlvl_stg1_done_int_reg_3[3]));
  FDRE \gen_mux_rd[0].mux_rd_fall0_r_reg[0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0 ),
        .Q(\gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \gen_mux_rd[0].mux_rd_fall1_r_reg[0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0 ),
        .Q(\gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \gen_mux_rd[0].mux_rd_fall2_r_reg[0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0 ),
        .Q(\gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \gen_mux_rd[0].mux_rd_fall3_r_reg[0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0 ),
        .Q(\gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0] ),
        .R(1'b0));
  LUT3 #(
    .INIT(8'h95)) 
    \gen_mux_rd[0].mux_rd_rise0_r[0]_i_2 
       (.I0(\rd_mux_sel_r_reg_n_0_[2] ),
        .I1(Q[1]),
        .I2(Q[0]),
        .O(\rd_mux_sel_r_reg[2]_0 ));
  FDRE \gen_mux_rd[0].mux_rd_rise0_r_reg[0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ),
        .Q(\gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \gen_mux_rd[0].mux_rd_rise1_r_reg[0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd[0].mux_rd_rise1_r_reg[0]_0 ),
        .Q(\gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \gen_mux_rd[0].mux_rd_rise2_r_reg[0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0 ),
        .Q(\gen_mux_rd[0].mux_rd_rise2_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \gen_mux_rd[0].mux_rd_rise3_r_reg[0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0 ),
        .Q(\gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \gen_mux_rd[1].mux_rd_fall0_r_reg[1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ),
        .Q(\gen_mux_rd[1].mux_rd_fall0_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \gen_mux_rd[1].mux_rd_fall1_r_reg[1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ),
        .Q(\gen_mux_rd[1].mux_rd_fall1_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \gen_mux_rd[1].mux_rd_fall2_r_reg[1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ),
        .Q(\gen_mux_rd[1].mux_rd_fall2_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \gen_mux_rd[1].mux_rd_fall3_r_reg[1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ),
        .Q(\gen_mux_rd[1].mux_rd_fall3_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \gen_mux_rd[1].mux_rd_rise0_r_reg[1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ),
        .Q(\gen_mux_rd[1].mux_rd_rise0_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \gen_mux_rd[1].mux_rd_rise1_r_reg[1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ),
        .Q(\gen_mux_rd[1].mux_rd_rise1_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \gen_mux_rd[1].mux_rd_rise2_r_reg[1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ),
        .Q(\gen_mux_rd[1].mux_rd_rise2_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \gen_mux_rd[1].mux_rd_rise3_r_reg[1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ),
        .Q(\gen_mux_rd[1].mux_rd_rise3_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \gen_mux_rd[2].mux_rd_fall0_r_reg[2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0 ),
        .Q(\gen_mux_rd[2].mux_rd_fall0_r_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \gen_mux_rd[2].mux_rd_fall1_r_reg[2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0 ),
        .Q(\gen_mux_rd[2].mux_rd_fall1_r_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \gen_mux_rd[2].mux_rd_fall2_r_reg[2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0 ),
        .Q(\gen_mux_rd[2].mux_rd_fall2_r_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \gen_mux_rd[2].mux_rd_fall3_r_reg[2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 ),
        .Q(\gen_mux_rd[2].mux_rd_fall3_r_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \gen_mux_rd[2].mux_rd_rise0_r_reg[2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ),
        .Q(\gen_mux_rd[2].mux_rd_rise0_r_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \gen_mux_rd[2].mux_rd_rise1_r_reg[2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0 ),
        .Q(\gen_mux_rd[2].mux_rd_rise1_r_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \gen_mux_rd[2].mux_rd_rise2_r_reg[2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0 ),
        .Q(\gen_mux_rd[2].mux_rd_rise2_r_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \gen_mux_rd[2].mux_rd_rise3_r_reg[2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0 ),
        .Q(\gen_mux_rd[2].mux_rd_rise3_r_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \gen_mux_rd[3].mux_rd_fall0_r_reg[3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ),
        .Q(\gen_mux_rd[3].mux_rd_fall0_r_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \gen_mux_rd[3].mux_rd_fall1_r_reg[3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ),
        .Q(\gen_mux_rd[3].mux_rd_fall1_r_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \gen_mux_rd[3].mux_rd_fall2_r_reg[3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ),
        .Q(\gen_mux_rd[3].mux_rd_fall2_r_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \gen_mux_rd[3].mux_rd_fall3_r_reg[3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ),
        .Q(\gen_mux_rd[3].mux_rd_fall3_r_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \gen_mux_rd[3].mux_rd_rise0_r_reg[3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ),
        .Q(\gen_mux_rd[3].mux_rd_rise0_r_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \gen_mux_rd[3].mux_rd_rise1_r_reg[3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ),
        .Q(\gen_mux_rd[3].mux_rd_rise1_r_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \gen_mux_rd[3].mux_rd_rise2_r_reg[3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ),
        .Q(\gen_mux_rd[3].mux_rd_rise2_r_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \gen_mux_rd[3].mux_rd_rise3_r_reg[3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ),
        .Q(\gen_mux_rd[3].mux_rd_rise3_r_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \gen_mux_rd[4].mux_rd_fall0_r_reg[4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0 ),
        .Q(\gen_mux_rd[4].mux_rd_fall0_r_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \gen_mux_rd[4].mux_rd_fall1_r_reg[4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0 ),
        .Q(\gen_mux_rd[4].mux_rd_fall1_r_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \gen_mux_rd[4].mux_rd_fall2_r_reg[4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0 ),
        .Q(\gen_mux_rd[4].mux_rd_fall2_r_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \gen_mux_rd[4].mux_rd_fall3_r_reg[4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0 ),
        .Q(\gen_mux_rd[4].mux_rd_fall3_r_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \gen_mux_rd[4].mux_rd_rise0_r_reg[4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0 ),
        .Q(\gen_mux_rd[4].mux_rd_rise0_r_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \gen_mux_rd[4].mux_rd_rise1_r_reg[4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0 ),
        .Q(\gen_mux_rd[4].mux_rd_rise1_r_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \gen_mux_rd[4].mux_rd_rise2_r_reg[4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0 ),
        .Q(\gen_mux_rd[4].mux_rd_rise2_r_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \gen_mux_rd[4].mux_rd_rise3_r_reg[4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0 ),
        .Q(\gen_mux_rd[4].mux_rd_rise3_r_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \gen_mux_rd[5].mux_rd_fall0_r_reg[5] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ),
        .Q(\gen_mux_rd[5].mux_rd_fall0_r_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \gen_mux_rd[5].mux_rd_fall1_r_reg[5] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ),
        .Q(\gen_mux_rd[5].mux_rd_fall1_r_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \gen_mux_rd[5].mux_rd_fall2_r_reg[5] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ),
        .Q(\gen_mux_rd[5].mux_rd_fall2_r_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \gen_mux_rd[5].mux_rd_fall3_r_reg[5] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ),
        .Q(\gen_mux_rd[5].mux_rd_fall3_r_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \gen_mux_rd[5].mux_rd_rise0_r_reg[5] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0 ),
        .Q(\gen_mux_rd[5].mux_rd_rise0_r_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \gen_mux_rd[5].mux_rd_rise1_r_reg[5] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ),
        .Q(\gen_mux_rd[5].mux_rd_rise1_r_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \gen_mux_rd[5].mux_rd_rise2_r_reg[5] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ),
        .Q(\gen_mux_rd[5].mux_rd_rise2_r_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \gen_mux_rd[5].mux_rd_rise3_r_reg[5] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ),
        .Q(\gen_mux_rd[5].mux_rd_rise3_r_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \gen_mux_rd[6].mux_rd_fall0_r_reg[6] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0 ),
        .Q(\gen_mux_rd[6].mux_rd_fall0_r_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \gen_mux_rd[6].mux_rd_fall1_r_reg[6] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0 ),
        .Q(\gen_mux_rd[6].mux_rd_fall1_r_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \gen_mux_rd[6].mux_rd_fall2_r_reg[6] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0 ),
        .Q(\gen_mux_rd[6].mux_rd_fall2_r_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \gen_mux_rd[6].mux_rd_fall3_r_reg[6] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0 ),
        .Q(\gen_mux_rd[6].mux_rd_fall3_r_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \gen_mux_rd[6].mux_rd_rise0_r_reg[6] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0 ),
        .Q(\gen_mux_rd[6].mux_rd_rise0_r_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \gen_mux_rd[6].mux_rd_rise1_r_reg[6] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0 ),
        .Q(\gen_mux_rd[6].mux_rd_rise1_r_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \gen_mux_rd[6].mux_rd_rise2_r_reg[6] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0 ),
        .Q(\gen_mux_rd[6].mux_rd_rise2_r_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \gen_mux_rd[6].mux_rd_rise3_r_reg[6] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0 ),
        .Q(\gen_mux_rd[6].mux_rd_rise3_r_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \gen_mux_rd[7].mux_rd_fall0_r_reg[7] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ),
        .Q(\gen_mux_rd[7].mux_rd_fall0_r_reg_n_0_[7] ),
        .R(1'b0));
  FDRE \gen_mux_rd[7].mux_rd_fall1_r_reg[7] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ),
        .Q(\gen_mux_rd[7].mux_rd_fall1_r_reg_n_0_[7] ),
        .R(1'b0));
  FDRE \gen_mux_rd[7].mux_rd_fall2_r_reg[7] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ),
        .Q(\gen_mux_rd[7].mux_rd_fall2_r_reg_n_0_[7] ),
        .R(1'b0));
  FDRE \gen_mux_rd[7].mux_rd_fall3_r_reg[7] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ),
        .Q(\gen_mux_rd[7].mux_rd_fall3_r_reg_n_0_[7] ),
        .R(1'b0));
  FDRE \gen_mux_rd[7].mux_rd_rise0_r_reg[7] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0 ),
        .Q(\gen_mux_rd[7].mux_rd_rise0_r_reg_n_0_[7] ),
        .R(1'b0));
  FDRE \gen_mux_rd[7].mux_rd_rise1_r_reg[7] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ),
        .Q(\gen_mux_rd[7].mux_rd_rise1_r_reg_n_0_[7] ),
        .R(1'b0));
  FDRE \gen_mux_rd[7].mux_rd_rise2_r_reg[7] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ),
        .Q(\gen_mux_rd[7].mux_rd_rise2_r_reg_n_0_[7] ),
        .R(1'b0));
  FDRE \gen_mux_rd[7].mux_rd_rise3_r_reg[7] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ),
        .Q(\gen_mux_rd[7].mux_rd_rise3_r_reg_n_0_[7] ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[0].old_sr_fall0_r_reg[0][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_95 ),
        .Q(\gen_old_sr_div4.gen_old_sr[0].old_sr_fall0_r_reg[0]_191 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[0].old_sr_fall1_r_reg[0][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_71 ),
        .Q(\gen_old_sr_div4.gen_old_sr[0].old_sr_fall1_r_reg[0]_207 ),
        .R(1'b0));
  LUT2 #(
    .INIT(4'h8)) 
    \gen_old_sr_div4.gen_old_sr[0].old_sr_fall2_r[0][0]_i_1 
       (.I0(store_sr_r_reg_n_0),
        .I1(sr_valid_r_reg_n_0),
        .O(store_sr_r0));
  FDRE \gen_old_sr_div4.gen_old_sr[0].old_sr_fall2_r_reg[0][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_79 ),
        .Q(\gen_old_sr_div4.gen_old_sr[0].old_sr_fall2_r_reg[0]_175 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[0].old_sr_fall3_r_reg[0][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_55 ),
        .Q(\gen_old_sr_div4.gen_old_sr[0].old_sr_fall3_r_reg[0]_183 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[0].old_sr_rise0_r_reg[0][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_47 ),
        .Q(\gen_old_sr_div4.gen_old_sr[0].old_sr_rise0_r_reg[0]_223 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[0].old_sr_rise1_r_reg[0][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_87 ),
        .Q(\gen_old_sr_div4.gen_old_sr[0].old_sr_rise1_r_reg[0]_199 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[0].old_sr_rise2_r_reg[0][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_63 ),
        .Q(\gen_old_sr_div4.gen_old_sr[0].old_sr_rise2_r_reg[0]_215 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[0].old_sr_rise3_r_reg[0][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_103 ),
        .Q(\gen_old_sr_div4.gen_old_sr[0].old_sr_rise3_r_reg[0]_231 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall0_r_reg[0][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_95 ),
        .Q(\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall0_r_reg[0]_143 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall1_r_reg[0][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_71 ),
        .Q(\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall1_r_reg[0]_119 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall2_r_reg[0][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_79 ),
        .Q(\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall2_r_reg[0]_127 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[0].prev_sr_fall3_r_reg[0][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_55 ),
        .Q(\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall3_r_reg[0]_151 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise0_r_reg[0][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_47 ),
        .Q(\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise0_r_reg[0]_159 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise1_r_reg[0][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_87 ),
        .Q(\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise1_r_reg[0]_111 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise2_r_reg[0][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_63 ),
        .Q(\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise2_r_reg[0]_135 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[0].prev_sr_rise3_r_reg[0][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_103 ),
        .Q(\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise3_r_reg[0]_167 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[1].old_sr_fall0_r_reg[1][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_96 ),
        .Q(\gen_old_sr_div4.gen_old_sr[1].old_sr_fall0_r_reg[1]_192 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[1].old_sr_fall1_r_reg[1][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_72 ),
        .Q(\gen_old_sr_div4.gen_old_sr[1].old_sr_fall1_r_reg[1]_208 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[1].old_sr_fall2_r_reg[1][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_80 ),
        .Q(\gen_old_sr_div4.gen_old_sr[1].old_sr_fall2_r_reg[1]_176 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[1].old_sr_fall3_r_reg[1][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_56 ),
        .Q(\gen_old_sr_div4.gen_old_sr[1].old_sr_fall3_r_reg[1]_184 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[1].old_sr_rise0_r_reg[1][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_48 ),
        .Q(\gen_old_sr_div4.gen_old_sr[1].old_sr_rise0_r_reg[1]_224 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[1].old_sr_rise1_r_reg[1][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_88 ),
        .Q(\gen_old_sr_div4.gen_old_sr[1].old_sr_rise1_r_reg[1]_200 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[1].old_sr_rise2_r_reg[1][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_64 ),
        .Q(\gen_old_sr_div4.gen_old_sr[1].old_sr_rise2_r_reg[1]_216 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[1].old_sr_rise3_r_reg[1][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_104 ),
        .Q(\gen_old_sr_div4.gen_old_sr[1].old_sr_rise3_r_reg[1]_232 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall0_r_reg[1][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_96 ),
        .Q(\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall0_r_reg[1]_144 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall1_r_reg[1][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_72 ),
        .Q(\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall1_r_reg[1]_120 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall2_r_reg[1][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_80 ),
        .Q(\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall2_r_reg[1]_128 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[1].prev_sr_fall3_r_reg[1][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_56 ),
        .Q(\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall3_r_reg[1]_152 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise0_r_reg[1][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_48 ),
        .Q(\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise0_r_reg[1]_160 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise1_r_reg[1][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_88 ),
        .Q(\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise1_r_reg[1]_112 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise2_r_reg[1][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_64 ),
        .Q(\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise2_r_reg[1]_136 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[1].prev_sr_rise3_r_reg[1][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_104 ),
        .Q(\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise3_r_reg[1]_168 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[2].old_sr_fall0_r_reg[2][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_97 ),
        .Q(\gen_old_sr_div4.gen_old_sr[2].old_sr_fall0_r_reg[2]_193 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[2].old_sr_fall1_r_reg[2][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_73 ),
        .Q(\gen_old_sr_div4.gen_old_sr[2].old_sr_fall1_r_reg[2]_209 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[2].old_sr_fall2_r_reg[2][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_81 ),
        .Q(\gen_old_sr_div4.gen_old_sr[2].old_sr_fall2_r_reg[2]_177 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[2].old_sr_fall3_r_reg[2][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_57 ),
        .Q(\gen_old_sr_div4.gen_old_sr[2].old_sr_fall3_r_reg[2]_185 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[2].old_sr_rise0_r_reg[2][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_49 ),
        .Q(\gen_old_sr_div4.gen_old_sr[2].old_sr_rise0_r_reg[2]_225 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[2].old_sr_rise1_r_reg[2][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_89 ),
        .Q(\gen_old_sr_div4.gen_old_sr[2].old_sr_rise1_r_reg[2]_201 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[2].old_sr_rise2_r_reg[2][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_65 ),
        .Q(\gen_old_sr_div4.gen_old_sr[2].old_sr_rise2_r_reg[2]_217 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[2].old_sr_rise3_r_reg[2][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_105 ),
        .Q(\gen_old_sr_div4.gen_old_sr[2].old_sr_rise3_r_reg[2]_233 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall0_r_reg[2][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_97 ),
        .Q(\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall0_r_reg[2]_145 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall1_r_reg[2][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_73 ),
        .Q(\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall1_r_reg[2]_121 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall2_r_reg[2][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_81 ),
        .Q(\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall2_r_reg[2]_129 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[2].prev_sr_fall3_r_reg[2][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_57 ),
        .Q(\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall3_r_reg[2]_153 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise0_r_reg[2][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_49 ),
        .Q(\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise0_r_reg[2]_161 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise1_r_reg[2][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_89 ),
        .Q(\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise1_r_reg[2]_113 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise2_r_reg[2][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_65 ),
        .Q(\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise2_r_reg[2]_137 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[2].prev_sr_rise3_r_reg[2][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_105 ),
        .Q(\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise3_r_reg[2]_169 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[3].old_sr_fall0_r_reg[3][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_98 ),
        .Q(\gen_old_sr_div4.gen_old_sr[3].old_sr_fall0_r_reg[3]_194 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[3].old_sr_fall1_r_reg[3][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_74 ),
        .Q(\gen_old_sr_div4.gen_old_sr[3].old_sr_fall1_r_reg[3]_210 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[3].old_sr_fall2_r_reg[3][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_82 ),
        .Q(\gen_old_sr_div4.gen_old_sr[3].old_sr_fall2_r_reg[3]_178 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[3].old_sr_fall3_r_reg[3][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_58 ),
        .Q(\gen_old_sr_div4.gen_old_sr[3].old_sr_fall3_r_reg[3]_186 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[3].old_sr_rise0_r_reg[3][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_50 ),
        .Q(\gen_old_sr_div4.gen_old_sr[3].old_sr_rise0_r_reg[3]_226 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[3].old_sr_rise1_r_reg[3][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_90 ),
        .Q(\gen_old_sr_div4.gen_old_sr[3].old_sr_rise1_r_reg[3]_202 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[3].old_sr_rise2_r_reg[3][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_66 ),
        .Q(\gen_old_sr_div4.gen_old_sr[3].old_sr_rise2_r_reg[3]_218 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[3].old_sr_rise3_r_reg[3][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_106 ),
        .Q(\gen_old_sr_div4.gen_old_sr[3].old_sr_rise3_r_reg[3]_234 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall0_r_reg[3][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_98 ),
        .Q(\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall0_r_reg[3]_146 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall1_r_reg[3][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_74 ),
        .Q(\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall1_r_reg[3]_122 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall2_r_reg[3][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_82 ),
        .Q(\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall2_r_reg[3]_130 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[3].prev_sr_fall3_r_reg[3][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_58 ),
        .Q(\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall3_r_reg[3]_154 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise0_r_reg[3][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_50 ),
        .Q(\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise0_r_reg[3]_162 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise1_r_reg[3][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_90 ),
        .Q(\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise1_r_reg[3]_114 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise2_r_reg[3][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_66 ),
        .Q(\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise2_r_reg[3]_138 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[3].prev_sr_rise3_r_reg[3][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_106 ),
        .Q(\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise3_r_reg[3]_170 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[4].old_sr_fall0_r_reg[4][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_99 ),
        .Q(\gen_old_sr_div4.gen_old_sr[4].old_sr_fall0_r_reg[4]_195 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[4].old_sr_fall1_r_reg[4][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_75 ),
        .Q(\gen_old_sr_div4.gen_old_sr[4].old_sr_fall1_r_reg[4]_211 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[4].old_sr_fall2_r_reg[4][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_83 ),
        .Q(\gen_old_sr_div4.gen_old_sr[4].old_sr_fall2_r_reg[4]_179 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[4].old_sr_fall3_r_reg[4][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_59 ),
        .Q(\gen_old_sr_div4.gen_old_sr[4].old_sr_fall3_r_reg[4]_187 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[4].old_sr_rise0_r_reg[4][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_51 ),
        .Q(\gen_old_sr_div4.gen_old_sr[4].old_sr_rise0_r_reg[4]_227 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[4].old_sr_rise1_r_reg[4][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_91 ),
        .Q(\gen_old_sr_div4.gen_old_sr[4].old_sr_rise1_r_reg[4]_203 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[4].old_sr_rise2_r_reg[4][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_67 ),
        .Q(\gen_old_sr_div4.gen_old_sr[4].old_sr_rise2_r_reg[4]_219 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[4].old_sr_rise3_r_reg[4][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_107 ),
        .Q(\gen_old_sr_div4.gen_old_sr[4].old_sr_rise3_r_reg[4]_235 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall0_r_reg[4][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_99 ),
        .Q(\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall0_r_reg[4]_147 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall1_r_reg[4][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_75 ),
        .Q(\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall1_r_reg[4]_123 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall2_r_reg[4][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_83 ),
        .Q(\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall2_r_reg[4]_131 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[4].prev_sr_fall3_r_reg[4][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_59 ),
        .Q(\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall3_r_reg[4]_155 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise0_r_reg[4][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_51 ),
        .Q(\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise0_r_reg[4]_163 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise1_r_reg[4][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_91 ),
        .Q(\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise1_r_reg[4]_115 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise2_r_reg[4][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_67 ),
        .Q(\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise2_r_reg[4]_139 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[4].prev_sr_rise3_r_reg[4][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_107 ),
        .Q(\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise3_r_reg[4]_171 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[5].old_sr_fall0_r_reg[5][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_100 ),
        .Q(\gen_old_sr_div4.gen_old_sr[5].old_sr_fall0_r_reg[5]_196 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[5].old_sr_fall1_r_reg[5][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_76 ),
        .Q(\gen_old_sr_div4.gen_old_sr[5].old_sr_fall1_r_reg[5]_212 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[5].old_sr_fall2_r_reg[5][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_84 ),
        .Q(\gen_old_sr_div4.gen_old_sr[5].old_sr_fall2_r_reg[5]_180 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[5].old_sr_fall3_r_reg[5][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_60 ),
        .Q(\gen_old_sr_div4.gen_old_sr[5].old_sr_fall3_r_reg[5]_188 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[5].old_sr_rise0_r_reg[5][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_52 ),
        .Q(\gen_old_sr_div4.gen_old_sr[5].old_sr_rise0_r_reg[5]_228 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[5].old_sr_rise1_r_reg[5][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_92 ),
        .Q(\gen_old_sr_div4.gen_old_sr[5].old_sr_rise1_r_reg[5]_204 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[5].old_sr_rise2_r_reg[5][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_68 ),
        .Q(\gen_old_sr_div4.gen_old_sr[5].old_sr_rise2_r_reg[5]_220 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[5].old_sr_rise3_r_reg[5][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_108 ),
        .Q(\gen_old_sr_div4.gen_old_sr[5].old_sr_rise3_r_reg[5]_236 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall0_r_reg[5][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_100 ),
        .Q(\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall0_r_reg[5]_148 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall1_r_reg[5][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_76 ),
        .Q(\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall1_r_reg[5]_124 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall2_r_reg[5][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_84 ),
        .Q(\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall2_r_reg[5]_132 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[5].prev_sr_fall3_r_reg[5][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_60 ),
        .Q(\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall3_r_reg[5]_156 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise0_r_reg[5][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_52 ),
        .Q(\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise0_r_reg[5]_164 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise1_r_reg[5][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_92 ),
        .Q(\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise1_r_reg[5]_116 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise2_r_reg[5][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_68 ),
        .Q(\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise2_r_reg[5]_140 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[5].prev_sr_rise3_r_reg[5][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_108 ),
        .Q(\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise3_r_reg[5]_172 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[6].old_sr_fall0_r_reg[6][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_101 ),
        .Q(\gen_old_sr_div4.gen_old_sr[6].old_sr_fall0_r_reg[6]_197 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[6].old_sr_fall1_r_reg[6][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_77 ),
        .Q(\gen_old_sr_div4.gen_old_sr[6].old_sr_fall1_r_reg[6]_213 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[6].old_sr_fall2_r_reg[6][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_85 ),
        .Q(\gen_old_sr_div4.gen_old_sr[6].old_sr_fall2_r_reg[6]_181 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[6].old_sr_fall3_r_reg[6][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_61 ),
        .Q(\gen_old_sr_div4.gen_old_sr[6].old_sr_fall3_r_reg[6]_189 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[6].old_sr_rise0_r_reg[6][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_53 ),
        .Q(\gen_old_sr_div4.gen_old_sr[6].old_sr_rise0_r_reg[6]_229 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[6].old_sr_rise1_r_reg[6][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_93 ),
        .Q(\gen_old_sr_div4.gen_old_sr[6].old_sr_rise1_r_reg[6]_205 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[6].old_sr_rise2_r_reg[6][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_69 ),
        .Q(\gen_old_sr_div4.gen_old_sr[6].old_sr_rise2_r_reg[6]_221 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[6].old_sr_rise3_r_reg[6][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_109 ),
        .Q(\gen_old_sr_div4.gen_old_sr[6].old_sr_rise3_r_reg[6]_237 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall0_r_reg[6][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_101 ),
        .Q(\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall0_r_reg[6]_149 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall1_r_reg[6][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_77 ),
        .Q(\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall1_r_reg[6]_125 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall2_r_reg[6][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_85 ),
        .Q(\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall2_r_reg[6]_133 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[6].prev_sr_fall3_r_reg[6][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_61 ),
        .Q(\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall3_r_reg[6]_157 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise0_r_reg[6][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_53 ),
        .Q(\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise0_r_reg[6]_165 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise1_r_reg[6][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_93 ),
        .Q(\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise1_r_reg[6]_117 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise2_r_reg[6][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_69 ),
        .Q(\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise2_r_reg[6]_141 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[6].prev_sr_rise3_r_reg[6][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_109 ),
        .Q(\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise3_r_reg[6]_173 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[7].old_sr_fall0_r_reg[7][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_102 ),
        .Q(\gen_old_sr_div4.gen_old_sr[7].old_sr_fall0_r_reg[7]_198 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[7].old_sr_fall1_r_reg[7][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_78 ),
        .Q(\gen_old_sr_div4.gen_old_sr[7].old_sr_fall1_r_reg[7]_214 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[7].old_sr_fall2_r_reg[7][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_86 ),
        .Q(\gen_old_sr_div4.gen_old_sr[7].old_sr_fall2_r_reg[7]_182 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[7].old_sr_fall3_r_reg[7][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_62 ),
        .Q(\gen_old_sr_div4.gen_old_sr[7].old_sr_fall3_r_reg[7]_190 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[7].old_sr_rise0_r_reg[7][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_54 ),
        .Q(\gen_old_sr_div4.gen_old_sr[7].old_sr_rise0_r_reg[7]_230 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[7].old_sr_rise1_r_reg[7][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_94 ),
        .Q(\gen_old_sr_div4.gen_old_sr[7].old_sr_rise1_r_reg[7]_206 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[7].old_sr_rise2_r_reg[7][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_70 ),
        .Q(\gen_old_sr_div4.gen_old_sr[7].old_sr_rise2_r_reg[7]_222 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[7].old_sr_rise3_r_reg[7][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(store_sr_r0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_110 ),
        .Q(\gen_old_sr_div4.gen_old_sr[7].old_sr_rise3_r_reg[7]_238 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall0_r_reg[7][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_102 ),
        .Q(\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall0_r_reg[7]_150 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall1_r_reg[7][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_78 ),
        .Q(\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall1_r_reg[7]_126 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall2_r_reg[7][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_86 ),
        .Q(\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall2_r_reg[7]_134 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[7].prev_sr_fall3_r_reg[7][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_62 ),
        .Q(\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall3_r_reg[7]_158 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise0_r_reg[7][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_54 ),
        .Q(\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise0_r_reg[7]_166 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise1_r_reg[7][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_94 ),
        .Q(\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise1_r_reg[7]_118 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise2_r_reg[7][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_70 ),
        .Q(\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise2_r_reg[7]_142 ),
        .R(1'b0));
  FDRE \gen_old_sr_div4.gen_old_sr[7].prev_sr_rise3_r_reg[7][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r_reg_n_0),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_110 ),
        .Q(\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise3_r_reg[7]_174 ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall0_r_reg[0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_95 ),
        .Q(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall0_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r[0]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_71 ),
        .O(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r[0]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r_reg[0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r[0]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r[0]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_79 ),
        .O(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r[0]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r_reg[0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall2_r[0]_i_1_n_0 ),
        .Q(pat0_match_fall2_r[0]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall3_r_reg[0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_55 ),
        .Q(pat0_match_fall3_r[0]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise0_r_reg[0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_47 ),
        .Q(pat0_match_rise0_r[0]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r[0]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_87 ),
        .O(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r[0]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r_reg[0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise1_r[0]_i_1_n_0 ),
        .Q(pat0_match_rise1_r[0]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise2_r_reg[0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_63 ),
        .Q(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise2_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise3_r[0]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_103 ),
        .O(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise3_r[0]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise3_r_reg[0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise3_r[0]_i_1_n_0 ),
        .Q(idel_pat0_match_rise3_r[0]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall1_r_reg[0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_71 ),
        .Q(pat0_match_fall1_r[0]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r[0]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_55 ),
        .O(\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r[0]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r_reg[0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r[0]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r[0]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_47 ),
        .O(\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r[0]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r_reg[0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r[0]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise1_r_reg[0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_87 ),
        .Q(idel_pat1_match_rise1_r[0]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r[0]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_63 ),
        .O(\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r[0]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r_reg[0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise2_r[0]_i_1_n_0 ),
        .Q(pat0_match_rise2_r[0]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise3_r_reg[0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_103 ),
        .Q(pat0_match_rise3_r[0]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[0].pat0_match_fall0_r[0]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_95 ),
        .O(\gen_pat_match_div4.gen_pat_match[0].pat0_match_fall0_r[0]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[0].pat0_match_fall0_r_reg[0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[0].pat0_match_fall0_r[0]_i_1_n_0 ),
        .Q(pat0_match_fall0_r[0]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[0].pat1_match_fall2_r_reg[0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_79 ),
        .Q(\gen_pat_match_div4.gen_pat_match[0].pat1_match_fall2_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall0_r_reg[1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_96 ),
        .Q(pat0_match_fall0_r[1]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r[1]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_72 ),
        .O(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r[1]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r_reg[1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall1_r[1]_i_1_n_0 ),
        .Q(pat0_match_fall1_r[1]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall2_r_reg[1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_80 ),
        .Q(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall2_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall3_r_reg[1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_56 ),
        .Q(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall3_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r[1]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_48 ),
        .O(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r[1]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r_reg[1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r[1]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise1_r_reg[1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_88 ),
        .Q(idel_pat1_match_rise1_r[1]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r[1]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_64 ),
        .O(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r[1]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r_reg[1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r[1]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r[1]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_104 ),
        .O(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r[1]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r_reg[1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise3_r[1]_i_1_n_0 ),
        .Q(idel_pat0_match_rise3_r[1]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r[1]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_96 ),
        .O(\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r[1]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r_reg[1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r[1]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall1_r_reg[1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_72 ),
        .Q(\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall1_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r[1]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_80 ),
        .O(\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r[1]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r_reg[1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall2_r[1]_i_1_n_0 ),
        .Q(pat0_match_fall2_r[1]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_rise2_r_reg[1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_64 ),
        .Q(pat0_match_rise2_r[1]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r[1]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_56 ),
        .O(\gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r[1]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r_reg[1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[1].pat0_match_fall3_r[1]_i_1_n_0 ),
        .Q(pat0_match_fall3_r[1]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[1].pat0_match_rise0_r_reg[1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_48 ),
        .Q(pat0_match_rise0_r[1]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[1].pat0_match_rise1_r[1]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_88 ),
        .O(\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise1_r[1]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[1].pat0_match_rise1_r_reg[1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[1].pat0_match_rise1_r[1]_i_1_n_0 ),
        .Q(pat0_match_rise1_r[1]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[1].pat0_match_rise3_r_reg[1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_104 ),
        .Q(pat0_match_rise3_r[1]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall0_r_reg[2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_97 ),
        .Q(pat0_match_fall0_r[2]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall1_r_reg[2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_73 ),
        .Q(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall1_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r[2]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_81 ),
        .O(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r[2]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r_reg[2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r[2]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r[2]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_57 ),
        .O(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r[2]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r_reg[2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall3_r[2]_i_1_n_0 ),
        .Q(pat0_match_fall3_r[2]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r[2]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_49 ),
        .O(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r[2]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r_reg[2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r[2]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise1_r_reg[2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_89 ),
        .Q(pat0_match_rise1_r[2]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r[2]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_65 ),
        .O(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r[2]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r_reg[2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise2_r[2]_i_1_n_0 ),
        .Q(pat0_match_rise2_r[2]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise3_r_reg[2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_105 ),
        .Q(idel_pat0_match_rise3_r[2]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r[2]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_97 ),
        .O(\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r[2]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r_reg[2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r[2]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall2_r_reg[2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_81 ),
        .Q(pat0_match_fall2_r[2]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise0_r_reg[2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_49 ),
        .Q(pat0_match_rise0_r[2]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise1_r[2]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_89 ),
        .O(\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise1_r[2]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise1_r_reg[2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise1_r[2]_i_1_n_0 ),
        .Q(idel_pat1_match_rise1_r[2]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise2_r_reg[2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_65 ),
        .Q(\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise2_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r[2]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_105 ),
        .O(\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r[2]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r_reg[2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise3_r[2]_i_1_n_0 ),
        .Q(pat0_match_rise3_r[2]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[2].pat0_match_fall1_r[2]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_73 ),
        .O(\gen_pat_match_div4.gen_pat_match[2].pat0_match_fall1_r[2]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[2].pat0_match_fall1_r_reg[2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[2].pat0_match_fall1_r[2]_i_1_n_0 ),
        .Q(pat0_match_fall1_r[2]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[2].pat1_match_fall3_r_reg[2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_57 ),
        .Q(\gen_pat_match_div4.gen_pat_match[2].pat1_match_fall3_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r[3]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_98 ),
        .O(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r[3]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r_reg[3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r[3]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall1_r_reg[3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_74 ),
        .Q(pat0_match_fall1_r[3]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r[3]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_82 ),
        .O(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r[3]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r_reg[3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall2_r[3]_i_1_n_0 ),
        .Q(pat0_match_fall2_r[3]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall3_r_reg[3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_58 ),
        .Q(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall3_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r[3]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_50 ),
        .O(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r[3]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r_reg[3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise0_r[3]_i_1_n_0 ),
        .Q(pat0_match_rise0_r[3]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise1_r_reg[3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_90 ),
        .Q(pat0_match_rise1_r[3]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise2_r_reg[3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_66 ),
        .Q(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise2_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise3_r[3]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_106 ),
        .O(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise3_r[3]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise3_r_reg[3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise3_r[3]_i_1_n_0 ),
        .Q(idel_pat0_match_rise3_r[3]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall0_r_reg[3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_98 ),
        .Q(pat0_match_fall0_r[3]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r[3]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_74 ),
        .O(\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r[3]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r_reg[3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r[3]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall2_r_reg[3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_82 ),
        .Q(\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall2_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r[3]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_58 ),
        .O(\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r[3]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r_reg[3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall3_r[3]_i_1_n_0 ),
        .Q(pat0_match_fall3_r[3]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r[3]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_90 ),
        .O(\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r[3]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r_reg[3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise1_r[3]_i_1_n_0 ),
        .Q(idel_pat1_match_rise1_r[3]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_rise3_r_reg[3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_106 ),
        .Q(pat0_match_rise3_r[3]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[3].pat0_match_rise2_r[3]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_66 ),
        .O(\gen_pat_match_div4.gen_pat_match[3].pat0_match_rise2_r[3]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[3].pat0_match_rise2_r_reg[3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[3].pat0_match_rise2_r[3]_i_1_n_0 ),
        .Q(pat0_match_rise2_r[3]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[3].pat1_match_rise0_r_reg[3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_50 ),
        .Q(\gen_pat_match_div4.gen_pat_match[3].pat1_match_rise0_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall0_r_reg[4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_99 ),
        .Q(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall0_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r[4]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_75 ),
        .O(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r[4]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r_reg[4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r[4]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r[4]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_83 ),
        .O(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r[4]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r_reg[4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall2_r[4]_i_1_n_0 ),
        .Q(pat0_match_fall2_r[4]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall3_r_reg[4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_59 ),
        .Q(pat0_match_fall3_r[4]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise0_r_reg[4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_51 ),
        .Q(pat0_match_rise0_r[4]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r[4]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_91 ),
        .O(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r[4]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r_reg[4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise1_r[4]_i_1_n_0 ),
        .Q(pat0_match_rise1_r[4]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise2_r_reg[4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_67 ),
        .Q(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise2_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise3_r[4]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_107 ),
        .O(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise3_r[4]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise3_r_reg[4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise3_r[4]_i_1_n_0 ),
        .Q(idel_pat0_match_rise3_r[4]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall1_r_reg[4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_75 ),
        .Q(pat0_match_fall1_r[4]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r[4]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_59 ),
        .O(\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r[4]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r_reg[4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r[4]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r[4]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_51 ),
        .O(\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r[4]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r_reg[4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r[4]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise1_r_reg[4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_91 ),
        .Q(idel_pat1_match_rise1_r[4]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r[4]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_67 ),
        .O(\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r[4]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r_reg[4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise2_r[4]_i_1_n_0 ),
        .Q(pat0_match_rise2_r[4]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise3_r_reg[4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_107 ),
        .Q(pat0_match_rise3_r[4]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[4].pat0_match_fall0_r[4]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_99 ),
        .O(\gen_pat_match_div4.gen_pat_match[4].pat0_match_fall0_r[4]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[4].pat0_match_fall0_r_reg[4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[4].pat0_match_fall0_r[4]_i_1_n_0 ),
        .Q(pat0_match_fall0_r[4]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[4].pat1_match_fall2_r_reg[4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_83 ),
        .Q(\gen_pat_match_div4.gen_pat_match[4].pat1_match_fall2_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall0_r_reg[5] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_100 ),
        .Q(pat0_match_fall0_r[5]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r[5]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_76 ),
        .O(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r[5]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r_reg[5] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall1_r[5]_i_1_n_0 ),
        .Q(pat0_match_fall1_r[5]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall2_r_reg[5] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_84 ),
        .Q(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall2_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall3_r_reg[5] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_60 ),
        .Q(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall3_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r[5]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_52 ),
        .O(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r[5]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r_reg[5] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r[5]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise1_r_reg[5] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_92 ),
        .Q(idel_pat1_match_rise1_r[5]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r[5]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_68 ),
        .O(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r[5]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r_reg[5] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r[5]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r[5]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_108 ),
        .O(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r[5]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r_reg[5] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise3_r[5]_i_1_n_0 ),
        .Q(idel_pat0_match_rise3_r[5]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r[5]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_100 ),
        .O(\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r[5]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r_reg[5] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r[5]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall1_r_reg[5] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_76 ),
        .Q(\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall1_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r[5]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_84 ),
        .O(\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r[5]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r_reg[5] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall2_r[5]_i_1_n_0 ),
        .Q(pat0_match_fall2_r[5]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_rise2_r_reg[5] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_68 ),
        .Q(pat0_match_rise2_r[5]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r[5]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_60 ),
        .O(\gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r[5]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r_reg[5] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[5].pat0_match_fall3_r[5]_i_1_n_0 ),
        .Q(pat0_match_fall3_r[5]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[5].pat0_match_rise0_r_reg[5] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_52 ),
        .Q(pat0_match_rise0_r[5]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[5].pat0_match_rise1_r[5]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_92 ),
        .O(\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise1_r[5]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[5].pat0_match_rise1_r_reg[5] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[5].pat0_match_rise1_r[5]_i_1_n_0 ),
        .Q(pat0_match_rise1_r[5]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[5].pat0_match_rise3_r_reg[5] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_108 ),
        .Q(pat0_match_rise3_r[5]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall0_r_reg[6] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_101 ),
        .Q(pat0_match_fall0_r[6]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall1_r_reg[6] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_77 ),
        .Q(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall1_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r[6]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_85 ),
        .O(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r[6]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r_reg[6] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r[6]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r[6]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_61 ),
        .O(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r[6]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r_reg[6] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall3_r[6]_i_1_n_0 ),
        .Q(pat0_match_fall3_r[6]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r[6]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_53 ),
        .O(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r[6]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r_reg[6] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r[6]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise1_r_reg[6] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_93 ),
        .Q(pat0_match_rise1_r[6]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r[6]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_69 ),
        .O(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r[6]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r_reg[6] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise2_r[6]_i_1_n_0 ),
        .Q(pat0_match_rise2_r[6]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise3_r_reg[6] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_109 ),
        .Q(idel_pat0_match_rise3_r[6]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r[6]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_101 ),
        .O(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r[6]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r_reg[6] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r[6]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall2_r_reg[6] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_85 ),
        .Q(pat0_match_fall2_r[6]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise0_r_reg[6] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_53 ),
        .Q(pat0_match_rise0_r[6]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise1_r[6]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_93 ),
        .O(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise1_r[6]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise1_r_reg[6] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise1_r[6]_i_1_n_0 ),
        .Q(idel_pat1_match_rise1_r[6]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise2_r_reg[6] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_69 ),
        .Q(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise2_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r[6]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_109 ),
        .O(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r[6]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r_reg[6] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise3_r[6]_i_1_n_0 ),
        .Q(pat0_match_rise3_r[6]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[6].pat0_match_fall1_r[6]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_77 ),
        .O(\gen_pat_match_div4.gen_pat_match[6].pat0_match_fall1_r[6]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[6].pat0_match_fall1_r_reg[6] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[6].pat0_match_fall1_r[6]_i_1_n_0 ),
        .Q(pat0_match_fall1_r[6]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[6].pat1_match_fall3_r_reg[6] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_61 ),
        .Q(\gen_pat_match_div4.gen_pat_match[6].pat1_match_fall3_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r[7]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_102 ),
        .O(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r[7]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r_reg[7] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r[7]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall1_r_reg[7] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_78 ),
        .Q(pat0_match_fall1_r[7]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r[7]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_86 ),
        .O(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r[7]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r_reg[7] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall2_r[7]_i_1_n_0 ),
        .Q(pat0_match_fall2_r[7]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall3_r_reg[7] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_62 ),
        .Q(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall3_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r[7]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_54 ),
        .O(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r[7]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r_reg[7] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise0_r[7]_i_1_n_0 ),
        .Q(pat0_match_rise0_r[7]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise1_r_reg[7] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_94 ),
        .Q(pat0_match_rise1_r[7]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise2_r_reg[7] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_70 ),
        .Q(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise2_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise3_r[7]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_110 ),
        .O(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise3_r[7]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise3_r_reg[7] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise3_r[7]_i_1_n_0 ),
        .Q(idel_pat0_match_rise3_r[7]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall0_r_reg[7] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_102 ),
        .Q(pat0_match_fall0_r[7]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r[7]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_78 ),
        .O(\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r[7]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r_reg[7] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r[7]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall2_r_reg[7] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_86 ),
        .Q(\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall2_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r[7]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_62 ),
        .O(\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r[7]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r_reg[7] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall3_r[7]_i_1_n_0 ),
        .Q(pat0_match_fall3_r[7]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r[7]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_94 ),
        .O(\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r[7]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r_reg[7] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise1_r[7]_i_1_n_0 ),
        .Q(idel_pat1_match_rise1_r[7]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_rise3_r_reg[7] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_110 ),
        .Q(pat0_match_rise3_r[7]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[7].pat0_match_rise2_r[7]_i_1 
       (.I0(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_70 ),
        .O(\gen_pat_match_div4.gen_pat_match[7].pat0_match_rise2_r[7]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[7].pat0_match_rise2_r_reg[7] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[7].pat0_match_rise2_r[7]_i_1_n_0 ),
        .Q(pat0_match_rise2_r[7]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[7].pat1_match_rise0_r_reg[7] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_54 ),
        .Q(\gen_pat_match_div4.gen_pat_match[7].pat1_match_rise0_r_reg ),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h00008000)) 
    \gen_pat_match_div4.idel_pat0_data_match_r_i_1 
       (.I0(idel_pat0_match_fall0_and_r),
        .I1(idel_pat0_match_rise1_and_r),
        .I2(idel_pat0_match_rise3_and_r),
        .I3(idel_pat0_match_fall3_and_r),
        .I4(\gen_pat_match_div4.idel_pat0_data_match_r_i_2_n_0 ),
        .O(idel_pat0_data_match_r0));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \gen_pat_match_div4.idel_pat0_data_match_r_i_2 
       (.I0(idel_pat0_match_fall1_and_r),
        .I1(idel_pat0_match_fall2_and_r),
        .I2(idel_pat0_match_rise0_and_r),
        .I3(idel_pat0_match_rise2_and_r),
        .O(\gen_pat_match_div4.idel_pat0_data_match_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.idel_pat0_data_match_r_reg 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(idel_pat0_data_match_r0),
        .Q(\gen_pat_match_div4.idel_pat0_data_match_r_reg_n_0 ),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \gen_pat_match_div4.idel_pat0_match_fall0_and_r_i_1 
       (.I0(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r_reg ),
        .I1(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall0_r_reg ),
        .I2(\gen_pat_match_div4.pat1_match_fall0_and_r_i_2_n_0 ),
        .I3(pat0_match_fall0_r[2]),
        .I4(pat0_match_fall0_r[5]),
        .I5(pat0_match_fall0_r[6]),
        .O(\gen_pat_match_div4.idel_pat0_match_fall0_and_r_i_1_n_0 ));
  FDRE \gen_pat_match_div4.idel_pat0_match_fall0_and_r_reg 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.idel_pat0_match_fall0_and_r_i_1_n_0 ),
        .Q(idel_pat0_match_fall0_and_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \gen_pat_match_div4.idel_pat0_match_fall1_and_r_i_1 
       (.I0(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall1_r_reg ),
        .I1(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r_reg ),
        .I2(\gen_pat_match_div4.pat1_match_fall1_and_r_i_2_n_0 ),
        .I3(pat0_match_fall1_r[1]),
        .I4(pat0_match_fall1_r[5]),
        .I5(pat0_match_fall1_r[7]),
        .O(\gen_pat_match_div4.idel_pat0_match_fall1_and_r_i_1_n_0 ));
  FDRE \gen_pat_match_div4.idel_pat0_match_fall1_and_r_reg 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.idel_pat0_match_fall1_and_r_i_1_n_0 ),
        .Q(idel_pat0_match_fall1_and_r),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair216" *) 
  LUT3 #(
    .INIT(8'h80)) 
    \gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_1 
       (.I0(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r_reg ),
        .I1(\gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_2_n_0 ),
        .I2(pat0_match_fall2_r[3]),
        .O(\gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_2 
       (.I0(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall2_r_reg ),
        .I1(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r_reg ),
        .I2(pat0_match_fall2_r[0]),
        .I3(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall2_r_reg ),
        .I4(pat0_match_fall2_r[4]),
        .I5(pat0_match_fall2_r[7]),
        .O(\gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.idel_pat0_match_fall2_and_r_reg 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.idel_pat0_match_fall2_and_r_i_1_n_0 ),
        .Q(idel_pat0_match_fall2_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h00008000)) 
    \gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_1 
       (.I0(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall3_r_reg ),
        .I1(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall3_r_reg ),
        .I2(pat0_match_fall3_r[6]),
        .I3(pat0_match_fall3_r[4]),
        .I4(\gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_2_n_0 ),
        .O(\gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_2 
       (.I0(pat0_match_fall3_r[0]),
        .I1(pat0_match_fall3_r[2]),
        .I2(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall3_r_reg ),
        .I3(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall3_r_reg ),
        .O(\gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.idel_pat0_match_fall3_and_r_reg 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.idel_pat0_match_fall3_and_r_i_1_n_0 ),
        .Q(idel_pat0_match_fall3_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.idel_pat0_match_rise0_and_r_i_1 
       (.I0(\gen_pat_match_div4.pat1_match_rise0_and_r_i_2_n_0 ),
        .I1(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r_reg ),
        .I2(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r_reg ),
        .I3(pat0_match_rise0_r[7]),
        .I4(pat0_match_rise0_r[3]),
        .O(\gen_pat_match_div4.idel_pat0_match_rise0_and_r_i_1_n_0 ));
  FDRE \gen_pat_match_div4.idel_pat0_match_rise0_and_r_reg 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.idel_pat0_match_rise0_and_r_i_1_n_0 ),
        .Q(idel_pat0_match_rise0_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.idel_pat0_match_rise1_and_r_i_1 
       (.I0(\gen_pat_match_div4.pat0_match_rise1_and_r_i_2_n_0 ),
        .I1(idel_pat1_match_rise1_r[5]),
        .I2(idel_pat1_match_rise1_r[1]),
        .I3(pat0_match_rise1_r[4]),
        .I4(pat0_match_rise1_r[0]),
        .O(\gen_pat_match_div4.idel_pat0_match_rise1_and_r_i_1_n_0 ));
  FDRE \gen_pat_match_div4.idel_pat0_match_rise1_and_r_reg 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.idel_pat0_match_rise1_and_r_i_1_n_0 ),
        .Q(idel_pat0_match_rise1_and_r),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair205" *) 
  LUT3 #(
    .INIT(8'h80)) 
    \gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_1 
       (.I0(pat0_match_rise2_r[6]),
        .I1(\gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_2_n_0 ),
        .I2(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise2_r_reg ),
        .O(\gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_2 
       (.I0(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_rise2_r_reg ),
        .I1(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_rise2_r_reg ),
        .I2(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise2_r_reg ),
        .I3(pat0_match_rise2_r[2]),
        .I4(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r_reg ),
        .I5(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r_reg ),
        .O(\gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.idel_pat0_match_rise2_and_r_reg 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.idel_pat0_match_rise2_and_r_i_1_n_0 ),
        .Q(idel_pat0_match_rise2_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.idel_pat0_match_rise3_and_r_i_1 
       (.I0(\gen_pat_match_div4.pat1_match_rise3_and_r_i_2_n_0 ),
        .I1(idel_pat0_match_rise3_r[6]),
        .I2(idel_pat0_match_rise3_r[2]),
        .I3(idel_pat0_match_rise3_r[5]),
        .I4(idel_pat0_match_rise3_r[1]),
        .O(\gen_pat_match_div4.idel_pat0_match_rise3_and_r_i_1_n_0 ));
  FDRE \gen_pat_match_div4.idel_pat0_match_rise3_and_r_reg 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.idel_pat0_match_rise3_and_r_i_1_n_0 ),
        .Q(idel_pat0_match_rise3_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h00008000)) 
    \gen_pat_match_div4.idel_pat1_data_match_r_i_1 
       (.I0(idel_pat1_match_rise1_and_r),
        .I1(idel_pat1_match_fall1_and_r),
        .I2(idel_pat1_match_rise3_and_r),
        .I3(idel_pat1_match_fall0_and_r),
        .I4(\gen_pat_match_div4.idel_pat1_data_match_r_i_2_n_0 ),
        .O(idel_pat1_data_match_r0));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \gen_pat_match_div4.idel_pat1_data_match_r_i_2 
       (.I0(idel_pat1_match_fall2_and_r),
        .I1(idel_pat1_match_rise2_and_r),
        .I2(idel_pat1_match_rise0_and_r),
        .I3(idel_pat1_match_fall3_and_r),
        .O(\gen_pat_match_div4.idel_pat1_data_match_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.idel_pat1_data_match_r_reg 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(idel_pat1_data_match_r0),
        .Q(\gen_pat_match_div4.idel_pat1_data_match_r_reg_n_0 ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair213" *) 
  LUT3 #(
    .INIT(8'h80)) 
    \gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_1 
       (.I0(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r_reg ),
        .I1(\gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_2_n_0 ),
        .I2(pat0_match_fall0_r[7]),
        .O(\gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_2 
       (.I0(\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall0_r_reg ),
        .I1(pat0_match_fall0_r[3]),
        .I2(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall0_r_reg ),
        .I3(\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall0_r_reg ),
        .I4(\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r_reg ),
        .I5(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall0_r_reg ),
        .O(\gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.idel_pat1_match_fall0_and_r_reg 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.idel_pat1_match_fall0_and_r_i_1_n_0 ),
        .Q(idel_pat1_match_fall0_and_r),
        .R(1'b0));
  LUT3 #(
    .INIT(8'h80)) 
    \gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_1 
       (.I0(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall1_r_reg ),
        .I1(\gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_2_n_0 ),
        .I2(\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall1_r_reg ),
        .O(\gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_2 
       (.I0(pat0_match_fall1_r[4]),
        .I1(pat0_match_fall1_r[0]),
        .I2(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall1_r_reg ),
        .I3(\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall1_r_reg ),
        .I4(\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall1_r_reg ),
        .I5(\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall1_r_reg ),
        .O(\gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.idel_pat1_match_fall1_and_r_reg 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.idel_pat1_match_fall1_and_r_i_1_n_0 ),
        .Q(idel_pat1_match_fall1_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.idel_pat1_match_fall2_and_r_i_1 
       (.I0(pat0_match_fall2_r[6]),
        .I1(\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall2_r_reg ),
        .I2(\gen_pat_match_div4.pat0_match_fall2_and_r_i_2_n_0 ),
        .I3(pat0_match_fall2_r[5]),
        .I4(\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall2_r_reg ),
        .O(\gen_pat_match_div4.idel_pat1_match_fall2_and_r_i_1_n_0 ));
  FDRE \gen_pat_match_div4.idel_pat1_match_fall2_and_r_reg 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.idel_pat1_match_fall2_and_r_i_1_n_0 ),
        .Q(idel_pat1_match_fall2_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.idel_pat1_match_fall3_and_r_i_1 
       (.I0(\gen_pat_match_div4.pat0_match_fall3_and_r_i_2_n_0 ),
        .I1(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_fall3_r_reg ),
        .I2(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_fall3_r_reg ),
        .I3(\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r_reg ),
        .I4(\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r_reg ),
        .O(\gen_pat_match_div4.idel_pat1_match_fall3_and_r_i_1_n_0 ));
  FDRE \gen_pat_match_div4.idel_pat1_match_fall3_and_r_reg 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.idel_pat1_match_fall3_and_r_i_1_n_0 ),
        .Q(idel_pat1_match_fall3_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.idel_pat1_match_rise0_and_r_i_1 
       (.I0(\gen_pat_match_div4.pat0_match_rise0_and_r_i_2_n_0 ),
        .I1(\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_rise0_r_reg ),
        .I2(\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_rise0_r_reg ),
        .I3(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r_reg ),
        .I4(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r_reg ),
        .O(\gen_pat_match_div4.idel_pat1_match_rise0_and_r_i_1_n_0 ));
  FDRE \gen_pat_match_div4.idel_pat1_match_rise0_and_r_reg 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.idel_pat1_match_rise0_and_r_i_1_n_0 ),
        .Q(idel_pat1_match_rise0_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.idel_pat1_match_rise1_and_r_i_1 
       (.I0(\gen_pat_match_div4.pat1_match_rise1_and_r_i_2_n_0 ),
        .I1(idel_pat1_match_rise1_r[6]),
        .I2(idel_pat1_match_rise1_r[2]),
        .I3(idel_pat1_match_rise1_r[7]),
        .I4(idel_pat1_match_rise1_r[3]),
        .O(\gen_pat_match_div4.idel_pat1_match_rise1_and_r_i_1_n_0 ));
  FDRE \gen_pat_match_div4.idel_pat1_match_rise1_and_r_reg 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.idel_pat1_match_rise1_and_r_i_1_n_0 ),
        .Q(idel_pat1_match_rise1_and_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \gen_pat_match_div4.idel_pat1_match_rise2_and_r_i_1 
       (.I0(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise2_r_reg ),
        .I1(pat0_match_rise2_r[4]),
        .I2(\gen_pat_match_div4.pat1_match_rise2_and_r_i_2_n_0 ),
        .I3(pat0_match_rise2_r[1]),
        .I4(pat0_match_rise2_r[5]),
        .I5(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise2_r_reg ),
        .O(\gen_pat_match_div4.idel_pat1_match_rise2_and_r_i_1_n_0 ));
  FDRE \gen_pat_match_div4.idel_pat1_match_rise2_and_r_reg 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.idel_pat1_match_rise2_and_r_i_1_n_0 ),
        .Q(idel_pat1_match_rise2_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.idel_pat1_match_rise3_and_r_i_1 
       (.I0(\gen_pat_match_div4.pat0_match_rise3_and_r_i_2_n_0 ),
        .I1(idel_pat0_match_rise3_r[5]),
        .I2(idel_pat0_match_rise3_r[1]),
        .I3(pat0_match_rise3_r[6]),
        .I4(pat0_match_rise3_r[2]),
        .O(\gen_pat_match_div4.idel_pat1_match_rise3_and_r_i_1_n_0 ));
  FDRE \gen_pat_match_div4.idel_pat1_match_rise3_and_r_reg 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.idel_pat1_match_rise3_and_r_i_1_n_0 ),
        .Q(idel_pat1_match_rise3_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h00008000)) 
    \gen_pat_match_div4.pat0_data_match_r_i_1 
       (.I0(pat0_match_rise1_and_r),
        .I1(pat0_match_fall2_and_r),
        .I2(pat0_match_rise3_and_r),
        .I3(pat0_match_fall0_and_r),
        .I4(\gen_pat_match_div4.pat0_data_match_r_i_2_n_0 ),
        .O(pat0_data_match_r0));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \gen_pat_match_div4.pat0_data_match_r_i_2 
       (.I0(pat0_match_rise2_and_r),
        .I1(pat0_match_fall1_and_r),
        .I2(pat0_match_rise0_and_r),
        .I3(pat0_match_fall3_and_r),
        .O(\gen_pat_match_div4.pat0_data_match_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.pat0_data_match_r_reg 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(pat0_data_match_r0),
        .Q(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair213" *) 
  LUT3 #(
    .INIT(8'h80)) 
    \gen_pat_match_div4.pat0_match_fall0_and_r_i_1 
       (.I0(pat0_match_fall0_r[6]),
        .I1(\gen_pat_match_div4.pat0_match_fall0_and_r_i_2_n_0 ),
        .I2(pat0_match_fall0_r[7]),
        .O(\gen_pat_match_div4.pat0_match_fall0_and_r_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \gen_pat_match_div4.pat0_match_fall0_and_r_i_2 
       (.I0(pat0_match_fall0_r[4]),
        .I1(pat0_match_fall0_r[2]),
        .I2(pat0_match_fall0_r[0]),
        .I3(pat0_match_fall0_r[1]),
        .I4(pat0_match_fall0_r[3]),
        .I5(pat0_match_fall0_r[5]),
        .O(\gen_pat_match_div4.pat0_match_fall0_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.pat0_match_fall0_and_r_reg 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.pat0_match_fall0_and_r_i_1_n_0 ),
        .Q(pat0_match_fall0_and_r),
        .R(1'b0));
  LUT3 #(
    .INIT(8'h80)) 
    \gen_pat_match_div4.pat0_match_fall1_and_r_i_1 
       (.I0(pat0_match_fall1_r[6]),
        .I1(\gen_pat_match_div4.pat0_match_fall1_and_r_i_2_n_0 ),
        .I2(pat0_match_fall1_r[7]),
        .O(\gen_pat_match_div4.pat0_match_fall1_and_r_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \gen_pat_match_div4.pat0_match_fall1_and_r_i_2 
       (.I0(pat0_match_fall1_r[4]),
        .I1(pat0_match_fall1_r[1]),
        .I2(pat0_match_fall1_r[3]),
        .I3(pat0_match_fall1_r[2]),
        .I4(pat0_match_fall1_r[0]),
        .I5(pat0_match_fall1_r[5]),
        .O(\gen_pat_match_div4.pat0_match_fall1_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.pat0_match_fall1_and_r_reg 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.pat0_match_fall1_and_r_i_1_n_0 ),
        .Q(pat0_match_fall1_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.pat0_match_fall2_and_r_i_1 
       (.I0(pat0_match_fall2_r[7]),
        .I1(pat0_match_fall2_r[5]),
        .I2(\gen_pat_match_div4.pat0_match_fall2_and_r_i_2_n_0 ),
        .I3(pat0_match_fall2_r[6]),
        .I4(pat0_match_fall2_r[3]),
        .O(\gen_pat_match_div4.pat0_match_fall2_and_r_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h8000)) 
    \gen_pat_match_div4.pat0_match_fall2_and_r_i_2 
       (.I0(pat0_match_fall2_r[2]),
        .I1(pat0_match_fall2_r[1]),
        .I2(pat0_match_fall2_r[0]),
        .I3(pat0_match_fall2_r[4]),
        .O(\gen_pat_match_div4.pat0_match_fall2_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.pat0_match_fall2_and_r_reg 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.pat0_match_fall2_and_r_i_1_n_0 ),
        .Q(pat0_match_fall2_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.pat0_match_fall3_and_r_i_1 
       (.I0(\gen_pat_match_div4.pat0_match_fall3_and_r_i_2_n_0 ),
        .I1(pat0_match_fall3_r[4]),
        .I2(pat0_match_fall3_r[1]),
        .I3(pat0_match_fall3_r[5]),
        .I4(pat0_match_fall3_r[0]),
        .O(\gen_pat_match_div4.pat0_match_fall3_and_r_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h8000)) 
    \gen_pat_match_div4.pat0_match_fall3_and_r_i_2 
       (.I0(pat0_match_fall3_r[2]),
        .I1(pat0_match_fall3_r[7]),
        .I2(pat0_match_fall3_r[3]),
        .I3(pat0_match_fall3_r[6]),
        .O(\gen_pat_match_div4.pat0_match_fall3_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.pat0_match_fall3_and_r_reg 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.pat0_match_fall3_and_r_i_1_n_0 ),
        .Q(pat0_match_fall3_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.pat0_match_rise0_and_r_i_1 
       (.I0(\gen_pat_match_div4.pat0_match_rise0_and_r_i_2_n_0 ),
        .I1(pat0_match_rise0_r[5]),
        .I2(pat0_match_rise0_r[1]),
        .I3(pat0_match_rise0_r[4]),
        .I4(pat0_match_rise0_r[0]),
        .O(\gen_pat_match_div4.pat0_match_rise0_and_r_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h8000)) 
    \gen_pat_match_div4.pat0_match_rise0_and_r_i_2 
       (.I0(pat0_match_rise0_r[2]),
        .I1(pat0_match_rise0_r[6]),
        .I2(pat0_match_rise0_r[3]),
        .I3(pat0_match_rise0_r[7]),
        .O(\gen_pat_match_div4.pat0_match_rise0_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.pat0_match_rise0_and_r_reg 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.pat0_match_rise0_and_r_i_1_n_0 ),
        .Q(pat0_match_rise0_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.pat0_match_rise1_and_r_i_1 
       (.I0(\gen_pat_match_div4.pat0_match_rise1_and_r_i_2_n_0 ),
        .I1(pat0_match_rise1_r[5]),
        .I2(pat0_match_rise1_r[1]),
        .I3(pat0_match_rise1_r[4]),
        .I4(pat0_match_rise1_r[0]),
        .O(\gen_pat_match_div4.pat0_match_rise1_and_r_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h8000)) 
    \gen_pat_match_div4.pat0_match_rise1_and_r_i_2 
       (.I0(pat0_match_rise1_r[3]),
        .I1(pat0_match_rise1_r[7]),
        .I2(pat0_match_rise1_r[2]),
        .I3(pat0_match_rise1_r[6]),
        .O(\gen_pat_match_div4.pat0_match_rise1_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.pat0_match_rise1_and_r_reg 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.pat0_match_rise1_and_r_i_1_n_0 ),
        .Q(pat0_match_rise1_and_r),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair205" *) 
  LUT3 #(
    .INIT(8'h80)) 
    \gen_pat_match_div4.pat0_match_rise2_and_r_i_1 
       (.I0(pat0_match_rise2_r[7]),
        .I1(\gen_pat_match_div4.pat0_match_rise2_and_r_i_2_n_0 ),
        .I2(pat0_match_rise2_r[6]),
        .O(\gen_pat_match_div4.pat0_match_rise2_and_r_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \gen_pat_match_div4.pat0_match_rise2_and_r_i_2 
       (.I0(pat0_match_rise2_r[4]),
        .I1(pat0_match_rise2_r[2]),
        .I2(pat0_match_rise2_r[0]),
        .I3(pat0_match_rise2_r[1]),
        .I4(pat0_match_rise2_r[3]),
        .I5(pat0_match_rise2_r[5]),
        .O(\gen_pat_match_div4.pat0_match_rise2_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.pat0_match_rise2_and_r_reg 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.pat0_match_rise2_and_r_i_1_n_0 ),
        .Q(pat0_match_rise2_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.pat0_match_rise3_and_r_i_1 
       (.I0(pat0_match_rise3_r[6]),
        .I1(pat0_match_rise3_r[2]),
        .I2(pat0_match_rise3_r[5]),
        .I3(pat0_match_rise3_r[1]),
        .I4(\gen_pat_match_div4.pat0_match_rise3_and_r_i_2_n_0 ),
        .O(\gen_pat_match_div4.pat0_match_rise3_and_r_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h8000)) 
    \gen_pat_match_div4.pat0_match_rise3_and_r_i_2 
       (.I0(pat0_match_rise3_r[3]),
        .I1(pat0_match_rise3_r[7]),
        .I2(pat0_match_rise3_r[0]),
        .I3(pat0_match_rise3_r[4]),
        .O(\gen_pat_match_div4.pat0_match_rise3_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.pat0_match_rise3_and_r_reg 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.pat0_match_rise3_and_r_i_1_n_0 ),
        .Q(pat0_match_rise3_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h00008000)) 
    \gen_pat_match_div4.pat1_data_match_r_i_1 
       (.I0(pat1_match_fall0_and_r),
        .I1(pat1_match_rise1_and_r),
        .I2(pat1_match_rise3_and_r),
        .I3(pat1_match_fall2_and_r),
        .I4(\gen_pat_match_div4.pat1_data_match_r_i_2_n_0 ),
        .O(pat1_data_match_r0));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \gen_pat_match_div4.pat1_data_match_r_i_2 
       (.I0(pat1_match_rise2_and_r),
        .I1(pat1_match_fall1_and_r),
        .I2(pat1_match_rise0_and_r),
        .I3(pat1_match_fall3_and_r),
        .O(\gen_pat_match_div4.pat1_data_match_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.pat1_data_match_r_reg 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(pat1_data_match_r0),
        .Q(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \gen_pat_match_div4.pat1_match_fall0_and_r_i_1 
       (.I0(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_fall0_r_reg ),
        .I1(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall0_r_reg ),
        .I2(\gen_pat_match_div4.pat1_match_fall0_and_r_i_2_n_0 ),
        .I3(\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_fall0_r_reg ),
        .I4(pat0_match_fall0_r[5]),
        .I5(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_fall0_r_reg ),
        .O(\gen_pat_match_div4.pat1_match_fall0_and_r_i_1_n_0 ));
  LUT3 #(
    .INIT(8'h80)) 
    \gen_pat_match_div4.pat1_match_fall0_and_r_i_2 
       (.I0(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall0_r_reg ),
        .I1(pat0_match_fall0_r[1]),
        .I2(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_fall0_r_reg ),
        .O(\gen_pat_match_div4.pat1_match_fall0_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.pat1_match_fall0_and_r_reg 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.pat1_match_fall0_and_r_i_1_n_0 ),
        .Q(pat1_match_fall0_and_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \gen_pat_match_div4.pat1_match_fall1_and_r_i_1 
       (.I0(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall1_r_reg ),
        .I1(\gen_pat_match_div4.gen_pat_match[4].idel_pat0_match_fall1_r_reg ),
        .I2(\gen_pat_match_div4.pat1_match_fall1_and_r_i_2_n_0 ),
        .I3(\gen_pat_match_div4.gen_pat_match[1].idel_pat1_match_fall1_r_reg ),
        .I4(\gen_pat_match_div4.gen_pat_match[5].idel_pat1_match_fall1_r_reg ),
        .I5(pat0_match_fall1_r[7]),
        .O(\gen_pat_match_div4.pat1_match_fall1_and_r_i_1_n_0 ));
  LUT3 #(
    .INIT(8'h80)) 
    \gen_pat_match_div4.pat1_match_fall1_and_r_i_2 
       (.I0(pat0_match_fall1_r[3]),
        .I1(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall1_r_reg ),
        .I2(\gen_pat_match_div4.gen_pat_match[0].idel_pat0_match_fall1_r_reg ),
        .O(\gen_pat_match_div4.pat1_match_fall1_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.pat1_match_fall1_and_r_reg 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.pat1_match_fall1_and_r_i_1_n_0 ),
        .Q(pat1_match_fall1_and_r),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair216" *) 
  LUT3 #(
    .INIT(8'h80)) 
    \gen_pat_match_div4.pat1_match_fall2_and_r_i_1 
       (.I0(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_fall2_r_reg ),
        .I1(\gen_pat_match_div4.pat1_match_fall2_and_r_i_2_n_0 ),
        .I2(\gen_pat_match_div4.gen_pat_match[7].idel_pat1_match_fall2_r_reg ),
        .O(\gen_pat_match_div4.pat1_match_fall2_and_r_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \gen_pat_match_div4.pat1_match_fall2_and_r_i_2 
       (.I0(\gen_pat_match_div4.gen_pat_match[4].pat1_match_fall2_r_reg ),
        .I1(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_fall2_r_reg ),
        .I2(pat0_match_fall2_r[1]),
        .I3(\gen_pat_match_div4.gen_pat_match[0].pat1_match_fall2_r_reg ),
        .I4(\gen_pat_match_div4.gen_pat_match[3].idel_pat1_match_fall2_r_reg ),
        .I5(pat0_match_fall2_r[5]),
        .O(\gen_pat_match_div4.pat1_match_fall2_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.pat1_match_fall2_and_r_reg 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.pat1_match_fall2_and_r_i_1_n_0 ),
        .Q(pat1_match_fall2_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h00008000)) 
    \gen_pat_match_div4.pat1_match_fall3_and_r_i_1 
       (.I0(\gen_pat_match_div4.gen_pat_match[6].pat1_match_fall3_r_reg ),
        .I1(\gen_pat_match_div4.gen_pat_match[4].idel_pat1_match_fall3_r_reg ),
        .I2(pat0_match_fall3_r[7]),
        .I3(pat0_match_fall3_r[5]),
        .I4(\gen_pat_match_div4.pat1_match_fall3_and_r_i_2_n_0 ),
        .O(\gen_pat_match_div4.pat1_match_fall3_and_r_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \gen_pat_match_div4.pat1_match_fall3_and_r_i_2 
       (.I0(pat0_match_fall3_r[1]),
        .I1(pat0_match_fall3_r[3]),
        .I2(\gen_pat_match_div4.gen_pat_match[0].idel_pat1_match_fall3_r_reg ),
        .I3(\gen_pat_match_div4.gen_pat_match[2].pat1_match_fall3_r_reg ),
        .O(\gen_pat_match_div4.pat1_match_fall3_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.pat1_match_fall3_and_r_reg 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.pat1_match_fall3_and_r_i_1_n_0 ),
        .Q(pat1_match_fall3_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.pat1_match_rise0_and_r_i_1 
       (.I0(\gen_pat_match_div4.pat1_match_rise0_and_r_i_2_n_0 ),
        .I1(\gen_pat_match_div4.gen_pat_match[7].pat1_match_rise0_r_reg ),
        .I2(\gen_pat_match_div4.gen_pat_match[3].pat1_match_rise0_r_reg ),
        .I3(\gen_pat_match_div4.gen_pat_match[6].idel_pat0_match_rise0_r_reg ),
        .I4(\gen_pat_match_div4.gen_pat_match[2].idel_pat0_match_rise0_r_reg ),
        .O(\gen_pat_match_div4.pat1_match_rise0_and_r_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h8000)) 
    \gen_pat_match_div4.pat1_match_rise0_and_r_i_2 
       (.I0(pat0_match_rise0_r[0]),
        .I1(pat0_match_rise0_r[4]),
        .I2(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise0_r_reg ),
        .I3(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise0_r_reg ),
        .O(\gen_pat_match_div4.pat1_match_rise0_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.pat1_match_rise0_and_r_reg 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.pat1_match_rise0_and_r_i_1_n_0 ),
        .Q(pat1_match_rise0_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.pat1_match_rise1_and_r_i_1 
       (.I0(\gen_pat_match_div4.pat1_match_rise1_and_r_i_2_n_0 ),
        .I1(idel_pat1_match_rise1_r[7]),
        .I2(idel_pat1_match_rise1_r[3]),
        .I3(pat0_match_rise1_r[6]),
        .I4(pat0_match_rise1_r[2]),
        .O(\gen_pat_match_div4.pat1_match_rise1_and_r_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h8000)) 
    \gen_pat_match_div4.pat1_match_rise1_and_r_i_2 
       (.I0(idel_pat1_match_rise1_r[0]),
        .I1(idel_pat1_match_rise1_r[4]),
        .I2(idel_pat1_match_rise1_r[1]),
        .I3(idel_pat1_match_rise1_r[5]),
        .O(\gen_pat_match_div4.pat1_match_rise1_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.pat1_match_rise1_and_r_reg 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.pat1_match_rise1_and_r_i_1_n_0 ),
        .Q(pat1_match_rise1_and_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \gen_pat_match_div4.pat1_match_rise2_and_r_i_1 
       (.I0(\gen_pat_match_div4.gen_pat_match[6].idel_pat1_match_rise2_r_reg ),
        .I1(pat0_match_rise2_r[4]),
        .I2(\gen_pat_match_div4.pat1_match_rise2_and_r_i_2_n_0 ),
        .I3(\gen_pat_match_div4.gen_pat_match[1].idel_pat0_match_rise2_r_reg ),
        .I4(\gen_pat_match_div4.gen_pat_match[5].idel_pat0_match_rise2_r_reg ),
        .I5(\gen_pat_match_div4.gen_pat_match[7].idel_pat0_match_rise2_r_reg ),
        .O(\gen_pat_match_div4.pat1_match_rise2_and_r_i_1_n_0 ));
  LUT3 #(
    .INIT(8'h80)) 
    \gen_pat_match_div4.pat1_match_rise2_and_r_i_2 
       (.I0(\gen_pat_match_div4.gen_pat_match[3].idel_pat0_match_rise2_r_reg ),
        .I1(\gen_pat_match_div4.gen_pat_match[2].idel_pat1_match_rise2_r_reg ),
        .I2(pat0_match_rise2_r[0]),
        .O(\gen_pat_match_div4.pat1_match_rise2_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.pat1_match_rise2_and_r_reg 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.pat1_match_rise2_and_r_i_1_n_0 ),
        .Q(pat1_match_rise2_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.pat1_match_rise3_and_r_i_1 
       (.I0(pat0_match_rise3_r[6]),
        .I1(pat0_match_rise3_r[2]),
        .I2(pat0_match_rise3_r[5]),
        .I3(pat0_match_rise3_r[1]),
        .I4(\gen_pat_match_div4.pat1_match_rise3_and_r_i_2_n_0 ),
        .O(\gen_pat_match_div4.pat1_match_rise3_and_r_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h8000)) 
    \gen_pat_match_div4.pat1_match_rise3_and_r_i_2 
       (.I0(idel_pat0_match_rise3_r[4]),
        .I1(idel_pat0_match_rise3_r[7]),
        .I2(idel_pat0_match_rise3_r[0]),
        .I3(idel_pat0_match_rise3_r[3]),
        .O(\gen_pat_match_div4.pat1_match_rise3_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.pat1_match_rise3_and_r_reg 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.pat1_match_rise3_and_r_i_1_n_0 ),
        .Q(pat1_match_rise3_and_r),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(E),
        .D(\gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_95 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(E),
        .D(\gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_71 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(E),
        .D(\gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_79 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(E),
        .D(\gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_55 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(E),
        .D(\gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_47 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(E),
        .D(\gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_87 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(E),
        .D(\gen_mux_rd[0].mux_rd_rise2_r_reg_n_0_[0] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_63 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(E),
        .D(\gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_103 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(E),
        .D(\gen_mux_rd[1].mux_rd_fall0_r_reg_n_0_[1] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_96 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(E),
        .D(\gen_mux_rd[1].mux_rd_fall1_r_reg_n_0_[1] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_72 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(E),
        .D(\gen_mux_rd[1].mux_rd_fall2_r_reg_n_0_[1] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_80 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(E),
        .D(\gen_mux_rd[1].mux_rd_fall3_r_reg_n_0_[1] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_56 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(E),
        .D(\gen_mux_rd[1].mux_rd_rise0_r_reg_n_0_[1] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_48 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(E),
        .D(\gen_mux_rd[1].mux_rd_rise1_r_reg_n_0_[1] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_88 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(E),
        .D(\gen_mux_rd[1].mux_rd_rise2_r_reg_n_0_[1] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_64 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(E),
        .D(\gen_mux_rd[1].mux_rd_rise3_r_reg_n_0_[1] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_104 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(E),
        .D(\gen_mux_rd[2].mux_rd_fall0_r_reg_n_0_[2] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_97 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(E),
        .D(\gen_mux_rd[2].mux_rd_fall1_r_reg_n_0_[2] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_73 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(E),
        .D(\gen_mux_rd[2].mux_rd_fall2_r_reg_n_0_[2] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_81 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(E),
        .D(\gen_mux_rd[2].mux_rd_fall3_r_reg_n_0_[2] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_57 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(E),
        .D(\gen_mux_rd[2].mux_rd_rise0_r_reg_n_0_[2] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_49 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(E),
        .D(\gen_mux_rd[2].mux_rd_rise1_r_reg_n_0_[2] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_89 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(E),
        .D(\gen_mux_rd[2].mux_rd_rise2_r_reg_n_0_[2] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_65 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(E),
        .D(\gen_mux_rd[2].mux_rd_rise3_r_reg_n_0_[2] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_105 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(E),
        .D(\gen_mux_rd[3].mux_rd_fall0_r_reg_n_0_[3] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_98 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(E),
        .D(\gen_mux_rd[3].mux_rd_fall1_r_reg_n_0_[3] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_74 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(E),
        .D(\gen_mux_rd[3].mux_rd_fall2_r_reg_n_0_[3] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_82 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(E),
        .D(\gen_mux_rd[3].mux_rd_fall3_r_reg_n_0_[3] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_58 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(E),
        .D(\gen_mux_rd[3].mux_rd_rise0_r_reg_n_0_[3] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_50 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(E),
        .D(\gen_mux_rd[3].mux_rd_rise1_r_reg_n_0_[3] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_90 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(E),
        .D(\gen_mux_rd[3].mux_rd_rise2_r_reg_n_0_[3] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_66 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(E),
        .D(\gen_mux_rd[3].mux_rd_rise3_r_reg_n_0_[3] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_106 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(E),
        .D(\gen_mux_rd[4].mux_rd_fall0_r_reg_n_0_[4] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_99 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(E),
        .D(\gen_mux_rd[4].mux_rd_fall1_r_reg_n_0_[4] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_75 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(E),
        .D(\gen_mux_rd[4].mux_rd_fall2_r_reg_n_0_[4] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_83 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(E),
        .D(\gen_mux_rd[4].mux_rd_fall3_r_reg_n_0_[4] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_59 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(E),
        .D(\gen_mux_rd[4].mux_rd_rise0_r_reg_n_0_[4] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_51 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(E),
        .D(\gen_mux_rd[4].mux_rd_rise1_r_reg_n_0_[4] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_91 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(E),
        .D(\gen_mux_rd[4].mux_rd_rise2_r_reg_n_0_[4] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_67 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(E),
        .D(\gen_mux_rd[4].mux_rd_rise3_r_reg_n_0_[4] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_107 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(E),
        .D(\gen_mux_rd[5].mux_rd_fall0_r_reg_n_0_[5] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_100 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(E),
        .D(\gen_mux_rd[5].mux_rd_fall1_r_reg_n_0_[5] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_76 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(E),
        .D(\gen_mux_rd[5].mux_rd_fall2_r_reg_n_0_[5] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_84 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(E),
        .D(\gen_mux_rd[5].mux_rd_fall3_r_reg_n_0_[5] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_60 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(E),
        .D(\gen_mux_rd[5].mux_rd_rise0_r_reg_n_0_[5] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_52 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(E),
        .D(\gen_mux_rd[5].mux_rd_rise1_r_reg_n_0_[5] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_92 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(E),
        .D(\gen_mux_rd[5].mux_rd_rise2_r_reg_n_0_[5] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_68 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(E),
        .D(\gen_mux_rd[5].mux_rd_rise3_r_reg_n_0_[5] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_108 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(E),
        .D(\gen_mux_rd[6].mux_rd_fall0_r_reg_n_0_[6] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_101 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(E),
        .D(\gen_mux_rd[6].mux_rd_fall1_r_reg_n_0_[6] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_77 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(E),
        .D(\gen_mux_rd[6].mux_rd_fall2_r_reg_n_0_[6] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_85 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(E),
        .D(\gen_mux_rd[6].mux_rd_fall3_r_reg_n_0_[6] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_61 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(E),
        .D(\gen_mux_rd[6].mux_rd_rise0_r_reg_n_0_[6] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_53 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(E),
        .D(\gen_mux_rd[6].mux_rd_rise1_r_reg_n_0_[6] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_93 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(E),
        .D(\gen_mux_rd[6].mux_rd_rise2_r_reg_n_0_[6] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_69 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(E),
        .D(\gen_mux_rd[6].mux_rd_rise3_r_reg_n_0_[6] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_109 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(E),
        .D(\gen_mux_rd[7].mux_rd_fall0_r_reg_n_0_[7] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_102 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(E),
        .D(\gen_mux_rd[7].mux_rd_fall1_r_reg_n_0_[7] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_78 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(E),
        .D(\gen_mux_rd[7].mux_rd_fall2_r_reg_n_0_[7] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_86 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(E),
        .D(\gen_mux_rd[7].mux_rd_fall3_r_reg_n_0_[7] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_62 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(E),
        .D(\gen_mux_rd[7].mux_rd_rise0_r_reg_n_0_[7] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_54 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(E),
        .D(\gen_mux_rd[7].mux_rd_rise1_r_reg_n_0_[7] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_94 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(E),
        .D(\gen_mux_rd[7].mux_rd_rise2_r_reg_n_0_[7] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_70 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(E),
        .D(\gen_mux_rd[7].mux_rd_rise3_r_reg_n_0_[7] ),
        .Q(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_110 ),
        .R(1'b0));
  FDRE \gen_sr_match_div4.gen_sr_match[0].old_sr_diff_r_reg[0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r_reg[0]_inv_n_0 ),
        .Q(\gen_sr_match_div4.gen_sr_match[0].old_sr_diff_r_reg_n_0_[0] ),
        .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF7FFF)) 
    \gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r[0]_inv_i_1 
       (.I0(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r_reg_n_0_[0] ),
        .I1(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r_reg_n_0_[0] ),
        .I2(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r_reg_n_0_[0] ),
        .I3(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r_reg_n_0_[0] ),
        .I4(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r[0]_inv_i_2_n_0 ),
        .O(p_490_out));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r[0]_inv_i_2 
       (.I0(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r_reg_n_0_[0] ),
        .I1(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r_reg_n_0_[0] ),
        .I2(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r_reg_n_0_[0] ),
        .I3(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r_reg_n_0_[0] ),
        .O(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r[0]_inv_i_2_n_0 ));
  FDRE #(
    .INIT(1'b1)) 
    \gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r_reg[0]_inv 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(p_490_out),
        .Q(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_cyc2_r_reg[0]_inv_n_0 ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair199" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r[0]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_95 ),
        .I3(\gen_old_sr_div4.gen_old_sr[0].old_sr_fall0_r_reg[0]_191 ),
        .O(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r[0]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r_reg[0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r[0]_i_1_n_0 ),
        .Q(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall0_r_reg_n_0_[0] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair186" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r[0]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_71 ),
        .I3(\gen_old_sr_div4.gen_old_sr[0].old_sr_fall1_r_reg[0]_207 ),
        .O(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r[0]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r_reg[0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r[0]_i_1_n_0 ),
        .Q(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall1_r_reg_n_0_[0] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair195" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r[0]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_79 ),
        .I3(\gen_old_sr_div4.gen_old_sr[0].old_sr_fall2_r_reg[0]_175 ),
        .O(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r[0]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r_reg[0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r[0]_i_1_n_0 ),
        .Q(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall2_r_reg_n_0_[0] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair203" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r[0]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_55 ),
        .I3(\gen_old_sr_div4.gen_old_sr[0].old_sr_fall3_r_reg[0]_183 ),
        .O(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r[0]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r_reg[0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r[0]_i_1_n_0 ),
        .Q(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_fall3_r_reg_n_0_[0] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair153" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r[0]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_47 ),
        .I3(\gen_old_sr_div4.gen_old_sr[0].old_sr_rise0_r_reg[0]_223 ),
        .O(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r[0]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r_reg[0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r[0]_i_1_n_0 ),
        .Q(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise0_r_reg_n_0_[0] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair191" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r[0]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_87 ),
        .I3(\gen_old_sr_div4.gen_old_sr[0].old_sr_rise1_r_reg[0]_199 ),
        .O(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r[0]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r_reg[0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r[0]_i_1_n_0 ),
        .Q(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise1_r_reg_n_0_[0] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair158" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r[0]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_63 ),
        .I3(\gen_old_sr_div4.gen_old_sr[0].old_sr_rise2_r_reg[0]_215 ),
        .O(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r[0]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r_reg[0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r[0]_i_1_n_0 ),
        .Q(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise2_r_reg_n_0_[0] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair149" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r[0]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_103 ),
        .I3(\gen_old_sr_div4.gen_old_sr[0].old_sr_rise3_r_reg[0]_231 ),
        .O(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r[0]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r_reg[0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r[0]_i_1_n_0 ),
        .Q(\gen_sr_match_div4.gen_sr_match[0].old_sr_match_rise3_r_reg_n_0_[0] ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1 
       (.I0(sr_valid_r2),
        .O(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg[0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r_reg[0]_inv_n_0 ),
        .Q(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg_n_0_[0] ),
        .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF7FFF)) 
    \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r[0]_inv_i_1 
       (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r_reg_n_0_[0] ),
        .I1(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r_reg_n_0_[0] ),
        .I2(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r_reg_n_0_[0] ),
        .I3(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r_reg_n_0_[0] ),
        .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r[0]_inv_i_2_n_0 ),
        .O(p_515_out));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r[0]_inv_i_2 
       (.I0(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r_reg_n_0_[0] ),
        .I1(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r_reg_n_0_[0] ),
        .I2(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r_reg_n_0_[0] ),
        .I3(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r_reg_n_0_[0] ),
        .O(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r[0]_inv_i_2_n_0 ));
  FDRE #(
    .INIT(1'b1)) 
    \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r_reg[0]_inv 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(p_515_out),
        .Q(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_cyc2_r_reg[0]_inv_n_0 ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair199" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall0_r_reg[0]_95 ),
        .I3(\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall0_r_reg[0]_143 ),
        .O(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r_reg[0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r[0]_i_1_n_0 ),
        .Q(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall0_r_reg_n_0_[0] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair186" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r[0]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall1_r_reg[0]_71 ),
        .I3(\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall1_r_reg[0]_119 ),
        .O(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r[0]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r_reg[0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r[0]_i_1_n_0 ),
        .Q(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall1_r_reg_n_0_[0] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair195" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r[0]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall2_r_reg[0]_79 ),
        .I3(\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall2_r_reg[0]_127 ),
        .O(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r[0]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r_reg[0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r[0]_i_1_n_0 ),
        .Q(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall2_r_reg_n_0_[0] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair203" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r[0]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_fall3_r_reg[0]_55 ),
        .I3(\gen_old_sr_div4.gen_old_sr[0].prev_sr_fall3_r_reg[0]_151 ),
        .O(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r[0]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r_reg[0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r[0]_i_1_n_0 ),
        .Q(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_fall3_r_reg_n_0_[0] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair153" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r[0]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise0_r_reg[0]_47 ),
        .I3(\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise0_r_reg[0]_159 ),
        .O(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r[0]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r_reg[0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r[0]_i_1_n_0 ),
        .Q(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise0_r_reg_n_0_[0] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair191" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r[0]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise1_r_reg[0]_87 ),
        .I3(\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise1_r_reg[0]_111 ),
        .O(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r[0]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r_reg[0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r[0]_i_1_n_0 ),
        .Q(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise1_r_reg_n_0_[0] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair158" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r[0]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise2_r_reg[0]_63 ),
        .I3(\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise2_r_reg[0]_135 ),
        .O(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r[0]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r_reg[0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r[0]_i_1_n_0 ),
        .Q(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise2_r_reg_n_0_[0] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair149" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r[0]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[0].sr_rise3_r_reg[0]_103 ),
        .I3(\gen_old_sr_div4.gen_old_sr[0].prev_sr_rise3_r_reg[0]_167 ),
        .O(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r[0]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r_reg[0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r[0]_i_1_n_0 ),
        .Q(\gen_sr_match_div4.gen_sr_match[0].prev_sr_match_rise3_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \gen_sr_match_div4.gen_sr_match[1].old_sr_diff_r_reg[1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r_reg[1]_inv_n_0 ),
        .Q(p_1_in17_in),
        .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF7FFF)) 
    \gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r[1]_inv_i_1 
       (.I0(p_7_in438_in),
        .I1(p_5_in436_in),
        .I2(p_6_in437_in),
        .I3(p_1_in439_in),
        .I4(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r[1]_inv_i_2_n_0 ),
        .O(p_440_out));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r[1]_inv_i_2 
       (.I0(p_3_in434_in),
        .I1(p_4_in435_in),
        .I2(p_2_in433_in),
        .I3(p_0_in432_in),
        .O(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r[1]_inv_i_2_n_0 ));
  FDRE #(
    .INIT(1'b1)) 
    \gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r_reg[1]_inv 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(p_440_out),
        .Q(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_cyc2_r_reg[1]_inv_n_0 ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair176" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall0_r[1]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_96 ),
        .I3(\gen_old_sr_div4.gen_old_sr[1].old_sr_fall0_r_reg[1]_192 ),
        .O(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall0_r[1]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall0_r_reg[1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall0_r[1]_i_1_n_0 ),
        .Q(p_0_in432_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair139" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall1_r[1]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_72 ),
        .I3(\gen_old_sr_div4.gen_old_sr[1].old_sr_fall1_r_reg[1]_208 ),
        .O(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall1_r[1]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall1_r_reg[1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall1_r[1]_i_1_n_0 ),
        .Q(p_3_in434_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair145" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall2_r[1]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_80 ),
        .I3(\gen_old_sr_div4.gen_old_sr[1].old_sr_fall2_r_reg[1]_176 ),
        .O(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall2_r[1]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall2_r_reg[1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall2_r[1]_i_1_n_0 ),
        .Q(p_5_in436_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair180" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall3_r[1]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_56 ),
        .I3(\gen_old_sr_div4.gen_old_sr[1].old_sr_fall3_r_reg[1]_184 ),
        .O(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall3_r[1]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall3_r_reg[1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_fall3_r[1]_i_1_n_0 ),
        .Q(p_7_in438_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair167" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise0_r[1]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_48 ),
        .I3(\gen_old_sr_div4.gen_old_sr[1].old_sr_rise0_r_reg[1]_224 ),
        .O(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise0_r[1]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise0_r_reg[1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise0_r[1]_i_1_n_0 ),
        .Q(p_1_in439_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair133" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise1_r[1]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_88 ),
        .I3(\gen_old_sr_div4.gen_old_sr[1].old_sr_rise1_r_reg[1]_200 ),
        .O(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise1_r[1]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise1_r_reg[1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise1_r[1]_i_1_n_0 ),
        .Q(p_2_in433_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair171" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise2_r[1]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_64 ),
        .I3(\gen_old_sr_div4.gen_old_sr[1].old_sr_rise2_r_reg[1]_216 ),
        .O(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise2_r[1]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise2_r_reg[1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise2_r[1]_i_1_n_0 ),
        .Q(p_4_in435_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair163" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise3_r[1]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_104 ),
        .I3(\gen_old_sr_div4.gen_old_sr[1].old_sr_rise3_r_reg[1]_232 ),
        .O(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise3_r[1]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise3_r_reg[1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[1].old_sr_match_rise3_r[1]_i_1_n_0 ),
        .Q(p_6_in437_in),
        .R(1'b0));
  FDRE \gen_sr_match_div4.gen_sr_match[1].prev_sr_diff_r_reg[1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r_reg[1]_inv_n_0 ),
        .Q(p_0_in103_in),
        .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF7FFF)) 
    \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r[1]_inv_i_1 
       (.I0(p_6_in462_in),
        .I1(p_5_in461_in),
        .I2(p_7_in463_in),
        .I3(p_1_in464_in),
        .I4(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r[1]_inv_i_2_n_0 ),
        .O(p_465_out));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r[1]_inv_i_2 
       (.I0(p_3_in459_in),
        .I1(p_4_in460_in),
        .I2(p_2_in458_in),
        .I3(p_0_in457_in),
        .O(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r[1]_inv_i_2_n_0 ));
  FDRE #(
    .INIT(1'b1)) 
    \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r_reg[1]_inv 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(p_465_out),
        .Q(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_cyc2_r_reg[1]_inv_n_0 ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair176" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall0_r[1]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall0_r_reg[1]_96 ),
        .I3(\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall0_r_reg[1]_144 ),
        .O(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall0_r[1]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall0_r_reg[1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall0_r[1]_i_1_n_0 ),
        .Q(p_0_in457_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair139" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall1_r[1]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall1_r_reg[1]_72 ),
        .I3(\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall1_r_reg[1]_120 ),
        .O(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall1_r[1]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall1_r_reg[1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall1_r[1]_i_1_n_0 ),
        .Q(p_3_in459_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair145" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall2_r[1]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall2_r_reg[1]_80 ),
        .I3(\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall2_r_reg[1]_128 ),
        .O(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall2_r[1]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall2_r_reg[1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall2_r[1]_i_1_n_0 ),
        .Q(p_5_in461_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair180" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall3_r[1]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_fall3_r_reg[1]_56 ),
        .I3(\gen_old_sr_div4.gen_old_sr[1].prev_sr_fall3_r_reg[1]_152 ),
        .O(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall3_r[1]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall3_r_reg[1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_fall3_r[1]_i_1_n_0 ),
        .Q(p_7_in463_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair167" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise0_r[1]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise0_r_reg[1]_48 ),
        .I3(\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise0_r_reg[1]_160 ),
        .O(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise0_r[1]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise0_r_reg[1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise0_r[1]_i_1_n_0 ),
        .Q(p_1_in464_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair133" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise1_r[1]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise1_r_reg[1]_88 ),
        .I3(\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise1_r_reg[1]_112 ),
        .O(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise1_r[1]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise1_r_reg[1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise1_r[1]_i_1_n_0 ),
        .Q(p_2_in458_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair171" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise2_r[1]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise2_r_reg[1]_64 ),
        .I3(\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise2_r_reg[1]_136 ),
        .O(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise2_r[1]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise2_r_reg[1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise2_r[1]_i_1_n_0 ),
        .Q(p_4_in460_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair163" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise3_r[1]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[1].sr_rise3_r_reg[1]_104 ),
        .I3(\gen_old_sr_div4.gen_old_sr[1].prev_sr_rise3_r_reg[1]_168 ),
        .O(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise3_r[1]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise3_r_reg[1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[1].prev_sr_match_rise3_r[1]_i_1_n_0 ),
        .Q(p_6_in462_in),
        .R(1'b0));
  FDRE \gen_sr_match_div4.gen_sr_match[2].old_sr_diff_r_reg[2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r_reg[2]_inv_n_0 ),
        .Q(p_1_in14_in),
        .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF7FFF)) 
    \gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r[2]_inv_i_1 
       (.I0(p_7_in388_in),
        .I1(p_6_in387_in),
        .I2(p_5_in386_in),
        .I3(p_1_in389_in),
        .I4(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r[2]_inv_i_2_n_0 ),
        .O(p_390_out));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r[2]_inv_i_2 
       (.I0(p_3_in384_in),
        .I1(p_4_in385_in),
        .I2(p_0_in382_in),
        .I3(p_2_in383_in),
        .O(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r[2]_inv_i_2_n_0 ));
  FDRE #(
    .INIT(1'b1)) 
    \gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r_reg[2]_inv 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(p_390_out),
        .Q(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_cyc2_r_reg[2]_inv_n_0 ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair200" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall0_r[2]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_97 ),
        .I3(\gen_old_sr_div4.gen_old_sr[2].old_sr_fall0_r_reg[2]_193 ),
        .O(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall0_r[2]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall0_r_reg[2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall0_r[2]_i_1_n_0 ),
        .Q(p_0_in382_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair185" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall1_r[2]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_73 ),
        .I3(\gen_old_sr_div4.gen_old_sr[2].old_sr_fall1_r_reg[2]_209 ),
        .O(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall1_r[2]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall1_r_reg[2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall1_r[2]_i_1_n_0 ),
        .Q(p_3_in384_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair196" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall2_r[2]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_81 ),
        .I3(\gen_old_sr_div4.gen_old_sr[2].old_sr_fall2_r_reg[2]_177 ),
        .O(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall2_r[2]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall2_r_reg[2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall2_r[2]_i_1_n_0 ),
        .Q(p_5_in386_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair183" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall3_r[2]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_57 ),
        .I3(\gen_old_sr_div4.gen_old_sr[2].old_sr_fall3_r_reg[2]_185 ),
        .O(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall3_r[2]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall3_r_reg[2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_fall3_r[2]_i_1_n_0 ),
        .Q(p_7_in388_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair152" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise0_r[2]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_49 ),
        .I3(\gen_old_sr_div4.gen_old_sr[2].old_sr_rise0_r_reg[2]_225 ),
        .O(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise0_r[2]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise0_r_reg[2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise0_r[2]_i_1_n_0 ),
        .Q(p_1_in389_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair192" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise1_r[2]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_89 ),
        .I3(\gen_old_sr_div4.gen_old_sr[2].old_sr_rise1_r_reg[2]_201 ),
        .O(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise1_r[2]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise1_r_reg[2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise1_r[2]_i_1_n_0 ),
        .Q(p_2_in383_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair157" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise2_r[2]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_65 ),
        .I3(\gen_old_sr_div4.gen_old_sr[2].old_sr_rise2_r_reg[2]_217 ),
        .O(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise2_r[2]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise2_r_reg[2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise2_r[2]_i_1_n_0 ),
        .Q(p_4_in385_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair148" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise3_r[2]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_105 ),
        .I3(\gen_old_sr_div4.gen_old_sr[2].old_sr_rise3_r_reg[2]_233 ),
        .O(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise3_r[2]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise3_r_reg[2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[2].old_sr_match_rise3_r[2]_i_1_n_0 ),
        .Q(p_6_in387_in),
        .R(1'b0));
  FDRE \gen_sr_match_div4.gen_sr_match[2].prev_sr_diff_r_reg[2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r_reg[2]_inv_n_0 ),
        .Q(p_0_in100_in),
        .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF7FFF)) 
    \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r[2]_inv_i_1 
       (.I0(p_7_in413_in),
        .I1(p_5_in411_in),
        .I2(p_6_in412_in),
        .I3(p_1_in414_in),
        .I4(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r[2]_inv_i_2_n_0 ),
        .O(p_415_out));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r[2]_inv_i_2 
       (.I0(p_3_in409_in),
        .I1(p_4_in410_in),
        .I2(p_2_in408_in),
        .I3(p_0_in407_in),
        .O(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r[2]_inv_i_2_n_0 ));
  FDRE #(
    .INIT(1'b1)) 
    \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r_reg[2]_inv 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(p_415_out),
        .Q(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_cyc2_r_reg[2]_inv_n_0 ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair200" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall0_r[2]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall0_r_reg[2]_97 ),
        .I3(\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall0_r_reg[2]_145 ),
        .O(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall0_r[2]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall0_r_reg[2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall0_r[2]_i_1_n_0 ),
        .Q(p_0_in407_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair185" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall1_r[2]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall1_r_reg[2]_73 ),
        .I3(\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall1_r_reg[2]_121 ),
        .O(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall1_r[2]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall1_r_reg[2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall1_r[2]_i_1_n_0 ),
        .Q(p_3_in409_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair196" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall2_r[2]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall2_r_reg[2]_81 ),
        .I3(\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall2_r_reg[2]_129 ),
        .O(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall2_r[2]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall2_r_reg[2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall2_r[2]_i_1_n_0 ),
        .Q(p_5_in411_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair183" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall3_r[2]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_fall3_r_reg[2]_57 ),
        .I3(\gen_old_sr_div4.gen_old_sr[2].prev_sr_fall3_r_reg[2]_153 ),
        .O(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall3_r[2]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall3_r_reg[2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_fall3_r[2]_i_1_n_0 ),
        .Q(p_7_in413_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair152" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise0_r[2]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise0_r_reg[2]_49 ),
        .I3(\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise0_r_reg[2]_161 ),
        .O(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise0_r[2]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise0_r_reg[2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise0_r[2]_i_1_n_0 ),
        .Q(p_1_in414_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair192" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise1_r[2]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise1_r_reg[2]_89 ),
        .I3(\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise1_r_reg[2]_113 ),
        .O(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise1_r[2]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise1_r_reg[2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise1_r[2]_i_1_n_0 ),
        .Q(p_2_in408_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair157" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise2_r[2]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise2_r_reg[2]_65 ),
        .I3(\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise2_r_reg[2]_137 ),
        .O(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise2_r[2]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise2_r_reg[2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise2_r[2]_i_1_n_0 ),
        .Q(p_4_in410_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair148" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise3_r[2]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[2].sr_rise3_r_reg[2]_105 ),
        .I3(\gen_old_sr_div4.gen_old_sr[2].prev_sr_rise3_r_reg[2]_169 ),
        .O(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise3_r[2]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise3_r_reg[2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[2].prev_sr_match_rise3_r[2]_i_1_n_0 ),
        .Q(p_6_in412_in),
        .R(1'b0));
  FDRE \gen_sr_match_div4.gen_sr_match[3].old_sr_diff_r_reg[3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r_reg[3]_inv_n_0 ),
        .Q(p_1_in11_in),
        .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF7FFF)) 
    \gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r[3]_inv_i_1 
       (.I0(p_7_in338_in),
        .I1(p_6_in337_in),
        .I2(p_3_in334_in),
        .I3(p_1_in339_in),
        .I4(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r[3]_inv_i_2_n_0 ),
        .O(p_340_out));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r[3]_inv_i_2 
       (.I0(p_4_in335_in),
        .I1(p_5_in336_in),
        .I2(p_0_in332_in),
        .I3(p_2_in333_in),
        .O(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r[3]_inv_i_2_n_0 ));
  FDRE #(
    .INIT(1'b1)) 
    \gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r_reg[3]_inv 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(p_340_out),
        .Q(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_cyc2_r_reg[3]_inv_n_0 ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair175" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall0_r[3]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_98 ),
        .I3(\gen_old_sr_div4.gen_old_sr[3].old_sr_fall0_r_reg[3]_194 ),
        .O(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall0_r[3]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall0_r_reg[3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall0_r[3]_i_1_n_0 ),
        .Q(p_0_in332_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair141" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall1_r[3]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_74 ),
        .I3(\gen_old_sr_div4.gen_old_sr[3].old_sr_fall1_r_reg[3]_210 ),
        .O(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall1_r[3]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall1_r_reg[3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall1_r[3]_i_1_n_0 ),
        .Q(p_3_in334_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair144" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall2_r[3]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_82 ),
        .I3(\gen_old_sr_div4.gen_old_sr[3].old_sr_fall2_r_reg[3]_178 ),
        .O(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall2_r[3]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall2_r_reg[3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall2_r[3]_i_1_n_0 ),
        .Q(p_5_in336_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair179" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall3_r[3]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_58 ),
        .I3(\gen_old_sr_div4.gen_old_sr[3].old_sr_fall3_r_reg[3]_186 ),
        .O(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall3_r[3]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall3_r_reg[3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_fall3_r[3]_i_1_n_0 ),
        .Q(p_7_in338_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair166" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise0_r[3]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_50 ),
        .I3(\gen_old_sr_div4.gen_old_sr[3].old_sr_rise0_r_reg[3]_226 ),
        .O(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise0_r[3]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise0_r_reg[3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise0_r[3]_i_1_n_0 ),
        .Q(p_1_in339_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair172" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise1_r[3]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_90 ),
        .I3(\gen_old_sr_div4.gen_old_sr[3].old_sr_rise1_r_reg[3]_202 ),
        .O(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise1_r[3]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise1_r_reg[3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise1_r[3]_i_1_n_0 ),
        .Q(p_2_in333_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair170" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise2_r[3]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_66 ),
        .I3(\gen_old_sr_div4.gen_old_sr[3].old_sr_rise2_r_reg[3]_218 ),
        .O(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise2_r[3]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise2_r_reg[3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise2_r[3]_i_1_n_0 ),
        .Q(p_4_in335_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair162" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise3_r[3]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_106 ),
        .I3(\gen_old_sr_div4.gen_old_sr[3].old_sr_rise3_r_reg[3]_234 ),
        .O(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise3_r[3]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise3_r_reg[3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[3].old_sr_match_rise3_r[3]_i_1_n_0 ),
        .Q(p_6_in337_in),
        .R(1'b0));
  FDRE \gen_sr_match_div4.gen_sr_match[3].prev_sr_diff_r_reg[3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r_reg[3]_inv_n_0 ),
        .Q(p_0_in97_in),
        .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF7FFF)) 
    \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r[3]_inv_i_1 
       (.I0(p_5_in361_in),
        .I1(p_4_in360_in),
        .I2(p_7_in363_in),
        .I3(p_6_in362_in),
        .I4(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r[3]_inv_i_2_n_0 ),
        .O(p_365_out));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r[3]_inv_i_2 
       (.I0(p_0_in357_in),
        .I1(p_3_in359_in),
        .I2(p_2_in358_in),
        .I3(p_1_in364_in),
        .O(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r[3]_inv_i_2_n_0 ));
  FDRE #(
    .INIT(1'b1)) 
    \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r_reg[3]_inv 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(p_365_out),
        .Q(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_cyc2_r_reg[3]_inv_n_0 ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair175" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall0_r[3]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall0_r_reg[3]_98 ),
        .I3(\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall0_r_reg[3]_146 ),
        .O(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall0_r[3]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall0_r_reg[3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall0_r[3]_i_1_n_0 ),
        .Q(p_0_in357_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair141" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall1_r[3]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall1_r_reg[3]_74 ),
        .I3(\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall1_r_reg[3]_122 ),
        .O(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall1_r[3]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall1_r_reg[3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall1_r[3]_i_1_n_0 ),
        .Q(p_3_in359_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair144" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall2_r[3]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall2_r_reg[3]_82 ),
        .I3(\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall2_r_reg[3]_130 ),
        .O(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall2_r[3]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall2_r_reg[3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall2_r[3]_i_1_n_0 ),
        .Q(p_5_in361_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair179" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall3_r[3]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_fall3_r_reg[3]_58 ),
        .I3(\gen_old_sr_div4.gen_old_sr[3].prev_sr_fall3_r_reg[3]_154 ),
        .O(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall3_r[3]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall3_r_reg[3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_fall3_r[3]_i_1_n_0 ),
        .Q(p_7_in363_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair166" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise0_r[3]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise0_r_reg[3]_50 ),
        .I3(\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise0_r_reg[3]_162 ),
        .O(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise0_r[3]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise0_r_reg[3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise0_r[3]_i_1_n_0 ),
        .Q(p_1_in364_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair172" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise1_r[3]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise1_r_reg[3]_90 ),
        .I3(\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise1_r_reg[3]_114 ),
        .O(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise1_r[3]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise1_r_reg[3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise1_r[3]_i_1_n_0 ),
        .Q(p_2_in358_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair170" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise2_r[3]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise2_r_reg[3]_66 ),
        .I3(\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise2_r_reg[3]_138 ),
        .O(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise2_r[3]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise2_r_reg[3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise2_r[3]_i_1_n_0 ),
        .Q(p_4_in360_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair162" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise3_r[3]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[3].sr_rise3_r_reg[3]_106 ),
        .I3(\gen_old_sr_div4.gen_old_sr[3].prev_sr_rise3_r_reg[3]_170 ),
        .O(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise3_r[3]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise3_r_reg[3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[3].prev_sr_match_rise3_r[3]_i_1_n_0 ),
        .Q(p_6_in362_in),
        .R(1'b0));
  FDRE \gen_sr_match_div4.gen_sr_match[4].old_sr_diff_r_reg[4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r_reg[4]_inv_n_0 ),
        .Q(p_1_in8_in),
        .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF7FFF)) 
    \gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r[4]_inv_i_1 
       (.I0(p_7_in288_in),
        .I1(p_6_in287_in),
        .I2(p_0_in282_in),
        .I3(p_1_in289_in),
        .I4(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r[4]_inv_i_2_n_0 ),
        .O(p_290_out));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r[4]_inv_i_2 
       (.I0(p_4_in285_in),
        .I1(p_5_in286_in),
        .I2(p_2_in283_in),
        .I3(p_3_in284_in),
        .O(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r[4]_inv_i_2_n_0 ));
  FDRE #(
    .INIT(1'b1)) 
    \gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r_reg[4]_inv 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(p_290_out),
        .Q(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_cyc2_r_reg[4]_inv_n_0 ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair201" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall0_r[4]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_99 ),
        .I3(\gen_old_sr_div4.gen_old_sr[4].old_sr_fall0_r_reg[4]_195 ),
        .O(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall0_r[4]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall0_r_reg[4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall0_r[4]_i_1_n_0 ),
        .Q(p_0_in282_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair184" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall1_r[4]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_75 ),
        .I3(\gen_old_sr_div4.gen_old_sr[4].old_sr_fall1_r_reg[4]_211 ),
        .O(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall1_r[4]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall1_r_reg[4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall1_r[4]_i_1_n_0 ),
        .Q(p_3_in284_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair197" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall2_r[4]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_83 ),
        .I3(\gen_old_sr_div4.gen_old_sr[4].old_sr_fall2_r_reg[4]_179 ),
        .O(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall2_r[4]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall2_r_reg[4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall2_r[4]_i_1_n_0 ),
        .Q(p_5_in286_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair188" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall3_r[4]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_59 ),
        .I3(\gen_old_sr_div4.gen_old_sr[4].old_sr_fall3_r_reg[4]_187 ),
        .O(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall3_r[4]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall3_r_reg[4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_fall3_r[4]_i_1_n_0 ),
        .Q(p_7_in288_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair151" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise0_r[4]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_51 ),
        .I3(\gen_old_sr_div4.gen_old_sr[4].old_sr_rise0_r_reg[4]_227 ),
        .O(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise0_r[4]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise0_r_reg[4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise0_r[4]_i_1_n_0 ),
        .Q(p_1_in289_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair193" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise1_r[4]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_91 ),
        .I3(\gen_old_sr_div4.gen_old_sr[4].old_sr_rise1_r_reg[4]_203 ),
        .O(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise1_r[4]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise1_r_reg[4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise1_r[4]_i_1_n_0 ),
        .Q(p_2_in283_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair155" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise2_r[4]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_67 ),
        .I3(\gen_old_sr_div4.gen_old_sr[4].old_sr_rise2_r_reg[4]_219 ),
        .O(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise2_r[4]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise2_r_reg[4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise2_r[4]_i_1_n_0 ),
        .Q(p_4_in285_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair147" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise3_r[4]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_107 ),
        .I3(\gen_old_sr_div4.gen_old_sr[4].old_sr_rise3_r_reg[4]_235 ),
        .O(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise3_r[4]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise3_r_reg[4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[4].old_sr_match_rise3_r[4]_i_1_n_0 ),
        .Q(p_6_in287_in),
        .R(1'b0));
  FDRE \gen_sr_match_div4.gen_sr_match[4].prev_sr_diff_r_reg[4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r_reg[4]_inv_n_0 ),
        .Q(p_0_in94_in),
        .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF7FFF)) 
    \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r[4]_inv_i_1 
       (.I0(p_6_in312_in),
        .I1(p_5_in311_in),
        .I2(p_7_in313_in),
        .I3(p_1_in314_in),
        .I4(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r[4]_inv_i_2_n_0 ),
        .O(p_315_out));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r[4]_inv_i_2 
       (.I0(p_3_in309_in),
        .I1(p_4_in310_in),
        .I2(p_0_in307_in),
        .I3(p_2_in308_in),
        .O(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r[4]_inv_i_2_n_0 ));
  FDRE #(
    .INIT(1'b1)) 
    \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r_reg[4]_inv 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(p_315_out),
        .Q(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_cyc2_r_reg[4]_inv_n_0 ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair201" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall0_r[4]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall0_r_reg[4]_99 ),
        .I3(\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall0_r_reg[4]_147 ),
        .O(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall0_r[4]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall0_r_reg[4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall0_r[4]_i_1_n_0 ),
        .Q(p_0_in307_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair184" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall1_r[4]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall1_r_reg[4]_75 ),
        .I3(\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall1_r_reg[4]_123 ),
        .O(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall1_r[4]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall1_r_reg[4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall1_r[4]_i_1_n_0 ),
        .Q(p_3_in309_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair197" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall2_r[4]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall2_r_reg[4]_83 ),
        .I3(\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall2_r_reg[4]_131 ),
        .O(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall2_r[4]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall2_r_reg[4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall2_r[4]_i_1_n_0 ),
        .Q(p_5_in311_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair188" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall3_r[4]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_fall3_r_reg[4]_59 ),
        .I3(\gen_old_sr_div4.gen_old_sr[4].prev_sr_fall3_r_reg[4]_155 ),
        .O(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall3_r[4]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall3_r_reg[4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_fall3_r[4]_i_1_n_0 ),
        .Q(p_7_in313_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair151" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise0_r[4]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise0_r_reg[4]_51 ),
        .I3(\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise0_r_reg[4]_163 ),
        .O(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise0_r[4]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise0_r_reg[4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise0_r[4]_i_1_n_0 ),
        .Q(p_1_in314_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair193" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise1_r[4]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise1_r_reg[4]_91 ),
        .I3(\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise1_r_reg[4]_115 ),
        .O(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise1_r[4]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise1_r_reg[4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise1_r[4]_i_1_n_0 ),
        .Q(p_2_in308_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair155" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise2_r[4]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise2_r_reg[4]_67 ),
        .I3(\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise2_r_reg[4]_139 ),
        .O(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise2_r[4]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise2_r_reg[4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise2_r[4]_i_1_n_0 ),
        .Q(p_4_in310_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair147" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise3_r[4]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[4].sr_rise3_r_reg[4]_107 ),
        .I3(\gen_old_sr_div4.gen_old_sr[4].prev_sr_rise3_r_reg[4]_171 ),
        .O(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise3_r[4]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise3_r_reg[4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[4].prev_sr_match_rise3_r[4]_i_1_n_0 ),
        .Q(p_6_in312_in),
        .R(1'b0));
  FDRE \gen_sr_match_div4.gen_sr_match[5].old_sr_diff_r_reg[5] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r_reg[5]_inv_n_0 ),
        .Q(p_1_in5_in),
        .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF7FFF)) 
    \gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r[5]_inv_i_1 
       (.I0(p_7_in238_in),
        .I1(p_6_in237_in),
        .I2(p_0_in232_in),
        .I3(p_1_in239_in),
        .I4(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r[5]_inv_i_2_n_0 ),
        .O(p_240_out));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r[5]_inv_i_2 
       (.I0(p_4_in235_in),
        .I1(p_5_in236_in),
        .I2(p_2_in233_in),
        .I3(p_3_in234_in),
        .O(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r[5]_inv_i_2_n_0 ));
  FDRE #(
    .INIT(1'b1)) 
    \gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r_reg[5]_inv 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(p_240_out),
        .Q(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_cyc2_r_reg[5]_inv_n_0 ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair174" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall0_r[5]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_100 ),
        .I3(\gen_old_sr_div4.gen_old_sr[5].old_sr_fall0_r_reg[5]_196 ),
        .O(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall0_r[5]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall0_r_reg[5] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall0_r[5]_i_1_n_0 ),
        .Q(p_0_in232_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair143" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall1_r[5]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_76 ),
        .I3(\gen_old_sr_div4.gen_old_sr[5].old_sr_fall1_r_reg[5]_212 ),
        .O(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall1_r[5]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall1_r_reg[5] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall1_r[5]_i_1_n_0 ),
        .Q(p_3_in234_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair182" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall2_r[5]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_84 ),
        .I3(\gen_old_sr_div4.gen_old_sr[5].old_sr_fall2_r_reg[5]_180 ),
        .O(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall2_r[5]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall2_r_reg[5] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall2_r[5]_i_1_n_0 ),
        .Q(p_5_in236_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair178" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall3_r[5]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_60 ),
        .I3(\gen_old_sr_div4.gen_old_sr[5].old_sr_fall3_r_reg[5]_188 ),
        .O(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall3_r[5]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall3_r_reg[5] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_fall3_r[5]_i_1_n_0 ),
        .Q(p_7_in238_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair165" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise0_r[5]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_52 ),
        .I3(\gen_old_sr_div4.gen_old_sr[5].old_sr_rise0_r_reg[5]_228 ),
        .O(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise0_r[5]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise0_r_reg[5] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise0_r[5]_i_1_n_0 ),
        .Q(p_1_in239_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair135" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise1_r[5]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_92 ),
        .I3(\gen_old_sr_div4.gen_old_sr[5].old_sr_rise1_r_reg[5]_204 ),
        .O(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise1_r[5]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise1_r_reg[5] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise1_r[5]_i_1_n_0 ),
        .Q(p_2_in233_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair169" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise2_r[5]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_68 ),
        .I3(\gen_old_sr_div4.gen_old_sr[5].old_sr_rise2_r_reg[5]_220 ),
        .O(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise2_r[5]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise2_r_reg[5] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise2_r[5]_i_1_n_0 ),
        .Q(p_4_in235_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair161" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise3_r[5]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_108 ),
        .I3(\gen_old_sr_div4.gen_old_sr[5].old_sr_rise3_r_reg[5]_236 ),
        .O(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise3_r[5]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise3_r_reg[5] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[5].old_sr_match_rise3_r[5]_i_1_n_0 ),
        .Q(p_6_in237_in),
        .R(1'b0));
  FDRE \gen_sr_match_div4.gen_sr_match[5].prev_sr_diff_r_reg[5] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r_reg[5]_inv_n_0 ),
        .Q(p_0_in91_in),
        .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF7FFF)) 
    \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r[5]_inv_i_1 
       (.I0(p_7_in263_in),
        .I1(p_6_in262_in),
        .I2(p_0_in257_in),
        .I3(p_1_in264_in),
        .I4(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r[5]_inv_i_2_n_0 ),
        .O(p_265_out));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r[5]_inv_i_2 
       (.I0(p_4_in260_in),
        .I1(p_5_in261_in),
        .I2(p_2_in258_in),
        .I3(p_3_in259_in),
        .O(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r[5]_inv_i_2_n_0 ));
  FDRE #(
    .INIT(1'b1)) 
    \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r_reg[5]_inv 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(p_265_out),
        .Q(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_cyc2_r_reg[5]_inv_n_0 ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair174" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall0_r[5]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall0_r_reg[5]_100 ),
        .I3(\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall0_r_reg[5]_148 ),
        .O(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall0_r[5]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall0_r_reg[5] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall0_r[5]_i_1_n_0 ),
        .Q(p_0_in257_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair143" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall1_r[5]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall1_r_reg[5]_76 ),
        .I3(\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall1_r_reg[5]_124 ),
        .O(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall1_r[5]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall1_r_reg[5] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall1_r[5]_i_1_n_0 ),
        .Q(p_3_in259_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair182" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall2_r[5]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall2_r_reg[5]_84 ),
        .I3(\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall2_r_reg[5]_132 ),
        .O(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall2_r[5]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall2_r_reg[5] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall2_r[5]_i_1_n_0 ),
        .Q(p_5_in261_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair178" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall3_r[5]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_fall3_r_reg[5]_60 ),
        .I3(\gen_old_sr_div4.gen_old_sr[5].prev_sr_fall3_r_reg[5]_156 ),
        .O(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall3_r[5]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall3_r_reg[5] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_fall3_r[5]_i_1_n_0 ),
        .Q(p_7_in263_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair165" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise0_r[5]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise0_r_reg[5]_52 ),
        .I3(\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise0_r_reg[5]_164 ),
        .O(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise0_r[5]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise0_r_reg[5] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise0_r[5]_i_1_n_0 ),
        .Q(p_1_in264_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair135" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise1_r[5]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise1_r_reg[5]_92 ),
        .I3(\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise1_r_reg[5]_116 ),
        .O(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise1_r[5]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise1_r_reg[5] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise1_r[5]_i_1_n_0 ),
        .Q(p_2_in258_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair169" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise2_r[5]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise2_r_reg[5]_68 ),
        .I3(\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise2_r_reg[5]_140 ),
        .O(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise2_r[5]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise2_r_reg[5] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise2_r[5]_i_1_n_0 ),
        .Q(p_4_in260_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair161" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise3_r[5]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[5].sr_rise3_r_reg[5]_108 ),
        .I3(\gen_old_sr_div4.gen_old_sr[5].prev_sr_rise3_r_reg[5]_172 ),
        .O(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise3_r[5]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise3_r_reg[5] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[5].prev_sr_match_rise3_r[5]_i_1_n_0 ),
        .Q(p_6_in262_in),
        .R(1'b0));
  FDRE \gen_sr_match_div4.gen_sr_match[6].old_sr_diff_r_reg[6] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r_reg[6]_inv_n_0 ),
        .Q(p_1_in2_in),
        .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF7FFF)) 
    \gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r[6]_inv_i_1 
       (.I0(p_7_in188_in),
        .I1(p_6_in187_in),
        .I2(p_0_in182_in),
        .I3(p_1_in189_in),
        .I4(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r[6]_inv_i_2_n_0 ),
        .O(p_190_out));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r[6]_inv_i_2 
       (.I0(p_4_in185_in),
        .I1(p_5_in186_in),
        .I2(p_2_in183_in),
        .I3(p_3_in184_in),
        .O(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r[6]_inv_i_2_n_0 ));
  FDRE #(
    .INIT(1'b1)) 
    \gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r_reg[6]_inv 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(p_190_out),
        .Q(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_cyc2_r_reg[6]_inv_n_0 ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair202" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall0_r[6]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_101 ),
        .I3(\gen_old_sr_div4.gen_old_sr[6].old_sr_fall0_r_reg[6]_197 ),
        .O(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall0_r[6]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall0_r_reg[6] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall0_r[6]_i_1_n_0 ),
        .Q(p_0_in182_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair159" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall1_r[6]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_77 ),
        .I3(\gen_old_sr_div4.gen_old_sr[6].old_sr_fall1_r_reg[6]_213 ),
        .O(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall1_r[6]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall1_r_reg[6] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall1_r[6]_i_1_n_0 ),
        .Q(p_3_in184_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair198" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall2_r[6]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_85 ),
        .I3(\gen_old_sr_div4.gen_old_sr[6].old_sr_fall2_r_reg[6]_181 ),
        .O(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall2_r[6]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall2_r_reg[6] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall2_r[6]_i_1_n_0 ),
        .Q(p_5_in186_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair204" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall3_r[6]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_61 ),
        .I3(\gen_old_sr_div4.gen_old_sr[6].old_sr_fall3_r_reg[6]_189 ),
        .O(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall3_r[6]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall3_r_reg[6] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_fall3_r[6]_i_1_n_0 ),
        .Q(p_7_in188_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair150" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise0_r[6]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_53 ),
        .I3(\gen_old_sr_div4.gen_old_sr[6].old_sr_rise0_r_reg[6]_229 ),
        .O(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise0_r[6]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise0_r_reg[6] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise0_r[6]_i_1_n_0 ),
        .Q(p_1_in189_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair194" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise1_r[6]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_93 ),
        .I3(\gen_old_sr_div4.gen_old_sr[6].old_sr_rise1_r_reg[6]_205 ),
        .O(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise1_r[6]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise1_r_reg[6] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise1_r[6]_i_1_n_0 ),
        .Q(p_2_in183_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair154" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise2_r[6]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_69 ),
        .I3(\gen_old_sr_div4.gen_old_sr[6].old_sr_rise2_r_reg[6]_221 ),
        .O(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise2_r[6]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise2_r_reg[6] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise2_r[6]_i_1_n_0 ),
        .Q(p_4_in185_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair156" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise3_r[6]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_109 ),
        .I3(\gen_old_sr_div4.gen_old_sr[6].old_sr_rise3_r_reg[6]_237 ),
        .O(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise3_r[6]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise3_r_reg[6] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[6].old_sr_match_rise3_r[6]_i_1_n_0 ),
        .Q(p_6_in187_in),
        .R(1'b0));
  FDRE \gen_sr_match_div4.gen_sr_match[6].prev_sr_diff_r_reg[6] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r_reg[6]_inv_n_0 ),
        .Q(p_0_in88_in),
        .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF7FFF)) 
    \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r[6]_inv_i_1 
       (.I0(p_7_in213_in),
        .I1(p_6_in212_in),
        .I2(p_0_in207_in),
        .I3(p_1_in214_in),
        .I4(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r[6]_inv_i_2_n_0 ),
        .O(p_215_out));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r[6]_inv_i_2 
       (.I0(p_4_in210_in),
        .I1(p_5_in211_in),
        .I2(p_2_in208_in),
        .I3(p_3_in209_in),
        .O(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r[6]_inv_i_2_n_0 ));
  FDRE #(
    .INIT(1'b1)) 
    \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r_reg[6]_inv 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(p_215_out),
        .Q(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_cyc2_r_reg[6]_inv_n_0 ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair202" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall0_r[6]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall0_r_reg[6]_101 ),
        .I3(\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall0_r_reg[6]_149 ),
        .O(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall0_r[6]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall0_r_reg[6] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall0_r[6]_i_1_n_0 ),
        .Q(p_0_in207_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair159" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall1_r[6]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall1_r_reg[6]_77 ),
        .I3(\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall1_r_reg[6]_125 ),
        .O(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall1_r[6]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall1_r_reg[6] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall1_r[6]_i_1_n_0 ),
        .Q(p_3_in209_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair198" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall2_r[6]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall2_r_reg[6]_85 ),
        .I3(\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall2_r_reg[6]_133 ),
        .O(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall2_r[6]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall2_r_reg[6] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall2_r[6]_i_1_n_0 ),
        .Q(p_5_in211_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair204" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall3_r[6]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_fall3_r_reg[6]_61 ),
        .I3(\gen_old_sr_div4.gen_old_sr[6].prev_sr_fall3_r_reg[6]_157 ),
        .O(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall3_r[6]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall3_r_reg[6] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_fall3_r[6]_i_1_n_0 ),
        .Q(p_7_in213_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair150" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise0_r[6]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise0_r_reg[6]_53 ),
        .I3(\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise0_r_reg[6]_165 ),
        .O(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise0_r[6]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise0_r_reg[6] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise0_r[6]_i_1_n_0 ),
        .Q(p_1_in214_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair194" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise1_r[6]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise1_r_reg[6]_93 ),
        .I3(\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise1_r_reg[6]_117 ),
        .O(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise1_r[6]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise1_r_reg[6] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise1_r[6]_i_1_n_0 ),
        .Q(p_2_in208_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair154" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise2_r[6]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise2_r_reg[6]_69 ),
        .I3(\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise2_r_reg[6]_141 ),
        .O(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise2_r[6]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise2_r_reg[6] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise2_r[6]_i_1_n_0 ),
        .Q(p_4_in210_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair156" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise3_r[6]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[6].sr_rise3_r_reg[6]_109 ),
        .I3(\gen_old_sr_div4.gen_old_sr[6].prev_sr_rise3_r_reg[6]_173 ),
        .O(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise3_r[6]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise3_r_reg[6] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[6].prev_sr_match_rise3_r[6]_i_1_n_0 ),
        .Q(p_6_in212_in),
        .R(1'b0));
  FDRE \gen_sr_match_div4.gen_sr_match[7].old_sr_diff_r_reg[7] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r_reg[7]_inv_n_0 ),
        .Q(\gen_sr_match_div4.gen_sr_match[7].old_sr_diff_r_reg_n_0_[7] ),
        .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF7FFF)) 
    \gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r[7]_inv_i_1 
       (.I0(p_7_in),
        .I1(p_6_in137_in),
        .I2(p_0_in135_in),
        .I3(p_1_in138_in),
        .I4(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r[7]_inv_i_2_n_0 ),
        .O(p_139_out));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r[7]_inv_i_2 
       (.I0(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r_reg_n_0_[7] ),
        .I1(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall2_r_reg_n_0_[7] ),
        .I2(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r_reg_n_0_[7] ),
        .I3(p_3_in136_in),
        .O(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r[7]_inv_i_2_n_0 ));
  FDRE #(
    .INIT(1'b1)) 
    \gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r_reg[7]_inv 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(p_139_out),
        .Q(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_cyc2_r_reg[7]_inv_n_0 ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair173" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall0_r[7]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_102 ),
        .I3(\gen_old_sr_div4.gen_old_sr[7].old_sr_fall0_r_reg[7]_198 ),
        .O(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall0_r[7]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall0_r_reg[7] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall0_r[7]_i_1_n_0 ),
        .Q(p_0_in135_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair146" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall1_r[7]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_78 ),
        .I3(\gen_old_sr_div4.gen_old_sr[7].old_sr_fall1_r_reg[7]_214 ),
        .O(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall1_r[7]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall1_r_reg[7] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall1_r[7]_i_1_n_0 ),
        .Q(p_3_in136_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair181" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall2_r[7]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_86 ),
        .I3(\gen_old_sr_div4.gen_old_sr[7].old_sr_fall2_r_reg[7]_182 ),
        .O(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall2_r[7]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall2_r_reg[7] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall2_r[7]_i_1_n_0 ),
        .Q(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall2_r_reg_n_0_[7] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair177" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall3_r[7]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_62 ),
        .I3(\gen_old_sr_div4.gen_old_sr[7].old_sr_fall3_r_reg[7]_190 ),
        .O(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall3_r[7]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall3_r_reg[7] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_fall3_r[7]_i_1_n_0 ),
        .Q(p_7_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair164" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise0_r[7]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_54 ),
        .I3(\gen_old_sr_div4.gen_old_sr[7].old_sr_rise0_r_reg[7]_230 ),
        .O(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise0_r[7]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise0_r_reg[7] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise0_r[7]_i_1_n_0 ),
        .Q(p_1_in138_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair137" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r[7]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_94 ),
        .I3(\gen_old_sr_div4.gen_old_sr[7].old_sr_rise1_r_reg[7]_206 ),
        .O(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r[7]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r_reg[7] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r[7]_i_1_n_0 ),
        .Q(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise1_r_reg_n_0_[7] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair168" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r[7]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_70 ),
        .I3(\gen_old_sr_div4.gen_old_sr[7].old_sr_rise2_r_reg[7]_222 ),
        .O(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r[7]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r_reg[7] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r[7]_i_1_n_0 ),
        .Q(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise2_r_reg_n_0_[7] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair160" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r[7]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_110 ),
        .I3(\gen_old_sr_div4.gen_old_sr[7].old_sr_rise3_r_reg[7]_238 ),
        .O(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r[7]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r_reg[7] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[7].old_sr_match_rise3_r[7]_i_1_n_0 ),
        .Q(p_6_in137_in),
        .R(1'b0));
  FDRE \gen_sr_match_div4.gen_sr_match[7].prev_sr_diff_r_reg[7] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r_reg[7]_inv_n_0 ),
        .Q(\gen_sr_match_div4.gen_sr_match[7].prev_sr_diff_r_reg_n_0_[7] ),
        .R(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r[0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF7FFF)) 
    \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r[7]_inv_i_1 
       (.I0(p_7_in163_in),
        .I1(p_6_in162_in),
        .I2(p_0_in157_in),
        .I3(p_1_in164_in),
        .I4(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r[7]_inv_i_2_n_0 ),
        .O(p_165_out));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r[7]_inv_i_2 
       (.I0(p_4_in160_in),
        .I1(p_5_in161_in),
        .I2(p_2_in158_in),
        .I3(p_3_in159_in),
        .O(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r[7]_inv_i_2_n_0 ));
  FDRE #(
    .INIT(1'b1)) 
    \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r_reg[7]_inv 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(p_165_out),
        .Q(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_cyc2_r_reg[7]_inv_n_0 ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair173" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall0_r[7]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall0_r_reg[7]_102 ),
        .I3(\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall0_r_reg[7]_150 ),
        .O(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall0_r[7]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall0_r_reg[7] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall0_r[7]_i_1_n_0 ),
        .Q(p_0_in157_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair146" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall1_r[7]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall1_r_reg[7]_78 ),
        .I3(\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall1_r_reg[7]_126 ),
        .O(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall1_r[7]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall1_r_reg[7] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall1_r[7]_i_1_n_0 ),
        .Q(p_3_in159_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair181" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall2_r[7]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall2_r_reg[7]_86 ),
        .I3(\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall2_r_reg[7]_134 ),
        .O(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall2_r[7]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall2_r_reg[7] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall2_r[7]_i_1_n_0 ),
        .Q(p_5_in161_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair177" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall3_r[7]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_fall3_r_reg[7]_62 ),
        .I3(\gen_old_sr_div4.gen_old_sr[7].prev_sr_fall3_r_reg[7]_158 ),
        .O(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall3_r[7]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall3_r_reg[7] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_fall3_r[7]_i_1_n_0 ),
        .Q(p_7_in163_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair164" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise0_r[7]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise0_r_reg[7]_54 ),
        .I3(\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise0_r_reg[7]_166 ),
        .O(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise0_r[7]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise0_r_reg[7] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise0_r[7]_i_1_n_0 ),
        .Q(p_1_in164_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair137" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise1_r[7]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise1_r_reg[7]_94 ),
        .I3(\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise1_r_reg[7]_118 ),
        .O(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise1_r[7]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise1_r_reg[7] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise1_r[7]_i_1_n_0 ),
        .Q(p_2_in158_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair168" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise2_r[7]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise2_r_reg[7]_70 ),
        .I3(\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise2_r_reg[7]_142 ),
        .O(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise2_r[7]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise2_r_reg[7] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise2_r[7]_i_1_n_0 ),
        .Q(p_4_in160_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair160" *) 
  LUT4 #(
    .INIT(16'hE00E)) 
    \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise3_r[7]_i_1 
       (.I0(\gen_pat_match_div4.pat1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat0_data_match_r_reg_n_0 ),
        .I2(\gen_sr_div4.gen_sr_len_eq1.gen_sr[7].sr_rise3_r_reg[7]_110 ),
        .I3(\gen_old_sr_div4.gen_old_sr[7].prev_sr_rise3_r_reg[7]_174 ),
        .O(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise3_r[7]_i_1_n_0 ));
  FDRE \gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise3_r_reg[7] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_sr_match_div4.gen_sr_match[7].prev_sr_match_rise3_r[7]_i_1_n_0 ),
        .Q(p_6_in162_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair223" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \gen_track_left_edge[0].pb_cnt_eye_size_r[0][0]_i_1 
       (.I0(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_239 [0]),
        .O(p_0_in__3[0]));
  (* SOFT_HLUTNM = "soft_lutpair223" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \gen_track_left_edge[0].pb_cnt_eye_size_r[0][1]_i_1 
       (.I0(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_239 [1]),
        .I1(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_239 [0]),
        .O(p_0_in__3[1]));
  (* SOFT_HLUTNM = "soft_lutpair187" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \gen_track_left_edge[0].pb_cnt_eye_size_r[0][2]_i_1 
       (.I0(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_239 [2]),
        .I1(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_239 [0]),
        .I2(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_239 [1]),
        .O(p_0_in__3[2]));
  (* SOFT_HLUTNM = "soft_lutpair187" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \gen_track_left_edge[0].pb_cnt_eye_size_r[0][3]_i_1 
       (.I0(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_239 [3]),
        .I1(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_239 [1]),
        .I2(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_239 [0]),
        .I3(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_239 [2]),
        .O(p_0_in__3[3]));
  LUT5 #(
    .INIT(32'hFFEFAAAA)) 
    \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[16] ),
        .I1(\gen_track_left_edge[0].pb_last_tap_jitter_r_reg_n_0_[0] ),
        .I2(samp_cnt_done_r_reg_n_0),
        .I3(\gen_track_left_edge[0].pb_found_edge_r_reg_n_0_[0] ),
        .I4(\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_4_n_0 ),
        .O(\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h11100000)) 
    \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_2 
       (.I0(\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0 ),
        .I1(pb_detect_edge_done_r[0]),
        .I2(store_sr_req_pulsed_r),
        .I3(p_34_in),
        .I4(samp_cnt_done_r_reg_n_0),
        .O(pb_cnt_eye_size_r));
  (* SOFT_HLUTNM = "soft_lutpair105" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_3 
       (.I0(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_239 [4]),
        .I1(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_239 [2]),
        .I2(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_239 [0]),
        .I3(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_239 [1]),
        .I4(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_239 [3]),
        .O(p_0_in__3[4]));
  LUT6 #(
    .INIT(64'h1111111111111110)) 
    \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_4 
       (.I0(\FSM_onehot_cal1_state_r[34]_i_4_n_0 ),
        .I1(pb_detect_edge_done_r[0]),
        .I2(\gen_track_left_edge[0].pb_last_tap_jitter_r_reg_n_0_[0] ),
        .I3(\gen_sr_match_div4.gen_sr_match[0].old_sr_diff_r_reg_n_0_[0] ),
        .I4(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg_n_0_[0] ),
        .I5(samp_cnt_done_r_reg_n_0),
        .O(\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair105" *) 
  LUT5 #(
    .INIT(32'h00008000)) 
    \gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5 
       (.I0(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_239 [2]),
        .I1(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_239 [0]),
        .I2(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_239 [1]),
        .I3(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_239 [3]),
        .I4(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_239 [4]),
        .O(\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0 ));
  FDRE \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(pb_cnt_eye_size_r),
        .D(p_0_in__3[0]),
        .Q(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_239 [0]),
        .R(\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0][1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(pb_cnt_eye_size_r),
        .D(p_0_in__3[1]),
        .Q(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_239 [1]),
        .R(\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0][2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(pb_cnt_eye_size_r),
        .D(p_0_in__3[2]),
        .Q(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_239 [2]),
        .R(\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0][3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(pb_cnt_eye_size_r),
        .D(p_0_in__3[3]),
        .Q(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_239 [3]),
        .R(\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0][4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(pb_cnt_eye_size_r),
        .D(p_0_in__3[4]),
        .Q(\gen_track_left_edge[0].pb_cnt_eye_size_r_reg[0]_239 [4]),
        .R(\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hEEEEEEE0)) 
    \gen_track_left_edge[0].pb_detect_edge_done_r[0]_i_1 
       (.I0(store_sr_req_pulsed_r),
        .I1(p_34_in),
        .I2(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg_n_0_[0] ),
        .I3(samp_cnt_done_r_reg_n_0),
        .I4(pb_detect_edge_done_r[0]),
        .O(\gen_track_left_edge[0].pb_detect_edge_done_r[0]_i_1_n_0 ));
  FDRE \gen_track_left_edge[0].pb_detect_edge_done_r_reg[0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_track_left_edge[0].pb_detect_edge_done_r[0]_i_1_n_0 ),
        .Q(pb_detect_edge_done_r[0]),
        .R(\FSM_onehot_cal1_state_r_reg_n_0_[16] ));
  LUT6 #(
    .INIT(64'h5555555501000101)) 
    \gen_track_left_edge[0].pb_found_edge_r[0]_i_1 
       (.I0(\FSM_onehot_cal1_state_r[34]_i_4_n_0 ),
        .I1(pb_detect_edge_done_r[0]),
        .I2(\gen_track_left_edge[0].pb_found_edge_r[0]_i_2_n_0 ),
        .I3(\gen_track_left_edge[0].pb_last_tap_jitter_r_reg_n_0_[0] ),
        .I4(samp_cnt_done_r_reg_n_0),
        .I5(\gen_track_left_edge[0].pb_found_edge_r_reg_n_0_[0] ),
        .O(\gen_track_left_edge[0].pb_found_edge_r[0]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h0001)) 
    \gen_track_left_edge[0].pb_found_edge_r[0]_i_2 
       (.I0(samp_cnt_done_r_reg_n_0),
        .I1(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg_n_0_[0] ),
        .I2(\gen_sr_match_div4.gen_sr_match[0].old_sr_diff_r_reg_n_0_[0] ),
        .I3(\gen_track_left_edge[0].pb_last_tap_jitter_r_reg_n_0_[0] ),
        .O(\gen_track_left_edge[0].pb_found_edge_r[0]_i_2_n_0 ));
  FDRE \gen_track_left_edge[0].pb_found_edge_r_reg[0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_track_left_edge[0].pb_found_edge_r[0]_i_1_n_0 ),
        .Q(\gen_track_left_edge[0].pb_found_edge_r_reg_n_0_[0] ),
        .R(\FSM_onehot_cal1_state_r_reg_n_0_[16] ));
  LUT6 #(
    .INIT(64'h55555F5500000800)) 
    \gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_1 
       (.I0(\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_4_n_0 ),
        .I1(\gen_track_left_edge[0].pb_cnt_eye_size_r[0][4]_i_5_n_0 ),
        .I2(\gen_track_left_edge[0].pb_last_tap_jitter_r_reg_n_0_[0] ),
        .I3(samp_cnt_done_r_reg_n_0),
        .I4(\gen_track_left_edge[0].pb_found_edge_r_reg_n_0_[0] ),
        .I5(pb_found_stable_eye_r[0]),
        .O(\gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_1_n_0 ));
  FDRE \gen_track_left_edge[0].pb_found_stable_eye_r_reg[0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_track_left_edge[0].pb_found_stable_eye_r[0]_i_1_n_0 ),
        .Q(pb_found_stable_eye_r[0]),
        .R(\FSM_onehot_cal1_state_r_reg_n_0_[16] ));
  LUT6 #(
    .INIT(64'h00000000FDFD0100)) 
    \gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_1 
       (.I0(samp_cnt_done_r_reg_n_0),
        .I1(pb_detect_edge_done_r[0]),
        .I2(\FSM_onehot_cal1_state_r[34]_i_4_n_0 ),
        .I3(\gen_sr_match_div4.gen_sr_match[0].prev_sr_diff_r_reg_n_0_[0] ),
        .I4(\gen_track_left_edge[0].pb_last_tap_jitter_r_reg_n_0_[0] ),
        .I5(\FSM_onehot_cal1_state_r_reg_n_0_[16] ),
        .O(\gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_1_n_0 ));
  FDRE \gen_track_left_edge[0].pb_last_tap_jitter_r_reg[0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_track_left_edge[0].pb_last_tap_jitter_r[0]_i_1_n_0 ),
        .Q(\gen_track_left_edge[0].pb_last_tap_jitter_r_reg_n_0_[0] ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair224" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \gen_track_left_edge[1].pb_cnt_eye_size_r[1][0]_i_1 
       (.I0(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_240 [0]),
        .O(p_0_in__4[0]));
  (* SOFT_HLUTNM = "soft_lutpair224" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \gen_track_left_edge[1].pb_cnt_eye_size_r[1][1]_i_1 
       (.I0(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_240 [1]),
        .I1(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_240 [0]),
        .O(p_0_in__4[1]));
  (* SOFT_HLUTNM = "soft_lutpair142" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \gen_track_left_edge[1].pb_cnt_eye_size_r[1][2]_i_1 
       (.I0(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_240 [2]),
        .I1(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_240 [0]),
        .I2(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_240 [1]),
        .O(p_0_in__4[2]));
  (* SOFT_HLUTNM = "soft_lutpair142" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \gen_track_left_edge[1].pb_cnt_eye_size_r[1][3]_i_1 
       (.I0(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_240 [3]),
        .I1(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_240 [1]),
        .I2(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_240 [0]),
        .I3(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_240 [2]),
        .O(p_0_in__4[3]));
  LUT5 #(
    .INIT(32'hFFEFAAAA)) 
    \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[16] ),
        .I1(\gen_track_left_edge[1].pb_found_edge_r_reg_n_0_[1] ),
        .I2(samp_cnt_done_r_reg_n_0),
        .I3(p_0_in16_in),
        .I4(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_4_n_0 ),
        .O(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h11100000)) 
    \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2 
       (.I0(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_5_n_0 ),
        .I1(pb_detect_edge_done_r[1]),
        .I2(store_sr_req_pulsed_r),
        .I3(p_34_in),
        .I4(samp_cnt_done_r_reg_n_0),
        .O(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair83" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_3 
       (.I0(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_240 [4]),
        .I1(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_240 [2]),
        .I2(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_240 [0]),
        .I3(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_240 [1]),
        .I4(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_240 [3]),
        .O(p_0_in__4[4]));
  LUT6 #(
    .INIT(64'h1111111111111110)) 
    \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_4 
       (.I0(\FSM_onehot_cal1_state_r[34]_i_4_n_0 ),
        .I1(pb_detect_edge_done_r[1]),
        .I2(p_0_in16_in),
        .I3(p_1_in17_in),
        .I4(p_0_in103_in),
        .I5(samp_cnt_done_r_reg_n_0),
        .O(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair83" *) 
  LUT5 #(
    .INIT(32'h00008000)) 
    \gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_5 
       (.I0(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_240 [2]),
        .I1(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_240 [0]),
        .I2(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_240 [1]),
        .I3(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_240 [3]),
        .I4(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_240 [4]),
        .O(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_5_n_0 ));
  FDRE \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0 ),
        .D(p_0_in__4[0]),
        .Q(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_240 [0]),
        .R(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1][1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0 ),
        .D(p_0_in__4[1]),
        .Q(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_240 [1]),
        .R(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1][2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0 ),
        .D(p_0_in__4[2]),
        .Q(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_240 [2]),
        .R(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1][3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0 ),
        .D(p_0_in__4[3]),
        .Q(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_240 [3]),
        .R(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1][4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_2_n_0 ),
        .D(p_0_in__4[4]),
        .Q(\gen_track_left_edge[1].pb_cnt_eye_size_r_reg[1]_240 [4]),
        .R(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair82" *) 
  LUT5 #(
    .INIT(32'hEEEEEEE0)) 
    \gen_track_left_edge[1].pb_detect_edge_done_r[1]_i_1 
       (.I0(store_sr_req_pulsed_r),
        .I1(p_34_in),
        .I2(p_0_in103_in),
        .I3(samp_cnt_done_r_reg_n_0),
        .I4(pb_detect_edge_done_r[1]),
        .O(\gen_track_left_edge[1].pb_detect_edge_done_r[1]_i_1_n_0 ));
  FDRE \gen_track_left_edge[1].pb_detect_edge_done_r_reg[1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_track_left_edge[1].pb_detect_edge_done_r[1]_i_1_n_0 ),
        .Q(pb_detect_edge_done_r[1]),
        .R(\FSM_onehot_cal1_state_r_reg_n_0_[16] ));
  LUT6 #(
    .INIT(64'h5501550155005501)) 
    \gen_track_left_edge[1].pb_found_edge_r[1]_i_1 
       (.I0(\FSM_onehot_cal1_state_r[34]_i_4_n_0 ),
        .I1(pb_detect_edge_done_r[1]),
        .I2(\gen_track_left_edge[1].pb_found_edge_r[1]_i_2_n_0 ),
        .I3(\gen_track_left_edge[1].pb_found_edge_r_reg_n_0_[1] ),
        .I4(samp_cnt_done_r_reg_n_0),
        .I5(p_0_in16_in),
        .O(\gen_track_left_edge[1].pb_found_edge_r[1]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h0001)) 
    \gen_track_left_edge[1].pb_found_edge_r[1]_i_2 
       (.I0(samp_cnt_done_r_reg_n_0),
        .I1(p_0_in103_in),
        .I2(p_1_in17_in),
        .I3(p_0_in16_in),
        .O(\gen_track_left_edge[1].pb_found_edge_r[1]_i_2_n_0 ));
  FDRE \gen_track_left_edge[1].pb_found_edge_r_reg[1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_track_left_edge[1].pb_found_edge_r[1]_i_1_n_0 ),
        .Q(\gen_track_left_edge[1].pb_found_edge_r_reg_n_0_[1] ),
        .R(\FSM_onehot_cal1_state_r_reg_n_0_[16] ));
  LUT6 #(
    .INIT(64'h55555F5500000800)) 
    \gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_1 
       (.I0(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_4_n_0 ),
        .I1(\gen_track_left_edge[1].pb_cnt_eye_size_r[1][4]_i_5_n_0 ),
        .I2(\gen_track_left_edge[1].pb_found_edge_r_reg_n_0_[1] ),
        .I3(samp_cnt_done_r_reg_n_0),
        .I4(p_0_in16_in),
        .I5(pb_found_stable_eye_r[1]),
        .O(\gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_1_n_0 ));
  FDRE \gen_track_left_edge[1].pb_found_stable_eye_r_reg[1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_track_left_edge[1].pb_found_stable_eye_r[1]_i_1_n_0 ),
        .Q(pb_found_stable_eye_r[1]),
        .R(\FSM_onehot_cal1_state_r_reg_n_0_[16] ));
  LUT6 #(
    .INIT(64'h00000000FDFD0100)) 
    \gen_track_left_edge[1].pb_last_tap_jitter_r[1]_i_1 
       (.I0(samp_cnt_done_r_reg_n_0),
        .I1(pb_detect_edge_done_r[1]),
        .I2(\FSM_onehot_cal1_state_r[34]_i_4_n_0 ),
        .I3(p_0_in103_in),
        .I4(p_0_in16_in),
        .I5(\FSM_onehot_cal1_state_r_reg_n_0_[16] ),
        .O(\gen_track_left_edge[1].pb_last_tap_jitter_r[1]_i_1_n_0 ));
  FDRE \gen_track_left_edge[1].pb_last_tap_jitter_r_reg[1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_track_left_edge[1].pb_last_tap_jitter_r[1]_i_1_n_0 ),
        .Q(p_0_in16_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair225" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \gen_track_left_edge[2].pb_cnt_eye_size_r[2][0]_i_1 
       (.I0(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_241 [0]),
        .O(p_0_in__5[0]));
  (* SOFT_HLUTNM = "soft_lutpair225" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \gen_track_left_edge[2].pb_cnt_eye_size_r[2][1]_i_1 
       (.I0(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_241 [1]),
        .I1(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_241 [0]),
        .O(p_0_in__5[1]));
  (* SOFT_HLUTNM = "soft_lutpair189" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \gen_track_left_edge[2].pb_cnt_eye_size_r[2][2]_i_1 
       (.I0(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_241 [2]),
        .I1(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_241 [0]),
        .I2(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_241 [1]),
        .O(p_0_in__5[2]));
  (* SOFT_HLUTNM = "soft_lutpair189" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \gen_track_left_edge[2].pb_cnt_eye_size_r[2][3]_i_1 
       (.I0(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_241 [3]),
        .I1(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_241 [1]),
        .I2(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_241 [0]),
        .I3(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_241 [2]),
        .O(p_0_in__5[3]));
  LUT5 #(
    .INIT(32'hFFEFAAAA)) 
    \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[16] ),
        .I1(\gen_track_left_edge[2].pb_found_edge_r_reg_n_0_[2] ),
        .I2(samp_cnt_done_r_reg_n_0),
        .I3(p_0_in13_in),
        .I4(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_4_n_0 ),
        .O(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h11100000)) 
    \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2 
       (.I0(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_5_n_0 ),
        .I1(pb_detect_edge_done_r[2]),
        .I2(store_sr_req_pulsed_r),
        .I3(p_34_in),
        .I4(samp_cnt_done_r_reg_n_0),
        .O(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair91" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_3 
       (.I0(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_241 [4]),
        .I1(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_241 [2]),
        .I2(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_241 [0]),
        .I3(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_241 [1]),
        .I4(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_241 [3]),
        .O(p_0_in__5[4]));
  LUT6 #(
    .INIT(64'h1111111111111110)) 
    \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_4 
       (.I0(\FSM_onehot_cal1_state_r[34]_i_4_n_0 ),
        .I1(pb_detect_edge_done_r[2]),
        .I2(p_0_in13_in),
        .I3(p_1_in14_in),
        .I4(p_0_in100_in),
        .I5(samp_cnt_done_r_reg_n_0),
        .O(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair91" *) 
  LUT5 #(
    .INIT(32'h00008000)) 
    \gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_5 
       (.I0(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_241 [2]),
        .I1(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_241 [0]),
        .I2(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_241 [1]),
        .I3(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_241 [3]),
        .I4(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_241 [4]),
        .O(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_5_n_0 ));
  FDRE \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0 ),
        .D(p_0_in__5[0]),
        .Q(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_241 [0]),
        .R(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2][1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0 ),
        .D(p_0_in__5[1]),
        .Q(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_241 [1]),
        .R(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2][2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0 ),
        .D(p_0_in__5[2]),
        .Q(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_241 [2]),
        .R(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2][3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0 ),
        .D(p_0_in__5[3]),
        .Q(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_241 [3]),
        .R(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2][4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_2_n_0 ),
        .D(p_0_in__5[4]),
        .Q(\gen_track_left_edge[2].pb_cnt_eye_size_r_reg[2]_241 [4]),
        .R(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hEEEEEEE0)) 
    \gen_track_left_edge[2].pb_detect_edge_done_r[2]_i_1 
       (.I0(store_sr_req_pulsed_r),
        .I1(p_34_in),
        .I2(p_0_in100_in),
        .I3(samp_cnt_done_r_reg_n_0),
        .I4(pb_detect_edge_done_r[2]),
        .O(\gen_track_left_edge[2].pb_detect_edge_done_r[2]_i_1_n_0 ));
  FDRE \gen_track_left_edge[2].pb_detect_edge_done_r_reg[2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_track_left_edge[2].pb_detect_edge_done_r[2]_i_1_n_0 ),
        .Q(pb_detect_edge_done_r[2]),
        .R(\FSM_onehot_cal1_state_r_reg_n_0_[16] ));
  LUT6 #(
    .INIT(64'h5501550155005501)) 
    \gen_track_left_edge[2].pb_found_edge_r[2]_i_1 
       (.I0(\FSM_onehot_cal1_state_r[34]_i_4_n_0 ),
        .I1(pb_detect_edge_done_r[2]),
        .I2(\gen_track_left_edge[2].pb_found_edge_r[2]_i_2_n_0 ),
        .I3(\gen_track_left_edge[2].pb_found_edge_r_reg_n_0_[2] ),
        .I4(samp_cnt_done_r_reg_n_0),
        .I5(p_0_in13_in),
        .O(\gen_track_left_edge[2].pb_found_edge_r[2]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h0001)) 
    \gen_track_left_edge[2].pb_found_edge_r[2]_i_2 
       (.I0(samp_cnt_done_r_reg_n_0),
        .I1(p_0_in100_in),
        .I2(p_1_in14_in),
        .I3(p_0_in13_in),
        .O(\gen_track_left_edge[2].pb_found_edge_r[2]_i_2_n_0 ));
  FDRE \gen_track_left_edge[2].pb_found_edge_r_reg[2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_track_left_edge[2].pb_found_edge_r[2]_i_1_n_0 ),
        .Q(\gen_track_left_edge[2].pb_found_edge_r_reg_n_0_[2] ),
        .R(\FSM_onehot_cal1_state_r_reg_n_0_[16] ));
  LUT6 #(
    .INIT(64'h55555F5500000800)) 
    \gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_1 
       (.I0(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_4_n_0 ),
        .I1(\gen_track_left_edge[2].pb_cnt_eye_size_r[2][4]_i_5_n_0 ),
        .I2(\gen_track_left_edge[2].pb_found_edge_r_reg_n_0_[2] ),
        .I3(samp_cnt_done_r_reg_n_0),
        .I4(p_0_in13_in),
        .I5(pb_found_stable_eye_r[2]),
        .O(\gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_1_n_0 ));
  FDRE \gen_track_left_edge[2].pb_found_stable_eye_r_reg[2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_track_left_edge[2].pb_found_stable_eye_r[2]_i_1_n_0 ),
        .Q(pb_found_stable_eye_r[2]),
        .R(\FSM_onehot_cal1_state_r_reg_n_0_[16] ));
  LUT6 #(
    .INIT(64'h00000000FDFD0100)) 
    \gen_track_left_edge[2].pb_last_tap_jitter_r[2]_i_1 
       (.I0(samp_cnt_done_r_reg_n_0),
        .I1(pb_detect_edge_done_r[2]),
        .I2(\FSM_onehot_cal1_state_r[34]_i_4_n_0 ),
        .I3(p_0_in100_in),
        .I4(p_0_in13_in),
        .I5(\FSM_onehot_cal1_state_r_reg_n_0_[16] ),
        .O(\gen_track_left_edge[2].pb_last_tap_jitter_r[2]_i_1_n_0 ));
  FDRE \gen_track_left_edge[2].pb_last_tap_jitter_r_reg[2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_track_left_edge[2].pb_last_tap_jitter_r[2]_i_1_n_0 ),
        .Q(p_0_in13_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair226" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \gen_track_left_edge[3].pb_cnt_eye_size_r[3][0]_i_1 
       (.I0(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_242 [0]),
        .O(p_0_in__6[0]));
  (* SOFT_HLUTNM = "soft_lutpair226" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \gen_track_left_edge[3].pb_cnt_eye_size_r[3][1]_i_1 
       (.I0(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_242 [1]),
        .I1(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_242 [0]),
        .O(p_0_in__6[1]));
  (* SOFT_HLUTNM = "soft_lutpair140" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \gen_track_left_edge[3].pb_cnt_eye_size_r[3][2]_i_1 
       (.I0(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_242 [2]),
        .I1(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_242 [0]),
        .I2(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_242 [1]),
        .O(p_0_in__6[2]));
  (* SOFT_HLUTNM = "soft_lutpair140" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \gen_track_left_edge[3].pb_cnt_eye_size_r[3][3]_i_1 
       (.I0(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_242 [3]),
        .I1(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_242 [1]),
        .I2(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_242 [0]),
        .I3(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_242 [2]),
        .O(p_0_in__6[3]));
  LUT5 #(
    .INIT(32'hFFEFAAAA)) 
    \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[16] ),
        .I1(\gen_track_left_edge[3].pb_found_edge_r_reg_n_0_[3] ),
        .I2(samp_cnt_done_r_reg_n_0),
        .I3(p_0_in10_in),
        .I4(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_4_n_0 ),
        .O(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h11100000)) 
    \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2 
       (.I0(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_5_n_0 ),
        .I1(pb_detect_edge_done_r[3]),
        .I2(store_sr_req_pulsed_r),
        .I3(p_34_in),
        .I4(samp_cnt_done_r_reg_n_0),
        .O(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair92" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_3 
       (.I0(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_242 [4]),
        .I1(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_242 [2]),
        .I2(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_242 [0]),
        .I3(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_242 [1]),
        .I4(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_242 [3]),
        .O(p_0_in__6[4]));
  LUT6 #(
    .INIT(64'h1111111111111110)) 
    \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_4 
       (.I0(\FSM_onehot_cal1_state_r[34]_i_4_n_0 ),
        .I1(pb_detect_edge_done_r[3]),
        .I2(p_0_in10_in),
        .I3(p_1_in11_in),
        .I4(p_0_in97_in),
        .I5(samp_cnt_done_r_reg_n_0),
        .O(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair92" *) 
  LUT5 #(
    .INIT(32'h00008000)) 
    \gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_5 
       (.I0(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_242 [2]),
        .I1(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_242 [0]),
        .I2(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_242 [1]),
        .I3(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_242 [3]),
        .I4(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_242 [4]),
        .O(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_5_n_0 ));
  FDRE \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0 ),
        .D(p_0_in__6[0]),
        .Q(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_242 [0]),
        .R(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3][1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0 ),
        .D(p_0_in__6[1]),
        .Q(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_242 [1]),
        .R(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3][2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0 ),
        .D(p_0_in__6[2]),
        .Q(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_242 [2]),
        .R(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3][3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0 ),
        .D(p_0_in__6[3]),
        .Q(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_242 [3]),
        .R(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3][4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_2_n_0 ),
        .D(p_0_in__6[4]),
        .Q(\gen_track_left_edge[3].pb_cnt_eye_size_r_reg[3]_242 [4]),
        .R(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hEEEEEEE0)) 
    \gen_track_left_edge[3].pb_detect_edge_done_r[3]_i_1 
       (.I0(store_sr_req_pulsed_r),
        .I1(p_34_in),
        .I2(p_0_in97_in),
        .I3(samp_cnt_done_r_reg_n_0),
        .I4(pb_detect_edge_done_r[3]),
        .O(\gen_track_left_edge[3].pb_detect_edge_done_r[3]_i_1_n_0 ));
  FDRE \gen_track_left_edge[3].pb_detect_edge_done_r_reg[3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_track_left_edge[3].pb_detect_edge_done_r[3]_i_1_n_0 ),
        .Q(pb_detect_edge_done_r[3]),
        .R(\FSM_onehot_cal1_state_r_reg_n_0_[16] ));
  LUT6 #(
    .INIT(64'h5501550155005501)) 
    \gen_track_left_edge[3].pb_found_edge_r[3]_i_1 
       (.I0(\FSM_onehot_cal1_state_r[34]_i_4_n_0 ),
        .I1(pb_detect_edge_done_r[3]),
        .I2(\gen_track_left_edge[3].pb_found_edge_r[3]_i_2_n_0 ),
        .I3(\gen_track_left_edge[3].pb_found_edge_r_reg_n_0_[3] ),
        .I4(samp_cnt_done_r_reg_n_0),
        .I5(p_0_in10_in),
        .O(\gen_track_left_edge[3].pb_found_edge_r[3]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h0001)) 
    \gen_track_left_edge[3].pb_found_edge_r[3]_i_2 
       (.I0(samp_cnt_done_r_reg_n_0),
        .I1(p_0_in97_in),
        .I2(p_1_in11_in),
        .I3(p_0_in10_in),
        .O(\gen_track_left_edge[3].pb_found_edge_r[3]_i_2_n_0 ));
  FDRE \gen_track_left_edge[3].pb_found_edge_r_reg[3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_track_left_edge[3].pb_found_edge_r[3]_i_1_n_0 ),
        .Q(\gen_track_left_edge[3].pb_found_edge_r_reg_n_0_[3] ),
        .R(\FSM_onehot_cal1_state_r_reg_n_0_[16] ));
  LUT6 #(
    .INIT(64'h55555F5500000800)) 
    \gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_1 
       (.I0(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_4_n_0 ),
        .I1(\gen_track_left_edge[3].pb_cnt_eye_size_r[3][4]_i_5_n_0 ),
        .I2(\gen_track_left_edge[3].pb_found_edge_r_reg_n_0_[3] ),
        .I3(samp_cnt_done_r_reg_n_0),
        .I4(p_0_in10_in),
        .I5(pb_found_stable_eye_r[3]),
        .O(\gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_1_n_0 ));
  FDRE \gen_track_left_edge[3].pb_found_stable_eye_r_reg[3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_track_left_edge[3].pb_found_stable_eye_r[3]_i_1_n_0 ),
        .Q(pb_found_stable_eye_r[3]),
        .R(\FSM_onehot_cal1_state_r_reg_n_0_[16] ));
  LUT6 #(
    .INIT(64'h00000000FDFD0100)) 
    \gen_track_left_edge[3].pb_last_tap_jitter_r[3]_i_1 
       (.I0(samp_cnt_done_r_reg_n_0),
        .I1(pb_detect_edge_done_r[3]),
        .I2(\FSM_onehot_cal1_state_r[34]_i_4_n_0 ),
        .I3(p_0_in97_in),
        .I4(p_0_in10_in),
        .I5(\FSM_onehot_cal1_state_r_reg_n_0_[16] ),
        .O(\gen_track_left_edge[3].pb_last_tap_jitter_r[3]_i_1_n_0 ));
  FDRE \gen_track_left_edge[3].pb_last_tap_jitter_r_reg[3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_track_left_edge[3].pb_last_tap_jitter_r[3]_i_1_n_0 ),
        .Q(p_0_in10_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair227" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \gen_track_left_edge[4].pb_cnt_eye_size_r[4][0]_i_1 
       (.I0(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_243 [0]),
        .O(p_0_in__7[0]));
  (* SOFT_HLUTNM = "soft_lutpair227" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \gen_track_left_edge[4].pb_cnt_eye_size_r[4][1]_i_1 
       (.I0(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_243 [1]),
        .I1(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_243 [0]),
        .O(p_0_in__7[1]));
  (* SOFT_HLUTNM = "soft_lutpair138" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \gen_track_left_edge[4].pb_cnt_eye_size_r[4][2]_i_1 
       (.I0(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_243 [2]),
        .I1(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_243 [0]),
        .I2(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_243 [1]),
        .O(p_0_in__7[2]));
  (* SOFT_HLUTNM = "soft_lutpair138" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \gen_track_left_edge[4].pb_cnt_eye_size_r[4][3]_i_1 
       (.I0(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_243 [3]),
        .I1(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_243 [1]),
        .I2(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_243 [0]),
        .I3(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_243 [2]),
        .O(p_0_in__7[3]));
  LUT5 #(
    .INIT(32'hFFEFAAAA)) 
    \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[16] ),
        .I1(\gen_track_left_edge[4].pb_found_edge_r_reg_n_0_[4] ),
        .I2(samp_cnt_done_r_reg_n_0),
        .I3(p_0_in7_in),
        .I4(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_4_n_0 ),
        .O(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h11100000)) 
    \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2 
       (.I0(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_5_n_0 ),
        .I1(pb_detect_edge_done_r[4]),
        .I2(store_sr_req_pulsed_r),
        .I3(p_34_in),
        .I4(samp_cnt_done_r_reg_n_0),
        .O(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair93" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_3 
       (.I0(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_243 [4]),
        .I1(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_243 [2]),
        .I2(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_243 [0]),
        .I3(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_243 [1]),
        .I4(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_243 [3]),
        .O(p_0_in__7[4]));
  LUT6 #(
    .INIT(64'h1111111111111110)) 
    \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_4 
       (.I0(\FSM_onehot_cal1_state_r[34]_i_4_n_0 ),
        .I1(pb_detect_edge_done_r[4]),
        .I2(p_0_in7_in),
        .I3(p_1_in8_in),
        .I4(p_0_in94_in),
        .I5(samp_cnt_done_r_reg_n_0),
        .O(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair93" *) 
  LUT5 #(
    .INIT(32'h00008000)) 
    \gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_5 
       (.I0(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_243 [2]),
        .I1(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_243 [0]),
        .I2(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_243 [1]),
        .I3(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_243 [3]),
        .I4(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_243 [4]),
        .O(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_5_n_0 ));
  FDRE \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0 ),
        .D(p_0_in__7[0]),
        .Q(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_243 [0]),
        .R(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4][1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0 ),
        .D(p_0_in__7[1]),
        .Q(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_243 [1]),
        .R(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4][2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0 ),
        .D(p_0_in__7[2]),
        .Q(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_243 [2]),
        .R(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4][3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0 ),
        .D(p_0_in__7[3]),
        .Q(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_243 [3]),
        .R(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4][4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_2_n_0 ),
        .D(p_0_in__7[4]),
        .Q(\gen_track_left_edge[4].pb_cnt_eye_size_r_reg[4]_243 [4]),
        .R(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hEEEEEEE0)) 
    \gen_track_left_edge[4].pb_detect_edge_done_r[4]_i_1 
       (.I0(store_sr_req_pulsed_r),
        .I1(p_34_in),
        .I2(p_0_in94_in),
        .I3(samp_cnt_done_r_reg_n_0),
        .I4(pb_detect_edge_done_r[4]),
        .O(\gen_track_left_edge[4].pb_detect_edge_done_r[4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[4].pb_detect_edge_done_r_reg[4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_track_left_edge[4].pb_detect_edge_done_r[4]_i_1_n_0 ),
        .Q(pb_detect_edge_done_r[4]),
        .R(\FSM_onehot_cal1_state_r_reg_n_0_[16] ));
  LUT6 #(
    .INIT(64'h5501550155005501)) 
    \gen_track_left_edge[4].pb_found_edge_r[4]_i_1 
       (.I0(\FSM_onehot_cal1_state_r[34]_i_4_n_0 ),
        .I1(pb_detect_edge_done_r[4]),
        .I2(\gen_track_left_edge[4].pb_found_edge_r[4]_i_2_n_0 ),
        .I3(\gen_track_left_edge[4].pb_found_edge_r_reg_n_0_[4] ),
        .I4(samp_cnt_done_r_reg_n_0),
        .I5(p_0_in7_in),
        .O(\gen_track_left_edge[4].pb_found_edge_r[4]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h0001)) 
    \gen_track_left_edge[4].pb_found_edge_r[4]_i_2 
       (.I0(samp_cnt_done_r_reg_n_0),
        .I1(p_0_in94_in),
        .I2(p_1_in8_in),
        .I3(p_0_in7_in),
        .O(\gen_track_left_edge[4].pb_found_edge_r[4]_i_2_n_0 ));
  FDRE \gen_track_left_edge[4].pb_found_edge_r_reg[4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_track_left_edge[4].pb_found_edge_r[4]_i_1_n_0 ),
        .Q(\gen_track_left_edge[4].pb_found_edge_r_reg_n_0_[4] ),
        .R(\FSM_onehot_cal1_state_r_reg_n_0_[16] ));
  LUT6 #(
    .INIT(64'h55555F5500000800)) 
    \gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_1 
       (.I0(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_4_n_0 ),
        .I1(\gen_track_left_edge[4].pb_cnt_eye_size_r[4][4]_i_5_n_0 ),
        .I2(\gen_track_left_edge[4].pb_found_edge_r_reg_n_0_[4] ),
        .I3(samp_cnt_done_r_reg_n_0),
        .I4(p_0_in7_in),
        .I5(pb_found_stable_eye_r[4]),
        .O(\gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[4].pb_found_stable_eye_r_reg[4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_track_left_edge[4].pb_found_stable_eye_r[4]_i_1_n_0 ),
        .Q(pb_found_stable_eye_r[4]),
        .R(\FSM_onehot_cal1_state_r_reg_n_0_[16] ));
  LUT6 #(
    .INIT(64'h00000000FDFD0100)) 
    \gen_track_left_edge[4].pb_last_tap_jitter_r[4]_i_1 
       (.I0(samp_cnt_done_r_reg_n_0),
        .I1(pb_detect_edge_done_r[4]),
        .I2(\FSM_onehot_cal1_state_r[34]_i_4_n_0 ),
        .I3(p_0_in94_in),
        .I4(p_0_in7_in),
        .I5(\FSM_onehot_cal1_state_r_reg_n_0_[16] ),
        .O(\gen_track_left_edge[4].pb_last_tap_jitter_r[4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[4].pb_last_tap_jitter_r_reg[4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_track_left_edge[4].pb_last_tap_jitter_r[4]_i_1_n_0 ),
        .Q(p_0_in7_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair228" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \gen_track_left_edge[5].pb_cnt_eye_size_r[5][0]_i_1 
       (.I0(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_244 [0]),
        .O(p_0_in__8[0]));
  (* SOFT_HLUTNM = "soft_lutpair228" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \gen_track_left_edge[5].pb_cnt_eye_size_r[5][1]_i_1 
       (.I0(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_244 [1]),
        .I1(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_244 [0]),
        .O(p_0_in__8[1]));
  (* SOFT_HLUTNM = "soft_lutpair190" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \gen_track_left_edge[5].pb_cnt_eye_size_r[5][2]_i_1 
       (.I0(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_244 [2]),
        .I1(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_244 [0]),
        .I2(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_244 [1]),
        .O(p_0_in__8[2]));
  (* SOFT_HLUTNM = "soft_lutpair190" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \gen_track_left_edge[5].pb_cnt_eye_size_r[5][3]_i_1 
       (.I0(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_244 [3]),
        .I1(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_244 [1]),
        .I2(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_244 [0]),
        .I3(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_244 [2]),
        .O(p_0_in__8[3]));
  LUT5 #(
    .INIT(32'hFFEFAAAA)) 
    \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[16] ),
        .I1(\gen_track_left_edge[5].pb_found_edge_r_reg_n_0_[5] ),
        .I2(samp_cnt_done_r_reg_n_0),
        .I3(p_0_in4_in),
        .I4(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_4_n_0 ),
        .O(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h11100000)) 
    \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2 
       (.I0(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_5_n_0 ),
        .I1(pb_detect_edge_done_r[5]),
        .I2(store_sr_req_pulsed_r),
        .I3(p_34_in),
        .I4(samp_cnt_done_r_reg_n_0),
        .O(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair95" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_3 
       (.I0(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_244 [4]),
        .I1(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_244 [2]),
        .I2(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_244 [0]),
        .I3(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_244 [1]),
        .I4(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_244 [3]),
        .O(p_0_in__8[4]));
  LUT6 #(
    .INIT(64'h1111111111111110)) 
    \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_4 
       (.I0(\FSM_onehot_cal1_state_r[34]_i_4_n_0 ),
        .I1(pb_detect_edge_done_r[5]),
        .I2(p_0_in4_in),
        .I3(p_1_in5_in),
        .I4(p_0_in91_in),
        .I5(samp_cnt_done_r_reg_n_0),
        .O(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair95" *) 
  LUT5 #(
    .INIT(32'h00008000)) 
    \gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_5 
       (.I0(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_244 [2]),
        .I1(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_244 [0]),
        .I2(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_244 [1]),
        .I3(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_244 [3]),
        .I4(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_244 [4]),
        .O(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_5_n_0 ));
  FDRE \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0 ),
        .D(p_0_in__8[0]),
        .Q(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_244 [0]),
        .R(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5][1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0 ),
        .D(p_0_in__8[1]),
        .Q(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_244 [1]),
        .R(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5][2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0 ),
        .D(p_0_in__8[2]),
        .Q(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_244 [2]),
        .R(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5][3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0 ),
        .D(p_0_in__8[3]),
        .Q(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_244 [3]),
        .R(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5][4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_2_n_0 ),
        .D(p_0_in__8[4]),
        .Q(\gen_track_left_edge[5].pb_cnt_eye_size_r_reg[5]_244 [4]),
        .R(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hEEEEEEE0)) 
    \gen_track_left_edge[5].pb_detect_edge_done_r[5]_i_1 
       (.I0(store_sr_req_pulsed_r),
        .I1(p_34_in),
        .I2(p_0_in91_in),
        .I3(samp_cnt_done_r_reg_n_0),
        .I4(pb_detect_edge_done_r[5]),
        .O(\gen_track_left_edge[5].pb_detect_edge_done_r[5]_i_1_n_0 ));
  FDRE \gen_track_left_edge[5].pb_detect_edge_done_r_reg[5] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_track_left_edge[5].pb_detect_edge_done_r[5]_i_1_n_0 ),
        .Q(pb_detect_edge_done_r[5]),
        .R(\FSM_onehot_cal1_state_r_reg_n_0_[16] ));
  LUT6 #(
    .INIT(64'h5501550155005501)) 
    \gen_track_left_edge[5].pb_found_edge_r[5]_i_1 
       (.I0(\FSM_onehot_cal1_state_r[34]_i_4_n_0 ),
        .I1(pb_detect_edge_done_r[5]),
        .I2(\gen_track_left_edge[5].pb_found_edge_r[5]_i_2_n_0 ),
        .I3(\gen_track_left_edge[5].pb_found_edge_r_reg_n_0_[5] ),
        .I4(samp_cnt_done_r_reg_n_0),
        .I5(p_0_in4_in),
        .O(\gen_track_left_edge[5].pb_found_edge_r[5]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h0001)) 
    \gen_track_left_edge[5].pb_found_edge_r[5]_i_2 
       (.I0(samp_cnt_done_r_reg_n_0),
        .I1(p_0_in91_in),
        .I2(p_1_in5_in),
        .I3(p_0_in4_in),
        .O(\gen_track_left_edge[5].pb_found_edge_r[5]_i_2_n_0 ));
  FDRE \gen_track_left_edge[5].pb_found_edge_r_reg[5] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_track_left_edge[5].pb_found_edge_r[5]_i_1_n_0 ),
        .Q(\gen_track_left_edge[5].pb_found_edge_r_reg_n_0_[5] ),
        .R(\FSM_onehot_cal1_state_r_reg_n_0_[16] ));
  LUT6 #(
    .INIT(64'h55555F5500000800)) 
    \gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_1 
       (.I0(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_4_n_0 ),
        .I1(\gen_track_left_edge[5].pb_cnt_eye_size_r[5][4]_i_5_n_0 ),
        .I2(\gen_track_left_edge[5].pb_found_edge_r_reg_n_0_[5] ),
        .I3(samp_cnt_done_r_reg_n_0),
        .I4(p_0_in4_in),
        .I5(pb_found_stable_eye_r[5]),
        .O(\gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_1_n_0 ));
  FDRE \gen_track_left_edge[5].pb_found_stable_eye_r_reg[5] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_track_left_edge[5].pb_found_stable_eye_r[5]_i_1_n_0 ),
        .Q(pb_found_stable_eye_r[5]),
        .R(\FSM_onehot_cal1_state_r_reg_n_0_[16] ));
  LUT6 #(
    .INIT(64'h00000000FDFD0100)) 
    \gen_track_left_edge[5].pb_last_tap_jitter_r[5]_i_1 
       (.I0(samp_cnt_done_r_reg_n_0),
        .I1(pb_detect_edge_done_r[5]),
        .I2(\FSM_onehot_cal1_state_r[34]_i_4_n_0 ),
        .I3(p_0_in91_in),
        .I4(p_0_in4_in),
        .I5(\FSM_onehot_cal1_state_r_reg_n_0_[16] ),
        .O(\gen_track_left_edge[5].pb_last_tap_jitter_r[5]_i_1_n_0 ));
  FDRE \gen_track_left_edge[5].pb_last_tap_jitter_r_reg[5] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_track_left_edge[5].pb_last_tap_jitter_r[5]_i_1_n_0 ),
        .Q(p_0_in4_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair229" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \gen_track_left_edge[6].pb_cnt_eye_size_r[6][0]_i_1 
       (.I0(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_245 [0]),
        .O(p_0_in__9[0]));
  (* SOFT_HLUTNM = "soft_lutpair229" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \gen_track_left_edge[6].pb_cnt_eye_size_r[6][1]_i_1 
       (.I0(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_245 [1]),
        .I1(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_245 [0]),
        .O(p_0_in__9[1]));
  (* SOFT_HLUTNM = "soft_lutpair136" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \gen_track_left_edge[6].pb_cnt_eye_size_r[6][2]_i_1 
       (.I0(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_245 [2]),
        .I1(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_245 [0]),
        .I2(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_245 [1]),
        .O(p_0_in__9[2]));
  (* SOFT_HLUTNM = "soft_lutpair136" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \gen_track_left_edge[6].pb_cnt_eye_size_r[6][3]_i_1 
       (.I0(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_245 [3]),
        .I1(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_245 [1]),
        .I2(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_245 [0]),
        .I3(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_245 [2]),
        .O(p_0_in__9[3]));
  LUT5 #(
    .INIT(32'hFFEFAAAA)) 
    \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[16] ),
        .I1(\gen_track_left_edge[6].pb_found_edge_r_reg_n_0_[6] ),
        .I2(samp_cnt_done_r_reg_n_0),
        .I3(p_0_in1_in),
        .I4(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_4_n_0 ),
        .O(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h11100000)) 
    \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2 
       (.I0(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_5_n_0 ),
        .I1(pb_detect_edge_done_r[6]),
        .I2(store_sr_req_pulsed_r),
        .I3(p_34_in),
        .I4(samp_cnt_done_r_reg_n_0),
        .O(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair96" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_3 
       (.I0(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_245 [4]),
        .I1(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_245 [2]),
        .I2(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_245 [0]),
        .I3(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_245 [1]),
        .I4(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_245 [3]),
        .O(p_0_in__9[4]));
  LUT6 #(
    .INIT(64'h1111111111111110)) 
    \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_4 
       (.I0(\FSM_onehot_cal1_state_r[34]_i_4_n_0 ),
        .I1(pb_detect_edge_done_r[6]),
        .I2(p_0_in1_in),
        .I3(p_1_in2_in),
        .I4(p_0_in88_in),
        .I5(samp_cnt_done_r_reg_n_0),
        .O(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair96" *) 
  LUT5 #(
    .INIT(32'h00008000)) 
    \gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_5 
       (.I0(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_245 [2]),
        .I1(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_245 [0]),
        .I2(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_245 [1]),
        .I3(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_245 [3]),
        .I4(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_245 [4]),
        .O(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_5_n_0 ));
  FDRE \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0 ),
        .D(p_0_in__9[0]),
        .Q(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_245 [0]),
        .R(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6][1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0 ),
        .D(p_0_in__9[1]),
        .Q(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_245 [1]),
        .R(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6][2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0 ),
        .D(p_0_in__9[2]),
        .Q(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_245 [2]),
        .R(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6][3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0 ),
        .D(p_0_in__9[3]),
        .Q(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_245 [3]),
        .R(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6][4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_2_n_0 ),
        .D(p_0_in__9[4]),
        .Q(\gen_track_left_edge[6].pb_cnt_eye_size_r_reg[6]_245 [4]),
        .R(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hEEEEEEE0)) 
    \gen_track_left_edge[6].pb_detect_edge_done_r[6]_i_1 
       (.I0(store_sr_req_pulsed_r),
        .I1(p_34_in),
        .I2(p_0_in88_in),
        .I3(samp_cnt_done_r_reg_n_0),
        .I4(pb_detect_edge_done_r[6]),
        .O(\gen_track_left_edge[6].pb_detect_edge_done_r[6]_i_1_n_0 ));
  FDRE \gen_track_left_edge[6].pb_detect_edge_done_r_reg[6] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_track_left_edge[6].pb_detect_edge_done_r[6]_i_1_n_0 ),
        .Q(pb_detect_edge_done_r[6]),
        .R(\FSM_onehot_cal1_state_r_reg_n_0_[16] ));
  LUT6 #(
    .INIT(64'h5501550155005501)) 
    \gen_track_left_edge[6].pb_found_edge_r[6]_i_1 
       (.I0(\FSM_onehot_cal1_state_r[34]_i_4_n_0 ),
        .I1(pb_detect_edge_done_r[6]),
        .I2(\gen_track_left_edge[6].pb_found_edge_r[6]_i_2_n_0 ),
        .I3(\gen_track_left_edge[6].pb_found_edge_r_reg_n_0_[6] ),
        .I4(samp_cnt_done_r_reg_n_0),
        .I5(p_0_in1_in),
        .O(\gen_track_left_edge[6].pb_found_edge_r[6]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h0001)) 
    \gen_track_left_edge[6].pb_found_edge_r[6]_i_2 
       (.I0(samp_cnt_done_r_reg_n_0),
        .I1(p_0_in88_in),
        .I2(p_1_in2_in),
        .I3(p_0_in1_in),
        .O(\gen_track_left_edge[6].pb_found_edge_r[6]_i_2_n_0 ));
  FDRE \gen_track_left_edge[6].pb_found_edge_r_reg[6] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_track_left_edge[6].pb_found_edge_r[6]_i_1_n_0 ),
        .Q(\gen_track_left_edge[6].pb_found_edge_r_reg_n_0_[6] ),
        .R(\FSM_onehot_cal1_state_r_reg_n_0_[16] ));
  LUT6 #(
    .INIT(64'h55555F5500000800)) 
    \gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_1 
       (.I0(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_4_n_0 ),
        .I1(\gen_track_left_edge[6].pb_cnt_eye_size_r[6][4]_i_5_n_0 ),
        .I2(\gen_track_left_edge[6].pb_found_edge_r_reg_n_0_[6] ),
        .I3(samp_cnt_done_r_reg_n_0),
        .I4(p_0_in1_in),
        .I5(pb_found_stable_eye_r[6]),
        .O(\gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_1_n_0 ));
  FDRE \gen_track_left_edge[6].pb_found_stable_eye_r_reg[6] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_track_left_edge[6].pb_found_stable_eye_r[6]_i_1_n_0 ),
        .Q(pb_found_stable_eye_r[6]),
        .R(\FSM_onehot_cal1_state_r_reg_n_0_[16] ));
  LUT6 #(
    .INIT(64'h00000000FDFD0100)) 
    \gen_track_left_edge[6].pb_last_tap_jitter_r[6]_i_1 
       (.I0(samp_cnt_done_r_reg_n_0),
        .I1(pb_detect_edge_done_r[6]),
        .I2(\FSM_onehot_cal1_state_r[34]_i_4_n_0 ),
        .I3(p_0_in88_in),
        .I4(p_0_in1_in),
        .I5(\FSM_onehot_cal1_state_r_reg_n_0_[16] ),
        .O(\gen_track_left_edge[6].pb_last_tap_jitter_r[6]_i_1_n_0 ));
  FDRE \gen_track_left_edge[6].pb_last_tap_jitter_r_reg[6] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_track_left_edge[6].pb_last_tap_jitter_r[6]_i_1_n_0 ),
        .Q(p_0_in1_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair230" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \gen_track_left_edge[7].pb_cnt_eye_size_r[7][0]_i_1 
       (.I0(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_246 [0]),
        .O(p_0_in__10[0]));
  (* SOFT_HLUTNM = "soft_lutpair230" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \gen_track_left_edge[7].pb_cnt_eye_size_r[7][1]_i_1 
       (.I0(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_246 [1]),
        .I1(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_246 [0]),
        .O(p_0_in__10[1]));
  (* SOFT_HLUTNM = "soft_lutpair134" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \gen_track_left_edge[7].pb_cnt_eye_size_r[7][2]_i_1 
       (.I0(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_246 [2]),
        .I1(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_246 [0]),
        .I2(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_246 [1]),
        .O(p_0_in__10[2]));
  (* SOFT_HLUTNM = "soft_lutpair134" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \gen_track_left_edge[7].pb_cnt_eye_size_r[7][3]_i_1 
       (.I0(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_246 [3]),
        .I1(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_246 [1]),
        .I2(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_246 [0]),
        .I3(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_246 [2]),
        .O(p_0_in__10[3]));
  LUT5 #(
    .INIT(32'hFFEFAAAA)) 
    \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[16] ),
        .I1(\gen_track_left_edge[7].pb_found_edge_r_reg_n_0_[7] ),
        .I2(samp_cnt_done_r_reg_n_0),
        .I3(p_0_in),
        .I4(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_4_n_0 ),
        .O(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h11100000)) 
    \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2 
       (.I0(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_5_n_0 ),
        .I1(pb_detect_edge_done_r[7]),
        .I2(store_sr_req_pulsed_r),
        .I3(p_34_in),
        .I4(samp_cnt_done_r_reg_n_0),
        .O(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair101" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_3 
       (.I0(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_246 [4]),
        .I1(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_246 [2]),
        .I2(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_246 [0]),
        .I3(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_246 [1]),
        .I4(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_246 [3]),
        .O(p_0_in__10[4]));
  LUT6 #(
    .INIT(64'h1111111111111110)) 
    \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_4 
       (.I0(\FSM_onehot_cal1_state_r[34]_i_4_n_0 ),
        .I1(pb_detect_edge_done_r[7]),
        .I2(p_0_in),
        .I3(\gen_sr_match_div4.gen_sr_match[7].old_sr_diff_r_reg_n_0_[7] ),
        .I4(\gen_sr_match_div4.gen_sr_match[7].prev_sr_diff_r_reg_n_0_[7] ),
        .I5(samp_cnt_done_r_reg_n_0),
        .O(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair101" *) 
  LUT5 #(
    .INIT(32'h00008000)) 
    \gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_5 
       (.I0(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_246 [2]),
        .I1(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_246 [0]),
        .I2(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_246 [1]),
        .I3(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_246 [3]),
        .I4(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_246 [4]),
        .O(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_5_n_0 ));
  FDRE \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0 ),
        .D(p_0_in__10[0]),
        .Q(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_246 [0]),
        .R(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7][1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0 ),
        .D(p_0_in__10[1]),
        .Q(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_246 [1]),
        .R(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7][2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0 ),
        .D(p_0_in__10[2]),
        .Q(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_246 [2]),
        .R(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7][3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0 ),
        .D(p_0_in__10[3]),
        .Q(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_246 [3]),
        .R(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0 ));
  FDRE \gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7][4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_2_n_0 ),
        .D(p_0_in__10[4]),
        .Q(\gen_track_left_edge[7].pb_cnt_eye_size_r_reg[7]_246 [4]),
        .R(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hEEEEEEE0)) 
    \gen_track_left_edge[7].pb_detect_edge_done_r[7]_i_1 
       (.I0(store_sr_req_pulsed_r),
        .I1(p_34_in),
        .I2(\gen_sr_match_div4.gen_sr_match[7].prev_sr_diff_r_reg_n_0_[7] ),
        .I3(samp_cnt_done_r_reg_n_0),
        .I4(pb_detect_edge_done_r[7]),
        .O(\gen_track_left_edge[7].pb_detect_edge_done_r[7]_i_1_n_0 ));
  FDRE \gen_track_left_edge[7].pb_detect_edge_done_r_reg[7] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_track_left_edge[7].pb_detect_edge_done_r[7]_i_1_n_0 ),
        .Q(pb_detect_edge_done_r[7]),
        .R(\FSM_onehot_cal1_state_r_reg_n_0_[16] ));
  LUT6 #(
    .INIT(64'h5501550155005501)) 
    \gen_track_left_edge[7].pb_found_edge_r[7]_i_1 
       (.I0(\FSM_onehot_cal1_state_r[34]_i_4_n_0 ),
        .I1(pb_detect_edge_done_r[7]),
        .I2(\gen_track_left_edge[7].pb_found_edge_r[7]_i_2_n_0 ),
        .I3(\gen_track_left_edge[7].pb_found_edge_r_reg_n_0_[7] ),
        .I4(samp_cnt_done_r_reg_n_0),
        .I5(p_0_in),
        .O(\gen_track_left_edge[7].pb_found_edge_r[7]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h0001)) 
    \gen_track_left_edge[7].pb_found_edge_r[7]_i_2 
       (.I0(samp_cnt_done_r_reg_n_0),
        .I1(\gen_sr_match_div4.gen_sr_match[7].prev_sr_diff_r_reg_n_0_[7] ),
        .I2(\gen_sr_match_div4.gen_sr_match[7].old_sr_diff_r_reg_n_0_[7] ),
        .I3(p_0_in),
        .O(\gen_track_left_edge[7].pb_found_edge_r[7]_i_2_n_0 ));
  FDRE \gen_track_left_edge[7].pb_found_edge_r_reg[7] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_track_left_edge[7].pb_found_edge_r[7]_i_1_n_0 ),
        .Q(\gen_track_left_edge[7].pb_found_edge_r_reg_n_0_[7] ),
        .R(\FSM_onehot_cal1_state_r_reg_n_0_[16] ));
  LUT6 #(
    .INIT(64'h55555F5500000800)) 
    \gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_1 
       (.I0(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_4_n_0 ),
        .I1(\gen_track_left_edge[7].pb_cnt_eye_size_r[7][4]_i_5_n_0 ),
        .I2(\gen_track_left_edge[7].pb_found_edge_r_reg_n_0_[7] ),
        .I3(samp_cnt_done_r_reg_n_0),
        .I4(p_0_in),
        .I5(pb_found_stable_eye_r[7]),
        .O(\gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_1_n_0 ));
  FDRE \gen_track_left_edge[7].pb_found_stable_eye_r_reg[7] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_track_left_edge[7].pb_found_stable_eye_r[7]_i_1_n_0 ),
        .Q(pb_found_stable_eye_r[7]),
        .R(\FSM_onehot_cal1_state_r_reg_n_0_[16] ));
  LUT6 #(
    .INIT(64'h00000000FDFD0100)) 
    \gen_track_left_edge[7].pb_last_tap_jitter_r[7]_i_1 
       (.I0(samp_cnt_done_r_reg_n_0),
        .I1(pb_detect_edge_done_r[7]),
        .I2(\FSM_onehot_cal1_state_r[34]_i_4_n_0 ),
        .I3(\gen_sr_match_div4.gen_sr_match[7].prev_sr_diff_r_reg_n_0_[7] ),
        .I4(p_0_in),
        .I5(\FSM_onehot_cal1_state_r_reg_n_0_[16] ),
        .O(\gen_track_left_edge[7].pb_last_tap_jitter_r[7]_i_1_n_0 ));
  FDRE \gen_track_left_edge[7].pb_last_tap_jitter_r_reg[7] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\gen_track_left_edge[7].pb_last_tap_jitter_r[7]_i_1_n_0 ),
        .Q(p_0_in),
        .R(1'b0));
  LUT4 #(
    .INIT(16'hC580)) 
    idel_adj_inc_i_1
       (.I0(\idel_dec_cnt[4]_i_3_n_0 ),
        .I1(cal1_wait_r),
        .I2(\FSM_onehot_cal1_state_r_reg_n_0_[3] ),
        .I3(idel_adj_inc_reg_n_0),
        .O(idel_adj_inc_i_1_n_0));
  FDRE idel_adj_inc_reg
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(idel_adj_inc_i_1_n_0),
        .Q(idel_adj_inc_reg_n_0),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 [1]));
  (* SOFT_HLUTNM = "soft_lutpair109" *) 
  LUT4 #(
    .INIT(16'h8F88)) 
    \idel_dec_cnt[0]_i_1 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[1] ),
        .I1(idelay_tap_cnt_r[0]),
        .I2(\idel_dec_cnt_reg_n_0_[0] ),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[15] ),
        .O(idel_dec_cnt[0]));
  LUT5 #(
    .INIT(32'hF88F8888)) 
    \idel_dec_cnt[1]_i_1 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[1] ),
        .I1(idelay_tap_cnt_r[1]),
        .I2(\idel_dec_cnt_reg_n_0_[1] ),
        .I3(\idel_dec_cnt_reg_n_0_[0] ),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[15] ),
        .O(idel_dec_cnt[1]));
  LUT6 #(
    .INIT(64'hF8F8F88F88888888)) 
    \idel_dec_cnt[2]_i_1 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[1] ),
        .I1(idelay_tap_cnt_r[2]),
        .I2(\idel_dec_cnt_reg_n_0_[2] ),
        .I3(\idel_dec_cnt_reg_n_0_[0] ),
        .I4(\idel_dec_cnt_reg_n_0_[1] ),
        .I5(\FSM_onehot_cal1_state_r_reg_n_0_[15] ),
        .O(idel_dec_cnt[2]));
  LUT5 #(
    .INIT(32'h8FF88888)) 
    \idel_dec_cnt[3]_i_1 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[1] ),
        .I1(idelay_tap_cnt_r[3]),
        .I2(\idel_dec_cnt_reg_n_0_[3] ),
        .I3(\idel_dec_cnt[3]_i_2_n_0 ),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[15] ),
        .O(idel_dec_cnt[3]));
  LUT3 #(
    .INIT(8'h01)) 
    \idel_dec_cnt[3]_i_2 
       (.I0(\idel_dec_cnt_reg_n_0_[0] ),
        .I1(\idel_dec_cnt_reg_n_0_[1] ),
        .I2(\idel_dec_cnt_reg_n_0_[2] ),
        .O(\idel_dec_cnt[3]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFF8F8FFF8)) 
    \idel_dec_cnt[4]_i_1 
       (.I0(\FSM_onehot_cal1_state_r[22]_i_2_n_0 ),
        .I1(idel_mpr_pat_detect_r),
        .I2(\idel_dec_cnt[4]_i_3_n_0 ),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[15] ),
        .I4(\idel_dec_cnt[4]_i_4_n_0 ),
        .I5(\FSM_onehot_cal1_state_r[15]_i_2_n_0 ),
        .O(\idel_dec_cnt[4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h8FF88888)) 
    \idel_dec_cnt[4]_i_2 
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[1] ),
        .I1(idelay_tap_cnt_r[4]),
        .I2(\idel_dec_cnt_reg_n_0_[4] ),
        .I3(\idel_dec_cnt[4]_i_5_n_0 ),
        .I4(\FSM_onehot_cal1_state_r_reg_n_0_[15] ),
        .O(idel_dec_cnt[4]));
  (* SOFT_HLUTNM = "soft_lutpair124" *) 
  LUT4 #(
    .INIT(16'hA800)) 
    \idel_dec_cnt[4]_i_3 
       (.I0(detect_edge_done_r),
        .I1(\gen_pat_match_div4.idel_pat1_data_match_r_reg_n_0 ),
        .I2(\gen_pat_match_div4.idel_pat0_data_match_r_reg_n_0 ),
        .I3(p_34_in),
        .O(\idel_dec_cnt[4]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair84" *) 
  LUT5 #(
    .INIT(32'h00000001)) 
    \idel_dec_cnt[4]_i_4 
       (.I0(\idel_dec_cnt_reg_n_0_[3] ),
        .I1(\idel_dec_cnt_reg_n_0_[0] ),
        .I2(\idel_dec_cnt_reg_n_0_[1] ),
        .I3(\idel_dec_cnt_reg_n_0_[2] ),
        .I4(\idel_dec_cnt_reg_n_0_[4] ),
        .O(\idel_dec_cnt[4]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair84" *) 
  LUT4 #(
    .INIT(16'h0001)) 
    \idel_dec_cnt[4]_i_5 
       (.I0(\idel_dec_cnt_reg_n_0_[2] ),
        .I1(\idel_dec_cnt_reg_n_0_[1] ),
        .I2(\idel_dec_cnt_reg_n_0_[0] ),
        .I3(\idel_dec_cnt_reg_n_0_[3] ),
        .O(\idel_dec_cnt[4]_i_5_n_0 ));
  FDRE \idel_dec_cnt_reg[0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\idel_dec_cnt[4]_i_1_n_0 ),
        .D(idel_dec_cnt[0]),
        .Q(\idel_dec_cnt_reg_n_0_[0] ),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 [1]));
  FDRE \idel_dec_cnt_reg[1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\idel_dec_cnt[4]_i_1_n_0 ),
        .D(idel_dec_cnt[1]),
        .Q(\idel_dec_cnt_reg_n_0_[1] ),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 [1]));
  FDRE \idel_dec_cnt_reg[2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\idel_dec_cnt[4]_i_1_n_0 ),
        .D(idel_dec_cnt[2]),
        .Q(\idel_dec_cnt_reg_n_0_[2] ),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 [1]));
  FDRE \idel_dec_cnt_reg[3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\idel_dec_cnt[4]_i_1_n_0 ),
        .D(idel_dec_cnt[3]),
        .Q(\idel_dec_cnt_reg_n_0_[3] ),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 [1]));
  FDRE \idel_dec_cnt_reg[4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\idel_dec_cnt[4]_i_1_n_0 ),
        .D(idel_dec_cnt[4]),
        .Q(\idel_dec_cnt_reg_n_0_[4] ),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 [1]));
  (* SOFT_HLUTNM = "soft_lutpair110" *) 
  LUT4 #(
    .INIT(16'hCCCE)) 
    idel_pat_detect_valid_r_i_1
       (.I0(idel_pat_detect_valid_r_reg_n_0),
        .I1(p_0_in549_in),
        .I2(cal1_dq_idel_inc),
        .I3(store_sr_req_pulsed_r),
        .O(idel_pat_detect_valid_r_i_1_n_0));
  FDRE idel_pat_detect_valid_r_reg
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(idel_pat_detect_valid_r_i_1_n_0),
        .Q(idel_pat_detect_valid_r_reg_n_0),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 [1]));
  (* SOFT_HLUTNM = "soft_lutpair85" *) 
  LUT3 #(
    .INIT(8'h04)) 
    \idelay_tap_cnt_r[0][0][0]_i_1 
       (.I0(pi_stg2_f_incdec_timing_reg_0),
        .I1(idelay_ce_int),
        .I2(idelay_tap_cnt_slice_r[0]),
        .O(\idelay_tap_cnt_r[0][0][0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair85" *) 
  LUT5 #(
    .INIT(32'h04404004)) 
    \idelay_tap_cnt_r[0][0][1]_i_1 
       (.I0(pi_stg2_f_incdec_timing_reg_0),
        .I1(idelay_ce_int),
        .I2(idelay_tap_cnt_slice_r[0]),
        .I3(idelay_tap_cnt_slice_r[1]),
        .I4(idelay_inc_int),
        .O(\idelay_tap_cnt_r[0][0][1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0444400044400004)) 
    \idelay_tap_cnt_r[0][0][2]_i_1 
       (.I0(pi_stg2_f_incdec_timing_reg_0),
        .I1(idelay_ce_int),
        .I2(idelay_inc_int),
        .I3(idelay_tap_cnt_slice_r[0]),
        .I4(idelay_tap_cnt_slice_r[2]),
        .I5(idelay_tap_cnt_slice_r[1]),
        .O(\idelay_tap_cnt_r[0][0][2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h28A0A0A0A0A0A082)) 
    \idelay_tap_cnt_r[0][0][3]_i_1 
       (.I0(\idelay_tap_cnt_r[0][0][3]_i_2_n_0 ),
        .I1(idelay_tap_cnt_slice_r[2]),
        .I2(idelay_tap_cnt_slice_r[3]),
        .I3(idelay_tap_cnt_slice_r[0]),
        .I4(idelay_inc_int),
        .I5(idelay_tap_cnt_slice_r[1]),
        .O(\idelay_tap_cnt_r[0][0][3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair114" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \idelay_tap_cnt_r[0][0][3]_i_2 
       (.I0(idelay_ce_int),
        .I1(pi_stg2_f_incdec_timing_reg_0),
        .O(\idelay_tap_cnt_r[0][0][3]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair212" *) 
  LUT3 #(
    .INIT(8'h04)) 
    \idelay_tap_cnt_r[0][0][4]_i_2 
       (.I0(pi_stg2_f_incdec_timing_reg_0),
        .I1(idelay_ce_int),
        .I2(\idelay_tap_cnt_r[0][0][4]_i_6_n_0 ),
        .O(\idelay_tap_cnt_r[0][0][4]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair214" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \idelay_tap_cnt_r[0][0][4]_i_3 
       (.I0(\cal1_cnt_cpt_r_reg_n_0_[0] ),
        .I1(\cal1_cnt_cpt_r_reg_n_0_[1] ),
        .O(\cal1_cnt_cpt_r_reg[0]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair127" *) 
  LUT4 #(
    .INIT(16'h0100)) 
    \idelay_tap_cnt_r[0][0][4]_i_4 
       (.I0(\cal1_cnt_cpt_r_reg_n_0_[2] ),
        .I1(\rnk_cnt_r_reg_n_0_[1] ),
        .I2(\rnk_cnt_r_reg_n_0_[0] ),
        .I3(idelay_ce_int),
        .O(\cal1_cnt_cpt_r_reg[2]_0 ));
  LUT6 #(
    .INIT(64'h9555555555555556)) 
    \idelay_tap_cnt_r[0][0][4]_i_6 
       (.I0(idelay_tap_cnt_slice_r[4]),
        .I1(idelay_tap_cnt_slice_r[0]),
        .I2(idelay_inc_int),
        .I3(idelay_tap_cnt_slice_r[1]),
        .I4(idelay_tap_cnt_slice_r[3]),
        .I5(idelay_tap_cnt_slice_r[2]),
        .O(\idelay_tap_cnt_r[0][0][4]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair218" *) 
  LUT3 #(
    .INIT(8'h01)) 
    \idelay_tap_cnt_r[0][1][4]_i_2 
       (.I0(\rnk_cnt_r_reg_n_0_[0] ),
        .I1(\rnk_cnt_r_reg_n_0_[1] ),
        .I2(\cal1_cnt_cpt_r_reg_n_0_[2] ),
        .O(\rnk_cnt_r_reg[0]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair217" *) 
  LUT3 #(
    .INIT(8'h08)) 
    \idelay_tap_cnt_r[0][1][4]_i_3 
       (.I0(idelay_ce_int),
        .I1(\cal1_cnt_cpt_r_reg_n_0_[0] ),
        .I2(\cal1_cnt_cpt_r_reg_n_0_[1] ),
        .O(cal1_dq_idel_ce_reg_1));
  LUT6 #(
    .INIT(64'h0000000200000000)) 
    \idelay_tap_cnt_r[0][2][4]_i_2 
       (.I0(idelay_ce_int),
        .I1(\rnk_cnt_r_reg_n_0_[0] ),
        .I2(\rnk_cnt_r_reg_n_0_[1] ),
        .I3(\cal1_cnt_cpt_r_reg_n_0_[2] ),
        .I4(\cal1_cnt_cpt_r_reg_n_0_[0] ),
        .I5(\cal1_cnt_cpt_r_reg_n_0_[1] ),
        .O(cal1_dq_idel_ce_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair217" *) 
  LUT3 #(
    .INIT(8'h7F)) 
    \idelay_tap_cnt_r[0][3][4]_i_2 
       (.I0(idelay_ce_int),
        .I1(\cal1_cnt_cpt_r_reg_n_0_[1] ),
        .I2(\cal1_cnt_cpt_r_reg_n_0_[0] ),
        .O(cal1_dq_idel_ce_reg_2));
  (* SOFT_HLUTNM = "soft_lutpair127" *) 
  LUT4 #(
    .INIT(16'hEFFF)) 
    \idelay_tap_cnt_r[0][4][4]_i_2 
       (.I0(\rnk_cnt_r_reg_n_0_[1] ),
        .I1(\rnk_cnt_r_reg_n_0_[0] ),
        .I2(\cal1_cnt_cpt_r_reg_n_0_[2] ),
        .I3(idelay_ce_int),
        .O(\rnk_cnt_r_reg[1]_0 ));
  LUT6 #(
    .INIT(64'h0000000000004000)) 
    \idelay_tap_cnt_r[0][6][4]_i_2 
       (.I0(\cal1_cnt_cpt_r_reg_n_0_[0] ),
        .I1(\cal1_cnt_cpt_r_reg_n_0_[1] ),
        .I2(idelay_ce_int),
        .I3(\cal1_cnt_cpt_r_reg_n_0_[2] ),
        .I4(\rnk_cnt_r_reg_n_0_[0] ),
        .I5(\rnk_cnt_r_reg_n_0_[1] ),
        .O(\cal1_cnt_cpt_r_reg[0]_1 ));
  FDRE \idelay_tap_cnt_r_reg[0][0][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\idelay_tap_cnt_r_reg[0][0][4]_0 ),
        .D(\idelay_tap_cnt_r[0][0][0]_i_1_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][0][0] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][0][1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\idelay_tap_cnt_r_reg[0][0][4]_0 ),
        .D(\idelay_tap_cnt_r[0][0][1]_i_1_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][0][1] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][0][2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\idelay_tap_cnt_r_reg[0][0][4]_0 ),
        .D(\idelay_tap_cnt_r[0][0][2]_i_1_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][0][2] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][0][3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\idelay_tap_cnt_r_reg[0][0][4]_0 ),
        .D(\idelay_tap_cnt_r[0][0][3]_i_1_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][0][3] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][0][4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\idelay_tap_cnt_r_reg[0][0][4]_0 ),
        .D(\idelay_tap_cnt_r[0][0][4]_i_2_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][0][4] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][1][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\idelay_tap_cnt_r_reg[0][1][4]_0 ),
        .D(\idelay_tap_cnt_r[0][0][0]_i_1_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][1][0] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][1][1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\idelay_tap_cnt_r_reg[0][1][4]_0 ),
        .D(\idelay_tap_cnt_r[0][0][1]_i_1_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][1][1] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][1][2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\idelay_tap_cnt_r_reg[0][1][4]_0 ),
        .D(\idelay_tap_cnt_r[0][0][2]_i_1_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][1][2] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][1][3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\idelay_tap_cnt_r_reg[0][1][4]_0 ),
        .D(\idelay_tap_cnt_r[0][0][3]_i_1_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][1][3] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][1][4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\idelay_tap_cnt_r_reg[0][1][4]_0 ),
        .D(\idelay_tap_cnt_r[0][0][4]_i_2_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][1][4] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][2][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\idelay_tap_cnt_r_reg[0][2][4]_0 ),
        .D(\idelay_tap_cnt_r[0][0][0]_i_1_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][2][0] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][2][1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\idelay_tap_cnt_r_reg[0][2][4]_0 ),
        .D(\idelay_tap_cnt_r[0][0][1]_i_1_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][2][1] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][2][2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\idelay_tap_cnt_r_reg[0][2][4]_0 ),
        .D(\idelay_tap_cnt_r[0][0][2]_i_1_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][2][2] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][2][3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\idelay_tap_cnt_r_reg[0][2][4]_0 ),
        .D(\idelay_tap_cnt_r[0][0][3]_i_1_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][2][3] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][2][4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\idelay_tap_cnt_r_reg[0][2][4]_0 ),
        .D(\idelay_tap_cnt_r[0][0][4]_i_2_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][2][4] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][3][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\idelay_tap_cnt_r_reg[0][3][4]_0 ),
        .D(\idelay_tap_cnt_r[0][0][0]_i_1_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][3][0] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][3][1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\idelay_tap_cnt_r_reg[0][3][4]_0 ),
        .D(\idelay_tap_cnt_r[0][0][1]_i_1_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][3][1] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][3][2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\idelay_tap_cnt_r_reg[0][3][4]_0 ),
        .D(\idelay_tap_cnt_r[0][0][2]_i_1_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][3][2] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][3][3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\idelay_tap_cnt_r_reg[0][3][4]_0 ),
        .D(\idelay_tap_cnt_r[0][0][3]_i_1_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][3][3] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][3][4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\idelay_tap_cnt_r_reg[0][3][4]_0 ),
        .D(\idelay_tap_cnt_r[0][0][4]_i_2_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][3][4] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][4][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\idelay_tap_cnt_r_reg[0][4][4]_0 ),
        .D(\idelay_tap_cnt_r[0][0][0]_i_1_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][4][0] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][4][1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\idelay_tap_cnt_r_reg[0][4][4]_0 ),
        .D(\idelay_tap_cnt_r[0][0][1]_i_1_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][4][1] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][4][2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\idelay_tap_cnt_r_reg[0][4][4]_0 ),
        .D(\idelay_tap_cnt_r[0][0][2]_i_1_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][4][2] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][4][3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\idelay_tap_cnt_r_reg[0][4][4]_0 ),
        .D(\idelay_tap_cnt_r[0][0][3]_i_1_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][4][3] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][4][4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\idelay_tap_cnt_r_reg[0][4][4]_0 ),
        .D(\idelay_tap_cnt_r[0][0][4]_i_2_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][4][4] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][5][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\idelay_tap_cnt_r_reg[0][5][4]_0 ),
        .D(\idelay_tap_cnt_r[0][0][0]_i_1_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][5][0] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][5][1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\idelay_tap_cnt_r_reg[0][5][4]_0 ),
        .D(\idelay_tap_cnt_r[0][0][1]_i_1_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][5][1] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][5][2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\idelay_tap_cnt_r_reg[0][5][4]_0 ),
        .D(\idelay_tap_cnt_r[0][0][2]_i_1_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][5][2] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][5][3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\idelay_tap_cnt_r_reg[0][5][4]_0 ),
        .D(\idelay_tap_cnt_r[0][0][3]_i_1_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][5][3] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][5][4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\idelay_tap_cnt_r_reg[0][5][4]_0 ),
        .D(\idelay_tap_cnt_r[0][0][4]_i_2_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][5][4] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][6][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\idelay_tap_cnt_r_reg[0][6][4]_0 ),
        .D(\idelay_tap_cnt_r[0][0][0]_i_1_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][6][0] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][6][1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\idelay_tap_cnt_r_reg[0][6][4]_0 ),
        .D(\idelay_tap_cnt_r[0][0][1]_i_1_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][6][1] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][6][2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\idelay_tap_cnt_r_reg[0][6][4]_0 ),
        .D(\idelay_tap_cnt_r[0][0][2]_i_1_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][6][2] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][6][3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\idelay_tap_cnt_r_reg[0][6][4]_0 ),
        .D(\idelay_tap_cnt_r[0][0][3]_i_1_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][6][3] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][6][4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\idelay_tap_cnt_r_reg[0][6][4]_0 ),
        .D(\idelay_tap_cnt_r[0][0][4]_i_2_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][6][4] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][7][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\idelay_tap_cnt_r_reg[0][7][4]_0 ),
        .D(\idelay_tap_cnt_r[0][0][0]_i_1_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][7][0] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][7][1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\idelay_tap_cnt_r_reg[0][7][4]_0 ),
        .D(\idelay_tap_cnt_r[0][0][1]_i_1_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][7][1] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][7][2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\idelay_tap_cnt_r_reg[0][7][4]_0 ),
        .D(\idelay_tap_cnt_r[0][0][2]_i_1_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][7][2] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][7][3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\idelay_tap_cnt_r_reg[0][7][4]_0 ),
        .D(\idelay_tap_cnt_r[0][0][3]_i_1_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][7][3] ),
        .R(1'b0));
  FDRE \idelay_tap_cnt_r_reg[0][7][4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\idelay_tap_cnt_r_reg[0][7][4]_0 ),
        .D(\idelay_tap_cnt_r[0][0][4]_i_2_n_0 ),
        .Q(\idelay_tap_cnt_r_reg_n_0_[0][7][4] ),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \idelay_tap_cnt_slice_r[0]_i_2 
       (.I0(\idelay_tap_cnt_r_reg_n_0_[0][3][0] ),
        .I1(\idelay_tap_cnt_r_reg_n_0_[0][2][0] ),
        .I2(\cal1_cnt_cpt_r_reg_n_0_[1] ),
        .I3(\idelay_tap_cnt_r_reg_n_0_[0][1][0] ),
        .I4(\cal1_cnt_cpt_r_reg_n_0_[0] ),
        .I5(\idelay_tap_cnt_r_reg_n_0_[0][0][0] ),
        .O(\idelay_tap_cnt_slice_r[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \idelay_tap_cnt_slice_r[0]_i_3 
       (.I0(\idelay_tap_cnt_r_reg_n_0_[0][7][0] ),
        .I1(\idelay_tap_cnt_r_reg_n_0_[0][6][0] ),
        .I2(\cal1_cnt_cpt_r_reg_n_0_[1] ),
        .I3(\idelay_tap_cnt_r_reg_n_0_[0][5][0] ),
        .I4(\cal1_cnt_cpt_r_reg_n_0_[0] ),
        .I5(\idelay_tap_cnt_r_reg_n_0_[0][4][0] ),
        .O(\idelay_tap_cnt_slice_r[0]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \idelay_tap_cnt_slice_r[1]_i_2 
       (.I0(\idelay_tap_cnt_r_reg_n_0_[0][3][1] ),
        .I1(\idelay_tap_cnt_r_reg_n_0_[0][2][1] ),
        .I2(\cal1_cnt_cpt_r_reg_n_0_[1] ),
        .I3(\idelay_tap_cnt_r_reg_n_0_[0][1][1] ),
        .I4(\cal1_cnt_cpt_r_reg_n_0_[0] ),
        .I5(\idelay_tap_cnt_r_reg_n_0_[0][0][1] ),
        .O(\idelay_tap_cnt_slice_r[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \idelay_tap_cnt_slice_r[1]_i_3 
       (.I0(\idelay_tap_cnt_r_reg_n_0_[0][7][1] ),
        .I1(\idelay_tap_cnt_r_reg_n_0_[0][6][1] ),
        .I2(\cal1_cnt_cpt_r_reg_n_0_[1] ),
        .I3(\idelay_tap_cnt_r_reg_n_0_[0][5][1] ),
        .I4(\cal1_cnt_cpt_r_reg_n_0_[0] ),
        .I5(\idelay_tap_cnt_r_reg_n_0_[0][4][1] ),
        .O(\idelay_tap_cnt_slice_r[1]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \idelay_tap_cnt_slice_r[2]_i_2 
       (.I0(\idelay_tap_cnt_r_reg_n_0_[0][3][2] ),
        .I1(\idelay_tap_cnt_r_reg_n_0_[0][2][2] ),
        .I2(\cal1_cnt_cpt_r_reg_n_0_[1] ),
        .I3(\idelay_tap_cnt_r_reg_n_0_[0][1][2] ),
        .I4(\cal1_cnt_cpt_r_reg_n_0_[0] ),
        .I5(\idelay_tap_cnt_r_reg_n_0_[0][0][2] ),
        .O(\idelay_tap_cnt_slice_r[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \idelay_tap_cnt_slice_r[2]_i_3 
       (.I0(\idelay_tap_cnt_r_reg_n_0_[0][7][2] ),
        .I1(\idelay_tap_cnt_r_reg_n_0_[0][6][2] ),
        .I2(\cal1_cnt_cpt_r_reg_n_0_[1] ),
        .I3(\idelay_tap_cnt_r_reg_n_0_[0][5][2] ),
        .I4(\cal1_cnt_cpt_r_reg_n_0_[0] ),
        .I5(\idelay_tap_cnt_r_reg_n_0_[0][4][2] ),
        .O(\idelay_tap_cnt_slice_r[2]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \idelay_tap_cnt_slice_r[3]_i_2 
       (.I0(\idelay_tap_cnt_r_reg_n_0_[0][3][3] ),
        .I1(\idelay_tap_cnt_r_reg_n_0_[0][2][3] ),
        .I2(\cal1_cnt_cpt_r_reg_n_0_[1] ),
        .I3(\idelay_tap_cnt_r_reg_n_0_[0][1][3] ),
        .I4(\cal1_cnt_cpt_r_reg_n_0_[0] ),
        .I5(\idelay_tap_cnt_r_reg_n_0_[0][0][3] ),
        .O(\idelay_tap_cnt_slice_r[3]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \idelay_tap_cnt_slice_r[3]_i_3 
       (.I0(\idelay_tap_cnt_r_reg_n_0_[0][7][3] ),
        .I1(\idelay_tap_cnt_r_reg_n_0_[0][6][3] ),
        .I2(\cal1_cnt_cpt_r_reg_n_0_[1] ),
        .I3(\idelay_tap_cnt_r_reg_n_0_[0][5][3] ),
        .I4(\cal1_cnt_cpt_r_reg_n_0_[0] ),
        .I5(\idelay_tap_cnt_r_reg_n_0_[0][4][3] ),
        .O(\idelay_tap_cnt_slice_r[3]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \idelay_tap_cnt_slice_r[4]_i_2 
       (.I0(\idelay_tap_cnt_r_reg_n_0_[0][3][4] ),
        .I1(\idelay_tap_cnt_r_reg_n_0_[0][2][4] ),
        .I2(\cal1_cnt_cpt_r_reg_n_0_[1] ),
        .I3(\idelay_tap_cnt_r_reg_n_0_[0][1][4] ),
        .I4(\cal1_cnt_cpt_r_reg_n_0_[0] ),
        .I5(\idelay_tap_cnt_r_reg_n_0_[0][0][4] ),
        .O(\idelay_tap_cnt_slice_r[4]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \idelay_tap_cnt_slice_r[4]_i_3 
       (.I0(\idelay_tap_cnt_r_reg_n_0_[0][7][4] ),
        .I1(\idelay_tap_cnt_r_reg_n_0_[0][6][4] ),
        .I2(\cal1_cnt_cpt_r_reg_n_0_[1] ),
        .I3(\idelay_tap_cnt_r_reg_n_0_[0][5][4] ),
        .I4(\cal1_cnt_cpt_r_reg_n_0_[0] ),
        .I5(\idelay_tap_cnt_r_reg_n_0_[0][4][4] ),
        .O(\idelay_tap_cnt_slice_r[4]_i_3_n_0 ));
  FDRE \idelay_tap_cnt_slice_r_reg[0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(idelay_tap_cnt_r[0]),
        .Q(idelay_tap_cnt_slice_r[0]),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 [1]));
  MUXF7 \idelay_tap_cnt_slice_r_reg[0]_i_1 
       (.I0(\idelay_tap_cnt_slice_r[0]_i_2_n_0 ),
        .I1(\idelay_tap_cnt_slice_r[0]_i_3_n_0 ),
        .O(idelay_tap_cnt_r[0]),
        .S(\cal1_cnt_cpt_r_reg_n_0_[2] ));
  FDRE \idelay_tap_cnt_slice_r_reg[1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(idelay_tap_cnt_r[1]),
        .Q(idelay_tap_cnt_slice_r[1]),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 [1]));
  MUXF7 \idelay_tap_cnt_slice_r_reg[1]_i_1 
       (.I0(\idelay_tap_cnt_slice_r[1]_i_2_n_0 ),
        .I1(\idelay_tap_cnt_slice_r[1]_i_3_n_0 ),
        .O(idelay_tap_cnt_r[1]),
        .S(\cal1_cnt_cpt_r_reg_n_0_[2] ));
  FDRE \idelay_tap_cnt_slice_r_reg[2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(idelay_tap_cnt_r[2]),
        .Q(idelay_tap_cnt_slice_r[2]),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 [1]));
  MUXF7 \idelay_tap_cnt_slice_r_reg[2]_i_1 
       (.I0(\idelay_tap_cnt_slice_r[2]_i_2_n_0 ),
        .I1(\idelay_tap_cnt_slice_r[2]_i_3_n_0 ),
        .O(idelay_tap_cnt_r[2]),
        .S(\cal1_cnt_cpt_r_reg_n_0_[2] ));
  FDRE \idelay_tap_cnt_slice_r_reg[3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(idelay_tap_cnt_r[3]),
        .Q(idelay_tap_cnt_slice_r[3]),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 [1]));
  MUXF7 \idelay_tap_cnt_slice_r_reg[3]_i_1 
       (.I0(\idelay_tap_cnt_slice_r[3]_i_2_n_0 ),
        .I1(\idelay_tap_cnt_slice_r[3]_i_3_n_0 ),
        .O(idelay_tap_cnt_r[3]),
        .S(\cal1_cnt_cpt_r_reg_n_0_[2] ));
  FDRE \idelay_tap_cnt_slice_r_reg[4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(idelay_tap_cnt_r[4]),
        .Q(idelay_tap_cnt_slice_r[4]),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 [1]));
  MUXF7 \idelay_tap_cnt_slice_r_reg[4]_i_1 
       (.I0(\idelay_tap_cnt_slice_r[4]_i_2_n_0 ),
        .I1(\idelay_tap_cnt_slice_r[4]_i_3_n_0 ),
        .O(idelay_tap_cnt_r[4]),
        .S(\cal1_cnt_cpt_r_reg_n_0_[2] ));
  (* SOFT_HLUTNM = "soft_lutpair209" *) 
  LUT3 #(
    .INIT(8'h02)) 
    idelay_tap_limit_r_i_1
       (.I0(idelay_tap_limit_r_i_2_n_0),
        .I1(new_cnt_cpt_r_reg_0),
        .I2(\done_cnt_reg[2]_0 ),
        .O(idelay_tap_limit_r_i_1_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    idelay_tap_limit_r_i_2
       (.I0(idelay_tap_cnt_r[3]),
        .I1(idelay_tap_cnt_r[0]),
        .I2(idelay_tap_cnt_r[2]),
        .I3(idelay_tap_cnt_r[4]),
        .I4(idelay_tap_cnt_r[1]),
        .I5(idelay_tap_limit_r_reg_n_0),
        .O(idelay_tap_limit_r_i_2_n_0));
  FDRE idelay_tap_limit_r_reg
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(idelay_tap_limit_r_i_1_n_0),
        .Q(idelay_tap_limit_r_reg_n_0),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair115" *) 
  LUT4 #(
    .INIT(16'h000B)) 
    \init_state_r[1]_i_28 
       (.I0(rdlvl_stg1_done_r1),
        .I1(rdlvl_stg1_done_int_reg_0),
        .I2(rdlvl_stg1_rank_done),
        .I3(\init_state_r[1]_i_16 ),
        .O(rdlvl_stg1_done_r1_reg));
  LUT5 #(
    .INIT(32'h00000200)) 
    \mpr_4to1.idel_mpr_pat_detect_r_i_1 
       (.I0(\mpr_4to1.inhibit_edge_detect_r_i_4_n_0 ),
        .I1(\mpr_4to1.idel_mpr_pat_detect_r_i_2_n_0 ),
        .I2(p_1_in26_in),
        .I3(\mpr_4to1.idel_mpr_pat_detect_r_i_3_n_0 ),
        .I4(inhibit_edge_detect_r),
        .O(\mpr_4to1.idel_mpr_pat_detect_r_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair123" *) 
  LUT4 #(
    .INIT(16'h0008)) 
    \mpr_4to1.idel_mpr_pat_detect_r_i_2 
       (.I0(p_0_in549_in),
        .I1(idel_pat_detect_valid_r_reg_n_0),
        .I2(\mpr_4to1.stable_idel_cnt_reg_n_0_[1] ),
        .I3(\mpr_4to1.stable_idel_cnt_reg_n_0_[2] ),
        .O(\mpr_4to1.idel_mpr_pat_detect_r_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF00100000)) 
    \mpr_4to1.idel_mpr_pat_detect_r_i_3 
       (.I0(\mpr_4to1.inhibit_edge_detect_r_i_3_n_0 ),
        .I1(\mpr_4to1.stable_idel_cnt_reg_n_0_[0] ),
        .I2(\mpr_4to1.stable_idel_cnt_reg_n_0_[1] ),
        .I3(\mpr_4to1.stable_idel_cnt_reg_n_0_[2] ),
        .I4(\mpr_4to1.stable_idel_cnt[2]_i_4_n_0 ),
        .I5(idel_mpr_pat_detect_r),
        .O(\mpr_4to1.idel_mpr_pat_detect_r_i_3_n_0 ));
  FDRE \mpr_4to1.idel_mpr_pat_detect_r_reg 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\mpr_4to1.idel_mpr_pat_detect_r_i_1_n_0 ),
        .Q(idel_mpr_pat_detect_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hF700FFFF)) 
    \mpr_4to1.inhibit_edge_detect_r_i_1 
       (.I0(\mpr_4to1.inhibit_edge_detect_r_i_2_n_0 ),
        .I1(p_0_in549_in),
        .I2(\mpr_4to1.inhibit_edge_detect_r_i_3_n_0 ),
        .I3(inhibit_edge_detect_r),
        .I4(\mpr_4to1.inhibit_edge_detect_r_i_4_n_0 ),
        .O(\mpr_4to1.inhibit_edge_detect_r_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \mpr_4to1.inhibit_edge_detect_r_i_2 
       (.I0(idelay_tap_cnt_r[3]),
        .I1(idelay_tap_cnt_r[4]),
        .I2(idelay_tap_cnt_r[1]),
        .I3(idelay_tap_cnt_r[2]),
        .O(\mpr_4to1.inhibit_edge_detect_r_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFBFF)) 
    \mpr_4to1.inhibit_edge_detect_r_i_3 
       (.I0(mpr_rd_rise2_prev_r),
        .I1(mpr_rd_fall2_prev_r),
        .I2(mpr_rd_rise1_prev_r),
        .I3(mpr_rd_fall0_prev_r),
        .I4(\mpr_4to1.inhibit_edge_detect_r_i_5_n_0 ),
        .O(\mpr_4to1.inhibit_edge_detect_r_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h5555555555554555)) 
    \mpr_4to1.inhibit_edge_detect_r_i_4 
       (.I0(pi_stg2_f_incdec_timing_reg_0),
        .I1(\mpr_4to1.inhibit_edge_detect_r_i_6_n_0 ),
        .I2(mpr_rd_rise2_prev_r),
        .I3(mpr_rd_rise1_prev_r),
        .I4(mpr_rd_fall1_prev_r),
        .I5(mpr_rd_fall0_prev_r),
        .O(\mpr_4to1.inhibit_edge_detect_r_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair113" *) 
  LUT4 #(
    .INIT(16'hFFDF)) 
    \mpr_4to1.inhibit_edge_detect_r_i_5 
       (.I0(mpr_rd_fall1_prev_r),
        .I1(mpr_rd_rise3_prev_r),
        .I2(mpr_rd_fall3_prev_r),
        .I3(mpr_rd_rise0_prev_r),
        .O(\mpr_4to1.inhibit_edge_detect_r_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair113" *) 
  LUT4 #(
    .INIT(16'hFFF7)) 
    \mpr_4to1.inhibit_edge_detect_r_i_6 
       (.I0(mpr_rd_rise3_prev_r),
        .I1(mpr_rd_rise0_prev_r),
        .I2(mpr_rd_fall2_prev_r),
        .I3(mpr_rd_fall3_prev_r),
        .O(\mpr_4to1.inhibit_edge_detect_r_i_6_n_0 ));
  FDRE \mpr_4to1.inhibit_edge_detect_r_reg 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\mpr_4to1.inhibit_edge_detect_r_i_1_n_0 ),
        .Q(inhibit_edge_detect_r),
        .R(1'b0));
  LUT3 #(
    .INIT(8'h06)) 
    \mpr_4to1.stable_idel_cnt[0]_i_1 
       (.I0(\mpr_4to1.stable_idel_cnt_reg_n_0_[0] ),
        .I1(stable_idel_cnt),
        .I2(stable_idel_cnt0),
        .O(\mpr_4to1.stable_idel_cnt[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair94" *) 
  LUT4 #(
    .INIT(16'h006A)) 
    \mpr_4to1.stable_idel_cnt[1]_i_1 
       (.I0(\mpr_4to1.stable_idel_cnt_reg_n_0_[1] ),
        .I1(stable_idel_cnt),
        .I2(\mpr_4to1.stable_idel_cnt_reg_n_0_[0] ),
        .I3(stable_idel_cnt0),
        .O(\mpr_4to1.stable_idel_cnt[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair94" *) 
  LUT5 #(
    .INIT(32'h00006AAA)) 
    \mpr_4to1.stable_idel_cnt[2]_i_1 
       (.I0(\mpr_4to1.stable_idel_cnt_reg_n_0_[2] ),
        .I1(stable_idel_cnt),
        .I2(\mpr_4to1.stable_idel_cnt_reg_n_0_[1] ),
        .I3(\mpr_4to1.stable_idel_cnt_reg_n_0_[0] ),
        .I4(stable_idel_cnt0),
        .O(\mpr_4to1.stable_idel_cnt[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000040)) 
    \mpr_4to1.stable_idel_cnt[2]_i_2 
       (.I0(\mpr_4to1.stable_idel_cnt[2]_i_4_n_0 ),
        .I1(p_0_in549_in),
        .I2(idel_pat_detect_valid_r_reg_n_0),
        .I3(\mpr_4to1.stable_idel_cnt_reg_n_0_[1] ),
        .I4(\mpr_4to1.stable_idel_cnt_reg_n_0_[2] ),
        .I5(\FSM_onehot_cal1_state_r[16]_i_3_n_0 ),
        .O(stable_idel_cnt));
  (* SOFT_HLUTNM = "soft_lutpair212" *) 
  LUT3 #(
    .INIT(8'hFE)) 
    \mpr_4to1.stable_idel_cnt[2]_i_3 
       (.I0(\mpr_4to1.stable_idel_cnt[2]_i_4_n_0 ),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[8] ),
        .I2(pi_stg2_f_incdec_timing_reg_0),
        .O(stable_idel_cnt0));
  LUT6 #(
    .INIT(64'hFFFFFFFFBEFFFFBE)) 
    \mpr_4to1.stable_idel_cnt[2]_i_4 
       (.I0(\mpr_4to1.stable_idel_cnt[2]_i_5_n_0 ),
        .I1(\gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0] ),
        .I2(mpr_rd_rise3_prev_r),
        .I3(\gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0] ),
        .I4(mpr_rd_fall1_prev_r),
        .I5(\mpr_4to1.stable_idel_cnt[2]_i_6_n_0 ),
        .O(\mpr_4to1.stable_idel_cnt[2]_i_4_n_0 ));
  LUT4 #(
    .INIT(16'h6FF6)) 
    \mpr_4to1.stable_idel_cnt[2]_i_5 
       (.I0(\gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0] ),
        .I1(mpr_rd_fall3_prev_r),
        .I2(\gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0] ),
        .I3(mpr_rd_rise0_prev_r),
        .O(\mpr_4to1.stable_idel_cnt[2]_i_5_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF6FF6)) 
    \mpr_4to1.stable_idel_cnt[2]_i_6 
       (.I0(mpr_rd_rise2_prev_r),
        .I1(\gen_mux_rd[0].mux_rd_rise2_r_reg_n_0_[0] ),
        .I2(mpr_rd_fall0_prev_r),
        .I3(\gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0] ),
        .I4(\mpr_4to1.stable_idel_cnt[2]_i_7_n_0 ),
        .O(\mpr_4to1.stable_idel_cnt[2]_i_6_n_0 ));
  LUT4 #(
    .INIT(16'h6FF6)) 
    \mpr_4to1.stable_idel_cnt[2]_i_7 
       (.I0(\gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0] ),
        .I1(mpr_rd_fall2_prev_r),
        .I2(\gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0] ),
        .I3(mpr_rd_rise1_prev_r),
        .O(\mpr_4to1.stable_idel_cnt[2]_i_7_n_0 ));
  FDRE \mpr_4to1.stable_idel_cnt_reg[0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\mpr_4to1.stable_idel_cnt[0]_i_1_n_0 ),
        .Q(\mpr_4to1.stable_idel_cnt_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \mpr_4to1.stable_idel_cnt_reg[1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\mpr_4to1.stable_idel_cnt[1]_i_1_n_0 ),
        .Q(\mpr_4to1.stable_idel_cnt_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \mpr_4to1.stable_idel_cnt_reg[2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\mpr_4to1.stable_idel_cnt[2]_i_1_n_0 ),
        .Q(\mpr_4to1.stable_idel_cnt_reg_n_0_[2] ),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hDC)) 
    mpr_dec_cpt_r_i_1
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[16] ),
        .I1(mpr_dec_cpt_r),
        .I2(mpr_dec_cpt_r_reg_n_0),
        .O(mpr_dec_cpt_r_i_1_n_0));
  FDRE mpr_dec_cpt_r_reg
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(mpr_dec_cpt_r_i_1_n_0),
        .Q(mpr_dec_cpt_r_reg_n_0),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 [1]));
  FDRE mpr_rd_fall0_prev_r_reg
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(mpr_rd_rise0_prev_r0),
        .D(\gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0] ),
        .Q(mpr_rd_fall0_prev_r),
        .R(1'b0));
  FDRE mpr_rd_fall1_prev_r_reg
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(mpr_rd_rise0_prev_r0),
        .D(\gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0] ),
        .Q(mpr_rd_fall1_prev_r),
        .R(1'b0));
  FDRE mpr_rd_fall2_prev_r_reg
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(mpr_rd_rise0_prev_r0),
        .D(\gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0] ),
        .Q(mpr_rd_fall2_prev_r),
        .R(1'b0));
  FDRE mpr_rd_fall3_prev_r_reg
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(mpr_rd_rise0_prev_r0),
        .D(\gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0] ),
        .Q(mpr_rd_fall3_prev_r),
        .R(1'b0));
  FDRE mpr_rd_rise0_prev_r_reg
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(mpr_rd_rise0_prev_r0),
        .D(\gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0] ),
        .Q(mpr_rd_rise0_prev_r),
        .R(1'b0));
  LUT3 #(
    .INIT(8'hEA)) 
    mpr_rd_rise1_prev_r_i_1
       (.I0(p_1_in26_in),
        .I1(p_0_in549_in),
        .I2(idel_pat_detect_valid_r_reg_n_0),
        .O(mpr_rd_rise0_prev_r0));
  FDRE mpr_rd_rise1_prev_r_reg
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(mpr_rd_rise0_prev_r0),
        .D(\gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0] ),
        .Q(mpr_rd_rise1_prev_r),
        .R(1'b0));
  FDRE mpr_rd_rise2_prev_r_reg
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(mpr_rd_rise0_prev_r0),
        .D(\gen_mux_rd[0].mux_rd_rise2_r_reg_n_0_[0] ),
        .Q(mpr_rd_rise2_prev_r),
        .R(1'b0));
  FDRE mpr_rd_rise3_prev_r_reg
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(mpr_rd_rise0_prev_r0),
        .D(\gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0] ),
        .Q(mpr_rd_rise3_prev_r),
        .R(1'b0));
  FDRE mpr_rdlvl_start_r_reg
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(mpr_rdlvl_start_r_reg_0),
        .Q(mpr_rdlvl_start_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hAAAAAAAAEAEEAAAA)) 
    new_cnt_cpt_r_i_1
       (.I0(new_cnt_cpt_r_i_2_n_0),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[7] ),
        .I2(mpr_rdlvl_start_r),
        .I3(mpr_rdlvl_start_r_reg_0),
        .I4(rdlvl_stg1_start_r_reg_0),
        .I5(rdlvl_stg1_start_r),
        .O(new_cnt_cpt_r));
  LUT6 #(
    .INIT(64'h0888888888888888)) 
    new_cnt_cpt_r_i_2
       (.I0(prech_done),
        .I1(cal1_prech_req_r),
        .I2(\cal1_cnt_cpt_r_reg_n_0_[2] ),
        .I3(\cal1_cnt_cpt_r[2]_i_3_n_0 ),
        .I4(\cal1_cnt_cpt_r_reg_n_0_[0] ),
        .I5(\cal1_cnt_cpt_r_reg_n_0_[1] ),
        .O(new_cnt_cpt_r_i_2_n_0));
  FDRE new_cnt_cpt_r_reg
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(new_cnt_cpt_r),
        .Q(new_cnt_cpt_r_reg_0),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 [1]));
  LUT6 #(
    .INIT(64'h0000000000040000)) 
    pi_cnt_dec_i_1
       (.I0(pi_cnt_dec_i_2_n_0),
        .I1(dqs_po_dec_done_r2),
        .I2(pi_stg2_f_incdec_timing_reg_0),
        .I3(wait_cnt_r_reg[1]),
        .I4(wait_cnt_r_reg[0]),
        .I5(\pi_rdval_cnt[5]_i_3_n_0 ),
        .O(pi_cnt_dec_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair122" *) 
  LUT2 #(
    .INIT(4'hE)) 
    pi_cnt_dec_i_2
       (.I0(wait_cnt_r_reg[2]),
        .I1(wait_cnt_r_reg[3]),
        .O(pi_cnt_dec_i_2_n_0));
  FDRE pi_cnt_dec_reg
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(pi_cnt_dec_i_1_n_0),
        .Q(pi_cnt_dec_reg_0),
        .R(1'b0));
  FDRE pi_en_stg2_f_reg
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(pi_en_stg2_f_timing),
        .Q(rdlvl_pi_stg2_f_en),
        .R(1'b0));
  LUT2 #(
    .INIT(4'hE)) 
    pi_en_stg2_f_timing_i_1
       (.I0(cal1_dlyce_cpt_r_reg_n_0),
        .I1(pi_cnt_dec_reg_0),
        .O(pi_en_stg2_f_timing_i_1_n_0));
  FDRE pi_en_stg2_f_timing_reg
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(pi_en_stg2_f_timing_i_1_n_0),
        .Q(pi_en_stg2_f_timing),
        .R(SR[1]));
  FDRE pi_fine_dly_dec_done_reg
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(fine_dly_dec_done_r2),
        .Q(pi_fine_dly_dec_done),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair89" *) 
  LUT5 #(
    .INIT(32'h080808FB)) 
    \pi_rdval_cnt[0]_i_1 
       (.I0(D[0]),
        .I1(dqs_po_dec_done_r1),
        .I2(dqs_po_dec_done_r2),
        .I3(pi_rdval_cnt[0]),
        .I4(\pi_rdval_cnt[5]_i_3_n_0 ),
        .O(\pi_rdval_cnt[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h08FB0808080808FB)) 
    \pi_rdval_cnt[1]_i_1 
       (.I0(D[1]),
        .I1(dqs_po_dec_done_r1),
        .I2(dqs_po_dec_done_r2),
        .I3(\pi_rdval_cnt[5]_i_3_n_0 ),
        .I4(pi_rdval_cnt[0]),
        .I5(pi_rdval_cnt[1]),
        .O(\pi_rdval_cnt[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h88888888BBB8888B)) 
    \pi_rdval_cnt[2]_i_1 
       (.I0(D[2]),
        .I1(\pi_rdval_cnt[3]_i_2_n_0 ),
        .I2(pi_rdval_cnt[1]),
        .I3(pi_rdval_cnt[0]),
        .I4(pi_rdval_cnt[2]),
        .I5(\pi_rdval_cnt[5]_i_3_n_0 ),
        .O(\pi_rdval_cnt[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h88888888BB8B88B8)) 
    \pi_rdval_cnt[3]_i_1 
       (.I0(D[3]),
        .I1(\pi_rdval_cnt[3]_i_2_n_0 ),
        .I2(\pi_rdval_cnt[3]_i_3_n_0 ),
        .I3(pi_rdval_cnt[2]),
        .I4(pi_rdval_cnt[3]),
        .I5(\pi_rdval_cnt[5]_i_3_n_0 ),
        .O(\pi_rdval_cnt[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair89" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \pi_rdval_cnt[3]_i_2 
       (.I0(dqs_po_dec_done_r1),
        .I1(dqs_po_dec_done_r2),
        .O(\pi_rdval_cnt[3]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair118" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \pi_rdval_cnt[3]_i_3 
       (.I0(pi_rdval_cnt[1]),
        .I1(pi_rdval_cnt[0]),
        .O(\pi_rdval_cnt[3]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h08FB0808FB08FB08)) 
    \pi_rdval_cnt[4]_i_1 
       (.I0(D[4]),
        .I1(dqs_po_dec_done_r1),
        .I2(dqs_po_dec_done_r2),
        .I3(pi_rdval_cnt[4]),
        .I4(pi_rdval_cnt[5]),
        .I5(\pi_rdval_cnt[5]_i_4_n_0 ),
        .O(\pi_rdval_cnt[4]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFFAE)) 
    \pi_rdval_cnt[5]_i_1 
       (.I0(pi_cnt_dec_reg_0),
        .I1(dqs_po_dec_done_r1),
        .I2(dqs_po_dec_done_r2),
        .I3(\pi_rdval_cnt[5]_i_3_n_0 ),
        .O(\pi_rdval_cnt[5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFB080808FB08FB08)) 
    \pi_rdval_cnt[5]_i_2 
       (.I0(D[5]),
        .I1(dqs_po_dec_done_r1),
        .I2(dqs_po_dec_done_r2),
        .I3(pi_rdval_cnt[5]),
        .I4(pi_rdval_cnt[4]),
        .I5(\pi_rdval_cnt[5]_i_4_n_0 ),
        .O(\pi_rdval_cnt[5]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \pi_rdval_cnt[5]_i_3 
       (.I0(pi_rdval_cnt[3]),
        .I1(pi_rdval_cnt[2]),
        .I2(pi_rdval_cnt[1]),
        .I3(pi_rdval_cnt[0]),
        .I4(pi_rdval_cnt[5]),
        .I5(pi_rdval_cnt[4]),
        .O(\pi_rdval_cnt[5]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair118" *) 
  LUT4 #(
    .INIT(16'h0001)) 
    \pi_rdval_cnt[5]_i_4 
       (.I0(pi_rdval_cnt[0]),
        .I1(pi_rdval_cnt[1]),
        .I2(pi_rdval_cnt[2]),
        .I3(pi_rdval_cnt[3]),
        .O(\pi_rdval_cnt[5]_i_4_n_0 ));
  FDRE \pi_rdval_cnt_reg[0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\pi_rdval_cnt[5]_i_1_n_0 ),
        .D(\pi_rdval_cnt[0]_i_1_n_0 ),
        .Q(pi_rdval_cnt[0]),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 [1]));
  FDRE \pi_rdval_cnt_reg[1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\pi_rdval_cnt[5]_i_1_n_0 ),
        .D(\pi_rdval_cnt[1]_i_1_n_0 ),
        .Q(pi_rdval_cnt[1]),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 [1]));
  FDRE \pi_rdval_cnt_reg[2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\pi_rdval_cnt[5]_i_1_n_0 ),
        .D(\pi_rdval_cnt[2]_i_1_n_0 ),
        .Q(pi_rdval_cnt[2]),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 [1]));
  FDRE \pi_rdval_cnt_reg[3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\pi_rdval_cnt[5]_i_1_n_0 ),
        .D(\pi_rdval_cnt[3]_i_1_n_0 ),
        .Q(pi_rdval_cnt[3]),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 [1]));
  FDRE \pi_rdval_cnt_reg[4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\pi_rdval_cnt[5]_i_1_n_0 ),
        .D(\pi_rdval_cnt[4]_i_1_n_0 ),
        .Q(pi_rdval_cnt[4]),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 [1]));
  FDRE \pi_rdval_cnt_reg[5] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\pi_rdval_cnt[5]_i_1_n_0 ),
        .D(\pi_rdval_cnt[5]_i_2_n_0 ),
        .Q(pi_rdval_cnt[5]),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 [1]));
  FDRE pi_stg2_f_incdec_reg
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(pi_stg2_f_incdec_timing),
        .Q(rdlvl_pi_stg2_f_incdec),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair114" *) 
  LUT4 #(
    .INIT(16'h0008)) 
    pi_stg2_f_incdec_timing_i_1
       (.I0(cal1_dlyce_cpt_r_reg_n_0),
        .I1(cal1_dlyinc_cpt_r_reg_n_0),
        .I2(pi_cnt_dec_reg_0),
        .I3(pi_stg2_f_incdec_timing_reg_0),
        .O(pi_stg2_f_incdec_timing_i_1_n_0));
  FDRE pi_stg2_f_incdec_timing_reg
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(pi_stg2_f_incdec_timing_i_1_n_0),
        .Q(pi_stg2_f_incdec_timing),
        .R(1'b0));
  FDRE pi_stg2_load_reg
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(pi_stg2_load_timing),
        .Q(pi_stg2_load_reg_0),
        .R(1'b0));
  LUT3 #(
    .INIT(8'h04)) 
    pi_stg2_load_timing_i_1
       (.I0(regl_dqs_cnt[3]),
        .I1(\pi_stg2_reg_l_timing[5]_i_3_n_0 ),
        .I2(\regl_rank_cnt[1]_i_3_n_0 ),
        .O(pi_stg2_load_timing_i_1_n_0));
  FDRE pi_stg2_load_timing_reg
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(pi_stg2_load_timing_i_1_n_0),
        .Q(pi_stg2_load_timing),
        .R(1'b0));
  FDRE \pi_stg2_reg_l_reg[0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(pi_stg2_reg_l_timing[0]),
        .Q(\pi_stg2_reg_l_reg[5]_0 [0]),
        .R(1'b0));
  FDRE \pi_stg2_reg_l_reg[1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(pi_stg2_reg_l_timing[1]),
        .Q(\pi_stg2_reg_l_reg[5]_0 [1]),
        .R(1'b0));
  FDRE \pi_stg2_reg_l_reg[2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(pi_stg2_reg_l_timing[2]),
        .Q(\pi_stg2_reg_l_reg[5]_0 [2]),
        .R(1'b0));
  FDRE \pi_stg2_reg_l_reg[3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(pi_stg2_reg_l_timing[3]),
        .Q(\pi_stg2_reg_l_reg[5]_0 [3]),
        .R(1'b0));
  FDRE \pi_stg2_reg_l_reg[4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(pi_stg2_reg_l_timing[4]),
        .Q(\pi_stg2_reg_l_reg[5]_0 [4]),
        .R(1'b0));
  FDRE \pi_stg2_reg_l_reg[5] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(pi_stg2_reg_l_timing[5]),
        .Q(\pi_stg2_reg_l_reg[5]_0 [5]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \pi_stg2_reg_l_timing[0]_i_2 
       (.I0(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][0] ),
        .I1(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][0] ),
        .I2(regl_dqs_cnt[1]),
        .I3(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][0] ),
        .I4(regl_dqs_cnt[0]),
        .I5(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][0] ),
        .O(\pi_stg2_reg_l_timing[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \pi_stg2_reg_l_timing[0]_i_3 
       (.I0(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][7][0] ),
        .I1(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][6][0] ),
        .I2(regl_dqs_cnt[1]),
        .I3(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][5][0] ),
        .I4(regl_dqs_cnt[0]),
        .I5(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][4][0] ),
        .O(\pi_stg2_reg_l_timing[0]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \pi_stg2_reg_l_timing[1]_i_2 
       (.I0(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][1] ),
        .I1(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][1] ),
        .I2(regl_dqs_cnt[1]),
        .I3(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][1] ),
        .I4(regl_dqs_cnt[0]),
        .I5(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][1] ),
        .O(\pi_stg2_reg_l_timing[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \pi_stg2_reg_l_timing[1]_i_3 
       (.I0(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][7][1] ),
        .I1(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][6][1] ),
        .I2(regl_dqs_cnt[1]),
        .I3(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][5][1] ),
        .I4(regl_dqs_cnt[0]),
        .I5(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][4][1] ),
        .O(\pi_stg2_reg_l_timing[1]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \pi_stg2_reg_l_timing[2]_i_2 
       (.I0(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][2] ),
        .I1(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][2] ),
        .I2(regl_dqs_cnt[1]),
        .I3(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][2] ),
        .I4(regl_dqs_cnt[0]),
        .I5(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][2] ),
        .O(\pi_stg2_reg_l_timing[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \pi_stg2_reg_l_timing[2]_i_3 
       (.I0(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][7][2] ),
        .I1(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][6][2] ),
        .I2(regl_dqs_cnt[1]),
        .I3(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][5][2] ),
        .I4(regl_dqs_cnt[0]),
        .I5(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][4][2] ),
        .O(\pi_stg2_reg_l_timing[2]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \pi_stg2_reg_l_timing[3]_i_2 
       (.I0(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][3] ),
        .I1(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][3] ),
        .I2(regl_dqs_cnt[1]),
        .I3(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][3] ),
        .I4(regl_dqs_cnt[0]),
        .I5(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][3] ),
        .O(\pi_stg2_reg_l_timing[3]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \pi_stg2_reg_l_timing[3]_i_3 
       (.I0(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][7][3] ),
        .I1(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][6][3] ),
        .I2(regl_dqs_cnt[1]),
        .I3(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][5][3] ),
        .I4(regl_dqs_cnt[0]),
        .I5(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][4][3] ),
        .O(\pi_stg2_reg_l_timing[3]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \pi_stg2_reg_l_timing[4]_i_2 
       (.I0(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][4] ),
        .I1(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][4] ),
        .I2(regl_dqs_cnt[1]),
        .I3(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][4] ),
        .I4(regl_dqs_cnt[0]),
        .I5(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][4] ),
        .O(\pi_stg2_reg_l_timing[4]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \pi_stg2_reg_l_timing[4]_i_3 
       (.I0(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][7][4] ),
        .I1(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][6][4] ),
        .I2(regl_dqs_cnt[1]),
        .I3(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][5][4] ),
        .I4(regl_dqs_cnt[0]),
        .I5(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][4][4] ),
        .O(\pi_stg2_reg_l_timing[4]_i_3_n_0 ));
  LUT3 #(
    .INIT(8'hEF)) 
    \pi_stg2_reg_l_timing[5]_i_1 
       (.I0(\regl_rank_cnt[1]_i_3_n_0 ),
        .I1(regl_dqs_cnt[3]),
        .I2(\pi_stg2_reg_l_timing[5]_i_3_n_0 ),
        .O(\pi_stg2_reg_l_timing[5]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00020000)) 
    \pi_stg2_reg_l_timing[5]_i_3 
       (.I0(p_0_in541_in),
        .I1(done_cnt[2]),
        .I2(done_cnt[3]),
        .I3(done_cnt[1]),
        .I4(done_cnt[0]),
        .O(\pi_stg2_reg_l_timing[5]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \pi_stg2_reg_l_timing[5]_i_4 
       (.I0(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][5] ),
        .I1(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][5] ),
        .I2(regl_dqs_cnt[1]),
        .I3(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][5] ),
        .I4(regl_dqs_cnt[0]),
        .I5(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][5] ),
        .O(\pi_stg2_reg_l_timing[5]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \pi_stg2_reg_l_timing[5]_i_5 
       (.I0(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][7][5] ),
        .I1(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][6][5] ),
        .I2(regl_dqs_cnt[1]),
        .I3(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][5][5] ),
        .I4(regl_dqs_cnt[0]),
        .I5(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][4][5] ),
        .O(\pi_stg2_reg_l_timing[5]_i_5_n_0 ));
  FDRE \pi_stg2_reg_l_timing_reg[0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(rdlvl_dqs_tap_cnt_r[0]),
        .Q(pi_stg2_reg_l_timing[0]),
        .R(\pi_stg2_reg_l_timing[5]_i_1_n_0 ));
  MUXF7 \pi_stg2_reg_l_timing_reg[0]_i_1 
       (.I0(\pi_stg2_reg_l_timing[0]_i_2_n_0 ),
        .I1(\pi_stg2_reg_l_timing[0]_i_3_n_0 ),
        .O(rdlvl_dqs_tap_cnt_r[0]),
        .S(regl_dqs_cnt[2]));
  FDRE \pi_stg2_reg_l_timing_reg[1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(rdlvl_dqs_tap_cnt_r[1]),
        .Q(pi_stg2_reg_l_timing[1]),
        .R(\pi_stg2_reg_l_timing[5]_i_1_n_0 ));
  MUXF7 \pi_stg2_reg_l_timing_reg[1]_i_1 
       (.I0(\pi_stg2_reg_l_timing[1]_i_2_n_0 ),
        .I1(\pi_stg2_reg_l_timing[1]_i_3_n_0 ),
        .O(rdlvl_dqs_tap_cnt_r[1]),
        .S(regl_dqs_cnt[2]));
  FDRE \pi_stg2_reg_l_timing_reg[2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(rdlvl_dqs_tap_cnt_r[2]),
        .Q(pi_stg2_reg_l_timing[2]),
        .R(\pi_stg2_reg_l_timing[5]_i_1_n_0 ));
  MUXF7 \pi_stg2_reg_l_timing_reg[2]_i_1 
       (.I0(\pi_stg2_reg_l_timing[2]_i_2_n_0 ),
        .I1(\pi_stg2_reg_l_timing[2]_i_3_n_0 ),
        .O(rdlvl_dqs_tap_cnt_r[2]),
        .S(regl_dqs_cnt[2]));
  FDRE \pi_stg2_reg_l_timing_reg[3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(rdlvl_dqs_tap_cnt_r[3]),
        .Q(pi_stg2_reg_l_timing[3]),
        .R(\pi_stg2_reg_l_timing[5]_i_1_n_0 ));
  MUXF7 \pi_stg2_reg_l_timing_reg[3]_i_1 
       (.I0(\pi_stg2_reg_l_timing[3]_i_2_n_0 ),
        .I1(\pi_stg2_reg_l_timing[3]_i_3_n_0 ),
        .O(rdlvl_dqs_tap_cnt_r[3]),
        .S(regl_dqs_cnt[2]));
  FDRE \pi_stg2_reg_l_timing_reg[4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(rdlvl_dqs_tap_cnt_r[4]),
        .Q(pi_stg2_reg_l_timing[4]),
        .R(\pi_stg2_reg_l_timing[5]_i_1_n_0 ));
  MUXF7 \pi_stg2_reg_l_timing_reg[4]_i_1 
       (.I0(\pi_stg2_reg_l_timing[4]_i_2_n_0 ),
        .I1(\pi_stg2_reg_l_timing[4]_i_3_n_0 ),
        .O(rdlvl_dqs_tap_cnt_r[4]),
        .S(regl_dqs_cnt[2]));
  FDRE \pi_stg2_reg_l_timing_reg[5] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(rdlvl_dqs_tap_cnt_r[5]),
        .Q(pi_stg2_reg_l_timing[5]),
        .R(\pi_stg2_reg_l_timing[5]_i_1_n_0 ));
  MUXF7 \pi_stg2_reg_l_timing_reg[5]_i_2 
       (.I0(\pi_stg2_reg_l_timing[5]_i_4_n_0 ),
        .I1(\pi_stg2_reg_l_timing[5]_i_5_n_0 ),
        .O(rdlvl_dqs_tap_cnt_r[5]),
        .S(regl_dqs_cnt[2]));
  LUT5 #(
    .INIT(32'hFFFEFEFE)) 
    prech_req_r_i_1
       (.I0(rdlvl_prech_req),
        .I1(wrcal_prech_req),
        .I2(prech_req_r_reg),
        .I3(dqs_found_prech_req),
        .I4(prech_req_r_reg_0),
        .O(prech_req));
  FDRE \rd_mux_sel_r_reg[0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\cal1_cnt_cpt_r_reg_n_0_[0] ),
        .Q(Q[0]),
        .R(1'b0));
  FDRE \rd_mux_sel_r_reg[1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\cal1_cnt_cpt_r_reg_n_0_[1] ),
        .Q(Q[1]),
        .R(1'b0));
  FDRE \rd_mux_sel_r_reg[2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\cal1_cnt_cpt_r_reg_n_0_[2] ),
        .Q(\rd_mux_sel_r_reg_n_0_[2] ),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \rdlvl_dqs_tap_cnt_r[0][0][5]_i_1 
       (.I0(Q[1]),
        .I1(Q[0]),
        .I2(\rd_mux_sel_r_reg_n_0_[2] ),
        .I3(\rnk_cnt_r_reg_n_0_[0] ),
        .I4(\rnk_cnt_r_reg_n_0_[1] ),
        .I5(\rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0 ),
        .O(\rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFEFFFFFFFFFFFFFF)) 
    \rdlvl_dqs_tap_cnt_r[0][0][5]_i_2 
       (.I0(\cal1_state_r1_reg_n_0_[4] ),
        .I1(\cal1_state_r1_reg_n_0_[5] ),
        .I2(\cal1_state_r1_reg_n_0_[0] ),
        .I3(\cal1_state_r1_reg_n_0_[2] ),
        .I4(\cal1_state_r1_reg_n_0_[1] ),
        .I5(\cal1_state_r1_reg_n_0_[3] ),
        .O(\rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000100000000)) 
    \rdlvl_dqs_tap_cnt_r[0][1][5]_i_1 
       (.I0(\rd_mux_sel_r_reg_n_0_[2] ),
        .I1(\rnk_cnt_r_reg_n_0_[0] ),
        .I2(\rnk_cnt_r_reg_n_0_[1] ),
        .I3(\rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0 ),
        .I4(Q[1]),
        .I5(Q[0]),
        .O(\rdlvl_dqs_tap_cnt_r[0][1][5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000100000000)) 
    \rdlvl_dqs_tap_cnt_r[0][2][5]_i_1 
       (.I0(\rd_mux_sel_r_reg_n_0_[2] ),
        .I1(\rnk_cnt_r_reg_n_0_[0] ),
        .I2(\rnk_cnt_r_reg_n_0_[1] ),
        .I3(\rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0 ),
        .I4(Q[0]),
        .I5(Q[1]),
        .O(\rdlvl_dqs_tap_cnt_r[0][2][5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0001000000000000)) 
    \rdlvl_dqs_tap_cnt_r[0][3][5]_i_1 
       (.I0(\rd_mux_sel_r_reg_n_0_[2] ),
        .I1(\rnk_cnt_r_reg_n_0_[0] ),
        .I2(\rnk_cnt_r_reg_n_0_[1] ),
        .I3(\rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0 ),
        .I4(Q[1]),
        .I5(Q[0]),
        .O(\rdlvl_dqs_tap_cnt_r[0][3][5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000010)) 
    \rdlvl_dqs_tap_cnt_r[0][4][5]_i_1 
       (.I0(Q[1]),
        .I1(Q[0]),
        .I2(\rd_mux_sel_r_reg_n_0_[2] ),
        .I3(\rnk_cnt_r_reg_n_0_[0] ),
        .I4(\rnk_cnt_r_reg_n_0_[1] ),
        .I5(\rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0 ),
        .O(\rdlvl_dqs_tap_cnt_r[0][4][5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000040)) 
    \rdlvl_dqs_tap_cnt_r[0][5][5]_i_1 
       (.I0(Q[1]),
        .I1(Q[0]),
        .I2(\rd_mux_sel_r_reg_n_0_[2] ),
        .I3(\rnk_cnt_r_reg_n_0_[0] ),
        .I4(\rnk_cnt_r_reg_n_0_[1] ),
        .I5(\rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0 ),
        .O(\rdlvl_dqs_tap_cnt_r[0][5][5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000040)) 
    \rdlvl_dqs_tap_cnt_r[0][6][5]_i_1 
       (.I0(Q[0]),
        .I1(Q[1]),
        .I2(\rd_mux_sel_r_reg_n_0_[2] ),
        .I3(\rnk_cnt_r_reg_n_0_[0] ),
        .I4(\rnk_cnt_r_reg_n_0_[1] ),
        .I5(\rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0 ),
        .O(\rdlvl_dqs_tap_cnt_r[0][6][5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000080)) 
    \rdlvl_dqs_tap_cnt_r[0][7][5]_i_1 
       (.I0(Q[1]),
        .I1(Q[0]),
        .I2(\rd_mux_sel_r_reg_n_0_[2] ),
        .I3(\rnk_cnt_r_reg_n_0_[0] ),
        .I4(\rnk_cnt_r_reg_n_0_[1] ),
        .I5(\rdlvl_dqs_tap_cnt_r[0][0][5]_i_2_n_0 ),
        .O(\rdlvl_dqs_tap_cnt_r[0][7][5]_i_1_n_0 ));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][0][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][0] ),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 [0]));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][0][1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][1] ),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 [0]));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][0][2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[2] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][2] ),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 [1]));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][0][3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[3] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][3] ),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 [1]));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][0][4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[4] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][4] ),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 [1]));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][0][5] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\rdlvl_dqs_tap_cnt_r[0][0][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[5] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][0][5] ),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 [1]));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][1][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\rdlvl_dqs_tap_cnt_r[0][1][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][0] ),
        .R(SR[1]));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][1][1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\rdlvl_dqs_tap_cnt_r[0][1][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][1] ),
        .R(SR[1]));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][1][2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\rdlvl_dqs_tap_cnt_r[0][1][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[2] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][2] ),
        .R(SR[1]));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][1][3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\rdlvl_dqs_tap_cnt_r[0][1][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[3] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][3] ),
        .R(SR[1]));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][1][4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\rdlvl_dqs_tap_cnt_r[0][1][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[4] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][4] ),
        .R(SR[1]));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][1][5] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\rdlvl_dqs_tap_cnt_r[0][1][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[5] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][1][5] ),
        .R(SR[1]));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][2][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\rdlvl_dqs_tap_cnt_r[0][2][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][0] ),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 [0]));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][2][1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\rdlvl_dqs_tap_cnt_r[0][2][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][1] ),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 [0]));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][2][2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\rdlvl_dqs_tap_cnt_r[0][2][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[2] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][2] ),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 [0]));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][2][3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\rdlvl_dqs_tap_cnt_r[0][2][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[3] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][3] ),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 [0]));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][2][4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\rdlvl_dqs_tap_cnt_r[0][2][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[4] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][4] ),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 [0]));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][2][5] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\rdlvl_dqs_tap_cnt_r[0][2][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[5] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][2][5] ),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 [0]));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][3][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\rdlvl_dqs_tap_cnt_r[0][3][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][0] ),
        .R(SR[1]));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][3][1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\rdlvl_dqs_tap_cnt_r[0][3][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][1] ),
        .R(SR[1]));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][3][2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\rdlvl_dqs_tap_cnt_r[0][3][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[2] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][2] ),
        .R(SR[1]));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][3][3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\rdlvl_dqs_tap_cnt_r[0][3][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[3] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][3] ),
        .R(SR[1]));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][3][4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\rdlvl_dqs_tap_cnt_r[0][3][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[4] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][4] ),
        .R(SR[1]));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][3][5] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\rdlvl_dqs_tap_cnt_r[0][3][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[5] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][3][5] ),
        .R(SR[1]));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][4][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\rdlvl_dqs_tap_cnt_r[0][4][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][4][0] ),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 [0]));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][4][1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\rdlvl_dqs_tap_cnt_r[0][4][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][4][1] ),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 [0]));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][4][2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\rdlvl_dqs_tap_cnt_r[0][4][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[2] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][4][2] ),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 [0]));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][4][3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\rdlvl_dqs_tap_cnt_r[0][4][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[3] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][4][3] ),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 [0]));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][4][4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\rdlvl_dqs_tap_cnt_r[0][4][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[4] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][4][4] ),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 [0]));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][4][5] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\rdlvl_dqs_tap_cnt_r[0][4][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[5] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][4][5] ),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 [0]));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][5][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\rdlvl_dqs_tap_cnt_r[0][5][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][5][0] ),
        .R(SR[1]));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][5][1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\rdlvl_dqs_tap_cnt_r[0][5][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][5][1] ),
        .R(SR[1]));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][5][2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\rdlvl_dqs_tap_cnt_r[0][5][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[2] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][5][2] ),
        .R(SR[1]));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][5][3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\rdlvl_dqs_tap_cnt_r[0][5][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[3] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][5][3] ),
        .R(SR[1]));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][5][4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\rdlvl_dqs_tap_cnt_r[0][5][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[4] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][5][4] ),
        .R(SR[1]));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][5][5] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\rdlvl_dqs_tap_cnt_r[0][5][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[5] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][5][5] ),
        .R(SR[1]));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][6][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\rdlvl_dqs_tap_cnt_r[0][6][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][6][0] ),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 [0]));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][6][1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\rdlvl_dqs_tap_cnt_r[0][6][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][6][1] ),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 [0]));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][6][2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\rdlvl_dqs_tap_cnt_r[0][6][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[2] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][6][2] ),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 [0]));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][6][3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\rdlvl_dqs_tap_cnt_r[0][6][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[3] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][6][3] ),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 [0]));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][6][4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\rdlvl_dqs_tap_cnt_r[0][6][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[4] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][6][4] ),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 [0]));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][6][5] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\rdlvl_dqs_tap_cnt_r[0][6][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[5] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][6][5] ),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 [0]));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][7][0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\rdlvl_dqs_tap_cnt_r[0][7][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][7][0] ),
        .R(SR[0]));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][7][1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\rdlvl_dqs_tap_cnt_r[0][7][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][7][1] ),
        .R(SR[1]));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][7][2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\rdlvl_dqs_tap_cnt_r[0][7][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[2] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][7][2] ),
        .R(SR[1]));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][7][3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\rdlvl_dqs_tap_cnt_r[0][7][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[3] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][7][3] ),
        .R(SR[1]));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][7][4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\rdlvl_dqs_tap_cnt_r[0][7][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[4] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][7][4] ),
        .R(SR[1]));
  FDRE \rdlvl_dqs_tap_cnt_r_reg[0][7][5] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\rdlvl_dqs_tap_cnt_r[0][7][5]_i_1_n_0 ),
        .D(\tap_cnt_cpt_r_reg_n_0_[5] ),
        .Q(\rdlvl_dqs_tap_cnt_r_reg_n_0_[0][7][5] ),
        .R(SR[1]));
  LUT6 #(
    .INIT(64'hAAAAAAABAAAAAAA8)) 
    rdlvl_last_byte_done_int_i_1
       (.I0(cal1_prech_req_r),
        .I1(\FSM_onehot_cal1_state_r[5]_i_1_n_0 ),
        .I2(p_27_in),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[7] ),
        .I4(\rnk_cnt_r[1]_i_2_n_0 ),
        .I5(rdlvl_last_byte_done),
        .O(rdlvl_last_byte_done_int_i_1_n_0));
  FDRE rdlvl_last_byte_done_int_reg
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(rdlvl_last_byte_done_int_i_1_n_0),
        .Q(rdlvl_last_byte_done),
        .R(SR[1]));
  LUT5 #(
    .INIT(32'hFEFFFE00)) 
    rdlvl_pi_incdec_i_1
       (.I0(mpr_dec_cpt_r),
        .I1(rdlvl_pi_incdec_i_2_n_0),
        .I2(rdlvl_pi_incdec_i_3_n_0),
        .I3(rdlvl_pi_incdec_i_4_n_0),
        .I4(rdlvl_pi_incdec),
        .O(rdlvl_pi_incdec_i_1_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFF0FFFEFFF0)) 
    rdlvl_pi_incdec_i_2
       (.I0(p_8_in),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[8] ),
        .I2(p_14_in),
        .I3(\FSM_onehot_cal1_state_r_reg_n_0_[29] ),
        .I4(cal1_wait_r),
        .I5(p_27_in),
        .O(rdlvl_pi_incdec_i_2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair117" *) 
  LUT3 #(
    .INIT(8'h8A)) 
    rdlvl_pi_incdec_i_3
       (.I0(\FSM_onehot_cal1_state_r_reg_n_0_[7] ),
        .I1(mpr_rdlvl_start_r),
        .I2(mpr_rdlvl_start_r_reg_0),
        .O(rdlvl_pi_incdec_i_3_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFCD)) 
    rdlvl_pi_incdec_i_4
       (.I0(cal1_wait_r),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[29] ),
        .I2(rdlvl_pi_incdec_i_5_n_0),
        .I3(p_14_in),
        .I4(\cal1_state_r1[0]_i_2_n_0 ),
        .I5(rdlvl_rank_done_r_i_3_n_0),
        .O(rdlvl_pi_incdec_i_4_n_0));
  (* SOFT_HLUTNM = "soft_lutpair129" *) 
  LUT2 #(
    .INIT(4'h1)) 
    rdlvl_pi_incdec_i_5
       (.I0(p_8_in),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[8] ),
        .O(rdlvl_pi_incdec_i_5_n_0));
  FDRE rdlvl_pi_incdec_reg
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(rdlvl_pi_incdec_i_1_n_0),
        .Q(rdlvl_pi_incdec),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 [0]));
  FDRE rdlvl_prech_req_reg
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(cal1_prech_req_r__0),
        .Q(rdlvl_prech_req),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 [1]));
  LUT6 #(
    .INIT(64'hA0A0A0FFA0A0A080)) 
    rdlvl_rank_done_r_i_1
       (.I0(cal1_prech_req_r),
        .I1(prech_done),
        .I2(rdlvl_rank_done_r_i_2_n_0),
        .I3(rdlvl_rank_done_r_i_3_n_0),
        .I4(p_0_in541_in),
        .I5(rdlvl_stg1_rank_done),
        .O(rdlvl_rank_done_r_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair214" *) 
  LUT3 #(
    .INIT(8'h80)) 
    rdlvl_rank_done_r_i_2
       (.I0(\cal1_cnt_cpt_r_reg_n_0_[1] ),
        .I1(\cal1_cnt_cpt_r_reg_n_0_[0] ),
        .I2(\cal1_cnt_cpt_r_reg_n_0_[2] ),
        .O(rdlvl_rank_done_r_i_2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair210" *) 
  LUT2 #(
    .INIT(4'hE)) 
    rdlvl_rank_done_r_i_3
       (.I0(p_27_in),
        .I1(\FSM_onehot_cal1_state_r_reg_n_0_[7] ),
        .O(rdlvl_rank_done_r_i_3_n_0));
  FDRE rdlvl_rank_done_r_reg
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(rdlvl_rank_done_r_i_1_n_0),
        .Q(rdlvl_stg1_rank_done),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 [1]));
  (* SOFT_HLUTNM = "soft_lutpair115" *) 
  LUT2 #(
    .INIT(4'hE)) 
    rdlvl_stg1_done_int_i_1
       (.I0(rdlvl_stg1_done_int),
        .I1(rdlvl_stg1_done_int_reg_0),
        .O(rdlvl_stg1_done_int_i_1_n_0));
  (* syn_maxfan = "30" *) 
  FDRE rdlvl_stg1_done_int_reg
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(rdlvl_stg1_done_int_i_1_n_0),
        .Q(rdlvl_stg1_done_int_reg_0),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 [1]));
  FDRE rdlvl_stg1_start_r_reg
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(rdlvl_stg1_start_r_reg_0),
        .Q(rdlvl_stg1_start_r),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair90" *) 
  LUT4 #(
    .INIT(16'h00E6)) 
    \regl_dqs_cnt[0]_i_1 
       (.I0(regl_dqs_cnt[0]),
        .I1(\pi_stg2_reg_l_timing[5]_i_3_n_0 ),
        .I2(\FSM_onehot_cal1_state_r[5]_i_1_n_0 ),
        .I3(\regl_rank_cnt[1]_i_3_n_0 ),
        .O(\regl_dqs_cnt[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair90" *) 
  LUT5 #(
    .INIT(32'h0000EE6A)) 
    \regl_dqs_cnt[1]_i_1 
       (.I0(regl_dqs_cnt[1]),
        .I1(\pi_stg2_reg_l_timing[5]_i_3_n_0 ),
        .I2(regl_dqs_cnt[0]),
        .I3(\FSM_onehot_cal1_state_r[5]_i_1_n_0 ),
        .I4(\regl_rank_cnt[1]_i_3_n_0 ),
        .O(\regl_dqs_cnt[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000EEEE6AAA)) 
    \regl_dqs_cnt[2]_i_1 
       (.I0(regl_dqs_cnt[2]),
        .I1(\pi_stg2_reg_l_timing[5]_i_3_n_0 ),
        .I2(regl_dqs_cnt[0]),
        .I3(regl_dqs_cnt[1]),
        .I4(\FSM_onehot_cal1_state_r[5]_i_1_n_0 ),
        .I5(\regl_rank_cnt[1]_i_3_n_0 ),
        .O(\regl_dqs_cnt[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0444444444444444)) 
    \regl_dqs_cnt[3]_i_1 
       (.I0(\regl_rank_cnt[1]_i_3_n_0 ),
        .I1(regl_dqs_cnt[3]),
        .I2(regl_dqs_cnt[1]),
        .I3(regl_dqs_cnt[0]),
        .I4(regl_dqs_cnt[2]),
        .I5(\pi_stg2_reg_l_timing[5]_i_3_n_0 ),
        .O(\regl_dqs_cnt[3]_i_1_n_0 ));
  FDRE \regl_dqs_cnt_r_reg[0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(regl_dqs_cnt[0]),
        .Q(regl_dqs_cnt_r[0]),
        .R(1'b0));
  FDRE \regl_dqs_cnt_r_reg[1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(regl_dqs_cnt[1]),
        .Q(regl_dqs_cnt_r[1]),
        .R(1'b0));
  FDRE \regl_dqs_cnt_r_reg[2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(regl_dqs_cnt[2]),
        .Q(regl_dqs_cnt_r[2]),
        .R(1'b0));
  FDRE \regl_dqs_cnt_r_reg[3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(regl_dqs_cnt[3]),
        .Q(regl_dqs_cnt_r[3]),
        .R(1'b0));
  FDRE \regl_dqs_cnt_reg[0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\regl_dqs_cnt[0]_i_1_n_0 ),
        .Q(regl_dqs_cnt[0]),
        .R(1'b0));
  FDRE \regl_dqs_cnt_reg[1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\regl_dqs_cnt[1]_i_1_n_0 ),
        .Q(regl_dqs_cnt[1]),
        .R(1'b0));
  FDRE \regl_dqs_cnt_reg[2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\regl_dqs_cnt[2]_i_1_n_0 ),
        .Q(regl_dqs_cnt[2]),
        .R(1'b0));
  FDRE \regl_dqs_cnt_reg[3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\regl_dqs_cnt[3]_i_1_n_0 ),
        .Q(regl_dqs_cnt[3]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair116" *) 
  LUT4 #(
    .INIT(16'h0062)) 
    \regl_rank_cnt[0]_i_1 
       (.I0(regl_rank_cnt[0]),
        .I1(regl_rank_cnt0),
        .I2(regl_rank_cnt[1]),
        .I3(\regl_rank_cnt[1]_i_3_n_0 ),
        .O(\regl_rank_cnt[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair116" *) 
  LUT4 #(
    .INIT(16'h006A)) 
    \regl_rank_cnt[1]_i_1 
       (.I0(regl_rank_cnt[1]),
        .I1(regl_rank_cnt0),
        .I2(regl_rank_cnt[0]),
        .I3(\regl_rank_cnt[1]_i_3_n_0 ),
        .O(\regl_rank_cnt[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair88" *) 
  LUT5 #(
    .INIT(32'h00008000)) 
    \regl_rank_cnt[1]_i_2 
       (.I0(\pi_stg2_reg_l_timing[5]_i_3_n_0 ),
        .I1(regl_dqs_cnt[2]),
        .I2(regl_dqs_cnt[0]),
        .I3(regl_dqs_cnt[1]),
        .I4(regl_dqs_cnt[3]),
        .O(regl_rank_cnt0));
  (* SOFT_HLUTNM = "soft_lutpair97" *) 
  LUT5 #(
    .INIT(32'hAAAAAAAB)) 
    \regl_rank_cnt[1]_i_3 
       (.I0(\done_cnt_reg[2]_0 ),
        .I1(done_cnt[3]),
        .I2(done_cnt[1]),
        .I3(done_cnt[0]),
        .I4(done_cnt[2]),
        .O(\regl_rank_cnt[1]_i_3_n_0 ));
  FDRE \regl_rank_cnt_reg[0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\regl_rank_cnt[0]_i_1_n_0 ),
        .Q(regl_rank_cnt[0]),
        .R(1'b0));
  FDRE \regl_rank_cnt_reg[1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\regl_rank_cnt[1]_i_1_n_0 ),
        .Q(regl_rank_cnt[1]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair232" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \right_edge_taps_r[0]_i_1 
       (.I0(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .I1(store_sr_req_pulsed_r),
        .O(right_edge_taps_r[0]));
  (* SOFT_HLUTNM = "soft_lutpair232" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \right_edge_taps_r[1]_i_1 
       (.I0(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .I1(store_sr_req_pulsed_r),
        .O(right_edge_taps_r[1]));
  (* SOFT_HLUTNM = "soft_lutpair231" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \right_edge_taps_r[2]_i_1 
       (.I0(\tap_cnt_cpt_r_reg_n_0_[2] ),
        .I1(store_sr_req_pulsed_r),
        .O(right_edge_taps_r[2]));
  (* SOFT_HLUTNM = "soft_lutpair208" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \right_edge_taps_r[3]_i_1 
       (.I0(\tap_cnt_cpt_r_reg_n_0_[3] ),
        .I1(store_sr_req_pulsed_r),
        .O(right_edge_taps_r[3]));
  (* SOFT_HLUTNM = "soft_lutpair231" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \right_edge_taps_r[4]_i_1 
       (.I0(\tap_cnt_cpt_r_reg_n_0_[4] ),
        .I1(store_sr_req_pulsed_r),
        .O(right_edge_taps_r[4]));
  LUT4 #(
    .INIT(16'hBAAA)) 
    \right_edge_taps_r[5]_i_1 
       (.I0(cal1_prech_req_r),
        .I1(found_first_edge_r_reg_n_0),
        .I2(found_stable_eye_last_r),
        .I3(\first_edge_taps_r[5]_i_3_n_0 ),
        .O(\right_edge_taps_r[5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair125" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \right_edge_taps_r[5]_i_2 
       (.I0(\tap_cnt_cpt_r_reg_n_0_[5] ),
        .I1(store_sr_req_pulsed_r),
        .O(right_edge_taps_r[5]));
  FDRE \right_edge_taps_r_reg[0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\right_edge_taps_r[5]_i_1_n_0 ),
        .D(right_edge_taps_r[0]),
        .Q(\right_edge_taps_r_reg_n_0_[0] ),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 [1]));
  FDRE \right_edge_taps_r_reg[1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\right_edge_taps_r[5]_i_1_n_0 ),
        .D(right_edge_taps_r[1]),
        .Q(\right_edge_taps_r_reg_n_0_[1] ),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 [1]));
  FDRE \right_edge_taps_r_reg[2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\right_edge_taps_r[5]_i_1_n_0 ),
        .D(right_edge_taps_r[2]),
        .Q(\right_edge_taps_r_reg_n_0_[2] ),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 [1]));
  FDRE \right_edge_taps_r_reg[3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\right_edge_taps_r[5]_i_1_n_0 ),
        .D(right_edge_taps_r[3]),
        .Q(\right_edge_taps_r_reg_n_0_[3] ),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 [1]));
  FDRE \right_edge_taps_r_reg[4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\right_edge_taps_r[5]_i_1_n_0 ),
        .D(right_edge_taps_r[4]),
        .Q(\right_edge_taps_r_reg_n_0_[4] ),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 [1]));
  FDRE \right_edge_taps_r_reg[5] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\right_edge_taps_r[5]_i_1_n_0 ),
        .D(right_edge_taps_r[5]),
        .Q(\right_edge_taps_r_reg_n_0_[5] ),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 [1]));
  LUT6 #(
    .INIT(64'h03A8038833883388)) 
    \rnk_cnt_r[0]_i_1__0 
       (.I0(cal1_prech_req_r),
        .I1(p_0_in541_in),
        .I2(\rnk_cnt_r[1]_i_2_n_0 ),
        .I3(\rnk_cnt_r_reg_n_0_[0] ),
        .I4(\rnk_cnt_r_reg_n_0_[1] ),
        .I5(prech_done),
        .O(\rnk_cnt_r[0]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h03ABA80033BB8800)) 
    \rnk_cnt_r[1]_i_1__0 
       (.I0(cal1_prech_req_r),
        .I1(p_0_in541_in),
        .I2(\rnk_cnt_r[1]_i_2_n_0 ),
        .I3(\rnk_cnt_r_reg_n_0_[0] ),
        .I4(\rnk_cnt_r_reg_n_0_[1] ),
        .I5(prech_done),
        .O(\rnk_cnt_r[1]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair121" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \rnk_cnt_r[1]_i_2 
       (.I0(\cal1_cnt_cpt_r_reg_n_0_[2] ),
        .I1(\cal1_cnt_cpt_r_reg_n_0_[0] ),
        .I2(\cal1_cnt_cpt_r_reg_n_0_[1] ),
        .I3(cal1_prech_req_r),
        .O(\rnk_cnt_r[1]_i_2_n_0 ));
  FDRE \rnk_cnt_r_reg[0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\rnk_cnt_r[0]_i_1__0_n_0 ),
        .Q(\rnk_cnt_r_reg_n_0_[0] ),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 [1]));
  FDRE \rnk_cnt_r_reg[1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(\rnk_cnt_r[1]_i_1__0_n_0 ),
        .Q(\rnk_cnt_r_reg_n_0_[1] ),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 [1]));
  LUT6 #(
    .INIT(64'h00000000AAAE0000)) 
    samp_cnt_done_r_i_1
       (.I0(samp_cnt_done_r_reg_n_0),
        .I1(samp_cnt_done_r_i_2_n_0),
        .I2(samp_cnt_done_r_i_3_n_0),
        .I3(samp_cnt_done_r_i_4_n_0),
        .I4(samp_edge_cnt0_en_r),
        .I5(\done_cnt_reg[2]_0 ),
        .O(samp_cnt_done_r_i_1_n_0));
  LUT4 #(
    .INIT(16'h0010)) 
    samp_cnt_done_r_i_2
       (.I0(samp_edge_cnt1_r_reg[11]),
        .I1(samp_edge_cnt1_r_reg[7]),
        .I2(samp_edge_cnt1_r_reg[0]),
        .I3(samp_edge_cnt1_r_reg[6]),
        .O(samp_cnt_done_r_i_2_n_0));
  LUT4 #(
    .INIT(16'hFFFE)) 
    samp_cnt_done_r_i_3
       (.I0(samp_edge_cnt1_r_reg[1]),
        .I1(samp_edge_cnt1_r_reg[10]),
        .I2(samp_edge_cnt1_r_reg[8]),
        .I3(samp_edge_cnt1_r_reg[3]),
        .O(samp_cnt_done_r_i_3_n_0));
  LUT4 #(
    .INIT(16'hFFFE)) 
    samp_cnt_done_r_i_4
       (.I0(samp_edge_cnt1_r_reg[4]),
        .I1(samp_edge_cnt1_r_reg[9]),
        .I2(samp_edge_cnt1_r_reg[2]),
        .I3(samp_edge_cnt1_r_reg[5]),
        .O(samp_cnt_done_r_i_4_n_0));
  FDRE samp_cnt_done_r_reg
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(samp_cnt_done_r_i_1_n_0),
        .Q(samp_cnt_done_r_reg_n_0),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair124" *) 
  LUT2 #(
    .INIT(4'hE)) 
    samp_edge_cnt0_en_r_i_1
       (.I0(store_sr_req_pulsed_r),
        .I1(p_34_in),
        .O(pb_detect_edge));
  FDRE samp_edge_cnt0_en_r_reg
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(pb_detect_edge),
        .Q(samp_edge_cnt0_en_r),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \samp_edge_cnt0_r[0]_i_3 
       (.I0(samp_edge_cnt0_r_reg[0]),
        .O(\samp_edge_cnt0_r[0]_i_3_n_0 ));
  FDRE \samp_edge_cnt0_r_reg[0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r2),
        .D(\samp_edge_cnt0_r_reg[0]_i_2_n_7 ),
        .Q(samp_edge_cnt0_r_reg[0]),
        .R(\samp_edge_cnt1_r_reg[0]_0 ));
  CARRY4 \samp_edge_cnt0_r_reg[0]_i_2 
       (.CI(1'b0),
        .CO({\samp_edge_cnt0_r_reg[0]_i_2_n_0 ,\samp_edge_cnt0_r_reg[0]_i_2_n_1 ,\samp_edge_cnt0_r_reg[0]_i_2_n_2 ,\samp_edge_cnt0_r_reg[0]_i_2_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b1}),
        .O({\samp_edge_cnt0_r_reg[0]_i_2_n_4 ,\samp_edge_cnt0_r_reg[0]_i_2_n_5 ,\samp_edge_cnt0_r_reg[0]_i_2_n_6 ,\samp_edge_cnt0_r_reg[0]_i_2_n_7 }),
        .S({samp_edge_cnt0_r_reg[3:1],\samp_edge_cnt0_r[0]_i_3_n_0 }));
  FDRE \samp_edge_cnt0_r_reg[10] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r2),
        .D(\samp_edge_cnt0_r_reg[8]_i_1_n_5 ),
        .Q(samp_edge_cnt0_r_reg[10]),
        .R(\samp_edge_cnt1_r_reg[0]_0 ));
  FDRE \samp_edge_cnt0_r_reg[11] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r2),
        .D(\samp_edge_cnt0_r_reg[8]_i_1_n_4 ),
        .Q(samp_edge_cnt0_r_reg[11]),
        .R(\samp_edge_cnt1_r_reg[0]_0 ));
  FDRE \samp_edge_cnt0_r_reg[1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r2),
        .D(\samp_edge_cnt0_r_reg[0]_i_2_n_6 ),
        .Q(samp_edge_cnt0_r_reg[1]),
        .R(\samp_edge_cnt1_r_reg[0]_0 ));
  FDRE \samp_edge_cnt0_r_reg[2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r2),
        .D(\samp_edge_cnt0_r_reg[0]_i_2_n_5 ),
        .Q(samp_edge_cnt0_r_reg[2]),
        .R(\samp_edge_cnt1_r_reg[0]_0 ));
  FDRE \samp_edge_cnt0_r_reg[3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r2),
        .D(\samp_edge_cnt0_r_reg[0]_i_2_n_4 ),
        .Q(samp_edge_cnt0_r_reg[3]),
        .R(\samp_edge_cnt1_r_reg[0]_0 ));
  FDRE \samp_edge_cnt0_r_reg[4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r2),
        .D(\samp_edge_cnt0_r_reg[4]_i_1_n_7 ),
        .Q(samp_edge_cnt0_r_reg[4]),
        .R(\samp_edge_cnt1_r_reg[0]_0 ));
  CARRY4 \samp_edge_cnt0_r_reg[4]_i_1 
       (.CI(\samp_edge_cnt0_r_reg[0]_i_2_n_0 ),
        .CO({\samp_edge_cnt0_r_reg[4]_i_1_n_0 ,\samp_edge_cnt0_r_reg[4]_i_1_n_1 ,\samp_edge_cnt0_r_reg[4]_i_1_n_2 ,\samp_edge_cnt0_r_reg[4]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\samp_edge_cnt0_r_reg[4]_i_1_n_4 ,\samp_edge_cnt0_r_reg[4]_i_1_n_5 ,\samp_edge_cnt0_r_reg[4]_i_1_n_6 ,\samp_edge_cnt0_r_reg[4]_i_1_n_7 }),
        .S(samp_edge_cnt0_r_reg[7:4]));
  FDRE \samp_edge_cnt0_r_reg[5] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r2),
        .D(\samp_edge_cnt0_r_reg[4]_i_1_n_6 ),
        .Q(samp_edge_cnt0_r_reg[5]),
        .R(\samp_edge_cnt1_r_reg[0]_0 ));
  FDRE \samp_edge_cnt0_r_reg[6] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r2),
        .D(\samp_edge_cnt0_r_reg[4]_i_1_n_5 ),
        .Q(samp_edge_cnt0_r_reg[6]),
        .R(\samp_edge_cnt1_r_reg[0]_0 ));
  FDRE \samp_edge_cnt0_r_reg[7] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r2),
        .D(\samp_edge_cnt0_r_reg[4]_i_1_n_4 ),
        .Q(samp_edge_cnt0_r_reg[7]),
        .R(\samp_edge_cnt1_r_reg[0]_0 ));
  FDRE \samp_edge_cnt0_r_reg[8] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r2),
        .D(\samp_edge_cnt0_r_reg[8]_i_1_n_7 ),
        .Q(samp_edge_cnt0_r_reg[8]),
        .R(\samp_edge_cnt1_r_reg[0]_0 ));
  CARRY4 \samp_edge_cnt0_r_reg[8]_i_1 
       (.CI(\samp_edge_cnt0_r_reg[4]_i_1_n_0 ),
        .CO({\NLW_samp_edge_cnt0_r_reg[8]_i_1_CO_UNCONNECTED [3],\samp_edge_cnt0_r_reg[8]_i_1_n_1 ,\samp_edge_cnt0_r_reg[8]_i_1_n_2 ,\samp_edge_cnt0_r_reg[8]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\samp_edge_cnt0_r_reg[8]_i_1_n_4 ,\samp_edge_cnt0_r_reg[8]_i_1_n_5 ,\samp_edge_cnt0_r_reg[8]_i_1_n_6 ,\samp_edge_cnt0_r_reg[8]_i_1_n_7 }),
        .S(samp_edge_cnt0_r_reg[11:8]));
  FDRE \samp_edge_cnt0_r_reg[9] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(sr_valid_r2),
        .D(\samp_edge_cnt0_r_reg[8]_i_1_n_6 ),
        .Q(samp_edge_cnt0_r_reg[9]),
        .R(\samp_edge_cnt1_r_reg[0]_0 ));
  LUT5 #(
    .INIT(32'h00000200)) 
    samp_edge_cnt1_en_r_i_1
       (.I0(samp_edge_cnt1_en_r_i_2_n_0),
        .I1(samp_edge_cnt1_en_r_i_3_n_0),
        .I2(samp_edge_cnt0_r_reg[2]),
        .I3(samp_edge_cnt0_r_reg[0]),
        .I4(samp_edge_cnt0_r_reg[5]),
        .O(samp_edge_cnt1_en_r0));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    samp_edge_cnt1_en_r_i_2
       (.I0(samp_edge_cnt0_r_reg[10]),
        .I1(samp_edge_cnt0_r_reg[4]),
        .I2(samp_edge_cnt0_r_reg[9]),
        .I3(samp_edge_cnt0_r_reg[7]),
        .I4(samp_edge_cnt0_r_reg[11]),
        .I5(samp_edge_cnt0_r_reg[6]),
        .O(samp_edge_cnt1_en_r_i_2_n_0));
  LUT4 #(
    .INIT(16'hFFEF)) 
    samp_edge_cnt1_en_r_i_3
       (.I0(samp_edge_cnt0_r_reg[8]),
        .I1(samp_edge_cnt0_r_reg[3]),
        .I2(sr_valid_r2),
        .I3(samp_edge_cnt0_r_reg[1]),
        .O(samp_edge_cnt1_en_r_i_3_n_0));
  FDRE samp_edge_cnt1_en_r_reg
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(samp_edge_cnt1_en_r0),
        .Q(samp_edge_cnt1_en_r),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 [1]));
  LUT1 #(
    .INIT(2'h1)) 
    \samp_edge_cnt1_r[0]_i_2 
       (.I0(samp_edge_cnt1_r_reg[0]),
        .O(\samp_edge_cnt1_r[0]_i_2_n_0 ));
  FDRE \samp_edge_cnt1_r_reg[0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(samp_edge_cnt1_en_r),
        .D(\samp_edge_cnt1_r_reg[0]_i_1_n_7 ),
        .Q(samp_edge_cnt1_r_reg[0]),
        .R(\samp_edge_cnt1_r_reg[0]_0 ));
  CARRY4 \samp_edge_cnt1_r_reg[0]_i_1 
       (.CI(1'b0),
        .CO({\samp_edge_cnt1_r_reg[0]_i_1_n_0 ,\samp_edge_cnt1_r_reg[0]_i_1_n_1 ,\samp_edge_cnt1_r_reg[0]_i_1_n_2 ,\samp_edge_cnt1_r_reg[0]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b1}),
        .O({\samp_edge_cnt1_r_reg[0]_i_1_n_4 ,\samp_edge_cnt1_r_reg[0]_i_1_n_5 ,\samp_edge_cnt1_r_reg[0]_i_1_n_6 ,\samp_edge_cnt1_r_reg[0]_i_1_n_7 }),
        .S({samp_edge_cnt1_r_reg[3:1],\samp_edge_cnt1_r[0]_i_2_n_0 }));
  FDRE \samp_edge_cnt1_r_reg[10] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(samp_edge_cnt1_en_r),
        .D(\samp_edge_cnt1_r_reg[8]_i_1_n_5 ),
        .Q(samp_edge_cnt1_r_reg[10]),
        .R(\samp_edge_cnt1_r_reg[0]_0 ));
  FDRE \samp_edge_cnt1_r_reg[11] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(samp_edge_cnt1_en_r),
        .D(\samp_edge_cnt1_r_reg[8]_i_1_n_4 ),
        .Q(samp_edge_cnt1_r_reg[11]),
        .R(\samp_edge_cnt1_r_reg[0]_0 ));
  FDRE \samp_edge_cnt1_r_reg[1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(samp_edge_cnt1_en_r),
        .D(\samp_edge_cnt1_r_reg[0]_i_1_n_6 ),
        .Q(samp_edge_cnt1_r_reg[1]),
        .R(\samp_edge_cnt1_r_reg[0]_0 ));
  FDRE \samp_edge_cnt1_r_reg[2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(samp_edge_cnt1_en_r),
        .D(\samp_edge_cnt1_r_reg[0]_i_1_n_5 ),
        .Q(samp_edge_cnt1_r_reg[2]),
        .R(\samp_edge_cnt1_r_reg[0]_0 ));
  FDRE \samp_edge_cnt1_r_reg[3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(samp_edge_cnt1_en_r),
        .D(\samp_edge_cnt1_r_reg[0]_i_1_n_4 ),
        .Q(samp_edge_cnt1_r_reg[3]),
        .R(\samp_edge_cnt1_r_reg[0]_0 ));
  FDRE \samp_edge_cnt1_r_reg[4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(samp_edge_cnt1_en_r),
        .D(\samp_edge_cnt1_r_reg[4]_i_1_n_7 ),
        .Q(samp_edge_cnt1_r_reg[4]),
        .R(\samp_edge_cnt1_r_reg[0]_0 ));
  CARRY4 \samp_edge_cnt1_r_reg[4]_i_1 
       (.CI(\samp_edge_cnt1_r_reg[0]_i_1_n_0 ),
        .CO({\samp_edge_cnt1_r_reg[4]_i_1_n_0 ,\samp_edge_cnt1_r_reg[4]_i_1_n_1 ,\samp_edge_cnt1_r_reg[4]_i_1_n_2 ,\samp_edge_cnt1_r_reg[4]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\samp_edge_cnt1_r_reg[4]_i_1_n_4 ,\samp_edge_cnt1_r_reg[4]_i_1_n_5 ,\samp_edge_cnt1_r_reg[4]_i_1_n_6 ,\samp_edge_cnt1_r_reg[4]_i_1_n_7 }),
        .S(samp_edge_cnt1_r_reg[7:4]));
  FDRE \samp_edge_cnt1_r_reg[5] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(samp_edge_cnt1_en_r),
        .D(\samp_edge_cnt1_r_reg[4]_i_1_n_6 ),
        .Q(samp_edge_cnt1_r_reg[5]),
        .R(\samp_edge_cnt1_r_reg[0]_0 ));
  FDRE \samp_edge_cnt1_r_reg[6] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(samp_edge_cnt1_en_r),
        .D(\samp_edge_cnt1_r_reg[4]_i_1_n_5 ),
        .Q(samp_edge_cnt1_r_reg[6]),
        .R(\samp_edge_cnt1_r_reg[0]_0 ));
  FDRE \samp_edge_cnt1_r_reg[7] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(samp_edge_cnt1_en_r),
        .D(\samp_edge_cnt1_r_reg[4]_i_1_n_4 ),
        .Q(samp_edge_cnt1_r_reg[7]),
        .R(\samp_edge_cnt1_r_reg[0]_0 ));
  FDRE \samp_edge_cnt1_r_reg[8] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(samp_edge_cnt1_en_r),
        .D(\samp_edge_cnt1_r_reg[8]_i_1_n_7 ),
        .Q(samp_edge_cnt1_r_reg[8]),
        .R(\samp_edge_cnt1_r_reg[0]_0 ));
  CARRY4 \samp_edge_cnt1_r_reg[8]_i_1 
       (.CI(\samp_edge_cnt1_r_reg[4]_i_1_n_0 ),
        .CO({\NLW_samp_edge_cnt1_r_reg[8]_i_1_CO_UNCONNECTED [3],\samp_edge_cnt1_r_reg[8]_i_1_n_1 ,\samp_edge_cnt1_r_reg[8]_i_1_n_2 ,\samp_edge_cnt1_r_reg[8]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\samp_edge_cnt1_r_reg[8]_i_1_n_4 ,\samp_edge_cnt1_r_reg[8]_i_1_n_5 ,\samp_edge_cnt1_r_reg[8]_i_1_n_6 ,\samp_edge_cnt1_r_reg[8]_i_1_n_7 }),
        .S(samp_edge_cnt1_r_reg[11:8]));
  FDRE \samp_edge_cnt1_r_reg[9] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(samp_edge_cnt1_en_r),
        .D(\samp_edge_cnt1_r_reg[8]_i_1_n_6 ),
        .Q(samp_edge_cnt1_r_reg[9]),
        .R(\samp_edge_cnt1_r_reg[0]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \second_edge_taps_r[0]_i_1 
       (.I0(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .O(tap_cnt_cpt_r0));
  (* SOFT_HLUTNM = "soft_lutpair215" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \second_edge_taps_r[1]_i_1 
       (.I0(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .I1(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .O(\second_edge_taps_r[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair215" *) 
  LUT3 #(
    .INIT(8'hE1)) 
    \second_edge_taps_r[2]_i_1 
       (.I0(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .I1(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .I2(\tap_cnt_cpt_r_reg_n_0_[2] ),
        .O(\second_edge_taps_r[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair98" *) 
  LUT4 #(
    .INIT(16'hFE01)) 
    \second_edge_taps_r[3]_i_1 
       (.I0(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .I1(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .I2(\tap_cnt_cpt_r_reg_n_0_[2] ),
        .I3(\tap_cnt_cpt_r_reg_n_0_[3] ),
        .O(\second_edge_taps_r[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair98" *) 
  LUT5 #(
    .INIT(32'hFFFE0001)) 
    \second_edge_taps_r[4]_i_1 
       (.I0(\tap_cnt_cpt_r_reg_n_0_[2] ),
        .I1(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .I2(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .I3(\tap_cnt_cpt_r_reg_n_0_[3] ),
        .I4(\tap_cnt_cpt_r_reg_n_0_[4] ),
        .O(\second_edge_taps_r[4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h0000EAAA)) 
    \second_edge_taps_r[5]_i_1 
       (.I0(cal1_prech_req_r),
        .I1(\first_edge_taps_r[5]_i_3_n_0 ),
        .I2(found_first_edge_r_reg_n_0),
        .I3(found_stable_eye_last_r),
        .I4(store_sr_req_pulsed_r),
        .O(\second_edge_taps_r[5]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hEAAA)) 
    \second_edge_taps_r[5]_i_2 
       (.I0(cal1_prech_req_r),
        .I1(\first_edge_taps_r[5]_i_3_n_0 ),
        .I2(found_first_edge_r_reg_n_0),
        .I3(found_stable_eye_last_r),
        .O(\second_edge_taps_r[5]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFE00000001)) 
    \second_edge_taps_r[5]_i_3 
       (.I0(\tap_cnt_cpt_r_reg_n_0_[3] ),
        .I1(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .I2(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .I3(\tap_cnt_cpt_r_reg_n_0_[2] ),
        .I4(\tap_cnt_cpt_r_reg_n_0_[4] ),
        .I5(\tap_cnt_cpt_r_reg_n_0_[5] ),
        .O(\second_edge_taps_r[5]_i_3_n_0 ));
  FDRE \second_edge_taps_r_reg[0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\second_edge_taps_r[5]_i_2_n_0 ),
        .D(tap_cnt_cpt_r0),
        .Q(\second_edge_taps_r_reg_n_0_[0] ),
        .R(\second_edge_taps_r[5]_i_1_n_0 ));
  FDRE \second_edge_taps_r_reg[1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\second_edge_taps_r[5]_i_2_n_0 ),
        .D(\second_edge_taps_r[1]_i_1_n_0 ),
        .Q(\second_edge_taps_r_reg_n_0_[1] ),
        .R(\second_edge_taps_r[5]_i_1_n_0 ));
  FDRE \second_edge_taps_r_reg[2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\second_edge_taps_r[5]_i_2_n_0 ),
        .D(\second_edge_taps_r[2]_i_1_n_0 ),
        .Q(\second_edge_taps_r_reg_n_0_[2] ),
        .R(\second_edge_taps_r[5]_i_1_n_0 ));
  FDRE \second_edge_taps_r_reg[3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\second_edge_taps_r[5]_i_2_n_0 ),
        .D(\second_edge_taps_r[3]_i_1_n_0 ),
        .Q(\second_edge_taps_r_reg_n_0_[3] ),
        .R(\second_edge_taps_r[5]_i_1_n_0 ));
  FDRE \second_edge_taps_r_reg[4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\second_edge_taps_r[5]_i_2_n_0 ),
        .D(\second_edge_taps_r[4]_i_1_n_0 ),
        .Q(\second_edge_taps_r_reg_n_0_[4] ),
        .R(\second_edge_taps_r[5]_i_1_n_0 ));
  FDRE \second_edge_taps_r_reg[5] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(\second_edge_taps_r[5]_i_2_n_0 ),
        .D(\second_edge_taps_r[5]_i_3_n_0 ),
        .Q(\second_edge_taps_r_reg_n_0_[5] ),
        .R(\second_edge_taps_r[5]_i_1_n_0 ));
  FDRE sr_valid_r1_reg
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(sr_valid_r_reg_n_0),
        .Q(sr_valid_r1),
        .R(1'b0));
  FDRE sr_valid_r2_reg
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(sr_valid_r1),
        .Q(sr_valid_r2),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0000000000000008)) 
    sr_valid_r_i_1
       (.I0(rdlvl_stg1_start_r_reg_0),
        .I1(E),
        .I2(cnt_shift_r_reg[3]),
        .I3(cnt_shift_r_reg[2]),
        .I4(cnt_shift_r_reg[0]),
        .I5(cnt_shift_r_reg[1]),
        .O(sr_valid_r_i_1_n_0));
  FDRE sr_valid_r_reg
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(sr_valid_r_i_1_n_0),
        .Q(sr_valid_r_reg_n_0),
        .R(sr_valid_r_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair211" *) 
  LUT3 #(
    .INIT(8'h45)) 
    \stg1_wr_rd_cnt[4]_i_2 
       (.I0(\stg1_wr_rd_cnt_reg[3] ),
        .I1(rdlvl_stg1_done_int_reg_0),
        .I2(stg1_wr_done),
        .O(rdlvl_stg1_done_int_reg_1));
  LUT3 #(
    .INIT(8'hBA)) 
    store_sr_r_i_1
       (.I0(store_sr_req_r_reg_n_0),
        .I1(sr_valid_r_reg_n_0),
        .I2(store_sr_r_reg_n_0),
        .O(store_sr_r_i_1_n_0));
  FDRE store_sr_r_reg
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(store_sr_r_i_1_n_0),
        .Q(store_sr_r_reg_n_0),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 [1]));
  FDRE store_sr_req_pulsed_r_reg
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(store_sr_req_pulsed_r),
        .Q(store_sr_req_pulsed_r__0),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 [1]));
  (* SOFT_HLUTNM = "soft_lutpair102" *) 
  LUT5 #(
    .INIT(32'h44444F44)) 
    store_sr_req_r_i_1
       (.I0(store_sr_req_pulsed_r__0),
        .I1(store_sr_req_pulsed_r),
        .I2(cal1_wait_r),
        .I3(p_27_in),
        .I4(store_sr_req_r_i_2_n_0),
        .O(store_sr_req_r));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFFE)) 
    store_sr_req_r_i_2
       (.I0(D[5]),
        .I1(D[1]),
        .I2(D[2]),
        .I3(D[3]),
        .I4(D[0]),
        .I5(D[4]),
        .O(store_sr_req_r_i_2_n_0));
  FDRE store_sr_req_r_reg
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(store_sr_req_r),
        .Q(store_sr_req_r_reg_n_0),
        .R(\rdlvl_dqs_tap_cnt_r_reg[0][0][2]_0 [1]));
  (* SOFT_HLUTNM = "soft_lutpair120" *) 
  LUT3 #(
    .INIT(8'h69)) 
    \tap_cnt_cpt_r[1]_i_1 
       (.I0(cal1_dlyinc_cpt_r_reg_n_0),
        .I1(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .I2(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .O(\tap_cnt_cpt_r[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair99" *) 
  LUT4 #(
    .INIT(16'h6AA9)) 
    \tap_cnt_cpt_r[2]_i_1 
       (.I0(\tap_cnt_cpt_r_reg_n_0_[2] ),
        .I1(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .I2(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .I3(cal1_dlyinc_cpt_r_reg_n_0),
        .O(p_0_in__0[2]));
  (* SOFT_HLUTNM = "soft_lutpair99" *) 
  LUT5 #(
    .INIT(32'h6CCCCCC9)) 
    \tap_cnt_cpt_r[3]_i_1 
       (.I0(cal1_dlyinc_cpt_r_reg_n_0),
        .I1(\tap_cnt_cpt_r_reg_n_0_[3] ),
        .I2(\tap_cnt_cpt_r_reg_n_0_[2] ),
        .I3(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .I4(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .O(p_0_in__0[3]));
  LUT6 #(
    .INIT(64'h6CCCCCCCCCCCCCC9)) 
    \tap_cnt_cpt_r[4]_i_1 
       (.I0(cal1_dlyinc_cpt_r_reg_n_0),
        .I1(\tap_cnt_cpt_r_reg_n_0_[4] ),
        .I2(\tap_cnt_cpt_r_reg_n_0_[3] ),
        .I3(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .I4(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .I5(\tap_cnt_cpt_r_reg_n_0_[2] ),
        .O(p_0_in__0[4]));
  LUT4 #(
    .INIT(16'hAA8A)) 
    \tap_cnt_cpt_r[5]_i_2 
       (.I0(cal1_dlyce_cpt_r_reg_n_0),
        .I1(\tap_cnt_cpt_r_reg_n_0_[5] ),
        .I2(\tap_cnt_cpt_r[5]_i_4_n_0 ),
        .I3(cal1_dlyinc_cpt_r_reg_n_0),
        .O(tap_cnt_cpt_r));
  LUT4 #(
    .INIT(16'h1DD1)) 
    \tap_cnt_cpt_r[5]_i_3 
       (.I0(\tap_cnt_cpt_r[5]_i_5_n_0 ),
        .I1(cal1_dlyinc_cpt_r_reg_n_0),
        .I2(\tap_cnt_cpt_r_reg_n_0_[5] ),
        .I3(\tap_cnt_cpt_r[5]_i_6_n_0 ),
        .O(p_0_in__0[5]));
  (* SOFT_HLUTNM = "soft_lutpair86" *) 
  LUT5 #(
    .INIT(32'h00000001)) 
    \tap_cnt_cpt_r[5]_i_4 
       (.I0(\tap_cnt_cpt_r_reg_n_0_[3] ),
        .I1(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .I2(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .I3(\tap_cnt_cpt_r_reg_n_0_[2] ),
        .I4(\tap_cnt_cpt_r_reg_n_0_[4] ),
        .O(\tap_cnt_cpt_r[5]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h5555555555555556)) 
    \tap_cnt_cpt_r[5]_i_5 
       (.I0(\tap_cnt_cpt_r_reg_n_0_[5] ),
        .I1(\tap_cnt_cpt_r_reg_n_0_[4] ),
        .I2(\tap_cnt_cpt_r_reg_n_0_[2] ),
        .I3(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .I4(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .I5(\tap_cnt_cpt_r_reg_n_0_[3] ),
        .O(\tap_cnt_cpt_r[5]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair86" *) 
  LUT5 #(
    .INIT(32'h80000000)) 
    \tap_cnt_cpt_r[5]_i_6 
       (.I0(\tap_cnt_cpt_r_reg_n_0_[3] ),
        .I1(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .I2(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .I3(\tap_cnt_cpt_r_reg_n_0_[2] ),
        .I4(\tap_cnt_cpt_r_reg_n_0_[4] ),
        .O(\tap_cnt_cpt_r[5]_i_6_n_0 ));
  FDRE \tap_cnt_cpt_r_reg[0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(tap_cnt_cpt_r),
        .D(tap_cnt_cpt_r0),
        .Q(\tap_cnt_cpt_r_reg_n_0_[0] ),
        .R(\tap_cnt_cpt_r_reg[5]_0 ));
  FDRE \tap_cnt_cpt_r_reg[1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(tap_cnt_cpt_r),
        .D(\tap_cnt_cpt_r[1]_i_1_n_0 ),
        .Q(\tap_cnt_cpt_r_reg_n_0_[1] ),
        .R(\tap_cnt_cpt_r_reg[5]_0 ));
  FDRE \tap_cnt_cpt_r_reg[2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(tap_cnt_cpt_r),
        .D(p_0_in__0[2]),
        .Q(\tap_cnt_cpt_r_reg_n_0_[2] ),
        .R(\tap_cnt_cpt_r_reg[5]_0 ));
  FDRE \tap_cnt_cpt_r_reg[3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(tap_cnt_cpt_r),
        .D(p_0_in__0[3]),
        .Q(\tap_cnt_cpt_r_reg_n_0_[3] ),
        .R(\tap_cnt_cpt_r_reg[5]_0 ));
  FDRE \tap_cnt_cpt_r_reg[4] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(tap_cnt_cpt_r),
        .D(p_0_in__0[4]),
        .Q(\tap_cnt_cpt_r_reg_n_0_[4] ),
        .R(\tap_cnt_cpt_r_reg[5]_0 ));
  FDRE \tap_cnt_cpt_r_reg[5] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(tap_cnt_cpt_r),
        .D(p_0_in__0[5]),
        .Q(\tap_cnt_cpt_r_reg_n_0_[5] ),
        .R(\tap_cnt_cpt_r_reg[5]_0 ));
  LUT6 #(
    .INIT(64'h000000000000AA80)) 
    tap_limit_cpt_r_i_1
       (.I0(tap_limit_cpt_r_i_2_n_0),
        .I1(\tap_cnt_cpt_r_reg_n_0_[5] ),
        .I2(\tap_cnt_cpt_r[5]_i_6_n_0 ),
        .I3(tap_limit_cpt_r),
        .I4(\done_cnt_reg[2]_0 ),
        .I5(new_cnt_cpt_r_reg_0),
        .O(tap_limit_cpt_r_i_1_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFEFF)) 
    tap_limit_cpt_r_i_2
       (.I0(\cal1_state_r1_reg_n_0_[4] ),
        .I1(\cal1_state_r1_reg_n_0_[5] ),
        .I2(\cal1_state_r1_reg_n_0_[0] ),
        .I3(\cal1_state_r1_reg_n_0_[2] ),
        .I4(\cal1_state_r1_reg_n_0_[1] ),
        .I5(\cal1_state_r1_reg_n_0_[3] ),
        .O(tap_limit_cpt_r_i_2_n_0));
  FDRE tap_limit_cpt_r_reg
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(1'b1),
        .D(tap_limit_cpt_r_i_1_n_0),
        .Q(tap_limit_cpt_r),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \wait_cnt_r[0]_i_1__0 
       (.I0(wait_cnt_r_reg[0]),
        .O(wait_cnt_r0__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair221" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \wait_cnt_r[1]_i_1__0 
       (.I0(wait_cnt_r_reg[1]),
        .I1(wait_cnt_r_reg[0]),
        .O(\wait_cnt_r[1]_i_1__0_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair221" *) 
  LUT3 #(
    .INIT(8'hA9)) 
    \wait_cnt_r[2]_i_1 
       (.I0(wait_cnt_r_reg[2]),
        .I1(wait_cnt_r_reg[0]),
        .I2(wait_cnt_r_reg[1]),
        .O(wait_cnt_r0__0[2]));
  LUT5 #(
    .INIT(32'hAAAAAAA8)) 
    \wait_cnt_r[3]_i_2__0 
       (.I0(dqs_po_dec_done_r2),
        .I1(wait_cnt_r_reg[2]),
        .I2(wait_cnt_r_reg[3]),
        .I3(wait_cnt_r_reg[1]),
        .I4(wait_cnt_r_reg[0]),
        .O(wait_cnt_r0));
  (* SOFT_HLUTNM = "soft_lutpair122" *) 
  LUT4 #(
    .INIT(16'hAAA9)) 
    \wait_cnt_r[3]_i_3 
       (.I0(wait_cnt_r_reg[3]),
        .I1(wait_cnt_r_reg[2]),
        .I2(wait_cnt_r_reg[1]),
        .I3(wait_cnt_r_reg[0]),
        .O(wait_cnt_r0__0[3]));
  FDRE \wait_cnt_r_reg[0] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(wait_cnt_r0),
        .D(wait_cnt_r0__0[0]),
        .Q(wait_cnt_r_reg[0]),
        .R(\wait_cnt_r_reg[0]_0 ));
  FDRE \wait_cnt_r_reg[1] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(wait_cnt_r0),
        .D(\wait_cnt_r[1]_i_1__0_n_0 ),
        .Q(wait_cnt_r_reg[1]),
        .R(\wait_cnt_r_reg[0]_0 ));
  FDRE \wait_cnt_r_reg[2] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(wait_cnt_r0),
        .D(wait_cnt_r0__0[2]),
        .Q(wait_cnt_r_reg[2]),
        .R(\wait_cnt_r_reg[0]_0 ));
  FDSE \wait_cnt_r_reg[3] 
       (.C(rdlvl_pi_incdec_reg_0),
        .CE(wait_cnt_r0),
        .D(wait_cnt_r0__0[3]),
        .Q(wait_cnt_r_reg[3]),
        .S(\wait_cnt_r_reg[0]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair211" *) 
  LUT3 #(
    .INIT(8'h7F)) 
    \wrdq_div1_4to1_wrcal_first.phy_wrdata[510]_i_1 
       (.I0(rdlvl_stg1_done_int_reg_0),
        .I1(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56] ),
        .I2(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[56]_0 ),
        .O(rdlvl_stg1_done_int_reg_2));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_phy_tempmon" *) 
module mig_mig_7series_v4_2_ddr_phy_tempmon
   (tempmon_pi_f_inc,
    tempmon_sel_pi_incdec,
    D,
    pi_f_inc_reg_0,
    rdlvl_stg1_done_int_reg,
    calib_in_common4_out,
    pi_f_dec_reg_0,
    \four_dec_min_limit_reg[0]_0 ,
    mc_ref_zq_wip,
    pi_f_dec_reg_1,
    \neutral_max_limit_reg[11]_0 ,
    \one_dec_min_limit_reg[11]_0 ,
    \device_temp_101_reg[0]_0 ,
    \one_dec_max_limit_reg[2]_0 ,
    calib_in_common,
    calib_sel1__1,
    cmd_delay_start0,
    \calib_zero_inputs_reg[2] ,
    dqs_po_dec_done,
    pi_fine_dly_dec_done,
    Q,
    \gen_byte_sel_div2.calib_in_common_i_2 ,
    \gen_byte_sel_div2.calib_in_common_i_3 ,
    \gen_byte_sel_div2.calib_in_common_i_2_0 ,
    \gen_byte_sel_div2.calib_in_common_i_2_1 ,
    \calib_sel_reg[0] ,
    calib_complete,
    \device_temp_101_reg[11]_0 );
  output tempmon_pi_f_inc;
  output tempmon_sel_pi_incdec;
  output [2:0]D;
  output pi_f_inc_reg_0;
  output rdlvl_stg1_done_int_reg;
  output calib_in_common4_out;
  input pi_f_dec_reg_0;
  input \four_dec_min_limit_reg[0]_0 ;
  input mc_ref_zq_wip;
  input [0:0]pi_f_dec_reg_1;
  input \neutral_max_limit_reg[11]_0 ;
  input \one_dec_min_limit_reg[11]_0 ;
  input \device_temp_101_reg[0]_0 ;
  input \one_dec_max_limit_reg[2]_0 ;
  input calib_in_common;
  input calib_sel1__1;
  input cmd_delay_start0;
  input \calib_zero_inputs_reg[2] ;
  input dqs_po_dec_done;
  input pi_fine_dly_dec_done;
  input [1:0]Q;
  input \gen_byte_sel_div2.calib_in_common_i_2 ;
  input \gen_byte_sel_div2.calib_in_common_i_3 ;
  input \gen_byte_sel_div2.calib_in_common_i_2_0 ;
  input \gen_byte_sel_div2.calib_in_common_i_2_1 ;
  input \calib_sel_reg[0] ;
  input calib_complete;
  input [11:0]\device_temp_101_reg[11]_0 ;

  wire [2:0]D;
  wire [1:0]Q;
  wire calib_complete;
  wire calib_in_common;
  wire calib_in_common4_out;
  wire calib_sel1__1;
  wire \calib_sel_reg[0] ;
  wire \calib_zero_inputs[0]_i_2_n_0 ;
  wire \calib_zero_inputs[2]_i_2_n_0 ;
  wire \calib_zero_inputs_reg[2] ;
  wire cmd_delay_start0;
  wire [11:0]device_temp_101;
  wire \device_temp_101_reg[0]_0 ;
  wire [11:0]\device_temp_101_reg[11]_0 ;
  wire [11:0]device_temp_init;
  wire \device_temp_init[11]_i_2_n_0 ;
  wire \device_temp_init[11]_i_3_n_0 ;
  wire dqs_po_dec_done;
  wire [11:0]four_dec_min_limit;
  wire \four_dec_min_limit[11]_i_2_n_0 ;
  wire \four_dec_min_limit[11]_i_3_n_0 ;
  wire \four_dec_min_limit[5]_i_2_n_0 ;
  wire \four_dec_min_limit[5]_i_3_n_0 ;
  wire \four_dec_min_limit[5]_i_4_n_0 ;
  wire \four_dec_min_limit[9]_i_2_n_0 ;
  wire \four_dec_min_limit[9]_i_3_n_0 ;
  wire \four_dec_min_limit[9]_i_4_n_0 ;
  wire \four_dec_min_limit[9]_i_5_n_0 ;
  wire [11:2]four_dec_min_limit_nxt;
  wire \four_dec_min_limit_reg[0]_0 ;
  wire \four_dec_min_limit_reg[11]_i_1_n_3 ;
  wire \four_dec_min_limit_reg[5]_i_1_n_0 ;
  wire \four_dec_min_limit_reg[5]_i_1_n_1 ;
  wire \four_dec_min_limit_reg[5]_i_1_n_2 ;
  wire \four_dec_min_limit_reg[5]_i_1_n_3 ;
  wire \four_dec_min_limit_reg[9]_i_1_n_0 ;
  wire \four_dec_min_limit_reg[9]_i_1_n_1 ;
  wire \four_dec_min_limit_reg[9]_i_1_n_2 ;
  wire \four_dec_min_limit_reg[9]_i_1_n_3 ;
  wire [11:2]four_inc_max_limit;
  wire \four_inc_max_limit[11]_i_2_n_0 ;
  wire \four_inc_max_limit[11]_i_3_n_0 ;
  wire \four_inc_max_limit[4]_i_2_n_0 ;
  wire \four_inc_max_limit[4]_i_3_n_0 ;
  wire \four_inc_max_limit[4]_i_4_n_0 ;
  wire \four_inc_max_limit[4]_i_5_n_0 ;
  wire \four_inc_max_limit[8]_i_2_n_0 ;
  wire \four_inc_max_limit[8]_i_3_n_0 ;
  wire [11:2]four_inc_max_limit_nxt;
  wire \four_inc_max_limit_reg[11]_i_1_n_2 ;
  wire \four_inc_max_limit_reg[11]_i_1_n_3 ;
  wire \four_inc_max_limit_reg[4]_i_1_n_0 ;
  wire \four_inc_max_limit_reg[4]_i_1_n_1 ;
  wire \four_inc_max_limit_reg[4]_i_1_n_2 ;
  wire \four_inc_max_limit_reg[4]_i_1_n_3 ;
  wire \four_inc_max_limit_reg[8]_i_1_n_0 ;
  wire \four_inc_max_limit_reg[8]_i_1_n_1 ;
  wire \four_inc_max_limit_reg[8]_i_1_n_2 ;
  wire \four_inc_max_limit_reg[8]_i_1_n_3 ;
  wire \gen_byte_sel_div2.calib_in_common_i_2 ;
  wire \gen_byte_sel_div2.calib_in_common_i_2_0 ;
  wire \gen_byte_sel_div2.calib_in_common_i_2_1 ;
  wire \gen_byte_sel_div2.calib_in_common_i_3 ;
  wire mc_ref_zq_wip;
  wire [11:2]neutral_max_limit;
  wire \neutral_max_limit[4]_i_2_n_0 ;
  wire \neutral_max_limit[4]_i_3_n_0 ;
  wire \neutral_max_limit[4]_i_4_n_0 ;
  wire \neutral_max_limit[8]_i_2_n_0 ;
  wire \neutral_max_limit[8]_i_3_n_0 ;
  wire [11:2]neutral_max_limit_nxt;
  wire \neutral_max_limit_reg[11]_0 ;
  wire \neutral_max_limit_reg[11]_i_1_n_2 ;
  wire \neutral_max_limit_reg[11]_i_1_n_3 ;
  wire \neutral_max_limit_reg[4]_i_1_n_0 ;
  wire \neutral_max_limit_reg[4]_i_1_n_1 ;
  wire \neutral_max_limit_reg[4]_i_1_n_2 ;
  wire \neutral_max_limit_reg[4]_i_1_n_3 ;
  wire \neutral_max_limit_reg[8]_i_1_n_0 ;
  wire \neutral_max_limit_reg[8]_i_1_n_1 ;
  wire \neutral_max_limit_reg[8]_i_1_n_2 ;
  wire \neutral_max_limit_reg[8]_i_1_n_3 ;
  wire [11:2]neutral_min_limit;
  wire \neutral_min_limit[11]_i_2_n_0 ;
  wire \neutral_min_limit[11]_i_3_n_0 ;
  wire \neutral_min_limit[5]_i_2_n_0 ;
  wire \neutral_min_limit[5]_i_3_n_0 ;
  wire \neutral_min_limit[5]_i_4_n_0 ;
  wire \neutral_min_limit[9]_i_2_n_0 ;
  wire \neutral_min_limit[9]_i_3_n_0 ;
  wire \neutral_min_limit[9]_i_4_n_0 ;
  wire \neutral_min_limit[9]_i_5_n_0 ;
  wire [11:2]neutral_min_limit_nxt;
  wire \neutral_min_limit_reg[11]_i_1_n_3 ;
  wire \neutral_min_limit_reg[5]_i_1_n_0 ;
  wire \neutral_min_limit_reg[5]_i_1_n_1 ;
  wire \neutral_min_limit_reg[5]_i_1_n_2 ;
  wire \neutral_min_limit_reg[5]_i_1_n_3 ;
  wire \neutral_min_limit_reg[9]_i_1_n_0 ;
  wire \neutral_min_limit_reg[9]_i_1_n_1 ;
  wire \neutral_min_limit_reg[9]_i_1_n_2 ;
  wire \neutral_min_limit_reg[9]_i_1_n_3 ;
  wire [11:2]one_dec_max_limit;
  wire \one_dec_max_limit[4]_i_2_n_0 ;
  wire \one_dec_max_limit[8]_i_2_n_0 ;
  wire \one_dec_max_limit[8]_i_3_n_0 ;
  wire \one_dec_max_limit[8]_i_4_n_0 ;
  wire [11:2]one_dec_max_limit_nxt;
  wire \one_dec_max_limit_reg[11]_i_1_n_2 ;
  wire \one_dec_max_limit_reg[11]_i_1_n_3 ;
  wire \one_dec_max_limit_reg[2]_0 ;
  wire \one_dec_max_limit_reg[4]_i_1_n_0 ;
  wire \one_dec_max_limit_reg[4]_i_1_n_1 ;
  wire \one_dec_max_limit_reg[4]_i_1_n_2 ;
  wire \one_dec_max_limit_reg[4]_i_1_n_3 ;
  wire \one_dec_max_limit_reg[8]_i_1_n_0 ;
  wire \one_dec_max_limit_reg[8]_i_1_n_1 ;
  wire \one_dec_max_limit_reg[8]_i_1_n_2 ;
  wire \one_dec_max_limit_reg[8]_i_1_n_3 ;
  wire [11:2]one_dec_min_limit;
  wire \one_dec_min_limit[11]_i_2_n_0 ;
  wire \one_dec_min_limit[11]_i_3_n_0 ;
  wire \one_dec_min_limit[5]_i_2_n_0 ;
  wire \one_dec_min_limit[5]_i_3_n_0 ;
  wire \one_dec_min_limit[5]_i_4_n_0 ;
  wire \one_dec_min_limit[9]_i_2_n_0 ;
  wire \one_dec_min_limit[9]_i_3_n_0 ;
  wire \one_dec_min_limit[9]_i_4_n_0 ;
  wire \one_dec_min_limit[9]_i_5_n_0 ;
  wire [11:2]one_dec_min_limit_nxt;
  wire \one_dec_min_limit_reg[11]_0 ;
  wire \one_dec_min_limit_reg[11]_i_1_n_3 ;
  wire \one_dec_min_limit_reg[5]_i_1_n_0 ;
  wire \one_dec_min_limit_reg[5]_i_1_n_1 ;
  wire \one_dec_min_limit_reg[5]_i_1_n_2 ;
  wire \one_dec_min_limit_reg[5]_i_1_n_3 ;
  wire \one_dec_min_limit_reg[9]_i_1_n_0 ;
  wire \one_dec_min_limit_reg[9]_i_1_n_1 ;
  wire \one_dec_min_limit_reg[9]_i_1_n_2 ;
  wire \one_dec_min_limit_reg[9]_i_1_n_3 ;
  wire [11:1]one_inc_max_limit;
  wire \one_inc_max_limit[11]_i_2_n_0 ;
  wire \one_inc_max_limit[11]_i_3_n_0 ;
  wire \one_inc_max_limit[11]_i_4_n_0 ;
  wire \one_inc_max_limit[4]_i_2_n_0 ;
  wire \one_inc_max_limit[8]_i_2_n_0 ;
  wire \one_inc_max_limit[8]_i_3_n_0 ;
  wire [11:1]one_inc_max_limit_nxt;
  wire \one_inc_max_limit_reg[11]_i_1_n_2 ;
  wire \one_inc_max_limit_reg[11]_i_1_n_3 ;
  wire \one_inc_max_limit_reg[4]_i_1_n_0 ;
  wire \one_inc_max_limit_reg[4]_i_1_n_1 ;
  wire \one_inc_max_limit_reg[4]_i_1_n_2 ;
  wire \one_inc_max_limit_reg[4]_i_1_n_3 ;
  wire \one_inc_max_limit_reg[8]_i_1_n_0 ;
  wire \one_inc_max_limit_reg[8]_i_1_n_1 ;
  wire \one_inc_max_limit_reg[8]_i_1_n_2 ;
  wire \one_inc_max_limit_reg[8]_i_1_n_3 ;
  wire [11:1]one_inc_min_limit;
  wire \one_inc_min_limit[11]_i_2_n_0 ;
  wire \one_inc_min_limit[11]_i_3_n_0 ;
  wire \one_inc_min_limit[5]_i_2_n_0 ;
  wire \one_inc_min_limit[5]_i_3_n_0 ;
  wire \one_inc_min_limit[5]_i_4_n_0 ;
  wire \one_inc_min_limit[9]_i_2_n_0 ;
  wire \one_inc_min_limit[9]_i_3_n_0 ;
  wire \one_inc_min_limit[9]_i_4_n_0 ;
  wire \one_inc_min_limit[9]_i_5_n_0 ;
  wire [11:2]one_inc_min_limit_nxt;
  wire \one_inc_min_limit_reg[11]_i_1_n_3 ;
  wire \one_inc_min_limit_reg[5]_i_1_n_0 ;
  wire \one_inc_min_limit_reg[5]_i_1_n_1 ;
  wire \one_inc_min_limit_reg[5]_i_1_n_2 ;
  wire \one_inc_min_limit_reg[5]_i_1_n_3 ;
  wire \one_inc_min_limit_reg[9]_i_1_n_0 ;
  wire \one_inc_min_limit_reg[9]_i_1_n_1 ;
  wire \one_inc_min_limit_reg[9]_i_1_n_2 ;
  wire \one_inc_min_limit_reg[9]_i_1_n_3 ;
  wire p_0_in;
  wire pi_f_dec_i_2_n_0;
  wire pi_f_dec_nxt;
  wire pi_f_dec_reg_0;
  wire [0:0]pi_f_dec_reg_1;
  wire pi_f_inc_i_2_n_0;
  wire pi_f_inc_i_3_n_0;
  wire pi_f_inc_i_4_n_0;
  wire pi_f_inc_i_5_n_0;
  wire pi_f_inc_i_6_n_0;
  wire pi_f_inc_i_7_n_0;
  wire pi_f_inc_nxt;
  wire pi_f_inc_reg_0;
  wire pi_fine_dly_dec_done;
  wire rdlvl_stg1_done_int_reg;
  wire temp_cmp_four_dec_min_101;
  wire temp_cmp_four_dec_min_102;
  wire temp_cmp_four_dec_min_102_i_10_n_0;
  wire temp_cmp_four_dec_min_102_i_11_n_0;
  wire temp_cmp_four_dec_min_102_i_12_n_0;
  wire temp_cmp_four_dec_min_102_i_13_n_0;
  wire temp_cmp_four_dec_min_102_i_14_n_0;
  wire temp_cmp_four_dec_min_102_i_3_n_0;
  wire temp_cmp_four_dec_min_102_i_4_n_0;
  wire temp_cmp_four_dec_min_102_i_5_n_0;
  wire temp_cmp_four_dec_min_102_i_6_n_0;
  wire temp_cmp_four_dec_min_102_i_7_n_0;
  wire temp_cmp_four_dec_min_102_i_8_n_0;
  wire temp_cmp_four_dec_min_102_i_9_n_0;
  wire temp_cmp_four_dec_min_102_reg_i_1_n_3;
  wire temp_cmp_four_dec_min_102_reg_i_2_n_0;
  wire temp_cmp_four_dec_min_102_reg_i_2_n_1;
  wire temp_cmp_four_dec_min_102_reg_i_2_n_2;
  wire temp_cmp_four_dec_min_102_reg_i_2_n_3;
  wire temp_cmp_four_inc_max_101;
  wire temp_cmp_four_inc_max_102;
  wire temp_cmp_four_inc_max_102_i_10_n_0;
  wire temp_cmp_four_inc_max_102_i_11_n_0;
  wire temp_cmp_four_inc_max_102_i_12_n_0;
  wire temp_cmp_four_inc_max_102_i_13_n_0;
  wire temp_cmp_four_inc_max_102_i_14_n_0;
  wire temp_cmp_four_inc_max_102_i_3_n_0;
  wire temp_cmp_four_inc_max_102_i_4_n_0;
  wire temp_cmp_four_inc_max_102_i_5_n_0;
  wire temp_cmp_four_inc_max_102_i_6_n_0;
  wire temp_cmp_four_inc_max_102_i_7_n_0;
  wire temp_cmp_four_inc_max_102_i_8_n_0;
  wire temp_cmp_four_inc_max_102_i_9_n_0;
  wire temp_cmp_four_inc_max_102_reg_i_1_n_3;
  wire temp_cmp_four_inc_max_102_reg_i_2_n_0;
  wire temp_cmp_four_inc_max_102_reg_i_2_n_1;
  wire temp_cmp_four_inc_max_102_reg_i_2_n_2;
  wire temp_cmp_four_inc_max_102_reg_i_2_n_3;
  wire temp_cmp_neutral_max_101;
  wire temp_cmp_neutral_max_102;
  wire temp_cmp_neutral_max_102_i_10_n_0;
  wire temp_cmp_neutral_max_102_i_11_n_0;
  wire temp_cmp_neutral_max_102_i_12_n_0;
  wire temp_cmp_neutral_max_102_i_13_n_0;
  wire temp_cmp_neutral_max_102_i_14_n_0;
  wire temp_cmp_neutral_max_102_i_3_n_0;
  wire temp_cmp_neutral_max_102_i_4_n_0;
  wire temp_cmp_neutral_max_102_i_5_n_0;
  wire temp_cmp_neutral_max_102_i_6_n_0;
  wire temp_cmp_neutral_max_102_i_7_n_0;
  wire temp_cmp_neutral_max_102_i_8_n_0;
  wire temp_cmp_neutral_max_102_i_9_n_0;
  wire temp_cmp_neutral_max_102_reg_i_1_n_3;
  wire temp_cmp_neutral_max_102_reg_i_2_n_0;
  wire temp_cmp_neutral_max_102_reg_i_2_n_1;
  wire temp_cmp_neutral_max_102_reg_i_2_n_2;
  wire temp_cmp_neutral_max_102_reg_i_2_n_3;
  wire temp_cmp_neutral_min_101;
  wire temp_cmp_neutral_min_102;
  wire temp_cmp_neutral_min_102_i_10_n_0;
  wire temp_cmp_neutral_min_102_i_11_n_0;
  wire temp_cmp_neutral_min_102_i_12_n_0;
  wire temp_cmp_neutral_min_102_i_13_n_0;
  wire temp_cmp_neutral_min_102_i_14_n_0;
  wire temp_cmp_neutral_min_102_i_3_n_0;
  wire temp_cmp_neutral_min_102_i_4_n_0;
  wire temp_cmp_neutral_min_102_i_5_n_0;
  wire temp_cmp_neutral_min_102_i_6_n_0;
  wire temp_cmp_neutral_min_102_i_7_n_0;
  wire temp_cmp_neutral_min_102_i_8_n_0;
  wire temp_cmp_neutral_min_102_i_9_n_0;
  wire temp_cmp_neutral_min_102_reg_i_1_n_3;
  wire temp_cmp_neutral_min_102_reg_i_2_n_0;
  wire temp_cmp_neutral_min_102_reg_i_2_n_1;
  wire temp_cmp_neutral_min_102_reg_i_2_n_2;
  wire temp_cmp_neutral_min_102_reg_i_2_n_3;
  wire temp_cmp_one_dec_max_101;
  wire temp_cmp_one_dec_max_102;
  wire temp_cmp_one_dec_max_102_i_10_n_0;
  wire temp_cmp_one_dec_max_102_i_11_n_0;
  wire temp_cmp_one_dec_max_102_i_12_n_0;
  wire temp_cmp_one_dec_max_102_i_13_n_0;
  wire temp_cmp_one_dec_max_102_i_14_n_0;
  wire temp_cmp_one_dec_max_102_i_3_n_0;
  wire temp_cmp_one_dec_max_102_i_4_n_0;
  wire temp_cmp_one_dec_max_102_i_5_n_0;
  wire temp_cmp_one_dec_max_102_i_6_n_0;
  wire temp_cmp_one_dec_max_102_i_7_n_0;
  wire temp_cmp_one_dec_max_102_i_8_n_0;
  wire temp_cmp_one_dec_max_102_i_9_n_0;
  wire temp_cmp_one_dec_max_102_reg_i_1_n_3;
  wire temp_cmp_one_dec_max_102_reg_i_2_n_0;
  wire temp_cmp_one_dec_max_102_reg_i_2_n_1;
  wire temp_cmp_one_dec_max_102_reg_i_2_n_2;
  wire temp_cmp_one_dec_max_102_reg_i_2_n_3;
  wire temp_cmp_one_dec_min_101;
  wire temp_cmp_one_dec_min_102;
  wire temp_cmp_one_dec_min_102_i_10_n_0;
  wire temp_cmp_one_dec_min_102_i_11_n_0;
  wire temp_cmp_one_dec_min_102_i_12_n_0;
  wire temp_cmp_one_dec_min_102_i_13_n_0;
  wire temp_cmp_one_dec_min_102_i_14_n_0;
  wire temp_cmp_one_dec_min_102_i_3_n_0;
  wire temp_cmp_one_dec_min_102_i_4_n_0;
  wire temp_cmp_one_dec_min_102_i_5_n_0;
  wire temp_cmp_one_dec_min_102_i_6_n_0;
  wire temp_cmp_one_dec_min_102_i_7_n_0;
  wire temp_cmp_one_dec_min_102_i_8_n_0;
  wire temp_cmp_one_dec_min_102_i_9_n_0;
  wire temp_cmp_one_dec_min_102_reg_i_1_n_3;
  wire temp_cmp_one_dec_min_102_reg_i_2_n_0;
  wire temp_cmp_one_dec_min_102_reg_i_2_n_1;
  wire temp_cmp_one_dec_min_102_reg_i_2_n_2;
  wire temp_cmp_one_dec_min_102_reg_i_2_n_3;
  wire temp_cmp_one_inc_max_101;
  wire temp_cmp_one_inc_max_102;
  wire temp_cmp_one_inc_max_102_i_10_n_0;
  wire temp_cmp_one_inc_max_102_i_11_n_0;
  wire temp_cmp_one_inc_max_102_i_12_n_0;
  wire temp_cmp_one_inc_max_102_i_13_n_0;
  wire temp_cmp_one_inc_max_102_i_14_n_0;
  wire temp_cmp_one_inc_max_102_i_3_n_0;
  wire temp_cmp_one_inc_max_102_i_4_n_0;
  wire temp_cmp_one_inc_max_102_i_5_n_0;
  wire temp_cmp_one_inc_max_102_i_6_n_0;
  wire temp_cmp_one_inc_max_102_i_7_n_0;
  wire temp_cmp_one_inc_max_102_i_8_n_0;
  wire temp_cmp_one_inc_max_102_i_9_n_0;
  wire temp_cmp_one_inc_max_102_reg_i_1_n_3;
  wire temp_cmp_one_inc_max_102_reg_i_2_n_0;
  wire temp_cmp_one_inc_max_102_reg_i_2_n_1;
  wire temp_cmp_one_inc_max_102_reg_i_2_n_2;
  wire temp_cmp_one_inc_max_102_reg_i_2_n_3;
  wire temp_cmp_one_inc_min_101;
  wire temp_cmp_one_inc_min_102;
  wire temp_cmp_one_inc_min_102_i_10_n_0;
  wire temp_cmp_one_inc_min_102_i_11_n_0;
  wire temp_cmp_one_inc_min_102_i_12_n_0;
  wire temp_cmp_one_inc_min_102_i_13_n_0;
  wire temp_cmp_one_inc_min_102_i_14_n_0;
  wire temp_cmp_one_inc_min_102_i_3_n_0;
  wire temp_cmp_one_inc_min_102_i_4_n_0;
  wire temp_cmp_one_inc_min_102_i_5_n_0;
  wire temp_cmp_one_inc_min_102_i_6_n_0;
  wire temp_cmp_one_inc_min_102_i_7_n_0;
  wire temp_cmp_one_inc_min_102_i_8_n_0;
  wire temp_cmp_one_inc_min_102_i_9_n_0;
  wire temp_cmp_one_inc_min_102_reg_i_1_n_3;
  wire temp_cmp_one_inc_min_102_reg_i_2_n_0;
  wire temp_cmp_one_inc_min_102_reg_i_2_n_1;
  wire temp_cmp_one_inc_min_102_reg_i_2_n_2;
  wire temp_cmp_one_inc_min_102_reg_i_2_n_3;
  wire temp_cmp_three_dec_max_101;
  wire temp_cmp_three_dec_max_102;
  wire temp_cmp_three_dec_max_102_i_10_n_0;
  wire temp_cmp_three_dec_max_102_i_11_n_0;
  wire temp_cmp_three_dec_max_102_i_12_n_0;
  wire temp_cmp_three_dec_max_102_i_13_n_0;
  wire temp_cmp_three_dec_max_102_i_14_n_0;
  wire temp_cmp_three_dec_max_102_i_3_n_0;
  wire temp_cmp_three_dec_max_102_i_4_n_0;
  wire temp_cmp_three_dec_max_102_i_5_n_0;
  wire temp_cmp_three_dec_max_102_i_6_n_0;
  wire temp_cmp_three_dec_max_102_i_7_n_0;
  wire temp_cmp_three_dec_max_102_i_8_n_0;
  wire temp_cmp_three_dec_max_102_i_9_n_0;
  wire temp_cmp_three_dec_max_102_reg_i_1_n_3;
  wire temp_cmp_three_dec_max_102_reg_i_2_n_0;
  wire temp_cmp_three_dec_max_102_reg_i_2_n_1;
  wire temp_cmp_three_dec_max_102_reg_i_2_n_2;
  wire temp_cmp_three_dec_max_102_reg_i_2_n_3;
  wire temp_cmp_three_dec_min_101;
  wire temp_cmp_three_dec_min_102;
  wire temp_cmp_three_dec_min_102_i_10_n_0;
  wire temp_cmp_three_dec_min_102_i_11_n_0;
  wire temp_cmp_three_dec_min_102_i_12_n_0;
  wire temp_cmp_three_dec_min_102_i_13_n_0;
  wire temp_cmp_three_dec_min_102_i_14_n_0;
  wire temp_cmp_three_dec_min_102_i_3_n_0;
  wire temp_cmp_three_dec_min_102_i_4_n_0;
  wire temp_cmp_three_dec_min_102_i_5_n_0;
  wire temp_cmp_three_dec_min_102_i_6_n_0;
  wire temp_cmp_three_dec_min_102_i_7_n_0;
  wire temp_cmp_three_dec_min_102_i_8_n_0;
  wire temp_cmp_three_dec_min_102_i_9_n_0;
  wire temp_cmp_three_dec_min_102_reg_i_1_n_3;
  wire temp_cmp_three_dec_min_102_reg_i_2_n_0;
  wire temp_cmp_three_dec_min_102_reg_i_2_n_1;
  wire temp_cmp_three_dec_min_102_reg_i_2_n_2;
  wire temp_cmp_three_dec_min_102_reg_i_2_n_3;
  wire temp_cmp_three_inc_max_101;
  wire temp_cmp_three_inc_max_102;
  wire temp_cmp_three_inc_max_102_i_10_n_0;
  wire temp_cmp_three_inc_max_102_i_11_n_0;
  wire temp_cmp_three_inc_max_102_i_12_n_0;
  wire temp_cmp_three_inc_max_102_i_13_n_0;
  wire temp_cmp_three_inc_max_102_i_14_n_0;
  wire temp_cmp_three_inc_max_102_i_3_n_0;
  wire temp_cmp_three_inc_max_102_i_4_n_0;
  wire temp_cmp_three_inc_max_102_i_5_n_0;
  wire temp_cmp_three_inc_max_102_i_6_n_0;
  wire temp_cmp_three_inc_max_102_i_7_n_0;
  wire temp_cmp_three_inc_max_102_i_8_n_0;
  wire temp_cmp_three_inc_max_102_i_9_n_0;
  wire temp_cmp_three_inc_max_102_reg_i_1_n_3;
  wire temp_cmp_three_inc_max_102_reg_i_2_n_0;
  wire temp_cmp_three_inc_max_102_reg_i_2_n_1;
  wire temp_cmp_three_inc_max_102_reg_i_2_n_2;
  wire temp_cmp_three_inc_max_102_reg_i_2_n_3;
  wire temp_cmp_three_inc_min_101;
  wire temp_cmp_three_inc_min_102;
  wire temp_cmp_three_inc_min_102_i_10_n_0;
  wire temp_cmp_three_inc_min_102_i_11_n_0;
  wire temp_cmp_three_inc_min_102_i_12_n_0;
  wire temp_cmp_three_inc_min_102_i_13_n_0;
  wire temp_cmp_three_inc_min_102_i_14_n_0;
  wire temp_cmp_three_inc_min_102_i_3_n_0;
  wire temp_cmp_three_inc_min_102_i_4_n_0;
  wire temp_cmp_three_inc_min_102_i_5_n_0;
  wire temp_cmp_three_inc_min_102_i_6_n_0;
  wire temp_cmp_three_inc_min_102_i_7_n_0;
  wire temp_cmp_three_inc_min_102_i_8_n_0;
  wire temp_cmp_three_inc_min_102_i_9_n_0;
  wire temp_cmp_three_inc_min_102_reg_i_1_n_3;
  wire temp_cmp_three_inc_min_102_reg_i_2_n_0;
  wire temp_cmp_three_inc_min_102_reg_i_2_n_1;
  wire temp_cmp_three_inc_min_102_reg_i_2_n_2;
  wire temp_cmp_three_inc_min_102_reg_i_2_n_3;
  wire temp_cmp_two_dec_max_101;
  wire temp_cmp_two_dec_max_102;
  wire temp_cmp_two_dec_max_102_i_10_n_0;
  wire temp_cmp_two_dec_max_102_i_11_n_0;
  wire temp_cmp_two_dec_max_102_i_12_n_0;
  wire temp_cmp_two_dec_max_102_i_13_n_0;
  wire temp_cmp_two_dec_max_102_i_14_n_0;
  wire temp_cmp_two_dec_max_102_i_3_n_0;
  wire temp_cmp_two_dec_max_102_i_4_n_0;
  wire temp_cmp_two_dec_max_102_i_5_n_0;
  wire temp_cmp_two_dec_max_102_i_6_n_0;
  wire temp_cmp_two_dec_max_102_i_7_n_0;
  wire temp_cmp_two_dec_max_102_i_8_n_0;
  wire temp_cmp_two_dec_max_102_i_9_n_0;
  wire temp_cmp_two_dec_max_102_reg_i_1_n_3;
  wire temp_cmp_two_dec_max_102_reg_i_2_n_0;
  wire temp_cmp_two_dec_max_102_reg_i_2_n_1;
  wire temp_cmp_two_dec_max_102_reg_i_2_n_2;
  wire temp_cmp_two_dec_max_102_reg_i_2_n_3;
  wire temp_cmp_two_dec_min_101;
  wire temp_cmp_two_dec_min_102;
  wire temp_cmp_two_dec_min_102_i_10_n_0;
  wire temp_cmp_two_dec_min_102_i_11_n_0;
  wire temp_cmp_two_dec_min_102_i_12_n_0;
  wire temp_cmp_two_dec_min_102_i_13_n_0;
  wire temp_cmp_two_dec_min_102_i_14_n_0;
  wire temp_cmp_two_dec_min_102_i_3_n_0;
  wire temp_cmp_two_dec_min_102_i_4_n_0;
  wire temp_cmp_two_dec_min_102_i_5_n_0;
  wire temp_cmp_two_dec_min_102_i_6_n_0;
  wire temp_cmp_two_dec_min_102_i_7_n_0;
  wire temp_cmp_two_dec_min_102_i_8_n_0;
  wire temp_cmp_two_dec_min_102_i_9_n_0;
  wire temp_cmp_two_dec_min_102_reg_i_1_n_3;
  wire temp_cmp_two_dec_min_102_reg_i_2_n_0;
  wire temp_cmp_two_dec_min_102_reg_i_2_n_1;
  wire temp_cmp_two_dec_min_102_reg_i_2_n_2;
  wire temp_cmp_two_dec_min_102_reg_i_2_n_3;
  wire temp_cmp_two_inc_max_101;
  wire temp_cmp_two_inc_max_102;
  wire temp_cmp_two_inc_max_102_i_10_n_0;
  wire temp_cmp_two_inc_max_102_i_11_n_0;
  wire temp_cmp_two_inc_max_102_i_12_n_0;
  wire temp_cmp_two_inc_max_102_i_13_n_0;
  wire temp_cmp_two_inc_max_102_i_14_n_0;
  wire temp_cmp_two_inc_max_102_i_3_n_0;
  wire temp_cmp_two_inc_max_102_i_4_n_0;
  wire temp_cmp_two_inc_max_102_i_5_n_0;
  wire temp_cmp_two_inc_max_102_i_6_n_0;
  wire temp_cmp_two_inc_max_102_i_7_n_0;
  wire temp_cmp_two_inc_max_102_i_8_n_0;
  wire temp_cmp_two_inc_max_102_i_9_n_0;
  wire temp_cmp_two_inc_max_102_reg_i_1_n_3;
  wire temp_cmp_two_inc_max_102_reg_i_2_n_0;
  wire temp_cmp_two_inc_max_102_reg_i_2_n_1;
  wire temp_cmp_two_inc_max_102_reg_i_2_n_2;
  wire temp_cmp_two_inc_max_102_reg_i_2_n_3;
  wire temp_cmp_two_inc_min_101;
  wire temp_cmp_two_inc_min_102;
  wire temp_cmp_two_inc_min_102_i_10_n_0;
  wire temp_cmp_two_inc_min_102_i_11_n_0;
  wire temp_cmp_two_inc_min_102_i_12_n_0;
  wire temp_cmp_two_inc_min_102_i_13_n_0;
  wire temp_cmp_two_inc_min_102_i_14_n_0;
  wire temp_cmp_two_inc_min_102_i_3_n_0;
  wire temp_cmp_two_inc_min_102_i_4_n_0;
  wire temp_cmp_two_inc_min_102_i_5_n_0;
  wire temp_cmp_two_inc_min_102_i_6_n_0;
  wire temp_cmp_two_inc_min_102_i_7_n_0;
  wire temp_cmp_two_inc_min_102_i_8_n_0;
  wire temp_cmp_two_inc_min_102_i_9_n_0;
  wire temp_cmp_two_inc_min_102_reg_i_1_n_3;
  wire temp_cmp_two_inc_min_102_reg_i_2_n_0;
  wire temp_cmp_two_inc_min_102_reg_i_2_n_1;
  wire temp_cmp_two_inc_min_102_reg_i_2_n_2;
  wire temp_cmp_two_inc_min_102_reg_i_2_n_3;
  wire tempmon_init_complete;
  wire tempmon_pi_f_dec;
  wire tempmon_pi_f_inc;
  wire tempmon_sample_en_101;
  wire tempmon_sample_en_102;
  wire tempmon_sel_pi_incdec;
  wire [10:0]tempmon_state;
  wire \tempmon_state[10]_i_10_n_0 ;
  wire \tempmon_state[10]_i_11_n_0 ;
  wire \tempmon_state[10]_i_12_n_0 ;
  wire \tempmon_state[10]_i_13_n_0 ;
  wire \tempmon_state[10]_i_14_n_0 ;
  wire \tempmon_state[10]_i_15_n_0 ;
  wire \tempmon_state[10]_i_1_n_0 ;
  wire \tempmon_state[10]_i_3_n_0 ;
  wire \tempmon_state[10]_i_4_n_0 ;
  wire \tempmon_state[10]_i_5_n_0 ;
  wire \tempmon_state[10]_i_6_n_0 ;
  wire \tempmon_state[10]_i_7_n_0 ;
  wire \tempmon_state[10]_i_8_n_0 ;
  wire \tempmon_state[10]_i_9_n_0 ;
  wire \tempmon_state[6]_i_2_n_0 ;
  wire tempmon_state_init;
  wire [10:0]tempmon_state_nxt;
  wire [11:0]three_dec_max_limit;
  wire \three_dec_max_limit[0]_i_1_n_0 ;
  wire \three_dec_max_limit[10]_i_1_n_0 ;
  wire \three_dec_max_limit[11]_i_1_n_0 ;
  wire \three_dec_max_limit[11]_i_3_n_0 ;
  wire \three_dec_max_limit[1]_i_1_n_0 ;
  wire \three_dec_max_limit[2]_i_1_n_0 ;
  wire \three_dec_max_limit[3]_i_1_n_0 ;
  wire \three_dec_max_limit[4]_i_1_n_0 ;
  wire \three_dec_max_limit[5]_i_1_n_0 ;
  wire \three_dec_max_limit[6]_i_1_n_0 ;
  wire \three_dec_max_limit[7]_i_1_n_0 ;
  wire \three_dec_max_limit[8]_i_1_n_0 ;
  wire \three_dec_max_limit[8]_i_3_n_0 ;
  wire \three_dec_max_limit[8]_i_4_n_0 ;
  wire \three_dec_max_limit[9]_i_1_n_0 ;
  wire \three_dec_max_limit_reg[11]_i_2_n_2 ;
  wire \three_dec_max_limit_reg[11]_i_2_n_3 ;
  wire \three_dec_max_limit_reg[11]_i_2_n_5 ;
  wire \three_dec_max_limit_reg[11]_i_2_n_6 ;
  wire \three_dec_max_limit_reg[11]_i_2_n_7 ;
  wire \three_dec_max_limit_reg[4]_i_2_n_0 ;
  wire \three_dec_max_limit_reg[4]_i_2_n_1 ;
  wire \three_dec_max_limit_reg[4]_i_2_n_2 ;
  wire \three_dec_max_limit_reg[4]_i_2_n_3 ;
  wire \three_dec_max_limit_reg[4]_i_2_n_4 ;
  wire \three_dec_max_limit_reg[4]_i_2_n_5 ;
  wire \three_dec_max_limit_reg[4]_i_2_n_6 ;
  wire \three_dec_max_limit_reg[8]_i_2_n_0 ;
  wire \three_dec_max_limit_reg[8]_i_2_n_1 ;
  wire \three_dec_max_limit_reg[8]_i_2_n_2 ;
  wire \three_dec_max_limit_reg[8]_i_2_n_3 ;
  wire \three_dec_max_limit_reg[8]_i_2_n_4 ;
  wire \three_dec_max_limit_reg[8]_i_2_n_5 ;
  wire \three_dec_max_limit_reg[8]_i_2_n_6 ;
  wire \three_dec_max_limit_reg[8]_i_2_n_7 ;
  wire [11:0]three_dec_min_limit;
  wire \three_dec_min_limit[11]_i_2_n_0 ;
  wire \three_dec_min_limit[11]_i_3_n_0 ;
  wire \three_dec_min_limit[5]_i_2_n_0 ;
  wire \three_dec_min_limit[5]_i_3_n_0 ;
  wire \three_dec_min_limit[5]_i_4_n_0 ;
  wire \three_dec_min_limit[9]_i_2_n_0 ;
  wire \three_dec_min_limit[9]_i_3_n_0 ;
  wire \three_dec_min_limit[9]_i_4_n_0 ;
  wire \three_dec_min_limit[9]_i_5_n_0 ;
  wire [11:2]three_dec_min_limit_nxt;
  wire \three_dec_min_limit_reg[11]_i_1_n_3 ;
  wire \three_dec_min_limit_reg[5]_i_1_n_0 ;
  wire \three_dec_min_limit_reg[5]_i_1_n_1 ;
  wire \three_dec_min_limit_reg[5]_i_1_n_2 ;
  wire \three_dec_min_limit_reg[5]_i_1_n_3 ;
  wire \three_dec_min_limit_reg[9]_i_1_n_0 ;
  wire \three_dec_min_limit_reg[9]_i_1_n_1 ;
  wire \three_dec_min_limit_reg[9]_i_1_n_2 ;
  wire \three_dec_min_limit_reg[9]_i_1_n_3 ;
  wire [11:2]three_inc_max_limit;
  wire \three_inc_max_limit[11]_i_2_n_0 ;
  wire \three_inc_max_limit[11]_i_3_n_0 ;
  wire \three_inc_max_limit[4]_i_2_n_0 ;
  wire \three_inc_max_limit[4]_i_3_n_0 ;
  wire \three_inc_max_limit[8]_i_2_n_0 ;
  wire \three_inc_max_limit[8]_i_3_n_0 ;
  wire \three_inc_max_limit[8]_i_4_n_0 ;
  wire [11:2]three_inc_max_limit_nxt;
  wire \three_inc_max_limit_reg[11]_i_1_n_2 ;
  wire \three_inc_max_limit_reg[11]_i_1_n_3 ;
  wire \three_inc_max_limit_reg[4]_i_1_n_0 ;
  wire \three_inc_max_limit_reg[4]_i_1_n_1 ;
  wire \three_inc_max_limit_reg[4]_i_1_n_2 ;
  wire \three_inc_max_limit_reg[4]_i_1_n_3 ;
  wire \three_inc_max_limit_reg[4]_i_1_n_7 ;
  wire \three_inc_max_limit_reg[8]_i_1_n_0 ;
  wire \three_inc_max_limit_reg[8]_i_1_n_1 ;
  wire \three_inc_max_limit_reg[8]_i_1_n_2 ;
  wire \three_inc_max_limit_reg[8]_i_1_n_3 ;
  wire [11:2]three_inc_min_limit;
  wire \three_inc_min_limit[11]_i_2_n_0 ;
  wire \three_inc_min_limit[11]_i_3_n_0 ;
  wire \three_inc_min_limit[5]_i_2_n_0 ;
  wire \three_inc_min_limit[5]_i_3_n_0 ;
  wire \three_inc_min_limit[5]_i_4_n_0 ;
  wire \three_inc_min_limit[9]_i_2_n_0 ;
  wire \three_inc_min_limit[9]_i_3_n_0 ;
  wire \three_inc_min_limit[9]_i_4_n_0 ;
  wire \three_inc_min_limit[9]_i_5_n_0 ;
  wire [11:2]three_inc_min_limit_nxt;
  wire \three_inc_min_limit_reg[11]_i_1_n_3 ;
  wire \three_inc_min_limit_reg[5]_i_1_n_0 ;
  wire \three_inc_min_limit_reg[5]_i_1_n_1 ;
  wire \three_inc_min_limit_reg[5]_i_1_n_2 ;
  wire \three_inc_min_limit_reg[5]_i_1_n_3 ;
  wire \three_inc_min_limit_reg[9]_i_1_n_0 ;
  wire \three_inc_min_limit_reg[9]_i_1_n_1 ;
  wire \three_inc_min_limit_reg[9]_i_1_n_2 ;
  wire \three_inc_min_limit_reg[9]_i_1_n_3 ;
  wire [11:0]two_dec_max_limit;
  wire \two_dec_max_limit[0]_i_1_n_0 ;
  wire \two_dec_max_limit[11]_i_2_n_0 ;
  wire \two_dec_max_limit[4]_i_2_n_0 ;
  wire \two_dec_max_limit[4]_i_3_n_0 ;
  wire \two_dec_max_limit[8]_i_2_n_0 ;
  wire [11:1]two_dec_max_limit_nxt;
  wire \two_dec_max_limit_reg[11]_i_1_n_2 ;
  wire \two_dec_max_limit_reg[11]_i_1_n_3 ;
  wire \two_dec_max_limit_reg[4]_i_1_n_0 ;
  wire \two_dec_max_limit_reg[4]_i_1_n_1 ;
  wire \two_dec_max_limit_reg[4]_i_1_n_2 ;
  wire \two_dec_max_limit_reg[4]_i_1_n_3 ;
  wire \two_dec_max_limit_reg[8]_i_1_n_0 ;
  wire \two_dec_max_limit_reg[8]_i_1_n_1 ;
  wire \two_dec_max_limit_reg[8]_i_1_n_2 ;
  wire \two_dec_max_limit_reg[8]_i_1_n_3 ;
  wire [11:2]two_dec_min_limit;
  wire \two_dec_min_limit[11]_i_2_n_0 ;
  wire \two_dec_min_limit[11]_i_3_n_0 ;
  wire \two_dec_min_limit[5]_i_2_n_0 ;
  wire \two_dec_min_limit[5]_i_3_n_0 ;
  wire \two_dec_min_limit[5]_i_4_n_0 ;
  wire \two_dec_min_limit[9]_i_2_n_0 ;
  wire \two_dec_min_limit[9]_i_3_n_0 ;
  wire \two_dec_min_limit[9]_i_4_n_0 ;
  wire \two_dec_min_limit[9]_i_5_n_0 ;
  wire [11:2]two_dec_min_limit_nxt;
  wire \two_dec_min_limit_reg[11]_i_1_n_3 ;
  wire \two_dec_min_limit_reg[5]_i_1_n_0 ;
  wire \two_dec_min_limit_reg[5]_i_1_n_1 ;
  wire \two_dec_min_limit_reg[5]_i_1_n_2 ;
  wire \two_dec_min_limit_reg[5]_i_1_n_3 ;
  wire \two_dec_min_limit_reg[9]_i_1_n_0 ;
  wire \two_dec_min_limit_reg[9]_i_1_n_1 ;
  wire \two_dec_min_limit_reg[9]_i_1_n_2 ;
  wire \two_dec_min_limit_reg[9]_i_1_n_3 ;
  wire [11:1]two_inc_max_limit;
  wire \two_inc_max_limit[11]_i_2_n_0 ;
  wire \two_inc_max_limit[11]_i_3_n_0 ;
  wire \two_inc_max_limit[11]_i_4_n_0 ;
  wire \two_inc_max_limit[1]_i_1_n_0 ;
  wire \two_inc_max_limit[4]_i_2_n_0 ;
  wire \two_inc_max_limit[4]_i_3_n_0 ;
  wire \two_inc_max_limit[4]_i_4_n_0 ;
  wire \two_inc_max_limit[8]_i_2_n_0 ;
  wire [11:2]two_inc_max_limit_nxt;
  wire \two_inc_max_limit_reg[11]_i_1_n_2 ;
  wire \two_inc_max_limit_reg[11]_i_1_n_3 ;
  wire \two_inc_max_limit_reg[4]_i_1_n_0 ;
  wire \two_inc_max_limit_reg[4]_i_1_n_1 ;
  wire \two_inc_max_limit_reg[4]_i_1_n_2 ;
  wire \two_inc_max_limit_reg[4]_i_1_n_3 ;
  wire \two_inc_max_limit_reg[8]_i_1_n_0 ;
  wire \two_inc_max_limit_reg[8]_i_1_n_1 ;
  wire \two_inc_max_limit_reg[8]_i_1_n_2 ;
  wire \two_inc_max_limit_reg[8]_i_1_n_3 ;
  wire [11:1]two_inc_min_limit;
  wire \two_inc_min_limit[11]_i_2_n_0 ;
  wire \two_inc_min_limit[11]_i_3_n_0 ;
  wire \two_inc_min_limit[5]_i_2_n_0 ;
  wire \two_inc_min_limit[5]_i_3_n_0 ;
  wire \two_inc_min_limit[5]_i_4_n_0 ;
  wire \two_inc_min_limit[9]_i_2_n_0 ;
  wire \two_inc_min_limit[9]_i_3_n_0 ;
  wire \two_inc_min_limit[9]_i_4_n_0 ;
  wire \two_inc_min_limit[9]_i_5_n_0 ;
  wire [11:2]two_inc_min_limit_nxt;
  wire \two_inc_min_limit_reg[11]_i_1_n_3 ;
  wire \two_inc_min_limit_reg[5]_i_1_n_0 ;
  wire \two_inc_min_limit_reg[5]_i_1_n_1 ;
  wire \two_inc_min_limit_reg[5]_i_1_n_2 ;
  wire \two_inc_min_limit_reg[5]_i_1_n_3 ;
  wire \two_inc_min_limit_reg[9]_i_1_n_0 ;
  wire \two_inc_min_limit_reg[9]_i_1_n_1 ;
  wire \two_inc_min_limit_reg[9]_i_1_n_2 ;
  wire \two_inc_min_limit_reg[9]_i_1_n_3 ;
  wire update_temp_101__0;
  wire update_temp_102;
  wire [3:1]\NLW_four_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED ;
  wire [3:2]\NLW_four_dec_min_limit_reg[11]_i_1_O_UNCONNECTED ;
  wire [3:2]\NLW_four_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED ;
  wire [3:3]\NLW_four_inc_max_limit_reg[11]_i_1_O_UNCONNECTED ;
  wire [3:2]\NLW_neutral_max_limit_reg[11]_i_1_CO_UNCONNECTED ;
  wire [3:3]\NLW_neutral_max_limit_reg[11]_i_1_O_UNCONNECTED ;
  wire [0:0]\NLW_neutral_max_limit_reg[4]_i_1_O_UNCONNECTED ;
  wire [3:1]\NLW_neutral_min_limit_reg[11]_i_1_CO_UNCONNECTED ;
  wire [3:2]\NLW_neutral_min_limit_reg[11]_i_1_O_UNCONNECTED ;
  wire [3:2]\NLW_one_dec_max_limit_reg[11]_i_1_CO_UNCONNECTED ;
  wire [3:3]\NLW_one_dec_max_limit_reg[11]_i_1_O_UNCONNECTED ;
  wire [0:0]\NLW_one_dec_max_limit_reg[4]_i_1_O_UNCONNECTED ;
  wire [3:1]\NLW_one_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED ;
  wire [3:2]\NLW_one_dec_min_limit_reg[11]_i_1_O_UNCONNECTED ;
  wire [3:2]\NLW_one_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED ;
  wire [3:3]\NLW_one_inc_max_limit_reg[11]_i_1_O_UNCONNECTED ;
  wire [0:0]\NLW_one_inc_max_limit_reg[4]_i_1_O_UNCONNECTED ;
  wire [3:1]\NLW_one_inc_min_limit_reg[11]_i_1_CO_UNCONNECTED ;
  wire [3:2]\NLW_one_inc_min_limit_reg[11]_i_1_O_UNCONNECTED ;
  wire [3:2]NLW_temp_cmp_four_dec_min_102_reg_i_1_CO_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_four_dec_min_102_reg_i_1_O_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_four_dec_min_102_reg_i_2_O_UNCONNECTED;
  wire [3:2]NLW_temp_cmp_four_inc_max_102_reg_i_1_CO_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_four_inc_max_102_reg_i_1_O_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_four_inc_max_102_reg_i_2_O_UNCONNECTED;
  wire [3:2]NLW_temp_cmp_neutral_max_102_reg_i_1_CO_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_neutral_max_102_reg_i_1_O_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_neutral_max_102_reg_i_2_O_UNCONNECTED;
  wire [3:2]NLW_temp_cmp_neutral_min_102_reg_i_1_CO_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_neutral_min_102_reg_i_1_O_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_neutral_min_102_reg_i_2_O_UNCONNECTED;
  wire [3:2]NLW_temp_cmp_one_dec_max_102_reg_i_1_CO_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_one_dec_max_102_reg_i_1_O_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_one_dec_max_102_reg_i_2_O_UNCONNECTED;
  wire [3:2]NLW_temp_cmp_one_dec_min_102_reg_i_1_CO_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_one_dec_min_102_reg_i_1_O_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_one_dec_min_102_reg_i_2_O_UNCONNECTED;
  wire [3:2]NLW_temp_cmp_one_inc_max_102_reg_i_1_CO_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_one_inc_max_102_reg_i_1_O_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_one_inc_max_102_reg_i_2_O_UNCONNECTED;
  wire [3:2]NLW_temp_cmp_one_inc_min_102_reg_i_1_CO_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_one_inc_min_102_reg_i_1_O_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_one_inc_min_102_reg_i_2_O_UNCONNECTED;
  wire [3:2]NLW_temp_cmp_three_dec_max_102_reg_i_1_CO_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_three_dec_max_102_reg_i_1_O_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_three_dec_max_102_reg_i_2_O_UNCONNECTED;
  wire [3:2]NLW_temp_cmp_three_dec_min_102_reg_i_1_CO_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_three_dec_min_102_reg_i_1_O_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_three_dec_min_102_reg_i_2_O_UNCONNECTED;
  wire [3:2]NLW_temp_cmp_three_inc_max_102_reg_i_1_CO_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_three_inc_max_102_reg_i_1_O_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_three_inc_max_102_reg_i_2_O_UNCONNECTED;
  wire [3:2]NLW_temp_cmp_three_inc_min_102_reg_i_1_CO_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_three_inc_min_102_reg_i_1_O_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_three_inc_min_102_reg_i_2_O_UNCONNECTED;
  wire [3:2]NLW_temp_cmp_two_dec_max_102_reg_i_1_CO_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_two_dec_max_102_reg_i_1_O_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_two_dec_max_102_reg_i_2_O_UNCONNECTED;
  wire [3:2]NLW_temp_cmp_two_dec_min_102_reg_i_1_CO_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_two_dec_min_102_reg_i_1_O_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_two_dec_min_102_reg_i_2_O_UNCONNECTED;
  wire [3:2]NLW_temp_cmp_two_inc_max_102_reg_i_1_CO_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_two_inc_max_102_reg_i_1_O_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_two_inc_max_102_reg_i_2_O_UNCONNECTED;
  wire [3:2]NLW_temp_cmp_two_inc_min_102_reg_i_1_CO_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_two_inc_min_102_reg_i_1_O_UNCONNECTED;
  wire [3:0]NLW_temp_cmp_two_inc_min_102_reg_i_2_O_UNCONNECTED;
  wire [2:2]\NLW_three_dec_max_limit_reg[11]_i_2_CO_UNCONNECTED ;
  wire [3:3]\NLW_three_dec_max_limit_reg[11]_i_2_O_UNCONNECTED ;
  wire [0:0]\NLW_three_dec_max_limit_reg[4]_i_2_O_UNCONNECTED ;
  wire [3:1]\NLW_three_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED ;
  wire [3:2]\NLW_three_dec_min_limit_reg[11]_i_1_O_UNCONNECTED ;
  wire [3:2]\NLW_three_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED ;
  wire [3:3]\NLW_three_inc_max_limit_reg[11]_i_1_O_UNCONNECTED ;
  wire [3:1]\NLW_three_inc_min_limit_reg[11]_i_1_CO_UNCONNECTED ;
  wire [3:2]\NLW_three_inc_min_limit_reg[11]_i_1_O_UNCONNECTED ;
  wire [3:2]\NLW_two_dec_max_limit_reg[11]_i_1_CO_UNCONNECTED ;
  wire [3:3]\NLW_two_dec_max_limit_reg[11]_i_1_O_UNCONNECTED ;
  wire [0:0]\NLW_two_dec_max_limit_reg[4]_i_1_O_UNCONNECTED ;
  wire [3:1]\NLW_two_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED ;
  wire [3:2]\NLW_two_dec_min_limit_reg[11]_i_1_O_UNCONNECTED ;
  wire [3:2]\NLW_two_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED ;
  wire [3:3]\NLW_two_inc_max_limit_reg[11]_i_1_O_UNCONNECTED ;
  wire [0:0]\NLW_two_inc_max_limit_reg[4]_i_1_O_UNCONNECTED ;
  wire [3:1]\NLW_two_inc_min_limit_reg[11]_i_1_CO_UNCONNECTED ;
  wire [3:2]\NLW_two_inc_min_limit_reg[11]_i_1_O_UNCONNECTED ;

  (* SOFT_HLUTNM = "soft_lutpair238" *) 
  LUT4 #(
    .INIT(16'hABAA)) 
    \calib_sel[4]_i_1 
       (.I0(\calib_sel_reg[0] ),
        .I1(tempmon_pi_f_inc),
        .I2(tempmon_pi_f_dec),
        .I3(calib_complete),
        .O(pi_f_inc_reg_0));
  LUT6 #(
    .INIT(64'hBFBAAAAAAAAAAAAA)) 
    \calib_zero_inputs[0]_i_1 
       (.I0(pi_f_inc_reg_0),
        .I1(\calib_zero_inputs_reg[2] ),
        .I2(calib_sel1__1),
        .I3(\calib_zero_inputs[0]_i_2_n_0 ),
        .I4(dqs_po_dec_done),
        .I5(pi_fine_dly_dec_done),
        .O(D[0]));
  (* SOFT_HLUTNM = "soft_lutpair236" *) 
  LUT5 #(
    .INIT(32'h00000001)) 
    \calib_zero_inputs[0]_i_2 
       (.I0(calib_in_common),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(tempmon_pi_f_dec),
        .I4(tempmon_pi_f_inc),
        .O(\calib_zero_inputs[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAABAAAAAAAA)) 
    \calib_zero_inputs[1]_i_1 
       (.I0(pi_f_inc_reg_0),
        .I1(calib_in_common),
        .I2(tempmon_pi_f_inc),
        .I3(tempmon_pi_f_dec),
        .I4(calib_sel1__1),
        .I5(cmd_delay_start0),
        .O(D[1]));
  LUT6 #(
    .INIT(64'hBFBAAAAAAAAAAAAA)) 
    \calib_zero_inputs[2]_i_1 
       (.I0(pi_f_inc_reg_0),
        .I1(\calib_zero_inputs_reg[2] ),
        .I2(calib_sel1__1),
        .I3(\calib_zero_inputs[2]_i_2_n_0 ),
        .I4(dqs_po_dec_done),
        .I5(pi_fine_dly_dec_done),
        .O(D[2]));
  (* SOFT_HLUTNM = "soft_lutpair236" *) 
  LUT5 #(
    .INIT(32'h0000000E)) 
    \calib_zero_inputs[2]_i_2 
       (.I0(Q[1]),
        .I1(Q[0]),
        .I2(calib_in_common),
        .I3(tempmon_pi_f_dec),
        .I4(tempmon_pi_f_inc),
        .O(\calib_zero_inputs[2]_i_2_n_0 ));
  FDRE \device_temp_101_reg[0] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(\device_temp_101_reg[11]_0 [0]),
        .Q(device_temp_101[0]),
        .R(\device_temp_101_reg[0]_0 ));
  FDRE \device_temp_101_reg[10] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(\device_temp_101_reg[11]_0 [10]),
        .Q(device_temp_101[10]),
        .R(\device_temp_101_reg[0]_0 ));
  FDRE \device_temp_101_reg[11] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(\device_temp_101_reg[11]_0 [11]),
        .Q(device_temp_101[11]),
        .R(\device_temp_101_reg[0]_0 ));
  FDRE \device_temp_101_reg[1] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(\device_temp_101_reg[11]_0 [1]),
        .Q(device_temp_101[1]),
        .R(\device_temp_101_reg[0]_0 ));
  FDRE \device_temp_101_reg[2] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(\device_temp_101_reg[11]_0 [2]),
        .Q(device_temp_101[2]),
        .R(\device_temp_101_reg[0]_0 ));
  FDRE \device_temp_101_reg[3] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(\device_temp_101_reg[11]_0 [3]),
        .Q(device_temp_101[3]),
        .R(\device_temp_101_reg[0]_0 ));
  FDRE \device_temp_101_reg[4] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(\device_temp_101_reg[11]_0 [4]),
        .Q(device_temp_101[4]),
        .R(\device_temp_101_reg[0]_0 ));
  FDRE \device_temp_101_reg[5] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(\device_temp_101_reg[11]_0 [5]),
        .Q(device_temp_101[5]),
        .R(\device_temp_101_reg[0]_0 ));
  FDRE \device_temp_101_reg[6] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(\device_temp_101_reg[11]_0 [6]),
        .Q(device_temp_101[6]),
        .R(\device_temp_101_reg[0]_0 ));
  FDRE \device_temp_101_reg[7] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(\device_temp_101_reg[11]_0 [7]),
        .Q(device_temp_101[7]),
        .R(\device_temp_101_reg[0]_0 ));
  FDRE \device_temp_101_reg[8] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(\device_temp_101_reg[11]_0 [8]),
        .Q(device_temp_101[8]),
        .R(\device_temp_101_reg[0]_0 ));
  FDRE \device_temp_101_reg[9] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(\device_temp_101_reg[11]_0 [9]),
        .Q(device_temp_101[9]),
        .R(\device_temp_101_reg[0]_0 ));
  LUT5 #(
    .INIT(32'h00000001)) 
    \device_temp_init[11]_i_1 
       (.I0(tempmon_state[9]),
        .I1(tempmon_state[7]),
        .I2(tempmon_state[8]),
        .I3(\device_temp_init[11]_i_2_n_0 ),
        .I4(\device_temp_init[11]_i_3_n_0 ),
        .O(tempmon_state_init));
  LUT4 #(
    .INIT(16'hFFFD)) 
    \device_temp_init[11]_i_2 
       (.I0(tempmon_state[1]),
        .I1(tempmon_state[2]),
        .I2(tempmon_state[3]),
        .I3(tempmon_state[10]),
        .O(\device_temp_init[11]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair239" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    \device_temp_init[11]_i_3 
       (.I0(tempmon_state[0]),
        .I1(tempmon_state[4]),
        .I2(tempmon_state[5]),
        .I3(tempmon_state[6]),
        .O(\device_temp_init[11]_i_3_n_0 ));
  FDRE \device_temp_init_reg[0] 
       (.C(pi_f_dec_reg_0),
        .CE(tempmon_state_init),
        .D(device_temp_101[0]),
        .Q(device_temp_init[0]),
        .R(\device_temp_101_reg[0]_0 ));
  FDRE \device_temp_init_reg[10] 
       (.C(pi_f_dec_reg_0),
        .CE(tempmon_state_init),
        .D(device_temp_101[10]),
        .Q(device_temp_init[10]),
        .R(\device_temp_101_reg[0]_0 ));
  FDRE \device_temp_init_reg[11] 
       (.C(pi_f_dec_reg_0),
        .CE(tempmon_state_init),
        .D(device_temp_101[11]),
        .Q(device_temp_init[11]),
        .R(\device_temp_101_reg[0]_0 ));
  FDRE \device_temp_init_reg[1] 
       (.C(pi_f_dec_reg_0),
        .CE(tempmon_state_init),
        .D(device_temp_101[1]),
        .Q(device_temp_init[1]),
        .R(\device_temp_101_reg[0]_0 ));
  FDRE \device_temp_init_reg[2] 
       (.C(pi_f_dec_reg_0),
        .CE(tempmon_state_init),
        .D(device_temp_101[2]),
        .Q(device_temp_init[2]),
        .R(\device_temp_101_reg[0]_0 ));
  FDRE \device_temp_init_reg[3] 
       (.C(pi_f_dec_reg_0),
        .CE(tempmon_state_init),
        .D(device_temp_101[3]),
        .Q(device_temp_init[3]),
        .R(\device_temp_101_reg[0]_0 ));
  FDRE \device_temp_init_reg[4] 
       (.C(pi_f_dec_reg_0),
        .CE(tempmon_state_init),
        .D(device_temp_101[4]),
        .Q(device_temp_init[4]),
        .R(\device_temp_101_reg[0]_0 ));
  FDRE \device_temp_init_reg[5] 
       (.C(pi_f_dec_reg_0),
        .CE(tempmon_state_init),
        .D(device_temp_101[5]),
        .Q(device_temp_init[5]),
        .R(\device_temp_101_reg[0]_0 ));
  FDRE \device_temp_init_reg[6] 
       (.C(pi_f_dec_reg_0),
        .CE(tempmon_state_init),
        .D(device_temp_101[6]),
        .Q(device_temp_init[6]),
        .R(\device_temp_101_reg[0]_0 ));
  FDRE \device_temp_init_reg[7] 
       (.C(pi_f_dec_reg_0),
        .CE(tempmon_state_init),
        .D(device_temp_101[7]),
        .Q(device_temp_init[7]),
        .R(\device_temp_101_reg[0]_0 ));
  FDRE \device_temp_init_reg[8] 
       (.C(pi_f_dec_reg_0),
        .CE(tempmon_state_init),
        .D(device_temp_101[8]),
        .Q(device_temp_init[8]),
        .R(\device_temp_101_reg[0]_0 ));
  FDRE \device_temp_init_reg[9] 
       (.C(pi_f_dec_reg_0),
        .CE(tempmon_state_init),
        .D(device_temp_101[9]),
        .Q(device_temp_init[9]),
        .R(\device_temp_101_reg[0]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \four_dec_min_limit[11]_i_2 
       (.I0(three_dec_max_limit[11]),
        .O(\four_dec_min_limit[11]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \four_dec_min_limit[11]_i_3 
       (.I0(three_dec_max_limit[10]),
        .O(\four_dec_min_limit[11]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \four_dec_min_limit[5]_i_2 
       (.I0(three_dec_max_limit[5]),
        .O(\four_dec_min_limit[5]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \four_dec_min_limit[5]_i_3 
       (.I0(three_dec_max_limit[4]),
        .O(\four_dec_min_limit[5]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \four_dec_min_limit[5]_i_4 
       (.I0(three_dec_max_limit[3]),
        .O(\four_dec_min_limit[5]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \four_dec_min_limit[9]_i_2 
       (.I0(three_dec_max_limit[9]),
        .O(\four_dec_min_limit[9]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \four_dec_min_limit[9]_i_3 
       (.I0(three_dec_max_limit[8]),
        .O(\four_dec_min_limit[9]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \four_dec_min_limit[9]_i_4 
       (.I0(three_dec_max_limit[7]),
        .O(\four_dec_min_limit[9]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \four_dec_min_limit[9]_i_5 
       (.I0(three_dec_max_limit[6]),
        .O(\four_dec_min_limit[9]_i_5_n_0 ));
  FDRE \four_dec_min_limit_reg[0] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(three_dec_max_limit[0]),
        .Q(four_dec_min_limit[0]),
        .R(\four_dec_min_limit_reg[0]_0 ));
  FDRE \four_dec_min_limit_reg[10] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(four_dec_min_limit_nxt[10]),
        .Q(four_dec_min_limit[10]),
        .R(\four_dec_min_limit_reg[0]_0 ));
  FDRE \four_dec_min_limit_reg[11] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(four_dec_min_limit_nxt[11]),
        .Q(four_dec_min_limit[11]),
        .R(\four_dec_min_limit_reg[0]_0 ));
  CARRY4 \four_dec_min_limit_reg[11]_i_1 
       (.CI(\four_dec_min_limit_reg[9]_i_1_n_0 ),
        .CO({\NLW_four_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED [3:1],\four_dec_min_limit_reg[11]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,three_dec_max_limit[10]}),
        .O({\NLW_four_dec_min_limit_reg[11]_i_1_O_UNCONNECTED [3:2],four_dec_min_limit_nxt[11:10]}),
        .S({1'b0,1'b0,\four_dec_min_limit[11]_i_2_n_0 ,\four_dec_min_limit[11]_i_3_n_0 }));
  FDRE \four_dec_min_limit_reg[1] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(three_dec_max_limit[1]),
        .Q(four_dec_min_limit[1]),
        .R(\four_dec_min_limit_reg[0]_0 ));
  FDRE \four_dec_min_limit_reg[2] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(four_dec_min_limit_nxt[2]),
        .Q(four_dec_min_limit[2]),
        .R(\four_dec_min_limit_reg[0]_0 ));
  FDRE \four_dec_min_limit_reg[3] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(four_dec_min_limit_nxt[3]),
        .Q(four_dec_min_limit[3]),
        .R(\four_dec_min_limit_reg[0]_0 ));
  FDRE \four_dec_min_limit_reg[4] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(four_dec_min_limit_nxt[4]),
        .Q(four_dec_min_limit[4]),
        .R(\four_dec_min_limit_reg[0]_0 ));
  FDRE \four_dec_min_limit_reg[5] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(four_dec_min_limit_nxt[5]),
        .Q(four_dec_min_limit[5]),
        .R(\four_dec_min_limit_reg[0]_0 ));
  CARRY4 \four_dec_min_limit_reg[5]_i_1 
       (.CI(1'b0),
        .CO({\four_dec_min_limit_reg[5]_i_1_n_0 ,\four_dec_min_limit_reg[5]_i_1_n_1 ,\four_dec_min_limit_reg[5]_i_1_n_2 ,\four_dec_min_limit_reg[5]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({three_dec_max_limit[5:3],1'b0}),
        .O(four_dec_min_limit_nxt[5:2]),
        .S({\four_dec_min_limit[5]_i_2_n_0 ,\four_dec_min_limit[5]_i_3_n_0 ,\four_dec_min_limit[5]_i_4_n_0 ,three_dec_max_limit[2]}));
  FDRE \four_dec_min_limit_reg[6] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(four_dec_min_limit_nxt[6]),
        .Q(four_dec_min_limit[6]),
        .R(\four_dec_min_limit_reg[0]_0 ));
  FDRE \four_dec_min_limit_reg[7] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(four_dec_min_limit_nxt[7]),
        .Q(four_dec_min_limit[7]),
        .R(\four_dec_min_limit_reg[0]_0 ));
  FDRE \four_dec_min_limit_reg[8] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(four_dec_min_limit_nxt[8]),
        .Q(four_dec_min_limit[8]),
        .R(\four_dec_min_limit_reg[0]_0 ));
  FDRE \four_dec_min_limit_reg[9] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(four_dec_min_limit_nxt[9]),
        .Q(four_dec_min_limit[9]),
        .R(\four_dec_min_limit_reg[0]_0 ));
  CARRY4 \four_dec_min_limit_reg[9]_i_1 
       (.CI(\four_dec_min_limit_reg[5]_i_1_n_0 ),
        .CO({\four_dec_min_limit_reg[9]_i_1_n_0 ,\four_dec_min_limit_reg[9]_i_1_n_1 ,\four_dec_min_limit_reg[9]_i_1_n_2 ,\four_dec_min_limit_reg[9]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI(three_dec_max_limit[9:6]),
        .O(four_dec_min_limit_nxt[9:6]),
        .S({\four_dec_min_limit[9]_i_2_n_0 ,\four_dec_min_limit[9]_i_3_n_0 ,\four_dec_min_limit[9]_i_4_n_0 ,\four_dec_min_limit[9]_i_5_n_0 }));
  LUT1 #(
    .INIT(2'h1)) 
    \four_inc_max_limit[11]_i_2 
       (.I0(device_temp_init[11]),
        .O(\four_inc_max_limit[11]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \four_inc_max_limit[11]_i_3 
       (.I0(device_temp_init[10]),
        .O(\four_inc_max_limit[11]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \four_inc_max_limit[4]_i_2 
       (.I0(device_temp_init[4]),
        .O(\four_inc_max_limit[4]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \four_inc_max_limit[4]_i_3 
       (.I0(device_temp_init[3]),
        .O(\four_inc_max_limit[4]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \four_inc_max_limit[4]_i_4 
       (.I0(device_temp_init[2]),
        .O(\four_inc_max_limit[4]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \four_inc_max_limit[4]_i_5 
       (.I0(device_temp_init[1]),
        .O(\four_inc_max_limit[4]_i_5_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \four_inc_max_limit[8]_i_2 
       (.I0(device_temp_init[7]),
        .O(\four_inc_max_limit[8]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \four_inc_max_limit[8]_i_3 
       (.I0(device_temp_init[5]),
        .O(\four_inc_max_limit[8]_i_3_n_0 ));
  FDRE \four_inc_max_limit_reg[10] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(four_inc_max_limit_nxt[10]),
        .Q(four_inc_max_limit[10]),
        .R(\one_dec_max_limit_reg[2]_0 ));
  FDRE \four_inc_max_limit_reg[11] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(four_inc_max_limit_nxt[11]),
        .Q(four_inc_max_limit[11]),
        .R(\one_dec_max_limit_reg[2]_0 ));
  CARRY4 \four_inc_max_limit_reg[11]_i_1 
       (.CI(\four_inc_max_limit_reg[8]_i_1_n_0 ),
        .CO({\NLW_four_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED [3:2],\four_inc_max_limit_reg[11]_i_1_n_2 ,\four_inc_max_limit_reg[11]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,device_temp_init[10],1'b0}),
        .O({\NLW_four_inc_max_limit_reg[11]_i_1_O_UNCONNECTED [3],four_inc_max_limit_nxt[11:9]}),
        .S({1'b0,\four_inc_max_limit[11]_i_2_n_0 ,\four_inc_max_limit[11]_i_3_n_0 ,device_temp_init[9]}));
  FDRE \four_inc_max_limit_reg[2] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(four_inc_max_limit_nxt[2]),
        .Q(four_inc_max_limit[2]),
        .R(\one_dec_max_limit_reg[2]_0 ));
  FDRE \four_inc_max_limit_reg[3] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(four_inc_max_limit_nxt[3]),
        .Q(four_inc_max_limit[3]),
        .R(\one_dec_max_limit_reg[2]_0 ));
  FDRE \four_inc_max_limit_reg[4] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(four_inc_max_limit_nxt[4]),
        .Q(four_inc_max_limit[4]),
        .R(\one_dec_max_limit_reg[2]_0 ));
  CARRY4 \four_inc_max_limit_reg[4]_i_1 
       (.CI(1'b0),
        .CO({\four_inc_max_limit_reg[4]_i_1_n_0 ,\four_inc_max_limit_reg[4]_i_1_n_1 ,\four_inc_max_limit_reg[4]_i_1_n_2 ,\four_inc_max_limit_reg[4]_i_1_n_3 }),
        .CYINIT(device_temp_init[0]),
        .DI(device_temp_init[4:1]),
        .O({four_inc_max_limit_nxt[4:2],two_dec_max_limit_nxt[1]}),
        .S({\four_inc_max_limit[4]_i_2_n_0 ,\four_inc_max_limit[4]_i_3_n_0 ,\four_inc_max_limit[4]_i_4_n_0 ,\four_inc_max_limit[4]_i_5_n_0 }));
  FDRE \four_inc_max_limit_reg[5] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(four_inc_max_limit_nxt[5]),
        .Q(four_inc_max_limit[5]),
        .R(\one_dec_max_limit_reg[2]_0 ));
  FDRE \four_inc_max_limit_reg[6] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(four_inc_max_limit_nxt[6]),
        .Q(four_inc_max_limit[6]),
        .R(\one_dec_max_limit_reg[2]_0 ));
  FDRE \four_inc_max_limit_reg[7] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(four_inc_max_limit_nxt[7]),
        .Q(four_inc_max_limit[7]),
        .R(\one_dec_max_limit_reg[2]_0 ));
  FDRE \four_inc_max_limit_reg[8] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(four_inc_max_limit_nxt[8]),
        .Q(four_inc_max_limit[8]),
        .R(\one_dec_max_limit_reg[2]_0 ));
  CARRY4 \four_inc_max_limit_reg[8]_i_1 
       (.CI(\four_inc_max_limit_reg[4]_i_1_n_0 ),
        .CO({\four_inc_max_limit_reg[8]_i_1_n_0 ,\four_inc_max_limit_reg[8]_i_1_n_1 ,\four_inc_max_limit_reg[8]_i_1_n_2 ,\four_inc_max_limit_reg[8]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,device_temp_init[7],1'b0,device_temp_init[5]}),
        .O(four_inc_max_limit_nxt[8:5]),
        .S({device_temp_init[8],\four_inc_max_limit[8]_i_2_n_0 ,device_temp_init[6],\four_inc_max_limit[8]_i_3_n_0 }));
  FDRE \four_inc_max_limit_reg[9] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(four_inc_max_limit_nxt[9]),
        .Q(four_inc_max_limit[9]),
        .R(\one_dec_max_limit_reg[2]_0 ));
  LUT6 #(
    .INIT(64'hA800000000000000)) 
    \gen_byte_sel_div2.calib_in_common_i_4 
       (.I0(\gen_byte_sel_div2.calib_in_common_i_2_1 ),
        .I1(tempmon_pi_f_inc),
        .I2(tempmon_pi_f_dec),
        .I3(\gen_byte_sel_div2.calib_in_common_i_2_0 ),
        .I4(\gen_byte_sel_div2.calib_in_common_i_3 ),
        .I5(\gen_byte_sel_div2.calib_in_common_i_2 ),
        .O(calib_in_common4_out));
  LUT6 #(
    .INIT(64'hFFFFFF7FFFFFFFFF)) 
    \gen_byte_sel_div2.calib_in_common_i_5 
       (.I0(\gen_byte_sel_div2.calib_in_common_i_2 ),
        .I1(\gen_byte_sel_div2.calib_in_common_i_3 ),
        .I2(\gen_byte_sel_div2.calib_in_common_i_2_0 ),
        .I3(tempmon_pi_f_inc),
        .I4(tempmon_pi_f_dec),
        .I5(\gen_byte_sel_div2.calib_in_common_i_2_1 ),
        .O(rdlvl_stg1_done_int_reg));
  LUT1 #(
    .INIT(2'h1)) 
    \neutral_max_limit[4]_i_2 
       (.I0(device_temp_init[4]),
        .O(\neutral_max_limit[4]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \neutral_max_limit[4]_i_3 
       (.I0(device_temp_init[2]),
        .O(\neutral_max_limit[4]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \neutral_max_limit[4]_i_4 
       (.I0(device_temp_init[1]),
        .O(\neutral_max_limit[4]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \neutral_max_limit[8]_i_2 
       (.I0(device_temp_init[6]),
        .O(\neutral_max_limit[8]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \neutral_max_limit[8]_i_3 
       (.I0(device_temp_init[5]),
        .O(\neutral_max_limit[8]_i_3_n_0 ));
  FDRE \neutral_max_limit_reg[10] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(neutral_max_limit_nxt[10]),
        .Q(neutral_max_limit[10]),
        .R(\neutral_max_limit_reg[11]_0 ));
  FDRE \neutral_max_limit_reg[11] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(neutral_max_limit_nxt[11]),
        .Q(neutral_max_limit[11]),
        .R(\neutral_max_limit_reg[11]_0 ));
  CARRY4 \neutral_max_limit_reg[11]_i_1 
       (.CI(\neutral_max_limit_reg[8]_i_1_n_0 ),
        .CO({\NLW_neutral_max_limit_reg[11]_i_1_CO_UNCONNECTED [3:2],\neutral_max_limit_reg[11]_i_1_n_2 ,\neutral_max_limit_reg[11]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\NLW_neutral_max_limit_reg[11]_i_1_O_UNCONNECTED [3],neutral_max_limit_nxt[11:9]}),
        .S({1'b0,device_temp_init[11:9]}));
  FDRE \neutral_max_limit_reg[2] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(neutral_max_limit_nxt[2]),
        .Q(neutral_max_limit[2]),
        .R(\neutral_max_limit_reg[11]_0 ));
  FDRE \neutral_max_limit_reg[3] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(neutral_max_limit_nxt[3]),
        .Q(neutral_max_limit[3]),
        .R(\neutral_max_limit_reg[11]_0 ));
  FDRE \neutral_max_limit_reg[4] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(neutral_max_limit_nxt[4]),
        .Q(neutral_max_limit[4]),
        .R(\neutral_max_limit_reg[11]_0 ));
  CARRY4 \neutral_max_limit_reg[4]_i_1 
       (.CI(1'b0),
        .CO({\neutral_max_limit_reg[4]_i_1_n_0 ,\neutral_max_limit_reg[4]_i_1_n_1 ,\neutral_max_limit_reg[4]_i_1_n_2 ,\neutral_max_limit_reg[4]_i_1_n_3 }),
        .CYINIT(device_temp_init[0]),
        .DI({device_temp_init[4],1'b0,device_temp_init[2:1]}),
        .O({neutral_max_limit_nxt[4:2],\NLW_neutral_max_limit_reg[4]_i_1_O_UNCONNECTED [0]}),
        .S({\neutral_max_limit[4]_i_2_n_0 ,device_temp_init[3],\neutral_max_limit[4]_i_3_n_0 ,\neutral_max_limit[4]_i_4_n_0 }));
  FDRE \neutral_max_limit_reg[5] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(neutral_max_limit_nxt[5]),
        .Q(neutral_max_limit[5]),
        .R(\neutral_max_limit_reg[11]_0 ));
  FDRE \neutral_max_limit_reg[6] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(neutral_max_limit_nxt[6]),
        .Q(neutral_max_limit[6]),
        .R(\neutral_max_limit_reg[11]_0 ));
  FDRE \neutral_max_limit_reg[7] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(neutral_max_limit_nxt[7]),
        .Q(neutral_max_limit[7]),
        .R(\neutral_max_limit_reg[11]_0 ));
  FDRE \neutral_max_limit_reg[8] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(neutral_max_limit_nxt[8]),
        .Q(neutral_max_limit[8]),
        .R(\neutral_max_limit_reg[11]_0 ));
  CARRY4 \neutral_max_limit_reg[8]_i_1 
       (.CI(\neutral_max_limit_reg[4]_i_1_n_0 ),
        .CO({\neutral_max_limit_reg[8]_i_1_n_0 ,\neutral_max_limit_reg[8]_i_1_n_1 ,\neutral_max_limit_reg[8]_i_1_n_2 ,\neutral_max_limit_reg[8]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,device_temp_init[6:5]}),
        .O(neutral_max_limit_nxt[8:5]),
        .S({device_temp_init[8:7],\neutral_max_limit[8]_i_2_n_0 ,\neutral_max_limit[8]_i_3_n_0 }));
  FDRE \neutral_max_limit_reg[9] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(neutral_max_limit_nxt[9]),
        .Q(neutral_max_limit[9]),
        .R(\neutral_max_limit_reg[11]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \neutral_min_limit[11]_i_2 
       (.I0(one_inc_max_limit[11]),
        .O(\neutral_min_limit[11]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \neutral_min_limit[11]_i_3 
       (.I0(one_inc_max_limit[10]),
        .O(\neutral_min_limit[11]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \neutral_min_limit[5]_i_2 
       (.I0(one_inc_max_limit[5]),
        .O(\neutral_min_limit[5]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \neutral_min_limit[5]_i_3 
       (.I0(one_inc_max_limit[4]),
        .O(\neutral_min_limit[5]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \neutral_min_limit[5]_i_4 
       (.I0(one_inc_max_limit[3]),
        .O(\neutral_min_limit[5]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \neutral_min_limit[9]_i_2 
       (.I0(one_inc_max_limit[9]),
        .O(\neutral_min_limit[9]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \neutral_min_limit[9]_i_3 
       (.I0(one_inc_max_limit[8]),
        .O(\neutral_min_limit[9]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \neutral_min_limit[9]_i_4 
       (.I0(one_inc_max_limit[7]),
        .O(\neutral_min_limit[9]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \neutral_min_limit[9]_i_5 
       (.I0(one_inc_max_limit[6]),
        .O(\neutral_min_limit[9]_i_5_n_0 ));
  FDRE \neutral_min_limit_reg[10] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(neutral_min_limit_nxt[10]),
        .Q(neutral_min_limit[10]),
        .R(\four_dec_min_limit_reg[0]_0 ));
  FDRE \neutral_min_limit_reg[11] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(neutral_min_limit_nxt[11]),
        .Q(neutral_min_limit[11]),
        .R(\four_dec_min_limit_reg[0]_0 ));
  CARRY4 \neutral_min_limit_reg[11]_i_1 
       (.CI(\neutral_min_limit_reg[9]_i_1_n_0 ),
        .CO({\NLW_neutral_min_limit_reg[11]_i_1_CO_UNCONNECTED [3:1],\neutral_min_limit_reg[11]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,one_inc_max_limit[10]}),
        .O({\NLW_neutral_min_limit_reg[11]_i_1_O_UNCONNECTED [3:2],neutral_min_limit_nxt[11:10]}),
        .S({1'b0,1'b0,\neutral_min_limit[11]_i_2_n_0 ,\neutral_min_limit[11]_i_3_n_0 }));
  FDRE \neutral_min_limit_reg[2] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(neutral_min_limit_nxt[2]),
        .Q(neutral_min_limit[2]),
        .R(\four_dec_min_limit_reg[0]_0 ));
  FDRE \neutral_min_limit_reg[3] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(neutral_min_limit_nxt[3]),
        .Q(neutral_min_limit[3]),
        .R(\four_dec_min_limit_reg[0]_0 ));
  FDRE \neutral_min_limit_reg[4] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(neutral_min_limit_nxt[4]),
        .Q(neutral_min_limit[4]),
        .R(\four_dec_min_limit_reg[0]_0 ));
  FDRE \neutral_min_limit_reg[5] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(neutral_min_limit_nxt[5]),
        .Q(neutral_min_limit[5]),
        .R(\four_dec_min_limit_reg[0]_0 ));
  CARRY4 \neutral_min_limit_reg[5]_i_1 
       (.CI(1'b0),
        .CO({\neutral_min_limit_reg[5]_i_1_n_0 ,\neutral_min_limit_reg[5]_i_1_n_1 ,\neutral_min_limit_reg[5]_i_1_n_2 ,\neutral_min_limit_reg[5]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({one_inc_max_limit[5:3],1'b0}),
        .O(neutral_min_limit_nxt[5:2]),
        .S({\neutral_min_limit[5]_i_2_n_0 ,\neutral_min_limit[5]_i_3_n_0 ,\neutral_min_limit[5]_i_4_n_0 ,one_inc_max_limit[2]}));
  FDRE \neutral_min_limit_reg[6] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(neutral_min_limit_nxt[6]),
        .Q(neutral_min_limit[6]),
        .R(\four_dec_min_limit_reg[0]_0 ));
  FDRE \neutral_min_limit_reg[7] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(neutral_min_limit_nxt[7]),
        .Q(neutral_min_limit[7]),
        .R(\four_dec_min_limit_reg[0]_0 ));
  FDRE \neutral_min_limit_reg[8] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(neutral_min_limit_nxt[8]),
        .Q(neutral_min_limit[8]),
        .R(\four_dec_min_limit_reg[0]_0 ));
  FDRE \neutral_min_limit_reg[9] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(neutral_min_limit_nxt[9]),
        .Q(neutral_min_limit[9]),
        .R(\four_dec_min_limit_reg[0]_0 ));
  CARRY4 \neutral_min_limit_reg[9]_i_1 
       (.CI(\neutral_min_limit_reg[5]_i_1_n_0 ),
        .CO({\neutral_min_limit_reg[9]_i_1_n_0 ,\neutral_min_limit_reg[9]_i_1_n_1 ,\neutral_min_limit_reg[9]_i_1_n_2 ,\neutral_min_limit_reg[9]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI(one_inc_max_limit[9:6]),
        .O(neutral_min_limit_nxt[9:6]),
        .S({\neutral_min_limit[9]_i_2_n_0 ,\neutral_min_limit[9]_i_3_n_0 ,\neutral_min_limit[9]_i_4_n_0 ,\neutral_min_limit[9]_i_5_n_0 }));
  LUT1 #(
    .INIT(2'h1)) 
    \one_dec_max_limit[4]_i_2 
       (.I0(device_temp_init[2]),
        .O(\one_dec_max_limit[4]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_dec_max_limit[8]_i_2 
       (.I0(device_temp_init[8]),
        .O(\one_dec_max_limit[8]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_dec_max_limit[8]_i_3 
       (.I0(device_temp_init[6]),
        .O(\one_dec_max_limit[8]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_dec_max_limit[8]_i_4 
       (.I0(device_temp_init[5]),
        .O(\one_dec_max_limit[8]_i_4_n_0 ));
  FDRE \one_dec_max_limit_reg[10] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(one_dec_max_limit_nxt[10]),
        .Q(one_dec_max_limit[10]),
        .R(\one_dec_max_limit_reg[2]_0 ));
  FDRE \one_dec_max_limit_reg[11] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(one_dec_max_limit_nxt[11]),
        .Q(one_dec_max_limit[11]),
        .R(\one_dec_max_limit_reg[2]_0 ));
  CARRY4 \one_dec_max_limit_reg[11]_i_1 
       (.CI(\one_dec_max_limit_reg[8]_i_1_n_0 ),
        .CO({\NLW_one_dec_max_limit_reg[11]_i_1_CO_UNCONNECTED [3:2],\one_dec_max_limit_reg[11]_i_1_n_2 ,\one_dec_max_limit_reg[11]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\NLW_one_dec_max_limit_reg[11]_i_1_O_UNCONNECTED [3],one_dec_max_limit_nxt[11:9]}),
        .S({1'b0,device_temp_init[11:9]}));
  FDRE \one_dec_max_limit_reg[2] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(one_dec_max_limit_nxt[2]),
        .Q(one_dec_max_limit[2]),
        .R(\one_dec_max_limit_reg[2]_0 ));
  FDRE \one_dec_max_limit_reg[3] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(one_dec_max_limit_nxt[3]),
        .Q(one_dec_max_limit[3]),
        .R(\one_dec_max_limit_reg[2]_0 ));
  FDRE \one_dec_max_limit_reg[4] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(one_dec_max_limit_nxt[4]),
        .Q(one_dec_max_limit[4]),
        .R(\one_dec_max_limit_reg[2]_0 ));
  CARRY4 \one_dec_max_limit_reg[4]_i_1 
       (.CI(1'b0),
        .CO({\one_dec_max_limit_reg[4]_i_1_n_0 ,\one_dec_max_limit_reg[4]_i_1_n_1 ,\one_dec_max_limit_reg[4]_i_1_n_2 ,\one_dec_max_limit_reg[4]_i_1_n_3 }),
        .CYINIT(device_temp_init[0]),
        .DI({1'b0,1'b0,device_temp_init[2],1'b0}),
        .O({one_dec_max_limit_nxt[4:2],\NLW_one_dec_max_limit_reg[4]_i_1_O_UNCONNECTED [0]}),
        .S({device_temp_init[4:3],\one_dec_max_limit[4]_i_2_n_0 ,device_temp_init[1]}));
  FDRE \one_dec_max_limit_reg[5] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(one_dec_max_limit_nxt[5]),
        .Q(one_dec_max_limit[5]),
        .R(\one_dec_max_limit_reg[2]_0 ));
  FDRE \one_dec_max_limit_reg[6] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(one_dec_max_limit_nxt[6]),
        .Q(one_dec_max_limit[6]),
        .R(\one_dec_max_limit_reg[2]_0 ));
  FDRE \one_dec_max_limit_reg[7] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(one_dec_max_limit_nxt[7]),
        .Q(one_dec_max_limit[7]),
        .R(\one_dec_max_limit_reg[2]_0 ));
  FDRE \one_dec_max_limit_reg[8] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(one_dec_max_limit_nxt[8]),
        .Q(one_dec_max_limit[8]),
        .R(\one_dec_max_limit_reg[2]_0 ));
  CARRY4 \one_dec_max_limit_reg[8]_i_1 
       (.CI(\one_dec_max_limit_reg[4]_i_1_n_0 ),
        .CO({\one_dec_max_limit_reg[8]_i_1_n_0 ,\one_dec_max_limit_reg[8]_i_1_n_1 ,\one_dec_max_limit_reg[8]_i_1_n_2 ,\one_dec_max_limit_reg[8]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({device_temp_init[8],1'b0,device_temp_init[6:5]}),
        .O(one_dec_max_limit_nxt[8:5]),
        .S({\one_dec_max_limit[8]_i_2_n_0 ,device_temp_init[7],\one_dec_max_limit[8]_i_3_n_0 ,\one_dec_max_limit[8]_i_4_n_0 }));
  FDRE \one_dec_max_limit_reg[9] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(one_dec_max_limit_nxt[9]),
        .Q(one_dec_max_limit[9]),
        .R(\one_dec_max_limit_reg[2]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_dec_min_limit[11]_i_2 
       (.I0(neutral_max_limit[11]),
        .O(\one_dec_min_limit[11]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_dec_min_limit[11]_i_3 
       (.I0(neutral_max_limit[10]),
        .O(\one_dec_min_limit[11]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_dec_min_limit[5]_i_2 
       (.I0(neutral_max_limit[5]),
        .O(\one_dec_min_limit[5]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_dec_min_limit[5]_i_3 
       (.I0(neutral_max_limit[4]),
        .O(\one_dec_min_limit[5]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_dec_min_limit[5]_i_4 
       (.I0(neutral_max_limit[3]),
        .O(\one_dec_min_limit[5]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_dec_min_limit[9]_i_2 
       (.I0(neutral_max_limit[9]),
        .O(\one_dec_min_limit[9]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_dec_min_limit[9]_i_3 
       (.I0(neutral_max_limit[8]),
        .O(\one_dec_min_limit[9]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_dec_min_limit[9]_i_4 
       (.I0(neutral_max_limit[7]),
        .O(\one_dec_min_limit[9]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_dec_min_limit[9]_i_5 
       (.I0(neutral_max_limit[6]),
        .O(\one_dec_min_limit[9]_i_5_n_0 ));
  FDRE \one_dec_min_limit_reg[10] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(one_dec_min_limit_nxt[10]),
        .Q(one_dec_min_limit[10]),
        .R(\one_dec_min_limit_reg[11]_0 ));
  FDRE \one_dec_min_limit_reg[11] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(one_dec_min_limit_nxt[11]),
        .Q(one_dec_min_limit[11]),
        .R(\one_dec_min_limit_reg[11]_0 ));
  CARRY4 \one_dec_min_limit_reg[11]_i_1 
       (.CI(\one_dec_min_limit_reg[9]_i_1_n_0 ),
        .CO({\NLW_one_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED [3:1],\one_dec_min_limit_reg[11]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,neutral_max_limit[10]}),
        .O({\NLW_one_dec_min_limit_reg[11]_i_1_O_UNCONNECTED [3:2],one_dec_min_limit_nxt[11:10]}),
        .S({1'b0,1'b0,\one_dec_min_limit[11]_i_2_n_0 ,\one_dec_min_limit[11]_i_3_n_0 }));
  FDRE \one_dec_min_limit_reg[2] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(one_dec_min_limit_nxt[2]),
        .Q(one_dec_min_limit[2]),
        .R(\one_dec_min_limit_reg[11]_0 ));
  FDRE \one_dec_min_limit_reg[3] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(one_dec_min_limit_nxt[3]),
        .Q(one_dec_min_limit[3]),
        .R(\one_dec_min_limit_reg[11]_0 ));
  FDRE \one_dec_min_limit_reg[4] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(one_dec_min_limit_nxt[4]),
        .Q(one_dec_min_limit[4]),
        .R(\one_dec_min_limit_reg[11]_0 ));
  FDRE \one_dec_min_limit_reg[5] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(one_dec_min_limit_nxt[5]),
        .Q(one_dec_min_limit[5]),
        .R(\one_dec_min_limit_reg[11]_0 ));
  CARRY4 \one_dec_min_limit_reg[5]_i_1 
       (.CI(1'b0),
        .CO({\one_dec_min_limit_reg[5]_i_1_n_0 ,\one_dec_min_limit_reg[5]_i_1_n_1 ,\one_dec_min_limit_reg[5]_i_1_n_2 ,\one_dec_min_limit_reg[5]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({neutral_max_limit[5:3],1'b0}),
        .O(one_dec_min_limit_nxt[5:2]),
        .S({\one_dec_min_limit[5]_i_2_n_0 ,\one_dec_min_limit[5]_i_3_n_0 ,\one_dec_min_limit[5]_i_4_n_0 ,neutral_max_limit[2]}));
  FDRE \one_dec_min_limit_reg[6] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(one_dec_min_limit_nxt[6]),
        .Q(one_dec_min_limit[6]),
        .R(\one_dec_min_limit_reg[11]_0 ));
  FDRE \one_dec_min_limit_reg[7] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(one_dec_min_limit_nxt[7]),
        .Q(one_dec_min_limit[7]),
        .R(\one_dec_min_limit_reg[11]_0 ));
  FDRE \one_dec_min_limit_reg[8] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(one_dec_min_limit_nxt[8]),
        .Q(one_dec_min_limit[8]),
        .R(\one_dec_min_limit_reg[11]_0 ));
  FDRE \one_dec_min_limit_reg[9] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(one_dec_min_limit_nxt[9]),
        .Q(one_dec_min_limit[9]),
        .R(\one_dec_min_limit_reg[11]_0 ));
  CARRY4 \one_dec_min_limit_reg[9]_i_1 
       (.CI(\one_dec_min_limit_reg[5]_i_1_n_0 ),
        .CO({\one_dec_min_limit_reg[9]_i_1_n_0 ,\one_dec_min_limit_reg[9]_i_1_n_1 ,\one_dec_min_limit_reg[9]_i_1_n_2 ,\one_dec_min_limit_reg[9]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI(neutral_max_limit[9:6]),
        .O(one_dec_min_limit_nxt[9:6]),
        .S({\one_dec_min_limit[9]_i_2_n_0 ,\one_dec_min_limit[9]_i_3_n_0 ,\one_dec_min_limit[9]_i_4_n_0 ,\one_dec_min_limit[9]_i_5_n_0 }));
  LUT1 #(
    .INIT(2'h1)) 
    \one_inc_max_limit[11]_i_2 
       (.I0(device_temp_init[11]),
        .O(\one_inc_max_limit[11]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_inc_max_limit[11]_i_3 
       (.I0(device_temp_init[10]),
        .O(\one_inc_max_limit[11]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_inc_max_limit[11]_i_4 
       (.I0(device_temp_init[9]),
        .O(\one_inc_max_limit[11]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h6)) 
    \one_inc_max_limit[1]_i_1 
       (.I0(device_temp_init[0]),
        .I1(device_temp_init[1]),
        .O(one_inc_max_limit_nxt[1]));
  LUT1 #(
    .INIT(2'h1)) 
    \one_inc_max_limit[4]_i_2 
       (.I0(device_temp_init[3]),
        .O(\one_inc_max_limit[4]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_inc_max_limit[8]_i_2 
       (.I0(device_temp_init[8]),
        .O(\one_inc_max_limit[8]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_inc_max_limit[8]_i_3 
       (.I0(device_temp_init[7]),
        .O(\one_inc_max_limit[8]_i_3_n_0 ));
  FDRE \one_inc_max_limit_reg[10] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(one_inc_max_limit_nxt[10]),
        .Q(one_inc_max_limit[10]),
        .R(\one_dec_max_limit_reg[2]_0 ));
  FDRE \one_inc_max_limit_reg[11] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(one_inc_max_limit_nxt[11]),
        .Q(one_inc_max_limit[11]),
        .R(\one_dec_max_limit_reg[2]_0 ));
  CARRY4 \one_inc_max_limit_reg[11]_i_1 
       (.CI(\one_inc_max_limit_reg[8]_i_1_n_0 ),
        .CO({\NLW_one_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED [3:2],\one_inc_max_limit_reg[11]_i_1_n_2 ,\one_inc_max_limit_reg[11]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,device_temp_init[10:9]}),
        .O({\NLW_one_inc_max_limit_reg[11]_i_1_O_UNCONNECTED [3],one_inc_max_limit_nxt[11:9]}),
        .S({1'b0,\one_inc_max_limit[11]_i_2_n_0 ,\one_inc_max_limit[11]_i_3_n_0 ,\one_inc_max_limit[11]_i_4_n_0 }));
  FDRE \one_inc_max_limit_reg[1] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(one_inc_max_limit_nxt[1]),
        .Q(one_inc_max_limit[1]),
        .R(\one_dec_max_limit_reg[2]_0 ));
  FDRE \one_inc_max_limit_reg[2] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(one_inc_max_limit_nxt[2]),
        .Q(one_inc_max_limit[2]),
        .R(\one_dec_max_limit_reg[2]_0 ));
  FDRE \one_inc_max_limit_reg[3] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(one_inc_max_limit_nxt[3]),
        .Q(one_inc_max_limit[3]),
        .R(\one_dec_max_limit_reg[2]_0 ));
  FDRE \one_inc_max_limit_reg[4] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(one_inc_max_limit_nxt[4]),
        .Q(one_inc_max_limit[4]),
        .R(\one_dec_max_limit_reg[2]_0 ));
  CARRY4 \one_inc_max_limit_reg[4]_i_1 
       (.CI(1'b0),
        .CO({\one_inc_max_limit_reg[4]_i_1_n_0 ,\one_inc_max_limit_reg[4]_i_1_n_1 ,\one_inc_max_limit_reg[4]_i_1_n_2 ,\one_inc_max_limit_reg[4]_i_1_n_3 }),
        .CYINIT(device_temp_init[0]),
        .DI({1'b0,device_temp_init[3],1'b0,1'b0}),
        .O({one_inc_max_limit_nxt[4:2],\NLW_one_inc_max_limit_reg[4]_i_1_O_UNCONNECTED [0]}),
        .S({device_temp_init[4],\one_inc_max_limit[4]_i_2_n_0 ,device_temp_init[2:1]}));
  FDRE \one_inc_max_limit_reg[5] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(one_inc_max_limit_nxt[5]),
        .Q(one_inc_max_limit[5]),
        .R(\one_dec_max_limit_reg[2]_0 ));
  FDRE \one_inc_max_limit_reg[6] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(one_inc_max_limit_nxt[6]),
        .Q(one_inc_max_limit[6]),
        .R(\one_dec_max_limit_reg[2]_0 ));
  FDRE \one_inc_max_limit_reg[7] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(one_inc_max_limit_nxt[7]),
        .Q(one_inc_max_limit[7]),
        .R(\one_dec_max_limit_reg[2]_0 ));
  FDRE \one_inc_max_limit_reg[8] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(one_inc_max_limit_nxt[8]),
        .Q(one_inc_max_limit[8]),
        .R(\one_dec_max_limit_reg[2]_0 ));
  CARRY4 \one_inc_max_limit_reg[8]_i_1 
       (.CI(\one_inc_max_limit_reg[4]_i_1_n_0 ),
        .CO({\one_inc_max_limit_reg[8]_i_1_n_0 ,\one_inc_max_limit_reg[8]_i_1_n_1 ,\one_inc_max_limit_reg[8]_i_1_n_2 ,\one_inc_max_limit_reg[8]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({device_temp_init[8:7],1'b0,1'b0}),
        .O(one_inc_max_limit_nxt[8:5]),
        .S({\one_inc_max_limit[8]_i_2_n_0 ,\one_inc_max_limit[8]_i_3_n_0 ,device_temp_init[6:5]}));
  FDRE \one_inc_max_limit_reg[9] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(one_inc_max_limit_nxt[9]),
        .Q(one_inc_max_limit[9]),
        .R(\one_dec_max_limit_reg[2]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_inc_min_limit[11]_i_2 
       (.I0(two_inc_max_limit[11]),
        .O(\one_inc_min_limit[11]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_inc_min_limit[11]_i_3 
       (.I0(two_inc_max_limit[10]),
        .O(\one_inc_min_limit[11]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_inc_min_limit[5]_i_2 
       (.I0(two_inc_max_limit[5]),
        .O(\one_inc_min_limit[5]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_inc_min_limit[5]_i_3 
       (.I0(two_inc_max_limit[4]),
        .O(\one_inc_min_limit[5]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_inc_min_limit[5]_i_4 
       (.I0(two_inc_max_limit[3]),
        .O(\one_inc_min_limit[5]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_inc_min_limit[9]_i_2 
       (.I0(two_inc_max_limit[9]),
        .O(\one_inc_min_limit[9]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_inc_min_limit[9]_i_3 
       (.I0(two_inc_max_limit[8]),
        .O(\one_inc_min_limit[9]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_inc_min_limit[9]_i_4 
       (.I0(two_inc_max_limit[7]),
        .O(\one_inc_min_limit[9]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \one_inc_min_limit[9]_i_5 
       (.I0(two_inc_max_limit[6]),
        .O(\one_inc_min_limit[9]_i_5_n_0 ));
  FDRE \one_inc_min_limit_reg[10] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(one_inc_min_limit_nxt[10]),
        .Q(one_inc_min_limit[10]),
        .R(\neutral_max_limit_reg[11]_0 ));
  FDRE \one_inc_min_limit_reg[11] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(one_inc_min_limit_nxt[11]),
        .Q(one_inc_min_limit[11]),
        .R(\neutral_max_limit_reg[11]_0 ));
  CARRY4 \one_inc_min_limit_reg[11]_i_1 
       (.CI(\one_inc_min_limit_reg[9]_i_1_n_0 ),
        .CO({\NLW_one_inc_min_limit_reg[11]_i_1_CO_UNCONNECTED [3:1],\one_inc_min_limit_reg[11]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,two_inc_max_limit[10]}),
        .O({\NLW_one_inc_min_limit_reg[11]_i_1_O_UNCONNECTED [3:2],one_inc_min_limit_nxt[11:10]}),
        .S({1'b0,1'b0,\one_inc_min_limit[11]_i_2_n_0 ,\one_inc_min_limit[11]_i_3_n_0 }));
  FDRE \one_inc_min_limit_reg[1] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(two_inc_max_limit[1]),
        .Q(one_inc_min_limit[1]),
        .R(\neutral_max_limit_reg[11]_0 ));
  FDRE \one_inc_min_limit_reg[2] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(one_inc_min_limit_nxt[2]),
        .Q(one_inc_min_limit[2]),
        .R(\neutral_max_limit_reg[11]_0 ));
  FDRE \one_inc_min_limit_reg[3] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(one_inc_min_limit_nxt[3]),
        .Q(one_inc_min_limit[3]),
        .R(\neutral_max_limit_reg[11]_0 ));
  FDRE \one_inc_min_limit_reg[4] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(one_inc_min_limit_nxt[4]),
        .Q(one_inc_min_limit[4]),
        .R(\neutral_max_limit_reg[11]_0 ));
  FDRE \one_inc_min_limit_reg[5] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(one_inc_min_limit_nxt[5]),
        .Q(one_inc_min_limit[5]),
        .R(\neutral_max_limit_reg[11]_0 ));
  CARRY4 \one_inc_min_limit_reg[5]_i_1 
       (.CI(1'b0),
        .CO({\one_inc_min_limit_reg[5]_i_1_n_0 ,\one_inc_min_limit_reg[5]_i_1_n_1 ,\one_inc_min_limit_reg[5]_i_1_n_2 ,\one_inc_min_limit_reg[5]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({two_inc_max_limit[5:3],1'b0}),
        .O(one_inc_min_limit_nxt[5:2]),
        .S({\one_inc_min_limit[5]_i_2_n_0 ,\one_inc_min_limit[5]_i_3_n_0 ,\one_inc_min_limit[5]_i_4_n_0 ,two_inc_max_limit[2]}));
  FDRE \one_inc_min_limit_reg[6] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(one_inc_min_limit_nxt[6]),
        .Q(one_inc_min_limit[6]),
        .R(\neutral_max_limit_reg[11]_0 ));
  FDRE \one_inc_min_limit_reg[7] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(one_inc_min_limit_nxt[7]),
        .Q(one_inc_min_limit[7]),
        .R(\neutral_max_limit_reg[11]_0 ));
  FDRE \one_inc_min_limit_reg[8] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(one_inc_min_limit_nxt[8]),
        .Q(one_inc_min_limit[8]),
        .R(\neutral_max_limit_reg[11]_0 ));
  FDRE \one_inc_min_limit_reg[9] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(one_inc_min_limit_nxt[9]),
        .Q(one_inc_min_limit[9]),
        .R(\neutral_max_limit_reg[11]_0 ));
  CARRY4 \one_inc_min_limit_reg[9]_i_1 
       (.CI(\one_inc_min_limit_reg[5]_i_1_n_0 ),
        .CO({\one_inc_min_limit_reg[9]_i_1_n_0 ,\one_inc_min_limit_reg[9]_i_1_n_1 ,\one_inc_min_limit_reg[9]_i_1_n_2 ,\one_inc_min_limit_reg[9]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI(two_inc_max_limit[9:6]),
        .O(one_inc_min_limit_nxt[9:6]),
        .S({\one_inc_min_limit[9]_i_2_n_0 ,\one_inc_min_limit[9]_i_3_n_0 ,\one_inc_min_limit[9]_i_4_n_0 ,\one_inc_min_limit[9]_i_5_n_0 }));
  LUT4 #(
    .INIT(16'h8A88)) 
    pi_f_dec_i_1
       (.I0(\tempmon_state[10]_i_6_n_0 ),
        .I1(\tempmon_state[10]_i_5_n_0 ),
        .I2(pi_f_dec_i_2_n_0),
        .I3(update_temp_102),
        .O(pi_f_dec_nxt));
  LUT6 #(
    .INIT(64'h0000077707770777)) 
    pi_f_dec_i_2
       (.I0(tempmon_state[3]),
        .I1(temp_cmp_three_inc_max_102),
        .I2(temp_cmp_two_inc_max_102),
        .I3(tempmon_state[4]),
        .I4(temp_cmp_one_inc_max_102),
        .I5(tempmon_state[5]),
        .O(pi_f_dec_i_2_n_0));
  FDRE pi_f_dec_reg
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(pi_f_dec_nxt),
        .Q(tempmon_pi_f_dec),
        .R(pi_f_dec_reg_1));
  LUT6 #(
    .INIT(64'hFFF7555500000000)) 
    pi_f_inc_i_1
       (.I0(pi_f_inc_i_2_n_0),
        .I1(pi_f_inc_i_3_n_0),
        .I2(pi_f_inc_i_4_n_0),
        .I3(pi_f_inc_i_5_n_0),
        .I4(update_temp_102),
        .I5(\tempmon_state[10]_i_6_n_0 ),
        .O(pi_f_inc_nxt));
  LUT6 #(
    .INIT(64'h00FFF7FFF7FFF7FF)) 
    pi_f_inc_i_2
       (.I0(temp_cmp_one_inc_min_102),
        .I1(tempmon_state[5]),
        .I2(temp_cmp_one_inc_max_102),
        .I3(update_temp_102),
        .I4(temp_cmp_four_dec_min_102),
        .I5(tempmon_state[10]),
        .O(pi_f_inc_i_2_n_0));
  LUT6 #(
    .INIT(64'hF7000000F777F777)) 
    pi_f_inc_i_3
       (.I0(tempmon_state[8]),
        .I1(temp_cmp_two_dec_min_102),
        .I2(temp_cmp_two_dec_max_102),
        .I3(update_temp_102),
        .I4(temp_cmp_one_dec_max_102),
        .I5(pi_f_inc_i_6_n_0),
        .O(pi_f_inc_i_3_n_0));
  LUT6 #(
    .INIT(64'h40FF404040404040)) 
    pi_f_inc_i_4
       (.I0(temp_cmp_three_inc_max_102),
        .I1(tempmon_state[3]),
        .I2(temp_cmp_three_inc_min_102),
        .I3(temp_cmp_two_inc_max_102),
        .I4(tempmon_state[4]),
        .I5(temp_cmp_two_inc_min_102),
        .O(pi_f_inc_i_4_n_0));
  LUT6 #(
    .INIT(64'h0808FF88FF08FF88)) 
    pi_f_inc_i_5
       (.I0(tempmon_state[9]),
        .I1(temp_cmp_three_dec_min_102),
        .I2(temp_cmp_three_dec_max_102),
        .I3(pi_f_inc_i_7_n_0),
        .I4(update_temp_102),
        .I5(temp_cmp_neutral_max_102),
        .O(pi_f_inc_i_5_n_0));
  LUT2 #(
    .INIT(4'h8)) 
    pi_f_inc_i_6
       (.I0(tempmon_state[7]),
        .I1(temp_cmp_one_dec_min_102),
        .O(pi_f_inc_i_6_n_0));
  (* SOFT_HLUTNM = "soft_lutpair234" *) 
  LUT2 #(
    .INIT(4'h8)) 
    pi_f_inc_i_7
       (.I0(tempmon_state[6]),
        .I1(temp_cmp_neutral_min_102),
        .O(pi_f_inc_i_7_n_0));
  FDRE pi_f_inc_reg
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(pi_f_inc_nxt),
        .Q(tempmon_pi_f_inc),
        .R(\four_dec_min_limit_reg[0]_0 ));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_four_dec_min_102_i_10
       (.I0(four_dec_min_limit[0]),
        .I1(device_temp_101[0]),
        .I2(device_temp_101[1]),
        .I3(four_dec_min_limit[1]),
        .O(temp_cmp_four_dec_min_102_i_10_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_four_dec_min_102_i_11
       (.I0(four_dec_min_limit[6]),
        .I1(device_temp_101[6]),
        .I2(four_dec_min_limit[7]),
        .I3(device_temp_101[7]),
        .O(temp_cmp_four_dec_min_102_i_11_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_four_dec_min_102_i_12
       (.I0(four_dec_min_limit[4]),
        .I1(device_temp_101[4]),
        .I2(four_dec_min_limit[5]),
        .I3(device_temp_101[5]),
        .O(temp_cmp_four_dec_min_102_i_12_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_four_dec_min_102_i_13
       (.I0(four_dec_min_limit[2]),
        .I1(device_temp_101[2]),
        .I2(four_dec_min_limit[3]),
        .I3(device_temp_101[3]),
        .O(temp_cmp_four_dec_min_102_i_13_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_four_dec_min_102_i_14
       (.I0(four_dec_min_limit[0]),
        .I1(device_temp_101[0]),
        .I2(four_dec_min_limit[1]),
        .I3(device_temp_101[1]),
        .O(temp_cmp_four_dec_min_102_i_14_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_four_dec_min_102_i_3
       (.I0(four_dec_min_limit[10]),
        .I1(device_temp_101[10]),
        .I2(device_temp_101[11]),
        .I3(four_dec_min_limit[11]),
        .O(temp_cmp_four_dec_min_102_i_3_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_four_dec_min_102_i_4
       (.I0(four_dec_min_limit[8]),
        .I1(device_temp_101[8]),
        .I2(device_temp_101[9]),
        .I3(four_dec_min_limit[9]),
        .O(temp_cmp_four_dec_min_102_i_4_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_four_dec_min_102_i_5
       (.I0(four_dec_min_limit[10]),
        .I1(device_temp_101[10]),
        .I2(four_dec_min_limit[11]),
        .I3(device_temp_101[11]),
        .O(temp_cmp_four_dec_min_102_i_5_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_four_dec_min_102_i_6
       (.I0(four_dec_min_limit[8]),
        .I1(device_temp_101[8]),
        .I2(four_dec_min_limit[9]),
        .I3(device_temp_101[9]),
        .O(temp_cmp_four_dec_min_102_i_6_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_four_dec_min_102_i_7
       (.I0(four_dec_min_limit[6]),
        .I1(device_temp_101[6]),
        .I2(device_temp_101[7]),
        .I3(four_dec_min_limit[7]),
        .O(temp_cmp_four_dec_min_102_i_7_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_four_dec_min_102_i_8
       (.I0(four_dec_min_limit[4]),
        .I1(device_temp_101[4]),
        .I2(device_temp_101[5]),
        .I3(four_dec_min_limit[5]),
        .O(temp_cmp_four_dec_min_102_i_8_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_four_dec_min_102_i_9
       (.I0(four_dec_min_limit[2]),
        .I1(device_temp_101[2]),
        .I2(device_temp_101[3]),
        .I3(four_dec_min_limit[3]),
        .O(temp_cmp_four_dec_min_102_i_9_n_0));
  FDRE temp_cmp_four_dec_min_102_reg
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(temp_cmp_four_dec_min_101),
        .Q(temp_cmp_four_dec_min_102),
        .R(1'b0));
  CARRY4 temp_cmp_four_dec_min_102_reg_i_1
       (.CI(temp_cmp_four_dec_min_102_reg_i_2_n_0),
        .CO({NLW_temp_cmp_four_dec_min_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_four_dec_min_101,temp_cmp_four_dec_min_102_reg_i_1_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,temp_cmp_four_dec_min_102_i_3_n_0,temp_cmp_four_dec_min_102_i_4_n_0}),
        .O(NLW_temp_cmp_four_dec_min_102_reg_i_1_O_UNCONNECTED[3:0]),
        .S({1'b0,1'b0,temp_cmp_four_dec_min_102_i_5_n_0,temp_cmp_four_dec_min_102_i_6_n_0}));
  CARRY4 temp_cmp_four_dec_min_102_reg_i_2
       (.CI(1'b0),
        .CO({temp_cmp_four_dec_min_102_reg_i_2_n_0,temp_cmp_four_dec_min_102_reg_i_2_n_1,temp_cmp_four_dec_min_102_reg_i_2_n_2,temp_cmp_four_dec_min_102_reg_i_2_n_3}),
        .CYINIT(1'b0),
        .DI({temp_cmp_four_dec_min_102_i_7_n_0,temp_cmp_four_dec_min_102_i_8_n_0,temp_cmp_four_dec_min_102_i_9_n_0,temp_cmp_four_dec_min_102_i_10_n_0}),
        .O(NLW_temp_cmp_four_dec_min_102_reg_i_2_O_UNCONNECTED[3:0]),
        .S({temp_cmp_four_dec_min_102_i_11_n_0,temp_cmp_four_dec_min_102_i_12_n_0,temp_cmp_four_dec_min_102_i_13_n_0,temp_cmp_four_dec_min_102_i_14_n_0}));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_four_inc_max_102_i_10
       (.I0(device_temp_101[0]),
        .I1(two_dec_max_limit[0]),
        .I2(two_inc_max_limit[1]),
        .I3(device_temp_101[1]),
        .O(temp_cmp_four_inc_max_102_i_10_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_four_inc_max_102_i_11
       (.I0(device_temp_101[6]),
        .I1(four_inc_max_limit[6]),
        .I2(device_temp_101[7]),
        .I3(four_inc_max_limit[7]),
        .O(temp_cmp_four_inc_max_102_i_11_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_four_inc_max_102_i_12
       (.I0(device_temp_101[4]),
        .I1(four_inc_max_limit[4]),
        .I2(device_temp_101[5]),
        .I3(four_inc_max_limit[5]),
        .O(temp_cmp_four_inc_max_102_i_12_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_four_inc_max_102_i_13
       (.I0(device_temp_101[2]),
        .I1(four_inc_max_limit[2]),
        .I2(device_temp_101[3]),
        .I3(four_inc_max_limit[3]),
        .O(temp_cmp_four_inc_max_102_i_13_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_four_inc_max_102_i_14
       (.I0(device_temp_101[0]),
        .I1(two_dec_max_limit[0]),
        .I2(device_temp_101[1]),
        .I3(two_inc_max_limit[1]),
        .O(temp_cmp_four_inc_max_102_i_14_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_four_inc_max_102_i_3
       (.I0(device_temp_101[10]),
        .I1(four_inc_max_limit[10]),
        .I2(four_inc_max_limit[11]),
        .I3(device_temp_101[11]),
        .O(temp_cmp_four_inc_max_102_i_3_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_four_inc_max_102_i_4
       (.I0(device_temp_101[8]),
        .I1(four_inc_max_limit[8]),
        .I2(four_inc_max_limit[9]),
        .I3(device_temp_101[9]),
        .O(temp_cmp_four_inc_max_102_i_4_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_four_inc_max_102_i_5
       (.I0(device_temp_101[10]),
        .I1(four_inc_max_limit[10]),
        .I2(device_temp_101[11]),
        .I3(four_inc_max_limit[11]),
        .O(temp_cmp_four_inc_max_102_i_5_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_four_inc_max_102_i_6
       (.I0(device_temp_101[8]),
        .I1(four_inc_max_limit[8]),
        .I2(device_temp_101[9]),
        .I3(four_inc_max_limit[9]),
        .O(temp_cmp_four_inc_max_102_i_6_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_four_inc_max_102_i_7
       (.I0(device_temp_101[6]),
        .I1(four_inc_max_limit[6]),
        .I2(four_inc_max_limit[7]),
        .I3(device_temp_101[7]),
        .O(temp_cmp_four_inc_max_102_i_7_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_four_inc_max_102_i_8
       (.I0(device_temp_101[4]),
        .I1(four_inc_max_limit[4]),
        .I2(four_inc_max_limit[5]),
        .I3(device_temp_101[5]),
        .O(temp_cmp_four_inc_max_102_i_8_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_four_inc_max_102_i_9
       (.I0(device_temp_101[2]),
        .I1(four_inc_max_limit[2]),
        .I2(four_inc_max_limit[3]),
        .I3(device_temp_101[3]),
        .O(temp_cmp_four_inc_max_102_i_9_n_0));
  FDRE temp_cmp_four_inc_max_102_reg
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(temp_cmp_four_inc_max_101),
        .Q(temp_cmp_four_inc_max_102),
        .R(1'b0));
  CARRY4 temp_cmp_four_inc_max_102_reg_i_1
       (.CI(temp_cmp_four_inc_max_102_reg_i_2_n_0),
        .CO({NLW_temp_cmp_four_inc_max_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_four_inc_max_101,temp_cmp_four_inc_max_102_reg_i_1_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,temp_cmp_four_inc_max_102_i_3_n_0,temp_cmp_four_inc_max_102_i_4_n_0}),
        .O(NLW_temp_cmp_four_inc_max_102_reg_i_1_O_UNCONNECTED[3:0]),
        .S({1'b0,1'b0,temp_cmp_four_inc_max_102_i_5_n_0,temp_cmp_four_inc_max_102_i_6_n_0}));
  CARRY4 temp_cmp_four_inc_max_102_reg_i_2
       (.CI(1'b0),
        .CO({temp_cmp_four_inc_max_102_reg_i_2_n_0,temp_cmp_four_inc_max_102_reg_i_2_n_1,temp_cmp_four_inc_max_102_reg_i_2_n_2,temp_cmp_four_inc_max_102_reg_i_2_n_3}),
        .CYINIT(1'b1),
        .DI({temp_cmp_four_inc_max_102_i_7_n_0,temp_cmp_four_inc_max_102_i_8_n_0,temp_cmp_four_inc_max_102_i_9_n_0,temp_cmp_four_inc_max_102_i_10_n_0}),
        .O(NLW_temp_cmp_four_inc_max_102_reg_i_2_O_UNCONNECTED[3:0]),
        .S({temp_cmp_four_inc_max_102_i_11_n_0,temp_cmp_four_inc_max_102_i_12_n_0,temp_cmp_four_inc_max_102_i_13_n_0,temp_cmp_four_inc_max_102_i_14_n_0}));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_neutral_max_102_i_10
       (.I0(device_temp_101[0]),
        .I1(two_dec_max_limit[0]),
        .I2(two_inc_max_limit[1]),
        .I3(device_temp_101[1]),
        .O(temp_cmp_neutral_max_102_i_10_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_neutral_max_102_i_11
       (.I0(device_temp_101[6]),
        .I1(neutral_max_limit[6]),
        .I2(device_temp_101[7]),
        .I3(neutral_max_limit[7]),
        .O(temp_cmp_neutral_max_102_i_11_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_neutral_max_102_i_12
       (.I0(device_temp_101[4]),
        .I1(neutral_max_limit[4]),
        .I2(device_temp_101[5]),
        .I3(neutral_max_limit[5]),
        .O(temp_cmp_neutral_max_102_i_12_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_neutral_max_102_i_13
       (.I0(device_temp_101[2]),
        .I1(neutral_max_limit[2]),
        .I2(device_temp_101[3]),
        .I3(neutral_max_limit[3]),
        .O(temp_cmp_neutral_max_102_i_13_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_neutral_max_102_i_14
       (.I0(device_temp_101[0]),
        .I1(two_dec_max_limit[0]),
        .I2(device_temp_101[1]),
        .I3(two_inc_max_limit[1]),
        .O(temp_cmp_neutral_max_102_i_14_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_neutral_max_102_i_3
       (.I0(device_temp_101[10]),
        .I1(neutral_max_limit[10]),
        .I2(neutral_max_limit[11]),
        .I3(device_temp_101[11]),
        .O(temp_cmp_neutral_max_102_i_3_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_neutral_max_102_i_4
       (.I0(device_temp_101[8]),
        .I1(neutral_max_limit[8]),
        .I2(neutral_max_limit[9]),
        .I3(device_temp_101[9]),
        .O(temp_cmp_neutral_max_102_i_4_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_neutral_max_102_i_5
       (.I0(device_temp_101[10]),
        .I1(neutral_max_limit[10]),
        .I2(device_temp_101[11]),
        .I3(neutral_max_limit[11]),
        .O(temp_cmp_neutral_max_102_i_5_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_neutral_max_102_i_6
       (.I0(device_temp_101[8]),
        .I1(neutral_max_limit[8]),
        .I2(device_temp_101[9]),
        .I3(neutral_max_limit[9]),
        .O(temp_cmp_neutral_max_102_i_6_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_neutral_max_102_i_7
       (.I0(device_temp_101[6]),
        .I1(neutral_max_limit[6]),
        .I2(neutral_max_limit[7]),
        .I3(device_temp_101[7]),
        .O(temp_cmp_neutral_max_102_i_7_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_neutral_max_102_i_8
       (.I0(device_temp_101[4]),
        .I1(neutral_max_limit[4]),
        .I2(neutral_max_limit[5]),
        .I3(device_temp_101[5]),
        .O(temp_cmp_neutral_max_102_i_8_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_neutral_max_102_i_9
       (.I0(device_temp_101[2]),
        .I1(neutral_max_limit[2]),
        .I2(neutral_max_limit[3]),
        .I3(device_temp_101[3]),
        .O(temp_cmp_neutral_max_102_i_9_n_0));
  FDRE temp_cmp_neutral_max_102_reg
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(temp_cmp_neutral_max_101),
        .Q(temp_cmp_neutral_max_102),
        .R(1'b0));
  CARRY4 temp_cmp_neutral_max_102_reg_i_1
       (.CI(temp_cmp_neutral_max_102_reg_i_2_n_0),
        .CO({NLW_temp_cmp_neutral_max_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_neutral_max_101,temp_cmp_neutral_max_102_reg_i_1_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,temp_cmp_neutral_max_102_i_3_n_0,temp_cmp_neutral_max_102_i_4_n_0}),
        .O(NLW_temp_cmp_neutral_max_102_reg_i_1_O_UNCONNECTED[3:0]),
        .S({1'b0,1'b0,temp_cmp_neutral_max_102_i_5_n_0,temp_cmp_neutral_max_102_i_6_n_0}));
  CARRY4 temp_cmp_neutral_max_102_reg_i_2
       (.CI(1'b0),
        .CO({temp_cmp_neutral_max_102_reg_i_2_n_0,temp_cmp_neutral_max_102_reg_i_2_n_1,temp_cmp_neutral_max_102_reg_i_2_n_2,temp_cmp_neutral_max_102_reg_i_2_n_3}),
        .CYINIT(1'b1),
        .DI({temp_cmp_neutral_max_102_i_7_n_0,temp_cmp_neutral_max_102_i_8_n_0,temp_cmp_neutral_max_102_i_9_n_0,temp_cmp_neutral_max_102_i_10_n_0}),
        .O(NLW_temp_cmp_neutral_max_102_reg_i_2_O_UNCONNECTED[3:0]),
        .S({temp_cmp_neutral_max_102_i_11_n_0,temp_cmp_neutral_max_102_i_12_n_0,temp_cmp_neutral_max_102_i_13_n_0,temp_cmp_neutral_max_102_i_14_n_0}));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_neutral_min_102_i_10
       (.I0(three_dec_min_limit[0]),
        .I1(device_temp_101[0]),
        .I2(device_temp_101[1]),
        .I3(two_inc_min_limit[1]),
        .O(temp_cmp_neutral_min_102_i_10_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_neutral_min_102_i_11
       (.I0(neutral_min_limit[6]),
        .I1(device_temp_101[6]),
        .I2(neutral_min_limit[7]),
        .I3(device_temp_101[7]),
        .O(temp_cmp_neutral_min_102_i_11_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_neutral_min_102_i_12
       (.I0(neutral_min_limit[4]),
        .I1(device_temp_101[4]),
        .I2(neutral_min_limit[5]),
        .I3(device_temp_101[5]),
        .O(temp_cmp_neutral_min_102_i_12_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_neutral_min_102_i_13
       (.I0(neutral_min_limit[2]),
        .I1(device_temp_101[2]),
        .I2(neutral_min_limit[3]),
        .I3(device_temp_101[3]),
        .O(temp_cmp_neutral_min_102_i_13_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_neutral_min_102_i_14
       (.I0(three_dec_min_limit[0]),
        .I1(device_temp_101[0]),
        .I2(two_inc_min_limit[1]),
        .I3(device_temp_101[1]),
        .O(temp_cmp_neutral_min_102_i_14_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_neutral_min_102_i_3
       (.I0(neutral_min_limit[10]),
        .I1(device_temp_101[10]),
        .I2(device_temp_101[11]),
        .I3(neutral_min_limit[11]),
        .O(temp_cmp_neutral_min_102_i_3_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_neutral_min_102_i_4
       (.I0(neutral_min_limit[8]),
        .I1(device_temp_101[8]),
        .I2(device_temp_101[9]),
        .I3(neutral_min_limit[9]),
        .O(temp_cmp_neutral_min_102_i_4_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_neutral_min_102_i_5
       (.I0(neutral_min_limit[10]),
        .I1(device_temp_101[10]),
        .I2(neutral_min_limit[11]),
        .I3(device_temp_101[11]),
        .O(temp_cmp_neutral_min_102_i_5_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_neutral_min_102_i_6
       (.I0(neutral_min_limit[8]),
        .I1(device_temp_101[8]),
        .I2(neutral_min_limit[9]),
        .I3(device_temp_101[9]),
        .O(temp_cmp_neutral_min_102_i_6_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_neutral_min_102_i_7
       (.I0(neutral_min_limit[6]),
        .I1(device_temp_101[6]),
        .I2(device_temp_101[7]),
        .I3(neutral_min_limit[7]),
        .O(temp_cmp_neutral_min_102_i_7_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_neutral_min_102_i_8
       (.I0(neutral_min_limit[4]),
        .I1(device_temp_101[4]),
        .I2(device_temp_101[5]),
        .I3(neutral_min_limit[5]),
        .O(temp_cmp_neutral_min_102_i_8_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_neutral_min_102_i_9
       (.I0(neutral_min_limit[2]),
        .I1(device_temp_101[2]),
        .I2(device_temp_101[3]),
        .I3(neutral_min_limit[3]),
        .O(temp_cmp_neutral_min_102_i_9_n_0));
  FDRE temp_cmp_neutral_min_102_reg
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(temp_cmp_neutral_min_101),
        .Q(temp_cmp_neutral_min_102),
        .R(1'b0));
  CARRY4 temp_cmp_neutral_min_102_reg_i_1
       (.CI(temp_cmp_neutral_min_102_reg_i_2_n_0),
        .CO({NLW_temp_cmp_neutral_min_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_neutral_min_101,temp_cmp_neutral_min_102_reg_i_1_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,temp_cmp_neutral_min_102_i_3_n_0,temp_cmp_neutral_min_102_i_4_n_0}),
        .O(NLW_temp_cmp_neutral_min_102_reg_i_1_O_UNCONNECTED[3:0]),
        .S({1'b0,1'b0,temp_cmp_neutral_min_102_i_5_n_0,temp_cmp_neutral_min_102_i_6_n_0}));
  CARRY4 temp_cmp_neutral_min_102_reg_i_2
       (.CI(1'b0),
        .CO({temp_cmp_neutral_min_102_reg_i_2_n_0,temp_cmp_neutral_min_102_reg_i_2_n_1,temp_cmp_neutral_min_102_reg_i_2_n_2,temp_cmp_neutral_min_102_reg_i_2_n_3}),
        .CYINIT(1'b0),
        .DI({temp_cmp_neutral_min_102_i_7_n_0,temp_cmp_neutral_min_102_i_8_n_0,temp_cmp_neutral_min_102_i_9_n_0,temp_cmp_neutral_min_102_i_10_n_0}),
        .O(NLW_temp_cmp_neutral_min_102_reg_i_2_O_UNCONNECTED[3:0]),
        .S({temp_cmp_neutral_min_102_i_11_n_0,temp_cmp_neutral_min_102_i_12_n_0,temp_cmp_neutral_min_102_i_13_n_0,temp_cmp_neutral_min_102_i_14_n_0}));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_one_dec_max_102_i_10
       (.I0(device_temp_101[0]),
        .I1(two_dec_max_limit[0]),
        .I2(one_inc_max_limit[1]),
        .I3(device_temp_101[1]),
        .O(temp_cmp_one_dec_max_102_i_10_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_one_dec_max_102_i_11
       (.I0(device_temp_101[6]),
        .I1(one_dec_max_limit[6]),
        .I2(device_temp_101[7]),
        .I3(one_dec_max_limit[7]),
        .O(temp_cmp_one_dec_max_102_i_11_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_one_dec_max_102_i_12
       (.I0(device_temp_101[4]),
        .I1(one_dec_max_limit[4]),
        .I2(device_temp_101[5]),
        .I3(one_dec_max_limit[5]),
        .O(temp_cmp_one_dec_max_102_i_12_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_one_dec_max_102_i_13
       (.I0(device_temp_101[2]),
        .I1(one_dec_max_limit[2]),
        .I2(device_temp_101[3]),
        .I3(one_dec_max_limit[3]),
        .O(temp_cmp_one_dec_max_102_i_13_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_one_dec_max_102_i_14
       (.I0(device_temp_101[0]),
        .I1(two_dec_max_limit[0]),
        .I2(device_temp_101[1]),
        .I3(one_inc_max_limit[1]),
        .O(temp_cmp_one_dec_max_102_i_14_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_one_dec_max_102_i_3
       (.I0(device_temp_101[10]),
        .I1(one_dec_max_limit[10]),
        .I2(one_dec_max_limit[11]),
        .I3(device_temp_101[11]),
        .O(temp_cmp_one_dec_max_102_i_3_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_one_dec_max_102_i_4
       (.I0(device_temp_101[8]),
        .I1(one_dec_max_limit[8]),
        .I2(one_dec_max_limit[9]),
        .I3(device_temp_101[9]),
        .O(temp_cmp_one_dec_max_102_i_4_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_one_dec_max_102_i_5
       (.I0(device_temp_101[10]),
        .I1(one_dec_max_limit[10]),
        .I2(device_temp_101[11]),
        .I3(one_dec_max_limit[11]),
        .O(temp_cmp_one_dec_max_102_i_5_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_one_dec_max_102_i_6
       (.I0(device_temp_101[8]),
        .I1(one_dec_max_limit[8]),
        .I2(device_temp_101[9]),
        .I3(one_dec_max_limit[9]),
        .O(temp_cmp_one_dec_max_102_i_6_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_one_dec_max_102_i_7
       (.I0(device_temp_101[6]),
        .I1(one_dec_max_limit[6]),
        .I2(one_dec_max_limit[7]),
        .I3(device_temp_101[7]),
        .O(temp_cmp_one_dec_max_102_i_7_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_one_dec_max_102_i_8
       (.I0(device_temp_101[4]),
        .I1(one_dec_max_limit[4]),
        .I2(one_dec_max_limit[5]),
        .I3(device_temp_101[5]),
        .O(temp_cmp_one_dec_max_102_i_8_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_one_dec_max_102_i_9
       (.I0(device_temp_101[2]),
        .I1(one_dec_max_limit[2]),
        .I2(one_dec_max_limit[3]),
        .I3(device_temp_101[3]),
        .O(temp_cmp_one_dec_max_102_i_9_n_0));
  FDRE temp_cmp_one_dec_max_102_reg
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(temp_cmp_one_dec_max_101),
        .Q(temp_cmp_one_dec_max_102),
        .R(1'b0));
  CARRY4 temp_cmp_one_dec_max_102_reg_i_1
       (.CI(temp_cmp_one_dec_max_102_reg_i_2_n_0),
        .CO({NLW_temp_cmp_one_dec_max_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_one_dec_max_101,temp_cmp_one_dec_max_102_reg_i_1_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,temp_cmp_one_dec_max_102_i_3_n_0,temp_cmp_one_dec_max_102_i_4_n_0}),
        .O(NLW_temp_cmp_one_dec_max_102_reg_i_1_O_UNCONNECTED[3:0]),
        .S({1'b0,1'b0,temp_cmp_one_dec_max_102_i_5_n_0,temp_cmp_one_dec_max_102_i_6_n_0}));
  CARRY4 temp_cmp_one_dec_max_102_reg_i_2
       (.CI(1'b0),
        .CO({temp_cmp_one_dec_max_102_reg_i_2_n_0,temp_cmp_one_dec_max_102_reg_i_2_n_1,temp_cmp_one_dec_max_102_reg_i_2_n_2,temp_cmp_one_dec_max_102_reg_i_2_n_3}),
        .CYINIT(1'b1),
        .DI({temp_cmp_one_dec_max_102_i_7_n_0,temp_cmp_one_dec_max_102_i_8_n_0,temp_cmp_one_dec_max_102_i_9_n_0,temp_cmp_one_dec_max_102_i_10_n_0}),
        .O(NLW_temp_cmp_one_dec_max_102_reg_i_2_O_UNCONNECTED[3:0]),
        .S({temp_cmp_one_dec_max_102_i_11_n_0,temp_cmp_one_dec_max_102_i_12_n_0,temp_cmp_one_dec_max_102_i_13_n_0,temp_cmp_one_dec_max_102_i_14_n_0}));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_one_dec_min_102_i_10
       (.I0(three_dec_min_limit[0]),
        .I1(device_temp_101[0]),
        .I2(device_temp_101[1]),
        .I3(one_inc_min_limit[1]),
        .O(temp_cmp_one_dec_min_102_i_10_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_one_dec_min_102_i_11
       (.I0(one_dec_min_limit[6]),
        .I1(device_temp_101[6]),
        .I2(one_dec_min_limit[7]),
        .I3(device_temp_101[7]),
        .O(temp_cmp_one_dec_min_102_i_11_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_one_dec_min_102_i_12
       (.I0(one_dec_min_limit[4]),
        .I1(device_temp_101[4]),
        .I2(one_dec_min_limit[5]),
        .I3(device_temp_101[5]),
        .O(temp_cmp_one_dec_min_102_i_12_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_one_dec_min_102_i_13
       (.I0(one_dec_min_limit[2]),
        .I1(device_temp_101[2]),
        .I2(one_dec_min_limit[3]),
        .I3(device_temp_101[3]),
        .O(temp_cmp_one_dec_min_102_i_13_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_one_dec_min_102_i_14
       (.I0(three_dec_min_limit[0]),
        .I1(device_temp_101[0]),
        .I2(one_inc_min_limit[1]),
        .I3(device_temp_101[1]),
        .O(temp_cmp_one_dec_min_102_i_14_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_one_dec_min_102_i_3
       (.I0(one_dec_min_limit[10]),
        .I1(device_temp_101[10]),
        .I2(device_temp_101[11]),
        .I3(one_dec_min_limit[11]),
        .O(temp_cmp_one_dec_min_102_i_3_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_one_dec_min_102_i_4
       (.I0(one_dec_min_limit[8]),
        .I1(device_temp_101[8]),
        .I2(device_temp_101[9]),
        .I3(one_dec_min_limit[9]),
        .O(temp_cmp_one_dec_min_102_i_4_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_one_dec_min_102_i_5
       (.I0(one_dec_min_limit[10]),
        .I1(device_temp_101[10]),
        .I2(one_dec_min_limit[11]),
        .I3(device_temp_101[11]),
        .O(temp_cmp_one_dec_min_102_i_5_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_one_dec_min_102_i_6
       (.I0(one_dec_min_limit[8]),
        .I1(device_temp_101[8]),
        .I2(one_dec_min_limit[9]),
        .I3(device_temp_101[9]),
        .O(temp_cmp_one_dec_min_102_i_6_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_one_dec_min_102_i_7
       (.I0(one_dec_min_limit[6]),
        .I1(device_temp_101[6]),
        .I2(device_temp_101[7]),
        .I3(one_dec_min_limit[7]),
        .O(temp_cmp_one_dec_min_102_i_7_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_one_dec_min_102_i_8
       (.I0(one_dec_min_limit[4]),
        .I1(device_temp_101[4]),
        .I2(device_temp_101[5]),
        .I3(one_dec_min_limit[5]),
        .O(temp_cmp_one_dec_min_102_i_8_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_one_dec_min_102_i_9
       (.I0(one_dec_min_limit[2]),
        .I1(device_temp_101[2]),
        .I2(device_temp_101[3]),
        .I3(one_dec_min_limit[3]),
        .O(temp_cmp_one_dec_min_102_i_9_n_0));
  FDRE temp_cmp_one_dec_min_102_reg
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(temp_cmp_one_dec_min_101),
        .Q(temp_cmp_one_dec_min_102),
        .R(1'b0));
  CARRY4 temp_cmp_one_dec_min_102_reg_i_1
       (.CI(temp_cmp_one_dec_min_102_reg_i_2_n_0),
        .CO({NLW_temp_cmp_one_dec_min_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_one_dec_min_101,temp_cmp_one_dec_min_102_reg_i_1_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,temp_cmp_one_dec_min_102_i_3_n_0,temp_cmp_one_dec_min_102_i_4_n_0}),
        .O(NLW_temp_cmp_one_dec_min_102_reg_i_1_O_UNCONNECTED[3:0]),
        .S({1'b0,1'b0,temp_cmp_one_dec_min_102_i_5_n_0,temp_cmp_one_dec_min_102_i_6_n_0}));
  CARRY4 temp_cmp_one_dec_min_102_reg_i_2
       (.CI(1'b0),
        .CO({temp_cmp_one_dec_min_102_reg_i_2_n_0,temp_cmp_one_dec_min_102_reg_i_2_n_1,temp_cmp_one_dec_min_102_reg_i_2_n_2,temp_cmp_one_dec_min_102_reg_i_2_n_3}),
        .CYINIT(1'b0),
        .DI({temp_cmp_one_dec_min_102_i_7_n_0,temp_cmp_one_dec_min_102_i_8_n_0,temp_cmp_one_dec_min_102_i_9_n_0,temp_cmp_one_dec_min_102_i_10_n_0}),
        .O(NLW_temp_cmp_one_dec_min_102_reg_i_2_O_UNCONNECTED[3:0]),
        .S({temp_cmp_one_dec_min_102_i_11_n_0,temp_cmp_one_dec_min_102_i_12_n_0,temp_cmp_one_dec_min_102_i_13_n_0,temp_cmp_one_dec_min_102_i_14_n_0}));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_one_inc_max_102_i_10
       (.I0(device_temp_101[0]),
        .I1(two_dec_max_limit[0]),
        .I2(one_inc_max_limit[1]),
        .I3(device_temp_101[1]),
        .O(temp_cmp_one_inc_max_102_i_10_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_one_inc_max_102_i_11
       (.I0(device_temp_101[6]),
        .I1(one_inc_max_limit[6]),
        .I2(device_temp_101[7]),
        .I3(one_inc_max_limit[7]),
        .O(temp_cmp_one_inc_max_102_i_11_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_one_inc_max_102_i_12
       (.I0(device_temp_101[4]),
        .I1(one_inc_max_limit[4]),
        .I2(device_temp_101[5]),
        .I3(one_inc_max_limit[5]),
        .O(temp_cmp_one_inc_max_102_i_12_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_one_inc_max_102_i_13
       (.I0(device_temp_101[2]),
        .I1(one_inc_max_limit[2]),
        .I2(device_temp_101[3]),
        .I3(one_inc_max_limit[3]),
        .O(temp_cmp_one_inc_max_102_i_13_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_one_inc_max_102_i_14
       (.I0(device_temp_101[0]),
        .I1(two_dec_max_limit[0]),
        .I2(device_temp_101[1]),
        .I3(one_inc_max_limit[1]),
        .O(temp_cmp_one_inc_max_102_i_14_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_one_inc_max_102_i_3
       (.I0(device_temp_101[10]),
        .I1(one_inc_max_limit[10]),
        .I2(one_inc_max_limit[11]),
        .I3(device_temp_101[11]),
        .O(temp_cmp_one_inc_max_102_i_3_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_one_inc_max_102_i_4
       (.I0(device_temp_101[8]),
        .I1(one_inc_max_limit[8]),
        .I2(one_inc_max_limit[9]),
        .I3(device_temp_101[9]),
        .O(temp_cmp_one_inc_max_102_i_4_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_one_inc_max_102_i_5
       (.I0(device_temp_101[10]),
        .I1(one_inc_max_limit[10]),
        .I2(device_temp_101[11]),
        .I3(one_inc_max_limit[11]),
        .O(temp_cmp_one_inc_max_102_i_5_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_one_inc_max_102_i_6
       (.I0(device_temp_101[8]),
        .I1(one_inc_max_limit[8]),
        .I2(device_temp_101[9]),
        .I3(one_inc_max_limit[9]),
        .O(temp_cmp_one_inc_max_102_i_6_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_one_inc_max_102_i_7
       (.I0(device_temp_101[6]),
        .I1(one_inc_max_limit[6]),
        .I2(one_inc_max_limit[7]),
        .I3(device_temp_101[7]),
        .O(temp_cmp_one_inc_max_102_i_7_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_one_inc_max_102_i_8
       (.I0(device_temp_101[4]),
        .I1(one_inc_max_limit[4]),
        .I2(one_inc_max_limit[5]),
        .I3(device_temp_101[5]),
        .O(temp_cmp_one_inc_max_102_i_8_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_one_inc_max_102_i_9
       (.I0(device_temp_101[2]),
        .I1(one_inc_max_limit[2]),
        .I2(one_inc_max_limit[3]),
        .I3(device_temp_101[3]),
        .O(temp_cmp_one_inc_max_102_i_9_n_0));
  FDRE temp_cmp_one_inc_max_102_reg
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(temp_cmp_one_inc_max_101),
        .Q(temp_cmp_one_inc_max_102),
        .R(1'b0));
  CARRY4 temp_cmp_one_inc_max_102_reg_i_1
       (.CI(temp_cmp_one_inc_max_102_reg_i_2_n_0),
        .CO({NLW_temp_cmp_one_inc_max_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_one_inc_max_101,temp_cmp_one_inc_max_102_reg_i_1_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,temp_cmp_one_inc_max_102_i_3_n_0,temp_cmp_one_inc_max_102_i_4_n_0}),
        .O(NLW_temp_cmp_one_inc_max_102_reg_i_1_O_UNCONNECTED[3:0]),
        .S({1'b0,1'b0,temp_cmp_one_inc_max_102_i_5_n_0,temp_cmp_one_inc_max_102_i_6_n_0}));
  CARRY4 temp_cmp_one_inc_max_102_reg_i_2
       (.CI(1'b0),
        .CO({temp_cmp_one_inc_max_102_reg_i_2_n_0,temp_cmp_one_inc_max_102_reg_i_2_n_1,temp_cmp_one_inc_max_102_reg_i_2_n_2,temp_cmp_one_inc_max_102_reg_i_2_n_3}),
        .CYINIT(1'b1),
        .DI({temp_cmp_one_inc_max_102_i_7_n_0,temp_cmp_one_inc_max_102_i_8_n_0,temp_cmp_one_inc_max_102_i_9_n_0,temp_cmp_one_inc_max_102_i_10_n_0}),
        .O(NLW_temp_cmp_one_inc_max_102_reg_i_2_O_UNCONNECTED[3:0]),
        .S({temp_cmp_one_inc_max_102_i_11_n_0,temp_cmp_one_inc_max_102_i_12_n_0,temp_cmp_one_inc_max_102_i_13_n_0,temp_cmp_one_inc_max_102_i_14_n_0}));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_one_inc_min_102_i_10
       (.I0(three_dec_min_limit[0]),
        .I1(device_temp_101[0]),
        .I2(device_temp_101[1]),
        .I3(one_inc_min_limit[1]),
        .O(temp_cmp_one_inc_min_102_i_10_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_one_inc_min_102_i_11
       (.I0(one_inc_min_limit[6]),
        .I1(device_temp_101[6]),
        .I2(one_inc_min_limit[7]),
        .I3(device_temp_101[7]),
        .O(temp_cmp_one_inc_min_102_i_11_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_one_inc_min_102_i_12
       (.I0(one_inc_min_limit[4]),
        .I1(device_temp_101[4]),
        .I2(one_inc_min_limit[5]),
        .I3(device_temp_101[5]),
        .O(temp_cmp_one_inc_min_102_i_12_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_one_inc_min_102_i_13
       (.I0(one_inc_min_limit[2]),
        .I1(device_temp_101[2]),
        .I2(one_inc_min_limit[3]),
        .I3(device_temp_101[3]),
        .O(temp_cmp_one_inc_min_102_i_13_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_one_inc_min_102_i_14
       (.I0(three_dec_min_limit[0]),
        .I1(device_temp_101[0]),
        .I2(one_inc_min_limit[1]),
        .I3(device_temp_101[1]),
        .O(temp_cmp_one_inc_min_102_i_14_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_one_inc_min_102_i_3
       (.I0(one_inc_min_limit[10]),
        .I1(device_temp_101[10]),
        .I2(device_temp_101[11]),
        .I3(one_inc_min_limit[11]),
        .O(temp_cmp_one_inc_min_102_i_3_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_one_inc_min_102_i_4
       (.I0(one_inc_min_limit[8]),
        .I1(device_temp_101[8]),
        .I2(device_temp_101[9]),
        .I3(one_inc_min_limit[9]),
        .O(temp_cmp_one_inc_min_102_i_4_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_one_inc_min_102_i_5
       (.I0(one_inc_min_limit[10]),
        .I1(device_temp_101[10]),
        .I2(one_inc_min_limit[11]),
        .I3(device_temp_101[11]),
        .O(temp_cmp_one_inc_min_102_i_5_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_one_inc_min_102_i_6
       (.I0(one_inc_min_limit[8]),
        .I1(device_temp_101[8]),
        .I2(one_inc_min_limit[9]),
        .I3(device_temp_101[9]),
        .O(temp_cmp_one_inc_min_102_i_6_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_one_inc_min_102_i_7
       (.I0(one_inc_min_limit[6]),
        .I1(device_temp_101[6]),
        .I2(device_temp_101[7]),
        .I3(one_inc_min_limit[7]),
        .O(temp_cmp_one_inc_min_102_i_7_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_one_inc_min_102_i_8
       (.I0(one_inc_min_limit[4]),
        .I1(device_temp_101[4]),
        .I2(device_temp_101[5]),
        .I3(one_inc_min_limit[5]),
        .O(temp_cmp_one_inc_min_102_i_8_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_one_inc_min_102_i_9
       (.I0(one_inc_min_limit[2]),
        .I1(device_temp_101[2]),
        .I2(device_temp_101[3]),
        .I3(one_inc_min_limit[3]),
        .O(temp_cmp_one_inc_min_102_i_9_n_0));
  FDRE temp_cmp_one_inc_min_102_reg
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(temp_cmp_one_inc_min_101),
        .Q(temp_cmp_one_inc_min_102),
        .R(1'b0));
  CARRY4 temp_cmp_one_inc_min_102_reg_i_1
       (.CI(temp_cmp_one_inc_min_102_reg_i_2_n_0),
        .CO({NLW_temp_cmp_one_inc_min_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_one_inc_min_101,temp_cmp_one_inc_min_102_reg_i_1_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,temp_cmp_one_inc_min_102_i_3_n_0,temp_cmp_one_inc_min_102_i_4_n_0}),
        .O(NLW_temp_cmp_one_inc_min_102_reg_i_1_O_UNCONNECTED[3:0]),
        .S({1'b0,1'b0,temp_cmp_one_inc_min_102_i_5_n_0,temp_cmp_one_inc_min_102_i_6_n_0}));
  CARRY4 temp_cmp_one_inc_min_102_reg_i_2
       (.CI(1'b0),
        .CO({temp_cmp_one_inc_min_102_reg_i_2_n_0,temp_cmp_one_inc_min_102_reg_i_2_n_1,temp_cmp_one_inc_min_102_reg_i_2_n_2,temp_cmp_one_inc_min_102_reg_i_2_n_3}),
        .CYINIT(1'b0),
        .DI({temp_cmp_one_inc_min_102_i_7_n_0,temp_cmp_one_inc_min_102_i_8_n_0,temp_cmp_one_inc_min_102_i_9_n_0,temp_cmp_one_inc_min_102_i_10_n_0}),
        .O(NLW_temp_cmp_one_inc_min_102_reg_i_2_O_UNCONNECTED[3:0]),
        .S({temp_cmp_one_inc_min_102_i_11_n_0,temp_cmp_one_inc_min_102_i_12_n_0,temp_cmp_one_inc_min_102_i_13_n_0,temp_cmp_one_inc_min_102_i_14_n_0}));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_three_dec_max_102_i_10
       (.I0(device_temp_101[0]),
        .I1(three_dec_max_limit[0]),
        .I2(three_dec_max_limit[1]),
        .I3(device_temp_101[1]),
        .O(temp_cmp_three_dec_max_102_i_10_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_three_dec_max_102_i_11
       (.I0(device_temp_101[6]),
        .I1(three_dec_max_limit[6]),
        .I2(device_temp_101[7]),
        .I3(three_dec_max_limit[7]),
        .O(temp_cmp_three_dec_max_102_i_11_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_three_dec_max_102_i_12
       (.I0(device_temp_101[4]),
        .I1(three_dec_max_limit[4]),
        .I2(device_temp_101[5]),
        .I3(three_dec_max_limit[5]),
        .O(temp_cmp_three_dec_max_102_i_12_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_three_dec_max_102_i_13
       (.I0(device_temp_101[2]),
        .I1(three_dec_max_limit[2]),
        .I2(device_temp_101[3]),
        .I3(three_dec_max_limit[3]),
        .O(temp_cmp_three_dec_max_102_i_13_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_three_dec_max_102_i_14
       (.I0(device_temp_101[0]),
        .I1(three_dec_max_limit[0]),
        .I2(device_temp_101[1]),
        .I3(three_dec_max_limit[1]),
        .O(temp_cmp_three_dec_max_102_i_14_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_three_dec_max_102_i_3
       (.I0(device_temp_101[10]),
        .I1(three_dec_max_limit[10]),
        .I2(three_dec_max_limit[11]),
        .I3(device_temp_101[11]),
        .O(temp_cmp_three_dec_max_102_i_3_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_three_dec_max_102_i_4
       (.I0(device_temp_101[8]),
        .I1(three_dec_max_limit[8]),
        .I2(three_dec_max_limit[9]),
        .I3(device_temp_101[9]),
        .O(temp_cmp_three_dec_max_102_i_4_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_three_dec_max_102_i_5
       (.I0(device_temp_101[10]),
        .I1(three_dec_max_limit[10]),
        .I2(device_temp_101[11]),
        .I3(three_dec_max_limit[11]),
        .O(temp_cmp_three_dec_max_102_i_5_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_three_dec_max_102_i_6
       (.I0(device_temp_101[8]),
        .I1(three_dec_max_limit[8]),
        .I2(device_temp_101[9]),
        .I3(three_dec_max_limit[9]),
        .O(temp_cmp_three_dec_max_102_i_6_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_three_dec_max_102_i_7
       (.I0(device_temp_101[6]),
        .I1(three_dec_max_limit[6]),
        .I2(three_dec_max_limit[7]),
        .I3(device_temp_101[7]),
        .O(temp_cmp_three_dec_max_102_i_7_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_three_dec_max_102_i_8
       (.I0(device_temp_101[4]),
        .I1(three_dec_max_limit[4]),
        .I2(three_dec_max_limit[5]),
        .I3(device_temp_101[5]),
        .O(temp_cmp_three_dec_max_102_i_8_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_three_dec_max_102_i_9
       (.I0(device_temp_101[2]),
        .I1(three_dec_max_limit[2]),
        .I2(three_dec_max_limit[3]),
        .I3(device_temp_101[3]),
        .O(temp_cmp_three_dec_max_102_i_9_n_0));
  FDRE temp_cmp_three_dec_max_102_reg
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(temp_cmp_three_dec_max_101),
        .Q(temp_cmp_three_dec_max_102),
        .R(1'b0));
  CARRY4 temp_cmp_three_dec_max_102_reg_i_1
       (.CI(temp_cmp_three_dec_max_102_reg_i_2_n_0),
        .CO({NLW_temp_cmp_three_dec_max_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_three_dec_max_101,temp_cmp_three_dec_max_102_reg_i_1_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,temp_cmp_three_dec_max_102_i_3_n_0,temp_cmp_three_dec_max_102_i_4_n_0}),
        .O(NLW_temp_cmp_three_dec_max_102_reg_i_1_O_UNCONNECTED[3:0]),
        .S({1'b0,1'b0,temp_cmp_three_dec_max_102_i_5_n_0,temp_cmp_three_dec_max_102_i_6_n_0}));
  CARRY4 temp_cmp_three_dec_max_102_reg_i_2
       (.CI(1'b0),
        .CO({temp_cmp_three_dec_max_102_reg_i_2_n_0,temp_cmp_three_dec_max_102_reg_i_2_n_1,temp_cmp_three_dec_max_102_reg_i_2_n_2,temp_cmp_three_dec_max_102_reg_i_2_n_3}),
        .CYINIT(1'b1),
        .DI({temp_cmp_three_dec_max_102_i_7_n_0,temp_cmp_three_dec_max_102_i_8_n_0,temp_cmp_three_dec_max_102_i_9_n_0,temp_cmp_three_dec_max_102_i_10_n_0}),
        .O(NLW_temp_cmp_three_dec_max_102_reg_i_2_O_UNCONNECTED[3:0]),
        .S({temp_cmp_three_dec_max_102_i_11_n_0,temp_cmp_three_dec_max_102_i_12_n_0,temp_cmp_three_dec_max_102_i_13_n_0,temp_cmp_three_dec_max_102_i_14_n_0}));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_three_dec_min_102_i_10
       (.I0(three_dec_min_limit[0]),
        .I1(device_temp_101[0]),
        .I2(device_temp_101[1]),
        .I3(three_dec_min_limit[1]),
        .O(temp_cmp_three_dec_min_102_i_10_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_three_dec_min_102_i_11
       (.I0(three_dec_min_limit[6]),
        .I1(device_temp_101[6]),
        .I2(three_dec_min_limit[7]),
        .I3(device_temp_101[7]),
        .O(temp_cmp_three_dec_min_102_i_11_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_three_dec_min_102_i_12
       (.I0(three_dec_min_limit[4]),
        .I1(device_temp_101[4]),
        .I2(three_dec_min_limit[5]),
        .I3(device_temp_101[5]),
        .O(temp_cmp_three_dec_min_102_i_12_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_three_dec_min_102_i_13
       (.I0(three_dec_min_limit[2]),
        .I1(device_temp_101[2]),
        .I2(three_dec_min_limit[3]),
        .I3(device_temp_101[3]),
        .O(temp_cmp_three_dec_min_102_i_13_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_three_dec_min_102_i_14
       (.I0(three_dec_min_limit[0]),
        .I1(device_temp_101[0]),
        .I2(three_dec_min_limit[1]),
        .I3(device_temp_101[1]),
        .O(temp_cmp_three_dec_min_102_i_14_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_three_dec_min_102_i_3
       (.I0(three_dec_min_limit[10]),
        .I1(device_temp_101[10]),
        .I2(device_temp_101[11]),
        .I3(three_dec_min_limit[11]),
        .O(temp_cmp_three_dec_min_102_i_3_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_three_dec_min_102_i_4
       (.I0(three_dec_min_limit[8]),
        .I1(device_temp_101[8]),
        .I2(device_temp_101[9]),
        .I3(three_dec_min_limit[9]),
        .O(temp_cmp_three_dec_min_102_i_4_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_three_dec_min_102_i_5
       (.I0(three_dec_min_limit[10]),
        .I1(device_temp_101[10]),
        .I2(three_dec_min_limit[11]),
        .I3(device_temp_101[11]),
        .O(temp_cmp_three_dec_min_102_i_5_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_three_dec_min_102_i_6
       (.I0(three_dec_min_limit[8]),
        .I1(device_temp_101[8]),
        .I2(three_dec_min_limit[9]),
        .I3(device_temp_101[9]),
        .O(temp_cmp_three_dec_min_102_i_6_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_three_dec_min_102_i_7
       (.I0(three_dec_min_limit[6]),
        .I1(device_temp_101[6]),
        .I2(device_temp_101[7]),
        .I3(three_dec_min_limit[7]),
        .O(temp_cmp_three_dec_min_102_i_7_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_three_dec_min_102_i_8
       (.I0(three_dec_min_limit[4]),
        .I1(device_temp_101[4]),
        .I2(device_temp_101[5]),
        .I3(three_dec_min_limit[5]),
        .O(temp_cmp_three_dec_min_102_i_8_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_three_dec_min_102_i_9
       (.I0(three_dec_min_limit[2]),
        .I1(device_temp_101[2]),
        .I2(device_temp_101[3]),
        .I3(three_dec_min_limit[3]),
        .O(temp_cmp_three_dec_min_102_i_9_n_0));
  FDRE temp_cmp_three_dec_min_102_reg
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(temp_cmp_three_dec_min_101),
        .Q(temp_cmp_three_dec_min_102),
        .R(1'b0));
  CARRY4 temp_cmp_three_dec_min_102_reg_i_1
       (.CI(temp_cmp_three_dec_min_102_reg_i_2_n_0),
        .CO({NLW_temp_cmp_three_dec_min_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_three_dec_min_101,temp_cmp_three_dec_min_102_reg_i_1_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,temp_cmp_three_dec_min_102_i_3_n_0,temp_cmp_three_dec_min_102_i_4_n_0}),
        .O(NLW_temp_cmp_three_dec_min_102_reg_i_1_O_UNCONNECTED[3:0]),
        .S({1'b0,1'b0,temp_cmp_three_dec_min_102_i_5_n_0,temp_cmp_three_dec_min_102_i_6_n_0}));
  CARRY4 temp_cmp_three_dec_min_102_reg_i_2
       (.CI(1'b0),
        .CO({temp_cmp_three_dec_min_102_reg_i_2_n_0,temp_cmp_three_dec_min_102_reg_i_2_n_1,temp_cmp_three_dec_min_102_reg_i_2_n_2,temp_cmp_three_dec_min_102_reg_i_2_n_3}),
        .CYINIT(1'b0),
        .DI({temp_cmp_three_dec_min_102_i_7_n_0,temp_cmp_three_dec_min_102_i_8_n_0,temp_cmp_three_dec_min_102_i_9_n_0,temp_cmp_three_dec_min_102_i_10_n_0}),
        .O(NLW_temp_cmp_three_dec_min_102_reg_i_2_O_UNCONNECTED[3:0]),
        .S({temp_cmp_three_dec_min_102_i_11_n_0,temp_cmp_three_dec_min_102_i_12_n_0,temp_cmp_three_dec_min_102_i_13_n_0,temp_cmp_three_dec_min_102_i_14_n_0}));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_three_inc_max_102_i_10
       (.I0(device_temp_101[0]),
        .I1(two_dec_max_limit[0]),
        .I2(one_inc_max_limit[1]),
        .I3(device_temp_101[1]),
        .O(temp_cmp_three_inc_max_102_i_10_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_three_inc_max_102_i_11
       (.I0(device_temp_101[6]),
        .I1(three_inc_max_limit[6]),
        .I2(device_temp_101[7]),
        .I3(three_inc_max_limit[7]),
        .O(temp_cmp_three_inc_max_102_i_11_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_three_inc_max_102_i_12
       (.I0(device_temp_101[4]),
        .I1(three_inc_max_limit[4]),
        .I2(device_temp_101[5]),
        .I3(three_inc_max_limit[5]),
        .O(temp_cmp_three_inc_max_102_i_12_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_three_inc_max_102_i_13
       (.I0(device_temp_101[2]),
        .I1(three_inc_max_limit[2]),
        .I2(device_temp_101[3]),
        .I3(three_inc_max_limit[3]),
        .O(temp_cmp_three_inc_max_102_i_13_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_three_inc_max_102_i_14
       (.I0(device_temp_101[0]),
        .I1(two_dec_max_limit[0]),
        .I2(device_temp_101[1]),
        .I3(one_inc_max_limit[1]),
        .O(temp_cmp_three_inc_max_102_i_14_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_three_inc_max_102_i_3
       (.I0(device_temp_101[10]),
        .I1(three_inc_max_limit[10]),
        .I2(three_inc_max_limit[11]),
        .I3(device_temp_101[11]),
        .O(temp_cmp_three_inc_max_102_i_3_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_three_inc_max_102_i_4
       (.I0(device_temp_101[8]),
        .I1(three_inc_max_limit[8]),
        .I2(three_inc_max_limit[9]),
        .I3(device_temp_101[9]),
        .O(temp_cmp_three_inc_max_102_i_4_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_three_inc_max_102_i_5
       (.I0(device_temp_101[10]),
        .I1(three_inc_max_limit[10]),
        .I2(device_temp_101[11]),
        .I3(three_inc_max_limit[11]),
        .O(temp_cmp_three_inc_max_102_i_5_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_three_inc_max_102_i_6
       (.I0(device_temp_101[8]),
        .I1(three_inc_max_limit[8]),
        .I2(device_temp_101[9]),
        .I3(three_inc_max_limit[9]),
        .O(temp_cmp_three_inc_max_102_i_6_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_three_inc_max_102_i_7
       (.I0(device_temp_101[6]),
        .I1(three_inc_max_limit[6]),
        .I2(three_inc_max_limit[7]),
        .I3(device_temp_101[7]),
        .O(temp_cmp_three_inc_max_102_i_7_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_three_inc_max_102_i_8
       (.I0(device_temp_101[4]),
        .I1(three_inc_max_limit[4]),
        .I2(three_inc_max_limit[5]),
        .I3(device_temp_101[5]),
        .O(temp_cmp_three_inc_max_102_i_8_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_three_inc_max_102_i_9
       (.I0(device_temp_101[2]),
        .I1(three_inc_max_limit[2]),
        .I2(three_inc_max_limit[3]),
        .I3(device_temp_101[3]),
        .O(temp_cmp_three_inc_max_102_i_9_n_0));
  FDRE temp_cmp_three_inc_max_102_reg
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(temp_cmp_three_inc_max_101),
        .Q(temp_cmp_three_inc_max_102),
        .R(1'b0));
  CARRY4 temp_cmp_three_inc_max_102_reg_i_1
       (.CI(temp_cmp_three_inc_max_102_reg_i_2_n_0),
        .CO({NLW_temp_cmp_three_inc_max_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_three_inc_max_101,temp_cmp_three_inc_max_102_reg_i_1_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,temp_cmp_three_inc_max_102_i_3_n_0,temp_cmp_three_inc_max_102_i_4_n_0}),
        .O(NLW_temp_cmp_three_inc_max_102_reg_i_1_O_UNCONNECTED[3:0]),
        .S({1'b0,1'b0,temp_cmp_three_inc_max_102_i_5_n_0,temp_cmp_three_inc_max_102_i_6_n_0}));
  CARRY4 temp_cmp_three_inc_max_102_reg_i_2
       (.CI(1'b0),
        .CO({temp_cmp_three_inc_max_102_reg_i_2_n_0,temp_cmp_three_inc_max_102_reg_i_2_n_1,temp_cmp_three_inc_max_102_reg_i_2_n_2,temp_cmp_three_inc_max_102_reg_i_2_n_3}),
        .CYINIT(1'b1),
        .DI({temp_cmp_three_inc_max_102_i_7_n_0,temp_cmp_three_inc_max_102_i_8_n_0,temp_cmp_three_inc_max_102_i_9_n_0,temp_cmp_three_inc_max_102_i_10_n_0}),
        .O(NLW_temp_cmp_three_inc_max_102_reg_i_2_O_UNCONNECTED[3:0]),
        .S({temp_cmp_three_inc_max_102_i_11_n_0,temp_cmp_three_inc_max_102_i_12_n_0,temp_cmp_three_inc_max_102_i_13_n_0,temp_cmp_three_inc_max_102_i_14_n_0}));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_three_inc_min_102_i_10
       (.I0(three_dec_min_limit[0]),
        .I1(device_temp_101[0]),
        .I2(device_temp_101[1]),
        .I3(one_inc_min_limit[1]),
        .O(temp_cmp_three_inc_min_102_i_10_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_three_inc_min_102_i_11
       (.I0(three_inc_min_limit[6]),
        .I1(device_temp_101[6]),
        .I2(three_inc_min_limit[7]),
        .I3(device_temp_101[7]),
        .O(temp_cmp_three_inc_min_102_i_11_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_three_inc_min_102_i_12
       (.I0(three_inc_min_limit[4]),
        .I1(device_temp_101[4]),
        .I2(three_inc_min_limit[5]),
        .I3(device_temp_101[5]),
        .O(temp_cmp_three_inc_min_102_i_12_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_three_inc_min_102_i_13
       (.I0(three_inc_min_limit[2]),
        .I1(device_temp_101[2]),
        .I2(three_inc_min_limit[3]),
        .I3(device_temp_101[3]),
        .O(temp_cmp_three_inc_min_102_i_13_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_three_inc_min_102_i_14
       (.I0(three_dec_min_limit[0]),
        .I1(device_temp_101[0]),
        .I2(one_inc_min_limit[1]),
        .I3(device_temp_101[1]),
        .O(temp_cmp_three_inc_min_102_i_14_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_three_inc_min_102_i_3
       (.I0(three_inc_min_limit[10]),
        .I1(device_temp_101[10]),
        .I2(device_temp_101[11]),
        .I3(three_inc_min_limit[11]),
        .O(temp_cmp_three_inc_min_102_i_3_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_three_inc_min_102_i_4
       (.I0(three_inc_min_limit[8]),
        .I1(device_temp_101[8]),
        .I2(device_temp_101[9]),
        .I3(three_inc_min_limit[9]),
        .O(temp_cmp_three_inc_min_102_i_4_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_three_inc_min_102_i_5
       (.I0(three_inc_min_limit[10]),
        .I1(device_temp_101[10]),
        .I2(three_inc_min_limit[11]),
        .I3(device_temp_101[11]),
        .O(temp_cmp_three_inc_min_102_i_5_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_three_inc_min_102_i_6
       (.I0(three_inc_min_limit[8]),
        .I1(device_temp_101[8]),
        .I2(three_inc_min_limit[9]),
        .I3(device_temp_101[9]),
        .O(temp_cmp_three_inc_min_102_i_6_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_three_inc_min_102_i_7
       (.I0(three_inc_min_limit[6]),
        .I1(device_temp_101[6]),
        .I2(device_temp_101[7]),
        .I3(three_inc_min_limit[7]),
        .O(temp_cmp_three_inc_min_102_i_7_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_three_inc_min_102_i_8
       (.I0(three_inc_min_limit[4]),
        .I1(device_temp_101[4]),
        .I2(device_temp_101[5]),
        .I3(three_inc_min_limit[5]),
        .O(temp_cmp_three_inc_min_102_i_8_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_three_inc_min_102_i_9
       (.I0(three_inc_min_limit[2]),
        .I1(device_temp_101[2]),
        .I2(device_temp_101[3]),
        .I3(three_inc_min_limit[3]),
        .O(temp_cmp_three_inc_min_102_i_9_n_0));
  FDRE temp_cmp_three_inc_min_102_reg
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(temp_cmp_three_inc_min_101),
        .Q(temp_cmp_three_inc_min_102),
        .R(1'b0));
  CARRY4 temp_cmp_three_inc_min_102_reg_i_1
       (.CI(temp_cmp_three_inc_min_102_reg_i_2_n_0),
        .CO({NLW_temp_cmp_three_inc_min_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_three_inc_min_101,temp_cmp_three_inc_min_102_reg_i_1_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,temp_cmp_three_inc_min_102_i_3_n_0,temp_cmp_three_inc_min_102_i_4_n_0}),
        .O(NLW_temp_cmp_three_inc_min_102_reg_i_1_O_UNCONNECTED[3:0]),
        .S({1'b0,1'b0,temp_cmp_three_inc_min_102_i_5_n_0,temp_cmp_three_inc_min_102_i_6_n_0}));
  CARRY4 temp_cmp_three_inc_min_102_reg_i_2
       (.CI(1'b0),
        .CO({temp_cmp_three_inc_min_102_reg_i_2_n_0,temp_cmp_three_inc_min_102_reg_i_2_n_1,temp_cmp_three_inc_min_102_reg_i_2_n_2,temp_cmp_three_inc_min_102_reg_i_2_n_3}),
        .CYINIT(1'b0),
        .DI({temp_cmp_three_inc_min_102_i_7_n_0,temp_cmp_three_inc_min_102_i_8_n_0,temp_cmp_three_inc_min_102_i_9_n_0,temp_cmp_three_inc_min_102_i_10_n_0}),
        .O(NLW_temp_cmp_three_inc_min_102_reg_i_2_O_UNCONNECTED[3:0]),
        .S({temp_cmp_three_inc_min_102_i_11_n_0,temp_cmp_three_inc_min_102_i_12_n_0,temp_cmp_three_inc_min_102_i_13_n_0,temp_cmp_three_inc_min_102_i_14_n_0}));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_two_dec_max_102_i_10
       (.I0(device_temp_101[0]),
        .I1(two_dec_max_limit[0]),
        .I2(two_dec_max_limit[1]),
        .I3(device_temp_101[1]),
        .O(temp_cmp_two_dec_max_102_i_10_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_two_dec_max_102_i_11
       (.I0(device_temp_101[6]),
        .I1(two_dec_max_limit[6]),
        .I2(device_temp_101[7]),
        .I3(two_dec_max_limit[7]),
        .O(temp_cmp_two_dec_max_102_i_11_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_two_dec_max_102_i_12
       (.I0(device_temp_101[4]),
        .I1(two_dec_max_limit[4]),
        .I2(device_temp_101[5]),
        .I3(two_dec_max_limit[5]),
        .O(temp_cmp_two_dec_max_102_i_12_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_two_dec_max_102_i_13
       (.I0(device_temp_101[2]),
        .I1(two_dec_max_limit[2]),
        .I2(device_temp_101[3]),
        .I3(two_dec_max_limit[3]),
        .O(temp_cmp_two_dec_max_102_i_13_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_two_dec_max_102_i_14
       (.I0(device_temp_101[0]),
        .I1(two_dec_max_limit[0]),
        .I2(device_temp_101[1]),
        .I3(two_dec_max_limit[1]),
        .O(temp_cmp_two_dec_max_102_i_14_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_two_dec_max_102_i_3
       (.I0(device_temp_101[10]),
        .I1(two_dec_max_limit[10]),
        .I2(two_dec_max_limit[11]),
        .I3(device_temp_101[11]),
        .O(temp_cmp_two_dec_max_102_i_3_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_two_dec_max_102_i_4
       (.I0(device_temp_101[8]),
        .I1(two_dec_max_limit[8]),
        .I2(two_dec_max_limit[9]),
        .I3(device_temp_101[9]),
        .O(temp_cmp_two_dec_max_102_i_4_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_two_dec_max_102_i_5
       (.I0(device_temp_101[10]),
        .I1(two_dec_max_limit[10]),
        .I2(device_temp_101[11]),
        .I3(two_dec_max_limit[11]),
        .O(temp_cmp_two_dec_max_102_i_5_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_two_dec_max_102_i_6
       (.I0(device_temp_101[8]),
        .I1(two_dec_max_limit[8]),
        .I2(device_temp_101[9]),
        .I3(two_dec_max_limit[9]),
        .O(temp_cmp_two_dec_max_102_i_6_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_two_dec_max_102_i_7
       (.I0(device_temp_101[6]),
        .I1(two_dec_max_limit[6]),
        .I2(two_dec_max_limit[7]),
        .I3(device_temp_101[7]),
        .O(temp_cmp_two_dec_max_102_i_7_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_two_dec_max_102_i_8
       (.I0(device_temp_101[4]),
        .I1(two_dec_max_limit[4]),
        .I2(two_dec_max_limit[5]),
        .I3(device_temp_101[5]),
        .O(temp_cmp_two_dec_max_102_i_8_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_two_dec_max_102_i_9
       (.I0(device_temp_101[2]),
        .I1(two_dec_max_limit[2]),
        .I2(two_dec_max_limit[3]),
        .I3(device_temp_101[3]),
        .O(temp_cmp_two_dec_max_102_i_9_n_0));
  FDRE temp_cmp_two_dec_max_102_reg
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(temp_cmp_two_dec_max_101),
        .Q(temp_cmp_two_dec_max_102),
        .R(1'b0));
  CARRY4 temp_cmp_two_dec_max_102_reg_i_1
       (.CI(temp_cmp_two_dec_max_102_reg_i_2_n_0),
        .CO({NLW_temp_cmp_two_dec_max_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_two_dec_max_101,temp_cmp_two_dec_max_102_reg_i_1_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,temp_cmp_two_dec_max_102_i_3_n_0,temp_cmp_two_dec_max_102_i_4_n_0}),
        .O(NLW_temp_cmp_two_dec_max_102_reg_i_1_O_UNCONNECTED[3:0]),
        .S({1'b0,1'b0,temp_cmp_two_dec_max_102_i_5_n_0,temp_cmp_two_dec_max_102_i_6_n_0}));
  CARRY4 temp_cmp_two_dec_max_102_reg_i_2
       (.CI(1'b0),
        .CO({temp_cmp_two_dec_max_102_reg_i_2_n_0,temp_cmp_two_dec_max_102_reg_i_2_n_1,temp_cmp_two_dec_max_102_reg_i_2_n_2,temp_cmp_two_dec_max_102_reg_i_2_n_3}),
        .CYINIT(1'b1),
        .DI({temp_cmp_two_dec_max_102_i_7_n_0,temp_cmp_two_dec_max_102_i_8_n_0,temp_cmp_two_dec_max_102_i_9_n_0,temp_cmp_two_dec_max_102_i_10_n_0}),
        .O(NLW_temp_cmp_two_dec_max_102_reg_i_2_O_UNCONNECTED[3:0]),
        .S({temp_cmp_two_dec_max_102_i_11_n_0,temp_cmp_two_dec_max_102_i_12_n_0,temp_cmp_two_dec_max_102_i_13_n_0,temp_cmp_two_dec_max_102_i_14_n_0}));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_two_dec_min_102_i_10
       (.I0(three_dec_min_limit[0]),
        .I1(device_temp_101[0]),
        .I2(device_temp_101[1]),
        .I3(two_inc_min_limit[1]),
        .O(temp_cmp_two_dec_min_102_i_10_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_two_dec_min_102_i_11
       (.I0(two_dec_min_limit[6]),
        .I1(device_temp_101[6]),
        .I2(two_dec_min_limit[7]),
        .I3(device_temp_101[7]),
        .O(temp_cmp_two_dec_min_102_i_11_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_two_dec_min_102_i_12
       (.I0(two_dec_min_limit[4]),
        .I1(device_temp_101[4]),
        .I2(two_dec_min_limit[5]),
        .I3(device_temp_101[5]),
        .O(temp_cmp_two_dec_min_102_i_12_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_two_dec_min_102_i_13
       (.I0(two_dec_min_limit[2]),
        .I1(device_temp_101[2]),
        .I2(two_dec_min_limit[3]),
        .I3(device_temp_101[3]),
        .O(temp_cmp_two_dec_min_102_i_13_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_two_dec_min_102_i_14
       (.I0(three_dec_min_limit[0]),
        .I1(device_temp_101[0]),
        .I2(two_inc_min_limit[1]),
        .I3(device_temp_101[1]),
        .O(temp_cmp_two_dec_min_102_i_14_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_two_dec_min_102_i_3
       (.I0(two_dec_min_limit[10]),
        .I1(device_temp_101[10]),
        .I2(device_temp_101[11]),
        .I3(two_dec_min_limit[11]),
        .O(temp_cmp_two_dec_min_102_i_3_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_two_dec_min_102_i_4
       (.I0(two_dec_min_limit[8]),
        .I1(device_temp_101[8]),
        .I2(device_temp_101[9]),
        .I3(two_dec_min_limit[9]),
        .O(temp_cmp_two_dec_min_102_i_4_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_two_dec_min_102_i_5
       (.I0(two_dec_min_limit[10]),
        .I1(device_temp_101[10]),
        .I2(two_dec_min_limit[11]),
        .I3(device_temp_101[11]),
        .O(temp_cmp_two_dec_min_102_i_5_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_two_dec_min_102_i_6
       (.I0(two_dec_min_limit[8]),
        .I1(device_temp_101[8]),
        .I2(two_dec_min_limit[9]),
        .I3(device_temp_101[9]),
        .O(temp_cmp_two_dec_min_102_i_6_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_two_dec_min_102_i_7
       (.I0(two_dec_min_limit[6]),
        .I1(device_temp_101[6]),
        .I2(device_temp_101[7]),
        .I3(two_dec_min_limit[7]),
        .O(temp_cmp_two_dec_min_102_i_7_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_two_dec_min_102_i_8
       (.I0(two_dec_min_limit[4]),
        .I1(device_temp_101[4]),
        .I2(device_temp_101[5]),
        .I3(two_dec_min_limit[5]),
        .O(temp_cmp_two_dec_min_102_i_8_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_two_dec_min_102_i_9
       (.I0(two_dec_min_limit[2]),
        .I1(device_temp_101[2]),
        .I2(device_temp_101[3]),
        .I3(two_dec_min_limit[3]),
        .O(temp_cmp_two_dec_min_102_i_9_n_0));
  FDRE temp_cmp_two_dec_min_102_reg
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(temp_cmp_two_dec_min_101),
        .Q(temp_cmp_two_dec_min_102),
        .R(1'b0));
  CARRY4 temp_cmp_two_dec_min_102_reg_i_1
       (.CI(temp_cmp_two_dec_min_102_reg_i_2_n_0),
        .CO({NLW_temp_cmp_two_dec_min_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_two_dec_min_101,temp_cmp_two_dec_min_102_reg_i_1_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,temp_cmp_two_dec_min_102_i_3_n_0,temp_cmp_two_dec_min_102_i_4_n_0}),
        .O(NLW_temp_cmp_two_dec_min_102_reg_i_1_O_UNCONNECTED[3:0]),
        .S({1'b0,1'b0,temp_cmp_two_dec_min_102_i_5_n_0,temp_cmp_two_dec_min_102_i_6_n_0}));
  CARRY4 temp_cmp_two_dec_min_102_reg_i_2
       (.CI(1'b0),
        .CO({temp_cmp_two_dec_min_102_reg_i_2_n_0,temp_cmp_two_dec_min_102_reg_i_2_n_1,temp_cmp_two_dec_min_102_reg_i_2_n_2,temp_cmp_two_dec_min_102_reg_i_2_n_3}),
        .CYINIT(1'b0),
        .DI({temp_cmp_two_dec_min_102_i_7_n_0,temp_cmp_two_dec_min_102_i_8_n_0,temp_cmp_two_dec_min_102_i_9_n_0,temp_cmp_two_dec_min_102_i_10_n_0}),
        .O(NLW_temp_cmp_two_dec_min_102_reg_i_2_O_UNCONNECTED[3:0]),
        .S({temp_cmp_two_dec_min_102_i_11_n_0,temp_cmp_two_dec_min_102_i_12_n_0,temp_cmp_two_dec_min_102_i_13_n_0,temp_cmp_two_dec_min_102_i_14_n_0}));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_two_inc_max_102_i_10
       (.I0(device_temp_101[0]),
        .I1(two_dec_max_limit[0]),
        .I2(two_inc_max_limit[1]),
        .I3(device_temp_101[1]),
        .O(temp_cmp_two_inc_max_102_i_10_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_two_inc_max_102_i_11
       (.I0(device_temp_101[6]),
        .I1(two_inc_max_limit[6]),
        .I2(device_temp_101[7]),
        .I3(two_inc_max_limit[7]),
        .O(temp_cmp_two_inc_max_102_i_11_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_two_inc_max_102_i_12
       (.I0(device_temp_101[4]),
        .I1(two_inc_max_limit[4]),
        .I2(device_temp_101[5]),
        .I3(two_inc_max_limit[5]),
        .O(temp_cmp_two_inc_max_102_i_12_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_two_inc_max_102_i_13
       (.I0(device_temp_101[2]),
        .I1(two_inc_max_limit[2]),
        .I2(device_temp_101[3]),
        .I3(two_inc_max_limit[3]),
        .O(temp_cmp_two_inc_max_102_i_13_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_two_inc_max_102_i_14
       (.I0(device_temp_101[0]),
        .I1(two_dec_max_limit[0]),
        .I2(device_temp_101[1]),
        .I3(two_inc_max_limit[1]),
        .O(temp_cmp_two_inc_max_102_i_14_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_two_inc_max_102_i_3
       (.I0(device_temp_101[10]),
        .I1(two_inc_max_limit[10]),
        .I2(two_inc_max_limit[11]),
        .I3(device_temp_101[11]),
        .O(temp_cmp_two_inc_max_102_i_3_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_two_inc_max_102_i_4
       (.I0(device_temp_101[8]),
        .I1(two_inc_max_limit[8]),
        .I2(two_inc_max_limit[9]),
        .I3(device_temp_101[9]),
        .O(temp_cmp_two_inc_max_102_i_4_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_two_inc_max_102_i_5
       (.I0(device_temp_101[10]),
        .I1(two_inc_max_limit[10]),
        .I2(device_temp_101[11]),
        .I3(two_inc_max_limit[11]),
        .O(temp_cmp_two_inc_max_102_i_5_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_two_inc_max_102_i_6
       (.I0(device_temp_101[8]),
        .I1(two_inc_max_limit[8]),
        .I2(device_temp_101[9]),
        .I3(two_inc_max_limit[9]),
        .O(temp_cmp_two_inc_max_102_i_6_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_two_inc_max_102_i_7
       (.I0(device_temp_101[6]),
        .I1(two_inc_max_limit[6]),
        .I2(two_inc_max_limit[7]),
        .I3(device_temp_101[7]),
        .O(temp_cmp_two_inc_max_102_i_7_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_two_inc_max_102_i_8
       (.I0(device_temp_101[4]),
        .I1(two_inc_max_limit[4]),
        .I2(two_inc_max_limit[5]),
        .I3(device_temp_101[5]),
        .O(temp_cmp_two_inc_max_102_i_8_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_two_inc_max_102_i_9
       (.I0(device_temp_101[2]),
        .I1(two_inc_max_limit[2]),
        .I2(two_inc_max_limit[3]),
        .I3(device_temp_101[3]),
        .O(temp_cmp_two_inc_max_102_i_9_n_0));
  FDRE temp_cmp_two_inc_max_102_reg
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(temp_cmp_two_inc_max_101),
        .Q(temp_cmp_two_inc_max_102),
        .R(1'b0));
  CARRY4 temp_cmp_two_inc_max_102_reg_i_1
       (.CI(temp_cmp_two_inc_max_102_reg_i_2_n_0),
        .CO({NLW_temp_cmp_two_inc_max_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_two_inc_max_101,temp_cmp_two_inc_max_102_reg_i_1_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,temp_cmp_two_inc_max_102_i_3_n_0,temp_cmp_two_inc_max_102_i_4_n_0}),
        .O(NLW_temp_cmp_two_inc_max_102_reg_i_1_O_UNCONNECTED[3:0]),
        .S({1'b0,1'b0,temp_cmp_two_inc_max_102_i_5_n_0,temp_cmp_two_inc_max_102_i_6_n_0}));
  CARRY4 temp_cmp_two_inc_max_102_reg_i_2
       (.CI(1'b0),
        .CO({temp_cmp_two_inc_max_102_reg_i_2_n_0,temp_cmp_two_inc_max_102_reg_i_2_n_1,temp_cmp_two_inc_max_102_reg_i_2_n_2,temp_cmp_two_inc_max_102_reg_i_2_n_3}),
        .CYINIT(1'b1),
        .DI({temp_cmp_two_inc_max_102_i_7_n_0,temp_cmp_two_inc_max_102_i_8_n_0,temp_cmp_two_inc_max_102_i_9_n_0,temp_cmp_two_inc_max_102_i_10_n_0}),
        .O(NLW_temp_cmp_two_inc_max_102_reg_i_2_O_UNCONNECTED[3:0]),
        .S({temp_cmp_two_inc_max_102_i_11_n_0,temp_cmp_two_inc_max_102_i_12_n_0,temp_cmp_two_inc_max_102_i_13_n_0,temp_cmp_two_inc_max_102_i_14_n_0}));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_two_inc_min_102_i_10
       (.I0(three_dec_min_limit[0]),
        .I1(device_temp_101[0]),
        .I2(device_temp_101[1]),
        .I3(two_inc_min_limit[1]),
        .O(temp_cmp_two_inc_min_102_i_10_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_two_inc_min_102_i_11
       (.I0(two_inc_min_limit[6]),
        .I1(device_temp_101[6]),
        .I2(two_inc_min_limit[7]),
        .I3(device_temp_101[7]),
        .O(temp_cmp_two_inc_min_102_i_11_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_two_inc_min_102_i_12
       (.I0(two_inc_min_limit[4]),
        .I1(device_temp_101[4]),
        .I2(two_inc_min_limit[5]),
        .I3(device_temp_101[5]),
        .O(temp_cmp_two_inc_min_102_i_12_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_two_inc_min_102_i_13
       (.I0(two_inc_min_limit[2]),
        .I1(device_temp_101[2]),
        .I2(two_inc_min_limit[3]),
        .I3(device_temp_101[3]),
        .O(temp_cmp_two_inc_min_102_i_13_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_two_inc_min_102_i_14
       (.I0(three_dec_min_limit[0]),
        .I1(device_temp_101[0]),
        .I2(two_inc_min_limit[1]),
        .I3(device_temp_101[1]),
        .O(temp_cmp_two_inc_min_102_i_14_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_two_inc_min_102_i_3
       (.I0(two_inc_min_limit[10]),
        .I1(device_temp_101[10]),
        .I2(device_temp_101[11]),
        .I3(two_inc_min_limit[11]),
        .O(temp_cmp_two_inc_min_102_i_3_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_two_inc_min_102_i_4
       (.I0(two_inc_min_limit[8]),
        .I1(device_temp_101[8]),
        .I2(device_temp_101[9]),
        .I3(two_inc_min_limit[9]),
        .O(temp_cmp_two_inc_min_102_i_4_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_two_inc_min_102_i_5
       (.I0(two_inc_min_limit[10]),
        .I1(device_temp_101[10]),
        .I2(two_inc_min_limit[11]),
        .I3(device_temp_101[11]),
        .O(temp_cmp_two_inc_min_102_i_5_n_0));
  LUT4 #(
    .INIT(16'h9009)) 
    temp_cmp_two_inc_min_102_i_6
       (.I0(two_inc_min_limit[8]),
        .I1(device_temp_101[8]),
        .I2(two_inc_min_limit[9]),
        .I3(device_temp_101[9]),
        .O(temp_cmp_two_inc_min_102_i_6_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_two_inc_min_102_i_7
       (.I0(two_inc_min_limit[6]),
        .I1(device_temp_101[6]),
        .I2(device_temp_101[7]),
        .I3(two_inc_min_limit[7]),
        .O(temp_cmp_two_inc_min_102_i_7_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_two_inc_min_102_i_8
       (.I0(two_inc_min_limit[4]),
        .I1(device_temp_101[4]),
        .I2(device_temp_101[5]),
        .I3(two_inc_min_limit[5]),
        .O(temp_cmp_two_inc_min_102_i_8_n_0));
  LUT4 #(
    .INIT(16'h2F02)) 
    temp_cmp_two_inc_min_102_i_9
       (.I0(two_inc_min_limit[2]),
        .I1(device_temp_101[2]),
        .I2(device_temp_101[3]),
        .I3(two_inc_min_limit[3]),
        .O(temp_cmp_two_inc_min_102_i_9_n_0));
  FDRE temp_cmp_two_inc_min_102_reg
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(temp_cmp_two_inc_min_101),
        .Q(temp_cmp_two_inc_min_102),
        .R(1'b0));
  CARRY4 temp_cmp_two_inc_min_102_reg_i_1
       (.CI(temp_cmp_two_inc_min_102_reg_i_2_n_0),
        .CO({NLW_temp_cmp_two_inc_min_102_reg_i_1_CO_UNCONNECTED[3:2],temp_cmp_two_inc_min_101,temp_cmp_two_inc_min_102_reg_i_1_n_3}),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,temp_cmp_two_inc_min_102_i_3_n_0,temp_cmp_two_inc_min_102_i_4_n_0}),
        .O(NLW_temp_cmp_two_inc_min_102_reg_i_1_O_UNCONNECTED[3:0]),
        .S({1'b0,1'b0,temp_cmp_two_inc_min_102_i_5_n_0,temp_cmp_two_inc_min_102_i_6_n_0}));
  CARRY4 temp_cmp_two_inc_min_102_reg_i_2
       (.CI(1'b0),
        .CO({temp_cmp_two_inc_min_102_reg_i_2_n_0,temp_cmp_two_inc_min_102_reg_i_2_n_1,temp_cmp_two_inc_min_102_reg_i_2_n_2,temp_cmp_two_inc_min_102_reg_i_2_n_3}),
        .CYINIT(1'b0),
        .DI({temp_cmp_two_inc_min_102_i_7_n_0,temp_cmp_two_inc_min_102_i_8_n_0,temp_cmp_two_inc_min_102_i_9_n_0,temp_cmp_two_inc_min_102_i_10_n_0}),
        .O(NLW_temp_cmp_two_inc_min_102_reg_i_2_O_UNCONNECTED[3:0]),
        .S({temp_cmp_two_inc_min_102_i_11_n_0,temp_cmp_two_inc_min_102_i_12_n_0,temp_cmp_two_inc_min_102_i_13_n_0,temp_cmp_two_inc_min_102_i_14_n_0}));
  FDRE tempmon_init_complete_reg
       (.C(pi_f_dec_reg_0),
        .CE(tempmon_state_init),
        .D(tempmon_state_init),
        .Q(tempmon_init_complete),
        .R(\four_dec_min_limit_reg[0]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair238" *) 
  LUT2 #(
    .INIT(4'hE)) 
    tempmon_pi_f_en_r_i_1
       (.I0(tempmon_pi_f_inc),
        .I1(tempmon_pi_f_dec),
        .O(tempmon_sel_pi_incdec));
  FDRE tempmon_sample_en_101_reg
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(mc_ref_zq_wip),
        .Q(tempmon_sample_en_101),
        .R(\four_dec_min_limit_reg[0]_0 ));
  FDRE tempmon_sample_en_102_reg
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(tempmon_sample_en_101),
        .Q(tempmon_sample_en_102),
        .R(\four_dec_min_limit_reg[0]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \tempmon_state[0]_i_1 
       (.I0(\tempmon_state[10]_i_6_n_0 ),
        .O(tempmon_state_nxt[0]));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFC444)) 
    \tempmon_state[10]_i_1 
       (.I0(\tempmon_state[10]_i_3_n_0 ),
        .I1(update_temp_102),
        .I2(temp_cmp_four_dec_min_102),
        .I3(tempmon_state[10]),
        .I4(\tempmon_state[10]_i_4_n_0 ),
        .I5(\tempmon_state[10]_i_5_n_0 ),
        .O(\tempmon_state[10]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair233" *) 
  LUT5 #(
    .INIT(32'h00010116)) 
    \tempmon_state[10]_i_10 
       (.I0(tempmon_state[0]),
        .I1(tempmon_state[1]),
        .I2(tempmon_state[2]),
        .I3(tempmon_state[3]),
        .I4(tempmon_state[4]),
        .O(\tempmon_state[10]_i_10_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair233" *) 
  LUT5 #(
    .INIT(32'hFFFEFEE8)) 
    \tempmon_state[10]_i_11 
       (.I0(tempmon_state[0]),
        .I1(tempmon_state[1]),
        .I2(tempmon_state[2]),
        .I3(tempmon_state[3]),
        .I4(tempmon_state[4]),
        .O(\tempmon_state[10]_i_11_n_0 ));
  LUT6 #(
    .INIT(64'h0000000100010116)) 
    \tempmon_state[10]_i_12 
       (.I0(tempmon_state[5]),
        .I1(tempmon_state[6]),
        .I2(tempmon_state[7]),
        .I3(tempmon_state[8]),
        .I4(tempmon_state[9]),
        .I5(tempmon_state[10]),
        .O(\tempmon_state[10]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFEFFFEFEE8)) 
    \tempmon_state[10]_i_13 
       (.I0(tempmon_state[5]),
        .I1(tempmon_state[6]),
        .I2(tempmon_state[7]),
        .I3(tempmon_state[8]),
        .I4(tempmon_state[9]),
        .I5(tempmon_state[10]),
        .O(\tempmon_state[10]_i_13_n_0 ));
  LUT4 #(
    .INIT(16'hF888)) 
    \tempmon_state[10]_i_14 
       (.I0(temp_cmp_two_dec_min_102),
        .I1(tempmon_state[8]),
        .I2(temp_cmp_three_inc_min_102),
        .I3(tempmon_state[3]),
        .O(\tempmon_state[10]_i_14_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair237" *) 
  LUT3 #(
    .INIT(8'h80)) 
    \tempmon_state[10]_i_15 
       (.I0(temp_cmp_two_dec_max_102),
        .I1(update_temp_102),
        .I2(tempmon_state[8]),
        .O(\tempmon_state[10]_i_15_n_0 ));
  LUT4 #(
    .INIT(16'h8000)) 
    \tempmon_state[10]_i_2 
       (.I0(update_temp_102),
        .I1(temp_cmp_three_dec_max_102),
        .I2(tempmon_state[9]),
        .I3(\tempmon_state[10]_i_6_n_0 ),
        .O(tempmon_state_nxt[10]));
  LUT6 #(
    .INIT(64'h0000022202220222)) 
    \tempmon_state[10]_i_3 
       (.I0(pi_f_dec_i_2_n_0),
        .I1(\tempmon_state[10]_i_7_n_0 ),
        .I2(temp_cmp_one_dec_min_102),
        .I3(tempmon_state[7]),
        .I4(temp_cmp_three_dec_min_102),
        .I5(tempmon_state[9]),
        .O(\tempmon_state[10]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair235" *) 
  LUT5 #(
    .INIT(32'hFFEFEFEF)) 
    \tempmon_state[10]_i_4 
       (.I0(\tempmon_state[10]_i_8_n_0 ),
        .I1(tempmon_state[1]),
        .I2(\tempmon_state[10]_i_6_n_0 ),
        .I3(tempmon_state[0]),
        .I4(calib_complete),
        .O(\tempmon_state[10]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFAAEAAAEAAAEAAA)) 
    \tempmon_state[10]_i_5 
       (.I0(\tempmon_state[10]_i_9_n_0 ),
        .I1(tempmon_state[6]),
        .I2(temp_cmp_neutral_max_102),
        .I3(update_temp_102),
        .I4(tempmon_state[7]),
        .I5(temp_cmp_one_dec_max_102),
        .O(\tempmon_state[10]_i_5_n_0 ));
  LUT4 #(
    .INIT(16'h0012)) 
    \tempmon_state[10]_i_6 
       (.I0(\tempmon_state[10]_i_10_n_0 ),
        .I1(\tempmon_state[10]_i_11_n_0 ),
        .I2(\tempmon_state[10]_i_12_n_0 ),
        .I3(\tempmon_state[10]_i_13_n_0 ),
        .O(\tempmon_state[10]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair234" *) 
  LUT5 #(
    .INIT(32'hFFFFF888)) 
    \tempmon_state[10]_i_7 
       (.I0(tempmon_state[4]),
        .I1(temp_cmp_two_inc_min_102),
        .I2(tempmon_state[6]),
        .I3(temp_cmp_neutral_min_102),
        .I4(\tempmon_state[10]_i_14_n_0 ),
        .O(\tempmon_state[10]_i_7_n_0 ));
  LUT3 #(
    .INIT(8'h80)) 
    \tempmon_state[10]_i_8 
       (.I0(temp_cmp_one_inc_min_102),
        .I1(tempmon_state[5]),
        .I2(update_temp_102),
        .O(\tempmon_state[10]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hFFF8F0F0F8F8F0F0)) 
    \tempmon_state[10]_i_9 
       (.I0(tempmon_state[2]),
        .I1(temp_cmp_four_inc_max_102),
        .I2(\tempmon_state[10]_i_15_n_0 ),
        .I3(tempmon_state[9]),
        .I4(update_temp_102),
        .I5(temp_cmp_three_dec_max_102),
        .O(\tempmon_state[10]_i_9_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair235" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \tempmon_state[1]_i_1 
       (.I0(\tempmon_state[10]_i_6_n_0 ),
        .I1(tempmon_state[0]),
        .O(tempmon_state_nxt[1]));
  LUT4 #(
    .INIT(16'h7000)) 
    \tempmon_state[2]_i_1 
       (.I0(temp_cmp_three_inc_max_102),
        .I1(update_temp_102),
        .I2(tempmon_state[3]),
        .I3(\tempmon_state[10]_i_6_n_0 ),
        .O(tempmon_state_nxt[2]));
  LUT5 #(
    .INIT(32'h8AAA8888)) 
    \tempmon_state[3]_i_1 
       (.I0(\tempmon_state[10]_i_6_n_0 ),
        .I1(tempmon_state[2]),
        .I2(temp_cmp_two_inc_max_102),
        .I3(update_temp_102),
        .I4(tempmon_state[4]),
        .O(tempmon_state_nxt[3]));
  LUT6 #(
    .INIT(64'h8080F000F080F000)) 
    \tempmon_state[4]_i_1 
       (.I0(temp_cmp_three_inc_max_102),
        .I1(tempmon_state[3]),
        .I2(\tempmon_state[10]_i_6_n_0 ),
        .I3(tempmon_state[5]),
        .I4(update_temp_102),
        .I5(temp_cmp_one_inc_max_102),
        .O(tempmon_state_nxt[4]));
  LUT6 #(
    .INIT(64'h8080F000F080F000)) 
    \tempmon_state[5]_i_1 
       (.I0(temp_cmp_two_inc_max_102),
        .I1(tempmon_state[4]),
        .I2(\tempmon_state[10]_i_6_n_0 ),
        .I3(tempmon_state[6]),
        .I4(update_temp_102),
        .I5(temp_cmp_neutral_max_102),
        .O(tempmon_state_nxt[5]));
  LUT6 #(
    .INIT(64'hFFFF0000BFA00000)) 
    \tempmon_state[6]_i_1 
       (.I0(\tempmon_state[6]_i_2_n_0 ),
        .I1(temp_cmp_one_dec_max_102),
        .I2(update_temp_102),
        .I3(tempmon_state[7]),
        .I4(\tempmon_state[10]_i_6_n_0 ),
        .I5(tempmon_state[1]),
        .O(tempmon_state_nxt[6]));
  (* SOFT_HLUTNM = "soft_lutpair239" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \tempmon_state[6]_i_2 
       (.I0(temp_cmp_one_inc_max_102),
        .I1(tempmon_state[5]),
        .O(\tempmon_state[6]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h80AAAAAA80008000)) 
    \tempmon_state[7]_i_1 
       (.I0(\tempmon_state[10]_i_6_n_0 ),
        .I1(tempmon_state[6]),
        .I2(temp_cmp_neutral_max_102),
        .I3(update_temp_102),
        .I4(temp_cmp_two_dec_max_102),
        .I5(tempmon_state[8]),
        .O(tempmon_state_nxt[7]));
  LUT6 #(
    .INIT(64'h8080F080F000F000)) 
    \tempmon_state[8]_i_1 
       (.I0(tempmon_state[7]),
        .I1(temp_cmp_one_dec_max_102),
        .I2(\tempmon_state[10]_i_6_n_0 ),
        .I3(tempmon_state[9]),
        .I4(temp_cmp_three_dec_max_102),
        .I5(update_temp_102),
        .O(tempmon_state_nxt[8]));
  (* SOFT_HLUTNM = "soft_lutpair237" *) 
  LUT5 #(
    .INIT(32'hAAAA8000)) 
    \tempmon_state[9]_i_1 
       (.I0(\tempmon_state[10]_i_6_n_0 ),
        .I1(temp_cmp_two_dec_max_102),
        .I2(update_temp_102),
        .I3(tempmon_state[8]),
        .I4(tempmon_state[10]),
        .O(tempmon_state_nxt[9]));
  (* FSM_ENCODED_STATES = "IDLE:00000000001,ONE_INC:00000100000,FOUR_DEC:10000000000,THREE_INC:00000001000,TWO_DEC:00100000000,FOUR_INC:00000000100,ONE_DEC:00010000000,INIT:00000000010,NEUTRAL:00001000000,TWO_INC:00000010000,THREE_DEC:01000000000" *) 
  FDSE \tempmon_state_reg[0] 
       (.C(pi_f_dec_reg_0),
        .CE(\tempmon_state[10]_i_1_n_0 ),
        .D(tempmon_state_nxt[0]),
        .Q(tempmon_state[0]),
        .S(\device_temp_101_reg[0]_0 ));
  (* FSM_ENCODED_STATES = "IDLE:00000000001,ONE_INC:00000100000,FOUR_DEC:10000000000,THREE_INC:00000001000,TWO_DEC:00100000000,FOUR_INC:00000000100,ONE_DEC:00010000000,INIT:00000000010,NEUTRAL:00001000000,TWO_INC:00000010000,THREE_DEC:01000000000" *) 
  FDRE \tempmon_state_reg[10] 
       (.C(pi_f_dec_reg_0),
        .CE(\tempmon_state[10]_i_1_n_0 ),
        .D(tempmon_state_nxt[10]),
        .Q(tempmon_state[10]),
        .R(\device_temp_101_reg[0]_0 ));
  (* FSM_ENCODED_STATES = "IDLE:00000000001,ONE_INC:00000100000,FOUR_DEC:10000000000,THREE_INC:00000001000,TWO_DEC:00100000000,FOUR_INC:00000000100,ONE_DEC:00010000000,INIT:00000000010,NEUTRAL:00001000000,TWO_INC:00000010000,THREE_DEC:01000000000" *) 
  FDRE \tempmon_state_reg[1] 
       (.C(pi_f_dec_reg_0),
        .CE(\tempmon_state[10]_i_1_n_0 ),
        .D(tempmon_state_nxt[1]),
        .Q(tempmon_state[1]),
        .R(\device_temp_101_reg[0]_0 ));
  (* FSM_ENCODED_STATES = "IDLE:00000000001,ONE_INC:00000100000,FOUR_DEC:10000000000,THREE_INC:00000001000,TWO_DEC:00100000000,FOUR_INC:00000000100,ONE_DEC:00010000000,INIT:00000000010,NEUTRAL:00001000000,TWO_INC:00000010000,THREE_DEC:01000000000" *) 
  FDRE \tempmon_state_reg[2] 
       (.C(pi_f_dec_reg_0),
        .CE(\tempmon_state[10]_i_1_n_0 ),
        .D(tempmon_state_nxt[2]),
        .Q(tempmon_state[2]),
        .R(\device_temp_101_reg[0]_0 ));
  (* FSM_ENCODED_STATES = "IDLE:00000000001,ONE_INC:00000100000,FOUR_DEC:10000000000,THREE_INC:00000001000,TWO_DEC:00100000000,FOUR_INC:00000000100,ONE_DEC:00010000000,INIT:00000000010,NEUTRAL:00001000000,TWO_INC:00000010000,THREE_DEC:01000000000" *) 
  FDRE \tempmon_state_reg[3] 
       (.C(pi_f_dec_reg_0),
        .CE(\tempmon_state[10]_i_1_n_0 ),
        .D(tempmon_state_nxt[3]),
        .Q(tempmon_state[3]),
        .R(\device_temp_101_reg[0]_0 ));
  (* FSM_ENCODED_STATES = "IDLE:00000000001,ONE_INC:00000100000,FOUR_DEC:10000000000,THREE_INC:00000001000,TWO_DEC:00100000000,FOUR_INC:00000000100,ONE_DEC:00010000000,INIT:00000000010,NEUTRAL:00001000000,TWO_INC:00000010000,THREE_DEC:01000000000" *) 
  FDRE \tempmon_state_reg[4] 
       (.C(pi_f_dec_reg_0),
        .CE(\tempmon_state[10]_i_1_n_0 ),
        .D(tempmon_state_nxt[4]),
        .Q(tempmon_state[4]),
        .R(\device_temp_101_reg[0]_0 ));
  (* FSM_ENCODED_STATES = "IDLE:00000000001,ONE_INC:00000100000,FOUR_DEC:10000000000,THREE_INC:00000001000,TWO_DEC:00100000000,FOUR_INC:00000000100,ONE_DEC:00010000000,INIT:00000000010,NEUTRAL:00001000000,TWO_INC:00000010000,THREE_DEC:01000000000" *) 
  FDRE \tempmon_state_reg[5] 
       (.C(pi_f_dec_reg_0),
        .CE(\tempmon_state[10]_i_1_n_0 ),
        .D(tempmon_state_nxt[5]),
        .Q(tempmon_state[5]),
        .R(\device_temp_101_reg[0]_0 ));
  (* FSM_ENCODED_STATES = "IDLE:00000000001,ONE_INC:00000100000,FOUR_DEC:10000000000,THREE_INC:00000001000,TWO_DEC:00100000000,FOUR_INC:00000000100,ONE_DEC:00010000000,INIT:00000000010,NEUTRAL:00001000000,TWO_INC:00000010000,THREE_DEC:01000000000" *) 
  FDRE \tempmon_state_reg[6] 
       (.C(pi_f_dec_reg_0),
        .CE(\tempmon_state[10]_i_1_n_0 ),
        .D(tempmon_state_nxt[6]),
        .Q(tempmon_state[6]),
        .R(\device_temp_101_reg[0]_0 ));
  (* FSM_ENCODED_STATES = "IDLE:00000000001,ONE_INC:00000100000,FOUR_DEC:10000000000,THREE_INC:00000001000,TWO_DEC:00100000000,FOUR_INC:00000000100,ONE_DEC:00010000000,INIT:00000000010,NEUTRAL:00001000000,TWO_INC:00000010000,THREE_DEC:01000000000" *) 
  FDRE \tempmon_state_reg[7] 
       (.C(pi_f_dec_reg_0),
        .CE(\tempmon_state[10]_i_1_n_0 ),
        .D(tempmon_state_nxt[7]),
        .Q(tempmon_state[7]),
        .R(\device_temp_101_reg[0]_0 ));
  (* FSM_ENCODED_STATES = "IDLE:00000000001,ONE_INC:00000100000,FOUR_DEC:10000000000,THREE_INC:00000001000,TWO_DEC:00100000000,FOUR_INC:00000000100,ONE_DEC:00010000000,INIT:00000000010,NEUTRAL:00001000000,TWO_INC:00000010000,THREE_DEC:01000000000" *) 
  FDRE \tempmon_state_reg[8] 
       (.C(pi_f_dec_reg_0),
        .CE(\tempmon_state[10]_i_1_n_0 ),
        .D(tempmon_state_nxt[8]),
        .Q(tempmon_state[8]),
        .R(\device_temp_101_reg[0]_0 ));
  (* FSM_ENCODED_STATES = "IDLE:00000000001,ONE_INC:00000100000,FOUR_DEC:10000000000,THREE_INC:00000001000,TWO_DEC:00100000000,FOUR_INC:00000000100,ONE_DEC:00010000000,INIT:00000000010,NEUTRAL:00001000000,TWO_INC:00000010000,THREE_DEC:01000000000" *) 
  FDRE \tempmon_state_reg[9] 
       (.C(pi_f_dec_reg_0),
        .CE(\tempmon_state[10]_i_1_n_0 ),
        .D(tempmon_state_nxt[9]),
        .Q(tempmon_state[9]),
        .R(\device_temp_101_reg[0]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair243" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \three_dec_max_limit[0]_i_1 
       (.I0(p_0_in),
        .I1(device_temp_init[0]),
        .O(\three_dec_max_limit[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair240" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \three_dec_max_limit[10]_i_1 
       (.I0(\three_dec_max_limit_reg[11]_i_2_n_6 ),
        .I1(p_0_in),
        .O(\three_dec_max_limit[10]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair241" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \three_dec_max_limit[11]_i_1 
       (.I0(\three_dec_max_limit_reg[11]_i_2_n_5 ),
        .I1(p_0_in),
        .O(\three_dec_max_limit[11]_i_1_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_dec_max_limit[11]_i_3 
       (.I0(device_temp_init[9]),
        .O(\three_dec_max_limit[11]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair245" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \three_dec_max_limit[1]_i_1 
       (.I0(\three_inc_max_limit_reg[4]_i_1_n_7 ),
        .I1(p_0_in),
        .O(\three_dec_max_limit[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair245" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \three_dec_max_limit[2]_i_1 
       (.I0(\three_dec_max_limit_reg[4]_i_2_n_6 ),
        .I1(p_0_in),
        .O(\three_dec_max_limit[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair244" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \three_dec_max_limit[3]_i_1 
       (.I0(\three_dec_max_limit_reg[4]_i_2_n_5 ),
        .I1(p_0_in),
        .O(\three_dec_max_limit[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair242" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \three_dec_max_limit[4]_i_1 
       (.I0(\three_dec_max_limit_reg[4]_i_2_n_4 ),
        .I1(p_0_in),
        .O(\three_dec_max_limit[4]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair241" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \three_dec_max_limit[5]_i_1 
       (.I0(\three_dec_max_limit_reg[8]_i_2_n_7 ),
        .I1(p_0_in),
        .O(\three_dec_max_limit[5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair243" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \three_dec_max_limit[6]_i_1 
       (.I0(\three_dec_max_limit_reg[8]_i_2_n_6 ),
        .I1(p_0_in),
        .O(\three_dec_max_limit[6]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair240" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \three_dec_max_limit[7]_i_1 
       (.I0(\three_dec_max_limit_reg[8]_i_2_n_5 ),
        .I1(p_0_in),
        .O(\three_dec_max_limit[7]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair244" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \three_dec_max_limit[8]_i_1 
       (.I0(\three_dec_max_limit_reg[8]_i_2_n_4 ),
        .I1(p_0_in),
        .O(\three_dec_max_limit[8]_i_1_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_dec_max_limit[8]_i_3 
       (.I0(device_temp_init[8]),
        .O(\three_dec_max_limit[8]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_dec_max_limit[8]_i_4 
       (.I0(device_temp_init[6]),
        .O(\three_dec_max_limit[8]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair242" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \three_dec_max_limit[9]_i_1 
       (.I0(\three_dec_max_limit_reg[11]_i_2_n_7 ),
        .I1(p_0_in),
        .O(\three_dec_max_limit[9]_i_1_n_0 ));
  FDRE \three_dec_max_limit_reg[0] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(\three_dec_max_limit[0]_i_1_n_0 ),
        .Q(three_dec_max_limit[0]),
        .R(\four_dec_min_limit_reg[0]_0 ));
  FDRE \three_dec_max_limit_reg[10] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(\three_dec_max_limit[10]_i_1_n_0 ),
        .Q(three_dec_max_limit[10]),
        .R(\four_dec_min_limit_reg[0]_0 ));
  FDRE \three_dec_max_limit_reg[11] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(\three_dec_max_limit[11]_i_1_n_0 ),
        .Q(three_dec_max_limit[11]),
        .R(\four_dec_min_limit_reg[0]_0 ));
  CARRY4 \three_dec_max_limit_reg[11]_i_2 
       (.CI(\three_dec_max_limit_reg[8]_i_2_n_0 ),
        .CO({p_0_in,\NLW_three_dec_max_limit_reg[11]_i_2_CO_UNCONNECTED [2],\three_dec_max_limit_reg[11]_i_2_n_2 ,\three_dec_max_limit_reg[11]_i_2_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,device_temp_init[9]}),
        .O({\NLW_three_dec_max_limit_reg[11]_i_2_O_UNCONNECTED [3],\three_dec_max_limit_reg[11]_i_2_n_5 ,\three_dec_max_limit_reg[11]_i_2_n_6 ,\three_dec_max_limit_reg[11]_i_2_n_7 }),
        .S({1'b1,device_temp_init[11:10],\three_dec_max_limit[11]_i_3_n_0 }));
  FDRE \three_dec_max_limit_reg[1] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(\three_dec_max_limit[1]_i_1_n_0 ),
        .Q(three_dec_max_limit[1]),
        .R(\four_dec_min_limit_reg[0]_0 ));
  FDRE \three_dec_max_limit_reg[2] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(\three_dec_max_limit[2]_i_1_n_0 ),
        .Q(three_dec_max_limit[2]),
        .R(\four_dec_min_limit_reg[0]_0 ));
  FDRE \three_dec_max_limit_reg[3] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(\three_dec_max_limit[3]_i_1_n_0 ),
        .Q(three_dec_max_limit[3]),
        .R(\four_dec_min_limit_reg[0]_0 ));
  FDRE \three_dec_max_limit_reg[4] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(\three_dec_max_limit[4]_i_1_n_0 ),
        .Q(three_dec_max_limit[4]),
        .R(\four_dec_min_limit_reg[0]_0 ));
  CARRY4 \three_dec_max_limit_reg[4]_i_2 
       (.CI(1'b0),
        .CO({\three_dec_max_limit_reg[4]_i_2_n_0 ,\three_dec_max_limit_reg[4]_i_2_n_1 ,\three_dec_max_limit_reg[4]_i_2_n_2 ,\three_dec_max_limit_reg[4]_i_2_n_3 }),
        .CYINIT(device_temp_init[0]),
        .DI({1'b0,1'b0,1'b0,1'b0}),
        .O({\three_dec_max_limit_reg[4]_i_2_n_4 ,\three_dec_max_limit_reg[4]_i_2_n_5 ,\three_dec_max_limit_reg[4]_i_2_n_6 ,\NLW_three_dec_max_limit_reg[4]_i_2_O_UNCONNECTED [0]}),
        .S(device_temp_init[4:1]));
  FDRE \three_dec_max_limit_reg[5] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(\three_dec_max_limit[5]_i_1_n_0 ),
        .Q(three_dec_max_limit[5]),
        .R(\four_dec_min_limit_reg[0]_0 ));
  FDRE \three_dec_max_limit_reg[6] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(\three_dec_max_limit[6]_i_1_n_0 ),
        .Q(three_dec_max_limit[6]),
        .R(\four_dec_min_limit_reg[0]_0 ));
  FDRE \three_dec_max_limit_reg[7] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(\three_dec_max_limit[7]_i_1_n_0 ),
        .Q(three_dec_max_limit[7]),
        .R(\four_dec_min_limit_reg[0]_0 ));
  FDRE \three_dec_max_limit_reg[8] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(\three_dec_max_limit[8]_i_1_n_0 ),
        .Q(three_dec_max_limit[8]),
        .R(\four_dec_min_limit_reg[0]_0 ));
  CARRY4 \three_dec_max_limit_reg[8]_i_2 
       (.CI(\three_dec_max_limit_reg[4]_i_2_n_0 ),
        .CO({\three_dec_max_limit_reg[8]_i_2_n_0 ,\three_dec_max_limit_reg[8]_i_2_n_1 ,\three_dec_max_limit_reg[8]_i_2_n_2 ,\three_dec_max_limit_reg[8]_i_2_n_3 }),
        .CYINIT(1'b0),
        .DI({device_temp_init[8],1'b0,device_temp_init[6],1'b0}),
        .O({\three_dec_max_limit_reg[8]_i_2_n_4 ,\three_dec_max_limit_reg[8]_i_2_n_5 ,\three_dec_max_limit_reg[8]_i_2_n_6 ,\three_dec_max_limit_reg[8]_i_2_n_7 }),
        .S({\three_dec_max_limit[8]_i_3_n_0 ,device_temp_init[7],\three_dec_max_limit[8]_i_4_n_0 ,device_temp_init[5]}));
  FDRE \three_dec_max_limit_reg[9] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(\three_dec_max_limit[9]_i_1_n_0 ),
        .Q(three_dec_max_limit[9]),
        .R(\four_dec_min_limit_reg[0]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_dec_min_limit[11]_i_2 
       (.I0(two_dec_max_limit[11]),
        .O(\three_dec_min_limit[11]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_dec_min_limit[11]_i_3 
       (.I0(two_dec_max_limit[10]),
        .O(\three_dec_min_limit[11]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_dec_min_limit[5]_i_2 
       (.I0(two_dec_max_limit[5]),
        .O(\three_dec_min_limit[5]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_dec_min_limit[5]_i_3 
       (.I0(two_dec_max_limit[4]),
        .O(\three_dec_min_limit[5]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_dec_min_limit[5]_i_4 
       (.I0(two_dec_max_limit[3]),
        .O(\three_dec_min_limit[5]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_dec_min_limit[9]_i_2 
       (.I0(two_dec_max_limit[9]),
        .O(\three_dec_min_limit[9]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_dec_min_limit[9]_i_3 
       (.I0(two_dec_max_limit[8]),
        .O(\three_dec_min_limit[9]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_dec_min_limit[9]_i_4 
       (.I0(two_dec_max_limit[7]),
        .O(\three_dec_min_limit[9]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_dec_min_limit[9]_i_5 
       (.I0(two_dec_max_limit[6]),
        .O(\three_dec_min_limit[9]_i_5_n_0 ));
  FDRE \three_dec_min_limit_reg[0] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(two_dec_max_limit[0]),
        .Q(three_dec_min_limit[0]),
        .R(\one_dec_min_limit_reg[11]_0 ));
  FDRE \three_dec_min_limit_reg[10] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(three_dec_min_limit_nxt[10]),
        .Q(three_dec_min_limit[10]),
        .R(\one_dec_min_limit_reg[11]_0 ));
  FDRE \three_dec_min_limit_reg[11] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(three_dec_min_limit_nxt[11]),
        .Q(three_dec_min_limit[11]),
        .R(\one_dec_min_limit_reg[11]_0 ));
  CARRY4 \three_dec_min_limit_reg[11]_i_1 
       (.CI(\three_dec_min_limit_reg[9]_i_1_n_0 ),
        .CO({\NLW_three_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED [3:1],\three_dec_min_limit_reg[11]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,two_dec_max_limit[10]}),
        .O({\NLW_three_dec_min_limit_reg[11]_i_1_O_UNCONNECTED [3:2],three_dec_min_limit_nxt[11:10]}),
        .S({1'b0,1'b0,\three_dec_min_limit[11]_i_2_n_0 ,\three_dec_min_limit[11]_i_3_n_0 }));
  FDRE \three_dec_min_limit_reg[1] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(two_dec_max_limit[1]),
        .Q(three_dec_min_limit[1]),
        .R(\one_dec_min_limit_reg[11]_0 ));
  FDRE \three_dec_min_limit_reg[2] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(three_dec_min_limit_nxt[2]),
        .Q(three_dec_min_limit[2]),
        .R(\one_dec_min_limit_reg[11]_0 ));
  FDRE \three_dec_min_limit_reg[3] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(three_dec_min_limit_nxt[3]),
        .Q(three_dec_min_limit[3]),
        .R(\one_dec_min_limit_reg[11]_0 ));
  FDRE \three_dec_min_limit_reg[4] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(three_dec_min_limit_nxt[4]),
        .Q(three_dec_min_limit[4]),
        .R(\one_dec_min_limit_reg[11]_0 ));
  FDRE \three_dec_min_limit_reg[5] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(three_dec_min_limit_nxt[5]),
        .Q(three_dec_min_limit[5]),
        .R(\one_dec_min_limit_reg[11]_0 ));
  CARRY4 \three_dec_min_limit_reg[5]_i_1 
       (.CI(1'b0),
        .CO({\three_dec_min_limit_reg[5]_i_1_n_0 ,\three_dec_min_limit_reg[5]_i_1_n_1 ,\three_dec_min_limit_reg[5]_i_1_n_2 ,\three_dec_min_limit_reg[5]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({two_dec_max_limit[5:3],1'b0}),
        .O(three_dec_min_limit_nxt[5:2]),
        .S({\three_dec_min_limit[5]_i_2_n_0 ,\three_dec_min_limit[5]_i_3_n_0 ,\three_dec_min_limit[5]_i_4_n_0 ,two_dec_max_limit[2]}));
  FDRE \three_dec_min_limit_reg[6] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(three_dec_min_limit_nxt[6]),
        .Q(three_dec_min_limit[6]),
        .R(\one_dec_min_limit_reg[11]_0 ));
  FDRE \three_dec_min_limit_reg[7] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(three_dec_min_limit_nxt[7]),
        .Q(three_dec_min_limit[7]),
        .R(\one_dec_min_limit_reg[11]_0 ));
  FDRE \three_dec_min_limit_reg[8] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(three_dec_min_limit_nxt[8]),
        .Q(three_dec_min_limit[8]),
        .R(\one_dec_min_limit_reg[11]_0 ));
  FDRE \three_dec_min_limit_reg[9] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(three_dec_min_limit_nxt[9]),
        .Q(three_dec_min_limit[9]),
        .R(\one_dec_min_limit_reg[11]_0 ));
  CARRY4 \three_dec_min_limit_reg[9]_i_1 
       (.CI(\three_dec_min_limit_reg[5]_i_1_n_0 ),
        .CO({\three_dec_min_limit_reg[9]_i_1_n_0 ,\three_dec_min_limit_reg[9]_i_1_n_1 ,\three_dec_min_limit_reg[9]_i_1_n_2 ,\three_dec_min_limit_reg[9]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI(two_dec_max_limit[9:6]),
        .O(three_dec_min_limit_nxt[9:6]),
        .S({\three_dec_min_limit[9]_i_2_n_0 ,\three_dec_min_limit[9]_i_3_n_0 ,\three_dec_min_limit[9]_i_4_n_0 ,\three_dec_min_limit[9]_i_5_n_0 }));
  LUT1 #(
    .INIT(2'h1)) 
    \three_inc_max_limit[11]_i_2 
       (.I0(device_temp_init[11]),
        .O(\three_inc_max_limit[11]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_inc_max_limit[11]_i_3 
       (.I0(device_temp_init[10]),
        .O(\three_inc_max_limit[11]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_inc_max_limit[4]_i_2 
       (.I0(device_temp_init[3]),
        .O(\three_inc_max_limit[4]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_inc_max_limit[4]_i_3 
       (.I0(device_temp_init[2]),
        .O(\three_inc_max_limit[4]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_inc_max_limit[8]_i_2 
       (.I0(device_temp_init[8]),
        .O(\three_inc_max_limit[8]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_inc_max_limit[8]_i_3 
       (.I0(device_temp_init[7]),
        .O(\three_inc_max_limit[8]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_inc_max_limit[8]_i_4 
       (.I0(device_temp_init[5]),
        .O(\three_inc_max_limit[8]_i_4_n_0 ));
  FDRE \three_inc_max_limit_reg[10] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(three_inc_max_limit_nxt[10]),
        .Q(three_inc_max_limit[10]),
        .R(\one_dec_max_limit_reg[2]_0 ));
  FDRE \three_inc_max_limit_reg[11] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(three_inc_max_limit_nxt[11]),
        .Q(three_inc_max_limit[11]),
        .R(\one_dec_max_limit_reg[2]_0 ));
  CARRY4 \three_inc_max_limit_reg[11]_i_1 
       (.CI(\three_inc_max_limit_reg[8]_i_1_n_0 ),
        .CO({\NLW_three_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED [3:2],\three_inc_max_limit_reg[11]_i_1_n_2 ,\three_inc_max_limit_reg[11]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,device_temp_init[10],1'b0}),
        .O({\NLW_three_inc_max_limit_reg[11]_i_1_O_UNCONNECTED [3],three_inc_max_limit_nxt[11:9]}),
        .S({1'b0,\three_inc_max_limit[11]_i_2_n_0 ,\three_inc_max_limit[11]_i_3_n_0 ,device_temp_init[9]}));
  FDRE \three_inc_max_limit_reg[2] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(three_inc_max_limit_nxt[2]),
        .Q(three_inc_max_limit[2]),
        .R(\one_dec_max_limit_reg[2]_0 ));
  FDRE \three_inc_max_limit_reg[3] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(three_inc_max_limit_nxt[3]),
        .Q(three_inc_max_limit[3]),
        .R(\one_dec_max_limit_reg[2]_0 ));
  FDRE \three_inc_max_limit_reg[4] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(three_inc_max_limit_nxt[4]),
        .Q(three_inc_max_limit[4]),
        .R(\one_dec_max_limit_reg[2]_0 ));
  CARRY4 \three_inc_max_limit_reg[4]_i_1 
       (.CI(1'b0),
        .CO({\three_inc_max_limit_reg[4]_i_1_n_0 ,\three_inc_max_limit_reg[4]_i_1_n_1 ,\three_inc_max_limit_reg[4]_i_1_n_2 ,\three_inc_max_limit_reg[4]_i_1_n_3 }),
        .CYINIT(device_temp_init[0]),
        .DI({1'b0,device_temp_init[3:2],1'b0}),
        .O({three_inc_max_limit_nxt[4:2],\three_inc_max_limit_reg[4]_i_1_n_7 }),
        .S({device_temp_init[4],\three_inc_max_limit[4]_i_2_n_0 ,\three_inc_max_limit[4]_i_3_n_0 ,device_temp_init[1]}));
  FDRE \three_inc_max_limit_reg[5] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(three_inc_max_limit_nxt[5]),
        .Q(three_inc_max_limit[5]),
        .R(\one_dec_max_limit_reg[2]_0 ));
  FDRE \three_inc_max_limit_reg[6] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(three_inc_max_limit_nxt[6]),
        .Q(three_inc_max_limit[6]),
        .R(\one_dec_max_limit_reg[2]_0 ));
  FDRE \three_inc_max_limit_reg[7] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(three_inc_max_limit_nxt[7]),
        .Q(three_inc_max_limit[7]),
        .R(\one_dec_max_limit_reg[2]_0 ));
  FDRE \three_inc_max_limit_reg[8] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(three_inc_max_limit_nxt[8]),
        .Q(three_inc_max_limit[8]),
        .R(\one_dec_max_limit_reg[2]_0 ));
  CARRY4 \three_inc_max_limit_reg[8]_i_1 
       (.CI(\three_inc_max_limit_reg[4]_i_1_n_0 ),
        .CO({\three_inc_max_limit_reg[8]_i_1_n_0 ,\three_inc_max_limit_reg[8]_i_1_n_1 ,\three_inc_max_limit_reg[8]_i_1_n_2 ,\three_inc_max_limit_reg[8]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({device_temp_init[8:7],1'b0,device_temp_init[5]}),
        .O(three_inc_max_limit_nxt[8:5]),
        .S({\three_inc_max_limit[8]_i_2_n_0 ,\three_inc_max_limit[8]_i_3_n_0 ,device_temp_init[6],\three_inc_max_limit[8]_i_4_n_0 }));
  FDRE \three_inc_max_limit_reg[9] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(three_inc_max_limit_nxt[9]),
        .Q(three_inc_max_limit[9]),
        .R(\one_dec_max_limit_reg[2]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_inc_min_limit[11]_i_2 
       (.I0(four_inc_max_limit[11]),
        .O(\three_inc_min_limit[11]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_inc_min_limit[11]_i_3 
       (.I0(four_inc_max_limit[10]),
        .O(\three_inc_min_limit[11]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_inc_min_limit[5]_i_2 
       (.I0(four_inc_max_limit[5]),
        .O(\three_inc_min_limit[5]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_inc_min_limit[5]_i_3 
       (.I0(four_inc_max_limit[4]),
        .O(\three_inc_min_limit[5]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_inc_min_limit[5]_i_4 
       (.I0(four_inc_max_limit[3]),
        .O(\three_inc_min_limit[5]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_inc_min_limit[9]_i_2 
       (.I0(four_inc_max_limit[9]),
        .O(\three_inc_min_limit[9]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_inc_min_limit[9]_i_3 
       (.I0(four_inc_max_limit[8]),
        .O(\three_inc_min_limit[9]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_inc_min_limit[9]_i_4 
       (.I0(four_inc_max_limit[7]),
        .O(\three_inc_min_limit[9]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \three_inc_min_limit[9]_i_5 
       (.I0(four_inc_max_limit[6]),
        .O(\three_inc_min_limit[9]_i_5_n_0 ));
  FDRE \three_inc_min_limit_reg[10] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(three_inc_min_limit_nxt[10]),
        .Q(three_inc_min_limit[10]),
        .R(\neutral_max_limit_reg[11]_0 ));
  FDRE \three_inc_min_limit_reg[11] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(three_inc_min_limit_nxt[11]),
        .Q(three_inc_min_limit[11]),
        .R(\neutral_max_limit_reg[11]_0 ));
  CARRY4 \three_inc_min_limit_reg[11]_i_1 
       (.CI(\three_inc_min_limit_reg[9]_i_1_n_0 ),
        .CO({\NLW_three_inc_min_limit_reg[11]_i_1_CO_UNCONNECTED [3:1],\three_inc_min_limit_reg[11]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,four_inc_max_limit[10]}),
        .O({\NLW_three_inc_min_limit_reg[11]_i_1_O_UNCONNECTED [3:2],three_inc_min_limit_nxt[11:10]}),
        .S({1'b0,1'b0,\three_inc_min_limit[11]_i_2_n_0 ,\three_inc_min_limit[11]_i_3_n_0 }));
  FDRE \three_inc_min_limit_reg[2] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(three_inc_min_limit_nxt[2]),
        .Q(three_inc_min_limit[2]),
        .R(\neutral_max_limit_reg[11]_0 ));
  FDRE \three_inc_min_limit_reg[3] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(three_inc_min_limit_nxt[3]),
        .Q(three_inc_min_limit[3]),
        .R(\neutral_max_limit_reg[11]_0 ));
  FDRE \three_inc_min_limit_reg[4] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(three_inc_min_limit_nxt[4]),
        .Q(three_inc_min_limit[4]),
        .R(\neutral_max_limit_reg[11]_0 ));
  FDRE \three_inc_min_limit_reg[5] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(three_inc_min_limit_nxt[5]),
        .Q(three_inc_min_limit[5]),
        .R(\neutral_max_limit_reg[11]_0 ));
  CARRY4 \three_inc_min_limit_reg[5]_i_1 
       (.CI(1'b0),
        .CO({\three_inc_min_limit_reg[5]_i_1_n_0 ,\three_inc_min_limit_reg[5]_i_1_n_1 ,\three_inc_min_limit_reg[5]_i_1_n_2 ,\three_inc_min_limit_reg[5]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({four_inc_max_limit[5:3],1'b0}),
        .O(three_inc_min_limit_nxt[5:2]),
        .S({\three_inc_min_limit[5]_i_2_n_0 ,\three_inc_min_limit[5]_i_3_n_0 ,\three_inc_min_limit[5]_i_4_n_0 ,four_inc_max_limit[2]}));
  FDRE \three_inc_min_limit_reg[6] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(three_inc_min_limit_nxt[6]),
        .Q(three_inc_min_limit[6]),
        .R(\neutral_max_limit_reg[11]_0 ));
  FDRE \three_inc_min_limit_reg[7] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(three_inc_min_limit_nxt[7]),
        .Q(three_inc_min_limit[7]),
        .R(\neutral_max_limit_reg[11]_0 ));
  FDRE \three_inc_min_limit_reg[8] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(three_inc_min_limit_nxt[8]),
        .Q(three_inc_min_limit[8]),
        .R(\neutral_max_limit_reg[11]_0 ));
  FDRE \three_inc_min_limit_reg[9] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(three_inc_min_limit_nxt[9]),
        .Q(three_inc_min_limit[9]),
        .R(\neutral_max_limit_reg[11]_0 ));
  CARRY4 \three_inc_min_limit_reg[9]_i_1 
       (.CI(\three_inc_min_limit_reg[5]_i_1_n_0 ),
        .CO({\three_inc_min_limit_reg[9]_i_1_n_0 ,\three_inc_min_limit_reg[9]_i_1_n_1 ,\three_inc_min_limit_reg[9]_i_1_n_2 ,\three_inc_min_limit_reg[9]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI(four_inc_max_limit[9:6]),
        .O(three_inc_min_limit_nxt[9:6]),
        .S({\three_inc_min_limit[9]_i_2_n_0 ,\three_inc_min_limit[9]_i_3_n_0 ,\three_inc_min_limit[9]_i_4_n_0 ,\three_inc_min_limit[9]_i_5_n_0 }));
  LUT1 #(
    .INIT(2'h1)) 
    \two_dec_max_limit[0]_i_1 
       (.I0(device_temp_init[0]),
        .O(\two_dec_max_limit[0]_i_1_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_dec_max_limit[11]_i_2 
       (.I0(device_temp_init[9]),
        .O(\two_dec_max_limit[11]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_dec_max_limit[4]_i_2 
       (.I0(device_temp_init[4]),
        .O(\two_dec_max_limit[4]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_dec_max_limit[4]_i_3 
       (.I0(device_temp_init[1]),
        .O(\two_dec_max_limit[4]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_dec_max_limit[8]_i_2 
       (.I0(device_temp_init[6]),
        .O(\two_dec_max_limit[8]_i_2_n_0 ));
  FDRE \two_dec_max_limit_reg[0] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(\two_dec_max_limit[0]_i_1_n_0 ),
        .Q(two_dec_max_limit[0]),
        .R(\neutral_max_limit_reg[11]_0 ));
  FDRE \two_dec_max_limit_reg[10] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(two_dec_max_limit_nxt[10]),
        .Q(two_dec_max_limit[10]),
        .R(\neutral_max_limit_reg[11]_0 ));
  FDRE \two_dec_max_limit_reg[11] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(two_dec_max_limit_nxt[11]),
        .Q(two_dec_max_limit[11]),
        .R(\neutral_max_limit_reg[11]_0 ));
  CARRY4 \two_dec_max_limit_reg[11]_i_1 
       (.CI(\two_dec_max_limit_reg[8]_i_1_n_0 ),
        .CO({\NLW_two_dec_max_limit_reg[11]_i_1_CO_UNCONNECTED [3:2],\two_dec_max_limit_reg[11]_i_1_n_2 ,\two_dec_max_limit_reg[11]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,device_temp_init[9]}),
        .O({\NLW_two_dec_max_limit_reg[11]_i_1_O_UNCONNECTED [3],two_dec_max_limit_nxt[11:9]}),
        .S({1'b0,device_temp_init[11:10],\two_dec_max_limit[11]_i_2_n_0 }));
  FDRE \two_dec_max_limit_reg[1] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(two_dec_max_limit_nxt[1]),
        .Q(two_dec_max_limit[1]),
        .R(\neutral_max_limit_reg[11]_0 ));
  FDRE \two_dec_max_limit_reg[2] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(two_dec_max_limit_nxt[2]),
        .Q(two_dec_max_limit[2]),
        .R(\neutral_max_limit_reg[11]_0 ));
  FDRE \two_dec_max_limit_reg[3] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(two_dec_max_limit_nxt[3]),
        .Q(two_dec_max_limit[3]),
        .R(\neutral_max_limit_reg[11]_0 ));
  FDRE \two_dec_max_limit_reg[4] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(two_dec_max_limit_nxt[4]),
        .Q(two_dec_max_limit[4]),
        .R(\neutral_max_limit_reg[11]_0 ));
  CARRY4 \two_dec_max_limit_reg[4]_i_1 
       (.CI(1'b0),
        .CO({\two_dec_max_limit_reg[4]_i_1_n_0 ,\two_dec_max_limit_reg[4]_i_1_n_1 ,\two_dec_max_limit_reg[4]_i_1_n_2 ,\two_dec_max_limit_reg[4]_i_1_n_3 }),
        .CYINIT(device_temp_init[0]),
        .DI({device_temp_init[4],1'b0,1'b0,device_temp_init[1]}),
        .O({two_dec_max_limit_nxt[4:2],\NLW_two_dec_max_limit_reg[4]_i_1_O_UNCONNECTED [0]}),
        .S({\two_dec_max_limit[4]_i_2_n_0 ,device_temp_init[3:2],\two_dec_max_limit[4]_i_3_n_0 }));
  FDRE \two_dec_max_limit_reg[5] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(two_dec_max_limit_nxt[5]),
        .Q(two_dec_max_limit[5]),
        .R(\neutral_max_limit_reg[11]_0 ));
  FDRE \two_dec_max_limit_reg[6] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(two_dec_max_limit_nxt[6]),
        .Q(two_dec_max_limit[6]),
        .R(\neutral_max_limit_reg[11]_0 ));
  FDRE \two_dec_max_limit_reg[7] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(two_dec_max_limit_nxt[7]),
        .Q(two_dec_max_limit[7]),
        .R(\neutral_max_limit_reg[11]_0 ));
  FDRE \two_dec_max_limit_reg[8] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(two_dec_max_limit_nxt[8]),
        .Q(two_dec_max_limit[8]),
        .R(\neutral_max_limit_reg[11]_0 ));
  CARRY4 \two_dec_max_limit_reg[8]_i_1 
       (.CI(\two_dec_max_limit_reg[4]_i_1_n_0 ),
        .CO({\two_dec_max_limit_reg[8]_i_1_n_0 ,\two_dec_max_limit_reg[8]_i_1_n_1 ,\two_dec_max_limit_reg[8]_i_1_n_2 ,\two_dec_max_limit_reg[8]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,device_temp_init[6],1'b0}),
        .O(two_dec_max_limit_nxt[8:5]),
        .S({device_temp_init[8:7],\two_dec_max_limit[8]_i_2_n_0 ,device_temp_init[5]}));
  FDRE \two_dec_max_limit_reg[9] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(two_dec_max_limit_nxt[9]),
        .Q(two_dec_max_limit[9]),
        .R(\neutral_max_limit_reg[11]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_dec_min_limit[11]_i_2 
       (.I0(one_dec_max_limit[11]),
        .O(\two_dec_min_limit[11]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_dec_min_limit[11]_i_3 
       (.I0(one_dec_max_limit[10]),
        .O(\two_dec_min_limit[11]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_dec_min_limit[5]_i_2 
       (.I0(one_dec_max_limit[5]),
        .O(\two_dec_min_limit[5]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_dec_min_limit[5]_i_3 
       (.I0(one_dec_max_limit[4]),
        .O(\two_dec_min_limit[5]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_dec_min_limit[5]_i_4 
       (.I0(one_dec_max_limit[3]),
        .O(\two_dec_min_limit[5]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_dec_min_limit[9]_i_2 
       (.I0(one_dec_max_limit[9]),
        .O(\two_dec_min_limit[9]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_dec_min_limit[9]_i_3 
       (.I0(one_dec_max_limit[8]),
        .O(\two_dec_min_limit[9]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_dec_min_limit[9]_i_4 
       (.I0(one_dec_max_limit[7]),
        .O(\two_dec_min_limit[9]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_dec_min_limit[9]_i_5 
       (.I0(one_dec_max_limit[6]),
        .O(\two_dec_min_limit[9]_i_5_n_0 ));
  FDRE \two_dec_min_limit_reg[10] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(two_dec_min_limit_nxt[10]),
        .Q(two_dec_min_limit[10]),
        .R(pi_f_dec_reg_1));
  FDRE \two_dec_min_limit_reg[11] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(two_dec_min_limit_nxt[11]),
        .Q(two_dec_min_limit[11]),
        .R(pi_f_dec_reg_1));
  CARRY4 \two_dec_min_limit_reg[11]_i_1 
       (.CI(\two_dec_min_limit_reg[9]_i_1_n_0 ),
        .CO({\NLW_two_dec_min_limit_reg[11]_i_1_CO_UNCONNECTED [3:1],\two_dec_min_limit_reg[11]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,one_dec_max_limit[10]}),
        .O({\NLW_two_dec_min_limit_reg[11]_i_1_O_UNCONNECTED [3:2],two_dec_min_limit_nxt[11:10]}),
        .S({1'b0,1'b0,\two_dec_min_limit[11]_i_2_n_0 ,\two_dec_min_limit[11]_i_3_n_0 }));
  FDRE \two_dec_min_limit_reg[2] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(two_dec_min_limit_nxt[2]),
        .Q(two_dec_min_limit[2]),
        .R(pi_f_dec_reg_1));
  FDRE \two_dec_min_limit_reg[3] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(two_dec_min_limit_nxt[3]),
        .Q(two_dec_min_limit[3]),
        .R(pi_f_dec_reg_1));
  FDRE \two_dec_min_limit_reg[4] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(two_dec_min_limit_nxt[4]),
        .Q(two_dec_min_limit[4]),
        .R(pi_f_dec_reg_1));
  FDRE \two_dec_min_limit_reg[5] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(two_dec_min_limit_nxt[5]),
        .Q(two_dec_min_limit[5]),
        .R(pi_f_dec_reg_1));
  CARRY4 \two_dec_min_limit_reg[5]_i_1 
       (.CI(1'b0),
        .CO({\two_dec_min_limit_reg[5]_i_1_n_0 ,\two_dec_min_limit_reg[5]_i_1_n_1 ,\two_dec_min_limit_reg[5]_i_1_n_2 ,\two_dec_min_limit_reg[5]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({one_dec_max_limit[5:3],1'b0}),
        .O(two_dec_min_limit_nxt[5:2]),
        .S({\two_dec_min_limit[5]_i_2_n_0 ,\two_dec_min_limit[5]_i_3_n_0 ,\two_dec_min_limit[5]_i_4_n_0 ,one_dec_max_limit[2]}));
  FDRE \two_dec_min_limit_reg[6] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(two_dec_min_limit_nxt[6]),
        .Q(two_dec_min_limit[6]),
        .R(pi_f_dec_reg_1));
  FDRE \two_dec_min_limit_reg[7] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(two_dec_min_limit_nxt[7]),
        .Q(two_dec_min_limit[7]),
        .R(pi_f_dec_reg_1));
  FDRE \two_dec_min_limit_reg[8] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(two_dec_min_limit_nxt[8]),
        .Q(two_dec_min_limit[8]),
        .R(pi_f_dec_reg_1));
  FDRE \two_dec_min_limit_reg[9] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(two_dec_min_limit_nxt[9]),
        .Q(two_dec_min_limit[9]),
        .R(pi_f_dec_reg_1));
  CARRY4 \two_dec_min_limit_reg[9]_i_1 
       (.CI(\two_dec_min_limit_reg[5]_i_1_n_0 ),
        .CO({\two_dec_min_limit_reg[9]_i_1_n_0 ,\two_dec_min_limit_reg[9]_i_1_n_1 ,\two_dec_min_limit_reg[9]_i_1_n_2 ,\two_dec_min_limit_reg[9]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI(one_dec_max_limit[9:6]),
        .O(two_dec_min_limit_nxt[9:6]),
        .S({\two_dec_min_limit[9]_i_2_n_0 ,\two_dec_min_limit[9]_i_3_n_0 ,\two_dec_min_limit[9]_i_4_n_0 ,\two_dec_min_limit[9]_i_5_n_0 }));
  LUT1 #(
    .INIT(2'h1)) 
    \two_inc_max_limit[11]_i_2 
       (.I0(device_temp_init[11]),
        .O(\two_inc_max_limit[11]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_inc_max_limit[11]_i_3 
       (.I0(device_temp_init[10]),
        .O(\two_inc_max_limit[11]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_inc_max_limit[11]_i_4 
       (.I0(device_temp_init[9]),
        .O(\two_inc_max_limit[11]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h9)) 
    \two_inc_max_limit[1]_i_1 
       (.I0(device_temp_init[0]),
        .I1(device_temp_init[1]),
        .O(\two_inc_max_limit[1]_i_1_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_inc_max_limit[4]_i_2 
       (.I0(device_temp_init[4]),
        .O(\two_inc_max_limit[4]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_inc_max_limit[4]_i_3 
       (.I0(device_temp_init[3]),
        .O(\two_inc_max_limit[4]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_inc_max_limit[4]_i_4 
       (.I0(device_temp_init[1]),
        .O(\two_inc_max_limit[4]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_inc_max_limit[8]_i_2 
       (.I0(device_temp_init[7]),
        .O(\two_inc_max_limit[8]_i_2_n_0 ));
  FDRE \two_inc_max_limit_reg[10] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(two_inc_max_limit_nxt[10]),
        .Q(two_inc_max_limit[10]),
        .R(\device_temp_101_reg[0]_0 ));
  FDRE \two_inc_max_limit_reg[11] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(two_inc_max_limit_nxt[11]),
        .Q(two_inc_max_limit[11]),
        .R(\device_temp_101_reg[0]_0 ));
  CARRY4 \two_inc_max_limit_reg[11]_i_1 
       (.CI(\two_inc_max_limit_reg[8]_i_1_n_0 ),
        .CO({\NLW_two_inc_max_limit_reg[11]_i_1_CO_UNCONNECTED [3:2],\two_inc_max_limit_reg[11]_i_1_n_2 ,\two_inc_max_limit_reg[11]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,device_temp_init[10:9]}),
        .O({\NLW_two_inc_max_limit_reg[11]_i_1_O_UNCONNECTED [3],two_inc_max_limit_nxt[11:9]}),
        .S({1'b0,\two_inc_max_limit[11]_i_2_n_0 ,\two_inc_max_limit[11]_i_3_n_0 ,\two_inc_max_limit[11]_i_4_n_0 }));
  FDRE \two_inc_max_limit_reg[1] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(\two_inc_max_limit[1]_i_1_n_0 ),
        .Q(two_inc_max_limit[1]),
        .R(\device_temp_101_reg[0]_0 ));
  FDRE \two_inc_max_limit_reg[2] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(two_inc_max_limit_nxt[2]),
        .Q(two_inc_max_limit[2]),
        .R(\device_temp_101_reg[0]_0 ));
  FDRE \two_inc_max_limit_reg[3] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(two_inc_max_limit_nxt[3]),
        .Q(two_inc_max_limit[3]),
        .R(\device_temp_101_reg[0]_0 ));
  FDRE \two_inc_max_limit_reg[4] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(two_inc_max_limit_nxt[4]),
        .Q(two_inc_max_limit[4]),
        .R(\device_temp_101_reg[0]_0 ));
  CARRY4 \two_inc_max_limit_reg[4]_i_1 
       (.CI(1'b0),
        .CO({\two_inc_max_limit_reg[4]_i_1_n_0 ,\two_inc_max_limit_reg[4]_i_1_n_1 ,\two_inc_max_limit_reg[4]_i_1_n_2 ,\two_inc_max_limit_reg[4]_i_1_n_3 }),
        .CYINIT(device_temp_init[0]),
        .DI({device_temp_init[4:3],1'b0,device_temp_init[1]}),
        .O({two_inc_max_limit_nxt[4:2],\NLW_two_inc_max_limit_reg[4]_i_1_O_UNCONNECTED [0]}),
        .S({\two_inc_max_limit[4]_i_2_n_0 ,\two_inc_max_limit[4]_i_3_n_0 ,device_temp_init[2],\two_inc_max_limit[4]_i_4_n_0 }));
  FDRE \two_inc_max_limit_reg[5] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(two_inc_max_limit_nxt[5]),
        .Q(two_inc_max_limit[5]),
        .R(\device_temp_101_reg[0]_0 ));
  FDRE \two_inc_max_limit_reg[6] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(two_inc_max_limit_nxt[6]),
        .Q(two_inc_max_limit[6]),
        .R(\device_temp_101_reg[0]_0 ));
  FDRE \two_inc_max_limit_reg[7] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(two_inc_max_limit_nxt[7]),
        .Q(two_inc_max_limit[7]),
        .R(\device_temp_101_reg[0]_0 ));
  FDRE \two_inc_max_limit_reg[8] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(two_inc_max_limit_nxt[8]),
        .Q(two_inc_max_limit[8]),
        .R(\device_temp_101_reg[0]_0 ));
  CARRY4 \two_inc_max_limit_reg[8]_i_1 
       (.CI(\two_inc_max_limit_reg[4]_i_1_n_0 ),
        .CO({\two_inc_max_limit_reg[8]_i_1_n_0 ,\two_inc_max_limit_reg[8]_i_1_n_1 ,\two_inc_max_limit_reg[8]_i_1_n_2 ,\two_inc_max_limit_reg[8]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,device_temp_init[7],1'b0,1'b0}),
        .O(two_inc_max_limit_nxt[8:5]),
        .S({device_temp_init[8],\two_inc_max_limit[8]_i_2_n_0 ,device_temp_init[6:5]}));
  FDRE \two_inc_max_limit_reg[9] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(two_inc_max_limit_nxt[9]),
        .Q(two_inc_max_limit[9]),
        .R(\device_temp_101_reg[0]_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_inc_min_limit[11]_i_2 
       (.I0(three_inc_max_limit[11]),
        .O(\two_inc_min_limit[11]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_inc_min_limit[11]_i_3 
       (.I0(three_inc_max_limit[10]),
        .O(\two_inc_min_limit[11]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_inc_min_limit[5]_i_2 
       (.I0(three_inc_max_limit[5]),
        .O(\two_inc_min_limit[5]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_inc_min_limit[5]_i_3 
       (.I0(three_inc_max_limit[4]),
        .O(\two_inc_min_limit[5]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_inc_min_limit[5]_i_4 
       (.I0(three_inc_max_limit[3]),
        .O(\two_inc_min_limit[5]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_inc_min_limit[9]_i_2 
       (.I0(three_inc_max_limit[9]),
        .O(\two_inc_min_limit[9]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_inc_min_limit[9]_i_3 
       (.I0(three_inc_max_limit[8]),
        .O(\two_inc_min_limit[9]_i_3_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_inc_min_limit[9]_i_4 
       (.I0(three_inc_max_limit[7]),
        .O(\two_inc_min_limit[9]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \two_inc_min_limit[9]_i_5 
       (.I0(three_inc_max_limit[6]),
        .O(\two_inc_min_limit[9]_i_5_n_0 ));
  FDRE \two_inc_min_limit_reg[10] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(two_inc_min_limit_nxt[10]),
        .Q(two_inc_min_limit[10]),
        .R(\four_dec_min_limit_reg[0]_0 ));
  FDRE \two_inc_min_limit_reg[11] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(two_inc_min_limit_nxt[11]),
        .Q(two_inc_min_limit[11]),
        .R(\four_dec_min_limit_reg[0]_0 ));
  CARRY4 \two_inc_min_limit_reg[11]_i_1 
       (.CI(\two_inc_min_limit_reg[9]_i_1_n_0 ),
        .CO({\NLW_two_inc_min_limit_reg[11]_i_1_CO_UNCONNECTED [3:1],\two_inc_min_limit_reg[11]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b0,1'b0,three_inc_max_limit[10]}),
        .O({\NLW_two_inc_min_limit_reg[11]_i_1_O_UNCONNECTED [3:2],two_inc_min_limit_nxt[11:10]}),
        .S({1'b0,1'b0,\two_inc_min_limit[11]_i_2_n_0 ,\two_inc_min_limit[11]_i_3_n_0 }));
  FDRE \two_inc_min_limit_reg[1] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(one_inc_max_limit[1]),
        .Q(two_inc_min_limit[1]),
        .R(\four_dec_min_limit_reg[0]_0 ));
  FDRE \two_inc_min_limit_reg[2] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(two_inc_min_limit_nxt[2]),
        .Q(two_inc_min_limit[2]),
        .R(\four_dec_min_limit_reg[0]_0 ));
  FDRE \two_inc_min_limit_reg[3] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(two_inc_min_limit_nxt[3]),
        .Q(two_inc_min_limit[3]),
        .R(\four_dec_min_limit_reg[0]_0 ));
  FDRE \two_inc_min_limit_reg[4] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(two_inc_min_limit_nxt[4]),
        .Q(two_inc_min_limit[4]),
        .R(\four_dec_min_limit_reg[0]_0 ));
  FDRE \two_inc_min_limit_reg[5] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(two_inc_min_limit_nxt[5]),
        .Q(two_inc_min_limit[5]),
        .R(\four_dec_min_limit_reg[0]_0 ));
  CARRY4 \two_inc_min_limit_reg[5]_i_1 
       (.CI(1'b0),
        .CO({\two_inc_min_limit_reg[5]_i_1_n_0 ,\two_inc_min_limit_reg[5]_i_1_n_1 ,\two_inc_min_limit_reg[5]_i_1_n_2 ,\two_inc_min_limit_reg[5]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({three_inc_max_limit[5:3],1'b0}),
        .O(two_inc_min_limit_nxt[5:2]),
        .S({\two_inc_min_limit[5]_i_2_n_0 ,\two_inc_min_limit[5]_i_3_n_0 ,\two_inc_min_limit[5]_i_4_n_0 ,three_inc_max_limit[2]}));
  FDRE \two_inc_min_limit_reg[6] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(two_inc_min_limit_nxt[6]),
        .Q(two_inc_min_limit[6]),
        .R(\four_dec_min_limit_reg[0]_0 ));
  FDRE \two_inc_min_limit_reg[7] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(two_inc_min_limit_nxt[7]),
        .Q(two_inc_min_limit[7]),
        .R(\four_dec_min_limit_reg[0]_0 ));
  FDRE \two_inc_min_limit_reg[8] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(two_inc_min_limit_nxt[8]),
        .Q(two_inc_min_limit[8]),
        .R(\four_dec_min_limit_reg[0]_0 ));
  FDRE \two_inc_min_limit_reg[9] 
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(two_inc_min_limit_nxt[9]),
        .Q(two_inc_min_limit[9]),
        .R(\four_dec_min_limit_reg[0]_0 ));
  CARRY4 \two_inc_min_limit_reg[9]_i_1 
       (.CI(\two_inc_min_limit_reg[5]_i_1_n_0 ),
        .CO({\two_inc_min_limit_reg[9]_i_1_n_0 ,\two_inc_min_limit_reg[9]_i_1_n_1 ,\two_inc_min_limit_reg[9]_i_1_n_2 ,\two_inc_min_limit_reg[9]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI(three_inc_max_limit[9:6]),
        .O(two_inc_min_limit_nxt[9:6]),
        .S({\two_inc_min_limit[9]_i_2_n_0 ,\two_inc_min_limit[9]_i_3_n_0 ,\two_inc_min_limit[9]_i_4_n_0 ,\two_inc_min_limit[9]_i_5_n_0 }));
  LUT3 #(
    .INIT(8'h20)) 
    update_temp_101
       (.I0(tempmon_init_complete),
        .I1(tempmon_sample_en_102),
        .I2(tempmon_sample_en_101),
        .O(update_temp_101__0));
  FDRE update_temp_102_reg
       (.C(pi_f_dec_reg_0),
        .CE(1'b1),
        .D(update_temp_101__0),
        .Q(update_temp_102),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_phy_top" *) 
module mig_mig_7series_v4_2_ddr_phy_top
   (ddr3_reset_n,
    ddr3_cas_n,
    ddr3_ras_n,
    ddr3_we_n,
    ddr3_addr,
    ddr3_ba,
    ddr3_cs_n,
    ddr3_odt,
    ddr3_cke,
    ddr3_dm,
    A_rst_primitives_reg,
    A_rst_primitives_reg_0,
    A_rst_primitives_reg_1,
    A_rst_primitives_reg_2,
    A_rst_primitives_reg_3,
    A_rst_primitives_reg_4,
    A_rst_primitives_reg_5,
    A_rst_primitives_reg_6,
    phy_mc_ctl_full,
    rst_tmp,
    po_cnt_dec_reg,
    po_cnt_dec_2,
    fine_adjust_reg,
    new_cnt_cpt_r_reg,
    rdlvl_stg1_start_reg,
    samp_edge_cnt0_en_r,
    pi_cnt_dec_reg,
    new_cnt_dqs_r_reg,
    prbs_rdlvl_done_pulse_reg,
    init_calib_complete,
    init_calib_complete_reg_rep__12,
    init_calib_complete_reg_rep__24,
    init_calib_complete_reg_rep__25,
    init_calib_complete_reg_rep__26,
    init_complete_r1_timing_reg,
    phy_mc_data_full,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_6 ,
    init_calib_complete_reg_rep__26_0,
    app_rd_data_valid,
    \read_fifo.tail_r_reg[0] ,
    \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0] ,
    \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] ,
    \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6] ,
    \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] ,
    \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][12] ,
    \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17] ,
    \init_state_r_reg[4] ,
    ddr_ck_out,
    of_ctl_full_v,
    ddr3_dq,
    ddr3_dqs_p,
    ddr3_dqs_n,
    idle,
    mmcm_ps_clk,
    rst_sync_r1,
    \entry_cnt_reg[4] ,
    freq_refclk,
    mem_refclk,
    sync_pulse,
    pll_locked,
    cal2_if_reset_reg,
    CLKB0,
    CLKB0_7,
    CLKB0_8,
    CLKB0_9,
    RST0,
    SR,
    CLKB0_10,
    CLKB0_11,
    CLKB0_12,
    CLKB0_13,
    \rstdiv2_sync_r_reg[11] ,
    iodelay_ctrl_rdy,
    out,
    \fine_dec_cnt_reg[5] ,
    \corse_inc_reg[6][2] ,
    \wl_dqs_tap_count_r_reg[0][5][5] ,
    po_en_stg2_f_reg,
    first_fail_detect_reg,
    \rdlvl_dqs_tap_cnt_r_reg[0][0][2] ,
    \samp_edge_cnt1_r_reg[0] ,
    \FSM_onehot_cal1_state_r_reg[7] ,
    \samples_cnt_r_reg[0] ,
    \en_cnt_div4.enable_wrlvl_cnt_reg[2] ,
    \victim_sel_reg[0] ,
    \four_dec_min_limit_reg[0] ,
    mc_ref_zq_wip,
    \one_dec_min_limit_reg[11] ,
    \one_dec_max_limit_reg[2] ,
    \idelay_tap_cnt_r_reg[0][0][4] ,
    \not_empty_wait_cnt_reg[4] ,
    \complex_num_writes_reg[1] ,
    d_in,
    Q,
    mc_address,
    mc_ras_n,
    mc_cas_n,
    mc_bank,
    mc_odt,
    mc_cke,
    mc_we_n,
    mc_cs_n,
    app_rd_data_valid_0,
    \read_fifo.tail_r ,
    \idelay_tap_cnt_r_reg[0][4][4] ,
    \pi_rst_stg1_cal_r_reg[1] ,
    \cmp_err_4to1.compare_err_f3_reg ,
    phy_dout,
    \fine_inc_reg[6][3] ,
    \corse_dec_reg[7][0] ,
    SS,
    \wait_cnt_r_reg[0] ,
    \tap_cnt_cpt_r_reg[5] ,
    \cnt_shift_r_reg[0] ,
    \wait_cnt_r_reg[0]_0 ,
    \en_cnt_div4.enable_wrlvl_cnt_reg[4] ,
    \device_temp_101_reg[11] ,
    \data_offset_1_i1_reg[0] ,
    \data_offset_1_i1_reg[1] ,
    \data_offset_1_i1_reg[2] ,
    mc_data_offset_1,
    \data_offset_1_i1_reg[4] ,
    \data_offset_1_i1_reg[5] ,
    \data_offset_2_i1_reg[0] ,
    \data_offset_2_i1_reg[1] ,
    \data_offset_2_i1_reg[2] ,
    mc_data_offset_2,
    \data_offset_2_i1_reg[4] ,
    \data_offset_2_i1_reg[5] ,
    mc_cmd,
    \phy_ctl_wd_i1_reg[17] ,
    \phy_ctl_wd_i1_reg[18] ,
    \phy_ctl_wd_i1_reg[19] ,
    mc_data_offset,
    \phy_ctl_wd_i1_reg[21] ,
    \phy_ctl_wd_i1_reg[22] ,
    mc_wrdata_en);
  output ddr3_reset_n;
  output ddr3_cas_n;
  output ddr3_ras_n;
  output ddr3_we_n;
  output [13:0]ddr3_addr;
  output [2:0]ddr3_ba;
  output [0:0]ddr3_cs_n;
  output [0:0]ddr3_odt;
  output [0:0]ddr3_cke;
  output [7:0]ddr3_dm;
  output A_rst_primitives_reg;
  output A_rst_primitives_reg_0;
  output A_rst_primitives_reg_1;
  output A_rst_primitives_reg_2;
  output A_rst_primitives_reg_3;
  output A_rst_primitives_reg_4;
  output A_rst_primitives_reg_5;
  output A_rst_primitives_reg_6;
  output phy_mc_ctl_full;
  output rst_tmp;
  output po_cnt_dec_reg;
  output po_cnt_dec_2;
  output fine_adjust_reg;
  output new_cnt_cpt_r_reg;
  output rdlvl_stg1_start_reg;
  output samp_edge_cnt0_en_r;
  output pi_cnt_dec_reg;
  output new_cnt_dqs_r_reg;
  output prbs_rdlvl_done_pulse_reg;
  output init_calib_complete;
  output init_calib_complete_reg_rep__12;
  output init_calib_complete_reg_rep__24;
  output init_calib_complete_reg_rep__25;
  output init_calib_complete_reg_rep__26;
  output init_complete_r1_timing_reg;
  output phy_mc_data_full;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_6 ;
  output init_calib_complete_reg_rep__26_0;
  output app_rd_data_valid;
  output \read_fifo.tail_r_reg[0] ;
  output \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0] ;
  output [5:0]\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] ;
  output \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6] ;
  output [5:0]\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] ;
  output \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][12] ;
  output [5:0]\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17] ;
  output \init_state_r_reg[4] ;
  output [1:0]ddr_ck_out;
  output [0:0]of_ctl_full_v;
  inout [63:0]ddr3_dq;
  inout [7:0]ddr3_dqs_p;
  inout [7:0]ddr3_dqs_n;
  input idle;
  input mmcm_ps_clk;
  input rst_sync_r1;
  input \entry_cnt_reg[4] ;
  input freq_refclk;
  input mem_refclk;
  input sync_pulse;
  input pll_locked;
  input cal2_if_reset_reg;
  input CLKB0;
  input CLKB0_7;
  input CLKB0_8;
  input CLKB0_9;
  input RST0;
  input [0:0]SR;
  input CLKB0_10;
  input CLKB0_11;
  input CLKB0_12;
  input CLKB0_13;
  input \rstdiv2_sync_r_reg[11] ;
  input [0:0]iodelay_ctrl_rdy;
  input out;
  input [1:0]\fine_dec_cnt_reg[5] ;
  input [1:0]\corse_inc_reg[6][2] ;
  input \wl_dqs_tap_count_r_reg[0][5][5] ;
  input po_en_stg2_f_reg;
  input first_fail_detect_reg;
  input [1:0]\rdlvl_dqs_tap_cnt_r_reg[0][0][2] ;
  input \samp_edge_cnt1_r_reg[0] ;
  input [0:0]\FSM_onehot_cal1_state_r_reg[7] ;
  input \samples_cnt_r_reg[0] ;
  input \en_cnt_div4.enable_wrlvl_cnt_reg[2] ;
  input [0:0]\victim_sel_reg[0] ;
  input \four_dec_min_limit_reg[0] ;
  input mc_ref_zq_wip;
  input \one_dec_min_limit_reg[11] ;
  input \one_dec_max_limit_reg[2] ;
  input \idelay_tap_cnt_r_reg[0][0][4] ;
  input \not_empty_wait_cnt_reg[4] ;
  input \complex_num_writes_reg[1] ;
  input [3:0]d_in;
  input [575:0]Q;
  input [38:0]mc_address;
  input [2:0]mc_ras_n;
  input [2:0]mc_cas_n;
  input [8:0]mc_bank;
  input [0:0]mc_odt;
  input [0:0]mc_cke;
  input [2:0]mc_we_n;
  input [0:0]mc_cs_n;
  input [0:0]app_rd_data_valid_0;
  input [0:0]\read_fifo.tail_r ;
  input \idelay_tap_cnt_r_reg[0][4][4] ;
  input \pi_rst_stg1_cal_r_reg[1] ;
  input \cmp_err_4to1.compare_err_f3_reg ;
  input [6:0]phy_dout;
  input [1:0]\fine_inc_reg[6][3] ;
  input [1:0]\corse_dec_reg[7][0] ;
  input [0:0]SS;
  input [0:0]\wait_cnt_r_reg[0] ;
  input [0:0]\tap_cnt_cpt_r_reg[5] ;
  input [0:0]\cnt_shift_r_reg[0] ;
  input [0:0]\wait_cnt_r_reg[0]_0 ;
  input \en_cnt_div4.enable_wrlvl_cnt_reg[4] ;
  input [11:0]\device_temp_101_reg[11] ;
  input \data_offset_1_i1_reg[0] ;
  input \data_offset_1_i1_reg[1] ;
  input \data_offset_1_i1_reg[2] ;
  input [0:0]mc_data_offset_1;
  input \data_offset_1_i1_reg[4] ;
  input \data_offset_1_i1_reg[5] ;
  input \data_offset_2_i1_reg[0] ;
  input \data_offset_2_i1_reg[1] ;
  input \data_offset_2_i1_reg[2] ;
  input [0:0]mc_data_offset_2;
  input \data_offset_2_i1_reg[4] ;
  input \data_offset_2_i1_reg[5] ;
  input [1:0]mc_cmd;
  input \phy_ctl_wd_i1_reg[17] ;
  input \phy_ctl_wd_i1_reg[18] ;
  input \phy_ctl_wd_i1_reg[19] ;
  input [0:0]mc_data_offset;
  input \phy_ctl_wd_i1_reg[21] ;
  input \phy_ctl_wd_i1_reg[22] ;
  input mc_wrdata_en;

  wire A_rst_primitives_reg;
  wire A_rst_primitives_reg_0;
  wire A_rst_primitives_reg_1;
  wire A_rst_primitives_reg_2;
  wire A_rst_primitives_reg_3;
  wire A_rst_primitives_reg_4;
  wire A_rst_primitives_reg_5;
  wire A_rst_primitives_reg_6;
  wire CLKB0;
  wire CLKB0_10;
  wire CLKB0_11;
  wire CLKB0_12;
  wire CLKB0_13;
  wire CLKB0_7;
  wire CLKB0_8;
  wire CLKB0_9;
  wire [0:0]\FSM_onehot_cal1_state_r_reg[7] ;
  wire [575:0]Q;
  wire RST0;
  wire [0:0]SR;
  wire [0:0]SS;
  wire app_rd_data_valid;
  wire [0:0]app_rd_data_valid_0;
  wire cal2_if_reset_reg;
  wire [4:0]calib_sel;
  wire \cmp_err_4to1.compare_err_f3_reg ;
  wire [0:0]\cnt_shift_r_reg[0] ;
  wire \complex_num_writes_reg[1] ;
  wire [1:0]\corse_dec_reg[7][0] ;
  wire [1:0]\corse_inc_reg[6][2] ;
  wire [3:0]d_in;
  wire [5:0]data_offset_1;
  wire \data_offset_1_i1_reg[0] ;
  wire \data_offset_1_i1_reg[1] ;
  wire \data_offset_1_i1_reg[2] ;
  wire \data_offset_1_i1_reg[4] ;
  wire \data_offset_1_i1_reg[5] ;
  wire [5:0]data_offset_2;
  wire \data_offset_2_i1_reg[0] ;
  wire \data_offset_2_i1_reg[1] ;
  wire \data_offset_2_i1_reg[2] ;
  wire \data_offset_2_i1_reg[4] ;
  wire \data_offset_2_i1_reg[5] ;
  wire [13:0]ddr3_addr;
  wire [2:0]ddr3_ba;
  wire ddr3_cas_n;
  wire [0:0]ddr3_cke;
  wire [0:0]ddr3_cs_n;
  wire [7:0]ddr3_dm;
  wire [63:0]ddr3_dq;
  wire [7:0]ddr3_dqs_n;
  wire [7:0]ddr3_dqs_p;
  wire [0:0]ddr3_odt;
  wire ddr3_ras_n;
  wire ddr3_reset_n;
  wire ddr3_we_n;
  wire [1:0]ddr_ck_out;
  wire [2:0]\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl/rd_mux_sel_r ;
  wire [11:0]\device_temp_101_reg[11] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ;
  wire \en_cnt_div4.enable_wrlvl_cnt_reg[2] ;
  wire \en_cnt_div4.enable_wrlvl_cnt_reg[4] ;
  wire \entry_cnt_reg[4] ;
  wire fine_adjust_reg;
  wire [1:0]\fine_dec_cnt_reg[5] ;
  wire [1:0]\fine_inc_reg[6][3] ;
  wire first_fail_detect_reg;
  wire \four_dec_min_limit_reg[0] ;
  wire freq_refclk;
  wire idelay_inc;
  wire \idelay_tap_cnt_r_reg[0][0][4] ;
  wire \idelay_tap_cnt_r_reg[0][4][4] ;
  wire idle;
  wire if_empty;
  wire init_calib_complete;
  wire init_calib_complete_reg_rep__12;
  wire init_calib_complete_reg_rep__24;
  wire init_calib_complete_reg_rep__25;
  wire init_calib_complete_reg_rep__26;
  wire init_calib_complete_reg_rep__26_0;
  wire init_complete_r1_timing_reg;
  wire \init_state_r_reg[4] ;
  wire [0:0]iodelay_ctrl_rdy;
  wire [38:0]mc_address;
  wire [8:0]mc_bank;
  wire [2:0]mc_cas_n;
  wire [0:0]mc_cke;
  wire [1:0]mc_cmd;
  wire [0:0]mc_cs_n;
  wire [0:0]mc_data_offset;
  wire [0:0]mc_data_offset_1;
  wire [0:0]mc_data_offset_2;
  wire [0:0]mc_odt;
  wire [2:0]mc_ras_n;
  wire mc_ref_zq_wip;
  wire [2:0]mc_we_n;
  wire mc_wrdata_en;
  wire mem_refclk;
  wire mmcm_ps_clk;
  wire [54:0]mux_address;
  wire [11:0]mux_bank;
  wire [1:1]mux_cas_n;
  wire [3:3]mux_cke;
  wire [1:1]mux_cs_n;
  wire [0:0]mux_odt;
  wire [1:1]mux_ras_n;
  wire mux_reset_n;
  wire [1:1]mux_we_n;
  wire [511:0]mux_wrdata;
  wire [63:0]mux_wrdata_mask;
  wire new_cnt_cpt_r_reg;
  wire new_cnt_dqs_r_reg;
  wire \not_empty_wait_cnt_reg[4] ;
  wire [0:0]of_ctl_full_v;
  wire \one_dec_max_limit_reg[2] ;
  wire \one_dec_min_limit_reg[11] ;
  wire out;
  wire phy_cmd_wr_en;
  wire [24:0]phy_ctl_wd;
  wire \phy_ctl_wd_i1_reg[17] ;
  wire \phy_ctl_wd_i1_reg[18] ;
  wire \phy_ctl_wd_i1_reg[19] ;
  wire \phy_ctl_wd_i1_reg[21] ;
  wire \phy_ctl_wd_i1_reg[22] ;
  wire phy_data_wr_en;
  wire [6:0]phy_dout;
  wire phy_if_reset;
  wire phy_mc_ctl_full;
  wire phy_mc_data_full;
  wire phy_mc_go;
  wire phy_rddata_en;
  wire phy_read_calib;
  wire phy_write_calib;
  wire pi_cnt_dec_reg;
  (* async_reg = "true" *) wire pi_counter_load_en;
  (* async_reg = "true" *) wire [5:0]pi_counter_load_val;
  (* async_reg = "true" *) wire [2:0]pi_dqs_find_rst;
  (* async_reg = "true" *) wire pi_enstg2_f_div2r1;
  (* async_reg = "true" *) wire pi_enstg2_f_div2r2;
  (* async_reg = "true" *) wire pi_enstg2_f_div2r3;
  (* async_reg = "true" *) wire pi_fine_enable;
  (* async_reg = "true" *) wire pi_fine_inc;
  (* async_reg = "true" *) wire [2:0]pi_rst_dqs_find;
  wire \pi_rst_stg1_cal_r_reg[1] ;
  (* async_reg = "true" *) wire pi_stg2_fincdec_div2r1;
  (* async_reg = "true" *) wire pi_stg2_fincdec_div2r2;
  (* async_reg = "true" *) wire pi_stg2_fincdec_div2r3;
  (* async_reg = "true" *) wire pi_stg2_load_div2r1;
  (* async_reg = "true" *) wire pi_stg2_load_div2r2;
  (* async_reg = "true" *) wire pi_stg2_load_div2r3;
  (* async_reg = "true" *) wire [5:0]pi_stg2_reg_l_div2r1;
  (* async_reg = "true" *) wire [5:0]pi_stg2_reg_l_div2r2;
  (* async_reg = "true" *) wire [5:0]pi_stg2_reg_l_div2r3;
  wire pll_locked;
  wire po_cnt_dec_2;
  wire po_cnt_dec_reg;
  wire po_en_stg2_f_reg;
  wire [2:0]po_stg2_wrcal_cnt;
  wire prbs_rdlvl_done_pulse_reg;
  wire \rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0] ;
  wire [5:0]\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] ;
  wire [5:0]\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] ;
  wire \rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6] ;
  wire \rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][12] ;
  wire [5:0]\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17] ;
  wire [1:0]\rdlvl_dqs_tap_cnt_r_reg[0][0][2] ;
  wire rdlvl_stg1_start_reg;
  wire [0:0]\read_fifo.tail_r ;
  wire \read_fifo.tail_r_reg[0] ;
  (* async_reg = "true" *) wire [2:0]rst_stg1_cal_div2r1;
  (* async_reg = "true" *) wire [2:0]rst_stg1_cal_div2r2;
  wire rst_sync_r1;
  wire rst_tmp;
  wire \rstdiv2_sync_r_reg[11] ;
  wire samp_edge_cnt0_en_r;
  wire \samp_edge_cnt1_r_reg[0] ;
  wire \samples_cnt_r_reg[0] ;
  wire sync_pulse;
  wire [0:0]\tap_cnt_cpt_r_reg[5] ;
  wire u_ddr_calib_top_n_1373;
  (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire u_ddr_calib_top_n_52;
  (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire u_ddr_calib_top_n_53;
  (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire u_ddr_calib_top_n_54;
  wire u_ddr_calib_top_n_64;
  wire u_ddr_calib_top_n_65;
  wire u_ddr_calib_top_n_66;
  wire u_ddr_calib_top_n_680;
  wire u_ddr_calib_top_n_681;
  wire u_ddr_calib_top_n_682;
  wire u_ddr_calib_top_n_683;
  wire u_ddr_calib_top_n_684;
  wire u_ddr_calib_top_n_685;
  wire u_ddr_calib_top_n_686;
  wire u_ddr_calib_top_n_687;
  wire u_ddr_calib_top_n_688;
  wire u_ddr_calib_top_n_689;
  wire u_ddr_calib_top_n_690;
  wire u_ddr_calib_top_n_691;
  wire u_ddr_calib_top_n_692;
  wire u_ddr_calib_top_n_693;
  wire u_ddr_calib_top_n_694;
  wire u_ddr_calib_top_n_695;
  wire u_ddr_calib_top_n_696;
  wire u_ddr_calib_top_n_697;
  wire u_ddr_calib_top_n_698;
  wire u_ddr_calib_top_n_699;
  wire u_ddr_calib_top_n_700;
  wire u_ddr_calib_top_n_701;
  wire u_ddr_calib_top_n_702;
  wire u_ddr_calib_top_n_703;
  wire u_ddr_calib_top_n_704;
  wire u_ddr_calib_top_n_705;
  wire u_ddr_calib_top_n_706;
  wire u_ddr_calib_top_n_707;
  wire u_ddr_calib_top_n_708;
  wire u_ddr_calib_top_n_709;
  wire u_ddr_calib_top_n_710;
  wire u_ddr_calib_top_n_711;
  wire u_ddr_calib_top_n_712;
  wire u_ddr_calib_top_n_713;
  wire u_ddr_calib_top_n_714;
  wire u_ddr_calib_top_n_715;
  wire u_ddr_calib_top_n_716;
  wire u_ddr_calib_top_n_717;
  wire u_ddr_calib_top_n_718;
  wire u_ddr_calib_top_n_719;
  wire u_ddr_calib_top_n_720;
  wire u_ddr_calib_top_n_721;
  wire u_ddr_calib_top_n_722;
  wire u_ddr_calib_top_n_723;
  wire u_ddr_calib_top_n_724;
  wire u_ddr_calib_top_n_725;
  wire u_ddr_calib_top_n_726;
  wire u_ddr_calib_top_n_727;
  wire u_ddr_calib_top_n_728;
  wire u_ddr_calib_top_n_729;
  wire u_ddr_calib_top_n_730;
  wire u_ddr_calib_top_n_731;
  wire u_ddr_calib_top_n_732;
  wire u_ddr_calib_top_n_733;
  wire u_ddr_calib_top_n_734;
  wire u_ddr_calib_top_n_735;
  wire u_ddr_calib_top_n_736;
  wire u_ddr_calib_top_n_737;
  wire u_ddr_calib_top_n_738;
  wire u_ddr_calib_top_n_739;
  wire u_ddr_calib_top_n_740;
  wire u_ddr_calib_top_n_741;
  wire u_ddr_calib_top_n_742;
  wire u_ddr_calib_top_n_743;
  wire u_ddr_calib_top_n_745;
  wire u_ddr_calib_top_n_746;
  wire u_ddr_calib_top_n_748;
  wire u_ddr_calib_top_n_749;
  wire u_ddr_calib_top_n_750;
  wire u_ddr_calib_top_n_751;
  wire u_ddr_calib_top_n_753;
  wire u_ddr_calib_top_n_754;
  wire u_ddr_calib_top_n_755;
  wire u_ddr_calib_top_n_756;
  wire u_ddr_calib_top_n_757;
  wire u_ddr_calib_top_n_758;
  wire u_ddr_calib_top_n_759;
  wire u_ddr_calib_top_n_760;
  wire u_ddr_calib_top_n_762;
  wire u_ddr_calib_top_n_763;
  wire [5:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/A_pi_counter_load_val ;
  wire [5:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_pi_counter_load_val ;
  wire [5:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_pi_counter_load_val ;
  wire [5:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_pi_counter_load_val ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/LD0 ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/idelay_ld_rst ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d2 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d3 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d4 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d5 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d6 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d7 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d9 ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/LD0 ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/idelay_ld_rst ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d2 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d3 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d4 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d5 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d7 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d8 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d9 ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/LD0 ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/idelay_ld_rst ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d3 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d4 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d8 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d9 ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/LD0 ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/idelay_ld_rst ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d2 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d3 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d4 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d5 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d6 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d7 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d8 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d9 ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/C_po_coarse_enable26_out ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/C_po_counter_read_en38_out ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/C_po_fine_enable23_out ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/C_po_fine_inc29_out ;
  wire [3:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d2 ;
  wire [1:1]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d4 ;
  wire [5:1]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d5 ;
  wire [5:5]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6 ;
  wire [3:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d7 ;
  wire [75:32]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out ;
  wire [3:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d4 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5 ;
  wire [7:4]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6 ;
  wire [3:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d8 ;
  wire [3:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d9 ;
  wire [3:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d1 ;
  wire [3:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d3 ;
  wire [3:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d4 ;
  wire [7:4]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d5 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d6 ;
  wire [3:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d7 ;
  wire [3:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d8 ;
  wire [3:0]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d9 ;
  wire [59:16]\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/mem_out ;
  wire [5:0]\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/A_pi_counter_load_val ;
  wire [5:0]\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/B_pi_counter_load_val ;
  wire [5:0]\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/C_pi_counter_load_val ;
  wire [5:0]\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/D_pi_counter_load_val ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/LD0 ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/idelay_ld_rst ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d2 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d3 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d4 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d5 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d6 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d7 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d9 ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/LD0 ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/idelay_ld_rst ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d2 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d3 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d4 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d5 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d7 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d8 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d9 ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/LD0 ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/idelay_ld_rst ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d3 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d4 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d8 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d9 ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/LD0 ;
  wire \u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/idelay_ld_rst ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d2 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d3 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d4 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d5 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d6 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d7 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d8 ;
  wire [7:0]\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d9 ;
  wire [5:0]\u_ddr_mc_phy/pi_counter_read_val_w[0]_1 ;
  wire [5:0]\u_ddr_mc_phy/pi_counter_read_val_w[2]_3 ;
  wire u_ddr_mc_phy_wrapper_n_1000;
  wire u_ddr_mc_phy_wrapper_n_1001;
  wire u_ddr_mc_phy_wrapper_n_1002;
  wire u_ddr_mc_phy_wrapper_n_1003;
  wire u_ddr_mc_phy_wrapper_n_1004;
  wire u_ddr_mc_phy_wrapper_n_1005;
  wire u_ddr_mc_phy_wrapper_n_1006;
  wire u_ddr_mc_phy_wrapper_n_1007;
  wire u_ddr_mc_phy_wrapper_n_1008;
  wire u_ddr_mc_phy_wrapper_n_1009;
  wire u_ddr_mc_phy_wrapper_n_1010;
  wire u_ddr_mc_phy_wrapper_n_1011;
  wire u_ddr_mc_phy_wrapper_n_1012;
  wire u_ddr_mc_phy_wrapper_n_1013;
  wire u_ddr_mc_phy_wrapper_n_1014;
  wire u_ddr_mc_phy_wrapper_n_1015;
  wire u_ddr_mc_phy_wrapper_n_1016;
  wire u_ddr_mc_phy_wrapper_n_1017;
  wire u_ddr_mc_phy_wrapper_n_1018;
  wire u_ddr_mc_phy_wrapper_n_1019;
  wire u_ddr_mc_phy_wrapper_n_1020;
  wire u_ddr_mc_phy_wrapper_n_1021;
  wire u_ddr_mc_phy_wrapper_n_1022;
  wire u_ddr_mc_phy_wrapper_n_1023;
  wire u_ddr_mc_phy_wrapper_n_1024;
  wire u_ddr_mc_phy_wrapper_n_1025;
  wire u_ddr_mc_phy_wrapper_n_1026;
  wire u_ddr_mc_phy_wrapper_n_1027;
  wire u_ddr_mc_phy_wrapper_n_1028;
  wire u_ddr_mc_phy_wrapper_n_1029;
  wire u_ddr_mc_phy_wrapper_n_1030;
  wire u_ddr_mc_phy_wrapper_n_1031;
  wire u_ddr_mc_phy_wrapper_n_1032;
  wire u_ddr_mc_phy_wrapper_n_1033;
  wire u_ddr_mc_phy_wrapper_n_1034;
  wire u_ddr_mc_phy_wrapper_n_1035;
  wire u_ddr_mc_phy_wrapper_n_1036;
  wire u_ddr_mc_phy_wrapper_n_1037;
  wire u_ddr_mc_phy_wrapper_n_1038;
  wire u_ddr_mc_phy_wrapper_n_1039;
  wire u_ddr_mc_phy_wrapper_n_1040;
  wire u_ddr_mc_phy_wrapper_n_1041;
  wire u_ddr_mc_phy_wrapper_n_1042;
  wire u_ddr_mc_phy_wrapper_n_1043;
  wire u_ddr_mc_phy_wrapper_n_1044;
  wire u_ddr_mc_phy_wrapper_n_1045;
  wire u_ddr_mc_phy_wrapper_n_1046;
  wire u_ddr_mc_phy_wrapper_n_1047;
  wire u_ddr_mc_phy_wrapper_n_1048;
  wire u_ddr_mc_phy_wrapper_n_1049;
  wire u_ddr_mc_phy_wrapper_n_1050;
  wire u_ddr_mc_phy_wrapper_n_1051;
  wire u_ddr_mc_phy_wrapper_n_1052;
  wire u_ddr_mc_phy_wrapper_n_1053;
  wire u_ddr_mc_phy_wrapper_n_1054;
  wire u_ddr_mc_phy_wrapper_n_1055;
  wire u_ddr_mc_phy_wrapper_n_1056;
  wire u_ddr_mc_phy_wrapper_n_1057;
  wire u_ddr_mc_phy_wrapper_n_1058;
  wire u_ddr_mc_phy_wrapper_n_1059;
  wire u_ddr_mc_phy_wrapper_n_1060;
  wire u_ddr_mc_phy_wrapper_n_1061;
  wire u_ddr_mc_phy_wrapper_n_1062;
  wire u_ddr_mc_phy_wrapper_n_1063;
  wire u_ddr_mc_phy_wrapper_n_1064;
  wire u_ddr_mc_phy_wrapper_n_1065;
  wire u_ddr_mc_phy_wrapper_n_1066;
  wire u_ddr_mc_phy_wrapper_n_1067;
  wire u_ddr_mc_phy_wrapper_n_1068;
  wire u_ddr_mc_phy_wrapper_n_1069;
  wire u_ddr_mc_phy_wrapper_n_1070;
  wire u_ddr_mc_phy_wrapper_n_1071;
  wire u_ddr_mc_phy_wrapper_n_1072;
  wire u_ddr_mc_phy_wrapper_n_1073;
  wire u_ddr_mc_phy_wrapper_n_1074;
  wire u_ddr_mc_phy_wrapper_n_1075;
  wire u_ddr_mc_phy_wrapper_n_1076;
  wire u_ddr_mc_phy_wrapper_n_1077;
  wire u_ddr_mc_phy_wrapper_n_1078;
  wire u_ddr_mc_phy_wrapper_n_1079;
  wire u_ddr_mc_phy_wrapper_n_1080;
  wire u_ddr_mc_phy_wrapper_n_1081;
  wire u_ddr_mc_phy_wrapper_n_1082;
  wire u_ddr_mc_phy_wrapper_n_1083;
  wire u_ddr_mc_phy_wrapper_n_1084;
  wire u_ddr_mc_phy_wrapper_n_1085;
  wire u_ddr_mc_phy_wrapper_n_1086;
  wire u_ddr_mc_phy_wrapper_n_1087;
  wire u_ddr_mc_phy_wrapper_n_1088;
  wire u_ddr_mc_phy_wrapper_n_1089;
  wire u_ddr_mc_phy_wrapper_n_1090;
  wire u_ddr_mc_phy_wrapper_n_1091;
  wire u_ddr_mc_phy_wrapper_n_1092;
  wire u_ddr_mc_phy_wrapper_n_1093;
  wire u_ddr_mc_phy_wrapper_n_1094;
  wire u_ddr_mc_phy_wrapper_n_1095;
  wire u_ddr_mc_phy_wrapper_n_1096;
  wire u_ddr_mc_phy_wrapper_n_1097;
  wire u_ddr_mc_phy_wrapper_n_1098;
  wire u_ddr_mc_phy_wrapper_n_1099;
  wire u_ddr_mc_phy_wrapper_n_1100;
  wire u_ddr_mc_phy_wrapper_n_1101;
  wire u_ddr_mc_phy_wrapper_n_1102;
  wire u_ddr_mc_phy_wrapper_n_1103;
  wire u_ddr_mc_phy_wrapper_n_1104;
  wire u_ddr_mc_phy_wrapper_n_1105;
  wire u_ddr_mc_phy_wrapper_n_1106;
  wire u_ddr_mc_phy_wrapper_n_1107;
  wire u_ddr_mc_phy_wrapper_n_1108;
  wire u_ddr_mc_phy_wrapper_n_1109;
  wire u_ddr_mc_phy_wrapper_n_1110;
  wire u_ddr_mc_phy_wrapper_n_1111;
  wire u_ddr_mc_phy_wrapper_n_1112;
  wire u_ddr_mc_phy_wrapper_n_1113;
  wire u_ddr_mc_phy_wrapper_n_1114;
  wire u_ddr_mc_phy_wrapper_n_1115;
  wire u_ddr_mc_phy_wrapper_n_1116;
  wire u_ddr_mc_phy_wrapper_n_1117;
  wire u_ddr_mc_phy_wrapper_n_1118;
  wire u_ddr_mc_phy_wrapper_n_1119;
  wire u_ddr_mc_phy_wrapper_n_1120;
  wire u_ddr_mc_phy_wrapper_n_1121;
  wire u_ddr_mc_phy_wrapper_n_1122;
  wire u_ddr_mc_phy_wrapper_n_1123;
  wire u_ddr_mc_phy_wrapper_n_1124;
  wire u_ddr_mc_phy_wrapper_n_1125;
  wire u_ddr_mc_phy_wrapper_n_1126;
  wire u_ddr_mc_phy_wrapper_n_1127;
  wire u_ddr_mc_phy_wrapper_n_1128;
  wire u_ddr_mc_phy_wrapper_n_1129;
  wire u_ddr_mc_phy_wrapper_n_1130;
  wire u_ddr_mc_phy_wrapper_n_1131;
  wire u_ddr_mc_phy_wrapper_n_1132;
  wire u_ddr_mc_phy_wrapper_n_1133;
  wire u_ddr_mc_phy_wrapper_n_1134;
  wire u_ddr_mc_phy_wrapper_n_1135;
  wire u_ddr_mc_phy_wrapper_n_1136;
  wire u_ddr_mc_phy_wrapper_n_1137;
  wire u_ddr_mc_phy_wrapper_n_1138;
  wire u_ddr_mc_phy_wrapper_n_1139;
  wire u_ddr_mc_phy_wrapper_n_1140;
  wire u_ddr_mc_phy_wrapper_n_1141;
  wire u_ddr_mc_phy_wrapper_n_1142;
  wire u_ddr_mc_phy_wrapper_n_1143;
  wire u_ddr_mc_phy_wrapper_n_1144;
  wire u_ddr_mc_phy_wrapper_n_1145;
  wire u_ddr_mc_phy_wrapper_n_1146;
  wire u_ddr_mc_phy_wrapper_n_1147;
  wire u_ddr_mc_phy_wrapper_n_1148;
  wire u_ddr_mc_phy_wrapper_n_1149;
  wire u_ddr_mc_phy_wrapper_n_1150;
  wire u_ddr_mc_phy_wrapper_n_1151;
  wire u_ddr_mc_phy_wrapper_n_1152;
  wire u_ddr_mc_phy_wrapper_n_1153;
  wire u_ddr_mc_phy_wrapper_n_1154;
  wire u_ddr_mc_phy_wrapper_n_1155;
  wire u_ddr_mc_phy_wrapper_n_1156;
  wire u_ddr_mc_phy_wrapper_n_1157;
  wire u_ddr_mc_phy_wrapper_n_1158;
  wire u_ddr_mc_phy_wrapper_n_1159;
  wire u_ddr_mc_phy_wrapper_n_1160;
  wire u_ddr_mc_phy_wrapper_n_1161;
  wire u_ddr_mc_phy_wrapper_n_1162;
  wire u_ddr_mc_phy_wrapper_n_1163;
  wire u_ddr_mc_phy_wrapper_n_1164;
  wire u_ddr_mc_phy_wrapper_n_1165;
  wire u_ddr_mc_phy_wrapper_n_1166;
  wire u_ddr_mc_phy_wrapper_n_1167;
  wire u_ddr_mc_phy_wrapper_n_1168;
  wire u_ddr_mc_phy_wrapper_n_1169;
  wire u_ddr_mc_phy_wrapper_n_1170;
  wire u_ddr_mc_phy_wrapper_n_1171;
  wire u_ddr_mc_phy_wrapper_n_1172;
  wire u_ddr_mc_phy_wrapper_n_1173;
  wire u_ddr_mc_phy_wrapper_n_1174;
  wire u_ddr_mc_phy_wrapper_n_1175;
  wire u_ddr_mc_phy_wrapper_n_1176;
  wire u_ddr_mc_phy_wrapper_n_1177;
  wire u_ddr_mc_phy_wrapper_n_1184;
  wire u_ddr_mc_phy_wrapper_n_1185;
  wire u_ddr_mc_phy_wrapper_n_1186;
  wire u_ddr_mc_phy_wrapper_n_1187;
  wire u_ddr_mc_phy_wrapper_n_1188;
  wire u_ddr_mc_phy_wrapper_n_1189;
  wire u_ddr_mc_phy_wrapper_n_1190;
  wire u_ddr_mc_phy_wrapper_n_1191;
  wire u_ddr_mc_phy_wrapper_n_1192;
  wire u_ddr_mc_phy_wrapper_n_1193;
  wire u_ddr_mc_phy_wrapper_n_1194;
  wire u_ddr_mc_phy_wrapper_n_1195;
  wire u_ddr_mc_phy_wrapper_n_1196;
  wire u_ddr_mc_phy_wrapper_n_1197;
  wire u_ddr_mc_phy_wrapper_n_1198;
  wire u_ddr_mc_phy_wrapper_n_1199;
  wire u_ddr_mc_phy_wrapper_n_1200;
  wire u_ddr_mc_phy_wrapper_n_1201;
  wire u_ddr_mc_phy_wrapper_n_1202;
  wire u_ddr_mc_phy_wrapper_n_1203;
  wire u_ddr_mc_phy_wrapper_n_1204;
  wire u_ddr_mc_phy_wrapper_n_1205;
  wire u_ddr_mc_phy_wrapper_n_1206;
  wire u_ddr_mc_phy_wrapper_n_1207;
  wire u_ddr_mc_phy_wrapper_n_1208;
  wire u_ddr_mc_phy_wrapper_n_1209;
  wire u_ddr_mc_phy_wrapper_n_1210;
  wire u_ddr_mc_phy_wrapper_n_1211;
  wire u_ddr_mc_phy_wrapper_n_1212;
  wire u_ddr_mc_phy_wrapper_n_1213;
  wire u_ddr_mc_phy_wrapper_n_1214;
  wire u_ddr_mc_phy_wrapper_n_1215;
  wire u_ddr_mc_phy_wrapper_n_1216;
  wire u_ddr_mc_phy_wrapper_n_1217;
  wire u_ddr_mc_phy_wrapper_n_1218;
  wire u_ddr_mc_phy_wrapper_n_1219;
  wire u_ddr_mc_phy_wrapper_n_1221;
  wire u_ddr_mc_phy_wrapper_n_1222;
  wire u_ddr_mc_phy_wrapper_n_1223;
  wire u_ddr_mc_phy_wrapper_n_1224;
  wire u_ddr_mc_phy_wrapper_n_1225;
  wire u_ddr_mc_phy_wrapper_n_1226;
  wire u_ddr_mc_phy_wrapper_n_1227;
  wire u_ddr_mc_phy_wrapper_n_1228;
  wire u_ddr_mc_phy_wrapper_n_1229;
  wire u_ddr_mc_phy_wrapper_n_1230;
  wire u_ddr_mc_phy_wrapper_n_1231;
  wire u_ddr_mc_phy_wrapper_n_1232;
  wire u_ddr_mc_phy_wrapper_n_1233;
  wire u_ddr_mc_phy_wrapper_n_1234;
  wire u_ddr_mc_phy_wrapper_n_1235;
  wire u_ddr_mc_phy_wrapper_n_1236;
  wire u_ddr_mc_phy_wrapper_n_1237;
  wire u_ddr_mc_phy_wrapper_n_1238;
  wire u_ddr_mc_phy_wrapper_n_1239;
  wire u_ddr_mc_phy_wrapper_n_1240;
  wire u_ddr_mc_phy_wrapper_n_1241;
  wire u_ddr_mc_phy_wrapper_n_1242;
  wire u_ddr_mc_phy_wrapper_n_1243;
  wire u_ddr_mc_phy_wrapper_n_1244;
  wire u_ddr_mc_phy_wrapper_n_1245;
  wire u_ddr_mc_phy_wrapper_n_1246;
  wire u_ddr_mc_phy_wrapper_n_1247;
  wire u_ddr_mc_phy_wrapper_n_1248;
  wire u_ddr_mc_phy_wrapper_n_1249;
  wire u_ddr_mc_phy_wrapper_n_1250;
  wire u_ddr_mc_phy_wrapper_n_1251;
  wire u_ddr_mc_phy_wrapper_n_1252;
  wire u_ddr_mc_phy_wrapper_n_1253;
  wire u_ddr_mc_phy_wrapper_n_1254;
  wire u_ddr_mc_phy_wrapper_n_1255;
  wire u_ddr_mc_phy_wrapper_n_1256;
  wire u_ddr_mc_phy_wrapper_n_1257;
  wire u_ddr_mc_phy_wrapper_n_1258;
  wire u_ddr_mc_phy_wrapper_n_1259;
  wire u_ddr_mc_phy_wrapper_n_1260;
  wire u_ddr_mc_phy_wrapper_n_1261;
  wire u_ddr_mc_phy_wrapper_n_1262;
  wire u_ddr_mc_phy_wrapper_n_1263;
  wire u_ddr_mc_phy_wrapper_n_1264;
  wire u_ddr_mc_phy_wrapper_n_1265;
  wire u_ddr_mc_phy_wrapper_n_1266;
  wire u_ddr_mc_phy_wrapper_n_1267;
  wire u_ddr_mc_phy_wrapper_n_1268;
  wire u_ddr_mc_phy_wrapper_n_1269;
  wire u_ddr_mc_phy_wrapper_n_1270;
  wire u_ddr_mc_phy_wrapper_n_1271;
  wire u_ddr_mc_phy_wrapper_n_1272;
  wire u_ddr_mc_phy_wrapper_n_1273;
  wire u_ddr_mc_phy_wrapper_n_1274;
  wire u_ddr_mc_phy_wrapper_n_1275;
  wire u_ddr_mc_phy_wrapper_n_1276;
  wire u_ddr_mc_phy_wrapper_n_1277;
  wire u_ddr_mc_phy_wrapper_n_1278;
  wire u_ddr_mc_phy_wrapper_n_1279;
  wire u_ddr_mc_phy_wrapper_n_1280;
  wire u_ddr_mc_phy_wrapper_n_1281;
  wire u_ddr_mc_phy_wrapper_n_1282;
  wire u_ddr_mc_phy_wrapper_n_1283;
  wire u_ddr_mc_phy_wrapper_n_1284;
  wire u_ddr_mc_phy_wrapper_n_1285;
  wire u_ddr_mc_phy_wrapper_n_1286;
  wire u_ddr_mc_phy_wrapper_n_1287;
  wire u_ddr_mc_phy_wrapper_n_1288;
  wire u_ddr_mc_phy_wrapper_n_1289;
  wire u_ddr_mc_phy_wrapper_n_1290;
  wire u_ddr_mc_phy_wrapper_n_1291;
  wire u_ddr_mc_phy_wrapper_n_1292;
  wire u_ddr_mc_phy_wrapper_n_1293;
  wire u_ddr_mc_phy_wrapper_n_1295;
  wire u_ddr_mc_phy_wrapper_n_1296;
  wire u_ddr_mc_phy_wrapper_n_1297;
  wire u_ddr_mc_phy_wrapper_n_1298;
  wire u_ddr_mc_phy_wrapper_n_1299;
  wire u_ddr_mc_phy_wrapper_n_1300;
  wire u_ddr_mc_phy_wrapper_n_1301;
  wire u_ddr_mc_phy_wrapper_n_1302;
  wire u_ddr_mc_phy_wrapper_n_1303;
  wire u_ddr_mc_phy_wrapper_n_1304;
  wire u_ddr_mc_phy_wrapper_n_1305;
  wire u_ddr_mc_phy_wrapper_n_1306;
  wire u_ddr_mc_phy_wrapper_n_1307;
  wire u_ddr_mc_phy_wrapper_n_1308;
  wire u_ddr_mc_phy_wrapper_n_1309;
  wire u_ddr_mc_phy_wrapper_n_1310;
  wire u_ddr_mc_phy_wrapper_n_1311;
  wire u_ddr_mc_phy_wrapper_n_1312;
  wire u_ddr_mc_phy_wrapper_n_1313;
  wire u_ddr_mc_phy_wrapper_n_1314;
  wire u_ddr_mc_phy_wrapper_n_1315;
  wire u_ddr_mc_phy_wrapper_n_1316;
  wire u_ddr_mc_phy_wrapper_n_1317;
  wire u_ddr_mc_phy_wrapper_n_1318;
  wire u_ddr_mc_phy_wrapper_n_1319;
  wire u_ddr_mc_phy_wrapper_n_1320;
  wire u_ddr_mc_phy_wrapper_n_1321;
  wire u_ddr_mc_phy_wrapper_n_1322;
  wire u_ddr_mc_phy_wrapper_n_1323;
  wire u_ddr_mc_phy_wrapper_n_1324;
  wire u_ddr_mc_phy_wrapper_n_1325;
  wire u_ddr_mc_phy_wrapper_n_1326;
  wire u_ddr_mc_phy_wrapper_n_1327;
  wire u_ddr_mc_phy_wrapper_n_1328;
  wire u_ddr_mc_phy_wrapper_n_1329;
  wire u_ddr_mc_phy_wrapper_n_1330;
  wire u_ddr_mc_phy_wrapper_n_1331;
  wire u_ddr_mc_phy_wrapper_n_1332;
  wire u_ddr_mc_phy_wrapper_n_1333;
  wire u_ddr_mc_phy_wrapper_n_1334;
  wire u_ddr_mc_phy_wrapper_n_1335;
  wire u_ddr_mc_phy_wrapper_n_1336;
  wire u_ddr_mc_phy_wrapper_n_1337;
  wire u_ddr_mc_phy_wrapper_n_1338;
  wire u_ddr_mc_phy_wrapper_n_1339;
  wire u_ddr_mc_phy_wrapper_n_1340;
  wire u_ddr_mc_phy_wrapper_n_1341;
  wire u_ddr_mc_phy_wrapper_n_1342;
  wire u_ddr_mc_phy_wrapper_n_1343;
  wire u_ddr_mc_phy_wrapper_n_1344;
  wire u_ddr_mc_phy_wrapper_n_1345;
  wire u_ddr_mc_phy_wrapper_n_1346;
  wire u_ddr_mc_phy_wrapper_n_1347;
  wire u_ddr_mc_phy_wrapper_n_1348;
  wire u_ddr_mc_phy_wrapper_n_1349;
  wire u_ddr_mc_phy_wrapper_n_1350;
  wire u_ddr_mc_phy_wrapper_n_1351;
  wire u_ddr_mc_phy_wrapper_n_1352;
  wire u_ddr_mc_phy_wrapper_n_1353;
  wire u_ddr_mc_phy_wrapper_n_1354;
  wire u_ddr_mc_phy_wrapper_n_1355;
  wire u_ddr_mc_phy_wrapper_n_1356;
  wire u_ddr_mc_phy_wrapper_n_1357;
  wire u_ddr_mc_phy_wrapper_n_1360;
  wire u_ddr_mc_phy_wrapper_n_33;
  wire u_ddr_mc_phy_wrapper_n_34;
  wire u_ddr_mc_phy_wrapper_n_35;
  wire u_ddr_mc_phy_wrapper_n_36;
  wire u_ddr_mc_phy_wrapper_n_37;
  wire u_ddr_mc_phy_wrapper_n_38;
  wire u_ddr_mc_phy_wrapper_n_39;
  wire u_ddr_mc_phy_wrapper_n_40;
  wire u_ddr_mc_phy_wrapper_n_59;
  wire u_ddr_mc_phy_wrapper_n_595;
  wire u_ddr_mc_phy_wrapper_n_596;
  wire u_ddr_mc_phy_wrapper_n_597;
  wire u_ddr_mc_phy_wrapper_n_598;
  wire u_ddr_mc_phy_wrapper_n_599;
  wire u_ddr_mc_phy_wrapper_n_600;
  wire u_ddr_mc_phy_wrapper_n_601;
  wire u_ddr_mc_phy_wrapper_n_602;
  wire u_ddr_mc_phy_wrapper_n_603;
  wire u_ddr_mc_phy_wrapper_n_604;
  wire u_ddr_mc_phy_wrapper_n_605;
  wire u_ddr_mc_phy_wrapper_n_606;
  wire u_ddr_mc_phy_wrapper_n_607;
  wire u_ddr_mc_phy_wrapper_n_608;
  wire u_ddr_mc_phy_wrapper_n_609;
  wire u_ddr_mc_phy_wrapper_n_61;
  wire u_ddr_mc_phy_wrapper_n_610;
  wire u_ddr_mc_phy_wrapper_n_611;
  wire u_ddr_mc_phy_wrapper_n_612;
  wire u_ddr_mc_phy_wrapper_n_613;
  wire u_ddr_mc_phy_wrapper_n_614;
  wire u_ddr_mc_phy_wrapper_n_615;
  wire u_ddr_mc_phy_wrapper_n_616;
  wire u_ddr_mc_phy_wrapper_n_617;
  wire u_ddr_mc_phy_wrapper_n_618;
  wire u_ddr_mc_phy_wrapper_n_619;
  wire u_ddr_mc_phy_wrapper_n_62;
  wire u_ddr_mc_phy_wrapper_n_620;
  wire u_ddr_mc_phy_wrapper_n_621;
  wire u_ddr_mc_phy_wrapper_n_622;
  wire u_ddr_mc_phy_wrapper_n_623;
  wire u_ddr_mc_phy_wrapper_n_624;
  wire u_ddr_mc_phy_wrapper_n_625;
  wire u_ddr_mc_phy_wrapper_n_626;
  wire u_ddr_mc_phy_wrapper_n_627;
  wire u_ddr_mc_phy_wrapper_n_628;
  wire u_ddr_mc_phy_wrapper_n_629;
  wire u_ddr_mc_phy_wrapper_n_63;
  wire u_ddr_mc_phy_wrapper_n_630;
  wire u_ddr_mc_phy_wrapper_n_631;
  wire u_ddr_mc_phy_wrapper_n_632;
  wire u_ddr_mc_phy_wrapper_n_633;
  wire u_ddr_mc_phy_wrapper_n_634;
  wire u_ddr_mc_phy_wrapper_n_635;
  wire u_ddr_mc_phy_wrapper_n_636;
  wire u_ddr_mc_phy_wrapper_n_637;
  wire u_ddr_mc_phy_wrapper_n_638;
  wire u_ddr_mc_phy_wrapper_n_639;
  wire u_ddr_mc_phy_wrapper_n_64;
  wire u_ddr_mc_phy_wrapper_n_640;
  wire u_ddr_mc_phy_wrapper_n_641;
  wire u_ddr_mc_phy_wrapper_n_642;
  wire u_ddr_mc_phy_wrapper_n_643;
  wire u_ddr_mc_phy_wrapper_n_644;
  wire u_ddr_mc_phy_wrapper_n_645;
  wire u_ddr_mc_phy_wrapper_n_646;
  wire u_ddr_mc_phy_wrapper_n_647;
  wire u_ddr_mc_phy_wrapper_n_648;
  wire u_ddr_mc_phy_wrapper_n_649;
  wire u_ddr_mc_phy_wrapper_n_65;
  wire u_ddr_mc_phy_wrapper_n_650;
  wire u_ddr_mc_phy_wrapper_n_651;
  wire u_ddr_mc_phy_wrapper_n_652;
  wire u_ddr_mc_phy_wrapper_n_653;
  wire u_ddr_mc_phy_wrapper_n_654;
  wire u_ddr_mc_phy_wrapper_n_655;
  wire u_ddr_mc_phy_wrapper_n_656;
  wire u_ddr_mc_phy_wrapper_n_657;
  wire u_ddr_mc_phy_wrapper_n_658;
  wire u_ddr_mc_phy_wrapper_n_66;
  wire u_ddr_mc_phy_wrapper_n_660;
  wire u_ddr_mc_phy_wrapper_n_661;
  wire u_ddr_mc_phy_wrapper_n_662;
  wire u_ddr_mc_phy_wrapper_n_663;
  wire u_ddr_mc_phy_wrapper_n_664;
  wire u_ddr_mc_phy_wrapper_n_665;
  wire u_ddr_mc_phy_wrapper_n_666;
  wire u_ddr_mc_phy_wrapper_n_667;
  wire u_ddr_mc_phy_wrapper_n_668;
  wire u_ddr_mc_phy_wrapper_n_669;
  wire u_ddr_mc_phy_wrapper_n_67;
  wire u_ddr_mc_phy_wrapper_n_670;
  wire u_ddr_mc_phy_wrapper_n_671;
  wire u_ddr_mc_phy_wrapper_n_672;
  wire u_ddr_mc_phy_wrapper_n_673;
  wire u_ddr_mc_phy_wrapper_n_674;
  wire u_ddr_mc_phy_wrapper_n_675;
  wire u_ddr_mc_phy_wrapper_n_676;
  wire u_ddr_mc_phy_wrapper_n_677;
  wire u_ddr_mc_phy_wrapper_n_678;
  wire u_ddr_mc_phy_wrapper_n_679;
  wire u_ddr_mc_phy_wrapper_n_68;
  wire u_ddr_mc_phy_wrapper_n_680;
  wire u_ddr_mc_phy_wrapper_n_681;
  wire u_ddr_mc_phy_wrapper_n_682;
  wire u_ddr_mc_phy_wrapper_n_683;
  wire u_ddr_mc_phy_wrapper_n_684;
  wire u_ddr_mc_phy_wrapper_n_685;
  wire u_ddr_mc_phy_wrapper_n_686;
  wire u_ddr_mc_phy_wrapper_n_687;
  wire u_ddr_mc_phy_wrapper_n_688;
  wire u_ddr_mc_phy_wrapper_n_689;
  wire u_ddr_mc_phy_wrapper_n_69;
  wire u_ddr_mc_phy_wrapper_n_690;
  wire u_ddr_mc_phy_wrapper_n_691;
  wire u_ddr_mc_phy_wrapper_n_692;
  wire u_ddr_mc_phy_wrapper_n_693;
  wire u_ddr_mc_phy_wrapper_n_694;
  wire u_ddr_mc_phy_wrapper_n_695;
  wire u_ddr_mc_phy_wrapper_n_696;
  wire u_ddr_mc_phy_wrapper_n_697;
  wire u_ddr_mc_phy_wrapper_n_698;
  wire u_ddr_mc_phy_wrapper_n_699;
  wire u_ddr_mc_phy_wrapper_n_70;
  wire u_ddr_mc_phy_wrapper_n_700;
  wire u_ddr_mc_phy_wrapper_n_701;
  wire u_ddr_mc_phy_wrapper_n_702;
  wire u_ddr_mc_phy_wrapper_n_703;
  wire u_ddr_mc_phy_wrapper_n_704;
  wire u_ddr_mc_phy_wrapper_n_705;
  wire u_ddr_mc_phy_wrapper_n_706;
  wire u_ddr_mc_phy_wrapper_n_707;
  wire u_ddr_mc_phy_wrapper_n_708;
  wire u_ddr_mc_phy_wrapper_n_709;
  wire u_ddr_mc_phy_wrapper_n_710;
  wire u_ddr_mc_phy_wrapper_n_711;
  wire u_ddr_mc_phy_wrapper_n_712;
  wire u_ddr_mc_phy_wrapper_n_713;
  wire u_ddr_mc_phy_wrapper_n_714;
  wire u_ddr_mc_phy_wrapper_n_715;
  wire u_ddr_mc_phy_wrapper_n_716;
  wire u_ddr_mc_phy_wrapper_n_717;
  wire u_ddr_mc_phy_wrapper_n_718;
  wire u_ddr_mc_phy_wrapper_n_719;
  wire u_ddr_mc_phy_wrapper_n_720;
  wire u_ddr_mc_phy_wrapper_n_721;
  wire u_ddr_mc_phy_wrapper_n_722;
  wire u_ddr_mc_phy_wrapper_n_723;
  wire u_ddr_mc_phy_wrapper_n_724;
  wire u_ddr_mc_phy_wrapper_n_725;
  wire u_ddr_mc_phy_wrapper_n_726;
  wire u_ddr_mc_phy_wrapper_n_727;
  wire u_ddr_mc_phy_wrapper_n_728;
  wire u_ddr_mc_phy_wrapper_n_729;
  wire u_ddr_mc_phy_wrapper_n_730;
  wire u_ddr_mc_phy_wrapper_n_731;
  wire u_ddr_mc_phy_wrapper_n_732;
  wire u_ddr_mc_phy_wrapper_n_733;
  wire u_ddr_mc_phy_wrapper_n_734;
  wire u_ddr_mc_phy_wrapper_n_735;
  wire u_ddr_mc_phy_wrapper_n_736;
  wire u_ddr_mc_phy_wrapper_n_737;
  wire u_ddr_mc_phy_wrapper_n_738;
  wire u_ddr_mc_phy_wrapper_n_739;
  wire u_ddr_mc_phy_wrapper_n_740;
  wire u_ddr_mc_phy_wrapper_n_741;
  wire u_ddr_mc_phy_wrapper_n_742;
  wire u_ddr_mc_phy_wrapper_n_743;
  wire u_ddr_mc_phy_wrapper_n_744;
  wire u_ddr_mc_phy_wrapper_n_745;
  wire u_ddr_mc_phy_wrapper_n_746;
  wire u_ddr_mc_phy_wrapper_n_747;
  wire u_ddr_mc_phy_wrapper_n_748;
  wire u_ddr_mc_phy_wrapper_n_749;
  wire u_ddr_mc_phy_wrapper_n_750;
  wire u_ddr_mc_phy_wrapper_n_751;
  wire u_ddr_mc_phy_wrapper_n_752;
  wire u_ddr_mc_phy_wrapper_n_753;
  wire u_ddr_mc_phy_wrapper_n_754;
  wire u_ddr_mc_phy_wrapper_n_755;
  wire u_ddr_mc_phy_wrapper_n_756;
  wire u_ddr_mc_phy_wrapper_n_757;
  wire u_ddr_mc_phy_wrapper_n_758;
  wire u_ddr_mc_phy_wrapper_n_759;
  wire u_ddr_mc_phy_wrapper_n_760;
  wire u_ddr_mc_phy_wrapper_n_761;
  wire u_ddr_mc_phy_wrapper_n_762;
  wire u_ddr_mc_phy_wrapper_n_763;
  wire u_ddr_mc_phy_wrapper_n_764;
  wire u_ddr_mc_phy_wrapper_n_765;
  wire u_ddr_mc_phy_wrapper_n_766;
  wire u_ddr_mc_phy_wrapper_n_767;
  wire u_ddr_mc_phy_wrapper_n_768;
  wire u_ddr_mc_phy_wrapper_n_769;
  wire u_ddr_mc_phy_wrapper_n_770;
  wire u_ddr_mc_phy_wrapper_n_771;
  wire u_ddr_mc_phy_wrapper_n_772;
  wire u_ddr_mc_phy_wrapper_n_773;
  wire u_ddr_mc_phy_wrapper_n_774;
  wire u_ddr_mc_phy_wrapper_n_775;
  wire u_ddr_mc_phy_wrapper_n_776;
  wire u_ddr_mc_phy_wrapper_n_777;
  wire u_ddr_mc_phy_wrapper_n_778;
  wire u_ddr_mc_phy_wrapper_n_779;
  wire u_ddr_mc_phy_wrapper_n_780;
  wire u_ddr_mc_phy_wrapper_n_781;
  wire u_ddr_mc_phy_wrapper_n_782;
  wire u_ddr_mc_phy_wrapper_n_783;
  wire u_ddr_mc_phy_wrapper_n_784;
  wire u_ddr_mc_phy_wrapper_n_785;
  wire u_ddr_mc_phy_wrapper_n_786;
  wire u_ddr_mc_phy_wrapper_n_787;
  wire u_ddr_mc_phy_wrapper_n_788;
  wire u_ddr_mc_phy_wrapper_n_789;
  wire u_ddr_mc_phy_wrapper_n_790;
  wire u_ddr_mc_phy_wrapper_n_791;
  wire u_ddr_mc_phy_wrapper_n_792;
  wire u_ddr_mc_phy_wrapper_n_793;
  wire u_ddr_mc_phy_wrapper_n_794;
  wire u_ddr_mc_phy_wrapper_n_795;
  wire u_ddr_mc_phy_wrapper_n_796;
  wire u_ddr_mc_phy_wrapper_n_797;
  wire u_ddr_mc_phy_wrapper_n_798;
  wire u_ddr_mc_phy_wrapper_n_799;
  wire u_ddr_mc_phy_wrapper_n_800;
  wire u_ddr_mc_phy_wrapper_n_801;
  wire u_ddr_mc_phy_wrapper_n_802;
  wire u_ddr_mc_phy_wrapper_n_803;
  wire u_ddr_mc_phy_wrapper_n_804;
  wire u_ddr_mc_phy_wrapper_n_805;
  wire u_ddr_mc_phy_wrapper_n_806;
  wire u_ddr_mc_phy_wrapper_n_807;
  wire u_ddr_mc_phy_wrapper_n_808;
  wire u_ddr_mc_phy_wrapper_n_809;
  wire u_ddr_mc_phy_wrapper_n_810;
  wire u_ddr_mc_phy_wrapper_n_811;
  wire u_ddr_mc_phy_wrapper_n_812;
  wire u_ddr_mc_phy_wrapper_n_813;
  wire u_ddr_mc_phy_wrapper_n_814;
  wire u_ddr_mc_phy_wrapper_n_815;
  wire u_ddr_mc_phy_wrapper_n_816;
  wire u_ddr_mc_phy_wrapper_n_817;
  wire u_ddr_mc_phy_wrapper_n_818;
  wire u_ddr_mc_phy_wrapper_n_819;
  wire u_ddr_mc_phy_wrapper_n_820;
  wire u_ddr_mc_phy_wrapper_n_821;
  wire u_ddr_mc_phy_wrapper_n_822;
  wire u_ddr_mc_phy_wrapper_n_823;
  wire u_ddr_mc_phy_wrapper_n_824;
  wire u_ddr_mc_phy_wrapper_n_825;
  wire u_ddr_mc_phy_wrapper_n_826;
  wire u_ddr_mc_phy_wrapper_n_827;
  wire u_ddr_mc_phy_wrapper_n_828;
  wire u_ddr_mc_phy_wrapper_n_829;
  wire u_ddr_mc_phy_wrapper_n_830;
  wire u_ddr_mc_phy_wrapper_n_831;
  wire u_ddr_mc_phy_wrapper_n_832;
  wire u_ddr_mc_phy_wrapper_n_833;
  wire u_ddr_mc_phy_wrapper_n_834;
  wire u_ddr_mc_phy_wrapper_n_835;
  wire u_ddr_mc_phy_wrapper_n_836;
  wire u_ddr_mc_phy_wrapper_n_837;
  wire u_ddr_mc_phy_wrapper_n_838;
  wire u_ddr_mc_phy_wrapper_n_839;
  wire u_ddr_mc_phy_wrapper_n_840;
  wire u_ddr_mc_phy_wrapper_n_841;
  wire u_ddr_mc_phy_wrapper_n_842;
  wire u_ddr_mc_phy_wrapper_n_843;
  wire u_ddr_mc_phy_wrapper_n_844;
  wire u_ddr_mc_phy_wrapper_n_845;
  wire u_ddr_mc_phy_wrapper_n_846;
  wire u_ddr_mc_phy_wrapper_n_847;
  wire u_ddr_mc_phy_wrapper_n_848;
  wire u_ddr_mc_phy_wrapper_n_849;
  wire u_ddr_mc_phy_wrapper_n_850;
  wire u_ddr_mc_phy_wrapper_n_851;
  wire u_ddr_mc_phy_wrapper_n_852;
  wire u_ddr_mc_phy_wrapper_n_853;
  wire u_ddr_mc_phy_wrapper_n_854;
  wire u_ddr_mc_phy_wrapper_n_855;
  wire u_ddr_mc_phy_wrapper_n_856;
  wire u_ddr_mc_phy_wrapper_n_857;
  wire u_ddr_mc_phy_wrapper_n_858;
  wire u_ddr_mc_phy_wrapper_n_859;
  wire u_ddr_mc_phy_wrapper_n_860;
  wire u_ddr_mc_phy_wrapper_n_861;
  wire u_ddr_mc_phy_wrapper_n_862;
  wire u_ddr_mc_phy_wrapper_n_863;
  wire u_ddr_mc_phy_wrapper_n_864;
  wire u_ddr_mc_phy_wrapper_n_865;
  wire u_ddr_mc_phy_wrapper_n_866;
  wire u_ddr_mc_phy_wrapper_n_867;
  wire u_ddr_mc_phy_wrapper_n_868;
  wire u_ddr_mc_phy_wrapper_n_869;
  wire u_ddr_mc_phy_wrapper_n_870;
  wire u_ddr_mc_phy_wrapper_n_871;
  wire u_ddr_mc_phy_wrapper_n_872;
  wire u_ddr_mc_phy_wrapper_n_873;
  wire u_ddr_mc_phy_wrapper_n_874;
  wire u_ddr_mc_phy_wrapper_n_875;
  wire u_ddr_mc_phy_wrapper_n_876;
  wire u_ddr_mc_phy_wrapper_n_877;
  wire u_ddr_mc_phy_wrapper_n_878;
  wire u_ddr_mc_phy_wrapper_n_879;
  wire u_ddr_mc_phy_wrapper_n_880;
  wire u_ddr_mc_phy_wrapper_n_881;
  wire u_ddr_mc_phy_wrapper_n_882;
  wire u_ddr_mc_phy_wrapper_n_883;
  wire u_ddr_mc_phy_wrapper_n_884;
  wire u_ddr_mc_phy_wrapper_n_885;
  wire u_ddr_mc_phy_wrapper_n_886;
  wire u_ddr_mc_phy_wrapper_n_887;
  wire u_ddr_mc_phy_wrapper_n_888;
  wire u_ddr_mc_phy_wrapper_n_889;
  wire u_ddr_mc_phy_wrapper_n_890;
  wire u_ddr_mc_phy_wrapper_n_891;
  wire u_ddr_mc_phy_wrapper_n_892;
  wire u_ddr_mc_phy_wrapper_n_893;
  wire u_ddr_mc_phy_wrapper_n_894;
  wire u_ddr_mc_phy_wrapper_n_895;
  wire u_ddr_mc_phy_wrapper_n_896;
  wire u_ddr_mc_phy_wrapper_n_897;
  wire u_ddr_mc_phy_wrapper_n_898;
  wire u_ddr_mc_phy_wrapper_n_899;
  wire u_ddr_mc_phy_wrapper_n_900;
  wire u_ddr_mc_phy_wrapper_n_901;
  wire u_ddr_mc_phy_wrapper_n_902;
  wire u_ddr_mc_phy_wrapper_n_903;
  wire u_ddr_mc_phy_wrapper_n_904;
  wire u_ddr_mc_phy_wrapper_n_905;
  wire u_ddr_mc_phy_wrapper_n_906;
  wire u_ddr_mc_phy_wrapper_n_907;
  wire u_ddr_mc_phy_wrapper_n_908;
  wire u_ddr_mc_phy_wrapper_n_909;
  wire u_ddr_mc_phy_wrapper_n_910;
  wire u_ddr_mc_phy_wrapper_n_911;
  wire u_ddr_mc_phy_wrapper_n_912;
  wire u_ddr_mc_phy_wrapper_n_913;
  wire u_ddr_mc_phy_wrapper_n_914;
  wire u_ddr_mc_phy_wrapper_n_915;
  wire u_ddr_mc_phy_wrapper_n_922;
  wire u_ddr_mc_phy_wrapper_n_923;
  wire u_ddr_mc_phy_wrapper_n_924;
  wire u_ddr_mc_phy_wrapper_n_925;
  wire u_ddr_mc_phy_wrapper_n_926;
  wire u_ddr_mc_phy_wrapper_n_927;
  wire u_ddr_mc_phy_wrapper_n_928;
  wire u_ddr_mc_phy_wrapper_n_929;
  wire u_ddr_mc_phy_wrapper_n_930;
  wire u_ddr_mc_phy_wrapper_n_931;
  wire u_ddr_mc_phy_wrapper_n_932;
  wire u_ddr_mc_phy_wrapper_n_933;
  wire u_ddr_mc_phy_wrapper_n_934;
  wire u_ddr_mc_phy_wrapper_n_935;
  wire u_ddr_mc_phy_wrapper_n_936;
  wire u_ddr_mc_phy_wrapper_n_937;
  wire u_ddr_mc_phy_wrapper_n_938;
  wire u_ddr_mc_phy_wrapper_n_939;
  wire u_ddr_mc_phy_wrapper_n_940;
  wire u_ddr_mc_phy_wrapper_n_941;
  wire u_ddr_mc_phy_wrapper_n_942;
  wire u_ddr_mc_phy_wrapper_n_943;
  wire u_ddr_mc_phy_wrapper_n_944;
  wire u_ddr_mc_phy_wrapper_n_945;
  wire u_ddr_mc_phy_wrapper_n_946;
  wire u_ddr_mc_phy_wrapper_n_947;
  wire u_ddr_mc_phy_wrapper_n_948;
  wire u_ddr_mc_phy_wrapper_n_949;
  wire u_ddr_mc_phy_wrapper_n_950;
  wire u_ddr_mc_phy_wrapper_n_951;
  wire u_ddr_mc_phy_wrapper_n_952;
  wire u_ddr_mc_phy_wrapper_n_953;
  wire u_ddr_mc_phy_wrapper_n_954;
  wire u_ddr_mc_phy_wrapper_n_955;
  wire u_ddr_mc_phy_wrapper_n_956;
  wire u_ddr_mc_phy_wrapper_n_957;
  wire u_ddr_mc_phy_wrapper_n_958;
  wire u_ddr_mc_phy_wrapper_n_959;
  wire u_ddr_mc_phy_wrapper_n_960;
  wire u_ddr_mc_phy_wrapper_n_961;
  wire u_ddr_mc_phy_wrapper_n_962;
  wire u_ddr_mc_phy_wrapper_n_963;
  wire u_ddr_mc_phy_wrapper_n_964;
  wire u_ddr_mc_phy_wrapper_n_965;
  wire u_ddr_mc_phy_wrapper_n_966;
  wire u_ddr_mc_phy_wrapper_n_967;
  wire u_ddr_mc_phy_wrapper_n_968;
  wire u_ddr_mc_phy_wrapper_n_969;
  wire u_ddr_mc_phy_wrapper_n_970;
  wire u_ddr_mc_phy_wrapper_n_971;
  wire u_ddr_mc_phy_wrapper_n_972;
  wire u_ddr_mc_phy_wrapper_n_973;
  wire u_ddr_mc_phy_wrapper_n_974;
  wire u_ddr_mc_phy_wrapper_n_975;
  wire u_ddr_mc_phy_wrapper_n_976;
  wire u_ddr_mc_phy_wrapper_n_977;
  wire u_ddr_mc_phy_wrapper_n_978;
  wire u_ddr_mc_phy_wrapper_n_979;
  wire u_ddr_mc_phy_wrapper_n_980;
  wire u_ddr_mc_phy_wrapper_n_981;
  wire u_ddr_mc_phy_wrapper_n_982;
  wire u_ddr_mc_phy_wrapper_n_983;
  wire u_ddr_mc_phy_wrapper_n_984;
  wire u_ddr_mc_phy_wrapper_n_985;
  wire u_ddr_mc_phy_wrapper_n_986;
  wire u_ddr_mc_phy_wrapper_n_987;
  wire u_ddr_mc_phy_wrapper_n_988;
  wire u_ddr_mc_phy_wrapper_n_989;
  wire u_ddr_mc_phy_wrapper_n_990;
  wire u_ddr_mc_phy_wrapper_n_991;
  wire u_ddr_mc_phy_wrapper_n_992;
  wire u_ddr_mc_phy_wrapper_n_993;
  wire u_ddr_mc_phy_wrapper_n_994;
  wire u_ddr_mc_phy_wrapper_n_995;
  wire u_ddr_mc_phy_wrapper_n_996;
  wire u_ddr_mc_phy_wrapper_n_997;
  wire u_ddr_mc_phy_wrapper_n_998;
  wire u_ddr_mc_phy_wrapper_n_999;
  wire \u_ddr_phy_wrcal/p_0_out ;
  wire [0:0]\victim_sel_reg[0] ;
  wire [0:0]\wait_cnt_r_reg[0] ;
  wire [0:0]\wait_cnt_r_reg[0]_0 ;
  wire \wl_dqs_tap_count_r_reg[0][5][5] ;

  LUT1 #(
    .INIT(2'h2)) 
    i_0
       (.I0(1'b0),
        .O(pi_enstg2_f_div2r1));
  LUT1 #(
    .INIT(2'h2)) 
    i_1
       (.I0(1'b0),
        .O(pi_enstg2_f_div2r2));
  LUT1 #(
    .INIT(2'h2)) 
    i_10
       (.I0(1'b0),
        .O(rst_stg1_cal_div2r1[1]));
  LUT1 #(
    .INIT(2'h2)) 
    i_11
       (.I0(1'b0),
        .O(rst_stg1_cal_div2r1[0]));
  LUT1 #(
    .INIT(2'h2)) 
    i_12
       (.I0(1'b0),
        .O(rst_stg1_cal_div2r2[2]));
  LUT1 #(
    .INIT(2'h2)) 
    i_13
       (.I0(1'b0),
        .O(rst_stg1_cal_div2r2[1]));
  LUT1 #(
    .INIT(2'h2)) 
    i_14
       (.I0(1'b0),
        .O(rst_stg1_cal_div2r2[0]));
  LUT1 #(
    .INIT(2'h2)) 
    i_15
       (.I0(1'b0),
        .O(pi_stg2_reg_l_div2r1[5]));
  LUT1 #(
    .INIT(2'h2)) 
    i_16
       (.I0(1'b0),
        .O(pi_stg2_reg_l_div2r1[4]));
  LUT1 #(
    .INIT(2'h2)) 
    i_17
       (.I0(1'b0),
        .O(pi_stg2_reg_l_div2r1[3]));
  LUT1 #(
    .INIT(2'h2)) 
    i_18
       (.I0(1'b0),
        .O(pi_stg2_reg_l_div2r1[2]));
  LUT1 #(
    .INIT(2'h2)) 
    i_19
       (.I0(1'b0),
        .O(pi_stg2_reg_l_div2r1[1]));
  LUT1 #(
    .INIT(2'h2)) 
    i_2
       (.I0(1'b0),
        .O(pi_enstg2_f_div2r3));
  LUT1 #(
    .INIT(2'h2)) 
    i_20
       (.I0(1'b0),
        .O(pi_stg2_reg_l_div2r1[0]));
  LUT1 #(
    .INIT(2'h2)) 
    i_21
       (.I0(1'b0),
        .O(pi_stg2_reg_l_div2r2[5]));
  LUT1 #(
    .INIT(2'h2)) 
    i_22
       (.I0(1'b0),
        .O(pi_stg2_reg_l_div2r2[4]));
  LUT1 #(
    .INIT(2'h2)) 
    i_23
       (.I0(1'b0),
        .O(pi_stg2_reg_l_div2r2[3]));
  LUT1 #(
    .INIT(2'h2)) 
    i_24
       (.I0(1'b0),
        .O(pi_stg2_reg_l_div2r2[2]));
  LUT1 #(
    .INIT(2'h2)) 
    i_25
       (.I0(1'b0),
        .O(pi_stg2_reg_l_div2r2[1]));
  LUT1 #(
    .INIT(2'h2)) 
    i_26
       (.I0(1'b0),
        .O(pi_stg2_reg_l_div2r2[0]));
  LUT1 #(
    .INIT(2'h2)) 
    i_27
       (.I0(1'b0),
        .O(pi_stg2_reg_l_div2r3[5]));
  LUT1 #(
    .INIT(2'h2)) 
    i_28
       (.I0(1'b0),
        .O(pi_stg2_reg_l_div2r3[4]));
  LUT1 #(
    .INIT(2'h2)) 
    i_29
       (.I0(1'b0),
        .O(pi_stg2_reg_l_div2r3[3]));
  LUT1 #(
    .INIT(2'h2)) 
    i_3
       (.I0(1'b0),
        .O(pi_stg2_fincdec_div2r1));
  LUT1 #(
    .INIT(2'h2)) 
    i_30
       (.I0(1'b0),
        .O(pi_stg2_reg_l_div2r3[2]));
  LUT1 #(
    .INIT(2'h2)) 
    i_31
       (.I0(1'b0),
        .O(pi_stg2_reg_l_div2r3[1]));
  LUT1 #(
    .INIT(2'h2)) 
    i_32
       (.I0(1'b0),
        .O(pi_stg2_reg_l_div2r3[0]));
  LUT1 #(
    .INIT(2'h2)) 
    i_33
       (.I0(1'b0),
        .O(pi_dqs_find_rst[2]));
  LUT1 #(
    .INIT(2'h2)) 
    i_34
       (.I0(1'b0),
        .O(pi_dqs_find_rst[1]));
  LUT1 #(
    .INIT(2'h2)) 
    i_35
       (.I0(1'b0),
        .O(pi_dqs_find_rst[0]));
  LUT1 #(
    .INIT(2'h2)) 
    i_4
       (.I0(1'b0),
        .O(pi_stg2_fincdec_div2r2));
  LUT1 #(
    .INIT(2'h2)) 
    i_5
       (.I0(1'b0),
        .O(pi_stg2_fincdec_div2r3));
  LUT1 #(
    .INIT(2'h2)) 
    i_6
       (.I0(1'b0),
        .O(pi_stg2_load_div2r1));
  LUT1 #(
    .INIT(2'h2)) 
    i_7
       (.I0(1'b0),
        .O(pi_stg2_load_div2r2));
  LUT1 #(
    .INIT(2'h2)) 
    i_8
       (.I0(1'b0),
        .O(pi_stg2_load_div2r3));
  LUT1 #(
    .INIT(2'h2)) 
    i_9
       (.I0(1'b0),
        .O(rst_stg1_cal_div2r1[2]));
  mig_mig_7series_v4_2_ddr_calib_top u_ddr_calib_top
       (.COUNTERLOADVAL(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/A_pi_counter_load_val ),
        .C_po_coarse_enable26_out(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/C_po_coarse_enable26_out ),
        .C_po_counter_read_en38_out(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/C_po_counter_read_en38_out ),
        .C_po_fine_enable23_out(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/C_po_fine_enable23_out ),
        .C_po_fine_inc29_out(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/C_po_fine_inc29_out ),
        .D({phy_ctl_wd[24:17],phy_ctl_wd[2:0]}),
        .D1(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d1 ),
        .D2(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d2 ),
        .D3(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d3 ),
        .D4(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d4 ),
        .D5(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d5 ),
        .D6(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d6 ),
        .D7(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d7 ),
        .D8(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d8 ),
        .D9(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d9 ),
        .E(new_cnt_dqs_r_reg),
        .\FSM_onehot_cal1_state_r_reg[7] (\FSM_onehot_cal1_state_r_reg[7] ),
        .LD0(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/LD0 ),
        .LD0_0(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/LD0 ),
        .LD0_1(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/LD0 ),
        .LD0_2(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/LD0 ),
        .LD0_3(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/LD0 ),
        .LD0_4(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/LD0 ),
        .LD0_5(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/LD0 ),
        .LD0_6(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/LD0 ),
        .Q(phy_mc_go),
        .SR(u_ddr_calib_top_n_1373),
        .SS(SS),
        .app_rd_data_valid(app_rd_data_valid),
        .app_rd_data_valid_0(app_rd_data_valid_0),
        .cal2_if_reset_reg(cal2_if_reset_reg),
        .calib_sel({calib_sel[4:3],calib_sel[1:0]}),
        .\calib_sel_reg[0]_0 (u_ddr_calib_top_n_693),
        .\calib_sel_reg[0]_1 (u_ddr_calib_top_n_707),
        .\calib_sel_reg[0]_2 (u_ddr_calib_top_n_709),
        .\calib_sel_reg[0]_3 (u_ddr_calib_top_n_710),
        .\calib_sel_reg[0]_4 (u_ddr_calib_top_n_725),
        .\calib_sel_reg[0]_5 (u_ddr_calib_top_n_739),
        .\calib_sel_reg[0]_6 (u_ddr_calib_top_n_741),
        .\calib_sel_reg[0]_7 (u_ddr_calib_top_n_742),
        .\calib_sel_reg[1]_0 (u_ddr_calib_top_n_680),
        .\calib_sel_reg[1]_1 (u_ddr_calib_top_n_681),
        .\calib_sel_reg[1]_10 (u_ddr_calib_top_n_691),
        .\calib_sel_reg[1]_11 (u_ddr_calib_top_n_692),
        .\calib_sel_reg[1]_12 (u_ddr_calib_top_n_694),
        .\calib_sel_reg[1]_13 (u_ddr_calib_top_n_695),
        .\calib_sel_reg[1]_14 (u_ddr_calib_top_n_696),
        .\calib_sel_reg[1]_15 (u_ddr_calib_top_n_697),
        .\calib_sel_reg[1]_16 (u_ddr_calib_top_n_698),
        .\calib_sel_reg[1]_17 (u_ddr_calib_top_n_699),
        .\calib_sel_reg[1]_18 (u_ddr_calib_top_n_700),
        .\calib_sel_reg[1]_19 (u_ddr_calib_top_n_701),
        .\calib_sel_reg[1]_2 (u_ddr_calib_top_n_682),
        .\calib_sel_reg[1]_20 (u_ddr_calib_top_n_702),
        .\calib_sel_reg[1]_21 (u_ddr_calib_top_n_703),
        .\calib_sel_reg[1]_22 (u_ddr_calib_top_n_704),
        .\calib_sel_reg[1]_23 (u_ddr_calib_top_n_705),
        .\calib_sel_reg[1]_24 (u_ddr_calib_top_n_712),
        .\calib_sel_reg[1]_25 (u_ddr_calib_top_n_713),
        .\calib_sel_reg[1]_26 (u_ddr_calib_top_n_714),
        .\calib_sel_reg[1]_27 (u_ddr_calib_top_n_715),
        .\calib_sel_reg[1]_28 (u_ddr_calib_top_n_716),
        .\calib_sel_reg[1]_29 (u_ddr_calib_top_n_717),
        .\calib_sel_reg[1]_3 (u_ddr_calib_top_n_683),
        .\calib_sel_reg[1]_30 (u_ddr_calib_top_n_718),
        .\calib_sel_reg[1]_31 (u_ddr_calib_top_n_719),
        .\calib_sel_reg[1]_32 (u_ddr_calib_top_n_720),
        .\calib_sel_reg[1]_33 (u_ddr_calib_top_n_722),
        .\calib_sel_reg[1]_34 (u_ddr_calib_top_n_723),
        .\calib_sel_reg[1]_35 (u_ddr_calib_top_n_724),
        .\calib_sel_reg[1]_36 (u_ddr_calib_top_n_726),
        .\calib_sel_reg[1]_37 (u_ddr_calib_top_n_727),
        .\calib_sel_reg[1]_38 (u_ddr_calib_top_n_728),
        .\calib_sel_reg[1]_39 (u_ddr_calib_top_n_729),
        .\calib_sel_reg[1]_4 (u_ddr_calib_top_n_684),
        .\calib_sel_reg[1]_40 (u_ddr_calib_top_n_730),
        .\calib_sel_reg[1]_41 (u_ddr_calib_top_n_731),
        .\calib_sel_reg[1]_42 (u_ddr_calib_top_n_732),
        .\calib_sel_reg[1]_43 (u_ddr_calib_top_n_733),
        .\calib_sel_reg[1]_44 (u_ddr_calib_top_n_734),
        .\calib_sel_reg[1]_45 (u_ddr_calib_top_n_735),
        .\calib_sel_reg[1]_46 (u_ddr_calib_top_n_736),
        .\calib_sel_reg[1]_47 (u_ddr_calib_top_n_737),
        .\calib_sel_reg[1]_48 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_pi_counter_load_val ),
        .\calib_sel_reg[1]_49 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_pi_counter_load_val ),
        .\calib_sel_reg[1]_5 (u_ddr_calib_top_n_685),
        .\calib_sel_reg[1]_50 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/A_pi_counter_load_val ),
        .\calib_sel_reg[1]_51 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/B_pi_counter_load_val ),
        .\calib_sel_reg[1]_52 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/C_pi_counter_load_val ),
        .\calib_sel_reg[1]_6 (u_ddr_calib_top_n_686),
        .\calib_sel_reg[1]_7 (u_ddr_calib_top_n_687),
        .\calib_sel_reg[1]_8 (u_ddr_calib_top_n_688),
        .\calib_sel_reg[1]_9 (u_ddr_calib_top_n_690),
        .\cmd_pipe_plus.mc_cas_n_reg[1] (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d4 ),
        .\cmd_pipe_plus.mc_cke_reg[3] (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d7 ),
        .\cmd_pipe_plus.mc_cke_reg[3]_0 ({mux_cke,mux_we_n,mux_ras_n,mux_cas_n,mux_cs_n,mux_odt}),
        .\cmd_pipe_plus.mc_data_offset_1_reg[5] (data_offset_1),
        .\cmd_pipe_plus.mc_data_offset_2_reg[5] (data_offset_2),
        .\cmd_pipe_plus.mc_odt_reg[0] (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d2 ),
        .\cmd_pipe_plus.mc_ras_n_reg[1] ({\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d5 [5],\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d5 [1]}),
        .\cmd_pipe_plus.mc_we_n_reg[1] (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6 ),
        .\cmp_err_4to1.compare_err_f3_reg (\cmp_err_4to1.compare_err_f3_reg ),
        .\cnt_shift_r_reg[0] (\cnt_shift_r_reg[0] ),
        .\complex_num_writes_reg[1] (\complex_num_writes_reg[1] ),
        .\corse_dec_reg[7][0] (\corse_dec_reg[7][0] ),
        .\corse_inc_reg[6][2] (\corse_inc_reg[6][2] ),
        .d_in({mux_address[51],mux_address[37],mux_address[23],mux_address[9],mux_address[43],mux_address[29],mux_address[15],mux_address[1],mux_address[47],mux_address[33],mux_address[19],mux_address[5],mux_address[42],mux_address[28],mux_address[14],mux_address[0],mux_address[54],mux_address[40],mux_address[26],mux_address[12],mux_address[45],mux_address[31],mux_address[17],mux_address[3],init_calib_complete,mux_address[27],mux_address[46],mux_address[32],mux_address[18],mux_address[4],mux_address[52],mux_address[38],mux_address[24],mux_address[10],mux_address[49],mux_address[35],mux_address[21],mux_address[7]}),
        .\data_offset_1_i1_reg[0] (\data_offset_1_i1_reg[0] ),
        .\data_offset_1_i1_reg[1] (\data_offset_1_i1_reg[1] ),
        .\data_offset_1_i1_reg[2] (\data_offset_1_i1_reg[2] ),
        .\data_offset_1_i1_reg[4] (\data_offset_1_i1_reg[4] ),
        .\data_offset_1_i1_reg[5] (\data_offset_1_i1_reg[5] ),
        .\data_offset_2_i1_reg[0] (\data_offset_2_i1_reg[0] ),
        .\data_offset_2_i1_reg[1] (\data_offset_2_i1_reg[1] ),
        .\data_offset_2_i1_reg[2] (\data_offset_2_i1_reg[2] ),
        .\data_offset_2_i1_reg[4] (\data_offset_2_i1_reg[4] ),
        .\data_offset_2_i1_reg[5] (\data_offset_2_i1_reg[5] ),
        .\device_temp_101_reg[11] (\device_temp_101_reg[11] ),
        .\dout_o_reg[15] (\entry_cnt_reg[4] ),
        .dqs_po_stg2_f_incdec_reg(u_ddr_calib_top_n_753),
        .dqs_po_stg2_f_incdec_reg_0(u_ddr_calib_top_n_754),
        .dqs_po_stg2_f_incdec_reg_1(u_ddr_calib_top_n_755),
        .dqs_po_stg2_f_incdec_reg_2(u_ddr_calib_top_n_756),
        .dqs_po_stg2_f_incdec_reg_3(u_ddr_calib_top_n_757),
        .dqs_po_stg2_f_incdec_reg_4(u_ddr_calib_top_n_758),
        .dqs_po_stg2_f_incdec_reg_5(u_ddr_calib_top_n_759),
        .dqs_po_stg2_f_incdec_reg_6(u_ddr_calib_top_n_760),
        .dqs_po_stg2_f_incdec_reg_7(u_ddr_calib_top_n_762),
        .dqs_po_stg2_f_incdec_reg_8(u_ddr_calib_top_n_763),
        .dqs_wl_po_stg2_c_incdec_reg(u_ddr_calib_top_n_689),
        .dqs_wl_po_stg2_c_incdec_reg_0(u_ddr_calib_top_n_721),
        .\en_cnt_div4.enable_wrlvl_cnt_reg[2] (\en_cnt_div4.enable_wrlvl_cnt_reg[2] ),
        .\en_cnt_div4.enable_wrlvl_cnt_reg[4] (\en_cnt_div4.enable_wrlvl_cnt_reg[4] ),
        .fine_adjust_reg(fine_adjust_reg),
        .\fine_dec_cnt_reg[5] (\fine_dec_cnt_reg[5] ),
        .\fine_inc_reg[6][3] (\fine_inc_reg[6][3] ),
        .first_fail_detect_reg(first_fail_detect_reg),
        .\four_dec_min_limit_reg[0] (\four_dec_min_limit_reg[0] ),
        .\gen_byte_sel_div2.calib_in_common_reg_0 (u_ddr_calib_top_n_745),
        .\gen_byte_sel_div2.calib_in_common_reg_1 (u_ddr_calib_top_n_746),
        .\gen_byte_sel_div2.calib_in_common_reg_2 (u_ddr_calib_top_n_748),
        .\gen_byte_sel_div2.calib_in_common_reg_3 (u_ddr_calib_top_n_749),
        .\gen_byte_sel_div2.calib_in_common_reg_4 (u_ddr_calib_top_n_750),
        .\gen_byte_sel_div2.calib_in_common_reg_5 (u_ddr_calib_top_n_751),
        .\gen_mux_rd[0].mux_rd_fall0_r1_reg[0] (u_ddr_mc_phy_wrapper_n_1229),
        .\gen_mux_rd[0].mux_rd_fall0_r_reg[0] (u_ddr_mc_phy_wrapper_n_646),
        .\gen_mux_rd[0].mux_rd_fall1_r1_reg[0] (u_ddr_mc_phy_wrapper_n_1245),
        .\gen_mux_rd[0].mux_rd_fall1_r_reg[0] (u_ddr_mc_phy_wrapper_n_651),
        .\gen_mux_rd[0].mux_rd_fall2_r1_reg[0] (u_ddr_mc_phy_wrapper_n_1261),
        .\gen_mux_rd[0].mux_rd_fall2_r_reg[0] (u_ddr_mc_phy_wrapper_n_655),
        .\gen_mux_rd[0].mux_rd_fall3_r1_reg[0] (u_ddr_mc_phy_wrapper_n_1277),
        .\gen_mux_rd[0].mux_rd_fall3_r_reg[0] (u_ddr_mc_phy_wrapper_n_636),
        .\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] (u_ddr_mc_phy_wrapper_n_1221),
        .\gen_mux_rd[0].mux_rd_rise0_r_reg[0] (u_ddr_mc_phy_wrapper_n_644),
        .\gen_mux_rd[0].mux_rd_rise1_r1_reg[0] (u_ddr_mc_phy_wrapper_n_1237),
        .\gen_mux_rd[0].mux_rd_rise1_r_reg[0] (u_ddr_mc_phy_wrapper_n_606),
        .\gen_mux_rd[0].mux_rd_rise2_r1_reg[0] (u_ddr_mc_phy_wrapper_n_1253),
        .\gen_mux_rd[0].mux_rd_rise2_r_reg[0] (u_ddr_mc_phy_wrapper_n_617),
        .\gen_mux_rd[0].mux_rd_rise3_r1_reg[0] (u_ddr_mc_phy_wrapper_n_1269),
        .\gen_mux_rd[0].mux_rd_rise3_r_reg[0] (u_ddr_mc_phy_wrapper_n_657),
        .\gen_mux_rd[1].mux_rd_fall0_r1_reg[1] (u_ddr_mc_phy_wrapper_n_1230),
        .\gen_mux_rd[1].mux_rd_fall0_r_reg[1] (u_ddr_mc_phy_wrapper_n_601),
        .\gen_mux_rd[1].mux_rd_fall1_r1_reg[1] (u_ddr_mc_phy_wrapper_n_1246),
        .\gen_mux_rd[1].mux_rd_fall1_r_reg[1] (u_ddr_mc_phy_wrapper_n_612),
        .\gen_mux_rd[1].mux_rd_fall2_r1_reg[1] (u_ddr_mc_phy_wrapper_n_1262),
        .\gen_mux_rd[1].mux_rd_fall2_r_reg[1] (u_ddr_mc_phy_wrapper_n_624),
        .\gen_mux_rd[1].mux_rd_fall3_r1_reg[1] (u_ddr_mc_phy_wrapper_n_1278),
        .\gen_mux_rd[1].mux_rd_fall3_r_reg[1] (u_ddr_mc_phy_wrapper_n_637),
        .\gen_mux_rd[1].mux_rd_rise0_r1_reg[1] (u_ddr_mc_phy_wrapper_n_1222),
        .\gen_mux_rd[1].mux_rd_rise0_r_reg[1] (u_ddr_mc_phy_wrapper_n_595),
        .\gen_mux_rd[1].mux_rd_rise1_r1_reg[1] (u_ddr_mc_phy_wrapper_n_1238),
        .\gen_mux_rd[1].mux_rd_rise1_r_reg[1] (u_ddr_mc_phy_wrapper_n_607),
        .\gen_mux_rd[1].mux_rd_rise2_r1_reg[1] (u_ddr_mc_phy_wrapper_n_1254),
        .\gen_mux_rd[1].mux_rd_rise2_r_reg[1] (u_ddr_mc_phy_wrapper_n_618),
        .\gen_mux_rd[1].mux_rd_rise3_r1_reg[1] (u_ddr_mc_phy_wrapper_n_1270),
        .\gen_mux_rd[1].mux_rd_rise3_r_reg[1] (u_ddr_mc_phy_wrapper_n_630),
        .\gen_mux_rd[2].mux_rd_fall0_r1_reg[2] (u_ddr_mc_phy_wrapper_n_1231),
        .\gen_mux_rd[2].mux_rd_fall0_r_reg[2] (u_ddr_mc_phy_wrapper_n_647),
        .\gen_mux_rd[2].mux_rd_fall1_r1_reg[2] (u_ddr_mc_phy_wrapper_n_1247),
        .\gen_mux_rd[2].mux_rd_fall1_r_reg[2] (u_ddr_mc_phy_wrapper_n_652),
        .\gen_mux_rd[2].mux_rd_fall2_r1_reg[2] (u_ddr_mc_phy_wrapper_n_1263),
        .\gen_mux_rd[2].mux_rd_fall2_r_reg[2] (u_ddr_mc_phy_wrapper_n_625),
        .\gen_mux_rd[2].mux_rd_fall3_r1_reg[2] (u_ddr_mc_phy_wrapper_n_1279),
        .\gen_mux_rd[2].mux_rd_fall3_r_reg[2] (u_ddr_mc_phy_wrapper_n_638),
        .\gen_mux_rd[2].mux_rd_rise0_r1_reg[2] (u_ddr_mc_phy_wrapper_n_1223),
        .\gen_mux_rd[2].mux_rd_rise0_r_reg[2] (u_ddr_mc_phy_wrapper_n_596),
        .\gen_mux_rd[2].mux_rd_rise1_r1_reg[2] (u_ddr_mc_phy_wrapper_n_1239),
        .\gen_mux_rd[2].mux_rd_rise1_r_reg[2] (u_ddr_mc_phy_wrapper_n_649),
        .\gen_mux_rd[2].mux_rd_rise2_r1_reg[2] (u_ddr_mc_phy_wrapper_n_1255),
        .\gen_mux_rd[2].mux_rd_rise2_r_reg[2] (u_ddr_mc_phy_wrapper_n_619),
        .\gen_mux_rd[2].mux_rd_rise3_r1_reg[2] (u_ddr_mc_phy_wrapper_n_1271),
        .\gen_mux_rd[2].mux_rd_rise3_r_reg[2] (u_ddr_mc_phy_wrapper_n_631),
        .\gen_mux_rd[3].mux_rd_fall0_r1_reg[3] (u_ddr_mc_phy_wrapper_n_1232),
        .\gen_mux_rd[3].mux_rd_fall0_r_reg[3] (u_ddr_mc_phy_wrapper_n_602),
        .\gen_mux_rd[3].mux_rd_fall1_r1_reg[3] (u_ddr_mc_phy_wrapper_n_1248),
        .\gen_mux_rd[3].mux_rd_fall1_r_reg[3] (u_ddr_mc_phy_wrapper_n_613),
        .\gen_mux_rd[3].mux_rd_fall2_r1_reg[3] (u_ddr_mc_phy_wrapper_n_1264),
        .\gen_mux_rd[3].mux_rd_fall2_r_reg[3] (u_ddr_mc_phy_wrapper_n_626),
        .\gen_mux_rd[3].mux_rd_fall3_r1_reg[3] (u_ddr_mc_phy_wrapper_n_1280),
        .\gen_mux_rd[3].mux_rd_fall3_r_reg[3] (u_ddr_mc_phy_wrapper_n_639),
        .\gen_mux_rd[3].mux_rd_rise0_r1_reg[3] (u_ddr_mc_phy_wrapper_n_1224),
        .\gen_mux_rd[3].mux_rd_rise0_r_reg[3] (u_ddr_mc_phy_wrapper_n_597),
        .\gen_mux_rd[3].mux_rd_rise1_r1_reg[3] (u_ddr_mc_phy_wrapper_n_1240),
        .\gen_mux_rd[3].mux_rd_rise1_r_reg[3] (u_ddr_mc_phy_wrapper_n_608),
        .\gen_mux_rd[3].mux_rd_rise2_r1_reg[3] (u_ddr_mc_phy_wrapper_n_1256),
        .\gen_mux_rd[3].mux_rd_rise2_r_reg[3] (u_ddr_mc_phy_wrapper_n_620),
        .\gen_mux_rd[3].mux_rd_rise3_r1_reg[3] (u_ddr_mc_phy_wrapper_n_1272),
        .\gen_mux_rd[3].mux_rd_rise3_r_reg[3] (u_ddr_mc_phy_wrapper_n_632),
        .\gen_mux_rd[4].mux_rd_fall0_r1_reg[4] (u_ddr_mc_phy_wrapper_n_1233),
        .\gen_mux_rd[4].mux_rd_fall0_r_reg[4] (u_ddr_mc_phy_wrapper_n_648),
        .\gen_mux_rd[4].mux_rd_fall1_r1_reg[4] (u_ddr_mc_phy_wrapper_n_1249),
        .\gen_mux_rd[4].mux_rd_fall1_r_reg[4] (u_ddr_mc_phy_wrapper_n_653),
        .\gen_mux_rd[4].mux_rd_fall2_r1_reg[4] (u_ddr_mc_phy_wrapper_n_1265),
        .\gen_mux_rd[4].mux_rd_fall2_r_reg[4] (u_ddr_mc_phy_wrapper_n_656),
        .\gen_mux_rd[4].mux_rd_fall3_r1_reg[4] (u_ddr_mc_phy_wrapper_n_1281),
        .\gen_mux_rd[4].mux_rd_fall3_r_reg[4] (u_ddr_mc_phy_wrapper_n_640),
        .\gen_mux_rd[4].mux_rd_rise0_r1_reg[4] (u_ddr_mc_phy_wrapper_n_1225),
        .\gen_mux_rd[4].mux_rd_rise0_r_reg[4] (u_ddr_mc_phy_wrapper_n_645),
        .\gen_mux_rd[4].mux_rd_rise1_r1_reg[4] (u_ddr_mc_phy_wrapper_n_1241),
        .\gen_mux_rd[4].mux_rd_rise1_r_reg[4] (u_ddr_mc_phy_wrapper_n_650),
        .\gen_mux_rd[4].mux_rd_rise2_r1_reg[4] (u_ddr_mc_phy_wrapper_n_1257),
        .\gen_mux_rd[4].mux_rd_rise2_r_reg[4] (u_ddr_mc_phy_wrapper_n_654),
        .\gen_mux_rd[4].mux_rd_rise3_r1_reg[4] (u_ddr_mc_phy_wrapper_n_1273),
        .\gen_mux_rd[4].mux_rd_rise3_r_reg[4] (u_ddr_mc_phy_wrapper_n_658),
        .\gen_mux_rd[5].mux_rd_fall0_r1_reg[5] (u_ddr_mc_phy_wrapper_n_1234),
        .\gen_mux_rd[5].mux_rd_fall0_r_reg[5] (u_ddr_mc_phy_wrapper_n_603),
        .\gen_mux_rd[5].mux_rd_fall1_r1_reg[5] (u_ddr_mc_phy_wrapper_n_1250),
        .\gen_mux_rd[5].mux_rd_fall1_r_reg[5] (u_ddr_mc_phy_wrapper_n_614),
        .\gen_mux_rd[5].mux_rd_fall2_r1_reg[5] (u_ddr_mc_phy_wrapper_n_1266),
        .\gen_mux_rd[5].mux_rd_fall2_r_reg[5] (u_ddr_mc_phy_wrapper_n_627),
        .\gen_mux_rd[5].mux_rd_fall3_r1_reg[5] (u_ddr_mc_phy_wrapper_n_1282),
        .\gen_mux_rd[5].mux_rd_fall3_r_reg[5] (u_ddr_mc_phy_wrapper_n_641),
        .\gen_mux_rd[5].mux_rd_rise0_r1_reg[5] (u_ddr_mc_phy_wrapper_n_1226),
        .\gen_mux_rd[5].mux_rd_rise0_r_reg[5] (u_ddr_mc_phy_wrapper_n_598),
        .\gen_mux_rd[5].mux_rd_rise1_r1_reg[5] (u_ddr_mc_phy_wrapper_n_1242),
        .\gen_mux_rd[5].mux_rd_rise1_r_reg[5] (u_ddr_mc_phy_wrapper_n_609),
        .\gen_mux_rd[5].mux_rd_rise2_r1_reg[5] (u_ddr_mc_phy_wrapper_n_1258),
        .\gen_mux_rd[5].mux_rd_rise2_r_reg[5] (u_ddr_mc_phy_wrapper_n_621),
        .\gen_mux_rd[5].mux_rd_rise3_r1_reg[5] (u_ddr_mc_phy_wrapper_n_1274),
        .\gen_mux_rd[5].mux_rd_rise3_r_reg[5] (u_ddr_mc_phy_wrapper_n_633),
        .\gen_mux_rd[6].mux_rd_fall0_r1_reg[6] (u_ddr_mc_phy_wrapper_n_1235),
        .\gen_mux_rd[6].mux_rd_fall0_r_reg[6] (u_ddr_mc_phy_wrapper_n_604),
        .\gen_mux_rd[6].mux_rd_fall1_r1_reg[6] (u_ddr_mc_phy_wrapper_n_1251),
        .\gen_mux_rd[6].mux_rd_fall1_r_reg[6] (u_ddr_mc_phy_wrapper_n_615),
        .\gen_mux_rd[6].mux_rd_fall2_r1_reg[6] (u_ddr_mc_phy_wrapper_n_1267),
        .\gen_mux_rd[6].mux_rd_fall2_r_reg[6] (u_ddr_mc_phy_wrapper_n_628),
        .\gen_mux_rd[6].mux_rd_fall3_r1_reg[6] (u_ddr_mc_phy_wrapper_n_1283),
        .\gen_mux_rd[6].mux_rd_fall3_r_reg[6] (u_ddr_mc_phy_wrapper_n_642),
        .\gen_mux_rd[6].mux_rd_rise0_r1_reg[6] (u_ddr_mc_phy_wrapper_n_1227),
        .\gen_mux_rd[6].mux_rd_rise0_r_reg[6] (u_ddr_mc_phy_wrapper_n_599),
        .\gen_mux_rd[6].mux_rd_rise1_r1_reg[6] (u_ddr_mc_phy_wrapper_n_1243),
        .\gen_mux_rd[6].mux_rd_rise1_r_reg[6] (u_ddr_mc_phy_wrapper_n_610),
        .\gen_mux_rd[6].mux_rd_rise2_r1_reg[6] (u_ddr_mc_phy_wrapper_n_1259),
        .\gen_mux_rd[6].mux_rd_rise2_r_reg[6] (u_ddr_mc_phy_wrapper_n_622),
        .\gen_mux_rd[6].mux_rd_rise3_r1_reg[6] (u_ddr_mc_phy_wrapper_n_1275),
        .\gen_mux_rd[6].mux_rd_rise3_r_reg[6] (u_ddr_mc_phy_wrapper_n_634),
        .\gen_mux_rd[7].mux_rd_fall0_r1_reg[7] (u_ddr_mc_phy_wrapper_n_1236),
        .\gen_mux_rd[7].mux_rd_fall0_r_reg[7] (u_ddr_mc_phy_wrapper_n_605),
        .\gen_mux_rd[7].mux_rd_fall1_r1_reg[7] (u_ddr_mc_phy_wrapper_n_1252),
        .\gen_mux_rd[7].mux_rd_fall1_r_reg[7] (u_ddr_mc_phy_wrapper_n_616),
        .\gen_mux_rd[7].mux_rd_fall2_r1_reg[7] (u_ddr_mc_phy_wrapper_n_1268),
        .\gen_mux_rd[7].mux_rd_fall2_r_reg[7] (u_ddr_mc_phy_wrapper_n_629),
        .\gen_mux_rd[7].mux_rd_fall3_r1_reg[7] (u_ddr_mc_phy_wrapper_n_1284),
        .\gen_mux_rd[7].mux_rd_fall3_r_reg[7] (u_ddr_mc_phy_wrapper_n_643),
        .\gen_mux_rd[7].mux_rd_rise0_r1_reg[7] (u_ddr_mc_phy_wrapper_n_1228),
        .\gen_mux_rd[7].mux_rd_rise0_r_reg[7] (u_ddr_mc_phy_wrapper_n_600),
        .\gen_mux_rd[7].mux_rd_rise1_r1_reg[7] (u_ddr_mc_phy_wrapper_n_1244),
        .\gen_mux_rd[7].mux_rd_rise1_r_reg[7] (u_ddr_mc_phy_wrapper_n_611),
        .\gen_mux_rd[7].mux_rd_rise2_r1_reg[7] (u_ddr_mc_phy_wrapper_n_1260),
        .\gen_mux_rd[7].mux_rd_rise2_r_reg[7] (u_ddr_mc_phy_wrapper_n_623),
        .\gen_mux_rd[7].mux_rd_rise3_r1_reg[7] (u_ddr_mc_phy_wrapper_n_1276),
        .\gen_mux_rd[7].mux_rd_rise3_r_reg[7] (u_ddr_mc_phy_wrapper_n_635),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] (u_ddr_mc_phy_wrapper_n_1310),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] (u_ddr_mc_phy_wrapper_n_1350),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] (u_ddr_mc_phy_wrapper_n_1326),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] (u_ddr_mc_phy_wrapper_n_1302),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] (u_ddr_mc_phy_wrapper_n_1342),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] (u_ddr_mc_phy_wrapper_n_1318),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] (u_ddr_mc_phy_wrapper_n_1334),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] (u_ddr_mc_phy_wrapper_n_1311),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] (u_ddr_mc_phy_wrapper_n_1351),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] (u_ddr_mc_phy_wrapper_n_1327),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] (u_ddr_mc_phy_wrapper_n_1303),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] (u_ddr_mc_phy_wrapper_n_1343),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] (u_ddr_mc_phy_wrapper_n_1295),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] (u_ddr_mc_phy_wrapper_n_1319),
        .\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] (u_ddr_mc_phy_wrapper_n_1335),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] (u_ddr_mc_phy_wrapper_n_1312),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] (u_ddr_mc_phy_wrapper_n_1352),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] (u_ddr_mc_phy_wrapper_n_1328),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] (u_ddr_mc_phy_wrapper_n_1304),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] (u_ddr_mc_phy_wrapper_n_1344),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] (u_ddr_mc_phy_wrapper_n_1296),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] (u_ddr_mc_phy_wrapper_n_1320),
        .\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] (u_ddr_mc_phy_wrapper_n_1336),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] (u_ddr_mc_phy_wrapper_n_1313),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] (u_ddr_mc_phy_wrapper_n_1353),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] (u_ddr_mc_phy_wrapper_n_1329),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] (u_ddr_mc_phy_wrapper_n_1305),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] (u_ddr_mc_phy_wrapper_n_1345),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] (u_ddr_mc_phy_wrapper_n_1297),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] (u_ddr_mc_phy_wrapper_n_1321),
        .\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] (u_ddr_mc_phy_wrapper_n_1337),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] (u_ddr_mc_phy_wrapper_n_1314),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] (u_ddr_mc_phy_wrapper_n_1354),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] (u_ddr_mc_phy_wrapper_n_1330),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] (u_ddr_mc_phy_wrapper_n_1306),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] (u_ddr_mc_phy_wrapper_n_1346),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] (u_ddr_mc_phy_wrapper_n_1298),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] (u_ddr_mc_phy_wrapper_n_1322),
        .\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] (u_ddr_mc_phy_wrapper_n_1338),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] (u_ddr_mc_phy_wrapper_n_1315),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] (u_ddr_mc_phy_wrapper_n_1355),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] (u_ddr_mc_phy_wrapper_n_1331),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] (u_ddr_mc_phy_wrapper_n_1307),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] (u_ddr_mc_phy_wrapper_n_1347),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] (u_ddr_mc_phy_wrapper_n_1299),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] (u_ddr_mc_phy_wrapper_n_1323),
        .\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] (u_ddr_mc_phy_wrapper_n_1339),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] (u_ddr_mc_phy_wrapper_n_1316),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] (u_ddr_mc_phy_wrapper_n_1356),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] (u_ddr_mc_phy_wrapper_n_1332),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] (u_ddr_mc_phy_wrapper_n_1308),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] (u_ddr_mc_phy_wrapper_n_1348),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] (u_ddr_mc_phy_wrapper_n_1300),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] (u_ddr_mc_phy_wrapper_n_1324),
        .\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] (u_ddr_mc_phy_wrapper_n_1340),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] (u_ddr_mc_phy_wrapper_n_1317),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] (u_ddr_mc_phy_wrapper_n_1357),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] (u_ddr_mc_phy_wrapper_n_1333),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] (u_ddr_mc_phy_wrapper_n_1309),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] (u_ddr_mc_phy_wrapper_n_1349),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] (u_ddr_mc_phy_wrapper_n_1301),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] (u_ddr_mc_phy_wrapper_n_1325),
        .\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] (u_ddr_mc_phy_wrapper_n_1341),
        .\gen_no_mirror.div_clk_loop[0].phy_address_reg[2] (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d8 ),
        .\gen_no_mirror.div_clk_loop[0].phy_address_reg[8] (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d4 ),
        .\gen_no_mirror.div_clk_loop[0].phy_address_reg[9] (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d9 ),
        .\gen_no_mirror.div_clk_loop[0].phy_bank_reg[0] (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6 ),
        .\gen_no_mirror.div_clk_loop[0].phy_bank_reg[1] (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5 ),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_5 ),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_5 ),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_5 ),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_5 ),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_6 ),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_2 ),
        .\gen_rd[0].rd_data_rise_wl_r_reg[0]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_5 ),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ),
        .\gen_rd[1].rd_data_rise_wl_r_reg[1]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ),
        .\gen_rd[2].rd_data_rise_wl_r_reg[2] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ),
        .\gen_rd[2].rd_data_rise_wl_r_reg[2]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ),
        .\gen_rd[2].rd_data_rise_wl_r_reg[2]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_3 ),
        .\gen_rd[2].rd_data_rise_wl_r_reg[2]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ),
        .\gen_rd[2].rd_data_rise_wl_r_reg[2]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ),
        .\gen_rd[2].rd_data_rise_wl_r_reg[2]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3 ),
        .\gen_rd[2].rd_data_rise_wl_r_reg[2]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ),
        .\gen_rd[2].rd_data_rise_wl_r_reg[2]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ),
        .\gen_rd[3].rd_data_rise_wl_r_reg[3] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_4 ),
        .\gen_rd[3].rd_data_rise_wl_r_reg[3]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_4 ),
        .\gen_rd[3].rd_data_rise_wl_r_reg[3]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ),
        .\gen_rd[3].rd_data_rise_wl_r_reg[3]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_4 ),
        .\gen_rd[3].rd_data_rise_wl_r_reg[3]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_4 ),
        .\gen_rd[3].rd_data_rise_wl_r_reg[3]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ),
        .\gen_rd[3].rd_data_rise_wl_r_reg[3]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_5 ),
        .\gen_rd[3].rd_data_rise_wl_r_reg[3]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_4 ),
        .\gen_rd[4].rd_data_rise_wl_r_reg[4] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_6 ),
        .\gen_rd[4].rd_data_rise_wl_r_reg[4]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_6 ),
        .\gen_rd[4].rd_data_rise_wl_r_reg[4]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ),
        .\gen_rd[4].rd_data_rise_wl_r_reg[4]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_6 ),
        .\gen_rd[4].rd_data_rise_wl_r_reg[4]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_6 ),
        .\gen_rd[4].rd_data_rise_wl_r_reg[4]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_5 ),
        .\gen_rd[4].rd_data_rise_wl_r_reg[4]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_6 ),
        .\gen_rd[4].rd_data_rise_wl_r_reg[4]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_6 ),
        .\gen_rd[5].rd_data_rise_wl_r_reg[5] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ),
        .\gen_rd[5].rd_data_rise_wl_r_reg[5]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ),
        .\gen_rd[5].rd_data_rise_wl_r_reg[5]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ),
        .\gen_rd[5].rd_data_rise_wl_r_reg[5]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ),
        .\gen_rd[5].rd_data_rise_wl_r_reg[5]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ),
        .\gen_rd[5].rd_data_rise_wl_r_reg[5]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ),
        .\gen_rd[5].rd_data_rise_wl_r_reg[5]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_3 ),
        .\gen_rd[5].rd_data_rise_wl_r_reg[5]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2 ),
        .\gen_rd[6].rd_data_rise_wl_r_reg[6] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_3 ),
        .\gen_rd[6].rd_data_rise_wl_r_reg[6]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_3 ),
        .\gen_rd[6].rd_data_rise_wl_r_reg[6]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ),
        .\gen_rd[6].rd_data_rise_wl_r_reg[6]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_3 ),
        .\gen_rd[6].rd_data_rise_wl_r_reg[6]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_3 ),
        .\gen_rd[6].rd_data_rise_wl_r_reg[6]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ),
        .\gen_rd[6].rd_data_rise_wl_r_reg[6]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_4 ),
        .\gen_rd[6].rd_data_rise_wl_r_reg[6]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_3 ),
        .\gen_rd[7].rd_data_rise_wl_r_reg[7] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ),
        .\gen_rd[7].rd_data_rise_wl_r_reg[7]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ),
        .\gen_rd[7].rd_data_rise_wl_r_reg[7]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_4 ),
        .\gen_rd[7].rd_data_rise_wl_r_reg[7]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ),
        .\gen_rd[7].rd_data_rise_wl_r_reg[7]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ),
        .\gen_rd[7].rd_data_rise_wl_r_reg[7]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_4 ),
        .\gen_rd[7].rd_data_rise_wl_r_reg[7]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1 ),
        .\gen_rd[7].rd_data_rise_wl_r_reg[7]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ),
        .idelay_ce_r2_reg_0(u_ddr_calib_top_n_706),
        .idelay_ce_r2_reg_1(u_ddr_calib_top_n_738),
        .idelay_inc(idelay_inc),
        .idelay_ld_rst(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/idelay_ld_rst ),
        .idelay_ld_rst_10(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/idelay_ld_rst ),
        .idelay_ld_rst_11(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/idelay_ld_rst ),
        .idelay_ld_rst_12(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/idelay_ld_rst ),
        .idelay_ld_rst_13(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/idelay_ld_rst ),
        .idelay_ld_rst_7(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/idelay_ld_rst ),
        .idelay_ld_rst_8(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/idelay_ld_rst ),
        .idelay_ld_rst_9(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/idelay_ld_rst ),
        .\idelay_tap_cnt_r_reg[0][0][4] (\idelay_tap_cnt_r_reg[0][0][4] ),
        .\idelay_tap_cnt_r_reg[0][4][4] (\idelay_tap_cnt_r_reg[0][4][4] ),
        .if_empty(if_empty),
        .ififo_rst_reg({pi_rst_dqs_find[2],pi_rst_dqs_find[0]}),
        .in0({u_ddr_mc_phy_wrapper_n_33,u_ddr_mc_phy_wrapper_n_34,u_ddr_mc_phy_wrapper_n_35,u_ddr_mc_phy_wrapper_n_36,u_ddr_mc_phy_wrapper_n_37,u_ddr_mc_phy_wrapper_n_38,u_ddr_mc_phy_wrapper_n_39,u_ddr_mc_phy_wrapper_n_40}),
        .init_calib_complete_reg_rep_0(u_ddr_calib_top_n_52),
        .init_calib_complete_reg_rep__0_0(u_ddr_calib_top_n_53),
        .init_calib_complete_reg_rep__11_0(u_ddr_calib_top_n_54),
        .init_calib_complete_reg_rep__12_0(init_calib_complete_reg_rep__12),
        .init_calib_complete_reg_rep__24_0(init_calib_complete_reg_rep__24),
        .init_calib_complete_reg_rep__25_0(init_calib_complete_reg_rep__25),
        .init_calib_complete_reg_rep__26_0(init_calib_complete_reg_rep__26),
        .init_calib_complete_reg_rep__26_1(init_calib_complete_reg_rep__26_0),
        .init_complete_r1_timing_reg(init_complete_r1_timing_reg),
        .\init_state_r_reg[4] (\init_state_r_reg[4] ),
        .mc_address({mc_address[37],mc_address[35:14],mc_address[12],mc_address[10:0]}),
        .mc_bank(mc_bank),
        .mc_cas_n(mc_cas_n[1]),
        .mc_cke(mc_cke),
        .mc_cmd(mc_cmd),
        .mc_data_offset(mc_data_offset),
        .mc_data_offset_1(mc_data_offset_1),
        .mc_data_offset_2(mc_data_offset_2),
        .mc_odt(mc_odt),
        .mc_ras_n(mc_ras_n[1]),
        .mc_ref_zq_wip(mc_ref_zq_wip),
        .mc_we_n(mc_we_n[1]),
        .mc_wrdata_en(mc_wrdata_en),
        .mem_out({u_ddr_mc_phy_wrapper_n_1184,u_ddr_mc_phy_wrapper_n_1185,u_ddr_mc_phy_wrapper_n_1186,u_ddr_mc_phy_wrapper_n_1187,u_ddr_mc_phy_wrapper_n_1188,u_ddr_mc_phy_wrapper_n_1189,u_ddr_mc_phy_wrapper_n_1190,u_ddr_mc_phy_wrapper_n_1191,u_ddr_mc_phy_wrapper_n_1192,u_ddr_mc_phy_wrapper_n_1193,u_ddr_mc_phy_wrapper_n_1194,u_ddr_mc_phy_wrapper_n_1195,u_ddr_mc_phy_wrapper_n_1196,u_ddr_mc_phy_wrapper_n_1197,u_ddr_mc_phy_wrapper_n_1198,u_ddr_mc_phy_wrapper_n_1199,u_ddr_mc_phy_wrapper_n_1200,u_ddr_mc_phy_wrapper_n_1201,u_ddr_mc_phy_wrapper_n_1202,u_ddr_mc_phy_wrapper_n_1203,u_ddr_mc_phy_wrapper_n_1204,u_ddr_mc_phy_wrapper_n_1205,u_ddr_mc_phy_wrapper_n_1206,u_ddr_mc_phy_wrapper_n_1207,u_ddr_mc_phy_wrapper_n_1208,u_ddr_mc_phy_wrapper_n_1209,u_ddr_mc_phy_wrapper_n_1210,u_ddr_mc_phy_wrapper_n_1211,u_ddr_mc_phy_wrapper_n_1212,u_ddr_mc_phy_wrapper_n_1213,u_ddr_mc_phy_wrapper_n_1214,u_ddr_mc_phy_wrapper_n_1215,u_ddr_mc_phy_wrapper_n_1216,u_ddr_mc_phy_wrapper_n_1217,u_ddr_mc_phy_wrapper_n_1218,u_ddr_mc_phy_wrapper_n_1219}),
        .mem_reg_0_15_12_17(Q),
        .mux_reset_n(mux_reset_n),
        .new_cnt_cpt_r_reg(new_cnt_cpt_r_reg),
        .\not_empty_wait_cnt_reg[4] (\not_empty_wait_cnt_reg[4] ),
        .\one_dec_max_limit_reg[2] (\one_dec_max_limit_reg[2] ),
        .\one_dec_min_limit_reg[11] (\one_dec_min_limit_reg[11] ),
        .out(pi_fine_enable),
        .out_fifo(u_ddr_mc_phy_wrapper_n_70),
        .out_fifo_0({\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [75:72],\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [67:64],\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [55:52],\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [47:40],\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [35:32]}),
        .out_fifo_1(u_ddr_mc_phy_wrapper_n_1360),
        .out_fifo_10({u_ddr_mc_phy_wrapper_n_660,u_ddr_mc_phy_wrapper_n_661,u_ddr_mc_phy_wrapper_n_662,u_ddr_mc_phy_wrapper_n_663,u_ddr_mc_phy_wrapper_n_664,u_ddr_mc_phy_wrapper_n_665,u_ddr_mc_phy_wrapper_n_666,u_ddr_mc_phy_wrapper_n_667,u_ddr_mc_phy_wrapper_n_668,u_ddr_mc_phy_wrapper_n_669,u_ddr_mc_phy_wrapper_n_670,u_ddr_mc_phy_wrapper_n_671,u_ddr_mc_phy_wrapper_n_672,u_ddr_mc_phy_wrapper_n_673,u_ddr_mc_phy_wrapper_n_674,u_ddr_mc_phy_wrapper_n_675,u_ddr_mc_phy_wrapper_n_676,u_ddr_mc_phy_wrapper_n_677,u_ddr_mc_phy_wrapper_n_678,u_ddr_mc_phy_wrapper_n_679,u_ddr_mc_phy_wrapper_n_680,u_ddr_mc_phy_wrapper_n_681,u_ddr_mc_phy_wrapper_n_682,u_ddr_mc_phy_wrapper_n_683,u_ddr_mc_phy_wrapper_n_684,u_ddr_mc_phy_wrapper_n_685,u_ddr_mc_phy_wrapper_n_686,u_ddr_mc_phy_wrapper_n_687,u_ddr_mc_phy_wrapper_n_688,u_ddr_mc_phy_wrapper_n_689,u_ddr_mc_phy_wrapper_n_690,u_ddr_mc_phy_wrapper_n_691,u_ddr_mc_phy_wrapper_n_692,u_ddr_mc_phy_wrapper_n_693,u_ddr_mc_phy_wrapper_n_694,u_ddr_mc_phy_wrapper_n_695,u_ddr_mc_phy_wrapper_n_696,u_ddr_mc_phy_wrapper_n_697,u_ddr_mc_phy_wrapper_n_698,u_ddr_mc_phy_wrapper_n_699,u_ddr_mc_phy_wrapper_n_700,u_ddr_mc_phy_wrapper_n_701,u_ddr_mc_phy_wrapper_n_702,u_ddr_mc_phy_wrapper_n_703,u_ddr_mc_phy_wrapper_n_704,u_ddr_mc_phy_wrapper_n_705,u_ddr_mc_phy_wrapper_n_706,u_ddr_mc_phy_wrapper_n_707,u_ddr_mc_phy_wrapper_n_708,u_ddr_mc_phy_wrapper_n_709,u_ddr_mc_phy_wrapper_n_710,u_ddr_mc_phy_wrapper_n_711,u_ddr_mc_phy_wrapper_n_712,u_ddr_mc_phy_wrapper_n_713,u_ddr_mc_phy_wrapper_n_714,u_ddr_mc_phy_wrapper_n_715,u_ddr_mc_phy_wrapper_n_716,u_ddr_mc_phy_wrapper_n_717,u_ddr_mc_phy_wrapper_n_718,u_ddr_mc_phy_wrapper_n_719,u_ddr_mc_phy_wrapper_n_720,u_ddr_mc_phy_wrapper_n_721,u_ddr_mc_phy_wrapper_n_722,u_ddr_mc_phy_wrapper_n_723}),
        .out_fifo_11(u_ddr_mc_phy_wrapper_n_59),
        .out_fifo_12({u_ddr_mc_phy_wrapper_n_724,u_ddr_mc_phy_wrapper_n_725,u_ddr_mc_phy_wrapper_n_726,u_ddr_mc_phy_wrapper_n_727,u_ddr_mc_phy_wrapper_n_728,u_ddr_mc_phy_wrapper_n_729,u_ddr_mc_phy_wrapper_n_730,u_ddr_mc_phy_wrapper_n_731,u_ddr_mc_phy_wrapper_n_732,u_ddr_mc_phy_wrapper_n_733,u_ddr_mc_phy_wrapper_n_734,u_ddr_mc_phy_wrapper_n_735,u_ddr_mc_phy_wrapper_n_736,u_ddr_mc_phy_wrapper_n_737,u_ddr_mc_phy_wrapper_n_738,u_ddr_mc_phy_wrapper_n_739,u_ddr_mc_phy_wrapper_n_740,u_ddr_mc_phy_wrapper_n_741,u_ddr_mc_phy_wrapper_n_742,u_ddr_mc_phy_wrapper_n_743,u_ddr_mc_phy_wrapper_n_744,u_ddr_mc_phy_wrapper_n_745,u_ddr_mc_phy_wrapper_n_746,u_ddr_mc_phy_wrapper_n_747,u_ddr_mc_phy_wrapper_n_748,u_ddr_mc_phy_wrapper_n_749,u_ddr_mc_phy_wrapper_n_750,u_ddr_mc_phy_wrapper_n_751,u_ddr_mc_phy_wrapper_n_752,u_ddr_mc_phy_wrapper_n_753,u_ddr_mc_phy_wrapper_n_754,u_ddr_mc_phy_wrapper_n_755,u_ddr_mc_phy_wrapper_n_756,u_ddr_mc_phy_wrapper_n_757,u_ddr_mc_phy_wrapper_n_758,u_ddr_mc_phy_wrapper_n_759,u_ddr_mc_phy_wrapper_n_760,u_ddr_mc_phy_wrapper_n_761,u_ddr_mc_phy_wrapper_n_762,u_ddr_mc_phy_wrapper_n_763,u_ddr_mc_phy_wrapper_n_764,u_ddr_mc_phy_wrapper_n_765,u_ddr_mc_phy_wrapper_n_766,u_ddr_mc_phy_wrapper_n_767,u_ddr_mc_phy_wrapper_n_768,u_ddr_mc_phy_wrapper_n_769,u_ddr_mc_phy_wrapper_n_770,u_ddr_mc_phy_wrapper_n_771,u_ddr_mc_phy_wrapper_n_772,u_ddr_mc_phy_wrapper_n_773,u_ddr_mc_phy_wrapper_n_774,u_ddr_mc_phy_wrapper_n_775,u_ddr_mc_phy_wrapper_n_776,u_ddr_mc_phy_wrapper_n_777,u_ddr_mc_phy_wrapper_n_778,u_ddr_mc_phy_wrapper_n_779,u_ddr_mc_phy_wrapper_n_780,u_ddr_mc_phy_wrapper_n_781,u_ddr_mc_phy_wrapper_n_782,u_ddr_mc_phy_wrapper_n_783,u_ddr_mc_phy_wrapper_n_784,u_ddr_mc_phy_wrapper_n_785,u_ddr_mc_phy_wrapper_n_786,u_ddr_mc_phy_wrapper_n_787}),
        .out_fifo_13(u_ddr_mc_phy_wrapper_n_61),
        .out_fifo_14({u_ddr_mc_phy_wrapper_n_788,u_ddr_mc_phy_wrapper_n_789,u_ddr_mc_phy_wrapper_n_790,u_ddr_mc_phy_wrapper_n_791,u_ddr_mc_phy_wrapper_n_792,u_ddr_mc_phy_wrapper_n_793,u_ddr_mc_phy_wrapper_n_794,u_ddr_mc_phy_wrapper_n_795,u_ddr_mc_phy_wrapper_n_796,u_ddr_mc_phy_wrapper_n_797,u_ddr_mc_phy_wrapper_n_798,u_ddr_mc_phy_wrapper_n_799,u_ddr_mc_phy_wrapper_n_800,u_ddr_mc_phy_wrapper_n_801,u_ddr_mc_phy_wrapper_n_802,u_ddr_mc_phy_wrapper_n_803,u_ddr_mc_phy_wrapper_n_804,u_ddr_mc_phy_wrapper_n_805,u_ddr_mc_phy_wrapper_n_806,u_ddr_mc_phy_wrapper_n_807,u_ddr_mc_phy_wrapper_n_808,u_ddr_mc_phy_wrapper_n_809,u_ddr_mc_phy_wrapper_n_810,u_ddr_mc_phy_wrapper_n_811,u_ddr_mc_phy_wrapper_n_812,u_ddr_mc_phy_wrapper_n_813,u_ddr_mc_phy_wrapper_n_814,u_ddr_mc_phy_wrapper_n_815,u_ddr_mc_phy_wrapper_n_816,u_ddr_mc_phy_wrapper_n_817,u_ddr_mc_phy_wrapper_n_818,u_ddr_mc_phy_wrapper_n_819,u_ddr_mc_phy_wrapper_n_820,u_ddr_mc_phy_wrapper_n_821,u_ddr_mc_phy_wrapper_n_822,u_ddr_mc_phy_wrapper_n_823,u_ddr_mc_phy_wrapper_n_824,u_ddr_mc_phy_wrapper_n_825,u_ddr_mc_phy_wrapper_n_826,u_ddr_mc_phy_wrapper_n_827,u_ddr_mc_phy_wrapper_n_828,u_ddr_mc_phy_wrapper_n_829,u_ddr_mc_phy_wrapper_n_830,u_ddr_mc_phy_wrapper_n_831,u_ddr_mc_phy_wrapper_n_832,u_ddr_mc_phy_wrapper_n_833,u_ddr_mc_phy_wrapper_n_834,u_ddr_mc_phy_wrapper_n_835,u_ddr_mc_phy_wrapper_n_836,u_ddr_mc_phy_wrapper_n_837,u_ddr_mc_phy_wrapper_n_838,u_ddr_mc_phy_wrapper_n_839,u_ddr_mc_phy_wrapper_n_840,u_ddr_mc_phy_wrapper_n_841,u_ddr_mc_phy_wrapper_n_842,u_ddr_mc_phy_wrapper_n_843,u_ddr_mc_phy_wrapper_n_844,u_ddr_mc_phy_wrapper_n_845,u_ddr_mc_phy_wrapper_n_846,u_ddr_mc_phy_wrapper_n_847,u_ddr_mc_phy_wrapper_n_848,u_ddr_mc_phy_wrapper_n_849,u_ddr_mc_phy_wrapper_n_850,u_ddr_mc_phy_wrapper_n_851}),
        .out_fifo_15(u_ddr_mc_phy_wrapper_n_62),
        .out_fifo_16({u_ddr_mc_phy_wrapper_n_852,u_ddr_mc_phy_wrapper_n_853,u_ddr_mc_phy_wrapper_n_854,u_ddr_mc_phy_wrapper_n_855,u_ddr_mc_phy_wrapper_n_856,u_ddr_mc_phy_wrapper_n_857,u_ddr_mc_phy_wrapper_n_858,u_ddr_mc_phy_wrapper_n_859,u_ddr_mc_phy_wrapper_n_860,u_ddr_mc_phy_wrapper_n_861,u_ddr_mc_phy_wrapper_n_862,u_ddr_mc_phy_wrapper_n_863,u_ddr_mc_phy_wrapper_n_864,u_ddr_mc_phy_wrapper_n_865,u_ddr_mc_phy_wrapper_n_866,u_ddr_mc_phy_wrapper_n_867,u_ddr_mc_phy_wrapper_n_868,u_ddr_mc_phy_wrapper_n_869,u_ddr_mc_phy_wrapper_n_870,u_ddr_mc_phy_wrapper_n_871,u_ddr_mc_phy_wrapper_n_872,u_ddr_mc_phy_wrapper_n_873,u_ddr_mc_phy_wrapper_n_874,u_ddr_mc_phy_wrapper_n_875,u_ddr_mc_phy_wrapper_n_876,u_ddr_mc_phy_wrapper_n_877,u_ddr_mc_phy_wrapper_n_878,u_ddr_mc_phy_wrapper_n_879,u_ddr_mc_phy_wrapper_n_880,u_ddr_mc_phy_wrapper_n_881,u_ddr_mc_phy_wrapper_n_882,u_ddr_mc_phy_wrapper_n_883,u_ddr_mc_phy_wrapper_n_884,u_ddr_mc_phy_wrapper_n_885,u_ddr_mc_phy_wrapper_n_886,u_ddr_mc_phy_wrapper_n_887,u_ddr_mc_phy_wrapper_n_888,u_ddr_mc_phy_wrapper_n_889,u_ddr_mc_phy_wrapper_n_890,u_ddr_mc_phy_wrapper_n_891,u_ddr_mc_phy_wrapper_n_892,u_ddr_mc_phy_wrapper_n_893,u_ddr_mc_phy_wrapper_n_894,u_ddr_mc_phy_wrapper_n_895,u_ddr_mc_phy_wrapper_n_896,u_ddr_mc_phy_wrapper_n_897,u_ddr_mc_phy_wrapper_n_898,u_ddr_mc_phy_wrapper_n_899,u_ddr_mc_phy_wrapper_n_900,u_ddr_mc_phy_wrapper_n_901,u_ddr_mc_phy_wrapper_n_902,u_ddr_mc_phy_wrapper_n_903,u_ddr_mc_phy_wrapper_n_904,u_ddr_mc_phy_wrapper_n_905,u_ddr_mc_phy_wrapper_n_906,u_ddr_mc_phy_wrapper_n_907,u_ddr_mc_phy_wrapper_n_908,u_ddr_mc_phy_wrapper_n_909,u_ddr_mc_phy_wrapper_n_910,u_ddr_mc_phy_wrapper_n_911,u_ddr_mc_phy_wrapper_n_912,u_ddr_mc_phy_wrapper_n_913,u_ddr_mc_phy_wrapper_n_914,u_ddr_mc_phy_wrapper_n_915}),
        .out_fifo_17(u_ddr_mc_phy_wrapper_n_63),
        .out_fifo_18({\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/mem_out [59:56],\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/mem_out [53],\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/mem_out [45],\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/mem_out [41],\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/mem_out [33],\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/mem_out [19:16]}),
        .out_fifo_19(u_ddr_mc_phy_wrapper_n_69),
        .out_fifo_2({u_ddr_mc_phy_wrapper_n_922,u_ddr_mc_phy_wrapper_n_923,u_ddr_mc_phy_wrapper_n_924,u_ddr_mc_phy_wrapper_n_925,u_ddr_mc_phy_wrapper_n_926,u_ddr_mc_phy_wrapper_n_927,u_ddr_mc_phy_wrapper_n_928,u_ddr_mc_phy_wrapper_n_929,u_ddr_mc_phy_wrapper_n_930,u_ddr_mc_phy_wrapper_n_931,u_ddr_mc_phy_wrapper_n_932,u_ddr_mc_phy_wrapper_n_933,u_ddr_mc_phy_wrapper_n_934,u_ddr_mc_phy_wrapper_n_935,u_ddr_mc_phy_wrapper_n_936,u_ddr_mc_phy_wrapper_n_937,u_ddr_mc_phy_wrapper_n_938,u_ddr_mc_phy_wrapper_n_939,u_ddr_mc_phy_wrapper_n_940,u_ddr_mc_phy_wrapper_n_941,u_ddr_mc_phy_wrapper_n_942,u_ddr_mc_phy_wrapper_n_943,u_ddr_mc_phy_wrapper_n_944,u_ddr_mc_phy_wrapper_n_945,u_ddr_mc_phy_wrapper_n_946,u_ddr_mc_phy_wrapper_n_947,u_ddr_mc_phy_wrapper_n_948,u_ddr_mc_phy_wrapper_n_949,u_ddr_mc_phy_wrapper_n_950,u_ddr_mc_phy_wrapper_n_951,u_ddr_mc_phy_wrapper_n_952,u_ddr_mc_phy_wrapper_n_953,u_ddr_mc_phy_wrapper_n_954,u_ddr_mc_phy_wrapper_n_955,u_ddr_mc_phy_wrapper_n_956,u_ddr_mc_phy_wrapper_n_957,u_ddr_mc_phy_wrapper_n_958,u_ddr_mc_phy_wrapper_n_959,u_ddr_mc_phy_wrapper_n_960,u_ddr_mc_phy_wrapper_n_961,u_ddr_mc_phy_wrapper_n_962,u_ddr_mc_phy_wrapper_n_963,u_ddr_mc_phy_wrapper_n_964,u_ddr_mc_phy_wrapper_n_965,u_ddr_mc_phy_wrapper_n_966,u_ddr_mc_phy_wrapper_n_967,u_ddr_mc_phy_wrapper_n_968,u_ddr_mc_phy_wrapper_n_969,u_ddr_mc_phy_wrapper_n_970,u_ddr_mc_phy_wrapper_n_971,u_ddr_mc_phy_wrapper_n_972,u_ddr_mc_phy_wrapper_n_973,u_ddr_mc_phy_wrapper_n_974,u_ddr_mc_phy_wrapper_n_975,u_ddr_mc_phy_wrapper_n_976,u_ddr_mc_phy_wrapper_n_977,u_ddr_mc_phy_wrapper_n_978,u_ddr_mc_phy_wrapper_n_979,u_ddr_mc_phy_wrapper_n_980,u_ddr_mc_phy_wrapper_n_981,u_ddr_mc_phy_wrapper_n_982,u_ddr_mc_phy_wrapper_n_983,u_ddr_mc_phy_wrapper_n_984,u_ddr_mc_phy_wrapper_n_985}),
        .out_fifo_3(u_ddr_mc_phy_wrapper_n_65),
        .out_fifo_4({u_ddr_mc_phy_wrapper_n_986,u_ddr_mc_phy_wrapper_n_987,u_ddr_mc_phy_wrapper_n_988,u_ddr_mc_phy_wrapper_n_989,u_ddr_mc_phy_wrapper_n_990,u_ddr_mc_phy_wrapper_n_991,u_ddr_mc_phy_wrapper_n_992,u_ddr_mc_phy_wrapper_n_993,u_ddr_mc_phy_wrapper_n_994,u_ddr_mc_phy_wrapper_n_995,u_ddr_mc_phy_wrapper_n_996,u_ddr_mc_phy_wrapper_n_997,u_ddr_mc_phy_wrapper_n_998,u_ddr_mc_phy_wrapper_n_999,u_ddr_mc_phy_wrapper_n_1000,u_ddr_mc_phy_wrapper_n_1001,u_ddr_mc_phy_wrapper_n_1002,u_ddr_mc_phy_wrapper_n_1003,u_ddr_mc_phy_wrapper_n_1004,u_ddr_mc_phy_wrapper_n_1005,u_ddr_mc_phy_wrapper_n_1006,u_ddr_mc_phy_wrapper_n_1007,u_ddr_mc_phy_wrapper_n_1008,u_ddr_mc_phy_wrapper_n_1009,u_ddr_mc_phy_wrapper_n_1010,u_ddr_mc_phy_wrapper_n_1011,u_ddr_mc_phy_wrapper_n_1012,u_ddr_mc_phy_wrapper_n_1013,u_ddr_mc_phy_wrapper_n_1014,u_ddr_mc_phy_wrapper_n_1015,u_ddr_mc_phy_wrapper_n_1016,u_ddr_mc_phy_wrapper_n_1017,u_ddr_mc_phy_wrapper_n_1018,u_ddr_mc_phy_wrapper_n_1019,u_ddr_mc_phy_wrapper_n_1020,u_ddr_mc_phy_wrapper_n_1021,u_ddr_mc_phy_wrapper_n_1022,u_ddr_mc_phy_wrapper_n_1023,u_ddr_mc_phy_wrapper_n_1024,u_ddr_mc_phy_wrapper_n_1025,u_ddr_mc_phy_wrapper_n_1026,u_ddr_mc_phy_wrapper_n_1027,u_ddr_mc_phy_wrapper_n_1028,u_ddr_mc_phy_wrapper_n_1029,u_ddr_mc_phy_wrapper_n_1030,u_ddr_mc_phy_wrapper_n_1031,u_ddr_mc_phy_wrapper_n_1032,u_ddr_mc_phy_wrapper_n_1033,u_ddr_mc_phy_wrapper_n_1034,u_ddr_mc_phy_wrapper_n_1035,u_ddr_mc_phy_wrapper_n_1036,u_ddr_mc_phy_wrapper_n_1037,u_ddr_mc_phy_wrapper_n_1038,u_ddr_mc_phy_wrapper_n_1039,u_ddr_mc_phy_wrapper_n_1040,u_ddr_mc_phy_wrapper_n_1041,u_ddr_mc_phy_wrapper_n_1042,u_ddr_mc_phy_wrapper_n_1043,u_ddr_mc_phy_wrapper_n_1044,u_ddr_mc_phy_wrapper_n_1045,u_ddr_mc_phy_wrapper_n_1046,u_ddr_mc_phy_wrapper_n_1047,u_ddr_mc_phy_wrapper_n_1048,u_ddr_mc_phy_wrapper_n_1049}),
        .out_fifo_5(u_ddr_mc_phy_wrapper_n_66),
        .out_fifo_6({u_ddr_mc_phy_wrapper_n_1050,u_ddr_mc_phy_wrapper_n_1051,u_ddr_mc_phy_wrapper_n_1052,u_ddr_mc_phy_wrapper_n_1053,u_ddr_mc_phy_wrapper_n_1054,u_ddr_mc_phy_wrapper_n_1055,u_ddr_mc_phy_wrapper_n_1056,u_ddr_mc_phy_wrapper_n_1057,u_ddr_mc_phy_wrapper_n_1058,u_ddr_mc_phy_wrapper_n_1059,u_ddr_mc_phy_wrapper_n_1060,u_ddr_mc_phy_wrapper_n_1061,u_ddr_mc_phy_wrapper_n_1062,u_ddr_mc_phy_wrapper_n_1063,u_ddr_mc_phy_wrapper_n_1064,u_ddr_mc_phy_wrapper_n_1065,u_ddr_mc_phy_wrapper_n_1066,u_ddr_mc_phy_wrapper_n_1067,u_ddr_mc_phy_wrapper_n_1068,u_ddr_mc_phy_wrapper_n_1069,u_ddr_mc_phy_wrapper_n_1070,u_ddr_mc_phy_wrapper_n_1071,u_ddr_mc_phy_wrapper_n_1072,u_ddr_mc_phy_wrapper_n_1073,u_ddr_mc_phy_wrapper_n_1074,u_ddr_mc_phy_wrapper_n_1075,u_ddr_mc_phy_wrapper_n_1076,u_ddr_mc_phy_wrapper_n_1077,u_ddr_mc_phy_wrapper_n_1078,u_ddr_mc_phy_wrapper_n_1079,u_ddr_mc_phy_wrapper_n_1080,u_ddr_mc_phy_wrapper_n_1081,u_ddr_mc_phy_wrapper_n_1082,u_ddr_mc_phy_wrapper_n_1083,u_ddr_mc_phy_wrapper_n_1084,u_ddr_mc_phy_wrapper_n_1085,u_ddr_mc_phy_wrapper_n_1086,u_ddr_mc_phy_wrapper_n_1087,u_ddr_mc_phy_wrapper_n_1088,u_ddr_mc_phy_wrapper_n_1089,u_ddr_mc_phy_wrapper_n_1090,u_ddr_mc_phy_wrapper_n_1091,u_ddr_mc_phy_wrapper_n_1092,u_ddr_mc_phy_wrapper_n_1093,u_ddr_mc_phy_wrapper_n_1094,u_ddr_mc_phy_wrapper_n_1095,u_ddr_mc_phy_wrapper_n_1096,u_ddr_mc_phy_wrapper_n_1097,u_ddr_mc_phy_wrapper_n_1098,u_ddr_mc_phy_wrapper_n_1099,u_ddr_mc_phy_wrapper_n_1100,u_ddr_mc_phy_wrapper_n_1101,u_ddr_mc_phy_wrapper_n_1102,u_ddr_mc_phy_wrapper_n_1103,u_ddr_mc_phy_wrapper_n_1104,u_ddr_mc_phy_wrapper_n_1105,u_ddr_mc_phy_wrapper_n_1106,u_ddr_mc_phy_wrapper_n_1107,u_ddr_mc_phy_wrapper_n_1108,u_ddr_mc_phy_wrapper_n_1109,u_ddr_mc_phy_wrapper_n_1110,u_ddr_mc_phy_wrapper_n_1111,u_ddr_mc_phy_wrapper_n_1112,u_ddr_mc_phy_wrapper_n_1113}),
        .out_fifo_7(u_ddr_mc_phy_wrapper_n_67),
        .out_fifo_8({u_ddr_mc_phy_wrapper_n_1114,u_ddr_mc_phy_wrapper_n_1115,u_ddr_mc_phy_wrapper_n_1116,u_ddr_mc_phy_wrapper_n_1117,u_ddr_mc_phy_wrapper_n_1118,u_ddr_mc_phy_wrapper_n_1119,u_ddr_mc_phy_wrapper_n_1120,u_ddr_mc_phy_wrapper_n_1121,u_ddr_mc_phy_wrapper_n_1122,u_ddr_mc_phy_wrapper_n_1123,u_ddr_mc_phy_wrapper_n_1124,u_ddr_mc_phy_wrapper_n_1125,u_ddr_mc_phy_wrapper_n_1126,u_ddr_mc_phy_wrapper_n_1127,u_ddr_mc_phy_wrapper_n_1128,u_ddr_mc_phy_wrapper_n_1129,u_ddr_mc_phy_wrapper_n_1130,u_ddr_mc_phy_wrapper_n_1131,u_ddr_mc_phy_wrapper_n_1132,u_ddr_mc_phy_wrapper_n_1133,u_ddr_mc_phy_wrapper_n_1134,u_ddr_mc_phy_wrapper_n_1135,u_ddr_mc_phy_wrapper_n_1136,u_ddr_mc_phy_wrapper_n_1137,u_ddr_mc_phy_wrapper_n_1138,u_ddr_mc_phy_wrapper_n_1139,u_ddr_mc_phy_wrapper_n_1140,u_ddr_mc_phy_wrapper_n_1141,u_ddr_mc_phy_wrapper_n_1142,u_ddr_mc_phy_wrapper_n_1143,u_ddr_mc_phy_wrapper_n_1144,u_ddr_mc_phy_wrapper_n_1145,u_ddr_mc_phy_wrapper_n_1146,u_ddr_mc_phy_wrapper_n_1147,u_ddr_mc_phy_wrapper_n_1148,u_ddr_mc_phy_wrapper_n_1149,u_ddr_mc_phy_wrapper_n_1150,u_ddr_mc_phy_wrapper_n_1151,u_ddr_mc_phy_wrapper_n_1152,u_ddr_mc_phy_wrapper_n_1153,u_ddr_mc_phy_wrapper_n_1154,u_ddr_mc_phy_wrapper_n_1155,u_ddr_mc_phy_wrapper_n_1156,u_ddr_mc_phy_wrapper_n_1157,u_ddr_mc_phy_wrapper_n_1158,u_ddr_mc_phy_wrapper_n_1159,u_ddr_mc_phy_wrapper_n_1160,u_ddr_mc_phy_wrapper_n_1161,u_ddr_mc_phy_wrapper_n_1162,u_ddr_mc_phy_wrapper_n_1163,u_ddr_mc_phy_wrapper_n_1164,u_ddr_mc_phy_wrapper_n_1165,u_ddr_mc_phy_wrapper_n_1166,u_ddr_mc_phy_wrapper_n_1167,u_ddr_mc_phy_wrapper_n_1168,u_ddr_mc_phy_wrapper_n_1169,u_ddr_mc_phy_wrapper_n_1170,u_ddr_mc_phy_wrapper_n_1171,u_ddr_mc_phy_wrapper_n_1172,u_ddr_mc_phy_wrapper_n_1173,u_ddr_mc_phy_wrapper_n_1174,u_ddr_mc_phy_wrapper_n_1175,u_ddr_mc_phy_wrapper_n_1176,u_ddr_mc_phy_wrapper_n_1177}),
        .out_fifo_9(u_ddr_mc_phy_wrapper_n_68),
        .p_0_out(\u_ddr_phy_wrcal/p_0_out ),
        .phy_cmd_wr_en(phy_cmd_wr_en),
        .\phy_ctl_wd_i1_reg[17] (\phy_ctl_wd_i1_reg[17] ),
        .\phy_ctl_wd_i1_reg[18] (\phy_ctl_wd_i1_reg[18] ),
        .\phy_ctl_wd_i1_reg[19] (\phy_ctl_wd_i1_reg[19] ),
        .\phy_ctl_wd_i1_reg[21] (\phy_ctl_wd_i1_reg[21] ),
        .\phy_ctl_wd_i1_reg[22] (\phy_ctl_wd_i1_reg[22] ),
        .phy_data_wr_en(phy_data_wr_en),
        .phy_dout({mux_address[48],mux_address[34],mux_address[20],mux_address[6],mux_address[44],mux_address[30],mux_address[16],mux_address[2],mux_bank[9],mux_bank[6],mux_bank[3],mux_bank[0],mux_bank[10],mux_bank[7],mux_bank[4],mux_bank[1],mux_bank[11],mux_bank[8],mux_bank[5],mux_bank[2],mux_address[50],mux_address[36],mux_address[22],mux_address[8]}),
        .phy_if_reset(phy_if_reset),
        .phy_rddata_en(phy_rddata_en),
        .phy_read_calib(phy_read_calib),
        .phy_write_calib(phy_write_calib),
        .pi_cnt_dec_reg(pi_cnt_dec_reg),
        .pi_counter_load_en(pi_counter_load_en),
        .pi_counter_load_val(pi_counter_load_val),
        .\pi_dqs_found_lanes_r1_reg[0] (pi_fine_inc),
        .\pi_dqs_found_lanes_r1_reg[0]_0 (pi_counter_load_en),
        .\pi_dqs_found_lanes_r1_reg[0]_1 (pi_counter_load_val),
        .pi_fine_enable(pi_fine_enable),
        .pi_fine_inc(pi_fine_inc),
        .pi_phase_locked_all_r1_reg(u_ddr_mc_phy_wrapper_n_64),
        .pi_rst_dqs_find(pi_rst_dqs_find),
        .\pi_rst_stg1_cal_r_reg[1] (\pi_rst_stg1_cal_r_reg[1] ),
        .\pi_rst_stg1_cal_reg[0] (u_ddr_calib_top_n_708),
        .\pi_rst_stg1_cal_reg[2] (u_ddr_calib_top_n_740),
        .pi_stg2_load_reg(u_ddr_calib_top_n_711),
        .pi_stg2_load_reg_0(u_ddr_calib_top_n_743),
        .\pi_stg2_reg_l_reg[5] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_pi_counter_load_val ),
        .\pi_stg2_reg_l_reg[5]_0 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/D_pi_counter_load_val ),
        .po_cnt_dec_2(po_cnt_dec_2),
        .po_cnt_dec_reg(po_cnt_dec_reg),
        .po_en_stg2_f_reg(po_en_stg2_f_reg),
        .\po_rdval_cnt_reg[0] (u_ddr_mc_phy_wrapper_n_1285),
        .\po_rdval_cnt_reg[1] (u_ddr_mc_phy_wrapper_n_1286),
        .\po_rdval_cnt_reg[2] (u_ddr_mc_phy_wrapper_n_1287),
        .\po_rdval_cnt_reg[3] (u_ddr_mc_phy_wrapper_n_1288),
        .\po_rdval_cnt_reg[4] (u_ddr_mc_phy_wrapper_n_1289),
        .\po_rdval_cnt_reg[5] (u_ddr_mc_phy_wrapper_n_1290),
        .\po_rdval_cnt_reg[6] (u_ddr_mc_phy_wrapper_n_1291),
        .\po_rdval_cnt_reg[7] (u_ddr_mc_phy_wrapper_n_1292),
        .\po_rdval_cnt_reg[8] (u_ddr_mc_phy_wrapper_n_1293),
        .\po_stg2_wrcal_cnt_reg[2] (po_stg2_wrcal_cnt),
        .prbs_rdlvl_done_pulse_reg(prbs_rdlvl_done_pulse_reg),
        .\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0] (\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0] ),
        .\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] (\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] ),
        .\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] (\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] ),
        .\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6] (\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6] ),
        .\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][12] (\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][12] ),
        .\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17] (\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17] ),
        .\rd_mux_sel_r_reg[1] ({u_ddr_calib_top_n_65,u_ddr_calib_top_n_66}),
        .\rd_mux_sel_r_reg[2] (u_ddr_calib_top_n_64),
        .\rd_mux_sel_r_reg[2]_0 (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl/rd_mux_sel_r ),
        .\rdlvl_cpt_tap_cnt_reg[5] (\u_ddr_mc_phy/pi_counter_read_val_w[2]_3 ),
        .\rdlvl_cpt_tap_cnt_reg[5]_0 (\u_ddr_mc_phy/pi_counter_read_val_w[0]_1 ),
        .\rdlvl_dqs_tap_cnt_r_reg[0][0][2] (\rdlvl_dqs_tap_cnt_r_reg[0][0][2] ),
        .rdlvl_stg1_start_reg(rdlvl_stg1_start_reg),
        .\read_fifo.tail_r (\read_fifo.tail_r ),
        .\read_fifo.tail_r_reg[0] (\read_fifo.tail_r_reg[0] ),
        .samp_edge_cnt0_en_r(samp_edge_cnt0_en_r),
        .\samp_edge_cnt1_r_reg[0] (\samp_edge_cnt1_r_reg[0] ),
        .\samples_cnt_r_reg[0] (\samples_cnt_r_reg[0] ),
        .\tap_cnt_cpt_r_reg[5] (\tap_cnt_cpt_r_reg[5] ),
        .\victim_sel_reg[0] (\victim_sel_reg[0] ),
        .\wait_cnt_r_reg[0] (\wait_cnt_r_reg[0] ),
        .\wait_cnt_r_reg[0]_0 (\wait_cnt_r_reg[0]_0 ),
        .\wl_dqs_tap_count_r_reg[0][5][5] (\wl_dqs_tap_count_r_reg[0][5][5] ),
        .\write_buffer.wr_buf_out_data_reg[448] (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1 ),
        .\write_buffer.wr_buf_out_data_reg[450] (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d3 ),
        .\write_buffer.wr_buf_out_data_reg[451] (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d4 ),
        .\write_buffer.wr_buf_out_data_reg[452] (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d5 ),
        .\write_buffer.wr_buf_out_data_reg[453] (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d6 ),
        .\write_buffer.wr_buf_out_data_reg[454] (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d7 ),
        .\write_buffer.wr_buf_out_data_reg[455] ({mux_wrdata[455],mux_wrdata[391],mux_wrdata[327],mux_wrdata[263],mux_wrdata[199],mux_wrdata[135],mux_wrdata[71],mux_wrdata[7],mux_wrdata[454],mux_wrdata[390],mux_wrdata[326],mux_wrdata[262],mux_wrdata[198],mux_wrdata[134],mux_wrdata[70],mux_wrdata[6],mux_wrdata[453],mux_wrdata[389],mux_wrdata[325],mux_wrdata[261],mux_wrdata[197],mux_wrdata[133],mux_wrdata[69],mux_wrdata[5],mux_wrdata[452],mux_wrdata[388],mux_wrdata[324],mux_wrdata[260],mux_wrdata[196],mux_wrdata[132],mux_wrdata[68],mux_wrdata[4],mux_wrdata[451],mux_wrdata[387],mux_wrdata[323],mux_wrdata[259],mux_wrdata[195],mux_wrdata[131],mux_wrdata[67],mux_wrdata[3],mux_wrdata[450],mux_wrdata[386],mux_wrdata[322],mux_wrdata[258],mux_wrdata[194],mux_wrdata[130],mux_wrdata[66],mux_wrdata[2],mux_wrdata[449],mux_wrdata[385],mux_wrdata[321],mux_wrdata[257],mux_wrdata[193],mux_wrdata[129],mux_wrdata[65],mux_wrdata[1],mux_wrdata[448],mux_wrdata[384],mux_wrdata[320],mux_wrdata[256],mux_wrdata[192],mux_wrdata[128],mux_wrdata[64],mux_wrdata[0],mux_wrdata_mask[56],mux_wrdata_mask[48],mux_wrdata_mask[40],mux_wrdata_mask[32],mux_wrdata_mask[24],mux_wrdata_mask[16],mux_wrdata_mask[8],mux_wrdata_mask[0]}),
        .\write_buffer.wr_buf_out_data_reg[455]_0 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d9 ),
        .\write_buffer.wr_buf_out_data_reg[456] (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d2 ),
        .\write_buffer.wr_buf_out_data_reg[457] (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d3 ),
        .\write_buffer.wr_buf_out_data_reg[458] (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d4 ),
        .\write_buffer.wr_buf_out_data_reg[459] (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d5 ),
        .\write_buffer.wr_buf_out_data_reg[460] (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6 ),
        .\write_buffer.wr_buf_out_data_reg[461] (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d7 ),
        .\write_buffer.wr_buf_out_data_reg[462] (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d8 ),
        .\write_buffer.wr_buf_out_data_reg[463] ({mux_wrdata[463],mux_wrdata[399],mux_wrdata[335],mux_wrdata[271],mux_wrdata[207],mux_wrdata[143],mux_wrdata[79],mux_wrdata[15],mux_wrdata[462],mux_wrdata[398],mux_wrdata[334],mux_wrdata[270],mux_wrdata[206],mux_wrdata[142],mux_wrdata[78],mux_wrdata[14],mux_wrdata[461],mux_wrdata[397],mux_wrdata[333],mux_wrdata[269],mux_wrdata[205],mux_wrdata[141],mux_wrdata[77],mux_wrdata[13],mux_wrdata[460],mux_wrdata[396],mux_wrdata[332],mux_wrdata[268],mux_wrdata[204],mux_wrdata[140],mux_wrdata[76],mux_wrdata[12],mux_wrdata[459],mux_wrdata[395],mux_wrdata[331],mux_wrdata[267],mux_wrdata[203],mux_wrdata[139],mux_wrdata[75],mux_wrdata[11],mux_wrdata[458],mux_wrdata[394],mux_wrdata[330],mux_wrdata[266],mux_wrdata[202],mux_wrdata[138],mux_wrdata[74],mux_wrdata[10],mux_wrdata[457],mux_wrdata[393],mux_wrdata[329],mux_wrdata[265],mux_wrdata[201],mux_wrdata[137],mux_wrdata[73],mux_wrdata[9],mux_wrdata[456],mux_wrdata[392],mux_wrdata[328],mux_wrdata[264],mux_wrdata[200],mux_wrdata[136],mux_wrdata[72],mux_wrdata[8],mux_wrdata_mask[57],mux_wrdata_mask[49],mux_wrdata_mask[41],mux_wrdata_mask[33],mux_wrdata_mask[25],mux_wrdata_mask[17],mux_wrdata_mask[9],mux_wrdata_mask[1]}),
        .\write_buffer.wr_buf_out_data_reg[463]_0 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d9 ),
        .\write_buffer.wr_buf_out_data_reg[464] (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2 ),
        .\write_buffer.wr_buf_out_data_reg[465] (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d3 ),
        .\write_buffer.wr_buf_out_data_reg[466] (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d4 ),
        .\write_buffer.wr_buf_out_data_reg[467] (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5 ),
        .\write_buffer.wr_buf_out_data_reg[468] (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6 ),
        .\write_buffer.wr_buf_out_data_reg[469] (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7 ),
        .\write_buffer.wr_buf_out_data_reg[470] (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d8 ),
        .\write_buffer.wr_buf_out_data_reg[471] ({mux_wrdata[471],mux_wrdata[407],mux_wrdata[343],mux_wrdata[279],mux_wrdata[215],mux_wrdata[151],mux_wrdata[87],mux_wrdata[23],mux_wrdata[470],mux_wrdata[406],mux_wrdata[342],mux_wrdata[278],mux_wrdata[214],mux_wrdata[150],mux_wrdata[86],mux_wrdata[22],mux_wrdata[469],mux_wrdata[405],mux_wrdata[341],mux_wrdata[277],mux_wrdata[213],mux_wrdata[149],mux_wrdata[85],mux_wrdata[21],mux_wrdata[468],mux_wrdata[404],mux_wrdata[340],mux_wrdata[276],mux_wrdata[212],mux_wrdata[148],mux_wrdata[84],mux_wrdata[20],mux_wrdata[467],mux_wrdata[403],mux_wrdata[339],mux_wrdata[275],mux_wrdata[211],mux_wrdata[147],mux_wrdata[83],mux_wrdata[19],mux_wrdata[466],mux_wrdata[402],mux_wrdata[338],mux_wrdata[274],mux_wrdata[210],mux_wrdata[146],mux_wrdata[82],mux_wrdata[18],mux_wrdata[465],mux_wrdata[401],mux_wrdata[337],mux_wrdata[273],mux_wrdata[209],mux_wrdata[145],mux_wrdata[81],mux_wrdata[17],mux_wrdata[464],mux_wrdata[400],mux_wrdata[336],mux_wrdata[272],mux_wrdata[208],mux_wrdata[144],mux_wrdata[80],mux_wrdata[16],mux_wrdata_mask[58],mux_wrdata_mask[50],mux_wrdata_mask[42],mux_wrdata_mask[34],mux_wrdata_mask[26],mux_wrdata_mask[18],mux_wrdata_mask[10],mux_wrdata_mask[2]}),
        .\write_buffer.wr_buf_out_data_reg[471]_0 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d9 ),
        .\write_buffer.wr_buf_out_data_reg[472] (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d2 ),
        .\write_buffer.wr_buf_out_data_reg[473] (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d3 ),
        .\write_buffer.wr_buf_out_data_reg[474] (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d4 ),
        .\write_buffer.wr_buf_out_data_reg[475] (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d5 ),
        .\write_buffer.wr_buf_out_data_reg[476] (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d6 ),
        .\write_buffer.wr_buf_out_data_reg[477] (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d7 ),
        .\write_buffer.wr_buf_out_data_reg[478] (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d8 ),
        .\write_buffer.wr_buf_out_data_reg[479] ({mux_wrdata[479],mux_wrdata[415],mux_wrdata[351],mux_wrdata[287],mux_wrdata[223],mux_wrdata[159],mux_wrdata[95],mux_wrdata[31],mux_wrdata[478],mux_wrdata[414],mux_wrdata[350],mux_wrdata[286],mux_wrdata[222],mux_wrdata[158],mux_wrdata[94],mux_wrdata[30],mux_wrdata[477],mux_wrdata[413],mux_wrdata[349],mux_wrdata[285],mux_wrdata[221],mux_wrdata[157],mux_wrdata[93],mux_wrdata[29],mux_wrdata[476],mux_wrdata[412],mux_wrdata[348],mux_wrdata[284],mux_wrdata[220],mux_wrdata[156],mux_wrdata[92],mux_wrdata[28],mux_wrdata[475],mux_wrdata[411],mux_wrdata[347],mux_wrdata[283],mux_wrdata[219],mux_wrdata[155],mux_wrdata[91],mux_wrdata[27],mux_wrdata[474],mux_wrdata[410],mux_wrdata[346],mux_wrdata[282],mux_wrdata[218],mux_wrdata[154],mux_wrdata[90],mux_wrdata[26],mux_wrdata[473],mux_wrdata[409],mux_wrdata[345],mux_wrdata[281],mux_wrdata[217],mux_wrdata[153],mux_wrdata[89],mux_wrdata[25],mux_wrdata[472],mux_wrdata[408],mux_wrdata[344],mux_wrdata[280],mux_wrdata[216],mux_wrdata[152],mux_wrdata[88],mux_wrdata[24],mux_wrdata_mask[59],mux_wrdata_mask[51],mux_wrdata_mask[43],mux_wrdata_mask[35],mux_wrdata_mask[27],mux_wrdata_mask[19],mux_wrdata_mask[11],mux_wrdata_mask[3]}),
        .\write_buffer.wr_buf_out_data_reg[479]_0 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d9 ),
        .\write_buffer.wr_buf_out_data_reg[480] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1 ),
        .\write_buffer.wr_buf_out_data_reg[481] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d2 ),
        .\write_buffer.wr_buf_out_data_reg[482] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d3 ),
        .\write_buffer.wr_buf_out_data_reg[483] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d4 ),
        .\write_buffer.wr_buf_out_data_reg[484] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d5 ),
        .\write_buffer.wr_buf_out_data_reg[485] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d6 ),
        .\write_buffer.wr_buf_out_data_reg[486] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d7 ),
        .\write_buffer.wr_buf_out_data_reg[487] ({mux_wrdata[487],mux_wrdata[423],mux_wrdata[359],mux_wrdata[295],mux_wrdata[231],mux_wrdata[167],mux_wrdata[103],mux_wrdata[39],mux_wrdata[486],mux_wrdata[422],mux_wrdata[358],mux_wrdata[294],mux_wrdata[230],mux_wrdata[166],mux_wrdata[102],mux_wrdata[38],mux_wrdata[485],mux_wrdata[421],mux_wrdata[357],mux_wrdata[293],mux_wrdata[229],mux_wrdata[165],mux_wrdata[101],mux_wrdata[37],mux_wrdata[484],mux_wrdata[420],mux_wrdata[356],mux_wrdata[292],mux_wrdata[228],mux_wrdata[164],mux_wrdata[100],mux_wrdata[36],mux_wrdata[483],mux_wrdata[419],mux_wrdata[355],mux_wrdata[291],mux_wrdata[227],mux_wrdata[163],mux_wrdata[99],mux_wrdata[35],mux_wrdata[482],mux_wrdata[418],mux_wrdata[354],mux_wrdata[290],mux_wrdata[226],mux_wrdata[162],mux_wrdata[98],mux_wrdata[34],mux_wrdata[481],mux_wrdata[417],mux_wrdata[353],mux_wrdata[289],mux_wrdata[225],mux_wrdata[161],mux_wrdata[97],mux_wrdata[33],mux_wrdata[480],mux_wrdata[416],mux_wrdata[352],mux_wrdata[288],mux_wrdata[224],mux_wrdata[160],mux_wrdata[96],mux_wrdata[32],mux_wrdata_mask[60],mux_wrdata_mask[52],mux_wrdata_mask[44],mux_wrdata_mask[36],mux_wrdata_mask[28],mux_wrdata_mask[20],mux_wrdata_mask[12],mux_wrdata_mask[4]}),
        .\write_buffer.wr_buf_out_data_reg[487]_0 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d9 ),
        .\write_buffer.wr_buf_out_data_reg[488] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d2 ),
        .\write_buffer.wr_buf_out_data_reg[489] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d3 ),
        .\write_buffer.wr_buf_out_data_reg[490] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d4 ),
        .\write_buffer.wr_buf_out_data_reg[491] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d5 ),
        .\write_buffer.wr_buf_out_data_reg[492] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6 ),
        .\write_buffer.wr_buf_out_data_reg[493] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d7 ),
        .\write_buffer.wr_buf_out_data_reg[494] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d8 ),
        .\write_buffer.wr_buf_out_data_reg[495] ({mux_wrdata[495],mux_wrdata[431],mux_wrdata[367],mux_wrdata[303],mux_wrdata[239],mux_wrdata[175],mux_wrdata[111],mux_wrdata[47],mux_wrdata[494],mux_wrdata[430],mux_wrdata[366],mux_wrdata[302],mux_wrdata[238],mux_wrdata[174],mux_wrdata[110],mux_wrdata[46],mux_wrdata[493],mux_wrdata[429],mux_wrdata[365],mux_wrdata[301],mux_wrdata[237],mux_wrdata[173],mux_wrdata[109],mux_wrdata[45],mux_wrdata[492],mux_wrdata[428],mux_wrdata[364],mux_wrdata[300],mux_wrdata[236],mux_wrdata[172],mux_wrdata[108],mux_wrdata[44],mux_wrdata[491],mux_wrdata[427],mux_wrdata[363],mux_wrdata[299],mux_wrdata[235],mux_wrdata[171],mux_wrdata[107],mux_wrdata[43],mux_wrdata[490],mux_wrdata[426],mux_wrdata[362],mux_wrdata[298],mux_wrdata[234],mux_wrdata[170],mux_wrdata[106],mux_wrdata[42],mux_wrdata[489],mux_wrdata[425],mux_wrdata[361],mux_wrdata[297],mux_wrdata[233],mux_wrdata[169],mux_wrdata[105],mux_wrdata[41],mux_wrdata[488],mux_wrdata[424],mux_wrdata[360],mux_wrdata[296],mux_wrdata[232],mux_wrdata[168],mux_wrdata[104],mux_wrdata[40],mux_wrdata_mask[61],mux_wrdata_mask[53],mux_wrdata_mask[45],mux_wrdata_mask[37],mux_wrdata_mask[29],mux_wrdata_mask[21],mux_wrdata_mask[13],mux_wrdata_mask[5]}),
        .\write_buffer.wr_buf_out_data_reg[495]_0 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d9 ),
        .\write_buffer.wr_buf_out_data_reg[496] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2 ),
        .\write_buffer.wr_buf_out_data_reg[497] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d3 ),
        .\write_buffer.wr_buf_out_data_reg[498] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d4 ),
        .\write_buffer.wr_buf_out_data_reg[499] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5 ),
        .\write_buffer.wr_buf_out_data_reg[500] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6 ),
        .\write_buffer.wr_buf_out_data_reg[501] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7 ),
        .\write_buffer.wr_buf_out_data_reg[502] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d8 ),
        .\write_buffer.wr_buf_out_data_reg[503] ({mux_wrdata[503],mux_wrdata[439],mux_wrdata[375],mux_wrdata[311],mux_wrdata[247],mux_wrdata[183],mux_wrdata[119],mux_wrdata[55],mux_wrdata[502],mux_wrdata[438],mux_wrdata[374],mux_wrdata[310],mux_wrdata[246],mux_wrdata[182],mux_wrdata[118],mux_wrdata[54],mux_wrdata[501],mux_wrdata[437],mux_wrdata[373],mux_wrdata[309],mux_wrdata[245],mux_wrdata[181],mux_wrdata[117],mux_wrdata[53],mux_wrdata[500],mux_wrdata[436],mux_wrdata[372],mux_wrdata[308],mux_wrdata[244],mux_wrdata[180],mux_wrdata[116],mux_wrdata[52],mux_wrdata[499],mux_wrdata[435],mux_wrdata[371],mux_wrdata[307],mux_wrdata[243],mux_wrdata[179],mux_wrdata[115],mux_wrdata[51],mux_wrdata[498],mux_wrdata[434],mux_wrdata[370],mux_wrdata[306],mux_wrdata[242],mux_wrdata[178],mux_wrdata[114],mux_wrdata[50],mux_wrdata[497],mux_wrdata[433],mux_wrdata[369],mux_wrdata[305],mux_wrdata[241],mux_wrdata[177],mux_wrdata[113],mux_wrdata[49],mux_wrdata[496],mux_wrdata[432],mux_wrdata[368],mux_wrdata[304],mux_wrdata[240],mux_wrdata[176],mux_wrdata[112],mux_wrdata[48],mux_wrdata_mask[62],mux_wrdata_mask[54],mux_wrdata_mask[46],mux_wrdata_mask[38],mux_wrdata_mask[30],mux_wrdata_mask[22],mux_wrdata_mask[14],mux_wrdata_mask[6]}),
        .\write_buffer.wr_buf_out_data_reg[503]_0 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d9 ),
        .\write_buffer.wr_buf_out_data_reg[504] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d2 ),
        .\write_buffer.wr_buf_out_data_reg[505] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d3 ),
        .\write_buffer.wr_buf_out_data_reg[506] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d4 ),
        .\write_buffer.wr_buf_out_data_reg[507] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d5 ),
        .\write_buffer.wr_buf_out_data_reg[508] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d6 ),
        .\write_buffer.wr_buf_out_data_reg[509] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d7 ),
        .\write_buffer.wr_buf_out_data_reg[510] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d8 ),
        .\write_buffer.wr_buf_out_data_reg[511] ({mux_wrdata[511],mux_wrdata[447],mux_wrdata[383],mux_wrdata[319],mux_wrdata[255],mux_wrdata[191],mux_wrdata[127],mux_wrdata[63],mux_wrdata[510],mux_wrdata[446],mux_wrdata[382],mux_wrdata[318],mux_wrdata[254],mux_wrdata[190],mux_wrdata[126],mux_wrdata[62],mux_wrdata[509],mux_wrdata[445],mux_wrdata[381],mux_wrdata[317],mux_wrdata[253],mux_wrdata[189],mux_wrdata[125],mux_wrdata[61],mux_wrdata[508],mux_wrdata[444],mux_wrdata[380],mux_wrdata[316],mux_wrdata[252],mux_wrdata[188],mux_wrdata[124],mux_wrdata[60],mux_wrdata[507],mux_wrdata[443],mux_wrdata[379],mux_wrdata[315],mux_wrdata[251],mux_wrdata[187],mux_wrdata[123],mux_wrdata[59],mux_wrdata[506],mux_wrdata[442],mux_wrdata[378],mux_wrdata[314],mux_wrdata[250],mux_wrdata[186],mux_wrdata[122],mux_wrdata[58],mux_wrdata[505],mux_wrdata[441],mux_wrdata[377],mux_wrdata[313],mux_wrdata[249],mux_wrdata[185],mux_wrdata[121],mux_wrdata[57],mux_wrdata[504],mux_wrdata[440],mux_wrdata[376],mux_wrdata[312],mux_wrdata[248],mux_wrdata[184],mux_wrdata[120],mux_wrdata[56],mux_wrdata_mask[63],mux_wrdata_mask[55],mux_wrdata_mask[47],mux_wrdata_mask[39],mux_wrdata_mask[31],mux_wrdata_mask[23],mux_wrdata_mask[15],mux_wrdata_mask[7]}),
        .\write_buffer.wr_buf_out_data_reg[511]_0 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d9 ));
  mig_mig_7series_v4_2_ddr_mc_phy_wrapper u_ddr_mc_phy_wrapper
       (.A_rst_primitives_reg(A_rst_primitives_reg),
        .A_rst_primitives_reg_0(A_rst_primitives_reg_0),
        .A_rst_primitives_reg_1(A_rst_primitives_reg_1),
        .A_rst_primitives_reg_2(A_rst_primitives_reg_2),
        .A_rst_primitives_reg_3(A_rst_primitives_reg_3),
        .A_rst_primitives_reg_4(A_rst_primitives_reg_4),
        .A_rst_primitives_reg_5(A_rst_primitives_reg_5),
        .A_rst_primitives_reg_6(A_rst_primitives_reg_6),
        .A_rst_primitives_reg_7(u_ddr_mc_phy_wrapper_n_64),
        .CLKB0(CLKB0),
        .CLKB0_10(CLKB0_10),
        .CLKB0_11(CLKB0_11),
        .CLKB0_12(CLKB0_12),
        .CLKB0_13(CLKB0_13),
        .CLKB0_7(CLKB0_7),
        .CLKB0_8(CLKB0_8),
        .CLKB0_9(CLKB0_9),
        .COUNTERLOADVAL(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/A_pi_counter_load_val ),
        .C_po_coarse_enable26_out(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/C_po_coarse_enable26_out ),
        .C_po_counter_read_en38_out(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/C_po_counter_read_en38_out ),
        .C_po_fine_enable23_out(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/C_po_fine_enable23_out ),
        .C_po_fine_inc29_out(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/C_po_fine_inc29_out ),
        .D({phy_ctl_wd[24:17],phy_ctl_wd[2:0]}),
        .D1(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d1 ),
        .D2(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d2 ),
        .D3(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d3 ),
        .D4(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d4 ),
        .D5(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d5 ),
        .D6(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d6 ),
        .D7(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d7 ),
        .D8(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d8 ),
        .D9(\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d9 ),
        .LD0(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/LD0 ),
        .LD0_10(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/LD0 ),
        .LD0_11(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/LD0 ),
        .LD0_12(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/LD0 ),
        .LD0_13(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/LD0 ),
        .LD0_7(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/LD0 ),
        .LD0_8(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/LD0 ),
        .LD0_9(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/LD0 ),
        .Q(Q[575:512]),
        .RST0(RST0),
        .SR(SR),
        .calib_sel({calib_sel[4:3],calib_sel[1:0]}),
        .d_in({init_calib_complete,d_in}),
        .\data_offset_1_i1_reg[5]_0 (data_offset_1),
        .\data_offset_2_i1_reg[5]_0 (data_offset_2),
        .ddr3_addr(ddr3_addr),
        .ddr3_ba(ddr3_ba),
        .ddr3_cas_n(ddr3_cas_n),
        .ddr3_cke(ddr3_cke),
        .ddr3_cs_n(ddr3_cs_n),
        .ddr3_dm(ddr3_dm),
        .ddr3_dq(ddr3_dq),
        .ddr3_dqs_n(ddr3_dqs_n),
        .ddr3_dqs_p(ddr3_dqs_p),
        .ddr3_odt(ddr3_odt),
        .ddr3_ras_n(ddr3_ras_n),
        .ddr3_reset_n(ddr3_reset_n),
        .ddr3_we_n(ddr3_we_n),
        .ddr_ck_out(ddr_ck_out),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ),
        .\entry_cnt_reg[4] (\entry_cnt_reg[4] ),
        .freq_refclk(freq_refclk),
        .\gen_mux_rd[0].mux_rd_rise0_r1_reg[0] (\ddr_phy_prbs_rdlvl_gen.u_ddr_phy_prbs_rdlvl/rd_mux_sel_r ),
        .\gen_mux_rd[0].mux_rd_rise0_r_reg[0] ({u_ddr_calib_top_n_65,u_ddr_calib_top_n_66}),
        .\gen_mux_rd[1].mux_rd_rise0_r_reg[1] (u_ddr_calib_top_n_64),
        .\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] (po_stg2_wrcal_cnt),
        .idelay_inc(idelay_inc),
        .idelay_ld_rst(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/idelay_ld_rst ),
        .idelay_ld_rst_0(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/idelay_ld_rst ),
        .idelay_ld_rst_1(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/idelay_ld_rst ),
        .idelay_ld_rst_2(\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/idelay_ld_rst ),
        .idelay_ld_rst_3(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/idelay_ld_rst ),
        .idelay_ld_rst_4(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/ddr_byte_group_io/idelay_ld_rst ),
        .idelay_ld_rst_5(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/idelay_ld_rst ),
        .idelay_ld_rst_6(\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/ddr_byte_group_io/idelay_ld_rst ),
        .idle(idle),
        .if_empty(if_empty),
        .ififo_rst_reg(u_ddr_calib_top_n_685),
        .ififo_rst_reg_0(u_ddr_calib_top_n_696),
        .ififo_rst_reg_1(u_ddr_calib_top_n_702),
        .ififo_rst_reg_2(u_ddr_calib_top_n_708),
        .ififo_rst_reg_3(u_ddr_calib_top_n_717),
        .ififo_rst_reg_4(u_ddr_calib_top_n_728),
        .ififo_rst_reg_5(u_ddr_calib_top_n_734),
        .ififo_rst_reg_6(u_ddr_calib_top_n_740),
        .in0({u_ddr_mc_phy_wrapper_n_33,u_ddr_mc_phy_wrapper_n_34,u_ddr_mc_phy_wrapper_n_35,u_ddr_mc_phy_wrapper_n_36,u_ddr_mc_phy_wrapper_n_37,u_ddr_mc_phy_wrapper_n_38,u_ddr_mc_phy_wrapper_n_39,u_ddr_mc_phy_wrapper_n_40}),
        .\input_[9].iserdes_dq_.iserdesdq (u_ddr_calib_top_n_683),
        .\input_[9].iserdes_dq_.iserdesdq_0 (u_ddr_calib_top_n_694),
        .\input_[9].iserdes_dq_.iserdesdq_1 (u_ddr_calib_top_n_700),
        .\input_[9].iserdes_dq_.iserdesdq_2 (u_ddr_calib_top_n_706),
        .\input_[9].iserdes_dq_.iserdesdq_3 (u_ddr_calib_top_n_715),
        .\input_[9].iserdes_dq_.iserdesdq_4 (u_ddr_calib_top_n_726),
        .\input_[9].iserdes_dq_.iserdesdq_5 (u_ddr_calib_top_n_732),
        .\input_[9].iserdes_dq_.iserdesdq_6 (u_ddr_calib_top_n_738),
        .iodelay_ctrl_rdy(iodelay_ctrl_rdy),
        .\mcGo_r_reg[15] (phy_mc_go),
        .mc_address({mc_address[38],mc_address[36],mc_address[13],mc_address[11]}),
        .mc_cas_n(mc_cas_n),
        .mc_cs_n(mc_cs_n),
        .mc_ras_n({mc_ras_n[2],mc_ras_n[0]}),
        .mc_we_n({mc_we_n[2],mc_we_n[0]}),
        .mem_out({\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/mem_out [59:56],\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/mem_out [53],\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/mem_out [45],\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/mem_out [41],\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/mem_out [33],\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/mem_out [19:16]}),
        .mem_refclk(mem_refclk),
        .mmcm_ps_clk(mmcm_ps_clk),
        .mux_address({mux_address[54],mux_address[52:42],mux_address[40],mux_address[38:26],mux_address[24:14],mux_address[12],mux_address[10:0]}),
        .mux_reset_n(mux_reset_n),
        .\my_empty_reg[1] (u_ddr_mc_phy_wrapper_n_59),
        .\my_empty_reg[1]_0 (u_ddr_mc_phy_wrapper_n_61),
        .\my_empty_reg[1]_1 (u_ddr_mc_phy_wrapper_n_62),
        .\my_empty_reg[1]_2 (u_ddr_mc_phy_wrapper_n_63),
        .\my_empty_reg[1]_3 (u_ddr_mc_phy_wrapper_n_65),
        .\my_empty_reg[1]_4 (u_ddr_mc_phy_wrapper_n_66),
        .\my_empty_reg[1]_5 (u_ddr_mc_phy_wrapper_n_67),
        .\my_empty_reg[1]_6 (u_ddr_mc_phy_wrapper_n_68),
        .\my_empty_reg[1]_7 (u_ddr_mc_phy_wrapper_n_69),
        .\my_empty_reg[1]_8 (u_ddr_mc_phy_wrapper_n_70),
        .\my_empty_reg[1]_9 (u_ddr_mc_phy_wrapper_n_1360),
        .\my_empty_reg[7] (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1 ),
        .\my_empty_reg[7]_0 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d2 ),
        .\my_empty_reg[7]_1 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d3 ),
        .\my_empty_reg[7]_10 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d5 ),
        .\my_empty_reg[7]_11 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6 ),
        .\my_empty_reg[7]_12 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d7 ),
        .\my_empty_reg[7]_13 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d8 ),
        .\my_empty_reg[7]_14 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d9 ),
        .\my_empty_reg[7]_15 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2 ),
        .\my_empty_reg[7]_16 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d3 ),
        .\my_empty_reg[7]_17 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d4 ),
        .\my_empty_reg[7]_18 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5 ),
        .\my_empty_reg[7]_19 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6 ),
        .\my_empty_reg[7]_2 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d4 ),
        .\my_empty_reg[7]_20 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7 ),
        .\my_empty_reg[7]_21 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d8 ),
        .\my_empty_reg[7]_22 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d9 ),
        .\my_empty_reg[7]_23 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d2 ),
        .\my_empty_reg[7]_24 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d3 ),
        .\my_empty_reg[7]_25 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d4 ),
        .\my_empty_reg[7]_26 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d5 ),
        .\my_empty_reg[7]_27 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d6 ),
        .\my_empty_reg[7]_28 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d7 ),
        .\my_empty_reg[7]_29 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d8 ),
        .\my_empty_reg[7]_3 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d5 ),
        .\my_empty_reg[7]_30 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d9 ),
        .\my_empty_reg[7]_31 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d1 ),
        .\my_empty_reg[7]_32 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d3 ),
        .\my_empty_reg[7]_33 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d4 ),
        .\my_empty_reg[7]_34 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d5 ),
        .\my_empty_reg[7]_35 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d6 ),
        .\my_empty_reg[7]_36 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d7 ),
        .\my_empty_reg[7]_37 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d9 ),
        .\my_empty_reg[7]_38 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d2 ),
        .\my_empty_reg[7]_39 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d3 ),
        .\my_empty_reg[7]_4 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d6 ),
        .\my_empty_reg[7]_40 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d4 ),
        .\my_empty_reg[7]_41 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d5 ),
        .\my_empty_reg[7]_42 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6 ),
        .\my_empty_reg[7]_43 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d7 ),
        .\my_empty_reg[7]_44 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d8 ),
        .\my_empty_reg[7]_45 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d9 ),
        .\my_empty_reg[7]_46 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d2 ),
        .\my_empty_reg[7]_47 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d3 ),
        .\my_empty_reg[7]_48 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d4 ),
        .\my_empty_reg[7]_49 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5 ),
        .\my_empty_reg[7]_5 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d7 ),
        .\my_empty_reg[7]_50 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6 ),
        .\my_empty_reg[7]_51 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d7 ),
        .\my_empty_reg[7]_52 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d8 ),
        .\my_empty_reg[7]_53 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d9 ),
        .\my_empty_reg[7]_54 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d2 ),
        .\my_empty_reg[7]_55 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d3 ),
        .\my_empty_reg[7]_56 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d4 ),
        .\my_empty_reg[7]_57 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d5 ),
        .\my_empty_reg[7]_58 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d6 ),
        .\my_empty_reg[7]_59 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d7 ),
        .\my_empty_reg[7]_6 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/of_d9 ),
        .\my_empty_reg[7]_60 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d8 ),
        .\my_empty_reg[7]_61 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d9 ),
        .\my_empty_reg[7]_62 (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d4 ),
        .\my_empty_reg[7]_63 (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d5 ),
        .\my_empty_reg[7]_64 (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d6 ),
        .\my_empty_reg[7]_65 (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/of_d8 ),
        .\my_empty_reg[7]_7 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d2 ),
        .\my_empty_reg[7]_8 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d3 ),
        .\my_empty_reg[7]_9 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d4 ),
        .\my_full_reg[3] (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d2 ),
        .\my_full_reg[3]_0 (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d4 ),
        .\my_full_reg[3]_1 ({\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d5 [5],\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d5 [1]}),
        .\my_full_reg[3]_2 (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d6 ),
        .\my_full_reg[3]_3 (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/of_d7 ),
        .of_ctl_full_v(of_ctl_full_v),
        .out(out),
        .out_fifo(u_ddr_calib_top_n_54),
        .out_fifo_0(u_ddr_calib_top_n_53),
        .out_fifo_1(u_ddr_calib_top_n_52),
        .out_fifo_2(init_calib_complete_reg_rep__26),
        .out_fifo_i_39({mux_bank[9],mux_bank[6],mux_bank[3],mux_bank[0],mux_bank[10],mux_bank[7],mux_bank[4],mux_bank[1],mux_bank[11],mux_bank[8],mux_bank[5],mux_bank[2]}),
        .out_fifo_i_47__8({mux_cke,phy_dout[6],mux_we_n,phy_dout[5:4],mux_ras_n,phy_dout[3:2],mux_cas_n,phy_dout[1],mux_cs_n,phy_dout[0],mux_odt}),
        .out_fifo_i_75__0({mux_wrdata[455],mux_wrdata[391],mux_wrdata[327],mux_wrdata[263],mux_wrdata[199],mux_wrdata[135],mux_wrdata[71],mux_wrdata[7],mux_wrdata[454],mux_wrdata[390],mux_wrdata[326],mux_wrdata[262],mux_wrdata[198],mux_wrdata[134],mux_wrdata[70],mux_wrdata[6],mux_wrdata[453],mux_wrdata[389],mux_wrdata[325],mux_wrdata[261],mux_wrdata[197],mux_wrdata[133],mux_wrdata[69],mux_wrdata[5],mux_wrdata[452],mux_wrdata[388],mux_wrdata[324],mux_wrdata[260],mux_wrdata[196],mux_wrdata[132],mux_wrdata[68],mux_wrdata[4],mux_wrdata[451],mux_wrdata[387],mux_wrdata[323],mux_wrdata[259],mux_wrdata[195],mux_wrdata[131],mux_wrdata[67],mux_wrdata[3],mux_wrdata[450],mux_wrdata[386],mux_wrdata[322],mux_wrdata[258],mux_wrdata[194],mux_wrdata[130],mux_wrdata[66],mux_wrdata[2],mux_wrdata[449],mux_wrdata[385],mux_wrdata[321],mux_wrdata[257],mux_wrdata[193],mux_wrdata[129],mux_wrdata[65],mux_wrdata[1],mux_wrdata[448],mux_wrdata[384],mux_wrdata[320],mux_wrdata[256],mux_wrdata[192],mux_wrdata[128],mux_wrdata[64],mux_wrdata[0],mux_wrdata_mask[56],mux_wrdata_mask[48],mux_wrdata_mask[40],mux_wrdata_mask[32],mux_wrdata_mask[24],mux_wrdata_mask[16],mux_wrdata_mask[8],mux_wrdata_mask[0]}),
        .out_fifo_i_75__1({mux_wrdata[463],mux_wrdata[399],mux_wrdata[335],mux_wrdata[271],mux_wrdata[207],mux_wrdata[143],mux_wrdata[79],mux_wrdata[15],mux_wrdata[462],mux_wrdata[398],mux_wrdata[334],mux_wrdata[270],mux_wrdata[206],mux_wrdata[142],mux_wrdata[78],mux_wrdata[14],mux_wrdata[461],mux_wrdata[397],mux_wrdata[333],mux_wrdata[269],mux_wrdata[205],mux_wrdata[141],mux_wrdata[77],mux_wrdata[13],mux_wrdata[460],mux_wrdata[396],mux_wrdata[332],mux_wrdata[268],mux_wrdata[204],mux_wrdata[140],mux_wrdata[76],mux_wrdata[12],mux_wrdata[459],mux_wrdata[395],mux_wrdata[331],mux_wrdata[267],mux_wrdata[203],mux_wrdata[139],mux_wrdata[75],mux_wrdata[11],mux_wrdata[458],mux_wrdata[394],mux_wrdata[330],mux_wrdata[266],mux_wrdata[202],mux_wrdata[138],mux_wrdata[74],mux_wrdata[10],mux_wrdata[457],mux_wrdata[393],mux_wrdata[329],mux_wrdata[265],mux_wrdata[201],mux_wrdata[137],mux_wrdata[73],mux_wrdata[9],mux_wrdata[456],mux_wrdata[392],mux_wrdata[328],mux_wrdata[264],mux_wrdata[200],mux_wrdata[136],mux_wrdata[72],mux_wrdata[8],mux_wrdata_mask[57],mux_wrdata_mask[49],mux_wrdata_mask[41],mux_wrdata_mask[33],mux_wrdata_mask[25],mux_wrdata_mask[17],mux_wrdata_mask[9],mux_wrdata_mask[1]}),
        .out_fifo_i_75__2({mux_wrdata[471],mux_wrdata[407],mux_wrdata[343],mux_wrdata[279],mux_wrdata[215],mux_wrdata[151],mux_wrdata[87],mux_wrdata[23],mux_wrdata[470],mux_wrdata[406],mux_wrdata[342],mux_wrdata[278],mux_wrdata[214],mux_wrdata[150],mux_wrdata[86],mux_wrdata[22],mux_wrdata[469],mux_wrdata[405],mux_wrdata[341],mux_wrdata[277],mux_wrdata[213],mux_wrdata[149],mux_wrdata[85],mux_wrdata[21],mux_wrdata[468],mux_wrdata[404],mux_wrdata[340],mux_wrdata[276],mux_wrdata[212],mux_wrdata[148],mux_wrdata[84],mux_wrdata[20],mux_wrdata[467],mux_wrdata[403],mux_wrdata[339],mux_wrdata[275],mux_wrdata[211],mux_wrdata[147],mux_wrdata[83],mux_wrdata[19],mux_wrdata[466],mux_wrdata[402],mux_wrdata[338],mux_wrdata[274],mux_wrdata[210],mux_wrdata[146],mux_wrdata[82],mux_wrdata[18],mux_wrdata[465],mux_wrdata[401],mux_wrdata[337],mux_wrdata[273],mux_wrdata[209],mux_wrdata[145],mux_wrdata[81],mux_wrdata[17],mux_wrdata[464],mux_wrdata[400],mux_wrdata[336],mux_wrdata[272],mux_wrdata[208],mux_wrdata[144],mux_wrdata[80],mux_wrdata[16],mux_wrdata_mask[58],mux_wrdata_mask[50],mux_wrdata_mask[42],mux_wrdata_mask[34],mux_wrdata_mask[26],mux_wrdata_mask[18],mux_wrdata_mask[10],mux_wrdata_mask[2]}),
        .out_fifo_i_75__3({mux_wrdata[479],mux_wrdata[415],mux_wrdata[351],mux_wrdata[287],mux_wrdata[223],mux_wrdata[159],mux_wrdata[95],mux_wrdata[31],mux_wrdata[478],mux_wrdata[414],mux_wrdata[350],mux_wrdata[286],mux_wrdata[222],mux_wrdata[158],mux_wrdata[94],mux_wrdata[30],mux_wrdata[477],mux_wrdata[413],mux_wrdata[349],mux_wrdata[285],mux_wrdata[221],mux_wrdata[157],mux_wrdata[93],mux_wrdata[29],mux_wrdata[476],mux_wrdata[412],mux_wrdata[348],mux_wrdata[284],mux_wrdata[220],mux_wrdata[156],mux_wrdata[92],mux_wrdata[28],mux_wrdata[475],mux_wrdata[411],mux_wrdata[347],mux_wrdata[283],mux_wrdata[219],mux_wrdata[155],mux_wrdata[91],mux_wrdata[27],mux_wrdata[474],mux_wrdata[410],mux_wrdata[346],mux_wrdata[282],mux_wrdata[218],mux_wrdata[154],mux_wrdata[90],mux_wrdata[26],mux_wrdata[473],mux_wrdata[409],mux_wrdata[345],mux_wrdata[281],mux_wrdata[217],mux_wrdata[153],mux_wrdata[89],mux_wrdata[25],mux_wrdata[472],mux_wrdata[408],mux_wrdata[344],mux_wrdata[280],mux_wrdata[216],mux_wrdata[152],mux_wrdata[88],mux_wrdata[24],mux_wrdata_mask[59],mux_wrdata_mask[51],mux_wrdata_mask[43],mux_wrdata_mask[35],mux_wrdata_mask[27],mux_wrdata_mask[19],mux_wrdata_mask[11],mux_wrdata_mask[3]}),
        .out_fifo_i_75__5({mux_wrdata[495],mux_wrdata[431],mux_wrdata[367],mux_wrdata[303],mux_wrdata[239],mux_wrdata[175],mux_wrdata[111],mux_wrdata[47],mux_wrdata[494],mux_wrdata[430],mux_wrdata[366],mux_wrdata[302],mux_wrdata[238],mux_wrdata[174],mux_wrdata[110],mux_wrdata[46],mux_wrdata[493],mux_wrdata[429],mux_wrdata[365],mux_wrdata[301],mux_wrdata[237],mux_wrdata[173],mux_wrdata[109],mux_wrdata[45],mux_wrdata[492],mux_wrdata[428],mux_wrdata[364],mux_wrdata[300],mux_wrdata[236],mux_wrdata[172],mux_wrdata[108],mux_wrdata[44],mux_wrdata[491],mux_wrdata[427],mux_wrdata[363],mux_wrdata[299],mux_wrdata[235],mux_wrdata[171],mux_wrdata[107],mux_wrdata[43],mux_wrdata[490],mux_wrdata[426],mux_wrdata[362],mux_wrdata[298],mux_wrdata[234],mux_wrdata[170],mux_wrdata[106],mux_wrdata[42],mux_wrdata[489],mux_wrdata[425],mux_wrdata[361],mux_wrdata[297],mux_wrdata[233],mux_wrdata[169],mux_wrdata[105],mux_wrdata[41],mux_wrdata[488],mux_wrdata[424],mux_wrdata[360],mux_wrdata[296],mux_wrdata[232],mux_wrdata[168],mux_wrdata[104],mux_wrdata[40],mux_wrdata_mask[61],mux_wrdata_mask[53],mux_wrdata_mask[45],mux_wrdata_mask[37],mux_wrdata_mask[29],mux_wrdata_mask[21],mux_wrdata_mask[13],mux_wrdata_mask[5]}),
        .out_fifo_i_75__6({mux_wrdata[503],mux_wrdata[439],mux_wrdata[375],mux_wrdata[311],mux_wrdata[247],mux_wrdata[183],mux_wrdata[119],mux_wrdata[55],mux_wrdata[502],mux_wrdata[438],mux_wrdata[374],mux_wrdata[310],mux_wrdata[246],mux_wrdata[182],mux_wrdata[118],mux_wrdata[54],mux_wrdata[501],mux_wrdata[437],mux_wrdata[373],mux_wrdata[309],mux_wrdata[245],mux_wrdata[181],mux_wrdata[117],mux_wrdata[53],mux_wrdata[500],mux_wrdata[436],mux_wrdata[372],mux_wrdata[308],mux_wrdata[244],mux_wrdata[180],mux_wrdata[116],mux_wrdata[52],mux_wrdata[499],mux_wrdata[435],mux_wrdata[371],mux_wrdata[307],mux_wrdata[243],mux_wrdata[179],mux_wrdata[115],mux_wrdata[51],mux_wrdata[498],mux_wrdata[434],mux_wrdata[370],mux_wrdata[306],mux_wrdata[242],mux_wrdata[178],mux_wrdata[114],mux_wrdata[50],mux_wrdata[497],mux_wrdata[433],mux_wrdata[369],mux_wrdata[305],mux_wrdata[241],mux_wrdata[177],mux_wrdata[113],mux_wrdata[49],mux_wrdata[496],mux_wrdata[432],mux_wrdata[368],mux_wrdata[304],mux_wrdata[240],mux_wrdata[176],mux_wrdata[112],mux_wrdata[48],mux_wrdata_mask[62],mux_wrdata_mask[54],mux_wrdata_mask[46],mux_wrdata_mask[38],mux_wrdata_mask[30],mux_wrdata_mask[22],mux_wrdata_mask[14],mux_wrdata_mask[6]}),
        .out_fifo_i_75__7({mux_wrdata[511],mux_wrdata[447],mux_wrdata[383],mux_wrdata[319],mux_wrdata[255],mux_wrdata[191],mux_wrdata[127],mux_wrdata[63],mux_wrdata[510],mux_wrdata[446],mux_wrdata[382],mux_wrdata[318],mux_wrdata[254],mux_wrdata[190],mux_wrdata[126],mux_wrdata[62],mux_wrdata[509],mux_wrdata[445],mux_wrdata[381],mux_wrdata[317],mux_wrdata[253],mux_wrdata[189],mux_wrdata[125],mux_wrdata[61],mux_wrdata[508],mux_wrdata[444],mux_wrdata[380],mux_wrdata[316],mux_wrdata[252],mux_wrdata[188],mux_wrdata[124],mux_wrdata[60],mux_wrdata[507],mux_wrdata[443],mux_wrdata[379],mux_wrdata[315],mux_wrdata[251],mux_wrdata[187],mux_wrdata[123],mux_wrdata[59],mux_wrdata[506],mux_wrdata[442],mux_wrdata[378],mux_wrdata[314],mux_wrdata[250],mux_wrdata[186],mux_wrdata[122],mux_wrdata[58],mux_wrdata[505],mux_wrdata[441],mux_wrdata[377],mux_wrdata[313],mux_wrdata[249],mux_wrdata[185],mux_wrdata[121],mux_wrdata[57],mux_wrdata[504],mux_wrdata[440],mux_wrdata[376],mux_wrdata[312],mux_wrdata[248],mux_wrdata[184],mux_wrdata[120],mux_wrdata[56],mux_wrdata_mask[63],mux_wrdata_mask[55],mux_wrdata_mask[47],mux_wrdata_mask[39],mux_wrdata_mask[31],mux_wrdata_mask[23],mux_wrdata_mask[15],mux_wrdata_mask[7]}),
        .p_0_out(\u_ddr_phy_wrcal/p_0_out ),
        .phy_cmd_wr_en(phy_cmd_wr_en),
        .phy_data_wr_en(phy_data_wr_en),
        .phy_dout({mux_wrdata[487],mux_wrdata[423],mux_wrdata[359],mux_wrdata[295],mux_wrdata[231],mux_wrdata[167],mux_wrdata[103],mux_wrdata[39],mux_wrdata[486],mux_wrdata[422],mux_wrdata[358],mux_wrdata[294],mux_wrdata[230],mux_wrdata[166],mux_wrdata[102],mux_wrdata[38],mux_wrdata[485],mux_wrdata[421],mux_wrdata[357],mux_wrdata[293],mux_wrdata[229],mux_wrdata[165],mux_wrdata[101],mux_wrdata[37],mux_wrdata[484],mux_wrdata[420],mux_wrdata[356],mux_wrdata[292],mux_wrdata[228],mux_wrdata[164],mux_wrdata[100],mux_wrdata[36],mux_wrdata[483],mux_wrdata[419],mux_wrdata[355],mux_wrdata[291],mux_wrdata[227],mux_wrdata[163],mux_wrdata[99],mux_wrdata[35],mux_wrdata[482],mux_wrdata[418],mux_wrdata[354],mux_wrdata[290],mux_wrdata[226],mux_wrdata[162],mux_wrdata[98],mux_wrdata[34],mux_wrdata[481],mux_wrdata[417],mux_wrdata[353],mux_wrdata[289],mux_wrdata[225],mux_wrdata[161],mux_wrdata[97],mux_wrdata[33],mux_wrdata[480],mux_wrdata[416],mux_wrdata[352],mux_wrdata[288],mux_wrdata[224],mux_wrdata[160],mux_wrdata[96],mux_wrdata[32],mux_wrdata_mask[60],mux_wrdata_mask[52],mux_wrdata_mask[44],mux_wrdata_mask[36],mux_wrdata_mask[28],mux_wrdata_mask[20],mux_wrdata_mask[12],mux_wrdata_mask[4]}),
        .phy_if_reset(phy_if_reset),
        .phy_mc_ctl_full(phy_mc_ctl_full),
        .phy_mc_ctl_full_r_reg(cal2_if_reset_reg),
        .phy_mc_data_full(phy_mc_data_full),
        .phy_rddata_en(phy_rddata_en),
        .phy_read_calib(phy_read_calib),
        .phy_write_calib(phy_write_calib),
        .\pi_counter_read_val_reg[5] (\u_ddr_mc_phy/pi_counter_read_val_w[0]_1 ),
        .\pi_counter_read_val_reg[5]_0 (\u_ddr_mc_phy/pi_counter_read_val_w[2]_3 ),
        .\pi_dqs_found_lanes_r1_reg[0] (u_ddr_calib_top_n_687),
        .\pi_dqs_found_lanes_r1_reg[0]_0 (u_ddr_calib_top_n_680),
        .\pi_dqs_found_lanes_r1_reg[0]_1 (u_ddr_calib_top_n_681),
        .\pi_dqs_found_lanes_r1_reg[0]_2 (u_ddr_calib_top_n_686),
        .\pi_dqs_found_lanes_r1_reg[10] (u_ddr_calib_top_n_737),
        .\pi_dqs_found_lanes_r1_reg[10]_0 (u_ddr_calib_top_n_724),
        .\pi_dqs_found_lanes_r1_reg[10]_1 (u_ddr_calib_top_n_735),
        .\pi_dqs_found_lanes_r1_reg[10]_2 (u_ddr_calib_top_n_736),
        .\pi_dqs_found_lanes_r1_reg[10]_3 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/C_pi_counter_load_val ),
        .\pi_dqs_found_lanes_r1_reg[11] (u_ddr_calib_top_n_743),
        .\pi_dqs_found_lanes_r1_reg[11]_0 (u_ddr_calib_top_n_722),
        .\pi_dqs_found_lanes_r1_reg[11]_1 (u_ddr_calib_top_n_741),
        .\pi_dqs_found_lanes_r1_reg[11]_2 (u_ddr_calib_top_n_742),
        .\pi_dqs_found_lanes_r1_reg[11]_3 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/D_pi_counter_load_val ),
        .\pi_dqs_found_lanes_r1_reg[1] (u_ddr_calib_top_n_699),
        .\pi_dqs_found_lanes_r1_reg[1]_0 (u_ddr_calib_top_n_693),
        .\pi_dqs_found_lanes_r1_reg[1]_1 (u_ddr_calib_top_n_697),
        .\pi_dqs_found_lanes_r1_reg[1]_2 (u_ddr_calib_top_n_698),
        .\pi_dqs_found_lanes_r1_reg[1]_3 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/B_pi_counter_load_val ),
        .\pi_dqs_found_lanes_r1_reg[2] (u_ddr_calib_top_n_705),
        .\pi_dqs_found_lanes_r1_reg[2]_0 (u_ddr_calib_top_n_692),
        .\pi_dqs_found_lanes_r1_reg[2]_1 (u_ddr_calib_top_n_703),
        .\pi_dqs_found_lanes_r1_reg[2]_2 (u_ddr_calib_top_n_704),
        .\pi_dqs_found_lanes_r1_reg[2]_3 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/C_pi_counter_load_val ),
        .\pi_dqs_found_lanes_r1_reg[3] (u_ddr_calib_top_n_711),
        .\pi_dqs_found_lanes_r1_reg[3]_0 (u_ddr_calib_top_n_690),
        .\pi_dqs_found_lanes_r1_reg[3]_1 (u_ddr_calib_top_n_709),
        .\pi_dqs_found_lanes_r1_reg[3]_2 (u_ddr_calib_top_n_710),
        .\pi_dqs_found_lanes_r1_reg[3]_3 (\u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/D_pi_counter_load_val ),
        .\pi_dqs_found_lanes_r1_reg[8] (u_ddr_calib_top_n_719),
        .\pi_dqs_found_lanes_r1_reg[8]_0 (u_ddr_calib_top_n_712),
        .\pi_dqs_found_lanes_r1_reg[8]_1 (u_ddr_calib_top_n_713),
        .\pi_dqs_found_lanes_r1_reg[8]_2 (u_ddr_calib_top_n_718),
        .\pi_dqs_found_lanes_r1_reg[8]_3 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/A_pi_counter_load_val ),
        .\pi_dqs_found_lanes_r1_reg[9] (u_ddr_calib_top_n_731),
        .\pi_dqs_found_lanes_r1_reg[9]_0 (u_ddr_calib_top_n_725),
        .\pi_dqs_found_lanes_r1_reg[9]_1 (u_ddr_calib_top_n_729),
        .\pi_dqs_found_lanes_r1_reg[9]_2 (u_ddr_calib_top_n_730),
        .\pi_dqs_found_lanes_r1_reg[9]_3 (\u_ddr_mc_phy/ddr_phy_4lanes_2.u_ddr_phy_4lanes/B_pi_counter_load_val ),
        .pll_locked(pll_locked),
        .\po_counter_read_val_reg[0] (u_ddr_mc_phy_wrapper_n_1285),
        .\po_counter_read_val_reg[0]_0 (u_ddr_calib_top_n_1373),
        .\po_counter_read_val_reg[1] (u_ddr_mc_phy_wrapper_n_1286),
        .\po_counter_read_val_reg[2] (u_ddr_mc_phy_wrapper_n_1287),
        .\po_counter_read_val_reg[3] (u_ddr_mc_phy_wrapper_n_1288),
        .\po_counter_read_val_reg[4] (u_ddr_mc_phy_wrapper_n_1289),
        .\po_counter_read_val_reg[5] (u_ddr_mc_phy_wrapper_n_1290),
        .\po_counter_read_val_reg[6] (u_ddr_mc_phy_wrapper_n_1291),
        .\po_counter_read_val_reg[7] (u_ddr_mc_phy_wrapper_n_1292),
        .\po_counter_read_val_reg[8] (u_ddr_mc_phy_wrapper_n_1293),
        .\po_counter_read_val_reg[8]_0 (u_ddr_calib_top_n_745),
        .\po_counter_read_val_reg[8]_1 (u_ddr_calib_top_n_751),
        .\po_counter_read_val_reg[8]_10 (u_ddr_calib_top_n_753),
        .\po_counter_read_val_reg[8]_11 (u_ddr_calib_top_n_688),
        .\po_counter_read_val_reg[8]_12 (u_ddr_calib_top_n_695),
        .\po_counter_read_val_reg[8]_13 (u_ddr_calib_top_n_754),
        .\po_counter_read_val_reg[8]_14 (u_ddr_calib_top_n_691),
        .\po_counter_read_val_reg[8]_15 (u_ddr_calib_top_n_701),
        .\po_counter_read_val_reg[8]_16 (u_ddr_calib_top_n_755),
        .\po_counter_read_val_reg[8]_17 (u_ddr_calib_top_n_689),
        .\po_counter_read_val_reg[8]_18 (u_ddr_calib_top_n_707),
        .\po_counter_read_val_reg[8]_19 (u_ddr_calib_top_n_756),
        .\po_counter_read_val_reg[8]_2 (u_ddr_calib_top_n_748),
        .\po_counter_read_val_reg[8]_20 (u_ddr_calib_top_n_716),
        .\po_counter_read_val_reg[8]_21 (u_ddr_calib_top_n_714),
        .\po_counter_read_val_reg[8]_22 (u_ddr_calib_top_n_757),
        .\po_counter_read_val_reg[8]_23 (u_ddr_calib_top_n_720),
        .\po_counter_read_val_reg[8]_24 (u_ddr_calib_top_n_727),
        .\po_counter_read_val_reg[8]_25 (u_ddr_calib_top_n_758),
        .\po_counter_read_val_reg[8]_26 (u_ddr_calib_top_n_723),
        .\po_counter_read_val_reg[8]_27 (u_ddr_calib_top_n_733),
        .\po_counter_read_val_reg[8]_28 (u_ddr_calib_top_n_759),
        .\po_counter_read_val_reg[8]_29 (u_ddr_calib_top_n_721),
        .\po_counter_read_val_reg[8]_3 (u_ddr_calib_top_n_762),
        .\po_counter_read_val_reg[8]_30 (u_ddr_calib_top_n_739),
        .\po_counter_read_val_reg[8]_31 (u_ddr_calib_top_n_760),
        .\po_counter_read_val_reg[8]_4 (u_ddr_calib_top_n_746),
        .\po_counter_read_val_reg[8]_5 (u_ddr_calib_top_n_750),
        .\po_counter_read_val_reg[8]_6 (u_ddr_calib_top_n_749),
        .\po_counter_read_val_reg[8]_7 (u_ddr_calib_top_n_763),
        .\po_counter_read_val_reg[8]_8 (u_ddr_calib_top_n_684),
        .\po_counter_read_val_reg[8]_9 (u_ddr_calib_top_n_682),
        .\po_stg2_wrcal_cnt_reg[2] (u_ddr_mc_phy_wrapper_n_1295),
        .\po_stg2_wrcal_cnt_reg[2]_0 (u_ddr_mc_phy_wrapper_n_1296),
        .\po_stg2_wrcal_cnt_reg[2]_1 (u_ddr_mc_phy_wrapper_n_1297),
        .\po_stg2_wrcal_cnt_reg[2]_10 (u_ddr_mc_phy_wrapper_n_1306),
        .\po_stg2_wrcal_cnt_reg[2]_11 (u_ddr_mc_phy_wrapper_n_1307),
        .\po_stg2_wrcal_cnt_reg[2]_12 (u_ddr_mc_phy_wrapper_n_1308),
        .\po_stg2_wrcal_cnt_reg[2]_13 (u_ddr_mc_phy_wrapper_n_1309),
        .\po_stg2_wrcal_cnt_reg[2]_14 (u_ddr_mc_phy_wrapper_n_1310),
        .\po_stg2_wrcal_cnt_reg[2]_15 (u_ddr_mc_phy_wrapper_n_1311),
        .\po_stg2_wrcal_cnt_reg[2]_16 (u_ddr_mc_phy_wrapper_n_1312),
        .\po_stg2_wrcal_cnt_reg[2]_17 (u_ddr_mc_phy_wrapper_n_1313),
        .\po_stg2_wrcal_cnt_reg[2]_18 (u_ddr_mc_phy_wrapper_n_1314),
        .\po_stg2_wrcal_cnt_reg[2]_19 (u_ddr_mc_phy_wrapper_n_1315),
        .\po_stg2_wrcal_cnt_reg[2]_2 (u_ddr_mc_phy_wrapper_n_1298),
        .\po_stg2_wrcal_cnt_reg[2]_20 (u_ddr_mc_phy_wrapper_n_1316),
        .\po_stg2_wrcal_cnt_reg[2]_21 (u_ddr_mc_phy_wrapper_n_1317),
        .\po_stg2_wrcal_cnt_reg[2]_22 (u_ddr_mc_phy_wrapper_n_1318),
        .\po_stg2_wrcal_cnt_reg[2]_23 (u_ddr_mc_phy_wrapper_n_1319),
        .\po_stg2_wrcal_cnt_reg[2]_24 (u_ddr_mc_phy_wrapper_n_1320),
        .\po_stg2_wrcal_cnt_reg[2]_25 (u_ddr_mc_phy_wrapper_n_1321),
        .\po_stg2_wrcal_cnt_reg[2]_26 (u_ddr_mc_phy_wrapper_n_1322),
        .\po_stg2_wrcal_cnt_reg[2]_27 (u_ddr_mc_phy_wrapper_n_1323),
        .\po_stg2_wrcal_cnt_reg[2]_28 (u_ddr_mc_phy_wrapper_n_1324),
        .\po_stg2_wrcal_cnt_reg[2]_29 (u_ddr_mc_phy_wrapper_n_1325),
        .\po_stg2_wrcal_cnt_reg[2]_3 (u_ddr_mc_phy_wrapper_n_1299),
        .\po_stg2_wrcal_cnt_reg[2]_30 (u_ddr_mc_phy_wrapper_n_1326),
        .\po_stg2_wrcal_cnt_reg[2]_31 (u_ddr_mc_phy_wrapper_n_1327),
        .\po_stg2_wrcal_cnt_reg[2]_32 (u_ddr_mc_phy_wrapper_n_1328),
        .\po_stg2_wrcal_cnt_reg[2]_33 (u_ddr_mc_phy_wrapper_n_1329),
        .\po_stg2_wrcal_cnt_reg[2]_34 (u_ddr_mc_phy_wrapper_n_1330),
        .\po_stg2_wrcal_cnt_reg[2]_35 (u_ddr_mc_phy_wrapper_n_1331),
        .\po_stg2_wrcal_cnt_reg[2]_36 (u_ddr_mc_phy_wrapper_n_1332),
        .\po_stg2_wrcal_cnt_reg[2]_37 (u_ddr_mc_phy_wrapper_n_1333),
        .\po_stg2_wrcal_cnt_reg[2]_38 (u_ddr_mc_phy_wrapper_n_1334),
        .\po_stg2_wrcal_cnt_reg[2]_39 (u_ddr_mc_phy_wrapper_n_1335),
        .\po_stg2_wrcal_cnt_reg[2]_4 (u_ddr_mc_phy_wrapper_n_1300),
        .\po_stg2_wrcal_cnt_reg[2]_40 (u_ddr_mc_phy_wrapper_n_1336),
        .\po_stg2_wrcal_cnt_reg[2]_41 (u_ddr_mc_phy_wrapper_n_1337),
        .\po_stg2_wrcal_cnt_reg[2]_42 (u_ddr_mc_phy_wrapper_n_1338),
        .\po_stg2_wrcal_cnt_reg[2]_43 (u_ddr_mc_phy_wrapper_n_1339),
        .\po_stg2_wrcal_cnt_reg[2]_44 (u_ddr_mc_phy_wrapper_n_1340),
        .\po_stg2_wrcal_cnt_reg[2]_45 (u_ddr_mc_phy_wrapper_n_1341),
        .\po_stg2_wrcal_cnt_reg[2]_46 (u_ddr_mc_phy_wrapper_n_1342),
        .\po_stg2_wrcal_cnt_reg[2]_47 (u_ddr_mc_phy_wrapper_n_1343),
        .\po_stg2_wrcal_cnt_reg[2]_48 (u_ddr_mc_phy_wrapper_n_1344),
        .\po_stg2_wrcal_cnt_reg[2]_49 (u_ddr_mc_phy_wrapper_n_1345),
        .\po_stg2_wrcal_cnt_reg[2]_5 (u_ddr_mc_phy_wrapper_n_1301),
        .\po_stg2_wrcal_cnt_reg[2]_50 (u_ddr_mc_phy_wrapper_n_1346),
        .\po_stg2_wrcal_cnt_reg[2]_51 (u_ddr_mc_phy_wrapper_n_1347),
        .\po_stg2_wrcal_cnt_reg[2]_52 (u_ddr_mc_phy_wrapper_n_1348),
        .\po_stg2_wrcal_cnt_reg[2]_53 (u_ddr_mc_phy_wrapper_n_1349),
        .\po_stg2_wrcal_cnt_reg[2]_54 (u_ddr_mc_phy_wrapper_n_1350),
        .\po_stg2_wrcal_cnt_reg[2]_55 (u_ddr_mc_phy_wrapper_n_1351),
        .\po_stg2_wrcal_cnt_reg[2]_56 (u_ddr_mc_phy_wrapper_n_1352),
        .\po_stg2_wrcal_cnt_reg[2]_57 (u_ddr_mc_phy_wrapper_n_1353),
        .\po_stg2_wrcal_cnt_reg[2]_58 (u_ddr_mc_phy_wrapper_n_1354),
        .\po_stg2_wrcal_cnt_reg[2]_59 (u_ddr_mc_phy_wrapper_n_1355),
        .\po_stg2_wrcal_cnt_reg[2]_6 (u_ddr_mc_phy_wrapper_n_1302),
        .\po_stg2_wrcal_cnt_reg[2]_60 (u_ddr_mc_phy_wrapper_n_1356),
        .\po_stg2_wrcal_cnt_reg[2]_61 (u_ddr_mc_phy_wrapper_n_1357),
        .\po_stg2_wrcal_cnt_reg[2]_7 (u_ddr_mc_phy_wrapper_n_1303),
        .\po_stg2_wrcal_cnt_reg[2]_8 (u_ddr_mc_phy_wrapper_n_1304),
        .\po_stg2_wrcal_cnt_reg[2]_9 (u_ddr_mc_phy_wrapper_n_1305),
        .\rd_mux_sel_r_reg[2] (u_ddr_mc_phy_wrapper_n_595),
        .\rd_mux_sel_r_reg[2]_0 (u_ddr_mc_phy_wrapper_n_596),
        .\rd_mux_sel_r_reg[2]_1 (u_ddr_mc_phy_wrapper_n_597),
        .\rd_mux_sel_r_reg[2]_10 (u_ddr_mc_phy_wrapper_n_606),
        .\rd_mux_sel_r_reg[2]_100 (u_ddr_mc_phy_wrapper_n_1258),
        .\rd_mux_sel_r_reg[2]_101 (u_ddr_mc_phy_wrapper_n_1259),
        .\rd_mux_sel_r_reg[2]_102 (u_ddr_mc_phy_wrapper_n_1260),
        .\rd_mux_sel_r_reg[2]_103 (u_ddr_mc_phy_wrapper_n_1261),
        .\rd_mux_sel_r_reg[2]_104 (u_ddr_mc_phy_wrapper_n_1262),
        .\rd_mux_sel_r_reg[2]_105 (u_ddr_mc_phy_wrapper_n_1263),
        .\rd_mux_sel_r_reg[2]_106 (u_ddr_mc_phy_wrapper_n_1264),
        .\rd_mux_sel_r_reg[2]_107 (u_ddr_mc_phy_wrapper_n_1265),
        .\rd_mux_sel_r_reg[2]_108 (u_ddr_mc_phy_wrapper_n_1266),
        .\rd_mux_sel_r_reg[2]_109 (u_ddr_mc_phy_wrapper_n_1267),
        .\rd_mux_sel_r_reg[2]_11 (u_ddr_mc_phy_wrapper_n_607),
        .\rd_mux_sel_r_reg[2]_110 (u_ddr_mc_phy_wrapper_n_1268),
        .\rd_mux_sel_r_reg[2]_111 (u_ddr_mc_phy_wrapper_n_1269),
        .\rd_mux_sel_r_reg[2]_112 (u_ddr_mc_phy_wrapper_n_1270),
        .\rd_mux_sel_r_reg[2]_113 (u_ddr_mc_phy_wrapper_n_1271),
        .\rd_mux_sel_r_reg[2]_114 (u_ddr_mc_phy_wrapper_n_1272),
        .\rd_mux_sel_r_reg[2]_115 (u_ddr_mc_phy_wrapper_n_1273),
        .\rd_mux_sel_r_reg[2]_116 (u_ddr_mc_phy_wrapper_n_1274),
        .\rd_mux_sel_r_reg[2]_117 (u_ddr_mc_phy_wrapper_n_1275),
        .\rd_mux_sel_r_reg[2]_118 (u_ddr_mc_phy_wrapper_n_1276),
        .\rd_mux_sel_r_reg[2]_119 (u_ddr_mc_phy_wrapper_n_1277),
        .\rd_mux_sel_r_reg[2]_12 (u_ddr_mc_phy_wrapper_n_608),
        .\rd_mux_sel_r_reg[2]_120 (u_ddr_mc_phy_wrapper_n_1278),
        .\rd_mux_sel_r_reg[2]_121 (u_ddr_mc_phy_wrapper_n_1279),
        .\rd_mux_sel_r_reg[2]_122 (u_ddr_mc_phy_wrapper_n_1280),
        .\rd_mux_sel_r_reg[2]_123 (u_ddr_mc_phy_wrapper_n_1281),
        .\rd_mux_sel_r_reg[2]_124 (u_ddr_mc_phy_wrapper_n_1282),
        .\rd_mux_sel_r_reg[2]_125 (u_ddr_mc_phy_wrapper_n_1283),
        .\rd_mux_sel_r_reg[2]_126 (u_ddr_mc_phy_wrapper_n_1284),
        .\rd_mux_sel_r_reg[2]_13 (u_ddr_mc_phy_wrapper_n_609),
        .\rd_mux_sel_r_reg[2]_14 (u_ddr_mc_phy_wrapper_n_610),
        .\rd_mux_sel_r_reg[2]_15 (u_ddr_mc_phy_wrapper_n_611),
        .\rd_mux_sel_r_reg[2]_16 (u_ddr_mc_phy_wrapper_n_612),
        .\rd_mux_sel_r_reg[2]_17 (u_ddr_mc_phy_wrapper_n_613),
        .\rd_mux_sel_r_reg[2]_18 (u_ddr_mc_phy_wrapper_n_614),
        .\rd_mux_sel_r_reg[2]_19 (u_ddr_mc_phy_wrapper_n_615),
        .\rd_mux_sel_r_reg[2]_2 (u_ddr_mc_phy_wrapper_n_598),
        .\rd_mux_sel_r_reg[2]_20 (u_ddr_mc_phy_wrapper_n_616),
        .\rd_mux_sel_r_reg[2]_21 (u_ddr_mc_phy_wrapper_n_617),
        .\rd_mux_sel_r_reg[2]_22 (u_ddr_mc_phy_wrapper_n_618),
        .\rd_mux_sel_r_reg[2]_23 (u_ddr_mc_phy_wrapper_n_619),
        .\rd_mux_sel_r_reg[2]_24 (u_ddr_mc_phy_wrapper_n_620),
        .\rd_mux_sel_r_reg[2]_25 (u_ddr_mc_phy_wrapper_n_621),
        .\rd_mux_sel_r_reg[2]_26 (u_ddr_mc_phy_wrapper_n_622),
        .\rd_mux_sel_r_reg[2]_27 (u_ddr_mc_phy_wrapper_n_623),
        .\rd_mux_sel_r_reg[2]_28 (u_ddr_mc_phy_wrapper_n_624),
        .\rd_mux_sel_r_reg[2]_29 (u_ddr_mc_phy_wrapper_n_625),
        .\rd_mux_sel_r_reg[2]_3 (u_ddr_mc_phy_wrapper_n_599),
        .\rd_mux_sel_r_reg[2]_30 (u_ddr_mc_phy_wrapper_n_626),
        .\rd_mux_sel_r_reg[2]_31 (u_ddr_mc_phy_wrapper_n_627),
        .\rd_mux_sel_r_reg[2]_32 (u_ddr_mc_phy_wrapper_n_628),
        .\rd_mux_sel_r_reg[2]_33 (u_ddr_mc_phy_wrapper_n_629),
        .\rd_mux_sel_r_reg[2]_34 (u_ddr_mc_phy_wrapper_n_630),
        .\rd_mux_sel_r_reg[2]_35 (u_ddr_mc_phy_wrapper_n_631),
        .\rd_mux_sel_r_reg[2]_36 (u_ddr_mc_phy_wrapper_n_632),
        .\rd_mux_sel_r_reg[2]_37 (u_ddr_mc_phy_wrapper_n_633),
        .\rd_mux_sel_r_reg[2]_38 (u_ddr_mc_phy_wrapper_n_634),
        .\rd_mux_sel_r_reg[2]_39 (u_ddr_mc_phy_wrapper_n_635),
        .\rd_mux_sel_r_reg[2]_4 (u_ddr_mc_phy_wrapper_n_600),
        .\rd_mux_sel_r_reg[2]_40 (u_ddr_mc_phy_wrapper_n_636),
        .\rd_mux_sel_r_reg[2]_41 (u_ddr_mc_phy_wrapper_n_637),
        .\rd_mux_sel_r_reg[2]_42 (u_ddr_mc_phy_wrapper_n_638),
        .\rd_mux_sel_r_reg[2]_43 (u_ddr_mc_phy_wrapper_n_639),
        .\rd_mux_sel_r_reg[2]_44 (u_ddr_mc_phy_wrapper_n_640),
        .\rd_mux_sel_r_reg[2]_45 (u_ddr_mc_phy_wrapper_n_641),
        .\rd_mux_sel_r_reg[2]_46 (u_ddr_mc_phy_wrapper_n_642),
        .\rd_mux_sel_r_reg[2]_47 (u_ddr_mc_phy_wrapper_n_643),
        .\rd_mux_sel_r_reg[2]_48 (u_ddr_mc_phy_wrapper_n_644),
        .\rd_mux_sel_r_reg[2]_49 (u_ddr_mc_phy_wrapper_n_645),
        .\rd_mux_sel_r_reg[2]_5 (u_ddr_mc_phy_wrapper_n_601),
        .\rd_mux_sel_r_reg[2]_50 (u_ddr_mc_phy_wrapper_n_646),
        .\rd_mux_sel_r_reg[2]_51 (u_ddr_mc_phy_wrapper_n_647),
        .\rd_mux_sel_r_reg[2]_52 (u_ddr_mc_phy_wrapper_n_648),
        .\rd_mux_sel_r_reg[2]_53 (u_ddr_mc_phy_wrapper_n_649),
        .\rd_mux_sel_r_reg[2]_54 (u_ddr_mc_phy_wrapper_n_650),
        .\rd_mux_sel_r_reg[2]_55 (u_ddr_mc_phy_wrapper_n_651),
        .\rd_mux_sel_r_reg[2]_56 (u_ddr_mc_phy_wrapper_n_652),
        .\rd_mux_sel_r_reg[2]_57 (u_ddr_mc_phy_wrapper_n_653),
        .\rd_mux_sel_r_reg[2]_58 (u_ddr_mc_phy_wrapper_n_654),
        .\rd_mux_sel_r_reg[2]_59 (u_ddr_mc_phy_wrapper_n_655),
        .\rd_mux_sel_r_reg[2]_6 (u_ddr_mc_phy_wrapper_n_602),
        .\rd_mux_sel_r_reg[2]_60 (u_ddr_mc_phy_wrapper_n_656),
        .\rd_mux_sel_r_reg[2]_61 (u_ddr_mc_phy_wrapper_n_657),
        .\rd_mux_sel_r_reg[2]_62 (u_ddr_mc_phy_wrapper_n_658),
        .\rd_mux_sel_r_reg[2]_63 (u_ddr_mc_phy_wrapper_n_1221),
        .\rd_mux_sel_r_reg[2]_64 (u_ddr_mc_phy_wrapper_n_1222),
        .\rd_mux_sel_r_reg[2]_65 (u_ddr_mc_phy_wrapper_n_1223),
        .\rd_mux_sel_r_reg[2]_66 (u_ddr_mc_phy_wrapper_n_1224),
        .\rd_mux_sel_r_reg[2]_67 (u_ddr_mc_phy_wrapper_n_1225),
        .\rd_mux_sel_r_reg[2]_68 (u_ddr_mc_phy_wrapper_n_1226),
        .\rd_mux_sel_r_reg[2]_69 (u_ddr_mc_phy_wrapper_n_1227),
        .\rd_mux_sel_r_reg[2]_7 (u_ddr_mc_phy_wrapper_n_603),
        .\rd_mux_sel_r_reg[2]_70 (u_ddr_mc_phy_wrapper_n_1228),
        .\rd_mux_sel_r_reg[2]_71 (u_ddr_mc_phy_wrapper_n_1229),
        .\rd_mux_sel_r_reg[2]_72 (u_ddr_mc_phy_wrapper_n_1230),
        .\rd_mux_sel_r_reg[2]_73 (u_ddr_mc_phy_wrapper_n_1231),
        .\rd_mux_sel_r_reg[2]_74 (u_ddr_mc_phy_wrapper_n_1232),
        .\rd_mux_sel_r_reg[2]_75 (u_ddr_mc_phy_wrapper_n_1233),
        .\rd_mux_sel_r_reg[2]_76 (u_ddr_mc_phy_wrapper_n_1234),
        .\rd_mux_sel_r_reg[2]_77 (u_ddr_mc_phy_wrapper_n_1235),
        .\rd_mux_sel_r_reg[2]_78 (u_ddr_mc_phy_wrapper_n_1236),
        .\rd_mux_sel_r_reg[2]_79 (u_ddr_mc_phy_wrapper_n_1237),
        .\rd_mux_sel_r_reg[2]_8 (u_ddr_mc_phy_wrapper_n_604),
        .\rd_mux_sel_r_reg[2]_80 (u_ddr_mc_phy_wrapper_n_1238),
        .\rd_mux_sel_r_reg[2]_81 (u_ddr_mc_phy_wrapper_n_1239),
        .\rd_mux_sel_r_reg[2]_82 (u_ddr_mc_phy_wrapper_n_1240),
        .\rd_mux_sel_r_reg[2]_83 (u_ddr_mc_phy_wrapper_n_1241),
        .\rd_mux_sel_r_reg[2]_84 (u_ddr_mc_phy_wrapper_n_1242),
        .\rd_mux_sel_r_reg[2]_85 (u_ddr_mc_phy_wrapper_n_1243),
        .\rd_mux_sel_r_reg[2]_86 (u_ddr_mc_phy_wrapper_n_1244),
        .\rd_mux_sel_r_reg[2]_87 (u_ddr_mc_phy_wrapper_n_1245),
        .\rd_mux_sel_r_reg[2]_88 (u_ddr_mc_phy_wrapper_n_1246),
        .\rd_mux_sel_r_reg[2]_89 (u_ddr_mc_phy_wrapper_n_1247),
        .\rd_mux_sel_r_reg[2]_9 (u_ddr_mc_phy_wrapper_n_605),
        .\rd_mux_sel_r_reg[2]_90 (u_ddr_mc_phy_wrapper_n_1248),
        .\rd_mux_sel_r_reg[2]_91 (u_ddr_mc_phy_wrapper_n_1249),
        .\rd_mux_sel_r_reg[2]_92 (u_ddr_mc_phy_wrapper_n_1250),
        .\rd_mux_sel_r_reg[2]_93 (u_ddr_mc_phy_wrapper_n_1251),
        .\rd_mux_sel_r_reg[2]_94 (u_ddr_mc_phy_wrapper_n_1252),
        .\rd_mux_sel_r_reg[2]_95 (u_ddr_mc_phy_wrapper_n_1253),
        .\rd_mux_sel_r_reg[2]_96 (u_ddr_mc_phy_wrapper_n_1254),
        .\rd_mux_sel_r_reg[2]_97 (u_ddr_mc_phy_wrapper_n_1255),
        .\rd_mux_sel_r_reg[2]_98 (u_ddr_mc_phy_wrapper_n_1256),
        .\rd_mux_sel_r_reg[2]_99 (u_ddr_mc_phy_wrapper_n_1257),
        .\rd_ptr_reg[3] ({u_ddr_mc_phy_wrapper_n_660,u_ddr_mc_phy_wrapper_n_661,u_ddr_mc_phy_wrapper_n_662,u_ddr_mc_phy_wrapper_n_663,u_ddr_mc_phy_wrapper_n_664,u_ddr_mc_phy_wrapper_n_665,u_ddr_mc_phy_wrapper_n_666,u_ddr_mc_phy_wrapper_n_667,u_ddr_mc_phy_wrapper_n_668,u_ddr_mc_phy_wrapper_n_669,u_ddr_mc_phy_wrapper_n_670,u_ddr_mc_phy_wrapper_n_671,u_ddr_mc_phy_wrapper_n_672,u_ddr_mc_phy_wrapper_n_673,u_ddr_mc_phy_wrapper_n_674,u_ddr_mc_phy_wrapper_n_675,u_ddr_mc_phy_wrapper_n_676,u_ddr_mc_phy_wrapper_n_677,u_ddr_mc_phy_wrapper_n_678,u_ddr_mc_phy_wrapper_n_679,u_ddr_mc_phy_wrapper_n_680,u_ddr_mc_phy_wrapper_n_681,u_ddr_mc_phy_wrapper_n_682,u_ddr_mc_phy_wrapper_n_683,u_ddr_mc_phy_wrapper_n_684,u_ddr_mc_phy_wrapper_n_685,u_ddr_mc_phy_wrapper_n_686,u_ddr_mc_phy_wrapper_n_687,u_ddr_mc_phy_wrapper_n_688,u_ddr_mc_phy_wrapper_n_689,u_ddr_mc_phy_wrapper_n_690,u_ddr_mc_phy_wrapper_n_691,u_ddr_mc_phy_wrapper_n_692,u_ddr_mc_phy_wrapper_n_693,u_ddr_mc_phy_wrapper_n_694,u_ddr_mc_phy_wrapper_n_695,u_ddr_mc_phy_wrapper_n_696,u_ddr_mc_phy_wrapper_n_697,u_ddr_mc_phy_wrapper_n_698,u_ddr_mc_phy_wrapper_n_699,u_ddr_mc_phy_wrapper_n_700,u_ddr_mc_phy_wrapper_n_701,u_ddr_mc_phy_wrapper_n_702,u_ddr_mc_phy_wrapper_n_703,u_ddr_mc_phy_wrapper_n_704,u_ddr_mc_phy_wrapper_n_705,u_ddr_mc_phy_wrapper_n_706,u_ddr_mc_phy_wrapper_n_707,u_ddr_mc_phy_wrapper_n_708,u_ddr_mc_phy_wrapper_n_709,u_ddr_mc_phy_wrapper_n_710,u_ddr_mc_phy_wrapper_n_711,u_ddr_mc_phy_wrapper_n_712,u_ddr_mc_phy_wrapper_n_713,u_ddr_mc_phy_wrapper_n_714,u_ddr_mc_phy_wrapper_n_715,u_ddr_mc_phy_wrapper_n_716,u_ddr_mc_phy_wrapper_n_717,u_ddr_mc_phy_wrapper_n_718,u_ddr_mc_phy_wrapper_n_719,u_ddr_mc_phy_wrapper_n_720,u_ddr_mc_phy_wrapper_n_721,u_ddr_mc_phy_wrapper_n_722,u_ddr_mc_phy_wrapper_n_723}),
        .\rd_ptr_reg[3]_0 ({u_ddr_mc_phy_wrapper_n_724,u_ddr_mc_phy_wrapper_n_725,u_ddr_mc_phy_wrapper_n_726,u_ddr_mc_phy_wrapper_n_727,u_ddr_mc_phy_wrapper_n_728,u_ddr_mc_phy_wrapper_n_729,u_ddr_mc_phy_wrapper_n_730,u_ddr_mc_phy_wrapper_n_731,u_ddr_mc_phy_wrapper_n_732,u_ddr_mc_phy_wrapper_n_733,u_ddr_mc_phy_wrapper_n_734,u_ddr_mc_phy_wrapper_n_735,u_ddr_mc_phy_wrapper_n_736,u_ddr_mc_phy_wrapper_n_737,u_ddr_mc_phy_wrapper_n_738,u_ddr_mc_phy_wrapper_n_739,u_ddr_mc_phy_wrapper_n_740,u_ddr_mc_phy_wrapper_n_741,u_ddr_mc_phy_wrapper_n_742,u_ddr_mc_phy_wrapper_n_743,u_ddr_mc_phy_wrapper_n_744,u_ddr_mc_phy_wrapper_n_745,u_ddr_mc_phy_wrapper_n_746,u_ddr_mc_phy_wrapper_n_747,u_ddr_mc_phy_wrapper_n_748,u_ddr_mc_phy_wrapper_n_749,u_ddr_mc_phy_wrapper_n_750,u_ddr_mc_phy_wrapper_n_751,u_ddr_mc_phy_wrapper_n_752,u_ddr_mc_phy_wrapper_n_753,u_ddr_mc_phy_wrapper_n_754,u_ddr_mc_phy_wrapper_n_755,u_ddr_mc_phy_wrapper_n_756,u_ddr_mc_phy_wrapper_n_757,u_ddr_mc_phy_wrapper_n_758,u_ddr_mc_phy_wrapper_n_759,u_ddr_mc_phy_wrapper_n_760,u_ddr_mc_phy_wrapper_n_761,u_ddr_mc_phy_wrapper_n_762,u_ddr_mc_phy_wrapper_n_763,u_ddr_mc_phy_wrapper_n_764,u_ddr_mc_phy_wrapper_n_765,u_ddr_mc_phy_wrapper_n_766,u_ddr_mc_phy_wrapper_n_767,u_ddr_mc_phy_wrapper_n_768,u_ddr_mc_phy_wrapper_n_769,u_ddr_mc_phy_wrapper_n_770,u_ddr_mc_phy_wrapper_n_771,u_ddr_mc_phy_wrapper_n_772,u_ddr_mc_phy_wrapper_n_773,u_ddr_mc_phy_wrapper_n_774,u_ddr_mc_phy_wrapper_n_775,u_ddr_mc_phy_wrapper_n_776,u_ddr_mc_phy_wrapper_n_777,u_ddr_mc_phy_wrapper_n_778,u_ddr_mc_phy_wrapper_n_779,u_ddr_mc_phy_wrapper_n_780,u_ddr_mc_phy_wrapper_n_781,u_ddr_mc_phy_wrapper_n_782,u_ddr_mc_phy_wrapper_n_783,u_ddr_mc_phy_wrapper_n_784,u_ddr_mc_phy_wrapper_n_785,u_ddr_mc_phy_wrapper_n_786,u_ddr_mc_phy_wrapper_n_787}),
        .\rd_ptr_reg[3]_1 ({u_ddr_mc_phy_wrapper_n_788,u_ddr_mc_phy_wrapper_n_789,u_ddr_mc_phy_wrapper_n_790,u_ddr_mc_phy_wrapper_n_791,u_ddr_mc_phy_wrapper_n_792,u_ddr_mc_phy_wrapper_n_793,u_ddr_mc_phy_wrapper_n_794,u_ddr_mc_phy_wrapper_n_795,u_ddr_mc_phy_wrapper_n_796,u_ddr_mc_phy_wrapper_n_797,u_ddr_mc_phy_wrapper_n_798,u_ddr_mc_phy_wrapper_n_799,u_ddr_mc_phy_wrapper_n_800,u_ddr_mc_phy_wrapper_n_801,u_ddr_mc_phy_wrapper_n_802,u_ddr_mc_phy_wrapper_n_803,u_ddr_mc_phy_wrapper_n_804,u_ddr_mc_phy_wrapper_n_805,u_ddr_mc_phy_wrapper_n_806,u_ddr_mc_phy_wrapper_n_807,u_ddr_mc_phy_wrapper_n_808,u_ddr_mc_phy_wrapper_n_809,u_ddr_mc_phy_wrapper_n_810,u_ddr_mc_phy_wrapper_n_811,u_ddr_mc_phy_wrapper_n_812,u_ddr_mc_phy_wrapper_n_813,u_ddr_mc_phy_wrapper_n_814,u_ddr_mc_phy_wrapper_n_815,u_ddr_mc_phy_wrapper_n_816,u_ddr_mc_phy_wrapper_n_817,u_ddr_mc_phy_wrapper_n_818,u_ddr_mc_phy_wrapper_n_819,u_ddr_mc_phy_wrapper_n_820,u_ddr_mc_phy_wrapper_n_821,u_ddr_mc_phy_wrapper_n_822,u_ddr_mc_phy_wrapper_n_823,u_ddr_mc_phy_wrapper_n_824,u_ddr_mc_phy_wrapper_n_825,u_ddr_mc_phy_wrapper_n_826,u_ddr_mc_phy_wrapper_n_827,u_ddr_mc_phy_wrapper_n_828,u_ddr_mc_phy_wrapper_n_829,u_ddr_mc_phy_wrapper_n_830,u_ddr_mc_phy_wrapper_n_831,u_ddr_mc_phy_wrapper_n_832,u_ddr_mc_phy_wrapper_n_833,u_ddr_mc_phy_wrapper_n_834,u_ddr_mc_phy_wrapper_n_835,u_ddr_mc_phy_wrapper_n_836,u_ddr_mc_phy_wrapper_n_837,u_ddr_mc_phy_wrapper_n_838,u_ddr_mc_phy_wrapper_n_839,u_ddr_mc_phy_wrapper_n_840,u_ddr_mc_phy_wrapper_n_841,u_ddr_mc_phy_wrapper_n_842,u_ddr_mc_phy_wrapper_n_843,u_ddr_mc_phy_wrapper_n_844,u_ddr_mc_phy_wrapper_n_845,u_ddr_mc_phy_wrapper_n_846,u_ddr_mc_phy_wrapper_n_847,u_ddr_mc_phy_wrapper_n_848,u_ddr_mc_phy_wrapper_n_849,u_ddr_mc_phy_wrapper_n_850,u_ddr_mc_phy_wrapper_n_851}),
        .\rd_ptr_reg[3]_2 ({u_ddr_mc_phy_wrapper_n_852,u_ddr_mc_phy_wrapper_n_853,u_ddr_mc_phy_wrapper_n_854,u_ddr_mc_phy_wrapper_n_855,u_ddr_mc_phy_wrapper_n_856,u_ddr_mc_phy_wrapper_n_857,u_ddr_mc_phy_wrapper_n_858,u_ddr_mc_phy_wrapper_n_859,u_ddr_mc_phy_wrapper_n_860,u_ddr_mc_phy_wrapper_n_861,u_ddr_mc_phy_wrapper_n_862,u_ddr_mc_phy_wrapper_n_863,u_ddr_mc_phy_wrapper_n_864,u_ddr_mc_phy_wrapper_n_865,u_ddr_mc_phy_wrapper_n_866,u_ddr_mc_phy_wrapper_n_867,u_ddr_mc_phy_wrapper_n_868,u_ddr_mc_phy_wrapper_n_869,u_ddr_mc_phy_wrapper_n_870,u_ddr_mc_phy_wrapper_n_871,u_ddr_mc_phy_wrapper_n_872,u_ddr_mc_phy_wrapper_n_873,u_ddr_mc_phy_wrapper_n_874,u_ddr_mc_phy_wrapper_n_875,u_ddr_mc_phy_wrapper_n_876,u_ddr_mc_phy_wrapper_n_877,u_ddr_mc_phy_wrapper_n_878,u_ddr_mc_phy_wrapper_n_879,u_ddr_mc_phy_wrapper_n_880,u_ddr_mc_phy_wrapper_n_881,u_ddr_mc_phy_wrapper_n_882,u_ddr_mc_phy_wrapper_n_883,u_ddr_mc_phy_wrapper_n_884,u_ddr_mc_phy_wrapper_n_885,u_ddr_mc_phy_wrapper_n_886,u_ddr_mc_phy_wrapper_n_887,u_ddr_mc_phy_wrapper_n_888,u_ddr_mc_phy_wrapper_n_889,u_ddr_mc_phy_wrapper_n_890,u_ddr_mc_phy_wrapper_n_891,u_ddr_mc_phy_wrapper_n_892,u_ddr_mc_phy_wrapper_n_893,u_ddr_mc_phy_wrapper_n_894,u_ddr_mc_phy_wrapper_n_895,u_ddr_mc_phy_wrapper_n_896,u_ddr_mc_phy_wrapper_n_897,u_ddr_mc_phy_wrapper_n_898,u_ddr_mc_phy_wrapper_n_899,u_ddr_mc_phy_wrapper_n_900,u_ddr_mc_phy_wrapper_n_901,u_ddr_mc_phy_wrapper_n_902,u_ddr_mc_phy_wrapper_n_903,u_ddr_mc_phy_wrapper_n_904,u_ddr_mc_phy_wrapper_n_905,u_ddr_mc_phy_wrapper_n_906,u_ddr_mc_phy_wrapper_n_907,u_ddr_mc_phy_wrapper_n_908,u_ddr_mc_phy_wrapper_n_909,u_ddr_mc_phy_wrapper_n_910,u_ddr_mc_phy_wrapper_n_911,u_ddr_mc_phy_wrapper_n_912,u_ddr_mc_phy_wrapper_n_913,u_ddr_mc_phy_wrapper_n_914,u_ddr_mc_phy_wrapper_n_915}),
        .\rd_ptr_reg[3]_3 ({u_ddr_mc_phy_wrapper_n_922,u_ddr_mc_phy_wrapper_n_923,u_ddr_mc_phy_wrapper_n_924,u_ddr_mc_phy_wrapper_n_925,u_ddr_mc_phy_wrapper_n_926,u_ddr_mc_phy_wrapper_n_927,u_ddr_mc_phy_wrapper_n_928,u_ddr_mc_phy_wrapper_n_929,u_ddr_mc_phy_wrapper_n_930,u_ddr_mc_phy_wrapper_n_931,u_ddr_mc_phy_wrapper_n_932,u_ddr_mc_phy_wrapper_n_933,u_ddr_mc_phy_wrapper_n_934,u_ddr_mc_phy_wrapper_n_935,u_ddr_mc_phy_wrapper_n_936,u_ddr_mc_phy_wrapper_n_937,u_ddr_mc_phy_wrapper_n_938,u_ddr_mc_phy_wrapper_n_939,u_ddr_mc_phy_wrapper_n_940,u_ddr_mc_phy_wrapper_n_941,u_ddr_mc_phy_wrapper_n_942,u_ddr_mc_phy_wrapper_n_943,u_ddr_mc_phy_wrapper_n_944,u_ddr_mc_phy_wrapper_n_945,u_ddr_mc_phy_wrapper_n_946,u_ddr_mc_phy_wrapper_n_947,u_ddr_mc_phy_wrapper_n_948,u_ddr_mc_phy_wrapper_n_949,u_ddr_mc_phy_wrapper_n_950,u_ddr_mc_phy_wrapper_n_951,u_ddr_mc_phy_wrapper_n_952,u_ddr_mc_phy_wrapper_n_953,u_ddr_mc_phy_wrapper_n_954,u_ddr_mc_phy_wrapper_n_955,u_ddr_mc_phy_wrapper_n_956,u_ddr_mc_phy_wrapper_n_957,u_ddr_mc_phy_wrapper_n_958,u_ddr_mc_phy_wrapper_n_959,u_ddr_mc_phy_wrapper_n_960,u_ddr_mc_phy_wrapper_n_961,u_ddr_mc_phy_wrapper_n_962,u_ddr_mc_phy_wrapper_n_963,u_ddr_mc_phy_wrapper_n_964,u_ddr_mc_phy_wrapper_n_965,u_ddr_mc_phy_wrapper_n_966,u_ddr_mc_phy_wrapper_n_967,u_ddr_mc_phy_wrapper_n_968,u_ddr_mc_phy_wrapper_n_969,u_ddr_mc_phy_wrapper_n_970,u_ddr_mc_phy_wrapper_n_971,u_ddr_mc_phy_wrapper_n_972,u_ddr_mc_phy_wrapper_n_973,u_ddr_mc_phy_wrapper_n_974,u_ddr_mc_phy_wrapper_n_975,u_ddr_mc_phy_wrapper_n_976,u_ddr_mc_phy_wrapper_n_977,u_ddr_mc_phy_wrapper_n_978,u_ddr_mc_phy_wrapper_n_979,u_ddr_mc_phy_wrapper_n_980,u_ddr_mc_phy_wrapper_n_981,u_ddr_mc_phy_wrapper_n_982,u_ddr_mc_phy_wrapper_n_983,u_ddr_mc_phy_wrapper_n_984,u_ddr_mc_phy_wrapper_n_985}),
        .\rd_ptr_reg[3]_4 ({u_ddr_mc_phy_wrapper_n_986,u_ddr_mc_phy_wrapper_n_987,u_ddr_mc_phy_wrapper_n_988,u_ddr_mc_phy_wrapper_n_989,u_ddr_mc_phy_wrapper_n_990,u_ddr_mc_phy_wrapper_n_991,u_ddr_mc_phy_wrapper_n_992,u_ddr_mc_phy_wrapper_n_993,u_ddr_mc_phy_wrapper_n_994,u_ddr_mc_phy_wrapper_n_995,u_ddr_mc_phy_wrapper_n_996,u_ddr_mc_phy_wrapper_n_997,u_ddr_mc_phy_wrapper_n_998,u_ddr_mc_phy_wrapper_n_999,u_ddr_mc_phy_wrapper_n_1000,u_ddr_mc_phy_wrapper_n_1001,u_ddr_mc_phy_wrapper_n_1002,u_ddr_mc_phy_wrapper_n_1003,u_ddr_mc_phy_wrapper_n_1004,u_ddr_mc_phy_wrapper_n_1005,u_ddr_mc_phy_wrapper_n_1006,u_ddr_mc_phy_wrapper_n_1007,u_ddr_mc_phy_wrapper_n_1008,u_ddr_mc_phy_wrapper_n_1009,u_ddr_mc_phy_wrapper_n_1010,u_ddr_mc_phy_wrapper_n_1011,u_ddr_mc_phy_wrapper_n_1012,u_ddr_mc_phy_wrapper_n_1013,u_ddr_mc_phy_wrapper_n_1014,u_ddr_mc_phy_wrapper_n_1015,u_ddr_mc_phy_wrapper_n_1016,u_ddr_mc_phy_wrapper_n_1017,u_ddr_mc_phy_wrapper_n_1018,u_ddr_mc_phy_wrapper_n_1019,u_ddr_mc_phy_wrapper_n_1020,u_ddr_mc_phy_wrapper_n_1021,u_ddr_mc_phy_wrapper_n_1022,u_ddr_mc_phy_wrapper_n_1023,u_ddr_mc_phy_wrapper_n_1024,u_ddr_mc_phy_wrapper_n_1025,u_ddr_mc_phy_wrapper_n_1026,u_ddr_mc_phy_wrapper_n_1027,u_ddr_mc_phy_wrapper_n_1028,u_ddr_mc_phy_wrapper_n_1029,u_ddr_mc_phy_wrapper_n_1030,u_ddr_mc_phy_wrapper_n_1031,u_ddr_mc_phy_wrapper_n_1032,u_ddr_mc_phy_wrapper_n_1033,u_ddr_mc_phy_wrapper_n_1034,u_ddr_mc_phy_wrapper_n_1035,u_ddr_mc_phy_wrapper_n_1036,u_ddr_mc_phy_wrapper_n_1037,u_ddr_mc_phy_wrapper_n_1038,u_ddr_mc_phy_wrapper_n_1039,u_ddr_mc_phy_wrapper_n_1040,u_ddr_mc_phy_wrapper_n_1041,u_ddr_mc_phy_wrapper_n_1042,u_ddr_mc_phy_wrapper_n_1043,u_ddr_mc_phy_wrapper_n_1044,u_ddr_mc_phy_wrapper_n_1045,u_ddr_mc_phy_wrapper_n_1046,u_ddr_mc_phy_wrapper_n_1047,u_ddr_mc_phy_wrapper_n_1048,u_ddr_mc_phy_wrapper_n_1049}),
        .\rd_ptr_reg[3]_5 ({u_ddr_mc_phy_wrapper_n_1050,u_ddr_mc_phy_wrapper_n_1051,u_ddr_mc_phy_wrapper_n_1052,u_ddr_mc_phy_wrapper_n_1053,u_ddr_mc_phy_wrapper_n_1054,u_ddr_mc_phy_wrapper_n_1055,u_ddr_mc_phy_wrapper_n_1056,u_ddr_mc_phy_wrapper_n_1057,u_ddr_mc_phy_wrapper_n_1058,u_ddr_mc_phy_wrapper_n_1059,u_ddr_mc_phy_wrapper_n_1060,u_ddr_mc_phy_wrapper_n_1061,u_ddr_mc_phy_wrapper_n_1062,u_ddr_mc_phy_wrapper_n_1063,u_ddr_mc_phy_wrapper_n_1064,u_ddr_mc_phy_wrapper_n_1065,u_ddr_mc_phy_wrapper_n_1066,u_ddr_mc_phy_wrapper_n_1067,u_ddr_mc_phy_wrapper_n_1068,u_ddr_mc_phy_wrapper_n_1069,u_ddr_mc_phy_wrapper_n_1070,u_ddr_mc_phy_wrapper_n_1071,u_ddr_mc_phy_wrapper_n_1072,u_ddr_mc_phy_wrapper_n_1073,u_ddr_mc_phy_wrapper_n_1074,u_ddr_mc_phy_wrapper_n_1075,u_ddr_mc_phy_wrapper_n_1076,u_ddr_mc_phy_wrapper_n_1077,u_ddr_mc_phy_wrapper_n_1078,u_ddr_mc_phy_wrapper_n_1079,u_ddr_mc_phy_wrapper_n_1080,u_ddr_mc_phy_wrapper_n_1081,u_ddr_mc_phy_wrapper_n_1082,u_ddr_mc_phy_wrapper_n_1083,u_ddr_mc_phy_wrapper_n_1084,u_ddr_mc_phy_wrapper_n_1085,u_ddr_mc_phy_wrapper_n_1086,u_ddr_mc_phy_wrapper_n_1087,u_ddr_mc_phy_wrapper_n_1088,u_ddr_mc_phy_wrapper_n_1089,u_ddr_mc_phy_wrapper_n_1090,u_ddr_mc_phy_wrapper_n_1091,u_ddr_mc_phy_wrapper_n_1092,u_ddr_mc_phy_wrapper_n_1093,u_ddr_mc_phy_wrapper_n_1094,u_ddr_mc_phy_wrapper_n_1095,u_ddr_mc_phy_wrapper_n_1096,u_ddr_mc_phy_wrapper_n_1097,u_ddr_mc_phy_wrapper_n_1098,u_ddr_mc_phy_wrapper_n_1099,u_ddr_mc_phy_wrapper_n_1100,u_ddr_mc_phy_wrapper_n_1101,u_ddr_mc_phy_wrapper_n_1102,u_ddr_mc_phy_wrapper_n_1103,u_ddr_mc_phy_wrapper_n_1104,u_ddr_mc_phy_wrapper_n_1105,u_ddr_mc_phy_wrapper_n_1106,u_ddr_mc_phy_wrapper_n_1107,u_ddr_mc_phy_wrapper_n_1108,u_ddr_mc_phy_wrapper_n_1109,u_ddr_mc_phy_wrapper_n_1110,u_ddr_mc_phy_wrapper_n_1111,u_ddr_mc_phy_wrapper_n_1112,u_ddr_mc_phy_wrapper_n_1113}),
        .\rd_ptr_reg[3]_6 ({u_ddr_mc_phy_wrapper_n_1114,u_ddr_mc_phy_wrapper_n_1115,u_ddr_mc_phy_wrapper_n_1116,u_ddr_mc_phy_wrapper_n_1117,u_ddr_mc_phy_wrapper_n_1118,u_ddr_mc_phy_wrapper_n_1119,u_ddr_mc_phy_wrapper_n_1120,u_ddr_mc_phy_wrapper_n_1121,u_ddr_mc_phy_wrapper_n_1122,u_ddr_mc_phy_wrapper_n_1123,u_ddr_mc_phy_wrapper_n_1124,u_ddr_mc_phy_wrapper_n_1125,u_ddr_mc_phy_wrapper_n_1126,u_ddr_mc_phy_wrapper_n_1127,u_ddr_mc_phy_wrapper_n_1128,u_ddr_mc_phy_wrapper_n_1129,u_ddr_mc_phy_wrapper_n_1130,u_ddr_mc_phy_wrapper_n_1131,u_ddr_mc_phy_wrapper_n_1132,u_ddr_mc_phy_wrapper_n_1133,u_ddr_mc_phy_wrapper_n_1134,u_ddr_mc_phy_wrapper_n_1135,u_ddr_mc_phy_wrapper_n_1136,u_ddr_mc_phy_wrapper_n_1137,u_ddr_mc_phy_wrapper_n_1138,u_ddr_mc_phy_wrapper_n_1139,u_ddr_mc_phy_wrapper_n_1140,u_ddr_mc_phy_wrapper_n_1141,u_ddr_mc_phy_wrapper_n_1142,u_ddr_mc_phy_wrapper_n_1143,u_ddr_mc_phy_wrapper_n_1144,u_ddr_mc_phy_wrapper_n_1145,u_ddr_mc_phy_wrapper_n_1146,u_ddr_mc_phy_wrapper_n_1147,u_ddr_mc_phy_wrapper_n_1148,u_ddr_mc_phy_wrapper_n_1149,u_ddr_mc_phy_wrapper_n_1150,u_ddr_mc_phy_wrapper_n_1151,u_ddr_mc_phy_wrapper_n_1152,u_ddr_mc_phy_wrapper_n_1153,u_ddr_mc_phy_wrapper_n_1154,u_ddr_mc_phy_wrapper_n_1155,u_ddr_mc_phy_wrapper_n_1156,u_ddr_mc_phy_wrapper_n_1157,u_ddr_mc_phy_wrapper_n_1158,u_ddr_mc_phy_wrapper_n_1159,u_ddr_mc_phy_wrapper_n_1160,u_ddr_mc_phy_wrapper_n_1161,u_ddr_mc_phy_wrapper_n_1162,u_ddr_mc_phy_wrapper_n_1163,u_ddr_mc_phy_wrapper_n_1164,u_ddr_mc_phy_wrapper_n_1165,u_ddr_mc_phy_wrapper_n_1166,u_ddr_mc_phy_wrapper_n_1167,u_ddr_mc_phy_wrapper_n_1168,u_ddr_mc_phy_wrapper_n_1169,u_ddr_mc_phy_wrapper_n_1170,u_ddr_mc_phy_wrapper_n_1171,u_ddr_mc_phy_wrapper_n_1172,u_ddr_mc_phy_wrapper_n_1173,u_ddr_mc_phy_wrapper_n_1174,u_ddr_mc_phy_wrapper_n_1175,u_ddr_mc_phy_wrapper_n_1176,u_ddr_mc_phy_wrapper_n_1177}),
        .\rd_ptr_reg[3]_7 ({u_ddr_mc_phy_wrapper_n_1184,u_ddr_mc_phy_wrapper_n_1185,u_ddr_mc_phy_wrapper_n_1186,u_ddr_mc_phy_wrapper_n_1187,u_ddr_mc_phy_wrapper_n_1188,u_ddr_mc_phy_wrapper_n_1189,u_ddr_mc_phy_wrapper_n_1190,u_ddr_mc_phy_wrapper_n_1191,u_ddr_mc_phy_wrapper_n_1192,u_ddr_mc_phy_wrapper_n_1193,u_ddr_mc_phy_wrapper_n_1194,u_ddr_mc_phy_wrapper_n_1195,u_ddr_mc_phy_wrapper_n_1196,u_ddr_mc_phy_wrapper_n_1197,u_ddr_mc_phy_wrapper_n_1198,u_ddr_mc_phy_wrapper_n_1199,u_ddr_mc_phy_wrapper_n_1200,u_ddr_mc_phy_wrapper_n_1201,u_ddr_mc_phy_wrapper_n_1202,u_ddr_mc_phy_wrapper_n_1203,u_ddr_mc_phy_wrapper_n_1204,u_ddr_mc_phy_wrapper_n_1205,u_ddr_mc_phy_wrapper_n_1206,u_ddr_mc_phy_wrapper_n_1207,u_ddr_mc_phy_wrapper_n_1208,u_ddr_mc_phy_wrapper_n_1209,u_ddr_mc_phy_wrapper_n_1210,u_ddr_mc_phy_wrapper_n_1211,u_ddr_mc_phy_wrapper_n_1212,u_ddr_mc_phy_wrapper_n_1213,u_ddr_mc_phy_wrapper_n_1214,u_ddr_mc_phy_wrapper_n_1215,u_ddr_mc_phy_wrapper_n_1216,u_ddr_mc_phy_wrapper_n_1217,u_ddr_mc_phy_wrapper_n_1218,u_ddr_mc_phy_wrapper_n_1219}),
        .\rd_ptr_reg[3]_8 ({\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [75:72],\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [67:64],\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [55:52],\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [47:40],\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/mem_out [35:32]}),
        .\rd_ptr_reg[3]_9 (\u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/of_d9 ),
        .rst_sync_r1(rst_sync_r1),
        .rst_tmp(rst_tmp),
        .\rstdiv2_sync_r_reg[11] (\rstdiv2_sync_r_reg[11] ),
        .sync_pulse(sync_pulse));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_phy_wrcal" *) 
module mig_mig_7series_v4_2_ddr_phy_wrcal
   (wrcal_resume_w,
    E,
    wrcal_prech_req,
    wrcal_done_reg_0,
    wrcal_sanity_chk_done_reg_0,
    wrlvl_byte_redo,
    early1_data_reg_0,
    phy_if_reset_w,
    \po_stg2_wrcal_cnt_reg[3]_0 ,
    done_dqs_dec238_out,
    Q,
    LD0,
    LD0_0,
    LD0_1,
    LD0_2,
    LD0_3,
    LD0_4,
    LD0_5,
    LD0_6,
    wrcal_done_reg_1,
    \po_stg2_wrcal_cnt_reg[2]_0 ,
    early1_data_reg_1,
    \po_stg2_wrcal_cnt_reg[0]_0 ,
    \po_stg2_wrcal_cnt_reg[1]_0 ,
    \po_stg2_wrcal_cnt_reg[0]_1 ,
    \po_stg2_wrcal_cnt_reg[0]_2 ,
    \po_stg2_wrcal_cnt_reg[0]_3 ,
    \po_stg2_wrcal_cnt_reg[0]_4 ,
    \po_stg2_wrcal_cnt_reg[0]_5 ,
    \po_stg2_wrcal_cnt_reg[0]_6 ,
    \po_stg2_wrcal_cnt_reg[1]_1 ,
    \po_stg2_wrcal_cnt_reg[0]_7 ,
    \po_stg2_wrcal_cnt_reg[0]_8 ,
    \po_stg2_wrcal_cnt_reg[1]_2 ,
    wrcal_done_reg_2,
    wrcal_done_reg_3,
    wrlvl_byte_redo_reg_0,
    wrcal_done_reg_4,
    wrcal_pat_resume_reg_0,
    phy_rddata_en,
    wrcal_sanity_chk,
    p_0_out,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0 ,
    \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ,
    cal2_if_reset_reg_0,
    cal2_done_r_reg_0,
    wrlvl_byte_done,
    \corse_cnt[0][2]_i_3 ,
    \corse_cnt[0][2]_i_3_0 ,
    idelay_ce_int,
    \input_[9].iserdes_dq_.idelay_dq.idelaye2 ,
    calib_in_common,
    \input_[9].iserdes_dq_.idelay_dq.idelaye2_0 ,
    \input_[9].iserdes_dq_.idelay_dq.idelaye2_1 ,
    idelay_ld_rst,
    idelay_ld_rst_7,
    idelay_ld_rst_8,
    idelay_ld_rst_9,
    idelay_ld_rst_10,
    idelay_ld_rst_11,
    idelay_ld_rst_12,
    idelay_ld_rst_13,
    wrlvl_byte_redo_r,
    \wrlvl_redo_corse_inc[2]_i_7 ,
    \wrlvl_redo_corse_inc[2]_i_7_0 ,
    \idelay_tap_cnt_r_reg[0][4][4] ,
    \idelay_tap_cnt_r_reg[0][4][4]_0 ,
    \idelay_tap_cnt_r_reg[0][4][4]_1 ,
    \idelay_tap_cnt_r_reg[0][0][4] ,
    \idelay_tap_cnt_r_reg[0][0][4]_0 ,
    \idelay_tap_cnt_r_reg[0][5][4] ,
    \idelay_tap_cnt_r_reg[0][5][4]_0 ,
    \idelay_tap_cnt_r_reg[0][6][4] ,
    \idelay_tap_cnt_r_reg[0][7][4] ,
    \idelay_tap_cnt_r_reg[0][1][4] ,
    \idelay_tap_cnt_r_reg[0][2][4] ,
    \init_state_r[3]_i_13 ,
    wrlvl_done_r1,
    \init_state_r[2]_i_14 ,
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[508] ,
    \init_state_r[3]_i_13_0 ,
    \init_state_r[4]_i_27 ,
    \not_empty_wait_cnt_reg[4]_0 ,
    wrcal_rd_wait,
    prech_done,
    \cal2_state_r_reg[0]_0 );
  output wrcal_resume_w;
  output [0:0]E;
  output wrcal_prech_req;
  output wrcal_done_reg_0;
  output wrcal_sanity_chk_done_reg_0;
  output wrlvl_byte_redo;
  output early1_data_reg_0;
  output phy_if_reset_w;
  output \po_stg2_wrcal_cnt_reg[3]_0 ;
  output done_dqs_dec238_out;
  output [3:0]Q;
  output LD0;
  output LD0_0;
  output LD0_1;
  output LD0_2;
  output LD0_3;
  output LD0_4;
  output LD0_5;
  output LD0_6;
  output wrcal_done_reg_1;
  output \po_stg2_wrcal_cnt_reg[2]_0 ;
  output early1_data_reg_1;
  output \po_stg2_wrcal_cnt_reg[0]_0 ;
  output \po_stg2_wrcal_cnt_reg[1]_0 ;
  output \po_stg2_wrcal_cnt_reg[0]_1 ;
  output \po_stg2_wrcal_cnt_reg[0]_2 ;
  output [0:0]\po_stg2_wrcal_cnt_reg[0]_3 ;
  output [0:0]\po_stg2_wrcal_cnt_reg[0]_4 ;
  output [0:0]\po_stg2_wrcal_cnt_reg[0]_5 ;
  output [0:0]\po_stg2_wrcal_cnt_reg[0]_6 ;
  output [0:0]\po_stg2_wrcal_cnt_reg[1]_1 ;
  output [0:0]\po_stg2_wrcal_cnt_reg[0]_7 ;
  output [0:0]\po_stg2_wrcal_cnt_reg[0]_8 ;
  output [0:0]\po_stg2_wrcal_cnt_reg[1]_2 ;
  output wrcal_done_reg_2;
  output wrcal_done_reg_3;
  output wrlvl_byte_redo_reg_0;
  output wrcal_done_reg_4;
  input wrcal_pat_resume_reg_0;
  input phy_rddata_en;
  input wrcal_sanity_chk;
  input p_0_out;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0 ;
  input \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ;
  input cal2_if_reset_reg_0;
  input [0:0]cal2_done_r_reg_0;
  input wrlvl_byte_done;
  input [1:0]\corse_cnt[0][2]_i_3 ;
  input \corse_cnt[0][2]_i_3_0 ;
  input idelay_ce_int;
  input [1:0]\input_[9].iserdes_dq_.idelay_dq.idelaye2 ;
  input calib_in_common;
  input \input_[9].iserdes_dq_.idelay_dq.idelaye2_0 ;
  input \input_[9].iserdes_dq_.idelay_dq.idelaye2_1 ;
  input idelay_ld_rst;
  input idelay_ld_rst_7;
  input idelay_ld_rst_8;
  input idelay_ld_rst_9;
  input idelay_ld_rst_10;
  input idelay_ld_rst_11;
  input idelay_ld_rst_12;
  input idelay_ld_rst_13;
  input wrlvl_byte_redo_r;
  input \wrlvl_redo_corse_inc[2]_i_7 ;
  input \wrlvl_redo_corse_inc[2]_i_7_0 ;
  input \idelay_tap_cnt_r_reg[0][4][4] ;
  input \idelay_tap_cnt_r_reg[0][4][4]_0 ;
  input \idelay_tap_cnt_r_reg[0][4][4]_1 ;
  input \idelay_tap_cnt_r_reg[0][0][4] ;
  input \idelay_tap_cnt_r_reg[0][0][4]_0 ;
  input \idelay_tap_cnt_r_reg[0][5][4] ;
  input \idelay_tap_cnt_r_reg[0][5][4]_0 ;
  input \idelay_tap_cnt_r_reg[0][6][4] ;
  input \idelay_tap_cnt_r_reg[0][7][4] ;
  input \idelay_tap_cnt_r_reg[0][1][4] ;
  input \idelay_tap_cnt_r_reg[0][2][4] ;
  input \init_state_r[3]_i_13 ;
  input wrlvl_done_r1;
  input \init_state_r[2]_i_14 ;
  input \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[508] ;
  input \init_state_r[3]_i_13_0 ;
  input \init_state_r[4]_i_27 ;
  input \not_empty_wait_cnt_reg[4]_0 ;
  input wrcal_rd_wait;
  input prech_done;
  input \cal2_state_r_reg[0]_0 ;

  wire [0:0]E;
  wire LD0;
  wire LD0_0;
  wire LD0_1;
  wire LD0_2;
  wire LD0_3;
  wire LD0_4;
  wire LD0_5;
  wire LD0_6;
  wire [3:0]Q;
  wire cal2_done_r;
  wire cal2_done_r_i_1_n_0;
  wire [0:0]cal2_done_r_reg_0;
  wire cal2_if_reset_i_1_n_0;
  wire cal2_if_reset_i_2_n_0;
  wire cal2_if_reset_i_3_n_0;
  wire cal2_if_reset_i_4_n_0;
  wire cal2_if_reset_i_5_n_0;
  wire cal2_if_reset_reg_0;
  wire cal2_prech_req_r;
  wire cal2_prech_req_r_i_1_n_0;
  wire cal2_prech_req_r_i_2_n_0;
  wire cal2_state_r;
  wire \cal2_state_r[0]_i_2_n_0 ;
  wire \cal2_state_r[0]_i_3_n_0 ;
  wire \cal2_state_r[0]_i_4_n_0 ;
  wire \cal2_state_r[0]_i_5_n_0 ;
  wire \cal2_state_r[1]_i_2_n_0 ;
  wire \cal2_state_r[1]_i_3_n_0 ;
  wire \cal2_state_r[1]_i_4_n_0 ;
  wire \cal2_state_r[2]_i_1_n_0 ;
  wire \cal2_state_r[2]_i_2_n_0 ;
  wire \cal2_state_r[2]_i_3_n_0 ;
  wire \cal2_state_r[3]_i_2_n_0 ;
  wire \cal2_state_r[3]_i_3_n_0 ;
  wire \cal2_state_r[3]_i_4_n_0 ;
  wire \cal2_state_r[3]_i_5_n_0 ;
  wire \cal2_state_r[3]_i_6_n_0 ;
  wire \cal2_state_r[3]_i_7_n_0 ;
  wire \cal2_state_r[3]_i_8_n_0 ;
  wire \cal2_state_r[3]_i_9_n_0 ;
  wire \cal2_state_r_reg[0]_0 ;
  wire \cal2_state_r_reg[0]_i_1_n_0 ;
  wire \cal2_state_r_reg[1]_i_1_n_0 ;
  wire \cal2_state_r_reg_n_0_[0] ;
  wire \cal2_state_r_reg_n_0_[1] ;
  wire \cal2_state_r_reg_n_0_[2] ;
  wire \cal2_state_r_reg_n_0_[3] ;
  wire calib_in_common;
  wire [1:0]\corse_cnt[0][2]_i_3 ;
  wire \corse_cnt[0][2]_i_3_0 ;
  wire done_dqs_dec238_out;
  wire early1_data_i_1_n_0;
  wire early1_data_i_2_n_0;
  wire early1_data_i_3_n_0;
  wire early1_data_match_r0;
  wire early1_data_reg_0;
  wire early1_data_reg_1;
  wire early1_match_fall0_and_r;
  wire [7:0]early1_match_fall0_r;
  wire early1_match_fall1_and_r;
  wire early1_match_fall2_and_r;
  wire early1_match_fall3_and_r;
  wire early1_match_rise0_and_r;
  wire [7:0]early1_match_rise0_r;
  wire early1_match_rise1_and_r;
  wire early1_match_rise2_and_r;
  wire early1_match_rise3_and_r;
  wire early2_data_i_1_n_0;
  wire early2_data_match_r0;
  wire early2_data_reg_n_0;
  wire early2_match_fall0_and_r;
  wire [7:0]early2_match_fall0_r;
  wire early2_match_fall1_and_r;
  wire [7:0]early2_match_fall1_r;
  wire early2_match_fall2_and_r;
  wire [7:0]early2_match_fall2_r;
  wire early2_match_fall3_and_r;
  wire [7:0]early2_match_fall3_r;
  wire early2_match_rise0_and_r;
  wire [7:0]early2_match_rise0_r;
  wire early2_match_rise1_and_r;
  wire [7:0]early2_match_rise1_r;
  wire early2_match_rise2_and_r;
  wire [7:0]early2_match_rise2_r;
  wire early2_match_rise3_and_r;
  wire [7:0]early2_match_rise3_r;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg_n_0_[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg_n_0_[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg_n_0_[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg_n_0_[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg_n_0_[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg_n_0_[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg_n_0_[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg_n_0_[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg_n_0_[1] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg_n_0_[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg_n_0_[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg_n_0_[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg_n_0_[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg_n_0_[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg_n_0_[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg_n_0_[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg_n_0_[2] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg_n_0_[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg_n_0_[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg_n_0_[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg_n_0_[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg_n_0_[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg_n_0_[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg_n_0_[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg_n_0_[3] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg_n_0_[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg_n_0_[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg_n_0_[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg_n_0_[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg_n_0_[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg_n_0_[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg_n_0_[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg_n_0_[4] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg_n_0_[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg_n_0_[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg_n_0_[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg_n_0_[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg_n_0_[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg_n_0_[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg_n_0_[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg_n_0_[5] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg_n_0_[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg_n_0_[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg_n_0_[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg_n_0_[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg_n_0_[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg_n_0_[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg_n_0_[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg_n_0_[6] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg_n_0_[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg_n_0_[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg_n_0_[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg_n_0_[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg_n_0_[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg_n_0_[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg_n_0_[7] ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ;
  wire \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg_n_0_[7] ;
  wire \gen_pat_match_div4.early1_data_match_r_i_2_n_0 ;
  wire \gen_pat_match_div4.early1_data_match_r_reg_n_0 ;
  wire \gen_pat_match_div4.early1_match_fall0_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.early1_match_fall0_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.early1_match_fall1_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.early1_match_fall1_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.early1_match_fall2_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.early1_match_fall2_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.early1_match_fall3_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.early1_match_fall3_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.early1_match_rise0_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.early1_match_rise0_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.early1_match_rise1_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.early1_match_rise1_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.early1_match_rise2_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.early1_match_rise2_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.early1_match_rise3_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.early1_match_rise3_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.early2_data_match_r_i_2_n_0 ;
  wire \gen_pat_match_div4.early2_data_match_r_reg_n_0 ;
  wire \gen_pat_match_div4.early2_match_fall0_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.early2_match_fall0_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.early2_match_fall1_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.early2_match_fall1_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.early2_match_fall2_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.early2_match_fall2_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.early2_match_fall3_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.early2_match_fall3_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.early2_match_rise0_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.early2_match_rise0_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.early2_match_rise1_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.early2_match_rise1_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.early2_match_rise2_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.early2_match_rise2_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.early2_match_rise3_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.early2_match_rise3_and_r_i_2_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r[0]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[0].early1_match_fall3_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[0].early1_match_rise0_r[0]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[0].early2_match_rise3_r[0]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r[0]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[0].pat_match_fall1_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r[0]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[0].pat_match_fall3_r[0]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r[0]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[0].pat_match_rise3_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r[1]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r[1]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[1].early2_match_fall2_r[1]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[1].early2_match_rise0_r[1]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[1].pat_match_fall0_r[1]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r[1]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[1].pat_match_fall2_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[1].pat_match_fall3_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[1].pat_match_rise1_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r[1]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r[1]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r[2]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[2].early1_match_fall2_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r[2]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[2].early1_match_rise0_r[2]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[2].early1_match_rise1_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r[2]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r[2]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r[2]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[2].pat_match_rise1_r[2]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[2].pat_match_rise2_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r[2]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[3].early1_match_fall1_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r[3]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r[3]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[3].early2_match_rise0_r[3]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[3].pat_match_fall0_r[3]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[3].pat_match_fall1_r[3]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[3].pat_match_fall2_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r[3]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r[3]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r[4]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[4].early1_match_fall3_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[4].early1_match_rise0_r[4]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[4].early2_match_rise3_r[4]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r[4]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[4].pat_match_fall1_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r[4]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[4].pat_match_fall3_r[4]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r[4]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[4].pat_match_rise3_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r[5]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r[5]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[5].early2_match_fall2_r[5]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[5].early2_match_rise0_r[5]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[5].pat_match_fall0_r[5]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r[5]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[5].pat_match_fall2_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[5].pat_match_fall3_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[5].pat_match_rise1_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r[5]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r[5]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r[6]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[6].early1_match_fall2_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r[6]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[6].early1_match_rise0_r[6]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[6].early1_match_rise1_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r[6]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r[6]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r[6]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[6].pat_match_rise1_r[6]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[6].pat_match_rise2_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r[6]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[7].early1_match_fall1_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r[7]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r[7]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[7].early2_match_rise0_r[7]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[7].pat_match_fall0_r[7]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[7].pat_match_fall1_r[7]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[7].pat_match_fall2_r_reg ;
  wire \gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r[7]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r[7]_i_1_n_0 ;
  wire \gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r_reg ;
  wire \gen_pat_match_div4.pat_data_match_r_i_2_n_0 ;
  wire \gen_pat_match_div4.pat_data_match_r_reg_n_0 ;
  wire \gen_pat_match_div4.pat_data_match_valid_r_reg_n_0 ;
  wire \gen_pat_match_div4.pat_match_fall0_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.pat_match_fall1_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.pat_match_fall2_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.pat_match_fall3_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.pat_match_rise0_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.pat_match_rise1_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.pat_match_rise2_and_r_i_1_n_0 ;
  wire \gen_pat_match_div4.pat_match_rise3_and_r_i_1_n_0 ;
  wire \gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0]_263 ;
  wire \gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0]_303 ;
  wire \gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0]_279 ;
  wire \gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0]_255 ;
  wire \gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0]_295 ;
  wire \gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0]_247 ;
  wire \gen_sr_div4.gen_sr[0].sr_rise2_r_reg[0]_271 ;
  wire \gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0]_287 ;
  wire \gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1]_264 ;
  wire \gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1]_304 ;
  wire \gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1]_280 ;
  wire \gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1]_256 ;
  wire \gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1]_296 ;
  wire \gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1]_248 ;
  wire \gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1]_272 ;
  wire \gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1]_288 ;
  wire \gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2]_265 ;
  wire \gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2]_305 ;
  wire \gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2]_281 ;
  wire \gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2]_257 ;
  wire \gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2]_297 ;
  wire \gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2]_249 ;
  wire \gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2]_273 ;
  wire \gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2]_289 ;
  wire \gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3]_266 ;
  wire \gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3]_306 ;
  wire \gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3]_282 ;
  wire \gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3]_258 ;
  wire \gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3]_298 ;
  wire \gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3]_250 ;
  wire \gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3]_274 ;
  wire \gen_sr_div4.gen_sr[3].sr_rise3_r_reg[3]_290 ;
  wire \gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4]_267 ;
  wire \gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4]_307 ;
  wire \gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4]_283 ;
  wire \gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4]_259 ;
  wire \gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4]_299 ;
  wire \gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4]_251 ;
  wire \gen_sr_div4.gen_sr[4].sr_rise2_r_reg[4]_275 ;
  wire \gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4]_291 ;
  wire \gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5]_268 ;
  wire \gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5]_308 ;
  wire \gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5]_284 ;
  wire \gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5]_260 ;
  wire \gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5]_300 ;
  wire \gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5]_252 ;
  wire \gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5]_276 ;
  wire \gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5]_292 ;
  wire \gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6]_269 ;
  wire \gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6]_309 ;
  wire \gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6]_285 ;
  wire \gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6]_261 ;
  wire \gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6]_301 ;
  wire \gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6]_253 ;
  wire \gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6]_277 ;
  wire \gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6]_293 ;
  wire \gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7]_270 ;
  wire \gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7]_310 ;
  wire \gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7]_286 ;
  wire \gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7]_262 ;
  wire \gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7]_302 ;
  wire \gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7]_254 ;
  wire \gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7]_278 ;
  wire \gen_sr_div4.gen_sr[7].sr_rise3_r_reg[7]_294 ;
  wire idelay_ce_int;
  wire idelay_ld;
  wire idelay_ld_done_i_1_n_0;
  wire idelay_ld_done_i_2_n_0;
  wire idelay_ld_done_reg_n_0;
  wire idelay_ld_i_1_n_0;
  wire idelay_ld_i_2_n_0;
  wire idelay_ld_rst;
  wire idelay_ld_rst_10;
  wire idelay_ld_rst_11;
  wire idelay_ld_rst_12;
  wire idelay_ld_rst_13;
  wire idelay_ld_rst_7;
  wire idelay_ld_rst_8;
  wire idelay_ld_rst_9;
  wire \idelay_tap_cnt_r[0][0][4]_i_5_n_0 ;
  wire \idelay_tap_cnt_r[0][4][4]_i_3_n_0 ;
  wire \idelay_tap_cnt_r_reg[0][0][4] ;
  wire \idelay_tap_cnt_r_reg[0][0][4]_0 ;
  wire \idelay_tap_cnt_r_reg[0][1][4] ;
  wire \idelay_tap_cnt_r_reg[0][2][4] ;
  wire \idelay_tap_cnt_r_reg[0][4][4] ;
  wire \idelay_tap_cnt_r_reg[0][4][4]_0 ;
  wire \idelay_tap_cnt_r_reg[0][4][4]_1 ;
  wire \idelay_tap_cnt_r_reg[0][5][4] ;
  wire \idelay_tap_cnt_r_reg[0][5][4]_0 ;
  wire \idelay_tap_cnt_r_reg[0][6][4] ;
  wire \idelay_tap_cnt_r_reg[0][7][4] ;
  wire \init_state_r[2]_i_14 ;
  wire \init_state_r[3]_i_13 ;
  wire \init_state_r[3]_i_13_0 ;
  wire \init_state_r[4]_i_27 ;
  wire [1:0]\input_[9].iserdes_dq_.idelay_dq.idelaye2 ;
  wire \input_[9].iserdes_dq_.idelay_dq.idelaye2_0 ;
  wire \input_[9].iserdes_dq_.idelay_dq.idelaye2_1 ;
  wire \not_empty_wait_cnt[4]_i_1_n_0 ;
  wire \not_empty_wait_cnt_reg[4]_0 ;
  wire \not_empty_wait_cnt_reg_n_0_[0] ;
  wire \not_empty_wait_cnt_reg_n_0_[1] ;
  wire \not_empty_wait_cnt_reg_n_0_[2] ;
  wire \not_empty_wait_cnt_reg_n_0_[3] ;
  wire \not_empty_wait_cnt_reg_n_0_[4] ;
  wire [4:0]p_0_in;
  wire [3:0]p_0_in__0;
  wire p_0_out;
  wire p_1_in;
  wire pat_data_match_r0;
  wire pat_match_fall0_and_r;
  wire pat_match_fall1_and_r;
  wire pat_match_fall2_and_r;
  wire pat_match_fall3_and_r;
  wire pat_match_rise0_and_r;
  wire pat_match_rise1_and_r;
  wire pat_match_rise2_and_r;
  wire pat_match_rise3_and_r;
  wire phy_if_reset_w;
  wire phy_rddata_en;
  wire \po_stg2_wrcal_cnt_reg[0]_0 ;
  wire \po_stg2_wrcal_cnt_reg[0]_1 ;
  wire \po_stg2_wrcal_cnt_reg[0]_2 ;
  wire [0:0]\po_stg2_wrcal_cnt_reg[0]_3 ;
  wire [0:0]\po_stg2_wrcal_cnt_reg[0]_4 ;
  wire [0:0]\po_stg2_wrcal_cnt_reg[0]_5 ;
  wire [0:0]\po_stg2_wrcal_cnt_reg[0]_6 ;
  wire [0:0]\po_stg2_wrcal_cnt_reg[0]_7 ;
  wire [0:0]\po_stg2_wrcal_cnt_reg[0]_8 ;
  wire \po_stg2_wrcal_cnt_reg[1]_0 ;
  wire [0:0]\po_stg2_wrcal_cnt_reg[1]_1 ;
  wire [0:0]\po_stg2_wrcal_cnt_reg[1]_2 ;
  wire \po_stg2_wrcal_cnt_reg[2]_0 ;
  wire \po_stg2_wrcal_cnt_reg[3]_0 ;
  wire prech_done;
  wire rd_active_r1;
  wire rd_active_r3_reg_srl2_n_0;
  wire \tap_inc_wait_cnt[3]_i_1_n_0 ;
  wire [3:0]tap_inc_wait_cnt_reg;
  wire wrcal_done_i_1_n_0;
  wire wrcal_done_reg_0;
  wire wrcal_done_reg_1;
  wire wrcal_done_reg_2;
  wire wrcal_done_reg_3;
  wire wrcal_done_reg_4;
  wire [3:3]wrcal_dqs_cnt_r;
  wire \wrcal_dqs_cnt_r[0]_i_1_n_0 ;
  wire \wrcal_dqs_cnt_r[1]_i_1_n_0 ;
  wire \wrcal_dqs_cnt_r[2]_i_1_n_0 ;
  wire \wrcal_dqs_cnt_r[3]_i_1_n_0 ;
  wire \wrcal_dqs_cnt_r[3]_i_2_n_0 ;
  wire \wrcal_dqs_cnt_r[3]_i_3_n_0 ;
  wire \wrcal_dqs_cnt_r[3]_i_4_n_0 ;
  wire \wrcal_dqs_cnt_r_reg_n_0_[0] ;
  wire \wrcal_dqs_cnt_r_reg_n_0_[1] ;
  wire \wrcal_dqs_cnt_r_reg_n_0_[2] ;
  wire wrcal_pat_resume_r;
  wire wrcal_pat_resume_r2_reg_srl2_n_0;
  wire wrcal_pat_resume_r_i_1_n_0;
  wire wrcal_pat_resume_r_i_2_n_0;
  wire wrcal_pat_resume_r_i_3_n_0;
  wire wrcal_pat_resume_reg_0;
  wire wrcal_prech_req;
  wire wrcal_rd_wait;
  wire wrcal_resume_w;
  wire wrcal_sanity_chk;
  wire wrcal_sanity_chk_done_i_1_n_0;
  wire wrcal_sanity_chk_done_reg_0;
  wire wrcal_sanity_chk_r_reg_n_0;
  wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[508] ;
  wire wrlvl_byte_done;
  wire wrlvl_byte_done_r;
  wire wrlvl_byte_redo;
  wire wrlvl_byte_redo_i_1_n_0;
  wire wrlvl_byte_redo_i_2_n_0;
  wire wrlvl_byte_redo_i_3_n_0;
  wire wrlvl_byte_redo_r;
  wire wrlvl_byte_redo_reg_0;
  wire wrlvl_done_r1;
  wire \wrlvl_redo_corse_inc[2]_i_7 ;
  wire \wrlvl_redo_corse_inc[2]_i_7_0 ;

  LUT4 #(
    .INIT(16'hDD45)) 
    \FSM_sequential_wl_state_r[4]_i_21 
       (.I0(early1_data_reg_0),
        .I1(\wrlvl_redo_corse_inc[2]_i_7 ),
        .I2(early2_data_reg_n_0),
        .I3(\wrlvl_redo_corse_inc[2]_i_7_0 ),
        .O(early1_data_reg_1));
  LUT6 #(
    .INIT(64'hFFFFEFFF00002000)) 
    cal2_done_r_i_1
       (.I0(p_1_in),
        .I1(\cal2_state_r_reg_n_0_[3] ),
        .I2(\cal2_state_r_reg_n_0_[2] ),
        .I3(\cal2_state_r_reg_n_0_[1] ),
        .I4(\cal2_state_r_reg_n_0_[0] ),
        .I5(cal2_done_r),
        .O(cal2_done_r_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair533" *) 
  LUT2 #(
    .INIT(4'hB)) 
    cal2_done_r_i_2
       (.I0(wrcal_sanity_chk_r_reg_n_0),
        .I1(wrcal_sanity_chk),
        .O(p_1_in));
  FDRE cal2_done_r_reg
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(cal2_done_r_i_1_n_0),
        .Q(cal2_done_r),
        .R(cal2_done_r_reg_0));
  LUT6 #(
    .INIT(64'hFFFFBABF00008A80)) 
    cal2_if_reset_i_1
       (.I0(cal2_if_reset_i_2_n_0),
        .I1(cal2_if_reset_i_3_n_0),
        .I2(\cal2_state_r_reg_n_0_[0] ),
        .I3(cal2_if_reset_i_4_n_0),
        .I4(\cal2_state_r_reg_n_0_[3] ),
        .I5(phy_if_reset_w),
        .O(cal2_if_reset_i_1_n_0));
  LUT6 #(
    .INIT(64'h004F0040F000F000)) 
    cal2_if_reset_i_2
       (.I0(E),
        .I1(rd_active_r1),
        .I2(\cal2_state_r_reg_n_0_[0] ),
        .I3(\cal2_state_r_reg_n_0_[2] ),
        .I4(wrcal_sanity_chk_r_reg_n_0),
        .I5(\cal2_state_r_reg_n_0_[1] ),
        .O(cal2_if_reset_i_2_n_0));
  LUT6 #(
    .INIT(64'h00FF000040FF40FF)) 
    cal2_if_reset_i_3
       (.I0(E),
        .I1(wrlvl_byte_done),
        .I2(rd_active_r1),
        .I3(\cal2_state_r_reg_n_0_[1] ),
        .I4(idelay_ld_done_i_2_n_0),
        .I5(\cal2_state_r_reg_n_0_[2] ),
        .O(cal2_if_reset_i_3_n_0));
  LUT6 #(
    .INIT(64'hFF80FFFFFF800000)) 
    cal2_if_reset_i_4
       (.I0(prech_done),
        .I1(cal2_prech_req_r_i_2_n_0),
        .I2(wrcal_sanity_chk_r_reg_n_0),
        .I3(\cal2_state_r_reg_n_0_[2] ),
        .I4(\cal2_state_r_reg_n_0_[1] ),
        .I5(cal2_if_reset_i_5_n_0),
        .O(cal2_if_reset_i_4_n_0));
  LUT6 #(
    .INIT(64'h8000FFFF80000000)) 
    cal2_if_reset_i_5
       (.I0(tap_inc_wait_cnt_reg[2]),
        .I1(tap_inc_wait_cnt_reg[0]),
        .I2(tap_inc_wait_cnt_reg[1]),
        .I3(tap_inc_wait_cnt_reg[3]),
        .I4(\cal2_state_r_reg_n_0_[2] ),
        .I5(\cal2_state_r_reg[0]_0 ),
        .O(cal2_if_reset_i_5_n_0));
  FDRE cal2_if_reset_reg
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(cal2_if_reset_i_1_n_0),
        .Q(phy_if_reset_w),
        .R(cal2_if_reset_reg_0));
  LUT6 #(
    .INIT(64'h0000000010110000)) 
    cal2_prech_req_r_i_1
       (.I0(\cal2_state_r_reg_n_0_[3] ),
        .I1(\cal2_state_r_reg_n_0_[2] ),
        .I2(cal2_prech_req_r_i_2_n_0),
        .I3(wrcal_sanity_chk_r_reg_n_0),
        .I4(\cal2_state_r_reg_n_0_[1] ),
        .I5(\cal2_state_r_reg_n_0_[0] ),
        .O(cal2_prech_req_r_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair549" *) 
  LUT4 #(
    .INIT(16'h0080)) 
    cal2_prech_req_r_i_2
       (.I0(\wrcal_dqs_cnt_r_reg_n_0_[1] ),
        .I1(\wrcal_dqs_cnt_r_reg_n_0_[0] ),
        .I2(\wrcal_dqs_cnt_r_reg_n_0_[2] ),
        .I3(wrcal_dqs_cnt_r),
        .O(cal2_prech_req_r_i_2_n_0));
  FDRE cal2_prech_req_r_reg
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(cal2_prech_req_r_i_1_n_0),
        .Q(cal2_prech_req_r),
        .R(cal2_if_reset_reg_0));
  LUT6 #(
    .INIT(64'h00000000FF5D005D)) 
    \cal2_state_r[0]_i_2 
       (.I0(\cal2_state_r_reg_n_0_[2] ),
        .I1(idelay_ld_done_reg_n_0),
        .I2(wrcal_sanity_chk_r_reg_n_0),
        .I3(\cal2_state_r_reg_n_0_[1] ),
        .I4(\cal2_state_r[0]_i_4_n_0 ),
        .I5(\cal2_state_r_reg_n_0_[3] ),
        .O(\cal2_state_r[0]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h0000CCE2)) 
    \cal2_state_r[0]_i_3 
       (.I0(\cal2_state_r[0]_i_5_n_0 ),
        .I1(\cal2_state_r_reg_n_0_[2] ),
        .I2(tap_inc_wait_cnt_reg[0]),
        .I3(\cal2_state_r_reg_n_0_[1] ),
        .I4(\cal2_state_r_reg_n_0_[3] ),
        .O(\cal2_state_r[0]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FFFF7FFF)) 
    \cal2_state_r[0]_i_4 
       (.I0(prech_done),
        .I1(\wrcal_dqs_cnt_r_reg_n_0_[1] ),
        .I2(\wrcal_dqs_cnt_r_reg_n_0_[0] ),
        .I3(\wrcal_dqs_cnt_r_reg_n_0_[2] ),
        .I4(wrcal_dqs_cnt_r),
        .I5(\cal2_state_r_reg_n_0_[2] ),
        .O(\cal2_state_r[0]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h0000000054550000)) 
    \cal2_state_r[0]_i_5 
       (.I0(wrcal_sanity_chk_r_reg_n_0),
        .I1(\gen_pat_match_div4.early2_data_match_r_reg_n_0 ),
        .I2(\gen_pat_match_div4.early1_data_match_r_reg_n_0 ),
        .I3(idelay_ld_done_reg_n_0),
        .I4(\gen_pat_match_div4.pat_data_match_valid_r_reg_n_0 ),
        .I5(\gen_pat_match_div4.pat_data_match_r_reg_n_0 ),
        .O(\cal2_state_r[0]_i_5_n_0 ));
  LUT5 #(
    .INIT(32'h0F0050D0)) 
    \cal2_state_r[1]_i_2 
       (.I0(prech_done),
        .I1(cal2_prech_req_r_i_2_n_0),
        .I2(\cal2_state_r_reg_n_0_[1] ),
        .I3(wrcal_sanity_chk_r_reg_n_0),
        .I4(\cal2_state_r_reg_n_0_[2] ),
        .O(\cal2_state_r[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FFE200E2)) 
    \cal2_state_r[1]_i_3 
       (.I0(\cal2_state_r[1]_i_4_n_0 ),
        .I1(\gen_pat_match_div4.pat_data_match_r_reg_n_0 ),
        .I2(\gen_pat_match_div4.pat_data_match_valid_r_reg_n_0 ),
        .I3(\cal2_state_r_reg_n_0_[2] ),
        .I4(tap_inc_wait_cnt_reg[1]),
        .I5(\cal2_state_r_reg_n_0_[1] ),
        .O(\cal2_state_r[1]_i_3_n_0 ));
  LUT4 #(
    .INIT(16'h00C8)) 
    \cal2_state_r[1]_i_4 
       (.I0(\gen_pat_match_div4.early1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat_data_match_valid_r_reg_n_0 ),
        .I2(\gen_pat_match_div4.early2_data_match_r_reg_n_0 ),
        .I3(wrcal_sanity_chk_r_reg_n_0),
        .O(\cal2_state_r[1]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h4F4AFFFF4F4A0000)) 
    \cal2_state_r[2]_i_1 
       (.I0(\cal2_state_r_reg_n_0_[1] ),
        .I1(tap_inc_wait_cnt_reg[2]),
        .I2(\cal2_state_r_reg_n_0_[2] ),
        .I3(\cal2_state_r[2]_i_2_n_0 ),
        .I4(\cal2_state_r_reg_n_0_[0] ),
        .I5(\cal2_state_r[2]_i_3_n_0 ),
        .O(\cal2_state_r[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000010)) 
    \cal2_state_r[2]_i_2 
       (.I0(wrcal_sanity_chk_r_reg_n_0),
        .I1(\gen_pat_match_div4.early2_data_match_r_reg_n_0 ),
        .I2(\gen_pat_match_div4.pat_data_match_valid_r_reg_n_0 ),
        .I3(\gen_pat_match_div4.early1_data_match_r_reg_n_0 ),
        .I4(idelay_ld_done_reg_n_0),
        .I5(\gen_pat_match_div4.pat_data_match_r_reg_n_0 ),
        .O(\cal2_state_r[2]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h0F00D0D0)) 
    \cal2_state_r[2]_i_3 
       (.I0(prech_done),
        .I1(cal2_prech_req_r_i_2_n_0),
        .I2(\cal2_state_r_reg_n_0_[1] ),
        .I3(wrcal_sanity_chk_r_reg_n_0),
        .I4(\cal2_state_r_reg_n_0_[2] ),
        .O(\cal2_state_r[2]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h00E2FFFF00E20000)) 
    \cal2_state_r[3]_i_2 
       (.I0(\cal2_state_r[3]_i_5_n_0 ),
        .I1(\cal2_state_r_reg_n_0_[2] ),
        .I2(tap_inc_wait_cnt_reg[3]),
        .I3(\cal2_state_r_reg_n_0_[1] ),
        .I4(\cal2_state_r_reg_n_0_[0] ),
        .I5(\cal2_state_r_reg_n_0_[3] ),
        .O(\cal2_state_r[3]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h45404F4F45404A4A)) 
    \cal2_state_r[3]_i_3 
       (.I0(\cal2_state_r_reg_n_0_[3] ),
        .I1(\cal2_state_r[3]_i_6_n_0 ),
        .I2(\cal2_state_r_reg_n_0_[1] ),
        .I3(\cal2_state_r[3]_i_7_n_0 ),
        .I4(\cal2_state_r_reg_n_0_[2] ),
        .I5(\cal2_state_r_reg[0]_0 ),
        .O(\cal2_state_r[3]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FFE200E2)) 
    \cal2_state_r[3]_i_4 
       (.I0(\cal2_state_r[3]_i_8_n_0 ),
        .I1(\cal2_state_r_reg_n_0_[2] ),
        .I2(idelay_ld_done_i_2_n_0),
        .I3(\cal2_state_r_reg_n_0_[1] ),
        .I4(\cal2_state_r[3]_i_9_n_0 ),
        .I5(\cal2_state_r_reg_n_0_[3] ),
        .O(\cal2_state_r[3]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h7777777733333373)) 
    \cal2_state_r[3]_i_5 
       (.I0(\gen_pat_match_div4.pat_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.pat_data_match_valid_r_reg_n_0 ),
        .I2(idelay_ld_done_reg_n_0),
        .I3(\gen_pat_match_div4.early1_data_match_r_reg_n_0 ),
        .I4(\gen_pat_match_div4.early2_data_match_r_reg_n_0 ),
        .I5(wrcal_sanity_chk_r_reg_n_0),
        .O(\cal2_state_r[3]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair533" *) 
  LUT5 #(
    .INIT(32'h3B3B3808)) 
    \cal2_state_r[3]_i_6 
       (.I0(wrcal_sanity_chk),
        .I1(\cal2_state_r_reg_n_0_[2] ),
        .I2(wrcal_sanity_chk_r_reg_n_0),
        .I3(\wrcal_dqs_cnt_r[3]_i_4_n_0 ),
        .I4(prech_done),
        .O(\cal2_state_r[3]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair547" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \cal2_state_r[3]_i_7 
       (.I0(tap_inc_wait_cnt_reg[2]),
        .I1(tap_inc_wait_cnt_reg[0]),
        .I2(tap_inc_wait_cnt_reg[1]),
        .I3(tap_inc_wait_cnt_reg[3]),
        .O(\cal2_state_r[3]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \cal2_state_r[3]_i_8 
       (.I0(\not_empty_wait_cnt_reg_n_0_[2] ),
        .I1(\not_empty_wait_cnt_reg_n_0_[1] ),
        .I2(\not_empty_wait_cnt_reg_n_0_[0] ),
        .I3(\not_empty_wait_cnt_reg_n_0_[3] ),
        .I4(\not_empty_wait_cnt_reg_n_0_[4] ),
        .I5(\gen_pat_match_div4.pat_data_match_valid_r_reg_n_0 ),
        .O(\cal2_state_r[3]_i_8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair537" *) 
  LUT5 #(
    .INIT(32'h8888B888)) 
    \cal2_state_r[3]_i_9 
       (.I0(\cal2_state_r[3]_i_7_n_0 ),
        .I1(\cal2_state_r_reg_n_0_[2] ),
        .I2(rd_active_r1),
        .I3(wrlvl_byte_done),
        .I4(E),
        .O(\cal2_state_r[3]_i_9_n_0 ));
  FDRE \cal2_state_r_reg[0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(cal2_state_r),
        .D(\cal2_state_r_reg[0]_i_1_n_0 ),
        .Q(\cal2_state_r_reg_n_0_[0] ),
        .R(cal2_done_r_reg_0));
  MUXF7 \cal2_state_r_reg[0]_i_1 
       (.I0(\cal2_state_r[0]_i_2_n_0 ),
        .I1(\cal2_state_r[0]_i_3_n_0 ),
        .O(\cal2_state_r_reg[0]_i_1_n_0 ),
        .S(\cal2_state_r_reg_n_0_[0] ));
  FDRE \cal2_state_r_reg[1] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(cal2_state_r),
        .D(\cal2_state_r_reg[1]_i_1_n_0 ),
        .Q(\cal2_state_r_reg_n_0_[1] ),
        .R(cal2_done_r_reg_0));
  MUXF7 \cal2_state_r_reg[1]_i_1 
       (.I0(\cal2_state_r[1]_i_2_n_0 ),
        .I1(\cal2_state_r[1]_i_3_n_0 ),
        .O(\cal2_state_r_reg[1]_i_1_n_0 ),
        .S(\cal2_state_r_reg_n_0_[0] ));
  FDRE \cal2_state_r_reg[2] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(cal2_state_r),
        .D(\cal2_state_r[2]_i_1_n_0 ),
        .Q(\cal2_state_r_reg_n_0_[2] ),
        .R(cal2_done_r_reg_0));
  FDRE \cal2_state_r_reg[3] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(cal2_state_r),
        .D(\cal2_state_r[3]_i_2_n_0 ),
        .Q(\cal2_state_r_reg_n_0_[3] ),
        .R(cal2_done_r_reg_0));
  MUXF7 \cal2_state_r_reg[3]_i_1 
       (.I0(\cal2_state_r[3]_i_3_n_0 ),
        .I1(\cal2_state_r[3]_i_4_n_0 ),
        .O(cal2_state_r),
        .S(\cal2_state_r_reg_n_0_[0] ));
  (* SOFT_HLUTNM = "soft_lutpair534" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \corse_cnt[0][2]_i_10 
       (.I0(Q[0]),
        .I1(Q[1]),
        .O(\po_stg2_wrcal_cnt_reg[0]_0 ));
  LUT6 #(
    .INIT(64'hFFFFFBFFFFFFFFFF)) 
    \corse_cnt[0][2]_i_9 
       (.I0(Q[2]),
        .I1(done_dqs_dec238_out),
        .I2(Q[3]),
        .I3(\corse_cnt[0][2]_i_3 [0]),
        .I4(\corse_cnt[0][2]_i_3 [1]),
        .I5(\corse_cnt[0][2]_i_3_0 ),
        .O(\po_stg2_wrcal_cnt_reg[2]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair536" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \corse_cnt[1][2]_i_3 
       (.I0(Q[1]),
        .I1(Q[0]),
        .O(\po_stg2_wrcal_cnt_reg[1]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair554" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \corse_cnt[2][2]_i_3 
       (.I0(Q[0]),
        .I1(Q[1]),
        .O(\po_stg2_wrcal_cnt_reg[0]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair554" *) 
  LUT2 #(
    .INIT(4'h7)) 
    \corse_cnt[3][2]_i_3 
       (.I0(Q[0]),
        .I1(Q[1]),
        .O(\po_stg2_wrcal_cnt_reg[0]_2 ));
  LUT6 #(
    .INIT(64'hFFDFFFFFFFFFFFFF)) 
    \corse_cnt[4][2]_i_3 
       (.I0(done_dqs_dec238_out),
        .I1(Q[3]),
        .I2(\corse_cnt[0][2]_i_3 [0]),
        .I3(\corse_cnt[0][2]_i_3 [1]),
        .I4(\corse_cnt[0][2]_i_3_0 ),
        .I5(Q[2]),
        .O(\po_stg2_wrcal_cnt_reg[3]_0 ));
  LUT4 #(
    .INIT(16'h2F20)) 
    early1_data_i_1
       (.I0(\gen_pat_match_div4.early1_data_match_r_reg_n_0 ),
        .I1(\cal2_state_r_reg_n_0_[1] ),
        .I2(early1_data_i_2_n_0),
        .I3(early1_data_reg_0),
        .O(early1_data_i_1_n_0));
  LUT5 #(
    .INIT(32'h45400000)) 
    early1_data_i_2
       (.I0(\cal2_state_r_reg_n_0_[3] ),
        .I1(early1_data_i_3_n_0),
        .I2(\cal2_state_r_reg_n_0_[1] ),
        .I3(wrlvl_byte_redo_i_3_n_0),
        .I4(\cal2_state_r_reg_n_0_[0] ),
        .O(early1_data_i_2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair537" *) 
  LUT4 #(
    .INIT(16'h0040)) 
    early1_data_i_3
       (.I0(E),
        .I1(wrlvl_byte_done),
        .I2(rd_active_r1),
        .I3(\cal2_state_r_reg_n_0_[2] ),
        .O(early1_data_i_3_n_0));
  FDRE early1_data_reg
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(early1_data_i_1_n_0),
        .Q(early1_data_reg_0),
        .R(cal2_if_reset_reg_0));
  LUT5 #(
    .INIT(32'h04FF0400)) 
    early2_data_i_1
       (.I0(\gen_pat_match_div4.early1_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.early2_data_match_r_reg_n_0 ),
        .I2(\cal2_state_r_reg_n_0_[1] ),
        .I3(early1_data_i_2_n_0),
        .I4(early2_data_reg_n_0),
        .O(early2_data_i_1_n_0));
  FDRE early2_data_reg
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(early2_data_i_1_n_0),
        .Q(early2_data_reg_n_0),
        .R(cal2_done_r_reg_0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg[0]_0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg[0]_0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg[0]_0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg[0]_0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg[0]_0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg[0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(p_0_out),
        .Q(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg[0]_0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg[0]_0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg[1]_0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg[1]_0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg[1]_0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg[1]_0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg[1]_0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg[1]_0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg[1]_0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg[1]_0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg[2]_0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg[2]_0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg[2]_0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg[2]_0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg[2]_0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg[2]_0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg[2]_0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg[2]_0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg[3]_0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg[3]_0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg[3]_0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg[3]_0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg[3]_0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg[3]_0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg[3]_0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg[3]_0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg[4]_0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg[4]_0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg[4]_0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg[4]_0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg[4]_0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg[4]_0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg[4]_0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg[4]_0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg[5]_0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg[5]_0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg[5]_0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg[5]_0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg[5]_0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg[5]_0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg[5]_0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg[5]_0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg[6]_0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg[6]_0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg[6]_0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg[6]_0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg[6]_0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg[6]_0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg[6]_0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg[6]_0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg[7]_0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg_n_0_[7] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg[7]_0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg_n_0_[7] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg[7]_0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg_n_0_[7] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg[7]_0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg_n_0_[7] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg[7]_0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg_n_0_[7] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg[7]_0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg_n_0_[7] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg[7]_0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg_n_0_[7] ),
        .R(1'b0));
  FDRE \gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg[7]_0 ),
        .Q(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg_n_0_[7] ),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h00008000)) 
    \gen_pat_match_div4.early1_data_match_r_i_1 
       (.I0(early1_match_rise0_and_r),
        .I1(early1_match_fall3_and_r),
        .I2(early1_match_fall0_and_r),
        .I3(early1_match_fall2_and_r),
        .I4(\gen_pat_match_div4.early1_data_match_r_i_2_n_0 ),
        .O(early1_data_match_r0));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \gen_pat_match_div4.early1_data_match_r_i_2 
       (.I0(early1_match_rise2_and_r),
        .I1(early1_match_rise3_and_r),
        .I2(early1_match_rise1_and_r),
        .I3(early1_match_fall1_and_r),
        .O(\gen_pat_match_div4.early1_data_match_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.early1_data_match_r_reg 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(early1_data_match_r0),
        .Q(\gen_pat_match_div4.early1_data_match_r_reg_n_0 ),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h00008000)) 
    \gen_pat_match_div4.early1_match_fall0_and_r_i_1 
       (.I0(early1_match_fall0_r[2]),
        .I1(early1_match_fall0_r[0]),
        .I2(early1_match_fall0_r[6]),
        .I3(early1_match_fall0_r[4]),
        .I4(\gen_pat_match_div4.early1_match_fall0_and_r_i_2_n_0 ),
        .O(\gen_pat_match_div4.early1_match_fall0_and_r_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \gen_pat_match_div4.early1_match_fall0_and_r_i_2 
       (.I0(early1_match_fall0_r[1]),
        .I1(early1_match_fall0_r[3]),
        .I2(early1_match_fall0_r[5]),
        .I3(early1_match_fall0_r[7]),
        .O(\gen_pat_match_div4.early1_match_fall0_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.early1_match_fall0_and_r_reg 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.early1_match_fall0_and_r_i_1_n_0 ),
        .Q(early1_match_fall0_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.early1_match_fall1_and_r_i_1 
       (.I0(\gen_pat_match_div4.early1_match_fall1_and_r_i_2_n_0 ),
        .I1(\gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r_reg ),
        .I2(\gen_pat_match_div4.gen_pat_match[3].early1_match_fall1_r_reg ),
        .I3(\gen_pat_match_div4.gen_pat_match[7].early1_match_fall1_r_reg ),
        .I4(\gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r_reg ),
        .O(\gen_pat_match_div4.early1_match_fall1_and_r_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair543" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \gen_pat_match_div4.early1_match_fall1_and_r_i_2 
       (.I0(early2_match_fall1_r[0]),
        .I1(early2_match_fall1_r[5]),
        .I2(early2_match_fall1_r[1]),
        .I3(early2_match_fall1_r[4]),
        .O(\gen_pat_match_div4.early1_match_fall1_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.early1_match_fall1_and_r_reg 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.early1_match_fall1_and_r_i_1_n_0 ),
        .Q(early1_match_fall1_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.early1_match_fall2_and_r_i_1 
       (.I0(\gen_pat_match_div4.early1_match_fall2_and_r_i_2_n_0 ),
        .I1(\gen_pat_match_div4.gen_pat_match[6].early1_match_fall2_r_reg ),
        .I2(\gen_pat_match_div4.gen_pat_match[2].early1_match_fall2_r_reg ),
        .I3(early2_match_fall2_r[7]),
        .I4(early2_match_fall2_r[3]),
        .O(\gen_pat_match_div4.early1_match_fall2_and_r_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h8000)) 
    \gen_pat_match_div4.early1_match_fall2_and_r_i_2 
       (.I0(\gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r_reg ),
        .I1(\gen_pat_match_div4.gen_pat_match[5].pat_match_fall2_r_reg ),
        .I2(\gen_pat_match_div4.gen_pat_match[1].pat_match_fall2_r_reg ),
        .I3(\gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r_reg ),
        .O(\gen_pat_match_div4.early1_match_fall2_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.early1_match_fall2_and_r_reg 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.early1_match_fall2_and_r_i_1_n_0 ),
        .Q(early1_match_fall2_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.early1_match_fall3_and_r_i_1 
       (.I0(\gen_pat_match_div4.early1_match_fall3_and_r_i_2_n_0 ),
        .I1(\gen_pat_match_div4.gen_pat_match[4].early1_match_fall3_r_reg ),
        .I2(\gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r_reg ),
        .I3(\gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r_reg ),
        .I4(\gen_pat_match_div4.gen_pat_match[0].early1_match_fall3_r_reg ),
        .O(\gen_pat_match_div4.early1_match_fall3_and_r_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair540" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \gen_pat_match_div4.early1_match_fall3_and_r_i_2 
       (.I0(early2_match_fall3_r[1]),
        .I1(early2_match_fall3_r[5]),
        .I2(early2_match_fall3_r[3]),
        .I3(early2_match_fall3_r[7]),
        .O(\gen_pat_match_div4.early1_match_fall3_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.early1_match_fall3_and_r_reg 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.early1_match_fall3_and_r_i_1_n_0 ),
        .Q(early1_match_fall3_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h00008000)) 
    \gen_pat_match_div4.early1_match_rise0_and_r_i_1 
       (.I0(early1_match_rise0_r[2]),
        .I1(early1_match_rise0_r[0]),
        .I2(early1_match_rise0_r[6]),
        .I3(early1_match_rise0_r[4]),
        .I4(\gen_pat_match_div4.early1_match_rise0_and_r_i_2_n_0 ),
        .O(\gen_pat_match_div4.early1_match_rise0_and_r_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \gen_pat_match_div4.early1_match_rise0_and_r_i_2 
       (.I0(early1_match_rise0_r[1]),
        .I1(early1_match_rise0_r[3]),
        .I2(early1_match_rise0_r[5]),
        .I3(early1_match_rise0_r[7]),
        .O(\gen_pat_match_div4.early1_match_rise0_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.early1_match_rise0_and_r_reg 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.early1_match_rise0_and_r_i_1_n_0 ),
        .Q(early1_match_rise0_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.early1_match_rise1_and_r_i_1 
       (.I0(\gen_pat_match_div4.early1_match_rise1_and_r_i_2_n_0 ),
        .I1(\gen_pat_match_div4.gen_pat_match[6].early1_match_rise1_r_reg ),
        .I2(\gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r_reg ),
        .I3(\gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r_reg ),
        .I4(\gen_pat_match_div4.gen_pat_match[2].early1_match_rise1_r_reg ),
        .O(\gen_pat_match_div4.early1_match_rise1_and_r_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair545" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \gen_pat_match_div4.early1_match_rise1_and_r_i_2 
       (.I0(early2_match_rise1_r[0]),
        .I1(early2_match_rise1_r[5]),
        .I2(early2_match_rise1_r[1]),
        .I3(early2_match_rise1_r[4]),
        .O(\gen_pat_match_div4.early1_match_rise1_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.early1_match_rise1_and_r_reg 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.early1_match_rise1_and_r_i_1_n_0 ),
        .Q(early1_match_rise1_and_r),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair544" *) 
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.early1_match_rise2_and_r_i_1 
       (.I0(early2_match_rise2_r[7]),
        .I1(early2_match_rise2_r[6]),
        .I2(early2_match_rise2_r[3]),
        .I3(early2_match_rise2_r[2]),
        .I4(\gen_pat_match_div4.early1_match_rise2_and_r_i_2_n_0 ),
        .O(\gen_pat_match_div4.early1_match_rise2_and_r_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h8000)) 
    \gen_pat_match_div4.early1_match_rise2_and_r_i_2 
       (.I0(early2_match_rise2_r[0]),
        .I1(early2_match_rise2_r[4]),
        .I2(\gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r_reg ),
        .I3(\gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r_reg ),
        .O(\gen_pat_match_div4.early1_match_rise2_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.early1_match_rise2_and_r_reg 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.early1_match_rise2_and_r_i_1_n_0 ),
        .Q(early1_match_rise2_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.early1_match_rise3_and_r_i_1 
       (.I0(\gen_pat_match_div4.early1_match_rise3_and_r_i_2_n_0 ),
        .I1(early2_match_rise3_r[5]),
        .I2(early2_match_rise3_r[1]),
        .I3(\gen_pat_match_div4.gen_pat_match[4].pat_match_rise3_r_reg ),
        .I4(\gen_pat_match_div4.gen_pat_match[0].pat_match_rise3_r_reg ),
        .O(\gen_pat_match_div4.early1_match_rise3_and_r_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h8000)) 
    \gen_pat_match_div4.early1_match_rise3_and_r_i_2 
       (.I0(\gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r_reg ),
        .I1(early2_match_rise3_r[7]),
        .I2(early2_match_rise3_r[3]),
        .I3(\gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r_reg ),
        .O(\gen_pat_match_div4.early1_match_rise3_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.early1_match_rise3_and_r_reg 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.early1_match_rise3_and_r_i_1_n_0 ),
        .Q(early1_match_rise3_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h00008000)) 
    \gen_pat_match_div4.early2_data_match_r_i_1 
       (.I0(early2_match_rise3_and_r),
        .I1(early2_match_fall2_and_r),
        .I2(early2_match_fall1_and_r),
        .I3(early2_match_rise0_and_r),
        .I4(\gen_pat_match_div4.early2_data_match_r_i_2_n_0 ),
        .O(early2_data_match_r0));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \gen_pat_match_div4.early2_data_match_r_i_2 
       (.I0(early2_match_fall0_and_r),
        .I1(early2_match_rise2_and_r),
        .I2(early2_match_rise1_and_r),
        .I3(early2_match_fall3_and_r),
        .O(\gen_pat_match_div4.early2_data_match_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.early2_data_match_r_reg 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(early2_data_match_r0),
        .Q(\gen_pat_match_div4.early2_data_match_r_reg_n_0 ),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.early2_match_fall0_and_r_i_1 
       (.I0(\gen_pat_match_div4.early2_match_fall0_and_r_i_2_n_0 ),
        .I1(early2_match_fall0_r[3]),
        .I2(early2_match_fall0_r[1]),
        .I3(early2_match_fall0_r[7]),
        .I4(early2_match_fall0_r[5]),
        .O(\gen_pat_match_div4.early2_match_fall0_and_r_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair546" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \gen_pat_match_div4.early2_match_fall0_and_r_i_2 
       (.I0(early2_match_fall0_r[4]),
        .I1(early2_match_fall0_r[6]),
        .I2(early2_match_fall0_r[0]),
        .I3(early2_match_fall0_r[2]),
        .O(\gen_pat_match_div4.early2_match_fall0_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.early2_match_fall0_and_r_reg 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.early2_match_fall0_and_r_i_1_n_0 ),
        .Q(early2_match_fall0_and_r),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair543" *) 
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.early2_match_fall1_and_r_i_1 
       (.I0(early2_match_fall1_r[4]),
        .I1(early2_match_fall1_r[1]),
        .I2(early2_match_fall1_r[5]),
        .I3(early2_match_fall1_r[0]),
        .I4(\gen_pat_match_div4.early2_match_fall1_and_r_i_2_n_0 ),
        .O(\gen_pat_match_div4.early2_match_fall1_and_r_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h8000)) 
    \gen_pat_match_div4.early2_match_fall1_and_r_i_2 
       (.I0(early2_match_fall1_r[2]),
        .I1(early2_match_fall1_r[7]),
        .I2(early2_match_fall1_r[3]),
        .I3(early2_match_fall1_r[6]),
        .O(\gen_pat_match_div4.early2_match_fall1_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.early2_match_fall1_and_r_reg 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.early2_match_fall1_and_r_i_1_n_0 ),
        .Q(early2_match_fall1_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h00008000)) 
    \gen_pat_match_div4.early2_match_fall2_and_r_i_1 
       (.I0(early2_match_fall2_r[6]),
        .I1(early2_match_fall2_r[1]),
        .I2(early2_match_fall2_r[7]),
        .I3(early2_match_fall2_r[0]),
        .I4(\gen_pat_match_div4.early2_match_fall2_and_r_i_2_n_0 ),
        .O(\gen_pat_match_div4.early2_match_fall2_and_r_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \gen_pat_match_div4.early2_match_fall2_and_r_i_2 
       (.I0(early2_match_fall2_r[2]),
        .I1(early2_match_fall2_r[5]),
        .I2(early2_match_fall2_r[3]),
        .I3(early2_match_fall2_r[4]),
        .O(\gen_pat_match_div4.early2_match_fall2_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.early2_match_fall2_and_r_reg 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.early2_match_fall2_and_r_i_1_n_0 ),
        .Q(early2_match_fall2_and_r),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair540" *) 
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.early2_match_fall3_and_r_i_1 
       (.I0(early2_match_fall3_r[7]),
        .I1(early2_match_fall3_r[3]),
        .I2(early2_match_fall3_r[5]),
        .I3(early2_match_fall3_r[1]),
        .I4(\gen_pat_match_div4.early2_match_fall3_and_r_i_2_n_0 ),
        .O(\gen_pat_match_div4.early2_match_fall3_and_r_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h8000)) 
    \gen_pat_match_div4.early2_match_fall3_and_r_i_2 
       (.I0(early2_match_fall3_r[0]),
        .I1(early2_match_fall3_r[6]),
        .I2(early2_match_fall3_r[4]),
        .I3(early2_match_fall3_r[2]),
        .O(\gen_pat_match_div4.early2_match_fall3_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.early2_match_fall3_and_r_reg 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.early2_match_fall3_and_r_i_1_n_0 ),
        .Q(early2_match_fall3_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.early2_match_rise0_and_r_i_1 
       (.I0(\gen_pat_match_div4.early2_match_rise0_and_r_i_2_n_0 ),
        .I1(early2_match_rise0_r[3]),
        .I2(early2_match_rise0_r[1]),
        .I3(early2_match_rise0_r[7]),
        .I4(early2_match_rise0_r[5]),
        .O(\gen_pat_match_div4.early2_match_rise0_and_r_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair542" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \gen_pat_match_div4.early2_match_rise0_and_r_i_2 
       (.I0(early2_match_rise0_r[4]),
        .I1(early2_match_rise0_r[6]),
        .I2(early2_match_rise0_r[0]),
        .I3(early2_match_rise0_r[2]),
        .O(\gen_pat_match_div4.early2_match_rise0_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.early2_match_rise0_and_r_reg 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.early2_match_rise0_and_r_i_1_n_0 ),
        .Q(early2_match_rise0_and_r),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair545" *) 
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.early2_match_rise1_and_r_i_1 
       (.I0(early2_match_rise1_r[4]),
        .I1(early2_match_rise1_r[1]),
        .I2(early2_match_rise1_r[5]),
        .I3(early2_match_rise1_r[0]),
        .I4(\gen_pat_match_div4.early2_match_rise1_and_r_i_2_n_0 ),
        .O(\gen_pat_match_div4.early2_match_rise1_and_r_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h8000)) 
    \gen_pat_match_div4.early2_match_rise1_and_r_i_2 
       (.I0(early2_match_rise1_r[2]),
        .I1(early2_match_rise1_r[7]),
        .I2(early2_match_rise1_r[3]),
        .I3(early2_match_rise1_r[6]),
        .O(\gen_pat_match_div4.early2_match_rise1_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.early2_match_rise1_and_r_reg 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.early2_match_rise1_and_r_i_1_n_0 ),
        .Q(early2_match_rise1_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.early2_match_rise2_and_r_i_1 
       (.I0(\gen_pat_match_div4.early2_match_rise2_and_r_i_2_n_0 ),
        .I1(early2_match_rise2_r[4]),
        .I2(early2_match_rise2_r[0]),
        .I3(early2_match_rise2_r[5]),
        .I4(early2_match_rise2_r[1]),
        .O(\gen_pat_match_div4.early2_match_rise2_and_r_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair544" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \gen_pat_match_div4.early2_match_rise2_and_r_i_2 
       (.I0(early2_match_rise2_r[2]),
        .I1(early2_match_rise2_r[3]),
        .I2(early2_match_rise2_r[6]),
        .I3(early2_match_rise2_r[7]),
        .O(\gen_pat_match_div4.early2_match_rise2_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.early2_match_rise2_and_r_reg 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.early2_match_rise2_and_r_i_1_n_0 ),
        .Q(early2_match_rise2_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h00008000)) 
    \gen_pat_match_div4.early2_match_rise3_and_r_i_1 
       (.I0(early2_match_rise3_r[6]),
        .I1(early2_match_rise3_r[5]),
        .I2(early2_match_rise3_r[7]),
        .I3(early2_match_rise3_r[4]),
        .I4(\gen_pat_match_div4.early2_match_rise3_and_r_i_2_n_0 ),
        .O(\gen_pat_match_div4.early2_match_rise3_and_r_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \gen_pat_match_div4.early2_match_rise3_and_r_i_2 
       (.I0(early2_match_rise3_r[0]),
        .I1(early2_match_rise3_r[3]),
        .I2(early2_match_rise3_r[1]),
        .I3(early2_match_rise3_r[2]),
        .O(\gen_pat_match_div4.early2_match_rise3_and_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.early2_match_rise3_and_r_reg 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.early2_match_rise3_and_r_i_1_n_0 ),
        .Q(early2_match_rise3_and_r),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[0].early1_match_fall0_r_reg[0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0]_263 ),
        .Q(early1_match_fall0_r[0]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r[0]_i_1 
       (.I0(\gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0]_303 ),
        .O(\gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r[0]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r_reg[0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[0].early1_match_fall1_r[0]_i_1_n_0 ),
        .Q(early2_match_fall1_r[0]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[0].early1_match_fall3_r_reg[0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0]_255 ),
        .Q(\gen_pat_match_div4.gen_pat_match[0].early1_match_fall3_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[0].early1_match_rise0_r[0]_i_1 
       (.I0(\gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0]_295 ),
        .O(\gen_pat_match_div4.gen_pat_match[0].early1_match_rise0_r[0]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[0].early1_match_rise0_r_reg[0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[0].early1_match_rise0_r[0]_i_1_n_0 ),
        .Q(early1_match_rise0_r[0]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[0].early1_match_rise1_r_reg[0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0]_247 ),
        .Q(early2_match_rise1_r[0]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[0].early2_match_fall2_r_reg[0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0]_279 ),
        .Q(early2_match_fall2_r[0]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[0].early2_match_rise3_r[0]_i_1 
       (.I0(\gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0]_287 ),
        .O(\gen_pat_match_div4.gen_pat_match[0].early2_match_rise3_r[0]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[0].early2_match_rise3_r_reg[0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[0].early2_match_rise3_r[0]_i_1_n_0 ),
        .Q(early2_match_rise3_r[0]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r[0]_i_1 
       (.I0(\gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0]_263 ),
        .O(\gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r[0]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r_reg[0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[0].pat_match_fall0_r[0]_i_1_n_0 ),
        .Q(early2_match_fall0_r[0]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[0].pat_match_fall1_r_reg[0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0]_303 ),
        .Q(\gen_pat_match_div4.gen_pat_match[0].pat_match_fall1_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r[0]_i_1 
       (.I0(\gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0]_279 ),
        .O(\gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r[0]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r_reg[0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r[0]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[0].pat_match_fall2_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[0].pat_match_fall3_r[0]_i_1 
       (.I0(\gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0]_255 ),
        .O(\gen_pat_match_div4.gen_pat_match[0].pat_match_fall3_r[0]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[0].pat_match_fall3_r_reg[0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[0].pat_match_fall3_r[0]_i_1_n_0 ),
        .Q(early2_match_fall3_r[0]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[0].pat_match_rise0_r_reg[0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0]_295 ),
        .Q(early2_match_rise0_r[0]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r[0]_i_1 
       (.I0(\gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0]_247 ),
        .O(\gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r[0]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r_reg[0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r[0]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[0].pat_match_rise2_r_reg[0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[0].sr_rise2_r_reg[0]_271 ),
        .Q(early2_match_rise2_r[0]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[0].pat_match_rise3_r_reg[0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0]_287 ),
        .Q(\gen_pat_match_div4.gen_pat_match[0].pat_match_rise3_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[1].early1_match_fall1_r_reg[1] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1]_304 ),
        .Q(early2_match_fall1_r[1]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r[1]_i_1 
       (.I0(\gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1]_256 ),
        .O(\gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r[1]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r_reg[1] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[1].early1_match_fall3_r[1]_i_1_n_0 ),
        .Q(early2_match_fall3_r[1]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r[1]_i_1 
       (.I0(\gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1]_248 ),
        .O(\gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r[1]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r_reg[1] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[1].early1_match_rise1_r[1]_i_1_n_0 ),
        .Q(early2_match_rise1_r[1]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[1].early1_match_rise3_r_reg[1] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1]_288 ),
        .Q(early2_match_rise3_r[1]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[1].early2_match_fall0_r_reg[1] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1]_264 ),
        .Q(early2_match_fall0_r[1]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[1].early2_match_fall2_r[1]_i_1 
       (.I0(\gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1]_280 ),
        .O(\gen_pat_match_div4.gen_pat_match[1].early2_match_fall2_r[1]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[1].early2_match_fall2_r_reg[1] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[1].early2_match_fall2_r[1]_i_1_n_0 ),
        .Q(early2_match_fall2_r[1]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[1].early2_match_rise0_r[1]_i_1 
       (.I0(\gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1]_296 ),
        .O(\gen_pat_match_div4.gen_pat_match[1].early2_match_rise0_r[1]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[1].early2_match_rise0_r_reg[1] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[1].early2_match_rise0_r[1]_i_1_n_0 ),
        .Q(early2_match_rise0_r[1]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[1].early2_match_rise2_r_reg[1] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1]_272 ),
        .Q(early2_match_rise2_r[1]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[1].pat_match_fall0_r[1]_i_1 
       (.I0(\gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1]_264 ),
        .O(\gen_pat_match_div4.gen_pat_match[1].pat_match_fall0_r[1]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[1].pat_match_fall0_r_reg[1] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[1].pat_match_fall0_r[1]_i_1_n_0 ),
        .Q(early1_match_fall0_r[1]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r[1]_i_1 
       (.I0(\gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1]_304 ),
        .O(\gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r[1]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r_reg[1] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r[1]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[1].pat_match_fall2_r_reg[1] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1]_280 ),
        .Q(\gen_pat_match_div4.gen_pat_match[1].pat_match_fall2_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[1].pat_match_fall3_r_reg[1] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1]_256 ),
        .Q(\gen_pat_match_div4.gen_pat_match[1].pat_match_fall3_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[1].pat_match_rise0_r_reg[1] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1]_296 ),
        .Q(early1_match_rise0_r[1]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[1].pat_match_rise1_r_reg[1] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1]_248 ),
        .Q(\gen_pat_match_div4.gen_pat_match[1].pat_match_rise1_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r[1]_i_1 
       (.I0(\gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1]_272 ),
        .O(\gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r[1]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r_reg[1] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r[1]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[1].pat_match_rise2_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r[1]_i_1 
       (.I0(\gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1]_288 ),
        .O(\gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r[1]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r_reg[1] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r[1]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[2].early1_match_fall0_r_reg[2] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2]_265 ),
        .Q(early1_match_fall0_r[2]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r[2]_i_1 
       (.I0(\gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2]_305 ),
        .O(\gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r[2]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r_reg[2] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r[2]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[2].early1_match_fall1_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[2].early1_match_fall2_r_reg[2] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2]_281 ),
        .Q(\gen_pat_match_div4.gen_pat_match[2].early1_match_fall2_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r[2]_i_1 
       (.I0(\gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2]_257 ),
        .O(\gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r[2]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r_reg[2] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r[2]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[2].early1_match_fall3_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[2].early1_match_rise0_r[2]_i_1 
       (.I0(\gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2]_297 ),
        .O(\gen_pat_match_div4.gen_pat_match[2].early1_match_rise0_r[2]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[2].early1_match_rise0_r_reg[2] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[2].early1_match_rise0_r[2]_i_1_n_0 ),
        .Q(early1_match_rise0_r[2]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[2].early1_match_rise1_r_reg[2] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2]_249 ),
        .Q(\gen_pat_match_div4.gen_pat_match[2].early1_match_rise1_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r[2]_i_1 
       (.I0(\gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2]_273 ),
        .O(\gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r[2]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r_reg[2] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[2].early1_match_rise2_r[2]_i_1_n_0 ),
        .Q(early2_match_rise2_r[2]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[2].early2_match_rise3_r_reg[2] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2]_289 ),
        .Q(early2_match_rise3_r[2]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r[2]_i_1 
       (.I0(\gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2]_265 ),
        .O(\gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r[2]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r_reg[2] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[2].pat_match_fall0_r[2]_i_1_n_0 ),
        .Q(early2_match_fall0_r[2]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[2].pat_match_fall1_r_reg[2] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2]_305 ),
        .Q(early2_match_fall1_r[2]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r[2]_i_1 
       (.I0(\gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2]_281 ),
        .O(\gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r[2]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r_reg[2] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[2].pat_match_fall2_r[2]_i_1_n_0 ),
        .Q(early2_match_fall2_r[2]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[2].pat_match_fall3_r_reg[2] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2]_257 ),
        .Q(early2_match_fall3_r[2]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[2].pat_match_rise0_r_reg[2] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2]_297 ),
        .Q(early2_match_rise0_r[2]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[2].pat_match_rise1_r[2]_i_1 
       (.I0(\gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2]_249 ),
        .O(\gen_pat_match_div4.gen_pat_match[2].pat_match_rise1_r[2]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[2].pat_match_rise1_r_reg[2] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[2].pat_match_rise1_r[2]_i_1_n_0 ),
        .Q(early2_match_rise1_r[2]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[2].pat_match_rise2_r_reg[2] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2]_273 ),
        .Q(\gen_pat_match_div4.gen_pat_match[2].pat_match_rise2_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r[2]_i_1 
       (.I0(\gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2]_289 ),
        .O(\gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r[2]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r_reg[2] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r[2]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[2].pat_match_rise3_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[3].early1_match_fall1_r_reg[3] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3]_306 ),
        .Q(\gen_pat_match_div4.gen_pat_match[3].early1_match_fall1_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r[3]_i_1 
       (.I0(\gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3]_282 ),
        .O(\gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r[3]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r_reg[3] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[3].early1_match_fall2_r[3]_i_1_n_0 ),
        .Q(early2_match_fall2_r[3]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r[3]_i_1 
       (.I0(\gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3]_250 ),
        .O(\gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r[3]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r_reg[3] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r[3]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[3].early1_match_rise1_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[3].early1_match_rise2_r_reg[3] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3]_274 ),
        .Q(early2_match_rise2_r[3]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[3].early2_match_fall0_r_reg[3] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3]_266 ),
        .Q(early2_match_fall0_r[3]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[3].early2_match_rise0_r[3]_i_1 
       (.I0(\gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3]_298 ),
        .O(\gen_pat_match_div4.gen_pat_match[3].early2_match_rise0_r[3]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[3].early2_match_rise0_r_reg[3] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[3].early2_match_rise0_r[3]_i_1_n_0 ),
        .Q(early2_match_rise0_r[3]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[3].pat_match_fall0_r[3]_i_1 
       (.I0(\gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3]_266 ),
        .O(\gen_pat_match_div4.gen_pat_match[3].pat_match_fall0_r[3]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[3].pat_match_fall0_r_reg[3] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[3].pat_match_fall0_r[3]_i_1_n_0 ),
        .Q(early1_match_fall0_r[3]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[3].pat_match_fall1_r[3]_i_1 
       (.I0(\gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3]_306 ),
        .O(\gen_pat_match_div4.gen_pat_match[3].pat_match_fall1_r[3]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[3].pat_match_fall1_r_reg[3] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[3].pat_match_fall1_r[3]_i_1_n_0 ),
        .Q(early2_match_fall1_r[3]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[3].pat_match_fall2_r_reg[3] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3]_282 ),
        .Q(\gen_pat_match_div4.gen_pat_match[3].pat_match_fall2_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r[3]_i_1 
       (.I0(\gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3]_258 ),
        .O(\gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r[3]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r_reg[3] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[3].pat_match_fall3_r[3]_i_1_n_0 ),
        .Q(early2_match_fall3_r[3]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[3].pat_match_rise0_r_reg[3] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3]_298 ),
        .Q(early1_match_rise0_r[3]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[3].pat_match_rise1_r_reg[3] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3]_250 ),
        .Q(early2_match_rise1_r[3]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r[3]_i_1 
       (.I0(\gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3]_274 ),
        .O(\gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r[3]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r_reg[3] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r[3]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[3].pat_match_rise3_r_reg[3] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[3].sr_rise3_r_reg[3]_290 ),
        .Q(early2_match_rise3_r[3]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[4].early1_match_fall0_r_reg[4] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4]_267 ),
        .Q(early1_match_fall0_r[4]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r[4]_i_1 
       (.I0(\gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4]_307 ),
        .O(\gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r[4]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r_reg[4] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[4].early1_match_fall1_r[4]_i_1_n_0 ),
        .Q(early2_match_fall1_r[4]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[4].early1_match_fall3_r_reg[4] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4]_259 ),
        .Q(\gen_pat_match_div4.gen_pat_match[4].early1_match_fall3_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[4].early1_match_rise0_r[4]_i_1 
       (.I0(\gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4]_299 ),
        .O(\gen_pat_match_div4.gen_pat_match[4].early1_match_rise0_r[4]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[4].early1_match_rise0_r_reg[4] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[4].early1_match_rise0_r[4]_i_1_n_0 ),
        .Q(early1_match_rise0_r[4]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[4].early1_match_rise1_r_reg[4] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4]_251 ),
        .Q(early2_match_rise1_r[4]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[4].early2_match_fall2_r_reg[4] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4]_283 ),
        .Q(early2_match_fall2_r[4]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[4].early2_match_rise3_r[4]_i_1 
       (.I0(\gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4]_291 ),
        .O(\gen_pat_match_div4.gen_pat_match[4].early2_match_rise3_r[4]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[4].early2_match_rise3_r_reg[4] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[4].early2_match_rise3_r[4]_i_1_n_0 ),
        .Q(early2_match_rise3_r[4]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r[4]_i_1 
       (.I0(\gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4]_267 ),
        .O(\gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r[4]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r_reg[4] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[4].pat_match_fall0_r[4]_i_1_n_0 ),
        .Q(early2_match_fall0_r[4]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[4].pat_match_fall1_r_reg[4] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4]_307 ),
        .Q(\gen_pat_match_div4.gen_pat_match[4].pat_match_fall1_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r[4]_i_1 
       (.I0(\gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4]_283 ),
        .O(\gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r[4]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r_reg[4] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r[4]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[4].pat_match_fall2_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[4].pat_match_fall3_r[4]_i_1 
       (.I0(\gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4]_259 ),
        .O(\gen_pat_match_div4.gen_pat_match[4].pat_match_fall3_r[4]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[4].pat_match_fall3_r_reg[4] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[4].pat_match_fall3_r[4]_i_1_n_0 ),
        .Q(early2_match_fall3_r[4]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[4].pat_match_rise0_r_reg[4] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4]_299 ),
        .Q(early2_match_rise0_r[4]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r[4]_i_1 
       (.I0(\gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4]_251 ),
        .O(\gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r[4]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r_reg[4] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r[4]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[4].pat_match_rise2_r_reg[4] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[4].sr_rise2_r_reg[4]_275 ),
        .Q(early2_match_rise2_r[4]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[4].pat_match_rise3_r_reg[4] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4]_291 ),
        .Q(\gen_pat_match_div4.gen_pat_match[4].pat_match_rise3_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[5].early1_match_fall1_r_reg[5] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5]_308 ),
        .Q(early2_match_fall1_r[5]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r[5]_i_1 
       (.I0(\gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5]_260 ),
        .O(\gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r[5]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r_reg[5] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[5].early1_match_fall3_r[5]_i_1_n_0 ),
        .Q(early2_match_fall3_r[5]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r[5]_i_1 
       (.I0(\gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5]_252 ),
        .O(\gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r[5]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r_reg[5] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[5].early1_match_rise1_r[5]_i_1_n_0 ),
        .Q(early2_match_rise1_r[5]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[5].early1_match_rise3_r_reg[5] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5]_292 ),
        .Q(early2_match_rise3_r[5]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[5].early2_match_fall0_r_reg[5] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5]_268 ),
        .Q(early2_match_fall0_r[5]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[5].early2_match_fall2_r[5]_i_1 
       (.I0(\gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5]_284 ),
        .O(\gen_pat_match_div4.gen_pat_match[5].early2_match_fall2_r[5]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[5].early2_match_fall2_r_reg[5] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[5].early2_match_fall2_r[5]_i_1_n_0 ),
        .Q(early2_match_fall2_r[5]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[5].early2_match_rise0_r[5]_i_1 
       (.I0(\gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5]_300 ),
        .O(\gen_pat_match_div4.gen_pat_match[5].early2_match_rise0_r[5]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[5].early2_match_rise0_r_reg[5] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[5].early2_match_rise0_r[5]_i_1_n_0 ),
        .Q(early2_match_rise0_r[5]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[5].early2_match_rise2_r_reg[5] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5]_276 ),
        .Q(early2_match_rise2_r[5]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[5].pat_match_fall0_r[5]_i_1 
       (.I0(\gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5]_268 ),
        .O(\gen_pat_match_div4.gen_pat_match[5].pat_match_fall0_r[5]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[5].pat_match_fall0_r_reg[5] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[5].pat_match_fall0_r[5]_i_1_n_0 ),
        .Q(early1_match_fall0_r[5]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r[5]_i_1 
       (.I0(\gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5]_308 ),
        .O(\gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r[5]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r_reg[5] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r[5]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[5].pat_match_fall2_r_reg[5] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5]_284 ),
        .Q(\gen_pat_match_div4.gen_pat_match[5].pat_match_fall2_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[5].pat_match_fall3_r_reg[5] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5]_260 ),
        .Q(\gen_pat_match_div4.gen_pat_match[5].pat_match_fall3_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[5].pat_match_rise0_r_reg[5] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5]_300 ),
        .Q(early1_match_rise0_r[5]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[5].pat_match_rise1_r_reg[5] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5]_252 ),
        .Q(\gen_pat_match_div4.gen_pat_match[5].pat_match_rise1_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r[5]_i_1 
       (.I0(\gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5]_276 ),
        .O(\gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r[5]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r_reg[5] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r[5]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[5].pat_match_rise2_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r[5]_i_1 
       (.I0(\gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5]_292 ),
        .O(\gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r[5]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r_reg[5] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r[5]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[6].early1_match_fall0_r_reg[6] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6]_269 ),
        .Q(early1_match_fall0_r[6]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r[6]_i_1 
       (.I0(\gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6]_309 ),
        .O(\gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r[6]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r_reg[6] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r[6]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[6].early1_match_fall1_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[6].early1_match_fall2_r_reg[6] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6]_285 ),
        .Q(\gen_pat_match_div4.gen_pat_match[6].early1_match_fall2_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r[6]_i_1 
       (.I0(\gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6]_261 ),
        .O(\gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r[6]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r_reg[6] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r[6]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[6].early1_match_fall3_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[6].early1_match_rise0_r[6]_i_1 
       (.I0(\gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6]_301 ),
        .O(\gen_pat_match_div4.gen_pat_match[6].early1_match_rise0_r[6]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[6].early1_match_rise0_r_reg[6] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[6].early1_match_rise0_r[6]_i_1_n_0 ),
        .Q(early1_match_rise0_r[6]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[6].early1_match_rise1_r_reg[6] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6]_253 ),
        .Q(\gen_pat_match_div4.gen_pat_match[6].early1_match_rise1_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r[6]_i_1 
       (.I0(\gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6]_277 ),
        .O(\gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r[6]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r_reg[6] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[6].early1_match_rise2_r[6]_i_1_n_0 ),
        .Q(early2_match_rise2_r[6]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[6].early2_match_rise3_r_reg[6] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6]_293 ),
        .Q(early2_match_rise3_r[6]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r[6]_i_1 
       (.I0(\gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6]_269 ),
        .O(\gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r[6]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r_reg[6] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[6].pat_match_fall0_r[6]_i_1_n_0 ),
        .Q(early2_match_fall0_r[6]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[6].pat_match_fall1_r_reg[6] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6]_309 ),
        .Q(early2_match_fall1_r[6]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r[6]_i_1 
       (.I0(\gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6]_285 ),
        .O(\gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r[6]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r_reg[6] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[6].pat_match_fall2_r[6]_i_1_n_0 ),
        .Q(early2_match_fall2_r[6]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[6].pat_match_fall3_r_reg[6] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6]_261 ),
        .Q(early2_match_fall3_r[6]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[6].pat_match_rise0_r_reg[6] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6]_301 ),
        .Q(early2_match_rise0_r[6]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[6].pat_match_rise1_r[6]_i_1 
       (.I0(\gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6]_253 ),
        .O(\gen_pat_match_div4.gen_pat_match[6].pat_match_rise1_r[6]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[6].pat_match_rise1_r_reg[6] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[6].pat_match_rise1_r[6]_i_1_n_0 ),
        .Q(early2_match_rise1_r[6]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[6].pat_match_rise2_r_reg[6] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6]_277 ),
        .Q(\gen_pat_match_div4.gen_pat_match[6].pat_match_rise2_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r[6]_i_1 
       (.I0(\gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6]_293 ),
        .O(\gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r[6]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r_reg[6] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r[6]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[6].pat_match_rise3_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[7].early1_match_fall1_r_reg[7] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7]_310 ),
        .Q(\gen_pat_match_div4.gen_pat_match[7].early1_match_fall1_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r[7]_i_1 
       (.I0(\gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7]_286 ),
        .O(\gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r[7]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r_reg[7] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[7].early1_match_fall2_r[7]_i_1_n_0 ),
        .Q(early2_match_fall2_r[7]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r[7]_i_1 
       (.I0(\gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7]_254 ),
        .O(\gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r[7]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r_reg[7] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r[7]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[7].early1_match_rise1_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[7].early1_match_rise2_r_reg[7] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7]_278 ),
        .Q(early2_match_rise2_r[7]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[7].early2_match_fall0_r_reg[7] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7]_270 ),
        .Q(early2_match_fall0_r[7]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[7].early2_match_rise0_r[7]_i_1 
       (.I0(\gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7]_302 ),
        .O(\gen_pat_match_div4.gen_pat_match[7].early2_match_rise0_r[7]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[7].early2_match_rise0_r_reg[7] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[7].early2_match_rise0_r[7]_i_1_n_0 ),
        .Q(early2_match_rise0_r[7]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[7].pat_match_fall0_r[7]_i_1 
       (.I0(\gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7]_270 ),
        .O(\gen_pat_match_div4.gen_pat_match[7].pat_match_fall0_r[7]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[7].pat_match_fall0_r_reg[7] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[7].pat_match_fall0_r[7]_i_1_n_0 ),
        .Q(early1_match_fall0_r[7]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[7].pat_match_fall1_r[7]_i_1 
       (.I0(\gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7]_310 ),
        .O(\gen_pat_match_div4.gen_pat_match[7].pat_match_fall1_r[7]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[7].pat_match_fall1_r_reg[7] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[7].pat_match_fall1_r[7]_i_1_n_0 ),
        .Q(early2_match_fall1_r[7]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[7].pat_match_fall2_r_reg[7] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7]_286 ),
        .Q(\gen_pat_match_div4.gen_pat_match[7].pat_match_fall2_r_reg ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r[7]_i_1 
       (.I0(\gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7]_262 ),
        .O(\gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r[7]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r_reg[7] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[7].pat_match_fall3_r[7]_i_1_n_0 ),
        .Q(early2_match_fall3_r[7]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[7].pat_match_rise0_r_reg[7] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7]_302 ),
        .Q(early1_match_rise0_r[7]),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[7].pat_match_rise1_r_reg[7] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7]_254 ),
        .Q(early2_match_rise1_r[7]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r[7]_i_1 
       (.I0(\gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7]_278 ),
        .O(\gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r[7]_i_1_n_0 ));
  FDRE \gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r_reg[7] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r[7]_i_1_n_0 ),
        .Q(\gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r_reg ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.gen_pat_match[7].pat_match_rise3_r_reg[7] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_sr_div4.gen_sr[7].sr_rise3_r_reg[7]_294 ),
        .Q(early2_match_rise3_r[7]),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h00008000)) 
    \gen_pat_match_div4.pat_data_match_r_i_1 
       (.I0(pat_match_fall0_and_r),
        .I1(pat_match_rise2_and_r),
        .I2(pat_match_rise1_and_r),
        .I3(pat_match_fall1_and_r),
        .I4(\gen_pat_match_div4.pat_data_match_r_i_2_n_0 ),
        .O(pat_data_match_r0));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \gen_pat_match_div4.pat_data_match_r_i_2 
       (.I0(pat_match_rise0_and_r),
        .I1(pat_match_rise3_and_r),
        .I2(pat_match_fall3_and_r),
        .I3(pat_match_fall2_and_r),
        .O(\gen_pat_match_div4.pat_data_match_r_i_2_n_0 ));
  FDRE \gen_pat_match_div4.pat_data_match_r_reg 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(pat_data_match_r0),
        .Q(\gen_pat_match_div4.pat_data_match_r_reg_n_0 ),
        .R(1'b0));
  FDRE \gen_pat_match_div4.pat_data_match_valid_r_reg 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(rd_active_r3_reg_srl2_n_0),
        .Q(\gen_pat_match_div4.pat_data_match_valid_r_reg_n_0 ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair546" *) 
  LUT5 #(
    .INIT(32'h00008000)) 
    \gen_pat_match_div4.pat_match_fall0_and_r_i_1 
       (.I0(early2_match_fall0_r[2]),
        .I1(early2_match_fall0_r[0]),
        .I2(early2_match_fall0_r[6]),
        .I3(early2_match_fall0_r[4]),
        .I4(\gen_pat_match_div4.early1_match_fall0_and_r_i_2_n_0 ),
        .O(\gen_pat_match_div4.pat_match_fall0_and_r_i_1_n_0 ));
  FDRE \gen_pat_match_div4.pat_match_fall0_and_r_reg 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.pat_match_fall0_and_r_i_1_n_0 ),
        .Q(pat_match_fall0_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.pat_match_fall1_and_r_i_1 
       (.I0(\gen_pat_match_div4.early2_match_fall1_and_r_i_2_n_0 ),
        .I1(\gen_pat_match_div4.gen_pat_match[4].pat_match_fall1_r_reg ),
        .I2(\gen_pat_match_div4.gen_pat_match[1].pat_match_fall1_r_reg ),
        .I3(\gen_pat_match_div4.gen_pat_match[5].pat_match_fall1_r_reg ),
        .I4(\gen_pat_match_div4.gen_pat_match[0].pat_match_fall1_r_reg ),
        .O(\gen_pat_match_div4.pat_match_fall1_and_r_i_1_n_0 ));
  FDRE \gen_pat_match_div4.pat_match_fall1_and_r_reg 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.pat_match_fall1_and_r_i_1_n_0 ),
        .Q(pat_match_fall1_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.pat_match_fall2_and_r_i_1 
       (.I0(\gen_pat_match_div4.early1_match_fall2_and_r_i_2_n_0 ),
        .I1(\gen_pat_match_div4.gen_pat_match[7].pat_match_fall2_r_reg ),
        .I2(\gen_pat_match_div4.gen_pat_match[3].pat_match_fall2_r_reg ),
        .I3(early2_match_fall2_r[6]),
        .I4(early2_match_fall2_r[2]),
        .O(\gen_pat_match_div4.pat_match_fall2_and_r_i_1_n_0 ));
  FDRE \gen_pat_match_div4.pat_match_fall2_and_r_reg 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.pat_match_fall2_and_r_i_1_n_0 ),
        .Q(pat_match_fall2_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.pat_match_fall3_and_r_i_1 
       (.I0(\gen_pat_match_div4.early2_match_fall3_and_r_i_2_n_0 ),
        .I1(\gen_pat_match_div4.gen_pat_match[5].pat_match_fall3_r_reg ),
        .I2(\gen_pat_match_div4.gen_pat_match[1].pat_match_fall3_r_reg ),
        .I3(early2_match_fall3_r[7]),
        .I4(early2_match_fall3_r[3]),
        .O(\gen_pat_match_div4.pat_match_fall3_and_r_i_1_n_0 ));
  FDRE \gen_pat_match_div4.pat_match_fall3_and_r_reg 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.pat_match_fall3_and_r_i_1_n_0 ),
        .Q(pat_match_fall3_and_r),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair542" *) 
  LUT5 #(
    .INIT(32'h00008000)) 
    \gen_pat_match_div4.pat_match_rise0_and_r_i_1 
       (.I0(early2_match_rise0_r[2]),
        .I1(early2_match_rise0_r[0]),
        .I2(early2_match_rise0_r[6]),
        .I3(early2_match_rise0_r[4]),
        .I4(\gen_pat_match_div4.early1_match_rise0_and_r_i_2_n_0 ),
        .O(\gen_pat_match_div4.pat_match_rise0_and_r_i_1_n_0 ));
  FDRE \gen_pat_match_div4.pat_match_rise0_and_r_reg 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.pat_match_rise0_and_r_i_1_n_0 ),
        .Q(pat_match_rise0_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.pat_match_rise1_and_r_i_1 
       (.I0(\gen_pat_match_div4.early2_match_rise1_and_r_i_2_n_0 ),
        .I1(\gen_pat_match_div4.gen_pat_match[4].pat_match_rise1_r_reg ),
        .I2(\gen_pat_match_div4.gen_pat_match[1].pat_match_rise1_r_reg ),
        .I3(\gen_pat_match_div4.gen_pat_match[5].pat_match_rise1_r_reg ),
        .I4(\gen_pat_match_div4.gen_pat_match[0].pat_match_rise1_r_reg ),
        .O(\gen_pat_match_div4.pat_match_rise1_and_r_i_1_n_0 ));
  FDRE \gen_pat_match_div4.pat_match_rise1_and_r_reg 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.pat_match_rise1_and_r_i_1_n_0 ),
        .Q(pat_match_rise1_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.pat_match_rise2_and_r_i_1 
       (.I0(\gen_pat_match_div4.early1_match_rise2_and_r_i_2_n_0 ),
        .I1(\gen_pat_match_div4.gen_pat_match[6].pat_match_rise2_r_reg ),
        .I2(\gen_pat_match_div4.gen_pat_match[3].pat_match_rise2_r_reg ),
        .I3(\gen_pat_match_div4.gen_pat_match[7].pat_match_rise2_r_reg ),
        .I4(\gen_pat_match_div4.gen_pat_match[2].pat_match_rise2_r_reg ),
        .O(\gen_pat_match_div4.pat_match_rise2_and_r_i_1_n_0 ));
  FDRE \gen_pat_match_div4.pat_match_rise2_and_r_reg 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.pat_match_rise2_and_r_i_1_n_0 ),
        .Q(pat_match_rise2_and_r),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h80000000)) 
    \gen_pat_match_div4.pat_match_rise3_and_r_i_1 
       (.I0(\gen_pat_match_div4.early1_match_rise3_and_r_i_2_n_0 ),
        .I1(\gen_pat_match_div4.gen_pat_match[5].pat_match_rise3_r_reg ),
        .I2(\gen_pat_match_div4.gen_pat_match[1].pat_match_rise3_r_reg ),
        .I3(\gen_pat_match_div4.gen_pat_match[4].pat_match_rise3_r_reg ),
        .I4(\gen_pat_match_div4.gen_pat_match[0].pat_match_rise3_r_reg ),
        .O(\gen_pat_match_div4.pat_match_rise3_and_r_i_1_n_0 ));
  FDRE \gen_pat_match_div4.pat_match_rise3_and_r_reg 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_pat_match_div4.pat_match_rise3_and_r_i_1_n_0 ),
        .Q(pat_match_rise3_and_r),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0][0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall0_r_reg_n_0_[0] ),
        .Q(\gen_sr_div4.gen_sr[0].sr_fall0_r_reg[0]_263 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0][0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall1_r_reg_n_0_[0] ),
        .Q(\gen_sr_div4.gen_sr[0].sr_fall1_r_reg[0]_303 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0][0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall2_r_reg_n_0_[0] ),
        .Q(\gen_sr_div4.gen_sr[0].sr_fall2_r_reg[0]_279 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0][0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_fall3_r_reg_n_0_[0] ),
        .Q(\gen_sr_div4.gen_sr[0].sr_fall3_r_reg[0]_255 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0][0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise0_r_reg_n_0_[0] ),
        .Q(\gen_sr_div4.gen_sr[0].sr_rise0_r_reg[0]_295 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0][0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise1_r_reg_n_0_[0] ),
        .Q(\gen_sr_div4.gen_sr[0].sr_rise1_r_reg[0]_247 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[0].sr_rise2_r_reg[0][0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise2_r_reg_n_0_[0] ),
        .Q(\gen_sr_div4.gen_sr[0].sr_rise2_r_reg[0]_271 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0][0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[0].mux_rd_rise3_r_reg_n_0_[0] ),
        .Q(\gen_sr_div4.gen_sr[0].sr_rise3_r_reg[0]_287 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1][0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall0_r_reg_n_0_[1] ),
        .Q(\gen_sr_div4.gen_sr[1].sr_fall0_r_reg[1]_264 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1][0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall1_r_reg_n_0_[1] ),
        .Q(\gen_sr_div4.gen_sr[1].sr_fall1_r_reg[1]_304 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1][0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall2_r_reg_n_0_[1] ),
        .Q(\gen_sr_div4.gen_sr[1].sr_fall2_r_reg[1]_280 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1][0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_fall3_r_reg_n_0_[1] ),
        .Q(\gen_sr_div4.gen_sr[1].sr_fall3_r_reg[1]_256 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1][0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise0_r_reg_n_0_[1] ),
        .Q(\gen_sr_div4.gen_sr[1].sr_rise0_r_reg[1]_296 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1][0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise1_r_reg_n_0_[1] ),
        .Q(\gen_sr_div4.gen_sr[1].sr_rise1_r_reg[1]_248 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1][0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise2_r_reg_n_0_[1] ),
        .Q(\gen_sr_div4.gen_sr[1].sr_rise2_r_reg[1]_272 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1][0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[1].mux_rd_rise3_r_reg_n_0_[1] ),
        .Q(\gen_sr_div4.gen_sr[1].sr_rise3_r_reg[1]_288 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2][0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall0_r_reg_n_0_[2] ),
        .Q(\gen_sr_div4.gen_sr[2].sr_fall0_r_reg[2]_265 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2][0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall1_r_reg_n_0_[2] ),
        .Q(\gen_sr_div4.gen_sr[2].sr_fall1_r_reg[2]_305 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2][0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall2_r_reg_n_0_[2] ),
        .Q(\gen_sr_div4.gen_sr[2].sr_fall2_r_reg[2]_281 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2][0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_fall3_r_reg_n_0_[2] ),
        .Q(\gen_sr_div4.gen_sr[2].sr_fall3_r_reg[2]_257 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2][0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise0_r_reg_n_0_[2] ),
        .Q(\gen_sr_div4.gen_sr[2].sr_rise0_r_reg[2]_297 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2][0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise1_r_reg_n_0_[2] ),
        .Q(\gen_sr_div4.gen_sr[2].sr_rise1_r_reg[2]_249 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2][0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise2_r_reg_n_0_[2] ),
        .Q(\gen_sr_div4.gen_sr[2].sr_rise2_r_reg[2]_273 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2][0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[2].mux_rd_rise3_r_reg_n_0_[2] ),
        .Q(\gen_sr_div4.gen_sr[2].sr_rise3_r_reg[2]_289 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3][0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall0_r_reg_n_0_[3] ),
        .Q(\gen_sr_div4.gen_sr[3].sr_fall0_r_reg[3]_266 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3][0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall1_r_reg_n_0_[3] ),
        .Q(\gen_sr_div4.gen_sr[3].sr_fall1_r_reg[3]_306 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3][0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall2_r_reg_n_0_[3] ),
        .Q(\gen_sr_div4.gen_sr[3].sr_fall2_r_reg[3]_282 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3][0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_fall3_r_reg_n_0_[3] ),
        .Q(\gen_sr_div4.gen_sr[3].sr_fall3_r_reg[3]_258 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3][0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise0_r_reg_n_0_[3] ),
        .Q(\gen_sr_div4.gen_sr[3].sr_rise0_r_reg[3]_298 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3][0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise1_r_reg_n_0_[3] ),
        .Q(\gen_sr_div4.gen_sr[3].sr_rise1_r_reg[3]_250 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3][0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise2_r_reg_n_0_[3] ),
        .Q(\gen_sr_div4.gen_sr[3].sr_rise2_r_reg[3]_274 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[3].sr_rise3_r_reg[3][0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[3].mux_rd_rise3_r_reg_n_0_[3] ),
        .Q(\gen_sr_div4.gen_sr[3].sr_rise3_r_reg[3]_290 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4][0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall0_r_reg_n_0_[4] ),
        .Q(\gen_sr_div4.gen_sr[4].sr_fall0_r_reg[4]_267 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4][0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall1_r_reg_n_0_[4] ),
        .Q(\gen_sr_div4.gen_sr[4].sr_fall1_r_reg[4]_307 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4][0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall2_r_reg_n_0_[4] ),
        .Q(\gen_sr_div4.gen_sr[4].sr_fall2_r_reg[4]_283 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4][0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_fall3_r_reg_n_0_[4] ),
        .Q(\gen_sr_div4.gen_sr[4].sr_fall3_r_reg[4]_259 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4][0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise0_r_reg_n_0_[4] ),
        .Q(\gen_sr_div4.gen_sr[4].sr_rise0_r_reg[4]_299 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4][0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise1_r_reg_n_0_[4] ),
        .Q(\gen_sr_div4.gen_sr[4].sr_rise1_r_reg[4]_251 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[4].sr_rise2_r_reg[4][0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise2_r_reg_n_0_[4] ),
        .Q(\gen_sr_div4.gen_sr[4].sr_rise2_r_reg[4]_275 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4][0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[4].mux_rd_rise3_r_reg_n_0_[4] ),
        .Q(\gen_sr_div4.gen_sr[4].sr_rise3_r_reg[4]_291 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5][0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall0_r_reg_n_0_[5] ),
        .Q(\gen_sr_div4.gen_sr[5].sr_fall0_r_reg[5]_268 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5][0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall1_r_reg_n_0_[5] ),
        .Q(\gen_sr_div4.gen_sr[5].sr_fall1_r_reg[5]_308 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5][0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall2_r_reg_n_0_[5] ),
        .Q(\gen_sr_div4.gen_sr[5].sr_fall2_r_reg[5]_284 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5][0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_fall3_r_reg_n_0_[5] ),
        .Q(\gen_sr_div4.gen_sr[5].sr_fall3_r_reg[5]_260 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5][0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise0_r_reg_n_0_[5] ),
        .Q(\gen_sr_div4.gen_sr[5].sr_rise0_r_reg[5]_300 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5][0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise1_r_reg_n_0_[5] ),
        .Q(\gen_sr_div4.gen_sr[5].sr_rise1_r_reg[5]_252 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5][0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise2_r_reg_n_0_[5] ),
        .Q(\gen_sr_div4.gen_sr[5].sr_rise2_r_reg[5]_276 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5][0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[5].mux_rd_rise3_r_reg_n_0_[5] ),
        .Q(\gen_sr_div4.gen_sr[5].sr_rise3_r_reg[5]_292 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6][0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall0_r_reg_n_0_[6] ),
        .Q(\gen_sr_div4.gen_sr[6].sr_fall0_r_reg[6]_269 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6][0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall1_r_reg_n_0_[6] ),
        .Q(\gen_sr_div4.gen_sr[6].sr_fall1_r_reg[6]_309 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6][0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall2_r_reg_n_0_[6] ),
        .Q(\gen_sr_div4.gen_sr[6].sr_fall2_r_reg[6]_285 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6][0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_fall3_r_reg_n_0_[6] ),
        .Q(\gen_sr_div4.gen_sr[6].sr_fall3_r_reg[6]_261 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6][0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise0_r_reg_n_0_[6] ),
        .Q(\gen_sr_div4.gen_sr[6].sr_rise0_r_reg[6]_301 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6][0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise1_r_reg_n_0_[6] ),
        .Q(\gen_sr_div4.gen_sr[6].sr_rise1_r_reg[6]_253 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6][0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise2_r_reg_n_0_[6] ),
        .Q(\gen_sr_div4.gen_sr[6].sr_rise2_r_reg[6]_277 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6][0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[6].mux_rd_rise3_r_reg_n_0_[6] ),
        .Q(\gen_sr_div4.gen_sr[6].sr_rise3_r_reg[6]_293 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7][0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall0_r_reg_n_0_[7] ),
        .Q(\gen_sr_div4.gen_sr[7].sr_fall0_r_reg[7]_270 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7][0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall1_r_reg_n_0_[7] ),
        .Q(\gen_sr_div4.gen_sr[7].sr_fall1_r_reg[7]_310 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7][0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall2_r_reg_n_0_[7] ),
        .Q(\gen_sr_div4.gen_sr[7].sr_fall2_r_reg[7]_286 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7][0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_fall3_r_reg_n_0_[7] ),
        .Q(\gen_sr_div4.gen_sr[7].sr_fall3_r_reg[7]_262 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7][0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise0_r_reg_n_0_[7] ),
        .Q(\gen_sr_div4.gen_sr[7].sr_rise0_r_reg[7]_302 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7][0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise1_r_reg_n_0_[7] ),
        .Q(\gen_sr_div4.gen_sr[7].sr_rise1_r_reg[7]_254 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7][0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise2_r_reg_n_0_[7] ),
        .Q(\gen_sr_div4.gen_sr[7].sr_rise2_r_reg[7]_278 ),
        .R(1'b0));
  FDRE \gen_sr_div4.gen_sr[7].sr_rise3_r_reg[7][0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\gen_mux_rd_div4.gen_mux_rd[7].mux_rd_rise3_r_reg_n_0_[7] ),
        .Q(\gen_sr_div4.gen_sr[7].sr_rise3_r_reg[7]_294 ),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFFFCFF00000080)) 
    idelay_ld_done_i_1
       (.I0(idelay_ld_done_i_2_n_0),
        .I1(\cal2_state_r_reg_n_0_[0] ),
        .I2(\cal2_state_r_reg_n_0_[2] ),
        .I3(\cal2_state_r_reg_n_0_[1] ),
        .I4(\cal2_state_r_reg_n_0_[3] ),
        .I5(idelay_ld_done_reg_n_0),
        .O(idelay_ld_done_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair547" *) 
  LUT4 #(
    .INIT(16'h0002)) 
    idelay_ld_done_i_2
       (.I0(tap_inc_wait_cnt_reg[2]),
        .I1(tap_inc_wait_cnt_reg[0]),
        .I2(tap_inc_wait_cnt_reg[1]),
        .I3(tap_inc_wait_cnt_reg[3]),
        .O(idelay_ld_done_i_2_n_0));
  FDRE idelay_ld_done_reg
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(idelay_ld_done_i_1_n_0),
        .Q(idelay_ld_done_reg_n_0),
        .R(cal2_done_r_reg_0));
  LUT4 #(
    .INIT(16'h2F20)) 
    idelay_ld_i_1
       (.I0(\gen_pat_match_div4.pat_data_match_valid_r_reg_n_0 ),
        .I1(\cal2_state_r_reg_n_0_[2] ),
        .I2(idelay_ld_i_2_n_0),
        .I3(idelay_ld),
        .O(idelay_ld_i_1_n_0));
  LUT6 #(
    .INIT(64'h0000540400000000)) 
    idelay_ld_i_2
       (.I0(\cal2_state_r_reg_n_0_[3] ),
        .I1(\cal2_state_r[2]_i_2_n_0 ),
        .I2(\cal2_state_r_reg_n_0_[2] ),
        .I3(idelay_ld_done_i_2_n_0),
        .I4(\cal2_state_r_reg_n_0_[1] ),
        .I5(\cal2_state_r_reg_n_0_[0] ),
        .O(idelay_ld_i_2_n_0));
  FDRE idelay_ld_reg
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(idelay_ld_i_1_n_0),
        .Q(idelay_ld),
        .R(cal2_if_reset_reg_0));
  LUT6 #(
    .INIT(64'hFFFFFFFF888888F8)) 
    \idelay_tap_cnt_r[0][0][4]_i_1 
       (.I0(\idelay_tap_cnt_r_reg[0][4][4]_0 ),
        .I1(\idelay_tap_cnt_r_reg[0][0][4] ),
        .I2(\idelay_tap_cnt_r[0][0][4]_i_5_n_0 ),
        .I3(Q[0]),
        .I4(Q[1]),
        .I5(\idelay_tap_cnt_r_reg[0][0][4]_0 ),
        .O(\po_stg2_wrcal_cnt_reg[0]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair548" *) 
  LUT4 #(
    .INIT(16'h0010)) 
    \idelay_tap_cnt_r[0][0][4]_i_5 
       (.I0(Q[2]),
        .I1(Q[3]),
        .I2(idelay_ld),
        .I3(idelay_ce_int),
        .O(\idelay_tap_cnt_r[0][0][4]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFF202020)) 
    \idelay_tap_cnt_r[0][1][4]_i_1 
       (.I0(Q[0]),
        .I1(Q[1]),
        .I2(\idelay_tap_cnt_r[0][0][4]_i_5_n_0 ),
        .I3(\idelay_tap_cnt_r_reg[0][1][4] ),
        .I4(\idelay_tap_cnt_r_reg[0][5][4] ),
        .I5(\idelay_tap_cnt_r_reg[0][0][4]_0 ),
        .O(\po_stg2_wrcal_cnt_reg[0]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair534" *) 
  LUT5 #(
    .INIT(32'hFFFFAEAA)) 
    \idelay_tap_cnt_r[0][2][4]_i_1 
       (.I0(\idelay_tap_cnt_r_reg[0][2][4] ),
        .I1(\idelay_tap_cnt_r[0][0][4]_i_5_n_0 ),
        .I2(Q[0]),
        .I3(Q[1]),
        .I4(\idelay_tap_cnt_r_reg[0][0][4]_0 ),
        .O(\po_stg2_wrcal_cnt_reg[0]_8 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF8080FF80)) 
    \idelay_tap_cnt_r[0][3][4]_i_1 
       (.I0(Q[1]),
        .I1(Q[0]),
        .I2(\idelay_tap_cnt_r[0][0][4]_i_5_n_0 ),
        .I3(\idelay_tap_cnt_r_reg[0][1][4] ),
        .I4(\idelay_tap_cnt_r_reg[0][7][4] ),
        .I5(\idelay_tap_cnt_r_reg[0][0][4]_0 ),
        .O(\po_stg2_wrcal_cnt_reg[1]_2 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF4444444F)) 
    \idelay_tap_cnt_r[0][4][4]_i_1 
       (.I0(\idelay_tap_cnt_r_reg[0][4][4] ),
        .I1(\idelay_tap_cnt_r_reg[0][4][4]_0 ),
        .I2(Q[0]),
        .I3(Q[1]),
        .I4(\idelay_tap_cnt_r[0][4][4]_i_3_n_0 ),
        .I5(\idelay_tap_cnt_r_reg[0][4][4]_1 ),
        .O(\po_stg2_wrcal_cnt_reg[0]_3 ));
  (* SOFT_HLUTNM = "soft_lutpair548" *) 
  LUT4 #(
    .INIT(16'hFBFF)) 
    \idelay_tap_cnt_r[0][4][4]_i_3 
       (.I0(Q[3]),
        .I1(idelay_ld),
        .I2(idelay_ce_int),
        .I3(Q[2]),
        .O(\idelay_tap_cnt_r[0][4][4]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF0404FF04)) 
    \idelay_tap_cnt_r[0][5][4]_i_1 
       (.I0(\idelay_tap_cnt_r[0][4][4]_i_3_n_0 ),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(\idelay_tap_cnt_r_reg[0][5][4] ),
        .I4(\idelay_tap_cnt_r_reg[0][5][4]_0 ),
        .I5(\idelay_tap_cnt_r_reg[0][0][4]_0 ),
        .O(\po_stg2_wrcal_cnt_reg[0]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair536" *) 
  LUT5 #(
    .INIT(32'hFFFFAABA)) 
    \idelay_tap_cnt_r[0][6][4]_i_1 
       (.I0(\idelay_tap_cnt_r_reg[0][6][4] ),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(\idelay_tap_cnt_r[0][4][4]_i_3_n_0 ),
        .I4(\idelay_tap_cnt_r_reg[0][0][4]_0 ),
        .O(\po_stg2_wrcal_cnt_reg[0]_6 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF404040FF)) 
    \idelay_tap_cnt_r[0][7][4]_i_1 
       (.I0(\idelay_tap_cnt_r[0][4][4]_i_3_n_0 ),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(\idelay_tap_cnt_r_reg[0][7][4] ),
        .I4(\idelay_tap_cnt_r_reg[0][5][4]_0 ),
        .I5(\idelay_tap_cnt_r_reg[0][0][4]_0 ),
        .O(\po_stg2_wrcal_cnt_reg[1]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair535" *) 
  LUT5 #(
    .INIT(32'h7FFFFFFF)) 
    \init_state_r[2]_i_35 
       (.I0(wrcal_done_reg_0),
        .I1(\init_state_r[3]_i_13 ),
        .I2(wrlvl_done_r1),
        .I3(\init_state_r[2]_i_14 ),
        .I4(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[508] ),
        .O(wrcal_done_reg_2));
  LUT3 #(
    .INIT(8'hF7)) 
    \init_state_r[3]_i_23 
       (.I0(wrcal_done_reg_0),
        .I1(\init_state_r[3]_i_13 ),
        .I2(\init_state_r[3]_i_13_0 ),
        .O(wrcal_done_reg_3));
  (* SOFT_HLUTNM = "soft_lutpair552" *) 
  LUT3 #(
    .INIT(8'hFE)) 
    \init_state_r[4]_i_28 
       (.I0(wrlvl_byte_redo),
        .I1(\init_state_r[4]_i_27 ),
        .I2(wrcal_done_reg_0),
        .O(wrlvl_byte_redo_reg_0));
  LUT6 #(
    .INIT(64'hFFFFFFFF40404050)) 
    \input_[1].iserdes_dq_.idelay_dq.idelaye2_i_2 
       (.I0(\input_[9].iserdes_dq_.idelay_dq.idelaye2 [0]),
        .I1(calib_in_common),
        .I2(idelay_ld),
        .I3(\input_[9].iserdes_dq_.idelay_dq.idelaye2_0 ),
        .I4(\input_[9].iserdes_dq_.idelay_dq.idelaye2_1 ),
        .I5(idelay_ld_rst),
        .O(LD0));
  LUT6 #(
    .INIT(64'hFFFFFFFF40404050)) 
    \input_[1].iserdes_dq_.idelay_dq.idelaye2_i_2__0 
       (.I0(\input_[9].iserdes_dq_.idelay_dq.idelaye2 [1]),
        .I1(calib_in_common),
        .I2(idelay_ld),
        .I3(\input_[9].iserdes_dq_.idelay_dq.idelaye2_0 ),
        .I4(\input_[9].iserdes_dq_.idelay_dq.idelaye2_1 ),
        .I5(idelay_ld_rst_10),
        .O(LD0_3));
  LUT6 #(
    .INIT(64'hFFFFFFFF44005400)) 
    \input_[2].iserdes_dq_.idelay_dq.idelaye2_i_2 
       (.I0(\input_[9].iserdes_dq_.idelay_dq.idelaye2 [0]),
        .I1(calib_in_common),
        .I2(\input_[9].iserdes_dq_.idelay_dq.idelaye2_0 ),
        .I3(idelay_ld),
        .I4(\input_[9].iserdes_dq_.idelay_dq.idelaye2_1 ),
        .I5(idelay_ld_rst_7),
        .O(LD0_0));
  LUT6 #(
    .INIT(64'hFFFFFFFF45004400)) 
    \input_[2].iserdes_dq_.idelay_dq.idelaye2_i_2__0 
       (.I0(\input_[9].iserdes_dq_.idelay_dq.idelaye2 [0]),
        .I1(calib_in_common),
        .I2(\input_[9].iserdes_dq_.idelay_dq.idelaye2_0 ),
        .I3(idelay_ld),
        .I4(\input_[9].iserdes_dq_.idelay_dq.idelaye2_1 ),
        .I5(idelay_ld_rst_8),
        .O(LD0_1));
  LUT6 #(
    .INIT(64'hFFFFFFFF54440000)) 
    \input_[2].iserdes_dq_.idelay_dq.idelaye2_i_2__1 
       (.I0(\input_[9].iserdes_dq_.idelay_dq.idelaye2 [0]),
        .I1(calib_in_common),
        .I2(\input_[9].iserdes_dq_.idelay_dq.idelaye2_1 ),
        .I3(\input_[9].iserdes_dq_.idelay_dq.idelaye2_0 ),
        .I4(idelay_ld),
        .I5(idelay_ld_rst_9),
        .O(LD0_2));
  LUT6 #(
    .INIT(64'hFFFFFFFF44005400)) 
    \input_[2].iserdes_dq_.idelay_dq.idelaye2_i_2__2 
       (.I0(\input_[9].iserdes_dq_.idelay_dq.idelaye2 [1]),
        .I1(calib_in_common),
        .I2(\input_[9].iserdes_dq_.idelay_dq.idelaye2_0 ),
        .I3(idelay_ld),
        .I4(\input_[9].iserdes_dq_.idelay_dq.idelaye2_1 ),
        .I5(idelay_ld_rst_11),
        .O(LD0_4));
  LUT6 #(
    .INIT(64'hFFFFFFFF45004400)) 
    \input_[2].iserdes_dq_.idelay_dq.idelaye2_i_2__3 
       (.I0(\input_[9].iserdes_dq_.idelay_dq.idelaye2 [1]),
        .I1(calib_in_common),
        .I2(\input_[9].iserdes_dq_.idelay_dq.idelaye2_0 ),
        .I3(idelay_ld),
        .I4(\input_[9].iserdes_dq_.idelay_dq.idelaye2_1 ),
        .I5(idelay_ld_rst_12),
        .O(LD0_5));
  LUT6 #(
    .INIT(64'hFFFFFFFF54440000)) 
    \input_[2].iserdes_dq_.idelay_dq.idelaye2_i_2__4 
       (.I0(\input_[9].iserdes_dq_.idelay_dq.idelaye2 [1]),
        .I1(calib_in_common),
        .I2(\input_[9].iserdes_dq_.idelay_dq.idelaye2_1 ),
        .I3(\input_[9].iserdes_dq_.idelay_dq.idelaye2_0 ),
        .I4(idelay_ld),
        .I5(idelay_ld_rst_13),
        .O(LD0_6));
  LUT1 #(
    .INIT(2'h1)) 
    \not_empty_wait_cnt[0]_i_1 
       (.I0(\not_empty_wait_cnt_reg_n_0_[0] ),
        .O(p_0_in[0]));
  (* SOFT_HLUTNM = "soft_lutpair553" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \not_empty_wait_cnt[1]_i_1 
       (.I0(\not_empty_wait_cnt_reg_n_0_[0] ),
        .I1(\not_empty_wait_cnt_reg_n_0_[1] ),
        .O(p_0_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair553" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \not_empty_wait_cnt[2]_i_1 
       (.I0(\not_empty_wait_cnt_reg_n_0_[1] ),
        .I1(\not_empty_wait_cnt_reg_n_0_[0] ),
        .I2(\not_empty_wait_cnt_reg_n_0_[2] ),
        .O(p_0_in[2]));
  (* SOFT_HLUTNM = "soft_lutpair538" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \not_empty_wait_cnt[3]_i_1 
       (.I0(\not_empty_wait_cnt_reg_n_0_[3] ),
        .I1(\not_empty_wait_cnt_reg_n_0_[1] ),
        .I2(\not_empty_wait_cnt_reg_n_0_[2] ),
        .I3(\not_empty_wait_cnt_reg_n_0_[0] ),
        .O(p_0_in[3]));
  LUT6 #(
    .INIT(64'hFFFEFFFFFFFFFFFF)) 
    \not_empty_wait_cnt[4]_i_1 
       (.I0(\not_empty_wait_cnt_reg[4]_0 ),
        .I1(\cal2_state_r_reg_n_0_[3] ),
        .I2(\cal2_state_r_reg_n_0_[2] ),
        .I3(\cal2_state_r_reg_n_0_[1] ),
        .I4(\cal2_state_r_reg_n_0_[0] ),
        .I5(wrcal_rd_wait),
        .O(\not_empty_wait_cnt[4]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair538" *) 
  LUT5 #(
    .INIT(32'h6AAAAAAA)) 
    \not_empty_wait_cnt[4]_i_2 
       (.I0(\not_empty_wait_cnt_reg_n_0_[4] ),
        .I1(\not_empty_wait_cnt_reg_n_0_[0] ),
        .I2(\not_empty_wait_cnt_reg_n_0_[2] ),
        .I3(\not_empty_wait_cnt_reg_n_0_[1] ),
        .I4(\not_empty_wait_cnt_reg_n_0_[3] ),
        .O(p_0_in[4]));
  FDRE \not_empty_wait_cnt_reg[0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(p_0_in[0]),
        .Q(\not_empty_wait_cnt_reg_n_0_[0] ),
        .R(\not_empty_wait_cnt[4]_i_1_n_0 ));
  FDRE \not_empty_wait_cnt_reg[1] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(p_0_in[1]),
        .Q(\not_empty_wait_cnt_reg_n_0_[1] ),
        .R(\not_empty_wait_cnt[4]_i_1_n_0 ));
  FDRE \not_empty_wait_cnt_reg[2] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(p_0_in[2]),
        .Q(\not_empty_wait_cnt_reg_n_0_[2] ),
        .R(\not_empty_wait_cnt[4]_i_1_n_0 ));
  FDRE \not_empty_wait_cnt_reg[3] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(p_0_in[3]),
        .Q(\not_empty_wait_cnt_reg_n_0_[3] ),
        .R(\not_empty_wait_cnt[4]_i_1_n_0 ));
  FDRE \not_empty_wait_cnt_reg[4] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(p_0_in[4]),
        .Q(\not_empty_wait_cnt_reg_n_0_[4] ),
        .R(\not_empty_wait_cnt[4]_i_1_n_0 ));
  FDRE \po_stg2_wrcal_cnt_reg[0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\wrcal_dqs_cnt_r_reg_n_0_[0] ),
        .Q(Q[0]),
        .R(1'b0));
  FDRE \po_stg2_wrcal_cnt_reg[1] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\wrcal_dqs_cnt_r_reg_n_0_[1] ),
        .Q(Q[1]),
        .R(1'b0));
  FDRE \po_stg2_wrcal_cnt_reg[2] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(\wrcal_dqs_cnt_r_reg_n_0_[2] ),
        .Q(Q[2]),
        .R(1'b0));
  FDRE \po_stg2_wrcal_cnt_reg[3] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(wrcal_dqs_cnt_r),
        .Q(Q[3]),
        .R(1'b0));
  FDRE rd_active_r1_reg
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(E),
        .Q(rd_active_r1),
        .R(1'b0));
  (* srl_name = "\u_mig_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/rd_active_r3_reg_srl2 " *) 
  SRL16E rd_active_r3_reg_srl2
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(wrcal_pat_resume_reg_0),
        .D(rd_active_r1),
        .Q(rd_active_r3_reg_srl2_n_0));
  FDRE rd_active_r_reg
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(phy_rddata_en),
        .Q(E),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair555" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \tap_inc_wait_cnt[0]_i_1 
       (.I0(tap_inc_wait_cnt_reg[0]),
        .O(p_0_in__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair555" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \tap_inc_wait_cnt[1]_i_1 
       (.I0(tap_inc_wait_cnt_reg[1]),
        .I1(tap_inc_wait_cnt_reg[0]),
        .O(p_0_in__0[1]));
  (* SOFT_HLUTNM = "soft_lutpair550" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \tap_inc_wait_cnt[2]_i_1 
       (.I0(tap_inc_wait_cnt_reg[2]),
        .I1(tap_inc_wait_cnt_reg[0]),
        .I2(tap_inc_wait_cnt_reg[1]),
        .O(p_0_in__0[2]));
  LUT5 #(
    .INIT(32'hFFFFAFEF)) 
    \tap_inc_wait_cnt[3]_i_1 
       (.I0(\cal2_state_r_reg_n_0_[3] ),
        .I1(\cal2_state_r_reg_n_0_[1] ),
        .I2(\cal2_state_r_reg_n_0_[2] ),
        .I3(\cal2_state_r_reg_n_0_[0] ),
        .I4(\not_empty_wait_cnt_reg[4]_0 ),
        .O(\tap_inc_wait_cnt[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair550" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \tap_inc_wait_cnt[3]_i_2 
       (.I0(tap_inc_wait_cnt_reg[3]),
        .I1(tap_inc_wait_cnt_reg[1]),
        .I2(tap_inc_wait_cnt_reg[0]),
        .I3(tap_inc_wait_cnt_reg[2]),
        .O(p_0_in__0[3]));
  FDRE \tap_inc_wait_cnt_reg[0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(p_0_in__0[0]),
        .Q(tap_inc_wait_cnt_reg[0]),
        .R(\tap_inc_wait_cnt[3]_i_1_n_0 ));
  FDRE \tap_inc_wait_cnt_reg[1] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(p_0_in__0[1]),
        .Q(tap_inc_wait_cnt_reg[1]),
        .R(\tap_inc_wait_cnt[3]_i_1_n_0 ));
  FDRE \tap_inc_wait_cnt_reg[2] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(p_0_in__0[2]),
        .Q(tap_inc_wait_cnt_reg[2]),
        .R(\tap_inc_wait_cnt[3]_i_1_n_0 ));
  FDRE \tap_inc_wait_cnt_reg[3] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(p_0_in__0[3]),
        .Q(tap_inc_wait_cnt_reg[3]),
        .R(\tap_inc_wait_cnt[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair552" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \wl_tap_count_r[5]_i_3 
       (.I0(wrlvl_byte_redo),
        .I1(wrlvl_byte_redo_r),
        .O(done_dqs_dec238_out));
  (* SOFT_HLUTNM = "soft_lutpair539" *) 
  LUT5 #(
    .INIT(32'h45454500)) 
    wrcal_done_i_1
       (.I0(\not_empty_wait_cnt_reg[4]_0 ),
        .I1(wrcal_sanity_chk_r_reg_n_0),
        .I2(wrcal_sanity_chk),
        .I3(wrcal_done_reg_0),
        .I4(cal2_done_r),
        .O(wrcal_done_i_1_n_0));
  FDRE wrcal_done_reg
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(wrcal_done_i_1_n_0),
        .Q(wrcal_done_reg_0),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair551" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \wrcal_dqs_cnt_r[0]_i_1 
       (.I0(\wrcal_dqs_cnt_r_reg_n_0_[0] ),
        .I1(\cal2_state_r_reg_n_0_[2] ),
        .O(\wrcal_dqs_cnt_r[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair551" *) 
  LUT3 #(
    .INIT(8'h06)) 
    \wrcal_dqs_cnt_r[1]_i_1 
       (.I0(\wrcal_dqs_cnt_r_reg_n_0_[0] ),
        .I1(\wrcal_dqs_cnt_r_reg_n_0_[1] ),
        .I2(\cal2_state_r_reg_n_0_[2] ),
        .O(\wrcal_dqs_cnt_r[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair549" *) 
  LUT4 #(
    .INIT(16'h006A)) 
    \wrcal_dqs_cnt_r[2]_i_1 
       (.I0(\wrcal_dqs_cnt_r_reg_n_0_[2] ),
        .I1(\wrcal_dqs_cnt_r_reg_n_0_[1] ),
        .I2(\wrcal_dqs_cnt_r_reg_n_0_[0] ),
        .I3(\cal2_state_r_reg_n_0_[2] ),
        .O(\wrcal_dqs_cnt_r[2]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'h04)) 
    \wrcal_dqs_cnt_r[3]_i_1 
       (.I0(\cal2_state_r_reg_n_0_[3] ),
        .I1(\wrcal_dqs_cnt_r[3]_i_3_n_0 ),
        .I2(\cal2_state_r_reg_n_0_[0] ),
        .O(\wrcal_dqs_cnt_r[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair541" *) 
  LUT5 #(
    .INIT(32'h00007F80)) 
    \wrcal_dqs_cnt_r[3]_i_2 
       (.I0(\wrcal_dqs_cnt_r_reg_n_0_[1] ),
        .I1(\wrcal_dqs_cnt_r_reg_n_0_[0] ),
        .I2(\wrcal_dqs_cnt_r_reg_n_0_[2] ),
        .I3(wrcal_dqs_cnt_r),
        .I4(\cal2_state_r_reg_n_0_[2] ),
        .O(\wrcal_dqs_cnt_r[3]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h55C800C800000000)) 
    \wrcal_dqs_cnt_r[3]_i_3 
       (.I0(wrcal_sanity_chk_r_reg_n_0),
        .I1(\wrcal_dqs_cnt_r[3]_i_4_n_0 ),
        .I2(prech_done),
        .I3(\cal2_state_r_reg_n_0_[2] ),
        .I4(wrcal_sanity_chk),
        .I5(\cal2_state_r_reg_n_0_[1] ),
        .O(\wrcal_dqs_cnt_r[3]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair541" *) 
  LUT4 #(
    .INIT(16'hFF7F)) 
    \wrcal_dqs_cnt_r[3]_i_4 
       (.I0(\wrcal_dqs_cnt_r_reg_n_0_[1] ),
        .I1(\wrcal_dqs_cnt_r_reg_n_0_[0] ),
        .I2(\wrcal_dqs_cnt_r_reg_n_0_[2] ),
        .I3(wrcal_dqs_cnt_r),
        .O(\wrcal_dqs_cnt_r[3]_i_4_n_0 ));
  (* syn_maxfan = "10" *) 
  FDRE \wrcal_dqs_cnt_r_reg[0] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(\wrcal_dqs_cnt_r[3]_i_1_n_0 ),
        .D(\wrcal_dqs_cnt_r[0]_i_1_n_0 ),
        .Q(\wrcal_dqs_cnt_r_reg_n_0_[0] ),
        .R(cal2_done_r_reg_0));
  (* syn_maxfan = "10" *) 
  FDRE \wrcal_dqs_cnt_r_reg[1] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(\wrcal_dqs_cnt_r[3]_i_1_n_0 ),
        .D(\wrcal_dqs_cnt_r[1]_i_1_n_0 ),
        .Q(\wrcal_dqs_cnt_r_reg_n_0_[1] ),
        .R(cal2_done_r_reg_0));
  (* syn_maxfan = "10" *) 
  FDRE \wrcal_dqs_cnt_r_reg[2] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(\wrcal_dqs_cnt_r[3]_i_1_n_0 ),
        .D(\wrcal_dqs_cnt_r[2]_i_1_n_0 ),
        .Q(\wrcal_dqs_cnt_r_reg_n_0_[2] ),
        .R(cal2_done_r_reg_0));
  (* syn_maxfan = "10" *) 
  FDRE \wrcal_dqs_cnt_r_reg[3] 
       (.C(wrcal_pat_resume_reg_0),
        .CE(\wrcal_dqs_cnt_r[3]_i_1_n_0 ),
        .D(\wrcal_dqs_cnt_r[3]_i_2_n_0 ),
        .Q(wrcal_dqs_cnt_r),
        .R(cal2_done_r_reg_0));
  (* srl_name = "\u_mig_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_wrcal/wrcal_pat_resume_r2_reg_srl2 " *) 
  SRL16E wrcal_pat_resume_r2_reg_srl2
       (.A0(1'b1),
        .A1(1'b0),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(wrcal_pat_resume_reg_0),
        .D(wrcal_pat_resume_r),
        .Q(wrcal_pat_resume_r2_reg_srl2_n_0));
  LUT5 #(
    .INIT(32'hF8FFF800)) 
    wrcal_pat_resume_r_i_1
       (.I0(\cal2_state_r_reg_n_0_[2] ),
        .I1(idelay_ld_done_reg_n_0),
        .I2(\cal2_state_r_reg_n_0_[1] ),
        .I3(wrcal_pat_resume_r_i_2_n_0),
        .I4(wrcal_pat_resume_r),
        .O(wrcal_pat_resume_r_i_1_n_0));
  LUT6 #(
    .INIT(64'h08000800033C003C)) 
    wrcal_pat_resume_r_i_2
       (.I0(\cal2_state_r[3]_i_7_n_0 ),
        .I1(\cal2_state_r_reg_n_0_[0] ),
        .I2(\cal2_state_r_reg_n_0_[3] ),
        .I3(\cal2_state_r_reg_n_0_[2] ),
        .I4(wrcal_pat_resume_r_i_3_n_0),
        .I5(\cal2_state_r_reg_n_0_[1] ),
        .O(wrcal_pat_resume_r_i_2_n_0));
  LUT6 #(
    .INIT(64'h0000800000000000)) 
    wrcal_pat_resume_r_i_3
       (.I0(tap_inc_wait_cnt_reg[2]),
        .I1(idelay_ld_done_reg_n_0),
        .I2(tap_inc_wait_cnt_reg[0]),
        .I3(tap_inc_wait_cnt_reg[1]),
        .I4(wrcal_sanity_chk_r_reg_n_0),
        .I5(tap_inc_wait_cnt_reg[3]),
        .O(wrcal_pat_resume_r_i_3_n_0));
  FDRE wrcal_pat_resume_r_reg
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(wrcal_pat_resume_r_i_1_n_0),
        .Q(wrcal_pat_resume_r),
        .R(cal2_done_r_reg_0));
  FDRE wrcal_pat_resume_reg
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(wrcal_pat_resume_r2_reg_srl2_n_0),
        .Q(wrcal_resume_w),
        .R(1'b0));
  FDRE wrcal_prech_req_reg
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(cal2_prech_req_r),
        .Q(wrcal_prech_req),
        .R(cal2_done_r_reg_0));
  LUT6 #(
    .INIT(64'hFFFFFFFF00004000)) 
    wrcal_sanity_chk_done_i_1
       (.I0(\cal2_state_r_reg_n_0_[3] ),
        .I1(\cal2_state_r_reg_n_0_[2] ),
        .I2(wrcal_sanity_chk_r_reg_n_0),
        .I3(\cal2_state_r_reg_n_0_[1] ),
        .I4(\cal2_state_r_reg_n_0_[0] ),
        .I5(wrcal_sanity_chk_done_reg_0),
        .O(wrcal_sanity_chk_done_i_1_n_0));
  FDRE wrcal_sanity_chk_done_reg
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(wrcal_sanity_chk_done_i_1_n_0),
        .Q(wrcal_sanity_chk_done_reg_0),
        .R(cal2_if_reset_reg_0));
  FDRE wrcal_sanity_chk_r_reg
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(wrcal_sanity_chk),
        .Q(wrcal_sanity_chk_r_reg_n_0),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair539" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \wrdq_div1_4to1_wrcal_first.phy_wrdata[445]_i_1 
       (.I0(wrcal_done_reg_0),
        .O(wrcal_done_reg_1));
  (* SOFT_HLUTNM = "soft_lutpair535" *) 
  LUT2 #(
    .INIT(4'h7)) 
    \wrdq_div1_4to1_wrcal_first.phy_wrdata[508]_i_1 
       (.I0(wrcal_done_reg_0),
        .I1(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[508] ),
        .O(wrcal_done_reg_4));
  FDRE wrlvl_byte_done_r_reg
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(wrlvl_byte_done),
        .Q(wrlvl_byte_done_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0EFFFFFF0E000000)) 
    wrlvl_byte_redo_i_1
       (.I0(\gen_pat_match_div4.early2_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.early1_data_match_r_reg_n_0 ),
        .I2(\cal2_state_r_reg_n_0_[1] ),
        .I3(wrlvl_byte_redo_i_2_n_0),
        .I4(\cal2_state_r_reg_n_0_[0] ),
        .I5(wrlvl_byte_redo),
        .O(wrlvl_byte_redo_i_1_n_0));
  LUT6 #(
    .INIT(64'h0000000022222E22)) 
    wrlvl_byte_redo_i_2
       (.I0(wrlvl_byte_redo_i_3_n_0),
        .I1(\cal2_state_r_reg_n_0_[1] ),
        .I2(\cal2_state_r_reg_n_0_[2] ),
        .I3(wrlvl_byte_done),
        .I4(wrlvl_byte_done_r),
        .I5(\cal2_state_r_reg_n_0_[3] ),
        .O(wrlvl_byte_redo_i_2_n_0));
  LUT6 #(
    .INIT(64'h0000000000005040)) 
    wrlvl_byte_redo_i_3
       (.I0(\gen_pat_match_div4.pat_data_match_r_reg_n_0 ),
        .I1(\gen_pat_match_div4.early1_data_match_r_reg_n_0 ),
        .I2(\gen_pat_match_div4.pat_data_match_valid_r_reg_n_0 ),
        .I3(\gen_pat_match_div4.early2_data_match_r_reg_n_0 ),
        .I4(wrcal_sanity_chk_r_reg_n_0),
        .I5(\cal2_state_r_reg_n_0_[2] ),
        .O(wrlvl_byte_redo_i_3_n_0));
  FDRE wrlvl_byte_redo_reg
       (.C(wrcal_pat_resume_reg_0),
        .CE(1'b1),
        .D(wrlvl_byte_redo_i_1_n_0),
        .Q(wrlvl_byte_redo),
        .R(cal2_done_r_reg_0));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_phy_wrlvl" *) 
module mig_mig_7series_v4_2_ddr_phy_wrlvl
   (wr_level_done_r5,
    wrlvl_byte_redo_r,
    dqs_po_dec_done,
    dqs_po_en_stg2_f,
    po_cnt_dec_reg_0,
    wr_level_done_reg_0,
    wrlvl_rank_done,
    \FSM_sequential_wl_state_r_reg[4]_0 ,
    \dqs_count_r_reg[3]_0 ,
    \dqs_count_r_reg[2]_rep__0_0 ,
    \calib_sel_reg[1] ,
    \calib_sel_reg[1]_0 ,
    \calib_sel_reg[1]_1 ,
    dqs_wl_po_stg2_c_incdec_reg_0,
    \calib_sel_reg[1]_2 ,
    \calib_sel_reg[1]_3 ,
    \calib_sel_reg[1]_4 ,
    \calib_sel_reg[0] ,
    \calib_sel_reg[1]_5 ,
    \calib_sel_reg[1]_6 ,
    \calib_sel_reg[1]_7 ,
    dqs_wl_po_stg2_c_incdec_reg_1,
    \calib_sel_reg[1]_8 ,
    \calib_sel_reg[1]_9 ,
    \calib_sel_reg[1]_10 ,
    \calib_sel_reg[0]_0 ,
    C_po_coarse_enable26_out,
    \gen_byte_sel_div2.calib_in_common_reg ,
    \gen_byte_sel_div2.calib_in_common_reg_0 ,
    C_po_fine_enable23_out,
    \gen_byte_sel_div2.calib_in_common_reg_1 ,
    \gen_byte_sel_div2.calib_in_common_reg_2 ,
    dqs_po_stg2_f_incdec_reg_0,
    dqs_po_stg2_f_incdec_reg_1,
    dqs_po_stg2_f_incdec_reg_2,
    dqs_po_stg2_f_incdec_reg_3,
    dqs_po_stg2_f_incdec_reg_4,
    dqs_po_stg2_f_incdec_reg_5,
    dqs_po_stg2_f_incdec_reg_6,
    dqs_po_stg2_f_incdec_reg_7,
    C_po_fine_inc29_out,
    dqs_po_stg2_f_incdec_reg_8,
    dqs_po_stg2_f_incdec_reg_9,
    \po_stg2_wrcal_cnt_reg[2] ,
    \po_stg2_wrcal_cnt_reg[2]_0 ,
    \FSM_sequential_wl_state_r_reg[2]_0 ,
    \dqs_count_r_reg[0]_rep_0 ,
    \dqs_count_r_reg[1]_rep_0 ,
    done_dqs_tap_inc,
    SS,
    cmd_delay_start0,
    wrlvl_byte_done,
    Q,
    \dqs_count_r_reg[2]_rep__0_1 ,
    wrlvl_byte_redo,
    wr_level_start_r_reg_0,
    \fine_dec_cnt_reg[5]_0 ,
    \corse_inc_reg[6][2]_0 ,
    \wl_dqs_tap_count_r_reg[0][5][5]_0 ,
    wl_sm_start,
    phaser_out,
    phaser_out_0,
    po_enstg2_f,
    calib_in_common,
    phaser_out_1,
    ck_po_stg2_f_indec,
    \single_rank.done_dqs_dec_reg_0 ,
    done_dqs_dec238_out,
    \dqs_count_r_reg[3]_1 ,
    \corse_cnt_reg[7][0]_0 ,
    \corse_cnt_reg[7][0]_1 ,
    \corse_cnt_reg[6][0]_0 ,
    \corse_cnt_reg[5][0]_0 ,
    \corse_cnt_reg[4][0]_0 ,
    \corse_cnt_reg[3][0]_0 ,
    \FSM_sequential_wl_state_r_reg[0]_0 ,
    \wrlvl_redo_corse_inc[2]_i_4_0 ,
    \po_rdval_cnt_reg[7]_0 ,
    \po_rdval_cnt_reg[8]_0 ,
    \po_rdval_cnt_reg[0]_0 ,
    \po_rdval_cnt_reg[1]_0 ,
    \po_rdval_cnt_reg[2]_0 ,
    \po_rdval_cnt_reg[3]_0 ,
    \po_rdval_cnt_reg[4]_0 ,
    \po_rdval_cnt_reg[5]_0 ,
    \po_rdval_cnt_reg[6]_0 ,
    \wrlvl_redo_corse_inc_reg[2]_0 ,
    pi_fine_dly_dec_done,
    delaydec_cnt_r10_in,
    \fine_inc_reg[6][3]_0 ,
    \dqs_count_r_reg[2]_rep__0_2 ,
    \corse_dec_reg[7][0]_0 ,
    \wait_cnt_reg[0]_0 ,
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_0 ,
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_1 ,
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_2 ,
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_3 ,
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_4 ,
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_5 ,
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_6 ,
    \gen_rd[0].rd_data_rise_wl_r_reg[0]_7 ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_0 ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_1 ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_2 ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_3 ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_4 ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_5 ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_6 ,
    \gen_rd[1].rd_data_rise_wl_r_reg[1]_7 ,
    \gen_rd[2].rd_data_rise_wl_r_reg[2]_0 ,
    \gen_rd[2].rd_data_rise_wl_r_reg[2]_1 ,
    \gen_rd[2].rd_data_rise_wl_r_reg[2]_2 ,
    \gen_rd[2].rd_data_rise_wl_r_reg[2]_3 ,
    \gen_rd[2].rd_data_rise_wl_r_reg[2]_4 ,
    \gen_rd[2].rd_data_rise_wl_r_reg[2]_5 ,
    \gen_rd[2].rd_data_rise_wl_r_reg[2]_6 ,
    \gen_rd[2].rd_data_rise_wl_r_reg[2]_7 ,
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_0 ,
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_1 ,
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_2 ,
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_3 ,
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_4 ,
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_5 ,
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_6 ,
    \gen_rd[3].rd_data_rise_wl_r_reg[3]_7 ,
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_0 ,
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_1 ,
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_2 ,
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_3 ,
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_4 ,
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_5 ,
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_6 ,
    \gen_rd[4].rd_data_rise_wl_r_reg[4]_7 ,
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_0 ,
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_1 ,
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_2 ,
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_3 ,
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_4 ,
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_5 ,
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_6 ,
    \gen_rd[5].rd_data_rise_wl_r_reg[5]_7 ,
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_0 ,
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_1 ,
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_2 ,
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_3 ,
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_4 ,
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_5 ,
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_6 ,
    \gen_rd[6].rd_data_rise_wl_r_reg[6]_7 ,
    \gen_rd[7].rd_data_rise_wl_r_reg[7]_0 ,
    \gen_rd[7].rd_data_rise_wl_r_reg[7]_1 ,
    \gen_rd[7].rd_data_rise_wl_r_reg[7]_2 ,
    \gen_rd[7].rd_data_rise_wl_r_reg[7]_3 ,
    \gen_rd[7].rd_data_rise_wl_r_reg[7]_4 ,
    \gen_rd[7].rd_data_rise_wl_r_reg[7]_5 ,
    \gen_rd[7].rd_data_rise_wl_r_reg[7]_6 ,
    \gen_rd[7].rd_data_rise_wl_r_reg[7]_7 );
  output wr_level_done_r5;
  output wrlvl_byte_redo_r;
  output dqs_po_dec_done;
  output dqs_po_en_stg2_f;
  output po_cnt_dec_reg_0;
  output wr_level_done_reg_0;
  output wrlvl_rank_done;
  output [1:0]\FSM_sequential_wl_state_r_reg[4]_0 ;
  output [0:0]\dqs_count_r_reg[3]_0 ;
  output \dqs_count_r_reg[2]_rep__0_0 ;
  output \calib_sel_reg[1] ;
  output \calib_sel_reg[1]_0 ;
  output \calib_sel_reg[1]_1 ;
  output dqs_wl_po_stg2_c_incdec_reg_0;
  output \calib_sel_reg[1]_2 ;
  output \calib_sel_reg[1]_3 ;
  output \calib_sel_reg[1]_4 ;
  output \calib_sel_reg[0] ;
  output \calib_sel_reg[1]_5 ;
  output \calib_sel_reg[1]_6 ;
  output \calib_sel_reg[1]_7 ;
  output dqs_wl_po_stg2_c_incdec_reg_1;
  output \calib_sel_reg[1]_8 ;
  output \calib_sel_reg[1]_9 ;
  output \calib_sel_reg[1]_10 ;
  output \calib_sel_reg[0]_0 ;
  output C_po_coarse_enable26_out;
  output \gen_byte_sel_div2.calib_in_common_reg ;
  output \gen_byte_sel_div2.calib_in_common_reg_0 ;
  output C_po_fine_enable23_out;
  output \gen_byte_sel_div2.calib_in_common_reg_1 ;
  output \gen_byte_sel_div2.calib_in_common_reg_2 ;
  output dqs_po_stg2_f_incdec_reg_0;
  output dqs_po_stg2_f_incdec_reg_1;
  output dqs_po_stg2_f_incdec_reg_2;
  output dqs_po_stg2_f_incdec_reg_3;
  output dqs_po_stg2_f_incdec_reg_4;
  output dqs_po_stg2_f_incdec_reg_5;
  output dqs_po_stg2_f_incdec_reg_6;
  output dqs_po_stg2_f_incdec_reg_7;
  output C_po_fine_inc29_out;
  output dqs_po_stg2_f_incdec_reg_8;
  output dqs_po_stg2_f_incdec_reg_9;
  output \po_stg2_wrcal_cnt_reg[2] ;
  output \po_stg2_wrcal_cnt_reg[2]_0 ;
  output \FSM_sequential_wl_state_r_reg[2]_0 ;
  output \dqs_count_r_reg[0]_rep_0 ;
  output \dqs_count_r_reg[1]_rep_0 ;
  output done_dqs_tap_inc;
  output [0:0]SS;
  output cmd_delay_start0;
  output wrlvl_byte_done;
  input [0:0]Q;
  input \dqs_count_r_reg[2]_rep__0_1 ;
  input wrlvl_byte_redo;
  input wr_level_start_r_reg_0;
  input [0:0]\fine_dec_cnt_reg[5]_0 ;
  input [1:0]\corse_inc_reg[6][2]_0 ;
  input \wl_dqs_tap_count_r_reg[0][5][5]_0 ;
  input wl_sm_start;
  input phaser_out;
  input phaser_out_0;
  input [0:0]po_enstg2_f;
  input calib_in_common;
  input [2:0]phaser_out_1;
  input ck_po_stg2_f_indec;
  input \single_rank.done_dqs_dec_reg_0 ;
  input done_dqs_dec238_out;
  input [3:0]\dqs_count_r_reg[3]_1 ;
  input \corse_cnt_reg[7][0]_0 ;
  input \corse_cnt_reg[7][0]_1 ;
  input \corse_cnt_reg[6][0]_0 ;
  input \corse_cnt_reg[5][0]_0 ;
  input \corse_cnt_reg[4][0]_0 ;
  input \corse_cnt_reg[3][0]_0 ;
  input \FSM_sequential_wl_state_r_reg[0]_0 ;
  input \wrlvl_redo_corse_inc[2]_i_4_0 ;
  input \po_rdval_cnt_reg[7]_0 ;
  input \po_rdval_cnt_reg[8]_0 ;
  input \po_rdval_cnt_reg[0]_0 ;
  input \po_rdval_cnt_reg[1]_0 ;
  input \po_rdval_cnt_reg[2]_0 ;
  input \po_rdval_cnt_reg[3]_0 ;
  input \po_rdval_cnt_reg[4]_0 ;
  input \po_rdval_cnt_reg[5]_0 ;
  input \po_rdval_cnt_reg[6]_0 ;
  input \wrlvl_redo_corse_inc_reg[2]_0 ;
  input pi_fine_dly_dec_done;
  input delaydec_cnt_r10_in;
  input [1:0]\fine_inc_reg[6][3]_0 ;
  input \dqs_count_r_reg[2]_rep__0_2 ;
  input [1:0]\corse_dec_reg[7][0]_0 ;
  input [0:0]\wait_cnt_reg[0]_0 ;
  input \gen_rd[0].rd_data_rise_wl_r_reg[0]_0 ;
  input \gen_rd[0].rd_data_rise_wl_r_reg[0]_1 ;
  input \gen_rd[0].rd_data_rise_wl_r_reg[0]_2 ;
  input \gen_rd[0].rd_data_rise_wl_r_reg[0]_3 ;
  input \gen_rd[0].rd_data_rise_wl_r_reg[0]_4 ;
  input \gen_rd[0].rd_data_rise_wl_r_reg[0]_5 ;
  input \gen_rd[0].rd_data_rise_wl_r_reg[0]_6 ;
  input \gen_rd[0].rd_data_rise_wl_r_reg[0]_7 ;
  input \gen_rd[1].rd_data_rise_wl_r_reg[1]_0 ;
  input \gen_rd[1].rd_data_rise_wl_r_reg[1]_1 ;
  input \gen_rd[1].rd_data_rise_wl_r_reg[1]_2 ;
  input \gen_rd[1].rd_data_rise_wl_r_reg[1]_3 ;
  input \gen_rd[1].rd_data_rise_wl_r_reg[1]_4 ;
  input \gen_rd[1].rd_data_rise_wl_r_reg[1]_5 ;
  input \gen_rd[1].rd_data_rise_wl_r_reg[1]_6 ;
  input \gen_rd[1].rd_data_rise_wl_r_reg[1]_7 ;
  input \gen_rd[2].rd_data_rise_wl_r_reg[2]_0 ;
  input \gen_rd[2].rd_data_rise_wl_r_reg[2]_1 ;
  input \gen_rd[2].rd_data_rise_wl_r_reg[2]_2 ;
  input \gen_rd[2].rd_data_rise_wl_r_reg[2]_3 ;
  input \gen_rd[2].rd_data_rise_wl_r_reg[2]_4 ;
  input \gen_rd[2].rd_data_rise_wl_r_reg[2]_5 ;
  input \gen_rd[2].rd_data_rise_wl_r_reg[2]_6 ;
  input \gen_rd[2].rd_data_rise_wl_r_reg[2]_7 ;
  input \gen_rd[3].rd_data_rise_wl_r_reg[3]_0 ;
  input \gen_rd[3].rd_data_rise_wl_r_reg[3]_1 ;
  input \gen_rd[3].rd_data_rise_wl_r_reg[3]_2 ;
  input \gen_rd[3].rd_data_rise_wl_r_reg[3]_3 ;
  input \gen_rd[3].rd_data_rise_wl_r_reg[3]_4 ;
  input \gen_rd[3].rd_data_rise_wl_r_reg[3]_5 ;
  input \gen_rd[3].rd_data_rise_wl_r_reg[3]_6 ;
  input \gen_rd[3].rd_data_rise_wl_r_reg[3]_7 ;
  input \gen_rd[4].rd_data_rise_wl_r_reg[4]_0 ;
  input \gen_rd[4].rd_data_rise_wl_r_reg[4]_1 ;
  input \gen_rd[4].rd_data_rise_wl_r_reg[4]_2 ;
  input \gen_rd[4].rd_data_rise_wl_r_reg[4]_3 ;
  input \gen_rd[4].rd_data_rise_wl_r_reg[4]_4 ;
  input \gen_rd[4].rd_data_rise_wl_r_reg[4]_5 ;
  input \gen_rd[4].rd_data_rise_wl_r_reg[4]_6 ;
  input \gen_rd[4].rd_data_rise_wl_r_reg[4]_7 ;
  input \gen_rd[5].rd_data_rise_wl_r_reg[5]_0 ;
  input \gen_rd[5].rd_data_rise_wl_r_reg[5]_1 ;
  input \gen_rd[5].rd_data_rise_wl_r_reg[5]_2 ;
  input \gen_rd[5].rd_data_rise_wl_r_reg[5]_3 ;
  input \gen_rd[5].rd_data_rise_wl_r_reg[5]_4 ;
  input \gen_rd[5].rd_data_rise_wl_r_reg[5]_5 ;
  input \gen_rd[5].rd_data_rise_wl_r_reg[5]_6 ;
  input \gen_rd[5].rd_data_rise_wl_r_reg[5]_7 ;
  input \gen_rd[6].rd_data_rise_wl_r_reg[6]_0 ;
  input \gen_rd[6].rd_data_rise_wl_r_reg[6]_1 ;
  input \gen_rd[6].rd_data_rise_wl_r_reg[6]_2 ;
  input \gen_rd[6].rd_data_rise_wl_r_reg[6]_3 ;
  input \gen_rd[6].rd_data_rise_wl_r_reg[6]_4 ;
  input \gen_rd[6].rd_data_rise_wl_r_reg[6]_5 ;
  input \gen_rd[6].rd_data_rise_wl_r_reg[6]_6 ;
  input \gen_rd[6].rd_data_rise_wl_r_reg[6]_7 ;
  input \gen_rd[7].rd_data_rise_wl_r_reg[7]_0 ;
  input \gen_rd[7].rd_data_rise_wl_r_reg[7]_1 ;
  input \gen_rd[7].rd_data_rise_wl_r_reg[7]_2 ;
  input \gen_rd[7].rd_data_rise_wl_r_reg[7]_3 ;
  input \gen_rd[7].rd_data_rise_wl_r_reg[7]_4 ;
  input \gen_rd[7].rd_data_rise_wl_r_reg[7]_5 ;
  input \gen_rd[7].rd_data_rise_wl_r_reg[7]_6 ;
  input \gen_rd[7].rd_data_rise_wl_r_reg[7]_7 ;

  wire C_po_coarse_enable26_out;
  wire C_po_fine_enable23_out;
  wire C_po_fine_inc29_out;
  wire \FSM_sequential_wl_state_r[0]_i_10_n_0 ;
  wire \FSM_sequential_wl_state_r[0]_i_11_n_0 ;
  wire \FSM_sequential_wl_state_r[0]_i_12_n_0 ;
  wire \FSM_sequential_wl_state_r[0]_i_14_n_0 ;
  wire \FSM_sequential_wl_state_r[0]_i_15_n_0 ;
  wire \FSM_sequential_wl_state_r[0]_i_1_n_0 ;
  wire \FSM_sequential_wl_state_r[0]_i_2_n_0 ;
  wire \FSM_sequential_wl_state_r[0]_i_3_n_0 ;
  wire \FSM_sequential_wl_state_r[0]_i_4_n_0 ;
  wire \FSM_sequential_wl_state_r[0]_i_5_n_0 ;
  wire \FSM_sequential_wl_state_r[0]_i_6_n_0 ;
  wire \FSM_sequential_wl_state_r[0]_i_7_n_0 ;
  wire \FSM_sequential_wl_state_r[0]_i_8_n_0 ;
  wire \FSM_sequential_wl_state_r[0]_i_9_n_0 ;
  wire \FSM_sequential_wl_state_r[1]_i_10_n_0 ;
  wire \FSM_sequential_wl_state_r[1]_i_11_n_0 ;
  wire \FSM_sequential_wl_state_r[1]_i_1_n_0 ;
  wire \FSM_sequential_wl_state_r[1]_i_2_n_0 ;
  wire \FSM_sequential_wl_state_r[1]_i_3_n_0 ;
  wire \FSM_sequential_wl_state_r[1]_i_4_n_0 ;
  wire \FSM_sequential_wl_state_r[1]_i_5_n_0 ;
  wire \FSM_sequential_wl_state_r[1]_i_6_n_0 ;
  wire \FSM_sequential_wl_state_r[1]_i_7_n_0 ;
  wire \FSM_sequential_wl_state_r[1]_i_8_n_0 ;
  wire \FSM_sequential_wl_state_r[1]_i_9_n_0 ;
  wire \FSM_sequential_wl_state_r[2]_i_10_n_0 ;
  wire \FSM_sequential_wl_state_r[2]_i_11_n_0 ;
  wire \FSM_sequential_wl_state_r[2]_i_12_n_0 ;
  wire \FSM_sequential_wl_state_r[2]_i_13_n_0 ;
  wire \FSM_sequential_wl_state_r[2]_i_14_n_0 ;
  wire \FSM_sequential_wl_state_r[2]_i_1_n_0 ;
  wire \FSM_sequential_wl_state_r[2]_i_2_n_0 ;
  wire \FSM_sequential_wl_state_r[2]_i_3_n_0 ;
  wire \FSM_sequential_wl_state_r[2]_i_4_n_0 ;
  wire \FSM_sequential_wl_state_r[2]_i_5_n_0 ;
  wire \FSM_sequential_wl_state_r[2]_i_6_n_0 ;
  wire \FSM_sequential_wl_state_r[2]_i_7_n_0 ;
  wire \FSM_sequential_wl_state_r[2]_i_8_n_0 ;
  wire \FSM_sequential_wl_state_r[2]_i_9_n_0 ;
  wire \FSM_sequential_wl_state_r[3]_i_10_n_0 ;
  wire \FSM_sequential_wl_state_r[3]_i_11_n_0 ;
  wire \FSM_sequential_wl_state_r[3]_i_12_n_0 ;
  wire \FSM_sequential_wl_state_r[3]_i_13_n_0 ;
  wire \FSM_sequential_wl_state_r[3]_i_14_n_0 ;
  wire \FSM_sequential_wl_state_r[3]_i_1_n_0 ;
  wire \FSM_sequential_wl_state_r[3]_i_2_n_0 ;
  wire \FSM_sequential_wl_state_r[3]_i_3_n_0 ;
  wire \FSM_sequential_wl_state_r[3]_i_4_n_0 ;
  wire \FSM_sequential_wl_state_r[3]_i_5_n_0 ;
  wire \FSM_sequential_wl_state_r[3]_i_6_n_0 ;
  wire \FSM_sequential_wl_state_r[3]_i_7_n_0 ;
  wire \FSM_sequential_wl_state_r[3]_i_8_n_0 ;
  wire \FSM_sequential_wl_state_r[3]_i_9_n_0 ;
  wire \FSM_sequential_wl_state_r[4]_i_10_n_0 ;
  wire \FSM_sequential_wl_state_r[4]_i_11_n_0 ;
  wire \FSM_sequential_wl_state_r[4]_i_12_n_0 ;
  wire \FSM_sequential_wl_state_r[4]_i_13_n_0 ;
  wire \FSM_sequential_wl_state_r[4]_i_14_n_0 ;
  wire \FSM_sequential_wl_state_r[4]_i_15_n_0 ;
  wire \FSM_sequential_wl_state_r[4]_i_16_n_0 ;
  wire \FSM_sequential_wl_state_r[4]_i_17_n_0 ;
  wire \FSM_sequential_wl_state_r[4]_i_18_n_0 ;
  wire \FSM_sequential_wl_state_r[4]_i_1_n_0 ;
  wire \FSM_sequential_wl_state_r[4]_i_20_n_0 ;
  wire \FSM_sequential_wl_state_r[4]_i_2_n_0 ;
  wire \FSM_sequential_wl_state_r[4]_i_3_n_0 ;
  wire \FSM_sequential_wl_state_r[4]_i_4_n_0 ;
  wire \FSM_sequential_wl_state_r[4]_i_5_n_0 ;
  wire \FSM_sequential_wl_state_r[4]_i_6_n_0 ;
  wire \FSM_sequential_wl_state_r[4]_i_8_n_0 ;
  wire \FSM_sequential_wl_state_r[4]_i_9_n_0 ;
  wire \FSM_sequential_wl_state_r_reg[0]_0 ;
  wire \FSM_sequential_wl_state_r_reg[2]_0 ;
  wire [1:0]\FSM_sequential_wl_state_r_reg[4]_0 ;
  wire \FSM_sequential_wl_state_r_reg[4]_i_7_n_0 ;
  wire [0:0]Q;
  wire [0:0]SS;
  wire calib_in_common;
  wire \calib_sel_reg[0] ;
  wire \calib_sel_reg[0]_0 ;
  wire \calib_sel_reg[1] ;
  wire \calib_sel_reg[1]_0 ;
  wire \calib_sel_reg[1]_1 ;
  wire \calib_sel_reg[1]_10 ;
  wire \calib_sel_reg[1]_2 ;
  wire \calib_sel_reg[1]_3 ;
  wire \calib_sel_reg[1]_4 ;
  wire \calib_sel_reg[1]_5 ;
  wire \calib_sel_reg[1]_6 ;
  wire \calib_sel_reg[1]_7 ;
  wire \calib_sel_reg[1]_8 ;
  wire \calib_sel_reg[1]_9 ;
  wire ck_po_stg2_f_indec;
  wire cmd_delay_start0;
  wire [2:0]corse_cnt;
  wire \corse_cnt[0][0]_i_1_n_0 ;
  wire \corse_cnt[0][0]_i_3_n_0 ;
  wire \corse_cnt[0][0]_i_4_n_0 ;
  wire \corse_cnt[0][0]_i_5_n_0 ;
  wire \corse_cnt[0][0]_i_6_n_0 ;
  wire \corse_cnt[0][0]_i_7_n_0 ;
  wire \corse_cnt[0][0]_i_8_n_0 ;
  wire \corse_cnt[0][0]_i_9_n_0 ;
  wire \corse_cnt[0][1]_i_1_n_0 ;
  wire \corse_cnt[0][1]_i_3_n_0 ;
  wire \corse_cnt[0][1]_i_4_n_0 ;
  wire \corse_cnt[0][1]_i_5_n_0 ;
  wire \corse_cnt[0][1]_i_6_n_0 ;
  wire \corse_cnt[0][2]_i_11_n_0 ;
  wire \corse_cnt[0][2]_i_12_n_0 ;
  wire \corse_cnt[0][2]_i_13_n_0 ;
  wire \corse_cnt[0][2]_i_1_n_0 ;
  wire \corse_cnt[0][2]_i_3_n_0 ;
  wire \corse_cnt[0][2]_i_4_n_0 ;
  wire \corse_cnt[0][2]_i_5_n_0 ;
  wire \corse_cnt[0][2]_i_6_n_0 ;
  wire \corse_cnt[0][2]_i_7_n_0 ;
  wire \corse_cnt[0][2]_i_8_n_0 ;
  wire \corse_cnt[1][0]_i_1_n_0 ;
  wire \corse_cnt[1][1]_i_1_n_0 ;
  wire \corse_cnt[1][2]_i_1_n_0 ;
  wire \corse_cnt[1][2]_i_2_n_0 ;
  wire \corse_cnt[2][0]_i_1_n_0 ;
  wire \corse_cnt[2][1]_i_1_n_0 ;
  wire \corse_cnt[2][2]_i_1_n_0 ;
  wire \corse_cnt[2][2]_i_2_n_0 ;
  wire \corse_cnt[3][0]_i_1_n_0 ;
  wire \corse_cnt[3][1]_i_1_n_0 ;
  wire \corse_cnt[3][2]_i_1_n_0 ;
  wire \corse_cnt[3][2]_i_2_n_0 ;
  wire \corse_cnt[4][0]_i_1_n_0 ;
  wire \corse_cnt[4][1]_i_1_n_0 ;
  wire \corse_cnt[4][2]_i_1_n_0 ;
  wire \corse_cnt[4][2]_i_2_n_0 ;
  wire \corse_cnt[5][0]_i_1_n_0 ;
  wire \corse_cnt[5][1]_i_1_n_0 ;
  wire \corse_cnt[5][2]_i_1_n_0 ;
  wire \corse_cnt[5][2]_i_2_n_0 ;
  wire \corse_cnt[6][0]_i_1_n_0 ;
  wire \corse_cnt[6][1]_i_1_n_0 ;
  wire \corse_cnt[6][2]_i_1_n_0 ;
  wire \corse_cnt[6][2]_i_2_n_0 ;
  wire \corse_cnt[7][0]_i_1_n_0 ;
  wire \corse_cnt[7][1]_i_1_n_0 ;
  wire \corse_cnt[7][2]_i_1_n_0 ;
  wire \corse_cnt[7][2]_i_2_n_0 ;
  wire \corse_cnt_reg[3][0]_0 ;
  wire \corse_cnt_reg[4][0]_0 ;
  wire \corse_cnt_reg[5][0]_0 ;
  wire \corse_cnt_reg[6][0]_0 ;
  wire \corse_cnt_reg[7][0]_0 ;
  wire \corse_cnt_reg[7][0]_1 ;
  wire \corse_cnt_reg_n_0_[0][0] ;
  wire \corse_cnt_reg_n_0_[0][1] ;
  wire \corse_cnt_reg_n_0_[0][2] ;
  wire \corse_cnt_reg_n_0_[1][0] ;
  wire \corse_cnt_reg_n_0_[1][1] ;
  wire \corse_cnt_reg_n_0_[1][2] ;
  wire \corse_cnt_reg_n_0_[2][0] ;
  wire \corse_cnt_reg_n_0_[2][1] ;
  wire \corse_cnt_reg_n_0_[2][2] ;
  wire \corse_cnt_reg_n_0_[3][0] ;
  wire \corse_cnt_reg_n_0_[3][1] ;
  wire \corse_cnt_reg_n_0_[3][2] ;
  wire \corse_cnt_reg_n_0_[4][0] ;
  wire \corse_cnt_reg_n_0_[4][1] ;
  wire \corse_cnt_reg_n_0_[4][2] ;
  wire \corse_cnt_reg_n_0_[5][0] ;
  wire \corse_cnt_reg_n_0_[5][1] ;
  wire \corse_cnt_reg_n_0_[5][2] ;
  wire \corse_cnt_reg_n_0_[6][0] ;
  wire \corse_cnt_reg_n_0_[6][1] ;
  wire \corse_cnt_reg_n_0_[6][2] ;
  wire \corse_cnt_reg_n_0_[7][0] ;
  wire \corse_cnt_reg_n_0_[7][1] ;
  wire \corse_cnt_reg_n_0_[7][2] ;
  wire [1:0]corse_dec;
  wire \corse_dec[0][0]_i_1_n_0 ;
  wire \corse_dec[0][1]_i_1_n_0 ;
  wire \corse_dec[0][2]_i_11_n_0 ;
  wire \corse_dec[0][2]_i_12_n_0 ;
  wire \corse_dec[0][2]_i_1_n_0 ;
  wire \corse_dec[0][2]_i_4_n_0 ;
  wire \corse_dec[0][2]_i_5_n_0 ;
  wire \corse_dec[0][2]_i_6_n_0 ;
  wire \corse_dec[0][2]_i_7_n_0 ;
  wire \corse_dec[0][2]_i_8_n_0 ;
  wire \corse_dec[0][2]_i_9_n_0 ;
  wire \corse_dec[1][0]_i_1_n_0 ;
  wire \corse_dec[1][1]_i_1_n_0 ;
  wire \corse_dec[1][2]_i_1_n_0 ;
  wire \corse_dec[2][0]_i_1_n_0 ;
  wire \corse_dec[2][1]_i_1_n_0 ;
  wire \corse_dec[2][2]_i_1_n_0 ;
  wire \corse_dec[3][0]_i_1_n_0 ;
  wire \corse_dec[3][1]_i_1_n_0 ;
  wire \corse_dec[3][2]_i_1_n_0 ;
  wire \corse_dec[4][0]_i_1_n_0 ;
  wire \corse_dec[4][1]_i_1_n_0 ;
  wire \corse_dec[4][2]_i_1_n_0 ;
  wire \corse_dec[5][0]_i_1_n_0 ;
  wire \corse_dec[5][1]_i_1_n_0 ;
  wire \corse_dec[5][2]_i_1_n_0 ;
  wire \corse_dec[6][0]_i_1_n_0 ;
  wire \corse_dec[6][1]_i_1_n_0 ;
  wire \corse_dec[6][2]_i_1_n_0 ;
  wire \corse_dec[7][0]_i_1_n_0 ;
  wire \corse_dec[7][1]_i_1_n_0 ;
  wire \corse_dec[7][2]_i_1_n_0 ;
  wire \corse_dec_reg[0][2]_i_10_n_0 ;
  wire \corse_dec_reg[0][2]_i_2_n_0 ;
  wire \corse_dec_reg[0][2]_i_3_n_0 ;
  wire [2:0]\corse_dec_reg[0]_21 ;
  wire [2:0]\corse_dec_reg[1]_22 ;
  wire [2:0]\corse_dec_reg[2]_23 ;
  wire [2:0]\corse_dec_reg[3]_24 ;
  wire [2:0]\corse_dec_reg[4]_25 ;
  wire [2:0]\corse_dec_reg[5]_26 ;
  wire [2:0]\corse_dec_reg[6]_27 ;
  wire [1:0]\corse_dec_reg[7][0]_0 ;
  wire [2:0]\corse_dec_reg[7]_28 ;
  wire [2:0]corse_inc;
  wire \corse_inc[0][0]_i_1_n_0 ;
  wire \corse_inc[0][1]_i_1_n_0 ;
  wire \corse_inc[0][1]_i_5_n_0 ;
  wire \corse_inc[0][1]_i_6_n_0 ;
  wire \corse_inc[0][1]_i_7_n_0 ;
  wire \corse_inc[0][1]_i_8_n_0 ;
  wire \corse_inc[0][2]_i_1_n_0 ;
  wire \corse_inc[0][2]_i_3_n_0 ;
  wire \corse_inc[0][2]_i_4_n_0 ;
  wire \corse_inc[0][2]_i_5_n_0 ;
  wire \corse_inc[0][2]_i_7_n_0 ;
  wire \corse_inc[0][2]_i_8_n_0 ;
  wire \corse_inc[0][2]_i_9_n_0 ;
  wire \corse_inc[1][0]_i_1_n_0 ;
  wire \corse_inc[1][0]_i_2_n_0 ;
  wire \corse_inc[1][1]_i_1_n_0 ;
  wire \corse_inc[1][1]_i_2_n_0 ;
  wire \corse_inc[1][2]_i_1_n_0 ;
  wire \corse_inc[1][2]_i_2_n_0 ;
  wire \corse_inc[2][0]_i_1_n_0 ;
  wire \corse_inc[2][0]_i_2_n_0 ;
  wire \corse_inc[2][1]_i_1_n_0 ;
  wire \corse_inc[2][1]_i_2_n_0 ;
  wire \corse_inc[2][2]_i_1_n_0 ;
  wire \corse_inc[2][2]_i_2_n_0 ;
  wire \corse_inc[3][0]_i_1_n_0 ;
  wire \corse_inc[3][0]_i_2_n_0 ;
  wire \corse_inc[3][1]_i_1_n_0 ;
  wire \corse_inc[3][1]_i_2_n_0 ;
  wire \corse_inc[3][2]_i_1_n_0 ;
  wire \corse_inc[3][2]_i_2_n_0 ;
  wire \corse_inc[4][0]_i_1_n_0 ;
  wire \corse_inc[4][0]_i_2_n_0 ;
  wire \corse_inc[4][1]_i_1_n_0 ;
  wire \corse_inc[4][1]_i_2_n_0 ;
  wire \corse_inc[4][2]_i_1_n_0 ;
  wire \corse_inc[4][2]_i_2_n_0 ;
  wire \corse_inc[5][0]_i_1_n_0 ;
  wire \corse_inc[5][0]_i_2_n_0 ;
  wire \corse_inc[5][1]_i_1_n_0 ;
  wire \corse_inc[5][1]_i_2_n_0 ;
  wire \corse_inc[5][2]_i_1_n_0 ;
  wire \corse_inc[5][2]_i_2_n_0 ;
  wire \corse_inc[6][0]_i_1_n_0 ;
  wire \corse_inc[6][0]_i_2_n_0 ;
  wire \corse_inc[6][1]_i_1_n_0 ;
  wire \corse_inc[6][1]_i_2_n_0 ;
  wire \corse_inc[6][2]_i_1_n_0 ;
  wire \corse_inc[6][2]_i_2_n_0 ;
  wire \corse_inc[7][0]_i_1_n_0 ;
  wire \corse_inc[7][0]_i_2_n_0 ;
  wire \corse_inc[7][1]_i_1_n_0 ;
  wire \corse_inc[7][1]_i_2_n_0 ;
  wire \corse_inc[7][2]_i_1_n_0 ;
  wire \corse_inc[7][2]_i_2_n_0 ;
  wire \corse_inc_reg[0][1]_i_3_n_0 ;
  wire \corse_inc_reg[0][1]_i_4_n_0 ;
  wire \corse_inc_reg[0][2]_i_6_n_0 ;
  wire [2:0]\corse_inc_reg[0]_37 ;
  wire [2:0]\corse_inc_reg[1]_38 ;
  wire [2:0]\corse_inc_reg[2]_39 ;
  wire [2:0]\corse_inc_reg[3]_40 ;
  wire [2:0]\corse_inc_reg[4]_41 ;
  wire [2:0]\corse_inc_reg[5]_42 ;
  wire [1:0]\corse_inc_reg[6][2]_0 ;
  wire [2:0]\corse_inc_reg[6]_43 ;
  wire [2:0]\corse_inc_reg[7]_44 ;
  wire delaydec_cnt_r10_in;
  wire done_dqs_dec238_out;
  wire done_dqs_tap_inc;
  wire dq_cnt_inc_i_1_n_0;
  wire dq_cnt_inc_i_2_n_0;
  wire dq_cnt_inc_i_3_n_0;
  wire [2:0]dqs_count_r;
  wire \dqs_count_r[0]_i_1_n_0 ;
  wire \dqs_count_r[0]_i_2_n_0 ;
  wire \dqs_count_r[0]_i_3_n_0 ;
  wire \dqs_count_r[0]_i_4_n_0 ;
  wire \dqs_count_r[0]_i_5_n_0 ;
  wire \dqs_count_r[1]_i_1_n_0 ;
  wire \dqs_count_r[1]_i_2_n_0 ;
  wire \dqs_count_r[1]_i_3_n_0 ;
  wire \dqs_count_r[1]_i_4_n_0 ;
  wire \dqs_count_r[1]_i_5_n_0 ;
  wire \dqs_count_r[1]_i_6_n_0 ;
  wire \dqs_count_r[1]_rep_i_1_n_0 ;
  wire \dqs_count_r[2]_i_1_n_0 ;
  wire \dqs_count_r[2]_i_2_n_0 ;
  wire \dqs_count_r[2]_i_3_n_0 ;
  wire \dqs_count_r[2]_i_4_n_0 ;
  wire \dqs_count_r[2]_i_5_n_0 ;
  wire \dqs_count_r[2]_i_6_n_0 ;
  wire \dqs_count_r[2]_i_7_n_0 ;
  wire \dqs_count_r[2]_i_8_n_0 ;
  wire \dqs_count_r[2]_rep__0_i_1_n_0 ;
  wire \dqs_count_r[2]_rep_i_1_n_0 ;
  wire \dqs_count_r[3]_i_10_n_0 ;
  wire \dqs_count_r[3]_i_11_n_0 ;
  wire \dqs_count_r[3]_i_12_n_0 ;
  wire \dqs_count_r[3]_i_1_n_0 ;
  wire \dqs_count_r[3]_i_2_n_0 ;
  wire \dqs_count_r[3]_i_3_n_0 ;
  wire \dqs_count_r[3]_i_4_n_0 ;
  wire \dqs_count_r[3]_i_5_n_0 ;
  wire \dqs_count_r[3]_i_6_n_0 ;
  wire \dqs_count_r[3]_i_7_n_0 ;
  wire \dqs_count_r[3]_i_8_n_0 ;
  wire \dqs_count_r[3]_i_9_n_0 ;
  wire \dqs_count_r_reg[0]_rep_0 ;
  wire \dqs_count_r_reg[1]_rep_0 ;
  wire \dqs_count_r_reg[2]_rep__0_0 ;
  wire \dqs_count_r_reg[2]_rep__0_1 ;
  wire \dqs_count_r_reg[2]_rep__0_2 ;
  wire \dqs_count_r_reg[2]_rep_n_0 ;
  wire [0:0]\dqs_count_r_reg[3]_0 ;
  wire [3:0]\dqs_count_r_reg[3]_1 ;
  wire dqs_po_dec_done;
  wire dqs_po_en_stg2_f;
  wire dqs_po_en_stg2_f_i_1_n_0;
  wire dqs_po_stg2_f_incdec;
  wire dqs_po_stg2_f_incdec_i_1_n_0;
  wire dqs_po_stg2_f_incdec_i_2_n_0;
  wire dqs_po_stg2_f_incdec_reg_0;
  wire dqs_po_stg2_f_incdec_reg_1;
  wire dqs_po_stg2_f_incdec_reg_2;
  wire dqs_po_stg2_f_incdec_reg_3;
  wire dqs_po_stg2_f_incdec_reg_4;
  wire dqs_po_stg2_f_incdec_reg_5;
  wire dqs_po_stg2_f_incdec_reg_6;
  wire dqs_po_stg2_f_incdec_reg_7;
  wire dqs_po_stg2_f_incdec_reg_8;
  wire dqs_po_stg2_f_incdec_reg_9;
  wire dqs_wl_po_stg2_c_incdec_i_1_n_0;
  wire dqs_wl_po_stg2_c_incdec_reg_0;
  wire dqs_wl_po_stg2_c_incdec_reg_1;
  wire \final_coarse_tap_reg_n_0_[0][0] ;
  wire \final_coarse_tap_reg_n_0_[0][1] ;
  wire \final_coarse_tap_reg_n_0_[0][2] ;
  wire \final_coarse_tap_reg_n_0_[1][0] ;
  wire \final_coarse_tap_reg_n_0_[1][1] ;
  wire \final_coarse_tap_reg_n_0_[1][2] ;
  wire \final_coarse_tap_reg_n_0_[2][0] ;
  wire \final_coarse_tap_reg_n_0_[2][1] ;
  wire \final_coarse_tap_reg_n_0_[2][2] ;
  wire \final_coarse_tap_reg_n_0_[3][0] ;
  wire \final_coarse_tap_reg_n_0_[3][1] ;
  wire \final_coarse_tap_reg_n_0_[3][2] ;
  wire \final_coarse_tap_reg_n_0_[4][0] ;
  wire \final_coarse_tap_reg_n_0_[4][1] ;
  wire \final_coarse_tap_reg_n_0_[4][2] ;
  wire \final_coarse_tap_reg_n_0_[5][0] ;
  wire \final_coarse_tap_reg_n_0_[5][1] ;
  wire \final_coarse_tap_reg_n_0_[5][2] ;
  wire \final_coarse_tap_reg_n_0_[6][0] ;
  wire \final_coarse_tap_reg_n_0_[6][1] ;
  wire \final_coarse_tap_reg_n_0_[6][2] ;
  wire \final_coarse_tap_reg_n_0_[7][0] ;
  wire \final_coarse_tap_reg_n_0_[7][1] ;
  wire \final_coarse_tap_reg_n_0_[7][2] ;
  wire [5:0]fine_dec_cnt;
  wire \fine_dec_cnt[3]_i_2_n_0 ;
  wire \fine_dec_cnt[4]_i_2_n_0 ;
  wire \fine_dec_cnt[5]_i_10_n_0 ;
  wire \fine_dec_cnt[5]_i_1_n_0 ;
  wire \fine_dec_cnt[5]_i_3_n_0 ;
  wire \fine_dec_cnt[5]_i_4_n_0 ;
  wire \fine_dec_cnt[5]_i_5_n_0 ;
  wire \fine_dec_cnt[5]_i_6_n_0 ;
  wire \fine_dec_cnt[5]_i_7_n_0 ;
  wire \fine_dec_cnt[5]_i_8_n_0 ;
  wire \fine_dec_cnt[5]_i_9_n_0 ;
  wire [0:0]\fine_dec_cnt_reg[5]_0 ;
  wire \fine_dec_cnt_reg_n_0_[0] ;
  wire \fine_dec_cnt_reg_n_0_[1] ;
  wire \fine_dec_cnt_reg_n_0_[2] ;
  wire \fine_dec_cnt_reg_n_0_[3] ;
  wire \fine_dec_cnt_reg_n_0_[4] ;
  wire \fine_dec_cnt_reg_n_0_[5] ;
  wire [5:0]fine_inc;
  wire \fine_inc[0][1]_i_4_n_0 ;
  wire \fine_inc[0][1]_i_5_n_0 ;
  wire \fine_inc[0][1]_i_6_n_0 ;
  wire \fine_inc[0][1]_i_7_n_0 ;
  wire \fine_inc[0][2]_i_3_n_0 ;
  wire \fine_inc[0][2]_i_4_n_0 ;
  wire \fine_inc[0][2]_i_5_n_0 ;
  wire \fine_inc[0][3]_i_3_n_0 ;
  wire \fine_inc[0][3]_i_4_n_0 ;
  wire \fine_inc[0][3]_i_5_n_0 ;
  wire \fine_inc[0][4]_i_2_n_0 ;
  wire \fine_inc[0][5]_i_10_n_0 ;
  wire \fine_inc[0][5]_i_11_n_0 ;
  wire \fine_inc[0][5]_i_12_n_0 ;
  wire \fine_inc[0][5]_i_13_n_0 ;
  wire \fine_inc[0][5]_i_1_n_0 ;
  wire \fine_inc[0][5]_i_3_n_0 ;
  wire \fine_inc[0][5]_i_4_n_0 ;
  wire \fine_inc[0][5]_i_5_n_0 ;
  wire \fine_inc[0][5]_i_6_n_0 ;
  wire \fine_inc[0][5]_i_8_n_0 ;
  wire \fine_inc[1][0]_i_1_n_0 ;
  wire \fine_inc[1][1]_i_1_n_0 ;
  wire \fine_inc[1][2]_i_1_n_0 ;
  wire \fine_inc[1][3]_i_1_n_0 ;
  wire \fine_inc[1][4]_i_1_n_0 ;
  wire \fine_inc[1][5]_i_1_n_0 ;
  wire \fine_inc[1][5]_i_2_n_0 ;
  wire \fine_inc[1][5]_i_3_n_0 ;
  wire \fine_inc[2][0]_i_1_n_0 ;
  wire \fine_inc[2][1]_i_1_n_0 ;
  wire \fine_inc[2][2]_i_1_n_0 ;
  wire \fine_inc[2][3]_i_1_n_0 ;
  wire \fine_inc[2][4]_i_1_n_0 ;
  wire \fine_inc[2][5]_i_1_n_0 ;
  wire \fine_inc[2][5]_i_2_n_0 ;
  wire \fine_inc[2][5]_i_3_n_0 ;
  wire \fine_inc[3][0]_i_1_n_0 ;
  wire \fine_inc[3][1]_i_1_n_0 ;
  wire \fine_inc[3][2]_i_1_n_0 ;
  wire \fine_inc[3][3]_i_1_n_0 ;
  wire \fine_inc[3][4]_i_1_n_0 ;
  wire \fine_inc[3][5]_i_1_n_0 ;
  wire \fine_inc[3][5]_i_2_n_0 ;
  wire \fine_inc[3][5]_i_3_n_0 ;
  wire \fine_inc[4][0]_i_1_n_0 ;
  wire \fine_inc[4][1]_i_1_n_0 ;
  wire \fine_inc[4][2]_i_1_n_0 ;
  wire \fine_inc[4][3]_i_1_n_0 ;
  wire \fine_inc[4][4]_i_1_n_0 ;
  wire \fine_inc[4][5]_i_1_n_0 ;
  wire \fine_inc[4][5]_i_2_n_0 ;
  wire \fine_inc[4][5]_i_3_n_0 ;
  wire \fine_inc[5][0]_i_1_n_0 ;
  wire \fine_inc[5][1]_i_1_n_0 ;
  wire \fine_inc[5][2]_i_1_n_0 ;
  wire \fine_inc[5][3]_i_1_n_0 ;
  wire \fine_inc[5][4]_i_1_n_0 ;
  wire \fine_inc[5][5]_i_1_n_0 ;
  wire \fine_inc[5][5]_i_2_n_0 ;
  wire \fine_inc[5][5]_i_3_n_0 ;
  wire \fine_inc[6][0]_i_1_n_0 ;
  wire \fine_inc[6][1]_i_1_n_0 ;
  wire \fine_inc[6][2]_i_1_n_0 ;
  wire \fine_inc[6][3]_i_1_n_0 ;
  wire \fine_inc[6][4]_i_1_n_0 ;
  wire \fine_inc[6][5]_i_1_n_0 ;
  wire \fine_inc[6][5]_i_2_n_0 ;
  wire \fine_inc[6][5]_i_3_n_0 ;
  wire \fine_inc[7][0]_i_1_n_0 ;
  wire \fine_inc[7][1]_i_1_n_0 ;
  wire \fine_inc[7][2]_i_1_n_0 ;
  wire \fine_inc[7][3]_i_1_n_0 ;
  wire \fine_inc[7][4]_i_1_n_0 ;
  wire \fine_inc[7][5]_i_1_n_0 ;
  wire \fine_inc[7][5]_i_2_n_0 ;
  wire \fine_inc[7][5]_i_3_n_0 ;
  wire \fine_inc_reg[0][1]_i_2_n_0 ;
  wire \fine_inc_reg[0][1]_i_3_n_0 ;
  wire \fine_inc_reg[0][2]_i_2_n_0 ;
  wire \fine_inc_reg[0][3]_i_2_n_0 ;
  wire \fine_inc_reg[0][5]_i_7_n_0 ;
  wire \fine_inc_reg[0][5]_i_9_n_0 ;
  wire [5:0]\fine_inc_reg[0]_5 ;
  wire [5:0]\fine_inc_reg[1]_6 ;
  wire [5:0]\fine_inc_reg[2]_7 ;
  wire [5:0]\fine_inc_reg[3]_8 ;
  wire [5:0]\fine_inc_reg[4]_9 ;
  wire [5:0]\fine_inc_reg[5]_10 ;
  wire [1:0]\fine_inc_reg[6][3]_0 ;
  wire [5:0]\fine_inc_reg[6]_11 ;
  wire [5:0]\fine_inc_reg[7]_12 ;
  wire flag_ck_negedge09_out;
  wire flag_ck_negedge_i_1_n_0;
  wire flag_ck_negedge_i_2_n_0;
  wire flag_ck_negedge_i_4_n_0;
  wire flag_ck_negedge_i_5_n_0;
  wire flag_ck_negedge_i_6_n_0;
  wire flag_ck_negedge_reg_n_0;
  wire flag_init;
  wire flag_init_i_1_n_0;
  wire flag_init_i_2_n_0;
  wire \gen_byte_sel_div2.calib_in_common_reg ;
  wire \gen_byte_sel_div2.calib_in_common_reg_0 ;
  wire \gen_byte_sel_div2.calib_in_common_reg_1 ;
  wire \gen_byte_sel_div2.calib_in_common_reg_2 ;
  wire \gen_final_tap[0].final_val[0][5]_i_1_n_0 ;
  wire \gen_final_tap[0].final_val_reg_n_0_[0][0] ;
  wire \gen_final_tap[0].final_val_reg_n_0_[0][1] ;
  wire \gen_final_tap[0].final_val_reg_n_0_[0][2] ;
  wire \gen_final_tap[0].final_val_reg_n_0_[0][3] ;
  wire \gen_final_tap[0].final_val_reg_n_0_[0][4] ;
  wire \gen_final_tap[0].final_val_reg_n_0_[0][5] ;
  wire \gen_final_tap[1].final_val_reg_n_0_[1][0] ;
  wire \gen_final_tap[1].final_val_reg_n_0_[1][1] ;
  wire \gen_final_tap[1].final_val_reg_n_0_[1][2] ;
  wire \gen_final_tap[1].final_val_reg_n_0_[1][3] ;
  wire \gen_final_tap[1].final_val_reg_n_0_[1][4] ;
  wire \gen_final_tap[1].final_val_reg_n_0_[1][5] ;
  wire \gen_final_tap[2].final_val_reg_n_0_[2][0] ;
  wire \gen_final_tap[2].final_val_reg_n_0_[2][1] ;
  wire \gen_final_tap[2].final_val_reg_n_0_[2][2] ;
  wire \gen_final_tap[2].final_val_reg_n_0_[2][3] ;
  wire \gen_final_tap[2].final_val_reg_n_0_[2][4] ;
  wire \gen_final_tap[2].final_val_reg_n_0_[2][5] ;
  wire \gen_final_tap[3].final_val_reg_n_0_[3][0] ;
  wire \gen_final_tap[3].final_val_reg_n_0_[3][1] ;
  wire \gen_final_tap[3].final_val_reg_n_0_[3][2] ;
  wire \gen_final_tap[3].final_val_reg_n_0_[3][3] ;
  wire \gen_final_tap[3].final_val_reg_n_0_[3][4] ;
  wire \gen_final_tap[3].final_val_reg_n_0_[3][5] ;
  wire \gen_final_tap[4].final_val_reg_n_0_[4][0] ;
  wire \gen_final_tap[4].final_val_reg_n_0_[4][1] ;
  wire \gen_final_tap[4].final_val_reg_n_0_[4][2] ;
  wire \gen_final_tap[4].final_val_reg_n_0_[4][3] ;
  wire \gen_final_tap[4].final_val_reg_n_0_[4][4] ;
  wire \gen_final_tap[4].final_val_reg_n_0_[4][5] ;
  wire \gen_final_tap[5].final_val_reg_n_0_[5][0] ;
  wire \gen_final_tap[5].final_val_reg_n_0_[5][1] ;
  wire \gen_final_tap[5].final_val_reg_n_0_[5][2] ;
  wire \gen_final_tap[5].final_val_reg_n_0_[5][3] ;
  wire \gen_final_tap[5].final_val_reg_n_0_[5][4] ;
  wire \gen_final_tap[5].final_val_reg_n_0_[5][5] ;
  wire \gen_final_tap[6].final_val_reg_n_0_[6][0] ;
  wire \gen_final_tap[6].final_val_reg_n_0_[6][1] ;
  wire \gen_final_tap[6].final_val_reg_n_0_[6][2] ;
  wire \gen_final_tap[6].final_val_reg_n_0_[6][3] ;
  wire \gen_final_tap[6].final_val_reg_n_0_[6][4] ;
  wire \gen_final_tap[6].final_val_reg_n_0_[6][5] ;
  wire \gen_final_tap[7].final_val_reg_n_0_[7][0] ;
  wire \gen_final_tap[7].final_val_reg_n_0_[7][1] ;
  wire \gen_final_tap[7].final_val_reg_n_0_[7][2] ;
  wire \gen_final_tap[7].final_val_reg_n_0_[7][3] ;
  wire \gen_final_tap[7].final_val_reg_n_0_[7][4] ;
  wire \gen_final_tap[7].final_val_reg_n_0_[7][5] ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg[0]_0 ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg[0]_1 ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg[0]_2 ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg[0]_3 ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg[0]_4 ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg[0]_5 ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg[0]_6 ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg[0]_7 ;
  wire \gen_rd[0].rd_data_rise_wl_r_reg_n_0_[0] ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg[1]_0 ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg[1]_1 ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg[1]_2 ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg[1]_3 ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg[1]_4 ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg[1]_5 ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg[1]_6 ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg[1]_7 ;
  wire \gen_rd[1].rd_data_rise_wl_r_reg_n_0_[1] ;
  wire \gen_rd[2].rd_data_rise_wl_r_reg[2]_0 ;
  wire \gen_rd[2].rd_data_rise_wl_r_reg[2]_1 ;
  wire \gen_rd[2].rd_data_rise_wl_r_reg[2]_2 ;
  wire \gen_rd[2].rd_data_rise_wl_r_reg[2]_3 ;
  wire \gen_rd[2].rd_data_rise_wl_r_reg[2]_4 ;
  wire \gen_rd[2].rd_data_rise_wl_r_reg[2]_5 ;
  wire \gen_rd[2].rd_data_rise_wl_r_reg[2]_6 ;
  wire \gen_rd[2].rd_data_rise_wl_r_reg[2]_7 ;
  wire \gen_rd[2].rd_data_rise_wl_r_reg_n_0_[2] ;
  wire \gen_rd[3].rd_data_rise_wl_r_reg[3]_0 ;
  wire \gen_rd[3].rd_data_rise_wl_r_reg[3]_1 ;
  wire \gen_rd[3].rd_data_rise_wl_r_reg[3]_2 ;
  wire \gen_rd[3].rd_data_rise_wl_r_reg[3]_3 ;
  wire \gen_rd[3].rd_data_rise_wl_r_reg[3]_4 ;
  wire \gen_rd[3].rd_data_rise_wl_r_reg[3]_5 ;
  wire \gen_rd[3].rd_data_rise_wl_r_reg[3]_6 ;
  wire \gen_rd[3].rd_data_rise_wl_r_reg[3]_7 ;
  wire \gen_rd[3].rd_data_rise_wl_r_reg_n_0_[3] ;
  wire \gen_rd[4].rd_data_rise_wl_r_reg[4]_0 ;
  wire \gen_rd[4].rd_data_rise_wl_r_reg[4]_1 ;
  wire \gen_rd[4].rd_data_rise_wl_r_reg[4]_2 ;
  wire \gen_rd[4].rd_data_rise_wl_r_reg[4]_3 ;
  wire \gen_rd[4].rd_data_rise_wl_r_reg[4]_4 ;
  wire \gen_rd[4].rd_data_rise_wl_r_reg[4]_5 ;
  wire \gen_rd[4].rd_data_rise_wl_r_reg[4]_6 ;
  wire \gen_rd[4].rd_data_rise_wl_r_reg[4]_7 ;
  wire \gen_rd[4].rd_data_rise_wl_r_reg_n_0_[4] ;
  wire \gen_rd[5].rd_data_rise_wl_r_reg[5]_0 ;
  wire \gen_rd[5].rd_data_rise_wl_r_reg[5]_1 ;
  wire \gen_rd[5].rd_data_rise_wl_r_reg[5]_2 ;
  wire \gen_rd[5].rd_data_rise_wl_r_reg[5]_3 ;
  wire \gen_rd[5].rd_data_rise_wl_r_reg[5]_4 ;
  wire \gen_rd[5].rd_data_rise_wl_r_reg[5]_5 ;
  wire \gen_rd[5].rd_data_rise_wl_r_reg[5]_6 ;
  wire \gen_rd[5].rd_data_rise_wl_r_reg[5]_7 ;
  wire \gen_rd[5].rd_data_rise_wl_r_reg_n_0_[5] ;
  wire \gen_rd[6].rd_data_rise_wl_r_reg[6]_0 ;
  wire \gen_rd[6].rd_data_rise_wl_r_reg[6]_1 ;
  wire \gen_rd[6].rd_data_rise_wl_r_reg[6]_2 ;
  wire \gen_rd[6].rd_data_rise_wl_r_reg[6]_3 ;
  wire \gen_rd[6].rd_data_rise_wl_r_reg[6]_4 ;
  wire \gen_rd[6].rd_data_rise_wl_r_reg[6]_5 ;
  wire \gen_rd[6].rd_data_rise_wl_r_reg[6]_6 ;
  wire \gen_rd[6].rd_data_rise_wl_r_reg[6]_7 ;
  wire \gen_rd[6].rd_data_rise_wl_r_reg_n_0_[6] ;
  wire \gen_rd[7].rd_data_rise_wl_r_reg[7]_0 ;
  wire \gen_rd[7].rd_data_rise_wl_r_reg[7]_1 ;
  wire \gen_rd[7].rd_data_rise_wl_r_reg[7]_2 ;
  wire \gen_rd[7].rd_data_rise_wl_r_reg[7]_3 ;
  wire \gen_rd[7].rd_data_rise_wl_r_reg[7]_4 ;
  wire \gen_rd[7].rd_data_rise_wl_r_reg[7]_5 ;
  wire \gen_rd[7].rd_data_rise_wl_r_reg[7]_6 ;
  wire \gen_rd[7].rd_data_rise_wl_r_reg[7]_7 ;
  wire \gen_rd[7].rd_data_rise_wl_r_reg_n_0_[7] ;
  wire \incdec_wait_cnt[3]_i_1_n_0 ;
  wire [3:0]incdec_wait_cnt_reg;
  wire inhibit_edge_detect_r_i_1_n_0;
  wire inhibit_edge_detect_r_i_2_n_0;
  wire inhibit_edge_detect_r_i_3_n_0;
  wire inhibit_edge_detect_r_i_4_n_0;
  wire inhibit_edge_detect_r_i_5_n_0;
  wire inhibit_edge_detect_r_reg_n_0;
  wire [5:0]largest;
  wire p_0_in;
  wire p_0_in__0;
  wire [3:0]p_0_in__1;
  wire [3:0]p_0_in__2;
  wire \p_0_out_inferred__18/gen_rd[0].rd_data_rise_wl_r[0]_i_2_n_0 ;
  wire \p_0_out_inferred__19/gen_rd[1].rd_data_rise_wl_r[1]_i_1_n_0 ;
  wire \p_0_out_inferred__19/gen_rd[1].rd_data_rise_wl_r[1]_i_2_n_0 ;
  wire \p_0_out_inferred__20/gen_rd[2].rd_data_rise_wl_r[2]_i_1_n_0 ;
  wire \p_0_out_inferred__20/gen_rd[2].rd_data_rise_wl_r[2]_i_2_n_0 ;
  wire \p_0_out_inferred__21/gen_rd[3].rd_data_rise_wl_r[3]_i_1_n_0 ;
  wire \p_0_out_inferred__21/gen_rd[3].rd_data_rise_wl_r[3]_i_2_n_0 ;
  wire \p_0_out_inferred__22/gen_rd[4].rd_data_rise_wl_r[4]_i_1_n_0 ;
  wire \p_0_out_inferred__22/gen_rd[4].rd_data_rise_wl_r[4]_i_2_n_0 ;
  wire \p_0_out_inferred__23/gen_rd[5].rd_data_rise_wl_r[5]_i_1_n_0 ;
  wire \p_0_out_inferred__23/gen_rd[5].rd_data_rise_wl_r[5]_i_2_n_0 ;
  wire \p_0_out_inferred__24/gen_rd[6].rd_data_rise_wl_r[6]_i_1_n_0 ;
  wire \p_0_out_inferred__24/gen_rd[6].rd_data_rise_wl_r[6]_i_2_n_0 ;
  wire \p_0_out_inferred__25/gen_rd[7].rd_data_rise_wl_r[7]_i_1_n_0 ;
  wire \p_0_out_inferred__25/gen_rd[7].rd_data_rise_wl_r[7]_i_2_n_0 ;
  wire phaser_out;
  wire phaser_out_0;
  wire [2:0]phaser_out_1;
  wire phy_ctl_ready_r4_reg_srl4_n_0;
  wire phy_ctl_ready_r5;
  wire phy_ctl_ready_r6_reg_n_0;
  wire pi_fine_dly_dec_done;
  wire po_cnt_dec_i_1_n_0;
  wire po_cnt_dec_i_2_n_0;
  wire po_cnt_dec_reg_0;
  wire po_dec_done;
  wire po_dec_done_i_1_n_0;
  wire po_dec_done_i_2_n_0;
  wire [0:0]po_enstg2_f;
  wire [8:0]po_rdval_cnt;
  wire \po_rdval_cnt[0]_i_1_n_0 ;
  wire \po_rdval_cnt[1]_i_1_n_0 ;
  wire \po_rdval_cnt[2]_i_1_n_0 ;
  wire \po_rdval_cnt[3]_i_1_n_0 ;
  wire \po_rdval_cnt[3]_i_3_n_0 ;
  wire \po_rdval_cnt[4]_i_1_n_0 ;
  wire \po_rdval_cnt[4]_i_3_n_0 ;
  wire \po_rdval_cnt[5]_i_1_n_0 ;
  wire \po_rdval_cnt[6]_i_1_n_0 ;
  wire \po_rdval_cnt[6]_i_3_n_0 ;
  wire \po_rdval_cnt[6]_i_4_n_0 ;
  wire \po_rdval_cnt[7]_i_1_n_0 ;
  wire \po_rdval_cnt[8]_i_1_n_0 ;
  wire \po_rdval_cnt[8]_i_2_n_0 ;
  wire \po_rdval_cnt[8]_i_3_n_0 ;
  wire \po_rdval_cnt[8]_i_5_n_0 ;
  wire \po_rdval_cnt[8]_i_6_n_0 ;
  wire \po_rdval_cnt_reg[0]_0 ;
  wire \po_rdval_cnt_reg[1]_0 ;
  wire \po_rdval_cnt_reg[2]_0 ;
  wire \po_rdval_cnt_reg[3]_0 ;
  wire \po_rdval_cnt_reg[4]_0 ;
  wire \po_rdval_cnt_reg[5]_0 ;
  wire \po_rdval_cnt_reg[6]_0 ;
  wire \po_rdval_cnt_reg[7]_0 ;
  wire \po_rdval_cnt_reg[8]_0 ;
  wire [2:2]po_stg2_cincdec;
  wire \po_stg2_wrcal_cnt_reg[2] ;
  wire \po_stg2_wrcal_cnt_reg[2]_0 ;
  wire \rank_cnt_r[0]_i_1_n_0 ;
  wire \rank_cnt_r[1]_i_1_n_0 ;
  wire \rank_cnt_r[1]_i_2_n_0 ;
  wire \rank_cnt_r_reg_n_0_[0] ;
  wire \rank_cnt_r_reg_n_0_[1] ;
  wire rd_data_edge_detect_r0;
  wire \rd_data_edge_detect_r[0]_i_1_n_0 ;
  wire \rd_data_edge_detect_r[1]_i_1_n_0 ;
  wire \rd_data_edge_detect_r[2]_i_1_n_0 ;
  wire \rd_data_edge_detect_r[3]_i_1_n_0 ;
  wire \rd_data_edge_detect_r[4]_i_1_n_0 ;
  wire \rd_data_edge_detect_r[5]_i_1_n_0 ;
  wire \rd_data_edge_detect_r[6]_i_1_n_0 ;
  wire \rd_data_edge_detect_r[7]_i_10_n_0 ;
  wire \rd_data_edge_detect_r[7]_i_11_n_0 ;
  wire \rd_data_edge_detect_r[7]_i_2_n_0 ;
  wire \rd_data_edge_detect_r[7]_i_3_n_0 ;
  wire \rd_data_edge_detect_r[7]_i_4_n_0 ;
  wire \rd_data_edge_detect_r[7]_i_6_n_0 ;
  wire \rd_data_edge_detect_r[7]_i_7_n_0 ;
  wire \rd_data_edge_detect_r[7]_i_8_n_0 ;
  wire \rd_data_edge_detect_r_reg[7]_i_5_n_0 ;
  wire \rd_data_edge_detect_r_reg[7]_i_9_n_0 ;
  wire \rd_data_edge_detect_r_reg_n_0_[0] ;
  wire \rd_data_edge_detect_r_reg_n_0_[1] ;
  wire \rd_data_edge_detect_r_reg_n_0_[2] ;
  wire \rd_data_edge_detect_r_reg_n_0_[3] ;
  wire \rd_data_edge_detect_r_reg_n_0_[4] ;
  wire \rd_data_edge_detect_r_reg_n_0_[5] ;
  wire \rd_data_edge_detect_r_reg_n_0_[6] ;
  wire \rd_data_edge_detect_r_reg_n_0_[7] ;
  wire rd_data_previous_r0;
  wire \rd_data_previous_r[7]_i_2_n_0 ;
  wire \rd_data_previous_r[7]_i_3_n_0 ;
  wire \rd_data_previous_r[7]_i_4_n_0 ;
  wire \rd_data_previous_r[7]_i_5_n_0 ;
  wire \rd_data_previous_r_reg_n_0_[0] ;
  wire \rd_data_previous_r_reg_n_0_[1] ;
  wire \rd_data_previous_r_reg_n_0_[2] ;
  wire \rd_data_previous_r_reg_n_0_[3] ;
  wire \rd_data_previous_r_reg_n_0_[4] ;
  wire \rd_data_previous_r_reg_n_0_[5] ;
  wire \rd_data_previous_r_reg_n_0_[6] ;
  wire \rd_data_previous_r_reg_n_0_[7] ;
  wire \single_rank.done_dqs_dec_i_1_n_0 ;
  wire \single_rank.done_dqs_dec_reg_0 ;
  wire \smallest[0][0]_i_3_n_0 ;
  wire \smallest[0][0]_i_4_n_0 ;
  wire \smallest[0][1]_i_3_n_0 ;
  wire \smallest[0][1]_i_4_n_0 ;
  wire \smallest[0][2]_i_3_n_0 ;
  wire \smallest[0][2]_i_4_n_0 ;
  wire \smallest[0][3]_i_3_n_0 ;
  wire \smallest[0][3]_i_4_n_0 ;
  wire \smallest[0][4]_i_3_n_0 ;
  wire \smallest[0][4]_i_4_n_0 ;
  wire \smallest[0][5]_i_1_n_0 ;
  wire \smallest[0][5]_i_3_n_0 ;
  wire \smallest[0][5]_i_5_n_0 ;
  wire \smallest[0][5]_i_6_n_0 ;
  wire \smallest[1][0]_i_1_n_0 ;
  wire \smallest[1][1]_i_1_n_0 ;
  wire \smallest[1][2]_i_1_n_0 ;
  wire \smallest[1][3]_i_1_n_0 ;
  wire \smallest[1][4]_i_1_n_0 ;
  wire \smallest[1][5]_i_1_n_0 ;
  wire \smallest[1][5]_i_2_n_0 ;
  wire \smallest[2][0]_i_1_n_0 ;
  wire \smallest[2][1]_i_1_n_0 ;
  wire \smallest[2][2]_i_1_n_0 ;
  wire \smallest[2][3]_i_1_n_0 ;
  wire \smallest[2][4]_i_1_n_0 ;
  wire \smallest[2][5]_i_1_n_0 ;
  wire \smallest[2][5]_i_2_n_0 ;
  wire \smallest[3][0]_i_1_n_0 ;
  wire \smallest[3][1]_i_1_n_0 ;
  wire \smallest[3][2]_i_1_n_0 ;
  wire \smallest[3][3]_i_1_n_0 ;
  wire \smallest[3][4]_i_1_n_0 ;
  wire \smallest[3][5]_i_1_n_0 ;
  wire \smallest[3][5]_i_2_n_0 ;
  wire \smallest[4][0]_i_1_n_0 ;
  wire \smallest[4][1]_i_1_n_0 ;
  wire \smallest[4][2]_i_1_n_0 ;
  wire \smallest[4][3]_i_1_n_0 ;
  wire \smallest[4][4]_i_1_n_0 ;
  wire \smallest[4][5]_i_1_n_0 ;
  wire \smallest[4][5]_i_2_n_0 ;
  wire \smallest[5][0]_i_1_n_0 ;
  wire \smallest[5][1]_i_1_n_0 ;
  wire \smallest[5][2]_i_1_n_0 ;
  wire \smallest[5][3]_i_1_n_0 ;
  wire \smallest[5][4]_i_1_n_0 ;
  wire \smallest[5][5]_i_1_n_0 ;
  wire \smallest[5][5]_i_2_n_0 ;
  wire \smallest[6][0]_i_1_n_0 ;
  wire \smallest[6][1]_i_1_n_0 ;
  wire \smallest[6][2]_i_1_n_0 ;
  wire \smallest[6][3]_i_1_n_0 ;
  wire \smallest[6][4]_i_1_n_0 ;
  wire \smallest[6][5]_i_1_n_0 ;
  wire \smallest[6][5]_i_2_n_0 ;
  wire \smallest[7][0]_i_1_n_0 ;
  wire \smallest[7][1]_i_1_n_0 ;
  wire \smallest[7][2]_i_1_n_0 ;
  wire \smallest[7][3]_i_1_n_0 ;
  wire \smallest[7][4]_i_1_n_0 ;
  wire \smallest[7][5]_i_1_n_0 ;
  wire \smallest[7][5]_i_2_n_0 ;
  wire \smallest_reg[0][0]_i_2_n_0 ;
  wire \smallest_reg[0][1]_i_2_n_0 ;
  wire \smallest_reg[0][2]_i_2_n_0 ;
  wire \smallest_reg[0][3]_i_2_n_0 ;
  wire \smallest_reg[0][4]_i_2_n_0 ;
  wire \smallest_reg[0][5]_i_4_n_0 ;
  wire [5:0]\smallest_reg[0]_13 ;
  wire [5:0]\smallest_reg[1]_14 ;
  wire [5:0]\smallest_reg[2]_15 ;
  wire [5:0]\smallest_reg[3]_16 ;
  wire [5:0]\smallest_reg[4]_17 ;
  wire [5:0]\smallest_reg[5]_18 ;
  wire [5:0]\smallest_reg[6]_19 ;
  wire [5:0]\smallest_reg[7]_20 ;
  wire stable_cnt;
  wire stable_cnt0;
  wire \stable_cnt[3]_i_4_n_0 ;
  wire \stable_cnt[3]_i_5_n_0 ;
  wire \stable_cnt[3]_i_6_n_0 ;
  wire \stable_cnt[3]_i_7_n_0 ;
  wire \stable_cnt[3]_i_8_n_0 ;
  wire \stable_cnt[3]_i_9_n_0 ;
  wire \stable_cnt_reg_n_0_[0] ;
  wire \stable_cnt_reg_n_0_[1] ;
  wire \stable_cnt_reg_n_0_[2] ;
  wire \stable_cnt_reg_n_0_[3] ;
  wire wait_cnt0;
  wire [3:0]wait_cnt0__0;
  wire \wait_cnt[1]_i_1_n_0 ;
  wire [3:0]wait_cnt_reg;
  wire [0:0]\wait_cnt_reg[0]_0 ;
  wire wl_corse_cnt;
  wire \wl_corse_cnt[0][0][0]_i_2_n_0 ;
  wire \wl_corse_cnt[0][0][0]_i_3_n_0 ;
  wire \wl_corse_cnt[0][0][1]_i_2_n_0 ;
  wire \wl_corse_cnt[0][0][1]_i_3_n_0 ;
  wire \wl_corse_cnt[0][0][2]_i_2_n_0 ;
  wire \wl_corse_cnt[0][0][2]_i_3_n_0 ;
  wire \wl_corse_cnt_reg[0][0][0]_i_1_n_0 ;
  wire \wl_corse_cnt_reg[0][0][1]_i_1_n_0 ;
  wire \wl_corse_cnt_reg[0][0][2]_i_1_n_0 ;
  wire [2:0]\wl_corse_cnt_reg[0][0]_29 ;
  wire [2:0]\wl_corse_cnt_reg[0][1]_30 ;
  wire [2:0]\wl_corse_cnt_reg[0][2]_31 ;
  wire [2:0]\wl_corse_cnt_reg[0][3]_32 ;
  wire [2:0]\wl_corse_cnt_reg[0][4]_33 ;
  wire [2:0]\wl_corse_cnt_reg[0][5]_34 ;
  wire [2:0]\wl_corse_cnt_reg[0][6]_35 ;
  wire [2:0]\wl_corse_cnt_reg[0][7]_36 ;
  wire \wl_dqs_tap_count_r[0][0][5]_i_2_n_0 ;
  wire \wl_dqs_tap_count_r[0][0][5]_i_3_n_0 ;
  wire \wl_dqs_tap_count_r[0][1][5]_i_1_n_0 ;
  wire \wl_dqs_tap_count_r[0][2][5]_i_1_n_0 ;
  wire \wl_dqs_tap_count_r[0][3][5]_i_1_n_0 ;
  wire \wl_dqs_tap_count_r[0][4][5]_i_1_n_0 ;
  wire \wl_dqs_tap_count_r[0][5][5]_i_1_n_0 ;
  wire \wl_dqs_tap_count_r[0][6][5]_i_1_n_0 ;
  wire \wl_dqs_tap_count_r[0][7][5]_i_1_n_0 ;
  wire \wl_dqs_tap_count_r_reg[0][5][5]_0 ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][0][0] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][0][1] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][0][2] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][0][3] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][0][4] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][0][5] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][1][0] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][1][1] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][1][2] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][1][3] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][1][4] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][1][5] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][2][0] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][2][1] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][2][2] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][2][3] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][2][4] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][2][5] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][3][0] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][3][1] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][3][2] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][3][3] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][3][4] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][3][5] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][4][0] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][4][1] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][4][2] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][4][3] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][4][4] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][4][5] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][5][0] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][5][1] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][5][2] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][5][3] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][5][4] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][5][5] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][6][0] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][6][1] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][6][2] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][6][3] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][6][4] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][6][5] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][7][0] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][7][1] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][7][2] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][7][3] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][7][4] ;
  wire \wl_dqs_tap_count_r_reg_n_0_[0][7][5] ;
  wire wl_edge_detect_valid_r_i_1_n_0;
  wire wl_edge_detect_valid_r_reg_n_0;
  wire wl_sm_start;
  wire \wl_state_r1[0]_i_1_n_0 ;
  wire \wl_state_r1[1]_i_1_n_0 ;
  wire \wl_state_r1[2]_i_1_n_0 ;
  wire \wl_state_r1[3]_i_1_n_0 ;
  wire \wl_state_r1[4]_i_1_n_0 ;
  wire \wl_state_r1_reg_n_0_[0] ;
  wire \wl_state_r1_reg_n_0_[1] ;
  wire \wl_state_r1_reg_n_0_[2] ;
  wire \wl_state_r1_reg_n_0_[3] ;
  wire \wl_state_r1_reg_n_0_[4] ;
  wire [2:0]wl_state_r__0;
  wire [5:0]wl_tap_count_r;
  wire \wl_tap_count_r[0]_i_3_n_0 ;
  wire \wl_tap_count_r[0]_i_4_n_0 ;
  wire \wl_tap_count_r[1]_i_3_n_0 ;
  wire \wl_tap_count_r[1]_i_4_n_0 ;
  wire \wl_tap_count_r[2]_i_2_n_0 ;
  wire \wl_tap_count_r[2]_i_4_n_0 ;
  wire \wl_tap_count_r[2]_i_5_n_0 ;
  wire \wl_tap_count_r[3]_i_3_n_0 ;
  wire \wl_tap_count_r[3]_i_4_n_0 ;
  wire \wl_tap_count_r[3]_i_5_n_0 ;
  wire \wl_tap_count_r[4]_i_2_n_0 ;
  wire \wl_tap_count_r[4]_i_3_n_0 ;
  wire \wl_tap_count_r[4]_i_4_n_0 ;
  wire \wl_tap_count_r[4]_i_6_n_0 ;
  wire \wl_tap_count_r[4]_i_7_n_0 ;
  wire \wl_tap_count_r[5]_i_1_n_0 ;
  wire \wl_tap_count_r[5]_i_4_n_0 ;
  wire \wl_tap_count_r[5]_i_6_n_0 ;
  wire \wl_tap_count_r[5]_i_7_n_0 ;
  wire \wl_tap_count_r_reg[0]_i_2_n_0 ;
  wire \wl_tap_count_r_reg[1]_i_2_n_0 ;
  wire \wl_tap_count_r_reg[2]_i_3_n_0 ;
  wire \wl_tap_count_r_reg[3]_i_2_n_0 ;
  wire \wl_tap_count_r_reg[4]_i_5_n_0 ;
  wire \wl_tap_count_r_reg[5]_i_5_n_0 ;
  wire \wl_tap_count_r_reg_n_0_[0] ;
  wire \wl_tap_count_r_reg_n_0_[1] ;
  wire \wl_tap_count_r_reg_n_0_[2] ;
  wire \wl_tap_count_r_reg_n_0_[3] ;
  wire \wl_tap_count_r_reg_n_0_[4] ;
  wire \wl_tap_count_r_reg_n_0_[5] ;
  wire wr_level_done_i_1_n_0;
  wire wr_level_done_r1;
  wire wr_level_done_r2;
  wire wr_level_done_r3;
  wire wr_level_done_r4;
  wire wr_level_done_r5;
  wire wr_level_done_r_i_1_n_0;
  wire wr_level_done_r_i_2_n_0;
  wire wr_level_done_r_reg_n_0;
  wire wr_level_done_reg_0;
  wire wr_level_start_r;
  wire wr_level_start_r_reg_0;
  wire wrlvl_byte_done;
  wire wrlvl_byte_done_i_1_n_0;
  wire wrlvl_byte_redo;
  wire wrlvl_byte_redo_r;
  wire wrlvl_rank_done;
  wire wrlvl_rank_done_r_i_1_n_0;
  wire wrlvl_rank_done_r_i_2_n_0;
  wire wrlvl_rank_done_r_i_3_n_0;
  wire \wrlvl_redo_corse_inc[0]_i_1_n_0 ;
  wire \wrlvl_redo_corse_inc[1]_i_1_n_0 ;
  wire \wrlvl_redo_corse_inc[2]_i_10_n_0 ;
  wire \wrlvl_redo_corse_inc[2]_i_11_n_0 ;
  wire \wrlvl_redo_corse_inc[2]_i_12_n_0 ;
  wire \wrlvl_redo_corse_inc[2]_i_1_n_0 ;
  wire \wrlvl_redo_corse_inc[2]_i_2_n_0 ;
  wire \wrlvl_redo_corse_inc[2]_i_3_n_0 ;
  wire \wrlvl_redo_corse_inc[2]_i_4_0 ;
  wire \wrlvl_redo_corse_inc[2]_i_4_n_0 ;
  wire \wrlvl_redo_corse_inc[2]_i_7_n_0 ;
  wire \wrlvl_redo_corse_inc[2]_i_8_n_0 ;
  wire \wrlvl_redo_corse_inc[2]_i_9_n_0 ;
  wire \wrlvl_redo_corse_inc_reg[2]_0 ;
  wire \wrlvl_redo_corse_inc_reg_n_0_[0] ;
  wire \wrlvl_redo_corse_inc_reg_n_0_[1] ;
  wire \wrlvl_redo_corse_inc_reg_n_0_[2] ;

  LUT6 #(
    .INIT(64'h00000000FFFFEAAA)) 
    \FSM_sequential_wl_state_r[0]_i_1 
       (.I0(\FSM_sequential_wl_state_r[0]_i_2_n_0 ),
        .I1(wl_state_r__0[1]),
        .I2(\FSM_sequential_wl_state_r[0]_i_3_n_0 ),
        .I3(\FSM_sequential_wl_state_r[0]_i_4_n_0 ),
        .I4(\FSM_sequential_wl_state_r[0]_i_5_n_0 ),
        .I5(\FSM_sequential_wl_state_r[0]_i_6_n_0 ),
        .O(\FSM_sequential_wl_state_r[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFA0FFACFFACFFACF)) 
    \FSM_sequential_wl_state_r[0]_i_10 
       (.I0(\fine_dec_cnt[5]_i_5_n_0 ),
        .I1(\FSM_sequential_wl_state_r[4]_i_17_n_0 ),
        .I2(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I4(wrlvl_byte_redo),
        .I5(\FSM_sequential_wl_state_r[2]_i_9_n_0 ),
        .O(\FSM_sequential_wl_state_r[0]_i_10_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair380" *) 
  LUT3 #(
    .INIT(8'hBE)) 
    \FSM_sequential_wl_state_r[0]_i_11 
       (.I0(wl_state_r__0[0]),
        .I1(wl_state_r__0[2]),
        .I2(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .O(\FSM_sequential_wl_state_r[0]_i_11_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair372" *) 
  LUT3 #(
    .INIT(8'h45)) 
    \FSM_sequential_wl_state_r[0]_i_12 
       (.I0(wl_state_r__0[2]),
        .I1(wl_state_r__0[0]),
        .I2(\FSM_sequential_wl_state_r[4]_i_17_n_0 ),
        .O(\FSM_sequential_wl_state_r[0]_i_12_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair303" *) 
  LUT5 #(
    .INIT(32'hFF5DFFFF)) 
    \FSM_sequential_wl_state_r[0]_i_14 
       (.I0(\fine_inc[7][5]_i_3_n_0 ),
        .I1(wrlvl_byte_redo),
        .I2(wl_state_r__0[0]),
        .I3(wl_state_r__0[2]),
        .I4(wl_state_r__0[1]),
        .O(\FSM_sequential_wl_state_r[0]_i_14_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair301" *) 
  LUT3 #(
    .INIT(8'h80)) 
    \FSM_sequential_wl_state_r[0]_i_15 
       (.I0(\wl_tap_count_r_reg_n_0_[3] ),
        .I1(\wl_tap_count_r_reg_n_0_[4] ),
        .I2(\wl_tap_count_r_reg_n_0_[5] ),
        .O(\FSM_sequential_wl_state_r[0]_i_15_n_0 ));
  LUT6 #(
    .INIT(64'h2000022200000222)) 
    \FSM_sequential_wl_state_r[0]_i_2 
       (.I0(\FSM_sequential_wl_state_r[0]_i_7_n_0 ),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I2(wl_state_r__0[2]),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I4(wl_state_r__0[0]),
        .I5(wr_level_done_r5),
        .O(\FSM_sequential_wl_state_r[0]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair313" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \FSM_sequential_wl_state_r[0]_i_3 
       (.I0(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I1(wl_state_r__0[2]),
        .O(\FSM_sequential_wl_state_r[0]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h44444F4444444444)) 
    \FSM_sequential_wl_state_r[0]_i_4 
       (.I0(\FSM_sequential_wl_state_r[0]_i_8_n_0 ),
        .I1(\FSM_sequential_wl_state_r[0]_i_9_n_0 ),
        .I2(\FSM_sequential_wl_state_r[2]_i_9_n_0 ),
        .I3(\rd_data_edge_detect_r[7]_i_4_n_0 ),
        .I4(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I5(wrlvl_byte_redo),
        .O(\FSM_sequential_wl_state_r[0]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h00000000F4F400FF)) 
    \FSM_sequential_wl_state_r[0]_i_5 
       (.I0(wl_state_r__0[0]),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I2(\FSM_sequential_wl_state_r[0]_i_10_n_0 ),
        .I3(\FSM_sequential_wl_state_r[0]_i_11_n_0 ),
        .I4(\FSM_sequential_wl_state_r[0]_i_12_n_0 ),
        .I5(wl_state_r__0[1]),
        .O(\FSM_sequential_wl_state_r[0]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000AA2000)) 
    \FSM_sequential_wl_state_r[0]_i_6 
       (.I0(\fine_inc[0][5]_i_3_n_0 ),
        .I1(\FSM_sequential_wl_state_r_reg[0]_0 ),
        .I2(\FSM_sequential_wl_state_r[4]_i_11_n_0 ),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I4(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I5(\FSM_sequential_wl_state_r[0]_i_14_n_0 ),
        .O(\FSM_sequential_wl_state_r[0]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFBF)) 
    \FSM_sequential_wl_state_r[0]_i_7 
       (.I0(wl_state_r__0[0]),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I2(wrlvl_byte_redo),
        .I3(\wrlvl_redo_corse_inc_reg_n_0_[1] ),
        .I4(\wrlvl_redo_corse_inc_reg_n_0_[0] ),
        .I5(\wrlvl_redo_corse_inc_reg_n_0_[2] ),
        .O(\FSM_sequential_wl_state_r[0]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h0000FB00FFFF0000)) 
    \FSM_sequential_wl_state_r[0]_i_8 
       (.I0(\rd_data_edge_detect_r_reg[7]_i_5_n_0 ),
        .I1(wl_edge_detect_valid_r_reg_n_0),
        .I2(\FSM_sequential_wl_state_r[0]_i_15_n_0 ),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I4(wl_state_r__0[2]),
        .I5(wl_state_r__0[0]),
        .O(\FSM_sequential_wl_state_r[0]_i_8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair306" *) 
  LUT5 #(
    .INIT(32'hFFFEF0F0)) 
    \FSM_sequential_wl_state_r[0]_i_9 
       (.I0(\corse_dec_reg[0][2]_i_2_n_0 ),
        .I1(\corse_dec_reg[0][2]_i_3_n_0 ),
        .I2(wl_state_r__0[0]),
        .I3(\corse_dec_reg[0][2]_i_10_n_0 ),
        .I4(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .O(\FSM_sequential_wl_state_r[0]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hFFF4FFF4FFFFFFF4)) 
    \FSM_sequential_wl_state_r[1]_i_1 
       (.I0(\FSM_sequential_wl_state_r[1]_i_2_n_0 ),
        .I1(\FSM_sequential_wl_state_r[1]_i_3_n_0 ),
        .I2(\FSM_sequential_wl_state_r[1]_i_4_n_0 ),
        .I3(\FSM_sequential_wl_state_r[1]_i_5_n_0 ),
        .I4(\FSM_sequential_wl_state_r[1]_i_6_n_0 ),
        .I5(\FSM_sequential_wl_state_r[1]_i_7_n_0 ),
        .O(\FSM_sequential_wl_state_r[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair322" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \FSM_sequential_wl_state_r[1]_i_10 
       (.I0(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I1(wl_state_r__0[1]),
        .O(\FSM_sequential_wl_state_r[1]_i_10_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair359" *) 
  LUT4 #(
    .INIT(16'h0100)) 
    \FSM_sequential_wl_state_r[1]_i_11 
       (.I0(\wrlvl_redo_corse_inc_reg_n_0_[2] ),
        .I1(\wrlvl_redo_corse_inc_reg_n_0_[0] ),
        .I2(\wrlvl_redo_corse_inc_reg_n_0_[1] ),
        .I3(wrlvl_byte_redo),
        .O(\FSM_sequential_wl_state_r[1]_i_11_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair300" *) 
  LUT5 #(
    .INIT(32'hDD5FDD55)) 
    \FSM_sequential_wl_state_r[1]_i_2 
       (.I0(wl_state_r__0[0]),
        .I1(wl_state_r__0[1]),
        .I2(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I3(wl_state_r__0[2]),
        .I4(\FSM_sequential_wl_state_r[3]_i_14_n_0 ),
        .O(\FSM_sequential_wl_state_r[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF22E2FFFFCCCC)) 
    \FSM_sequential_wl_state_r[1]_i_3 
       (.I0(\fine_inc[0][5]_i_3_n_0 ),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I2(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I3(\FSM_sequential_wl_state_r[1]_i_8_n_0 ),
        .I4(wl_state_r__0[2]),
        .I5(wl_state_r__0[1]),
        .O(\FSM_sequential_wl_state_r[1]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h00190019FF000000)) 
    \FSM_sequential_wl_state_r[1]_i_4 
       (.I0(wl_state_r__0[2]),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I2(\FSM_sequential_wl_state_r[4]_i_11_n_0 ),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I4(\FSM_sequential_wl_state_r[4]_i_17_n_0 ),
        .I5(wl_state_r__0[1]),
        .O(\FSM_sequential_wl_state_r[1]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h5504555555045504)) 
    \FSM_sequential_wl_state_r[1]_i_5 
       (.I0(wl_state_r__0[0]),
        .I1(\rd_data_edge_detect_r[7]_i_4_n_0 ),
        .I2(\FSM_sequential_wl_state_r[1]_i_9_n_0 ),
        .I3(\FSM_sequential_wl_state_r[3]_i_2_n_0 ),
        .I4(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I5(\FSM_sequential_wl_state_r[1]_i_10_n_0 ),
        .O(\FSM_sequential_wl_state_r[1]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFEFFFEFEFFFFFFFF)) 
    \FSM_sequential_wl_state_r[1]_i_6 
       (.I0(\fine_inc[0][5]_i_3_n_0 ),
        .I1(wrlvl_byte_redo),
        .I2(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I3(wr_level_done_r5),
        .I4(wl_sm_start),
        .I5(\FSM_sequential_wl_state_r[4]_i_11_n_0 ),
        .O(\FSM_sequential_wl_state_r[1]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hF7FFF7F3FFFFFFFF)) 
    \FSM_sequential_wl_state_r[1]_i_7 
       (.I0(\FSM_sequential_wl_state_r[4]_i_16_n_0 ),
        .I1(wl_state_r__0[1]),
        .I2(wl_state_r__0[0]),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I4(\FSM_sequential_wl_state_r[1]_i_11_n_0 ),
        .I5(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .O(\FSM_sequential_wl_state_r[1]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h8AAAAAAAAAAAAAAA)) 
    \FSM_sequential_wl_state_r[1]_i_8 
       (.I0(wl_edge_detect_valid_r_reg_n_0),
        .I1(\rd_data_edge_detect_r_reg[7]_i_5_n_0 ),
        .I2(\wl_tap_count_r_reg_n_0_[5] ),
        .I3(\wl_tap_count_r_reg_n_0_[4] ),
        .I4(\wl_tap_count_r_reg_n_0_[3] ),
        .I5(\FSM_sequential_wl_state_r[3]_i_7_n_0 ),
        .O(\FSM_sequential_wl_state_r[1]_i_8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair381" *) 
  LUT3 #(
    .INIT(8'hDF)) 
    \FSM_sequential_wl_state_r[1]_i_9 
       (.I0(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I2(wrlvl_byte_redo),
        .O(\FSM_sequential_wl_state_r[1]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hAAA8AAAAA8A8A8A8)) 
    \FSM_sequential_wl_state_r[2]_i_1 
       (.I0(\FSM_sequential_wl_state_r[2]_i_2_n_0 ),
        .I1(\FSM_sequential_wl_state_r[2]_i_3_n_0 ),
        .I2(\FSM_sequential_wl_state_r[2]_i_4_n_0 ),
        .I3(\FSM_sequential_wl_state_r[2]_i_5_n_0 ),
        .I4(\FSM_sequential_wl_state_r[2]_i_6_n_0 ),
        .I5(\FSM_sequential_wl_state_r[2]_i_7_n_0 ),
        .O(\FSM_sequential_wl_state_r[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF5200F200)) 
    \FSM_sequential_wl_state_r[2]_i_10 
       (.I0(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I1(\fine_dec_cnt[5]_i_5_n_0 ),
        .I2(wl_state_r__0[2]),
        .I3(wl_state_r__0[0]),
        .I4(wr_level_done_r5),
        .I5(\FSM_sequential_wl_state_r[2]_i_14_n_0 ),
        .O(\FSM_sequential_wl_state_r[2]_i_10_n_0 ));
  LUT3 #(
    .INIT(8'h08)) 
    \FSM_sequential_wl_state_r[2]_i_11 
       (.I0(wr_level_start_r),
        .I1(wl_sm_start),
        .I2(wr_level_done_r_reg_n_0),
        .O(\FSM_sequential_wl_state_r[2]_i_11_n_0 ));
  LUT6 #(
    .INIT(64'hFE00FFFFFFFFFFFF)) 
    \FSM_sequential_wl_state_r[2]_i_12 
       (.I0(\wrlvl_redo_corse_inc_reg_n_0_[1] ),
        .I1(\wrlvl_redo_corse_inc_reg_n_0_[0] ),
        .I2(\wrlvl_redo_corse_inc_reg_n_0_[2] ),
        .I3(wrlvl_byte_redo),
        .I4(\dqs_count_r[3]_i_12_n_0 ),
        .I5(\wl_tap_count_r[4]_i_4_n_0 ),
        .O(\FSM_sequential_wl_state_r[2]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'h333337333333F733)) 
    \FSM_sequential_wl_state_r[2]_i_13 
       (.I0(p_0_in),
        .I1(wl_state_r__0[1]),
        .I2(wl_state_r__0[2]),
        .I3(wl_state_r__0[0]),
        .I4(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I5(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .O(\FSM_sequential_wl_state_r[2]_i_13_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair315" *) 
  LUT5 #(
    .INIT(32'hFFFFC800)) 
    \FSM_sequential_wl_state_r[2]_i_14 
       (.I0(\FSM_sequential_wl_state_r[4]_i_17_n_0 ),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I2(wl_state_r__0[0]),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I4(wl_state_r__0[1]),
        .O(\FSM_sequential_wl_state_r[2]_i_14_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF80000000)) 
    \FSM_sequential_wl_state_r[2]_i_2 
       (.I0(\FSM_sequential_wl_state_r[2]_i_8_n_0 ),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I2(wl_state_r__0[0]),
        .I3(wrlvl_byte_redo),
        .I4(\FSM_sequential_wl_state_r[2]_i_9_n_0 ),
        .I5(\FSM_sequential_wl_state_r[2]_i_10_n_0 ),
        .O(\FSM_sequential_wl_state_r[2]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair327" *) 
  LUT5 #(
    .INIT(32'h80A00020)) 
    \FSM_sequential_wl_state_r[2]_i_3 
       (.I0(wl_state_r__0[2]),
        .I1(wl_state_r__0[0]),
        .I2(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I3(\FSM_sequential_wl_state_r[2]_i_11_n_0 ),
        .I4(\FSM_sequential_wl_state_r[4]_i_11_n_0 ),
        .O(\FSM_sequential_wl_state_r[2]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF54545554)) 
    \FSM_sequential_wl_state_r[2]_i_4 
       (.I0(\FSM_sequential_wl_state_r[2]_i_12_n_0 ),
        .I1(\FSM_sequential_wl_state_r[4]_i_11_n_0 ),
        .I2(wrlvl_byte_redo),
        .I3(wl_sm_start),
        .I4(wr_level_done_r5),
        .I5(\FSM_sequential_wl_state_r[2]_i_13_n_0 ),
        .O(\FSM_sequential_wl_state_r[2]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair356" *) 
  LUT4 #(
    .INIT(16'h008F)) 
    \FSM_sequential_wl_state_r[2]_i_5 
       (.I0(\FSM_sequential_wl_state_r[2]_i_9_n_0 ),
        .I1(\rd_data_edge_detect_r[7]_i_4_n_0 ),
        .I2(wrlvl_byte_redo),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .O(\FSM_sequential_wl_state_r[2]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h20202020FFFF00FF)) 
    \FSM_sequential_wl_state_r[2]_i_6 
       (.I0(\FSM_sequential_wl_state_r[3]_i_3_n_0 ),
        .I1(\rd_data_edge_detect_r_reg[7]_i_5_n_0 ),
        .I2(wl_edge_detect_valid_r_reg_n_0),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I4(\FSM_sequential_wl_state_r[4]_i_16_n_0 ),
        .I5(wl_state_r__0[0]),
        .O(\FSM_sequential_wl_state_r[2]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair304" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \FSM_sequential_wl_state_r[2]_i_7 
       (.I0(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I1(wl_state_r__0[2]),
        .O(\FSM_sequential_wl_state_r[2]_i_7_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair381" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \FSM_sequential_wl_state_r[2]_i_8 
       (.I0(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I1(\FSM_sequential_wl_state_r[4]_i_17_n_0 ),
        .O(\FSM_sequential_wl_state_r[2]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFE888E8880000)) 
    \FSM_sequential_wl_state_r[2]_i_9 
       (.I0(\wl_corse_cnt_reg[0][0][1]_i_1_n_0 ),
        .I1(\wrlvl_redo_corse_inc_reg_n_0_[1] ),
        .I2(\wl_corse_cnt_reg[0][0][0]_i_1_n_0 ),
        .I3(\wrlvl_redo_corse_inc_reg_n_0_[0] ),
        .I4(\wl_corse_cnt_reg[0][0][2]_i_1_n_0 ),
        .I5(\wrlvl_redo_corse_inc_reg_n_0_[2] ),
        .O(\FSM_sequential_wl_state_r[2]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFBA00)) 
    \FSM_sequential_wl_state_r[3]_i_1 
       (.I0(\FSM_sequential_wl_state_r[3]_i_2_n_0 ),
        .I1(\FSM_sequential_wl_state_r[3]_i_3_n_0 ),
        .I2(\FSM_sequential_wl_state_r[3]_i_4_n_0 ),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I4(\FSM_sequential_wl_state_r[3]_i_5_n_0 ),
        .I5(\FSM_sequential_wl_state_r[3]_i_6_n_0 ),
        .O(\FSM_sequential_wl_state_r[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair380" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \FSM_sequential_wl_state_r[3]_i_10 
       (.I0(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I1(wl_state_r__0[0]),
        .O(\FSM_sequential_wl_state_r[3]_i_10_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair357" *) 
  LUT4 #(
    .INIT(16'h0100)) 
    \FSM_sequential_wl_state_r[3]_i_11 
       (.I0(p_0_in),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I2(wl_state_r__0[2]),
        .I3(wl_state_r__0[0]),
        .O(\FSM_sequential_wl_state_r[3]_i_11_n_0 ));
  LUT6 #(
    .INIT(64'h000000FB00000000)) 
    \FSM_sequential_wl_state_r[3]_i_12 
       (.I0(wrlvl_byte_redo),
        .I1(wl_sm_start),
        .I2(wr_level_done_r5),
        .I3(wl_state_r__0[0]),
        .I4(wl_state_r__0[2]),
        .I5(\wl_tap_count_r[4]_i_4_n_0 ),
        .O(\FSM_sequential_wl_state_r[3]_i_12_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair344" *) 
  LUT5 #(
    .INIT(32'h82A22020)) 
    \FSM_sequential_wl_state_r[3]_i_13 
       (.I0(wl_state_r__0[2]),
        .I1(wl_state_r__0[0]),
        .I2(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I3(\FSM_sequential_wl_state_r[2]_i_11_n_0 ),
        .I4(wl_state_r__0[1]),
        .O(\FSM_sequential_wl_state_r[3]_i_13_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair351" *) 
  LUT4 #(
    .INIT(16'hBFFF)) 
    \FSM_sequential_wl_state_r[3]_i_14 
       (.I0(\rd_data_edge_detect_r_reg[7]_i_9_n_0 ),
        .I1(\stable_cnt_reg_n_0_[3] ),
        .I2(\stable_cnt_reg_n_0_[1] ),
        .I3(\stable_cnt_reg_n_0_[2] ),
        .O(\FSM_sequential_wl_state_r[3]_i_14_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair345" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \FSM_sequential_wl_state_r[3]_i_2 
       (.I0(wl_state_r__0[1]),
        .I1(wl_state_r__0[2]),
        .O(\FSM_sequential_wl_state_r[3]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair301" *) 
  LUT5 #(
    .INIT(32'h00008000)) 
    \FSM_sequential_wl_state_r[3]_i_3 
       (.I0(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I1(\wl_tap_count_r_reg_n_0_[3] ),
        .I2(\wl_tap_count_r_reg_n_0_[4] ),
        .I3(\wl_tap_count_r_reg_n_0_[5] ),
        .I4(\FSM_sequential_wl_state_r[3]_i_7_n_0 ),
        .O(\FSM_sequential_wl_state_r[3]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h00002F00AFAFAFAF)) 
    \FSM_sequential_wl_state_r[3]_i_4 
       (.I0(wl_edge_detect_valid_r_reg_n_0),
        .I1(\rd_data_edge_detect_r_reg[7]_i_5_n_0 ),
        .I2(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I3(wl_state_r__0[0]),
        .I4(\FSM_sequential_wl_state_r[3]_i_8_n_0 ),
        .I5(\FSM_sequential_wl_state_r[3]_i_9_n_0 ),
        .O(\FSM_sequential_wl_state_r[3]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFF404)) 
    \FSM_sequential_wl_state_r[3]_i_5 
       (.I0(\FSM_sequential_wl_state_r[4]_i_17_n_0 ),
        .I1(\FSM_sequential_wl_state_r[3]_i_10_n_0 ),
        .I2(wl_state_r__0[1]),
        .I3(\FSM_sequential_wl_state_r[3]_i_11_n_0 ),
        .I4(\FSM_sequential_wl_state_r[3]_i_12_n_0 ),
        .I5(\FSM_sequential_wl_state_r[3]_i_13_n_0 ),
        .O(\FSM_sequential_wl_state_r[3]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h0002000000020002)) 
    \FSM_sequential_wl_state_r[3]_i_6 
       (.I0(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I1(wl_state_r__0[1]),
        .I2(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I3(wl_state_r__0[2]),
        .I4(\FSM_sequential_wl_state_r[3]_i_14_n_0 ),
        .I5(wl_state_r__0[0]),
        .O(\FSM_sequential_wl_state_r[3]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair375" *) 
  LUT3 #(
    .INIT(8'h80)) 
    \FSM_sequential_wl_state_r[3]_i_7 
       (.I0(\wl_corse_cnt_reg[0][0][2]_i_1_n_0 ),
        .I1(\wl_corse_cnt_reg[0][0][1]_i_1_n_0 ),
        .I2(\wl_corse_cnt_reg[0][0][0]_i_1_n_0 ),
        .O(\FSM_sequential_wl_state_r[3]_i_7_n_0 ));
  LUT2 #(
    .INIT(4'hB)) 
    \FSM_sequential_wl_state_r[3]_i_8 
       (.I0(wl_state_r__0[2]),
        .I1(wl_state_r__0[1]),
        .O(\FSM_sequential_wl_state_r[3]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'h4F4F4F4FFF4F4F4F)) 
    \FSM_sequential_wl_state_r[3]_i_9 
       (.I0(\FSM_sequential_wl_state_r[4]_i_17_n_0 ),
        .I1(wl_state_r__0[0]),
        .I2(\dqs_count_r[3]_i_4_n_0 ),
        .I3(wl_state_r__0[1]),
        .I4(wrlvl_byte_redo),
        .I5(\rd_data_edge_detect_r[7]_i_4_n_0 ),
        .O(\FSM_sequential_wl_state_r[3]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF0054FF54)) 
    \FSM_sequential_wl_state_r[4]_i_1 
       (.I0(\FSM_sequential_wl_state_r[4]_i_3_n_0 ),
        .I1(\FSM_sequential_wl_state_r[4]_i_4_n_0 ),
        .I2(\FSM_sequential_wl_state_r[4]_i_5_n_0 ),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I4(\FSM_sequential_wl_state_r[4]_i_6_n_0 ),
        .I5(\FSM_sequential_wl_state_r_reg[4]_i_7_n_0 ),
        .O(\FSM_sequential_wl_state_r[4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hCA000A00FFFFFFFF)) 
    \FSM_sequential_wl_state_r[4]_i_10 
       (.I0(\fine_dec_cnt[5]_i_5_n_0 ),
        .I1(\rd_data_edge_detect_r_reg[7]_i_5_n_0 ),
        .I2(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I4(wl_edge_detect_valid_r_reg_n_0),
        .I5(\FSM_sequential_wl_state_r[4]_i_20_n_0 ),
        .O(\FSM_sequential_wl_state_r[4]_i_10_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair361" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \FSM_sequential_wl_state_r[4]_i_11 
       (.I0(\corse_inc[0][2]_i_7_n_0 ),
        .I1(\corse_inc_reg[0][2]_i_6_n_0 ),
        .O(\FSM_sequential_wl_state_r[4]_i_11_n_0 ));
  LUT6 #(
    .INIT(64'h7070707000707070)) 
    \FSM_sequential_wl_state_r[4]_i_12 
       (.I0(\wrlvl_redo_corse_inc[2]_i_4_0 ),
        .I1(done_dqs_dec238_out),
        .I2(wl_state_r__0[1]),
        .I3(wr_level_start_r),
        .I4(wl_sm_start),
        .I5(wr_level_done_r_reg_n_0),
        .O(\FSM_sequential_wl_state_r[4]_i_12_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair347" *) 
  LUT4 #(
    .INIT(16'hFFEF)) 
    \FSM_sequential_wl_state_r[4]_i_13 
       (.I0(incdec_wait_cnt_reg[1]),
        .I1(incdec_wait_cnt_reg[0]),
        .I2(incdec_wait_cnt_reg[3]),
        .I3(incdec_wait_cnt_reg[2]),
        .O(\FSM_sequential_wl_state_r[4]_i_13_n_0 ));
  LUT5 #(
    .INIT(32'h08A008AF)) 
    \FSM_sequential_wl_state_r[4]_i_14 
       (.I0(wl_sm_start),
        .I1(wl_state_r__0[0]),
        .I2(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I3(wl_state_r__0[2]),
        .I4(\FSM_sequential_wl_state_r[4]_i_13_n_0 ),
        .O(\FSM_sequential_wl_state_r[4]_i_14_n_0 ));
  LUT5 #(
    .INIT(32'h55551110)) 
    \FSM_sequential_wl_state_r[4]_i_15 
       (.I0(wl_state_r__0[2]),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I2(wl_sm_start),
        .I3(wrlvl_byte_redo),
        .I4(wl_state_r__0[0]),
        .O(\FSM_sequential_wl_state_r[4]_i_15_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair306" *) 
  LUT3 #(
    .INIT(8'h01)) 
    \FSM_sequential_wl_state_r[4]_i_16 
       (.I0(\corse_dec_reg[0][2]_i_2_n_0 ),
        .I1(\corse_dec_reg[0][2]_i_3_n_0 ),
        .I2(\corse_dec_reg[0][2]_i_10_n_0 ),
        .O(\FSM_sequential_wl_state_r[4]_i_16_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \FSM_sequential_wl_state_r[4]_i_17 
       (.I0(\fine_dec_cnt_reg_n_0_[3] ),
        .I1(\fine_dec_cnt_reg_n_0_[0] ),
        .I2(\fine_dec_cnt_reg_n_0_[1] ),
        .I3(\fine_dec_cnt_reg_n_0_[2] ),
        .I4(\fine_dec_cnt_reg_n_0_[4] ),
        .I5(\fine_dec_cnt_reg_n_0_[5] ),
        .O(\FSM_sequential_wl_state_r[4]_i_17_n_0 ));
  LUT6 #(
    .INIT(64'h4444000040000000)) 
    \FSM_sequential_wl_state_r[4]_i_18 
       (.I0(wl_state_r__0[1]),
        .I1(wl_state_r__0[0]),
        .I2(wr_level_done_r5),
        .I3(wl_state_r__0[2]),
        .I4(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I5(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .O(\FSM_sequential_wl_state_r[4]_i_18_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair303" *) 
  LUT3 #(
    .INIT(8'h08)) 
    \FSM_sequential_wl_state_r[4]_i_19 
       (.I0(wl_state_r__0[2]),
        .I1(wl_state_r__0[1]),
        .I2(wl_state_r__0[0]),
        .O(\FSM_sequential_wl_state_r_reg[2]_0 ));
  LUT6 #(
    .INIT(64'hFEEEFEEEEEEEFEEE)) 
    \FSM_sequential_wl_state_r[4]_i_2 
       (.I0(\FSM_sequential_wl_state_r[4]_i_8_n_0 ),
        .I1(\FSM_sequential_wl_state_r[4]_i_9_n_0 ),
        .I2(\FSM_sequential_wl_state_r[4]_i_10_n_0 ),
        .I3(wl_state_r__0[0]),
        .I4(wl_state_r__0[2]),
        .I5(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .O(\FSM_sequential_wl_state_r[4]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair346" *) 
  LUT5 #(
    .INIT(32'h55550510)) 
    \FSM_sequential_wl_state_r[4]_i_20 
       (.I0(wl_state_r__0[2]),
        .I1(p_0_in),
        .I2(wl_state_r__0[1]),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I4(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .O(\FSM_sequential_wl_state_r[4]_i_20_n_0 ));
  LUT6 #(
    .INIT(64'h000F010F00F0F0F0)) 
    \FSM_sequential_wl_state_r[4]_i_3 
       (.I0(wrlvl_byte_redo),
        .I1(wr_level_done_r5),
        .I2(wl_state_r__0[2]),
        .I3(wl_state_r__0[1]),
        .I4(wl_sm_start),
        .I5(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .O(\FSM_sequential_wl_state_r[4]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair328" *) 
  LUT5 #(
    .INIT(32'h70000000)) 
    \FSM_sequential_wl_state_r[4]_i_4 
       (.I0(\FSM_sequential_wl_state_r[4]_i_11_n_0 ),
        .I1(\fine_inc[0][5]_i_3_n_0 ),
        .I2(wl_state_r__0[0]),
        .I3(wl_state_r__0[1]),
        .I4(wr_level_done_r5),
        .O(\FSM_sequential_wl_state_r[4]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair326" *) 
  LUT5 #(
    .INIT(32'h7E7E7EFF)) 
    \FSM_sequential_wl_state_r[4]_i_5 
       (.I0(wl_state_r__0[2]),
        .I1(wl_state_r__0[1]),
        .I2(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I3(\FSM_sequential_wl_state_r[4]_i_12_n_0 ),
        .I4(wl_state_r__0[0]),
        .O(\FSM_sequential_wl_state_r[4]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFF8A0075FF8A7075)) 
    \FSM_sequential_wl_state_r[4]_i_6 
       (.I0(wl_state_r__0[0]),
        .I1(\FSM_sequential_wl_state_r[4]_i_13_n_0 ),
        .I2(wl_state_r__0[1]),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I4(wl_state_r__0[2]),
        .I5(wl_sm_start),
        .O(\FSM_sequential_wl_state_r[4]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h0000080000880888)) 
    \FSM_sequential_wl_state_r[4]_i_8 
       (.I0(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I2(wl_state_r__0[0]),
        .I3(wl_state_r__0[1]),
        .I4(\FSM_sequential_wl_state_r[4]_i_16_n_0 ),
        .I5(\FSM_sequential_wl_state_r[4]_i_17_n_0 ),
        .O(\FSM_sequential_wl_state_r[4]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hBFBBBBBBAAAAAAAA)) 
    \FSM_sequential_wl_state_r[4]_i_9 
       (.I0(\FSM_sequential_wl_state_r[4]_i_18_n_0 ),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I2(wr_level_done_r_reg_n_0),
        .I3(wl_sm_start),
        .I4(wr_level_start_r),
        .I5(\FSM_sequential_wl_state_r_reg[2]_0 ),
        .O(\FSM_sequential_wl_state_r[4]_i_9_n_0 ));
  (* FSM_ENCODED_STATES = "WL_FINE_DEC:00000,WL_2RANK_DQS_CNT:00010,WL_2RANK_TAP_DEC:00100,WL_CORSE_INC_WAIT2:00101,WL_CORSE_INC_WAIT1:00111,WL_INIT_FINE_INC_WAIT1:01000,WL_CORSE_INC_WAIT:01010,WL_INIT_FINE_INC:01100,WL_CORSE_INC_WAIT_TMP:10000,WL_CORSE_INC:01011,WL_FINE_DEC_WAIT1:00001,WL_INIT:10010,WL_FINE_INC_WAIT:10011,WL_CORSE_DEC_WAIT1:10101,WL_DQS_CNT:10100,WL_IDLE:01110,WL_INIT_FINE_DEC_WAIT1:10111,WL_DQS_CHECK:00011,WL_2RANK_FINAL_TAP:01111,WL_FINE_INC:01101,WL_CORSE_DEC_WAIT:11010,WL_INIT_FINE_DEC_WAIT:11000,WL_CORSE_DEC:10110,WL_EDGE_CHECK:11011,WL_WAIT:00110,WL_INIT_FINE_DEC:11001,WL_FINE_DEC_WAIT:10001,WL_INIT_FINE_INC_WAIT:01001" *) 
  FDRE \FSM_sequential_wl_state_r_reg[0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\FSM_sequential_wl_state_r[4]_i_1_n_0 ),
        .D(\FSM_sequential_wl_state_r[0]_i_1_n_0 ),
        .Q(wl_state_r__0[0]),
        .R(\fine_inc_reg[6][3]_0 [1]));
  (* FSM_ENCODED_STATES = "WL_FINE_DEC:00000,WL_2RANK_DQS_CNT:00010,WL_2RANK_TAP_DEC:00100,WL_CORSE_INC_WAIT2:00101,WL_CORSE_INC_WAIT1:00111,WL_INIT_FINE_INC_WAIT1:01000,WL_CORSE_INC_WAIT:01010,WL_INIT_FINE_INC:01100,WL_CORSE_INC_WAIT_TMP:10000,WL_CORSE_INC:01011,WL_FINE_DEC_WAIT1:00001,WL_INIT:10010,WL_FINE_INC_WAIT:10011,WL_CORSE_DEC_WAIT1:10101,WL_DQS_CNT:10100,WL_IDLE:01110,WL_INIT_FINE_DEC_WAIT1:10111,WL_DQS_CHECK:00011,WL_2RANK_FINAL_TAP:01111,WL_FINE_INC:01101,WL_CORSE_DEC_WAIT:11010,WL_INIT_FINE_DEC_WAIT:11000,WL_CORSE_DEC:10110,WL_EDGE_CHECK:11011,WL_WAIT:00110,WL_INIT_FINE_DEC:11001,WL_FINE_DEC_WAIT:10001,WL_INIT_FINE_INC_WAIT:01001" *) 
  FDSE \FSM_sequential_wl_state_r_reg[1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\FSM_sequential_wl_state_r[4]_i_1_n_0 ),
        .D(\FSM_sequential_wl_state_r[1]_i_1_n_0 ),
        .Q(wl_state_r__0[1]),
        .S(\fine_inc_reg[6][3]_0 [1]));
  (* FSM_ENCODED_STATES = "WL_FINE_DEC:00000,WL_2RANK_DQS_CNT:00010,WL_2RANK_TAP_DEC:00100,WL_CORSE_INC_WAIT2:00101,WL_CORSE_INC_WAIT1:00111,WL_INIT_FINE_INC_WAIT1:01000,WL_CORSE_INC_WAIT:01010,WL_INIT_FINE_INC:01100,WL_CORSE_INC_WAIT_TMP:10000,WL_CORSE_INC:01011,WL_FINE_DEC_WAIT1:00001,WL_INIT:10010,WL_FINE_INC_WAIT:10011,WL_CORSE_DEC_WAIT1:10101,WL_DQS_CNT:10100,WL_IDLE:01110,WL_INIT_FINE_DEC_WAIT1:10111,WL_DQS_CHECK:00011,WL_2RANK_FINAL_TAP:01111,WL_FINE_INC:01101,WL_CORSE_DEC_WAIT:11010,WL_INIT_FINE_DEC_WAIT:11000,WL_CORSE_DEC:10110,WL_EDGE_CHECK:11011,WL_WAIT:00110,WL_INIT_FINE_DEC:11001,WL_FINE_DEC_WAIT:10001,WL_INIT_FINE_INC_WAIT:01001" *) 
  FDSE \FSM_sequential_wl_state_r_reg[2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\FSM_sequential_wl_state_r[4]_i_1_n_0 ),
        .D(\FSM_sequential_wl_state_r[2]_i_1_n_0 ),
        .Q(wl_state_r__0[2]),
        .S(\fine_inc_reg[6][3]_0 [1]));
  (* FSM_ENCODED_STATES = "WL_FINE_DEC:00000,WL_2RANK_DQS_CNT:00010,WL_2RANK_TAP_DEC:00100,WL_CORSE_INC_WAIT2:00101,WL_CORSE_INC_WAIT1:00111,WL_INIT_FINE_INC_WAIT1:01000,WL_CORSE_INC_WAIT:01010,WL_INIT_FINE_INC:01100,WL_CORSE_INC_WAIT_TMP:10000,WL_CORSE_INC:01011,WL_FINE_DEC_WAIT1:00001,WL_INIT:10010,WL_FINE_INC_WAIT:10011,WL_CORSE_DEC_WAIT1:10101,WL_DQS_CNT:10100,WL_IDLE:01110,WL_INIT_FINE_DEC_WAIT1:10111,WL_DQS_CHECK:00011,WL_2RANK_FINAL_TAP:01111,WL_FINE_INC:01101,WL_CORSE_DEC_WAIT:11010,WL_INIT_FINE_DEC_WAIT:11000,WL_CORSE_DEC:10110,WL_EDGE_CHECK:11011,WL_WAIT:00110,WL_INIT_FINE_DEC:11001,WL_FINE_DEC_WAIT:10001,WL_INIT_FINE_INC_WAIT:01001" *) 
  FDSE \FSM_sequential_wl_state_r_reg[3] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\FSM_sequential_wl_state_r[4]_i_1_n_0 ),
        .D(\FSM_sequential_wl_state_r[3]_i_1_n_0 ),
        .Q(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .S(\fine_inc_reg[6][3]_0 [1]));
  (* FSM_ENCODED_STATES = "WL_FINE_DEC:00000,WL_2RANK_DQS_CNT:00010,WL_2RANK_TAP_DEC:00100,WL_CORSE_INC_WAIT2:00101,WL_CORSE_INC_WAIT1:00111,WL_INIT_FINE_INC_WAIT1:01000,WL_CORSE_INC_WAIT:01010,WL_INIT_FINE_INC:01100,WL_CORSE_INC_WAIT_TMP:10000,WL_CORSE_INC:01011,WL_FINE_DEC_WAIT1:00001,WL_INIT:10010,WL_FINE_INC_WAIT:10011,WL_CORSE_DEC_WAIT1:10101,WL_DQS_CNT:10100,WL_IDLE:01110,WL_INIT_FINE_DEC_WAIT1:10111,WL_DQS_CHECK:00011,WL_2RANK_FINAL_TAP:01111,WL_FINE_INC:01101,WL_CORSE_DEC_WAIT:11010,WL_INIT_FINE_DEC_WAIT:11000,WL_CORSE_DEC:10110,WL_EDGE_CHECK:11011,WL_WAIT:00110,WL_INIT_FINE_DEC:11001,WL_FINE_DEC_WAIT:10001,WL_INIT_FINE_INC_WAIT:01001" *) 
  FDRE \FSM_sequential_wl_state_r_reg[4] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\FSM_sequential_wl_state_r[4]_i_1_n_0 ),
        .D(\FSM_sequential_wl_state_r[4]_i_2_n_0 ),
        .Q(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .R(\fine_inc_reg[6][3]_0 [1]));
  MUXF7 \FSM_sequential_wl_state_r_reg[4]_i_7 
       (.I0(\FSM_sequential_wl_state_r[4]_i_14_n_0 ),
        .I1(\FSM_sequential_wl_state_r[4]_i_15_n_0 ),
        .O(\FSM_sequential_wl_state_r_reg[4]_i_7_n_0 ),
        .S(wl_state_r__0[1]));
  (* SOFT_HLUTNM = "soft_lutpair366" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \corse_cnt[0][0]_i_1 
       (.I0(corse_cnt[0]),
        .I1(\corse_cnt[0][2]_i_3_n_0 ),
        .I2(\corse_cnt_reg_n_0_[0][0] ),
        .O(\corse_cnt[0][0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h88888A88AAAAAAAA)) 
    \corse_cnt[0][0]_i_2 
       (.I0(wl_state_r__0[1]),
        .I1(\corse_cnt[0][0]_i_3_n_0 ),
        .I2(\wl_corse_cnt_reg[0][0][0]_i_1_n_0 ),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I4(wl_state_r__0[2]),
        .I5(\corse_cnt[0][0]_i_4_n_0 ),
        .O(corse_cnt[0]));
  (* SOFT_HLUTNM = "soft_lutpair304" *) 
  LUT5 #(
    .INIT(32'h0C080008)) 
    \corse_cnt[0][0]_i_3 
       (.I0(\corse_cnt[0][0]_i_5_n_0 ),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I2(wl_state_r__0[2]),
        .I3(\dqs_count_r_reg[2]_rep__0_0 ),
        .I4(\corse_cnt[0][0]_i_6_n_0 ),
        .O(\corse_cnt[0][0]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FF1BFFFF)) 
    \corse_cnt[0][0]_i_4 
       (.I0(\dqs_count_r_reg[3]_1 [2]),
        .I1(\corse_cnt[0][0]_i_7_n_0 ),
        .I2(\corse_cnt[0][0]_i_8_n_0 ),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I4(wl_state_r__0[2]),
        .I5(\corse_cnt[0][0]_i_9_n_0 ),
        .O(\corse_cnt[0][0]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \corse_cnt[0][0]_i_5 
       (.I0(\final_coarse_tap_reg_n_0_[3][0] ),
        .I1(\final_coarse_tap_reg_n_0_[2][0] ),
        .I2(\dqs_count_r_reg[1]_rep_0 ),
        .I3(\final_coarse_tap_reg_n_0_[1][0] ),
        .I4(\dqs_count_r_reg[0]_rep_0 ),
        .I5(\final_coarse_tap_reg_n_0_[0][0] ),
        .O(\corse_cnt[0][0]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \corse_cnt[0][0]_i_6 
       (.I0(\final_coarse_tap_reg_n_0_[7][0] ),
        .I1(\final_coarse_tap_reg_n_0_[6][0] ),
        .I2(\dqs_count_r_reg[1]_rep_0 ),
        .I3(\final_coarse_tap_reg_n_0_[5][0] ),
        .I4(\dqs_count_r_reg[0]_rep_0 ),
        .I5(\final_coarse_tap_reg_n_0_[4][0] ),
        .O(\corse_cnt[0][0]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \corse_cnt[0][0]_i_7 
       (.I0(\final_coarse_tap_reg_n_0_[3][0] ),
        .I1(\final_coarse_tap_reg_n_0_[2][0] ),
        .I2(\dqs_count_r_reg[3]_1 [1]),
        .I3(\final_coarse_tap_reg_n_0_[1][0] ),
        .I4(\dqs_count_r_reg[3]_1 [0]),
        .I5(\final_coarse_tap_reg_n_0_[0][0] ),
        .O(\corse_cnt[0][0]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \corse_cnt[0][0]_i_8 
       (.I0(\final_coarse_tap_reg_n_0_[7][0] ),
        .I1(\final_coarse_tap_reg_n_0_[6][0] ),
        .I2(\dqs_count_r_reg[3]_1 [1]),
        .I3(\final_coarse_tap_reg_n_0_[5][0] ),
        .I4(\dqs_count_r_reg[3]_1 [0]),
        .I5(\final_coarse_tap_reg_n_0_[4][0] ),
        .O(\corse_cnt[0][0]_i_8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair346" *) 
  LUT3 #(
    .INIT(8'h02)) 
    \corse_cnt[0][0]_i_9 
       (.I0(p_0_in),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I2(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .O(\corse_cnt[0][0]_i_9_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair367" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \corse_cnt[0][1]_i_1 
       (.I0(corse_cnt[1]),
        .I1(\corse_cnt[0][2]_i_3_n_0 ),
        .I2(\corse_cnt_reg_n_0_[0][1] ),
        .O(\corse_cnt[0][1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h888A8A8888888888)) 
    \corse_cnt[0][1]_i_2 
       (.I0(wl_state_r__0[1]),
        .I1(\corse_cnt[0][1]_i_3_n_0 ),
        .I2(wl_state_r__0[2]),
        .I3(\wl_corse_cnt_reg[0][0][0]_i_1_n_0 ),
        .I4(\wl_corse_cnt_reg[0][0][1]_i_1_n_0 ),
        .I5(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .O(corse_cnt[1]));
  LUT6 #(
    .INIT(64'hAEAAAEAAAFAFAEAA)) 
    \corse_cnt[0][1]_i_3 
       (.I0(\corse_cnt[0][1]_i_4_n_0 ),
        .I1(\po_stg2_wrcal_cnt_reg[2] ),
        .I2(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I3(wl_state_r__0[2]),
        .I4(p_0_in),
        .I5(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .O(\corse_cnt[0][1]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'h0C080008)) 
    \corse_cnt[0][1]_i_4 
       (.I0(\corse_cnt[0][1]_i_5_n_0 ),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I2(wl_state_r__0[2]),
        .I3(\dqs_count_r_reg[2]_rep__0_0 ),
        .I4(\corse_cnt[0][1]_i_6_n_0 ),
        .O(\corse_cnt[0][1]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \corse_cnt[0][1]_i_5 
       (.I0(\final_coarse_tap_reg_n_0_[3][1] ),
        .I1(\final_coarse_tap_reg_n_0_[2][1] ),
        .I2(\dqs_count_r_reg[1]_rep_0 ),
        .I3(\final_coarse_tap_reg_n_0_[1][1] ),
        .I4(\dqs_count_r_reg[0]_rep_0 ),
        .I5(\final_coarse_tap_reg_n_0_[0][1] ),
        .O(\corse_cnt[0][1]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \corse_cnt[0][1]_i_6 
       (.I0(\final_coarse_tap_reg_n_0_[7][1] ),
        .I1(\final_coarse_tap_reg_n_0_[6][1] ),
        .I2(\dqs_count_r_reg[1]_rep_0 ),
        .I3(\final_coarse_tap_reg_n_0_[5][1] ),
        .I4(\dqs_count_r_reg[0]_rep_0 ),
        .I5(\final_coarse_tap_reg_n_0_[4][1] ),
        .O(\corse_cnt[0][1]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair365" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \corse_cnt[0][2]_i_1 
       (.I0(corse_cnt[2]),
        .I1(\corse_cnt[0][2]_i_3_n_0 ),
        .I2(\corse_cnt_reg_n_0_[0][2] ),
        .O(\corse_cnt[0][2]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h0C080008)) 
    \corse_cnt[0][2]_i_11 
       (.I0(\corse_cnt[0][2]_i_12_n_0 ),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I2(wl_state_r__0[2]),
        .I3(\dqs_count_r_reg[2]_rep__0_0 ),
        .I4(\corse_cnt[0][2]_i_13_n_0 ),
        .O(\corse_cnt[0][2]_i_11_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \corse_cnt[0][2]_i_12 
       (.I0(\final_coarse_tap_reg_n_0_[3][2] ),
        .I1(\final_coarse_tap_reg_n_0_[2][2] ),
        .I2(\dqs_count_r_reg[1]_rep_0 ),
        .I3(\final_coarse_tap_reg_n_0_[1][2] ),
        .I4(\dqs_count_r_reg[0]_rep_0 ),
        .I5(\final_coarse_tap_reg_n_0_[0][2] ),
        .O(\corse_cnt[0][2]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \corse_cnt[0][2]_i_13 
       (.I0(\final_coarse_tap_reg_n_0_[7][2] ),
        .I1(\final_coarse_tap_reg_n_0_[6][2] ),
        .I2(\dqs_count_r_reg[1]_rep_0 ),
        .I3(\final_coarse_tap_reg_n_0_[5][2] ),
        .I4(\dqs_count_r_reg[0]_rep_0 ),
        .I5(\final_coarse_tap_reg_n_0_[4][2] ),
        .O(\corse_cnt[0][2]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'h8A88888888888A88)) 
    \corse_cnt[0][2]_i_2 
       (.I0(wl_state_r__0[1]),
        .I1(\corse_cnt[0][2]_i_4_n_0 ),
        .I2(wl_state_r__0[2]),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I4(\wl_corse_cnt_reg[0][0][2]_i_1_n_0 ),
        .I5(\corse_cnt[0][2]_i_5_n_0 ),
        .O(corse_cnt[2]));
  LUT6 #(
    .INIT(64'hBA00BA00BA00FFFF)) 
    \corse_cnt[0][2]_i_3 
       (.I0(\corse_cnt[0][2]_i_6_n_0 ),
        .I1(\corse_cnt[0][2]_i_7_n_0 ),
        .I2(\fine_inc[0][5]_i_4_n_0 ),
        .I3(\corse_cnt[0][2]_i_8_n_0 ),
        .I4(\corse_cnt_reg[3][0]_0 ),
        .I5(\corse_cnt_reg[4][0]_0 ),
        .O(\corse_cnt[0][2]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hF0F0F0F0F8F8FFF8)) 
    \corse_cnt[0][2]_i_4 
       (.I0(wl_state_r__0[2]),
        .I1(\po_stg2_wrcal_cnt_reg[2]_0 ),
        .I2(\corse_cnt[0][2]_i_11_n_0 ),
        .I3(p_0_in),
        .I4(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I5(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .O(\corse_cnt[0][2]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair375" *) 
  LUT2 #(
    .INIT(4'h7)) 
    \corse_cnt[0][2]_i_5 
       (.I0(\wl_corse_cnt_reg[0][0][0]_i_1_n_0 ),
        .I1(\wl_corse_cnt_reg[0][0][1]_i_1_n_0 ),
        .O(\corse_cnt[0][2]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    \corse_cnt[0][2]_i_6 
       (.I0(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I1(p_0_in),
        .O(\corse_cnt[0][2]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair356" *) 
  LUT3 #(
    .INIT(8'h4F)) 
    \corse_cnt[0][2]_i_7 
       (.I0(wrlvl_byte_redo),
        .I1(wr_level_done_r5),
        .I2(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .O(\corse_cnt[0][2]_i_7_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair300" *) 
  LUT4 #(
    .INIT(16'h0040)) 
    \corse_cnt[0][2]_i_8 
       (.I0(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I1(wl_state_r__0[0]),
        .I2(wl_state_r__0[1]),
        .I3(wl_state_r__0[2]),
        .O(\corse_cnt[0][2]_i_8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair368" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \corse_cnt[1][0]_i_1 
       (.I0(corse_cnt[0]),
        .I1(\corse_cnt[1][2]_i_2_n_0 ),
        .I2(\corse_cnt_reg_n_0_[1][0] ),
        .O(\corse_cnt[1][0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair367" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \corse_cnt[1][1]_i_1 
       (.I0(corse_cnt[1]),
        .I1(\corse_cnt[1][2]_i_2_n_0 ),
        .I2(\corse_cnt_reg_n_0_[1][1] ),
        .O(\corse_cnt[1][1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair365" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \corse_cnt[1][2]_i_1 
       (.I0(corse_cnt[2]),
        .I1(\corse_cnt[1][2]_i_2_n_0 ),
        .I2(\corse_cnt_reg_n_0_[1][2] ),
        .O(\corse_cnt[1][2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hBA00BA00BA00FFFF)) 
    \corse_cnt[1][2]_i_2 
       (.I0(\corse_cnt[0][2]_i_6_n_0 ),
        .I1(\corse_cnt[0][2]_i_7_n_0 ),
        .I2(\fine_inc[1][5]_i_3_n_0 ),
        .I3(\corse_cnt[0][2]_i_8_n_0 ),
        .I4(\corse_cnt_reg[3][0]_0 ),
        .I5(\corse_cnt_reg[5][0]_0 ),
        .O(\corse_cnt[1][2]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair366" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \corse_cnt[2][0]_i_1 
       (.I0(corse_cnt[0]),
        .I1(\corse_cnt[2][2]_i_2_n_0 ),
        .I2(\corse_cnt_reg_n_0_[2][0] ),
        .O(\corse_cnt[2][0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair370" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \corse_cnt[2][1]_i_1 
       (.I0(corse_cnt[1]),
        .I1(\corse_cnt[2][2]_i_2_n_0 ),
        .I2(\corse_cnt_reg_n_0_[2][1] ),
        .O(\corse_cnt[2][1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair373" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \corse_cnt[2][2]_i_1 
       (.I0(corse_cnt[2]),
        .I1(\corse_cnt[2][2]_i_2_n_0 ),
        .I2(\corse_cnt_reg_n_0_[2][2] ),
        .O(\corse_cnt[2][2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hBA00BA00BA00FFFF)) 
    \corse_cnt[2][2]_i_2 
       (.I0(\corse_cnt[0][2]_i_6_n_0 ),
        .I1(\corse_cnt[0][2]_i_7_n_0 ),
        .I2(\fine_inc[2][5]_i_3_n_0 ),
        .I3(\corse_cnt[0][2]_i_8_n_0 ),
        .I4(\corse_cnt_reg[3][0]_0 ),
        .I5(\corse_cnt_reg[6][0]_0 ),
        .O(\corse_cnt[2][2]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair368" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \corse_cnt[3][0]_i_1 
       (.I0(corse_cnt[0]),
        .I1(\corse_cnt[3][2]_i_2_n_0 ),
        .I2(\corse_cnt_reg_n_0_[3][0] ),
        .O(\corse_cnt[3][0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair377" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \corse_cnt[3][1]_i_1 
       (.I0(corse_cnt[1]),
        .I1(\corse_cnt[3][2]_i_2_n_0 ),
        .I2(\corse_cnt_reg_n_0_[3][1] ),
        .O(\corse_cnt[3][1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair373" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \corse_cnt[3][2]_i_1 
       (.I0(corse_cnt[2]),
        .I1(\corse_cnt[3][2]_i_2_n_0 ),
        .I2(\corse_cnt_reg_n_0_[3][2] ),
        .O(\corse_cnt[3][2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hBA00BA00BA00FFFF)) 
    \corse_cnt[3][2]_i_2 
       (.I0(\corse_cnt[0][2]_i_6_n_0 ),
        .I1(\corse_cnt[0][2]_i_7_n_0 ),
        .I2(\fine_inc[3][5]_i_3_n_0 ),
        .I3(\corse_cnt[0][2]_i_8_n_0 ),
        .I4(\corse_cnt_reg[3][0]_0 ),
        .I5(\corse_cnt_reg[7][0]_1 ),
        .O(\corse_cnt[3][2]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair369" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \corse_cnt[4][0]_i_1 
       (.I0(corse_cnt[0]),
        .I1(\corse_cnt[4][2]_i_2_n_0 ),
        .I2(\corse_cnt_reg_n_0_[4][0] ),
        .O(\corse_cnt[4][0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair379" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \corse_cnt[4][1]_i_1 
       (.I0(corse_cnt[1]),
        .I1(\corse_cnt[4][2]_i_2_n_0 ),
        .I2(\corse_cnt_reg_n_0_[4][1] ),
        .O(\corse_cnt[4][1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair376" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \corse_cnt[4][2]_i_1 
       (.I0(corse_cnt[2]),
        .I1(\corse_cnt[4][2]_i_2_n_0 ),
        .I2(\corse_cnt_reg_n_0_[4][2] ),
        .O(\corse_cnt[4][2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hBA00BA00BA00FFFF)) 
    \corse_cnt[4][2]_i_2 
       (.I0(\corse_cnt[0][2]_i_6_n_0 ),
        .I1(\corse_cnt[0][2]_i_7_n_0 ),
        .I2(\fine_inc[4][5]_i_3_n_0 ),
        .I3(\corse_cnt[0][2]_i_8_n_0 ),
        .I4(\corse_cnt_reg[7][0]_0 ),
        .I5(\corse_cnt_reg[4][0]_0 ),
        .O(\corse_cnt[4][2]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair369" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \corse_cnt[5][0]_i_1 
       (.I0(corse_cnt[0]),
        .I1(\corse_cnt[5][2]_i_2_n_0 ),
        .I2(\corse_cnt_reg_n_0_[5][0] ),
        .O(\corse_cnt[5][0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair379" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \corse_cnt[5][1]_i_1 
       (.I0(corse_cnt[1]),
        .I1(\corse_cnt[5][2]_i_2_n_0 ),
        .I2(\corse_cnt_reg_n_0_[5][1] ),
        .O(\corse_cnt[5][1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair378" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \corse_cnt[5][2]_i_1 
       (.I0(corse_cnt[2]),
        .I1(\corse_cnt[5][2]_i_2_n_0 ),
        .I2(\corse_cnt_reg_n_0_[5][2] ),
        .O(\corse_cnt[5][2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hBA00BA00BA00FFFF)) 
    \corse_cnt[5][2]_i_2 
       (.I0(\corse_cnt[0][2]_i_6_n_0 ),
        .I1(\corse_cnt[0][2]_i_7_n_0 ),
        .I2(\fine_inc[5][5]_i_3_n_0 ),
        .I3(\corse_cnt[0][2]_i_8_n_0 ),
        .I4(\corse_cnt_reg[7][0]_0 ),
        .I5(\corse_cnt_reg[5][0]_0 ),
        .O(\corse_cnt[5][2]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair374" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \corse_cnt[6][0]_i_1 
       (.I0(corse_cnt[0]),
        .I1(\corse_cnt[6][2]_i_2_n_0 ),
        .I2(\corse_cnt_reg_n_0_[6][0] ),
        .O(\corse_cnt[6][0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair377" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \corse_cnt[6][1]_i_1 
       (.I0(corse_cnt[1]),
        .I1(\corse_cnt[6][2]_i_2_n_0 ),
        .I2(\corse_cnt_reg_n_0_[6][1] ),
        .O(\corse_cnt[6][1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair378" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \corse_cnt[6][2]_i_1 
       (.I0(corse_cnt[2]),
        .I1(\corse_cnt[6][2]_i_2_n_0 ),
        .I2(\corse_cnt_reg_n_0_[6][2] ),
        .O(\corse_cnt[6][2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hBA00BA00BA00FFFF)) 
    \corse_cnt[6][2]_i_2 
       (.I0(\corse_cnt[0][2]_i_6_n_0 ),
        .I1(\corse_cnt[0][2]_i_7_n_0 ),
        .I2(\fine_inc[6][5]_i_3_n_0 ),
        .I3(\corse_cnt[0][2]_i_8_n_0 ),
        .I4(\corse_cnt_reg[7][0]_0 ),
        .I5(\corse_cnt_reg[6][0]_0 ),
        .O(\corse_cnt[6][2]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair374" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \corse_cnt[7][0]_i_1 
       (.I0(corse_cnt[0]),
        .I1(\corse_cnt[7][2]_i_2_n_0 ),
        .I2(\corse_cnt_reg_n_0_[7][0] ),
        .O(\corse_cnt[7][0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair370" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \corse_cnt[7][1]_i_1 
       (.I0(corse_cnt[1]),
        .I1(\corse_cnt[7][2]_i_2_n_0 ),
        .I2(\corse_cnt_reg_n_0_[7][1] ),
        .O(\corse_cnt[7][1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair376" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \corse_cnt[7][2]_i_1 
       (.I0(corse_cnt[2]),
        .I1(\corse_cnt[7][2]_i_2_n_0 ),
        .I2(\corse_cnt_reg_n_0_[7][2] ),
        .O(\corse_cnt[7][2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hBA00BA00BA00FFFF)) 
    \corse_cnt[7][2]_i_2 
       (.I0(\corse_cnt[0][2]_i_6_n_0 ),
        .I1(\corse_cnt[0][2]_i_7_n_0 ),
        .I2(\fine_inc[7][5]_i_3_n_0 ),
        .I3(\corse_cnt[0][2]_i_8_n_0 ),
        .I4(\corse_cnt_reg[7][0]_0 ),
        .I5(\corse_cnt_reg[7][0]_1 ),
        .O(\corse_cnt[7][2]_i_2_n_0 ));
  FDRE \corse_cnt_reg[0][0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\corse_cnt[0][0]_i_1_n_0 ),
        .Q(\corse_cnt_reg_n_0_[0][0] ),
        .R(\corse_inc_reg[6][2]_0 [1]));
  FDRE \corse_cnt_reg[0][1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\corse_cnt[0][1]_i_1_n_0 ),
        .Q(\corse_cnt_reg_n_0_[0][1] ),
        .R(\corse_inc_reg[6][2]_0 [1]));
  FDRE \corse_cnt_reg[0][2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\corse_cnt[0][2]_i_1_n_0 ),
        .Q(\corse_cnt_reg_n_0_[0][2] ),
        .R(\corse_inc_reg[6][2]_0 [1]));
  FDRE \corse_cnt_reg[1][0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\corse_cnt[1][0]_i_1_n_0 ),
        .Q(\corse_cnt_reg_n_0_[1][0] ),
        .R(\corse_inc_reg[6][2]_0 [1]));
  FDRE \corse_cnt_reg[1][1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\corse_cnt[1][1]_i_1_n_0 ),
        .Q(\corse_cnt_reg_n_0_[1][1] ),
        .R(\corse_inc_reg[6][2]_0 [1]));
  FDRE \corse_cnt_reg[1][2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\corse_cnt[1][2]_i_1_n_0 ),
        .Q(\corse_cnt_reg_n_0_[1][2] ),
        .R(\corse_inc_reg[6][2]_0 [1]));
  FDRE \corse_cnt_reg[2][0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\corse_cnt[2][0]_i_1_n_0 ),
        .Q(\corse_cnt_reg_n_0_[2][0] ),
        .R(\corse_inc_reg[6][2]_0 [1]));
  FDRE \corse_cnt_reg[2][1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\corse_cnt[2][1]_i_1_n_0 ),
        .Q(\corse_cnt_reg_n_0_[2][1] ),
        .R(\corse_inc_reg[6][2]_0 [1]));
  FDRE \corse_cnt_reg[2][2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\corse_cnt[2][2]_i_1_n_0 ),
        .Q(\corse_cnt_reg_n_0_[2][2] ),
        .R(\corse_inc_reg[6][2]_0 [1]));
  FDRE \corse_cnt_reg[3][0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\corse_cnt[3][0]_i_1_n_0 ),
        .Q(\corse_cnt_reg_n_0_[3][0] ),
        .R(\corse_inc_reg[6][2]_0 [1]));
  FDRE \corse_cnt_reg[3][1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\corse_cnt[3][1]_i_1_n_0 ),
        .Q(\corse_cnt_reg_n_0_[3][1] ),
        .R(\corse_inc_reg[6][2]_0 [1]));
  FDRE \corse_cnt_reg[3][2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\corse_cnt[3][2]_i_1_n_0 ),
        .Q(\corse_cnt_reg_n_0_[3][2] ),
        .R(\corse_inc_reg[6][2]_0 [1]));
  FDRE \corse_cnt_reg[4][0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\corse_cnt[4][0]_i_1_n_0 ),
        .Q(\corse_cnt_reg_n_0_[4][0] ),
        .R(\corse_inc_reg[6][2]_0 [1]));
  FDRE \corse_cnt_reg[4][1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\corse_cnt[4][1]_i_1_n_0 ),
        .Q(\corse_cnt_reg_n_0_[4][1] ),
        .R(\corse_inc_reg[6][2]_0 [1]));
  FDRE \corse_cnt_reg[4][2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\corse_cnt[4][2]_i_1_n_0 ),
        .Q(\corse_cnt_reg_n_0_[4][2] ),
        .R(\corse_inc_reg[6][2]_0 [1]));
  FDRE \corse_cnt_reg[5][0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\corse_cnt[5][0]_i_1_n_0 ),
        .Q(\corse_cnt_reg_n_0_[5][0] ),
        .R(\corse_inc_reg[6][2]_0 [1]));
  FDRE \corse_cnt_reg[5][1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\corse_cnt[5][1]_i_1_n_0 ),
        .Q(\corse_cnt_reg_n_0_[5][1] ),
        .R(\corse_inc_reg[6][2]_0 [1]));
  FDRE \corse_cnt_reg[5][2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\corse_cnt[5][2]_i_1_n_0 ),
        .Q(\corse_cnt_reg_n_0_[5][2] ),
        .R(\corse_inc_reg[6][2]_0 [1]));
  FDRE \corse_cnt_reg[6][0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\corse_cnt[6][0]_i_1_n_0 ),
        .Q(\corse_cnt_reg_n_0_[6][0] ),
        .R(\corse_inc_reg[6][2]_0 [1]));
  FDRE \corse_cnt_reg[6][1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\corse_cnt[6][1]_i_1_n_0 ),
        .Q(\corse_cnt_reg_n_0_[6][1] ),
        .R(\corse_inc_reg[6][2]_0 [1]));
  FDRE \corse_cnt_reg[6][2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\corse_cnt[6][2]_i_1_n_0 ),
        .Q(\corse_cnt_reg_n_0_[6][2] ),
        .R(\corse_inc_reg[6][2]_0 [1]));
  FDRE \corse_cnt_reg[7][0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\corse_cnt[7][0]_i_1_n_0 ),
        .Q(\corse_cnt_reg_n_0_[7][0] ),
        .R(\corse_inc_reg[6][2]_0 [1]));
  FDRE \corse_cnt_reg[7][1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\corse_cnt[7][1]_i_1_n_0 ),
        .Q(\corse_cnt_reg_n_0_[7][1] ),
        .R(\corse_inc_reg[6][2]_0 [1]));
  FDRE \corse_cnt_reg[7][2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\corse_cnt[7][2]_i_1_n_0 ),
        .Q(\corse_cnt_reg_n_0_[7][2] ),
        .R(\corse_inc_reg[6][2]_0 [1]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \corse_dec[0][0]_i_1 
       (.I0(corse_dec[0]),
        .I1(\fine_inc[0][5]_i_4_n_0 ),
        .I2(\corse_dec[0][2]_i_5_n_0 ),
        .I3(\corse_dec_reg[0]_21 [0]),
        .O(\corse_dec[0][0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair364" *) 
  LUT4 #(
    .INIT(16'h0004)) 
    \corse_dec[0][0]_i_2 
       (.I0(\corse_dec_reg[0][2]_i_3_n_0 ),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I2(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I3(\FSM_sequential_wl_state_r[4]_i_16_n_0 ),
        .O(corse_dec[0]));
  LUT4 #(
    .INIT(16'hFB08)) 
    \corse_dec[0][1]_i_1 
       (.I0(corse_dec[1]),
        .I1(\fine_inc[0][5]_i_4_n_0 ),
        .I2(\corse_dec[0][2]_i_5_n_0 ),
        .I3(\corse_dec_reg[0]_21 [1]),
        .O(\corse_dec[0][1]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h30000055)) 
    \corse_dec[0][1]_i_2 
       (.I0(\corse_dec[0][2]_i_4_n_0 ),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I2(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I3(\corse_dec_reg[0][2]_i_3_n_0 ),
        .I4(\corse_dec_reg[0][2]_i_2_n_0 ),
        .O(corse_dec[1]));
  LUT6 #(
    .INIT(64'hFFFF0EFF00000E00)) 
    \corse_dec[0][2]_i_1 
       (.I0(\corse_dec_reg[0][2]_i_2_n_0 ),
        .I1(\corse_dec_reg[0][2]_i_3_n_0 ),
        .I2(\corse_dec[0][2]_i_4_n_0 ),
        .I3(\fine_inc[0][5]_i_4_n_0 ),
        .I4(\corse_dec[0][2]_i_5_n_0 ),
        .I5(\corse_dec_reg[0]_21 [2]),
        .O(\corse_dec[0][2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \corse_dec[0][2]_i_11 
       (.I0(\corse_dec_reg[3]_24 [2]),
        .I1(\corse_dec_reg[2]_23 [2]),
        .I2(dqs_count_r[1]),
        .I3(\corse_dec_reg[1]_22 [2]),
        .I4(dqs_count_r[0]),
        .I5(\corse_dec_reg[0]_21 [2]),
        .O(\corse_dec[0][2]_i_11_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \corse_dec[0][2]_i_12 
       (.I0(\corse_dec_reg[7]_28 [2]),
        .I1(\corse_dec_reg[6]_27 [2]),
        .I2(dqs_count_r[1]),
        .I3(\corse_dec_reg[5]_26 [2]),
        .I4(dqs_count_r[0]),
        .I5(\corse_dec_reg[4]_25 [2]),
        .O(\corse_dec[0][2]_i_12_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair364" *) 
  LUT3 #(
    .INIT(8'hBF)) 
    \corse_dec[0][2]_i_4 
       (.I0(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I2(\corse_dec_reg[0][2]_i_10_n_0 ),
        .O(\corse_dec[0][2]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair331" *) 
  LUT5 #(
    .INIT(32'hFFFFDFFF)) 
    \corse_dec[0][2]_i_5 
       (.I0(wl_state_r__0[1]),
        .I1(wl_state_r__0[0]),
        .I2(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I3(wl_state_r__0[2]),
        .I4(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .O(\corse_dec[0][2]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \corse_dec[0][2]_i_6 
       (.I0(\corse_dec_reg[3]_24 [1]),
        .I1(\corse_dec_reg[2]_23 [1]),
        .I2(dqs_count_r[1]),
        .I3(\corse_dec_reg[1]_22 [1]),
        .I4(dqs_count_r[0]),
        .I5(\corse_dec_reg[0]_21 [1]),
        .O(\corse_dec[0][2]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \corse_dec[0][2]_i_7 
       (.I0(\corse_dec_reg[7]_28 [1]),
        .I1(\corse_dec_reg[6]_27 [1]),
        .I2(dqs_count_r[1]),
        .I3(\corse_dec_reg[5]_26 [1]),
        .I4(dqs_count_r[0]),
        .I5(\corse_dec_reg[4]_25 [1]),
        .O(\corse_dec[0][2]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \corse_dec[0][2]_i_8 
       (.I0(\corse_dec_reg[3]_24 [0]),
        .I1(\corse_dec_reg[2]_23 [0]),
        .I2(dqs_count_r[1]),
        .I3(\corse_dec_reg[1]_22 [0]),
        .I4(dqs_count_r[0]),
        .I5(\corse_dec_reg[0]_21 [0]),
        .O(\corse_dec[0][2]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \corse_dec[0][2]_i_9 
       (.I0(\corse_dec_reg[7]_28 [0]),
        .I1(\corse_dec_reg[6]_27 [0]),
        .I2(dqs_count_r[1]),
        .I3(\corse_dec_reg[5]_26 [0]),
        .I4(dqs_count_r[0]),
        .I5(\corse_dec_reg[4]_25 [0]),
        .O(\corse_dec[0][2]_i_9_n_0 ));
  LUT4 #(
    .INIT(16'hFB08)) 
    \corse_dec[1][0]_i_1 
       (.I0(corse_dec[0]),
        .I1(\fine_inc[1][5]_i_3_n_0 ),
        .I2(\corse_dec[0][2]_i_5_n_0 ),
        .I3(\corse_dec_reg[1]_22 [0]),
        .O(\corse_dec[1][0]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFB08)) 
    \corse_dec[1][1]_i_1 
       (.I0(corse_dec[1]),
        .I1(\fine_inc[1][5]_i_3_n_0 ),
        .I2(\corse_dec[0][2]_i_5_n_0 ),
        .I3(\corse_dec_reg[1]_22 [1]),
        .O(\corse_dec[1][1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0EFF00000E00)) 
    \corse_dec[1][2]_i_1 
       (.I0(\corse_dec_reg[0][2]_i_2_n_0 ),
        .I1(\corse_dec_reg[0][2]_i_3_n_0 ),
        .I2(\corse_dec[0][2]_i_4_n_0 ),
        .I3(\fine_inc[1][5]_i_3_n_0 ),
        .I4(\corse_dec[0][2]_i_5_n_0 ),
        .I5(\corse_dec_reg[1]_22 [2]),
        .O(\corse_dec[1][2]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFB08)) 
    \corse_dec[2][0]_i_1 
       (.I0(corse_dec[0]),
        .I1(\fine_inc[2][5]_i_3_n_0 ),
        .I2(\corse_dec[0][2]_i_5_n_0 ),
        .I3(\corse_dec_reg[2]_23 [0]),
        .O(\corse_dec[2][0]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFB08)) 
    \corse_dec[2][1]_i_1 
       (.I0(corse_dec[1]),
        .I1(\fine_inc[2][5]_i_3_n_0 ),
        .I2(\corse_dec[0][2]_i_5_n_0 ),
        .I3(\corse_dec_reg[2]_23 [1]),
        .O(\corse_dec[2][1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0EFF00000E00)) 
    \corse_dec[2][2]_i_1 
       (.I0(\corse_dec_reg[0][2]_i_2_n_0 ),
        .I1(\corse_dec_reg[0][2]_i_3_n_0 ),
        .I2(\corse_dec[0][2]_i_4_n_0 ),
        .I3(\fine_inc[2][5]_i_3_n_0 ),
        .I4(\corse_dec[0][2]_i_5_n_0 ),
        .I5(\corse_dec_reg[2]_23 [2]),
        .O(\corse_dec[2][2]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFB08)) 
    \corse_dec[3][0]_i_1 
       (.I0(corse_dec[0]),
        .I1(\fine_inc[3][5]_i_3_n_0 ),
        .I2(\corse_dec[0][2]_i_5_n_0 ),
        .I3(\corse_dec_reg[3]_24 [0]),
        .O(\corse_dec[3][0]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFB08)) 
    \corse_dec[3][1]_i_1 
       (.I0(corse_dec[1]),
        .I1(\fine_inc[3][5]_i_3_n_0 ),
        .I2(\corse_dec[0][2]_i_5_n_0 ),
        .I3(\corse_dec_reg[3]_24 [1]),
        .O(\corse_dec[3][1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0EFF00000E00)) 
    \corse_dec[3][2]_i_1 
       (.I0(\corse_dec_reg[0][2]_i_2_n_0 ),
        .I1(\corse_dec_reg[0][2]_i_3_n_0 ),
        .I2(\corse_dec[0][2]_i_4_n_0 ),
        .I3(\fine_inc[3][5]_i_3_n_0 ),
        .I4(\corse_dec[0][2]_i_5_n_0 ),
        .I5(\corse_dec_reg[3]_24 [2]),
        .O(\corse_dec[3][2]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFB08)) 
    \corse_dec[4][0]_i_1 
       (.I0(corse_dec[0]),
        .I1(\fine_inc[4][5]_i_3_n_0 ),
        .I2(\corse_dec[0][2]_i_5_n_0 ),
        .I3(\corse_dec_reg[4]_25 [0]),
        .O(\corse_dec[4][0]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFB08)) 
    \corse_dec[4][1]_i_1 
       (.I0(corse_dec[1]),
        .I1(\fine_inc[4][5]_i_3_n_0 ),
        .I2(\corse_dec[0][2]_i_5_n_0 ),
        .I3(\corse_dec_reg[4]_25 [1]),
        .O(\corse_dec[4][1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0EFF00000E00)) 
    \corse_dec[4][2]_i_1 
       (.I0(\corse_dec_reg[0][2]_i_2_n_0 ),
        .I1(\corse_dec_reg[0][2]_i_3_n_0 ),
        .I2(\corse_dec[0][2]_i_4_n_0 ),
        .I3(\fine_inc[4][5]_i_3_n_0 ),
        .I4(\corse_dec[0][2]_i_5_n_0 ),
        .I5(\corse_dec_reg[4]_25 [2]),
        .O(\corse_dec[4][2]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFB08)) 
    \corse_dec[5][0]_i_1 
       (.I0(corse_dec[0]),
        .I1(\fine_inc[5][5]_i_3_n_0 ),
        .I2(\corse_dec[0][2]_i_5_n_0 ),
        .I3(\corse_dec_reg[5]_26 [0]),
        .O(\corse_dec[5][0]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFB08)) 
    \corse_dec[5][1]_i_1 
       (.I0(corse_dec[1]),
        .I1(\fine_inc[5][5]_i_3_n_0 ),
        .I2(\corse_dec[0][2]_i_5_n_0 ),
        .I3(\corse_dec_reg[5]_26 [1]),
        .O(\corse_dec[5][1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0EFF00000E00)) 
    \corse_dec[5][2]_i_1 
       (.I0(\corse_dec_reg[0][2]_i_2_n_0 ),
        .I1(\corse_dec_reg[0][2]_i_3_n_0 ),
        .I2(\corse_dec[0][2]_i_4_n_0 ),
        .I3(\fine_inc[5][5]_i_3_n_0 ),
        .I4(\corse_dec[0][2]_i_5_n_0 ),
        .I5(\corse_dec_reg[5]_26 [2]),
        .O(\corse_dec[5][2]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFB08)) 
    \corse_dec[6][0]_i_1 
       (.I0(corse_dec[0]),
        .I1(\fine_inc[6][5]_i_3_n_0 ),
        .I2(\corse_dec[0][2]_i_5_n_0 ),
        .I3(\corse_dec_reg[6]_27 [0]),
        .O(\corse_dec[6][0]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFB08)) 
    \corse_dec[6][1]_i_1 
       (.I0(corse_dec[1]),
        .I1(\fine_inc[6][5]_i_3_n_0 ),
        .I2(\corse_dec[0][2]_i_5_n_0 ),
        .I3(\corse_dec_reg[6]_27 [1]),
        .O(\corse_dec[6][1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0EFF00000E00)) 
    \corse_dec[6][2]_i_1 
       (.I0(\corse_dec_reg[0][2]_i_2_n_0 ),
        .I1(\corse_dec_reg[0][2]_i_3_n_0 ),
        .I2(\corse_dec[0][2]_i_4_n_0 ),
        .I3(\fine_inc[6][5]_i_3_n_0 ),
        .I4(\corse_dec[0][2]_i_5_n_0 ),
        .I5(\corse_dec_reg[6]_27 [2]),
        .O(\corse_dec[6][2]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFB08)) 
    \corse_dec[7][0]_i_1 
       (.I0(corse_dec[0]),
        .I1(\fine_inc[7][5]_i_3_n_0 ),
        .I2(\corse_dec[0][2]_i_5_n_0 ),
        .I3(\corse_dec_reg[7]_28 [0]),
        .O(\corse_dec[7][0]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFB08)) 
    \corse_dec[7][1]_i_1 
       (.I0(corse_dec[1]),
        .I1(\fine_inc[7][5]_i_3_n_0 ),
        .I2(\corse_dec[0][2]_i_5_n_0 ),
        .I3(\corse_dec_reg[7]_28 [1]),
        .O(\corse_dec[7][1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF0EFF00000E00)) 
    \corse_dec[7][2]_i_1 
       (.I0(\corse_dec_reg[0][2]_i_2_n_0 ),
        .I1(\corse_dec_reg[0][2]_i_3_n_0 ),
        .I2(\corse_dec[0][2]_i_4_n_0 ),
        .I3(\fine_inc[7][5]_i_3_n_0 ),
        .I4(\corse_dec[0][2]_i_5_n_0 ),
        .I5(\corse_dec_reg[7]_28 [2]),
        .O(\corse_dec[7][2]_i_1_n_0 ));
  FDRE \corse_dec_reg[0][0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\corse_dec[0][0]_i_1_n_0 ),
        .Q(\corse_dec_reg[0]_21 [0]),
        .R(\corse_dec_reg[7][0]_0 [1]));
  FDRE \corse_dec_reg[0][1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\corse_dec[0][1]_i_1_n_0 ),
        .Q(\corse_dec_reg[0]_21 [1]),
        .R(\corse_dec_reg[7][0]_0 [1]));
  FDRE \corse_dec_reg[0][2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\corse_dec[0][2]_i_1_n_0 ),
        .Q(\corse_dec_reg[0]_21 [2]),
        .R(\corse_dec_reg[7][0]_0 [1]));
  MUXF7 \corse_dec_reg[0][2]_i_10 
       (.I0(\corse_dec[0][2]_i_11_n_0 ),
        .I1(\corse_dec[0][2]_i_12_n_0 ),
        .O(\corse_dec_reg[0][2]_i_10_n_0 ),
        .S(dqs_count_r[2]));
  MUXF7 \corse_dec_reg[0][2]_i_2 
       (.I0(\corse_dec[0][2]_i_6_n_0 ),
        .I1(\corse_dec[0][2]_i_7_n_0 ),
        .O(\corse_dec_reg[0][2]_i_2_n_0 ),
        .S(dqs_count_r[2]));
  MUXF7 \corse_dec_reg[0][2]_i_3 
       (.I0(\corse_dec[0][2]_i_8_n_0 ),
        .I1(\corse_dec[0][2]_i_9_n_0 ),
        .O(\corse_dec_reg[0][2]_i_3_n_0 ),
        .S(dqs_count_r[2]));
  FDRE \corse_dec_reg[1][0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\corse_dec[1][0]_i_1_n_0 ),
        .Q(\corse_dec_reg[1]_22 [0]),
        .R(\corse_dec_reg[7][0]_0 [1]));
  FDRE \corse_dec_reg[1][1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\corse_dec[1][1]_i_1_n_0 ),
        .Q(\corse_dec_reg[1]_22 [1]),
        .R(\corse_dec_reg[7][0]_0 [1]));
  FDRE \corse_dec_reg[1][2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\corse_dec[1][2]_i_1_n_0 ),
        .Q(\corse_dec_reg[1]_22 [2]),
        .R(\corse_dec_reg[7][0]_0 [1]));
  FDRE \corse_dec_reg[2][0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\corse_dec[2][0]_i_1_n_0 ),
        .Q(\corse_dec_reg[2]_23 [0]),
        .R(\corse_dec_reg[7][0]_0 [1]));
  FDRE \corse_dec_reg[2][1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\corse_dec[2][1]_i_1_n_0 ),
        .Q(\corse_dec_reg[2]_23 [1]),
        .R(\corse_dec_reg[7][0]_0 [1]));
  FDRE \corse_dec_reg[2][2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\corse_dec[2][2]_i_1_n_0 ),
        .Q(\corse_dec_reg[2]_23 [2]),
        .R(\corse_dec_reg[7][0]_0 [1]));
  FDRE \corse_dec_reg[3][0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\corse_dec[3][0]_i_1_n_0 ),
        .Q(\corse_dec_reg[3]_24 [0]),
        .R(\corse_dec_reg[7][0]_0 [1]));
  FDRE \corse_dec_reg[3][1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\corse_dec[3][1]_i_1_n_0 ),
        .Q(\corse_dec_reg[3]_24 [1]),
        .R(\corse_dec_reg[7][0]_0 [1]));
  FDRE \corse_dec_reg[3][2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\corse_dec[3][2]_i_1_n_0 ),
        .Q(\corse_dec_reg[3]_24 [2]),
        .R(\corse_dec_reg[7][0]_0 [1]));
  FDRE \corse_dec_reg[4][0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\corse_dec[4][0]_i_1_n_0 ),
        .Q(\corse_dec_reg[4]_25 [0]),
        .R(\corse_dec_reg[7][0]_0 [1]));
  FDRE \corse_dec_reg[4][1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\corse_dec[4][1]_i_1_n_0 ),
        .Q(\corse_dec_reg[4]_25 [1]),
        .R(\corse_dec_reg[7][0]_0 [1]));
  FDRE \corse_dec_reg[4][2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\corse_dec[4][2]_i_1_n_0 ),
        .Q(\corse_dec_reg[4]_25 [2]),
        .R(\corse_dec_reg[7][0]_0 [1]));
  FDRE \corse_dec_reg[5][0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\corse_dec[5][0]_i_1_n_0 ),
        .Q(\corse_dec_reg[5]_26 [0]),
        .R(\corse_dec_reg[7][0]_0 [1]));
  FDRE \corse_dec_reg[5][1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\corse_dec[5][1]_i_1_n_0 ),
        .Q(\corse_dec_reg[5]_26 [1]),
        .R(\corse_dec_reg[7][0]_0 [1]));
  FDRE \corse_dec_reg[5][2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\corse_dec[5][2]_i_1_n_0 ),
        .Q(\corse_dec_reg[5]_26 [2]),
        .R(\corse_dec_reg[7][0]_0 [1]));
  FDRE \corse_dec_reg[6][0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\corse_dec[6][0]_i_1_n_0 ),
        .Q(\corse_dec_reg[6]_27 [0]),
        .R(\corse_dec_reg[7][0]_0 [1]));
  FDRE \corse_dec_reg[6][1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\corse_dec[6][1]_i_1_n_0 ),
        .Q(\corse_dec_reg[6]_27 [1]),
        .R(\corse_dec_reg[7][0]_0 [1]));
  FDRE \corse_dec_reg[6][2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\corse_dec[6][2]_i_1_n_0 ),
        .Q(\corse_dec_reg[6]_27 [2]),
        .R(\corse_dec_reg[7][0]_0 [1]));
  FDRE \corse_dec_reg[7][0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\corse_dec[7][0]_i_1_n_0 ),
        .Q(\corse_dec_reg[7]_28 [0]),
        .R(\corse_dec_reg[7][0]_0 [1]));
  FDRE \corse_dec_reg[7][1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\corse_dec[7][1]_i_1_n_0 ),
        .Q(\corse_dec_reg[7]_28 [1]),
        .R(\corse_dec_reg[7][0]_0 [1]));
  FDRE \corse_dec_reg[7][2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\corse_dec[7][2]_i_1_n_0 ),
        .Q(\corse_dec_reg[7]_28 [2]),
        .R(\corse_dec_reg[7][0]_0 [1]));
  LUT6 #(
    .INIT(64'hBBBBFFBF88880080)) 
    \corse_inc[0][0]_i_1 
       (.I0(corse_inc[0]),
        .I1(\corse_inc[0][2]_i_3_n_0 ),
        .I2(\fine_inc[0][5]_i_4_n_0 ),
        .I3(\corse_inc[0][2]_i_4_n_0 ),
        .I4(\corse_inc[0][2]_i_5_n_0 ),
        .I5(\corse_inc_reg[0]_37 [0]),
        .O(\corse_inc[0][0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair309" *) 
  LUT5 #(
    .INIT(32'h11B11111)) 
    \corse_inc[0][0]_i_2 
       (.I0(wl_state_r__0[2]),
        .I1(\corse_inc_reg[0][1]_i_3_n_0 ),
        .I2(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I4(\final_coarse_tap_reg_n_0_[0][0] ),
        .O(corse_inc[0]));
  LUT6 #(
    .INIT(64'hBBBBFFBF88880080)) 
    \corse_inc[0][1]_i_1 
       (.I0(corse_inc[1]),
        .I1(\corse_inc[0][2]_i_3_n_0 ),
        .I2(\fine_inc[0][5]_i_4_n_0 ),
        .I3(\corse_inc[0][2]_i_4_n_0 ),
        .I4(\corse_inc[0][2]_i_5_n_0 ),
        .I5(\corse_inc_reg[0]_37 [1]),
        .O(\corse_inc[0][1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h4141EB4141414141)) 
    \corse_inc[0][1]_i_2 
       (.I0(wl_state_r__0[2]),
        .I1(\corse_inc_reg[0][1]_i_3_n_0 ),
        .I2(\corse_inc_reg[0][1]_i_4_n_0 ),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I4(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I5(\final_coarse_tap_reg_n_0_[0][1] ),
        .O(corse_inc[1]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \corse_inc[0][1]_i_5 
       (.I0(\corse_inc_reg[3]_40 [0]),
        .I1(\corse_inc_reg[2]_39 [0]),
        .I2(\dqs_count_r_reg[1]_rep_0 ),
        .I3(\corse_inc_reg[1]_38 [0]),
        .I4(\dqs_count_r_reg[0]_rep_0 ),
        .I5(\corse_inc_reg[0]_37 [0]),
        .O(\corse_inc[0][1]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \corse_inc[0][1]_i_6 
       (.I0(\corse_inc_reg[7]_44 [0]),
        .I1(\corse_inc_reg[6]_43 [0]),
        .I2(\dqs_count_r_reg[1]_rep_0 ),
        .I3(\corse_inc_reg[5]_42 [0]),
        .I4(\dqs_count_r_reg[0]_rep_0 ),
        .I5(\corse_inc_reg[4]_41 [0]),
        .O(\corse_inc[0][1]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \corse_inc[0][1]_i_7 
       (.I0(\corse_inc_reg[3]_40 [1]),
        .I1(\corse_inc_reg[2]_39 [1]),
        .I2(\dqs_count_r_reg[1]_rep_0 ),
        .I3(\corse_inc_reg[1]_38 [1]),
        .I4(\dqs_count_r_reg[0]_rep_0 ),
        .I5(\corse_inc_reg[0]_37 [1]),
        .O(\corse_inc[0][1]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \corse_inc[0][1]_i_8 
       (.I0(\corse_inc_reg[7]_44 [1]),
        .I1(\corse_inc_reg[6]_43 [1]),
        .I2(\dqs_count_r_reg[1]_rep_0 ),
        .I3(\corse_inc_reg[5]_42 [1]),
        .I4(\dqs_count_r_reg[0]_rep_0 ),
        .I5(\corse_inc_reg[4]_41 [1]),
        .O(\corse_inc[0][1]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hBBBBFFBF88880080)) 
    \corse_inc[0][2]_i_1 
       (.I0(corse_inc[2]),
        .I1(\corse_inc[0][2]_i_3_n_0 ),
        .I2(\fine_inc[0][5]_i_4_n_0 ),
        .I3(\corse_inc[0][2]_i_4_n_0 ),
        .I4(\corse_inc[0][2]_i_5_n_0 ),
        .I5(\corse_inc_reg[0]_37 [2]),
        .O(\corse_inc[0][2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0606F60606060606)) 
    \corse_inc[0][2]_i_2 
       (.I0(\corse_inc_reg[0][2]_i_6_n_0 ),
        .I1(\corse_inc[0][2]_i_7_n_0 ),
        .I2(wl_state_r__0[2]),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I4(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I5(\final_coarse_tap_reg_n_0_[0][2] ),
        .O(corse_inc[2]));
  (* SOFT_HLUTNM = "soft_lutpair315" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \corse_inc[0][2]_i_3 
       (.I0(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I1(wl_state_r__0[1]),
        .I2(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I3(wl_state_r__0[0]),
        .O(\corse_inc[0][2]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair358" *) 
  LUT4 #(
    .INIT(16'hFFFB)) 
    \corse_inc[0][2]_i_4 
       (.I0(\FSM_sequential_wl_state_r[4]_i_11_n_0 ),
        .I1(wr_level_done_r5),
        .I2(wrlvl_byte_redo),
        .I3(wl_state_r__0[2]),
        .O(\corse_inc[0][2]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair337" *) 
  LUT3 #(
    .INIT(8'h08)) 
    \corse_inc[0][2]_i_5 
       (.I0(wl_state_r__0[2]),
        .I1(wr_level_done_r4),
        .I2(wr_level_done_r5),
        .O(\corse_inc[0][2]_i_5_n_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    \corse_inc[0][2]_i_7 
       (.I0(\corse_inc_reg[0][1]_i_4_n_0 ),
        .I1(\corse_inc_reg[0][1]_i_3_n_0 ),
        .O(\corse_inc[0][2]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \corse_inc[0][2]_i_8 
       (.I0(\corse_inc_reg[3]_40 [2]),
        .I1(\corse_inc_reg[2]_39 [2]),
        .I2(\dqs_count_r_reg[1]_rep_0 ),
        .I3(\corse_inc_reg[1]_38 [2]),
        .I4(\dqs_count_r_reg[0]_rep_0 ),
        .I5(\corse_inc_reg[0]_37 [2]),
        .O(\corse_inc[0][2]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \corse_inc[0][2]_i_9 
       (.I0(\corse_inc_reg[7]_44 [2]),
        .I1(\corse_inc_reg[6]_43 [2]),
        .I2(\dqs_count_r_reg[1]_rep_0 ),
        .I3(\corse_inc_reg[5]_42 [2]),
        .I4(\dqs_count_r_reg[0]_rep_0 ),
        .I5(\corse_inc_reg[4]_41 [2]),
        .O(\corse_inc[0][2]_i_9_n_0 ));
  LUT6 #(
    .INIT(64'hBBBBFFBF88880080)) 
    \corse_inc[1][0]_i_1 
       (.I0(\corse_inc[1][0]_i_2_n_0 ),
        .I1(\corse_inc[0][2]_i_3_n_0 ),
        .I2(\fine_inc[1][5]_i_3_n_0 ),
        .I3(\corse_inc[0][2]_i_4_n_0 ),
        .I4(\corse_inc[0][2]_i_5_n_0 ),
        .I5(\corse_inc_reg[1]_38 [0]),
        .O(\corse_inc[1][0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair310" *) 
  LUT5 #(
    .INIT(32'h11B11111)) 
    \corse_inc[1][0]_i_2 
       (.I0(wl_state_r__0[2]),
        .I1(\corse_inc_reg[0][1]_i_3_n_0 ),
        .I2(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I4(\final_coarse_tap_reg_n_0_[1][0] ),
        .O(\corse_inc[1][0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hBBBBFFBF88880080)) 
    \corse_inc[1][1]_i_1 
       (.I0(\corse_inc[1][1]_i_2_n_0 ),
        .I1(\corse_inc[0][2]_i_3_n_0 ),
        .I2(\fine_inc[1][5]_i_3_n_0 ),
        .I3(\corse_inc[0][2]_i_4_n_0 ),
        .I4(\corse_inc[0][2]_i_5_n_0 ),
        .I5(\corse_inc_reg[1]_38 [1]),
        .O(\corse_inc[1][1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h4141EB4141414141)) 
    \corse_inc[1][1]_i_2 
       (.I0(wl_state_r__0[2]),
        .I1(\corse_inc_reg[0][1]_i_3_n_0 ),
        .I2(\corse_inc_reg[0][1]_i_4_n_0 ),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I4(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I5(\final_coarse_tap_reg_n_0_[1][1] ),
        .O(\corse_inc[1][1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hBBBBFFBF88880080)) 
    \corse_inc[1][2]_i_1 
       (.I0(\corse_inc[1][2]_i_2_n_0 ),
        .I1(\corse_inc[0][2]_i_3_n_0 ),
        .I2(\fine_inc[1][5]_i_3_n_0 ),
        .I3(\corse_inc[0][2]_i_4_n_0 ),
        .I4(\corse_inc[0][2]_i_5_n_0 ),
        .I5(\corse_inc_reg[1]_38 [2]),
        .O(\corse_inc[1][2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0606F60606060606)) 
    \corse_inc[1][2]_i_2 
       (.I0(\corse_inc_reg[0][2]_i_6_n_0 ),
        .I1(\corse_inc[0][2]_i_7_n_0 ),
        .I2(wl_state_r__0[2]),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I4(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I5(\final_coarse_tap_reg_n_0_[1][2] ),
        .O(\corse_inc[1][2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hBBBBFFBF88880080)) 
    \corse_inc[2][0]_i_1 
       (.I0(\corse_inc[2][0]_i_2_n_0 ),
        .I1(\corse_inc[0][2]_i_3_n_0 ),
        .I2(\fine_inc[2][5]_i_3_n_0 ),
        .I3(\corse_inc[0][2]_i_4_n_0 ),
        .I4(\corse_inc[0][2]_i_5_n_0 ),
        .I5(\corse_inc_reg[2]_39 [0]),
        .O(\corse_inc[2][0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair311" *) 
  LUT5 #(
    .INIT(32'h11B11111)) 
    \corse_inc[2][0]_i_2 
       (.I0(wl_state_r__0[2]),
        .I1(\corse_inc_reg[0][1]_i_3_n_0 ),
        .I2(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I4(\final_coarse_tap_reg_n_0_[2][0] ),
        .O(\corse_inc[2][0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hBBBBFFBF88880080)) 
    \corse_inc[2][1]_i_1 
       (.I0(\corse_inc[2][1]_i_2_n_0 ),
        .I1(\corse_inc[0][2]_i_3_n_0 ),
        .I2(\fine_inc[2][5]_i_3_n_0 ),
        .I3(\corse_inc[0][2]_i_4_n_0 ),
        .I4(\corse_inc[0][2]_i_5_n_0 ),
        .I5(\corse_inc_reg[2]_39 [1]),
        .O(\corse_inc[2][1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h4141EB4141414141)) 
    \corse_inc[2][1]_i_2 
       (.I0(wl_state_r__0[2]),
        .I1(\corse_inc_reg[0][1]_i_3_n_0 ),
        .I2(\corse_inc_reg[0][1]_i_4_n_0 ),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I4(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I5(\final_coarse_tap_reg_n_0_[2][1] ),
        .O(\corse_inc[2][1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hBBBBFFBF88880080)) 
    \corse_inc[2][2]_i_1 
       (.I0(\corse_inc[2][2]_i_2_n_0 ),
        .I1(\corse_inc[0][2]_i_3_n_0 ),
        .I2(\fine_inc[2][5]_i_3_n_0 ),
        .I3(\corse_inc[0][2]_i_4_n_0 ),
        .I4(\corse_inc[0][2]_i_5_n_0 ),
        .I5(\corse_inc_reg[2]_39 [2]),
        .O(\corse_inc[2][2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0606F60606060606)) 
    \corse_inc[2][2]_i_2 
       (.I0(\corse_inc_reg[0][2]_i_6_n_0 ),
        .I1(\corse_inc[0][2]_i_7_n_0 ),
        .I2(wl_state_r__0[2]),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I4(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I5(\final_coarse_tap_reg_n_0_[2][2] ),
        .O(\corse_inc[2][2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hBBBBFFBF88880080)) 
    \corse_inc[3][0]_i_1 
       (.I0(\corse_inc[3][0]_i_2_n_0 ),
        .I1(\corse_inc[0][2]_i_3_n_0 ),
        .I2(\fine_inc[3][5]_i_3_n_0 ),
        .I3(\corse_inc[0][2]_i_4_n_0 ),
        .I4(\corse_inc[0][2]_i_5_n_0 ),
        .I5(\corse_inc_reg[3]_40 [0]),
        .O(\corse_inc[3][0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair312" *) 
  LUT5 #(
    .INIT(32'h11B11111)) 
    \corse_inc[3][0]_i_2 
       (.I0(wl_state_r__0[2]),
        .I1(\corse_inc_reg[0][1]_i_3_n_0 ),
        .I2(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I4(\final_coarse_tap_reg_n_0_[3][0] ),
        .O(\corse_inc[3][0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hBBBBFFBF88880080)) 
    \corse_inc[3][1]_i_1 
       (.I0(\corse_inc[3][1]_i_2_n_0 ),
        .I1(\corse_inc[0][2]_i_3_n_0 ),
        .I2(\fine_inc[3][5]_i_3_n_0 ),
        .I3(\corse_inc[0][2]_i_4_n_0 ),
        .I4(\corse_inc[0][2]_i_5_n_0 ),
        .I5(\corse_inc_reg[3]_40 [1]),
        .O(\corse_inc[3][1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h4141EB4141414141)) 
    \corse_inc[3][1]_i_2 
       (.I0(wl_state_r__0[2]),
        .I1(\corse_inc_reg[0][1]_i_3_n_0 ),
        .I2(\corse_inc_reg[0][1]_i_4_n_0 ),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I4(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I5(\final_coarse_tap_reg_n_0_[3][1] ),
        .O(\corse_inc[3][1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hBBBBFFBF88880080)) 
    \corse_inc[3][2]_i_1 
       (.I0(\corse_inc[3][2]_i_2_n_0 ),
        .I1(\corse_inc[0][2]_i_3_n_0 ),
        .I2(\fine_inc[3][5]_i_3_n_0 ),
        .I3(\corse_inc[0][2]_i_4_n_0 ),
        .I4(\corse_inc[0][2]_i_5_n_0 ),
        .I5(\corse_inc_reg[3]_40 [2]),
        .O(\corse_inc[3][2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0606F60606060606)) 
    \corse_inc[3][2]_i_2 
       (.I0(\corse_inc_reg[0][2]_i_6_n_0 ),
        .I1(\corse_inc[0][2]_i_7_n_0 ),
        .I2(wl_state_r__0[2]),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I4(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I5(\final_coarse_tap_reg_n_0_[3][2] ),
        .O(\corse_inc[3][2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hBBBBFFBF88880080)) 
    \corse_inc[4][0]_i_1 
       (.I0(\corse_inc[4][0]_i_2_n_0 ),
        .I1(\corse_inc[0][2]_i_3_n_0 ),
        .I2(\fine_inc[4][5]_i_3_n_0 ),
        .I3(\corse_inc[0][2]_i_4_n_0 ),
        .I4(\corse_inc[0][2]_i_5_n_0 ),
        .I5(\corse_inc_reg[4]_41 [0]),
        .O(\corse_inc[4][0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair313" *) 
  LUT5 #(
    .INIT(32'h11B11111)) 
    \corse_inc[4][0]_i_2 
       (.I0(wl_state_r__0[2]),
        .I1(\corse_inc_reg[0][1]_i_3_n_0 ),
        .I2(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I4(\final_coarse_tap_reg_n_0_[4][0] ),
        .O(\corse_inc[4][0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hBBBBFFBF88880080)) 
    \corse_inc[4][1]_i_1 
       (.I0(\corse_inc[4][1]_i_2_n_0 ),
        .I1(\corse_inc[0][2]_i_3_n_0 ),
        .I2(\fine_inc[4][5]_i_3_n_0 ),
        .I3(\corse_inc[0][2]_i_4_n_0 ),
        .I4(\corse_inc[0][2]_i_5_n_0 ),
        .I5(\corse_inc_reg[4]_41 [1]),
        .O(\corse_inc[4][1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h4141EB4141414141)) 
    \corse_inc[4][1]_i_2 
       (.I0(wl_state_r__0[2]),
        .I1(\corse_inc_reg[0][1]_i_3_n_0 ),
        .I2(\corse_inc_reg[0][1]_i_4_n_0 ),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I4(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I5(\final_coarse_tap_reg_n_0_[4][1] ),
        .O(\corse_inc[4][1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hBBBBFFBF88880080)) 
    \corse_inc[4][2]_i_1 
       (.I0(\corse_inc[4][2]_i_2_n_0 ),
        .I1(\corse_inc[0][2]_i_3_n_0 ),
        .I2(\fine_inc[4][5]_i_3_n_0 ),
        .I3(\corse_inc[0][2]_i_4_n_0 ),
        .I4(\corse_inc[0][2]_i_5_n_0 ),
        .I5(\corse_inc_reg[4]_41 [2]),
        .O(\corse_inc[4][2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0606F60606060606)) 
    \corse_inc[4][2]_i_2 
       (.I0(\corse_inc_reg[0][2]_i_6_n_0 ),
        .I1(\corse_inc[0][2]_i_7_n_0 ),
        .I2(wl_state_r__0[2]),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I4(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I5(\final_coarse_tap_reg_n_0_[4][2] ),
        .O(\corse_inc[4][2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hBBBBFFBF88880080)) 
    \corse_inc[5][0]_i_1 
       (.I0(\corse_inc[5][0]_i_2_n_0 ),
        .I1(\corse_inc[0][2]_i_3_n_0 ),
        .I2(\fine_inc[5][5]_i_3_n_0 ),
        .I3(\corse_inc[0][2]_i_4_n_0 ),
        .I4(\corse_inc[0][2]_i_5_n_0 ),
        .I5(\corse_inc_reg[5]_42 [0]),
        .O(\corse_inc[5][0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h11B11111)) 
    \corse_inc[5][0]_i_2 
       (.I0(wl_state_r__0[2]),
        .I1(\corse_inc_reg[0][1]_i_3_n_0 ),
        .I2(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I4(\final_coarse_tap_reg_n_0_[5][0] ),
        .O(\corse_inc[5][0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hBBBBFFBF88880080)) 
    \corse_inc[5][1]_i_1 
       (.I0(\corse_inc[5][1]_i_2_n_0 ),
        .I1(\corse_inc[0][2]_i_3_n_0 ),
        .I2(\fine_inc[5][5]_i_3_n_0 ),
        .I3(\corse_inc[0][2]_i_4_n_0 ),
        .I4(\corse_inc[0][2]_i_5_n_0 ),
        .I5(\corse_inc_reg[5]_42 [1]),
        .O(\corse_inc[5][1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h4141EB4141414141)) 
    \corse_inc[5][1]_i_2 
       (.I0(wl_state_r__0[2]),
        .I1(\corse_inc_reg[0][1]_i_3_n_0 ),
        .I2(\corse_inc_reg[0][1]_i_4_n_0 ),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I4(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I5(\final_coarse_tap_reg_n_0_[5][1] ),
        .O(\corse_inc[5][1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hBBBBFFBF88880080)) 
    \corse_inc[5][2]_i_1 
       (.I0(\corse_inc[5][2]_i_2_n_0 ),
        .I1(\corse_inc[0][2]_i_3_n_0 ),
        .I2(\fine_inc[5][5]_i_3_n_0 ),
        .I3(\corse_inc[0][2]_i_4_n_0 ),
        .I4(\corse_inc[0][2]_i_5_n_0 ),
        .I5(\corse_inc_reg[5]_42 [2]),
        .O(\corse_inc[5][2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0606F60606060606)) 
    \corse_inc[5][2]_i_2 
       (.I0(\corse_inc_reg[0][2]_i_6_n_0 ),
        .I1(\corse_inc[0][2]_i_7_n_0 ),
        .I2(wl_state_r__0[2]),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I4(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I5(\final_coarse_tap_reg_n_0_[5][2] ),
        .O(\corse_inc[5][2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hBBBBFFBF88880080)) 
    \corse_inc[6][0]_i_1 
       (.I0(\corse_inc[6][0]_i_2_n_0 ),
        .I1(\corse_inc[0][2]_i_3_n_0 ),
        .I2(\fine_inc[6][5]_i_3_n_0 ),
        .I3(\corse_inc[0][2]_i_4_n_0 ),
        .I4(\corse_inc[0][2]_i_5_n_0 ),
        .I5(\corse_inc_reg[6]_43 [0]),
        .O(\corse_inc[6][0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h11B11111)) 
    \corse_inc[6][0]_i_2 
       (.I0(wl_state_r__0[2]),
        .I1(\corse_inc_reg[0][1]_i_3_n_0 ),
        .I2(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I4(\final_coarse_tap_reg_n_0_[6][0] ),
        .O(\corse_inc[6][0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hBBBBFFBF88880080)) 
    \corse_inc[6][1]_i_1 
       (.I0(\corse_inc[6][1]_i_2_n_0 ),
        .I1(\corse_inc[0][2]_i_3_n_0 ),
        .I2(\fine_inc[6][5]_i_3_n_0 ),
        .I3(\corse_inc[0][2]_i_4_n_0 ),
        .I4(\corse_inc[0][2]_i_5_n_0 ),
        .I5(\corse_inc_reg[6]_43 [1]),
        .O(\corse_inc[6][1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h4141EB4141414141)) 
    \corse_inc[6][1]_i_2 
       (.I0(wl_state_r__0[2]),
        .I1(\corse_inc_reg[0][1]_i_3_n_0 ),
        .I2(\corse_inc_reg[0][1]_i_4_n_0 ),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I4(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I5(\final_coarse_tap_reg_n_0_[6][1] ),
        .O(\corse_inc[6][1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hBBBBFFBF88880080)) 
    \corse_inc[6][2]_i_1 
       (.I0(\corse_inc[6][2]_i_2_n_0 ),
        .I1(\corse_inc[0][2]_i_3_n_0 ),
        .I2(\fine_inc[6][5]_i_3_n_0 ),
        .I3(\corse_inc[0][2]_i_4_n_0 ),
        .I4(\corse_inc[0][2]_i_5_n_0 ),
        .I5(\corse_inc_reg[6]_43 [2]),
        .O(\corse_inc[6][2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0606F60606060606)) 
    \corse_inc[6][2]_i_2 
       (.I0(\corse_inc_reg[0][2]_i_6_n_0 ),
        .I1(\corse_inc[0][2]_i_7_n_0 ),
        .I2(wl_state_r__0[2]),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I4(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I5(\final_coarse_tap_reg_n_0_[6][2] ),
        .O(\corse_inc[6][2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hBBBBFFBF88880080)) 
    \corse_inc[7][0]_i_1 
       (.I0(\corse_inc[7][0]_i_2_n_0 ),
        .I1(\corse_inc[0][2]_i_3_n_0 ),
        .I2(\fine_inc[7][5]_i_3_n_0 ),
        .I3(\corse_inc[0][2]_i_4_n_0 ),
        .I4(\corse_inc[0][2]_i_5_n_0 ),
        .I5(\corse_inc_reg[7]_44 [0]),
        .O(\corse_inc[7][0]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h11B11111)) 
    \corse_inc[7][0]_i_2 
       (.I0(wl_state_r__0[2]),
        .I1(\corse_inc_reg[0][1]_i_3_n_0 ),
        .I2(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I4(\final_coarse_tap_reg_n_0_[7][0] ),
        .O(\corse_inc[7][0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hBBBBFFBF88880080)) 
    \corse_inc[7][1]_i_1 
       (.I0(\corse_inc[7][1]_i_2_n_0 ),
        .I1(\corse_inc[0][2]_i_3_n_0 ),
        .I2(\fine_inc[7][5]_i_3_n_0 ),
        .I3(\corse_inc[0][2]_i_4_n_0 ),
        .I4(\corse_inc[0][2]_i_5_n_0 ),
        .I5(\corse_inc_reg[7]_44 [1]),
        .O(\corse_inc[7][1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h4141EB4141414141)) 
    \corse_inc[7][1]_i_2 
       (.I0(wl_state_r__0[2]),
        .I1(\corse_inc_reg[0][1]_i_3_n_0 ),
        .I2(\corse_inc_reg[0][1]_i_4_n_0 ),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I4(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I5(\final_coarse_tap_reg_n_0_[7][1] ),
        .O(\corse_inc[7][1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hBBBBFFBF88880080)) 
    \corse_inc[7][2]_i_1 
       (.I0(\corse_inc[7][2]_i_2_n_0 ),
        .I1(\corse_inc[0][2]_i_3_n_0 ),
        .I2(\fine_inc[7][5]_i_3_n_0 ),
        .I3(\corse_inc[0][2]_i_4_n_0 ),
        .I4(\corse_inc[0][2]_i_5_n_0 ),
        .I5(\corse_inc_reg[7]_44 [2]),
        .O(\corse_inc[7][2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0606F60606060606)) 
    \corse_inc[7][2]_i_2 
       (.I0(\corse_inc_reg[0][2]_i_6_n_0 ),
        .I1(\corse_inc[0][2]_i_7_n_0 ),
        .I2(wl_state_r__0[2]),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I4(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I5(\final_coarse_tap_reg_n_0_[7][2] ),
        .O(\corse_inc[7][2]_i_2_n_0 ));
  FDRE \corse_inc_reg[0][0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\corse_inc[0][0]_i_1_n_0 ),
        .Q(\corse_inc_reg[0]_37 [0]),
        .R(\corse_inc_reg[6][2]_0 [0]));
  FDRE \corse_inc_reg[0][1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\corse_inc[0][1]_i_1_n_0 ),
        .Q(\corse_inc_reg[0]_37 [1]),
        .R(\corse_inc_reg[6][2]_0 [0]));
  MUXF7 \corse_inc_reg[0][1]_i_3 
       (.I0(\corse_inc[0][1]_i_5_n_0 ),
        .I1(\corse_inc[0][1]_i_6_n_0 ),
        .O(\corse_inc_reg[0][1]_i_3_n_0 ),
        .S(dqs_count_r[2]));
  MUXF7 \corse_inc_reg[0][1]_i_4 
       (.I0(\corse_inc[0][1]_i_7_n_0 ),
        .I1(\corse_inc[0][1]_i_8_n_0 ),
        .O(\corse_inc_reg[0][1]_i_4_n_0 ),
        .S(dqs_count_r[2]));
  FDRE \corse_inc_reg[0][2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\corse_inc[0][2]_i_1_n_0 ),
        .Q(\corse_inc_reg[0]_37 [2]),
        .R(\corse_inc_reg[6][2]_0 [1]));
  MUXF7 \corse_inc_reg[0][2]_i_6 
       (.I0(\corse_inc[0][2]_i_8_n_0 ),
        .I1(\corse_inc[0][2]_i_9_n_0 ),
        .O(\corse_inc_reg[0][2]_i_6_n_0 ),
        .S(dqs_count_r[2]));
  FDRE \corse_inc_reg[1][0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\corse_inc[1][0]_i_1_n_0 ),
        .Q(\corse_inc_reg[1]_38 [0]),
        .R(\corse_inc_reg[6][2]_0 [0]));
  FDRE \corse_inc_reg[1][1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\corse_inc[1][1]_i_1_n_0 ),
        .Q(\corse_inc_reg[1]_38 [1]),
        .R(\corse_inc_reg[6][2]_0 [0]));
  FDRE \corse_inc_reg[1][2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\corse_inc[1][2]_i_1_n_0 ),
        .Q(\corse_inc_reg[1]_38 [2]),
        .R(\corse_inc_reg[6][2]_0 [1]));
  FDRE \corse_inc_reg[2][0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\corse_inc[2][0]_i_1_n_0 ),
        .Q(\corse_inc_reg[2]_39 [0]),
        .R(\corse_inc_reg[6][2]_0 [0]));
  FDRE \corse_inc_reg[2][1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\corse_inc[2][1]_i_1_n_0 ),
        .Q(\corse_inc_reg[2]_39 [1]),
        .R(\corse_inc_reg[6][2]_0 [0]));
  FDRE \corse_inc_reg[2][2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\corse_inc[2][2]_i_1_n_0 ),
        .Q(\corse_inc_reg[2]_39 [2]),
        .R(\corse_inc_reg[6][2]_0 [1]));
  FDRE \corse_inc_reg[3][0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\corse_inc[3][0]_i_1_n_0 ),
        .Q(\corse_inc_reg[3]_40 [0]),
        .R(\corse_inc_reg[6][2]_0 [0]));
  FDRE \corse_inc_reg[3][1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\corse_inc[3][1]_i_1_n_0 ),
        .Q(\corse_inc_reg[3]_40 [1]),
        .R(\corse_inc_reg[6][2]_0 [0]));
  FDRE \corse_inc_reg[3][2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\corse_inc[3][2]_i_1_n_0 ),
        .Q(\corse_inc_reg[3]_40 [2]),
        .R(\corse_inc_reg[6][2]_0 [1]));
  FDRE \corse_inc_reg[4][0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\corse_inc[4][0]_i_1_n_0 ),
        .Q(\corse_inc_reg[4]_41 [0]),
        .R(\corse_inc_reg[6][2]_0 [0]));
  FDRE \corse_inc_reg[4][1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\corse_inc[4][1]_i_1_n_0 ),
        .Q(\corse_inc_reg[4]_41 [1]),
        .R(\corse_inc_reg[6][2]_0 [0]));
  FDRE \corse_inc_reg[4][2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\corse_inc[4][2]_i_1_n_0 ),
        .Q(\corse_inc_reg[4]_41 [2]),
        .R(\corse_inc_reg[6][2]_0 [1]));
  FDRE \corse_inc_reg[5][0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\corse_inc[5][0]_i_1_n_0 ),
        .Q(\corse_inc_reg[5]_42 [0]),
        .R(\corse_inc_reg[6][2]_0 [0]));
  FDRE \corse_inc_reg[5][1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\corse_inc[5][1]_i_1_n_0 ),
        .Q(\corse_inc_reg[5]_42 [1]),
        .R(\corse_inc_reg[6][2]_0 [0]));
  FDRE \corse_inc_reg[5][2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\corse_inc[5][2]_i_1_n_0 ),
        .Q(\corse_inc_reg[5]_42 [2]),
        .R(\corse_inc_reg[6][2]_0 [1]));
  FDRE \corse_inc_reg[6][0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\corse_inc[6][0]_i_1_n_0 ),
        .Q(\corse_inc_reg[6]_43 [0]),
        .R(\corse_inc_reg[6][2]_0 [0]));
  FDRE \corse_inc_reg[6][1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\corse_inc[6][1]_i_1_n_0 ),
        .Q(\corse_inc_reg[6]_43 [1]),
        .R(\corse_inc_reg[6][2]_0 [0]));
  FDRE \corse_inc_reg[6][2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\corse_inc[6][2]_i_1_n_0 ),
        .Q(\corse_inc_reg[6]_43 [2]),
        .R(\corse_inc_reg[6][2]_0 [1]));
  FDRE \corse_inc_reg[7][0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\corse_inc[7][0]_i_1_n_0 ),
        .Q(\corse_inc_reg[7]_44 [0]),
        .R(\corse_inc_reg[6][2]_0 [0]));
  FDRE \corse_inc_reg[7][1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\corse_inc[7][1]_i_1_n_0 ),
        .Q(\corse_inc_reg[7]_44 [1]),
        .R(\corse_inc_reg[6][2]_0 [0]));
  FDRE \corse_inc_reg[7][2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\corse_inc[7][2]_i_1_n_0 ),
        .Q(\corse_inc_reg[7]_44 [2]),
        .R(\corse_inc_reg[6][2]_0 [1]));
  (* SOFT_HLUTNM = "soft_lutpair348" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \ctl_lane_cnt[1]_i_2 
       (.I0(dqs_po_dec_done),
        .I1(pi_fine_dly_dec_done),
        .O(cmd_delay_start0));
  (* SOFT_HLUTNM = "soft_lutpair348" *) 
  LUT4 #(
    .INIT(16'hFFF7)) 
    \delaydec_cnt_r[5]_i_1 
       (.I0(dqs_po_dec_done),
        .I1(pi_fine_dly_dec_done),
        .I2(\single_rank.done_dqs_dec_reg_0 ),
        .I3(delaydec_cnt_r10_in),
        .O(SS));
  LUT6 #(
    .INIT(64'h005DFFFF005D0000)) 
    dq_cnt_inc_i_1
       (.I0(wl_state_r__0[2]),
        .I1(dq_cnt_inc_i_2_n_0),
        .I2(wrlvl_byte_redo),
        .I3(\fine_inc[7][5]_i_3_n_0 ),
        .I4(dq_cnt_inc_i_3_n_0),
        .I5(p_0_in),
        .O(dq_cnt_inc_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair312" *) 
  LUT2 #(
    .INIT(4'h2)) 
    dq_cnt_inc_i_2
       (.I0(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .O(dq_cnt_inc_i_2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair331" *) 
  LUT5 #(
    .INIT(32'h00000042)) 
    dq_cnt_inc_i_3
       (.I0(wl_state_r__0[1]),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I2(wl_state_r__0[2]),
        .I3(wl_state_r__0[0]),
        .I4(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .O(dq_cnt_inc_i_3_n_0));
  FDSE dq_cnt_inc_reg
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(dq_cnt_inc_i_1_n_0),
        .Q(p_0_in),
        .S(\corse_inc_reg[6][2]_0 [0]));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFF200F2)) 
    \dqs_count_r[0]_i_1 
       (.I0(dqs_count_r[0]),
        .I1(\dqs_count_r[0]_i_2_n_0 ),
        .I2(\dqs_count_r[0]_i_3_n_0 ),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I4(\dqs_count_r[0]_i_4_n_0 ),
        .I5(\dqs_count_r[0]_i_5_n_0 ),
        .O(\dqs_count_r[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF7777777F)) 
    \dqs_count_r[0]_i_2 
       (.I0(wl_state_r__0[1]),
        .I1(wl_state_r__0[0]),
        .I2(wrlvl_byte_redo),
        .I3(p_0_in),
        .I4(wl_state_r__0[2]),
        .I5(\corse_inc[0][2]_i_5_n_0 ),
        .O(\dqs_count_r[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h00000000AC000000)) 
    \dqs_count_r[0]_i_3 
       (.I0(\dqs_count_r_reg[3]_1 [0]),
        .I1(dqs_count_r[0]),
        .I2(done_dqs_dec238_out),
        .I3(wl_state_r__0[2]),
        .I4(wl_state_r__0[1]),
        .I5(wl_state_r__0[0]),
        .O(\dqs_count_r[0]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h00000000F0DAC3DA)) 
    \dqs_count_r[0]_i_4 
       (.I0(\fine_inc[0][5]_i_3_n_0 ),
        .I1(\fine_inc[7][5]_i_3_n_0 ),
        .I2(dqs_count_r[0]),
        .I3(wl_state_r__0[2]),
        .I4(wrlvl_byte_redo),
        .I5(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .O(\dqs_count_r[0]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hF8780000FF0F0000)) 
    \dqs_count_r[0]_i_5 
       (.I0(\dqs_count_r[3]_i_11_n_0 ),
        .I1(\fine_inc[0][5]_i_3_n_0 ),
        .I2(dqs_count_r[0]),
        .I3(\fine_inc[7][5]_i_3_n_0 ),
        .I4(\dqs_count_r[3]_i_12_n_0 ),
        .I5(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .O(\dqs_count_r[0]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF55554055)) 
    \dqs_count_r[1]_i_1 
       (.I0(\dqs_count_r[1]_i_2_n_0 ),
        .I1(\dqs_count_r[3]_i_4_n_0 ),
        .I2(\dqs_count_r[1]_i_3_n_0 ),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I4(\dqs_count_r[1]_i_4_n_0 ),
        .I5(\dqs_count_r[1]_i_5_n_0 ),
        .O(\dqs_count_r[1]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h0000DD0D)) 
    \dqs_count_r[1]_i_2 
       (.I0(dqs_count_r[1]),
        .I1(\dqs_count_r[3]_i_8_n_0 ),
        .I2(\dqs_count_r_reg[3]_1 [1]),
        .I3(\dqs_count_r[3]_i_9_n_0 ),
        .I4(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .O(\dqs_count_r[1]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair302" *) 
  LUT5 #(
    .INIT(32'h66E6CCCC)) 
    \dqs_count_r[1]_i_3 
       (.I0(dqs_count_r[0]),
        .I1(dqs_count_r[1]),
        .I2(\dqs_count_r_reg[2]_rep__0_0 ),
        .I3(\dqs_count_r_reg[3]_0 ),
        .I4(\fine_inc[0][5]_i_3_n_0 ),
        .O(\dqs_count_r[1]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h4400440044000440)) 
    \dqs_count_r[1]_i_4 
       (.I0(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I1(wl_state_r__0[2]),
        .I2(dqs_count_r[0]),
        .I3(dqs_count_r[1]),
        .I4(\fine_inc[7][5]_i_3_n_0 ),
        .I5(wrlvl_byte_redo),
        .O(\dqs_count_r[1]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h4CEC000000FF0000)) 
    \dqs_count_r[1]_i_5 
       (.I0(\dqs_count_r[3]_i_11_n_0 ),
        .I1(dqs_count_r[1]),
        .I2(\fine_inc[0][5]_i_3_n_0 ),
        .I3(\dqs_count_r[1]_i_6_n_0 ),
        .I4(\dqs_count_r[3]_i_12_n_0 ),
        .I5(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .O(\dqs_count_r[1]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair362" *) 
  LUT4 #(
    .INIT(16'h9919)) 
    \dqs_count_r[1]_i_6 
       (.I0(dqs_count_r[0]),
        .I1(dqs_count_r[1]),
        .I2(\dqs_count_r_reg[2]_rep__0_0 ),
        .I3(\dqs_count_r_reg[3]_0 ),
        .O(\dqs_count_r[1]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF55554055)) 
    \dqs_count_r[1]_rep_i_1 
       (.I0(\dqs_count_r[1]_i_2_n_0 ),
        .I1(\dqs_count_r[3]_i_4_n_0 ),
        .I2(\dqs_count_r[1]_i_3_n_0 ),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I4(\dqs_count_r[1]_i_4_n_0 ),
        .I5(\dqs_count_r[1]_i_5_n_0 ),
        .O(\dqs_count_r[1]_rep_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF2E22)) 
    \dqs_count_r[2]_i_1 
       (.I0(\dqs_count_r[2]_i_2_n_0 ),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I2(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I3(\dqs_count_r[2]_i_3_n_0 ),
        .I4(\dqs_count_r[2]_i_4_n_0 ),
        .O(\dqs_count_r[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFF80A280A280A280)) 
    \dqs_count_r[2]_i_2 
       (.I0(\FSM_sequential_wl_state_r_reg[2]_0 ),
        .I1(done_dqs_dec238_out),
        .I2(\dqs_count_r_reg[3]_1 [2]),
        .I3(\dqs_count_r_reg[2]_rep_n_0 ),
        .I4(\dqs_count_r[2]_i_5_n_0 ),
        .I5(\dqs_count_r[2]_i_6_n_0 ),
        .O(\dqs_count_r[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFF8FFFBF00770044)) 
    \dqs_count_r[2]_i_3 
       (.I0(wrlvl_byte_redo),
        .I1(wl_state_r__0[2]),
        .I2(\dqs_count_r_reg[3]_0 ),
        .I3(\dqs_count_r[2]_i_7_n_0 ),
        .I4(\fine_inc[0][5]_i_3_n_0 ),
        .I5(\dqs_count_r_reg[2]_rep__0_0 ),
        .O(\dqs_count_r[2]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h4CEC000000FF0000)) 
    \dqs_count_r[2]_i_4 
       (.I0(\dqs_count_r[3]_i_11_n_0 ),
        .I1(\dqs_count_r_reg[2]_rep__0_0 ),
        .I2(\fine_inc[0][5]_i_3_n_0 ),
        .I3(\dqs_count_r[2]_i_8_n_0 ),
        .I4(\dqs_count_r[3]_i_12_n_0 ),
        .I5(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .O(\dqs_count_r[2]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair323" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \dqs_count_r[2]_i_5 
       (.I0(wl_state_r__0[0]),
        .I1(wl_state_r__0[1]),
        .O(\dqs_count_r[2]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair337" *) 
  LUT5 #(
    .INIT(32'hBFBFBFB0)) 
    \dqs_count_r[2]_i_6 
       (.I0(wr_level_done_r5),
        .I1(wr_level_done_r4),
        .I2(wl_state_r__0[2]),
        .I3(p_0_in),
        .I4(wrlvl_byte_redo),
        .O(\dqs_count_r[2]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair371" *) 
  LUT2 #(
    .INIT(4'h7)) 
    \dqs_count_r[2]_i_7 
       (.I0(dqs_count_r[1]),
        .I1(dqs_count_r[0]),
        .O(\dqs_count_r[2]_i_7_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair355" *) 
  LUT4 #(
    .INIT(16'h803F)) 
    \dqs_count_r[2]_i_8 
       (.I0(\dqs_count_r_reg[3]_0 ),
        .I1(dqs_count_r[1]),
        .I2(dqs_count_r[0]),
        .I3(\dqs_count_r_reg[2]_rep__0_0 ),
        .O(\dqs_count_r[2]_i_8_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF2E22)) 
    \dqs_count_r[2]_rep__0_i_1 
       (.I0(\dqs_count_r[2]_i_2_n_0 ),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I2(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I3(\dqs_count_r[2]_i_3_n_0 ),
        .I4(\dqs_count_r[2]_i_4_n_0 ),
        .O(\dqs_count_r[2]_rep__0_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFF2E22)) 
    \dqs_count_r[2]_rep_i_1 
       (.I0(\dqs_count_r[2]_i_2_n_0 ),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I2(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I3(\dqs_count_r[2]_i_3_n_0 ),
        .I4(\dqs_count_r[2]_i_4_n_0 ),
        .O(\dqs_count_r[2]_rep_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h0282108A)) 
    \dqs_count_r[3]_i_1 
       (.I0(wl_state_r__0[1]),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I2(wl_state_r__0[2]),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I4(wl_state_r__0[0]),
        .O(\dqs_count_r[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair371" *) 
  LUT3 #(
    .INIT(8'h7F)) 
    \dqs_count_r[3]_i_10 
       (.I0(dqs_count_r[0]),
        .I1(dqs_count_r[1]),
        .I2(\dqs_count_r_reg[2]_rep__0_0 ),
        .O(\dqs_count_r[3]_i_10_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair361" *) 
  LUT4 #(
    .INIT(16'h0400)) 
    \dqs_count_r[3]_i_11 
       (.I0(\corse_inc_reg[0][2]_i_6_n_0 ),
        .I1(\corse_inc[0][2]_i_7_n_0 ),
        .I2(wrlvl_byte_redo),
        .I3(wr_level_done_r5),
        .O(\dqs_count_r[3]_i_11_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair358" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \dqs_count_r[3]_i_12 
       (.I0(wl_state_r__0[0]),
        .I1(wl_state_r__0[2]),
        .O(\dqs_count_r[3]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF55554000)) 
    \dqs_count_r[3]_i_2 
       (.I0(\dqs_count_r[3]_i_3_n_0 ),
        .I1(\dqs_count_r_reg[3]_0 ),
        .I2(\dqs_count_r[3]_i_4_n_0 ),
        .I3(\dqs_count_r[3]_i_5_n_0 ),
        .I4(\dqs_count_r[3]_i_6_n_0 ),
        .I5(\dqs_count_r[3]_i_7_n_0 ),
        .O(\dqs_count_r[3]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h0000DD0D)) 
    \dqs_count_r[3]_i_3 
       (.I0(\dqs_count_r_reg[3]_0 ),
        .I1(\dqs_count_r[3]_i_8_n_0 ),
        .I2(\dqs_count_r_reg[3]_1 [3]),
        .I3(\dqs_count_r[3]_i_9_n_0 ),
        .I4(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .O(\dqs_count_r[3]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair310" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \dqs_count_r[3]_i_4 
       (.I0(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I1(wl_state_r__0[2]),
        .O(\dqs_count_r[3]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair362" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \dqs_count_r[3]_i_5 
       (.I0(\dqs_count_r_reg[2]_rep__0_0 ),
        .I1(dqs_count_r[1]),
        .I2(dqs_count_r[0]),
        .I3(\fine_inc[0][5]_i_3_n_0 ),
        .O(\dqs_count_r[3]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h20202000FFFFFFFF)) 
    \dqs_count_r[3]_i_6 
       (.I0(\dqs_count_r_reg[3]_0 ),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I2(wl_state_r__0[2]),
        .I3(wrlvl_byte_redo),
        .I4(\dqs_count_r[3]_i_10_n_0 ),
        .I5(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .O(\dqs_count_r[3]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hF000F00070000000)) 
    \dqs_count_r[3]_i_7 
       (.I0(\dqs_count_r[3]_i_11_n_0 ),
        .I1(\fine_inc[0][5]_i_3_n_0 ),
        .I2(\dqs_count_r_reg[3]_0 ),
        .I3(\dqs_count_r[3]_i_12_n_0 ),
        .I4(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I5(\dqs_count_r[3]_i_10_n_0 ),
        .O(\dqs_count_r[3]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h5555FFFF0CFFFFFF)) 
    \dqs_count_r[3]_i_8 
       (.I0(\dqs_count_r[2]_i_6_n_0 ),
        .I1(wrlvl_byte_redo),
        .I2(wrlvl_byte_redo_r),
        .I3(wl_state_r__0[2]),
        .I4(wl_state_r__0[1]),
        .I5(wl_state_r__0[0]),
        .O(\dqs_count_r[3]_i_8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair345" *) 
  LUT5 #(
    .INIT(32'hFFFFF7FF)) 
    \dqs_count_r[3]_i_9 
       (.I0(wl_state_r__0[2]),
        .I1(wl_state_r__0[1]),
        .I2(wrlvl_byte_redo_r),
        .I3(wrlvl_byte_redo),
        .I4(wl_state_r__0[0]),
        .O(\dqs_count_r[3]_i_9_n_0 ));
  (* MAX_FANOUT = "50" *) 
  (* ORIG_CELL_NAME = "dqs_count_r_reg[0]" *) 
  FDRE \dqs_count_r_reg[0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\dqs_count_r[3]_i_1_n_0 ),
        .D(\dqs_count_r[0]_i_1_n_0 ),
        .Q(dqs_count_r[0]),
        .R(\fine_inc_reg[6][3]_0 [1]));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  (* MAX_FANOUT = "50" *) 
  (* ORIG_CELL_NAME = "dqs_count_r_reg[0]" *) 
  FDRE \dqs_count_r_reg[0]_rep 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\dqs_count_r[3]_i_1_n_0 ),
        .D(\dqs_count_r[0]_i_1_n_0 ),
        .Q(\dqs_count_r_reg[0]_rep_0 ),
        .R(\dqs_count_r_reg[2]_rep__0_2 ));
  (* MAX_FANOUT = "50" *) 
  (* ORIG_CELL_NAME = "dqs_count_r_reg[1]" *) 
  FDRE \dqs_count_r_reg[1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\dqs_count_r[3]_i_1_n_0 ),
        .D(\dqs_count_r[1]_i_1_n_0 ),
        .Q(dqs_count_r[1]),
        .R(\fine_inc_reg[6][3]_0 [1]));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  (* MAX_FANOUT = "50" *) 
  (* ORIG_CELL_NAME = "dqs_count_r_reg[1]" *) 
  FDRE \dqs_count_r_reg[1]_rep 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\dqs_count_r[3]_i_1_n_0 ),
        .D(\dqs_count_r[1]_rep_i_1_n_0 ),
        .Q(\dqs_count_r_reg[1]_rep_0 ),
        .R(\dqs_count_r_reg[2]_rep__0_2 ));
  (* MAX_FANOUT = "50" *) 
  (* ORIG_CELL_NAME = "dqs_count_r_reg[2]" *) 
  FDRE \dqs_count_r_reg[2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\dqs_count_r[3]_i_1_n_0 ),
        .D(\dqs_count_r[2]_i_1_n_0 ),
        .Q(dqs_count_r[2]),
        .R(\fine_inc_reg[6][3]_0 [1]));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  (* MAX_FANOUT = "50" *) 
  (* ORIG_CELL_NAME = "dqs_count_r_reg[2]" *) 
  FDRE \dqs_count_r_reg[2]_rep 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\dqs_count_r[3]_i_1_n_0 ),
        .D(\dqs_count_r[2]_rep_i_1_n_0 ),
        .Q(\dqs_count_r_reg[2]_rep_n_0 ),
        .R(\dqs_count_r_reg[2]_rep__0_2 ));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  (* MAX_FANOUT = "50" *) 
  (* ORIG_CELL_NAME = "dqs_count_r_reg[2]" *) 
  FDRE \dqs_count_r_reg[2]_rep__0 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\dqs_count_r[3]_i_1_n_0 ),
        .D(\dqs_count_r[2]_rep__0_i_1_n_0 ),
        .Q(\dqs_count_r_reg[2]_rep__0_0 ),
        .R(\dqs_count_r_reg[2]_rep__0_2 ));
  (* MAX_FANOUT = "50" *) 
  FDRE \dqs_count_r_reg[3] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\dqs_count_r[3]_i_1_n_0 ),
        .D(\dqs_count_r[3]_i_2_n_0 ),
        .Q(\dqs_count_r_reg[3]_0 ),
        .R(\fine_inc_reg[6][3]_0 [1]));
  (* syn_maxfan = "2" *) 
  FDRE dqs_po_dec_done_reg
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(po_dec_done),
        .Q(dqs_po_dec_done),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hAABAAABAAAEAAAAB)) 
    dqs_po_en_stg2_f_i_1
       (.I0(po_cnt_dec_reg_0),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I2(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I3(wl_state_r__0[1]),
        .I4(wl_state_r__0[0]),
        .I5(wl_state_r__0[2]),
        .O(dqs_po_en_stg2_f_i_1_n_0));
  FDRE dqs_po_en_stg2_f_reg
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(dqs_po_en_stg2_f_i_1_n_0),
        .Q(dqs_po_en_stg2_f),
        .R(\fine_dec_cnt_reg[5]_0 ));
  LUT6 #(
    .INIT(64'h0000000000200000)) 
    dqs_po_stg2_f_incdec_i_1
       (.I0(dqs_po_stg2_f_incdec_i_2_n_0),
        .I1(wl_state_r__0[1]),
        .I2(wl_state_r__0[2]),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I4(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I5(\single_rank.done_dqs_dec_reg_0 ),
        .O(dqs_po_stg2_f_incdec_i_1_n_0));
  LUT6 #(
    .INIT(64'h00000000FBFFFFFE)) 
    dqs_po_stg2_f_incdec_i_2
       (.I0(wl_state_r__0[2]),
        .I1(wl_state_r__0[0]),
        .I2(wl_state_r__0[1]),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I4(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I5(po_cnt_dec_reg_0),
        .O(dqs_po_stg2_f_incdec_i_2_n_0));
  FDRE dqs_po_stg2_f_incdec_reg
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(dqs_po_stg2_f_incdec_i_1_n_0),
        .Q(dqs_po_stg2_f_incdec),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair341" *) 
  LUT5 #(
    .INIT(32'h00000080)) 
    dqs_wl_po_stg2_c_incdec_i_1
       (.I0(wl_state_r__0[0]),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I2(wl_state_r__0[1]),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I4(wl_state_r__0[2]),
        .O(dqs_wl_po_stg2_c_incdec_i_1_n_0));
  FDRE dqs_wl_po_stg2_c_incdec_reg
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(dqs_wl_po_stg2_c_incdec_i_1_n_0),
        .Q(po_stg2_cincdec),
        .R(\corse_inc_reg[6][2]_0 [0]));
  FDRE \final_coarse_tap_reg[0][0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\wl_corse_cnt_reg[0][0]_29 [0]),
        .Q(\final_coarse_tap_reg_n_0_[0][0] ),
        .R(1'b0));
  FDRE \final_coarse_tap_reg[0][1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\wl_corse_cnt_reg[0][0]_29 [1]),
        .Q(\final_coarse_tap_reg_n_0_[0][1] ),
        .R(1'b0));
  FDRE \final_coarse_tap_reg[0][2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\wl_corse_cnt_reg[0][0]_29 [2]),
        .Q(\final_coarse_tap_reg_n_0_[0][2] ),
        .R(1'b0));
  FDRE \final_coarse_tap_reg[1][0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\wl_corse_cnt_reg[0][1]_30 [0]),
        .Q(\final_coarse_tap_reg_n_0_[1][0] ),
        .R(1'b0));
  FDRE \final_coarse_tap_reg[1][1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\wl_corse_cnt_reg[0][1]_30 [1]),
        .Q(\final_coarse_tap_reg_n_0_[1][1] ),
        .R(1'b0));
  FDRE \final_coarse_tap_reg[1][2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\wl_corse_cnt_reg[0][1]_30 [2]),
        .Q(\final_coarse_tap_reg_n_0_[1][2] ),
        .R(1'b0));
  FDRE \final_coarse_tap_reg[2][0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\wl_corse_cnt_reg[0][2]_31 [0]),
        .Q(\final_coarse_tap_reg_n_0_[2][0] ),
        .R(1'b0));
  FDRE \final_coarse_tap_reg[2][1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\wl_corse_cnt_reg[0][2]_31 [1]),
        .Q(\final_coarse_tap_reg_n_0_[2][1] ),
        .R(1'b0));
  FDRE \final_coarse_tap_reg[2][2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\wl_corse_cnt_reg[0][2]_31 [2]),
        .Q(\final_coarse_tap_reg_n_0_[2][2] ),
        .R(1'b0));
  FDRE \final_coarse_tap_reg[3][0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\wl_corse_cnt_reg[0][3]_32 [0]),
        .Q(\final_coarse_tap_reg_n_0_[3][0] ),
        .R(1'b0));
  FDRE \final_coarse_tap_reg[3][1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\wl_corse_cnt_reg[0][3]_32 [1]),
        .Q(\final_coarse_tap_reg_n_0_[3][1] ),
        .R(1'b0));
  FDRE \final_coarse_tap_reg[3][2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\wl_corse_cnt_reg[0][3]_32 [2]),
        .Q(\final_coarse_tap_reg_n_0_[3][2] ),
        .R(1'b0));
  FDRE \final_coarse_tap_reg[4][0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\wl_corse_cnt_reg[0][4]_33 [0]),
        .Q(\final_coarse_tap_reg_n_0_[4][0] ),
        .R(1'b0));
  FDRE \final_coarse_tap_reg[4][1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\wl_corse_cnt_reg[0][4]_33 [1]),
        .Q(\final_coarse_tap_reg_n_0_[4][1] ),
        .R(1'b0));
  FDRE \final_coarse_tap_reg[4][2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\wl_corse_cnt_reg[0][4]_33 [2]),
        .Q(\final_coarse_tap_reg_n_0_[4][2] ),
        .R(1'b0));
  FDRE \final_coarse_tap_reg[5][0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\wl_corse_cnt_reg[0][5]_34 [0]),
        .Q(\final_coarse_tap_reg_n_0_[5][0] ),
        .R(1'b0));
  FDRE \final_coarse_tap_reg[5][1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\wl_corse_cnt_reg[0][5]_34 [1]),
        .Q(\final_coarse_tap_reg_n_0_[5][1] ),
        .R(1'b0));
  FDRE \final_coarse_tap_reg[5][2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\wl_corse_cnt_reg[0][5]_34 [2]),
        .Q(\final_coarse_tap_reg_n_0_[5][2] ),
        .R(1'b0));
  FDRE \final_coarse_tap_reg[6][0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\wl_corse_cnt_reg[0][6]_35 [0]),
        .Q(\final_coarse_tap_reg_n_0_[6][0] ),
        .R(1'b0));
  FDRE \final_coarse_tap_reg[6][1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\wl_corse_cnt_reg[0][6]_35 [1]),
        .Q(\final_coarse_tap_reg_n_0_[6][1] ),
        .R(1'b0));
  FDRE \final_coarse_tap_reg[6][2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\wl_corse_cnt_reg[0][6]_35 [2]),
        .Q(\final_coarse_tap_reg_n_0_[6][2] ),
        .R(1'b0));
  FDRE \final_coarse_tap_reg[7][0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\wl_corse_cnt_reg[0][7]_36 [0]),
        .Q(\final_coarse_tap_reg_n_0_[7][0] ),
        .R(1'b0));
  FDRE \final_coarse_tap_reg[7][1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\wl_corse_cnt_reg[0][7]_36 [1]),
        .Q(\final_coarse_tap_reg_n_0_[7][1] ),
        .R(1'b0));
  FDRE \final_coarse_tap_reg[7][2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\wl_corse_cnt_reg[0][7]_36 [2]),
        .Q(\final_coarse_tap_reg_n_0_[7][2] ),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h00000000CCCC55C5)) 
    \fine_dec_cnt[0]_i_1 
       (.I0(\fine_dec_cnt_reg_n_0_[0] ),
        .I1(\wl_tap_count_r_reg_n_0_[0] ),
        .I2(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I4(wl_state_r__0[1]),
        .I5(wl_state_r__0[2]),
        .O(fine_dec_cnt[0]));
  LUT5 #(
    .INIT(32'h0000E22E)) 
    \fine_dec_cnt[1]_i_1 
       (.I0(\wl_tap_count_r_reg_n_0_[1] ),
        .I1(\fine_dec_cnt[5]_i_8_n_0 ),
        .I2(\fine_dec_cnt_reg_n_0_[1] ),
        .I3(\fine_dec_cnt_reg_n_0_[0] ),
        .I4(wl_state_r__0[2]),
        .O(fine_dec_cnt[1]));
  LUT6 #(
    .INIT(64'h00000000A9A9FF00)) 
    \fine_dec_cnt[2]_i_1 
       (.I0(\fine_dec_cnt_reg_n_0_[2] ),
        .I1(\fine_dec_cnt_reg_n_0_[1] ),
        .I2(\fine_dec_cnt_reg_n_0_[0] ),
        .I3(\wl_tap_count_r_reg_n_0_[2] ),
        .I4(\fine_dec_cnt[5]_i_8_n_0 ),
        .I5(wl_state_r__0[2]),
        .O(fine_dec_cnt[2]));
  LUT5 #(
    .INIT(32'h000099F0)) 
    \fine_dec_cnt[3]_i_1 
       (.I0(\fine_dec_cnt_reg_n_0_[3] ),
        .I1(\fine_dec_cnt[3]_i_2_n_0 ),
        .I2(\wl_tap_count_r_reg_n_0_[3] ),
        .I3(\fine_dec_cnt[5]_i_8_n_0 ),
        .I4(wl_state_r__0[2]),
        .O(fine_dec_cnt[3]));
  LUT3 #(
    .INIT(8'hFE)) 
    \fine_dec_cnt[3]_i_2 
       (.I0(\fine_dec_cnt_reg_n_0_[2] ),
        .I1(\fine_dec_cnt_reg_n_0_[1] ),
        .I2(\fine_dec_cnt_reg_n_0_[0] ),
        .O(\fine_dec_cnt[3]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h000099F0)) 
    \fine_dec_cnt[4]_i_1 
       (.I0(\fine_dec_cnt[4]_i_2_n_0 ),
        .I1(\fine_dec_cnt_reg_n_0_[4] ),
        .I2(\wl_tap_count_r_reg_n_0_[4] ),
        .I3(\fine_dec_cnt[5]_i_8_n_0 ),
        .I4(wl_state_r__0[2]),
        .O(fine_dec_cnt[4]));
  (* SOFT_HLUTNM = "soft_lutpair336" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    \fine_dec_cnt[4]_i_2 
       (.I0(\fine_dec_cnt_reg_n_0_[3] ),
        .I1(\fine_dec_cnt_reg_n_0_[0] ),
        .I2(\fine_dec_cnt_reg_n_0_[1] ),
        .I3(\fine_dec_cnt_reg_n_0_[2] ),
        .O(\fine_dec_cnt[4]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hBBBBBAAAAAAAAAAA)) 
    \fine_dec_cnt[5]_i_1 
       (.I0(\fine_dec_cnt[5]_i_3_n_0 ),
        .I1(\fine_dec_cnt[5]_i_4_n_0 ),
        .I2(\fine_dec_cnt[5]_i_5_n_0 ),
        .I3(wl_sm_start),
        .I4(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I5(\fine_dec_cnt[5]_i_6_n_0 ),
        .O(\fine_dec_cnt[5]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hBFFF)) 
    \fine_dec_cnt[5]_i_10 
       (.I0(\rd_data_edge_detect_r_reg[7]_i_5_n_0 ),
        .I1(\wl_tap_count_r_reg_n_0_[5] ),
        .I2(\wl_tap_count_r_reg_n_0_[4] ),
        .I3(\wl_tap_count_r_reg_n_0_[3] ),
        .O(\fine_dec_cnt[5]_i_10_n_0 ));
  LUT5 #(
    .INIT(32'h000066F0)) 
    \fine_dec_cnt[5]_i_2 
       (.I0(\fine_dec_cnt_reg_n_0_[5] ),
        .I1(\fine_dec_cnt[5]_i_7_n_0 ),
        .I2(\wl_tap_count_r_reg_n_0_[5] ),
        .I3(\fine_dec_cnt[5]_i_8_n_0 ),
        .I4(wl_state_r__0[2]),
        .O(fine_dec_cnt[5]));
  LUT6 #(
    .INIT(64'h0002808200020002)) 
    \fine_dec_cnt[5]_i_3 
       (.I0(\fine_dec_cnt[5]_i_9_n_0 ),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I2(wl_state_r__0[1]),
        .I3(\FSM_sequential_wl_state_r[4]_i_17_n_0 ),
        .I4(\rd_data_edge_detect_r[7]_i_4_n_0 ),
        .I5(wrlvl_byte_redo),
        .O(\fine_dec_cnt[5]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair344" *) 
  LUT3 #(
    .INIT(8'hDF)) 
    \fine_dec_cnt[5]_i_4 
       (.I0(wl_state_r__0[0]),
        .I1(wl_state_r__0[2]),
        .I2(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .O(\fine_dec_cnt[5]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair349" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \fine_dec_cnt[5]_i_5 
       (.I0(\rd_data_edge_detect_r_reg[7]_i_9_n_0 ),
        .I1(\stable_cnt_reg_n_0_[3] ),
        .I2(\stable_cnt_reg_n_0_[1] ),
        .I3(\stable_cnt_reg_n_0_[2] ),
        .O(\fine_dec_cnt[5]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h040004FF00FF00FF)) 
    \fine_dec_cnt[5]_i_6 
       (.I0(\FSM_sequential_wl_state_r[3]_i_7_n_0 ),
        .I1(wl_edge_detect_valid_r_reg_n_0),
        .I2(\fine_dec_cnt[5]_i_10_n_0 ),
        .I3(wl_state_r__0[1]),
        .I4(\FSM_sequential_wl_state_r[4]_i_17_n_0 ),
        .I5(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .O(\fine_dec_cnt[5]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair336" *) 
  LUT5 #(
    .INIT(32'h00000001)) 
    \fine_dec_cnt[5]_i_7 
       (.I0(\fine_dec_cnt_reg_n_0_[4] ),
        .I1(\fine_dec_cnt_reg_n_0_[2] ),
        .I2(\fine_dec_cnt_reg_n_0_[1] ),
        .I3(\fine_dec_cnt_reg_n_0_[0] ),
        .I4(\fine_dec_cnt_reg_n_0_[3] ),
        .O(\fine_dec_cnt[5]_i_7_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair335" *) 
  LUT3 #(
    .INIT(8'h45)) 
    \fine_dec_cnt[5]_i_8 
       (.I0(wl_state_r__0[1]),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I2(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .O(\fine_dec_cnt[5]_i_8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair327" *) 
  LUT3 #(
    .INIT(8'h01)) 
    \fine_dec_cnt[5]_i_9 
       (.I0(wl_state_r__0[2]),
        .I1(wl_state_r__0[0]),
        .I2(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .O(\fine_dec_cnt[5]_i_9_n_0 ));
  FDRE \fine_dec_cnt_reg[0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\fine_dec_cnt[5]_i_1_n_0 ),
        .D(fine_dec_cnt[0]),
        .Q(\fine_dec_cnt_reg_n_0_[0] ),
        .R(\fine_dec_cnt_reg[5]_0 ));
  FDRE \fine_dec_cnt_reg[1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\fine_dec_cnt[5]_i_1_n_0 ),
        .D(fine_dec_cnt[1]),
        .Q(\fine_dec_cnt_reg_n_0_[1] ),
        .R(\fine_dec_cnt_reg[5]_0 ));
  FDRE \fine_dec_cnt_reg[2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\fine_dec_cnt[5]_i_1_n_0 ),
        .D(fine_dec_cnt[2]),
        .Q(\fine_dec_cnt_reg_n_0_[2] ),
        .R(\fine_dec_cnt_reg[5]_0 ));
  FDRE \fine_dec_cnt_reg[3] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\fine_dec_cnt[5]_i_1_n_0 ),
        .D(fine_dec_cnt[3]),
        .Q(\fine_dec_cnt_reg_n_0_[3] ),
        .R(\fine_dec_cnt_reg[5]_0 ));
  FDRE \fine_dec_cnt_reg[4] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\fine_dec_cnt[5]_i_1_n_0 ),
        .D(fine_dec_cnt[4]),
        .Q(\fine_dec_cnt_reg_n_0_[4] ),
        .R(\fine_dec_cnt_reg[5]_0 ));
  FDRE \fine_dec_cnt_reg[5] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\fine_dec_cnt[5]_i_1_n_0 ),
        .D(fine_dec_cnt[5]),
        .Q(\fine_dec_cnt_reg_n_0_[5] ),
        .R(\fine_dec_cnt_reg[5]_0 ));
  LUT5 #(
    .INIT(32'h0B000100)) 
    \fine_inc[0][0]_i_1 
       (.I0(wl_state_r__0[1]),
        .I1(\fine_inc_reg[0][1]_i_2_n_0 ),
        .I2(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I3(wl_state_r__0[0]),
        .I4(\gen_final_tap[0].final_val_reg_n_0_[0][0] ),
        .O(fine_inc[0]));
  LUT6 #(
    .INIT(64'h00EB000000410000)) 
    \fine_inc[0][1]_i_1 
       (.I0(wl_state_r__0[1]),
        .I1(\fine_inc_reg[0][1]_i_2_n_0 ),
        .I2(\fine_inc_reg[0][1]_i_3_n_0 ),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I4(wl_state_r__0[0]),
        .I5(\gen_final_tap[0].final_val_reg_n_0_[0][1] ),
        .O(fine_inc[1]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \fine_inc[0][1]_i_4 
       (.I0(\fine_inc_reg[3]_8 [0]),
        .I1(\fine_inc_reg[2]_7 [0]),
        .I2(\dqs_count_r_reg[1]_rep_0 ),
        .I3(\fine_inc_reg[1]_6 [0]),
        .I4(\dqs_count_r_reg[0]_rep_0 ),
        .I5(\fine_inc_reg[0]_5 [0]),
        .O(\fine_inc[0][1]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \fine_inc[0][1]_i_5 
       (.I0(\fine_inc_reg[7]_12 [0]),
        .I1(\fine_inc_reg[6]_11 [0]),
        .I2(\dqs_count_r_reg[1]_rep_0 ),
        .I3(\fine_inc_reg[5]_10 [0]),
        .I4(\dqs_count_r_reg[0]_rep_0 ),
        .I5(\fine_inc_reg[4]_9 [0]),
        .O(\fine_inc[0][1]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \fine_inc[0][1]_i_6 
       (.I0(\fine_inc_reg[3]_8 [1]),
        .I1(\fine_inc_reg[2]_7 [1]),
        .I2(\dqs_count_r_reg[1]_rep_0 ),
        .I3(\fine_inc_reg[1]_6 [1]),
        .I4(\dqs_count_r_reg[0]_rep_0 ),
        .I5(\fine_inc_reg[0]_5 [1]),
        .O(\fine_inc[0][1]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \fine_inc[0][1]_i_7 
       (.I0(\fine_inc_reg[7]_12 [1]),
        .I1(\fine_inc_reg[6]_11 [1]),
        .I2(\dqs_count_r_reg[1]_rep_0 ),
        .I3(\fine_inc_reg[5]_10 [1]),
        .I4(\dqs_count_r_reg[0]_rep_0 ),
        .I5(\fine_inc_reg[4]_9 [1]),
        .O(\fine_inc[0][1]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h00EB000000410000)) 
    \fine_inc[0][2]_i_1 
       (.I0(wl_state_r__0[1]),
        .I1(\fine_inc_reg[0][2]_i_2_n_0 ),
        .I2(\fine_inc[0][2]_i_3_n_0 ),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I4(wl_state_r__0[0]),
        .I5(\gen_final_tap[0].final_val_reg_n_0_[0][2] ),
        .O(fine_inc[2]));
  LUT2 #(
    .INIT(4'hE)) 
    \fine_inc[0][2]_i_3 
       (.I0(\fine_inc_reg[0][1]_i_3_n_0 ),
        .I1(\fine_inc_reg[0][1]_i_2_n_0 ),
        .O(\fine_inc[0][2]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \fine_inc[0][2]_i_4 
       (.I0(\fine_inc_reg[3]_8 [2]),
        .I1(\fine_inc_reg[2]_7 [2]),
        .I2(\dqs_count_r_reg[1]_rep_0 ),
        .I3(\fine_inc_reg[1]_6 [2]),
        .I4(\dqs_count_r_reg[0]_rep_0 ),
        .I5(\fine_inc_reg[0]_5 [2]),
        .O(\fine_inc[0][2]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \fine_inc[0][2]_i_5 
       (.I0(\fine_inc_reg[7]_12 [2]),
        .I1(\fine_inc_reg[6]_11 [2]),
        .I2(\dqs_count_r_reg[1]_rep_0 ),
        .I3(\fine_inc_reg[5]_10 [2]),
        .I4(\dqs_count_r_reg[0]_rep_0 ),
        .I5(\fine_inc_reg[4]_9 [2]),
        .O(\fine_inc[0][2]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h00EB000000410000)) 
    \fine_inc[0][3]_i_1 
       (.I0(wl_state_r__0[1]),
        .I1(\fine_inc_reg[0][3]_i_2_n_0 ),
        .I2(\fine_inc[0][3]_i_3_n_0 ),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I4(wl_state_r__0[0]),
        .I5(\gen_final_tap[0].final_val_reg_n_0_[0][3] ),
        .O(fine_inc[3]));
  (* SOFT_HLUTNM = "soft_lutpair299" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \fine_inc[0][3]_i_3 
       (.I0(\fine_inc[0][2]_i_3_n_0 ),
        .I1(\fine_inc_reg[0][2]_i_2_n_0 ),
        .O(\fine_inc[0][3]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \fine_inc[0][3]_i_4 
       (.I0(\fine_inc_reg[3]_8 [3]),
        .I1(\fine_inc_reg[2]_7 [3]),
        .I2(\dqs_count_r_reg[1]_rep_0 ),
        .I3(\fine_inc_reg[1]_6 [3]),
        .I4(\dqs_count_r_reg[0]_rep_0 ),
        .I5(\fine_inc_reg[0]_5 [3]),
        .O(\fine_inc[0][3]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \fine_inc[0][3]_i_5 
       (.I0(\fine_inc_reg[7]_12 [3]),
        .I1(\fine_inc_reg[6]_11 [3]),
        .I2(\dqs_count_r_reg[1]_rep_0 ),
        .I3(\fine_inc_reg[5]_10 [3]),
        .I4(\dqs_count_r_reg[0]_rep_0 ),
        .I5(\fine_inc_reg[4]_9 [3]),
        .O(\fine_inc[0][3]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair321" *) 
  LUT5 #(
    .INIT(32'h40004444)) 
    \fine_inc[0][4]_i_1 
       (.I0(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I1(wl_state_r__0[0]),
        .I2(wl_state_r__0[1]),
        .I3(\gen_final_tap[0].final_val_reg_n_0_[0][4] ),
        .I4(\fine_inc[0][4]_i_2_n_0 ),
        .O(fine_inc[4]));
  (* SOFT_HLUTNM = "soft_lutpair360" *) 
  LUT4 #(
    .INIT(16'hBBBE)) 
    \fine_inc[0][4]_i_2 
       (.I0(wl_state_r__0[1]),
        .I1(\fine_inc_reg[0][5]_i_9_n_0 ),
        .I2(\fine_inc[0][3]_i_3_n_0 ),
        .I3(\fine_inc_reg[0][3]_i_2_n_0 ),
        .O(\fine_inc[0][4]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h202C202000000000)) 
    \fine_inc[0][5]_i_1 
       (.I0(wr_level_done_r4),
        .I1(wr_level_done_r5),
        .I2(wl_state_r__0[1]),
        .I3(\fine_inc[0][5]_i_3_n_0 ),
        .I4(\fine_inc[0][5]_i_4_n_0 ),
        .I5(\fine_inc[0][5]_i_5_n_0 ),
        .O(\fine_inc[0][5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \fine_inc[0][5]_i_10 
       (.I0(\fine_inc_reg[3]_8 [5]),
        .I1(\fine_inc_reg[2]_7 [5]),
        .I2(\dqs_count_r_reg[1]_rep_0 ),
        .I3(\fine_inc_reg[1]_6 [5]),
        .I4(\dqs_count_r_reg[0]_rep_0 ),
        .I5(\fine_inc_reg[0]_5 [5]),
        .O(\fine_inc[0][5]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \fine_inc[0][5]_i_11 
       (.I0(\fine_inc_reg[7]_12 [5]),
        .I1(\fine_inc_reg[6]_11 [5]),
        .I2(\dqs_count_r_reg[1]_rep_0 ),
        .I3(\fine_inc_reg[5]_10 [5]),
        .I4(\dqs_count_r_reg[0]_rep_0 ),
        .I5(\fine_inc_reg[4]_9 [5]),
        .O(\fine_inc[0][5]_i_11_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \fine_inc[0][5]_i_12 
       (.I0(\fine_inc_reg[3]_8 [4]),
        .I1(\fine_inc_reg[2]_7 [4]),
        .I2(\dqs_count_r_reg[1]_rep_0 ),
        .I3(\fine_inc_reg[1]_6 [4]),
        .I4(\dqs_count_r_reg[0]_rep_0 ),
        .I5(\fine_inc_reg[0]_5 [4]),
        .O(\fine_inc[0][5]_i_12_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \fine_inc[0][5]_i_13 
       (.I0(\fine_inc_reg[7]_12 [4]),
        .I1(\fine_inc_reg[6]_11 [4]),
        .I2(\dqs_count_r_reg[1]_rep_0 ),
        .I3(\fine_inc_reg[5]_10 [4]),
        .I4(\dqs_count_r_reg[0]_rep_0 ),
        .I5(\fine_inc_reg[4]_9 [4]),
        .O(\fine_inc[0][5]_i_13_n_0 ));
  LUT6 #(
    .INIT(64'hA280A280A28080A2)) 
    \fine_inc[0][5]_i_2 
       (.I0(\fine_inc[0][5]_i_6_n_0 ),
        .I1(wl_state_r__0[1]),
        .I2(\gen_final_tap[0].final_val_reg_n_0_[0][5] ),
        .I3(\fine_inc_reg[0][5]_i_7_n_0 ),
        .I4(\fine_inc[0][5]_i_8_n_0 ),
        .I5(\fine_inc_reg[0][5]_i_9_n_0 ),
        .O(fine_inc[5]));
  (* SOFT_HLUTNM = "soft_lutpair299" *) 
  LUT5 #(
    .INIT(32'h00000001)) 
    \fine_inc[0][5]_i_3 
       (.I0(\fine_inc[0][2]_i_3_n_0 ),
        .I1(\fine_inc_reg[0][2]_i_2_n_0 ),
        .I2(\fine_inc_reg[0][3]_i_2_n_0 ),
        .I3(\fine_inc_reg[0][5]_i_9_n_0 ),
        .I4(\fine_inc_reg[0][5]_i_7_n_0 ),
        .O(\fine_inc[0][5]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair353" *) 
  LUT4 #(
    .INIT(16'h0001)) 
    \fine_inc[0][5]_i_4 
       (.I0(dqs_count_r[0]),
        .I1(dqs_count_r[1]),
        .I2(\dqs_count_r_reg[2]_rep__0_0 ),
        .I3(\dqs_count_r_reg[3]_0 ),
        .O(\fine_inc[0][5]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair343" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \fine_inc[0][5]_i_5 
       (.I0(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I1(wl_state_r__0[0]),
        .I2(wl_state_r__0[2]),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .O(\fine_inc[0][5]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair307" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \fine_inc[0][5]_i_6 
       (.I0(wl_state_r__0[0]),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .O(\fine_inc[0][5]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair360" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \fine_inc[0][5]_i_8 
       (.I0(\fine_inc[0][3]_i_3_n_0 ),
        .I1(\fine_inc_reg[0][3]_i_2_n_0 ),
        .O(\fine_inc[0][5]_i_8_n_0 ));
  LUT5 #(
    .INIT(32'h0B000100)) 
    \fine_inc[1][0]_i_1 
       (.I0(wl_state_r__0[1]),
        .I1(\fine_inc_reg[0][1]_i_2_n_0 ),
        .I2(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I3(wl_state_r__0[0]),
        .I4(\gen_final_tap[1].final_val_reg_n_0_[1][0] ),
        .O(\fine_inc[1][0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00EB000000410000)) 
    \fine_inc[1][1]_i_1 
       (.I0(wl_state_r__0[1]),
        .I1(\fine_inc_reg[0][1]_i_2_n_0 ),
        .I2(\fine_inc_reg[0][1]_i_3_n_0 ),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I4(wl_state_r__0[0]),
        .I5(\gen_final_tap[1].final_val_reg_n_0_[1][1] ),
        .O(\fine_inc[1][1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00EB000000410000)) 
    \fine_inc[1][2]_i_1 
       (.I0(wl_state_r__0[1]),
        .I1(\fine_inc_reg[0][2]_i_2_n_0 ),
        .I2(\fine_inc[0][2]_i_3_n_0 ),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I4(wl_state_r__0[0]),
        .I5(\gen_final_tap[1].final_val_reg_n_0_[1][2] ),
        .O(\fine_inc[1][2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00EB000000410000)) 
    \fine_inc[1][3]_i_1 
       (.I0(wl_state_r__0[1]),
        .I1(\fine_inc_reg[0][3]_i_2_n_0 ),
        .I2(\fine_inc[0][3]_i_3_n_0 ),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I4(wl_state_r__0[0]),
        .I5(\gen_final_tap[1].final_val_reg_n_0_[1][3] ),
        .O(\fine_inc[1][3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair322" *) 
  LUT5 #(
    .INIT(32'h40004444)) 
    \fine_inc[1][4]_i_1 
       (.I0(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I1(wl_state_r__0[0]),
        .I2(wl_state_r__0[1]),
        .I3(\gen_final_tap[1].final_val_reg_n_0_[1][4] ),
        .I4(\fine_inc[0][4]_i_2_n_0 ),
        .O(\fine_inc[1][4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0020AA0000200000)) 
    \fine_inc[1][5]_i_1 
       (.I0(\fine_inc[0][5]_i_5_n_0 ),
        .I1(\fine_inc[0][5]_i_3_n_0 ),
        .I2(\fine_inc[1][5]_i_3_n_0 ),
        .I3(wl_state_r__0[1]),
        .I4(wr_level_done_r5),
        .I5(wr_level_done_r4),
        .O(\fine_inc[1][5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hA280A280A28080A2)) 
    \fine_inc[1][5]_i_2 
       (.I0(\fine_inc[0][5]_i_6_n_0 ),
        .I1(wl_state_r__0[1]),
        .I2(\gen_final_tap[1].final_val_reg_n_0_[1][5] ),
        .I3(\fine_inc_reg[0][5]_i_7_n_0 ),
        .I4(\fine_inc[0][5]_i_8_n_0 ),
        .I5(\fine_inc_reg[0][5]_i_9_n_0 ),
        .O(\fine_inc[1][5]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair353" *) 
  LUT4 #(
    .INIT(16'h0004)) 
    \fine_inc[1][5]_i_3 
       (.I0(dqs_count_r[1]),
        .I1(dqs_count_r[0]),
        .I2(\dqs_count_r_reg[2]_rep__0_0 ),
        .I3(\dqs_count_r_reg[3]_0 ),
        .O(\fine_inc[1][5]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'h0B000100)) 
    \fine_inc[2][0]_i_1 
       (.I0(wl_state_r__0[1]),
        .I1(\fine_inc_reg[0][1]_i_2_n_0 ),
        .I2(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I3(wl_state_r__0[0]),
        .I4(\gen_final_tap[2].final_val_reg_n_0_[2][0] ),
        .O(\fine_inc[2][0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00EB000000410000)) 
    \fine_inc[2][1]_i_1 
       (.I0(wl_state_r__0[1]),
        .I1(\fine_inc_reg[0][1]_i_2_n_0 ),
        .I2(\fine_inc_reg[0][1]_i_3_n_0 ),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I4(wl_state_r__0[0]),
        .I5(\gen_final_tap[2].final_val_reg_n_0_[2][1] ),
        .O(\fine_inc[2][1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00EB000000410000)) 
    \fine_inc[2][2]_i_1 
       (.I0(wl_state_r__0[1]),
        .I1(\fine_inc_reg[0][2]_i_2_n_0 ),
        .I2(\fine_inc[0][2]_i_3_n_0 ),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I4(wl_state_r__0[0]),
        .I5(\gen_final_tap[2].final_val_reg_n_0_[2][2] ),
        .O(\fine_inc[2][2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00EB000000410000)) 
    \fine_inc[2][3]_i_1 
       (.I0(wl_state_r__0[1]),
        .I1(\fine_inc_reg[0][3]_i_2_n_0 ),
        .I2(\fine_inc[0][3]_i_3_n_0 ),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I4(wl_state_r__0[0]),
        .I5(\gen_final_tap[2].final_val_reg_n_0_[2][3] ),
        .O(\fine_inc[2][3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair323" *) 
  LUT5 #(
    .INIT(32'h40004444)) 
    \fine_inc[2][4]_i_1 
       (.I0(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I1(wl_state_r__0[0]),
        .I2(wl_state_r__0[1]),
        .I3(\gen_final_tap[2].final_val_reg_n_0_[2][4] ),
        .I4(\fine_inc[0][4]_i_2_n_0 ),
        .O(\fine_inc[2][4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0020AA0000200000)) 
    \fine_inc[2][5]_i_1 
       (.I0(\fine_inc[0][5]_i_5_n_0 ),
        .I1(\fine_inc[0][5]_i_3_n_0 ),
        .I2(\fine_inc[2][5]_i_3_n_0 ),
        .I3(wl_state_r__0[1]),
        .I4(wr_level_done_r5),
        .I5(wr_level_done_r4),
        .O(\fine_inc[2][5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hA280A280A28080A2)) 
    \fine_inc[2][5]_i_2 
       (.I0(\fine_inc[0][5]_i_6_n_0 ),
        .I1(wl_state_r__0[1]),
        .I2(\gen_final_tap[2].final_val_reg_n_0_[2][5] ),
        .I3(\fine_inc_reg[0][5]_i_7_n_0 ),
        .I4(\fine_inc[0][5]_i_8_n_0 ),
        .I5(\fine_inc_reg[0][5]_i_9_n_0 ),
        .O(\fine_inc[2][5]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair352" *) 
  LUT4 #(
    .INIT(16'h0004)) 
    \fine_inc[2][5]_i_3 
       (.I0(dqs_count_r[0]),
        .I1(dqs_count_r[1]),
        .I2(\dqs_count_r_reg[2]_rep_n_0 ),
        .I3(\dqs_count_r_reg[3]_0 ),
        .O(\fine_inc[2][5]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'h0B000100)) 
    \fine_inc[3][0]_i_1 
       (.I0(wl_state_r__0[1]),
        .I1(\fine_inc_reg[0][1]_i_2_n_0 ),
        .I2(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I3(wl_state_r__0[0]),
        .I4(\gen_final_tap[3].final_val_reg_n_0_[3][0] ),
        .O(\fine_inc[3][0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00EB000000410000)) 
    \fine_inc[3][1]_i_1 
       (.I0(wl_state_r__0[1]),
        .I1(\fine_inc_reg[0][1]_i_2_n_0 ),
        .I2(\fine_inc_reg[0][1]_i_3_n_0 ),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I4(wl_state_r__0[0]),
        .I5(\gen_final_tap[3].final_val_reg_n_0_[3][1] ),
        .O(\fine_inc[3][1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00EB000000410000)) 
    \fine_inc[3][2]_i_1 
       (.I0(wl_state_r__0[1]),
        .I1(\fine_inc_reg[0][2]_i_2_n_0 ),
        .I2(\fine_inc[0][2]_i_3_n_0 ),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I4(wl_state_r__0[0]),
        .I5(\gen_final_tap[3].final_val_reg_n_0_[3][2] ),
        .O(\fine_inc[3][2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00EB000000410000)) 
    \fine_inc[3][3]_i_1 
       (.I0(wl_state_r__0[1]),
        .I1(\fine_inc_reg[0][3]_i_2_n_0 ),
        .I2(\fine_inc[0][3]_i_3_n_0 ),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I4(wl_state_r__0[0]),
        .I5(\gen_final_tap[3].final_val_reg_n_0_[3][3] ),
        .O(\fine_inc[3][3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair324" *) 
  LUT5 #(
    .INIT(32'h40004444)) 
    \fine_inc[3][4]_i_1 
       (.I0(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I1(wl_state_r__0[0]),
        .I2(wl_state_r__0[1]),
        .I3(\gen_final_tap[3].final_val_reg_n_0_[3][4] ),
        .I4(\fine_inc[0][4]_i_2_n_0 ),
        .O(\fine_inc[3][4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0020AA0000200000)) 
    \fine_inc[3][5]_i_1 
       (.I0(\fine_inc[0][5]_i_5_n_0 ),
        .I1(\fine_inc[0][5]_i_3_n_0 ),
        .I2(\fine_inc[3][5]_i_3_n_0 ),
        .I3(wl_state_r__0[1]),
        .I4(wr_level_done_r5),
        .I5(wr_level_done_r4),
        .O(\fine_inc[3][5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hA280A280A28080A2)) 
    \fine_inc[3][5]_i_2 
       (.I0(\fine_inc[0][5]_i_6_n_0 ),
        .I1(wl_state_r__0[1]),
        .I2(\gen_final_tap[3].final_val_reg_n_0_[3][5] ),
        .I3(\fine_inc_reg[0][5]_i_7_n_0 ),
        .I4(\fine_inc[0][5]_i_8_n_0 ),
        .I5(\fine_inc_reg[0][5]_i_9_n_0 ),
        .O(\fine_inc[3][5]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair352" *) 
  LUT4 #(
    .INIT(16'h1000)) 
    \fine_inc[3][5]_i_3 
       (.I0(\dqs_count_r_reg[2]_rep_n_0 ),
        .I1(\dqs_count_r_reg[3]_0 ),
        .I2(dqs_count_r[0]),
        .I3(dqs_count_r[1]),
        .O(\fine_inc[3][5]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'h0B000100)) 
    \fine_inc[4][0]_i_1 
       (.I0(wl_state_r__0[1]),
        .I1(\fine_inc_reg[0][1]_i_2_n_0 ),
        .I2(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I3(wl_state_r__0[0]),
        .I4(\gen_final_tap[4].final_val_reg_n_0_[4][0] ),
        .O(\fine_inc[4][0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00EB000000410000)) 
    \fine_inc[4][1]_i_1 
       (.I0(wl_state_r__0[1]),
        .I1(\fine_inc_reg[0][1]_i_2_n_0 ),
        .I2(\fine_inc_reg[0][1]_i_3_n_0 ),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I4(wl_state_r__0[0]),
        .I5(\gen_final_tap[4].final_val_reg_n_0_[4][1] ),
        .O(\fine_inc[4][1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00EB000000410000)) 
    \fine_inc[4][2]_i_1 
       (.I0(wl_state_r__0[1]),
        .I1(\fine_inc_reg[0][2]_i_2_n_0 ),
        .I2(\fine_inc[0][2]_i_3_n_0 ),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I4(wl_state_r__0[0]),
        .I5(\gen_final_tap[4].final_val_reg_n_0_[4][2] ),
        .O(\fine_inc[4][2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00EB000000410000)) 
    \fine_inc[4][3]_i_1 
       (.I0(wl_state_r__0[1]),
        .I1(\fine_inc_reg[0][3]_i_2_n_0 ),
        .I2(\fine_inc[0][3]_i_3_n_0 ),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I4(wl_state_r__0[0]),
        .I5(\gen_final_tap[4].final_val_reg_n_0_[4][3] ),
        .O(\fine_inc[4][3]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h40004444)) 
    \fine_inc[4][4]_i_1 
       (.I0(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I1(wl_state_r__0[0]),
        .I2(wl_state_r__0[1]),
        .I3(\gen_final_tap[4].final_val_reg_n_0_[4][4] ),
        .I4(\fine_inc[0][4]_i_2_n_0 ),
        .O(\fine_inc[4][4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0020AA0000200000)) 
    \fine_inc[4][5]_i_1 
       (.I0(\fine_inc[0][5]_i_5_n_0 ),
        .I1(\fine_inc[0][5]_i_3_n_0 ),
        .I2(\fine_inc[4][5]_i_3_n_0 ),
        .I3(wl_state_r__0[1]),
        .I4(wr_level_done_r5),
        .I5(wr_level_done_r4),
        .O(\fine_inc[4][5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hA280A280A28080A2)) 
    \fine_inc[4][5]_i_2 
       (.I0(\fine_inc[0][5]_i_6_n_0 ),
        .I1(wl_state_r__0[1]),
        .I2(\gen_final_tap[4].final_val_reg_n_0_[4][5] ),
        .I3(\fine_inc_reg[0][5]_i_7_n_0 ),
        .I4(\fine_inc[0][5]_i_8_n_0 ),
        .I5(\fine_inc_reg[0][5]_i_9_n_0 ),
        .O(\fine_inc[4][5]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair354" *) 
  LUT4 #(
    .INIT(16'h0010)) 
    \fine_inc[4][5]_i_3 
       (.I0(dqs_count_r[0]),
        .I1(dqs_count_r[1]),
        .I2(\dqs_count_r_reg[2]_rep__0_0 ),
        .I3(\dqs_count_r_reg[3]_0 ),
        .O(\fine_inc[4][5]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'h0B000100)) 
    \fine_inc[5][0]_i_1 
       (.I0(wl_state_r__0[1]),
        .I1(\fine_inc_reg[0][1]_i_2_n_0 ),
        .I2(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I3(wl_state_r__0[0]),
        .I4(\gen_final_tap[5].final_val_reg_n_0_[5][0] ),
        .O(\fine_inc[5][0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00EB000000410000)) 
    \fine_inc[5][1]_i_1 
       (.I0(wl_state_r__0[1]),
        .I1(\fine_inc_reg[0][1]_i_2_n_0 ),
        .I2(\fine_inc_reg[0][1]_i_3_n_0 ),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I4(wl_state_r__0[0]),
        .I5(\gen_final_tap[5].final_val_reg_n_0_[5][1] ),
        .O(\fine_inc[5][1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00EB000000410000)) 
    \fine_inc[5][2]_i_1 
       (.I0(wl_state_r__0[1]),
        .I1(\fine_inc_reg[0][2]_i_2_n_0 ),
        .I2(\fine_inc[0][2]_i_3_n_0 ),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I4(wl_state_r__0[0]),
        .I5(\gen_final_tap[5].final_val_reg_n_0_[5][2] ),
        .O(\fine_inc[5][2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00EB000000410000)) 
    \fine_inc[5][3]_i_1 
       (.I0(wl_state_r__0[1]),
        .I1(\fine_inc_reg[0][3]_i_2_n_0 ),
        .I2(\fine_inc[0][3]_i_3_n_0 ),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I4(wl_state_r__0[0]),
        .I5(\gen_final_tap[5].final_val_reg_n_0_[5][3] ),
        .O(\fine_inc[5][3]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h40004444)) 
    \fine_inc[5][4]_i_1 
       (.I0(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I1(wl_state_r__0[0]),
        .I2(wl_state_r__0[1]),
        .I3(\gen_final_tap[5].final_val_reg_n_0_[5][4] ),
        .I4(\fine_inc[0][4]_i_2_n_0 ),
        .O(\fine_inc[5][4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0020AA0000200000)) 
    \fine_inc[5][5]_i_1 
       (.I0(\fine_inc[0][5]_i_5_n_0 ),
        .I1(\fine_inc[0][5]_i_3_n_0 ),
        .I2(\fine_inc[5][5]_i_3_n_0 ),
        .I3(wl_state_r__0[1]),
        .I4(wr_level_done_r5),
        .I5(wr_level_done_r4),
        .O(\fine_inc[5][5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hA280A280A28080A2)) 
    \fine_inc[5][5]_i_2 
       (.I0(\fine_inc[0][5]_i_6_n_0 ),
        .I1(wl_state_r__0[1]),
        .I2(\gen_final_tap[5].final_val_reg_n_0_[5][5] ),
        .I3(\fine_inc_reg[0][5]_i_7_n_0 ),
        .I4(\fine_inc[0][5]_i_8_n_0 ),
        .I5(\fine_inc_reg[0][5]_i_9_n_0 ),
        .O(\fine_inc[5][5]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair354" *) 
  LUT4 #(
    .INIT(16'h0040)) 
    \fine_inc[5][5]_i_3 
       (.I0(dqs_count_r[1]),
        .I1(dqs_count_r[0]),
        .I2(\dqs_count_r_reg[2]_rep__0_0 ),
        .I3(\dqs_count_r_reg[3]_0 ),
        .O(\fine_inc[5][5]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'h0B000100)) 
    \fine_inc[6][0]_i_1 
       (.I0(wl_state_r__0[1]),
        .I1(\fine_inc_reg[0][1]_i_2_n_0 ),
        .I2(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I3(wl_state_r__0[0]),
        .I4(\gen_final_tap[6].final_val_reg_n_0_[6][0] ),
        .O(\fine_inc[6][0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00EB000000410000)) 
    \fine_inc[6][1]_i_1 
       (.I0(wl_state_r__0[1]),
        .I1(\fine_inc_reg[0][1]_i_2_n_0 ),
        .I2(\fine_inc_reg[0][1]_i_3_n_0 ),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I4(wl_state_r__0[0]),
        .I5(\gen_final_tap[6].final_val_reg_n_0_[6][1] ),
        .O(\fine_inc[6][1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00EB000000410000)) 
    \fine_inc[6][2]_i_1 
       (.I0(wl_state_r__0[1]),
        .I1(\fine_inc_reg[0][2]_i_2_n_0 ),
        .I2(\fine_inc[0][2]_i_3_n_0 ),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I4(wl_state_r__0[0]),
        .I5(\gen_final_tap[6].final_val_reg_n_0_[6][2] ),
        .O(\fine_inc[6][2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00EB000000410000)) 
    \fine_inc[6][3]_i_1 
       (.I0(wl_state_r__0[1]),
        .I1(\fine_inc_reg[0][3]_i_2_n_0 ),
        .I2(\fine_inc[0][3]_i_3_n_0 ),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I4(wl_state_r__0[0]),
        .I5(\gen_final_tap[6].final_val_reg_n_0_[6][3] ),
        .O(\fine_inc[6][3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair307" *) 
  LUT5 #(
    .INIT(32'h40004444)) 
    \fine_inc[6][4]_i_1 
       (.I0(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I1(wl_state_r__0[0]),
        .I2(wl_state_r__0[1]),
        .I3(\gen_final_tap[6].final_val_reg_n_0_[6][4] ),
        .I4(\fine_inc[0][4]_i_2_n_0 ),
        .O(\fine_inc[6][4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0020AA0000200000)) 
    \fine_inc[6][5]_i_1 
       (.I0(\fine_inc[0][5]_i_5_n_0 ),
        .I1(\fine_inc[0][5]_i_3_n_0 ),
        .I2(\fine_inc[6][5]_i_3_n_0 ),
        .I3(wl_state_r__0[1]),
        .I4(wr_level_done_r5),
        .I5(wr_level_done_r4),
        .O(\fine_inc[6][5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hA280A280A28080A2)) 
    \fine_inc[6][5]_i_2 
       (.I0(\fine_inc[0][5]_i_6_n_0 ),
        .I1(wl_state_r__0[1]),
        .I2(\gen_final_tap[6].final_val_reg_n_0_[6][5] ),
        .I3(\fine_inc_reg[0][5]_i_7_n_0 ),
        .I4(\fine_inc[0][5]_i_8_n_0 ),
        .I5(\fine_inc_reg[0][5]_i_9_n_0 ),
        .O(\fine_inc[6][5]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair355" *) 
  LUT4 #(
    .INIT(16'h0040)) 
    \fine_inc[6][5]_i_3 
       (.I0(dqs_count_r[0]),
        .I1(dqs_count_r[1]),
        .I2(\dqs_count_r_reg[2]_rep__0_0 ),
        .I3(\dqs_count_r_reg[3]_0 ),
        .O(\fine_inc[6][5]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'h0B000100)) 
    \fine_inc[7][0]_i_1 
       (.I0(wl_state_r__0[1]),
        .I1(\fine_inc_reg[0][1]_i_2_n_0 ),
        .I2(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I3(wl_state_r__0[0]),
        .I4(\gen_final_tap[7].final_val_reg_n_0_[7][0] ),
        .O(\fine_inc[7][0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00EB000000410000)) 
    \fine_inc[7][1]_i_1 
       (.I0(wl_state_r__0[1]),
        .I1(\fine_inc_reg[0][1]_i_2_n_0 ),
        .I2(\fine_inc_reg[0][1]_i_3_n_0 ),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I4(wl_state_r__0[0]),
        .I5(\gen_final_tap[7].final_val_reg_n_0_[7][1] ),
        .O(\fine_inc[7][1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00EB000000410000)) 
    \fine_inc[7][2]_i_1 
       (.I0(wl_state_r__0[1]),
        .I1(\fine_inc_reg[0][2]_i_2_n_0 ),
        .I2(\fine_inc[0][2]_i_3_n_0 ),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I4(wl_state_r__0[0]),
        .I5(\gen_final_tap[7].final_val_reg_n_0_[7][2] ),
        .O(\fine_inc[7][2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h00EB000000410000)) 
    \fine_inc[7][3]_i_1 
       (.I0(wl_state_r__0[1]),
        .I1(\fine_inc_reg[0][3]_i_2_n_0 ),
        .I2(\fine_inc[0][3]_i_3_n_0 ),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I4(wl_state_r__0[0]),
        .I5(\gen_final_tap[7].final_val_reg_n_0_[7][3] ),
        .O(\fine_inc[7][3]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h40004444)) 
    \fine_inc[7][4]_i_1 
       (.I0(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I1(wl_state_r__0[0]),
        .I2(wl_state_r__0[1]),
        .I3(\gen_final_tap[7].final_val_reg_n_0_[7][4] ),
        .I4(\fine_inc[0][4]_i_2_n_0 ),
        .O(\fine_inc[7][4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0020AA0000200000)) 
    \fine_inc[7][5]_i_1 
       (.I0(\fine_inc[0][5]_i_5_n_0 ),
        .I1(\fine_inc[0][5]_i_3_n_0 ),
        .I2(\fine_inc[7][5]_i_3_n_0 ),
        .I3(wl_state_r__0[1]),
        .I4(wr_level_done_r5),
        .I5(wr_level_done_r4),
        .O(\fine_inc[7][5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hA280A280A28080A2)) 
    \fine_inc[7][5]_i_2 
       (.I0(\fine_inc[0][5]_i_6_n_0 ),
        .I1(wl_state_r__0[1]),
        .I2(\gen_final_tap[7].final_val_reg_n_0_[7][5] ),
        .I3(\fine_inc_reg[0][5]_i_7_n_0 ),
        .I4(\fine_inc[0][5]_i_8_n_0 ),
        .I5(\fine_inc_reg[0][5]_i_9_n_0 ),
        .O(\fine_inc[7][5]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair302" *) 
  LUT4 #(
    .INIT(16'h4000)) 
    \fine_inc[7][5]_i_3 
       (.I0(\dqs_count_r_reg[3]_0 ),
        .I1(\dqs_count_r_reg[2]_rep__0_0 ),
        .I2(dqs_count_r[1]),
        .I3(dqs_count_r[0]),
        .O(\fine_inc[7][5]_i_3_n_0 ));
  FDRE \fine_inc_reg[0][0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\fine_inc[0][5]_i_1_n_0 ),
        .D(fine_inc[0]),
        .Q(\fine_inc_reg[0]_5 [0]),
        .R(\fine_inc_reg[6][3]_0 [0]));
  FDRE \fine_inc_reg[0][1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\fine_inc[0][5]_i_1_n_0 ),
        .D(fine_inc[1]),
        .Q(\fine_inc_reg[0]_5 [1]),
        .R(\fine_inc_reg[6][3]_0 [0]));
  MUXF7 \fine_inc_reg[0][1]_i_2 
       (.I0(\fine_inc[0][1]_i_4_n_0 ),
        .I1(\fine_inc[0][1]_i_5_n_0 ),
        .O(\fine_inc_reg[0][1]_i_2_n_0 ),
        .S(dqs_count_r[2]));
  MUXF7 \fine_inc_reg[0][1]_i_3 
       (.I0(\fine_inc[0][1]_i_6_n_0 ),
        .I1(\fine_inc[0][1]_i_7_n_0 ),
        .O(\fine_inc_reg[0][1]_i_3_n_0 ),
        .S(dqs_count_r[2]));
  FDRE \fine_inc_reg[0][2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\fine_inc[0][5]_i_1_n_0 ),
        .D(fine_inc[2]),
        .Q(\fine_inc_reg[0]_5 [2]),
        .R(\fine_inc_reg[6][3]_0 [0]));
  MUXF7 \fine_inc_reg[0][2]_i_2 
       (.I0(\fine_inc[0][2]_i_4_n_0 ),
        .I1(\fine_inc[0][2]_i_5_n_0 ),
        .O(\fine_inc_reg[0][2]_i_2_n_0 ),
        .S(dqs_count_r[2]));
  FDRE \fine_inc_reg[0][3] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\fine_inc[0][5]_i_1_n_0 ),
        .D(fine_inc[3]),
        .Q(\fine_inc_reg[0]_5 [3]),
        .R(\fine_inc_reg[6][3]_0 [1]));
  MUXF7 \fine_inc_reg[0][3]_i_2 
       (.I0(\fine_inc[0][3]_i_4_n_0 ),
        .I1(\fine_inc[0][3]_i_5_n_0 ),
        .O(\fine_inc_reg[0][3]_i_2_n_0 ),
        .S(dqs_count_r[2]));
  FDRE \fine_inc_reg[0][4] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\fine_inc[0][5]_i_1_n_0 ),
        .D(fine_inc[4]),
        .Q(\fine_inc_reg[0]_5 [4]),
        .R(\fine_inc_reg[6][3]_0 [1]));
  FDRE \fine_inc_reg[0][5] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\fine_inc[0][5]_i_1_n_0 ),
        .D(fine_inc[5]),
        .Q(\fine_inc_reg[0]_5 [5]),
        .R(\fine_inc_reg[6][3]_0 [1]));
  MUXF7 \fine_inc_reg[0][5]_i_7 
       (.I0(\fine_inc[0][5]_i_10_n_0 ),
        .I1(\fine_inc[0][5]_i_11_n_0 ),
        .O(\fine_inc_reg[0][5]_i_7_n_0 ),
        .S(dqs_count_r[2]));
  MUXF7 \fine_inc_reg[0][5]_i_9 
       (.I0(\fine_inc[0][5]_i_12_n_0 ),
        .I1(\fine_inc[0][5]_i_13_n_0 ),
        .O(\fine_inc_reg[0][5]_i_9_n_0 ),
        .S(dqs_count_r[2]));
  FDRE \fine_inc_reg[1][0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\fine_inc[1][5]_i_1_n_0 ),
        .D(\fine_inc[1][0]_i_1_n_0 ),
        .Q(\fine_inc_reg[1]_6 [0]),
        .R(\fine_inc_reg[6][3]_0 [0]));
  FDRE \fine_inc_reg[1][1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\fine_inc[1][5]_i_1_n_0 ),
        .D(\fine_inc[1][1]_i_1_n_0 ),
        .Q(\fine_inc_reg[1]_6 [1]),
        .R(\fine_inc_reg[6][3]_0 [0]));
  FDRE \fine_inc_reg[1][2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\fine_inc[1][5]_i_1_n_0 ),
        .D(\fine_inc[1][2]_i_1_n_0 ),
        .Q(\fine_inc_reg[1]_6 [2]),
        .R(\fine_inc_reg[6][3]_0 [0]));
  FDRE \fine_inc_reg[1][3] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\fine_inc[1][5]_i_1_n_0 ),
        .D(\fine_inc[1][3]_i_1_n_0 ),
        .Q(\fine_inc_reg[1]_6 [3]),
        .R(\fine_inc_reg[6][3]_0 [1]));
  FDRE \fine_inc_reg[1][4] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\fine_inc[1][5]_i_1_n_0 ),
        .D(\fine_inc[1][4]_i_1_n_0 ),
        .Q(\fine_inc_reg[1]_6 [4]),
        .R(\fine_inc_reg[6][3]_0 [1]));
  FDRE \fine_inc_reg[1][5] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\fine_inc[1][5]_i_1_n_0 ),
        .D(\fine_inc[1][5]_i_2_n_0 ),
        .Q(\fine_inc_reg[1]_6 [5]),
        .R(\fine_inc_reg[6][3]_0 [1]));
  FDRE \fine_inc_reg[2][0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\fine_inc[2][5]_i_1_n_0 ),
        .D(\fine_inc[2][0]_i_1_n_0 ),
        .Q(\fine_inc_reg[2]_7 [0]),
        .R(\fine_inc_reg[6][3]_0 [0]));
  FDRE \fine_inc_reg[2][1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\fine_inc[2][5]_i_1_n_0 ),
        .D(\fine_inc[2][1]_i_1_n_0 ),
        .Q(\fine_inc_reg[2]_7 [1]),
        .R(\fine_inc_reg[6][3]_0 [0]));
  FDRE \fine_inc_reg[2][2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\fine_inc[2][5]_i_1_n_0 ),
        .D(\fine_inc[2][2]_i_1_n_0 ),
        .Q(\fine_inc_reg[2]_7 [2]),
        .R(\fine_inc_reg[6][3]_0 [0]));
  FDRE \fine_inc_reg[2][3] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\fine_inc[2][5]_i_1_n_0 ),
        .D(\fine_inc[2][3]_i_1_n_0 ),
        .Q(\fine_inc_reg[2]_7 [3]),
        .R(\fine_inc_reg[6][3]_0 [1]));
  FDRE \fine_inc_reg[2][4] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\fine_inc[2][5]_i_1_n_0 ),
        .D(\fine_inc[2][4]_i_1_n_0 ),
        .Q(\fine_inc_reg[2]_7 [4]),
        .R(\fine_inc_reg[6][3]_0 [1]));
  FDRE \fine_inc_reg[2][5] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\fine_inc[2][5]_i_1_n_0 ),
        .D(\fine_inc[2][5]_i_2_n_0 ),
        .Q(\fine_inc_reg[2]_7 [5]),
        .R(\fine_inc_reg[6][3]_0 [1]));
  FDRE \fine_inc_reg[3][0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\fine_inc[3][5]_i_1_n_0 ),
        .D(\fine_inc[3][0]_i_1_n_0 ),
        .Q(\fine_inc_reg[3]_8 [0]),
        .R(\fine_inc_reg[6][3]_0 [0]));
  FDRE \fine_inc_reg[3][1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\fine_inc[3][5]_i_1_n_0 ),
        .D(\fine_inc[3][1]_i_1_n_0 ),
        .Q(\fine_inc_reg[3]_8 [1]),
        .R(\fine_inc_reg[6][3]_0 [0]));
  FDRE \fine_inc_reg[3][2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\fine_inc[3][5]_i_1_n_0 ),
        .D(\fine_inc[3][2]_i_1_n_0 ),
        .Q(\fine_inc_reg[3]_8 [2]),
        .R(\fine_inc_reg[6][3]_0 [0]));
  FDRE \fine_inc_reg[3][3] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\fine_inc[3][5]_i_1_n_0 ),
        .D(\fine_inc[3][3]_i_1_n_0 ),
        .Q(\fine_inc_reg[3]_8 [3]),
        .R(\fine_inc_reg[6][3]_0 [1]));
  FDRE \fine_inc_reg[3][4] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\fine_inc[3][5]_i_1_n_0 ),
        .D(\fine_inc[3][4]_i_1_n_0 ),
        .Q(\fine_inc_reg[3]_8 [4]),
        .R(\fine_inc_reg[6][3]_0 [1]));
  FDRE \fine_inc_reg[3][5] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\fine_inc[3][5]_i_1_n_0 ),
        .D(\fine_inc[3][5]_i_2_n_0 ),
        .Q(\fine_inc_reg[3]_8 [5]),
        .R(\fine_inc_reg[6][3]_0 [1]));
  FDRE \fine_inc_reg[4][0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\fine_inc[4][5]_i_1_n_0 ),
        .D(\fine_inc[4][0]_i_1_n_0 ),
        .Q(\fine_inc_reg[4]_9 [0]),
        .R(\fine_inc_reg[6][3]_0 [0]));
  FDRE \fine_inc_reg[4][1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\fine_inc[4][5]_i_1_n_0 ),
        .D(\fine_inc[4][1]_i_1_n_0 ),
        .Q(\fine_inc_reg[4]_9 [1]),
        .R(\fine_inc_reg[6][3]_0 [0]));
  FDRE \fine_inc_reg[4][2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\fine_inc[4][5]_i_1_n_0 ),
        .D(\fine_inc[4][2]_i_1_n_0 ),
        .Q(\fine_inc_reg[4]_9 [2]),
        .R(\fine_inc_reg[6][3]_0 [0]));
  FDRE \fine_inc_reg[4][3] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\fine_inc[4][5]_i_1_n_0 ),
        .D(\fine_inc[4][3]_i_1_n_0 ),
        .Q(\fine_inc_reg[4]_9 [3]),
        .R(\fine_inc_reg[6][3]_0 [1]));
  FDRE \fine_inc_reg[4][4] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\fine_inc[4][5]_i_1_n_0 ),
        .D(\fine_inc[4][4]_i_1_n_0 ),
        .Q(\fine_inc_reg[4]_9 [4]),
        .R(\fine_inc_reg[6][3]_0 [1]));
  FDRE \fine_inc_reg[4][5] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\fine_inc[4][5]_i_1_n_0 ),
        .D(\fine_inc[4][5]_i_2_n_0 ),
        .Q(\fine_inc_reg[4]_9 [5]),
        .R(\fine_inc_reg[6][3]_0 [1]));
  FDRE \fine_inc_reg[5][0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\fine_inc[5][5]_i_1_n_0 ),
        .D(\fine_inc[5][0]_i_1_n_0 ),
        .Q(\fine_inc_reg[5]_10 [0]),
        .R(\fine_inc_reg[6][3]_0 [0]));
  FDRE \fine_inc_reg[5][1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\fine_inc[5][5]_i_1_n_0 ),
        .D(\fine_inc[5][1]_i_1_n_0 ),
        .Q(\fine_inc_reg[5]_10 [1]),
        .R(\fine_inc_reg[6][3]_0 [0]));
  FDRE \fine_inc_reg[5][2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\fine_inc[5][5]_i_1_n_0 ),
        .D(\fine_inc[5][2]_i_1_n_0 ),
        .Q(\fine_inc_reg[5]_10 [2]),
        .R(\fine_inc_reg[6][3]_0 [0]));
  FDRE \fine_inc_reg[5][3] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\fine_inc[5][5]_i_1_n_0 ),
        .D(\fine_inc[5][3]_i_1_n_0 ),
        .Q(\fine_inc_reg[5]_10 [3]),
        .R(\fine_inc_reg[6][3]_0 [1]));
  FDRE \fine_inc_reg[5][4] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\fine_inc[5][5]_i_1_n_0 ),
        .D(\fine_inc[5][4]_i_1_n_0 ),
        .Q(\fine_inc_reg[5]_10 [4]),
        .R(\fine_inc_reg[6][3]_0 [1]));
  FDRE \fine_inc_reg[5][5] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\fine_inc[5][5]_i_1_n_0 ),
        .D(\fine_inc[5][5]_i_2_n_0 ),
        .Q(\fine_inc_reg[5]_10 [5]),
        .R(\fine_inc_reg[6][3]_0 [1]));
  FDRE \fine_inc_reg[6][0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\fine_inc[6][5]_i_1_n_0 ),
        .D(\fine_inc[6][0]_i_1_n_0 ),
        .Q(\fine_inc_reg[6]_11 [0]),
        .R(\fine_inc_reg[6][3]_0 [0]));
  FDRE \fine_inc_reg[6][1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\fine_inc[6][5]_i_1_n_0 ),
        .D(\fine_inc[6][1]_i_1_n_0 ),
        .Q(\fine_inc_reg[6]_11 [1]),
        .R(\fine_inc_reg[6][3]_0 [0]));
  FDRE \fine_inc_reg[6][2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\fine_inc[6][5]_i_1_n_0 ),
        .D(\fine_inc[6][2]_i_1_n_0 ),
        .Q(\fine_inc_reg[6]_11 [2]),
        .R(\fine_inc_reg[6][3]_0 [0]));
  FDRE \fine_inc_reg[6][3] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\fine_inc[6][5]_i_1_n_0 ),
        .D(\fine_inc[6][3]_i_1_n_0 ),
        .Q(\fine_inc_reg[6]_11 [3]),
        .R(\fine_inc_reg[6][3]_0 [1]));
  FDRE \fine_inc_reg[6][4] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\fine_inc[6][5]_i_1_n_0 ),
        .D(\fine_inc[6][4]_i_1_n_0 ),
        .Q(\fine_inc_reg[6]_11 [4]),
        .R(\fine_inc_reg[6][3]_0 [1]));
  FDRE \fine_inc_reg[6][5] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\fine_inc[6][5]_i_1_n_0 ),
        .D(\fine_inc[6][5]_i_2_n_0 ),
        .Q(\fine_inc_reg[6]_11 [5]),
        .R(\fine_inc_reg[6][3]_0 [1]));
  FDRE \fine_inc_reg[7][0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\fine_inc[7][5]_i_1_n_0 ),
        .D(\fine_inc[7][0]_i_1_n_0 ),
        .Q(\fine_inc_reg[7]_12 [0]),
        .R(\fine_inc_reg[6][3]_0 [0]));
  FDRE \fine_inc_reg[7][1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\fine_inc[7][5]_i_1_n_0 ),
        .D(\fine_inc[7][1]_i_1_n_0 ),
        .Q(\fine_inc_reg[7]_12 [1]),
        .R(\fine_inc_reg[6][3]_0 [0]));
  FDRE \fine_inc_reg[7][2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\fine_inc[7][5]_i_1_n_0 ),
        .D(\fine_inc[7][2]_i_1_n_0 ),
        .Q(\fine_inc_reg[7]_12 [2]),
        .R(\fine_inc_reg[6][3]_0 [0]));
  FDRE \fine_inc_reg[7][3] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\fine_inc[7][5]_i_1_n_0 ),
        .D(\fine_inc[7][3]_i_1_n_0 ),
        .Q(\fine_inc_reg[7]_12 [3]),
        .R(\fine_inc_reg[6][3]_0 [1]));
  FDRE \fine_inc_reg[7][4] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\fine_inc[7][5]_i_1_n_0 ),
        .D(\fine_inc[7][4]_i_1_n_0 ),
        .Q(\fine_inc_reg[7]_12 [4]),
        .R(\fine_inc_reg[6][3]_0 [1]));
  FDRE \fine_inc_reg[7][5] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\fine_inc[7][5]_i_1_n_0 ),
        .D(\fine_inc[7][5]_i_2_n_0 ),
        .Q(\fine_inc_reg[7]_12 [5]),
        .R(\fine_inc_reg[6][3]_0 [1]));
  LUT6 #(
    .INIT(64'h2222222220222222)) 
    flag_ck_negedge_i_1
       (.I0(\stable_cnt[3]_i_5_n_0 ),
        .I1(flag_ck_negedge_i_2_n_0),
        .I2(wl_state_r__0[2]),
        .I3(wl_state_r__0[1]),
        .I4(\fine_inc[0][5]_i_6_n_0 ),
        .I5(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .O(flag_ck_negedge_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair305" *) 
  LUT5 #(
    .INIT(32'hABABABAF)) 
    flag_ck_negedge_i_2
       (.I0(wr_level_done_r_reg_n_0),
        .I1(flag_ck_negedge_reg_n_0),
        .I2(flag_ck_negedge09_out),
        .I3(\stable_cnt_reg_n_0_[0] ),
        .I4(\FSM_sequential_wl_state_r[3]_i_14_n_0 ),
        .O(flag_ck_negedge_i_2_n_0));
  LUT6 #(
    .INIT(64'h4000FFFF40004000)) 
    flag_ck_negedge_i_3
       (.I0(wl_state_r__0[2]),
        .I1(\rank_cnt_r[1]_i_2_n_0 ),
        .I2(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I3(wl_state_r__0[0]),
        .I4(flag_ck_negedge_i_4_n_0),
        .I5(\rd_data_edge_detect_r_reg[7]_i_9_n_0 ),
        .O(flag_ck_negedge09_out));
  LUT6 #(
    .INIT(64'h0000000000010000)) 
    flag_ck_negedge_i_4
       (.I0(\stable_cnt_reg_n_0_[1] ),
        .I1(\stable_cnt_reg_n_0_[0] ),
        .I2(\stable_cnt_reg_n_0_[3] ),
        .I3(\stable_cnt_reg_n_0_[2] ),
        .I4(flag_ck_negedge_i_5_n_0),
        .I5(flag_ck_negedge_i_6_n_0),
        .O(flag_ck_negedge_i_4_n_0));
  (* SOFT_HLUTNM = "soft_lutpair319" *) 
  LUT5 #(
    .INIT(32'hFFFFFEFF)) 
    flag_ck_negedge_i_5
       (.I0(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I2(wl_state_r__0[2]),
        .I3(wl_state_r__0[0]),
        .I4(wl_state_r__0[1]),
        .O(flag_ck_negedge_i_5_n_0));
  (* SOFT_HLUTNM = "soft_lutpair319" *) 
  LUT5 #(
    .INIT(32'h00000401)) 
    flag_ck_negedge_i_6
       (.I0(wl_state_r__0[1]),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I2(wl_state_r__0[2]),
        .I3(wl_state_r__0[0]),
        .I4(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .O(flag_ck_negedge_i_6_n_0));
  FDRE flag_ck_negedge_reg
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(flag_ck_negedge_i_1_n_0),
        .Q(flag_ck_negedge_reg_n_0),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hAAAAA8AAAAAAAAAA)) 
    flag_init_i_1
       (.I0(flag_init),
        .I1(\wl_state_r1_reg_n_0_[0] ),
        .I2(\wl_state_r1_reg_n_0_[3] ),
        .I3(\wl_state_r1_reg_n_0_[2] ),
        .I4(\wl_state_r1_reg_n_0_[4] ),
        .I5(flag_init_i_2_n_0),
        .O(flag_init_i_1_n_0));
  (* SOFT_HLUTNM = "soft_lutpair333" *) 
  LUT5 #(
    .INIT(32'h00000040)) 
    flag_init_i_2
       (.I0(wl_state_r__0[0]),
        .I1(wl_state_r__0[1]),
        .I2(wl_state_r__0[2]),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I4(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .O(flag_init_i_2_n_0));
  FDSE flag_init_reg
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(flag_init_i_1_n_0),
        .Q(flag_init),
        .S(\wl_dqs_tap_count_r_reg[0][5][5]_0 ));
  LUT2 #(
    .INIT(4'h2)) 
    \gen_final_tap[0].final_val[0][5]_i_1 
       (.I0(wr_level_done_r2),
        .I1(wr_level_done_r3),
        .O(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ));
  FDRE \gen_final_tap[0].final_val_reg[0][0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\smallest_reg[0]_13 [0]),
        .Q(\gen_final_tap[0].final_val_reg_n_0_[0][0] ),
        .R(\corse_dec_reg[7][0]_0 [1]));
  FDRE \gen_final_tap[0].final_val_reg[0][1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\smallest_reg[0]_13 [1]),
        .Q(\gen_final_tap[0].final_val_reg_n_0_[0][1] ),
        .R(\corse_dec_reg[7][0]_0 [1]));
  FDRE \gen_final_tap[0].final_val_reg[0][2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\smallest_reg[0]_13 [2]),
        .Q(\gen_final_tap[0].final_val_reg_n_0_[0][2] ),
        .R(\corse_dec_reg[7][0]_0 [1]));
  FDRE \gen_final_tap[0].final_val_reg[0][3] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\smallest_reg[0]_13 [3]),
        .Q(\gen_final_tap[0].final_val_reg_n_0_[0][3] ),
        .R(\corse_dec_reg[7][0]_0 [1]));
  FDRE \gen_final_tap[0].final_val_reg[0][4] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\smallest_reg[0]_13 [4]),
        .Q(\gen_final_tap[0].final_val_reg_n_0_[0][4] ),
        .R(\corse_dec_reg[7][0]_0 [1]));
  FDRE \gen_final_tap[0].final_val_reg[0][5] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\smallest_reg[0]_13 [5]),
        .Q(\gen_final_tap[0].final_val_reg_n_0_[0][5] ),
        .R(\corse_dec_reg[7][0]_0 [1]));
  FDRE \gen_final_tap[1].final_val_reg[1][0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\smallest_reg[1]_14 [0]),
        .Q(\gen_final_tap[1].final_val_reg_n_0_[1][0] ),
        .R(\corse_dec_reg[7][0]_0 [1]));
  FDRE \gen_final_tap[1].final_val_reg[1][1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\smallest_reg[1]_14 [1]),
        .Q(\gen_final_tap[1].final_val_reg_n_0_[1][1] ),
        .R(\corse_dec_reg[7][0]_0 [1]));
  FDRE \gen_final_tap[1].final_val_reg[1][2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\smallest_reg[1]_14 [2]),
        .Q(\gen_final_tap[1].final_val_reg_n_0_[1][2] ),
        .R(\corse_dec_reg[7][0]_0 [1]));
  FDRE \gen_final_tap[1].final_val_reg[1][3] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\smallest_reg[1]_14 [3]),
        .Q(\gen_final_tap[1].final_val_reg_n_0_[1][3] ),
        .R(\corse_dec_reg[7][0]_0 [1]));
  FDRE \gen_final_tap[1].final_val_reg[1][4] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\smallest_reg[1]_14 [4]),
        .Q(\gen_final_tap[1].final_val_reg_n_0_[1][4] ),
        .R(\corse_dec_reg[7][0]_0 [1]));
  FDRE \gen_final_tap[1].final_val_reg[1][5] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\smallest_reg[1]_14 [5]),
        .Q(\gen_final_tap[1].final_val_reg_n_0_[1][5] ),
        .R(\corse_dec_reg[7][0]_0 [1]));
  FDRE \gen_final_tap[2].final_val_reg[2][0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\smallest_reg[2]_15 [0]),
        .Q(\gen_final_tap[2].final_val_reg_n_0_[2][0] ),
        .R(\wl_dqs_tap_count_r_reg[0][5][5]_0 ));
  FDRE \gen_final_tap[2].final_val_reg[2][1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\smallest_reg[2]_15 [1]),
        .Q(\gen_final_tap[2].final_val_reg_n_0_[2][1] ),
        .R(\wl_dqs_tap_count_r_reg[0][5][5]_0 ));
  FDRE \gen_final_tap[2].final_val_reg[2][2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\smallest_reg[2]_15 [2]),
        .Q(\gen_final_tap[2].final_val_reg_n_0_[2][2] ),
        .R(\wl_dqs_tap_count_r_reg[0][5][5]_0 ));
  FDRE \gen_final_tap[2].final_val_reg[2][3] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\smallest_reg[2]_15 [3]),
        .Q(\gen_final_tap[2].final_val_reg_n_0_[2][3] ),
        .R(\wl_dqs_tap_count_r_reg[0][5][5]_0 ));
  FDRE \gen_final_tap[2].final_val_reg[2][4] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\smallest_reg[2]_15 [4]),
        .Q(\gen_final_tap[2].final_val_reg_n_0_[2][4] ),
        .R(\wl_dqs_tap_count_r_reg[0][5][5]_0 ));
  FDRE \gen_final_tap[2].final_val_reg[2][5] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\smallest_reg[2]_15 [5]),
        .Q(\gen_final_tap[2].final_val_reg_n_0_[2][5] ),
        .R(\wl_dqs_tap_count_r_reg[0][5][5]_0 ));
  FDRE \gen_final_tap[3].final_val_reg[3][0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\smallest_reg[3]_16 [0]),
        .Q(\gen_final_tap[3].final_val_reg_n_0_[3][0] ),
        .R(\corse_dec_reg[7][0]_0 [1]));
  FDRE \gen_final_tap[3].final_val_reg[3][1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\smallest_reg[3]_16 [1]),
        .Q(\gen_final_tap[3].final_val_reg_n_0_[3][1] ),
        .R(\corse_dec_reg[7][0]_0 [1]));
  FDRE \gen_final_tap[3].final_val_reg[3][2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\smallest_reg[3]_16 [2]),
        .Q(\gen_final_tap[3].final_val_reg_n_0_[3][2] ),
        .R(\corse_dec_reg[7][0]_0 [1]));
  FDRE \gen_final_tap[3].final_val_reg[3][3] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\smallest_reg[3]_16 [3]),
        .Q(\gen_final_tap[3].final_val_reg_n_0_[3][3] ),
        .R(\corse_dec_reg[7][0]_0 [1]));
  FDRE \gen_final_tap[3].final_val_reg[3][4] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\smallest_reg[3]_16 [4]),
        .Q(\gen_final_tap[3].final_val_reg_n_0_[3][4] ),
        .R(\corse_dec_reg[7][0]_0 [1]));
  FDRE \gen_final_tap[3].final_val_reg[3][5] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\smallest_reg[3]_16 [5]),
        .Q(\gen_final_tap[3].final_val_reg_n_0_[3][5] ),
        .R(\corse_dec_reg[7][0]_0 [1]));
  FDRE \gen_final_tap[4].final_val_reg[4][0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\smallest_reg[4]_17 [0]),
        .Q(\gen_final_tap[4].final_val_reg_n_0_[4][0] ),
        .R(\wl_dqs_tap_count_r_reg[0][5][5]_0 ));
  FDRE \gen_final_tap[4].final_val_reg[4][1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\smallest_reg[4]_17 [1]),
        .Q(\gen_final_tap[4].final_val_reg_n_0_[4][1] ),
        .R(\wl_dqs_tap_count_r_reg[0][5][5]_0 ));
  FDRE \gen_final_tap[4].final_val_reg[4][2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\smallest_reg[4]_17 [2]),
        .Q(\gen_final_tap[4].final_val_reg_n_0_[4][2] ),
        .R(\wl_dqs_tap_count_r_reg[0][5][5]_0 ));
  FDRE \gen_final_tap[4].final_val_reg[4][3] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\smallest_reg[4]_17 [3]),
        .Q(\gen_final_tap[4].final_val_reg_n_0_[4][3] ),
        .R(\wl_dqs_tap_count_r_reg[0][5][5]_0 ));
  FDRE \gen_final_tap[4].final_val_reg[4][4] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\smallest_reg[4]_17 [4]),
        .Q(\gen_final_tap[4].final_val_reg_n_0_[4][4] ),
        .R(\wl_dqs_tap_count_r_reg[0][5][5]_0 ));
  FDRE \gen_final_tap[4].final_val_reg[4][5] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\smallest_reg[4]_17 [5]),
        .Q(\gen_final_tap[4].final_val_reg_n_0_[4][5] ),
        .R(\wl_dqs_tap_count_r_reg[0][5][5]_0 ));
  FDRE \gen_final_tap[5].final_val_reg[5][0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\smallest_reg[5]_18 [0]),
        .Q(\gen_final_tap[5].final_val_reg_n_0_[5][0] ),
        .R(\corse_inc_reg[6][2]_0 [1]));
  FDRE \gen_final_tap[5].final_val_reg[5][1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\smallest_reg[5]_18 [1]),
        .Q(\gen_final_tap[5].final_val_reg_n_0_[5][1] ),
        .R(\corse_dec_reg[7][0]_0 [1]));
  FDRE \gen_final_tap[5].final_val_reg[5][2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\smallest_reg[5]_18 [2]),
        .Q(\gen_final_tap[5].final_val_reg_n_0_[5][2] ),
        .R(\corse_dec_reg[7][0]_0 [1]));
  FDRE \gen_final_tap[5].final_val_reg[5][3] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\smallest_reg[5]_18 [3]),
        .Q(\gen_final_tap[5].final_val_reg_n_0_[5][3] ),
        .R(\corse_dec_reg[7][0]_0 [1]));
  FDRE \gen_final_tap[5].final_val_reg[5][4] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\smallest_reg[5]_18 [4]),
        .Q(\gen_final_tap[5].final_val_reg_n_0_[5][4] ),
        .R(\corse_dec_reg[7][0]_0 [1]));
  FDRE \gen_final_tap[5].final_val_reg[5][5] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\smallest_reg[5]_18 [5]),
        .Q(\gen_final_tap[5].final_val_reg_n_0_[5][5] ),
        .R(\corse_dec_reg[7][0]_0 [1]));
  FDRE \gen_final_tap[6].final_val_reg[6][0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\smallest_reg[6]_19 [0]),
        .Q(\gen_final_tap[6].final_val_reg_n_0_[6][0] ),
        .R(\wl_dqs_tap_count_r_reg[0][5][5]_0 ));
  FDRE \gen_final_tap[6].final_val_reg[6][1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\smallest_reg[6]_19 [1]),
        .Q(\gen_final_tap[6].final_val_reg_n_0_[6][1] ),
        .R(\wl_dqs_tap_count_r_reg[0][5][5]_0 ));
  FDRE \gen_final_tap[6].final_val_reg[6][2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\smallest_reg[6]_19 [2]),
        .Q(\gen_final_tap[6].final_val_reg_n_0_[6][2] ),
        .R(\wl_dqs_tap_count_r_reg[0][5][5]_0 ));
  FDRE \gen_final_tap[6].final_val_reg[6][3] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\smallest_reg[6]_19 [3]),
        .Q(\gen_final_tap[6].final_val_reg_n_0_[6][3] ),
        .R(\wl_dqs_tap_count_r_reg[0][5][5]_0 ));
  FDRE \gen_final_tap[6].final_val_reg[6][4] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\smallest_reg[6]_19 [4]),
        .Q(\gen_final_tap[6].final_val_reg_n_0_[6][4] ),
        .R(\wl_dqs_tap_count_r_reg[0][5][5]_0 ));
  FDRE \gen_final_tap[6].final_val_reg[6][5] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\smallest_reg[6]_19 [5]),
        .Q(\gen_final_tap[6].final_val_reg_n_0_[6][5] ),
        .R(\wl_dqs_tap_count_r_reg[0][5][5]_0 ));
  FDRE \gen_final_tap[7].final_val_reg[7][0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\smallest_reg[7]_20 [0]),
        .Q(\gen_final_tap[7].final_val_reg_n_0_[7][0] ),
        .R(\corse_inc_reg[6][2]_0 [1]));
  FDRE \gen_final_tap[7].final_val_reg[7][1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\smallest_reg[7]_20 [1]),
        .Q(\gen_final_tap[7].final_val_reg_n_0_[7][1] ),
        .R(\corse_inc_reg[6][2]_0 [1]));
  FDRE \gen_final_tap[7].final_val_reg[7][2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\smallest_reg[7]_20 [2]),
        .Q(\gen_final_tap[7].final_val_reg_n_0_[7][2] ),
        .R(\corse_inc_reg[6][2]_0 [1]));
  FDRE \gen_final_tap[7].final_val_reg[7][3] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\smallest_reg[7]_20 [3]),
        .Q(\gen_final_tap[7].final_val_reg_n_0_[7][3] ),
        .R(\corse_inc_reg[6][2]_0 [1]));
  FDRE \gen_final_tap[7].final_val_reg[7][4] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\smallest_reg[7]_20 [4]),
        .Q(\gen_final_tap[7].final_val_reg_n_0_[7][4] ),
        .R(\corse_inc_reg[6][2]_0 [1]));
  FDRE \gen_final_tap[7].final_val_reg[7][5] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\gen_final_tap[0].final_val[0][5]_i_1_n_0 ),
        .D(\smallest_reg[7]_20 [5]),
        .Q(\gen_final_tap[7].final_val_reg_n_0_[7][5] ),
        .R(\corse_inc_reg[6][2]_0 [1]));
  FDRE \gen_rd[0].rd_data_rise_wl_r_reg[0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(p_0_in__0),
        .Q(\gen_rd[0].rd_data_rise_wl_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \gen_rd[1].rd_data_rise_wl_r_reg[1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\p_0_out_inferred__19/gen_rd[1].rd_data_rise_wl_r[1]_i_1_n_0 ),
        .Q(\gen_rd[1].rd_data_rise_wl_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \gen_rd[2].rd_data_rise_wl_r_reg[2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\p_0_out_inferred__20/gen_rd[2].rd_data_rise_wl_r[2]_i_1_n_0 ),
        .Q(\gen_rd[2].rd_data_rise_wl_r_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \gen_rd[3].rd_data_rise_wl_r_reg[3] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\p_0_out_inferred__21/gen_rd[3].rd_data_rise_wl_r[3]_i_1_n_0 ),
        .Q(\gen_rd[3].rd_data_rise_wl_r_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \gen_rd[4].rd_data_rise_wl_r_reg[4] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\p_0_out_inferred__22/gen_rd[4].rd_data_rise_wl_r[4]_i_1_n_0 ),
        .Q(\gen_rd[4].rd_data_rise_wl_r_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \gen_rd[5].rd_data_rise_wl_r_reg[5] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\p_0_out_inferred__23/gen_rd[5].rd_data_rise_wl_r[5]_i_1_n_0 ),
        .Q(\gen_rd[5].rd_data_rise_wl_r_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \gen_rd[6].rd_data_rise_wl_r_reg[6] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\p_0_out_inferred__24/gen_rd[6].rd_data_rise_wl_r[6]_i_1_n_0 ),
        .Q(\gen_rd[6].rd_data_rise_wl_r_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \gen_rd[7].rd_data_rise_wl_r_reg[7] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\p_0_out_inferred__25/gen_rd[7].rd_data_rise_wl_r[7]_i_1_n_0 ),
        .Q(\gen_rd[7].rd_data_rise_wl_r_reg_n_0_[7] ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \incdec_wait_cnt[0]_i_1 
       (.I0(incdec_wait_cnt_reg[0]),
        .O(p_0_in__2[0]));
  (* SOFT_HLUTNM = "soft_lutpair384" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \incdec_wait_cnt[1]_i_1 
       (.I0(incdec_wait_cnt_reg[0]),
        .I1(incdec_wait_cnt_reg[1]),
        .O(p_0_in__2[1]));
  (* SOFT_HLUTNM = "soft_lutpair384" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \incdec_wait_cnt[2]_i_1 
       (.I0(incdec_wait_cnt_reg[2]),
        .I1(incdec_wait_cnt_reg[1]),
        .I2(incdec_wait_cnt_reg[0]),
        .O(p_0_in__2[2]));
  LUT6 #(
    .INIT(64'hEFFFFFFEFFFFFEFF)) 
    \incdec_wait_cnt[3]_i_1 
       (.I0(\single_rank.done_dqs_dec_reg_0 ),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I2(wl_state_r__0[2]),
        .I3(wl_state_r__0[0]),
        .I4(wl_state_r__0[1]),
        .I5(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .O(\incdec_wait_cnt[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair347" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \incdec_wait_cnt[3]_i_2 
       (.I0(incdec_wait_cnt_reg[3]),
        .I1(incdec_wait_cnt_reg[0]),
        .I2(incdec_wait_cnt_reg[1]),
        .I3(incdec_wait_cnt_reg[2]),
        .O(p_0_in__2[3]));
  FDRE \incdec_wait_cnt_reg[0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(p_0_in__2[0]),
        .Q(incdec_wait_cnt_reg[0]),
        .R(\incdec_wait_cnt[3]_i_1_n_0 ));
  FDRE \incdec_wait_cnt_reg[1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(p_0_in__2[1]),
        .Q(incdec_wait_cnt_reg[1]),
        .R(\incdec_wait_cnt[3]_i_1_n_0 ));
  FDRE \incdec_wait_cnt_reg[2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(p_0_in__2[2]),
        .Q(incdec_wait_cnt_reg[2]),
        .R(\incdec_wait_cnt[3]_i_1_n_0 ));
  FDRE \incdec_wait_cnt_reg[3] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(p_0_in__2[3]),
        .Q(incdec_wait_cnt_reg[3]),
        .R(\incdec_wait_cnt[3]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hEEEFEEE0)) 
    inhibit_edge_detect_r_i_1
       (.I0(wl_state_r__0[2]),
        .I1(inhibit_edge_detect_r_i_2_n_0),
        .I2(inhibit_edge_detect_r_i_3_n_0),
        .I3(inhibit_edge_detect_r_i_4_n_0),
        .I4(inhibit_edge_detect_r_reg_n_0),
        .O(inhibit_edge_detect_r_i_1_n_0));
  LUT6 #(
    .INIT(64'h00E2FFE2FFE2FFE2)) 
    inhibit_edge_detect_r_i_2
       (.I0(\rd_data_edge_detect_r_reg[7]_i_9_n_0 ),
        .I1(wl_state_r__0[1]),
        .I2(wrlvl_byte_redo),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I4(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I5(\FSM_sequential_wl_state_r[4]_i_17_n_0 ),
        .O(inhibit_edge_detect_r_i_2_n_0));
  LUT6 #(
    .INIT(64'h0101000008FF0000)) 
    inhibit_edge_detect_r_i_3
       (.I0(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I1(wl_state_r__0[2]),
        .I2(wl_state_r__0[0]),
        .I3(\FSM_sequential_wl_state_r[0]_i_7_n_0 ),
        .I4(wl_state_r__0[1]),
        .I5(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .O(inhibit_edge_detect_r_i_3_n_0));
  LUT6 #(
    .INIT(64'h0020022000200020)) 
    inhibit_edge_detect_r_i_4
       (.I0(inhibit_edge_detect_r_i_5_n_0),
        .I1(wl_state_r__0[2]),
        .I2(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I3(wl_state_r__0[0]),
        .I4(\FSM_sequential_wl_state_r[3]_i_14_n_0 ),
        .I5(wl_sm_start),
        .O(inhibit_edge_detect_r_i_4_n_0));
  (* SOFT_HLUTNM = "soft_lutpair338" *) 
  LUT2 #(
    .INIT(4'h2)) 
    inhibit_edge_detect_r_i_5
       (.I0(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I1(wl_state_r__0[1]),
        .O(inhibit_edge_detect_r_i_5_n_0));
  FDSE inhibit_edge_detect_r_reg
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(inhibit_edge_detect_r_i_1_n_0),
        .Q(inhibit_edge_detect_r_reg_n_0),
        .S(\corse_inc_reg[6][2]_0 [0]));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \p_0_out_inferred__18/gen_rd[0].rd_data_rise_wl_r[0]_i_1 
       (.I0(\gen_rd[0].rd_data_rise_wl_r_reg[0]_0 ),
        .I1(\gen_rd[0].rd_data_rise_wl_r_reg[0]_1 ),
        .I2(\gen_rd[0].rd_data_rise_wl_r_reg[0]_2 ),
        .I3(\gen_rd[0].rd_data_rise_wl_r_reg[0]_3 ),
        .I4(\p_0_out_inferred__18/gen_rd[0].rd_data_rise_wl_r[0]_i_2_n_0 ),
        .O(p_0_in__0));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \p_0_out_inferred__18/gen_rd[0].rd_data_rise_wl_r[0]_i_2 
       (.I0(\gen_rd[0].rd_data_rise_wl_r_reg[0]_4 ),
        .I1(\gen_rd[0].rd_data_rise_wl_r_reg[0]_5 ),
        .I2(\gen_rd[0].rd_data_rise_wl_r_reg[0]_6 ),
        .I3(\gen_rd[0].rd_data_rise_wl_r_reg[0]_7 ),
        .O(\p_0_out_inferred__18/gen_rd[0].rd_data_rise_wl_r[0]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \p_0_out_inferred__19/gen_rd[1].rd_data_rise_wl_r[1]_i_1 
       (.I0(\gen_rd[1].rd_data_rise_wl_r_reg[1]_0 ),
        .I1(\gen_rd[1].rd_data_rise_wl_r_reg[1]_1 ),
        .I2(\gen_rd[1].rd_data_rise_wl_r_reg[1]_2 ),
        .I3(\gen_rd[1].rd_data_rise_wl_r_reg[1]_3 ),
        .I4(\p_0_out_inferred__19/gen_rd[1].rd_data_rise_wl_r[1]_i_2_n_0 ),
        .O(\p_0_out_inferred__19/gen_rd[1].rd_data_rise_wl_r[1]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \p_0_out_inferred__19/gen_rd[1].rd_data_rise_wl_r[1]_i_2 
       (.I0(\gen_rd[1].rd_data_rise_wl_r_reg[1]_4 ),
        .I1(\gen_rd[1].rd_data_rise_wl_r_reg[1]_5 ),
        .I2(\gen_rd[1].rd_data_rise_wl_r_reg[1]_6 ),
        .I3(\gen_rd[1].rd_data_rise_wl_r_reg[1]_7 ),
        .O(\p_0_out_inferred__19/gen_rd[1].rd_data_rise_wl_r[1]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \p_0_out_inferred__20/gen_rd[2].rd_data_rise_wl_r[2]_i_1 
       (.I0(\gen_rd[2].rd_data_rise_wl_r_reg[2]_0 ),
        .I1(\gen_rd[2].rd_data_rise_wl_r_reg[2]_1 ),
        .I2(\gen_rd[2].rd_data_rise_wl_r_reg[2]_2 ),
        .I3(\gen_rd[2].rd_data_rise_wl_r_reg[2]_3 ),
        .I4(\p_0_out_inferred__20/gen_rd[2].rd_data_rise_wl_r[2]_i_2_n_0 ),
        .O(\p_0_out_inferred__20/gen_rd[2].rd_data_rise_wl_r[2]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \p_0_out_inferred__20/gen_rd[2].rd_data_rise_wl_r[2]_i_2 
       (.I0(\gen_rd[2].rd_data_rise_wl_r_reg[2]_4 ),
        .I1(\gen_rd[2].rd_data_rise_wl_r_reg[2]_5 ),
        .I2(\gen_rd[2].rd_data_rise_wl_r_reg[2]_6 ),
        .I3(\gen_rd[2].rd_data_rise_wl_r_reg[2]_7 ),
        .O(\p_0_out_inferred__20/gen_rd[2].rd_data_rise_wl_r[2]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \p_0_out_inferred__21/gen_rd[3].rd_data_rise_wl_r[3]_i_1 
       (.I0(\gen_rd[3].rd_data_rise_wl_r_reg[3]_0 ),
        .I1(\gen_rd[3].rd_data_rise_wl_r_reg[3]_1 ),
        .I2(\gen_rd[3].rd_data_rise_wl_r_reg[3]_2 ),
        .I3(\gen_rd[3].rd_data_rise_wl_r_reg[3]_3 ),
        .I4(\p_0_out_inferred__21/gen_rd[3].rd_data_rise_wl_r[3]_i_2_n_0 ),
        .O(\p_0_out_inferred__21/gen_rd[3].rd_data_rise_wl_r[3]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \p_0_out_inferred__21/gen_rd[3].rd_data_rise_wl_r[3]_i_2 
       (.I0(\gen_rd[3].rd_data_rise_wl_r_reg[3]_4 ),
        .I1(\gen_rd[3].rd_data_rise_wl_r_reg[3]_5 ),
        .I2(\gen_rd[3].rd_data_rise_wl_r_reg[3]_6 ),
        .I3(\gen_rd[3].rd_data_rise_wl_r_reg[3]_7 ),
        .O(\p_0_out_inferred__21/gen_rd[3].rd_data_rise_wl_r[3]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \p_0_out_inferred__22/gen_rd[4].rd_data_rise_wl_r[4]_i_1 
       (.I0(\gen_rd[4].rd_data_rise_wl_r_reg[4]_0 ),
        .I1(\gen_rd[4].rd_data_rise_wl_r_reg[4]_1 ),
        .I2(\gen_rd[4].rd_data_rise_wl_r_reg[4]_2 ),
        .I3(\gen_rd[4].rd_data_rise_wl_r_reg[4]_3 ),
        .I4(\p_0_out_inferred__22/gen_rd[4].rd_data_rise_wl_r[4]_i_2_n_0 ),
        .O(\p_0_out_inferred__22/gen_rd[4].rd_data_rise_wl_r[4]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \p_0_out_inferred__22/gen_rd[4].rd_data_rise_wl_r[4]_i_2 
       (.I0(\gen_rd[4].rd_data_rise_wl_r_reg[4]_4 ),
        .I1(\gen_rd[4].rd_data_rise_wl_r_reg[4]_5 ),
        .I2(\gen_rd[4].rd_data_rise_wl_r_reg[4]_6 ),
        .I3(\gen_rd[4].rd_data_rise_wl_r_reg[4]_7 ),
        .O(\p_0_out_inferred__22/gen_rd[4].rd_data_rise_wl_r[4]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \p_0_out_inferred__23/gen_rd[5].rd_data_rise_wl_r[5]_i_1 
       (.I0(\gen_rd[5].rd_data_rise_wl_r_reg[5]_0 ),
        .I1(\gen_rd[5].rd_data_rise_wl_r_reg[5]_1 ),
        .I2(\gen_rd[5].rd_data_rise_wl_r_reg[5]_2 ),
        .I3(\gen_rd[5].rd_data_rise_wl_r_reg[5]_3 ),
        .I4(\p_0_out_inferred__23/gen_rd[5].rd_data_rise_wl_r[5]_i_2_n_0 ),
        .O(\p_0_out_inferred__23/gen_rd[5].rd_data_rise_wl_r[5]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \p_0_out_inferred__23/gen_rd[5].rd_data_rise_wl_r[5]_i_2 
       (.I0(\gen_rd[5].rd_data_rise_wl_r_reg[5]_4 ),
        .I1(\gen_rd[5].rd_data_rise_wl_r_reg[5]_5 ),
        .I2(\gen_rd[5].rd_data_rise_wl_r_reg[5]_6 ),
        .I3(\gen_rd[5].rd_data_rise_wl_r_reg[5]_7 ),
        .O(\p_0_out_inferred__23/gen_rd[5].rd_data_rise_wl_r[5]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \p_0_out_inferred__24/gen_rd[6].rd_data_rise_wl_r[6]_i_1 
       (.I0(\gen_rd[6].rd_data_rise_wl_r_reg[6]_0 ),
        .I1(\gen_rd[6].rd_data_rise_wl_r_reg[6]_1 ),
        .I2(\gen_rd[6].rd_data_rise_wl_r_reg[6]_2 ),
        .I3(\gen_rd[6].rd_data_rise_wl_r_reg[6]_3 ),
        .I4(\p_0_out_inferred__24/gen_rd[6].rd_data_rise_wl_r[6]_i_2_n_0 ),
        .O(\p_0_out_inferred__24/gen_rd[6].rd_data_rise_wl_r[6]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \p_0_out_inferred__24/gen_rd[6].rd_data_rise_wl_r[6]_i_2 
       (.I0(\gen_rd[6].rd_data_rise_wl_r_reg[6]_4 ),
        .I1(\gen_rd[6].rd_data_rise_wl_r_reg[6]_5 ),
        .I2(\gen_rd[6].rd_data_rise_wl_r_reg[6]_6 ),
        .I3(\gen_rd[6].rd_data_rise_wl_r_reg[6]_7 ),
        .O(\p_0_out_inferred__24/gen_rd[6].rd_data_rise_wl_r[6]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \p_0_out_inferred__25/gen_rd[7].rd_data_rise_wl_r[7]_i_1 
       (.I0(\gen_rd[7].rd_data_rise_wl_r_reg[7]_0 ),
        .I1(\gen_rd[7].rd_data_rise_wl_r_reg[7]_1 ),
        .I2(\gen_rd[7].rd_data_rise_wl_r_reg[7]_2 ),
        .I3(\gen_rd[7].rd_data_rise_wl_r_reg[7]_3 ),
        .I4(\p_0_out_inferred__25/gen_rd[7].rd_data_rise_wl_r[7]_i_2_n_0 ),
        .O(\p_0_out_inferred__25/gen_rd[7].rd_data_rise_wl_r[7]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \p_0_out_inferred__25/gen_rd[7].rd_data_rise_wl_r[7]_i_2 
       (.I0(\gen_rd[7].rd_data_rise_wl_r_reg[7]_4 ),
        .I1(\gen_rd[7].rd_data_rise_wl_r_reg[7]_5 ),
        .I2(\gen_rd[7].rd_data_rise_wl_r_reg[7]_6 ),
        .I3(\gen_rd[7].rd_data_rise_wl_r_reg[7]_7 ),
        .O(\p_0_out_inferred__25/gen_rd[7].rd_data_rise_wl_r[7]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair329" *) 
  LUT5 #(
    .INIT(32'h0000F010)) 
    phaser_out_i_1
       (.I0(phaser_out),
        .I1(phaser_out_0),
        .I2(po_stg2_cincdec),
        .I3(calib_in_common),
        .I4(phaser_out_1[0]),
        .O(\calib_sel_reg[1]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair329" *) 
  LUT5 #(
    .INIT(32'h0000CC40)) 
    phaser_out_i_1__0
       (.I0(phaser_out),
        .I1(po_stg2_cincdec),
        .I2(phaser_out_0),
        .I3(calib_in_common),
        .I4(phaser_out_1[0]),
        .O(\calib_sel_reg[1]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair330" *) 
  LUT5 #(
    .INIT(32'h0000AA80)) 
    phaser_out_i_1__1
       (.I0(po_stg2_cincdec),
        .I1(phaser_out_0),
        .I2(phaser_out),
        .I3(calib_in_common),
        .I4(phaser_out_1[0]),
        .O(dqs_wl_po_stg2_c_incdec_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair330" *) 
  LUT5 #(
    .INIT(32'h0000CC08)) 
    phaser_out_i_1__2
       (.I0(phaser_out),
        .I1(po_stg2_cincdec),
        .I2(phaser_out_0),
        .I3(calib_in_common),
        .I4(phaser_out_1[0]),
        .O(\calib_sel_reg[1]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair332" *) 
  LUT5 #(
    .INIT(32'h0000F010)) 
    phaser_out_i_1__3
       (.I0(phaser_out),
        .I1(phaser_out_0),
        .I2(po_stg2_cincdec),
        .I3(calib_in_common),
        .I4(phaser_out_1[2]),
        .O(\calib_sel_reg[1]_6 ));
  (* SOFT_HLUTNM = "soft_lutpair332" *) 
  LUT5 #(
    .INIT(32'h0000CC40)) 
    phaser_out_i_1__4
       (.I0(phaser_out),
        .I1(po_stg2_cincdec),
        .I2(phaser_out_0),
        .I3(calib_in_common),
        .I4(phaser_out_1[2]),
        .O(\calib_sel_reg[1]_7 ));
  (* SOFT_HLUTNM = "soft_lutpair339" *) 
  LUT5 #(
    .INIT(32'h0000AA80)) 
    phaser_out_i_1__5
       (.I0(po_stg2_cincdec),
        .I1(phaser_out_0),
        .I2(phaser_out),
        .I3(calib_in_common),
        .I4(phaser_out_1[2]),
        .O(dqs_wl_po_stg2_c_incdec_reg_1));
  (* SOFT_HLUTNM = "soft_lutpair339" *) 
  LUT5 #(
    .INIT(32'h0000CC08)) 
    phaser_out_i_1__6
       (.I0(phaser_out),
        .I1(po_stg2_cincdec),
        .I2(phaser_out_0),
        .I3(calib_in_common),
        .I4(phaser_out_1[2]),
        .O(\calib_sel_reg[1]_8 ));
  (* SOFT_HLUTNM = "soft_lutpair340" *) 
  LUT5 #(
    .INIT(32'h00001000)) 
    phaser_out_i_1__7
       (.I0(calib_in_common),
        .I1(phaser_out_0),
        .I2(po_stg2_cincdec),
        .I3(phaser_out),
        .I4(phaser_out_1[1]),
        .O(C_po_coarse_enable26_out));
  (* SOFT_HLUTNM = "soft_lutpair340" *) 
  LUT5 #(
    .INIT(32'h00000040)) 
    phaser_out_i_1__8
       (.I0(calib_in_common),
        .I1(phaser_out_0),
        .I2(po_stg2_cincdec),
        .I3(phaser_out),
        .I4(phaser_out_1[1]),
        .O(\gen_byte_sel_div2.calib_in_common_reg ));
  LUT5 #(
    .INIT(32'h00004000)) 
    phaser_out_i_1__9
       (.I0(calib_in_common),
        .I1(phaser_out),
        .I2(phaser_out_0),
        .I3(po_stg2_cincdec),
        .I4(phaser_out_1[1]),
        .O(\gen_byte_sel_div2.calib_in_common_reg_0 ));
  (* SOFT_HLUTNM = "soft_lutpair314" *) 
  LUT5 #(
    .INIT(32'h0000F010)) 
    phaser_out_i_2
       (.I0(phaser_out),
        .I1(phaser_out_0),
        .I2(po_enstg2_f),
        .I3(calib_in_common),
        .I4(phaser_out_1[0]),
        .O(\calib_sel_reg[1] ));
  (* SOFT_HLUTNM = "soft_lutpair314" *) 
  LUT5 #(
    .INIT(32'h0000CC40)) 
    phaser_out_i_2__0
       (.I0(phaser_out),
        .I1(po_enstg2_f),
        .I2(phaser_out_0),
        .I3(calib_in_common),
        .I4(phaser_out_1[0]),
        .O(\calib_sel_reg[1]_3 ));
  (* SOFT_HLUTNM = "soft_lutpair320" *) 
  LUT5 #(
    .INIT(32'h0000CC08)) 
    phaser_out_i_2__1
       (.I0(phaser_out),
        .I1(po_enstg2_f),
        .I2(phaser_out_0),
        .I3(calib_in_common),
        .I4(phaser_out_1[0]),
        .O(\calib_sel_reg[1]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair320" *) 
  LUT5 #(
    .INIT(32'h0000AA80)) 
    phaser_out_i_2__2
       (.I0(po_enstg2_f),
        .I1(phaser_out_0),
        .I2(phaser_out),
        .I3(calib_in_common),
        .I4(phaser_out_1[0]),
        .O(\calib_sel_reg[0] ));
  (* SOFT_HLUTNM = "soft_lutpair317" *) 
  LUT5 #(
    .INIT(32'h0000F010)) 
    phaser_out_i_2__3
       (.I0(phaser_out),
        .I1(phaser_out_0),
        .I2(po_enstg2_f),
        .I3(calib_in_common),
        .I4(phaser_out_1[2]),
        .O(\calib_sel_reg[1]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair318" *) 
  LUT5 #(
    .INIT(32'h0000CC40)) 
    phaser_out_i_2__4
       (.I0(phaser_out),
        .I1(po_enstg2_f),
        .I2(phaser_out_0),
        .I3(calib_in_common),
        .I4(phaser_out_1[2]),
        .O(\calib_sel_reg[1]_9 ));
  (* SOFT_HLUTNM = "soft_lutpair317" *) 
  LUT5 #(
    .INIT(32'h0000CC08)) 
    phaser_out_i_2__5
       (.I0(phaser_out),
        .I1(po_enstg2_f),
        .I2(phaser_out_0),
        .I3(calib_in_common),
        .I4(phaser_out_1[2]),
        .O(\calib_sel_reg[1]_10 ));
  (* SOFT_HLUTNM = "soft_lutpair318" *) 
  LUT5 #(
    .INIT(32'h0000AA80)) 
    phaser_out_i_2__6
       (.I0(po_enstg2_f),
        .I1(phaser_out_0),
        .I2(phaser_out),
        .I3(calib_in_common),
        .I4(phaser_out_1[2]),
        .O(\calib_sel_reg[0]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair308" *) 
  LUT5 #(
    .INIT(32'h00001000)) 
    phaser_out_i_3
       (.I0(calib_in_common),
        .I1(phaser_out_0),
        .I2(po_enstg2_f),
        .I3(phaser_out),
        .I4(phaser_out_1[1]),
        .O(C_po_fine_enable23_out));
  (* SOFT_HLUTNM = "soft_lutpair308" *) 
  LUT5 #(
    .INIT(32'h00000040)) 
    phaser_out_i_3__0
       (.I0(calib_in_common),
        .I1(phaser_out_0),
        .I2(po_enstg2_f),
        .I3(phaser_out),
        .I4(phaser_out_1[1]),
        .O(\gen_byte_sel_div2.calib_in_common_reg_1 ));
  LUT5 #(
    .INIT(32'h00004000)) 
    phaser_out_i_3__1
       (.I0(calib_in_common),
        .I1(phaser_out),
        .I2(phaser_out_0),
        .I3(po_enstg2_f),
        .I4(phaser_out_1[1]),
        .O(\gen_byte_sel_div2.calib_in_common_reg_2 ));
  LUT6 #(
    .INIT(64'h00000000EEEE000E)) 
    phaser_out_i_3__2
       (.I0(dqs_po_stg2_f_incdec),
        .I1(ck_po_stg2_f_indec),
        .I2(phaser_out),
        .I3(phaser_out_0),
        .I4(calib_in_common),
        .I5(phaser_out_1[0]),
        .O(dqs_po_stg2_f_incdec_reg_0));
  LUT6 #(
    .INIT(64'h00000000EEEE0E00)) 
    phaser_out_i_3__3
       (.I0(dqs_po_stg2_f_incdec),
        .I1(ck_po_stg2_f_indec),
        .I2(phaser_out),
        .I3(phaser_out_0),
        .I4(calib_in_common),
        .I5(phaser_out_1[0]),
        .O(dqs_po_stg2_f_incdec_reg_1));
  LUT6 #(
    .INIT(64'h00000000EEEE00E0)) 
    phaser_out_i_3__4
       (.I0(dqs_po_stg2_f_incdec),
        .I1(ck_po_stg2_f_indec),
        .I2(phaser_out),
        .I3(phaser_out_0),
        .I4(calib_in_common),
        .I5(phaser_out_1[0]),
        .O(dqs_po_stg2_f_incdec_reg_2));
  LUT6 #(
    .INIT(64'h00000000EEEEE000)) 
    phaser_out_i_3__5
       (.I0(dqs_po_stg2_f_incdec),
        .I1(ck_po_stg2_f_indec),
        .I2(phaser_out_0),
        .I3(phaser_out),
        .I4(calib_in_common),
        .I5(phaser_out_1[0]),
        .O(dqs_po_stg2_f_incdec_reg_3));
  LUT6 #(
    .INIT(64'h00000000EEEE000E)) 
    phaser_out_i_3__6
       (.I0(dqs_po_stg2_f_incdec),
        .I1(ck_po_stg2_f_indec),
        .I2(phaser_out),
        .I3(phaser_out_0),
        .I4(calib_in_common),
        .I5(phaser_out_1[2]),
        .O(dqs_po_stg2_f_incdec_reg_4));
  LUT6 #(
    .INIT(64'h00000000EEEE0E00)) 
    phaser_out_i_3__7
       (.I0(dqs_po_stg2_f_incdec),
        .I1(ck_po_stg2_f_indec),
        .I2(phaser_out),
        .I3(phaser_out_0),
        .I4(calib_in_common),
        .I5(phaser_out_1[2]),
        .O(dqs_po_stg2_f_incdec_reg_5));
  LUT6 #(
    .INIT(64'h00000000EEEE00E0)) 
    phaser_out_i_3__8
       (.I0(dqs_po_stg2_f_incdec),
        .I1(ck_po_stg2_f_indec),
        .I2(phaser_out),
        .I3(phaser_out_0),
        .I4(calib_in_common),
        .I5(phaser_out_1[2]),
        .O(dqs_po_stg2_f_incdec_reg_6));
  LUT6 #(
    .INIT(64'h00000000EEEEE000)) 
    phaser_out_i_3__9
       (.I0(dqs_po_stg2_f_incdec),
        .I1(ck_po_stg2_f_indec),
        .I2(phaser_out_0),
        .I3(phaser_out),
        .I4(calib_in_common),
        .I5(phaser_out_1[2]),
        .O(dqs_po_stg2_f_incdec_reg_7));
  LUT6 #(
    .INIT(64'h00000000000E0000)) 
    phaser_out_i_4
       (.I0(dqs_po_stg2_f_incdec),
        .I1(ck_po_stg2_f_indec),
        .I2(calib_in_common),
        .I3(phaser_out_0),
        .I4(phaser_out),
        .I5(phaser_out_1[1]),
        .O(C_po_fine_inc29_out));
  LUT6 #(
    .INIT(64'h0000000000000E00)) 
    phaser_out_i_4__0
       (.I0(dqs_po_stg2_f_incdec),
        .I1(ck_po_stg2_f_indec),
        .I2(calib_in_common),
        .I3(phaser_out_0),
        .I4(phaser_out),
        .I5(phaser_out_1[1]),
        .O(dqs_po_stg2_f_incdec_reg_8));
  LUT6 #(
    .INIT(64'h000000000E000000)) 
    phaser_out_i_4__1
       (.I0(dqs_po_stg2_f_incdec),
        .I1(ck_po_stg2_f_indec),
        .I2(calib_in_common),
        .I3(phaser_out),
        .I4(phaser_out_0),
        .I5(phaser_out_1[1]),
        .O(dqs_po_stg2_f_incdec_reg_9));
  (* srl_name = "\u_mig_mig/u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/phy_ctl_ready_r4_reg_srl4 " *) 
  SRL16E phy_ctl_ready_r4_reg_srl4
       (.A0(1'b1),
        .A1(1'b1),
        .A2(1'b0),
        .A3(1'b0),
        .CE(1'b1),
        .CLK(\dqs_count_r_reg[2]_rep__0_1 ),
        .D(Q),
        .Q(phy_ctl_ready_r4_reg_srl4_n_0));
  FDRE phy_ctl_ready_r5_reg
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(phy_ctl_ready_r4_reg_srl4_n_0),
        .Q(phy_ctl_ready_r5),
        .R(1'b0));
  FDRE phy_ctl_ready_r6_reg
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(phy_ctl_ready_r5),
        .Q(phy_ctl_ready_r6_reg_n_0),
        .R(1'b0));
  LUT2 #(
    .INIT(4'h2)) 
    po_cnt_dec_i_1
       (.I0(po_cnt_dec_i_2_n_0),
        .I1(\po_rdval_cnt[8]_i_3_n_0 ),
        .O(po_cnt_dec_i_1_n_0));
  LUT6 #(
    .INIT(64'h0000000200000000)) 
    po_cnt_dec_i_2
       (.I0(wait_cnt_reg[0]),
        .I1(wait_cnt_reg[1]),
        .I2(\single_rank.done_dqs_dec_reg_0 ),
        .I3(wait_cnt_reg[2]),
        .I4(wait_cnt_reg[3]),
        .I5(phy_ctl_ready_r6_reg_n_0),
        .O(po_cnt_dec_i_2_n_0));
  FDRE po_cnt_dec_reg
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(po_cnt_dec_i_1_n_0),
        .Q(po_cnt_dec_reg_0),
        .R(1'b0));
  LUT4 #(
    .INIT(16'hFFEA)) 
    po_dec_done_i_1
       (.I0(po_dec_done_i_2_n_0),
        .I1(phy_ctl_ready_r6_reg_n_0),
        .I2(\po_rdval_cnt[8]_i_3_n_0 ),
        .I3(po_dec_done),
        .O(po_dec_done_i_1_n_0));
  LUT5 #(
    .INIT(32'h00000080)) 
    po_dec_done_i_2
       (.I0(\po_rdval_cnt[8]_i_6_n_0 ),
        .I1(po_cnt_dec_reg_0),
        .I2(po_rdval_cnt[0]),
        .I3(po_rdval_cnt[5]),
        .I4(po_rdval_cnt[6]),
        .O(po_dec_done_i_2_n_0));
  FDRE po_dec_done_reg
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(po_dec_done_i_1_n_0),
        .Q(po_dec_done),
        .R(\wl_dqs_tap_count_r_reg[0][5][5]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair325" *) 
  LUT5 #(
    .INIT(32'h0303AA03)) 
    \po_rdval_cnt[0]_i_1 
       (.I0(\po_rdval_cnt_reg[0]_0 ),
        .I1(po_rdval_cnt[0]),
        .I2(\po_rdval_cnt[8]_i_3_n_0 ),
        .I3(phy_ctl_ready_r5),
        .I4(phy_ctl_ready_r6_reg_n_0),
        .O(\po_rdval_cnt[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h08FB0808080808FB)) 
    \po_rdval_cnt[1]_i_1 
       (.I0(\po_rdval_cnt_reg[1]_0 ),
        .I1(phy_ctl_ready_r5),
        .I2(phy_ctl_ready_r6_reg_n_0),
        .I3(\po_rdval_cnt[8]_i_3_n_0 ),
        .I4(po_rdval_cnt[0]),
        .I5(po_rdval_cnt[1]),
        .O(\po_rdval_cnt[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h88888888BBB8888B)) 
    \po_rdval_cnt[2]_i_1 
       (.I0(\po_rdval_cnt_reg[2]_0 ),
        .I1(\po_rdval_cnt[6]_i_3_n_0 ),
        .I2(po_rdval_cnt[1]),
        .I3(po_rdval_cnt[0]),
        .I4(po_rdval_cnt[2]),
        .I5(\po_rdval_cnt[8]_i_3_n_0 ),
        .O(\po_rdval_cnt[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h88888888BB8B88B8)) 
    \po_rdval_cnt[3]_i_1 
       (.I0(\po_rdval_cnt_reg[3]_0 ),
        .I1(\po_rdval_cnt[6]_i_3_n_0 ),
        .I2(\po_rdval_cnt[3]_i_3_n_0 ),
        .I3(po_rdval_cnt[2]),
        .I4(po_rdval_cnt[3]),
        .I5(\po_rdval_cnt[8]_i_3_n_0 ),
        .O(\po_rdval_cnt[3]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    \po_rdval_cnt[3]_i_3 
       (.I0(po_rdval_cnt[1]),
        .I1(po_rdval_cnt[0]),
        .O(\po_rdval_cnt[3]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h08080808FB0808FB)) 
    \po_rdval_cnt[4]_i_1 
       (.I0(\po_rdval_cnt_reg[4]_0 ),
        .I1(phy_ctl_ready_r5),
        .I2(phy_ctl_ready_r6_reg_n_0),
        .I3(\po_rdval_cnt[4]_i_3_n_0 ),
        .I4(po_rdval_cnt[4]),
        .I5(\po_rdval_cnt[8]_i_3_n_0 ),
        .O(\po_rdval_cnt[4]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair316" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    \po_rdval_cnt[4]_i_3 
       (.I0(po_rdval_cnt[3]),
        .I1(po_rdval_cnt[2]),
        .I2(po_rdval_cnt[0]),
        .I3(po_rdval_cnt[1]),
        .O(\po_rdval_cnt[4]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0808080808FBFB08)) 
    \po_rdval_cnt[5]_i_1 
       (.I0(\po_rdval_cnt_reg[5]_0 ),
        .I1(phy_ctl_ready_r5),
        .I2(phy_ctl_ready_r6_reg_n_0),
        .I3(\po_rdval_cnt[6]_i_4_n_0 ),
        .I4(po_rdval_cnt[5]),
        .I5(\po_rdval_cnt[8]_i_3_n_0 ),
        .O(\po_rdval_cnt[5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h88888888BB8B88B8)) 
    \po_rdval_cnt[6]_i_1 
       (.I0(\po_rdval_cnt_reg[6]_0 ),
        .I1(\po_rdval_cnt[6]_i_3_n_0 ),
        .I2(\po_rdval_cnt[6]_i_4_n_0 ),
        .I3(po_rdval_cnt[5]),
        .I4(po_rdval_cnt[6]),
        .I5(\po_rdval_cnt[8]_i_3_n_0 ),
        .O(\po_rdval_cnt[6]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair325" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \po_rdval_cnt[6]_i_3 
       (.I0(phy_ctl_ready_r5),
        .I1(phy_ctl_ready_r6_reg_n_0),
        .O(\po_rdval_cnt[6]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair316" *) 
  LUT5 #(
    .INIT(32'h00000001)) 
    \po_rdval_cnt[6]_i_4 
       (.I0(po_rdval_cnt[4]),
        .I1(po_rdval_cnt[1]),
        .I2(po_rdval_cnt[0]),
        .I3(po_rdval_cnt[2]),
        .I4(po_rdval_cnt[3]),
        .O(\po_rdval_cnt[6]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'h08FBFB08)) 
    \po_rdval_cnt[7]_i_1 
       (.I0(\po_rdval_cnt_reg[7]_0 ),
        .I1(phy_ctl_ready_r5),
        .I2(phy_ctl_ready_r6_reg_n_0),
        .I3(po_rdval_cnt[7]),
        .I4(\po_rdval_cnt[8]_i_5_n_0 ),
        .O(\po_rdval_cnt[7]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'hFFF4)) 
    \po_rdval_cnt[8]_i_1 
       (.I0(phy_ctl_ready_r6_reg_n_0),
        .I1(phy_ctl_ready_r5),
        .I2(\po_rdval_cnt[8]_i_3_n_0 ),
        .I3(po_cnt_dec_reg_0),
        .O(\po_rdval_cnt[8]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFB080808FB08FB08)) 
    \po_rdval_cnt[8]_i_2 
       (.I0(\po_rdval_cnt_reg[8]_0 ),
        .I1(phy_ctl_ready_r5),
        .I2(phy_ctl_ready_r6_reg_n_0),
        .I3(po_rdval_cnt[8]),
        .I4(po_rdval_cnt[7]),
        .I5(\po_rdval_cnt[8]_i_5_n_0 ),
        .O(\po_rdval_cnt[8]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h00000002)) 
    \po_rdval_cnt[8]_i_3 
       (.I0(\po_rdval_cnt[6]_i_4_n_0 ),
        .I1(po_rdval_cnt[8]),
        .I2(po_rdval_cnt[7]),
        .I3(po_rdval_cnt[5]),
        .I4(po_rdval_cnt[6]),
        .O(\po_rdval_cnt[8]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'h000000B0)) 
    \po_rdval_cnt[8]_i_5 
       (.I0(po_rdval_cnt[0]),
        .I1(\po_rdval_cnt[8]_i_6_n_0 ),
        .I2(\po_rdval_cnt[6]_i_4_n_0 ),
        .I3(po_rdval_cnt[5]),
        .I4(po_rdval_cnt[6]),
        .O(\po_rdval_cnt[8]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \po_rdval_cnt[8]_i_6 
       (.I0(po_rdval_cnt[4]),
        .I1(po_rdval_cnt[2]),
        .I2(po_rdval_cnt[3]),
        .I3(po_rdval_cnt[8]),
        .I4(po_rdval_cnt[7]),
        .I5(po_rdval_cnt[1]),
        .O(\po_rdval_cnt[8]_i_6_n_0 ));
  FDRE \po_rdval_cnt_reg[0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\po_rdval_cnt[8]_i_1_n_0 ),
        .D(\po_rdval_cnt[0]_i_1_n_0 ),
        .Q(po_rdval_cnt[0]),
        .R(\corse_inc_reg[6][2]_0 [0]));
  FDRE \po_rdval_cnt_reg[1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\po_rdval_cnt[8]_i_1_n_0 ),
        .D(\po_rdval_cnt[1]_i_1_n_0 ),
        .Q(po_rdval_cnt[1]),
        .R(\corse_inc_reg[6][2]_0 [0]));
  FDRE \po_rdval_cnt_reg[2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\po_rdval_cnt[8]_i_1_n_0 ),
        .D(\po_rdval_cnt[2]_i_1_n_0 ),
        .Q(po_rdval_cnt[2]),
        .R(\corse_inc_reg[6][2]_0 [0]));
  FDRE \po_rdval_cnt_reg[3] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\po_rdval_cnt[8]_i_1_n_0 ),
        .D(\po_rdval_cnt[3]_i_1_n_0 ),
        .Q(po_rdval_cnt[3]),
        .R(\corse_inc_reg[6][2]_0 [0]));
  FDRE \po_rdval_cnt_reg[4] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\po_rdval_cnt[8]_i_1_n_0 ),
        .D(\po_rdval_cnt[4]_i_1_n_0 ),
        .Q(po_rdval_cnt[4]),
        .R(\corse_inc_reg[6][2]_0 [0]));
  FDRE \po_rdval_cnt_reg[5] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\po_rdval_cnt[8]_i_1_n_0 ),
        .D(\po_rdval_cnt[5]_i_1_n_0 ),
        .Q(po_rdval_cnt[5]),
        .R(\corse_inc_reg[6][2]_0 [0]));
  FDRE \po_rdval_cnt_reg[6] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\po_rdval_cnt[8]_i_1_n_0 ),
        .D(\po_rdval_cnt[6]_i_1_n_0 ),
        .Q(po_rdval_cnt[6]),
        .R(\corse_inc_reg[6][2]_0 [0]));
  FDRE \po_rdval_cnt_reg[7] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\po_rdval_cnt[8]_i_1_n_0 ),
        .D(\po_rdval_cnt[7]_i_1_n_0 ),
        .Q(po_rdval_cnt[7]),
        .R(\corse_inc_reg[6][2]_0 [0]));
  FDRE \po_rdval_cnt_reg[8] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\po_rdval_cnt[8]_i_1_n_0 ),
        .D(\po_rdval_cnt[8]_i_2_n_0 ),
        .Q(po_rdval_cnt[8]),
        .R(\corse_inc_reg[6][2]_0 [0]));
  LUT6 #(
    .INIT(64'hFF3FFFFF00800000)) 
    \rank_cnt_r[0]_i_1 
       (.I0(\rank_cnt_r_reg_n_0_[1] ),
        .I1(wl_state_r__0[0]),
        .I2(\dqs_count_r[3]_i_4_n_0 ),
        .I3(p_0_in),
        .I4(\rank_cnt_r[1]_i_2_n_0 ),
        .I5(\rank_cnt_r_reg_n_0_[0] ),
        .O(\rank_cnt_r[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFF7FFFFF00800000)) 
    \rank_cnt_r[1]_i_1 
       (.I0(\rank_cnt_r_reg_n_0_[0] ),
        .I1(wl_state_r__0[0]),
        .I2(\dqs_count_r[3]_i_4_n_0 ),
        .I3(p_0_in),
        .I4(\rank_cnt_r[1]_i_2_n_0 ),
        .I5(\rank_cnt_r_reg_n_0_[1] ),
        .O(\rank_cnt_r[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair321" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \rank_cnt_r[1]_i_2 
       (.I0(wl_state_r__0[1]),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .O(\rank_cnt_r[1]_i_2_n_0 ));
  FDRE \rank_cnt_r_reg[0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\rank_cnt_r[0]_i_1_n_0 ),
        .Q(\rank_cnt_r_reg_n_0_[0] ),
        .R(\fine_inc_reg[6][3]_0 [0]));
  FDRE \rank_cnt_r_reg[1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\rank_cnt_r[1]_i_1_n_0 ),
        .Q(\rank_cnt_r_reg_n_0_[1] ),
        .R(\fine_inc_reg[6][3]_0 [0]));
  LUT4 #(
    .INIT(16'h0020)) 
    \rd_data_edge_detect_r[0]_i_1 
       (.I0(\rd_data_edge_detect_r[7]_i_6_n_0 ),
        .I1(\rd_data_previous_r_reg_n_0_[0] ),
        .I2(\gen_rd[0].rd_data_rise_wl_r_reg_n_0_[0] ),
        .I3(\rd_data_edge_detect_r_reg[7]_i_5_n_0 ),
        .O(\rd_data_edge_detect_r[0]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h0020)) 
    \rd_data_edge_detect_r[1]_i_1 
       (.I0(\rd_data_edge_detect_r[7]_i_6_n_0 ),
        .I1(\rd_data_previous_r_reg_n_0_[1] ),
        .I2(\gen_rd[1].rd_data_rise_wl_r_reg_n_0_[1] ),
        .I3(\rd_data_edge_detect_r_reg[7]_i_5_n_0 ),
        .O(\rd_data_edge_detect_r[1]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h0020)) 
    \rd_data_edge_detect_r[2]_i_1 
       (.I0(\rd_data_edge_detect_r[7]_i_6_n_0 ),
        .I1(\rd_data_previous_r_reg_n_0_[2] ),
        .I2(\gen_rd[2].rd_data_rise_wl_r_reg_n_0_[2] ),
        .I3(\rd_data_edge_detect_r_reg[7]_i_5_n_0 ),
        .O(\rd_data_edge_detect_r[2]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h0020)) 
    \rd_data_edge_detect_r[3]_i_1 
       (.I0(\rd_data_edge_detect_r[7]_i_6_n_0 ),
        .I1(\rd_data_previous_r_reg_n_0_[3] ),
        .I2(\gen_rd[3].rd_data_rise_wl_r_reg_n_0_[3] ),
        .I3(\rd_data_edge_detect_r_reg[7]_i_5_n_0 ),
        .O(\rd_data_edge_detect_r[3]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h0020)) 
    \rd_data_edge_detect_r[4]_i_1 
       (.I0(\rd_data_edge_detect_r[7]_i_6_n_0 ),
        .I1(\rd_data_previous_r_reg_n_0_[4] ),
        .I2(\gen_rd[4].rd_data_rise_wl_r_reg_n_0_[4] ),
        .I3(\rd_data_edge_detect_r_reg[7]_i_5_n_0 ),
        .O(\rd_data_edge_detect_r[4]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h0020)) 
    \rd_data_edge_detect_r[5]_i_1 
       (.I0(\rd_data_edge_detect_r[7]_i_6_n_0 ),
        .I1(\rd_data_previous_r_reg_n_0_[5] ),
        .I2(\gen_rd[5].rd_data_rise_wl_r_reg_n_0_[5] ),
        .I3(\rd_data_edge_detect_r_reg[7]_i_5_n_0 ),
        .O(\rd_data_edge_detect_r[5]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h0020)) 
    \rd_data_edge_detect_r[6]_i_1 
       (.I0(\rd_data_edge_detect_r[7]_i_6_n_0 ),
        .I1(\rd_data_previous_r_reg_n_0_[6] ),
        .I2(\gen_rd[6].rd_data_rise_wl_r_reg_n_0_[6] ),
        .I3(\rd_data_edge_detect_r_reg[7]_i_5_n_0 ),
        .O(\rd_data_edge_detect_r[6]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \rd_data_edge_detect_r[7]_i_1 
       (.I0(\rd_data_edge_detect_r[7]_i_4_n_0 ),
        .I1(flag_init),
        .I2(inhibit_edge_detect_r_reg_n_0),
        .I3(\single_rank.done_dqs_dec_reg_0 ),
        .I4(flag_ck_negedge_reg_n_0),
        .O(rd_data_edge_detect_r0));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data_edge_detect_r[7]_i_10 
       (.I0(\rd_data_previous_r_reg_n_0_[3] ),
        .I1(\rd_data_previous_r_reg_n_0_[2] ),
        .I2(dqs_count_r[1]),
        .I3(\rd_data_previous_r_reg_n_0_[1] ),
        .I4(dqs_count_r[0]),
        .I5(\rd_data_previous_r_reg_n_0_[0] ),
        .O(\rd_data_edge_detect_r[7]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data_edge_detect_r[7]_i_11 
       (.I0(\rd_data_previous_r_reg_n_0_[7] ),
        .I1(\rd_data_previous_r_reg_n_0_[6] ),
        .I2(dqs_count_r[1]),
        .I3(\rd_data_previous_r_reg_n_0_[5] ),
        .I4(dqs_count_r[0]),
        .I5(\rd_data_previous_r_reg_n_0_[4] ),
        .O(\rd_data_edge_detect_r[7]_i_11_n_0 ));
  LUT6 #(
    .INIT(64'h06130411FFFFFFFF)) 
    \rd_data_edge_detect_r[7]_i_2 
       (.I0(wl_state_r__0[2]),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I2(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I3(wl_state_r__0[1]),
        .I4(wl_state_r__0[0]),
        .I5(\rd_data_edge_detect_r_reg[7]_i_5_n_0 ),
        .O(\rd_data_edge_detect_r[7]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'h0020)) 
    \rd_data_edge_detect_r[7]_i_3 
       (.I0(\rd_data_edge_detect_r[7]_i_6_n_0 ),
        .I1(\rd_data_previous_r_reg_n_0_[7] ),
        .I2(\gen_rd[7].rd_data_rise_wl_r_reg_n_0_[7] ),
        .I3(\rd_data_edge_detect_r_reg[7]_i_5_n_0 ),
        .O(\rd_data_edge_detect_r[7]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000001)) 
    \rd_data_edge_detect_r[7]_i_4 
       (.I0(\wl_tap_count_r_reg_n_0_[1] ),
        .I1(\wl_tap_count_r_reg_n_0_[0] ),
        .I2(\wl_tap_count_r_reg_n_0_[3] ),
        .I3(\wl_tap_count_r_reg_n_0_[2] ),
        .I4(\wl_tap_count_r_reg_n_0_[5] ),
        .I5(\wl_tap_count_r_reg_n_0_[4] ),
        .O(\rd_data_edge_detect_r[7]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair351" *) 
  LUT4 #(
    .INIT(16'hD555)) 
    \rd_data_edge_detect_r[7]_i_6 
       (.I0(\rd_data_edge_detect_r_reg[7]_i_9_n_0 ),
        .I1(\stable_cnt_reg_n_0_[3] ),
        .I2(\stable_cnt_reg_n_0_[1] ),
        .I3(\stable_cnt_reg_n_0_[2] ),
        .O(\rd_data_edge_detect_r[7]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data_edge_detect_r[7]_i_7 
       (.I0(\rd_data_edge_detect_r_reg_n_0_[3] ),
        .I1(\rd_data_edge_detect_r_reg_n_0_[2] ),
        .I2(\dqs_count_r_reg[1]_rep_0 ),
        .I3(\rd_data_edge_detect_r_reg_n_0_[1] ),
        .I4(\dqs_count_r_reg[0]_rep_0 ),
        .I5(\rd_data_edge_detect_r_reg_n_0_[0] ),
        .O(\rd_data_edge_detect_r[7]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \rd_data_edge_detect_r[7]_i_8 
       (.I0(\rd_data_edge_detect_r_reg_n_0_[7] ),
        .I1(\rd_data_edge_detect_r_reg_n_0_[6] ),
        .I2(\dqs_count_r_reg[1]_rep_0 ),
        .I3(\rd_data_edge_detect_r_reg_n_0_[5] ),
        .I4(\dqs_count_r_reg[0]_rep_0 ),
        .I5(\rd_data_edge_detect_r_reg_n_0_[4] ),
        .O(\rd_data_edge_detect_r[7]_i_8_n_0 ));
  FDRE \rd_data_edge_detect_r_reg[0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\rd_data_edge_detect_r[7]_i_2_n_0 ),
        .D(\rd_data_edge_detect_r[0]_i_1_n_0 ),
        .Q(\rd_data_edge_detect_r_reg_n_0_[0] ),
        .R(rd_data_edge_detect_r0));
  FDRE \rd_data_edge_detect_r_reg[1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\rd_data_edge_detect_r[7]_i_2_n_0 ),
        .D(\rd_data_edge_detect_r[1]_i_1_n_0 ),
        .Q(\rd_data_edge_detect_r_reg_n_0_[1] ),
        .R(rd_data_edge_detect_r0));
  FDRE \rd_data_edge_detect_r_reg[2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\rd_data_edge_detect_r[7]_i_2_n_0 ),
        .D(\rd_data_edge_detect_r[2]_i_1_n_0 ),
        .Q(\rd_data_edge_detect_r_reg_n_0_[2] ),
        .R(rd_data_edge_detect_r0));
  FDRE \rd_data_edge_detect_r_reg[3] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\rd_data_edge_detect_r[7]_i_2_n_0 ),
        .D(\rd_data_edge_detect_r[3]_i_1_n_0 ),
        .Q(\rd_data_edge_detect_r_reg_n_0_[3] ),
        .R(rd_data_edge_detect_r0));
  FDRE \rd_data_edge_detect_r_reg[4] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\rd_data_edge_detect_r[7]_i_2_n_0 ),
        .D(\rd_data_edge_detect_r[4]_i_1_n_0 ),
        .Q(\rd_data_edge_detect_r_reg_n_0_[4] ),
        .R(rd_data_edge_detect_r0));
  FDRE \rd_data_edge_detect_r_reg[5] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\rd_data_edge_detect_r[7]_i_2_n_0 ),
        .D(\rd_data_edge_detect_r[5]_i_1_n_0 ),
        .Q(\rd_data_edge_detect_r_reg_n_0_[5] ),
        .R(rd_data_edge_detect_r0));
  FDRE \rd_data_edge_detect_r_reg[6] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\rd_data_edge_detect_r[7]_i_2_n_0 ),
        .D(\rd_data_edge_detect_r[6]_i_1_n_0 ),
        .Q(\rd_data_edge_detect_r_reg_n_0_[6] ),
        .R(rd_data_edge_detect_r0));
  FDRE \rd_data_edge_detect_r_reg[7] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\rd_data_edge_detect_r[7]_i_2_n_0 ),
        .D(\rd_data_edge_detect_r[7]_i_3_n_0 ),
        .Q(\rd_data_edge_detect_r_reg_n_0_[7] ),
        .R(rd_data_edge_detect_r0));
  MUXF7 \rd_data_edge_detect_r_reg[7]_i_5 
       (.I0(\rd_data_edge_detect_r[7]_i_7_n_0 ),
        .I1(\rd_data_edge_detect_r[7]_i_8_n_0 ),
        .O(\rd_data_edge_detect_r_reg[7]_i_5_n_0 ),
        .S(dqs_count_r[2]));
  MUXF7 \rd_data_edge_detect_r_reg[7]_i_9 
       (.I0(\rd_data_edge_detect_r[7]_i_10_n_0 ),
        .I1(\rd_data_edge_detect_r[7]_i_11_n_0 ),
        .O(\rd_data_edge_detect_r_reg[7]_i_9_n_0 ),
        .S(dqs_count_r[2]));
  LUT6 #(
    .INIT(64'h555775DD55777577)) 
    \rd_data_previous_r[7]_i_1 
       (.I0(\rd_data_previous_r[7]_i_2_n_0 ),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I2(wl_state_r__0[0]),
        .I3(wl_state_r__0[2]),
        .I4(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I5(wl_state_r__0[1]),
        .O(rd_data_previous_r0));
  LUT6 #(
    .INIT(64'h5555555555555545)) 
    \rd_data_previous_r[7]_i_2 
       (.I0(\rd_data_previous_r[7]_i_3_n_0 ),
        .I1(\rd_data_previous_r[7]_i_4_n_0 ),
        .I2(\rd_data_previous_r[7]_i_5_n_0 ),
        .I3(wl_state_r__0[0]),
        .I4(wl_state_r__0[1]),
        .I5(\wl_state_r1_reg_n_0_[1] ),
        .O(\rd_data_previous_r[7]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000800000000000)) 
    \rd_data_previous_r[7]_i_3 
       (.I0(wl_state_r__0[1]),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I2(wl_edge_detect_valid_r_reg_n_0),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I4(wl_state_r__0[2]),
        .I5(wl_state_r__0[0]),
        .O(\rd_data_previous_r[7]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair350" *) 
  LUT4 #(
    .INIT(16'hFFEF)) 
    \rd_data_previous_r[7]_i_4 
       (.I0(\wl_state_r1_reg_n_0_[0] ),
        .I1(\wl_state_r1_reg_n_0_[3] ),
        .I2(\wl_state_r1_reg_n_0_[2] ),
        .I3(\wl_state_r1_reg_n_0_[4] ),
        .O(\rd_data_previous_r[7]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair309" *) 
  LUT3 #(
    .INIT(8'h08)) 
    \rd_data_previous_r[7]_i_5 
       (.I0(wl_state_r__0[2]),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I2(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .O(\rd_data_previous_r[7]_i_5_n_0 ));
  FDRE \rd_data_previous_r_reg[0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(rd_data_previous_r0),
        .D(\gen_rd[0].rd_data_rise_wl_r_reg_n_0_[0] ),
        .Q(\rd_data_previous_r_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \rd_data_previous_r_reg[1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(rd_data_previous_r0),
        .D(\gen_rd[1].rd_data_rise_wl_r_reg_n_0_[1] ),
        .Q(\rd_data_previous_r_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \rd_data_previous_r_reg[2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(rd_data_previous_r0),
        .D(\gen_rd[2].rd_data_rise_wl_r_reg_n_0_[2] ),
        .Q(\rd_data_previous_r_reg_n_0_[2] ),
        .R(1'b0));
  FDRE \rd_data_previous_r_reg[3] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(rd_data_previous_r0),
        .D(\gen_rd[3].rd_data_rise_wl_r_reg_n_0_[3] ),
        .Q(\rd_data_previous_r_reg_n_0_[3] ),
        .R(1'b0));
  FDRE \rd_data_previous_r_reg[4] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(rd_data_previous_r0),
        .D(\gen_rd[4].rd_data_rise_wl_r_reg_n_0_[4] ),
        .Q(\rd_data_previous_r_reg_n_0_[4] ),
        .R(1'b0));
  FDRE \rd_data_previous_r_reg[5] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(rd_data_previous_r0),
        .D(\gen_rd[5].rd_data_rise_wl_r_reg_n_0_[5] ),
        .Q(\rd_data_previous_r_reg_n_0_[5] ),
        .R(1'b0));
  FDRE \rd_data_previous_r_reg[6] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(rd_data_previous_r0),
        .D(\gen_rd[6].rd_data_rise_wl_r_reg_n_0_[6] ),
        .Q(\rd_data_previous_r_reg_n_0_[6] ),
        .R(1'b0));
  FDRE \rd_data_previous_r_reg[7] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(rd_data_previous_r0),
        .D(\gen_rd[7].rd_data_rise_wl_r_reg_n_0_[7] ),
        .Q(\rd_data_previous_r_reg_n_0_[7] ),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h000000BA)) 
    \single_rank.done_dqs_dec_i_1 
       (.I0(done_dqs_tap_inc),
        .I1(wr_level_done_r4),
        .I2(wr_level_done_r3),
        .I3(done_dqs_dec238_out),
        .I4(\single_rank.done_dqs_dec_reg_0 ),
        .O(\single_rank.done_dqs_dec_i_1_n_0 ));
  FDRE \single_rank.done_dqs_dec_reg 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\single_rank.done_dqs_dec_i_1_n_0 ),
        .Q(done_dqs_tap_inc),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hFFFEFFFF00020000)) 
    \smallest[0][0]_i_1 
       (.I0(\smallest_reg[0][0]_i_2_n_0 ),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I2(wl_state_r__0[0]),
        .I3(wl_state_r__0[1]),
        .I4(wl_state_r__0[2]),
        .I5(\wl_dqs_tap_count_r_reg_n_0_[0][0][0] ),
        .O(largest[0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \smallest[0][0]_i_3 
       (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][3][0] ),
        .I1(\wl_dqs_tap_count_r_reg_n_0_[0][2][0] ),
        .I2(\dqs_count_r_reg[1]_rep_0 ),
        .I3(\wl_dqs_tap_count_r_reg_n_0_[0][1][0] ),
        .I4(\dqs_count_r_reg[0]_rep_0 ),
        .I5(\wl_dqs_tap_count_r_reg_n_0_[0][0][0] ),
        .O(\smallest[0][0]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \smallest[0][0]_i_4 
       (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][7][0] ),
        .I1(\wl_dqs_tap_count_r_reg_n_0_[0][6][0] ),
        .I2(\dqs_count_r_reg[1]_rep_0 ),
        .I3(\wl_dqs_tap_count_r_reg_n_0_[0][5][0] ),
        .I4(\dqs_count_r_reg[0]_rep_0 ),
        .I5(\wl_dqs_tap_count_r_reg_n_0_[0][4][0] ),
        .O(\smallest[0][0]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFEFFFF00020000)) 
    \smallest[0][1]_i_1 
       (.I0(\smallest_reg[0][1]_i_2_n_0 ),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I2(wl_state_r__0[0]),
        .I3(wl_state_r__0[1]),
        .I4(wl_state_r__0[2]),
        .I5(\wl_dqs_tap_count_r_reg_n_0_[0][0][1] ),
        .O(largest[1]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \smallest[0][1]_i_3 
       (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][3][1] ),
        .I1(\wl_dqs_tap_count_r_reg_n_0_[0][2][1] ),
        .I2(\dqs_count_r_reg[1]_rep_0 ),
        .I3(\wl_dqs_tap_count_r_reg_n_0_[0][1][1] ),
        .I4(\dqs_count_r_reg[0]_rep_0 ),
        .I5(\wl_dqs_tap_count_r_reg_n_0_[0][0][1] ),
        .O(\smallest[0][1]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \smallest[0][1]_i_4 
       (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][7][1] ),
        .I1(\wl_dqs_tap_count_r_reg_n_0_[0][6][1] ),
        .I2(\dqs_count_r_reg[1]_rep_0 ),
        .I3(\wl_dqs_tap_count_r_reg_n_0_[0][5][1] ),
        .I4(\dqs_count_r_reg[0]_rep_0 ),
        .I5(\wl_dqs_tap_count_r_reg_n_0_[0][4][1] ),
        .O(\smallest[0][1]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFEFFFF00020000)) 
    \smallest[0][2]_i_1 
       (.I0(\smallest_reg[0][2]_i_2_n_0 ),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I2(wl_state_r__0[0]),
        .I3(wl_state_r__0[1]),
        .I4(wl_state_r__0[2]),
        .I5(\wl_dqs_tap_count_r_reg_n_0_[0][0][2] ),
        .O(largest[2]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \smallest[0][2]_i_3 
       (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][3][2] ),
        .I1(\wl_dqs_tap_count_r_reg_n_0_[0][2][2] ),
        .I2(\dqs_count_r_reg[1]_rep_0 ),
        .I3(\wl_dqs_tap_count_r_reg_n_0_[0][1][2] ),
        .I4(\dqs_count_r_reg[0]_rep_0 ),
        .I5(\wl_dqs_tap_count_r_reg_n_0_[0][0][2] ),
        .O(\smallest[0][2]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \smallest[0][2]_i_4 
       (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][7][2] ),
        .I1(\wl_dqs_tap_count_r_reg_n_0_[0][6][2] ),
        .I2(\dqs_count_r_reg[1]_rep_0 ),
        .I3(\wl_dqs_tap_count_r_reg_n_0_[0][5][2] ),
        .I4(\dqs_count_r_reg[0]_rep_0 ),
        .I5(\wl_dqs_tap_count_r_reg_n_0_[0][4][2] ),
        .O(\smallest[0][2]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFEFFFF00020000)) 
    \smallest[0][3]_i_1 
       (.I0(\smallest_reg[0][3]_i_2_n_0 ),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I2(wl_state_r__0[0]),
        .I3(wl_state_r__0[1]),
        .I4(wl_state_r__0[2]),
        .I5(\wl_dqs_tap_count_r_reg_n_0_[0][0][3] ),
        .O(largest[3]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \smallest[0][3]_i_3 
       (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][3][3] ),
        .I1(\wl_dqs_tap_count_r_reg_n_0_[0][2][3] ),
        .I2(\dqs_count_r_reg[1]_rep_0 ),
        .I3(\wl_dqs_tap_count_r_reg_n_0_[0][1][3] ),
        .I4(\dqs_count_r_reg[0]_rep_0 ),
        .I5(\wl_dqs_tap_count_r_reg_n_0_[0][0][3] ),
        .O(\smallest[0][3]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \smallest[0][3]_i_4 
       (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][7][3] ),
        .I1(\wl_dqs_tap_count_r_reg_n_0_[0][6][3] ),
        .I2(\dqs_count_r_reg[1]_rep_0 ),
        .I3(\wl_dqs_tap_count_r_reg_n_0_[0][5][3] ),
        .I4(\dqs_count_r_reg[0]_rep_0 ),
        .I5(\wl_dqs_tap_count_r_reg_n_0_[0][4][3] ),
        .O(\smallest[0][3]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hFFFEFFFF00020000)) 
    \smallest[0][4]_i_1 
       (.I0(\smallest_reg[0][4]_i_2_n_0 ),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I2(wl_state_r__0[0]),
        .I3(wl_state_r__0[1]),
        .I4(wl_state_r__0[2]),
        .I5(\wl_dqs_tap_count_r_reg_n_0_[0][0][4] ),
        .O(largest[4]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \smallest[0][4]_i_3 
       (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][3][4] ),
        .I1(\wl_dqs_tap_count_r_reg_n_0_[0][2][4] ),
        .I2(dqs_count_r[1]),
        .I3(\wl_dqs_tap_count_r_reg_n_0_[0][1][4] ),
        .I4(\dqs_count_r_reg[0]_rep_0 ),
        .I5(\wl_dqs_tap_count_r_reg_n_0_[0][0][4] ),
        .O(\smallest[0][4]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \smallest[0][4]_i_4 
       (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][7][4] ),
        .I1(\wl_dqs_tap_count_r_reg_n_0_[0][6][4] ),
        .I2(\dqs_count_r_reg[1]_rep_0 ),
        .I3(\wl_dqs_tap_count_r_reg_n_0_[0][5][4] ),
        .I4(\dqs_count_r_reg[0]_rep_0 ),
        .I5(\wl_dqs_tap_count_r_reg_n_0_[0][4][4] ),
        .O(\smallest[0][4]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'h00010000)) 
    \smallest[0][5]_i_1 
       (.I0(\dqs_count_r_reg[3]_0 ),
        .I1(\dqs_count_r_reg[2]_rep_n_0 ),
        .I2(dqs_count_r[1]),
        .I3(dqs_count_r[0]),
        .I4(\smallest[0][5]_i_3_n_0 ),
        .O(\smallest[0][5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFEFFFF00020000)) 
    \smallest[0][5]_i_2 
       (.I0(\smallest_reg[0][5]_i_4_n_0 ),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I2(wl_state_r__0[0]),
        .I3(wl_state_r__0[1]),
        .I4(wl_state_r__0[2]),
        .I5(\wl_dqs_tap_count_r_reg_n_0_[0][0][5] ),
        .O(largest[5]));
  (* SOFT_HLUTNM = "soft_lutpair326" *) 
  LUT4 #(
    .INIT(16'h0100)) 
    \smallest[0][5]_i_3 
       (.I0(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I1(wl_state_r__0[0]),
        .I2(wl_state_r__0[1]),
        .I3(wl_state_r__0[2]),
        .O(\smallest[0][5]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \smallest[0][5]_i_5 
       (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][3][5] ),
        .I1(\wl_dqs_tap_count_r_reg_n_0_[0][2][5] ),
        .I2(dqs_count_r[1]),
        .I3(\wl_dqs_tap_count_r_reg_n_0_[0][1][5] ),
        .I4(dqs_count_r[0]),
        .I5(\wl_dqs_tap_count_r_reg_n_0_[0][0][5] ),
        .O(\smallest[0][5]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \smallest[0][5]_i_6 
       (.I0(\wl_dqs_tap_count_r_reg_n_0_[0][7][5] ),
        .I1(\wl_dqs_tap_count_r_reg_n_0_[0][6][5] ),
        .I2(dqs_count_r[1]),
        .I3(\wl_dqs_tap_count_r_reg_n_0_[0][5][5] ),
        .I4(dqs_count_r[0]),
        .I5(\wl_dqs_tap_count_r_reg_n_0_[0][4][5] ),
        .O(\smallest[0][5]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hFFFEFFFF00020000)) 
    \smallest[1][0]_i_1 
       (.I0(\smallest_reg[0][0]_i_2_n_0 ),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I2(wl_state_r__0[0]),
        .I3(wl_state_r__0[1]),
        .I4(wl_state_r__0[2]),
        .I5(\wl_dqs_tap_count_r_reg_n_0_[0][1][0] ),
        .O(\smallest[1][0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFEFFFF00020000)) 
    \smallest[1][1]_i_1 
       (.I0(\smallest_reg[0][1]_i_2_n_0 ),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I2(wl_state_r__0[0]),
        .I3(wl_state_r__0[1]),
        .I4(wl_state_r__0[2]),
        .I5(\wl_dqs_tap_count_r_reg_n_0_[0][1][1] ),
        .O(\smallest[1][1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFEFFFF00020000)) 
    \smallest[1][2]_i_1 
       (.I0(\smallest_reg[0][2]_i_2_n_0 ),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I2(wl_state_r__0[0]),
        .I3(wl_state_r__0[1]),
        .I4(wl_state_r__0[2]),
        .I5(\wl_dqs_tap_count_r_reg_n_0_[0][1][2] ),
        .O(\smallest[1][2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFEFFFF00020000)) 
    \smallest[1][3]_i_1 
       (.I0(\smallest_reg[0][3]_i_2_n_0 ),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I2(wl_state_r__0[0]),
        .I3(wl_state_r__0[1]),
        .I4(wl_state_r__0[2]),
        .I5(\wl_dqs_tap_count_r_reg_n_0_[0][1][3] ),
        .O(\smallest[1][3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFEFFFF00020000)) 
    \smallest[1][4]_i_1 
       (.I0(\smallest_reg[0][4]_i_2_n_0 ),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I2(wl_state_r__0[0]),
        .I3(wl_state_r__0[1]),
        .I4(wl_state_r__0[2]),
        .I5(\wl_dqs_tap_count_r_reg_n_0_[0][1][4] ),
        .O(\smallest[1][4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00000200)) 
    \smallest[1][5]_i_1 
       (.I0(\smallest[0][5]_i_3_n_0 ),
        .I1(\dqs_count_r_reg[3]_0 ),
        .I2(\dqs_count_r_reg[2]_rep_n_0 ),
        .I3(dqs_count_r[0]),
        .I4(dqs_count_r[1]),
        .O(\smallest[1][5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFEFFFF00020000)) 
    \smallest[1][5]_i_2 
       (.I0(\smallest_reg[0][5]_i_4_n_0 ),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I2(wl_state_r__0[0]),
        .I3(wl_state_r__0[1]),
        .I4(wl_state_r__0[2]),
        .I5(\wl_dqs_tap_count_r_reg_n_0_[0][1][5] ),
        .O(\smallest[1][5]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFEFFFF00020000)) 
    \smallest[2][0]_i_1 
       (.I0(\smallest_reg[0][0]_i_2_n_0 ),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I2(wl_state_r__0[0]),
        .I3(wl_state_r__0[1]),
        .I4(wl_state_r__0[2]),
        .I5(\wl_dqs_tap_count_r_reg_n_0_[0][2][0] ),
        .O(\smallest[2][0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFEFFFF00020000)) 
    \smallest[2][1]_i_1 
       (.I0(\smallest_reg[0][1]_i_2_n_0 ),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I2(wl_state_r__0[0]),
        .I3(wl_state_r__0[1]),
        .I4(wl_state_r__0[2]),
        .I5(\wl_dqs_tap_count_r_reg_n_0_[0][2][1] ),
        .O(\smallest[2][1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFEFFFF00020000)) 
    \smallest[2][2]_i_1 
       (.I0(\smallest_reg[0][2]_i_2_n_0 ),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I2(wl_state_r__0[0]),
        .I3(wl_state_r__0[1]),
        .I4(wl_state_r__0[2]),
        .I5(\wl_dqs_tap_count_r_reg_n_0_[0][2][2] ),
        .O(\smallest[2][2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFEFFFF00020000)) 
    \smallest[2][3]_i_1 
       (.I0(\smallest_reg[0][3]_i_2_n_0 ),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I2(wl_state_r__0[0]),
        .I3(wl_state_r__0[1]),
        .I4(wl_state_r__0[2]),
        .I5(\wl_dqs_tap_count_r_reg_n_0_[0][2][3] ),
        .O(\smallest[2][3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFEFFFF00020000)) 
    \smallest[2][4]_i_1 
       (.I0(\smallest_reg[0][4]_i_2_n_0 ),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I2(wl_state_r__0[0]),
        .I3(wl_state_r__0[1]),
        .I4(wl_state_r__0[2]),
        .I5(\wl_dqs_tap_count_r_reg_n_0_[0][2][4] ),
        .O(\smallest[2][4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00000200)) 
    \smallest[2][5]_i_1 
       (.I0(\smallest[0][5]_i_3_n_0 ),
        .I1(\dqs_count_r_reg[3]_0 ),
        .I2(\dqs_count_r_reg[2]_rep_n_0 ),
        .I3(dqs_count_r[1]),
        .I4(dqs_count_r[0]),
        .O(\smallest[2][5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFEFFFF00020000)) 
    \smallest[2][5]_i_2 
       (.I0(\smallest_reg[0][5]_i_4_n_0 ),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I2(wl_state_r__0[0]),
        .I3(wl_state_r__0[1]),
        .I4(wl_state_r__0[2]),
        .I5(\wl_dqs_tap_count_r_reg_n_0_[0][2][5] ),
        .O(\smallest[2][5]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFEFFFF00020000)) 
    \smallest[3][0]_i_1 
       (.I0(\smallest_reg[0][0]_i_2_n_0 ),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I2(wl_state_r__0[0]),
        .I3(wl_state_r__0[1]),
        .I4(wl_state_r__0[2]),
        .I5(\wl_dqs_tap_count_r_reg_n_0_[0][3][0] ),
        .O(\smallest[3][0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFEFFFF00020000)) 
    \smallest[3][1]_i_1 
       (.I0(\smallest_reg[0][1]_i_2_n_0 ),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I2(wl_state_r__0[0]),
        .I3(wl_state_r__0[1]),
        .I4(wl_state_r__0[2]),
        .I5(\wl_dqs_tap_count_r_reg_n_0_[0][3][1] ),
        .O(\smallest[3][1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFEFFFF00020000)) 
    \smallest[3][2]_i_1 
       (.I0(\smallest_reg[0][2]_i_2_n_0 ),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I2(wl_state_r__0[0]),
        .I3(wl_state_r__0[1]),
        .I4(wl_state_r__0[2]),
        .I5(\wl_dqs_tap_count_r_reg_n_0_[0][3][2] ),
        .O(\smallest[3][2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFEFFFF00020000)) 
    \smallest[3][3]_i_1 
       (.I0(\smallest_reg[0][3]_i_2_n_0 ),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I2(wl_state_r__0[0]),
        .I3(wl_state_r__0[1]),
        .I4(wl_state_r__0[2]),
        .I5(\wl_dqs_tap_count_r_reg_n_0_[0][3][3] ),
        .O(\smallest[3][3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFEFFFF00020000)) 
    \smallest[3][4]_i_1 
       (.I0(\smallest_reg[0][4]_i_2_n_0 ),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I2(wl_state_r__0[0]),
        .I3(wl_state_r__0[1]),
        .I4(wl_state_r__0[2]),
        .I5(\wl_dqs_tap_count_r_reg_n_0_[0][3][4] ),
        .O(\smallest[3][4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00000080)) 
    \smallest[3][5]_i_1 
       (.I0(\smallest[0][5]_i_3_n_0 ),
        .I1(dqs_count_r[1]),
        .I2(dqs_count_r[0]),
        .I3(\dqs_count_r_reg[3]_0 ),
        .I4(\dqs_count_r_reg[2]_rep_n_0 ),
        .O(\smallest[3][5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFEFFFF00020000)) 
    \smallest[3][5]_i_2 
       (.I0(\smallest_reg[0][5]_i_4_n_0 ),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I2(wl_state_r__0[0]),
        .I3(wl_state_r__0[1]),
        .I4(wl_state_r__0[2]),
        .I5(\wl_dqs_tap_count_r_reg_n_0_[0][3][5] ),
        .O(\smallest[3][5]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFEFFFF00020000)) 
    \smallest[4][0]_i_1 
       (.I0(\smallest_reg[0][0]_i_2_n_0 ),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I2(wl_state_r__0[0]),
        .I3(wl_state_r__0[1]),
        .I4(wl_state_r__0[2]),
        .I5(\wl_dqs_tap_count_r_reg_n_0_[0][4][0] ),
        .O(\smallest[4][0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFEFFFF00020000)) 
    \smallest[4][1]_i_1 
       (.I0(\smallest_reg[0][1]_i_2_n_0 ),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I2(wl_state_r__0[0]),
        .I3(wl_state_r__0[1]),
        .I4(wl_state_r__0[2]),
        .I5(\wl_dqs_tap_count_r_reg_n_0_[0][4][1] ),
        .O(\smallest[4][1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFEFFFF00020000)) 
    \smallest[4][2]_i_1 
       (.I0(\smallest_reg[0][2]_i_2_n_0 ),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I2(wl_state_r__0[0]),
        .I3(wl_state_r__0[1]),
        .I4(wl_state_r__0[2]),
        .I5(\wl_dqs_tap_count_r_reg_n_0_[0][4][2] ),
        .O(\smallest[4][2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFEFFFF00020000)) 
    \smallest[4][3]_i_1 
       (.I0(\smallest_reg[0][3]_i_2_n_0 ),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I2(wl_state_r__0[0]),
        .I3(wl_state_r__0[1]),
        .I4(wl_state_r__0[2]),
        .I5(\wl_dqs_tap_count_r_reg_n_0_[0][4][3] ),
        .O(\smallest[4][3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFEFFFF00020000)) 
    \smallest[4][4]_i_1 
       (.I0(\smallest_reg[0][4]_i_2_n_0 ),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I2(wl_state_r__0[0]),
        .I3(wl_state_r__0[1]),
        .I4(wl_state_r__0[2]),
        .I5(\wl_dqs_tap_count_r_reg_n_0_[0][4][4] ),
        .O(\smallest[4][4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00000020)) 
    \smallest[4][5]_i_1 
       (.I0(\smallest[0][5]_i_3_n_0 ),
        .I1(\dqs_count_r_reg[3]_0 ),
        .I2(\dqs_count_r_reg[2]_rep_n_0 ),
        .I3(dqs_count_r[1]),
        .I4(dqs_count_r[0]),
        .O(\smallest[4][5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFEFFFF00020000)) 
    \smallest[4][5]_i_2 
       (.I0(\smallest_reg[0][5]_i_4_n_0 ),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I2(wl_state_r__0[0]),
        .I3(wl_state_r__0[1]),
        .I4(wl_state_r__0[2]),
        .I5(\wl_dqs_tap_count_r_reg_n_0_[0][4][5] ),
        .O(\smallest[4][5]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFEFFFF00020000)) 
    \smallest[5][0]_i_1 
       (.I0(\smallest_reg[0][0]_i_2_n_0 ),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I2(wl_state_r__0[0]),
        .I3(wl_state_r__0[1]),
        .I4(wl_state_r__0[2]),
        .I5(\wl_dqs_tap_count_r_reg_n_0_[0][5][0] ),
        .O(\smallest[5][0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFEFFFF00020000)) 
    \smallest[5][1]_i_1 
       (.I0(\smallest_reg[0][1]_i_2_n_0 ),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I2(wl_state_r__0[0]),
        .I3(wl_state_r__0[1]),
        .I4(wl_state_r__0[2]),
        .I5(\wl_dqs_tap_count_r_reg_n_0_[0][5][1] ),
        .O(\smallest[5][1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFEFFFF00020000)) 
    \smallest[5][2]_i_1 
       (.I0(\smallest_reg[0][2]_i_2_n_0 ),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I2(wl_state_r__0[0]),
        .I3(wl_state_r__0[1]),
        .I4(wl_state_r__0[2]),
        .I5(\wl_dqs_tap_count_r_reg_n_0_[0][5][2] ),
        .O(\smallest[5][2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFEFFFF00020000)) 
    \smallest[5][3]_i_1 
       (.I0(\smallest_reg[0][3]_i_2_n_0 ),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I2(wl_state_r__0[0]),
        .I3(wl_state_r__0[1]),
        .I4(wl_state_r__0[2]),
        .I5(\wl_dqs_tap_count_r_reg_n_0_[0][5][3] ),
        .O(\smallest[5][3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFEFFFF00020000)) 
    \smallest[5][4]_i_1 
       (.I0(\smallest_reg[0][4]_i_2_n_0 ),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I2(wl_state_r__0[0]),
        .I3(wl_state_r__0[1]),
        .I4(wl_state_r__0[2]),
        .I5(\wl_dqs_tap_count_r_reg_n_0_[0][5][4] ),
        .O(\smallest[5][4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00002000)) 
    \smallest[5][5]_i_1 
       (.I0(\smallest[0][5]_i_3_n_0 ),
        .I1(\dqs_count_r_reg[3]_0 ),
        .I2(\dqs_count_r_reg[2]_rep_n_0 ),
        .I3(dqs_count_r[0]),
        .I4(dqs_count_r[1]),
        .O(\smallest[5][5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFEFFFF00020000)) 
    \smallest[5][5]_i_2 
       (.I0(\smallest_reg[0][5]_i_4_n_0 ),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I2(wl_state_r__0[0]),
        .I3(wl_state_r__0[1]),
        .I4(wl_state_r__0[2]),
        .I5(\wl_dqs_tap_count_r_reg_n_0_[0][5][5] ),
        .O(\smallest[5][5]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFEFFFF00020000)) 
    \smallest[6][0]_i_1 
       (.I0(\smallest_reg[0][0]_i_2_n_0 ),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I2(wl_state_r__0[0]),
        .I3(wl_state_r__0[1]),
        .I4(wl_state_r__0[2]),
        .I5(\wl_dqs_tap_count_r_reg_n_0_[0][6][0] ),
        .O(\smallest[6][0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFEFFFF00020000)) 
    \smallest[6][1]_i_1 
       (.I0(\smallest_reg[0][1]_i_2_n_0 ),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I2(wl_state_r__0[0]),
        .I3(wl_state_r__0[1]),
        .I4(wl_state_r__0[2]),
        .I5(\wl_dqs_tap_count_r_reg_n_0_[0][6][1] ),
        .O(\smallest[6][1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFEFFFF00020000)) 
    \smallest[6][2]_i_1 
       (.I0(\smallest_reg[0][2]_i_2_n_0 ),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I2(wl_state_r__0[0]),
        .I3(wl_state_r__0[1]),
        .I4(wl_state_r__0[2]),
        .I5(\wl_dqs_tap_count_r_reg_n_0_[0][6][2] ),
        .O(\smallest[6][2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFEFFFF00020000)) 
    \smallest[6][3]_i_1 
       (.I0(\smallest_reg[0][3]_i_2_n_0 ),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I2(wl_state_r__0[0]),
        .I3(wl_state_r__0[1]),
        .I4(wl_state_r__0[2]),
        .I5(\wl_dqs_tap_count_r_reg_n_0_[0][6][3] ),
        .O(\smallest[6][3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFEFFFF00020000)) 
    \smallest[6][4]_i_1 
       (.I0(\smallest_reg[0][4]_i_2_n_0 ),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I2(wl_state_r__0[0]),
        .I3(wl_state_r__0[1]),
        .I4(wl_state_r__0[2]),
        .I5(\wl_dqs_tap_count_r_reg_n_0_[0][6][4] ),
        .O(\smallest[6][4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00002000)) 
    \smallest[6][5]_i_1 
       (.I0(\smallest[0][5]_i_3_n_0 ),
        .I1(\dqs_count_r_reg[3]_0 ),
        .I2(\dqs_count_r_reg[2]_rep_n_0 ),
        .I3(dqs_count_r[1]),
        .I4(dqs_count_r[0]),
        .O(\smallest[6][5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFEFFFF00020000)) 
    \smallest[6][5]_i_2 
       (.I0(\smallest_reg[0][5]_i_4_n_0 ),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I2(wl_state_r__0[0]),
        .I3(wl_state_r__0[1]),
        .I4(wl_state_r__0[2]),
        .I5(\wl_dqs_tap_count_r_reg_n_0_[0][6][5] ),
        .O(\smallest[6][5]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFEFFFF00020000)) 
    \smallest[7][0]_i_1 
       (.I0(\smallest_reg[0][0]_i_2_n_0 ),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I2(wl_state_r__0[0]),
        .I3(wl_state_r__0[1]),
        .I4(wl_state_r__0[2]),
        .I5(\wl_dqs_tap_count_r_reg_n_0_[0][7][0] ),
        .O(\smallest[7][0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFEFFFF00020000)) 
    \smallest[7][1]_i_1 
       (.I0(\smallest_reg[0][1]_i_2_n_0 ),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I2(wl_state_r__0[0]),
        .I3(wl_state_r__0[1]),
        .I4(wl_state_r__0[2]),
        .I5(\wl_dqs_tap_count_r_reg_n_0_[0][7][1] ),
        .O(\smallest[7][1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFEFFFF00020000)) 
    \smallest[7][2]_i_1 
       (.I0(\smallest_reg[0][2]_i_2_n_0 ),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I2(wl_state_r__0[0]),
        .I3(wl_state_r__0[1]),
        .I4(wl_state_r__0[2]),
        .I5(\wl_dqs_tap_count_r_reg_n_0_[0][7][2] ),
        .O(\smallest[7][2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFEFFFF00020000)) 
    \smallest[7][3]_i_1 
       (.I0(\smallest_reg[0][3]_i_2_n_0 ),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I2(wl_state_r__0[0]),
        .I3(wl_state_r__0[1]),
        .I4(wl_state_r__0[2]),
        .I5(\wl_dqs_tap_count_r_reg_n_0_[0][7][3] ),
        .O(\smallest[7][3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFEFFFF00020000)) 
    \smallest[7][4]_i_1 
       (.I0(\smallest_reg[0][4]_i_2_n_0 ),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I2(wl_state_r__0[0]),
        .I3(wl_state_r__0[1]),
        .I4(wl_state_r__0[2]),
        .I5(\wl_dqs_tap_count_r_reg_n_0_[0][7][4] ),
        .O(\smallest[7][4]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00800000)) 
    \smallest[7][5]_i_1 
       (.I0(dqs_count_r[0]),
        .I1(dqs_count_r[1]),
        .I2(\dqs_count_r_reg[2]_rep_n_0 ),
        .I3(\dqs_count_r_reg[3]_0 ),
        .I4(\smallest[0][5]_i_3_n_0 ),
        .O(\smallest[7][5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFFFEFFFF00020000)) 
    \smallest[7][5]_i_2 
       (.I0(\smallest_reg[0][5]_i_4_n_0 ),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I2(wl_state_r__0[0]),
        .I3(wl_state_r__0[1]),
        .I4(wl_state_r__0[2]),
        .I5(\wl_dqs_tap_count_r_reg_n_0_[0][7][5] ),
        .O(\smallest[7][5]_i_2_n_0 ));
  FDRE \smallest_reg[0][0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\smallest[0][5]_i_1_n_0 ),
        .D(largest[0]),
        .Q(\smallest_reg[0]_13 [0]),
        .R(\corse_dec_reg[7][0]_0 [0]));
  MUXF7 \smallest_reg[0][0]_i_2 
       (.I0(\smallest[0][0]_i_3_n_0 ),
        .I1(\smallest[0][0]_i_4_n_0 ),
        .O(\smallest_reg[0][0]_i_2_n_0 ),
        .S(dqs_count_r[2]));
  FDRE \smallest_reg[0][1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\smallest[0][5]_i_1_n_0 ),
        .D(largest[1]),
        .Q(\smallest_reg[0]_13 [1]),
        .R(\corse_dec_reg[7][0]_0 [0]));
  MUXF7 \smallest_reg[0][1]_i_2 
       (.I0(\smallest[0][1]_i_3_n_0 ),
        .I1(\smallest[0][1]_i_4_n_0 ),
        .O(\smallest_reg[0][1]_i_2_n_0 ),
        .S(dqs_count_r[2]));
  FDRE \smallest_reg[0][2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\smallest[0][5]_i_1_n_0 ),
        .D(largest[2]),
        .Q(\smallest_reg[0]_13 [2]),
        .R(\corse_dec_reg[7][0]_0 [0]));
  MUXF7 \smallest_reg[0][2]_i_2 
       (.I0(\smallest[0][2]_i_3_n_0 ),
        .I1(\smallest[0][2]_i_4_n_0 ),
        .O(\smallest_reg[0][2]_i_2_n_0 ),
        .S(dqs_count_r[2]));
  FDRE \smallest_reg[0][3] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\smallest[0][5]_i_1_n_0 ),
        .D(largest[3]),
        .Q(\smallest_reg[0]_13 [3]),
        .R(\corse_dec_reg[7][0]_0 [0]));
  MUXF7 \smallest_reg[0][3]_i_2 
       (.I0(\smallest[0][3]_i_3_n_0 ),
        .I1(\smallest[0][3]_i_4_n_0 ),
        .O(\smallest_reg[0][3]_i_2_n_0 ),
        .S(dqs_count_r[2]));
  FDRE \smallest_reg[0][4] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\smallest[0][5]_i_1_n_0 ),
        .D(largest[4]),
        .Q(\smallest_reg[0]_13 [4]),
        .R(\corse_dec_reg[7][0]_0 [0]));
  MUXF7 \smallest_reg[0][4]_i_2 
       (.I0(\smallest[0][4]_i_3_n_0 ),
        .I1(\smallest[0][4]_i_4_n_0 ),
        .O(\smallest_reg[0][4]_i_2_n_0 ),
        .S(dqs_count_r[2]));
  FDRE \smallest_reg[0][5] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\smallest[0][5]_i_1_n_0 ),
        .D(largest[5]),
        .Q(\smallest_reg[0]_13 [5]),
        .R(\corse_dec_reg[7][0]_0 [0]));
  MUXF7 \smallest_reg[0][5]_i_4 
       (.I0(\smallest[0][5]_i_5_n_0 ),
        .I1(\smallest[0][5]_i_6_n_0 ),
        .O(\smallest_reg[0][5]_i_4_n_0 ),
        .S(dqs_count_r[2]));
  FDRE \smallest_reg[1][0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\smallest[1][5]_i_1_n_0 ),
        .D(\smallest[1][0]_i_1_n_0 ),
        .Q(\smallest_reg[1]_14 [0]),
        .R(\corse_dec_reg[7][0]_0 [0]));
  FDRE \smallest_reg[1][1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\smallest[1][5]_i_1_n_0 ),
        .D(\smallest[1][1]_i_1_n_0 ),
        .Q(\smallest_reg[1]_14 [1]),
        .R(\corse_dec_reg[7][0]_0 [0]));
  FDRE \smallest_reg[1][2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\smallest[1][5]_i_1_n_0 ),
        .D(\smallest[1][2]_i_1_n_0 ),
        .Q(\smallest_reg[1]_14 [2]),
        .R(\corse_dec_reg[7][0]_0 [0]));
  FDRE \smallest_reg[1][3] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\smallest[1][5]_i_1_n_0 ),
        .D(\smallest[1][3]_i_1_n_0 ),
        .Q(\smallest_reg[1]_14 [3]),
        .R(\corse_dec_reg[7][0]_0 [0]));
  FDRE \smallest_reg[1][4] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\smallest[1][5]_i_1_n_0 ),
        .D(\smallest[1][4]_i_1_n_0 ),
        .Q(\smallest_reg[1]_14 [4]),
        .R(\corse_dec_reg[7][0]_0 [0]));
  FDRE \smallest_reg[1][5] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\smallest[1][5]_i_1_n_0 ),
        .D(\smallest[1][5]_i_2_n_0 ),
        .Q(\smallest_reg[1]_14 [5]),
        .R(\corse_dec_reg[7][0]_0 [0]));
  FDRE \smallest_reg[2][0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\smallest[2][5]_i_1_n_0 ),
        .D(\smallest[2][0]_i_1_n_0 ),
        .Q(\smallest_reg[2]_15 [0]),
        .R(\corse_dec_reg[7][0]_0 [0]));
  FDRE \smallest_reg[2][1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\smallest[2][5]_i_1_n_0 ),
        .D(\smallest[2][1]_i_1_n_0 ),
        .Q(\smallest_reg[2]_15 [1]),
        .R(\corse_dec_reg[7][0]_0 [0]));
  FDRE \smallest_reg[2][2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\smallest[2][5]_i_1_n_0 ),
        .D(\smallest[2][2]_i_1_n_0 ),
        .Q(\smallest_reg[2]_15 [2]),
        .R(\corse_dec_reg[7][0]_0 [0]));
  FDRE \smallest_reg[2][3] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\smallest[2][5]_i_1_n_0 ),
        .D(\smallest[2][3]_i_1_n_0 ),
        .Q(\smallest_reg[2]_15 [3]),
        .R(\corse_dec_reg[7][0]_0 [0]));
  FDRE \smallest_reg[2][4] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\smallest[2][5]_i_1_n_0 ),
        .D(\smallest[2][4]_i_1_n_0 ),
        .Q(\smallest_reg[2]_15 [4]),
        .R(\corse_dec_reg[7][0]_0 [0]));
  FDRE \smallest_reg[2][5] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\smallest[2][5]_i_1_n_0 ),
        .D(\smallest[2][5]_i_2_n_0 ),
        .Q(\smallest_reg[2]_15 [5]),
        .R(\corse_dec_reg[7][0]_0 [0]));
  FDRE \smallest_reg[3][0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\smallest[3][5]_i_1_n_0 ),
        .D(\smallest[3][0]_i_1_n_0 ),
        .Q(\smallest_reg[3]_16 [0]),
        .R(\corse_dec_reg[7][0]_0 [0]));
  FDRE \smallest_reg[3][1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\smallest[3][5]_i_1_n_0 ),
        .D(\smallest[3][1]_i_1_n_0 ),
        .Q(\smallest_reg[3]_16 [1]),
        .R(\corse_dec_reg[7][0]_0 [0]));
  FDRE \smallest_reg[3][2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\smallest[3][5]_i_1_n_0 ),
        .D(\smallest[3][2]_i_1_n_0 ),
        .Q(\smallest_reg[3]_16 [2]),
        .R(\corse_dec_reg[7][0]_0 [0]));
  FDRE \smallest_reg[3][3] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\smallest[3][5]_i_1_n_0 ),
        .D(\smallest[3][3]_i_1_n_0 ),
        .Q(\smallest_reg[3]_16 [3]),
        .R(\corse_dec_reg[7][0]_0 [0]));
  FDRE \smallest_reg[3][4] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\smallest[3][5]_i_1_n_0 ),
        .D(\smallest[3][4]_i_1_n_0 ),
        .Q(\smallest_reg[3]_16 [4]),
        .R(\corse_dec_reg[7][0]_0 [0]));
  FDRE \smallest_reg[3][5] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\smallest[3][5]_i_1_n_0 ),
        .D(\smallest[3][5]_i_2_n_0 ),
        .Q(\smallest_reg[3]_16 [5]),
        .R(\corse_dec_reg[7][0]_0 [0]));
  FDRE \smallest_reg[4][0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\smallest[4][5]_i_1_n_0 ),
        .D(\smallest[4][0]_i_1_n_0 ),
        .Q(\smallest_reg[4]_17 [0]),
        .R(\corse_dec_reg[7][0]_0 [0]));
  FDRE \smallest_reg[4][1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\smallest[4][5]_i_1_n_0 ),
        .D(\smallest[4][1]_i_1_n_0 ),
        .Q(\smallest_reg[4]_17 [1]),
        .R(\corse_dec_reg[7][0]_0 [0]));
  FDRE \smallest_reg[4][2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\smallest[4][5]_i_1_n_0 ),
        .D(\smallest[4][2]_i_1_n_0 ),
        .Q(\smallest_reg[4]_17 [2]),
        .R(\corse_dec_reg[7][0]_0 [0]));
  FDRE \smallest_reg[4][3] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\smallest[4][5]_i_1_n_0 ),
        .D(\smallest[4][3]_i_1_n_0 ),
        .Q(\smallest_reg[4]_17 [3]),
        .R(\corse_dec_reg[7][0]_0 [0]));
  FDRE \smallest_reg[4][4] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\smallest[4][5]_i_1_n_0 ),
        .D(\smallest[4][4]_i_1_n_0 ),
        .Q(\smallest_reg[4]_17 [4]),
        .R(\corse_dec_reg[7][0]_0 [0]));
  FDRE \smallest_reg[4][5] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\smallest[4][5]_i_1_n_0 ),
        .D(\smallest[4][5]_i_2_n_0 ),
        .Q(\smallest_reg[4]_17 [5]),
        .R(\corse_dec_reg[7][0]_0 [0]));
  FDRE \smallest_reg[5][0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\smallest[5][5]_i_1_n_0 ),
        .D(\smallest[5][0]_i_1_n_0 ),
        .Q(\smallest_reg[5]_18 [0]),
        .R(\corse_dec_reg[7][0]_0 [0]));
  FDRE \smallest_reg[5][1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\smallest[5][5]_i_1_n_0 ),
        .D(\smallest[5][1]_i_1_n_0 ),
        .Q(\smallest_reg[5]_18 [1]),
        .R(\corse_dec_reg[7][0]_0 [0]));
  FDRE \smallest_reg[5][2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\smallest[5][5]_i_1_n_0 ),
        .D(\smallest[5][2]_i_1_n_0 ),
        .Q(\smallest_reg[5]_18 [2]),
        .R(\corse_dec_reg[7][0]_0 [0]));
  FDRE \smallest_reg[5][3] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\smallest[5][5]_i_1_n_0 ),
        .D(\smallest[5][3]_i_1_n_0 ),
        .Q(\smallest_reg[5]_18 [3]),
        .R(\corse_dec_reg[7][0]_0 [0]));
  FDRE \smallest_reg[5][4] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\smallest[5][5]_i_1_n_0 ),
        .D(\smallest[5][4]_i_1_n_0 ),
        .Q(\smallest_reg[5]_18 [4]),
        .R(\corse_dec_reg[7][0]_0 [0]));
  FDRE \smallest_reg[5][5] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\smallest[5][5]_i_1_n_0 ),
        .D(\smallest[5][5]_i_2_n_0 ),
        .Q(\smallest_reg[5]_18 [5]),
        .R(\corse_dec_reg[7][0]_0 [0]));
  FDRE \smallest_reg[6][0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\smallest[6][5]_i_1_n_0 ),
        .D(\smallest[6][0]_i_1_n_0 ),
        .Q(\smallest_reg[6]_19 [0]),
        .R(\corse_dec_reg[7][0]_0 [0]));
  FDRE \smallest_reg[6][1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\smallest[6][5]_i_1_n_0 ),
        .D(\smallest[6][1]_i_1_n_0 ),
        .Q(\smallest_reg[6]_19 [1]),
        .R(\corse_dec_reg[7][0]_0 [0]));
  FDRE \smallest_reg[6][2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\smallest[6][5]_i_1_n_0 ),
        .D(\smallest[6][2]_i_1_n_0 ),
        .Q(\smallest_reg[6]_19 [2]),
        .R(\corse_dec_reg[7][0]_0 [0]));
  FDRE \smallest_reg[6][3] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\smallest[6][5]_i_1_n_0 ),
        .D(\smallest[6][3]_i_1_n_0 ),
        .Q(\smallest_reg[6]_19 [3]),
        .R(\corse_dec_reg[7][0]_0 [0]));
  FDRE \smallest_reg[6][4] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\smallest[6][5]_i_1_n_0 ),
        .D(\smallest[6][4]_i_1_n_0 ),
        .Q(\smallest_reg[6]_19 [4]),
        .R(\corse_dec_reg[7][0]_0 [0]));
  FDRE \smallest_reg[6][5] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\smallest[6][5]_i_1_n_0 ),
        .D(\smallest[6][5]_i_2_n_0 ),
        .Q(\smallest_reg[6]_19 [5]),
        .R(\corse_dec_reg[7][0]_0 [0]));
  FDRE \smallest_reg[7][0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\smallest[7][5]_i_1_n_0 ),
        .D(\smallest[7][0]_i_1_n_0 ),
        .Q(\smallest_reg[7]_20 [0]),
        .R(\corse_dec_reg[7][0]_0 [0]));
  FDRE \smallest_reg[7][1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\smallest[7][5]_i_1_n_0 ),
        .D(\smallest[7][1]_i_1_n_0 ),
        .Q(\smallest_reg[7]_20 [1]),
        .R(\corse_dec_reg[7][0]_0 [0]));
  FDRE \smallest_reg[7][2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\smallest[7][5]_i_1_n_0 ),
        .D(\smallest[7][2]_i_1_n_0 ),
        .Q(\smallest_reg[7]_20 [2]),
        .R(\corse_dec_reg[7][0]_0 [0]));
  FDRE \smallest_reg[7][3] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\smallest[7][5]_i_1_n_0 ),
        .D(\smallest[7][3]_i_1_n_0 ),
        .Q(\smallest_reg[7]_20 [3]),
        .R(\corse_dec_reg[7][0]_0 [0]));
  FDRE \smallest_reg[7][4] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\smallest[7][5]_i_1_n_0 ),
        .D(\smallest[7][4]_i_1_n_0 ),
        .Q(\smallest_reg[7]_20 [4]),
        .R(\corse_dec_reg[7][0]_0 [0]));
  FDRE \smallest_reg[7][5] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\smallest[7][5]_i_1_n_0 ),
        .D(\smallest[7][5]_i_2_n_0 ),
        .Q(\smallest_reg[7]_20 [5]),
        .R(\corse_dec_reg[7][0]_0 [0]));
  (* SOFT_HLUTNM = "soft_lutpair305" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \stable_cnt[0]_i_1 
       (.I0(\stable_cnt_reg_n_0_[0] ),
        .O(p_0_in__1[0]));
  (* SOFT_HLUTNM = "soft_lutpair383" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \stable_cnt[1]_i_1 
       (.I0(\stable_cnt_reg_n_0_[0] ),
        .I1(\stable_cnt_reg_n_0_[1] ),
        .O(p_0_in__1[1]));
  (* SOFT_HLUTNM = "soft_lutpair383" *) 
  LUT3 #(
    .INIT(8'h6A)) 
    \stable_cnt[2]_i_1 
       (.I0(\stable_cnt_reg_n_0_[2] ),
        .I1(\stable_cnt_reg_n_0_[1] ),
        .I2(\stable_cnt_reg_n_0_[0] ),
        .O(p_0_in__1[2]));
  LUT6 #(
    .INIT(64'h55555557FFFFFFFF)) 
    \stable_cnt[3]_i_1 
       (.I0(\stable_cnt[3]_i_4_n_0 ),
        .I1(wl_state_r__0[0]),
        .I2(wl_state_r__0[1]),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I4(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I5(\stable_cnt[3]_i_5_n_0 ),
        .O(stable_cnt0));
  LUT5 #(
    .INIT(32'h00001555)) 
    \stable_cnt[3]_i_2 
       (.I0(\rd_data_edge_detect_r[7]_i_4_n_0 ),
        .I1(\stable_cnt_reg_n_0_[3] ),
        .I2(\stable_cnt_reg_n_0_[1] ),
        .I3(\stable_cnt_reg_n_0_[2] ),
        .I4(\rd_data_previous_r[7]_i_2_n_0 ),
        .O(stable_cnt));
  (* SOFT_HLUTNM = "soft_lutpair349" *) 
  LUT4 #(
    .INIT(16'h6AAA)) 
    \stable_cnt[3]_i_3 
       (.I0(\stable_cnt_reg_n_0_[3] ),
        .I1(\stable_cnt_reg_n_0_[0] ),
        .I2(\stable_cnt_reg_n_0_[1] ),
        .I3(\stable_cnt_reg_n_0_[2] ),
        .O(p_0_in__1[3]));
  LUT4 #(
    .INIT(16'h56A6)) 
    \stable_cnt[3]_i_4 
       (.I0(\rd_data_edge_detect_r_reg[7]_i_9_n_0 ),
        .I1(\stable_cnt[3]_i_6_n_0 ),
        .I2(\dqs_count_r_reg[2]_rep__0_0 ),
        .I3(\stable_cnt[3]_i_7_n_0 ),
        .O(\stable_cnt[3]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h00000000FBFB00FB)) 
    \stable_cnt[3]_i_5 
       (.I0(\stable_cnt[3]_i_8_n_0 ),
        .I1(\wl_state_r1_reg_n_0_[0] ),
        .I2(\wl_state_r1_reg_n_0_[1] ),
        .I3(\stable_cnt[3]_i_9_n_0 ),
        .I4(wl_state_r__0[1]),
        .I5(\single_rank.done_dqs_dec_reg_0 ),
        .O(\stable_cnt[3]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h505F3030505F3F3F)) 
    \stable_cnt[3]_i_6 
       (.I0(\gen_rd[3].rd_data_rise_wl_r_reg_n_0_[3] ),
        .I1(\gen_rd[2].rd_data_rise_wl_r_reg_n_0_[2] ),
        .I2(\dqs_count_r_reg[1]_rep_0 ),
        .I3(\gen_rd[1].rd_data_rise_wl_r_reg_n_0_[1] ),
        .I4(\dqs_count_r_reg[0]_rep_0 ),
        .I5(\gen_rd[0].rd_data_rise_wl_r_reg_n_0_[0] ),
        .O(\stable_cnt[3]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'h05F5030305F5F3F3)) 
    \stable_cnt[3]_i_7 
       (.I0(\gen_rd[5].rd_data_rise_wl_r_reg_n_0_[5] ),
        .I1(\gen_rd[4].rd_data_rise_wl_r_reg_n_0_[4] ),
        .I2(\dqs_count_r_reg[1]_rep_0 ),
        .I3(\gen_rd[7].rd_data_rise_wl_r_reg_n_0_[7] ),
        .I4(\dqs_count_r_reg[0]_rep_0 ),
        .I5(\gen_rd[6].rd_data_rise_wl_r_reg_n_0_[6] ),
        .O(\stable_cnt[3]_i_7_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair350" *) 
  LUT3 #(
    .INIT(8'hFB)) 
    \stable_cnt[3]_i_8 
       (.I0(\wl_state_r1_reg_n_0_[4] ),
        .I1(\wl_state_r1_reg_n_0_[2] ),
        .I2(\wl_state_r1_reg_n_0_[3] ),
        .O(\stable_cnt[3]_i_8_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair357" *) 
  LUT4 #(
    .INIT(16'h0040)) 
    \stable_cnt[3]_i_9 
       (.I0(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I1(wl_state_r__0[2]),
        .I2(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I3(wl_state_r__0[0]),
        .O(\stable_cnt[3]_i_9_n_0 ));
  FDRE \stable_cnt_reg[0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(stable_cnt),
        .D(p_0_in__1[0]),
        .Q(\stable_cnt_reg_n_0_[0] ),
        .R(stable_cnt0));
  FDRE \stable_cnt_reg[1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(stable_cnt),
        .D(p_0_in__1[1]),
        .Q(\stable_cnt_reg_n_0_[1] ),
        .R(stable_cnt0));
  FDRE \stable_cnt_reg[2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(stable_cnt),
        .D(p_0_in__1[2]),
        .Q(\stable_cnt_reg_n_0_[2] ),
        .R(stable_cnt0));
  FDRE \stable_cnt_reg[3] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(stable_cnt),
        .D(p_0_in__1[3]),
        .Q(\stable_cnt_reg_n_0_[3] ),
        .R(stable_cnt0));
  LUT1 #(
    .INIT(2'h1)) 
    \wait_cnt[0]_i_1 
       (.I0(wait_cnt_reg[0]),
        .O(wait_cnt0__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair382" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \wait_cnt[1]_i_1 
       (.I0(wait_cnt_reg[0]),
        .I1(wait_cnt_reg[1]),
        .O(\wait_cnt[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair382" *) 
  LUT3 #(
    .INIT(8'hA9)) 
    \wait_cnt[2]_i_1 
       (.I0(wait_cnt_reg[2]),
        .I1(wait_cnt_reg[1]),
        .I2(wait_cnt_reg[0]),
        .O(wait_cnt0__0[2]));
  LUT5 #(
    .INIT(32'hAAAAAAA8)) 
    \wait_cnt[3]_i_2 
       (.I0(phy_ctl_ready_r6_reg_n_0),
        .I1(wait_cnt_reg[3]),
        .I2(wait_cnt_reg[1]),
        .I3(wait_cnt_reg[0]),
        .I4(wait_cnt_reg[2]),
        .O(wait_cnt0));
  LUT4 #(
    .INIT(16'hAAA9)) 
    \wait_cnt[3]_i_3 
       (.I0(wait_cnt_reg[3]),
        .I1(wait_cnt_reg[2]),
        .I2(wait_cnt_reg[0]),
        .I3(wait_cnt_reg[1]),
        .O(wait_cnt0__0[3]));
  FDRE \wait_cnt_reg[0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(wait_cnt0),
        .D(wait_cnt0__0[0]),
        .Q(wait_cnt_reg[0]),
        .R(\wait_cnt_reg[0]_0 ));
  FDRE \wait_cnt_reg[1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(wait_cnt0),
        .D(\wait_cnt[1]_i_1_n_0 ),
        .Q(wait_cnt_reg[1]),
        .R(\wait_cnt_reg[0]_0 ));
  FDRE \wait_cnt_reg[2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(wait_cnt0),
        .D(wait_cnt0__0[2]),
        .Q(wait_cnt_reg[2]),
        .R(\wait_cnt_reg[0]_0 ));
  FDSE \wait_cnt_reg[3] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(wait_cnt0),
        .D(wait_cnt0__0[3]),
        .Q(wait_cnt_reg[3]),
        .S(\wait_cnt_reg[0]_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \wl_corse_cnt[0][0][0]_i_2 
       (.I0(\corse_cnt_reg_n_0_[3][0] ),
        .I1(\corse_cnt_reg_n_0_[2][0] ),
        .I2(\dqs_count_r_reg[1]_rep_0 ),
        .I3(\corse_cnt_reg_n_0_[1][0] ),
        .I4(\dqs_count_r_reg[0]_rep_0 ),
        .I5(\corse_cnt_reg_n_0_[0][0] ),
        .O(\wl_corse_cnt[0][0][0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \wl_corse_cnt[0][0][0]_i_3 
       (.I0(\corse_cnt_reg_n_0_[7][0] ),
        .I1(\corse_cnt_reg_n_0_[6][0] ),
        .I2(\dqs_count_r_reg[1]_rep_0 ),
        .I3(\corse_cnt_reg_n_0_[5][0] ),
        .I4(\dqs_count_r_reg[0]_rep_0 ),
        .I5(\corse_cnt_reg_n_0_[4][0] ),
        .O(\wl_corse_cnt[0][0][0]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \wl_corse_cnt[0][0][1]_i_2 
       (.I0(\corse_cnt_reg_n_0_[3][1] ),
        .I1(\corse_cnt_reg_n_0_[2][1] ),
        .I2(\dqs_count_r_reg[1]_rep_0 ),
        .I3(\corse_cnt_reg_n_0_[1][1] ),
        .I4(\dqs_count_r_reg[0]_rep_0 ),
        .I5(\corse_cnt_reg_n_0_[0][1] ),
        .O(\wl_corse_cnt[0][0][1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \wl_corse_cnt[0][0][1]_i_3 
       (.I0(\corse_cnt_reg_n_0_[7][1] ),
        .I1(\corse_cnt_reg_n_0_[6][1] ),
        .I2(\dqs_count_r_reg[1]_rep_0 ),
        .I3(\corse_cnt_reg_n_0_[5][1] ),
        .I4(\dqs_count_r_reg[0]_rep_0 ),
        .I5(\corse_cnt_reg_n_0_[4][1] ),
        .O(\wl_corse_cnt[0][0][1]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \wl_corse_cnt[0][0][2]_i_2 
       (.I0(\corse_cnt_reg_n_0_[3][2] ),
        .I1(\corse_cnt_reg_n_0_[2][2] ),
        .I2(\dqs_count_r_reg[1]_rep_0 ),
        .I3(\corse_cnt_reg_n_0_[1][2] ),
        .I4(\dqs_count_r_reg[0]_rep_0 ),
        .I5(\corse_cnt_reg_n_0_[0][2] ),
        .O(\wl_corse_cnt[0][0][2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \wl_corse_cnt[0][0][2]_i_3 
       (.I0(\corse_cnt_reg_n_0_[7][2] ),
        .I1(\corse_cnt_reg_n_0_[6][2] ),
        .I2(\dqs_count_r_reg[1]_rep_0 ),
        .I3(\corse_cnt_reg_n_0_[5][2] ),
        .I4(\dqs_count_r_reg[0]_rep_0 ),
        .I5(\corse_cnt_reg_n_0_[4][2] ),
        .O(\wl_corse_cnt[0][0][2]_i_3_n_0 ));
  FDRE \wl_corse_cnt_reg[0][0][0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(wl_corse_cnt),
        .D(\wl_corse_cnt_reg[0][0][0]_i_1_n_0 ),
        .Q(\wl_corse_cnt_reg[0][0]_29 [0]),
        .R(\corse_inc_reg[6][2]_0 [1]));
  MUXF7 \wl_corse_cnt_reg[0][0][0]_i_1 
       (.I0(\wl_corse_cnt[0][0][0]_i_2_n_0 ),
        .I1(\wl_corse_cnt[0][0][0]_i_3_n_0 ),
        .O(\wl_corse_cnt_reg[0][0][0]_i_1_n_0 ),
        .S(dqs_count_r[2]));
  FDRE \wl_corse_cnt_reg[0][0][1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(wl_corse_cnt),
        .D(\wl_corse_cnt_reg[0][0][1]_i_1_n_0 ),
        .Q(\wl_corse_cnt_reg[0][0]_29 [1]),
        .R(\corse_inc_reg[6][2]_0 [1]));
  MUXF7 \wl_corse_cnt_reg[0][0][1]_i_1 
       (.I0(\wl_corse_cnt[0][0][1]_i_2_n_0 ),
        .I1(\wl_corse_cnt[0][0][1]_i_3_n_0 ),
        .O(\wl_corse_cnt_reg[0][0][1]_i_1_n_0 ),
        .S(dqs_count_r[2]));
  FDRE \wl_corse_cnt_reg[0][0][2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(wl_corse_cnt),
        .D(\wl_corse_cnt_reg[0][0][2]_i_1_n_0 ),
        .Q(\wl_corse_cnt_reg[0][0]_29 [2]),
        .R(\corse_inc_reg[6][2]_0 [1]));
  MUXF7 \wl_corse_cnt_reg[0][0][2]_i_1 
       (.I0(\wl_corse_cnt[0][0][2]_i_2_n_0 ),
        .I1(\wl_corse_cnt[0][0][2]_i_3_n_0 ),
        .O(\wl_corse_cnt_reg[0][0][2]_i_1_n_0 ),
        .S(dqs_count_r[2]));
  FDRE \wl_corse_cnt_reg[0][1][0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\wl_dqs_tap_count_r[0][1][5]_i_1_n_0 ),
        .D(\wl_corse_cnt_reg[0][0][0]_i_1_n_0 ),
        .Q(\wl_corse_cnt_reg[0][1]_30 [0]),
        .R(\wl_dqs_tap_count_r_reg[0][5][5]_0 ));
  FDRE \wl_corse_cnt_reg[0][1][1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\wl_dqs_tap_count_r[0][1][5]_i_1_n_0 ),
        .D(\wl_corse_cnt_reg[0][0][1]_i_1_n_0 ),
        .Q(\wl_corse_cnt_reg[0][1]_30 [1]),
        .R(\wl_dqs_tap_count_r_reg[0][5][5]_0 ));
  FDRE \wl_corse_cnt_reg[0][1][2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\wl_dqs_tap_count_r[0][1][5]_i_1_n_0 ),
        .D(\wl_corse_cnt_reg[0][0][2]_i_1_n_0 ),
        .Q(\wl_corse_cnt_reg[0][1]_30 [2]),
        .R(\wl_dqs_tap_count_r_reg[0][5][5]_0 ));
  FDRE \wl_corse_cnt_reg[0][2][0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\wl_dqs_tap_count_r[0][2][5]_i_1_n_0 ),
        .D(\wl_corse_cnt_reg[0][0][0]_i_1_n_0 ),
        .Q(\wl_corse_cnt_reg[0][2]_31 [0]),
        .R(\corse_inc_reg[6][2]_0 [1]));
  FDRE \wl_corse_cnt_reg[0][2][1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\wl_dqs_tap_count_r[0][2][5]_i_1_n_0 ),
        .D(\wl_corse_cnt_reg[0][0][1]_i_1_n_0 ),
        .Q(\wl_corse_cnt_reg[0][2]_31 [1]),
        .R(\corse_inc_reg[6][2]_0 [1]));
  FDRE \wl_corse_cnt_reg[0][2][2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\wl_dqs_tap_count_r[0][2][5]_i_1_n_0 ),
        .D(\wl_corse_cnt_reg[0][0][2]_i_1_n_0 ),
        .Q(\wl_corse_cnt_reg[0][2]_31 [2]),
        .R(\corse_inc_reg[6][2]_0 [1]));
  FDRE \wl_corse_cnt_reg[0][3][0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\wl_dqs_tap_count_r[0][3][5]_i_1_n_0 ),
        .D(\wl_corse_cnt_reg[0][0][0]_i_1_n_0 ),
        .Q(\wl_corse_cnt_reg[0][3]_32 [0]),
        .R(\wl_dqs_tap_count_r_reg[0][5][5]_0 ));
  FDRE \wl_corse_cnt_reg[0][3][1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\wl_dqs_tap_count_r[0][3][5]_i_1_n_0 ),
        .D(\wl_corse_cnt_reg[0][0][1]_i_1_n_0 ),
        .Q(\wl_corse_cnt_reg[0][3]_32 [1]),
        .R(\wl_dqs_tap_count_r_reg[0][5][5]_0 ));
  FDRE \wl_corse_cnt_reg[0][3][2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\wl_dqs_tap_count_r[0][3][5]_i_1_n_0 ),
        .D(\wl_corse_cnt_reg[0][0][2]_i_1_n_0 ),
        .Q(\wl_corse_cnt_reg[0][3]_32 [2]),
        .R(\wl_dqs_tap_count_r_reg[0][5][5]_0 ));
  FDRE \wl_corse_cnt_reg[0][4][0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\wl_dqs_tap_count_r[0][4][5]_i_1_n_0 ),
        .D(\wl_corse_cnt_reg[0][0][0]_i_1_n_0 ),
        .Q(\wl_corse_cnt_reg[0][4]_33 [0]),
        .R(\corse_inc_reg[6][2]_0 [1]));
  FDRE \wl_corse_cnt_reg[0][4][1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\wl_dqs_tap_count_r[0][4][5]_i_1_n_0 ),
        .D(\wl_corse_cnt_reg[0][0][1]_i_1_n_0 ),
        .Q(\wl_corse_cnt_reg[0][4]_33 [1]),
        .R(\corse_inc_reg[6][2]_0 [1]));
  FDRE \wl_corse_cnt_reg[0][4][2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\wl_dqs_tap_count_r[0][4][5]_i_1_n_0 ),
        .D(\wl_corse_cnt_reg[0][0][2]_i_1_n_0 ),
        .Q(\wl_corse_cnt_reg[0][4]_33 [2]),
        .R(\corse_inc_reg[6][2]_0 [1]));
  FDRE \wl_corse_cnt_reg[0][5][0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\wl_dqs_tap_count_r[0][5][5]_i_1_n_0 ),
        .D(\wl_corse_cnt_reg[0][0][0]_i_1_n_0 ),
        .Q(\wl_corse_cnt_reg[0][5]_34 [0]),
        .R(\wl_dqs_tap_count_r_reg[0][5][5]_0 ));
  FDRE \wl_corse_cnt_reg[0][5][1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\wl_dqs_tap_count_r[0][5][5]_i_1_n_0 ),
        .D(\wl_corse_cnt_reg[0][0][1]_i_1_n_0 ),
        .Q(\wl_corse_cnt_reg[0][5]_34 [1]),
        .R(\wl_dqs_tap_count_r_reg[0][5][5]_0 ));
  FDRE \wl_corse_cnt_reg[0][5][2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\wl_dqs_tap_count_r[0][5][5]_i_1_n_0 ),
        .D(\wl_corse_cnt_reg[0][0][2]_i_1_n_0 ),
        .Q(\wl_corse_cnt_reg[0][5]_34 [2]),
        .R(\wl_dqs_tap_count_r_reg[0][5][5]_0 ));
  FDRE \wl_corse_cnt_reg[0][6][0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\wl_dqs_tap_count_r[0][6][5]_i_1_n_0 ),
        .D(\wl_corse_cnt_reg[0][0][0]_i_1_n_0 ),
        .Q(\wl_corse_cnt_reg[0][6]_35 [0]),
        .R(\corse_inc_reg[6][2]_0 [0]));
  FDRE \wl_corse_cnt_reg[0][6][1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\wl_dqs_tap_count_r[0][6][5]_i_1_n_0 ),
        .D(\wl_corse_cnt_reg[0][0][1]_i_1_n_0 ),
        .Q(\wl_corse_cnt_reg[0][6]_35 [1]),
        .R(\corse_inc_reg[6][2]_0 [0]));
  FDRE \wl_corse_cnt_reg[0][6][2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\wl_dqs_tap_count_r[0][6][5]_i_1_n_0 ),
        .D(\wl_corse_cnt_reg[0][0][2]_i_1_n_0 ),
        .Q(\wl_corse_cnt_reg[0][6]_35 [2]),
        .R(\corse_inc_reg[6][2]_0 [1]));
  FDRE \wl_corse_cnt_reg[0][7][0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\wl_dqs_tap_count_r[0][7][5]_i_1_n_0 ),
        .D(\wl_corse_cnt_reg[0][0][0]_i_1_n_0 ),
        .Q(\wl_corse_cnt_reg[0][7]_36 [0]),
        .R(\wl_dqs_tap_count_r_reg[0][5][5]_0 ));
  FDRE \wl_corse_cnt_reg[0][7][1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\wl_dqs_tap_count_r[0][7][5]_i_1_n_0 ),
        .D(\wl_corse_cnt_reg[0][0][1]_i_1_n_0 ),
        .Q(\wl_corse_cnt_reg[0][7]_36 [1]),
        .R(\wl_dqs_tap_count_r_reg[0][5][5]_0 ));
  FDRE \wl_corse_cnt_reg[0][7][2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\wl_dqs_tap_count_r[0][7][5]_i_1_n_0 ),
        .D(\wl_corse_cnt_reg[0][0][2]_i_1_n_0 ),
        .Q(\wl_corse_cnt_reg[0][7]_36 [2]),
        .R(\wl_dqs_tap_count_r_reg[0][5][5]_0 ));
  LUT5 #(
    .INIT(32'h00010000)) 
    \wl_dqs_tap_count_r[0][0][5]_i_1 
       (.I0(\dqs_count_r_reg[3]_0 ),
        .I1(\dqs_count_r_reg[2]_rep_n_0 ),
        .I2(dqs_count_r[1]),
        .I3(dqs_count_r[0]),
        .I4(\wl_dqs_tap_count_r[0][0][5]_i_2_n_0 ),
        .O(wl_corse_cnt));
  LUT6 #(
    .INIT(64'h00000000000220A0)) 
    \wl_dqs_tap_count_r[0][0][5]_i_2 
       (.I0(\wl_dqs_tap_count_r[0][0][5]_i_3_n_0 ),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I2(wl_state_r__0[2]),
        .I3(wl_state_r__0[1]),
        .I4(wl_state_r__0[0]),
        .I5(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .O(\wl_dqs_tap_count_r[0][0][5]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair334" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \wl_dqs_tap_count_r[0][0][5]_i_3 
       (.I0(\rank_cnt_r_reg_n_0_[0] ),
        .I1(\rank_cnt_r_reg_n_0_[1] ),
        .O(\wl_dqs_tap_count_r[0][0][5]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'h00000200)) 
    \wl_dqs_tap_count_r[0][1][5]_i_1 
       (.I0(\wl_dqs_tap_count_r[0][0][5]_i_2_n_0 ),
        .I1(\dqs_count_r_reg[3]_0 ),
        .I2(\dqs_count_r_reg[2]_rep_n_0 ),
        .I3(dqs_count_r[0]),
        .I4(dqs_count_r[1]),
        .O(\wl_dqs_tap_count_r[0][1][5]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00000200)) 
    \wl_dqs_tap_count_r[0][2][5]_i_1 
       (.I0(\wl_dqs_tap_count_r[0][0][5]_i_2_n_0 ),
        .I1(\dqs_count_r_reg[3]_0 ),
        .I2(\dqs_count_r_reg[2]_rep_n_0 ),
        .I3(dqs_count_r[1]),
        .I4(dqs_count_r[0]),
        .O(\wl_dqs_tap_count_r[0][2][5]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00000080)) 
    \wl_dqs_tap_count_r[0][3][5]_i_1 
       (.I0(\wl_dqs_tap_count_r[0][0][5]_i_2_n_0 ),
        .I1(dqs_count_r[1]),
        .I2(dqs_count_r[0]),
        .I3(\dqs_count_r_reg[3]_0 ),
        .I4(\dqs_count_r_reg[2]_rep_n_0 ),
        .O(\wl_dqs_tap_count_r[0][3][5]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00000020)) 
    \wl_dqs_tap_count_r[0][4][5]_i_1 
       (.I0(\wl_dqs_tap_count_r[0][0][5]_i_2_n_0 ),
        .I1(\dqs_count_r_reg[3]_0 ),
        .I2(\dqs_count_r_reg[2]_rep_n_0 ),
        .I3(dqs_count_r[1]),
        .I4(dqs_count_r[0]),
        .O(\wl_dqs_tap_count_r[0][4][5]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00002000)) 
    \wl_dqs_tap_count_r[0][5][5]_i_1 
       (.I0(\wl_dqs_tap_count_r[0][0][5]_i_2_n_0 ),
        .I1(\dqs_count_r_reg[3]_0 ),
        .I2(\dqs_count_r_reg[2]_rep_n_0 ),
        .I3(dqs_count_r[0]),
        .I4(dqs_count_r[1]),
        .O(\wl_dqs_tap_count_r[0][5][5]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00002000)) 
    \wl_dqs_tap_count_r[0][6][5]_i_1 
       (.I0(\wl_dqs_tap_count_r[0][0][5]_i_2_n_0 ),
        .I1(\dqs_count_r_reg[3]_0 ),
        .I2(\dqs_count_r_reg[2]_rep_n_0 ),
        .I3(dqs_count_r[1]),
        .I4(dqs_count_r[0]),
        .O(\wl_dqs_tap_count_r[0][6][5]_i_1_n_0 ));
  LUT5 #(
    .INIT(32'h00008000)) 
    \wl_dqs_tap_count_r[0][7][5]_i_1 
       (.I0(\wl_dqs_tap_count_r[0][0][5]_i_2_n_0 ),
        .I1(dqs_count_r[0]),
        .I2(dqs_count_r[1]),
        .I3(\dqs_count_r_reg[2]_rep_n_0 ),
        .I4(\dqs_count_r_reg[3]_0 ),
        .O(\wl_dqs_tap_count_r[0][7][5]_i_1_n_0 ));
  FDRE \wl_dqs_tap_count_r_reg[0][0][0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(wl_corse_cnt),
        .D(\wl_tap_count_r_reg_n_0_[0] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][0][0] ),
        .R(\fine_inc_reg[6][3]_0 [0]));
  FDRE \wl_dqs_tap_count_r_reg[0][0][1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(wl_corse_cnt),
        .D(\wl_tap_count_r_reg_n_0_[1] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][0][1] ),
        .R(\fine_inc_reg[6][3]_0 [0]));
  FDRE \wl_dqs_tap_count_r_reg[0][0][2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(wl_corse_cnt),
        .D(\wl_tap_count_r_reg_n_0_[2] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][0][2] ),
        .R(\fine_inc_reg[6][3]_0 [0]));
  FDRE \wl_dqs_tap_count_r_reg[0][0][3] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(wl_corse_cnt),
        .D(\wl_tap_count_r_reg_n_0_[3] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][0][3] ),
        .R(\fine_inc_reg[6][3]_0 [0]));
  FDRE \wl_dqs_tap_count_r_reg[0][0][4] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(wl_corse_cnt),
        .D(\wl_tap_count_r_reg_n_0_[4] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][0][4] ),
        .R(\fine_inc_reg[6][3]_0 [0]));
  FDRE \wl_dqs_tap_count_r_reg[0][0][5] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(wl_corse_cnt),
        .D(\wl_tap_count_r_reg_n_0_[5] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][0][5] ),
        .R(\fine_inc_reg[6][3]_0 [0]));
  FDRE \wl_dqs_tap_count_r_reg[0][1][0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\wl_dqs_tap_count_r[0][1][5]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[0] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][1][0] ),
        .R(\fine_inc_reg[6][3]_0 [1]));
  FDRE \wl_dqs_tap_count_r_reg[0][1][1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\wl_dqs_tap_count_r[0][1][5]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[1] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][1][1] ),
        .R(\fine_inc_reg[6][3]_0 [1]));
  FDRE \wl_dqs_tap_count_r_reg[0][1][2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\wl_dqs_tap_count_r[0][1][5]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[2] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][1][2] ),
        .R(\fine_inc_reg[6][3]_0 [1]));
  FDRE \wl_dqs_tap_count_r_reg[0][1][3] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\wl_dqs_tap_count_r[0][1][5]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[3] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][1][3] ),
        .R(\fine_inc_reg[6][3]_0 [1]));
  FDRE \wl_dqs_tap_count_r_reg[0][1][4] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\wl_dqs_tap_count_r[0][1][5]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[4] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][1][4] ),
        .R(\fine_inc_reg[6][3]_0 [0]));
  FDRE \wl_dqs_tap_count_r_reg[0][1][5] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\wl_dqs_tap_count_r[0][1][5]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[5] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][1][5] ),
        .R(\fine_inc_reg[6][3]_0 [0]));
  FDRE \wl_dqs_tap_count_r_reg[0][2][0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\wl_dqs_tap_count_r[0][2][5]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[0] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][2][0] ),
        .R(\fine_inc_reg[6][3]_0 [0]));
  FDRE \wl_dqs_tap_count_r_reg[0][2][1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\wl_dqs_tap_count_r[0][2][5]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[1] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][2][1] ),
        .R(\fine_inc_reg[6][3]_0 [0]));
  FDRE \wl_dqs_tap_count_r_reg[0][2][2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\wl_dqs_tap_count_r[0][2][5]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[2] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][2][2] ),
        .R(\fine_inc_reg[6][3]_0 [0]));
  FDRE \wl_dqs_tap_count_r_reg[0][2][3] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\wl_dqs_tap_count_r[0][2][5]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[3] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][2][3] ),
        .R(\fine_inc_reg[6][3]_0 [0]));
  FDRE \wl_dqs_tap_count_r_reg[0][2][4] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\wl_dqs_tap_count_r[0][2][5]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[4] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][2][4] ),
        .R(\fine_inc_reg[6][3]_0 [0]));
  FDRE \wl_dqs_tap_count_r_reg[0][2][5] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\wl_dqs_tap_count_r[0][2][5]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[5] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][2][5] ),
        .R(\fine_inc_reg[6][3]_0 [0]));
  FDRE \wl_dqs_tap_count_r_reg[0][3][0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\wl_dqs_tap_count_r[0][3][5]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[0] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][3][0] ),
        .R(\fine_inc_reg[6][3]_0 [1]));
  FDRE \wl_dqs_tap_count_r_reg[0][3][1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\wl_dqs_tap_count_r[0][3][5]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[1] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][3][1] ),
        .R(\fine_inc_reg[6][3]_0 [1]));
  FDRE \wl_dqs_tap_count_r_reg[0][3][2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\wl_dqs_tap_count_r[0][3][5]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[2] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][3][2] ),
        .R(\fine_inc_reg[6][3]_0 [1]));
  FDRE \wl_dqs_tap_count_r_reg[0][3][3] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\wl_dqs_tap_count_r[0][3][5]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[3] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][3][3] ),
        .R(\fine_inc_reg[6][3]_0 [1]));
  FDRE \wl_dqs_tap_count_r_reg[0][3][4] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\wl_dqs_tap_count_r[0][3][5]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[4] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][3][4] ),
        .R(\fine_inc_reg[6][3]_0 [1]));
  FDRE \wl_dqs_tap_count_r_reg[0][3][5] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\wl_dqs_tap_count_r[0][3][5]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[5] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][3][5] ),
        .R(\fine_inc_reg[6][3]_0 [1]));
  FDRE \wl_dqs_tap_count_r_reg[0][4][0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\wl_dqs_tap_count_r[0][4][5]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[0] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][4][0] ),
        .R(\fine_inc_reg[6][3]_0 [0]));
  FDRE \wl_dqs_tap_count_r_reg[0][4][1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\wl_dqs_tap_count_r[0][4][5]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[1] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][4][1] ),
        .R(\fine_inc_reg[6][3]_0 [0]));
  FDRE \wl_dqs_tap_count_r_reg[0][4][2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\wl_dqs_tap_count_r[0][4][5]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[2] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][4][2] ),
        .R(\fine_inc_reg[6][3]_0 [0]));
  FDRE \wl_dqs_tap_count_r_reg[0][4][3] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\wl_dqs_tap_count_r[0][4][5]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[3] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][4][3] ),
        .R(\fine_inc_reg[6][3]_0 [0]));
  FDRE \wl_dqs_tap_count_r_reg[0][4][4] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\wl_dqs_tap_count_r[0][4][5]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[4] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][4][4] ),
        .R(\fine_inc_reg[6][3]_0 [0]));
  FDRE \wl_dqs_tap_count_r_reg[0][4][5] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\wl_dqs_tap_count_r[0][4][5]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[5] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][4][5] ),
        .R(\fine_inc_reg[6][3]_0 [0]));
  FDRE \wl_dqs_tap_count_r_reg[0][5][0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\wl_dqs_tap_count_r[0][5][5]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[0] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][5][0] ),
        .R(\wl_dqs_tap_count_r_reg[0][5][5]_0 ));
  FDRE \wl_dqs_tap_count_r_reg[0][5][1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\wl_dqs_tap_count_r[0][5][5]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[1] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][5][1] ),
        .R(\wl_dqs_tap_count_r_reg[0][5][5]_0 ));
  FDRE \wl_dqs_tap_count_r_reg[0][5][2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\wl_dqs_tap_count_r[0][5][5]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[2] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][5][2] ),
        .R(\wl_dqs_tap_count_r_reg[0][5][5]_0 ));
  FDRE \wl_dqs_tap_count_r_reg[0][5][3] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\wl_dqs_tap_count_r[0][5][5]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[3] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][5][3] ),
        .R(\wl_dqs_tap_count_r_reg[0][5][5]_0 ));
  FDRE \wl_dqs_tap_count_r_reg[0][5][4] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\wl_dqs_tap_count_r[0][5][5]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[4] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][5][4] ),
        .R(\wl_dqs_tap_count_r_reg[0][5][5]_0 ));
  FDRE \wl_dqs_tap_count_r_reg[0][5][5] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\wl_dqs_tap_count_r[0][5][5]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[5] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][5][5] ),
        .R(\wl_dqs_tap_count_r_reg[0][5][5]_0 ));
  FDRE \wl_dqs_tap_count_r_reg[0][6][0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\wl_dqs_tap_count_r[0][6][5]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[0] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][6][0] ),
        .R(\corse_dec_reg[7][0]_0 [0]));
  FDRE \wl_dqs_tap_count_r_reg[0][6][1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\wl_dqs_tap_count_r[0][6][5]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[1] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][6][1] ),
        .R(\corse_dec_reg[7][0]_0 [1]));
  FDRE \wl_dqs_tap_count_r_reg[0][6][2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\wl_dqs_tap_count_r[0][6][5]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[2] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][6][2] ),
        .R(\corse_dec_reg[7][0]_0 [1]));
  FDRE \wl_dqs_tap_count_r_reg[0][6][3] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\wl_dqs_tap_count_r[0][6][5]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[3] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][6][3] ),
        .R(\fine_inc_reg[6][3]_0 [0]));
  FDRE \wl_dqs_tap_count_r_reg[0][6][4] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\wl_dqs_tap_count_r[0][6][5]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[4] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][6][4] ),
        .R(\fine_inc_reg[6][3]_0 [0]));
  FDRE \wl_dqs_tap_count_r_reg[0][6][5] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\wl_dqs_tap_count_r[0][6][5]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[5] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][6][5] ),
        .R(\fine_inc_reg[6][3]_0 [0]));
  FDRE \wl_dqs_tap_count_r_reg[0][7][0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\wl_dqs_tap_count_r[0][7][5]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[0] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][7][0] ),
        .R(\wl_dqs_tap_count_r_reg[0][5][5]_0 ));
  FDRE \wl_dqs_tap_count_r_reg[0][7][1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\wl_dqs_tap_count_r[0][7][5]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[1] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][7][1] ),
        .R(\wl_dqs_tap_count_r_reg[0][5][5]_0 ));
  FDRE \wl_dqs_tap_count_r_reg[0][7][2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\wl_dqs_tap_count_r[0][7][5]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[2] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][7][2] ),
        .R(\wl_dqs_tap_count_r_reg[0][5][5]_0 ));
  FDRE \wl_dqs_tap_count_r_reg[0][7][3] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\wl_dqs_tap_count_r[0][7][5]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[3] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][7][3] ),
        .R(\wl_dqs_tap_count_r_reg[0][5][5]_0 ));
  FDRE \wl_dqs_tap_count_r_reg[0][7][4] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\wl_dqs_tap_count_r[0][7][5]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[4] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][7][4] ),
        .R(\wl_dqs_tap_count_r_reg[0][5][5]_0 ));
  FDRE \wl_dqs_tap_count_r_reg[0][7][5] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\wl_dqs_tap_count_r[0][7][5]_i_1_n_0 ),
        .D(\wl_tap_count_r_reg_n_0_[5] ),
        .Q(\wl_dqs_tap_count_r_reg_n_0_[0][7][5] ),
        .R(\wl_dqs_tap_count_r_reg[0][5][5]_0 ));
  LUT6 #(
    .INIT(64'hAEAAAA2AA88AA8A8)) 
    wl_edge_detect_valid_r_i_1
       (.I0(wl_edge_detect_valid_r_reg_n_0),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I2(wl_state_r__0[2]),
        .I3(wl_state_r__0[1]),
        .I4(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I5(wl_state_r__0[0]),
        .O(wl_edge_detect_valid_r_i_1_n_0));
  FDRE wl_edge_detect_valid_r_reg
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(wl_edge_detect_valid_r_i_1_n_0),
        .Q(wl_edge_detect_valid_r_reg_n_0),
        .R(\wl_dqs_tap_count_r_reg[0][5][5]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair342" *) 
  LUT5 #(
    .INIT(32'h9293ADAE)) 
    \wl_state_r1[0]_i_1 
       (.I0(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I1(wl_state_r__0[1]),
        .I2(wl_state_r__0[0]),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I4(wl_state_r__0[2]),
        .O(\wl_state_r1[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair333" *) 
  LUT5 #(
    .INIT(32'h04FF0C3F)) 
    \wl_state_r1[1]_i_1 
       (.I0(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I1(wl_state_r__0[0]),
        .I2(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I3(wl_state_r__0[1]),
        .I4(wl_state_r__0[2]),
        .O(\wl_state_r1[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair342" *) 
  LUT5 #(
    .INIT(32'h37D83005)) 
    \wl_state_r1[2]_i_1 
       (.I0(wl_state_r__0[2]),
        .I1(wl_state_r__0[1]),
        .I2(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I3(wl_state_r__0[0]),
        .I4(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .O(\wl_state_r1[2]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair343" *) 
  LUT5 #(
    .INIT(32'hC2808775)) 
    \wl_state_r1[3]_i_1 
       (.I0(wl_state_r__0[2]),
        .I1(wl_state_r__0[0]),
        .I2(wl_state_r__0[1]),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I4(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .O(\wl_state_r1[3]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair341" *) 
  LUT5 #(
    .INIT(32'hDEC5E214)) 
    \wl_state_r1[4]_i_1 
       (.I0(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I1(wl_state_r__0[2]),
        .I2(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I3(wl_state_r__0[1]),
        .I4(wl_state_r__0[0]),
        .O(\wl_state_r1[4]_i_1_n_0 ));
  FDRE \wl_state_r1_reg[0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\wl_state_r1[0]_i_1_n_0 ),
        .Q(\wl_state_r1_reg_n_0_[0] ),
        .R(\corse_inc_reg[6][2]_0 [0]));
  FDRE \wl_state_r1_reg[1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\wl_state_r1[1]_i_1_n_0 ),
        .Q(\wl_state_r1_reg_n_0_[1] ),
        .R(\corse_inc_reg[6][2]_0 [0]));
  FDRE \wl_state_r1_reg[2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\wl_state_r1[2]_i_1_n_0 ),
        .Q(\wl_state_r1_reg_n_0_[2] ),
        .R(\corse_inc_reg[6][2]_0 [0]));
  FDRE \wl_state_r1_reg[3] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\wl_state_r1[3]_i_1_n_0 ),
        .Q(\wl_state_r1_reg_n_0_[3] ),
        .R(\corse_inc_reg[6][2]_0 [0]));
  FDRE \wl_state_r1_reg[4] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\wl_state_r1[4]_i_1_n_0 ),
        .Q(\wl_state_r1_reg_n_0_[4] ),
        .R(\corse_inc_reg[6][2]_0 [0]));
  LUT6 #(
    .INIT(64'h80808080808C8C8C)) 
    \wl_tap_count_r[0]_i_1 
       (.I0(\wl_tap_count_r_reg[0]_i_2_n_0 ),
        .I1(\wl_tap_count_r[4]_i_4_n_0 ),
        .I2(wl_state_r__0[1]),
        .I3(wr_level_done_r5),
        .I4(wl_state_r__0[0]),
        .I5(\wl_tap_count_r_reg_n_0_[0] ),
        .O(wl_tap_count_r[0]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \wl_tap_count_r[0]_i_3 
       (.I0(\smallest_reg[3]_16 [0]),
        .I1(\smallest_reg[2]_15 [0]),
        .I2(\dqs_count_r_reg[3]_1 [1]),
        .I3(\smallest_reg[1]_14 [0]),
        .I4(\dqs_count_r_reg[3]_1 [0]),
        .I5(\smallest_reg[0]_13 [0]),
        .O(\wl_tap_count_r[0]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \wl_tap_count_r[0]_i_4 
       (.I0(\smallest_reg[7]_20 [0]),
        .I1(\smallest_reg[6]_19 [0]),
        .I2(\dqs_count_r_reg[3]_1 [1]),
        .I3(\smallest_reg[5]_18 [0]),
        .I4(\dqs_count_r_reg[3]_1 [0]),
        .I5(\smallest_reg[4]_17 [0]),
        .O(\wl_tap_count_r[0]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h80808080808C8C80)) 
    \wl_tap_count_r[1]_i_1 
       (.I0(\wl_tap_count_r_reg[1]_i_2_n_0 ),
        .I1(\wl_tap_count_r[4]_i_4_n_0 ),
        .I2(wl_state_r__0[1]),
        .I3(\wl_tap_count_r_reg_n_0_[0] ),
        .I4(\wl_tap_count_r_reg_n_0_[1] ),
        .I5(\wl_tap_count_r[4]_i_2_n_0 ),
        .O(wl_tap_count_r[1]));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \wl_tap_count_r[1]_i_3 
       (.I0(\smallest_reg[3]_16 [1]),
        .I1(\smallest_reg[2]_15 [1]),
        .I2(\dqs_count_r_reg[3]_1 [1]),
        .I3(\smallest_reg[1]_14 [1]),
        .I4(\dqs_count_r_reg[3]_1 [0]),
        .I5(\smallest_reg[0]_13 [1]),
        .O(\wl_tap_count_r[1]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \wl_tap_count_r[1]_i_4 
       (.I0(\smallest_reg[7]_20 [1]),
        .I1(\smallest_reg[6]_19 [1]),
        .I2(\dqs_count_r_reg[3]_1 [1]),
        .I3(\smallest_reg[5]_18 [1]),
        .I4(\dqs_count_r_reg[3]_1 [0]),
        .I5(\smallest_reg[4]_17 [1]),
        .O(\wl_tap_count_r[1]_i_4_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair335" *) 
  LUT5 #(
    .INIT(32'h00008A00)) 
    \wl_tap_count_r[2]_i_1 
       (.I0(\wl_tap_count_r[2]_i_2_n_0 ),
        .I1(\wl_tap_count_r_reg[2]_i_3_n_0 ),
        .I2(wl_state_r__0[1]),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I4(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .O(wl_tap_count_r[2]));
  LUT6 #(
    .INIT(64'hAAAABEEEBEEEBEEE)) 
    \wl_tap_count_r[2]_i_2 
       (.I0(wl_state_r__0[1]),
        .I1(\wl_tap_count_r_reg_n_0_[2] ),
        .I2(\wl_tap_count_r_reg_n_0_[0] ),
        .I3(\wl_tap_count_r_reg_n_0_[1] ),
        .I4(wl_state_r__0[0]),
        .I5(wr_level_done_r5),
        .O(\wl_tap_count_r[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \wl_tap_count_r[2]_i_4 
       (.I0(\smallest_reg[3]_16 [2]),
        .I1(\smallest_reg[2]_15 [2]),
        .I2(\dqs_count_r_reg[3]_1 [1]),
        .I3(\smallest_reg[1]_14 [2]),
        .I4(\dqs_count_r_reg[3]_1 [0]),
        .I5(\smallest_reg[0]_13 [2]),
        .O(\wl_tap_count_r[2]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \wl_tap_count_r[2]_i_5 
       (.I0(\smallest_reg[7]_20 [2]),
        .I1(\smallest_reg[6]_19 [2]),
        .I2(\dqs_count_r_reg[3]_1 [1]),
        .I3(\smallest_reg[5]_18 [2]),
        .I4(\dqs_count_r_reg[3]_1 [0]),
        .I5(\smallest_reg[4]_17 [2]),
        .O(\wl_tap_count_r[2]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'h80808080808C8C80)) 
    \wl_tap_count_r[3]_i_1 
       (.I0(\wl_tap_count_r_reg[3]_i_2_n_0 ),
        .I1(\wl_tap_count_r[4]_i_4_n_0 ),
        .I2(wl_state_r__0[1]),
        .I3(\wl_tap_count_r_reg_n_0_[3] ),
        .I4(\wl_tap_count_r[3]_i_3_n_0 ),
        .I5(\wl_tap_count_r[4]_i_2_n_0 ),
        .O(wl_tap_count_r[3]));
  (* SOFT_HLUTNM = "soft_lutpair363" *) 
  LUT3 #(
    .INIT(8'h80)) 
    \wl_tap_count_r[3]_i_3 
       (.I0(\wl_tap_count_r_reg_n_0_[1] ),
        .I1(\wl_tap_count_r_reg_n_0_[0] ),
        .I2(\wl_tap_count_r_reg_n_0_[2] ),
        .O(\wl_tap_count_r[3]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \wl_tap_count_r[3]_i_4 
       (.I0(\smallest_reg[3]_16 [3]),
        .I1(\smallest_reg[2]_15 [3]),
        .I2(\dqs_count_r_reg[3]_1 [1]),
        .I3(\smallest_reg[1]_14 [3]),
        .I4(\dqs_count_r_reg[3]_1 [0]),
        .I5(\smallest_reg[0]_13 [3]),
        .O(\wl_tap_count_r[3]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \wl_tap_count_r[3]_i_5 
       (.I0(\smallest_reg[7]_20 [3]),
        .I1(\smallest_reg[6]_19 [3]),
        .I2(\dqs_count_r_reg[3]_1 [1]),
        .I3(\smallest_reg[5]_18 [3]),
        .I4(\dqs_count_r_reg[3]_1 [0]),
        .I5(\smallest_reg[4]_17 [3]),
        .O(\wl_tap_count_r[3]_i_5_n_0 ));
  LUT6 #(
    .INIT(64'hFF00140000001400)) 
    \wl_tap_count_r[4]_i_1 
       (.I0(\wl_tap_count_r[4]_i_2_n_0 ),
        .I1(\wl_tap_count_r[4]_i_3_n_0 ),
        .I2(\wl_tap_count_r_reg_n_0_[4] ),
        .I3(\wl_tap_count_r[4]_i_4_n_0 ),
        .I4(wl_state_r__0[1]),
        .I5(\wl_tap_count_r_reg[4]_i_5_n_0 ),
        .O(wl_tap_count_r[4]));
  (* SOFT_HLUTNM = "soft_lutpair328" *) 
  LUT2 #(
    .INIT(4'h8)) 
    \wl_tap_count_r[4]_i_2 
       (.I0(wr_level_done_r5),
        .I1(wl_state_r__0[0]),
        .O(\wl_tap_count_r[4]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair363" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \wl_tap_count_r[4]_i_3 
       (.I0(\wl_tap_count_r_reg_n_0_[2] ),
        .I1(\wl_tap_count_r_reg_n_0_[0] ),
        .I2(\wl_tap_count_r_reg_n_0_[1] ),
        .I3(\wl_tap_count_r_reg_n_0_[3] ),
        .O(\wl_tap_count_r[4]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair311" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \wl_tap_count_r[4]_i_4 
       (.I0(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .O(\wl_tap_count_r[4]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \wl_tap_count_r[4]_i_6 
       (.I0(\smallest_reg[3]_16 [4]),
        .I1(\smallest_reg[2]_15 [4]),
        .I2(\dqs_count_r_reg[3]_1 [1]),
        .I3(\smallest_reg[1]_14 [4]),
        .I4(\dqs_count_r_reg[3]_1 [0]),
        .I5(\smallest_reg[0]_13 [4]),
        .O(\wl_tap_count_r[4]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \wl_tap_count_r[4]_i_7 
       (.I0(\smallest_reg[7]_20 [4]),
        .I1(\smallest_reg[6]_19 [4]),
        .I2(\dqs_count_r_reg[3]_1 [1]),
        .I3(\smallest_reg[5]_18 [4]),
        .I4(\dqs_count_r_reg[3]_1 [0]),
        .I5(\smallest_reg[4]_17 [4]),
        .O(\wl_tap_count_r[4]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'h000330C020003003)) 
    \wl_tap_count_r[5]_i_1 
       (.I0(done_dqs_dec238_out),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I2(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I3(wl_state_r__0[2]),
        .I4(wl_state_r__0[1]),
        .I5(wl_state_r__0[0]),
        .O(\wl_tap_count_r[5]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair338" *) 
  LUT5 #(
    .INIT(32'h0000CA00)) 
    \wl_tap_count_r[5]_i_2 
       (.I0(\wl_tap_count_r[5]_i_4_n_0 ),
        .I1(\wl_tap_count_r_reg[5]_i_5_n_0 ),
        .I2(wl_state_r__0[1]),
        .I3(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I4(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .O(wl_tap_count_r[5]));
  LUT6 #(
    .INIT(64'h0770770077007700)) 
    \wl_tap_count_r[5]_i_4 
       (.I0(wr_level_done_r5),
        .I1(wl_state_r__0[0]),
        .I2(\wl_tap_count_r[3]_i_3_n_0 ),
        .I3(\wl_tap_count_r_reg_n_0_[5] ),
        .I4(\wl_tap_count_r_reg_n_0_[4] ),
        .I5(\wl_tap_count_r_reg_n_0_[3] ),
        .O(\wl_tap_count_r[5]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \wl_tap_count_r[5]_i_6 
       (.I0(\smallest_reg[3]_16 [5]),
        .I1(\smallest_reg[2]_15 [5]),
        .I2(\dqs_count_r_reg[3]_1 [1]),
        .I3(\smallest_reg[1]_14 [5]),
        .I4(\dqs_count_r_reg[3]_1 [0]),
        .I5(\smallest_reg[0]_13 [5]),
        .O(\wl_tap_count_r[5]_i_6_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \wl_tap_count_r[5]_i_7 
       (.I0(\smallest_reg[7]_20 [5]),
        .I1(\smallest_reg[6]_19 [5]),
        .I2(\dqs_count_r_reg[3]_1 [1]),
        .I3(\smallest_reg[5]_18 [5]),
        .I4(\dqs_count_r_reg[3]_1 [0]),
        .I5(\smallest_reg[4]_17 [5]),
        .O(\wl_tap_count_r[5]_i_7_n_0 ));
  FDRE \wl_tap_count_r_reg[0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\wl_tap_count_r[5]_i_1_n_0 ),
        .D(wl_tap_count_r[0]),
        .Q(\wl_tap_count_r_reg_n_0_[0] ),
        .R(\fine_inc_reg[6][3]_0 [1]));
  MUXF7 \wl_tap_count_r_reg[0]_i_2 
       (.I0(\wl_tap_count_r[0]_i_3_n_0 ),
        .I1(\wl_tap_count_r[0]_i_4_n_0 ),
        .O(\wl_tap_count_r_reg[0]_i_2_n_0 ),
        .S(\dqs_count_r_reg[3]_1 [2]));
  FDRE \wl_tap_count_r_reg[1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\wl_tap_count_r[5]_i_1_n_0 ),
        .D(wl_tap_count_r[1]),
        .Q(\wl_tap_count_r_reg_n_0_[1] ),
        .R(\fine_inc_reg[6][3]_0 [1]));
  MUXF7 \wl_tap_count_r_reg[1]_i_2 
       (.I0(\wl_tap_count_r[1]_i_3_n_0 ),
        .I1(\wl_tap_count_r[1]_i_4_n_0 ),
        .O(\wl_tap_count_r_reg[1]_i_2_n_0 ),
        .S(\dqs_count_r_reg[3]_1 [2]));
  FDRE \wl_tap_count_r_reg[2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\wl_tap_count_r[5]_i_1_n_0 ),
        .D(wl_tap_count_r[2]),
        .Q(\wl_tap_count_r_reg_n_0_[2] ),
        .R(\fine_inc_reg[6][3]_0 [1]));
  MUXF7 \wl_tap_count_r_reg[2]_i_3 
       (.I0(\wl_tap_count_r[2]_i_4_n_0 ),
        .I1(\wl_tap_count_r[2]_i_5_n_0 ),
        .O(\wl_tap_count_r_reg[2]_i_3_n_0 ),
        .S(\dqs_count_r_reg[3]_1 [2]));
  FDRE \wl_tap_count_r_reg[3] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\wl_tap_count_r[5]_i_1_n_0 ),
        .D(wl_tap_count_r[3]),
        .Q(\wl_tap_count_r_reg_n_0_[3] ),
        .R(\fine_inc_reg[6][3]_0 [1]));
  MUXF7 \wl_tap_count_r_reg[3]_i_2 
       (.I0(\wl_tap_count_r[3]_i_4_n_0 ),
        .I1(\wl_tap_count_r[3]_i_5_n_0 ),
        .O(\wl_tap_count_r_reg[3]_i_2_n_0 ),
        .S(\dqs_count_r_reg[3]_1 [2]));
  FDRE \wl_tap_count_r_reg[4] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\wl_tap_count_r[5]_i_1_n_0 ),
        .D(wl_tap_count_r[4]),
        .Q(\wl_tap_count_r_reg_n_0_[4] ),
        .R(\fine_inc_reg[6][3]_0 [1]));
  MUXF7 \wl_tap_count_r_reg[4]_i_5 
       (.I0(\wl_tap_count_r[4]_i_6_n_0 ),
        .I1(\wl_tap_count_r[4]_i_7_n_0 ),
        .O(\wl_tap_count_r_reg[4]_i_5_n_0 ),
        .S(\dqs_count_r_reg[3]_1 [2]));
  FDRE \wl_tap_count_r_reg[5] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(\wl_tap_count_r[5]_i_1_n_0 ),
        .D(wl_tap_count_r[5]),
        .Q(\wl_tap_count_r_reg_n_0_[5] ),
        .R(\fine_inc_reg[6][3]_0 [1]));
  MUXF7 \wl_tap_count_r_reg[5]_i_5 
       (.I0(\wl_tap_count_r[5]_i_6_n_0 ),
        .I1(\wl_tap_count_r[5]_i_7_n_0 ),
        .O(\wl_tap_count_r_reg[5]_i_5_n_0 ),
        .S(\dqs_count_r_reg[3]_1 [2]));
  LUT3 #(
    .INIT(8'h8A)) 
    wr_level_done_i_1
       (.I0(done_dqs_tap_inc),
        .I1(wrlvl_byte_redo_r),
        .I2(wrlvl_byte_redo),
        .O(wr_level_done_i_1_n_0));
  FDRE wr_level_done_r1_reg
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(wr_level_done_r_reg_n_0),
        .Q(wr_level_done_r1),
        .R(1'b0));
  FDRE wr_level_done_r2_reg
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(wr_level_done_r1),
        .Q(wr_level_done_r2),
        .R(1'b0));
  FDRE wr_level_done_r3_reg
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(wr_level_done_r2),
        .Q(wr_level_done_r3),
        .R(1'b0));
  FDRE wr_level_done_r4_reg
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(wr_level_done_r3),
        .Q(wr_level_done_r4),
        .R(1'b0));
  FDRE wr_level_done_r5_reg
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(wr_level_done_r4),
        .Q(wr_level_done_r5),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair334" *) 
  LUT5 #(
    .INIT(32'h01FF0100)) 
    wr_level_done_r_i_1
       (.I0(\rank_cnt_r_reg_n_0_[1] ),
        .I1(\rank_cnt_r_reg_n_0_[0] ),
        .I2(wl_state_r__0[2]),
        .I3(wr_level_done_r_i_2_n_0),
        .I4(wr_level_done_r_reg_n_0),
        .O(wr_level_done_r_i_1_n_0));
  LUT6 #(
    .INIT(64'h00A0000003000000)) 
    wr_level_done_r_i_2
       (.I0(done_dqs_dec238_out),
        .I1(p_0_in),
        .I2(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I3(wl_state_r__0[0]),
        .I4(\rank_cnt_r[1]_i_2_n_0 ),
        .I5(wl_state_r__0[2]),
        .O(wr_level_done_r_i_2_n_0));
  FDRE wr_level_done_r_reg
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(wr_level_done_r_i_1_n_0),
        .Q(wr_level_done_r_reg_n_0),
        .R(\wl_dqs_tap_count_r_reg[0][5][5]_0 ));
  (* syn_maxfan = "2" *) 
  FDRE wr_level_done_reg
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(wr_level_done_i_1_n_0),
        .Q(wr_level_done_reg_0),
        .R(1'b0));
  FDRE wr_level_start_r_reg
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(wr_level_start_r_reg_0),
        .Q(wr_level_start_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h00000000BAAA00AA)) 
    wrlvl_byte_done_i_1
       (.I0(wrlvl_byte_done),
        .I1(wr_level_done_r4),
        .I2(wr_level_done_r3),
        .I3(wrlvl_byte_redo),
        .I4(wrlvl_byte_redo_r),
        .I5(\single_rank.done_dqs_dec_reg_0 ),
        .O(wrlvl_byte_done_i_1_n_0));
  FDRE wrlvl_byte_done_reg
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(wrlvl_byte_done_i_1_n_0),
        .Q(wrlvl_byte_done),
        .R(1'b0));
  FDRE wrlvl_byte_redo_r_reg
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(wrlvl_byte_redo),
        .Q(wrlvl_byte_redo_r),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h4573557700220022)) 
    wrlvl_rank_done_r_i_1
       (.I0(wrlvl_rank_done_r_i_2_n_0),
        .I1(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I2(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I3(wl_state_r__0[2]),
        .I4(wrlvl_rank_done_r_i_3_n_0),
        .I5(wrlvl_rank_done),
        .O(wrlvl_rank_done_r_i_1_n_0));
  LUT6 #(
    .INIT(64'h0000000200000000)) 
    wrlvl_rank_done_r_i_2
       (.I0(wl_state_r__0[0]),
        .I1(wl_state_r__0[2]),
        .I2(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .I3(p_0_in),
        .I4(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I5(wl_state_r__0[1]),
        .O(wrlvl_rank_done_r_i_2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair324" *) 
  LUT2 #(
    .INIT(4'h2)) 
    wrlvl_rank_done_r_i_3
       (.I0(wl_state_r__0[1]),
        .I1(wl_state_r__0[0]),
        .O(wrlvl_rank_done_r_i_3_n_0));
  FDRE wrlvl_rank_done_r_reg
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(wrlvl_rank_done_r_i_1_n_0),
        .Q(wrlvl_rank_done),
        .R(\corse_inc_reg[6][2]_0 [0]));
  (* SOFT_HLUTNM = "soft_lutpair372" *) 
  LUT3 #(
    .INIT(8'h34)) 
    \wrlvl_redo_corse_inc[0]_i_1 
       (.I0(wl_state_r__0[2]),
        .I1(\wrlvl_redo_corse_inc[2]_i_4_n_0 ),
        .I2(\wrlvl_redo_corse_inc_reg_n_0_[0] ),
        .O(\wrlvl_redo_corse_inc[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h4440FFFF40440000)) 
    \wrlvl_redo_corse_inc[1]_i_1 
       (.I0(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I1(wl_state_r__0[1]),
        .I2(wl_state_r__0[2]),
        .I3(\wrlvl_redo_corse_inc_reg_n_0_[0] ),
        .I4(\wrlvl_redo_corse_inc[2]_i_4_n_0 ),
        .I5(\wrlvl_redo_corse_inc_reg_n_0_[1] ),
        .O(\wrlvl_redo_corse_inc[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hD100FFFFE2000000)) 
    \wrlvl_redo_corse_inc[2]_i_1 
       (.I0(\wrlvl_redo_corse_inc[2]_i_2_n_0 ),
        .I1(wl_state_r__0[2]),
        .I2(\wrlvl_redo_corse_inc[2]_i_3_n_0 ),
        .I3(\rank_cnt_r[1]_i_2_n_0 ),
        .I4(\wrlvl_redo_corse_inc[2]_i_4_n_0 ),
        .I5(\wrlvl_redo_corse_inc_reg_n_0_[2] ),
        .O(\wrlvl_redo_corse_inc[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \wrlvl_redo_corse_inc[2]_i_10 
       (.I0(\final_coarse_tap_reg_n_0_[3][2] ),
        .I1(\final_coarse_tap_reg_n_0_[2][2] ),
        .I2(\dqs_count_r_reg[3]_1 [1]),
        .I3(\final_coarse_tap_reg_n_0_[1][2] ),
        .I4(\dqs_count_r_reg[3]_1 [0]),
        .I5(\final_coarse_tap_reg_n_0_[0][2] ),
        .O(\wrlvl_redo_corse_inc[2]_i_10_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \wrlvl_redo_corse_inc[2]_i_11 
       (.I0(\final_coarse_tap_reg_n_0_[7][2] ),
        .I1(\final_coarse_tap_reg_n_0_[6][2] ),
        .I2(\dqs_count_r_reg[3]_1 [1]),
        .I3(\final_coarse_tap_reg_n_0_[5][2] ),
        .I4(\dqs_count_r_reg[3]_1 [0]),
        .I5(\final_coarse_tap_reg_n_0_[4][2] ),
        .O(\wrlvl_redo_corse_inc[2]_i_11_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair359" *) 
  LUT4 #(
    .INIT(16'hAAA8)) 
    \wrlvl_redo_corse_inc[2]_i_12 
       (.I0(wrlvl_byte_redo),
        .I1(\wrlvl_redo_corse_inc_reg_n_0_[2] ),
        .I2(\wrlvl_redo_corse_inc_reg_n_0_[0] ),
        .I3(\wrlvl_redo_corse_inc_reg_n_0_[1] ),
        .O(\wrlvl_redo_corse_inc[2]_i_12_n_0 ));
  LUT2 #(
    .INIT(4'h1)) 
    \wrlvl_redo_corse_inc[2]_i_2 
       (.I0(\wrlvl_redo_corse_inc_reg_n_0_[0] ),
        .I1(\wrlvl_redo_corse_inc_reg_n_0_[1] ),
        .O(\wrlvl_redo_corse_inc[2]_i_2_n_0 ));
  LUT3 #(
    .INIT(8'hD5)) 
    \wrlvl_redo_corse_inc[2]_i_3 
       (.I0(\wrlvl_redo_corse_inc_reg[2]_0 ),
        .I1(\po_stg2_wrcal_cnt_reg[2] ),
        .I2(\po_stg2_wrcal_cnt_reg[2]_0 ),
        .O(\wrlvl_redo_corse_inc[2]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0808080000000000)) 
    \wrlvl_redo_corse_inc[2]_i_4 
       (.I0(\wrlvl_redo_corse_inc[2]_i_7_n_0 ),
        .I1(wl_state_r__0[1]),
        .I2(\FSM_sequential_wl_state_r_reg[4]_0 [1]),
        .I3(wl_state_r__0[2]),
        .I4(wl_state_r__0[0]),
        .I5(\FSM_sequential_wl_state_r_reg[4]_0 [0]),
        .O(\wrlvl_redo_corse_inc[2]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h44444444444F4444)) 
    \wrlvl_redo_corse_inc[2]_i_7 
       (.I0(wl_state_r__0[2]),
        .I1(\wrlvl_redo_corse_inc[2]_i_12_n_0 ),
        .I2(\wrlvl_redo_corse_inc[2]_i_4_0 ),
        .I3(wl_state_r__0[0]),
        .I4(wrlvl_byte_redo),
        .I5(wrlvl_byte_redo_r),
        .O(\wrlvl_redo_corse_inc[2]_i_7_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \wrlvl_redo_corse_inc[2]_i_8 
       (.I0(\final_coarse_tap_reg_n_0_[3][1] ),
        .I1(\final_coarse_tap_reg_n_0_[2][1] ),
        .I2(\dqs_count_r_reg[3]_1 [1]),
        .I3(\final_coarse_tap_reg_n_0_[1][1] ),
        .I4(\dqs_count_r_reg[3]_1 [0]),
        .I5(\final_coarse_tap_reg_n_0_[0][1] ),
        .O(\wrlvl_redo_corse_inc[2]_i_8_n_0 ));
  LUT6 #(
    .INIT(64'hAFA0CFCFAFA0C0C0)) 
    \wrlvl_redo_corse_inc[2]_i_9 
       (.I0(\final_coarse_tap_reg_n_0_[7][1] ),
        .I1(\final_coarse_tap_reg_n_0_[6][1] ),
        .I2(\dqs_count_r_reg[3]_1 [1]),
        .I3(\final_coarse_tap_reg_n_0_[5][1] ),
        .I4(\dqs_count_r_reg[3]_1 [0]),
        .I5(\final_coarse_tap_reg_n_0_[4][1] ),
        .O(\wrlvl_redo_corse_inc[2]_i_9_n_0 ));
  FDRE \wrlvl_redo_corse_inc_reg[0] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\wrlvl_redo_corse_inc[0]_i_1_n_0 ),
        .Q(\wrlvl_redo_corse_inc_reg_n_0_[0] ),
        .R(\wl_dqs_tap_count_r_reg[0][5][5]_0 ));
  FDRE \wrlvl_redo_corse_inc_reg[1] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\wrlvl_redo_corse_inc[1]_i_1_n_0 ),
        .Q(\wrlvl_redo_corse_inc_reg_n_0_[1] ),
        .R(\wl_dqs_tap_count_r_reg[0][5][5]_0 ));
  FDRE \wrlvl_redo_corse_inc_reg[2] 
       (.C(\dqs_count_r_reg[2]_rep__0_1 ),
        .CE(1'b1),
        .D(\wrlvl_redo_corse_inc[2]_i_1_n_0 ),
        .Q(\wrlvl_redo_corse_inc_reg_n_0_[2] ),
        .R(\wl_dqs_tap_count_r_reg[0][5][5]_0 ));
  MUXF7 \wrlvl_redo_corse_inc_reg[2]_i_5 
       (.I0(\wrlvl_redo_corse_inc[2]_i_8_n_0 ),
        .I1(\wrlvl_redo_corse_inc[2]_i_9_n_0 ),
        .O(\po_stg2_wrcal_cnt_reg[2] ),
        .S(\dqs_count_r_reg[3]_1 [2]));
  MUXF7 \wrlvl_redo_corse_inc_reg[2]_i_6 
       (.I0(\wrlvl_redo_corse_inc[2]_i_10_n_0 ),
        .I1(\wrlvl_redo_corse_inc[2]_i_11_n_0 ),
        .O(\po_stg2_wrcal_cnt_reg[2]_0 ),
        .S(\dqs_count_r_reg[3]_1 [2]));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ddr_prbs_gen" *) 
module mig_mig_7series_v4_2_ddr_prbs_gen
   (phy_if_empty_r_reg_0,
    first_wrcal_pat_r_reg,
    first_wrcal_pat_r_reg_0,
    \dout_o_reg[9]_0 ,
    \dout_o_reg[9]_1 ,
    \dout_o_reg[10]_0 ,
    \dout_o_reg[10]_1 ,
    \dout_o_reg[11]_0 ,
    \dout_o_reg[11]_1 ,
    \dout_o_reg[12]_0 ,
    \dout_o_reg[12]_1 ,
    \dout_o_reg[12]_2 ,
    \dout_o_reg[12]_3 ,
    \dout_o_reg[13]_0 ,
    \dout_o_reg[13]_1 ,
    \dout_o_reg[13]_2 ,
    \dout_o_reg[13]_3 ,
    \dout_o_reg[14]_0 ,
    \dout_o_reg[14]_1 ,
    \dout_o_reg[8]_0 ,
    \dout_o_reg[8]_1 ,
    \dout_o_reg[8]_2 ,
    \dout_o_reg[8]_3 ,
    rdlvl_stg1_done_int_reg,
    \dout_o_reg[9]_2 ,
    rdlvl_stg1_done_int_reg_0,
    rdlvl_stg1_done_int_reg_1,
    \dout_o_reg[9]_3 ,
    rdlvl_stg1_done_int_reg_2,
    \dout_o_reg[10]_2 ,
    rdlvl_stg1_done_int_reg_3,
    \dout_o_reg[10]_3 ,
    rdlvl_stg1_done_int_reg_4,
    \dout_o_reg[11]_2 ,
    \dout_o_reg[11]_3 ,
    \dout_o_reg[12]_4 ,
    \dout_o_reg[12]_5 ,
    rdlvl_stg1_done_int_reg_5,
    rdlvl_stg1_done_int_reg_6,
    \dout_o_reg[6]_0 ,
    wrcal_done_reg,
    \dout_o_reg[15]_0 ,
    wrcal_done_reg_0,
    \dout_o_reg[15]_1 ,
    wrcal_done_reg_1,
    Q,
    prbs_out,
    if_empty,
    \dout_o_reg[15]_2 ,
    first_wrcal_pat_r,
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511] ,
    \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0 ,
    first_rdlvl_pat_r,
    \rd_addr_reg[3]_0 ,
    \rd_addr_reg[0]_0 ,
    \victim_sel_rotate.sel_reg[56]_0 ,
    D,
    SR,
    E);
  output phy_if_empty_r_reg_0;
  output first_wrcal_pat_r_reg;
  output first_wrcal_pat_r_reg_0;
  output \dout_o_reg[9]_0 ;
  output \dout_o_reg[9]_1 ;
  output \dout_o_reg[10]_0 ;
  output \dout_o_reg[10]_1 ;
  output \dout_o_reg[11]_0 ;
  output \dout_o_reg[11]_1 ;
  output \dout_o_reg[12]_0 ;
  output \dout_o_reg[12]_1 ;
  output \dout_o_reg[12]_2 ;
  output \dout_o_reg[12]_3 ;
  output \dout_o_reg[13]_0 ;
  output \dout_o_reg[13]_1 ;
  output \dout_o_reg[13]_2 ;
  output \dout_o_reg[13]_3 ;
  output \dout_o_reg[14]_0 ;
  output \dout_o_reg[14]_1 ;
  output \dout_o_reg[8]_0 ;
  output \dout_o_reg[8]_1 ;
  output \dout_o_reg[8]_2 ;
  output \dout_o_reg[8]_3 ;
  output rdlvl_stg1_done_int_reg;
  output \dout_o_reg[9]_2 ;
  output rdlvl_stg1_done_int_reg_0;
  output rdlvl_stg1_done_int_reg_1;
  output \dout_o_reg[9]_3 ;
  output rdlvl_stg1_done_int_reg_2;
  output \dout_o_reg[10]_2 ;
  output rdlvl_stg1_done_int_reg_3;
  output \dout_o_reg[10]_3 ;
  output rdlvl_stg1_done_int_reg_4;
  output \dout_o_reg[11]_2 ;
  output \dout_o_reg[11]_3 ;
  output \dout_o_reg[12]_4 ;
  output \dout_o_reg[12]_5 ;
  output rdlvl_stg1_done_int_reg_5;
  output rdlvl_stg1_done_int_reg_6;
  output \dout_o_reg[6]_0 ;
  output wrcal_done_reg;
  output \dout_o_reg[15]_0 ;
  output wrcal_done_reg_0;
  output \dout_o_reg[15]_1 ;
  output wrcal_done_reg_1;
  output [0:0]Q;
  output [63:0]prbs_out;
  input if_empty;
  input \dout_o_reg[15]_2 ;
  input first_wrcal_pat_r;
  input \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511] ;
  input \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0 ;
  input first_rdlvl_pat_r;
  input \rd_addr_reg[3]_0 ;
  input \rd_addr_reg[0]_0 ;
  input [0:0]\victim_sel_rotate.sel_reg[56]_0 ;
  input [7:0]D;
  input [0:0]SR;
  input [0:0]E;

  wire [7:0]D;
  wire [0:0]E;
  wire [0:0]Q;
  wire [0:0]SR;
  wire \dout_o[0]_i_1_n_0 ;
  wire \dout_o[0]_i_2_n_0 ;
  wire \dout_o[0]_i_3_n_0 ;
  wire \dout_o[0]_i_4_n_0 ;
  wire \dout_o[10]_i_1_n_0 ;
  wire \dout_o[10]_i_2_n_0 ;
  wire \dout_o[10]_i_3_n_0 ;
  wire \dout_o[11]_i_1_n_0 ;
  wire \dout_o[11]_i_2_n_0 ;
  wire \dout_o[11]_i_3_n_0 ;
  wire \dout_o[11]_i_4_n_0 ;
  wire \dout_o[12]_i_1_n_0 ;
  wire \dout_o[12]_i_2_n_0 ;
  wire \dout_o[12]_i_3_n_0 ;
  wire \dout_o[12]_i_4_n_0 ;
  wire \dout_o[13]_i_1_n_0 ;
  wire \dout_o[13]_i_2_n_0 ;
  wire \dout_o[13]_i_3_n_0 ;
  wire \dout_o[13]_i_4_n_0 ;
  wire \dout_o[14]_i_1_n_0 ;
  wire \dout_o[14]_i_2_n_0 ;
  wire \dout_o[14]_i_3_n_0 ;
  wire \dout_o[14]_i_4_n_0 ;
  wire \dout_o[15]_i_1_n_0 ;
  wire \dout_o[15]_i_2_n_0 ;
  wire \dout_o[15]_i_3_n_0 ;
  wire \dout_o[15]_i_4_n_0 ;
  wire \dout_o[1]_i_1_n_0 ;
  wire \dout_o[1]_i_2_n_0 ;
  wire \dout_o[1]_i_3_n_0 ;
  wire \dout_o[1]_i_4_n_0 ;
  wire \dout_o[2]_i_1_n_0 ;
  wire \dout_o[2]_i_2_n_0 ;
  wire \dout_o[2]_i_3_n_0 ;
  wire \dout_o[2]_i_4_n_0 ;
  wire \dout_o[3]_i_1_n_0 ;
  wire \dout_o[3]_i_2_n_0 ;
  wire \dout_o[3]_i_3_n_0 ;
  wire \dout_o[3]_i_4_n_0 ;
  wire \dout_o[4]_i_1_n_0 ;
  wire \dout_o[4]_i_2_n_0 ;
  wire \dout_o[4]_i_3_n_0 ;
  wire \dout_o[4]_i_4_n_0 ;
  wire \dout_o[5]_i_1_n_0 ;
  wire \dout_o[5]_i_2_n_0 ;
  wire \dout_o[5]_i_3_n_0 ;
  wire \dout_o[5]_i_4_n_0 ;
  wire \dout_o[6]_i_1_n_0 ;
  wire \dout_o[6]_i_2_n_0 ;
  wire \dout_o[6]_i_3_n_0 ;
  wire \dout_o[6]_i_4_n_0 ;
  wire \dout_o[7]_i_1_n_0 ;
  wire \dout_o[7]_i_2_n_0 ;
  wire \dout_o[7]_i_3_n_0 ;
  wire \dout_o[7]_i_4_n_0 ;
  wire \dout_o[8]_i_1_n_0 ;
  wire \dout_o[8]_i_2_n_0 ;
  wire \dout_o[8]_i_3_n_0 ;
  wire \dout_o[8]_i_4_n_0 ;
  wire \dout_o[9]_i_1_n_0 ;
  wire \dout_o[9]_i_2_n_0 ;
  wire \dout_o[9]_i_3_n_0 ;
  wire \dout_o[9]_i_4_n_0 ;
  wire \dout_o_reg[10]_0 ;
  wire \dout_o_reg[10]_1 ;
  wire \dout_o_reg[10]_2 ;
  wire \dout_o_reg[10]_3 ;
  wire \dout_o_reg[11]_0 ;
  wire \dout_o_reg[11]_1 ;
  wire \dout_o_reg[11]_2 ;
  wire \dout_o_reg[11]_3 ;
  wire \dout_o_reg[12]_0 ;
  wire \dout_o_reg[12]_1 ;
  wire \dout_o_reg[12]_2 ;
  wire \dout_o_reg[12]_3 ;
  wire \dout_o_reg[12]_4 ;
  wire \dout_o_reg[12]_5 ;
  wire \dout_o_reg[13]_0 ;
  wire \dout_o_reg[13]_1 ;
  wire \dout_o_reg[13]_2 ;
  wire \dout_o_reg[13]_3 ;
  wire \dout_o_reg[14]_0 ;
  wire \dout_o_reg[14]_1 ;
  wire \dout_o_reg[15]_0 ;
  wire \dout_o_reg[15]_1 ;
  wire \dout_o_reg[15]_2 ;
  wire \dout_o_reg[6]_0 ;
  wire \dout_o_reg[8]_0 ;
  wire \dout_o_reg[8]_1 ;
  wire \dout_o_reg[8]_2 ;
  wire \dout_o_reg[8]_3 ;
  wire \dout_o_reg[9]_0 ;
  wire \dout_o_reg[9]_1 ;
  wire \dout_o_reg[9]_2 ;
  wire \dout_o_reg[9]_3 ;
  wire \dout_o_reg_n_0_[0] ;
  wire first_rdlvl_pat_r;
  wire first_wrcal_pat_r;
  wire first_wrcal_pat_r_reg;
  wire first_wrcal_pat_r_reg_0;
  wire if_empty;
  wire p_0_in222_in;
  wire p_0_in226_in;
  wire p_0_in230_in;
  wire p_0_in234_in;
  wire p_0_in238_in;
  wire p_0_in242_in;
  wire p_0_in246_in;
  wire p_0_in250_in;
  wire p_1_in;
  wire p_1_in1032_in;
  wire p_1_in252_in;
  wire p_1_in382_in;
  wire p_1_in512_in;
  wire p_1_in642_in;
  wire p_1_in772_in;
  wire p_1_in902_in;
  wire [7:0]p_1_in__0;
  wire p_2_in;
  wire p_2_in254_in;
  wire p_2_in384_in;
  wire p_2_in514_in;
  wire p_2_in644_in;
  wire p_2_in774_in;
  wire p_2_in904_in;
  wire phy_if_empty_r_reg_0;
  wire [63:0]prbs_out;
  wire \rd_addr[2]_i_2_n_0 ;
  wire \rd_addr[3]_i_2_n_0 ;
  wire \rd_addr[4]_i_2_n_0 ;
  wire \rd_addr[7]_i_4_n_0 ;
  wire \rd_addr[7]_i_5_n_0 ;
  wire \rd_addr[7]_i_6_n_0 ;
  wire \rd_addr[7]_i_7_n_0 ;
  wire \rd_addr_reg[0]_0 ;
  wire \rd_addr_reg[3]_0 ;
  wire \rd_addr_reg_n_0_[0] ;
  wire \rd_addr_reg_n_0_[2] ;
  wire \rd_addr_reg_n_0_[3] ;
  wire \rd_addr_reg_n_0_[4] ;
  wire \rd_addr_reg_n_0_[5] ;
  wire \rd_addr_reg_n_0_[6] ;
  wire \rd_addr_reg_n_0_[7] ;
  wire rdlvl_stg1_done_int_reg;
  wire rdlvl_stg1_done_int_reg_0;
  wire rdlvl_stg1_done_int_reg_1;
  wire rdlvl_stg1_done_int_reg_2;
  wire rdlvl_stg1_done_int_reg_3;
  wire rdlvl_stg1_done_int_reg_4;
  wire rdlvl_stg1_done_int_reg_5;
  wire rdlvl_stg1_done_int_reg_6;
  wire [0:0]\victim_sel_rotate.sel_reg[56]_0 ;
  wire wrcal_done_reg;
  wire wrcal_done_reg_0;
  wire wrcal_done_reg_1;
  wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511] ;
  wire \wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0 ;

  LUT5 #(
    .INIT(32'hFCBBFC88)) 
    \dout_o[0]_i_1 
       (.I0(\dout_o[0]_i_2_n_0 ),
        .I1(\rd_addr_reg_n_0_[6] ),
        .I2(\dout_o[0]_i_3_n_0 ),
        .I3(\rd_addr_reg_n_0_[7] ),
        .I4(\dout_o[0]_i_4_n_0 ),
        .O(\dout_o[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFBA702DC40FD7BA7)) 
    \dout_o[0]_i_2 
       (.I0(\rd_addr_reg_n_0_[5] ),
        .I1(\rd_addr_reg_n_0_[3] ),
        .I2(\rd_addr_reg_n_0_[2] ),
        .I3(\rd_addr_reg_n_0_[0] ),
        .I4(Q),
        .I5(\rd_addr_reg_n_0_[4] ),
        .O(\dout_o[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFF941DDE1)) 
    \dout_o[0]_i_3 
       (.I0(\rd_addr_reg_n_0_[4] ),
        .I1(Q),
        .I2(\rd_addr_reg_n_0_[0] ),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(\rd_addr_reg_n_0_[3] ),
        .I5(\rd_addr_reg_n_0_[5] ),
        .O(\dout_o[0]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h5F74ABA8D4EB4862)) 
    \dout_o[0]_i_4 
       (.I0(\rd_addr_reg_n_0_[5] ),
        .I1(\rd_addr_reg_n_0_[3] ),
        .I2(\rd_addr_reg_n_0_[2] ),
        .I3(\rd_addr_reg_n_0_[0] ),
        .I4(\rd_addr_reg_n_0_[4] ),
        .I5(Q),
        .O(\dout_o[0]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \dout_o[10]_i_1 
       (.I0(\dout_o[12]_i_2_n_0 ),
        .I1(\rd_addr_reg_n_0_[6] ),
        .I2(\dout_o[10]_i_2_n_0 ),
        .I3(\rd_addr_reg_n_0_[7] ),
        .I4(\dout_o[10]_i_3_n_0 ),
        .O(\dout_o[10]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h000000004599CD27)) 
    \dout_o[10]_i_2 
       (.I0(\rd_addr_reg_n_0_[4] ),
        .I1(Q),
        .I2(\rd_addr_reg_n_0_[0] ),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(\rd_addr_reg_n_0_[3] ),
        .I5(\rd_addr_reg_n_0_[5] ),
        .O(\dout_o[10]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h139126016C0923FA)) 
    \dout_o[10]_i_3 
       (.I0(\rd_addr_reg_n_0_[5] ),
        .I1(\rd_addr_reg_n_0_[3] ),
        .I2(\rd_addr_reg_n_0_[2] ),
        .I3(\rd_addr_reg_n_0_[0] ),
        .I4(Q),
        .I5(\rd_addr_reg_n_0_[4] ),
        .O(\dout_o[10]_i_3_n_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \dout_o[11]_i_1 
       (.I0(\dout_o[11]_i_2_n_0 ),
        .I1(\rd_addr_reg_n_0_[6] ),
        .I2(\dout_o[11]_i_3_n_0 ),
        .I3(\rd_addr_reg_n_0_[7] ),
        .I4(\dout_o[11]_i_4_n_0 ),
        .O(\dout_o[11]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h713DD3CC4AE43A65)) 
    \dout_o[11]_i_2 
       (.I0(\rd_addr_reg_n_0_[5] ),
        .I1(\rd_addr_reg_n_0_[3] ),
        .I2(\rd_addr_reg_n_0_[2] ),
        .I3(\rd_addr_reg_n_0_[0] ),
        .I4(\rd_addr_reg_n_0_[4] ),
        .I5(Q),
        .O(\dout_o[11]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h00000000322002AD)) 
    \dout_o[11]_i_3 
       (.I0(Q),
        .I1(\rd_addr_reg_n_0_[4] ),
        .I2(\rd_addr_reg_n_0_[0] ),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(\rd_addr_reg_n_0_[3] ),
        .I5(\rd_addr_reg_n_0_[5] ),
        .O(\dout_o[11]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h7BB6E4333589857B)) 
    \dout_o[11]_i_4 
       (.I0(\rd_addr_reg_n_0_[5] ),
        .I1(\rd_addr_reg_n_0_[3] ),
        .I2(\rd_addr_reg_n_0_[2] ),
        .I3(Q),
        .I4(\rd_addr_reg_n_0_[4] ),
        .I5(\rd_addr_reg_n_0_[0] ),
        .O(\dout_o[11]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \dout_o[12]_i_1 
       (.I0(\dout_o[12]_i_2_n_0 ),
        .I1(\rd_addr_reg_n_0_[6] ),
        .I2(\dout_o[12]_i_3_n_0 ),
        .I3(\rd_addr_reg_n_0_[7] ),
        .I4(\dout_o[12]_i_4_n_0 ),
        .O(\dout_o[12]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h9100E82800132190)) 
    \dout_o[12]_i_2 
       (.I0(\rd_addr_reg_n_0_[5] ),
        .I1(\rd_addr_reg_n_0_[3] ),
        .I2(\rd_addr_reg_n_0_[2] ),
        .I3(\rd_addr_reg_n_0_[0] ),
        .I4(\rd_addr_reg_n_0_[4] ),
        .I5(Q),
        .O(\dout_o[12]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000031C1E208)) 
    \dout_o[12]_i_3 
       (.I0(\rd_addr_reg_n_0_[0] ),
        .I1(\rd_addr_reg_n_0_[4] ),
        .I2(Q),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(\rd_addr_reg_n_0_[3] ),
        .I5(\rd_addr_reg_n_0_[5] ),
        .O(\dout_o[12]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h447C4014C71C60A6)) 
    \dout_o[12]_i_4 
       (.I0(\rd_addr_reg_n_0_[5] ),
        .I1(\rd_addr_reg_n_0_[3] ),
        .I2(\rd_addr_reg_n_0_[2] ),
        .I3(\rd_addr_reg_n_0_[4] ),
        .I4(Q),
        .I5(\rd_addr_reg_n_0_[0] ),
        .O(\dout_o[12]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \dout_o[13]_i_1 
       (.I0(\dout_o[13]_i_2_n_0 ),
        .I1(\rd_addr_reg_n_0_[6] ),
        .I2(\dout_o[13]_i_3_n_0 ),
        .I3(\rd_addr_reg_n_0_[7] ),
        .I4(\dout_o[13]_i_4_n_0 ),
        .O(\dout_o[13]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h5D37E7F8E29A3F4D)) 
    \dout_o[13]_i_2 
       (.I0(\rd_addr_reg_n_0_[5] ),
        .I1(\rd_addr_reg_n_0_[2] ),
        .I2(\rd_addr_reg_n_0_[3] ),
        .I3(\rd_addr_reg_n_0_[0] ),
        .I4(\rd_addr_reg_n_0_[4] ),
        .I5(Q),
        .O(\dout_o[13]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000040055161)) 
    \dout_o[13]_i_3 
       (.I0(\rd_addr_reg_n_0_[4] ),
        .I1(Q),
        .I2(\rd_addr_reg_n_0_[0] ),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(\rd_addr_reg_n_0_[3] ),
        .I5(\rd_addr_reg_n_0_[5] ),
        .O(\dout_o[13]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h6EEDFF5CF2C694A7)) 
    \dout_o[13]_i_4 
       (.I0(\rd_addr_reg_n_0_[5] ),
        .I1(\rd_addr_reg_n_0_[3] ),
        .I2(\rd_addr_reg_n_0_[2] ),
        .I3(\rd_addr_reg_n_0_[0] ),
        .I4(\rd_addr_reg_n_0_[4] ),
        .I5(Q),
        .O(\dout_o[13]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \dout_o[14]_i_1 
       (.I0(\dout_o[14]_i_2_n_0 ),
        .I1(\rd_addr_reg_n_0_[6] ),
        .I2(\dout_o[14]_i_3_n_0 ),
        .I3(\rd_addr_reg_n_0_[7] ),
        .I4(\dout_o[14]_i_4_n_0 ),
        .O(\dout_o[14]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h9100682100130190)) 
    \dout_o[14]_i_2 
       (.I0(\rd_addr_reg_n_0_[5] ),
        .I1(\rd_addr_reg_n_0_[3] ),
        .I2(\rd_addr_reg_n_0_[2] ),
        .I3(\rd_addr_reg_n_0_[0] ),
        .I4(\rd_addr_reg_n_0_[4] ),
        .I5(Q),
        .O(\dout_o[14]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h00000000118A8B19)) 
    \dout_o[14]_i_3 
       (.I0(Q),
        .I1(\rd_addr_reg_n_0_[4] ),
        .I2(\rd_addr_reg_n_0_[0] ),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(\rd_addr_reg_n_0_[3] ),
        .I5(\rd_addr_reg_n_0_[5] ),
        .O(\dout_o[14]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hD473D375410D7424)) 
    \dout_o[14]_i_4 
       (.I0(\rd_addr_reg_n_0_[5] ),
        .I1(\rd_addr_reg_n_0_[3] ),
        .I2(\rd_addr_reg_n_0_[2] ),
        .I3(\rd_addr_reg_n_0_[4] ),
        .I4(\rd_addr_reg_n_0_[0] ),
        .I5(Q),
        .O(\dout_o[14]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \dout_o[15]_i_1 
       (.I0(\dout_o[15]_i_2_n_0 ),
        .I1(\rd_addr_reg_n_0_[6] ),
        .I2(\dout_o[15]_i_3_n_0 ),
        .I3(\rd_addr_reg_n_0_[7] ),
        .I4(\dout_o[15]_i_4_n_0 ),
        .O(\dout_o[15]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h5D27F5EADA9A3F4D)) 
    \dout_o[15]_i_2 
       (.I0(\rd_addr_reg_n_0_[5] ),
        .I1(\rd_addr_reg_n_0_[2] ),
        .I2(\rd_addr_reg_n_0_[3] ),
        .I3(\rd_addr_reg_n_0_[0] ),
        .I4(\rd_addr_reg_n_0_[4] ),
        .I5(Q),
        .O(\dout_o[15]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h000000004115533E)) 
    \dout_o[15]_i_3 
       (.I0(\rd_addr_reg_n_0_[4] ),
        .I1(Q),
        .I2(\rd_addr_reg_n_0_[0] ),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(\rd_addr_reg_n_0_[3] ),
        .I5(\rd_addr_reg_n_0_[5] ),
        .O(\dout_o[15]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h5EF9FF567BFFCDB5)) 
    \dout_o[15]_i_4 
       (.I0(\rd_addr_reg_n_0_[5] ),
        .I1(\rd_addr_reg_n_0_[3] ),
        .I2(\rd_addr_reg_n_0_[2] ),
        .I3(\rd_addr_reg_n_0_[0] ),
        .I4(Q),
        .I5(\rd_addr_reg_n_0_[4] ),
        .O(\dout_o[15]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \dout_o[1]_i_1 
       (.I0(\dout_o[1]_i_2_n_0 ),
        .I1(\rd_addr_reg_n_0_[6] ),
        .I2(\dout_o[1]_i_3_n_0 ),
        .I3(\rd_addr_reg_n_0_[7] ),
        .I4(\dout_o[1]_i_4_n_0 ),
        .O(\dout_o[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hE7E55AE75A58865A)) 
    \dout_o[1]_i_2 
       (.I0(\rd_addr_reg_n_0_[5] ),
        .I1(\rd_addr_reg_n_0_[3] ),
        .I2(\rd_addr_reg_n_0_[2] ),
        .I3(\rd_addr_reg_n_0_[4] ),
        .I4(Q),
        .I5(\rd_addr_reg_n_0_[0] ),
        .O(\dout_o[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000051880521)) 
    \dout_o[1]_i_3 
       (.I0(\rd_addr_reg_n_0_[4] ),
        .I1(Q),
        .I2(\rd_addr_reg_n_0_[0] ),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(\rd_addr_reg_n_0_[3] ),
        .I5(\rd_addr_reg_n_0_[5] ),
        .O(\dout_o[1]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h7ADF52E8C4A8E711)) 
    \dout_o[1]_i_4 
       (.I0(\rd_addr_reg_n_0_[5] ),
        .I1(\rd_addr_reg_n_0_[3] ),
        .I2(\rd_addr_reg_n_0_[4] ),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(\rd_addr_reg_n_0_[0] ),
        .I5(Q),
        .O(\dout_o[1]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \dout_o[2]_i_1 
       (.I0(\dout_o[2]_i_2_n_0 ),
        .I1(\rd_addr_reg_n_0_[6] ),
        .I2(\dout_o[2]_i_3_n_0 ),
        .I3(\rd_addr_reg_n_0_[7] ),
        .I4(\dout_o[2]_i_4_n_0 ),
        .O(\dout_o[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFB02235842E57B02)) 
    \dout_o[2]_i_2 
       (.I0(\rd_addr_reg_n_0_[5] ),
        .I1(\rd_addr_reg_n_0_[3] ),
        .I2(\rd_addr_reg_n_0_[2] ),
        .I3(\rd_addr_reg_n_0_[0] ),
        .I4(Q),
        .I5(\rd_addr_reg_n_0_[4] ),
        .O(\dout_o[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h00000000020DCBD5)) 
    \dout_o[2]_i_3 
       (.I0(\rd_addr_reg_n_0_[0] ),
        .I1(Q),
        .I2(\rd_addr_reg_n_0_[4] ),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(\rd_addr_reg_n_0_[3] ),
        .I5(\rd_addr_reg_n_0_[5] ),
        .O(\dout_o[2]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hCF45D0CFCE2B8950)) 
    \dout_o[2]_i_4 
       (.I0(\rd_addr_reg_n_0_[5] ),
        .I1(\rd_addr_reg_n_0_[3] ),
        .I2(\rd_addr_reg_n_0_[2] ),
        .I3(\rd_addr_reg_n_0_[0] ),
        .I4(Q),
        .I5(\rd_addr_reg_n_0_[4] ),
        .O(\dout_o[2]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \dout_o[3]_i_1 
       (.I0(\dout_o[3]_i_2_n_0 ),
        .I1(\rd_addr_reg_n_0_[6] ),
        .I2(\dout_o[3]_i_3_n_0 ),
        .I3(\rd_addr_reg_n_0_[7] ),
        .I4(\dout_o[3]_i_4_n_0 ),
        .O(\dout_o[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h46E55AC658188658)) 
    \dout_o[3]_i_2 
       (.I0(\rd_addr_reg_n_0_[5] ),
        .I1(\rd_addr_reg_n_0_[3] ),
        .I2(\rd_addr_reg_n_0_[2] ),
        .I3(\rd_addr_reg_n_0_[4] ),
        .I4(Q),
        .I5(\rd_addr_reg_n_0_[0] ),
        .O(\dout_o[3]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h00000000019C0421)) 
    \dout_o[3]_i_3 
       (.I0(\rd_addr_reg_n_0_[4] ),
        .I1(Q),
        .I2(\rd_addr_reg_n_0_[0] ),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(\rd_addr_reg_n_0_[3] ),
        .I5(\rd_addr_reg_n_0_[5] ),
        .O(\dout_o[3]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h2DCA4E194B652751)) 
    \dout_o[3]_i_4 
       (.I0(\rd_addr_reg_n_0_[5] ),
        .I1(\rd_addr_reg_n_0_[3] ),
        .I2(\rd_addr_reg_n_0_[2] ),
        .I3(Q),
        .I4(\rd_addr_reg_n_0_[4] ),
        .I5(\rd_addr_reg_n_0_[0] ),
        .O(\dout_o[3]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \dout_o[4]_i_1 
       (.I0(\dout_o[4]_i_2_n_0 ),
        .I1(\rd_addr_reg_n_0_[6] ),
        .I2(\dout_o[4]_i_3_n_0 ),
        .I3(\rd_addr_reg_n_0_[7] ),
        .I4(\dout_o[4]_i_4_n_0 ),
        .O(\dout_o[4]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hD87BBD58DE86587B)) 
    \dout_o[4]_i_2 
       (.I0(\rd_addr_reg_n_0_[5] ),
        .I1(\rd_addr_reg_n_0_[3] ),
        .I2(\rd_addr_reg_n_0_[2] ),
        .I3(\rd_addr_reg_n_0_[0] ),
        .I4(\rd_addr_reg_n_0_[4] ),
        .I5(Q),
        .O(\dout_o[4]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h000000000455F0E2)) 
    \dout_o[4]_i_3 
       (.I0(\rd_addr_reg_n_0_[4] ),
        .I1(\rd_addr_reg_n_0_[0] ),
        .I2(Q),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(\rd_addr_reg_n_0_[3] ),
        .I5(\rd_addr_reg_n_0_[5] ),
        .O(\dout_o[4]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h1A563E3E1BBEA40C)) 
    \dout_o[4]_i_4 
       (.I0(\rd_addr_reg_n_0_[5] ),
        .I1(\rd_addr_reg_n_0_[3] ),
        .I2(\rd_addr_reg_n_0_[2] ),
        .I3(\rd_addr_reg_n_0_[4] ),
        .I4(Q),
        .I5(\rd_addr_reg_n_0_[0] ),
        .O(\dout_o[4]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \dout_o[5]_i_1 
       (.I0(\dout_o[5]_i_2_n_0 ),
        .I1(\rd_addr_reg_n_0_[6] ),
        .I2(\dout_o[5]_i_3_n_0 ),
        .I3(\rd_addr_reg_n_0_[7] ),
        .I4(\dout_o[5]_i_4_n_0 ),
        .O(\dout_o[5]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h42588642FDA55AFD)) 
    \dout_o[5]_i_2 
       (.I0(\rd_addr_reg_n_0_[5] ),
        .I1(\rd_addr_reg_n_0_[3] ),
        .I2(\rd_addr_reg_n_0_[2] ),
        .I3(\rd_addr_reg_n_0_[4] ),
        .I4(Q),
        .I5(\rd_addr_reg_n_0_[0] ),
        .O(\dout_o[5]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000013A810A9)) 
    \dout_o[5]_i_3 
       (.I0(Q),
        .I1(\rd_addr_reg_n_0_[4] ),
        .I2(\rd_addr_reg_n_0_[0] ),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(\rd_addr_reg_n_0_[3] ),
        .I5(\rd_addr_reg_n_0_[5] ),
        .O(\dout_o[5]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h183B5DF6A40A3E0D)) 
    \dout_o[5]_i_4 
       (.I0(\rd_addr_reg_n_0_[5] ),
        .I1(\rd_addr_reg_n_0_[3] ),
        .I2(\rd_addr_reg_n_0_[2] ),
        .I3(\rd_addr_reg_n_0_[0] ),
        .I4(\rd_addr_reg_n_0_[4] ),
        .I5(Q),
        .O(\dout_o[5]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \dout_o[6]_i_1 
       (.I0(\dout_o[6]_i_2_n_0 ),
        .I1(\rd_addr_reg_n_0_[6] ),
        .I2(\dout_o[6]_i_3_n_0 ),
        .I3(\rd_addr_reg_n_0_[7] ),
        .I4(\dout_o[6]_i_4_n_0 ),
        .O(\dout_o[6]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hA35A585A84A7235A)) 
    \dout_o[6]_i_2 
       (.I0(\rd_addr_reg_n_0_[5] ),
        .I1(\rd_addr_reg_n_0_[3] ),
        .I2(\rd_addr_reg_n_0_[2] ),
        .I3(\rd_addr_reg_n_0_[0] ),
        .I4(\rd_addr_reg_n_0_[4] ),
        .I5(Q),
        .O(\dout_o[6]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h000000004441C9B1)) 
    \dout_o[6]_i_3 
       (.I0(\rd_addr_reg_n_0_[4] ),
        .I1(Q),
        .I2(\rd_addr_reg_n_0_[0] ),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(\rd_addr_reg_n_0_[3] ),
        .I5(\rd_addr_reg_n_0_[5] ),
        .O(\dout_o[6]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h00D98F5FB527B08E)) 
    \dout_o[6]_i_4 
       (.I0(\rd_addr_reg_n_0_[5] ),
        .I1(\rd_addr_reg_n_0_[3] ),
        .I2(\rd_addr_reg_n_0_[2] ),
        .I3(\rd_addr_reg_n_0_[4] ),
        .I4(\rd_addr_reg_n_0_[0] ),
        .I5(Q),
        .O(\dout_o[6]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \dout_o[7]_i_1 
       (.I0(\dout_o[7]_i_2_n_0 ),
        .I1(\rd_addr_reg_n_0_[6] ),
        .I2(\dout_o[7]_i_3_n_0 ),
        .I3(\rd_addr_reg_n_0_[7] ),
        .I4(\dout_o[7]_i_4_n_0 ),
        .O(\dout_o[7]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h5C00BF1AFFA5DC00)) 
    \dout_o[7]_i_2 
       (.I0(\rd_addr_reg_n_0_[5] ),
        .I1(\rd_addr_reg_n_0_[3] ),
        .I2(\rd_addr_reg_n_0_[2] ),
        .I3(\rd_addr_reg_n_0_[0] ),
        .I4(\rd_addr_reg_n_0_[4] ),
        .I5(Q),
        .O(\dout_o[7]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000016D00494)) 
    \dout_o[7]_i_3 
       (.I0(\rd_addr_reg_n_0_[4] ),
        .I1(Q),
        .I2(\rd_addr_reg_n_0_[0] ),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(\rd_addr_reg_n_0_[3] ),
        .I5(\rd_addr_reg_n_0_[5] ),
        .O(\dout_o[7]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'hAA852B305155E79F)) 
    \dout_o[7]_i_4 
       (.I0(\rd_addr_reg_n_0_[5] ),
        .I1(\rd_addr_reg_n_0_[3] ),
        .I2(\rd_addr_reg_n_0_[2] ),
        .I3(\rd_addr_reg_n_0_[0] ),
        .I4(Q),
        .I5(\rd_addr_reg_n_0_[4] ),
        .O(\dout_o[7]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'hFCBBFC88)) 
    \dout_o[8]_i_1 
       (.I0(\dout_o[8]_i_2_n_0 ),
        .I1(\rd_addr_reg_n_0_[6] ),
        .I2(\dout_o[8]_i_3_n_0 ),
        .I3(\rd_addr_reg_n_0_[7] ),
        .I4(\dout_o[8]_i_4_n_0 ),
        .O(\dout_o[8]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h91C9002800211311)) 
    \dout_o[8]_i_2 
       (.I0(\rd_addr_reg_n_0_[5] ),
        .I1(\rd_addr_reg_n_0_[3] ),
        .I2(\rd_addr_reg_n_0_[2] ),
        .I3(\rd_addr_reg_n_0_[4] ),
        .I4(\rd_addr_reg_n_0_[0] ),
        .I5(Q),
        .O(\dout_o[8]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFD8D3F245)) 
    \dout_o[8]_i_3 
       (.I0(\rd_addr_reg_n_0_[0] ),
        .I1(\rd_addr_reg_n_0_[4] ),
        .I2(Q),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(\rd_addr_reg_n_0_[3] ),
        .I5(\rd_addr_reg_n_0_[5] ),
        .O(\dout_o[8]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h0A06800432120528)) 
    \dout_o[8]_i_4 
       (.I0(\rd_addr_reg_n_0_[5] ),
        .I1(\rd_addr_reg_n_0_[3] ),
        .I2(Q),
        .I3(\rd_addr_reg_n_0_[4] ),
        .I4(\rd_addr_reg_n_0_[0] ),
        .I5(\rd_addr_reg_n_0_[2] ),
        .O(\dout_o[8]_i_4_n_0 ));
  LUT5 #(
    .INIT(32'h30BB3088)) 
    \dout_o[9]_i_1 
       (.I0(\dout_o[9]_i_2_n_0 ),
        .I1(\rd_addr_reg_n_0_[6] ),
        .I2(\dout_o[9]_i_3_n_0 ),
        .I3(\rd_addr_reg_n_0_[7] ),
        .I4(\dout_o[9]_i_4_n_0 ),
        .O(\dout_o[9]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hF3F5C3DC0AE47A65)) 
    \dout_o[9]_i_2 
       (.I0(\rd_addr_reg_n_0_[5] ),
        .I1(\rd_addr_reg_n_0_[3] ),
        .I2(\rd_addr_reg_n_0_[2] ),
        .I3(\rd_addr_reg_n_0_[0] ),
        .I4(\rd_addr_reg_n_0_[4] ),
        .I5(Q),
        .O(\dout_o[9]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h00000000040E06D5)) 
    \dout_o[9]_i_3 
       (.I0(\rd_addr_reg_n_0_[0] ),
        .I1(Q),
        .I2(\rd_addr_reg_n_0_[4] ),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(\rd_addr_reg_n_0_[3] ),
        .I5(\rd_addr_reg_n_0_[5] ),
        .O(\dout_o[9]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h20350802BEE285FB)) 
    \dout_o[9]_i_4 
       (.I0(\rd_addr_reg_n_0_[5] ),
        .I1(\rd_addr_reg_n_0_[3] ),
        .I2(\rd_addr_reg_n_0_[4] ),
        .I3(\rd_addr_reg_n_0_[2] ),
        .I4(\rd_addr_reg_n_0_[0] ),
        .I5(Q),
        .O(\dout_o[9]_i_4_n_0 ));
  FDRE \dout_o_reg[0] 
       (.C(\dout_o_reg[15]_2 ),
        .CE(1'b1),
        .D(\dout_o[0]_i_1_n_0 ),
        .Q(\dout_o_reg_n_0_[0] ),
        .R(1'b0));
  FDRE \dout_o_reg[10] 
       (.C(\dout_o_reg[15]_2 ),
        .CE(1'b1),
        .D(\dout_o[10]_i_1_n_0 ),
        .Q(p_1_in772_in),
        .R(1'b0));
  FDRE \dout_o_reg[11] 
       (.C(\dout_o_reg[15]_2 ),
        .CE(1'b1),
        .D(\dout_o[11]_i_1_n_0 ),
        .Q(p_1_in642_in),
        .R(1'b0));
  FDRE \dout_o_reg[12] 
       (.C(\dout_o_reg[15]_2 ),
        .CE(1'b1),
        .D(\dout_o[12]_i_1_n_0 ),
        .Q(p_1_in512_in),
        .R(1'b0));
  FDRE \dout_o_reg[13] 
       (.C(\dout_o_reg[15]_2 ),
        .CE(1'b1),
        .D(\dout_o[13]_i_1_n_0 ),
        .Q(p_1_in382_in),
        .R(1'b0));
  FDRE \dout_o_reg[14] 
       (.C(\dout_o_reg[15]_2 ),
        .CE(1'b1),
        .D(\dout_o[14]_i_1_n_0 ),
        .Q(p_1_in252_in),
        .R(1'b0));
  FDRE \dout_o_reg[15] 
       (.C(\dout_o_reg[15]_2 ),
        .CE(1'b1),
        .D(\dout_o[15]_i_1_n_0 ),
        .Q(p_1_in),
        .R(1'b0));
  FDRE \dout_o_reg[1] 
       (.C(\dout_o_reg[15]_2 ),
        .CE(1'b1),
        .D(\dout_o[1]_i_1_n_0 ),
        .Q(p_2_in904_in),
        .R(1'b0));
  FDRE \dout_o_reg[2] 
       (.C(\dout_o_reg[15]_2 ),
        .CE(1'b1),
        .D(\dout_o[2]_i_1_n_0 ),
        .Q(p_2_in774_in),
        .R(1'b0));
  FDRE \dout_o_reg[3] 
       (.C(\dout_o_reg[15]_2 ),
        .CE(1'b1),
        .D(\dout_o[3]_i_1_n_0 ),
        .Q(p_2_in644_in),
        .R(1'b0));
  FDRE \dout_o_reg[4] 
       (.C(\dout_o_reg[15]_2 ),
        .CE(1'b1),
        .D(\dout_o[4]_i_1_n_0 ),
        .Q(p_2_in514_in),
        .R(1'b0));
  FDRE \dout_o_reg[5] 
       (.C(\dout_o_reg[15]_2 ),
        .CE(1'b1),
        .D(\dout_o[5]_i_1_n_0 ),
        .Q(p_2_in384_in),
        .R(1'b0));
  FDRE \dout_o_reg[6] 
       (.C(\dout_o_reg[15]_2 ),
        .CE(1'b1),
        .D(\dout_o[6]_i_1_n_0 ),
        .Q(p_2_in254_in),
        .R(1'b0));
  FDRE \dout_o_reg[7] 
       (.C(\dout_o_reg[15]_2 ),
        .CE(1'b1),
        .D(\dout_o[7]_i_1_n_0 ),
        .Q(p_2_in),
        .R(1'b0));
  FDRE \dout_o_reg[8] 
       (.C(\dout_o_reg[15]_2 ),
        .CE(1'b1),
        .D(\dout_o[8]_i_1_n_0 ),
        .Q(p_1_in1032_in),
        .R(1'b0));
  FDRE \dout_o_reg[9] 
       (.C(\dout_o_reg[15]_2 ),
        .CE(1'b1),
        .D(\dout_o[9]_i_1_n_0 ),
        .Q(p_1_in902_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair558" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_mux_rd[0].compare_data_fall0_r1[0]_i_1 
       (.I0(p_2_in254_in),
        .I1(p_0_in222_in),
        .I2(p_1_in252_in),
        .O(prbs_out[8]));
  (* SOFT_HLUTNM = "soft_lutpair574" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_mux_rd[0].compare_data_fall1_r1[0]_i_1 
       (.I0(p_2_in514_in),
        .I1(p_0_in222_in),
        .I2(p_1_in512_in),
        .O(prbs_out[24]));
  (* SOFT_HLUTNM = "soft_lutpair600" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_mux_rd[0].compare_data_fall2_r1[0]_i_1 
       (.I0(p_2_in774_in),
        .I1(p_0_in222_in),
        .I2(p_1_in772_in),
        .O(prbs_out[40]));
  (* SOFT_HLUTNM = "soft_lutpair595" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_mux_rd[0].compare_data_fall3_r1[0]_i_1 
       (.I0(\dout_o_reg_n_0_[0] ),
        .I1(p_0_in222_in),
        .I2(p_1_in1032_in),
        .O(prbs_out[56]));
  (* SOFT_HLUTNM = "soft_lutpair601" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_mux_rd[0].compare_data_rise0_r1[0]_i_1 
       (.I0(p_2_in),
        .I1(p_0_in222_in),
        .I2(p_1_in),
        .O(prbs_out[0]));
  (* SOFT_HLUTNM = "soft_lutpair576" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_mux_rd[0].compare_data_rise1_r1[0]_i_1 
       (.I0(p_2_in384_in),
        .I1(p_0_in222_in),
        .I2(p_1_in382_in),
        .O(prbs_out[16]));
  (* SOFT_HLUTNM = "soft_lutpair563" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_mux_rd[0].compare_data_rise2_r1[0]_i_1 
       (.I0(p_2_in644_in),
        .I1(p_0_in222_in),
        .I2(p_1_in642_in),
        .O(prbs_out[32]));
  (* SOFT_HLUTNM = "soft_lutpair598" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_mux_rd[0].compare_data_rise3_r1[0]_i_1 
       (.I0(p_2_in904_in),
        .I1(p_0_in222_in),
        .I2(p_1_in902_in),
        .O(prbs_out[48]));
  (* SOFT_HLUTNM = "soft_lutpair608" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_mux_rd[1].compare_data_fall0_r1[1]_i_1 
       (.I0(p_2_in254_in),
        .I1(p_0_in226_in),
        .I2(p_1_in252_in),
        .O(prbs_out[9]));
  (* SOFT_HLUTNM = "soft_lutpair577" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_mux_rd[1].compare_data_fall1_r1[1]_i_1 
       (.I0(p_2_in514_in),
        .I1(p_0_in226_in),
        .I2(p_1_in512_in),
        .O(prbs_out[25]));
  (* SOFT_HLUTNM = "soft_lutpair585" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_mux_rd[1].compare_data_fall2_r1[1]_i_1 
       (.I0(p_2_in774_in),
        .I1(p_0_in226_in),
        .I2(p_1_in772_in),
        .O(prbs_out[41]));
  (* SOFT_HLUTNM = "soft_lutpair559" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_mux_rd[1].compare_data_fall3_r1[1]_i_1 
       (.I0(\dout_o_reg_n_0_[0] ),
        .I1(p_0_in226_in),
        .I2(p_1_in1032_in),
        .O(prbs_out[57]));
  (* SOFT_HLUTNM = "soft_lutpair602" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_mux_rd[1].compare_data_rise0_r1[1]_i_1 
       (.I0(p_2_in),
        .I1(p_0_in226_in),
        .I2(p_1_in),
        .O(prbs_out[1]));
  (* SOFT_HLUTNM = "soft_lutpair605" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_mux_rd[1].compare_data_rise1_r1[1]_i_1 
       (.I0(p_2_in384_in),
        .I1(p_0_in226_in),
        .I2(p_1_in382_in),
        .O(prbs_out[17]));
  (* SOFT_HLUTNM = "soft_lutpair593" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_mux_rd[1].compare_data_rise2_r1[1]_i_1 
       (.I0(p_2_in644_in),
        .I1(p_0_in226_in),
        .I2(p_1_in642_in),
        .O(prbs_out[33]));
  (* SOFT_HLUTNM = "soft_lutpair598" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_mux_rd[1].compare_data_rise3_r1[1]_i_1 
       (.I0(p_2_in904_in),
        .I1(p_0_in226_in),
        .I2(p_1_in902_in),
        .O(prbs_out[49]));
  (* SOFT_HLUTNM = "soft_lutpair608" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_mux_rd[2].compare_data_fall0_r1[2]_i_1 
       (.I0(p_2_in254_in),
        .I1(p_0_in230_in),
        .I2(p_1_in252_in),
        .O(prbs_out[10]));
  (* SOFT_HLUTNM = "soft_lutpair603" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_mux_rd[2].compare_data_fall1_r1[2]_i_1 
       (.I0(p_2_in514_in),
        .I1(p_0_in230_in),
        .I2(p_1_in512_in),
        .O(prbs_out[26]));
  (* SOFT_HLUTNM = "soft_lutpair573" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_mux_rd[2].compare_data_fall2_r1[2]_i_1 
       (.I0(p_2_in774_in),
        .I1(p_0_in230_in),
        .I2(p_1_in772_in),
        .O(prbs_out[42]));
  (* SOFT_HLUTNM = "soft_lutpair595" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_mux_rd[2].compare_data_fall3_r1[2]_i_1 
       (.I0(\dout_o_reg_n_0_[0] ),
        .I1(p_0_in230_in),
        .I2(p_1_in1032_in),
        .O(prbs_out[58]));
  (* SOFT_HLUTNM = "soft_lutpair557" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_mux_rd[2].compare_data_rise0_r1[2]_i_1 
       (.I0(p_2_in),
        .I1(p_0_in230_in),
        .I2(p_1_in),
        .O(prbs_out[2]));
  (* SOFT_HLUTNM = "soft_lutpair570" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_mux_rd[2].compare_data_rise1_r1[2]_i_1 
       (.I0(p_2_in384_in),
        .I1(p_0_in230_in),
        .I2(p_1_in382_in),
        .O(prbs_out[18]));
  (* SOFT_HLUTNM = "soft_lutpair591" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_mux_rd[2].compare_data_rise2_r1[2]_i_1 
       (.I0(p_2_in644_in),
        .I1(p_0_in230_in),
        .I2(p_1_in642_in),
        .O(prbs_out[34]));
  (* SOFT_HLUTNM = "soft_lutpair572" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_mux_rd[2].compare_data_rise3_r1[2]_i_1 
       (.I0(p_2_in904_in),
        .I1(p_0_in230_in),
        .I2(p_1_in902_in),
        .O(prbs_out[50]));
  (* SOFT_HLUTNM = "soft_lutpair607" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_mux_rd[3].compare_data_fall0_r1[3]_i_1 
       (.I0(p_2_in254_in),
        .I1(p_0_in234_in),
        .I2(p_1_in252_in),
        .O(prbs_out[11]));
  (* SOFT_HLUTNM = "soft_lutpair582" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_mux_rd[3].compare_data_fall1_r1[3]_i_1 
       (.I0(p_2_in514_in),
        .I1(p_0_in234_in),
        .I2(p_1_in512_in),
        .O(prbs_out[27]));
  (* SOFT_HLUTNM = "soft_lutpair600" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_mux_rd[3].compare_data_fall2_r1[3]_i_1 
       (.I0(p_2_in774_in),
        .I1(p_0_in234_in),
        .I2(p_1_in772_in),
        .O(prbs_out[43]));
  (* SOFT_HLUTNM = "soft_lutpair561" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_mux_rd[3].compare_data_fall3_r1[3]_i_1 
       (.I0(\dout_o_reg_n_0_[0] ),
        .I1(p_0_in234_in),
        .I2(p_1_in1032_in),
        .O(prbs_out[59]));
  (* SOFT_HLUTNM = "soft_lutpair609" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_mux_rd[3].compare_data_rise0_r1[3]_i_1 
       (.I0(p_2_in),
        .I1(p_0_in234_in),
        .I2(p_1_in),
        .O(prbs_out[3]));
  (* SOFT_HLUTNM = "soft_lutpair605" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_mux_rd[3].compare_data_rise1_r1[3]_i_1 
       (.I0(p_2_in384_in),
        .I1(p_0_in234_in),
        .I2(p_1_in382_in),
        .O(prbs_out[19]));
  (* SOFT_HLUTNM = "soft_lutpair587" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_mux_rd[3].compare_data_rise2_r1[3]_i_1 
       (.I0(p_2_in644_in),
        .I1(p_0_in234_in),
        .I2(p_1_in642_in),
        .O(prbs_out[35]));
  (* SOFT_HLUTNM = "soft_lutpair597" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_mux_rd[3].compare_data_rise3_r1[3]_i_1 
       (.I0(p_2_in904_in),
        .I1(p_0_in234_in),
        .I2(p_1_in902_in),
        .O(prbs_out[51]));
  (* SOFT_HLUTNM = "soft_lutpair567" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_mux_rd[4].compare_data_fall0_r1[4]_i_1 
       (.I0(p_2_in254_in),
        .I1(p_0_in238_in),
        .I2(p_1_in252_in),
        .O(prbs_out[12]));
  (* SOFT_HLUTNM = "soft_lutpair562" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_mux_rd[4].compare_data_fall1_r1[4]_i_1 
       (.I0(p_2_in514_in),
        .I1(p_0_in238_in),
        .I2(p_1_in512_in),
        .O(prbs_out[28]));
  (* SOFT_HLUTNM = "soft_lutpair583" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_mux_rd[4].compare_data_fall2_r1[4]_i_1 
       (.I0(p_2_in774_in),
        .I1(p_0_in238_in),
        .I2(p_1_in772_in),
        .O(prbs_out[44]));
  (* SOFT_HLUTNM = "soft_lutpair594" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_mux_rd[4].compare_data_fall3_r1[4]_i_1 
       (.I0(\dout_o_reg_n_0_[0] ),
        .I1(p_0_in238_in),
        .I2(p_1_in1032_in),
        .O(prbs_out[60]));
  (* SOFT_HLUTNM = "soft_lutpair609" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_mux_rd[4].compare_data_rise0_r1[4]_i_1 
       (.I0(p_2_in),
        .I1(p_0_in238_in),
        .I2(p_1_in),
        .O(prbs_out[4]));
  (* SOFT_HLUTNM = "soft_lutpair575" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_mux_rd[4].compare_data_rise1_r1[4]_i_1 
       (.I0(p_2_in384_in),
        .I1(p_0_in238_in),
        .I2(p_1_in382_in),
        .O(prbs_out[20]));
  (* SOFT_HLUTNM = "soft_lutpair564" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_mux_rd[4].compare_data_rise2_r1[4]_i_1 
       (.I0(p_2_in644_in),
        .I1(p_0_in238_in),
        .I2(p_1_in642_in),
        .O(prbs_out[36]));
  (* SOFT_HLUTNM = "soft_lutpair597" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_mux_rd[4].compare_data_rise3_r1[4]_i_1 
       (.I0(p_2_in904_in),
        .I1(p_0_in238_in),
        .I2(p_1_in902_in),
        .O(prbs_out[52]));
  (* SOFT_HLUTNM = "soft_lutpair607" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_mux_rd[5].compare_data_fall0_r1[5]_i_1 
       (.I0(p_2_in254_in),
        .I1(p_0_in242_in),
        .I2(p_1_in252_in),
        .O(prbs_out[13]));
  (* SOFT_HLUTNM = "soft_lutpair579" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_mux_rd[5].compare_data_fall1_r1[5]_i_1 
       (.I0(p_2_in514_in),
        .I1(p_0_in242_in),
        .I2(p_1_in512_in),
        .O(prbs_out[29]));
  (* SOFT_HLUTNM = "soft_lutpair599" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_mux_rd[5].compare_data_fall2_r1[5]_i_1 
       (.I0(p_2_in774_in),
        .I1(p_0_in242_in),
        .I2(p_1_in772_in),
        .O(prbs_out[45]));
  (* SOFT_HLUTNM = "soft_lutpair560" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_mux_rd[5].compare_data_fall3_r1[5]_i_1 
       (.I0(\dout_o_reg_n_0_[0] ),
        .I1(p_0_in242_in),
        .I2(p_1_in1032_in),
        .O(prbs_out[61]));
  (* SOFT_HLUTNM = "soft_lutpair602" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_mux_rd[5].compare_data_rise0_r1[5]_i_1 
       (.I0(p_2_in),
        .I1(p_0_in242_in),
        .I2(p_1_in),
        .O(prbs_out[5]));
  (* SOFT_HLUTNM = "soft_lutpair604" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_mux_rd[5].compare_data_rise1_r1[5]_i_1 
       (.I0(p_2_in384_in),
        .I1(p_0_in242_in),
        .I2(p_1_in382_in),
        .O(prbs_out[21]));
  (* SOFT_HLUTNM = "soft_lutpair593" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_mux_rd[5].compare_data_rise2_r1[5]_i_1 
       (.I0(p_2_in644_in),
        .I1(p_0_in242_in),
        .I2(p_1_in642_in),
        .O(prbs_out[37]));
  (* SOFT_HLUTNM = "soft_lutpair596" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_mux_rd[5].compare_data_rise3_r1[5]_i_1 
       (.I0(p_2_in904_in),
        .I1(p_0_in242_in),
        .I2(p_1_in902_in),
        .O(prbs_out[53]));
  (* SOFT_HLUTNM = "soft_lutpair606" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_mux_rd[6].compare_data_fall0_r1[6]_i_1 
       (.I0(p_2_in254_in),
        .I1(p_0_in246_in),
        .I2(p_1_in252_in),
        .O(prbs_out[14]));
  (* SOFT_HLUTNM = "soft_lutpair603" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_mux_rd[6].compare_data_fall1_r1[6]_i_1 
       (.I0(p_2_in514_in),
        .I1(p_0_in246_in),
        .I2(p_1_in512_in),
        .O(prbs_out[30]));
  (* SOFT_HLUTNM = "soft_lutpair566" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_mux_rd[6].compare_data_fall2_r1[6]_i_1 
       (.I0(p_2_in774_in),
        .I1(p_0_in246_in),
        .I2(p_1_in772_in),
        .O(prbs_out[46]));
  (* SOFT_HLUTNM = "soft_lutpair594" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_mux_rd[6].compare_data_fall3_r1[6]_i_1 
       (.I0(\dout_o_reg_n_0_[0] ),
        .I1(p_0_in246_in),
        .I2(p_1_in1032_in),
        .O(prbs_out[62]));
  (* SOFT_HLUTNM = "soft_lutpair569" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_mux_rd[6].compare_data_rise0_r1[6]_i_1 
       (.I0(p_2_in),
        .I1(p_0_in246_in),
        .I2(p_1_in),
        .O(prbs_out[6]));
  (* SOFT_HLUTNM = "soft_lutpair568" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_mux_rd[6].compare_data_rise1_r1[6]_i_1 
       (.I0(p_2_in384_in),
        .I1(p_0_in246_in),
        .I2(p_1_in382_in),
        .O(prbs_out[22]));
  (* SOFT_HLUTNM = "soft_lutpair591" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_mux_rd[6].compare_data_rise2_r1[6]_i_1 
       (.I0(p_2_in644_in),
        .I1(p_0_in246_in),
        .I2(p_1_in642_in),
        .O(prbs_out[38]));
  (* SOFT_HLUTNM = "soft_lutpair571" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_mux_rd[6].compare_data_rise3_r1[6]_i_1 
       (.I0(p_2_in904_in),
        .I1(p_0_in246_in),
        .I2(p_1_in902_in),
        .O(prbs_out[54]));
  (* SOFT_HLUTNM = "soft_lutpair606" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_mux_rd[7].compare_data_fall0_r1[7]_i_1 
       (.I0(p_2_in254_in),
        .I1(p_0_in250_in),
        .I2(p_1_in252_in),
        .O(prbs_out[15]));
  (* SOFT_HLUTNM = "soft_lutpair586" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_mux_rd[7].compare_data_fall1_r1[7]_i_1 
       (.I0(p_2_in514_in),
        .I1(p_0_in250_in),
        .I2(p_1_in512_in),
        .O(prbs_out[31]));
  (* SOFT_HLUTNM = "soft_lutpair599" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_mux_rd[7].compare_data_fall2_r1[7]_i_1 
       (.I0(p_2_in774_in),
        .I1(p_0_in250_in),
        .I2(p_1_in772_in),
        .O(prbs_out[47]));
  (* SOFT_HLUTNM = "soft_lutpair565" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_mux_rd[7].compare_data_fall3_r1[7]_i_1 
       (.I0(\dout_o_reg_n_0_[0] ),
        .I1(p_0_in250_in),
        .I2(p_1_in1032_in),
        .O(prbs_out[63]));
  (* SOFT_HLUTNM = "soft_lutpair601" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_mux_rd[7].compare_data_rise0_r1[7]_i_1 
       (.I0(p_2_in),
        .I1(p_0_in250_in),
        .I2(p_1_in),
        .O(prbs_out[7]));
  (* SOFT_HLUTNM = "soft_lutpair604" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_mux_rd[7].compare_data_rise1_r1[7]_i_1 
       (.I0(p_2_in384_in),
        .I1(p_0_in250_in),
        .I2(p_1_in382_in),
        .O(prbs_out[23]));
  (* SOFT_HLUTNM = "soft_lutpair588" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_mux_rd[7].compare_data_rise2_r1[7]_i_1 
       (.I0(p_2_in644_in),
        .I1(p_0_in250_in),
        .I2(p_1_in642_in),
        .O(prbs_out[39]));
  (* SOFT_HLUTNM = "soft_lutpair596" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \gen_mux_rd[7].compare_data_rise3_r1[7]_i_1 
       (.I0(p_2_in904_in),
        .I1(p_0_in250_in),
        .I2(p_1_in902_in),
        .O(prbs_out[55]));
  FDRE phy_if_empty_r_reg
       (.C(\dout_o_reg[15]_2 ),
        .CE(1'b1),
        .D(if_empty),
        .Q(phy_if_empty_r_reg_0),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair590" *) 
  LUT4 #(
    .INIT(16'h3233)) 
    \rd_addr[0]_i_1 
       (.I0(\rd_addr[2]_i_2_n_0 ),
        .I1(\rd_addr_reg_n_0_[0] ),
        .I2(Q),
        .I3(\rd_addr_reg_n_0_[2] ),
        .O(p_1_in__0[0]));
  LUT2 #(
    .INIT(4'h6)) 
    \rd_addr[1]_i_1 
       (.I0(\rd_addr_reg_n_0_[0] ),
        .I1(Q),
        .O(p_1_in__0[1]));
  (* SOFT_HLUTNM = "soft_lutpair590" *) 
  LUT4 #(
    .INIT(16'h7868)) 
    \rd_addr[2]_i_1 
       (.I0(\rd_addr_reg_n_0_[0] ),
        .I1(Q),
        .I2(\rd_addr_reg_n_0_[2] ),
        .I3(\rd_addr[2]_i_2_n_0 ),
        .O(p_1_in__0[2]));
  LUT6 #(
    .INIT(64'hFFFFFFF7FFF7FFFF)) 
    \rd_addr[2]_i_2 
       (.I0(\rd_addr_reg_n_0_[4] ),
        .I1(\rd_addr_reg_n_0_[7] ),
        .I2(\rd_addr_reg_n_0_[5] ),
        .I3(\rd_addr_reg_n_0_[6] ),
        .I4(\rd_addr_reg[0]_0 ),
        .I5(\rd_addr_reg_n_0_[3] ),
        .O(\rd_addr[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hBFFFFFBFFAAAAAAA)) 
    \rd_addr[3]_i_1 
       (.I0(\rd_addr[3]_i_2_n_0 ),
        .I1(\rd_addr_reg[3]_0 ),
        .I2(\rd_addr_reg_n_0_[2] ),
        .I3(\rd_addr_reg_n_0_[0] ),
        .I4(Q),
        .I5(\rd_addr_reg_n_0_[3] ),
        .O(p_1_in__0[3]));
  LUT6 #(
    .INIT(64'h4444444444440444)) 
    \rd_addr[3]_i_2 
       (.I0(Q),
        .I1(\rd_addr_reg_n_0_[3] ),
        .I2(\rd_addr_reg_n_0_[7] ),
        .I3(\rd_addr_reg_n_0_[4] ),
        .I4(\rd_addr_reg_n_0_[5] ),
        .I5(\rd_addr_reg_n_0_[6] ),
        .O(\rd_addr[3]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFF2222000F2222)) 
    \rd_addr[4]_i_1 
       (.I0(\rd_addr_reg_n_0_[3] ),
        .I1(\rd_addr[4]_i_2_n_0 ),
        .I2(\rd_addr_reg_n_0_[7] ),
        .I3(Q),
        .I4(\rd_addr_reg_n_0_[4] ),
        .I5(\rd_addr[7]_i_4_n_0 ),
        .O(p_1_in__0[4]));
  (* SOFT_HLUTNM = "soft_lutpair556" *) 
  LUT3 #(
    .INIT(8'h7F)) 
    \rd_addr[4]_i_2 
       (.I0(Q),
        .I1(\rd_addr_reg_n_0_[0] ),
        .I2(\rd_addr_reg_n_0_[2] ),
        .O(\rd_addr[4]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \rd_addr[5]_i_1 
       (.I0(Q),
        .I1(\rd_addr_reg_n_0_[0] ),
        .I2(\rd_addr_reg_n_0_[2] ),
        .I3(\rd_addr_reg_n_0_[3] ),
        .I4(\rd_addr_reg_n_0_[4] ),
        .I5(\rd_addr_reg_n_0_[5] ),
        .O(p_1_in__0[5]));
  (* SOFT_HLUTNM = "soft_lutpair592" *) 
  LUT3 #(
    .INIT(8'hD2)) 
    \rd_addr[6]_i_1 
       (.I0(\rd_addr_reg_n_0_[5] ),
        .I1(\rd_addr[7]_i_6_n_0 ),
        .I2(\rd_addr_reg_n_0_[6] ),
        .O(p_1_in__0[6]));
  LUT6 #(
    .INIT(64'hE0A0E0AFF0F0F0FF)) 
    \rd_addr[7]_i_3 
       (.I0(\rd_addr[7]_i_4_n_0 ),
        .I1(Q),
        .I2(\rd_addr_reg_n_0_[7] ),
        .I3(\rd_addr[7]_i_5_n_0 ),
        .I4(\rd_addr[7]_i_6_n_0 ),
        .I5(\rd_addr_reg_n_0_[4] ),
        .O(p_1_in__0[7]));
  LUT6 #(
    .INIT(64'h77FDFFFFFFFF77FD)) 
    \rd_addr[7]_i_4 
       (.I0(\rd_addr_reg_n_0_[2] ),
        .I1(\rd_addr_reg_n_0_[0] ),
        .I2(\rd_addr[7]_i_7_n_0 ),
        .I3(Q),
        .I4(\rd_addr_reg[3]_0 ),
        .I5(\rd_addr_reg_n_0_[3] ),
        .O(\rd_addr[7]_i_4_n_0 ));
  LUT2 #(
    .INIT(4'h7)) 
    \rd_addr[7]_i_5 
       (.I0(\rd_addr_reg_n_0_[5] ),
        .I1(\rd_addr_reg_n_0_[6] ),
        .O(\rd_addr[7]_i_5_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair556" *) 
  LUT5 #(
    .INIT(32'h7FFFFFFF)) 
    \rd_addr[7]_i_6 
       (.I0(\rd_addr_reg_n_0_[4] ),
        .I1(\rd_addr_reg_n_0_[3] ),
        .I2(\rd_addr_reg_n_0_[2] ),
        .I3(\rd_addr_reg_n_0_[0] ),
        .I4(Q),
        .O(\rd_addr[7]_i_6_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair592" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \rd_addr[7]_i_7 
       (.I0(\rd_addr_reg_n_0_[5] ),
        .I1(\rd_addr_reg_n_0_[6] ),
        .O(\rd_addr[7]_i_7_n_0 ));
  (* RAM_STYLE = "distributed" *) 
  FDRE \rd_addr_reg[0] 
       (.C(\dout_o_reg[15]_2 ),
        .CE(E),
        .D(p_1_in__0[0]),
        .Q(\rd_addr_reg_n_0_[0] ),
        .R(SR));
  (* RAM_STYLE = "distributed" *) 
  FDRE \rd_addr_reg[1] 
       (.C(\dout_o_reg[15]_2 ),
        .CE(E),
        .D(p_1_in__0[1]),
        .Q(Q),
        .R(SR));
  (* RAM_STYLE = "distributed" *) 
  FDRE \rd_addr_reg[2] 
       (.C(\dout_o_reg[15]_2 ),
        .CE(E),
        .D(p_1_in__0[2]),
        .Q(\rd_addr_reg_n_0_[2] ),
        .R(SR));
  (* RAM_STYLE = "distributed" *) 
  FDRE \rd_addr_reg[3] 
       (.C(\dout_o_reg[15]_2 ),
        .CE(E),
        .D(p_1_in__0[3]),
        .Q(\rd_addr_reg_n_0_[3] ),
        .R(SR));
  (* RAM_STYLE = "distributed" *) 
  FDRE \rd_addr_reg[4] 
       (.C(\dout_o_reg[15]_2 ),
        .CE(E),
        .D(p_1_in__0[4]),
        .Q(\rd_addr_reg_n_0_[4] ),
        .R(SR));
  (* RAM_STYLE = "distributed" *) 
  FDRE \rd_addr_reg[5] 
       (.C(\dout_o_reg[15]_2 ),
        .CE(E),
        .D(p_1_in__0[5]),
        .Q(\rd_addr_reg_n_0_[5] ),
        .R(SR));
  (* RAM_STYLE = "distributed" *) 
  FDRE \rd_addr_reg[6] 
       (.C(\dout_o_reg[15]_2 ),
        .CE(E),
        .D(p_1_in__0[6]),
        .Q(\rd_addr_reg_n_0_[6] ),
        .R(SR));
  (* RAM_STYLE = "distributed" *) 
  FDRE \rd_addr_reg[7] 
       (.C(\dout_o_reg[15]_2 ),
        .CE(E),
        .D(p_1_in__0[7]),
        .Q(\rd_addr_reg_n_0_[7] ),
        .R(SR));
  FDRE \victim_sel_rotate.sel_reg[56] 
       (.C(\dout_o_reg[15]_2 ),
        .CE(1'b1),
        .D(D[0]),
        .Q(p_0_in222_in),
        .R(\victim_sel_rotate.sel_reg[56]_0 ));
  FDRE \victim_sel_rotate.sel_reg[57] 
       (.C(\dout_o_reg[15]_2 ),
        .CE(1'b1),
        .D(D[1]),
        .Q(p_0_in226_in),
        .R(\victim_sel_rotate.sel_reg[56]_0 ));
  FDRE \victim_sel_rotate.sel_reg[58] 
       (.C(\dout_o_reg[15]_2 ),
        .CE(1'b1),
        .D(D[2]),
        .Q(p_0_in230_in),
        .R(\victim_sel_rotate.sel_reg[56]_0 ));
  FDRE \victim_sel_rotate.sel_reg[59] 
       (.C(\dout_o_reg[15]_2 ),
        .CE(1'b1),
        .D(D[3]),
        .Q(p_0_in234_in),
        .R(\victim_sel_rotate.sel_reg[56]_0 ));
  FDRE \victim_sel_rotate.sel_reg[60] 
       (.C(\dout_o_reg[15]_2 ),
        .CE(1'b1),
        .D(D[4]),
        .Q(p_0_in238_in),
        .R(\victim_sel_rotate.sel_reg[56]_0 ));
  FDRE \victim_sel_rotate.sel_reg[61] 
       (.C(\dout_o_reg[15]_2 ),
        .CE(1'b1),
        .D(D[5]),
        .Q(p_0_in242_in),
        .R(\victim_sel_rotate.sel_reg[56]_0 ));
  FDRE \victim_sel_rotate.sel_reg[62] 
       (.C(\dout_o_reg[15]_2 ),
        .CE(1'b1),
        .D(D[6]),
        .Q(p_0_in246_in),
        .R(\victim_sel_rotate.sel_reg[56]_0 ));
  FDRE \victim_sel_rotate.sel_reg[63] 
       (.C(\dout_o_reg[15]_2 ),
        .CE(1'b1),
        .D(D[7]),
        .Q(p_0_in250_in),
        .R(\victim_sel_rotate.sel_reg[56]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair558" *) 
  LUT5 #(
    .INIT(32'hE2FFFFFF)) 
    \wrdq_div1_4to1_wrcal_first.phy_wrdata[120]_i_1 
       (.I0(p_1_in252_in),
        .I1(p_0_in222_in),
        .I2(p_2_in254_in),
        .I3(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0 ),
        .I4(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511] ),
        .O(\dout_o_reg[14]_1 ));
  LUT6 #(
    .INIT(64'hA0AAA00088888888)) 
    \wrdq_div1_4to1_wrcal_first.phy_wrdata[121]_i_1 
       (.I0(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511] ),
        .I1(first_rdlvl_pat_r),
        .I2(p_2_in254_in),
        .I3(p_0_in226_in),
        .I4(p_1_in252_in),
        .I5(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0 ),
        .O(wrcal_done_reg));
  (* SOFT_HLUTNM = "soft_lutpair567" *) 
  LUT5 #(
    .INIT(32'hE2FFFFFF)) 
    \wrdq_div1_4to1_wrcal_first.phy_wrdata[124]_i_1 
       (.I0(p_1_in252_in),
        .I1(p_0_in238_in),
        .I2(p_2_in254_in),
        .I3(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0 ),
        .I4(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511] ),
        .O(\dout_o_reg[14]_0 ));
  LUT6 #(
    .INIT(64'hB800FF00B8000000)) 
    \wrdq_div1_4to1_wrcal_first.phy_wrdata[125]_i_1 
       (.I0(p_2_in254_in),
        .I1(p_0_in242_in),
        .I2(p_1_in252_in),
        .I3(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511] ),
        .I4(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0 ),
        .I5(first_rdlvl_pat_r),
        .O(\dout_o_reg[6]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair576" *) 
  LUT4 #(
    .INIT(16'hE2FF)) 
    \wrdq_div1_4to1_wrcal_first.phy_wrdata[184]_i_1 
       (.I0(p_1_in382_in),
        .I1(p_0_in222_in),
        .I2(p_2_in384_in),
        .I3(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0 ),
        .O(\dout_o_reg[13]_3 ));
  (* SOFT_HLUTNM = "soft_lutpair570" *) 
  LUT5 #(
    .INIT(32'hE2FFFFFF)) 
    \wrdq_div1_4to1_wrcal_first.phy_wrdata[186]_i_1 
       (.I0(p_1_in382_in),
        .I1(p_0_in230_in),
        .I2(p_2_in384_in),
        .I3(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0 ),
        .I4(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511] ),
        .O(\dout_o_reg[13]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair589" *) 
  LUT4 #(
    .INIT(16'hA808)) 
    \wrdq_div1_4to1_wrcal_first.phy_wrdata[187]_i_1 
       (.I0(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0 ),
        .I1(p_1_in382_in),
        .I2(p_0_in234_in),
        .I3(p_2_in384_in),
        .O(rdlvl_stg1_done_int_reg_6));
  (* SOFT_HLUTNM = "soft_lutpair575" *) 
  LUT4 #(
    .INIT(16'hE2FF)) 
    \wrdq_div1_4to1_wrcal_first.phy_wrdata[188]_i_1 
       (.I0(p_1_in382_in),
        .I1(p_0_in238_in),
        .I2(p_2_in384_in),
        .I3(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0 ),
        .O(\dout_o_reg[13]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair568" *) 
  LUT5 #(
    .INIT(32'hE2FFFFFF)) 
    \wrdq_div1_4to1_wrcal_first.phy_wrdata[190]_i_2 
       (.I0(p_1_in382_in),
        .I1(p_0_in246_in),
        .I2(p_2_in384_in),
        .I3(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0 ),
        .I4(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511] ),
        .O(\dout_o_reg[13]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair589" *) 
  LUT4 #(
    .INIT(16'hA808)) 
    \wrdq_div1_4to1_wrcal_first.phy_wrdata[191]_i_1 
       (.I0(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0 ),
        .I1(p_1_in382_in),
        .I2(p_0_in250_in),
        .I3(p_2_in384_in),
        .O(rdlvl_stg1_done_int_reg_5));
  (* SOFT_HLUTNM = "soft_lutpair574" *) 
  LUT5 #(
    .INIT(32'hE2000000)) 
    \wrdq_div1_4to1_wrcal_first.phy_wrdata[248]_i_1 
       (.I0(p_1_in512_in),
        .I1(p_0_in222_in),
        .I2(p_2_in514_in),
        .I3(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0 ),
        .I4(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511] ),
        .O(\dout_o_reg[12]_5 ));
  (* SOFT_HLUTNM = "soft_lutpair577" *) 
  LUT4 #(
    .INIT(16'hE2FF)) 
    \wrdq_div1_4to1_wrcal_first.phy_wrdata[249]_i_1 
       (.I0(p_1_in512_in),
        .I1(p_0_in226_in),
        .I2(p_2_in514_in),
        .I3(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0 ),
        .O(\dout_o_reg[12]_3 ));
  (* SOFT_HLUTNM = "soft_lutpair582" *) 
  LUT4 #(
    .INIT(16'hE2FF)) 
    \wrdq_div1_4to1_wrcal_first.phy_wrdata[251]_i_1 
       (.I0(p_1_in512_in),
        .I1(p_0_in234_in),
        .I2(p_2_in514_in),
        .I3(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0 ),
        .O(\dout_o_reg[12]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair562" *) 
  LUT5 #(
    .INIT(32'hE2000000)) 
    \wrdq_div1_4to1_wrcal_first.phy_wrdata[252]_i_1 
       (.I0(p_1_in512_in),
        .I1(p_0_in238_in),
        .I2(p_2_in514_in),
        .I3(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0 ),
        .I4(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511] ),
        .O(\dout_o_reg[12]_4 ));
  (* SOFT_HLUTNM = "soft_lutpair579" *) 
  LUT4 #(
    .INIT(16'hE2FF)) 
    \wrdq_div1_4to1_wrcal_first.phy_wrdata[253]_i_1 
       (.I0(p_1_in512_in),
        .I1(p_0_in242_in),
        .I2(p_2_in514_in),
        .I3(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0 ),
        .O(\dout_o_reg[12]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair586" *) 
  LUT4 #(
    .INIT(16'hE2FF)) 
    \wrdq_div1_4to1_wrcal_first.phy_wrdata[255]_i_1 
       (.I0(p_1_in512_in),
        .I1(p_0_in250_in),
        .I2(p_2_in514_in),
        .I3(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0 ),
        .O(\dout_o_reg[12]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair563" *) 
  LUT5 #(
    .INIT(32'hE2000000)) 
    \wrdq_div1_4to1_wrcal_first.phy_wrdata[312]_i_1 
       (.I0(p_1_in642_in),
        .I1(p_0_in222_in),
        .I2(p_2_in644_in),
        .I3(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0 ),
        .I4(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511] ),
        .O(\dout_o_reg[11]_3 ));
  (* SOFT_HLUTNM = "soft_lutpair587" *) 
  LUT4 #(
    .INIT(16'hE2FF)) 
    \wrdq_div1_4to1_wrcal_first.phy_wrdata[315]_i_1 
       (.I0(p_1_in642_in),
        .I1(p_0_in234_in),
        .I2(p_2_in644_in),
        .I3(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0 ),
        .O(\dout_o_reg[11]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair564" *) 
  LUT5 #(
    .INIT(32'hE2000000)) 
    \wrdq_div1_4to1_wrcal_first.phy_wrdata[316]_i_1 
       (.I0(p_1_in642_in),
        .I1(p_0_in238_in),
        .I2(p_2_in644_in),
        .I3(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0 ),
        .I4(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511] ),
        .O(\dout_o_reg[11]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair588" *) 
  LUT4 #(
    .INIT(16'hE2FF)) 
    \wrdq_div1_4to1_wrcal_first.phy_wrdata[319]_i_1 
       (.I0(p_1_in642_in),
        .I1(p_0_in250_in),
        .I2(p_2_in644_in),
        .I3(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0 ),
        .O(\dout_o_reg[11]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair584" *) 
  LUT4 #(
    .INIT(16'hE2FF)) 
    \wrdq_div1_4to1_wrcal_first.phy_wrdata[376]_i_1 
       (.I0(p_1_in772_in),
        .I1(p_0_in222_in),
        .I2(p_2_in774_in),
        .I3(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0 ),
        .O(\dout_o_reg[10]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair585" *) 
  LUT4 #(
    .INIT(16'hA808)) 
    \wrdq_div1_4to1_wrcal_first.phy_wrdata[377]_i_1 
       (.I0(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0 ),
        .I1(p_1_in772_in),
        .I2(p_0_in226_in),
        .I3(p_2_in774_in),
        .O(rdlvl_stg1_done_int_reg_4));
  (* SOFT_HLUTNM = "soft_lutpair573" *) 
  LUT5 #(
    .INIT(32'hE2000000)) 
    \wrdq_div1_4to1_wrcal_first.phy_wrdata[378]_i_1 
       (.I0(p_1_in772_in),
        .I1(p_0_in230_in),
        .I2(p_2_in774_in),
        .I3(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0 ),
        .I4(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511] ),
        .O(\dout_o_reg[10]_3 ));
  (* SOFT_HLUTNM = "soft_lutpair583" *) 
  LUT4 #(
    .INIT(16'hE2FF)) 
    \wrdq_div1_4to1_wrcal_first.phy_wrdata[380]_i_1 
       (.I0(p_1_in772_in),
        .I1(p_0_in238_in),
        .I2(p_2_in774_in),
        .I3(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0 ),
        .O(\dout_o_reg[10]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair584" *) 
  LUT4 #(
    .INIT(16'hA808)) 
    \wrdq_div1_4to1_wrcal_first.phy_wrdata[381]_i_1 
       (.I0(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0 ),
        .I1(p_1_in772_in),
        .I2(p_0_in242_in),
        .I3(p_2_in774_in),
        .O(rdlvl_stg1_done_int_reg_3));
  (* SOFT_HLUTNM = "soft_lutpair566" *) 
  LUT5 #(
    .INIT(32'hE2000000)) 
    \wrdq_div1_4to1_wrcal_first.phy_wrdata[382]_i_1 
       (.I0(p_1_in772_in),
        .I1(p_0_in246_in),
        .I2(p_2_in774_in),
        .I3(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0 ),
        .I4(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511] ),
        .O(\dout_o_reg[10]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair581" *) 
  LUT4 #(
    .INIT(16'hA808)) 
    \wrdq_div1_4to1_wrcal_first.phy_wrdata[440]_i_1 
       (.I0(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0 ),
        .I1(p_1_in902_in),
        .I2(p_0_in222_in),
        .I3(p_2_in904_in),
        .O(rdlvl_stg1_done_int_reg_2));
  (* SOFT_HLUTNM = "soft_lutpair580" *) 
  LUT4 #(
    .INIT(16'hE2FF)) 
    \wrdq_div1_4to1_wrcal_first.phy_wrdata[441]_i_1 
       (.I0(p_1_in902_in),
        .I1(p_0_in226_in),
        .I2(p_2_in904_in),
        .I3(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0 ),
        .O(\dout_o_reg[9]_1 ));
  (* SOFT_HLUTNM = "soft_lutpair572" *) 
  LUT5 #(
    .INIT(32'hE2000000)) 
    \wrdq_div1_4to1_wrcal_first.phy_wrdata[442]_i_1 
       (.I0(p_1_in902_in),
        .I1(p_0_in230_in),
        .I2(p_2_in904_in),
        .I3(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0 ),
        .I4(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511] ),
        .O(\dout_o_reg[9]_3 ));
  (* SOFT_HLUTNM = "soft_lutpair581" *) 
  LUT4 #(
    .INIT(16'hA808)) 
    \wrdq_div1_4to1_wrcal_first.phy_wrdata[443]_i_1 
       (.I0(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0 ),
        .I1(p_1_in902_in),
        .I2(p_0_in234_in),
        .I3(p_2_in904_in),
        .O(rdlvl_stg1_done_int_reg_1));
  (* SOFT_HLUTNM = "soft_lutpair580" *) 
  LUT4 #(
    .INIT(16'hA808)) 
    \wrdq_div1_4to1_wrcal_first.phy_wrdata[444]_i_1 
       (.I0(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0 ),
        .I1(p_1_in902_in),
        .I2(p_0_in238_in),
        .I3(p_2_in904_in),
        .O(rdlvl_stg1_done_int_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair578" *) 
  LUT4 #(
    .INIT(16'hE2FF)) 
    \wrdq_div1_4to1_wrcal_first.phy_wrdata[445]_i_2 
       (.I0(p_1_in902_in),
        .I1(p_0_in242_in),
        .I2(p_2_in904_in),
        .I3(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0 ),
        .O(\dout_o_reg[9]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair571" *) 
  LUT5 #(
    .INIT(32'hE2000000)) 
    \wrdq_div1_4to1_wrcal_first.phy_wrdata[446]_i_1 
       (.I0(p_1_in902_in),
        .I1(p_0_in246_in),
        .I2(p_2_in904_in),
        .I3(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0 ),
        .I4(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511] ),
        .O(\dout_o_reg[9]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair578" *) 
  LUT4 #(
    .INIT(16'hA808)) 
    \wrdq_div1_4to1_wrcal_first.phy_wrdata[447]_i_1 
       (.I0(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0 ),
        .I1(p_1_in902_in),
        .I2(p_0_in250_in),
        .I3(p_2_in904_in),
        .O(rdlvl_stg1_done_int_reg));
  (* SOFT_HLUTNM = "soft_lutpair559" *) 
  LUT5 #(
    .INIT(32'hE2000000)) 
    \wrdq_div1_4to1_wrcal_first.phy_wrdata[505]_i_1 
       (.I0(p_1_in1032_in),
        .I1(p_0_in226_in),
        .I2(\dout_o_reg_n_0_[0] ),
        .I3(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0 ),
        .I4(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511] ),
        .O(\dout_o_reg[8]_3 ));
  LUT6 #(
    .INIT(64'hEE2EEEEEEE2E2E2E)) 
    \wrdq_div1_4to1_wrcal_first.phy_wrdata[506]_i_1 
       (.I0(first_wrcal_pat_r),
        .I1(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511] ),
        .I2(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0 ),
        .I3(\dout_o_reg_n_0_[0] ),
        .I4(p_0_in230_in),
        .I5(p_1_in1032_in),
        .O(first_wrcal_pat_r_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair561" *) 
  LUT5 #(
    .INIT(32'hE2000000)) 
    \wrdq_div1_4to1_wrcal_first.phy_wrdata[507]_i_1 
       (.I0(p_1_in1032_in),
        .I1(p_0_in234_in),
        .I2(\dout_o_reg_n_0_[0] ),
        .I3(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0 ),
        .I4(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511] ),
        .O(\dout_o_reg[8]_2 ));
  (* SOFT_HLUTNM = "soft_lutpair560" *) 
  LUT5 #(
    .INIT(32'hE2000000)) 
    \wrdq_div1_4to1_wrcal_first.phy_wrdata[509]_i_1 
       (.I0(p_1_in1032_in),
        .I1(p_0_in242_in),
        .I2(\dout_o_reg_n_0_[0] ),
        .I3(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0 ),
        .I4(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511] ),
        .O(\dout_o_reg[8]_1 ));
  LUT6 #(
    .INIT(64'hEE2EEEEEEE2E2E2E)) 
    \wrdq_div1_4to1_wrcal_first.phy_wrdata[510]_i_2 
       (.I0(first_wrcal_pat_r),
        .I1(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511] ),
        .I2(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0 ),
        .I3(\dout_o_reg_n_0_[0] ),
        .I4(p_0_in246_in),
        .I5(p_1_in1032_in),
        .O(first_wrcal_pat_r_reg));
  (* SOFT_HLUTNM = "soft_lutpair565" *) 
  LUT5 #(
    .INIT(32'hE2000000)) 
    \wrdq_div1_4to1_wrcal_first.phy_wrdata[511]_i_2 
       (.I0(p_1_in1032_in),
        .I1(p_0_in250_in),
        .I2(\dout_o_reg_n_0_[0] ),
        .I3(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0 ),
        .I4(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511] ),
        .O(\dout_o_reg[8]_0 ));
  LUT6 #(
    .INIT(64'hF5FFF55577777777)) 
    \wrdq_div1_4to1_wrcal_first.phy_wrdata[57]_i_1 
       (.I0(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511] ),
        .I1(first_rdlvl_pat_r),
        .I2(p_2_in),
        .I3(p_0_in226_in),
        .I4(p_1_in),
        .I5(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0 ),
        .O(wrcal_done_reg_1));
  (* SOFT_HLUTNM = "soft_lutpair557" *) 
  LUT5 #(
    .INIT(32'hE2000000)) 
    \wrdq_div1_4to1_wrcal_first.phy_wrdata[58]_i_1 
       (.I0(p_1_in),
        .I1(p_0_in230_in),
        .I2(p_2_in),
        .I3(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0 ),
        .I4(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511] ),
        .O(\dout_o_reg[15]_1 ));
  LUT6 #(
    .INIT(64'hF5FFF55577777777)) 
    \wrdq_div1_4to1_wrcal_first.phy_wrdata[61]_i_1 
       (.I0(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511] ),
        .I1(first_rdlvl_pat_r),
        .I2(p_2_in),
        .I3(p_0_in242_in),
        .I4(p_1_in),
        .I5(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0 ),
        .O(wrcal_done_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair569" *) 
  LUT5 #(
    .INIT(32'hE2000000)) 
    \wrdq_div1_4to1_wrcal_first.phy_wrdata[62]_i_1 
       (.I0(p_1_in),
        .I1(p_0_in246_in),
        .I2(p_2_in),
        .I3(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511]_0 ),
        .I4(\wrdq_div1_4to1_wrcal_first.phy_wrdata_reg[511] ),
        .O(\dout_o_reg[15]_0 ));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_infrastructure" *) 
module mig_mig_7series_v4_2_infrastructure
   (\gen_mmcm.mmcm_i_i_1_0 ,
    \gen_mmcm.mmcm_i_0 ,
    mmcm_ps_clk,
    freq_refclk,
    mem_refclk,
    sync_pulse,
    rst_sync_r1,
    rstdiv0_sync_r1_reg_rep_0,
    SR,
    rstdiv0_sync_r1_reg_rep__2_0,
    rstdiv0_sync_r1_reg_rep__5_0,
    rstdiv0_sync_r1_reg_rep__7_0,
    rstdiv0_sync_r1_reg_rep__8_0,
    rstdiv0_sync_r1_reg_rep__9_0,
    rstdiv0_sync_r1_reg_rep__10_0,
    rstdiv0_sync_r1_reg_rep__12_0,
    rstdiv0_sync_r1_reg_rep__13_0,
    rstdiv0_sync_r1_reg_rep__14_0,
    rstdiv0_sync_r1_reg_rep__15_0,
    rstdiv0_sync_r1_reg_rep__16_0,
    rstdiv0_sync_r1_reg_rep__17_0,
    rstdiv0_sync_r1_reg_rep__18_0,
    rstdiv0_sync_r1_reg_rep__19_0,
    rstdiv0_sync_r1_reg_rep__20_0,
    rstdiv0_sync_r1_reg_rep__21_0,
    rstdiv0_sync_r1_reg_rep__22_0,
    rstdiv0_sync_r1_reg_rep__23_0,
    rstdiv0_sync_r1_reg_rep__24_0,
    rstdiv0_sync_r1_reg_rep__25_0,
    RST0,
    pll_locked,
    bm_end_r1_reg,
    bm_end_r1_reg_0,
    bm_end_r1_reg_1,
    \generate_maint_cmds.insert_maint_r_lcl_reg ,
    SS,
    po_cnt_dec_reg,
    fine_adjust_reg,
    new_cnt_cpt_r_reg,
    rdlvl_stg1_start_reg,
    samp_edge_cnt0_en_r_reg,
    pi_cnt_dec_reg,
    new_cnt_dqs_r_reg,
    rstdiv0_sync_r1_reg_rep__23_1,
    prbs_rdlvl_done_pulse_reg,
    out,
    AS,
    rst_tmp,
    bm_end_r1,
    bm_end_r1_0,
    bm_end_r1_1,
    insert_maint_r,
    po_cnt_dec,
    po_cnt_dec_2,
    \pi_rst_stg1_cal_r_reg[1] ,
    \tap_cnt_cpt_r_reg[5] ,
    \cnt_shift_r_reg[0] ,
    samp_edge_cnt0_en_r,
    pi_cnt_dec,
    \cmp_err_4to1.compare_err_f3_reg ,
    \en_cnt_div4.enable_wrlvl_cnt_reg[4] ,
    prbs_rdlvl_done_pulse);
  output \gen_mmcm.mmcm_i_i_1_0 ;
  output \gen_mmcm.mmcm_i_0 ;
  output mmcm_ps_clk;
  output freq_refclk;
  output mem_refclk;
  output sync_pulse;
  output rst_sync_r1;
  output rstdiv0_sync_r1_reg_rep_0;
  output [1:0]SR;
  output [1:0]rstdiv0_sync_r1_reg_rep__2_0;
  output [1:0]rstdiv0_sync_r1_reg_rep__5_0;
  output [1:0]rstdiv0_sync_r1_reg_rep__7_0;
  output [0:0]rstdiv0_sync_r1_reg_rep__8_0;
  output rstdiv0_sync_r1_reg_rep__9_0;
  output [1:0]rstdiv0_sync_r1_reg_rep__10_0;
  output rstdiv0_sync_r1_reg_rep__12_0;
  output rstdiv0_sync_r1_reg_rep__13_0;
  output [0:0]rstdiv0_sync_r1_reg_rep__14_0;
  output rstdiv0_sync_r1_reg_rep__15_0;
  output rstdiv0_sync_r1_reg_rep__16_0;
  output rstdiv0_sync_r1_reg_rep__17_0;
  output rstdiv0_sync_r1_reg_rep__18_0;
  output rstdiv0_sync_r1_reg_rep__19_0;
  output [0:0]rstdiv0_sync_r1_reg_rep__20_0;
  output rstdiv0_sync_r1_reg_rep__21_0;
  output rstdiv0_sync_r1_reg_rep__22_0;
  output rstdiv0_sync_r1_reg_rep__23_0;
  output rstdiv0_sync_r1_reg_rep__24_0;
  output rstdiv0_sync_r1_reg_rep__25_0;
  output RST0;
  output pll_locked;
  output bm_end_r1_reg;
  output bm_end_r1_reg_0;
  output bm_end_r1_reg_1;
  output \generate_maint_cmds.insert_maint_r_lcl_reg ;
  output [0:0]SS;
  output [0:0]po_cnt_dec_reg;
  output fine_adjust_reg;
  output [0:0]new_cnt_cpt_r_reg;
  output [0:0]rdlvl_stg1_start_reg;
  output samp_edge_cnt0_en_r_reg;
  output [0:0]pi_cnt_dec_reg;
  output new_cnt_dqs_r_reg;
  output rstdiv0_sync_r1_reg_rep__23_1;
  output prbs_rdlvl_done_pulse_reg;
  input out;
  input [0:0]AS;
  input rst_tmp;
  input bm_end_r1;
  input bm_end_r1_0;
  input bm_end_r1_1;
  input insert_maint_r;
  input po_cnt_dec;
  input po_cnt_dec_2;
  input \pi_rst_stg1_cal_r_reg[1] ;
  input \tap_cnt_cpt_r_reg[5] ;
  input \cnt_shift_r_reg[0] ;
  input samp_edge_cnt0_en_r;
  input pi_cnt_dec;
  input \cmp_err_4to1.compare_err_f3_reg ;
  input \en_cnt_div4.enable_wrlvl_cnt_reg[4] ;
  input prbs_rdlvl_done_pulse;

  wire [0:0]AS;
  wire RST0;
  wire RST0_0;
  wire [1:0]SR;
  wire [0:0]SS;
  wire bm_end_r1;
  wire bm_end_r1_0;
  wire bm_end_r1_1;
  wire bm_end_r1_reg;
  wire bm_end_r1_reg_0;
  wire bm_end_r1_reg_1;
  wire clk_div2_bufg_in;
  wire clk_pll_i;
  wire \cmp_err_4to1.compare_err_f3_reg ;
  wire \cnt_shift_r_reg[0] ;
  wire \en_cnt_div4.enable_wrlvl_cnt_reg[4] ;
  wire fine_adjust_reg;
  wire freq_refclk;
  wire \gen_mmcm.mmcm_i_0 ;
  wire \gen_mmcm.mmcm_i_i_1_0 ;
  wire \gen_mmcm.mmcm_i_n_17 ;
  wire \gen_mmcm.u_bufg_clk_div2_n_0 ;
  wire \generate_maint_cmds.insert_maint_r_lcl_reg ;
  wire insert_maint_r;
  wire mem_refclk;
  wire mmcm_ps_clk;
  wire mmcm_ps_clk_bufg_in;
  wire [0:0]new_cnt_cpt_r_reg;
  wire new_cnt_dqs_r_reg;
  wire out;
  wire p_0_in;
  wire pi_cnt_dec;
  wire [0:0]pi_cnt_dec_reg;
  wire \pi_rst_stg1_cal_r_reg[1] ;
  wire pll_clk3;
  wire pll_clk3_out;
  wire pll_clkfbout;
  wire pll_locked;
  wire pll_locked_i;
  wire po_cnt_dec;
  wire po_cnt_dec_2;
  wire [0:0]po_cnt_dec_reg;
  wire prbs_rdlvl_done_pulse;
  wire prbs_rdlvl_done_pulse_reg;
  wire [0:0]rdlvl_stg1_start_reg;
  wire [11:0]rst_sync_r;
  wire rst_sync_r1;
  wire rst_tmp;
  wire [11:0]rstdiv0_sync_r;
  wire rstdiv0_sync_r1_reg_rep_0;
  wire rstdiv0_sync_r1_reg_rep__0_n_0;
  wire [1:0]rstdiv0_sync_r1_reg_rep__10_0;
  wire rstdiv0_sync_r1_reg_rep__10_n_0;
  wire rstdiv0_sync_r1_reg_rep__11_n_0;
  wire rstdiv0_sync_r1_reg_rep__12_0;
  wire rstdiv0_sync_r1_reg_rep__12_n_0;
  wire rstdiv0_sync_r1_reg_rep__13_0;
  wire rstdiv0_sync_r1_reg_rep__13_n_0;
  wire [0:0]rstdiv0_sync_r1_reg_rep__14_0;
  wire rstdiv0_sync_r1_reg_rep__14_n_0;
  wire rstdiv0_sync_r1_reg_rep__15_0;
  wire rstdiv0_sync_r1_reg_rep__15_n_0;
  wire rstdiv0_sync_r1_reg_rep__16_0;
  wire rstdiv0_sync_r1_reg_rep__16_n_0;
  wire rstdiv0_sync_r1_reg_rep__17_0;
  wire rstdiv0_sync_r1_reg_rep__17_n_0;
  wire rstdiv0_sync_r1_reg_rep__18_0;
  wire rstdiv0_sync_r1_reg_rep__18_n_0;
  wire rstdiv0_sync_r1_reg_rep__19_0;
  wire rstdiv0_sync_r1_reg_rep__19_n_0;
  wire rstdiv0_sync_r1_reg_rep__1_n_0;
  wire [0:0]rstdiv0_sync_r1_reg_rep__20_0;
  wire rstdiv0_sync_r1_reg_rep__20_n_0;
  wire rstdiv0_sync_r1_reg_rep__21_0;
  wire rstdiv0_sync_r1_reg_rep__21_n_0;
  wire rstdiv0_sync_r1_reg_rep__22_0;
  wire rstdiv0_sync_r1_reg_rep__22_n_0;
  wire rstdiv0_sync_r1_reg_rep__23_0;
  wire rstdiv0_sync_r1_reg_rep__23_1;
  wire rstdiv0_sync_r1_reg_rep__23_n_0;
  wire rstdiv0_sync_r1_reg_rep__24_0;
  wire rstdiv0_sync_r1_reg_rep__24_n_0;
  wire rstdiv0_sync_r1_reg_rep__25_0;
  wire rstdiv0_sync_r1_reg_rep__25_n_0;
  wire [1:0]rstdiv0_sync_r1_reg_rep__2_0;
  wire rstdiv0_sync_r1_reg_rep__2_n_0;
  wire rstdiv0_sync_r1_reg_rep__3_n_0;
  wire rstdiv0_sync_r1_reg_rep__4_n_0;
  wire [1:0]rstdiv0_sync_r1_reg_rep__5_0;
  wire rstdiv0_sync_r1_reg_rep__5_n_0;
  wire rstdiv0_sync_r1_reg_rep__6_n_0;
  wire [1:0]rstdiv0_sync_r1_reg_rep__7_0;
  wire rstdiv0_sync_r1_reg_rep__7_n_0;
  wire [0:0]rstdiv0_sync_r1_reg_rep__8_0;
  wire rstdiv0_sync_r1_reg_rep__8_n_0;
  wire rstdiv0_sync_r1_reg_rep__9_0;
  wire rstdiv0_sync_r1_reg_rep__9_n_0;
  wire rstdiv0_sync_r1_reg_rep_n_0;
  (* MAX_FANOUT = "10" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire rstdiv2_sync_r1;
  wire \rstdiv2_sync_r_reg_n_0_[0] ;
  wire \rstdiv2_sync_r_reg_n_0_[10] ;
  wire \rstdiv2_sync_r_reg_n_0_[1] ;
  wire \rstdiv2_sync_r_reg_n_0_[2] ;
  wire \rstdiv2_sync_r_reg_n_0_[3] ;
  wire \rstdiv2_sync_r_reg_n_0_[4] ;
  wire \rstdiv2_sync_r_reg_n_0_[5] ;
  wire \rstdiv2_sync_r_reg_n_0_[6] ;
  wire \rstdiv2_sync_r_reg_n_0_[7] ;
  wire \rstdiv2_sync_r_reg_n_0_[8] ;
  wire \rstdiv2_sync_r_reg_n_0_[9] ;
  wire samp_edge_cnt0_en_r;
  wire samp_edge_cnt0_en_r_reg;
  wire sync_pulse;
  wire \tap_cnt_cpt_r_reg[5] ;
  wire \NLW_gen_mmcm.mmcm_i_CLKFBOUTB_UNCONNECTED ;
  wire \NLW_gen_mmcm.mmcm_i_CLKFBSTOPPED_UNCONNECTED ;
  wire \NLW_gen_mmcm.mmcm_i_CLKINSTOPPED_UNCONNECTED ;
  wire \NLW_gen_mmcm.mmcm_i_CLKOUT0B_UNCONNECTED ;
  wire \NLW_gen_mmcm.mmcm_i_CLKOUT1B_UNCONNECTED ;
  wire \NLW_gen_mmcm.mmcm_i_CLKOUT2_UNCONNECTED ;
  wire \NLW_gen_mmcm.mmcm_i_CLKOUT2B_UNCONNECTED ;
  wire \NLW_gen_mmcm.mmcm_i_CLKOUT3_UNCONNECTED ;
  wire \NLW_gen_mmcm.mmcm_i_CLKOUT3B_UNCONNECTED ;
  wire \NLW_gen_mmcm.mmcm_i_CLKOUT4_UNCONNECTED ;
  wire \NLW_gen_mmcm.mmcm_i_CLKOUT5_UNCONNECTED ;
  wire \NLW_gen_mmcm.mmcm_i_CLKOUT6_UNCONNECTED ;
  wire \NLW_gen_mmcm.mmcm_i_DRDY_UNCONNECTED ;
  wire [15:0]\NLW_gen_mmcm.mmcm_i_DO_UNCONNECTED ;
  wire NLW_plle2_i_CLKOUT4_UNCONNECTED;
  wire NLW_plle2_i_CLKOUT5_UNCONNECTED;
  wire NLW_plle2_i_DRDY_UNCONNECTED;
  wire [15:0]NLW_plle2_i_DO_UNCONNECTED;

  (* SOFT_HLUTNM = "soft_lutpair10" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \cmp_err_4to1.compare_err_i_3 
       (.I0(rstdiv0_sync_r1_reg_rep__22_0),
        .I1(\cmp_err_4to1.compare_err_f3_reg ),
        .O(new_cnt_dqs_r_reg));
  (* SOFT_HLUTNM = "soft_lutpair11" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \cnt_shift_r[3]_i_1 
       (.I0(rstdiv0_sync_r1_reg_rep__21_0),
        .I1(\cnt_shift_r_reg[0] ),
        .O(rdlvl_stg1_start_reg));
  (* SOFT_HLUTNM = "soft_lutpair9" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \complex_num_writes[2]_i_6 
       (.I0(rstdiv0_sync_r1_reg_rep__23_0),
        .I1(prbs_rdlvl_done_pulse),
        .O(prbs_rdlvl_done_pulse_reg));
  (* SOFT_HLUTNM = "soft_lutpair9" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \en_cnt_div4.enable_wrlvl_cnt[4]_i_2 
       (.I0(rstdiv0_sync_r1_reg_rep__23_0),
        .I1(\en_cnt_div4.enable_wrlvl_cnt_reg[4] ),
        .O(rstdiv0_sync_r1_reg_rep__23_1));
  (* BOX_TYPE = "PRIMITIVE" *) 
  MMCME2_ADV #(
    .BANDWIDTH("HIGH"),
    .CLKFBOUT_MULT_F(8.000000),
    .CLKFBOUT_PHASE(0.000000),
    .CLKFBOUT_USE_FINE_PS("FALSE"),
    .CLKIN1_PERIOD(10.000000),
    .CLKIN2_PERIOD(0.000000),
    .CLKOUT0_DIVIDE_F(16.000000),
    .CLKOUT0_DUTY_CYCLE(0.500000),
    .CLKOUT0_PHASE(0.000000),
    .CLKOUT0_USE_FINE_PS("TRUE"),
    .CLKOUT1_DIVIDE(4),
    .CLKOUT1_DUTY_CYCLE(0.500000),
    .CLKOUT1_PHASE(0.000000),
    .CLKOUT1_USE_FINE_PS("FALSE"),
    .CLKOUT2_DIVIDE(1),
    .CLKOUT2_DUTY_CYCLE(0.500000),
    .CLKOUT2_PHASE(0.000000),
    .CLKOUT2_USE_FINE_PS("FALSE"),
    .CLKOUT3_DIVIDE(1),
    .CLKOUT3_DUTY_CYCLE(0.500000),
    .CLKOUT3_PHASE(0.000000),
    .CLKOUT3_USE_FINE_PS("FALSE"),
    .CLKOUT4_CASCADE("FALSE"),
    .CLKOUT4_DIVIDE(1),
    .CLKOUT4_DUTY_CYCLE(0.500000),
    .CLKOUT4_PHASE(0.000000),
    .CLKOUT4_USE_FINE_PS("FALSE"),
    .CLKOUT5_DIVIDE(1),
    .CLKOUT5_DUTY_CYCLE(0.500000),
    .CLKOUT5_PHASE(0.000000),
    .CLKOUT5_USE_FINE_PS("FALSE"),
    .CLKOUT6_DIVIDE(1),
    .CLKOUT6_DUTY_CYCLE(0.500000),
    .CLKOUT6_PHASE(0.000000),
    .CLKOUT6_USE_FINE_PS("FALSE"),
    .COMPENSATION("BUF_IN"),
    .DIVCLK_DIVIDE(1),
    .IS_CLKINSEL_INVERTED(1'b0),
    .IS_PSEN_INVERTED(1'b0),
    .IS_PSINCDEC_INVERTED(1'b0),
    .IS_PWRDWN_INVERTED(1'b0),
    .IS_RST_INVERTED(1'b0),
    .REF_JITTER1(0.000000),
    .REF_JITTER2(0.010000),
    .SS_EN("FALSE"),
    .SS_MODE("CENTER_HIGH"),
    .SS_MOD_PERIOD(10000),
    .STARTUP_WAIT("FALSE")) 
    \gen_mmcm.mmcm_i 
       (.CLKFBIN(\gen_mmcm.mmcm_i_0 ),
        .CLKFBOUT(clk_pll_i),
        .CLKFBOUTB(\NLW_gen_mmcm.mmcm_i_CLKFBOUTB_UNCONNECTED ),
        .CLKFBSTOPPED(\NLW_gen_mmcm.mmcm_i_CLKFBSTOPPED_UNCONNECTED ),
        .CLKIN1(pll_clk3),
        .CLKIN2(1'b0),
        .CLKINSEL(1'b1),
        .CLKINSTOPPED(\NLW_gen_mmcm.mmcm_i_CLKINSTOPPED_UNCONNECTED ),
        .CLKOUT0(mmcm_ps_clk_bufg_in),
        .CLKOUT0B(\NLW_gen_mmcm.mmcm_i_CLKOUT0B_UNCONNECTED ),
        .CLKOUT1(clk_div2_bufg_in),
        .CLKOUT1B(\NLW_gen_mmcm.mmcm_i_CLKOUT1B_UNCONNECTED ),
        .CLKOUT2(\NLW_gen_mmcm.mmcm_i_CLKOUT2_UNCONNECTED ),
        .CLKOUT2B(\NLW_gen_mmcm.mmcm_i_CLKOUT2B_UNCONNECTED ),
        .CLKOUT3(\NLW_gen_mmcm.mmcm_i_CLKOUT3_UNCONNECTED ),
        .CLKOUT3B(\NLW_gen_mmcm.mmcm_i_CLKOUT3B_UNCONNECTED ),
        .CLKOUT4(\NLW_gen_mmcm.mmcm_i_CLKOUT4_UNCONNECTED ),
        .CLKOUT5(\NLW_gen_mmcm.mmcm_i_CLKOUT5_UNCONNECTED ),
        .CLKOUT6(\NLW_gen_mmcm.mmcm_i_CLKOUT6_UNCONNECTED ),
        .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .DCLK(1'b0),
        .DEN(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .DO(\NLW_gen_mmcm.mmcm_i_DO_UNCONNECTED [15:0]),
        .DRDY(\NLW_gen_mmcm.mmcm_i_DRDY_UNCONNECTED ),
        .DWE(1'b0),
        .LOCKED(\gen_mmcm.mmcm_i_i_1_0 ),
        .PSCLK(\gen_mmcm.mmcm_i_0 ),
        .PSDONE(\gen_mmcm.mmcm_i_n_17 ),
        .PSEN(1'b0),
        .PSINCDEC(1'b0),
        .PWRDWN(1'b0),
        .RST(RST0_0));
  LUT1 #(
    .INIT(2'h1)) 
    \gen_mmcm.mmcm_i_i_1 
       (.I0(pll_locked_i),
        .O(RST0_0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  BUFG \gen_mmcm.u_bufg_clk_div2 
       (.I(clk_div2_bufg_in),
        .O(\gen_mmcm.u_bufg_clk_div2_n_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  BUFG \gen_mmcm.u_bufg_mmcm_ps_clk 
       (.I(mmcm_ps_clk_bufg_in),
        .O(mmcm_ps_clk));
  (* SOFT_HLUTNM = "soft_lutpair12" *) 
  LUT2 #(
    .INIT(4'h7)) 
    phaser_ref_i_i_1
       (.I0(pll_locked_i),
        .I1(\gen_mmcm.mmcm_i_i_1_0 ),
        .O(RST0));
  (* SOFT_HLUTNM = "soft_lutpair12" *) 
  LUT2 #(
    .INIT(4'h8)) 
    phy_control_i_i_1
       (.I0(pll_locked_i),
        .I1(\gen_mmcm.mmcm_i_i_1_0 ),
        .O(pll_locked));
  (* SOFT_HLUTNM = "soft_lutpair13" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \pi_rst_stg1_cal_r[1]_i_2 
       (.I0(rstdiv0_sync_r1_reg_rep__21_0),
        .I1(\pi_rst_stg1_cal_r_reg[1] ),
        .O(fine_adjust_reg));
  (* BOX_TYPE = "PRIMITIVE" *) 
  PLLE2_ADV #(
    .BANDWIDTH("OPTIMIZED"),
    .CLKFBOUT_MULT(4),
    .CLKFBOUT_PHASE(0.000000),
    .CLKIN1_PERIOD(5.000000),
    .CLKIN2_PERIOD(0.000000),
    .CLKOUT0_DIVIDE(1),
    .CLKOUT0_DUTY_CYCLE(0.500000),
    .CLKOUT0_PHASE(0.000000),
    .CLKOUT1_DIVIDE(2),
    .CLKOUT1_DUTY_CYCLE(0.500000),
    .CLKOUT1_PHASE(0.000000),
    .CLKOUT2_DIVIDE(32),
    .CLKOUT2_DUTY_CYCLE(0.062500),
    .CLKOUT2_PHASE(9.843750),
    .CLKOUT3_DIVIDE(8),
    .CLKOUT3_DUTY_CYCLE(0.500000),
    .CLKOUT3_PHASE(0.000000),
    .CLKOUT4_DIVIDE(4),
    .CLKOUT4_DUTY_CYCLE(0.500000),
    .CLKOUT4_PHASE(168.750000),
    .CLKOUT5_DIVIDE(1),
    .CLKOUT5_DUTY_CYCLE(0.500000),
    .CLKOUT5_PHASE(0.000000),
    .COMPENSATION("INTERNAL"),
    .DIVCLK_DIVIDE(1),
    .IS_CLKINSEL_INVERTED(1'b0),
    .IS_PWRDWN_INVERTED(1'b0),
    .IS_RST_INVERTED(1'b0),
    .REF_JITTER1(0.010000),
    .REF_JITTER2(0.010000),
    .STARTUP_WAIT("FALSE")) 
    plle2_i
       (.CLKFBIN(pll_clkfbout),
        .CLKFBOUT(pll_clkfbout),
        .CLKIN1(out),
        .CLKIN2(1'b0),
        .CLKINSEL(1'b1),
        .CLKOUT0(freq_refclk),
        .CLKOUT1(mem_refclk),
        .CLKOUT2(sync_pulse),
        .CLKOUT3(pll_clk3_out),
        .CLKOUT4(NLW_plle2_i_CLKOUT4_UNCONNECTED),
        .CLKOUT5(NLW_plle2_i_CLKOUT5_UNCONNECTED),
        .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .DCLK(1'b0),
        .DEN(1'b0),
        .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .DO(NLW_plle2_i_DO_UNCONNECTED[15:0]),
        .DRDY(NLW_plle2_i_DRDY_UNCONNECTED),
        .DWE(1'b0),
        .LOCKED(pll_locked_i),
        .PWRDWN(1'b0),
        .RST(AS));
  (* SOFT_HLUTNM = "soft_lutpair7" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \ras_timer_r[1]_i_4__0 
       (.I0(rstdiv0_sync_r1_reg_rep__25_0),
        .I1(bm_end_r1),
        .O(bm_end_r1_reg));
  (* SOFT_HLUTNM = "soft_lutpair7" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \ras_timer_r[1]_i_4__1 
       (.I0(rstdiv0_sync_r1_reg_rep__25_0),
        .I1(bm_end_r1_0),
        .O(bm_end_r1_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair8" *) 
  LUT2 #(
    .INIT(4'hE)) 
    ras_timer_zero_r_i_3
       (.I0(rstdiv0_sync_r1_reg_rep__25_0),
        .I1(bm_end_r1_1),
        .O(bm_end_r1_reg_1));
  (* SOFT_HLUTNM = "soft_lutpair8" *) 
  LUT2 #(
    .INIT(4'h1)) 
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[3]_i_3 
       (.I0(rstdiv0_sync_r1_reg_rep__25_0),
        .I1(insert_maint_r),
        .O(\generate_maint_cmds.insert_maint_r_lcl_reg ));
  FDPE rst_sync_r1_reg
       (.C(mmcm_ps_clk),
        .CE(1'b1),
        .D(rst_sync_r[11]),
        .PRE(rst_tmp),
        .Q(rst_sync_r1));
  FDPE \rst_sync_r_reg[0] 
       (.C(mmcm_ps_clk),
        .CE(1'b1),
        .D(1'b0),
        .PRE(rst_tmp),
        .Q(rst_sync_r[0]));
  FDPE \rst_sync_r_reg[10] 
       (.C(mmcm_ps_clk),
        .CE(1'b1),
        .D(rst_sync_r[9]),
        .PRE(rst_tmp),
        .Q(rst_sync_r[10]));
  FDPE \rst_sync_r_reg[11] 
       (.C(mmcm_ps_clk),
        .CE(1'b1),
        .D(rst_sync_r[10]),
        .PRE(rst_tmp),
        .Q(rst_sync_r[11]));
  FDPE \rst_sync_r_reg[1] 
       (.C(mmcm_ps_clk),
        .CE(1'b1),
        .D(rst_sync_r[0]),
        .PRE(rst_tmp),
        .Q(rst_sync_r[1]));
  FDPE \rst_sync_r_reg[2] 
       (.C(mmcm_ps_clk),
        .CE(1'b1),
        .D(rst_sync_r[1]),
        .PRE(rst_tmp),
        .Q(rst_sync_r[2]));
  FDPE \rst_sync_r_reg[3] 
       (.C(mmcm_ps_clk),
        .CE(1'b1),
        .D(rst_sync_r[2]),
        .PRE(rst_tmp),
        .Q(rst_sync_r[3]));
  FDPE \rst_sync_r_reg[4] 
       (.C(mmcm_ps_clk),
        .CE(1'b1),
        .D(rst_sync_r[3]),
        .PRE(rst_tmp),
        .Q(rst_sync_r[4]));
  FDPE \rst_sync_r_reg[5] 
       (.C(mmcm_ps_clk),
        .CE(1'b1),
        .D(rst_sync_r[4]),
        .PRE(rst_tmp),
        .Q(rst_sync_r[5]));
  FDPE \rst_sync_r_reg[6] 
       (.C(mmcm_ps_clk),
        .CE(1'b1),
        .D(rst_sync_r[5]),
        .PRE(rst_tmp),
        .Q(rst_sync_r[6]));
  FDPE \rst_sync_r_reg[7] 
       (.C(mmcm_ps_clk),
        .CE(1'b1),
        .D(rst_sync_r[6]),
        .PRE(rst_tmp),
        .Q(rst_sync_r[7]));
  FDPE \rst_sync_r_reg[8] 
       (.C(mmcm_ps_clk),
        .CE(1'b1),
        .D(rst_sync_r[7]),
        .PRE(rst_tmp),
        .Q(rst_sync_r[8]));
  FDPE \rst_sync_r_reg[9] 
       (.C(mmcm_ps_clk),
        .CE(1'b1),
        .D(rst_sync_r[8]),
        .PRE(rst_tmp),
        .Q(rst_sync_r[9]));
  LUT1 #(
    .INIT(2'h2)) 
    rstdiv0_sync_r1_inst
       (.I0(rstdiv0_sync_r1_reg_rep_n_0),
        .O(rstdiv0_sync_r1_reg_rep_0));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  LUT1 #(
    .INIT(2'h2)) 
    rstdiv0_sync_r1_inst_rep
       (.I0(rstdiv0_sync_r1_reg_rep__0_n_0),
        .O(SR[0]));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  LUT1 #(
    .INIT(2'h2)) 
    rstdiv0_sync_r1_inst_rep__0
       (.I0(rstdiv0_sync_r1_reg_rep__1_n_0),
        .O(SR[1]));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  LUT1 #(
    .INIT(2'h2)) 
    rstdiv0_sync_r1_inst_rep__1
       (.I0(rstdiv0_sync_r1_reg_rep__2_n_0),
        .O(rstdiv0_sync_r1_reg_rep__2_0[1]));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  LUT1 #(
    .INIT(2'h2)) 
    rstdiv0_sync_r1_inst_rep__10
       (.I0(rstdiv0_sync_r1_reg_rep__11_n_0),
        .O(rstdiv0_sync_r1_reg_rep__10_0[0]));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  LUT1 #(
    .INIT(2'h2)) 
    rstdiv0_sync_r1_inst_rep__11
       (.I0(rstdiv0_sync_r1_reg_rep__12_n_0),
        .O(rstdiv0_sync_r1_reg_rep__12_0));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  LUT1 #(
    .INIT(2'h2)) 
    rstdiv0_sync_r1_inst_rep__12
       (.I0(rstdiv0_sync_r1_reg_rep__13_n_0),
        .O(rstdiv0_sync_r1_reg_rep__13_0));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  LUT1 #(
    .INIT(2'h2)) 
    rstdiv0_sync_r1_inst_rep__13
       (.I0(rstdiv0_sync_r1_reg_rep__14_n_0),
        .O(rstdiv0_sync_r1_reg_rep__14_0));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  LUT1 #(
    .INIT(2'h2)) 
    rstdiv0_sync_r1_inst_rep__14
       (.I0(rstdiv0_sync_r1_reg_rep__15_n_0),
        .O(rstdiv0_sync_r1_reg_rep__15_0));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  LUT1 #(
    .INIT(2'h2)) 
    rstdiv0_sync_r1_inst_rep__15
       (.I0(rstdiv0_sync_r1_reg_rep__16_n_0),
        .O(rstdiv0_sync_r1_reg_rep__16_0));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  LUT1 #(
    .INIT(2'h2)) 
    rstdiv0_sync_r1_inst_rep__16
       (.I0(rstdiv0_sync_r1_reg_rep__17_n_0),
        .O(rstdiv0_sync_r1_reg_rep__17_0));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  LUT1 #(
    .INIT(2'h2)) 
    rstdiv0_sync_r1_inst_rep__17
       (.I0(rstdiv0_sync_r1_reg_rep__18_n_0),
        .O(rstdiv0_sync_r1_reg_rep__18_0));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  LUT1 #(
    .INIT(2'h2)) 
    rstdiv0_sync_r1_inst_rep__18
       (.I0(rstdiv0_sync_r1_reg_rep__19_n_0),
        .O(rstdiv0_sync_r1_reg_rep__19_0));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  LUT1 #(
    .INIT(2'h2)) 
    rstdiv0_sync_r1_inst_rep__19
       (.I0(rstdiv0_sync_r1_reg_rep__20_n_0),
        .O(rstdiv0_sync_r1_reg_rep__20_0));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  LUT1 #(
    .INIT(2'h2)) 
    rstdiv0_sync_r1_inst_rep__2
       (.I0(rstdiv0_sync_r1_reg_rep__3_n_0),
        .O(rstdiv0_sync_r1_reg_rep__2_0[0]));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  LUT1 #(
    .INIT(2'h2)) 
    rstdiv0_sync_r1_inst_rep__20
       (.I0(rstdiv0_sync_r1_reg_rep__21_n_0),
        .O(rstdiv0_sync_r1_reg_rep__21_0));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  LUT1 #(
    .INIT(2'h2)) 
    rstdiv0_sync_r1_inst_rep__21
       (.I0(rstdiv0_sync_r1_reg_rep__22_n_0),
        .O(rstdiv0_sync_r1_reg_rep__22_0));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  LUT1 #(
    .INIT(2'h2)) 
    rstdiv0_sync_r1_inst_rep__22
       (.I0(rstdiv0_sync_r1_reg_rep__23_n_0),
        .O(rstdiv0_sync_r1_reg_rep__23_0));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  LUT1 #(
    .INIT(2'h2)) 
    rstdiv0_sync_r1_inst_rep__23
       (.I0(rstdiv0_sync_r1_reg_rep__24_n_0),
        .O(rstdiv0_sync_r1_reg_rep__24_0));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  LUT1 #(
    .INIT(2'h2)) 
    rstdiv0_sync_r1_inst_rep__24
       (.I0(rstdiv0_sync_r1_reg_rep__25_n_0),
        .O(rstdiv0_sync_r1_reg_rep__25_0));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  LUT1 #(
    .INIT(2'h2)) 
    rstdiv0_sync_r1_inst_rep__3
       (.I0(rstdiv0_sync_r1_reg_rep__4_n_0),
        .O(rstdiv0_sync_r1_reg_rep__5_0[0]));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  LUT1 #(
    .INIT(2'h2)) 
    rstdiv0_sync_r1_inst_rep__4
       (.I0(rstdiv0_sync_r1_reg_rep__5_n_0),
        .O(rstdiv0_sync_r1_reg_rep__5_0[1]));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  LUT1 #(
    .INIT(2'h2)) 
    rstdiv0_sync_r1_inst_rep__5
       (.I0(rstdiv0_sync_r1_reg_rep__6_n_0),
        .O(rstdiv0_sync_r1_reg_rep__7_0[0]));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  LUT1 #(
    .INIT(2'h2)) 
    rstdiv0_sync_r1_inst_rep__6
       (.I0(rstdiv0_sync_r1_reg_rep__7_n_0),
        .O(rstdiv0_sync_r1_reg_rep__7_0[1]));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  LUT1 #(
    .INIT(2'h2)) 
    rstdiv0_sync_r1_inst_rep__7
       (.I0(rstdiv0_sync_r1_reg_rep__8_n_0),
        .O(rstdiv0_sync_r1_reg_rep__8_0));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  LUT1 #(
    .INIT(2'h2)) 
    rstdiv0_sync_r1_inst_rep__8
       (.I0(rstdiv0_sync_r1_reg_rep__9_n_0),
        .O(rstdiv0_sync_r1_reg_rep__9_0));
  (* IS_FANOUT_CONSTRAINED = "1" *) 
  LUT1 #(
    .INIT(2'h2)) 
    rstdiv0_sync_r1_inst_rep__9
       (.I0(rstdiv0_sync_r1_reg_rep__10_n_0),
        .O(rstdiv0_sync_r1_reg_rep__10_0[1]));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep
       (.C(\gen_mmcm.mmcm_i_0 ),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(rst_tmp),
        .Q(rstdiv0_sync_r1_reg_rep_n_0));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep__0
       (.C(\gen_mmcm.mmcm_i_0 ),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(rst_tmp),
        .Q(rstdiv0_sync_r1_reg_rep__0_n_0));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep__1
       (.C(\gen_mmcm.mmcm_i_0 ),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(rst_tmp),
        .Q(rstdiv0_sync_r1_reg_rep__1_n_0));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep__10
       (.C(\gen_mmcm.mmcm_i_0 ),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(rst_tmp),
        .Q(rstdiv0_sync_r1_reg_rep__10_n_0));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep__11
       (.C(\gen_mmcm.mmcm_i_0 ),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(rst_tmp),
        .Q(rstdiv0_sync_r1_reg_rep__11_n_0));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep__12
       (.C(\gen_mmcm.mmcm_i_0 ),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(rst_tmp),
        .Q(rstdiv0_sync_r1_reg_rep__12_n_0));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep__13
       (.C(\gen_mmcm.mmcm_i_0 ),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(rst_tmp),
        .Q(rstdiv0_sync_r1_reg_rep__13_n_0));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep__14
       (.C(\gen_mmcm.mmcm_i_0 ),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(rst_tmp),
        .Q(rstdiv0_sync_r1_reg_rep__14_n_0));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep__15
       (.C(\gen_mmcm.mmcm_i_0 ),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(rst_tmp),
        .Q(rstdiv0_sync_r1_reg_rep__15_n_0));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep__16
       (.C(\gen_mmcm.mmcm_i_0 ),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(rst_tmp),
        .Q(rstdiv0_sync_r1_reg_rep__16_n_0));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep__17
       (.C(\gen_mmcm.mmcm_i_0 ),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(rst_tmp),
        .Q(rstdiv0_sync_r1_reg_rep__17_n_0));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep__18
       (.C(\gen_mmcm.mmcm_i_0 ),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(rst_tmp),
        .Q(rstdiv0_sync_r1_reg_rep__18_n_0));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep__19
       (.C(\gen_mmcm.mmcm_i_0 ),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(rst_tmp),
        .Q(rstdiv0_sync_r1_reg_rep__19_n_0));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep__2
       (.C(\gen_mmcm.mmcm_i_0 ),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(rst_tmp),
        .Q(rstdiv0_sync_r1_reg_rep__2_n_0));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep__20
       (.C(\gen_mmcm.mmcm_i_0 ),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(rst_tmp),
        .Q(rstdiv0_sync_r1_reg_rep__20_n_0));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep__21
       (.C(\gen_mmcm.mmcm_i_0 ),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(rst_tmp),
        .Q(rstdiv0_sync_r1_reg_rep__21_n_0));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep__22
       (.C(\gen_mmcm.mmcm_i_0 ),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(rst_tmp),
        .Q(rstdiv0_sync_r1_reg_rep__22_n_0));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep__23
       (.C(\gen_mmcm.mmcm_i_0 ),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(rst_tmp),
        .Q(rstdiv0_sync_r1_reg_rep__23_n_0));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep__24
       (.C(\gen_mmcm.mmcm_i_0 ),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(rst_tmp),
        .Q(rstdiv0_sync_r1_reg_rep__24_n_0));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep__25
       (.C(\gen_mmcm.mmcm_i_0 ),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(rst_tmp),
        .Q(rstdiv0_sync_r1_reg_rep__25_n_0));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep__3
       (.C(\gen_mmcm.mmcm_i_0 ),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(rst_tmp),
        .Q(rstdiv0_sync_r1_reg_rep__3_n_0));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep__4
       (.C(\gen_mmcm.mmcm_i_0 ),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(rst_tmp),
        .Q(rstdiv0_sync_r1_reg_rep__4_n_0));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep__5
       (.C(\gen_mmcm.mmcm_i_0 ),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(rst_tmp),
        .Q(rstdiv0_sync_r1_reg_rep__5_n_0));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep__6
       (.C(\gen_mmcm.mmcm_i_0 ),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(rst_tmp),
        .Q(rstdiv0_sync_r1_reg_rep__6_n_0));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep__7
       (.C(\gen_mmcm.mmcm_i_0 ),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(rst_tmp),
        .Q(rstdiv0_sync_r1_reg_rep__7_n_0));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep__8
       (.C(\gen_mmcm.mmcm_i_0 ),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(rst_tmp),
        .Q(rstdiv0_sync_r1_reg_rep__8_n_0));
  (* ORIG_CELL_NAME = "rstdiv0_sync_r1_reg" *) 
  FDPE rstdiv0_sync_r1_reg_rep__9
       (.C(\gen_mmcm.mmcm_i_0 ),
        .CE(1'b1),
        .D(rstdiv0_sync_r[11]),
        .PRE(rst_tmp),
        .Q(rstdiv0_sync_r1_reg_rep__9_n_0));
  FDPE \rstdiv0_sync_r_reg[0] 
       (.C(\gen_mmcm.mmcm_i_0 ),
        .CE(1'b1),
        .D(1'b0),
        .PRE(rst_tmp),
        .Q(rstdiv0_sync_r[0]));
  FDPE \rstdiv0_sync_r_reg[10] 
       (.C(\gen_mmcm.mmcm_i_0 ),
        .CE(1'b1),
        .D(rstdiv0_sync_r[9]),
        .PRE(rst_tmp),
        .Q(rstdiv0_sync_r[10]));
  FDPE \rstdiv0_sync_r_reg[11] 
       (.C(\gen_mmcm.mmcm_i_0 ),
        .CE(1'b1),
        .D(rstdiv0_sync_r[10]),
        .PRE(rst_tmp),
        .Q(rstdiv0_sync_r[11]));
  FDPE \rstdiv0_sync_r_reg[1] 
       (.C(\gen_mmcm.mmcm_i_0 ),
        .CE(1'b1),
        .D(rstdiv0_sync_r[0]),
        .PRE(rst_tmp),
        .Q(rstdiv0_sync_r[1]));
  FDPE \rstdiv0_sync_r_reg[2] 
       (.C(\gen_mmcm.mmcm_i_0 ),
        .CE(1'b1),
        .D(rstdiv0_sync_r[1]),
        .PRE(rst_tmp),
        .Q(rstdiv0_sync_r[2]));
  FDPE \rstdiv0_sync_r_reg[3] 
       (.C(\gen_mmcm.mmcm_i_0 ),
        .CE(1'b1),
        .D(rstdiv0_sync_r[2]),
        .PRE(rst_tmp),
        .Q(rstdiv0_sync_r[3]));
  FDPE \rstdiv0_sync_r_reg[4] 
       (.C(\gen_mmcm.mmcm_i_0 ),
        .CE(1'b1),
        .D(rstdiv0_sync_r[3]),
        .PRE(rst_tmp),
        .Q(rstdiv0_sync_r[4]));
  FDPE \rstdiv0_sync_r_reg[5] 
       (.C(\gen_mmcm.mmcm_i_0 ),
        .CE(1'b1),
        .D(rstdiv0_sync_r[4]),
        .PRE(rst_tmp),
        .Q(rstdiv0_sync_r[5]));
  FDPE \rstdiv0_sync_r_reg[6] 
       (.C(\gen_mmcm.mmcm_i_0 ),
        .CE(1'b1),
        .D(rstdiv0_sync_r[5]),
        .PRE(rst_tmp),
        .Q(rstdiv0_sync_r[6]));
  FDPE \rstdiv0_sync_r_reg[7] 
       (.C(\gen_mmcm.mmcm_i_0 ),
        .CE(1'b1),
        .D(rstdiv0_sync_r[6]),
        .PRE(rst_tmp),
        .Q(rstdiv0_sync_r[7]));
  FDPE \rstdiv0_sync_r_reg[8] 
       (.C(\gen_mmcm.mmcm_i_0 ),
        .CE(1'b1),
        .D(rstdiv0_sync_r[7]),
        .PRE(rst_tmp),
        .Q(rstdiv0_sync_r[8]));
  FDPE \rstdiv0_sync_r_reg[9] 
       (.C(\gen_mmcm.mmcm_i_0 ),
        .CE(1'b1),
        .D(rstdiv0_sync_r[8]),
        .PRE(rst_tmp),
        .Q(rstdiv0_sync_r[9]));
  (* RTL_MAX_FANOUT = "found" *) 
  (* syn_maxfan = "10" *) 
  FDPE rstdiv2_sync_r1_reg
       (.C(\gen_mmcm.u_bufg_clk_div2_n_0 ),
        .CE(1'b1),
        .D(p_0_in),
        .PRE(rst_tmp),
        .Q(rstdiv2_sync_r1));
  FDPE \rstdiv2_sync_r_reg[0] 
       (.C(\gen_mmcm.u_bufg_clk_div2_n_0 ),
        .CE(1'b1),
        .D(1'b0),
        .PRE(rst_tmp),
        .Q(\rstdiv2_sync_r_reg_n_0_[0] ));
  FDPE \rstdiv2_sync_r_reg[10] 
       (.C(\gen_mmcm.u_bufg_clk_div2_n_0 ),
        .CE(1'b1),
        .D(\rstdiv2_sync_r_reg_n_0_[9] ),
        .PRE(rst_tmp),
        .Q(\rstdiv2_sync_r_reg_n_0_[10] ));
  FDPE \rstdiv2_sync_r_reg[11] 
       (.C(\gen_mmcm.u_bufg_clk_div2_n_0 ),
        .CE(1'b1),
        .D(\rstdiv2_sync_r_reg_n_0_[10] ),
        .PRE(rst_tmp),
        .Q(p_0_in));
  FDPE \rstdiv2_sync_r_reg[1] 
       (.C(\gen_mmcm.u_bufg_clk_div2_n_0 ),
        .CE(1'b1),
        .D(\rstdiv2_sync_r_reg_n_0_[0] ),
        .PRE(rst_tmp),
        .Q(\rstdiv2_sync_r_reg_n_0_[1] ));
  FDPE \rstdiv2_sync_r_reg[2] 
       (.C(\gen_mmcm.u_bufg_clk_div2_n_0 ),
        .CE(1'b1),
        .D(\rstdiv2_sync_r_reg_n_0_[1] ),
        .PRE(rst_tmp),
        .Q(\rstdiv2_sync_r_reg_n_0_[2] ));
  FDPE \rstdiv2_sync_r_reg[3] 
       (.C(\gen_mmcm.u_bufg_clk_div2_n_0 ),
        .CE(1'b1),
        .D(\rstdiv2_sync_r_reg_n_0_[2] ),
        .PRE(rst_tmp),
        .Q(\rstdiv2_sync_r_reg_n_0_[3] ));
  FDPE \rstdiv2_sync_r_reg[4] 
       (.C(\gen_mmcm.u_bufg_clk_div2_n_0 ),
        .CE(1'b1),
        .D(\rstdiv2_sync_r_reg_n_0_[3] ),
        .PRE(rst_tmp),
        .Q(\rstdiv2_sync_r_reg_n_0_[4] ));
  FDPE \rstdiv2_sync_r_reg[5] 
       (.C(\gen_mmcm.u_bufg_clk_div2_n_0 ),
        .CE(1'b1),
        .D(\rstdiv2_sync_r_reg_n_0_[4] ),
        .PRE(rst_tmp),
        .Q(\rstdiv2_sync_r_reg_n_0_[5] ));
  FDPE \rstdiv2_sync_r_reg[6] 
       (.C(\gen_mmcm.u_bufg_clk_div2_n_0 ),
        .CE(1'b1),
        .D(\rstdiv2_sync_r_reg_n_0_[5] ),
        .PRE(rst_tmp),
        .Q(\rstdiv2_sync_r_reg_n_0_[6] ));
  FDPE \rstdiv2_sync_r_reg[7] 
       (.C(\gen_mmcm.u_bufg_clk_div2_n_0 ),
        .CE(1'b1),
        .D(\rstdiv2_sync_r_reg_n_0_[6] ),
        .PRE(rst_tmp),
        .Q(\rstdiv2_sync_r_reg_n_0_[7] ));
  FDPE \rstdiv2_sync_r_reg[8] 
       (.C(\gen_mmcm.u_bufg_clk_div2_n_0 ),
        .CE(1'b1),
        .D(\rstdiv2_sync_r_reg_n_0_[7] ),
        .PRE(rst_tmp),
        .Q(\rstdiv2_sync_r_reg_n_0_[8] ));
  FDPE \rstdiv2_sync_r_reg[9] 
       (.C(\gen_mmcm.u_bufg_clk_div2_n_0 ),
        .CE(1'b1),
        .D(\rstdiv2_sync_r_reg_n_0_[8] ),
        .PRE(rst_tmp),
        .Q(\rstdiv2_sync_r_reg_n_0_[9] ));
  (* SOFT_HLUTNM = "soft_lutpair13" *) 
  LUT2 #(
    .INIT(4'hB)) 
    \samp_edge_cnt0_r[0]_i_1 
       (.I0(rstdiv0_sync_r1_reg_rep__21_0),
        .I1(samp_edge_cnt0_en_r),
        .O(samp_edge_cnt0_en_r_reg));
  (* SOFT_HLUTNM = "soft_lutpair6" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \tap_cnt_cpt_r[5]_i_1 
       (.I0(rstdiv0_sync_r1_reg_rep__21_0),
        .I1(\tap_cnt_cpt_r_reg[5] ),
        .O(new_cnt_cpt_r_reg));
  (* BOX_TYPE = "PRIMITIVE" *) 
  BUFG u_bufg_clkdiv0
       (.I(clk_pll_i),
        .O(\gen_mmcm.mmcm_i_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  BUFH u_bufh_pll_clk3
       (.I(pll_clk3_out),
        .O(pll_clk3));
  (* SOFT_HLUTNM = "soft_lutpair6" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \wait_cnt[3]_i_1 
       (.I0(rstdiv0_sync_r1_reg_rep__21_0),
        .I1(po_cnt_dec),
        .O(SS));
  (* SOFT_HLUTNM = "soft_lutpair11" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \wait_cnt_r[3]_i_1 
       (.I0(rstdiv0_sync_r1_reg_rep__21_0),
        .I1(po_cnt_dec_2),
        .O(po_cnt_dec_reg));
  (* SOFT_HLUTNM = "soft_lutpair10" *) 
  LUT2 #(
    .INIT(4'hE)) 
    \wait_cnt_r[3]_i_1__0 
       (.I0(rstdiv0_sync_r1_reg_rep__22_0),
        .I1(pi_cnt_dec),
        .O(pi_cnt_dec_reg));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_iodelay_ctrl" *) 
module mig_mig_7series_v4_2_iodelay_ctrl
   (iodelay_ctrl_rdy,
    out,
    AS,
    clk_ref_i,
    sys_rst);
  output [0:0]iodelay_ctrl_rdy;
  output out;
  output [0:0]AS;
  input clk_ref_i;
  input sys_rst;

  wire [0:0]AS;
  wire clk_ref_i;
  wire [0:0]iodelay_ctrl_rdy;
  wire [0:0]rst_ref;
  wire \rst_ref_sync_r_reg_n_0_[0][0] ;
  wire \rst_ref_sync_r_reg_n_0_[0][10] ;
  wire \rst_ref_sync_r_reg_n_0_[0][11] ;
  wire \rst_ref_sync_r_reg_n_0_[0][12] ;
  wire \rst_ref_sync_r_reg_n_0_[0][13] ;
  wire \rst_ref_sync_r_reg_n_0_[0][1] ;
  wire \rst_ref_sync_r_reg_n_0_[0][2] ;
  wire \rst_ref_sync_r_reg_n_0_[0][3] ;
  wire \rst_ref_sync_r_reg_n_0_[0][4] ;
  wire \rst_ref_sync_r_reg_n_0_[0][5] ;
  wire \rst_ref_sync_r_reg_n_0_[0][6] ;
  wire \rst_ref_sync_r_reg_n_0_[0][7] ;
  wire \rst_ref_sync_r_reg_n_0_[0][8] ;
  wire \rst_ref_sync_r_reg_n_0_[0][9] ;
  (* RTL_KEEP = "true" *) wire sys_rst_i;

  assign out = sys_rst_i;
  assign sys_rst_i = sys_rst;
  LUT1 #(
    .INIT(2'h1)) 
    plle2_i_i_1
       (.I0(sys_rst_i),
        .O(AS));
  (* syn_maxfan = "10" *) 
  FDPE \rst_ref_sync_r_reg[0][0] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(1'b0),
        .PRE(AS),
        .Q(\rst_ref_sync_r_reg_n_0_[0][0] ));
  (* syn_maxfan = "10" *) 
  FDPE \rst_ref_sync_r_reg[0][10] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\rst_ref_sync_r_reg_n_0_[0][9] ),
        .PRE(AS),
        .Q(\rst_ref_sync_r_reg_n_0_[0][10] ));
  (* syn_maxfan = "10" *) 
  FDPE \rst_ref_sync_r_reg[0][11] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\rst_ref_sync_r_reg_n_0_[0][10] ),
        .PRE(AS),
        .Q(\rst_ref_sync_r_reg_n_0_[0][11] ));
  (* syn_maxfan = "10" *) 
  FDPE \rst_ref_sync_r_reg[0][12] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\rst_ref_sync_r_reg_n_0_[0][11] ),
        .PRE(AS),
        .Q(\rst_ref_sync_r_reg_n_0_[0][12] ));
  (* syn_maxfan = "10" *) 
  FDPE \rst_ref_sync_r_reg[0][13] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\rst_ref_sync_r_reg_n_0_[0][12] ),
        .PRE(AS),
        .Q(\rst_ref_sync_r_reg_n_0_[0][13] ));
  (* syn_maxfan = "10" *) 
  FDPE \rst_ref_sync_r_reg[0][14] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\rst_ref_sync_r_reg_n_0_[0][13] ),
        .PRE(AS),
        .Q(rst_ref));
  (* syn_maxfan = "10" *) 
  FDPE \rst_ref_sync_r_reg[0][1] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\rst_ref_sync_r_reg_n_0_[0][0] ),
        .PRE(AS),
        .Q(\rst_ref_sync_r_reg_n_0_[0][1] ));
  (* syn_maxfan = "10" *) 
  FDPE \rst_ref_sync_r_reg[0][2] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\rst_ref_sync_r_reg_n_0_[0][1] ),
        .PRE(AS),
        .Q(\rst_ref_sync_r_reg_n_0_[0][2] ));
  (* syn_maxfan = "10" *) 
  FDPE \rst_ref_sync_r_reg[0][3] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\rst_ref_sync_r_reg_n_0_[0][2] ),
        .PRE(AS),
        .Q(\rst_ref_sync_r_reg_n_0_[0][3] ));
  (* syn_maxfan = "10" *) 
  FDPE \rst_ref_sync_r_reg[0][4] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\rst_ref_sync_r_reg_n_0_[0][3] ),
        .PRE(AS),
        .Q(\rst_ref_sync_r_reg_n_0_[0][4] ));
  (* syn_maxfan = "10" *) 
  FDPE \rst_ref_sync_r_reg[0][5] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\rst_ref_sync_r_reg_n_0_[0][4] ),
        .PRE(AS),
        .Q(\rst_ref_sync_r_reg_n_0_[0][5] ));
  (* syn_maxfan = "10" *) 
  FDPE \rst_ref_sync_r_reg[0][6] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\rst_ref_sync_r_reg_n_0_[0][5] ),
        .PRE(AS),
        .Q(\rst_ref_sync_r_reg_n_0_[0][6] ));
  (* syn_maxfan = "10" *) 
  FDPE \rst_ref_sync_r_reg[0][7] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\rst_ref_sync_r_reg_n_0_[0][6] ),
        .PRE(AS),
        .Q(\rst_ref_sync_r_reg_n_0_[0][7] ));
  (* syn_maxfan = "10" *) 
  FDPE \rst_ref_sync_r_reg[0][8] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\rst_ref_sync_r_reg_n_0_[0][7] ),
        .PRE(AS),
        .Q(\rst_ref_sync_r_reg_n_0_[0][8] ));
  (* syn_maxfan = "10" *) 
  FDPE \rst_ref_sync_r_reg[0][9] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\rst_ref_sync_r_reg_n_0_[0][8] ),
        .PRE(AS),
        .Q(\rst_ref_sync_r_reg_n_0_[0][9] ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* IODELAY_GROUP = "MIG_IODELAY_MIG0" *) 
  IDELAYCTRL #(
    .SIM_DEVICE("7SERIES")) 
    u_idelayctrl_200
       (.RDY(iodelay_ctrl_rdy),
        .REFCLK(clk_ref_i),
        .RST(rst_ref));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_mc" *) 
module mig_mig_7series_v4_2_mc
   (app_ref_ack,
    app_zq_ack,
    \generate_maint_cmds.insert_maint_r_lcl_reg ,
    accept_ns,
    bm_end_r1,
    bm_end_r1_0,
    bm_end_r1_1,
    mc_cmd,
    app_sr_active,
    \read_fifo.tail_r_reg[0] ,
    phy_dout,
    mc_we_n,
    mc_ras_n,
    mc_cs_n,
    mc_cas_n,
    d_in,
    Q,
    \req_bank_r_lcl_reg[2] ,
    \req_bank_r_lcl_reg[2]_0 ,
    \req_bank_r_lcl_reg[2]_1 ,
    \req_bank_r_lcl_reg[2]_2 ,
    \req_row_r_lcl_reg[13] ,
    \pointer_ram.pointer_we ,
    wr_data_en,
    \read_fifo.fifo_out_data_r_reg[7] ,
    wr_data_addr,
    mc_ref_zq_wip,
    \cmd_pipe_plus.mc_bank_reg[8]_0 ,
    mc_odt,
    mc_cke,
    mc_wrdata_en,
    \cmd_pipe_plus.mc_data_offset_reg[3]_0 ,
    \cmd_pipe_plus.mc_data_offset_reg[5]_0 ,
    \cmd_pipe_plus.mc_data_offset_reg[4]_0 ,
    \cmd_pipe_plus.mc_data_offset_reg[2]_0 ,
    \cmd_pipe_plus.mc_data_offset_reg[1]_0 ,
    \cmd_pipe_plus.mc_data_offset_reg[0]_0 ,
    \cmd_pipe_plus.mc_data_offset_1_reg[3]_0 ,
    \cmd_pipe_plus.mc_data_offset_1_reg[5]_0 ,
    \cmd_pipe_plus.mc_data_offset_1_reg[4]_0 ,
    \cmd_pipe_plus.mc_data_offset_1_reg[2]_0 ,
    \cmd_pipe_plus.mc_data_offset_1_reg[1]_0 ,
    \cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ,
    \cmd_pipe_plus.mc_data_offset_2_reg[3]_0 ,
    \cmd_pipe_plus.mc_data_offset_2_reg[5]_0 ,
    \cmd_pipe_plus.mc_data_offset_2_reg[4]_0 ,
    \cmd_pipe_plus.mc_data_offset_2_reg[2]_0 ,
    \cmd_pipe_plus.mc_data_offset_2_reg[1]_0 ,
    \cmd_pipe_plus.mc_data_offset_2_reg[0]_0 ,
    idle,
    \last_master_r_reg[2] ,
    \periodic_read_request.periodic_rd_r_cnt_reg ,
    \periodic_rd_generation.periodic_rd_cntr1_r_reg ,
    phy_mc_ctl_full,
    \zq_cntrl.zq_request_logic.zq_request_r_reg ,
    of_ctl_full_v,
    SR,
    \periodic_read_request.periodic_rd_r_lcl_reg ,
    \grant_r_reg[0] ,
    app_zq_req,
    app_sr_req,
    \last_master_r_reg[2]_0 ,
    use_addr,
    cmd,
    \inhbt_act_faw.inhbt_act_faw_r_reg ,
    app_ref_req,
    \read_fifo.tail_r_reg[2] ,
    \cmd_pipe_plus.mc_data_offset_reg[5]_1 ,
    \cmd_pipe_plus.mc_data_offset_1_reg[5]_1 ,
    \cmd_pipe_plus.mc_data_offset_2_reg[5]_1 ,
    S,
    row_hit_r_reg,
    row_hit_r_reg_0,
    row_hit_r_reg_1,
    row_hit_r_reg_2,
    row_hit_r_reg_3,
    mem_reg_0_15_42_47,
    mem_reg_0_15_36_41,
    \periodic_rd_generation.periodic_rd_timer_r_reg[2] ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ,
    rb_hit_busy_r_reg,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[6] ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ,
    \rtp_timer_r_reg[1] ,
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] ,
    D,
    ras_timer_zero_r_reg,
    ras_timer_zero_r_reg_0,
    ras_timer_zero_r_reg_1,
    phy_mc_data_full,
    \rtp_timer_r_reg[0] ,
    ram_init_done_r,
    was_priority_reg,
    \req_data_buf_addr_r_reg[3] ,
    \req_bank_r_lcl_reg[2]_3 ,
    \req_col_r_reg[9] ,
    \read_fifo.tail_r_reg[0]_0 ,
    \cmd_pipe_plus.mc_data_offset_reg[0]_1 ,
    \cmd_pipe_plus.mc_data_offset_1_reg[0]_1 ,
    \cmd_pipe_plus.mc_data_offset_2_reg[0]_1 );
  output app_ref_ack;
  output app_zq_ack;
  output \generate_maint_cmds.insert_maint_r_lcl_reg ;
  output accept_ns;
  output bm_end_r1;
  output bm_end_r1_0;
  output bm_end_r1_1;
  output [1:0]mc_cmd;
  output app_sr_active;
  output [0:0]\read_fifo.tail_r_reg[0] ;
  output [6:0]phy_dout;
  output [2:0]mc_we_n;
  output [2:0]mc_ras_n;
  output [0:0]mc_cs_n;
  output [2:0]mc_cas_n;
  output [3:0]d_in;
  output [38:0]Q;
  output [2:0]\req_bank_r_lcl_reg[2] ;
  output [2:0]\req_bank_r_lcl_reg[2]_0 ;
  output [2:0]\req_bank_r_lcl_reg[2]_1 ;
  output [2:0]\req_bank_r_lcl_reg[2]_2 ;
  output [19:0]\req_row_r_lcl_reg[13] ;
  output \pointer_ram.pointer_we ;
  output wr_data_en;
  output [1:0]\read_fifo.fifo_out_data_r_reg[7] ;
  output [3:0]wr_data_addr;
  output mc_ref_zq_wip;
  output [8:0]\cmd_pipe_plus.mc_bank_reg[8]_0 ;
  output [0:0]mc_odt;
  output [0:0]mc_cke;
  output mc_wrdata_en;
  output [0:0]\cmd_pipe_plus.mc_data_offset_reg[3]_0 ;
  output \cmd_pipe_plus.mc_data_offset_reg[5]_0 ;
  output \cmd_pipe_plus.mc_data_offset_reg[4]_0 ;
  output \cmd_pipe_plus.mc_data_offset_reg[2]_0 ;
  output \cmd_pipe_plus.mc_data_offset_reg[1]_0 ;
  output \cmd_pipe_plus.mc_data_offset_reg[0]_0 ;
  output [0:0]\cmd_pipe_plus.mc_data_offset_1_reg[3]_0 ;
  output \cmd_pipe_plus.mc_data_offset_1_reg[5]_0 ;
  output \cmd_pipe_plus.mc_data_offset_1_reg[4]_0 ;
  output \cmd_pipe_plus.mc_data_offset_1_reg[2]_0 ;
  output \cmd_pipe_plus.mc_data_offset_1_reg[1]_0 ;
  output \cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ;
  output [0:0]\cmd_pipe_plus.mc_data_offset_2_reg[3]_0 ;
  output \cmd_pipe_plus.mc_data_offset_2_reg[5]_0 ;
  output \cmd_pipe_plus.mc_data_offset_2_reg[4]_0 ;
  output \cmd_pipe_plus.mc_data_offset_2_reg[2]_0 ;
  output \cmd_pipe_plus.mc_data_offset_2_reg[1]_0 ;
  output \cmd_pipe_plus.mc_data_offset_2_reg[0]_0 ;
  output idle;
  input \last_master_r_reg[2] ;
  input \periodic_read_request.periodic_rd_r_cnt_reg ;
  input \periodic_rd_generation.periodic_rd_cntr1_r_reg ;
  input phy_mc_ctl_full;
  input \zq_cntrl.zq_request_logic.zq_request_r_reg ;
  input [0:0]of_ctl_full_v;
  input [0:0]SR;
  input \periodic_read_request.periodic_rd_r_lcl_reg ;
  input \grant_r_reg[0] ;
  input app_zq_req;
  input app_sr_req;
  input \last_master_r_reg[2]_0 ;
  input use_addr;
  input [1:0]cmd;
  input \inhbt_act_faw.inhbt_act_faw_r_reg ;
  input app_ref_req;
  input \read_fifo.tail_r_reg[2] ;
  input [5:0]\cmd_pipe_plus.mc_data_offset_reg[5]_1 ;
  input [5:0]\cmd_pipe_plus.mc_data_offset_1_reg[5]_1 ;
  input [5:0]\cmd_pipe_plus.mc_data_offset_2_reg[5]_1 ;
  input [2:0]S;
  input [0:0]row_hit_r_reg;
  input [0:0]row_hit_r_reg_0;
  input [0:0]row_hit_r_reg_1;
  input [0:0]row_hit_r_reg_2;
  input [0:0]row_hit_r_reg_3;
  input mem_reg_0_15_42_47;
  input mem_reg_0_15_36_41;
  input \periodic_rd_generation.periodic_rd_timer_r_reg[2] ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ;
  input rb_hit_busy_r_reg;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[6] ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ;
  input \rtp_timer_r_reg[1] ;
  input \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] ;
  input [13:0]D;
  input ras_timer_zero_r_reg;
  input ras_timer_zero_r_reg_0;
  input ras_timer_zero_r_reg_1;
  input phy_mc_data_full;
  input \rtp_timer_r_reg[0] ;
  input ram_init_done_r;
  input was_priority_reg;
  input [3:0]\req_data_buf_addr_r_reg[3] ;
  input [2:0]\req_bank_r_lcl_reg[2]_3 ;
  input [9:0]\req_col_r_reg[9] ;
  input \read_fifo.tail_r_reg[0]_0 ;
  input \cmd_pipe_plus.mc_data_offset_reg[0]_1 ;
  input \cmd_pipe_plus.mc_data_offset_1_reg[0]_1 ;
  input \cmd_pipe_plus.mc_data_offset_2_reg[0]_1 ;

  wire [13:0]D;
  wire [38:0]Q;
  wire [2:0]S;
  wire [0:0]SR;
  wire accept_internal_r;
  wire accept_ns;
  wire app_ref_ack;
  wire app_ref_req;
  wire app_sr_active;
  wire app_sr_req;
  wire app_zq_ack;
  wire app_zq_req;
  wire [3:3]\arb_mux0/arb_row_col0/pre_4_1_1T_arb.pre_arb0/last_master_r ;
  wire \arb_mux0/arb_select0/cke_r ;
  wire [5:1]\arb_mux0/arb_select0/mc_data_offset1 ;
  wire [5:1]\arb_mux0/arb_select0/mc_data_offset_11 ;
  wire [5:1]\arb_mux0/arb_select0/mc_data_offset_21 ;
  wire \arb_mux0/cs_en2 ;
  wire \bank_cntrl[0].bank0/auto_pre_r ;
  wire \bank_cntrl[0].bank0/bank_queue0/set_order_q ;
  wire \bank_cntrl[0].bank0/bank_state0/col_wait_r ;
  wire \bank_cntrl[0].bank0/bank_state0/demand_priority_r ;
  wire \bank_cntrl[0].bank0/bank_state0/demanded_prior_r ;
  wire \bank_cntrl[0].bank0/q_has_rd ;
  wire [1:1]\bank_cntrl[0].bank0/rb_hit_busies_r ;
  wire \bank_cntrl[0].bank0/tail_r ;
  wire \bank_cntrl[0].bank0/wait_for_maint_r ;
  wire \bank_cntrl[1].bank0/auto_pre_r ;
  wire \bank_cntrl[1].bank0/bank_queue0/pre_bm_end_r ;
  wire \bank_cntrl[1].bank0/bank_queue0/set_order_q ;
  wire \bank_cntrl[1].bank0/bank_state0/col_wait_r ;
  wire \bank_cntrl[1].bank0/bank_state0/demand_priority_r ;
  wire \bank_cntrl[1].bank0/bank_state0/demanded_prior_r ;
  wire \bank_cntrl[1].bank0/bank_state0/req_bank_rdy_ns ;
  wire \bank_cntrl[1].bank0/pass_open_bank_r ;
  wire \bank_cntrl[1].bank0/q_has_rd ;
  wire \bank_cntrl[1].bank0/tail_r ;
  wire \bank_cntrl[1].bank0/wait_for_maint_r ;
  wire \bank_cntrl[2].bank0/auto_pre_r ;
  wire \bank_cntrl[2].bank0/bank_queue0/set_order_q ;
  wire \bank_cntrl[2].bank0/bank_state0/col_wait_r ;
  wire \bank_cntrl[2].bank0/bank_state0/demand_priority_r ;
  wire \bank_cntrl[2].bank0/bank_state0/demanded_prior_r ;
  wire \bank_cntrl[2].bank0/bank_state0/override_demand_ns ;
  wire \bank_cntrl[2].bank0/bank_state0/override_demand_r ;
  wire \bank_cntrl[2].bank0/q_has_rd ;
  wire [4:4]\bank_cntrl[2].bank0/rb_hit_busies_r ;
  wire \bank_cntrl[2].bank0/tail_r ;
  wire \bank_cntrl[2].bank0/wait_for_maint_r ;
  wire \bank_cntrl[3].bank0/auto_pre_r ;
  wire \bank_cntrl[3].bank0/bank_queue0/pre_bm_end_r ;
  wire \bank_cntrl[3].bank0/bank_queue0/set_order_q ;
  wire \bank_cntrl[3].bank0/bank_state0/col_wait_r ;
  wire \bank_cntrl[3].bank0/bank_state0/demand_priority_r ;
  wire \bank_cntrl[3].bank0/pass_open_bank_r ;
  wire \bank_cntrl[3].bank0/q_has_rd ;
  wire \bank_cntrl[3].bank0/tail_r ;
  wire \bank_cntrl[3].bank0/wait_for_maint_r ;
  wire [3:0]\bank_common0/maint_controller.maint_hit_busies_r ;
  wire \bank_common0/periodic_rd_cntr_r ;
  wire [3:0]\bank_common0/rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r ;
  wire bank_mach0_n_10;
  wire bank_mach0_n_104;
  wire bank_mach0_n_113;
  wire bank_mach0_n_114;
  wire bank_mach0_n_115;
  wire bank_mach0_n_116;
  wire bank_mach0_n_117;
  wire bank_mach0_n_122;
  wire bank_mach0_n_123;
  wire bank_mach0_n_124;
  wire bank_mach0_n_125;
  wire bank_mach0_n_126;
  wire bank_mach0_n_127;
  wire bank_mach0_n_128;
  wire bank_mach0_n_129;
  wire bank_mach0_n_131;
  wire bank_mach0_n_132;
  wire bank_mach0_n_133;
  wire bank_mach0_n_135;
  wire bank_mach0_n_136;
  wire bank_mach0_n_137;
  wire bank_mach0_n_138;
  wire bank_mach0_n_140;
  wire bank_mach0_n_141;
  wire bank_mach0_n_142;
  wire bank_mach0_n_143;
  wire bank_mach0_n_144;
  wire bank_mach0_n_147;
  wire bank_mach0_n_149;
  wire bank_mach0_n_150;
  wire bank_mach0_n_151;
  wire bank_mach0_n_152;
  wire bank_mach0_n_154;
  wire bank_mach0_n_155;
  wire bank_mach0_n_156;
  wire bank_mach0_n_157;
  wire bank_mach0_n_158;
  wire bank_mach0_n_159;
  wire bank_mach0_n_160;
  wire bank_mach0_n_161;
  wire bank_mach0_n_162;
  wire bank_mach0_n_163;
  wire bank_mach0_n_164;
  wire bank_mach0_n_257;
  wire bank_mach0_n_258;
  wire bank_mach0_n_259;
  wire bank_mach0_n_260;
  wire bank_mach0_n_261;
  wire bank_mach0_n_262;
  wire bank_mach0_n_263;
  wire bank_mach0_n_264;
  wire bank_mach0_n_265;
  wire bank_mach0_n_266;
  wire bank_mach0_n_267;
  wire bank_mach0_n_274;
  wire bank_mach0_n_275;
  wire bank_mach0_n_276;
  wire bank_mach0_n_277;
  wire bank_mach0_n_278;
  wire bank_mach0_n_58;
  wire bank_mach0_n_59;
  wire bank_mach0_n_91;
  wire bank_mach0_n_92;
  wire bank_mach0_n_93;
  wire bank_mach0_n_94;
  wire bank_mach0_n_96;
  wire bank_mach0_n_98;
  wire bm_end_r1;
  wire bm_end_r1_0;
  wire bm_end_r1_1;
  wire clear_periodic_rd_request;
  wire [1:0]cmd;
  wire \cmd_pipe_plus.mc_aux_out0_reg_n_0_[1] ;
  wire [8:0]\cmd_pipe_plus.mc_bank_reg[8]_0 ;
  wire \cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ;
  wire \cmd_pipe_plus.mc_data_offset_1_reg[0]_1 ;
  wire \cmd_pipe_plus.mc_data_offset_1_reg[1]_0 ;
  wire \cmd_pipe_plus.mc_data_offset_1_reg[2]_0 ;
  wire [0:0]\cmd_pipe_plus.mc_data_offset_1_reg[3]_0 ;
  wire \cmd_pipe_plus.mc_data_offset_1_reg[4]_0 ;
  wire \cmd_pipe_plus.mc_data_offset_1_reg[5]_0 ;
  wire [5:0]\cmd_pipe_plus.mc_data_offset_1_reg[5]_1 ;
  wire \cmd_pipe_plus.mc_data_offset_2_reg[0]_0 ;
  wire \cmd_pipe_plus.mc_data_offset_2_reg[0]_1 ;
  wire \cmd_pipe_plus.mc_data_offset_2_reg[1]_0 ;
  wire \cmd_pipe_plus.mc_data_offset_2_reg[2]_0 ;
  wire [0:0]\cmd_pipe_plus.mc_data_offset_2_reg[3]_0 ;
  wire \cmd_pipe_plus.mc_data_offset_2_reg[4]_0 ;
  wire \cmd_pipe_plus.mc_data_offset_2_reg[5]_0 ;
  wire [5:0]\cmd_pipe_plus.mc_data_offset_2_reg[5]_1 ;
  wire \cmd_pipe_plus.mc_data_offset_reg[0]_0 ;
  wire \cmd_pipe_plus.mc_data_offset_reg[0]_1 ;
  wire \cmd_pipe_plus.mc_data_offset_reg[1]_0 ;
  wire \cmd_pipe_plus.mc_data_offset_reg[2]_0 ;
  wire [0:0]\cmd_pipe_plus.mc_data_offset_reg[3]_0 ;
  wire \cmd_pipe_plus.mc_data_offset_reg[4]_0 ;
  wire \cmd_pipe_plus.mc_data_offset_reg[5]_0 ;
  wire [5:0]\cmd_pipe_plus.mc_data_offset_reg[5]_1 ;
  wire col_mach0_n_12;
  wire col_mach0_n_7;
  wire col_periodic_rd;
  wire col_rd_wr;
  wire col_rd_wr_r1;
  wire col_rd_wr_r2;
  wire [3:0]col_wr_data_buf_addr;
  wire [3:0]d_in;
  wire \generate_maint_cmds.insert_maint_r_lcl_reg ;
  wire \grant_r_reg[0] ;
  wire [3:0]head_r;
  wire i___0_n_0;
  wire i___12_n_0;
  wire i___13_n_0;
  wire i___14_n_0;
  wire i___15_n_0;
  wire i___16_n_0;
  wire i___17_n_0;
  wire i___18_n_0;
  wire i___19_n_0;
  wire i___1_n_0;
  wire i___20_n_0;
  wire i___21_n_0;
  wire i___22_n_0;
  wire i___23_n_0;
  wire i___24_n_0;
  wire i___25_n_0;
  wire i___26_n_0;
  wire i___27_n_0;
  wire i___28_n_0;
  wire i___29_n_0;
  wire i___2_n_0;
  wire i___30_n_0;
  wire i___31_n_0;
  wire i___32_n_0;
  wire i___33_n_0;
  wire i___34_n_0;
  wire i___35_n_0;
  wire i___36_n_0;
  wire i___37_n_0;
  wire i___38_n_0;
  wire i___39_n_0;
  wire i___3_n_0;
  wire i___40_n_0;
  wire i___41_n_0;
  wire i___42_n_0;
  wire i___43_n_0;
  wire i___44_n_0;
  wire i___45_n_0;
  wire i___46_n_0;
  wire i___47_n_0;
  wire i___48_n_0;
  wire i___49_n_0;
  wire i___4_n_0;
  wire i___50_n_0;
  wire i___51_n_0;
  wire i___52_n_0;
  wire i___53_n_0;
  wire i___54_n_0;
  wire i___55_n_0;
  wire i___56_n_0;
  wire i___57_n_0;
  wire i___58_n_0;
  wire i___59_n_0;
  wire i___5_n_0;
  wire i___60_n_0;
  wire i___61_n_0;
  wire i___62_n_0;
  wire i___63_n_0;
  wire i___64_n_0;
  wire i___65_n_0;
  wire i___66_n_0;
  wire i___67_n_0;
  wire i___68_n_0;
  wire i___69_n_0;
  wire i___6_n_0;
  wire i___70_n_0;
  wire i___71_n_0;
  wire i___72_n_0;
  wire i___73_n_0;
  wire i___74_n_0;
  wire i___75_n_0;
  wire i___76_n_0;
  wire i___77_n_0;
  wire i___78_n_0;
  wire i___79_n_0;
  wire i___7_n_0;
  wire i___80_n_0;
  wire i___81_n_0;
  wire i___82_n_0;
  wire i___83_n_0;
  wire i___84_n_0;
  wire i___85_n_0;
  wire i___86_n_0;
  wire i___87_n_0;
  wire i___88_n_0;
  wire i___89_n_0;
  wire i___8_n_0;
  wire i___90_n_0;
  wire i___91_n_0;
  wire i___92_n_0;
  wire i___93_n_0;
  wire i___94_n_0;
  wire i___95_n_0;
  wire i___9_n_0;
  wire i__n_0;
  wire idle;
  wire [3:0]idle_r;
  wire [2:0]\inhbt_act_faw.faw_cnt_r ;
  wire \inhbt_act_faw.inhbt_act_faw_r_reg ;
  wire inhbt_act_faw_r;
  wire insert_maint_r1;
  wire \last_master_r_reg[2] ;
  wire \last_master_r_reg[2]_0 ;
  wire maint_ref_zq_wip;
  wire maint_req_r;
  wire maint_sre_r;
  wire maint_srx_r;
  wire maint_wip_r;
  wire maint_zq_r;
  wire [41:0]mc_address_ns;
  wire [8:0]mc_bank_ns;
  wire [2:0]mc_cas_n;
  wire [2:0]mc_cas_n_ns;
  wire [0:0]mc_cke;
  wire [1:1]mc_cke_ns;
  wire [1:0]mc_cmd;
  wire [1:1]mc_cmd_ns;
  wire [0:0]mc_cs_n;
  wire [0:0]mc_cs_n_ns;
  wire [3:3]mc_data_offset_1_ns;
  wire [3:3]mc_data_offset_2_ns;
  wire [3:3]mc_data_offset_ns;
  wire [0:0]mc_odt;
  wire [0:0]mc_odt_ns;
  wire [2:0]mc_ras_n;
  wire [2:0]mc_ras_n_ns;
  wire mc_ref_zq_wip;
  wire mc_ref_zq_wip_ns;
  wire [2:0]mc_we_n;
  wire [2:0]mc_we_n_ns;
  wire mc_wrdata_en;
  wire mc_wrdata_en_ns;
  wire mem_reg_0_15_36_41;
  wire mem_reg_0_15_42_47;
  wire [0:0]of_ctl_full_v;
  wire p_130_out;
  wire p_52_out;
  wire periodic_rd_ack_r;
  wire \periodic_rd_generation.periodic_rd_cntr1_r_reg ;
  wire \periodic_rd_generation.periodic_rd_timer_r_reg[2] ;
  wire periodic_rd_r;
  wire \periodic_read_request.periodic_rd_r_cnt_reg ;
  wire \periodic_read_request.periodic_rd_r_lcl_reg ;
  wire [6:0]phy_dout;
  wire phy_mc_ctl_full;
  wire phy_mc_data_full;
  wire \pointer_ram.pointer_we ;
  wire [1:0]q_entry_r;
  wire ram_init_done_r;
  wire \rank_cntrl[0].rank_cntrl0/act_this_rank ;
  wire \rank_cntrl[0].rank_cntrl0/inhbt_act_faw.act_delayed ;
  wire \rank_cntrl[0].rank_cntrl0/periodic_rd_generation.periodic_rd_cntr1_r ;
  wire \rank_cntrl[0].rank_cntrl0/periodic_rd_generation.periodic_rd_request_r ;
  wire \rank_cntrl[0].rank_cntrl0/periodic_rd_generation.read_this_rank ;
  wire \rank_cntrl[0].rank_cntrl0/periodic_rd_generation.read_this_rank_r ;
  wire \rank_cntrl[0].rank_cntrl0/refresh_generation.refresh_bank_r ;
  wire [1:0]\rank_cntrl[0].rank_cntrl0/rtw_timer.rtw_cnt_ns ;
  wire \rank_common0/app_ref_r ;
  wire \rank_common0/app_zq_r ;
  wire [4:0]\rank_common0/maint_prescaler.maint_prescaler_r_reg ;
  wire [2:0]\rank_common0/maintenance_request.maint_arb0/last_master_r ;
  wire [2:0]\rank_common0/maintenance_request.maint_grant_r ;
  wire \rank_common0/maintenance_request.new_maint_rank_r ;
  wire \rank_common0/maintenance_request.upd_last_master_r ;
  wire \rank_common0/periodic_read_request.periodic_rd_grant_r ;
  wire \rank_common0/periodic_read_request.periodic_rd_r_cnt ;
  wire \rank_common0/periodic_read_request.upd_last_master_r ;
  wire [1:0]\rank_common0/refresh_timer.refresh_timer_r_reg ;
  wire \rank_common0/sr_cntrl.sre_request_logic.sre_request_r ;
  wire \rank_common0/zq_cntrl.zq_request_logic.zq_request_r ;
  wire rank_mach0_n_29;
  wire rank_mach0_n_32;
  wire rank_mach0_n_40;
  wire rank_mach0_n_41;
  wire rank_mach0_n_42;
  wire rank_mach0_n_43;
  wire rank_mach0_n_44;
  wire rank_mach0_n_45;
  wire rank_mach0_n_46;
  wire rank_mach0_n_47;
  wire rank_mach0_n_48;
  wire rank_mach0_n_49;
  wire rank_mach0_n_50;
  wire rank_mach0_n_51;
  wire rank_mach0_n_52;
  wire rank_mach0_n_53;
  wire rank_mach0_n_54;
  wire rank_mach0_n_55;
  wire rank_mach0_n_56;
  wire rank_mach0_n_57;
  wire rank_mach0_n_58;
  wire rank_mach0_n_59;
  wire rank_mach0_n_63;
  wire rank_mach0_n_64;
  wire ras_timer_zero_r_reg;
  wire ras_timer_zero_r_reg_0;
  wire ras_timer_zero_r_reg_1;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[6] ;
  wire [3:0]rb_hit_busy_r;
  wire rb_hit_busy_r_reg;
  wire [3:1]rd_wr_r;
  wire [1:0]\read_fifo.fifo_out_data_r_reg[7] ;
  wire [2:1]\read_fifo.tail_r ;
  wire [0:0]\read_fifo.tail_r_reg[0] ;
  wire \read_fifo.tail_r_reg[0]_0 ;
  wire \read_fifo.tail_r_reg[2] ;
  wire [2:0]\req_bank_r_lcl_reg[2] ;
  wire [2:0]\req_bank_r_lcl_reg[2]_0 ;
  wire [2:0]\req_bank_r_lcl_reg[2]_1 ;
  wire [2:0]\req_bank_r_lcl_reg[2]_2 ;
  wire [2:0]\req_bank_r_lcl_reg[2]_3 ;
  wire [9:0]\req_col_r_reg[9] ;
  wire [3:0]\req_data_buf_addr_r_reg[3] ;
  wire [19:0]\req_row_r_lcl_reg[13] ;
  wire [3:1]req_wr_r;
  wire [0:0]\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_ns ;
  wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] ;
  wire rnk_config_valid_r;
  wire [3:0]row_cmd_wr;
  wire [0:0]row_hit_r_reg;
  wire [0:0]row_hit_r_reg_0;
  wire [0:0]row_hit_r_reg_1;
  wire [0:0]row_hit_r_reg_2;
  wire [0:0]row_hit_r_reg_3;
  wire \rtp_timer_r_reg[0] ;
  wire \rtp_timer_r_reg[1] ;
  wire [1:0]\rtw_timer.rtw_cnt_r ;
  wire [3:0]sending_col;
  wire [3:3]sending_pre;
  wire [3:0]sending_row;
  wire sent_col;
  wire sent_col_r2;
  wire sent_row;
  wire use_addr;
  wire was_priority_reg;
  wire was_wr;
  wire [3:0]wr_data_addr;
  wire [3:0]wr_data_addr_ns;
  wire wr_data_en;
  wire wr_data_en_ns;
  wire [1:0]\wtr_timer.wtr_cnt_r ;
  wire \zq_cntrl.zq_request_logic.zq_request_r_reg ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_0 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_1 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_2 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_3 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_4 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_5 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_6 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_7 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_0 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_1 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_2 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_3 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_4 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_5 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_6 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_7 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_1 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_2 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_3 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_4 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_5 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_6 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_7 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_0 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_1 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_2 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_3 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_4 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_5 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_6 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_7 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_0 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_1 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_2 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_3 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_4 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_5 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_6 ;
  wire \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_7 ;
  wire [3:3]\NLW_zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_CO_UNCONNECTED ;

  mig_mig_7series_v4_2_bank_mach bank_mach0
       (.D(mc_data_offset_2_ns),
        .DIC(col_periodic_rd),
        .E(mc_cmd_ns),
        .Q(sending_col),
        .S(S),
        .SR(SR),
        .accept_internal_r(accept_internal_r),
        .accept_internal_r_reg(\grant_r_reg[0] ),
        .accept_ns(accept_ns),
        .accept_r_reg(bank_mach0_n_10),
        .act_this_rank(\rank_cntrl[0].rank_cntrl0/act_this_rank ),
        .act_wait_r_lcl_reg(bank_mach0_n_257),
        .act_wait_r_lcl_reg_0(bank_mach0_n_263),
        .act_wait_r_lcl_reg_1(bank_mach0_n_266),
        .act_wait_r_lcl_reg_2(i___27_n_0),
        .auto_pre_r(\bank_cntrl[0].bank0/auto_pre_r ),
        .auto_pre_r_19(\bank_cntrl[1].bank0/auto_pre_r ),
        .auto_pre_r_20(\bank_cntrl[2].bank0/auto_pre_r ),
        .auto_pre_r_21(\bank_cntrl[3].bank0/auto_pre_r ),
        .auto_pre_r_lcl_reg(i___55_n_0),
        .auto_pre_r_lcl_reg_0(i___61_n_0),
        .auto_pre_r_lcl_reg_1(i___62_n_0),
        .auto_pre_r_lcl_reg_2(i___63_n_0),
        .auto_pre_r_lcl_reg_3(i___64_n_0),
        .bm_end_r1(bm_end_r1),
        .bm_end_r1_0(bm_end_r1_0),
        .bm_end_r1_1(bm_end_r1_1),
        .cke_r(\arb_mux0/arb_select0/cke_r ),
        .cke_r_reg(\periodic_read_request.periodic_rd_r_cnt_reg ),
        .clear_periodic_rd_request(clear_periodic_rd_request),
        .cmd(cmd),
        .\cmd_pipe_plus.mc_address_reg[0] (i___68_n_0),
        .\cmd_pipe_plus.mc_address_reg[0]_0 (i___67_n_0),
        .\cmd_pipe_plus.mc_address_reg[3] (i___69_n_0),
        .\cmd_pipe_plus.mc_data_offset_1_reg[5] (\cmd_pipe_plus.mc_data_offset_1_reg[5]_1 ),
        .\cmd_pipe_plus.mc_data_offset_2_reg[5] (\cmd_pipe_plus.mc_data_offset_2_reg[5]_1 ),
        .\cmd_pipe_plus.mc_data_offset_reg[5] (\cmd_pipe_plus.mc_data_offset_reg[5]_1 ),
        .\cmd_pipe_plus.mc_odt_reg[0] (\cmd_pipe_plus.mc_aux_out0_reg_n_0_[1] ),
        .\cmd_pipe_plus.mc_we_n_reg[0] (i___66_n_0),
        .col_rd_wr(col_rd_wr),
        .col_wait_r(\bank_cntrl[0].bank0/bank_state0/col_wait_r ),
        .col_wait_r_0(\bank_cntrl[1].bank0/bank_state0/col_wait_r ),
        .col_wait_r_4(\bank_cntrl[2].bank0/bank_state0/col_wait_r ),
        .col_wait_r_8(\bank_cntrl[3].bank0/bank_state0/col_wait_r ),
        .col_wait_r_reg(i___26_n_0),
        .col_wait_r_reg_0(i___49_n_0),
        .col_wait_r_reg_1(i___30_n_0),
        .col_wait_r_reg_2(i___25_n_0),
        .col_wr_data_buf_addr(col_wr_data_buf_addr),
        .\compute_tail.tail_r_lcl_reg (bank_mach0_n_258),
        .\compute_tail.tail_r_lcl_reg_0 (bank_mach0_n_259),
        .\compute_tail.tail_r_lcl_reg_1 (bank_mach0_n_261),
        .\compute_tail.tail_r_lcl_reg_2 (bank_mach0_n_262),
        .\compute_tail.tail_r_lcl_reg_3 (i___2_n_0),
        .\compute_tail.tail_r_lcl_reg_4 (i___7_n_0),
        .\compute_tail.tail_r_lcl_reg_5 (i___8_n_0),
        .\compute_tail.tail_r_lcl_reg_6 (i___9_n_0),
        .cs_en2(\arb_mux0/cs_en2 ),
        .\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] (wr_data_addr_ns),
        .demand_priority_r(\bank_cntrl[0].bank0/bank_state0/demand_priority_r ),
        .demand_priority_r_1(\bank_cntrl[1].bank0/bank_state0/demand_priority_r ),
        .demand_priority_r_5(\bank_cntrl[2].bank0/bank_state0/demand_priority_r ),
        .demand_priority_r_9(\bank_cntrl[3].bank0/bank_state0/demand_priority_r ),
        .demand_priority_r_reg(bank_mach0_n_150),
        .demanded_prior_r(\bank_cntrl[0].bank0/bank_state0/demanded_prior_r ),
        .demanded_prior_r_2(\bank_cntrl[1].bank0/bank_state0/demanded_prior_r ),
        .demanded_prior_r_6(\bank_cntrl[2].bank0/bank_state0/demanded_prior_r ),
        .demanded_prior_r_reg(bank_mach0_n_265),
        .demanded_prior_r_reg_0(bank_mach0_n_277),
        .\generate_maint_cmds.insert_maint_r_lcl_reg (\generate_maint_cmds.insert_maint_r_lcl_reg ),
        .\grant_r[2]_i_3 (\wtr_timer.wtr_cnt_r [1]),
        .\grant_r_reg[0] (bank_mach0_n_113),
        .\grant_r_reg[0]_0 (bank_mach0_n_267),
        .\grant_r_reg[0]_1 (bank_mach0_n_274),
        .\grant_r_reg[0]_2 (bank_mach0_n_278),
        .\grant_r_reg[1] (bank_mach0_n_264),
        .\grant_r_reg[2] (bank_mach0_n_92),
        .\grant_r_reg[3] (sending_row),
        .\grant_r_reg[3]_0 (sending_pre),
        .\grant_r_reg[3]_1 (i___74_n_0),
        .\grant_r_reg[3]_2 (i___73_n_0),
        .\grant_r_reg[3]_3 (i___75_n_0),
        .granted_col_r_reg(bank_mach0_n_91),
        .granted_col_r_reg_0(mc_data_offset_1_ns),
        .granted_col_r_reg_1(mc_data_offset_ns),
        .granted_col_r_reg_2(i___84_n_0),
        .granted_col_r_reg_3(i___29_n_0),
        .granted_col_r_reg_4(i___86_n_0),
        .granted_col_r_reg_5(i___85_n_0),
        .granted_col_r_reg_6(i___28_n_0),
        .granted_row_r_reg(i___70_n_0),
        .head_r(head_r),
        .head_r_lcl_reg(i___3_n_0),
        .head_r_lcl_reg_0(i___4_n_0),
        .head_r_lcl_reg_1(i___5_n_0),
        .head_r_lcl_reg_2(i___6_n_0),
        .idle_r(idle_r),
        .idle_r_lcl_reg(bank_mach0_n_93),
        .idle_r_lcl_reg_0(bank_mach0_n_94),
        .idle_r_lcl_reg_1(bank_mach0_n_96),
        .idle_r_lcl_reg_2(bank_mach0_n_98),
        .idle_r_lcl_reg_3(bank_mach0_n_143),
        .idle_r_lcl_reg_4(bank_mach0_n_147),
        .idle_r_lcl_reg_5(bank_mach0_n_260),
        .inhbt_act_faw_r(inhbt_act_faw_r),
        .insert_maint_r1(insert_maint_r1),
        .\last_master_r_reg[3] (\arb_mux0/arb_row_col0/pre_4_1_1T_arb.pre_arb0/last_master_r ),
        .\maint_controller.maint_hit_busies_r_reg[3] (\bank_common0/maint_controller.maint_hit_busies_r ),
        .\maint_controller.maint_hit_busies_r_reg[3]_0 ({i___44_n_0,i___46_n_0,i___35_n_0,i___48_n_0}),
        .\maint_controller.maint_wip_r_lcl_reg (\last_master_r_reg[2] ),
        .\maint_controller.maint_wip_r_lcl_reg_0 (i___65_n_0),
        .\maint_controller.maint_wip_r_lcl_reg_1 (i___82_n_0),
        .maint_req_r(maint_req_r),
        .maint_srx_r(maint_srx_r),
        .maint_wip_r(maint_wip_r),
        .maint_zq_r(maint_zq_r),
        .mc_cas_n_ns(mc_cas_n_ns),
        .mc_cke_ns(mc_cke_ns),
        .mc_cs_n_ns(mc_cs_n_ns),
        .mc_odt_ns(mc_odt_ns),
        .mc_ras_n_ns({mc_ras_n_ns[2],mc_ras_n_ns[0]}),
        .mc_we_n_ns({mc_we_n_ns[2],mc_we_n_ns[0]}),
        .of_ctl_full_v(of_ctl_full_v),
        .ofs_rdy_r_reg(\zq_cntrl.zq_request_logic.zq_request_r_reg ),
        .\order_q_r_reg[1] (bank_mach0_n_152),
        .override_demand_ns(\bank_cntrl[2].bank0/bank_state0/override_demand_ns ),
        .override_demand_r(\bank_cntrl[2].bank0/bank_state0/override_demand_r ),
        .p_130_out(p_130_out),
        .p_52_out(p_52_out),
        .pass_open_bank_r(\bank_cntrl[1].bank0/pass_open_bank_r ),
        .pass_open_bank_r_10(\bank_cntrl[3].bank0/pass_open_bank_r ),
        .pass_open_bank_r_lcl_reg(bank_mach0_n_58),
        .pass_open_bank_r_lcl_reg_0(bank_mach0_n_59),
        .pass_open_bank_r_lcl_reg_1(i___72_n_0),
        .pass_open_bank_r_lcl_reg_2(i___71_n_0),
        .periodic_rd_ack_r(periodic_rd_ack_r),
        .periodic_rd_ack_r_lcl_reg(bank_mach0_n_133),
        .periodic_rd_cntr_r(\bank_common0/periodic_rd_cntr_r ),
        .periodic_rd_cntr_r_reg(\periodic_rd_generation.periodic_rd_cntr1_r_reg ),
        .periodic_rd_cntr_r_reg_0(i___58_n_0),
        .\periodic_rd_generation.read_this_rank (\rank_cntrl[0].rank_cntrl0/periodic_rd_generation.read_this_rank ),
        .\periodic_rd_generation.read_this_rank_r (\rank_cntrl[0].rank_cntrl0/periodic_rd_generation.read_this_rank_r ),
        .\periodic_rd_generation.read_this_rank_r_reg (bank_mach0_n_104),
        .periodic_rd_r(periodic_rd_r),
        .\periodic_read_request.periodic_rd_grant_r (\rank_common0/periodic_read_request.periodic_rd_grant_r ),
        .phy_mc_ctl_full(phy_mc_ctl_full),
        .phy_mc_data_full(phy_mc_data_full),
        .\pre_4_1_1T_arb.granted_pre_r_reg (mc_bank_ns),
        .\pre_4_1_1T_arb.granted_pre_r_reg_0 ({mc_address_ns[41:28],mc_address_ns[24:0]}),
        .pre_bm_end_r(\bank_cntrl[1].bank0/bank_queue0/pre_bm_end_r ),
        .pre_bm_end_r_11(\bank_cntrl[3].bank0/bank_queue0/pre_bm_end_r ),
        .pre_bm_end_r_reg(bank_mach0_n_117),
        .pre_bm_end_r_reg_0(bank_mach0_n_128),
        .pre_bm_end_r_reg_1(bank_mach0_n_129),
        .pre_bm_end_r_reg_2(bank_mach0_n_149),
        .pre_passing_open_bank_r_reg(bank_mach0_n_122),
        .pre_passing_open_bank_r_reg_0(bank_mach0_n_125),
        .q_entry_r(q_entry_r),
        .\q_entry_r_reg[0] (bank_mach0_n_132),
        .\q_entry_r_reg[0]_0 (bank_mach0_n_138),
        .\q_entry_r_reg[0]_1 (bank_mach0_n_141),
        .\q_entry_r_reg[0]_2 (bank_mach0_n_142),
        .\q_entry_r_reg[0]_3 (bank_mach0_n_144),
        .\q_entry_r_reg[0]_4 (bank_mach0_n_155),
        .\q_entry_r_reg[0]_5 (bank_mach0_n_156),
        .\q_entry_r_reg[0]_6 (i___33_n_0),
        .\q_entry_r_reg[1] (bank_mach0_n_131),
        .\q_entry_r_reg[1]_0 (bank_mach0_n_140),
        .\q_entry_r_reg[1]_1 (bank_mach0_n_157),
        .\q_entry_r_reg[1]_2 (i___38_n_0),
        .\q_entry_r_reg[1]_3 (i___34_n_0),
        .\q_entry_r_reg[1]_4 (i___39_n_0),
        .q_has_rd(\bank_cntrl[0].bank0/q_has_rd ),
        .q_has_rd_12(\bank_cntrl[3].bank0/q_has_rd ),
        .q_has_rd_3(\bank_cntrl[1].bank0/q_has_rd ),
        .q_has_rd_7(\bank_cntrl[2].bank0/q_has_rd ),
        .q_has_rd_r_reg(i___51_n_0),
        .q_has_rd_r_reg_0(i___36_n_0),
        .q_has_rd_r_reg_1(i___52_n_0),
        .q_has_rd_r_reg_2(i___54_n_0),
        .\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] ({\arb_mux0/arb_select0/mc_data_offset1 [5:4],\arb_mux0/arb_select0/mc_data_offset1 [2:1]}),
        .\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] ({\arb_mux0/arb_select0/mc_data_offset_11 [5:4],\arb_mux0/arb_select0/mc_data_offset_11 [2:1]}),
        .\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17] ({\arb_mux0/arb_select0/mc_data_offset_21 [5:4],\arb_mux0/arb_select0/mc_data_offset_21 [2:1]}),
        .\ras_timer_r_reg[0] (i___89_n_0),
        .\ras_timer_r_reg[0]_0 (i___88_n_0),
        .\ras_timer_r_reg[0]_1 (i___87_n_0),
        .\ras_timer_r_reg[0]_2 (i___90_n_0),
        .ras_timer_zero_r_reg(ras_timer_zero_r_reg),
        .ras_timer_zero_r_reg_0(ras_timer_zero_r_reg_0),
        .ras_timer_zero_r_reg_1(ras_timer_zero_r_reg_1),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[1] (\bank_cntrl[0].bank0/rb_hit_busies_r ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[2] (bank_mach0_n_123),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_0 (bank_mach0_n_154),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_1 (bank_mach0_n_158),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[2]_2 (bank_mach0_n_160),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[3] (bank_mach0_n_124),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_0 (bank_mach0_n_126),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[3]_1 (bank_mach0_n_163),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] (\bank_cntrl[2].bank0/rb_hit_busies_r ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_0 (bank_mach0_n_137),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[4]_1 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] (bank_mach0_n_127),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_0 (i___37_n_0),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[5]_1 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[6] (bank_mach0_n_116),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[6]_0 (\rb_hit_busies.rb_hit_busies_r_lcl_reg[6] ),
        .rb_hit_busy_r(rb_hit_busy_r),
        .rb_hit_busy_r_reg(bank_mach0_n_135),
        .rb_hit_busy_r_reg_0(bank_mach0_n_161),
        .rb_hit_busy_r_reg_1(rb_hit_busy_r_reg),
        .rd_wr_r_lcl_reg(rd_wr_r),
        .rd_wr_r_lcl_reg_0(i___59_n_0),
        .\req_bank_r_lcl_reg[2] (\req_bank_r_lcl_reg[2] ),
        .\req_bank_r_lcl_reg[2]_0 (\req_bank_r_lcl_reg[2]_0 ),
        .\req_bank_r_lcl_reg[2]_1 (\req_bank_r_lcl_reg[2]_1 ),
        .\req_bank_r_lcl_reg[2]_2 (\req_bank_r_lcl_reg[2]_2 ),
        .\req_bank_r_lcl_reg[2]_3 (\req_bank_r_lcl_reg[2]_3 ),
        .req_bank_rdy_ns(\bank_cntrl[1].bank0/bank_state0/req_bank_rdy_ns ),
        .req_bank_rdy_r_reg(i___41_n_0),
        .req_bank_rdy_r_reg_0(i___53_n_0),
        .req_bank_rdy_r_reg_1(i___56_n_0),
        .\req_col_r_reg[9] (\req_col_r_reg[9] ),
        .\req_data_buf_addr_r_reg[3] (\req_data_buf_addr_r_reg[3] ),
        .\req_row_r_lcl_reg[13] (\req_row_r_lcl_reg[13] ),
        .\req_row_r_lcl_reg[13]_0 (D),
        .req_wr_r_lcl_reg(req_wr_r),
        .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] (\inhbt_act_faw.inhbt_act_faw_r_reg ),
        .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[1] (\last_master_r_reg[2]_0 ),
        .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] (\bank_common0/rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r ),
        .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_0 (rank_mach0_n_63),
        .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3]_1 (\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] ),
        .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4] (bank_mach0_n_275),
        .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[4]_0 (i___83_n_0),
        .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7] (bank_mach0_n_276),
        .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[7]_0 ({i___60_n_0,\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_ns }),
        .rnk_config_valid_r(rnk_config_valid_r),
        .rnk_config_valid_r_lcl_reg(bank_mach0_n_151),
        .rnk_config_valid_r_lcl_reg_0(i___40_n_0),
        .row_cmd_wr(row_cmd_wr),
        .row_hit_r_reg(bank_mach0_n_136),
        .row_hit_r_reg_0(bank_mach0_n_159),
        .row_hit_r_reg_1(bank_mach0_n_162),
        .row_hit_r_reg_2(bank_mach0_n_164),
        .row_hit_r_reg_3(row_hit_r_reg),
        .row_hit_r_reg_4(row_hit_r_reg_0),
        .row_hit_r_reg_5(row_hit_r_reg_1),
        .row_hit_r_reg_6(row_hit_r_reg_2),
        .row_hit_r_reg_7(row_hit_r_reg_3),
        .\rtp_timer_r_reg[0] (\rtp_timer_r_reg[0] ),
        .\rtp_timer_r_reg[1] (\rtp_timer_r_reg[1] ),
        .\rtw_timer.rtw_cnt_r_reg[1] (\rank_cntrl[0].rank_cntrl0/rtw_timer.rtw_cnt_ns ),
        .\rtw_timer.rtw_cnt_r_reg[1]_0 (\rtw_timer.rtw_cnt_r ),
        .sent_col(sent_col),
        .sent_row(sent_row),
        .set_order_q(\bank_cntrl[3].bank0/bank_queue0/set_order_q ),
        .set_order_q_22(\bank_cntrl[2].bank0/bank_queue0/set_order_q ),
        .set_order_q_23(\bank_cntrl[0].bank0/bank_queue0/set_order_q ),
        .set_order_q_24(\bank_cntrl[1].bank0/bank_queue0/set_order_q ),
        .tail_r(\bank_cntrl[0].bank0/tail_r ),
        .tail_r_16(\bank_cntrl[1].bank0/tail_r ),
        .tail_r_17(\bank_cntrl[2].bank0/tail_r ),
        .tail_r_18(\bank_cntrl[3].bank0/tail_r ),
        .use_addr(use_addr),
        .wait_for_maint_r(\bank_cntrl[0].bank0/wait_for_maint_r ),
        .wait_for_maint_r_13(\bank_cntrl[1].bank0/wait_for_maint_r ),
        .wait_for_maint_r_14(\bank_cntrl[2].bank0/wait_for_maint_r ),
        .wait_for_maint_r_15(\bank_cntrl[3].bank0/wait_for_maint_r ),
        .wait_for_maint_r_lcl_reg(i___47_n_0),
        .wait_for_maint_r_lcl_reg_0(i___42_n_0),
        .wait_for_maint_r_lcl_reg_1(i___45_n_0),
        .wait_for_maint_r_lcl_reg_2(i___43_n_0),
        .was_priority_reg(was_priority_reg),
        .was_wr(was_wr),
        .\wr_this_rank_r_reg[0] (bank_mach0_n_114),
        .\wr_this_rank_r_reg[0]_0 (bank_mach0_n_115));
  FDRE \cmd_pipe_plus.mc_address_reg[0] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(mc_address_ns[0]),
        .Q(Q[0]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[10] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(mc_address_ns[10]),
        .Q(Q[10]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[11] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(mc_address_ns[11]),
        .Q(Q[11]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[12] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(mc_address_ns[12]),
        .Q(Q[12]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[13] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(mc_address_ns[13]),
        .Q(Q[13]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[14] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(mc_address_ns[14]),
        .Q(Q[14]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[15] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(mc_address_ns[15]),
        .Q(Q[15]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[16] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(mc_address_ns[16]),
        .Q(Q[16]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[17] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(mc_address_ns[17]),
        .Q(Q[17]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[18] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(mc_address_ns[18]),
        .Q(Q[18]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[19] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(mc_address_ns[19]),
        .Q(Q[19]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[1] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(mc_address_ns[1]),
        .Q(Q[1]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[20] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(mc_address_ns[20]),
        .Q(Q[20]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[21] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(mc_address_ns[21]),
        .Q(Q[21]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[22] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(mc_address_ns[22]),
        .Q(Q[22]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[23] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(mc_address_ns[23]),
        .Q(Q[23]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[24] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(mc_address_ns[24]),
        .Q(Q[24]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[28] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(mc_address_ns[28]),
        .Q(Q[25]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[29] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(mc_address_ns[29]),
        .Q(Q[26]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[2] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(mc_address_ns[2]),
        .Q(Q[2]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[30] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(mc_address_ns[30]),
        .Q(Q[27]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[31] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(mc_address_ns[31]),
        .Q(Q[28]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[32] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(mc_address_ns[32]),
        .Q(Q[29]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[33] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(mc_address_ns[33]),
        .Q(Q[30]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[34] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(mc_address_ns[34]),
        .Q(Q[31]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[35] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(mc_address_ns[35]),
        .Q(Q[32]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[36] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(mc_address_ns[36]),
        .Q(Q[33]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[37] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(mc_address_ns[37]),
        .Q(Q[34]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[38] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(mc_address_ns[38]),
        .Q(Q[35]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[39] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(mc_address_ns[39]),
        .Q(Q[36]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[3] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(mc_address_ns[3]),
        .Q(Q[3]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[40] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(mc_address_ns[40]),
        .Q(Q[37]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[41] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(mc_address_ns[41]),
        .Q(Q[38]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[4] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(mc_address_ns[4]),
        .Q(Q[4]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[5] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(mc_address_ns[5]),
        .Q(Q[5]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[6] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(mc_address_ns[6]),
        .Q(Q[6]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[7] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(mc_address_ns[7]),
        .Q(Q[7]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[8] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(mc_address_ns[8]),
        .Q(Q[8]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_address_reg[9] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(mc_address_ns[9]),
        .Q(Q[9]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_aux_out0_reg[1] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(i___22_n_0),
        .Q(\cmd_pipe_plus.mc_aux_out0_reg_n_0_[1] ),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_bank_reg[0] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(mc_bank_ns[0]),
        .Q(\cmd_pipe_plus.mc_bank_reg[8]_0 [0]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_bank_reg[1] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(mc_bank_ns[1]),
        .Q(\cmd_pipe_plus.mc_bank_reg[8]_0 [1]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_bank_reg[2] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(mc_bank_ns[2]),
        .Q(\cmd_pipe_plus.mc_bank_reg[8]_0 [2]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_bank_reg[3] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(mc_bank_ns[3]),
        .Q(\cmd_pipe_plus.mc_bank_reg[8]_0 [3]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_bank_reg[4] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(mc_bank_ns[4]),
        .Q(\cmd_pipe_plus.mc_bank_reg[8]_0 [4]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_bank_reg[5] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(mc_bank_ns[5]),
        .Q(\cmd_pipe_plus.mc_bank_reg[8]_0 [5]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_bank_reg[6] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(mc_bank_ns[6]),
        .Q(\cmd_pipe_plus.mc_bank_reg[8]_0 [6]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_bank_reg[7] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(mc_bank_ns[7]),
        .Q(\cmd_pipe_plus.mc_bank_reg[8]_0 [7]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_bank_reg[8] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(mc_bank_ns[8]),
        .Q(\cmd_pipe_plus.mc_bank_reg[8]_0 [8]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_cas_n_reg[0] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(mc_cas_n_ns[0]),
        .Q(mc_cas_n[0]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_cas_n_reg[1] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(mc_cas_n_ns[1]),
        .Q(mc_cas_n[1]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_cas_n_reg[2] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(mc_cas_n_ns[2]),
        .Q(mc_cas_n[2]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_cke_reg[3] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(mc_cke_ns),
        .Q(mc_cke),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_cmd_reg[0] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(sent_col),
        .Q(mc_cmd[0]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_cmd_reg[1] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(mc_cmd_ns),
        .Q(mc_cmd[1]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_cs_n_reg[0] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(mc_cs_n_ns),
        .Q(mc_cs_n),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_data_offset_1_reg[0] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(\cmd_pipe_plus.mc_data_offset_1_reg[0]_1 ),
        .Q(\cmd_pipe_plus.mc_data_offset_1_reg[0]_0 ),
        .R(bank_mach0_n_91));
  FDRE \cmd_pipe_plus.mc_data_offset_1_reg[1] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(\arb_mux0/arb_select0/mc_data_offset_11 [1]),
        .Q(\cmd_pipe_plus.mc_data_offset_1_reg[1]_0 ),
        .R(bank_mach0_n_91));
  FDRE \cmd_pipe_plus.mc_data_offset_1_reg[2] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(\arb_mux0/arb_select0/mc_data_offset_11 [2]),
        .Q(\cmd_pipe_plus.mc_data_offset_1_reg[2]_0 ),
        .R(bank_mach0_n_91));
  FDRE \cmd_pipe_plus.mc_data_offset_1_reg[3] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(mc_data_offset_1_ns),
        .Q(\cmd_pipe_plus.mc_data_offset_1_reg[3]_0 ),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_data_offset_1_reg[4] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(\arb_mux0/arb_select0/mc_data_offset_11 [4]),
        .Q(\cmd_pipe_plus.mc_data_offset_1_reg[4]_0 ),
        .R(bank_mach0_n_91));
  FDRE \cmd_pipe_plus.mc_data_offset_1_reg[5] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(\arb_mux0/arb_select0/mc_data_offset_11 [5]),
        .Q(\cmd_pipe_plus.mc_data_offset_1_reg[5]_0 ),
        .R(bank_mach0_n_91));
  FDRE \cmd_pipe_plus.mc_data_offset_2_reg[0] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(\cmd_pipe_plus.mc_data_offset_2_reg[0]_1 ),
        .Q(\cmd_pipe_plus.mc_data_offset_2_reg[0]_0 ),
        .R(bank_mach0_n_91));
  FDRE \cmd_pipe_plus.mc_data_offset_2_reg[1] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(\arb_mux0/arb_select0/mc_data_offset_21 [1]),
        .Q(\cmd_pipe_plus.mc_data_offset_2_reg[1]_0 ),
        .R(bank_mach0_n_91));
  FDRE \cmd_pipe_plus.mc_data_offset_2_reg[2] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(\arb_mux0/arb_select0/mc_data_offset_21 [2]),
        .Q(\cmd_pipe_plus.mc_data_offset_2_reg[2]_0 ),
        .R(bank_mach0_n_91));
  FDRE \cmd_pipe_plus.mc_data_offset_2_reg[3] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(mc_data_offset_2_ns),
        .Q(\cmd_pipe_plus.mc_data_offset_2_reg[3]_0 ),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_data_offset_2_reg[4] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(\arb_mux0/arb_select0/mc_data_offset_21 [4]),
        .Q(\cmd_pipe_plus.mc_data_offset_2_reg[4]_0 ),
        .R(bank_mach0_n_91));
  FDRE \cmd_pipe_plus.mc_data_offset_2_reg[5] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(\arb_mux0/arb_select0/mc_data_offset_21 [5]),
        .Q(\cmd_pipe_plus.mc_data_offset_2_reg[5]_0 ),
        .R(bank_mach0_n_91));
  FDRE \cmd_pipe_plus.mc_data_offset_reg[0] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(\cmd_pipe_plus.mc_data_offset_reg[0]_1 ),
        .Q(\cmd_pipe_plus.mc_data_offset_reg[0]_0 ),
        .R(bank_mach0_n_91));
  FDRE \cmd_pipe_plus.mc_data_offset_reg[1] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(\arb_mux0/arb_select0/mc_data_offset1 [1]),
        .Q(\cmd_pipe_plus.mc_data_offset_reg[1]_0 ),
        .R(bank_mach0_n_91));
  FDRE \cmd_pipe_plus.mc_data_offset_reg[2] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(\arb_mux0/arb_select0/mc_data_offset1 [2]),
        .Q(\cmd_pipe_plus.mc_data_offset_reg[2]_0 ),
        .R(bank_mach0_n_91));
  FDRE \cmd_pipe_plus.mc_data_offset_reg[3] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(mc_data_offset_ns),
        .Q(\cmd_pipe_plus.mc_data_offset_reg[3]_0 ),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_data_offset_reg[4] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(\arb_mux0/arb_select0/mc_data_offset1 [4]),
        .Q(\cmd_pipe_plus.mc_data_offset_reg[4]_0 ),
        .R(bank_mach0_n_91));
  FDRE \cmd_pipe_plus.mc_data_offset_reg[5] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(\arb_mux0/arb_select0/mc_data_offset1 [5]),
        .Q(\cmd_pipe_plus.mc_data_offset_reg[5]_0 ),
        .R(bank_mach0_n_91));
  FDRE \cmd_pipe_plus.mc_odt_reg[0] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(mc_odt_ns),
        .Q(mc_odt),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_ras_n_reg[0] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(mc_ras_n_ns[0]),
        .Q(mc_ras_n[0]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_ras_n_reg[1] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(i___23_n_0),
        .Q(mc_ras_n[1]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_ras_n_reg[2] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(mc_ras_n_ns[2]),
        .Q(mc_ras_n[2]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_we_n_reg[0] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(mc_we_n_ns[0]),
        .Q(mc_we_n[0]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_we_n_reg[1] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(bank_mach0_n_278),
        .Q(mc_we_n[1]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_we_n_reg[2] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(mc_we_n_ns[2]),
        .Q(mc_we_n[2]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.mc_wrdata_en_reg 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(mc_wrdata_en_ns),
        .Q(mc_wrdata_en),
        .R(1'b0));
  (* syn_maxfan = "30" *) 
  FDRE \cmd_pipe_plus.wr_data_addr_reg[0] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(wr_data_addr_ns[0]),
        .Q(wr_data_addr[0]),
        .R(1'b0));
  (* syn_maxfan = "30" *) 
  FDRE \cmd_pipe_plus.wr_data_addr_reg[1] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(wr_data_addr_ns[1]),
        .Q(wr_data_addr[1]),
        .R(1'b0));
  (* syn_maxfan = "30" *) 
  FDRE \cmd_pipe_plus.wr_data_addr_reg[2] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(wr_data_addr_ns[2]),
        .Q(wr_data_addr[2]),
        .R(1'b0));
  (* syn_maxfan = "30" *) 
  FDRE \cmd_pipe_plus.wr_data_addr_reg[3] 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(wr_data_addr_ns[3]),
        .Q(wr_data_addr[3]),
        .R(1'b0));
  FDRE \cmd_pipe_plus.wr_data_en_reg 
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(wr_data_en_ns),
        .Q(wr_data_en),
        .R(1'b0));
  mig_mig_7series_v4_2_col_mach col_mach0
       (.ADDRA({i___92_n_0,i___91_n_0,i___93_n_0}),
        .D(wr_data_addr_ns),
        .DIC(col_periodic_rd),
        .E(mc_cmd_ns),
        .col_rd_wr(col_rd_wr),
        .col_rd_wr_r1(col_rd_wr_r1),
        .col_rd_wr_r2(col_rd_wr_r2),
        .col_wr_data_buf_addr(col_wr_data_buf_addr),
        .maint_ref_zq_wip(maint_ref_zq_wip),
        .mc_cmd(mc_cmd[0]),
        .mc_ref_zq_wip_ns(mc_ref_zq_wip_ns),
        .\read_fifo.fifo_out_data_r_reg[7]_0 (\read_fifo.fifo_out_data_r_reg[7] ),
        .\read_fifo.fifo_out_data_r_reg[7]_1 (\inhbt_act_faw.inhbt_act_faw_r_reg ),
        .\read_fifo.head_r_reg[0]_0 (\periodic_rd_generation.periodic_rd_cntr1_r_reg ),
        .\read_fifo.head_r_reg[4]_0 (\last_master_r_reg[2] ),
        .\read_fifo.tail_r_reg[0]_0 (\read_fifo.tail_r_reg[0] ),
        .\read_fifo.tail_r_reg[0]_1 (\read_fifo.tail_r_reg[0]_0 ),
        .\read_fifo.tail_r_reg[1]_0 (\zq_cntrl.zq_request_logic.zq_request_r_reg ),
        .\read_fifo.tail_r_reg[2]_0 (\read_fifo.tail_r ),
        .\read_fifo.tail_r_reg[2]_1 (\read_fifo.tail_r_reg[2] ),
        .\read_fifo.tail_r_reg[4]_0 (col_mach0_n_7),
        .\read_fifo.tail_r_reg[4]_1 (col_mach0_n_12),
        .sent_col_r2(sent_col_r2));
  LUT5 #(
    .INIT(32'hFFFF0008)) 
    i_
       (.I0(\rank_cntrl[0].rank_cntrl0/periodic_rd_generation.periodic_rd_request_r ),
        .I1(\grant_r_reg[0] ),
        .I2(\rank_common0/periodic_read_request.upd_last_master_r ),
        .I3(periodic_rd_r),
        .I4(\rank_common0/periodic_read_request.periodic_rd_grant_r ),
        .O(i__n_0));
  LUT4 #(
    .INIT(16'h2F20)) 
    i___0
       (.I0(maint_sre_r),
        .I1(maint_srx_r),
        .I2(insert_maint_r1),
        .I3(app_sr_active),
        .O(i___0_n_0));
  LUT6 #(
    .INIT(64'hFFFFC400C400C400)) 
    i___1
       (.I0(\rank_cntrl[0].rank_cntrl0/refresh_generation.refresh_bank_r ),
        .I1(\grant_r_reg[0] ),
        .I2(\rank_common0/zq_cntrl.zq_request_logic.zq_request_r ),
        .I3(insert_maint_r1),
        .I4(maint_wip_r),
        .I5(maint_ref_zq_wip),
        .O(i___1_n_0));
  LUT2 #(
    .INIT(4'h2)) 
    i___10
       (.I0(sent_col_r2),
        .I1(col_rd_wr_r2),
        .O(mc_wrdata_en_ns));
  LUT2 #(
    .INIT(4'h2)) 
    i___11
       (.I0(mc_cmd[0]),
        .I1(col_rd_wr_r1),
        .O(wr_data_en_ns));
  LUT6 #(
    .INIT(64'h00000004FFFFFFFF)) 
    i___12
       (.I0(\rank_common0/maint_prescaler.maint_prescaler_r_reg [2]),
        .I1(\rank_common0/maint_prescaler.maint_prescaler_r_reg [0]),
        .I2(\rank_common0/maint_prescaler.maint_prescaler_r_reg [1]),
        .I3(\rank_common0/maint_prescaler.maint_prescaler_r_reg [3]),
        .I4(\rank_common0/maint_prescaler.maint_prescaler_r_reg [4]),
        .I5(\grant_r_reg[0] ),
        .O(i___12_n_0));
  LUT2 #(
    .INIT(4'hB)) 
    i___13
       (.I0(rank_mach0_n_29),
        .I1(\grant_r_reg[0] ),
        .O(i___13_n_0));
  LUT5 #(
    .INIT(32'hFF2AFFFF)) 
    i___14
       (.I0(\rank_common0/zq_cntrl.zq_request_logic.zq_request_r ),
        .I1(maint_zq_r),
        .I2(insert_maint_r1),
        .I3(app_zq_req),
        .I4(rank_mach0_n_32),
        .O(i___14_n_0));
  LUT5 #(
    .INIT(32'h00F8F0F8)) 
    i___15
       (.I0(app_sr_req),
        .I1(\grant_r_reg[0] ),
        .I2(\rank_common0/sr_cntrl.sre_request_logic.sre_request_r ),
        .I3(maint_sre_r),
        .I4(insert_maint_r1),
        .O(i___15_n_0));
  LUT5 #(
    .INIT(32'h54550400)) 
    i___16
       (.I0(\last_master_r_reg[2]_0 ),
        .I1(\rank_common0/maintenance_request.maint_grant_r [0]),
        .I2(\rank_common0/maintenance_request.new_maint_rank_r ),
        .I3(\rank_common0/maintenance_request.upd_last_master_r ),
        .I4(\rank_common0/maintenance_request.maint_arb0/last_master_r [0]),
        .O(i___16_n_0));
  LUT5 #(
    .INIT(32'h45444044)) 
    i___17
       (.I0(\last_master_r_reg[2]_0 ),
        .I1(\rank_common0/maintenance_request.maint_arb0/last_master_r [1]),
        .I2(\rank_common0/maintenance_request.new_maint_rank_r ),
        .I3(\rank_common0/maintenance_request.upd_last_master_r ),
        .I4(\rank_common0/maintenance_request.maint_grant_r [1]),
        .O(i___17_n_0));
  LUT5 #(
    .INIT(32'h10111511)) 
    i___18
       (.I0(\last_master_r_reg[2]_0 ),
        .I1(\rank_common0/maintenance_request.maint_arb0/last_master_r [2]),
        .I2(\rank_common0/maintenance_request.new_maint_rank_r ),
        .I3(\rank_common0/maintenance_request.upd_last_master_r ),
        .I4(\rank_common0/maintenance_request.maint_grant_r [2]),
        .O(i___18_n_0));
  LUT5 #(
    .INIT(32'h50405050)) 
    i___19
       (.I0(maint_wip_r),
        .I1(\rank_common0/sr_cntrl.sre_request_logic.sre_request_r ),
        .I2(\grant_r_reg[0] ),
        .I3(\rank_common0/zq_cntrl.zq_request_logic.zq_request_r ),
        .I4(\rank_cntrl[0].rank_cntrl0/refresh_generation.refresh_bank_r ),
        .O(i___19_n_0));
  LUT6 #(
    .INIT(64'hEECCFFCFEECCEECC)) 
    i___2
       (.I0(p_130_out),
        .I1(\bank_cntrl[0].bank0/bank_queue0/set_order_q ),
        .I2(idle_r[0]),
        .I3(bank_mach0_n_149),
        .I4(i___72_n_0),
        .I5(\bank_cntrl[0].bank0/tail_r ),
        .O(i___2_n_0));
  LUT6 #(
    .INIT(64'h00545454FFFFFFFF)) 
    i___20
       (.I0(bank_mach0_n_104),
        .I1(rank_mach0_n_64),
        .I2(\rank_cntrl[0].rank_cntrl0/periodic_rd_generation.periodic_rd_request_r ),
        .I3(clear_periodic_rd_request),
        .I4(\rank_cntrl[0].rank_cntrl0/periodic_rd_generation.periodic_rd_cntr1_r ),
        .I5(\grant_r_reg[0] ),
        .O(i___20_n_0));
  LUT3 #(
    .INIT(8'h78)) 
    i___21
       (.I0(\rank_common0/periodic_read_request.periodic_rd_grant_r ),
        .I1(periodic_rd_ack_r),
        .I2(\rank_cntrl[0].rank_cntrl0/periodic_rd_generation.periodic_rd_cntr1_r ),
        .O(i___21_n_0));
  LUT2 #(
    .INIT(4'h8)) 
    i___22
       (.I0(bank_mach0_n_92),
        .I1(sent_col),
        .O(i___22_n_0));
  LUT5 #(
    .INIT(32'hFFFEFFFF)) 
    i___23
       (.I0(sending_col[0]),
        .I1(sending_col[1]),
        .I2(sending_col[2]),
        .I3(sending_col[3]),
        .I4(sent_col),
        .O(i___23_n_0));
  LUT5 #(
    .INIT(32'h55550455)) 
    i___24
       (.I0(\last_master_r_reg[2]_0 ),
        .I1(\wtr_timer.wtr_cnt_r [1]),
        .I2(\wtr_timer.wtr_cnt_r [0]),
        .I3(bank_mach0_n_115),
        .I4(bank_mach0_n_114),
        .O(i___24_n_0));
  LUT6 #(
    .INIT(64'h5555555555040404)) 
    i___25
       (.I0(\last_master_r_reg[2]_0 ),
        .I1(\bank_cntrl[3].bank0/bank_state0/col_wait_r ),
        .I2(sending_col[3]),
        .I3(sending_row[3]),
        .I4(row_cmd_wr[3]),
        .I5(bank_mach0_n_116),
        .O(i___25_n_0));
  LUT6 #(
    .INIT(64'h5555555555040404)) 
    i___26
       (.I0(\last_master_r_reg[2]_0 ),
        .I1(\bank_cntrl[0].bank0/bank_state0/col_wait_r ),
        .I2(sending_col[0]),
        .I3(sending_row[0]),
        .I4(row_cmd_wr[0]),
        .I5(bank_mach0_n_123),
        .O(i___26_n_0));
  LUT3 #(
    .INIT(8'h07)) 
    i___27
       (.I0(sending_row[0]),
        .I1(row_cmd_wr[0]),
        .I2(bank_mach0_n_123),
        .O(i___27_n_0));
  LUT6 #(
    .INIT(64'h4444444444445455)) 
    i___28
       (.I0(\bank_cntrl[0].bank0/bank_state0/col_wait_r ),
        .I1(i___88_n_0),
        .I2(bank_mach0_n_125),
        .I3(\bank_cntrl[0].bank0/rb_hit_busies_r ),
        .I4(bank_mach0_n_124),
        .I5(bank_mach0_n_160),
        .O(i___28_n_0));
  LUT6 #(
    .INIT(64'h4444444444445455)) 
    i___29
       (.I0(\bank_cntrl[2].bank0/bank_state0/col_wait_r ),
        .I1(i___87_n_0),
        .I2(bank_mach0_n_122),
        .I3(\bank_cntrl[2].bank0/rb_hit_busies_r ),
        .I4(bank_mach0_n_127),
        .I5(bank_mach0_n_163),
        .O(i___29_n_0));
  LUT5 #(
    .INIT(32'hB8FFB800)) 
    i___3
       (.I0(bank_mach0_n_260),
        .I1(p_130_out),
        .I2(bank_mach0_n_144),
        .I3(bank_mach0_n_147),
        .I4(head_r[0]),
        .O(i___3_n_0));
  LUT6 #(
    .INIT(64'h5555555555040404)) 
    i___30
       (.I0(\last_master_r_reg[2]_0 ),
        .I1(\bank_cntrl[2].bank0/bank_state0/col_wait_r ),
        .I2(sending_col[2]),
        .I3(sending_row[2]),
        .I4(row_cmd_wr[2]),
        .I5(bank_mach0_n_126),
        .O(i___30_n_0));
  (* SOFT_HLUTNM = "soft_lutpair1212" *) 
  LUT3 #(
    .INIT(8'h04)) 
    i___31
       (.I0(p_52_out),
        .I1(bank_mach0_n_129),
        .I2(p_130_out),
        .O(i___31_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFFAAEAEAEA)) 
    i___32
       (.I0(p_130_out),
        .I1(\bank_cntrl[1].bank0/pass_open_bank_r ),
        .I2(sending_col[1]),
        .I3(rd_wr_r[1]),
        .I4(req_wr_r[1]),
        .I5(\bank_cntrl[1].bank0/bank_queue0/pre_bm_end_r ),
        .O(i___32_n_0));
  LUT6 #(
    .INIT(64'h9669699669969669)) 
    i___33
       (.I0(bank_mach0_n_129),
        .I1(idle_r[0]),
        .I2(idle_r[1]),
        .I3(idle_r[2]),
        .I4(idle_r[3]),
        .I5(p_130_out),
        .O(i___33_n_0));
  LUT5 #(
    .INIT(32'hFCDDFFFF)) 
    i___34
       (.I0(bank_mach0_n_154),
        .I1(\bank_cntrl[1].bank0/bank_queue0/set_order_q ),
        .I2(bank_mach0_n_133),
        .I3(idle_r[1]),
        .I4(bank_mach0_n_129),
        .O(i___34_n_0));
  LUT6 #(
    .INIT(64'h4444554544444444)) 
    i___35
       (.I0(i___37_n_0),
        .I1(\bank_common0/maint_controller.maint_hit_busies_r [1]),
        .I2(maint_req_r),
        .I3(\bank_common0/periodic_rd_cntr_r ),
        .I4(maint_wip_r),
        .I5(bank_mach0_n_93),
        .O(i___35_n_0));
  LUT6 #(
    .INIT(64'h4544555545444544)) 
    i___36
       (.I0(i___37_n_0),
        .I1(\bank_cntrl[1].bank0/q_has_rd ),
        .I2(was_wr),
        .I3(bank_mach0_n_135),
        .I4(idle_r[1]),
        .I5(maint_req_r),
        .O(i___36_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFFAAEAEAEA)) 
    i___37
       (.I0(\last_master_r_reg[2]_0 ),
        .I1(\bank_cntrl[1].bank0/pass_open_bank_r ),
        .I2(sending_col[1]),
        .I3(rd_wr_r[1]),
        .I4(req_wr_r[1]),
        .I5(\bank_cntrl[1].bank0/bank_queue0/pre_bm_end_r ),
        .O(i___37_n_0));
  LUT5 #(
    .INIT(32'h8117177E)) 
    i___38
       (.I0(bank_mach0_n_137),
        .I1(rb_hit_busy_r[0]),
        .I2(rb_hit_busy_r[2]),
        .I3(rb_hit_busy_r[1]),
        .I4(rb_hit_busy_r[3]),
        .O(i___38_n_0));
  LUT5 #(
    .INIT(32'hFCDDFFFF)) 
    i___39
       (.I0(bank_mach0_n_137),
        .I1(\bank_cntrl[3].bank0/bank_queue0/set_order_q ),
        .I2(bank_mach0_n_133),
        .I3(idle_r[3]),
        .I4(bank_mach0_n_117),
        .O(i___39_n_0));
  LUT6 #(
    .INIT(64'h88B8FFFF88B80000)) 
    i___4
       (.I0(bank_mach0_n_156),
        .I1(bank_mach0_n_129),
        .I2(bank_mach0_n_260),
        .I3(p_130_out),
        .I4(i___34_n_0),
        .I5(head_r[1]),
        .O(i___4_n_0));
  LUT6 #(
    .INIT(64'hEFEEEEEEFFFFFFFF)) 
    i___40
       (.I0(bank_mach0_n_151),
        .I1(rnk_config_valid_r),
        .I2(\bank_cntrl[2].bank0/bank_state0/override_demand_ns ),
        .I3(bank_mach0_n_150),
        .I4(\bank_cntrl[1].bank0/bank_state0/req_bank_rdy_ns ),
        .I5(bank_mach0_n_152),
        .O(i___40_n_0));
  LUT3 #(
    .INIT(8'h8F)) 
    i___41
       (.I0(req_wr_r[1]),
        .I1(rd_wr_r[1]),
        .I2(sending_col[1]),
        .O(i___41_n_0));
  LUT6 #(
    .INIT(64'hEAAAEAAAEAAAAAAA)) 
    i___42
       (.I0(\bank_cntrl[1].bank0/wait_for_maint_r ),
        .I1(accept_internal_r),
        .I2(idle_r[1]),
        .I3(head_r[1]),
        .I4(periodic_rd_ack_r),
        .I5(use_addr),
        .O(i___42_n_0));
  LUT6 #(
    .INIT(64'hEAAAEAAAEAAAAAAA)) 
    i___43
       (.I0(\bank_cntrl[3].bank0/wait_for_maint_r ),
        .I1(accept_internal_r),
        .I2(idle_r[3]),
        .I3(head_r[3]),
        .I4(periodic_rd_ack_r),
        .I5(use_addr),
        .O(i___43_n_0));
  LUT6 #(
    .INIT(64'h4444554544444444)) 
    i___44
       (.I0(i___55_n_0),
        .I1(\bank_common0/maint_controller.maint_hit_busies_r [3]),
        .I2(maint_req_r),
        .I3(\bank_common0/periodic_rd_cntr_r ),
        .I4(maint_wip_r),
        .I5(bank_mach0_n_94),
        .O(i___44_n_0));
  LUT6 #(
    .INIT(64'hEAAAEAAAEAAAAAAA)) 
    i___45
       (.I0(\bank_cntrl[2].bank0/wait_for_maint_r ),
        .I1(accept_internal_r),
        .I2(idle_r[2]),
        .I3(head_r[2]),
        .I4(periodic_rd_ack_r),
        .I5(use_addr),
        .O(i___45_n_0));
  LUT6 #(
    .INIT(64'h4444554544444444)) 
    i___46
       (.I0(bank_mach0_n_58),
        .I1(\bank_common0/maint_controller.maint_hit_busies_r [2]),
        .I2(maint_req_r),
        .I3(\bank_common0/periodic_rd_cntr_r ),
        .I4(maint_wip_r),
        .I5(bank_mach0_n_96),
        .O(i___46_n_0));
  LUT6 #(
    .INIT(64'hEAAAEAAAEAAAAAAA)) 
    i___47
       (.I0(\bank_cntrl[0].bank0/wait_for_maint_r ),
        .I1(accept_internal_r),
        .I2(idle_r[0]),
        .I3(head_r[0]),
        .I4(periodic_rd_ack_r),
        .I5(use_addr),
        .O(i___47_n_0));
  LUT6 #(
    .INIT(64'h4444554544444444)) 
    i___48
       (.I0(bank_mach0_n_59),
        .I1(\bank_common0/maint_controller.maint_hit_busies_r [0]),
        .I2(maint_req_r),
        .I3(\bank_common0/periodic_rd_cntr_r ),
        .I4(maint_wip_r),
        .I5(bank_mach0_n_98),
        .O(i___48_n_0));
  LUT6 #(
    .INIT(64'h5555555555040404)) 
    i___49
       (.I0(\last_master_r_reg[2]_0 ),
        .I1(\bank_cntrl[1].bank0/bank_state0/col_wait_r ),
        .I2(sending_col[1]),
        .I3(sending_row[1]),
        .I4(row_cmd_wr[1]),
        .I5(bank_mach0_n_158),
        .O(i___49_n_0));
  LUT6 #(
    .INIT(64'h2F20FFFF2F200000)) 
    i___5
       (.I0(bank_mach0_n_260),
        .I1(i___32_n_0),
        .I2(p_52_out),
        .I3(bank_mach0_n_142),
        .I4(bank_mach0_n_143),
        .I5(head_r[2]),
        .O(i___5_n_0));
  (* SOFT_HLUTNM = "soft_lutpair1212" *) 
  LUT3 #(
    .INIT(8'h04)) 
    i___50
       (.I0(p_52_out),
        .I1(bank_mach0_n_117),
        .I2(p_130_out),
        .O(i___50_n_0));
  LUT6 #(
    .INIT(64'h4544555545444544)) 
    i___51
       (.I0(bank_mach0_n_59),
        .I1(\bank_cntrl[0].bank0/q_has_rd ),
        .I2(was_wr),
        .I3(i___72_n_0),
        .I4(idle_r[0]),
        .I5(maint_req_r),
        .O(i___51_n_0));
  LUT6 #(
    .INIT(64'h4544555545444544)) 
    i___52
       (.I0(bank_mach0_n_58),
        .I1(\bank_cntrl[2].bank0/q_has_rd ),
        .I2(was_wr),
        .I3(bank_mach0_n_161),
        .I4(idle_r[2]),
        .I5(maint_req_r),
        .O(i___52_n_0));
  LUT3 #(
    .INIT(8'h8F)) 
    i___53
       (.I0(req_wr_r[2]),
        .I1(rd_wr_r[2]),
        .I2(sending_col[2]),
        .O(i___53_n_0));
  LUT6 #(
    .INIT(64'h4544555545444544)) 
    i___54
       (.I0(i___55_n_0),
        .I1(\bank_cntrl[3].bank0/q_has_rd ),
        .I2(was_wr),
        .I3(i___71_n_0),
        .I4(idle_r[3]),
        .I5(maint_req_r),
        .O(i___54_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFFAAEAEAEA)) 
    i___55
       (.I0(\last_master_r_reg[2]_0 ),
        .I1(\bank_cntrl[3].bank0/pass_open_bank_r ),
        .I2(sending_col[3]),
        .I3(rd_wr_r[3]),
        .I4(req_wr_r[3]),
        .I5(\bank_cntrl[3].bank0/bank_queue0/pre_bm_end_r ),
        .O(i___55_n_0));
  LUT3 #(
    .INIT(8'h8F)) 
    i___56
       (.I0(req_wr_r[3]),
        .I1(rd_wr_r[3]),
        .I2(sending_col[3]),
        .O(i___56_n_0));
  (* SOFT_HLUTNM = "soft_lutpair1208" *) 
  LUT3 #(
    .INIT(8'h78)) 
    i___57
       (.I0(periodic_rd_r),
        .I1(periodic_rd_ack_r),
        .I2(\rank_common0/periodic_read_request.periodic_rd_r_cnt ),
        .O(i___57_n_0));
  (* SOFT_HLUTNM = "soft_lutpair1209" *) 
  LUT3 #(
    .INIT(8'h78)) 
    i___58
       (.I0(periodic_rd_r),
        .I1(periodic_rd_ack_r),
        .I2(\bank_common0/periodic_rd_cntr_r ),
        .O(i___58_n_0));
  (* SOFT_HLUTNM = "soft_lutpair1209" *) 
  LUT4 #(
    .INIT(16'hBFAA)) 
    i___59
       (.I0(cmd[0]),
        .I1(periodic_rd_ack_r),
        .I2(\bank_common0/periodic_rd_cntr_r ),
        .I3(periodic_rd_r),
        .O(i___59_n_0));
  LUT6 #(
    .INIT(64'hB888FFFFB8880000)) 
    i___6
       (.I0(bank_mach0_n_138),
        .I1(bank_mach0_n_117),
        .I2(i___31_n_0),
        .I3(bank_mach0_n_260),
        .I4(i___39_n_0),
        .I5(head_r[3]),
        .O(i___6_n_0));
  LUT6 #(
    .INIT(64'h0101010101015101)) 
    i___60
       (.I0(\last_master_r_reg[2]_0 ),
        .I1(bank_mach0_n_276),
        .I2(\generate_maint_cmds.insert_maint_r_lcl_reg ),
        .I3(maint_srx_r),
        .I4(maint_sre_r),
        .I5(maint_zq_r),
        .O(i___60_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFF11110010)) 
    i___61
       (.I0(bank_mach0_n_159),
        .I1(bank_mach0_n_259),
        .I2(\bank_cntrl[0].bank0/bank_state0/col_wait_r ),
        .I3(sending_col[0]),
        .I4(row_cmd_wr[0]),
        .I5(\bank_cntrl[0].bank0/auto_pre_r ),
        .O(i___61_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFF11110010)) 
    i___62
       (.I0(bank_mach0_n_136),
        .I1(bank_mach0_n_262),
        .I2(\bank_cntrl[1].bank0/bank_state0/col_wait_r ),
        .I3(sending_col[1]),
        .I4(row_cmd_wr[1]),
        .I5(\bank_cntrl[1].bank0/auto_pre_r ),
        .O(i___62_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFF11110010)) 
    i___63
       (.I0(bank_mach0_n_162),
        .I1(bank_mach0_n_261),
        .I2(\bank_cntrl[2].bank0/bank_state0/col_wait_r ),
        .I3(sending_col[2]),
        .I4(row_cmd_wr[2]),
        .I5(\bank_cntrl[2].bank0/auto_pre_r ),
        .O(i___63_n_0));
  LUT6 #(
    .INIT(64'hFFFFFFFF11110010)) 
    i___64
       (.I0(bank_mach0_n_164),
        .I1(bank_mach0_n_258),
        .I2(\bank_cntrl[3].bank0/bank_state0/col_wait_r ),
        .I3(sending_col[3]),
        .I4(row_cmd_wr[3]),
        .I5(\bank_cntrl[3].bank0/auto_pre_r ),
        .O(i___64_n_0));
  LUT4 #(
    .INIT(16'hAAFB)) 
    i___65
       (.I0(\inhbt_act_faw.inhbt_act_faw_r_reg ),
        .I1(maint_req_r),
        .I2(\bank_common0/periodic_rd_cntr_r ),
        .I3(maint_wip_r),
        .O(i___65_n_0));
  LUT5 #(
    .INIT(32'h55FF55CF)) 
    i___66
       (.I0(row_cmd_wr[0]),
        .I1(maint_zq_r),
        .I2(insert_maint_r1),
        .I3(sending_row[0]),
        .I4(\inhbt_act_faw.inhbt_act_faw_r_reg ),
        .O(i___66_n_0));
  (* SOFT_HLUTNM = "soft_lutpair1207" *) 
  LUT5 #(
    .INIT(32'hEEEEEEE0)) 
    i___67
       (.I0(sent_row),
        .I1(insert_maint_r1),
        .I2(sending_row[3]),
        .I3(sending_row[2]),
        .I4(sending_row[1]),
        .O(i___67_n_0));
  (* SOFT_HLUTNM = "soft_lutpair1207" *) 
  LUT5 #(
    .INIT(32'hFFFFFFF1)) 
    i___68
       (.I0(sent_row),
        .I1(insert_maint_r1),
        .I2(sending_row[3]),
        .I3(sending_row[2]),
        .I4(sending_row[1]),
        .O(i___68_n_0));
  LUT3 #(
    .INIT(8'hEF)) 
    i___69
       (.I0(sending_row[2]),
        .I1(sending_row[3]),
        .I2(sending_row[1]),
        .O(i___69_n_0));
  LUT6 #(
    .INIT(64'hDDCCFFCFDDCCDDCC)) 
    i___7
       (.I0(bank_mach0_n_129),
        .I1(\bank_cntrl[1].bank0/bank_queue0/set_order_q ),
        .I2(idle_r[1]),
        .I3(i___50_n_0),
        .I4(bank_mach0_n_135),
        .I5(\bank_cntrl[1].bank0/tail_r ),
        .O(i___7_n_0));
  LUT5 #(
    .INIT(32'h00000015)) 
    i___70
       (.I0(bank_mach0_n_264),
        .I1(row_cmd_wr[2]),
        .I2(sending_row[2]),
        .I3(sending_row[0]),
        .I4(bank_mach0_n_257),
        .O(i___70_n_0));
  (* SOFT_HLUTNM = "soft_lutpair1210" *) 
  LUT4 #(
    .INIT(16'hF800)) 
    i___71
       (.I0(use_addr),
        .I1(bank_mach0_n_10),
        .I2(periodic_rd_ack_r),
        .I3(rb_hit_busy_r[3]),
        .O(i___71_n_0));
  (* SOFT_HLUTNM = "soft_lutpair1210" *) 
  LUT4 #(
    .INIT(16'hF800)) 
    i___72
       (.I0(use_addr),
        .I1(bank_mach0_n_10),
        .I2(periodic_rd_ack_r),
        .I3(rb_hit_busy_r[0]),
        .O(i___72_n_0));
  LUT5 #(
    .INIT(32'h00000015)) 
    i___73
       (.I0(bank_mach0_n_263),
        .I1(row_cmd_wr[3]),
        .I2(sending_row[3]),
        .I3(sending_row[1]),
        .I4(bank_mach0_n_267),
        .O(i___73_n_0));
  LUT5 #(
    .INIT(32'h00000015)) 
    i___74
       (.I0(bank_mach0_n_267),
        .I1(row_cmd_wr[1]),
        .I2(sending_row[1]),
        .I3(sending_row[3]),
        .I4(bank_mach0_n_266),
        .O(i___74_n_0));
  LUT4 #(
    .INIT(16'h0151)) 
    i___75
       (.I0(\inhbt_act_faw.inhbt_act_faw_r_reg ),
        .I1(\arb_mux0/arb_row_col0/pre_4_1_1T_arb.pre_arb0/last_master_r ),
        .I2(\arb_mux0/cs_en2 ),
        .I3(sending_pre),
        .O(i___75_n_0));
  (* SOFT_HLUTNM = "soft_lutpair1208" *) 
  LUT4 #(
    .INIT(16'hFF4C)) 
    i___76
       (.I0(periodic_rd_ack_r),
        .I1(periodic_rd_r),
        .I2(\rank_common0/periodic_read_request.periodic_rd_r_cnt ),
        .I3(\rank_common0/periodic_read_request.upd_last_master_r ),
        .O(i___76_n_0));
  LUT3 #(
    .INIT(8'hBA)) 
    i___77
       (.I0(app_ref_req),
        .I1(\rank_cntrl[0].rank_cntrl0/refresh_generation.refresh_bank_r ),
        .I2(\rank_common0/app_ref_r ),
        .O(i___77_n_0));
  LUT3 #(
    .INIT(8'hEA)) 
    i___78
       (.I0(app_zq_req),
        .I1(\rank_common0/app_zq_r ),
        .I2(\rank_common0/zq_cntrl.zq_request_logic.zq_request_r ),
        .O(i___78_n_0));
  (* SOFT_HLUTNM = "soft_lutpair1206" *) 
  LUT4 #(
    .INIT(16'h1441)) 
    i___79
       (.I0(\inhbt_act_faw.inhbt_act_faw_r_reg ),
        .I1(\rank_cntrl[0].rank_cntrl0/inhbt_act_faw.act_delayed ),
        .I2(bank_mach0_n_274),
        .I3(\inhbt_act_faw.faw_cnt_r [0]),
        .O(i___79_n_0));
  LUT6 #(
    .INIT(64'hEFEFCCCFEEEECCCC)) 
    i___8
       (.I0(p_52_out),
        .I1(\bank_cntrl[2].bank0/bank_queue0/set_order_q ),
        .I2(bank_mach0_n_161),
        .I3(idle_r[2]),
        .I4(bank_mach0_n_128),
        .I5(\bank_cntrl[2].bank0/tail_r ),
        .O(i___8_n_0));
  (* SOFT_HLUTNM = "soft_lutpair1206" *) 
  LUT5 #(
    .INIT(32'h44411444)) 
    i___80
       (.I0(\inhbt_act_faw.inhbt_act_faw_r_reg ),
        .I1(\inhbt_act_faw.faw_cnt_r [1]),
        .I2(bank_mach0_n_274),
        .I3(\rank_cntrl[0].rank_cntrl0/inhbt_act_faw.act_delayed ),
        .I4(\inhbt_act_faw.faw_cnt_r [0]),
        .O(i___80_n_0));
  LUT6 #(
    .INIT(64'h5551455500041000)) 
    i___81
       (.I0(\inhbt_act_faw.inhbt_act_faw_r_reg ),
        .I1(\inhbt_act_faw.faw_cnt_r [1]),
        .I2(\rank_cntrl[0].rank_cntrl0/inhbt_act_faw.act_delayed ),
        .I3(bank_mach0_n_274),
        .I4(\inhbt_act_faw.faw_cnt_r [0]),
        .I5(\inhbt_act_faw.faw_cnt_r [2]),
        .O(i___81_n_0));
  (* SOFT_HLUTNM = "soft_lutpair1211" *) 
  LUT4 #(
    .INIT(16'hF7FF)) 
    i___82
       (.I0(\bank_common0/rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r [1]),
        .I1(\bank_common0/rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r [0]),
        .I2(\bank_common0/rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r [2]),
        .I3(bank_mach0_n_275),
        .O(i___82_n_0));
  (* SOFT_HLUTNM = "soft_lutpair1211" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    i___83
       (.I0(\bank_common0/rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r [3]),
        .I1(\bank_common0/rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r [2]),
        .I2(\bank_common0/rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r [1]),
        .I3(\bank_common0/rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r [0]),
        .O(i___83_n_0));
  LUT6 #(
    .INIT(64'h0000000055550010)) 
    i___84
       (.I0(\bank_cntrl[2].bank0/bank_state0/override_demand_r ),
        .I1(\bank_cntrl[0].bank0/bank_state0/demanded_prior_r ),
        .I2(\bank_cntrl[0].bank0/bank_state0/demand_priority_r ),
        .I3(sending_col[0]),
        .I4(bank_mach0_n_265),
        .I5(\bank_cntrl[3].bank0/bank_state0/demand_priority_r ),
        .O(i___84_n_0));
  LUT6 #(
    .INIT(64'h0000000011111511)) 
    i___85
       (.I0(\bank_cntrl[2].bank0/bank_state0/override_demand_r ),
        .I1(bank_mach0_n_277),
        .I2(\bank_cntrl[2].bank0/bank_state0/demanded_prior_r ),
        .I3(\bank_cntrl[2].bank0/bank_state0/demand_priority_r ),
        .I4(sending_col[2]),
        .I5(\bank_cntrl[1].bank0/bank_state0/demand_priority_r ),
        .O(i___85_n_0));
  LUT6 #(
    .INIT(64'h0000000011111511)) 
    i___86
       (.I0(\bank_cntrl[2].bank0/bank_state0/override_demand_r ),
        .I1(bank_mach0_n_277),
        .I2(\bank_cntrl[1].bank0/bank_state0/demanded_prior_r ),
        .I3(\bank_cntrl[1].bank0/bank_state0/demand_priority_r ),
        .I4(sending_col[1]),
        .I5(\bank_cntrl[2].bank0/bank_state0/demand_priority_r ),
        .O(i___86_n_0));
  LUT3 #(
    .INIT(8'hEF)) 
    i___87
       (.I0(idle_r[2]),
        .I1(bank_mach0_n_140),
        .I2(bank_mach0_n_141),
        .O(i___87_n_0));
  LUT3 #(
    .INIT(8'hEF)) 
    i___88
       (.I0(idle_r[0]),
        .I1(q_entry_r[1]),
        .I2(q_entry_r[0]),
        .O(i___88_n_0));
  LUT3 #(
    .INIT(8'hEF)) 
    i___89
       (.I0(idle_r[3]),
        .I1(bank_mach0_n_131),
        .I2(bank_mach0_n_132),
        .O(i___89_n_0));
  LUT6 #(
    .INIT(64'hDDCCFFCFDDCCDDCC)) 
    i___9
       (.I0(bank_mach0_n_117),
        .I1(\bank_cntrl[3].bank0/bank_queue0/set_order_q ),
        .I2(idle_r[3]),
        .I3(i___31_n_0),
        .I4(i___71_n_0),
        .I5(\bank_cntrl[3].bank0/tail_r ),
        .O(i___9_n_0));
  LUT3 #(
    .INIT(8'hEF)) 
    i___90
       (.I0(idle_r[1]),
        .I1(bank_mach0_n_157),
        .I2(bank_mach0_n_155),
        .O(i___90_n_0));
  LUT5 #(
    .INIT(32'h15554000)) 
    i___91
       (.I0(\inhbt_act_faw.inhbt_act_faw_r_reg ),
        .I1(\read_fifo.tail_r_reg[0] ),
        .I2(\read_fifo.tail_r_reg[2] ),
        .I3(\read_fifo.tail_r [1]),
        .I4(\read_fifo.tail_r [2]),
        .O(i___91_n_0));
  LUT2 #(
    .INIT(4'h1)) 
    i___92
       (.I0(\inhbt_act_faw.inhbt_act_faw_r_reg ),
        .I1(col_mach0_n_12),
        .O(i___92_n_0));
  LUT4 #(
    .INIT(16'h1540)) 
    i___93
       (.I0(\inhbt_act_faw.inhbt_act_faw_r_reg ),
        .I1(\read_fifo.tail_r_reg[2] ),
        .I2(\read_fifo.tail_r_reg[0] ),
        .I3(\read_fifo.tail_r [1]),
        .O(i___93_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    i___94
       (.I0(\rank_common0/maint_prescaler.maint_prescaler_r_reg [0]),
        .I1(\rank_common0/maint_prescaler.maint_prescaler_r_reg [1]),
        .O(i___94_n_0));
  LUT2 #(
    .INIT(4'h9)) 
    i___95
       (.I0(\rank_common0/refresh_timer.refresh_timer_r_reg [0]),
        .I1(\rank_common0/refresh_timer.refresh_timer_r_reg [1]),
        .O(i___95_n_0));
  FDRE mc_read_idle_r_reg
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(col_mach0_n_7),
        .Q(idle),
        .R(\periodic_read_request.periodic_rd_r_lcl_reg ));
  FDRE mc_ref_zq_wip_r_reg
       (.C(\last_master_r_reg[2] ),
        .CE(1'b1),
        .D(mc_ref_zq_wip_ns),
        .Q(mc_ref_zq_wip),
        .R(1'b0));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_12_17_i_2__1
       (.I0(Q[13]),
        .I1(mem_reg_0_15_36_41),
        .O(d_in[0]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_18_23_i_1__7
       (.I0(Q[38]),
        .I1(mem_reg_0_15_36_41),
        .O(d_in[1]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_30_35_i_2__9
       (.I0(mc_cs_n),
        .I1(mem_reg_0_15_42_47),
        .O(phy_dout[0]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_30_35_i_3__9
       (.I0(mc_ras_n[2]),
        .I1(mem_reg_0_15_42_47),
        .O(phy_dout[4]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_36_41_i_1__9
       (.I0(Q[11]),
        .I1(mem_reg_0_15_36_41),
        .O(d_in[2]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_36_41_i_2__8
       (.I0(mc_cas_n[0]),
        .I1(mem_reg_0_15_36_41),
        .O(phy_dout[1]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_42_47_i_1__8
       (.I0(mc_cas_n[2]),
        .I1(mem_reg_0_15_42_47),
        .O(phy_dout[2]));
  LUT2 #(
    .INIT(4'h8)) 
    mem_reg_0_15_42_47_i_1__9
       (.I0(Q[36]),
        .I1(mem_reg_0_15_36_41),
        .O(d_in[3]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_42_47_i_3__9
       (.I0(mc_ras_n[0]),
        .I1(mem_reg_0_15_42_47),
        .O(phy_dout[3]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_48_53_i_2__9
       (.I0(mc_we_n[0]),
        .I1(mem_reg_0_15_42_47),
        .O(phy_dout[5]));
  LUT2 #(
    .INIT(4'hB)) 
    mem_reg_0_15_54_59_i_1__9
       (.I0(mc_we_n[2]),
        .I1(mem_reg_0_15_42_47),
        .O(phy_dout[6]));
  LUT2 #(
    .INIT(4'hB)) 
    \pointer_ram.rams[0].RAM32M0_i_1 
       (.I0(wr_data_en),
        .I1(ram_init_done_r),
        .O(\pointer_ram.pointer_we ));
  mig_mig_7series_v4_2_rank_mach rank_mach0
       (.D({i___17_n_0,i___16_n_0}),
        .O({\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_4 ,\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_5 ,\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_6 ,\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_7 }),
        .Q(\rank_common0/maint_prescaler.maint_prescaler_r_reg ),
        .S({rank_mach0_n_40,rank_mach0_n_41,rank_mach0_n_42,rank_mach0_n_43}),
        .SR(SR),
        .SS(i___12_n_0),
        .act_this_rank(\rank_cntrl[0].rank_cntrl0/act_this_rank ),
        .app_ref_ack(app_ref_ack),
        .app_ref_r(\rank_common0/app_ref_r ),
        .app_ref_r_reg(i___77_n_0),
        .app_ref_req(app_ref_req),
        .app_sr_active(app_sr_active),
        .app_sr_active_r_reg(i___0_n_0),
        .app_sr_req(app_sr_req),
        .app_zq_ack(app_zq_ack),
        .app_zq_r(\rank_common0/app_zq_r ),
        .app_zq_r_reg(i___78_n_0),
        .cke_r(\arb_mux0/arb_select0/cke_r ),
        .\grant_r_reg[0] (\grant_r_reg[0] ),
        .\grant_r_reg[2] (\rank_common0/maintenance_request.maint_grant_r ),
        .\grant_r_reg[2]_0 (i___18_n_0),
        .\inhbt_act_faw.act_delayed (\rank_cntrl[0].rank_cntrl0/inhbt_act_faw.act_delayed ),
        .\inhbt_act_faw.faw_cnt_r_reg[2] (\inhbt_act_faw.faw_cnt_r ),
        .\inhbt_act_faw.faw_cnt_r_reg[2]_0 ({i___81_n_0,i___80_n_0,i___79_n_0}),
        .\inhbt_act_faw.inhbt_act_faw_r_reg (\inhbt_act_faw.inhbt_act_faw_r_reg ),
        .\inhbt_act_faw.inhbt_act_faw_r_reg_0 (bank_mach0_n_274),
        .inhbt_act_faw_r(inhbt_act_faw_r),
        .init_calib_complete_reg_rep__26(rank_mach0_n_32),
        .insert_maint_r1(insert_maint_r1),
        .\last_master_r_reg[2] (\rank_common0/maintenance_request.maint_arb0/last_master_r ),
        .\last_master_r_reg[2]_0 (\last_master_r_reg[2] ),
        .\last_master_r_reg[2]_1 (\last_master_r_reg[2]_0 ),
        .\maint_prescaler.maint_prescaler_r_reg[1] (i___94_n_0),
        .maint_ref_zq_wip(maint_ref_zq_wip),
        .maint_ref_zq_wip_r_reg(i___1_n_0),
        .maint_req_r(maint_req_r),
        .maint_sre_r(maint_sre_r),
        .maint_srx_r(maint_srx_r),
        .maint_zq_r(maint_zq_r),
        .\maintenance_request.maint_sre_r_lcl_reg (rank_mach0_n_63),
        .\maintenance_request.maint_srx_r_lcl_reg (\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_ns ),
        .\maintenance_request.new_maint_rank_r (\rank_common0/maintenance_request.new_maint_rank_r ),
        .\maintenance_request.upd_last_master_r (\rank_common0/maintenance_request.upd_last_master_r ),
        .\maintenance_request.upd_last_master_r_reg (i___19_n_0),
        .mc_cke_ns(mc_cke_ns),
        .\periodic_rd_generation.periodic_rd_cntr1_r (\rank_cntrl[0].rank_cntrl0/periodic_rd_generation.periodic_rd_cntr1_r ),
        .\periodic_rd_generation.periodic_rd_cntr1_r_reg (\periodic_rd_generation.periodic_rd_cntr1_r_reg ),
        .\periodic_rd_generation.periodic_rd_cntr1_r_reg_0 (i___21_n_0),
        .\periodic_rd_generation.periodic_rd_request_r (\rank_cntrl[0].rank_cntrl0/periodic_rd_generation.periodic_rd_request_r ),
        .\periodic_rd_generation.periodic_rd_request_r_reg (i___20_n_0),
        .\periodic_rd_generation.periodic_rd_timer_r_reg[2] (rank_mach0_n_64),
        .\periodic_rd_generation.periodic_rd_timer_r_reg[2]_0 (bank_mach0_n_104),
        .\periodic_rd_generation.periodic_rd_timer_r_reg[2]_1 (\periodic_rd_generation.periodic_rd_timer_r_reg[2] ),
        .\periodic_rd_generation.read_this_rank (\rank_cntrl[0].rank_cntrl0/periodic_rd_generation.read_this_rank ),
        .\periodic_rd_generation.read_this_rank_r (\rank_cntrl[0].rank_cntrl0/periodic_rd_generation.read_this_rank_r ),
        .periodic_rd_r(periodic_rd_r),
        .\periodic_read_request.periodic_rd_grant_r (\rank_common0/periodic_read_request.periodic_rd_grant_r ),
        .\periodic_read_request.periodic_rd_grant_r_reg[0] (i__n_0),
        .\periodic_read_request.periodic_rd_r_cnt (\rank_common0/periodic_read_request.periodic_rd_r_cnt ),
        .\periodic_read_request.periodic_rd_r_cnt_reg (\periodic_read_request.periodic_rd_r_cnt_reg ),
        .\periodic_read_request.periodic_rd_r_cnt_reg_0 (i___57_n_0),
        .\periodic_read_request.periodic_rd_r_lcl_reg (\periodic_read_request.periodic_rd_r_lcl_reg ),
        .\periodic_read_request.periodic_rd_r_lcl_reg_0 (i___76_n_0),
        .\periodic_read_request.upd_last_master_r (\rank_common0/periodic_read_request.upd_last_master_r ),
        .\refresh_generation.refresh_bank_r (\rank_cntrl[0].rank_cntrl0/refresh_generation.refresh_bank_r ),
        .\refresh_timer.refresh_timer_r_reg[1] (\rank_common0/refresh_timer.refresh_timer_r_reg ),
        .\refresh_timer.refresh_timer_r_reg[1]_0 (i___95_n_0),
        .\refresh_timer.refresh_timer_r_reg[5] (rank_mach0_n_29),
        .\refresh_timer.refresh_timer_r_reg[5]_0 (i___13_n_0),
        .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] (\bank_common0/rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r [0]),
        .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 (\generate_maint_cmds.insert_maint_r_lcl_reg ),
        .\rtw_timer.rtw_cnt_r_reg[1] (\rtw_timer.rtw_cnt_r ),
        .\rtw_timer.rtw_cnt_r_reg[1]_0 (\rank_cntrl[0].rank_cntrl0/rtw_timer.rtw_cnt_ns ),
        .\sr_cntrl.sre_request_logic.sre_request_r (\rank_common0/sr_cntrl.sre_request_logic.sre_request_r ),
        .\sr_cntrl.sre_request_logic.sre_request_r_reg (i___15_n_0),
        .\wtr_timer.wtr_cnt_r_reg[0] (i___24_n_0),
        .\wtr_timer.wtr_cnt_r_reg[1] (\wtr_timer.wtr_cnt_r ),
        .\wtr_timer.wtr_cnt_r_reg[1]_0 (bank_mach0_n_113),
        .\zq_cntrl.zq_request_logic.zq_request_r (\rank_common0/zq_cntrl.zq_request_logic.zq_request_r ),
        .\zq_cntrl.zq_request_logic.zq_request_r_reg (\zq_cntrl.zq_request_logic.zq_request_r_reg ),
        .\zq_cntrl.zq_request_logic.zq_request_r_reg_0 (i___14_n_0),
        .\zq_cntrl.zq_timer.zq_timer_r_reg[11] ({rank_mach0_n_48,rank_mach0_n_49,rank_mach0_n_50,rank_mach0_n_51}),
        .\zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 ({\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_4 ,\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_5 ,\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_6 ,\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_7 }),
        .\zq_cntrl.zq_timer.zq_timer_r_reg[15] ({rank_mach0_n_52,rank_mach0_n_53,rank_mach0_n_54,rank_mach0_n_55}),
        .\zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 ({\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_4 ,\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_5 ,\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_6 ,\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_7 }),
        .\zq_cntrl.zq_timer.zq_timer_r_reg[19] ({rank_mach0_n_56,rank_mach0_n_57,rank_mach0_n_58,rank_mach0_n_59}),
        .\zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 ({\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_4 ,\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_5 ,\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_6 ,\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_7 }),
        .\zq_cntrl.zq_timer.zq_timer_r_reg[7] ({rank_mach0_n_44,rank_mach0_n_45,rank_mach0_n_46,rank_mach0_n_47}),
        .\zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 ({\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_4 ,\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_5 ,\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_6 ,\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_7 }));
  CARRY4 \zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3 
       (.CI(1'b0),
        .CO({\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_0 ,\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_1 ,\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_2 ,\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b1,1'b1,1'b1,1'b1}),
        .O({\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_4 ,\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_5 ,\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_6 ,\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_7 }),
        .S({rank_mach0_n_40,rank_mach0_n_41,rank_mach0_n_42,rank_mach0_n_43}));
  CARRY4 \zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1 
       (.CI(\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_0 ),
        .CO({\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_0 ,\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_1 ,\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_2 ,\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b1,1'b1,1'b1,1'b1}),
        .O({\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_4 ,\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_5 ,\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_6 ,\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_7 }),
        .S({rank_mach0_n_52,rank_mach0_n_53,rank_mach0_n_54,rank_mach0_n_55}));
  CARRY4 \zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1 
       (.CI(\zq_cntrl.zq_timer.zq_timer_r_reg[12]_i_1_n_0 ),
        .CO({\NLW_zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_CO_UNCONNECTED [3],\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_1 ,\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_2 ,\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b0,1'b1,1'b1,1'b1}),
        .O({\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_4 ,\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_5 ,\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_6 ,\zq_cntrl.zq_timer.zq_timer_r_reg[16]_i_1_n_7 }),
        .S({rank_mach0_n_56,rank_mach0_n_57,rank_mach0_n_58,rank_mach0_n_59}));
  CARRY4 \zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1 
       (.CI(\zq_cntrl.zq_timer.zq_timer_r_reg[0]_i_3_n_0 ),
        .CO({\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_0 ,\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_1 ,\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_2 ,\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b1,1'b1,1'b1,1'b1}),
        .O({\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_4 ,\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_5 ,\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_6 ,\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_7 }),
        .S({rank_mach0_n_44,rank_mach0_n_45,rank_mach0_n_46,rank_mach0_n_47}));
  CARRY4 \zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1 
       (.CI(\zq_cntrl.zq_timer.zq_timer_r_reg[4]_i_1_n_0 ),
        .CO({\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_0 ,\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_1 ,\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_2 ,\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_3 }),
        .CYINIT(1'b0),
        .DI({1'b1,1'b1,1'b1,1'b1}),
        .O({\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_4 ,\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_5 ,\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_6 ,\zq_cntrl.zq_timer.zq_timer_r_reg[8]_i_1_n_7 }),
        .S({rank_mach0_n_48,rank_mach0_n_49,rank_mach0_n_50,rank_mach0_n_51}));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_mem_intfc" *) 
module mig_mig_7series_v4_2_mem_intfc
   (app_ref_ack,
    app_zq_ack,
    \generate_maint_cmds.insert_maint_r_lcl_reg ,
    accept_ns,
    bm_end_r1,
    bm_end_r1_0,
    bm_end_r1_1,
    app_sr_active,
    ddr3_reset_n,
    ddr3_cas_n,
    ddr3_ras_n,
    ddr3_we_n,
    ddr3_addr,
    ddr3_ba,
    ddr3_cs_n,
    ddr3_odt,
    ddr3_cke,
    ddr3_dm,
    A_rst_primitives_reg,
    A_rst_primitives_reg_0,
    A_rst_primitives_reg_1,
    A_rst_primitives_reg_2,
    A_rst_primitives_reg_3,
    A_rst_primitives_reg_4,
    A_rst_primitives_reg_5,
    A_rst_primitives_reg_6,
    rst_tmp,
    po_cnt_dec_reg,
    po_cnt_dec_2,
    fine_adjust_reg,
    new_cnt_cpt_r_reg,
    rdlvl_stg1_start_reg,
    samp_edge_cnt0_en_r,
    pi_cnt_dec_reg,
    E,
    prbs_rdlvl_done_pulse_reg,
    init_calib_complete,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_6 ,
    req_bank_r,
    \req_row_r_lcl_reg[13] ,
    app_rd_data_valid,
    \init_state_r_reg[4] ,
    \pointer_ram.pointer_we ,
    wr_data_en,
    app_rd_data_end,
    wr_data_addr,
    ddr_ck_out,
    ddr3_dq,
    ddr3_dqs_p,
    ddr3_dqs_n,
    \last_master_r_reg[2] ,
    \periodic_read_request.periodic_rd_r_cnt_reg ,
    \periodic_rd_generation.periodic_rd_cntr1_r_reg ,
    \zq_cntrl.zq_request_logic.zq_request_r_reg ,
    SR,
    app_zq_req,
    app_sr_req,
    \last_master_r_reg[2]_0 ,
    use_addr,
    cmd,
    \inhbt_act_faw.inhbt_act_faw_r_reg ,
    app_ref_req,
    mmcm_ps_clk,
    rst_sync_r1,
    freq_refclk,
    mem_refclk,
    sync_pulse,
    pll_locked,
    cal2_if_reset_reg,
    CLKB0,
    CLKB0_7,
    CLKB0_8,
    CLKB0_9,
    RST0,
    CLKB0_10,
    CLKB0_11,
    CLKB0_12,
    CLKB0_13,
    \rstdiv2_sync_r_reg[11] ,
    iodelay_ctrl_rdy,
    out,
    S,
    row_hit_r_reg,
    row_hit_r_reg_0,
    row_hit_r_reg_1,
    row_hit_r_reg_2,
    row_hit_r_reg_3,
    \fine_dec_cnt_reg[5] ,
    \corse_inc_reg[6][2] ,
    \wl_dqs_tap_count_r_reg[0][5][5] ,
    first_fail_detect_reg,
    \rdlvl_dqs_tap_cnt_r_reg[0][0][2] ,
    \samp_edge_cnt1_r_reg[0] ,
    \FSM_onehot_cal1_state_r_reg[7] ,
    \samples_cnt_r_reg[0] ,
    \en_cnt_div4.enable_wrlvl_cnt_reg[2] ,
    \victim_sel_reg[0] ,
    \four_dec_min_limit_reg[0] ,
    \idelay_tap_cnt_r_reg[0][0][4] ,
    \rtp_timer_r_reg[1] ,
    \complex_num_writes_reg[1] ,
    Q,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ,
    rb_hit_busy_r_reg,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[6] ,
    \rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ,
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] ,
    D,
    ras_timer_zero_r_reg,
    ras_timer_zero_r_reg_0,
    ras_timer_zero_r_reg_1,
    \rtp_timer_r_reg[0] ,
    \pi_rst_stg1_cal_r_reg[1] ,
    \cmp_err_4to1.compare_err_f3_reg ,
    ram_init_done_r,
    was_priority_reg,
    \req_data_buf_addr_r_reg[3] ,
    \req_bank_r_lcl_reg[2] ,
    \req_col_r_reg[9] ,
    \fine_inc_reg[6][3] ,
    \corse_dec_reg[7][0] ,
    \smallest_reg[6][0] ,
    SS,
    \wait_cnt_r_reg[0] ,
    \tap_cnt_cpt_r_reg[5] ,
    \cnt_shift_r_reg[0] ,
    \wait_cnt_r_reg[0]_0 ,
    \en_cnt_div4.enable_wrlvl_cnt_reg[4] ,
    \device_temp_101_reg[11] );
  output app_ref_ack;
  output app_zq_ack;
  output \generate_maint_cmds.insert_maint_r_lcl_reg ;
  output accept_ns;
  output bm_end_r1;
  output bm_end_r1_0;
  output bm_end_r1_1;
  output app_sr_active;
  output ddr3_reset_n;
  output ddr3_cas_n;
  output ddr3_ras_n;
  output ddr3_we_n;
  output [13:0]ddr3_addr;
  output [2:0]ddr3_ba;
  output [0:0]ddr3_cs_n;
  output [0:0]ddr3_odt;
  output [0:0]ddr3_cke;
  output [7:0]ddr3_dm;
  output A_rst_primitives_reg;
  output A_rst_primitives_reg_0;
  output A_rst_primitives_reg_1;
  output A_rst_primitives_reg_2;
  output A_rst_primitives_reg_3;
  output A_rst_primitives_reg_4;
  output A_rst_primitives_reg_5;
  output A_rst_primitives_reg_6;
  output rst_tmp;
  output po_cnt_dec_reg;
  output po_cnt_dec_2;
  output fine_adjust_reg;
  output new_cnt_cpt_r_reg;
  output rdlvl_stg1_start_reg;
  output samp_edge_cnt0_en_r;
  output pi_cnt_dec_reg;
  output [0:0]E;
  output prbs_rdlvl_done_pulse_reg;
  output init_calib_complete;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_6 ;
  output [11:0]req_bank_r;
  output [19:0]\req_row_r_lcl_reg[13] ;
  output app_rd_data_valid;
  output \init_state_r_reg[4] ;
  output \pointer_ram.pointer_we ;
  output wr_data_en;
  output app_rd_data_end;
  output [3:0]wr_data_addr;
  output [1:0]ddr_ck_out;
  inout [63:0]ddr3_dq;
  inout [7:0]ddr3_dqs_p;
  inout [7:0]ddr3_dqs_n;
  input \last_master_r_reg[2] ;
  input \periodic_read_request.periodic_rd_r_cnt_reg ;
  input \periodic_rd_generation.periodic_rd_cntr1_r_reg ;
  input \zq_cntrl.zq_request_logic.zq_request_r_reg ;
  input [0:0]SR;
  input app_zq_req;
  input app_sr_req;
  input \last_master_r_reg[2]_0 ;
  input use_addr;
  input [1:0]cmd;
  input \inhbt_act_faw.inhbt_act_faw_r_reg ;
  input app_ref_req;
  input mmcm_ps_clk;
  input rst_sync_r1;
  input freq_refclk;
  input mem_refclk;
  input sync_pulse;
  input pll_locked;
  input cal2_if_reset_reg;
  input CLKB0;
  input CLKB0_7;
  input CLKB0_8;
  input CLKB0_9;
  input RST0;
  input CLKB0_10;
  input CLKB0_11;
  input CLKB0_12;
  input CLKB0_13;
  input \rstdiv2_sync_r_reg[11] ;
  input [0:0]iodelay_ctrl_rdy;
  input out;
  input [2:0]S;
  input [0:0]row_hit_r_reg;
  input [0:0]row_hit_r_reg_0;
  input [0:0]row_hit_r_reg_1;
  input [0:0]row_hit_r_reg_2;
  input [0:0]row_hit_r_reg_3;
  input [1:0]\fine_dec_cnt_reg[5] ;
  input [1:0]\corse_inc_reg[6][2] ;
  input \wl_dqs_tap_count_r_reg[0][5][5] ;
  input first_fail_detect_reg;
  input [1:0]\rdlvl_dqs_tap_cnt_r_reg[0][0][2] ;
  input \samp_edge_cnt1_r_reg[0] ;
  input [0:0]\FSM_onehot_cal1_state_r_reg[7] ;
  input \samples_cnt_r_reg[0] ;
  input \en_cnt_div4.enable_wrlvl_cnt_reg[2] ;
  input [0:0]\victim_sel_reg[0] ;
  input \four_dec_min_limit_reg[0] ;
  input \idelay_tap_cnt_r_reg[0][0][4] ;
  input \rtp_timer_r_reg[1] ;
  input \complex_num_writes_reg[1] ;
  input [575:0]Q;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ;
  input rb_hit_busy_r_reg;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[6] ;
  input \rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ;
  input \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] ;
  input [13:0]D;
  input ras_timer_zero_r_reg;
  input ras_timer_zero_r_reg_0;
  input ras_timer_zero_r_reg_1;
  input \rtp_timer_r_reg[0] ;
  input \pi_rst_stg1_cal_r_reg[1] ;
  input \cmp_err_4to1.compare_err_f3_reg ;
  input ram_init_done_r;
  input was_priority_reg;
  input [3:0]\req_data_buf_addr_r_reg[3] ;
  input [2:0]\req_bank_r_lcl_reg[2] ;
  input [9:0]\req_col_r_reg[9] ;
  input [1:0]\fine_inc_reg[6][3] ;
  input [0:0]\corse_dec_reg[7][0] ;
  input [0:0]\smallest_reg[6][0] ;
  input [0:0]SS;
  input [0:0]\wait_cnt_r_reg[0] ;
  input [0:0]\tap_cnt_cpt_r_reg[5] ;
  input [0:0]\cnt_shift_r_reg[0] ;
  input [0:0]\wait_cnt_r_reg[0]_0 ;
  input \en_cnt_div4.enable_wrlvl_cnt_reg[4] ;
  input [11:0]\device_temp_101_reg[11] ;

  wire A_rst_primitives_reg;
  wire A_rst_primitives_reg_0;
  wire A_rst_primitives_reg_1;
  wire A_rst_primitives_reg_2;
  wire A_rst_primitives_reg_3;
  wire A_rst_primitives_reg_4;
  wire A_rst_primitives_reg_5;
  wire A_rst_primitives_reg_6;
  wire CLKB0;
  wire CLKB0_10;
  wire CLKB0_11;
  wire CLKB0_12;
  wire CLKB0_13;
  wire CLKB0_7;
  wire CLKB0_8;
  wire CLKB0_9;
  wire [13:0]D;
  wire [0:0]E;
  wire [0:0]\FSM_onehot_cal1_state_r_reg[7] ;
  wire [575:0]Q;
  wire RST0;
  wire [2:0]S;
  wire [0:0]SR;
  wire [0:0]SS;
  wire accept_ns;
  wire app_rd_data_end;
  wire app_rd_data_valid;
  wire app_ref_ack;
  wire app_ref_req;
  wire app_sr_active;
  wire app_sr_req;
  wire app_zq_ack;
  wire app_zq_req;
  wire bm_end_r1;
  wire bm_end_r1_0;
  wire bm_end_r1_1;
  wire cal2_if_reset_reg;
  wire [1:0]cmd;
  wire \cmp_err_4to1.compare_err_f3_reg ;
  wire [0:0]\cnt_shift_r_reg[0] ;
  wire \col_mach0/p_0_in ;
  wire [0:0]\col_mach0/read_fifo.tail_r ;
  wire \complex_num_writes_reg[1] ;
  wire [0:0]\corse_dec_reg[7][0] ;
  wire [1:0]\corse_inc_reg[6][2] ;
  wire [13:0]ddr3_addr;
  wire [2:0]ddr3_ba;
  wire ddr3_cas_n;
  wire [0:0]ddr3_cke;
  wire [0:0]ddr3_cs_n;
  wire [7:0]ddr3_dm;
  wire [63:0]ddr3_dq;
  wire [7:0]ddr3_dqs_n;
  wire [7:0]ddr3_dqs_p;
  wire [0:0]ddr3_odt;
  wire ddr3_ras_n;
  wire ddr3_reset_n;
  wire ddr3_we_n;
  wire [1:0]ddr_ck_out;
  (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire ddr_phy_top0_n_52;
  (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire ddr_phy_top0_n_53;
  (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire ddr_phy_top0_n_54;
  (* MAX_FANOUT = "50" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire ddr_phy_top0_n_55;
  wire ddr_phy_top0_n_56;
  wire ddr_phy_top0_n_570;
  wire ddr_phy_top0_n_572;
  wire ddr_phy_top0_n_573;
  wire ddr_phy_top0_n_574;
  wire ddr_phy_top0_n_575;
  wire ddr_phy_top0_n_576;
  wire ddr_phy_top0_n_577;
  wire ddr_phy_top0_n_578;
  wire ddr_phy_top0_n_579;
  wire ddr_phy_top0_n_580;
  wire ddr_phy_top0_n_581;
  wire ddr_phy_top0_n_582;
  wire ddr_phy_top0_n_583;
  wire ddr_phy_top0_n_584;
  wire ddr_phy_top0_n_585;
  wire ddr_phy_top0_n_586;
  wire ddr_phy_top0_n_587;
  wire ddr_phy_top0_n_588;
  wire ddr_phy_top0_n_589;
  wire ddr_phy_top0_n_590;
  wire ddr_phy_top0_n_591;
  wire ddr_phy_top0_n_592;
  wire ddr_phy_top0_n_593;
  wire [11:0]\device_temp_101_reg[11] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ;
  wire \en_cnt_div4.enable_wrlvl_cnt_reg[2] ;
  wire \en_cnt_div4.enable_wrlvl_cnt_reg[4] ;
  wire fine_adjust_reg;
  wire [1:0]\fine_dec_cnt_reg[5] ;
  wire [1:0]\fine_inc_reg[6][3] ;
  wire first_fail_detect_reg;
  wire \four_dec_min_limit_reg[0] ;
  wire freq_refclk;
  wire \generate_maint_cmds.insert_maint_r_lcl_reg ;
  wire \idelay_tap_cnt_r_reg[0][0][4] ;
  wire idle;
  wire \inhbt_act_faw.inhbt_act_faw_r_reg ;
  wire init_calib_complete;
  wire \init_state_r_reg[4] ;
  wire [0:0]iodelay_ctrl_rdy;
  wire \last_master_r_reg[2] ;
  wire \last_master_r_reg[2]_0 ;
  wire mc0_n_124;
  wire mc0_n_125;
  wire mc0_n_126;
  wire mc0_n_127;
  wire mc0_n_128;
  wire mc0_n_129;
  wire mc0_n_130;
  wire mc0_n_131;
  wire mc0_n_132;
  wire mc0_n_133;
  wire mc0_n_134;
  wire mc0_n_135;
  wire mc0_n_136;
  wire mc0_n_137;
  wire mc0_n_138;
  wire mc0_n_139;
  wire mc0_n_140;
  wire mc0_n_141;
  wire [41:0]mc_address;
  wire [8:0]mc_bank;
  wire [2:0]mc_cas_n;
  wire [3:3]mc_cke;
  wire [1:0]mc_cmd;
  wire [0:0]mc_cs_n;
  wire [0:0]mc_odt;
  wire [2:0]mc_ras_n;
  wire [2:0]mc_we_n;
  wire mc_wrdata_en;
  wire mem_refclk;
  wire mmcm_ps_clk;
  wire [41:11]mux_address;
  wire [2:0]mux_cas_n;
  wire [2:0]mux_cs_n;
  wire [0:0]mux_ras_n;
  wire [2:0]mux_we_n;
  wire new_cnt_cpt_r_reg;
  wire out;
  wire \periodic_rd_generation.periodic_rd_cntr1_r_reg ;
  wire \periodic_read_request.periodic_rd_r_cnt_reg ;
  wire phy_mc_ctl_full;
  wire phy_mc_data_full;
  wire pi_cnt_dec_reg;
  wire \pi_rst_stg1_cal_r_reg[1] ;
  wire pll_locked;
  wire po_cnt_dec_2;
  wire po_cnt_dec_reg;
  wire \pointer_ram.pointer_we ;
  wire prbs_rdlvl_done_pulse_reg;
  wire ram_init_done_r;
  wire ras_timer_zero_r_reg;
  wire ras_timer_zero_r_reg_0;
  wire ras_timer_zero_r_reg_1;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ;
  wire \rb_hit_busies.rb_hit_busies_r_lcl_reg[6] ;
  wire rb_hit_busy_r_reg;
  wire [1:0]\rdlvl_dqs_tap_cnt_r_reg[0][0][2] ;
  wire rdlvl_stg1_start_reg;
  wire [11:0]req_bank_r;
  wire [2:0]\req_bank_r_lcl_reg[2] ;
  wire [9:0]\req_col_r_reg[9] ;
  wire [3:0]\req_data_buf_addr_r_reg[3] ;
  wire [19:0]\req_row_r_lcl_reg[13] ;
  wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] ;
  wire [0:0]row_hit_r_reg;
  wire [0:0]row_hit_r_reg_0;
  wire [0:0]row_hit_r_reg_1;
  wire [0:0]row_hit_r_reg_2;
  wire [0:0]row_hit_r_reg_3;
  wire rst_sync_r1;
  wire rst_tmp;
  wire \rstdiv2_sync_r_reg[11] ;
  wire \rtp_timer_r_reg[0] ;
  wire \rtp_timer_r_reg[1] ;
  wire samp_edge_cnt0_en_r;
  wire \samp_edge_cnt1_r_reg[0] ;
  wire \samples_cnt_r_reg[0] ;
  wire [0:0]\smallest_reg[6][0] ;
  wire sync_pulse;
  wire [0:0]\tap_cnt_cpt_r_reg[5] ;
  wire tempmon_sample_en;
  wire [1:1]\u_ddr_mc_phy_wrapper/u_ddr_mc_phy/of_ctl_full_v ;
  wire use_addr;
  wire [0:0]\victim_sel_reg[0] ;
  wire [0:0]\wait_cnt_r_reg[0] ;
  wire [0:0]\wait_cnt_r_reg[0]_0 ;
  wire was_priority_reg;
  wire \wl_dqs_tap_count_r_reg[0][5][5] ;
  wire [3:0]wr_data_addr;
  wire wr_data_en;
  wire \zq_cntrl.zq_request_logic.zq_request_r_reg ;

  mig_mig_7series_v4_2_ddr_phy_top ddr_phy_top0
       (.A_rst_primitives_reg(A_rst_primitives_reg),
        .A_rst_primitives_reg_0(A_rst_primitives_reg_0),
        .A_rst_primitives_reg_1(A_rst_primitives_reg_1),
        .A_rst_primitives_reg_2(A_rst_primitives_reg_2),
        .A_rst_primitives_reg_3(A_rst_primitives_reg_3),
        .A_rst_primitives_reg_4(A_rst_primitives_reg_4),
        .A_rst_primitives_reg_5(A_rst_primitives_reg_5),
        .A_rst_primitives_reg_6(A_rst_primitives_reg_6),
        .CLKB0(CLKB0),
        .CLKB0_10(CLKB0_10),
        .CLKB0_11(CLKB0_11),
        .CLKB0_12(CLKB0_12),
        .CLKB0_13(CLKB0_13),
        .CLKB0_7(CLKB0_7),
        .CLKB0_8(CLKB0_8),
        .CLKB0_9(CLKB0_9),
        .\FSM_onehot_cal1_state_r_reg[7] (\FSM_onehot_cal1_state_r_reg[7] ),
        .Q(Q),
        .RST0(RST0),
        .SR(SR),
        .SS(SS),
        .app_rd_data_valid(app_rd_data_valid),
        .app_rd_data_valid_0(\col_mach0/p_0_in ),
        .cal2_if_reset_reg(cal2_if_reset_reg),
        .\cmp_err_4to1.compare_err_f3_reg (\cmp_err_4to1.compare_err_f3_reg ),
        .\cnt_shift_r_reg[0] (\cnt_shift_r_reg[0] ),
        .\complex_num_writes_reg[1] (\complex_num_writes_reg[1] ),
        .\corse_dec_reg[7][0] ({\corse_dec_reg[7][0] ,\smallest_reg[6][0] }),
        .\corse_inc_reg[6][2] (\corse_inc_reg[6][2] ),
        .d_in({mux_address[39],mux_address[11],mux_address[41],mux_address[13]}),
        .\data_offset_1_i1_reg[0] (mc0_n_135),
        .\data_offset_1_i1_reg[1] (mc0_n_134),
        .\data_offset_1_i1_reg[2] (mc0_n_133),
        .\data_offset_1_i1_reg[4] (mc0_n_132),
        .\data_offset_1_i1_reg[5] (mc0_n_131),
        .\data_offset_2_i1_reg[0] (mc0_n_141),
        .\data_offset_2_i1_reg[1] (mc0_n_140),
        .\data_offset_2_i1_reg[2] (mc0_n_139),
        .\data_offset_2_i1_reg[4] (mc0_n_138),
        .\data_offset_2_i1_reg[5] (mc0_n_137),
        .ddr3_addr(ddr3_addr),
        .ddr3_ba(ddr3_ba),
        .ddr3_cas_n(ddr3_cas_n),
        .ddr3_cke(ddr3_cke),
        .ddr3_cs_n(ddr3_cs_n),
        .ddr3_dm(ddr3_dm),
        .ddr3_dq(ddr3_dq),
        .ddr3_dqs_n(ddr3_dqs_n),
        .ddr3_dqs_p(ddr3_dqs_p),
        .ddr3_odt(ddr3_odt),
        .ddr3_ras_n(ddr3_ras_n),
        .ddr3_reset_n(ddr3_reset_n),
        .ddr3_we_n(ddr3_we_n),
        .ddr_ck_out(ddr_ck_out),
        .\device_temp_101_reg[11] (\device_temp_101_reg[11] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ),
        .\en_cnt_div4.enable_wrlvl_cnt_reg[2] (\en_cnt_div4.enable_wrlvl_cnt_reg[2] ),
        .\en_cnt_div4.enable_wrlvl_cnt_reg[4] (\en_cnt_div4.enable_wrlvl_cnt_reg[4] ),
        .\entry_cnt_reg[4] (\last_master_r_reg[2] ),
        .fine_adjust_reg(fine_adjust_reg),
        .\fine_dec_cnt_reg[5] (\fine_dec_cnt_reg[5] ),
        .\fine_inc_reg[6][3] (\fine_inc_reg[6][3] ),
        .first_fail_detect_reg(first_fail_detect_reg),
        .\four_dec_min_limit_reg[0] (\four_dec_min_limit_reg[0] ),
        .freq_refclk(freq_refclk),
        .\idelay_tap_cnt_r_reg[0][0][4] (\idelay_tap_cnt_r_reg[0][0][4] ),
        .\idelay_tap_cnt_r_reg[0][4][4] (\rtp_timer_r_reg[0] ),
        .idle(idle),
        .init_calib_complete(init_calib_complete),
        .init_calib_complete_reg_rep__12(ddr_phy_top0_n_52),
        .init_calib_complete_reg_rep__24(ddr_phy_top0_n_53),
        .init_calib_complete_reg_rep__25(ddr_phy_top0_n_54),
        .init_calib_complete_reg_rep__26(ddr_phy_top0_n_55),
        .init_calib_complete_reg_rep__26_0(ddr_phy_top0_n_570),
        .init_complete_r1_timing_reg(ddr_phy_top0_n_56),
        .\init_state_r_reg[4] (\init_state_r_reg[4] ),
        .iodelay_ctrl_rdy(iodelay_ctrl_rdy),
        .mc_address({mc_address[41:28],mc_address[24:0]}),
        .mc_bank(mc_bank),
        .mc_cas_n(mc_cas_n),
        .mc_cke(mc_cke),
        .mc_cmd(mc_cmd),
        .mc_cs_n(mc_cs_n),
        .mc_data_offset(mc0_n_124),
        .mc_data_offset_1(mc0_n_130),
        .mc_data_offset_2(mc0_n_136),
        .mc_odt(mc_odt),
        .mc_ras_n(mc_ras_n),
        .mc_ref_zq_wip(tempmon_sample_en),
        .mc_we_n(mc_we_n),
        .mc_wrdata_en(mc_wrdata_en),
        .mem_refclk(mem_refclk),
        .mmcm_ps_clk(mmcm_ps_clk),
        .new_cnt_cpt_r_reg(new_cnt_cpt_r_reg),
        .new_cnt_dqs_r_reg(E),
        .\not_empty_wait_cnt_reg[4] (\rtp_timer_r_reg[1] ),
        .of_ctl_full_v(\u_ddr_mc_phy_wrapper/u_ddr_mc_phy/of_ctl_full_v ),
        .\one_dec_max_limit_reg[2] (\periodic_rd_generation.periodic_rd_cntr1_r_reg ),
        .\one_dec_min_limit_reg[11] (\zq_cntrl.zq_request_logic.zq_request_r_reg ),
        .out(out),
        .\phy_ctl_wd_i1_reg[17] (mc0_n_129),
        .\phy_ctl_wd_i1_reg[18] (mc0_n_128),
        .\phy_ctl_wd_i1_reg[19] (mc0_n_127),
        .\phy_ctl_wd_i1_reg[21] (mc0_n_126),
        .\phy_ctl_wd_i1_reg[22] (mc0_n_125),
        .phy_dout({mux_we_n[2],mux_we_n[0],mux_cs_n[2],mux_ras_n,mux_cas_n[2],mux_cas_n[0],mux_cs_n[0]}),
        .phy_mc_ctl_full(phy_mc_ctl_full),
        .phy_mc_data_full(phy_mc_data_full),
        .pi_cnt_dec_reg(pi_cnt_dec_reg),
        .\pi_rst_stg1_cal_r_reg[1] (\pi_rst_stg1_cal_r_reg[1] ),
        .pll_locked(pll_locked),
        .po_cnt_dec_2(po_cnt_dec_2),
        .po_cnt_dec_reg(po_cnt_dec_reg),
        .po_en_stg2_f_reg(\periodic_read_request.periodic_rd_r_cnt_reg ),
        .prbs_rdlvl_done_pulse_reg(prbs_rdlvl_done_pulse_reg),
        .\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][0] (ddr_phy_top0_n_573),
        .\rank_final_loop[0].bank_final_loop[0].final_data_offset_mc_reg[0][5] ({ddr_phy_top0_n_574,ddr_phy_top0_n_575,ddr_phy_top0_n_576,ddr_phy_top0_n_577,ddr_phy_top0_n_578,ddr_phy_top0_n_579}),
        .\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][11] ({ddr_phy_top0_n_581,ddr_phy_top0_n_582,ddr_phy_top0_n_583,ddr_phy_top0_n_584,ddr_phy_top0_n_585,ddr_phy_top0_n_586}),
        .\rank_final_loop[0].bank_final_loop[1].final_data_offset_mc_reg[0][6] (ddr_phy_top0_n_580),
        .\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][12] (ddr_phy_top0_n_587),
        .\rank_final_loop[0].bank_final_loop[2].final_data_offset_mc_reg[0][17] ({ddr_phy_top0_n_588,ddr_phy_top0_n_589,ddr_phy_top0_n_590,ddr_phy_top0_n_591,ddr_phy_top0_n_592,ddr_phy_top0_n_593}),
        .\rdlvl_dqs_tap_cnt_r_reg[0][0][2] (\rdlvl_dqs_tap_cnt_r_reg[0][0][2] ),
        .rdlvl_stg1_start_reg(rdlvl_stg1_start_reg),
        .\read_fifo.tail_r (\col_mach0/read_fifo.tail_r ),
        .\read_fifo.tail_r_reg[0] (ddr_phy_top0_n_572),
        .rst_sync_r1(rst_sync_r1),
        .rst_tmp(rst_tmp),
        .\rstdiv2_sync_r_reg[11] (\rstdiv2_sync_r_reg[11] ),
        .samp_edge_cnt0_en_r(samp_edge_cnt0_en_r),
        .\samp_edge_cnt1_r_reg[0] (\samp_edge_cnt1_r_reg[0] ),
        .\samples_cnt_r_reg[0] (\samples_cnt_r_reg[0] ),
        .sync_pulse(sync_pulse),
        .\tap_cnt_cpt_r_reg[5] (\tap_cnt_cpt_r_reg[5] ),
        .\victim_sel_reg[0] (\victim_sel_reg[0] ),
        .\wait_cnt_r_reg[0] (\wait_cnt_r_reg[0] ),
        .\wait_cnt_r_reg[0]_0 (\wait_cnt_r_reg[0]_0 ),
        .\wl_dqs_tap_count_r_reg[0][5][5] (\wl_dqs_tap_count_r_reg[0][5][5] ));
  mig_mig_7series_v4_2_mc mc0
       (.D(D),
        .Q({mc_address[41:28],mc_address[24:0]}),
        .S(S),
        .SR(SR),
        .accept_ns(accept_ns),
        .app_ref_ack(app_ref_ack),
        .app_ref_req(app_ref_req),
        .app_sr_active(app_sr_active),
        .app_sr_req(app_sr_req),
        .app_zq_ack(app_zq_ack),
        .app_zq_req(app_zq_req),
        .bm_end_r1(bm_end_r1),
        .bm_end_r1_0(bm_end_r1_0),
        .bm_end_r1_1(bm_end_r1_1),
        .cmd(cmd),
        .\cmd_pipe_plus.mc_bank_reg[8]_0 (mc_bank),
        .\cmd_pipe_plus.mc_data_offset_1_reg[0]_0 (mc0_n_135),
        .\cmd_pipe_plus.mc_data_offset_1_reg[0]_1 (ddr_phy_top0_n_580),
        .\cmd_pipe_plus.mc_data_offset_1_reg[1]_0 (mc0_n_134),
        .\cmd_pipe_plus.mc_data_offset_1_reg[2]_0 (mc0_n_133),
        .\cmd_pipe_plus.mc_data_offset_1_reg[3]_0 (mc0_n_130),
        .\cmd_pipe_plus.mc_data_offset_1_reg[4]_0 (mc0_n_132),
        .\cmd_pipe_plus.mc_data_offset_1_reg[5]_0 (mc0_n_131),
        .\cmd_pipe_plus.mc_data_offset_1_reg[5]_1 ({ddr_phy_top0_n_581,ddr_phy_top0_n_582,ddr_phy_top0_n_583,ddr_phy_top0_n_584,ddr_phy_top0_n_585,ddr_phy_top0_n_586}),
        .\cmd_pipe_plus.mc_data_offset_2_reg[0]_0 (mc0_n_141),
        .\cmd_pipe_plus.mc_data_offset_2_reg[0]_1 (ddr_phy_top0_n_587),
        .\cmd_pipe_plus.mc_data_offset_2_reg[1]_0 (mc0_n_140),
        .\cmd_pipe_plus.mc_data_offset_2_reg[2]_0 (mc0_n_139),
        .\cmd_pipe_plus.mc_data_offset_2_reg[3]_0 (mc0_n_136),
        .\cmd_pipe_plus.mc_data_offset_2_reg[4]_0 (mc0_n_138),
        .\cmd_pipe_plus.mc_data_offset_2_reg[5]_0 (mc0_n_137),
        .\cmd_pipe_plus.mc_data_offset_2_reg[5]_1 ({ddr_phy_top0_n_588,ddr_phy_top0_n_589,ddr_phy_top0_n_590,ddr_phy_top0_n_591,ddr_phy_top0_n_592,ddr_phy_top0_n_593}),
        .\cmd_pipe_plus.mc_data_offset_reg[0]_0 (mc0_n_129),
        .\cmd_pipe_plus.mc_data_offset_reg[0]_1 (ddr_phy_top0_n_573),
        .\cmd_pipe_plus.mc_data_offset_reg[1]_0 (mc0_n_128),
        .\cmd_pipe_plus.mc_data_offset_reg[2]_0 (mc0_n_127),
        .\cmd_pipe_plus.mc_data_offset_reg[3]_0 (mc0_n_124),
        .\cmd_pipe_plus.mc_data_offset_reg[4]_0 (mc0_n_126),
        .\cmd_pipe_plus.mc_data_offset_reg[5]_0 (mc0_n_125),
        .\cmd_pipe_plus.mc_data_offset_reg[5]_1 ({ddr_phy_top0_n_574,ddr_phy_top0_n_575,ddr_phy_top0_n_576,ddr_phy_top0_n_577,ddr_phy_top0_n_578,ddr_phy_top0_n_579}),
        .d_in({mux_address[39],mux_address[11],mux_address[41],mux_address[13]}),
        .\generate_maint_cmds.insert_maint_r_lcl_reg (\generate_maint_cmds.insert_maint_r_lcl_reg ),
        .\grant_r_reg[0] (ddr_phy_top0_n_55),
        .idle(idle),
        .\inhbt_act_faw.inhbt_act_faw_r_reg (\inhbt_act_faw.inhbt_act_faw_r_reg ),
        .\last_master_r_reg[2] (\last_master_r_reg[2] ),
        .\last_master_r_reg[2]_0 (\last_master_r_reg[2]_0 ),
        .mc_cas_n(mc_cas_n),
        .mc_cke(mc_cke),
        .mc_cmd(mc_cmd),
        .mc_cs_n(mc_cs_n),
        .mc_odt(mc_odt),
        .mc_ras_n(mc_ras_n),
        .mc_ref_zq_wip(tempmon_sample_en),
        .mc_we_n(mc_we_n),
        .mc_wrdata_en(mc_wrdata_en),
        .mem_reg_0_15_36_41(ddr_phy_top0_n_54),
        .mem_reg_0_15_42_47(ddr_phy_top0_n_53),
        .of_ctl_full_v(\u_ddr_mc_phy_wrapper/u_ddr_mc_phy/of_ctl_full_v ),
        .\periodic_rd_generation.periodic_rd_cntr1_r_reg (\periodic_rd_generation.periodic_rd_cntr1_r_reg ),
        .\periodic_rd_generation.periodic_rd_timer_r_reg[2] (ddr_phy_top0_n_52),
        .\periodic_read_request.periodic_rd_r_cnt_reg (\periodic_read_request.periodic_rd_r_cnt_reg ),
        .\periodic_read_request.periodic_rd_r_lcl_reg (ddr_phy_top0_n_570),
        .phy_dout({mux_we_n[2],mux_we_n[0],mux_cs_n[2],mux_ras_n,mux_cas_n[2],mux_cas_n[0],mux_cs_n[0]}),
        .phy_mc_ctl_full(phy_mc_ctl_full),
        .phy_mc_data_full(phy_mc_data_full),
        .\pointer_ram.pointer_we (\pointer_ram.pointer_we ),
        .ram_init_done_r(ram_init_done_r),
        .ras_timer_zero_r_reg(ras_timer_zero_r_reg),
        .ras_timer_zero_r_reg_0(ras_timer_zero_r_reg_0),
        .ras_timer_zero_r_reg_1(ras_timer_zero_r_reg_1),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] (\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] (\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] ),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[6] (\rb_hit_busies.rb_hit_busies_r_lcl_reg[6] ),
        .rb_hit_busy_r_reg(rb_hit_busy_r_reg),
        .\read_fifo.fifo_out_data_r_reg[7] ({app_rd_data_end,\col_mach0/p_0_in }),
        .\read_fifo.tail_r_reg[0] (\col_mach0/read_fifo.tail_r ),
        .\read_fifo.tail_r_reg[0]_0 (ddr_phy_top0_n_572),
        .\read_fifo.tail_r_reg[2] (ddr_phy_top0_n_56),
        .\req_bank_r_lcl_reg[2] (req_bank_r[2:0]),
        .\req_bank_r_lcl_reg[2]_0 (req_bank_r[5:3]),
        .\req_bank_r_lcl_reg[2]_1 (req_bank_r[8:6]),
        .\req_bank_r_lcl_reg[2]_2 (req_bank_r[11:9]),
        .\req_bank_r_lcl_reg[2]_3 (\req_bank_r_lcl_reg[2] ),
        .\req_col_r_reg[9] (\req_col_r_reg[9] ),
        .\req_data_buf_addr_r_reg[3] (\req_data_buf_addr_r_reg[3] ),
        .\req_row_r_lcl_reg[13] (\req_row_r_lcl_reg[13] ),
        .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] (\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] ),
        .row_hit_r_reg(row_hit_r_reg),
        .row_hit_r_reg_0(row_hit_r_reg_0),
        .row_hit_r_reg_1(row_hit_r_reg_1),
        .row_hit_r_reg_2(row_hit_r_reg_2),
        .row_hit_r_reg_3(row_hit_r_reg_3),
        .\rtp_timer_r_reg[0] (\rtp_timer_r_reg[0] ),
        .\rtp_timer_r_reg[1] (\rtp_timer_r_reg[1] ),
        .use_addr(use_addr),
        .was_priority_reg(was_priority_reg),
        .wr_data_addr(wr_data_addr),
        .wr_data_en(wr_data_en),
        .\zq_cntrl.zq_request_logic.zq_request_r_reg (\zq_cntrl.zq_request_logic.zq_request_r_reg ));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_memc_ui_top_std" *) 
module mig_mig_7series_v4_2_memc_ui_top_std
   (app_ref_ack,
    app_zq_ack,
    insert_maint_r,
    bm_end_r1,
    bm_end_r1_0,
    bm_end_r1_1,
    app_sr_active,
    ddr3_reset_n,
    ddr3_cas_n,
    ddr3_ras_n,
    ddr3_we_n,
    ddr3_addr,
    ddr3_ba,
    ddr3_cs_n,
    ddr3_odt,
    ddr3_cke,
    ddr3_dm,
    E,
    app_wdf_rdy,
    A_rst_primitives_reg,
    A_rst_primitives_reg_0,
    A_rst_primitives_reg_1,
    A_rst_primitives_reg_2,
    A_rst_primitives_reg_3,
    A_rst_primitives_reg_4,
    A_rst_primitives_reg_5,
    A_rst_primitives_reg_6,
    rst_tmp,
    po_cnt_dec,
    po_cnt_dec_2,
    fine_adjust_reg,
    new_cnt_cpt_r_reg,
    rdlvl_stg1_start_reg,
    samp_edge_cnt0_en_r,
    pi_cnt_dec,
    new_cnt_dqs_r_reg,
    prbs_rdlvl_done_pulse,
    init_calib_complete,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_6 ,
    app_rd_data_valid,
    \init_state_r_reg[4] ,
    app_rd_data_end,
    ddr_ck_out,
    ddr3_dq,
    ddr3_dqs_p,
    ddr3_dqs_n,
    \wr_req_counter.wr_req_cnt_r_reg[0] ,
    \periodic_read_request.periodic_rd_r_cnt_reg ,
    \periodic_rd_generation.periodic_rd_cntr1_r_reg ,
    \zq_cntrl.zq_request_logic.zq_request_r_reg ,
    SR,
    app_zq_req,
    app_sr_req,
    \last_master_r_reg[2] ,
    reset_reg_0,
    app_ref_req,
    mmcm_ps_clk,
    rst_sync_r1,
    freq_refclk,
    mem_refclk,
    sync_pulse,
    pll_locked,
    cal2_if_reset_reg,
    CLKB0,
    CLKB0_7,
    CLKB0_8,
    CLKB0_9,
    RST0,
    CLKB0_10,
    CLKB0_11,
    CLKB0_12,
    CLKB0_13,
    \rstdiv2_sync_r_reg[11] ,
    iodelay_ctrl_rdy,
    out,
    \fine_dec_cnt_reg[5] ,
    \corse_inc_reg[6][2] ,
    \wl_dqs_tap_count_r_reg[0][5][5] ,
    first_fail_detect_reg,
    \rdlvl_dqs_tap_cnt_r_reg[0][0][2] ,
    \samp_edge_cnt1_r_reg[0] ,
    \FSM_onehot_cal1_state_r_reg[7] ,
    \samples_cnt_r_reg[0] ,
    \en_cnt_div4.enable_wrlvl_cnt_reg[2] ,
    \victim_sel_reg[0] ,
    \four_dec_min_limit_reg[0] ,
    \idelay_tap_cnt_r_reg[0][0][4] ,
    \rtp_timer_r_reg[1] ,
    \complex_num_writes_reg[1] ,
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] ,
    ras_timer_zero_r_reg,
    ras_timer_zero_r_reg_0,
    ras_timer_zero_r_reg_1,
    \rtp_timer_r_reg[0] ,
    \pi_rst_stg1_cal_r_reg[1] ,
    \cmp_err_4to1.compare_err_f3_reg ,
    app_addr,
    app_cmd,
    app_wdf_data,
    app_wdf_mask,
    \fine_inc_reg[6][3] ,
    \wl_dqs_tap_count_r_reg[0][6][3] ,
    \corse_dec_reg[7][0] ,
    SS,
    \wait_cnt_r_reg[0] ,
    \tap_cnt_cpt_r_reg[5] ,
    \cnt_shift_r_reg[0] ,
    \wait_cnt_r_reg[0]_0 ,
    \en_cnt_div4.enable_wrlvl_cnt_reg[4] ,
    D,
    app_en,
    app_wdf_wren,
    app_wdf_end);
  output app_ref_ack;
  output app_zq_ack;
  output insert_maint_r;
  output bm_end_r1;
  output bm_end_r1_0;
  output bm_end_r1_1;
  output app_sr_active;
  output ddr3_reset_n;
  output ddr3_cas_n;
  output ddr3_ras_n;
  output ddr3_we_n;
  output [13:0]ddr3_addr;
  output [2:0]ddr3_ba;
  output [0:0]ddr3_cs_n;
  output [0:0]ddr3_odt;
  output [0:0]ddr3_cke;
  output [7:0]ddr3_dm;
  output [0:0]E;
  output app_wdf_rdy;
  output A_rst_primitives_reg;
  output A_rst_primitives_reg_0;
  output A_rst_primitives_reg_1;
  output A_rst_primitives_reg_2;
  output A_rst_primitives_reg_3;
  output A_rst_primitives_reg_4;
  output A_rst_primitives_reg_5;
  output A_rst_primitives_reg_6;
  output rst_tmp;
  output po_cnt_dec;
  output po_cnt_dec_2;
  output fine_adjust_reg;
  output new_cnt_cpt_r_reg;
  output rdlvl_stg1_start_reg;
  output samp_edge_cnt0_en_r;
  output pi_cnt_dec;
  output new_cnt_dqs_r_reg;
  output prbs_rdlvl_done_pulse;
  output init_calib_complete;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_6 ;
  output app_rd_data_valid;
  output \init_state_r_reg[4] ;
  output app_rd_data_end;
  output [1:0]ddr_ck_out;
  inout [63:0]ddr3_dq;
  inout [7:0]ddr3_dqs_p;
  inout [7:0]ddr3_dqs_n;
  input \wr_req_counter.wr_req_cnt_r_reg[0] ;
  input \periodic_read_request.periodic_rd_r_cnt_reg ;
  input \periodic_rd_generation.periodic_rd_cntr1_r_reg ;
  input \zq_cntrl.zq_request_logic.zq_request_r_reg ;
  input [0:0]SR;
  input app_zq_req;
  input app_sr_req;
  input \last_master_r_reg[2] ;
  input reset_reg_0;
  input app_ref_req;
  input mmcm_ps_clk;
  input rst_sync_r1;
  input freq_refclk;
  input mem_refclk;
  input sync_pulse;
  input pll_locked;
  input cal2_if_reset_reg;
  input CLKB0;
  input CLKB0_7;
  input CLKB0_8;
  input CLKB0_9;
  input RST0;
  input CLKB0_10;
  input CLKB0_11;
  input CLKB0_12;
  input CLKB0_13;
  input \rstdiv2_sync_r_reg[11] ;
  input [0:0]iodelay_ctrl_rdy;
  input out;
  input [1:0]\fine_dec_cnt_reg[5] ;
  input [1:0]\corse_inc_reg[6][2] ;
  input \wl_dqs_tap_count_r_reg[0][5][5] ;
  input first_fail_detect_reg;
  input [1:0]\rdlvl_dqs_tap_cnt_r_reg[0][0][2] ;
  input \samp_edge_cnt1_r_reg[0] ;
  input [0:0]\FSM_onehot_cal1_state_r_reg[7] ;
  input \samples_cnt_r_reg[0] ;
  input \en_cnt_div4.enable_wrlvl_cnt_reg[2] ;
  input [0:0]\victim_sel_reg[0] ;
  input \four_dec_min_limit_reg[0] ;
  input \idelay_tap_cnt_r_reg[0][0][4] ;
  input \rtp_timer_r_reg[1] ;
  input \complex_num_writes_reg[1] ;
  input \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] ;
  input ras_timer_zero_r_reg;
  input ras_timer_zero_r_reg_0;
  input ras_timer_zero_r_reg_1;
  input \rtp_timer_r_reg[0] ;
  input \pi_rst_stg1_cal_r_reg[1] ;
  input \cmp_err_4to1.compare_err_f3_reg ;
  input [26:0]app_addr;
  input [1:0]app_cmd;
  input [511:0]app_wdf_data;
  input [63:0]app_wdf_mask;
  input [0:0]\fine_inc_reg[6][3] ;
  input [1:0]\wl_dqs_tap_count_r_reg[0][6][3] ;
  input [0:0]\corse_dec_reg[7][0] ;
  input [0:0]SS;
  input [0:0]\wait_cnt_r_reg[0] ;
  input [0:0]\tap_cnt_cpt_r_reg[5] ;
  input [0:0]\cnt_shift_r_reg[0] ;
  input [0:0]\wait_cnt_r_reg[0]_0 ;
  input \en_cnt_div4.enable_wrlvl_cnt_reg[4] ;
  input [11:0]D;
  input app_en;
  input app_wdf_wren;
  input app_wdf_end;

  wire A_rst_primitives_reg;
  wire A_rst_primitives_reg_0;
  wire A_rst_primitives_reg_1;
  wire A_rst_primitives_reg_2;
  wire A_rst_primitives_reg_3;
  wire A_rst_primitives_reg_4;
  wire A_rst_primitives_reg_5;
  wire A_rst_primitives_reg_6;
  wire CLKB0;
  wire CLKB0_10;
  wire CLKB0_11;
  wire CLKB0_12;
  wire CLKB0_13;
  wire CLKB0_7;
  wire CLKB0_8;
  wire CLKB0_9;
  wire [11:0]D;
  wire [0:0]E;
  wire [0:0]\FSM_onehot_cal1_state_r_reg[7] ;
  wire RST0;
  wire [0:0]SR;
  wire [0:0]SS;
  wire accept_ns;
  wire [26:0]app_addr;
  wire [1:0]app_cmd;
  wire app_en;
  wire app_rd_data_end;
  wire app_rd_data_valid;
  wire app_ref_ack;
  wire app_ref_req;
  wire app_sr_active;
  wire app_sr_req;
  wire [511:0]app_wdf_data;
  wire app_wdf_end;
  wire [63:0]app_wdf_mask;
  wire app_wdf_rdy;
  wire app_wdf_wren;
  wire app_zq_ack;
  wire app_zq_req;
  wire [2:0]bank;
  wire bm_end_r1;
  wire bm_end_r1_0;
  wire bm_end_r1_1;
  wire cal2_if_reset_reg;
  wire [1:0]cmd;
  wire \cmp_err_4to1.compare_err_f3_reg ;
  wire [0:0]\cnt_shift_r_reg[0] ;
  wire [9:0]col;
  wire \complex_num_writes_reg[1] ;
  wire [0:0]\corse_dec_reg[7][0] ;
  wire [1:0]\corse_inc_reg[6][2] ;
  wire [3:0]data_buf_addr;
  wire [13:0]ddr3_addr;
  wire [2:0]ddr3_ba;
  wire ddr3_cas_n;
  wire [0:0]ddr3_cke;
  wire [0:0]ddr3_cs_n;
  wire [7:0]ddr3_dm;
  wire [63:0]ddr3_dq;
  wire [7:0]ddr3_dqs_n;
  wire [7:0]ddr3_dqs_p;
  wire [0:0]ddr3_odt;
  wire ddr3_ras_n;
  wire ddr3_reset_n;
  wire ddr3_we_n;
  wire [1:0]ddr_ck_out;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ;
  wire \en_cnt_div4.enable_wrlvl_cnt_reg[2] ;
  wire \en_cnt_div4.enable_wrlvl_cnt_reg[4] ;
  wire fine_adjust_reg;
  wire [1:0]\fine_dec_cnt_reg[5] ;
  wire [0:0]\fine_inc_reg[6][3] ;
  wire first_fail_detect_reg;
  wire \four_dec_min_limit_reg[0] ;
  wire freq_refclk;
  wire \idelay_tap_cnt_r_reg[0][0][4] ;
  wire init_calib_complete;
  wire \init_state_r_reg[4] ;
  wire insert_maint_r;
  wire [0:0]iodelay_ctrl_rdy;
  wire \last_master_r_reg[2] ;
  wire [11:0]\mc0/bank_mach0/req_bank_r ;
  wire [55:0]\mc0/bank_mach0/req_row_r ;
  wire mem_refclk;
  wire mmcm_ps_clk;
  wire new_cnt_cpt_r_reg;
  wire new_cnt_dqs_r_reg;
  wire out;
  wire \periodic_rd_generation.periodic_rd_cntr1_r_reg ;
  wire \periodic_read_request.periodic_rd_r_cnt_reg ;
  wire pi_cnt_dec;
  wire \pi_rst_stg1_cal_r_reg[1] ;
  wire pll_locked;
  wire po_cnt_dec;
  wire po_cnt_dec_2;
  wire prbs_rdlvl_done_pulse;
  wire ram_init_done_r;
  wire ras_timer_zero_r_reg;
  wire ras_timer_zero_r_reg_0;
  wire ras_timer_zero_r_reg_1;
  wire [1:0]\rdlvl_dqs_tap_cnt_r_reg[0][0][2] ;
  wire rdlvl_stg1_start_reg;
  wire reset_reg_0;
  wire reset_reg_n_0;
  wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] ;
  wire [13:0]row;
  wire rst_sync_r1;
  wire rst_tmp;
  wire \rstdiv2_sync_r_reg[11] ;
  wire \rtp_timer_r_reg[0] ;
  wire \rtp_timer_r_reg[1] ;
  wire samp_edge_cnt0_en_r;
  wire \samp_edge_cnt1_r_reg[0] ;
  wire \samples_cnt_r_reg[0] ;
  wire sync_pulse;
  wire [0:0]\tap_cnt_cpt_r_reg[5] ;
  wire u_ui_top_n_18;
  wire u_ui_top_n_19;
  wire u_ui_top_n_20;
  wire u_ui_top_n_21;
  wire u_ui_top_n_22;
  wire u_ui_top_n_23;
  wire u_ui_top_n_24;
  wire u_ui_top_n_25;
  wire u_ui_top_n_29;
  wire u_ui_top_n_3;
  wire u_ui_top_n_30;
  wire u_ui_top_n_31;
  wire \ui_wr_data0/pointer_ram.pointer_we ;
  wire use_addr;
  wire [0:0]\victim_sel_reg[0] ;
  wire [0:0]\wait_cnt_r_reg[0] ;
  wire [0:0]\wait_cnt_r_reg[0]_0 ;
  wire \wl_dqs_tap_count_r_reg[0][5][5] ;
  wire [1:0]\wl_dqs_tap_count_r_reg[0][6][3] ;
  wire [511:0]wr_data;
  wire [3:0]wr_data_addr;
  wire wr_data_en;
  wire [63:0]wr_data_mask;
  wire \wr_req_counter.wr_req_cnt_r_reg[0] ;
  wire \zq_cntrl.zq_request_logic.zq_request_r_reg ;

  mig_mig_7series_v4_2_mem_intfc mem_intfc0
       (.A_rst_primitives_reg(A_rst_primitives_reg),
        .A_rst_primitives_reg_0(A_rst_primitives_reg_0),
        .A_rst_primitives_reg_1(A_rst_primitives_reg_1),
        .A_rst_primitives_reg_2(A_rst_primitives_reg_2),
        .A_rst_primitives_reg_3(A_rst_primitives_reg_3),
        .A_rst_primitives_reg_4(A_rst_primitives_reg_4),
        .A_rst_primitives_reg_5(A_rst_primitives_reg_5),
        .A_rst_primitives_reg_6(A_rst_primitives_reg_6),
        .CLKB0(CLKB0),
        .CLKB0_10(CLKB0_10),
        .CLKB0_11(CLKB0_11),
        .CLKB0_12(CLKB0_12),
        .CLKB0_13(CLKB0_13),
        .CLKB0_7(CLKB0_7),
        .CLKB0_8(CLKB0_8),
        .CLKB0_9(CLKB0_9),
        .D(row),
        .E(new_cnt_dqs_r_reg),
        .\FSM_onehot_cal1_state_r_reg[7] (\FSM_onehot_cal1_state_r_reg[7] ),
        .Q({wr_data_mask,wr_data}),
        .RST0(RST0),
        .S({u_ui_top_n_21,u_ui_top_n_22,u_ui_top_n_23}),
        .SR(SR),
        .SS(SS),
        .accept_ns(accept_ns),
        .app_rd_data_end(app_rd_data_end),
        .app_rd_data_valid(app_rd_data_valid),
        .app_ref_ack(app_ref_ack),
        .app_ref_req(app_ref_req),
        .app_sr_active(app_sr_active),
        .app_sr_req(app_sr_req),
        .app_zq_ack(app_zq_ack),
        .app_zq_req(app_zq_req),
        .bm_end_r1(bm_end_r1),
        .bm_end_r1_0(bm_end_r1_0),
        .bm_end_r1_1(bm_end_r1_1),
        .cal2_if_reset_reg(cal2_if_reset_reg),
        .cmd(cmd),
        .\cmp_err_4to1.compare_err_f3_reg (\cmp_err_4to1.compare_err_f3_reg ),
        .\cnt_shift_r_reg[0] (\cnt_shift_r_reg[0] ),
        .\complex_num_writes_reg[1] (\complex_num_writes_reg[1] ),
        .\corse_dec_reg[7][0] (\corse_dec_reg[7][0] ),
        .\corse_inc_reg[6][2] (\corse_inc_reg[6][2] ),
        .ddr3_addr(ddr3_addr),
        .ddr3_ba(ddr3_ba),
        .ddr3_cas_n(ddr3_cas_n),
        .ddr3_cke(ddr3_cke),
        .ddr3_cs_n(ddr3_cs_n),
        .ddr3_dm(ddr3_dm),
        .ddr3_dq(ddr3_dq),
        .ddr3_dqs_n(ddr3_dqs_n),
        .ddr3_dqs_p(ddr3_dqs_p),
        .ddr3_odt(ddr3_odt),
        .ddr3_ras_n(ddr3_ras_n),
        .ddr3_reset_n(ddr3_reset_n),
        .ddr3_we_n(ddr3_we_n),
        .ddr_ck_out(ddr_ck_out),
        .\device_temp_101_reg[11] (D),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ),
        .\en_cnt_div4.enable_wrlvl_cnt_reg[2] (\en_cnt_div4.enable_wrlvl_cnt_reg[2] ),
        .\en_cnt_div4.enable_wrlvl_cnt_reg[4] (\en_cnt_div4.enable_wrlvl_cnt_reg[4] ),
        .fine_adjust_reg(fine_adjust_reg),
        .\fine_dec_cnt_reg[5] (\fine_dec_cnt_reg[5] ),
        .\fine_inc_reg[6][3] ({\fine_inc_reg[6][3] ,\wl_dqs_tap_count_r_reg[0][6][3] [1]}),
        .first_fail_detect_reg(first_fail_detect_reg),
        .\four_dec_min_limit_reg[0] (\four_dec_min_limit_reg[0] ),
        .freq_refclk(freq_refclk),
        .\generate_maint_cmds.insert_maint_r_lcl_reg (insert_maint_r),
        .\idelay_tap_cnt_r_reg[0][0][4] (\idelay_tap_cnt_r_reg[0][0][4] ),
        .\inhbt_act_faw.inhbt_act_faw_r_reg (reset_reg_0),
        .init_calib_complete(init_calib_complete),
        .\init_state_r_reg[4] (\init_state_r_reg[4] ),
        .iodelay_ctrl_rdy(iodelay_ctrl_rdy),
        .\last_master_r_reg[2] (\wr_req_counter.wr_req_cnt_r_reg[0] ),
        .\last_master_r_reg[2]_0 (\last_master_r_reg[2] ),
        .mem_refclk(mem_refclk),
        .mmcm_ps_clk(mmcm_ps_clk),
        .new_cnt_cpt_r_reg(new_cnt_cpt_r_reg),
        .out(out),
        .\periodic_rd_generation.periodic_rd_cntr1_r_reg (\periodic_rd_generation.periodic_rd_cntr1_r_reg ),
        .\periodic_read_request.periodic_rd_r_cnt_reg (\periodic_read_request.periodic_rd_r_cnt_reg ),
        .pi_cnt_dec_reg(pi_cnt_dec),
        .\pi_rst_stg1_cal_r_reg[1] (\pi_rst_stg1_cal_r_reg[1] ),
        .pll_locked(pll_locked),
        .po_cnt_dec_2(po_cnt_dec_2),
        .po_cnt_dec_reg(po_cnt_dec),
        .\pointer_ram.pointer_we (\ui_wr_data0/pointer_ram.pointer_we ),
        .prbs_rdlvl_done_pulse_reg(prbs_rdlvl_done_pulse),
        .ram_init_done_r(ram_init_done_r),
        .ras_timer_zero_r_reg(ras_timer_zero_r_reg),
        .ras_timer_zero_r_reg_0(ras_timer_zero_r_reg_0),
        .ras_timer_zero_r_reg_1(ras_timer_zero_r_reg_1),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[4] (u_ui_top_n_25),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[5] (u_ui_top_n_29),
        .\rb_hit_busies.rb_hit_busies_r_lcl_reg[6] (u_ui_top_n_30),
        .rb_hit_busy_r_reg(u_ui_top_n_31),
        .\rdlvl_dqs_tap_cnt_r_reg[0][0][2] (\rdlvl_dqs_tap_cnt_r_reg[0][0][2] ),
        .rdlvl_stg1_start_reg(rdlvl_stg1_start_reg),
        .req_bank_r(\mc0/bank_mach0/req_bank_r ),
        .\req_bank_r_lcl_reg[2] (bank),
        .\req_col_r_reg[9] (col),
        .\req_data_buf_addr_r_reg[3] (data_buf_addr),
        .\req_row_r_lcl_reg[13] ({\mc0/bank_mach0/req_row_r [55:54],\mc0/bank_mach0/req_row_r [41:40],\mc0/bank_mach0/req_row_r [27:23],\mc0/bank_mach0/req_row_r [13:12],\mc0/bank_mach0/req_row_r [8:0]}),
        .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] (\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] ),
        .row_hit_r_reg(u_ui_top_n_3),
        .row_hit_r_reg_0(u_ui_top_n_24),
        .row_hit_r_reg_1(u_ui_top_n_18),
        .row_hit_r_reg_2(u_ui_top_n_19),
        .row_hit_r_reg_3(u_ui_top_n_20),
        .rst_sync_r1(rst_sync_r1),
        .rst_tmp(rst_tmp),
        .\rstdiv2_sync_r_reg[11] (\rstdiv2_sync_r_reg[11] ),
        .\rtp_timer_r_reg[0] (\rtp_timer_r_reg[0] ),
        .\rtp_timer_r_reg[1] (\rtp_timer_r_reg[1] ),
        .samp_edge_cnt0_en_r(samp_edge_cnt0_en_r),
        .\samp_edge_cnt1_r_reg[0] (\samp_edge_cnt1_r_reg[0] ),
        .\samples_cnt_r_reg[0] (\samples_cnt_r_reg[0] ),
        .\smallest_reg[6][0] (\wl_dqs_tap_count_r_reg[0][6][3] [0]),
        .sync_pulse(sync_pulse),
        .\tap_cnt_cpt_r_reg[5] (\tap_cnt_cpt_r_reg[5] ),
        .use_addr(use_addr),
        .\victim_sel_reg[0] (\victim_sel_reg[0] ),
        .\wait_cnt_r_reg[0] (\wait_cnt_r_reg[0] ),
        .\wait_cnt_r_reg[0]_0 (\wait_cnt_r_reg[0]_0 ),
        .was_priority_reg(E),
        .\wl_dqs_tap_count_r_reg[0][5][5] (\wl_dqs_tap_count_r_reg[0][5][5] ),
        .wr_data_addr(wr_data_addr),
        .wr_data_en(wr_data_en),
        .\zq_cntrl.zq_request_logic.zq_request_r_reg (\zq_cntrl.zq_request_logic.zq_request_r_reg ));
  (* syn_maxfan = "10" *) 
  FDRE reset_reg
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0] ),
        .CE(1'b1),
        .D(reset_reg_0),
        .Q(reset_reg_n_0),
        .R(1'b0));
  mig_mig_7series_v4_2_ui_top u_ui_top
       (.D(row),
        .E(wr_data_en),
        .Q({wr_data_mask,wr_data}),
        .S({u_ui_top_n_21,u_ui_top_n_22,u_ui_top_n_23}),
        .accept_ns(accept_ns),
        .app_addr(app_addr),
        .\app_addr_r1_reg[23] (u_ui_top_n_3),
        .\app_addr_r1_reg[23]_0 (u_ui_top_n_18),
        .\app_addr_r1_reg[23]_1 (u_ui_top_n_19),
        .\app_addr_r1_reg[23]_2 (u_ui_top_n_20),
        .\app_addr_r1_reg[26] (bank),
        .\app_addr_r1_reg[9] (col),
        .app_cmd(app_cmd),
        .app_en(app_en),
        .app_rdy_r_reg(E),
        .app_wdf_data(app_wdf_data),
        .app_wdf_end(app_wdf_end),
        .app_wdf_mask(app_wdf_mask),
        .app_wdf_rdy(app_wdf_rdy),
        .app_wdf_wren(app_wdf_wren),
        .cmd(cmd),
        .\pointer_ram.pointer_we (\ui_wr_data0/pointer_ram.pointer_we ),
        .ram_init_done_r(ram_init_done_r),
        .req_bank_r(\mc0/bank_mach0/req_bank_r ),
        .\req_bank_r_lcl_reg[0] (u_ui_top_n_25),
        .\req_bank_r_lcl_reg[0]_0 (u_ui_top_n_29),
        .\req_bank_r_lcl_reg[2] (u_ui_top_n_30),
        .\req_bank_r_lcl_reg[2]_0 (u_ui_top_n_31),
        .\req_row_r_lcl_reg[10] (u_ui_top_n_24),
        .reset_reg(data_buf_addr),
        .row_hit_r_reg({\mc0/bank_mach0/req_row_r [55:54],\mc0/bank_mach0/req_row_r [41:40],\mc0/bank_mach0/req_row_r [27:23],\mc0/bank_mach0/req_row_r [13:12],\mc0/bank_mach0/req_row_r [8:0]}),
        .use_addr(use_addr),
        .wr_data_addr(wr_data_addr),
        .\wr_req_counter.wr_req_cnt_r_reg[0] (\wr_req_counter.wr_req_cnt_r_reg[0] ),
        .\wr_req_counter.wr_req_cnt_r_reg[0]_0 (reset_reg_n_0));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_poc_pd" *) 
module mig_mig_7series_v4_2_poc_pd
   (mmcm_ps_clk,
    in_dqs_lpbk_to_iddr_0,
    rst_sync_r1);
  input mmcm_ps_clk;
  input in_dqs_lpbk_to_iddr_0;
  input rst_sync_r1;

  wire in_dqs_lpbk_to_iddr_0;
  wire mmcm_ps_clk;
  wire q1;
  wire rst_sync_r1;
  wire NLW_u_phase_detector_Q2_UNCONNECTED;

  (* BOX_TYPE = "PRIMITIVE" *) 
  (* __SRVAL = "FALSE" *) 
  IDDR #(
    .DDR_CLK_EDGE("OPPOSITE_EDGE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .SRTYPE("SYNC")) 
    u_phase_detector
       (.C(mmcm_ps_clk),
        .CE(1'b1),
        .D(in_dqs_lpbk_to_iddr_0),
        .Q1(q1),
        .Q2(NLW_u_phase_detector_Q2_UNCONNECTED),
        .R(rst_sync_r1),
        .S(1'b0));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_poc_pd" *) 
module mig_mig_7series_v4_2_poc_pd_10
   (mmcm_ps_clk,
    in_dqs_lpbk_to_iddr_6,
    rst_sync_r1);
  input mmcm_ps_clk;
  input in_dqs_lpbk_to_iddr_6;
  input rst_sync_r1;

  wire in_dqs_lpbk_to_iddr_6;
  wire mmcm_ps_clk;
  wire q1;
  wire rst_sync_r1;
  wire NLW_u_phase_detector_Q2_UNCONNECTED;

  (* BOX_TYPE = "PRIMITIVE" *) 
  (* __SRVAL = "FALSE" *) 
  IDDR #(
    .DDR_CLK_EDGE("OPPOSITE_EDGE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .SRTYPE("SYNC")) 
    u_phase_detector
       (.C(mmcm_ps_clk),
        .CE(1'b1),
        .D(in_dqs_lpbk_to_iddr_6),
        .Q1(q1),
        .Q2(NLW_u_phase_detector_Q2_UNCONNECTED),
        .R(rst_sync_r1),
        .S(1'b0));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_poc_pd" *) 
module mig_mig_7series_v4_2_poc_pd_11
   (mmcm_ps_clk,
    in_dqs_lpbk_to_iddr_7,
    rst_sync_r1);
  input mmcm_ps_clk;
  input in_dqs_lpbk_to_iddr_7;
  input rst_sync_r1;

  wire in_dqs_lpbk_to_iddr_7;
  wire mmcm_ps_clk;
  wire q1;
  wire rst_sync_r1;
  wire NLW_u_phase_detector_Q2_UNCONNECTED;

  (* BOX_TYPE = "PRIMITIVE" *) 
  (* __SRVAL = "FALSE" *) 
  IDDR #(
    .DDR_CLK_EDGE("OPPOSITE_EDGE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .SRTYPE("SYNC")) 
    u_phase_detector
       (.C(mmcm_ps_clk),
        .CE(1'b1),
        .D(in_dqs_lpbk_to_iddr_7),
        .Q1(q1),
        .Q2(NLW_u_phase_detector_Q2_UNCONNECTED),
        .R(rst_sync_r1),
        .S(1'b0));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_poc_pd" *) 
module mig_mig_7series_v4_2_poc_pd_5
   (mmcm_ps_clk,
    in_dqs_lpbk_to_iddr_1,
    rst_sync_r1);
  input mmcm_ps_clk;
  input in_dqs_lpbk_to_iddr_1;
  input rst_sync_r1;

  wire in_dqs_lpbk_to_iddr_1;
  wire mmcm_ps_clk;
  wire q1;
  wire rst_sync_r1;
  wire NLW_u_phase_detector_Q2_UNCONNECTED;

  (* BOX_TYPE = "PRIMITIVE" *) 
  (* __SRVAL = "FALSE" *) 
  IDDR #(
    .DDR_CLK_EDGE("OPPOSITE_EDGE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .SRTYPE("SYNC")) 
    u_phase_detector
       (.C(mmcm_ps_clk),
        .CE(1'b1),
        .D(in_dqs_lpbk_to_iddr_1),
        .Q1(q1),
        .Q2(NLW_u_phase_detector_Q2_UNCONNECTED),
        .R(rst_sync_r1),
        .S(1'b0));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_poc_pd" *) 
module mig_mig_7series_v4_2_poc_pd_6
   (mmcm_ps_clk,
    in_dqs_lpbk_to_iddr_2,
    rst_sync_r1);
  input mmcm_ps_clk;
  input in_dqs_lpbk_to_iddr_2;
  input rst_sync_r1;

  wire in_dqs_lpbk_to_iddr_2;
  wire mmcm_ps_clk;
  wire q1;
  wire rst_sync_r1;
  wire NLW_u_phase_detector_Q2_UNCONNECTED;

  (* BOX_TYPE = "PRIMITIVE" *) 
  (* __SRVAL = "FALSE" *) 
  IDDR #(
    .DDR_CLK_EDGE("OPPOSITE_EDGE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .SRTYPE("SYNC")) 
    u_phase_detector
       (.C(mmcm_ps_clk),
        .CE(1'b1),
        .D(in_dqs_lpbk_to_iddr_2),
        .Q1(q1),
        .Q2(NLW_u_phase_detector_Q2_UNCONNECTED),
        .R(rst_sync_r1),
        .S(1'b0));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_poc_pd" *) 
module mig_mig_7series_v4_2_poc_pd_7
   (mmcm_ps_clk,
    in_dqs_lpbk_to_iddr_3,
    rst_sync_r1);
  input mmcm_ps_clk;
  input in_dqs_lpbk_to_iddr_3;
  input rst_sync_r1;

  wire in_dqs_lpbk_to_iddr_3;
  wire mmcm_ps_clk;
  wire q1;
  wire rst_sync_r1;
  wire NLW_u_phase_detector_Q2_UNCONNECTED;

  (* BOX_TYPE = "PRIMITIVE" *) 
  (* __SRVAL = "FALSE" *) 
  IDDR #(
    .DDR_CLK_EDGE("OPPOSITE_EDGE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .SRTYPE("SYNC")) 
    u_phase_detector
       (.C(mmcm_ps_clk),
        .CE(1'b1),
        .D(in_dqs_lpbk_to_iddr_3),
        .Q1(q1),
        .Q2(NLW_u_phase_detector_Q2_UNCONNECTED),
        .R(rst_sync_r1),
        .S(1'b0));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_poc_pd" *) 
module mig_mig_7series_v4_2_poc_pd_8
   (mmcm_ps_clk,
    in_dqs_lpbk_to_iddr_4,
    rst_sync_r1);
  input mmcm_ps_clk;
  input in_dqs_lpbk_to_iddr_4;
  input rst_sync_r1;

  wire in_dqs_lpbk_to_iddr_4;
  wire mmcm_ps_clk;
  wire q1;
  wire rst_sync_r1;
  wire NLW_u_phase_detector_Q2_UNCONNECTED;

  (* BOX_TYPE = "PRIMITIVE" *) 
  (* __SRVAL = "FALSE" *) 
  IDDR #(
    .DDR_CLK_EDGE("OPPOSITE_EDGE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .SRTYPE("SYNC")) 
    u_phase_detector
       (.C(mmcm_ps_clk),
        .CE(1'b1),
        .D(in_dqs_lpbk_to_iddr_4),
        .Q1(q1),
        .Q2(NLW_u_phase_detector_Q2_UNCONNECTED),
        .R(rst_sync_r1),
        .S(1'b0));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_poc_pd" *) 
module mig_mig_7series_v4_2_poc_pd_9
   (mmcm_ps_clk,
    in_dqs_lpbk_to_iddr_5,
    rst_sync_r1);
  input mmcm_ps_clk;
  input in_dqs_lpbk_to_iddr_5;
  input rst_sync_r1;

  wire in_dqs_lpbk_to_iddr_5;
  wire mmcm_ps_clk;
  wire q1;
  wire rst_sync_r1;
  wire NLW_u_phase_detector_Q2_UNCONNECTED;

  (* BOX_TYPE = "PRIMITIVE" *) 
  (* __SRVAL = "FALSE" *) 
  IDDR #(
    .DDR_CLK_EDGE("OPPOSITE_EDGE"),
    .INIT_Q1(1'b0),
    .INIT_Q2(1'b0),
    .IS_C_INVERTED(1'b0),
    .IS_D_INVERTED(1'b0),
    .SRTYPE("SYNC")) 
    u_phase_detector
       (.C(mmcm_ps_clk),
        .CE(1'b1),
        .D(in_dqs_lpbk_to_iddr_5),
        .Q1(q1),
        .Q2(NLW_u_phase_detector_Q2_UNCONNECTED),
        .R(rst_sync_r1),
        .S(1'b0));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_rank_cntrl" *) 
module mig_mig_7series_v4_2_rank_cntrl
   (\inhbt_act_faw.act_delayed ,
    \periodic_rd_generation.read_this_rank_r ,
    inhbt_act_faw_r,
    \periodic_rd_generation.periodic_rd_request_r ,
    \periodic_rd_generation.periodic_rd_cntr1_r ,
    \refresh_generation.refresh_bank_r_reg[0]_0 ,
    \wtr_timer.wtr_cnt_r_reg[1]_0 ,
    \periodic_rd_generation.periodic_rd_timer_r_reg[2]_0 ,
    \inhbt_act_faw.faw_cnt_r_reg[2]_0 ,
    \rtw_timer.rtw_cnt_r_reg[1]_0 ,
    act_this_rank,
    \periodic_rd_generation.periodic_rd_request_r_reg_0 ,
    \periodic_rd_generation.read_this_rank ,
    SR,
    \periodic_rd_generation.periodic_rd_request_r_reg_1 ,
    \periodic_rd_generation.periodic_rd_cntr1_r_reg_0 ,
    \periodic_rd_generation.periodic_rd_cntr1_r_reg_1 ,
    \refresh_generation.refresh_bank_r_reg[0]_1 ,
    \periodic_rd_generation.periodic_rd_timer_r_reg[2]_1 ,
    \periodic_rd_generation.periodic_rd_timer_r_reg[2]_2 ,
    maint_prescaler_tick_r,
    \wtr_timer.wtr_cnt_r_reg[1]_1 ,
    \wtr_timer.wtr_cnt_r_reg[1]_2 ,
    \inhbt_act_faw.inhbt_act_faw_r_reg_0 ,
    \inhbt_act_faw.inhbt_act_faw_r_reg_1 ,
    \inhbt_act_faw.faw_cnt_r_reg[2]_1 ,
    \wtr_timer.wtr_cnt_r_reg[0]_0 ,
    \rtw_timer.rtw_cnt_r_reg[1]_1 );
  output \inhbt_act_faw.act_delayed ;
  output \periodic_rd_generation.read_this_rank_r ;
  output inhbt_act_faw_r;
  output \periodic_rd_generation.periodic_rd_request_r ;
  output \periodic_rd_generation.periodic_rd_cntr1_r ;
  output \refresh_generation.refresh_bank_r_reg[0]_0 ;
  output [1:0]\wtr_timer.wtr_cnt_r_reg[1]_0 ;
  output \periodic_rd_generation.periodic_rd_timer_r_reg[2]_0 ;
  output [2:0]\inhbt_act_faw.faw_cnt_r_reg[2]_0 ;
  output [1:0]\rtw_timer.rtw_cnt_r_reg[1]_0 ;
  input act_this_rank;
  input \periodic_rd_generation.periodic_rd_request_r_reg_0 ;
  input \periodic_rd_generation.read_this_rank ;
  input [0:0]SR;
  input \periodic_rd_generation.periodic_rd_request_r_reg_1 ;
  input \periodic_rd_generation.periodic_rd_cntr1_r_reg_0 ;
  input \periodic_rd_generation.periodic_rd_cntr1_r_reg_1 ;
  input \refresh_generation.refresh_bank_r_reg[0]_1 ;
  input \periodic_rd_generation.periodic_rd_timer_r_reg[2]_1 ;
  input \periodic_rd_generation.periodic_rd_timer_r_reg[2]_2 ;
  input maint_prescaler_tick_r;
  input \wtr_timer.wtr_cnt_r_reg[1]_1 ;
  input \wtr_timer.wtr_cnt_r_reg[1]_2 ;
  input \inhbt_act_faw.inhbt_act_faw_r_reg_0 ;
  input \inhbt_act_faw.inhbt_act_faw_r_reg_1 ;
  input [2:0]\inhbt_act_faw.faw_cnt_r_reg[2]_1 ;
  input [0:0]\wtr_timer.wtr_cnt_r_reg[0]_0 ;
  input [1:0]\rtw_timer.rtw_cnt_r_reg[1]_1 ;

  wire [0:0]SR;
  wire act_this_rank;
  wire \inhbt_act_faw.act_delayed ;
  wire [2:0]\inhbt_act_faw.faw_cnt_r_reg[2]_0 ;
  wire [2:0]\inhbt_act_faw.faw_cnt_r_reg[2]_1 ;
  wire \inhbt_act_faw.inhbt_act_faw_r_i_1_n_0 ;
  wire \inhbt_act_faw.inhbt_act_faw_r_reg_0 ;
  wire \inhbt_act_faw.inhbt_act_faw_r_reg_1 ;
  wire inhbt_act_faw_r;
  wire maint_prescaler_tick_r;
  wire \periodic_rd_generation.periodic_rd_cntr1_r ;
  wire \periodic_rd_generation.periodic_rd_cntr1_r_reg_0 ;
  wire \periodic_rd_generation.periodic_rd_cntr1_r_reg_1 ;
  wire \periodic_rd_generation.periodic_rd_request_r ;
  wire \periodic_rd_generation.periodic_rd_request_r_reg_0 ;
  wire \periodic_rd_generation.periodic_rd_request_r_reg_1 ;
  wire [2:0]\periodic_rd_generation.periodic_rd_timer_r ;
  wire \periodic_rd_generation.periodic_rd_timer_r[0]_i_1_n_0 ;
  wire \periodic_rd_generation.periodic_rd_timer_r[1]_i_1_n_0 ;
  wire \periodic_rd_generation.periodic_rd_timer_r[2]_i_1_n_0 ;
  wire \periodic_rd_generation.periodic_rd_timer_r_reg[2]_0 ;
  wire \periodic_rd_generation.periodic_rd_timer_r_reg[2]_1 ;
  wire \periodic_rd_generation.periodic_rd_timer_r_reg[2]_2 ;
  wire \periodic_rd_generation.read_this_rank ;
  wire \periodic_rd_generation.read_this_rank_r ;
  wire \refresh_generation.refresh_bank_r_reg[0]_0 ;
  wire \refresh_generation.refresh_bank_r_reg[0]_1 ;
  wire [1:0]\rtw_timer.rtw_cnt_r_reg[1]_0 ;
  wire [1:0]\rtw_timer.rtw_cnt_r_reg[1]_1 ;
  wire [1:1]\wtr_timer.wtr_cnt_ns ;
  wire [0:0]\wtr_timer.wtr_cnt_r_reg[0]_0 ;
  wire [1:0]\wtr_timer.wtr_cnt_r_reg[1]_0 ;
  wire \wtr_timer.wtr_cnt_r_reg[1]_1 ;
  wire \wtr_timer.wtr_cnt_r_reg[1]_2 ;
  wire \NLW_inhbt_act_faw.SRLC32E0_Q31_UNCONNECTED ;

  LUT4 #(
    .INIT(16'h0040)) 
    i___20_i_2
       (.I0(\periodic_rd_generation.periodic_rd_timer_r [2]),
        .I1(\periodic_rd_generation.periodic_rd_timer_r [0]),
        .I2(maint_prescaler_tick_r),
        .I3(\periodic_rd_generation.periodic_rd_timer_r [1]),
        .O(\periodic_rd_generation.periodic_rd_timer_r_reg[2]_0 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  (* srl_bus_name = "\u_mig_mig/u_memc_ui_top_std/mem_intfc0/mc0/rank_mach0/rank_cntrl " *) 
  (* srl_name = "\u_mig_mig/u_memc_ui_top_std/mem_intfc0/mc0/rank_mach0/rank_cntrl[0].rank_cntrl0/inhbt_act_faw.SRLC32E0 " *) 
  SRLC32E #(
    .INIT(32'h00000000),
    .IS_CLK_INVERTED(1'b0)) 
    \inhbt_act_faw.SRLC32E0 
       (.A({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .CE(1'b1),
        .CLK(\periodic_rd_generation.periodic_rd_request_r_reg_0 ),
        .D(act_this_rank),
        .Q(\inhbt_act_faw.act_delayed ),
        .Q31(\NLW_inhbt_act_faw.SRLC32E0_Q31_UNCONNECTED ));
  FDRE \inhbt_act_faw.faw_cnt_r_reg[0] 
       (.C(\periodic_rd_generation.periodic_rd_request_r_reg_0 ),
        .CE(1'b1),
        .D(\inhbt_act_faw.faw_cnt_r_reg[2]_1 [0]),
        .Q(\inhbt_act_faw.faw_cnt_r_reg[2]_0 [0]),
        .R(1'b0));
  FDRE \inhbt_act_faw.faw_cnt_r_reg[1] 
       (.C(\periodic_rd_generation.periodic_rd_request_r_reg_0 ),
        .CE(1'b1),
        .D(\inhbt_act_faw.faw_cnt_r_reg[2]_1 [1]),
        .Q(\inhbt_act_faw.faw_cnt_r_reg[2]_0 [1]),
        .R(1'b0));
  FDRE \inhbt_act_faw.faw_cnt_r_reg[2] 
       (.C(\periodic_rd_generation.periodic_rd_request_r_reg_0 ),
        .CE(1'b1),
        .D(\inhbt_act_faw.faw_cnt_r_reg[2]_1 [2]),
        .Q(\inhbt_act_faw.faw_cnt_r_reg[2]_0 [2]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h0001000020000220)) 
    \inhbt_act_faw.inhbt_act_faw_r_i_1 
       (.I0(\inhbt_act_faw.faw_cnt_r_reg[2]_0 [2]),
        .I1(\inhbt_act_faw.inhbt_act_faw_r_reg_0 ),
        .I2(\inhbt_act_faw.act_delayed ),
        .I3(\inhbt_act_faw.inhbt_act_faw_r_reg_1 ),
        .I4(\inhbt_act_faw.faw_cnt_r_reg[2]_0 [0]),
        .I5(\inhbt_act_faw.faw_cnt_r_reg[2]_0 [1]),
        .O(\inhbt_act_faw.inhbt_act_faw_r_i_1_n_0 ));
  FDRE \inhbt_act_faw.inhbt_act_faw_r_reg 
       (.C(\periodic_rd_generation.periodic_rd_request_r_reg_0 ),
        .CE(1'b1),
        .D(\inhbt_act_faw.inhbt_act_faw_r_i_1_n_0 ),
        .Q(inhbt_act_faw_r),
        .R(1'b0));
  FDRE \periodic_rd_generation.periodic_rd_cntr1_r_reg 
       (.C(\periodic_rd_generation.periodic_rd_request_r_reg_0 ),
        .CE(1'b1),
        .D(\periodic_rd_generation.periodic_rd_cntr1_r_reg_1 ),
        .Q(\periodic_rd_generation.periodic_rd_cntr1_r ),
        .R(\periodic_rd_generation.periodic_rd_cntr1_r_reg_0 ));
  FDRE \periodic_rd_generation.periodic_rd_request_r_reg 
       (.C(\periodic_rd_generation.periodic_rd_request_r_reg_0 ),
        .CE(1'b1),
        .D(\periodic_rd_generation.periodic_rd_request_r_reg_1 ),
        .Q(\periodic_rd_generation.periodic_rd_request_r ),
        .R(SR));
  LUT6 #(
    .INIT(64'hBBFFFFBBBFFBFFBB)) 
    \periodic_rd_generation.periodic_rd_timer_r[0]_i_1 
       (.I0(\periodic_rd_generation.periodic_rd_timer_r_reg[2]_1 ),
        .I1(\periodic_rd_generation.periodic_rd_timer_r_reg[2]_2 ),
        .I2(\periodic_rd_generation.periodic_rd_timer_r [2]),
        .I3(\periodic_rd_generation.periodic_rd_timer_r [0]),
        .I4(maint_prescaler_tick_r),
        .I5(\periodic_rd_generation.periodic_rd_timer_r [1]),
        .O(\periodic_rd_generation.periodic_rd_timer_r[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h4400444400400000)) 
    \periodic_rd_generation.periodic_rd_timer_r[1]_i_1 
       (.I0(\periodic_rd_generation.periodic_rd_timer_r_reg[2]_1 ),
        .I1(\periodic_rd_generation.periodic_rd_timer_r_reg[2]_2 ),
        .I2(\periodic_rd_generation.periodic_rd_timer_r [2]),
        .I3(\periodic_rd_generation.periodic_rd_timer_r [0]),
        .I4(maint_prescaler_tick_r),
        .I5(\periodic_rd_generation.periodic_rd_timer_r [1]),
        .O(\periodic_rd_generation.periodic_rd_timer_r[1]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFBFBFBFBFFBBFBFB)) 
    \periodic_rd_generation.periodic_rd_timer_r[2]_i_1 
       (.I0(\periodic_rd_generation.periodic_rd_timer_r_reg[2]_1 ),
        .I1(\periodic_rd_generation.periodic_rd_timer_r_reg[2]_2 ),
        .I2(\periodic_rd_generation.periodic_rd_timer_r [2]),
        .I3(\periodic_rd_generation.periodic_rd_timer_r [0]),
        .I4(maint_prescaler_tick_r),
        .I5(\periodic_rd_generation.periodic_rd_timer_r [1]),
        .O(\periodic_rd_generation.periodic_rd_timer_r[2]_i_1_n_0 ));
  FDRE \periodic_rd_generation.periodic_rd_timer_r_reg[0] 
       (.C(\periodic_rd_generation.periodic_rd_request_r_reg_0 ),
        .CE(1'b1),
        .D(\periodic_rd_generation.periodic_rd_timer_r[0]_i_1_n_0 ),
        .Q(\periodic_rd_generation.periodic_rd_timer_r [0]),
        .R(1'b0));
  FDRE \periodic_rd_generation.periodic_rd_timer_r_reg[1] 
       (.C(\periodic_rd_generation.periodic_rd_request_r_reg_0 ),
        .CE(1'b1),
        .D(\periodic_rd_generation.periodic_rd_timer_r[1]_i_1_n_0 ),
        .Q(\periodic_rd_generation.periodic_rd_timer_r [1]),
        .R(1'b0));
  FDRE \periodic_rd_generation.periodic_rd_timer_r_reg[2] 
       (.C(\periodic_rd_generation.periodic_rd_request_r_reg_0 ),
        .CE(1'b1),
        .D(\periodic_rd_generation.periodic_rd_timer_r[2]_i_1_n_0 ),
        .Q(\periodic_rd_generation.periodic_rd_timer_r [2]),
        .R(1'b0));
  FDRE \periodic_rd_generation.read_this_rank_r_reg 
       (.C(\periodic_rd_generation.periodic_rd_request_r_reg_0 ),
        .CE(1'b1),
        .D(\periodic_rd_generation.read_this_rank ),
        .Q(\periodic_rd_generation.read_this_rank_r ),
        .R(1'b0));
  FDRE \refresh_generation.refresh_bank_r_reg[0] 
       (.C(\periodic_rd_generation.periodic_rd_request_r_reg_0 ),
        .CE(1'b1),
        .D(\refresh_generation.refresh_bank_r_reg[0]_1 ),
        .Q(\refresh_generation.refresh_bank_r_reg[0]_0 ),
        .R(1'b0));
  FDRE \rtw_timer.rtw_cnt_r_reg[0] 
       (.C(\periodic_rd_generation.periodic_rd_request_r_reg_0 ),
        .CE(1'b1),
        .D(\rtw_timer.rtw_cnt_r_reg[1]_1 [0]),
        .Q(\rtw_timer.rtw_cnt_r_reg[1]_0 [0]),
        .R(1'b0));
  FDRE \rtw_timer.rtw_cnt_r_reg[1] 
       (.C(\periodic_rd_generation.periodic_rd_request_r_reg_0 ),
        .CE(1'b1),
        .D(\rtw_timer.rtw_cnt_r_reg[1]_1 [1]),
        .Q(\rtw_timer.rtw_cnt_r_reg[1]_0 [1]),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h00D5)) 
    \wtr_timer.wtr_cnt_r[1]_i_1 
       (.I0(\wtr_timer.wtr_cnt_r_reg[1]_1 ),
        .I1(\wtr_timer.wtr_cnt_r_reg[1]_0 [0]),
        .I2(\wtr_timer.wtr_cnt_r_reg[1]_0 [1]),
        .I3(\wtr_timer.wtr_cnt_r_reg[1]_2 ),
        .O(\wtr_timer.wtr_cnt_ns ));
  FDRE \wtr_timer.wtr_cnt_r_reg[0] 
       (.C(\periodic_rd_generation.periodic_rd_request_r_reg_0 ),
        .CE(1'b1),
        .D(\wtr_timer.wtr_cnt_r_reg[0]_0 ),
        .Q(\wtr_timer.wtr_cnt_r_reg[1]_0 [0]),
        .R(1'b0));
  FDRE \wtr_timer.wtr_cnt_r_reg[1] 
       (.C(\periodic_rd_generation.periodic_rd_request_r_reg_0 ),
        .CE(1'b1),
        .D(\wtr_timer.wtr_cnt_ns ),
        .Q(\wtr_timer.wtr_cnt_r_reg[1]_0 [1]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_rank_common" *) 
module mig_mig_7series_v4_2_rank_common
   (maint_prescaler_tick_r,
    \maintenance_request.maint_sre_r_lcl_reg_0 ,
    \maintenance_request.upd_last_master_r_reg_0 ,
    \maintenance_request.new_maint_rank_r_reg_0 ,
    maint_req_r,
    \periodic_read_request.upd_last_master_r ,
    app_ref_ack,
    app_zq_ack,
    \zq_cntrl.zq_request_logic.zq_request_r_reg_0 ,
    \maintenance_request.maint_srx_r_lcl_reg_0 ,
    \sr_cntrl.sre_request_logic.sre_request_r_reg_0 ,
    \maintenance_request.maint_zq_r_lcl_reg_0 ,
    periodic_rd_r,
    app_ref_r,
    app_zq_r,
    \periodic_read_request.periodic_rd_r_cnt ,
    \periodic_read_request.periodic_rd_grant_r ,
    app_sr_active,
    maint_ref_zq_wip,
    Q,
    init_calib_complete_reg_rep__26,
    \refresh_timer.refresh_timer_r_reg[5]_0 ,
    \refresh_timer.refresh_timer_r_reg[1]_0 ,
    init_calib_complete_reg_rep__26_0,
    mc_cke_ns,
    \grant_r_reg[2] ,
    \last_master_r_reg[2] ,
    S,
    \zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 ,
    \zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 ,
    \zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 ,
    \zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 ,
    \maintenance_request.maint_srx_r_lcl_reg_1 ,
    \maintenance_request.maint_sre_r_lcl_reg_1 ,
    \last_master_r_reg[2]_0 ,
    \maintenance_request.upd_last_master_r_reg_1 ,
    \zq_cntrl.zq_request_logic.zq_request_r_reg_1 ,
    \zq_cntrl.zq_request_logic.zq_request_r_reg_2 ,
    SR,
    \sr_cntrl.sre_request_logic.sre_request_r_reg_1 ,
    \periodic_read_request.periodic_rd_r_lcl_reg_0 ,
    \periodic_read_request.periodic_rd_r_lcl_reg_1 ,
    app_ref_r_reg_0,
    app_zq_r_reg_0,
    \periodic_read_request.periodic_rd_r_cnt_reg_0 ,
    \periodic_read_request.periodic_rd_r_cnt_reg_1 ,
    \periodic_read_request.periodic_rd_grant_r_reg[0]_0 ,
    app_sr_active_r_reg_0,
    maint_ref_zq_wip_r_reg_0,
    O,
    \zq_cntrl.zq_timer.zq_timer_r_reg[7]_1 ,
    \zq_cntrl.zq_timer.zq_timer_r_reg[11]_1 ,
    \zq_cntrl.zq_timer.zq_timer_r_reg[15]_1 ,
    \zq_cntrl.zq_timer.zq_timer_r_reg[19]_1 ,
    \grant_r_reg[0] ,
    \grant_r_reg[0]_0 ,
    app_ref_req,
    insert_maint_r1,
    cke_r,
    app_sr_req,
    \last_master_r_reg[2]_1 ,
    D,
    \grant_r_reg[2]_0 ,
    \periodic_rd_generation.periodic_rd_request_r ,
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ,
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ,
    SS,
    \maint_prescaler.maint_prescaler_r_reg[1]_0 ,
    \refresh_timer.refresh_timer_r_reg[5]_1 ,
    \refresh_timer.refresh_timer_r_reg[1]_1 );
  output maint_prescaler_tick_r;
  output \maintenance_request.maint_sre_r_lcl_reg_0 ;
  output \maintenance_request.upd_last_master_r_reg_0 ;
  output \maintenance_request.new_maint_rank_r_reg_0 ;
  output maint_req_r;
  output \periodic_read_request.upd_last_master_r ;
  output app_ref_ack;
  output app_zq_ack;
  output \zq_cntrl.zq_request_logic.zq_request_r_reg_0 ;
  output \maintenance_request.maint_srx_r_lcl_reg_0 ;
  output \sr_cntrl.sre_request_logic.sre_request_r_reg_0 ;
  output \maintenance_request.maint_zq_r_lcl_reg_0 ;
  output periodic_rd_r;
  output app_ref_r;
  output app_zq_r;
  output \periodic_read_request.periodic_rd_r_cnt ;
  output \periodic_read_request.periodic_rd_grant_r ;
  output app_sr_active;
  output maint_ref_zq_wip;
  output [4:0]Q;
  output init_calib_complete_reg_rep__26;
  output \refresh_timer.refresh_timer_r_reg[5]_0 ;
  output [1:0]\refresh_timer.refresh_timer_r_reg[1]_0 ;
  output init_calib_complete_reg_rep__26_0;
  output [0:0]mc_cke_ns;
  output [2:0]\grant_r_reg[2] ;
  output [2:0]\last_master_r_reg[2] ;
  output [3:0]S;
  output [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 ;
  output [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 ;
  output [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 ;
  output [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 ;
  output [0:0]\maintenance_request.maint_srx_r_lcl_reg_1 ;
  output \maintenance_request.maint_sre_r_lcl_reg_1 ;
  input \last_master_r_reg[2]_0 ;
  input \maintenance_request.upd_last_master_r_reg_1 ;
  input \zq_cntrl.zq_request_logic.zq_request_r_reg_1 ;
  input \zq_cntrl.zq_request_logic.zq_request_r_reg_2 ;
  input [0:0]SR;
  input \sr_cntrl.sre_request_logic.sre_request_r_reg_1 ;
  input \periodic_read_request.periodic_rd_r_lcl_reg_0 ;
  input \periodic_read_request.periodic_rd_r_lcl_reg_1 ;
  input app_ref_r_reg_0;
  input app_zq_r_reg_0;
  input \periodic_read_request.periodic_rd_r_cnt_reg_0 ;
  input \periodic_read_request.periodic_rd_r_cnt_reg_1 ;
  input \periodic_read_request.periodic_rd_grant_r_reg[0]_0 ;
  input app_sr_active_r_reg_0;
  input maint_ref_zq_wip_r_reg_0;
  input [3:0]O;
  input [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[7]_1 ;
  input [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[11]_1 ;
  input [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[15]_1 ;
  input [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[19]_1 ;
  input \grant_r_reg[0] ;
  input \grant_r_reg[0]_0 ;
  input app_ref_req;
  input insert_maint_r1;
  input cke_r;
  input app_sr_req;
  input \last_master_r_reg[2]_1 ;
  input [1:0]D;
  input \grant_r_reg[2]_0 ;
  input \periodic_rd_generation.periodic_rd_request_r ;
  input [0:0]\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ;
  input \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ;
  input [0:0]SS;
  input [0:0]\maint_prescaler.maint_prescaler_r_reg[1]_0 ;
  input [0:0]\refresh_timer.refresh_timer_r_reg[5]_1 ;
  input [0:0]\refresh_timer.refresh_timer_r_reg[1]_1 ;

  wire [1:0]D;
  wire [3:0]O;
  wire [4:0]Q;
  wire [3:0]S;
  wire [0:0]SR;
  wire [0:0]SS;
  wire app_ref_ack;
  wire app_ref_ack_ns;
  wire app_ref_r;
  wire app_ref_r_reg_0;
  wire app_ref_req;
  wire app_sr_active;
  wire app_sr_active_r_reg_0;
  wire app_sr_req;
  wire app_zq_ack;
  wire app_zq_ack_ns;
  wire app_zq_r;
  wire app_zq_r_reg_0;
  wire cke_r;
  wire \grant_r_reg[0] ;
  wire \grant_r_reg[0]_0 ;
  wire [2:0]\grant_r_reg[2] ;
  wire \grant_r_reg[2]_0 ;
  wire i___13_i_2_n_0;
  wire init_calib_complete_reg_rep__26;
  wire init_calib_complete_reg_rep__26_0;
  wire insert_maint_r1;
  wire [2:0]\last_master_r_reg[2] ;
  wire \last_master_r_reg[2]_0 ;
  wire \last_master_r_reg[2]_1 ;
  wire [4:0]\maint_prescaler.maint_prescaler_r0 ;
  wire [0:0]\maint_prescaler.maint_prescaler_r_reg[1]_0 ;
  wire \maint_prescaler.maint_prescaler_tick_ns ;
  wire maint_prescaler_tick_r;
  wire maint_ref_zq_wip;
  wire maint_ref_zq_wip_r_reg_0;
  wire maint_req_r;
  wire \maintenance_request.maint_arb0_n_4 ;
  wire \maintenance_request.maint_arb0_n_8 ;
  wire \maintenance_request.maint_sre_ns ;
  wire \maintenance_request.maint_sre_r_lcl_reg_0 ;
  wire \maintenance_request.maint_sre_r_lcl_reg_1 ;
  wire \maintenance_request.maint_srx_r_lcl_reg_0 ;
  wire [0:0]\maintenance_request.maint_srx_r_lcl_reg_1 ;
  wire \maintenance_request.maint_zq_r_lcl_reg_0 ;
  wire \maintenance_request.new_maint_rank_r_reg_0 ;
  wire \maintenance_request.upd_last_master_r_reg_0 ;
  wire \maintenance_request.upd_last_master_r_reg_1 ;
  wire [0:0]mc_cke_ns;
  wire \periodic_rd_generation.periodic_rd_request_r ;
  wire periodic_rd_r;
  wire \periodic_read_request.periodic_rd_grant_r ;
  wire \periodic_read_request.periodic_rd_grant_r_reg[0]_0 ;
  wire \periodic_read_request.periodic_rd_r_cnt ;
  wire \periodic_read_request.periodic_rd_r_cnt_reg_0 ;
  wire \periodic_read_request.periodic_rd_r_cnt_reg_1 ;
  wire \periodic_read_request.periodic_rd_r_lcl_reg_0 ;
  wire \periodic_read_request.periodic_rd_r_lcl_reg_1 ;
  wire \periodic_read_request.upd_last_master_ns ;
  wire \periodic_read_request.upd_last_master_r ;
  wire \refresh_generation.refresh_bank_r[0]_i_2_n_0 ;
  wire [5:0]\refresh_timer.refresh_timer_r0 ;
  wire \refresh_timer.refresh_timer_r0_0 ;
  wire \refresh_timer.refresh_timer_r[5]_i_3_n_0 ;
  wire [5:2]\refresh_timer.refresh_timer_r_reg ;
  wire [1:0]\refresh_timer.refresh_timer_r_reg[1]_0 ;
  wire [0:0]\refresh_timer.refresh_timer_r_reg[1]_1 ;
  wire \refresh_timer.refresh_timer_r_reg[5]_0 ;
  wire [0:0]\refresh_timer.refresh_timer_r_reg[5]_1 ;
  wire [0:0]\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ;
  wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ;
  wire sel;
  wire \sr_cntrl.ckesr_timer.ckesr_timer_r ;
  wire \sr_cntrl.ckesr_timer.ckesr_timer_r[0]_i_1_n_0 ;
  wire \sr_cntrl.sre_request_logic.sre_request_r_reg_0 ;
  wire \sr_cntrl.sre_request_logic.sre_request_r_reg_1 ;
  wire \zq_cntrl.zq_request_logic.zq_request_r_reg_0 ;
  wire \zq_cntrl.zq_request_logic.zq_request_r_reg_1 ;
  wire \zq_cntrl.zq_request_logic.zq_request_r_reg_2 ;
  wire \zq_cntrl.zq_timer.zq_timer_r0 ;
  wire \zq_cntrl.zq_timer.zq_timer_r[0]_i_10_n_0 ;
  wire \zq_cntrl.zq_timer.zq_timer_r[0]_i_11_n_0 ;
  wire \zq_cntrl.zq_timer.zq_timer_r[0]_i_12_n_0 ;
  wire \zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ;
  wire \zq_cntrl.zq_timer.zq_timer_r[0]_i_4_n_0 ;
  wire \zq_cntrl.zq_timer.zq_timer_r[0]_i_9_n_0 ;
  wire [19:0]\zq_cntrl.zq_timer.zq_timer_r_reg ;
  wire [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 ;
  wire [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[11]_1 ;
  wire [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 ;
  wire [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[15]_1 ;
  wire [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 ;
  wire [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[19]_1 ;
  wire [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 ;
  wire [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[7]_1 ;

  (* SOFT_HLUTNM = "soft_lutpair1205" *) 
  LUT3 #(
    .INIT(8'h8A)) 
    app_ref_ack_r_i_1
       (.I0(app_ref_r),
        .I1(\grant_r_reg[0]_0 ),
        .I2(\grant_r_reg[0] ),
        .O(app_ref_ack_ns));
  FDRE #(
    .INIT(1'b0)) 
    app_ref_ack_r_reg
       (.C(\last_master_r_reg[2]_0 ),
        .CE(1'b1),
        .D(app_ref_ack_ns),
        .Q(app_ref_ack),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    app_ref_r_reg
       (.C(\last_master_r_reg[2]_0 ),
        .CE(1'b1),
        .D(app_ref_r_reg_0),
        .Q(app_ref_r),
        .R(\periodic_read_request.periodic_rd_r_lcl_reg_0 ));
  FDRE app_sr_active_r_reg
       (.C(\last_master_r_reg[2]_0 ),
        .CE(1'b1),
        .D(app_sr_active_r_reg_0),
        .Q(app_sr_active),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair1205" *) 
  LUT3 #(
    .INIT(8'h2A)) 
    app_zq_ack_r_i_1
       (.I0(app_zq_r),
        .I1(\grant_r_reg[0] ),
        .I2(\zq_cntrl.zq_request_logic.zq_request_r_reg_0 ),
        .O(app_zq_ack_ns));
  FDRE #(
    .INIT(1'b0)) 
    app_zq_ack_r_reg
       (.C(\last_master_r_reg[2]_0 ),
        .CE(1'b1),
        .D(app_zq_ack_ns),
        .Q(app_zq_ack),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    app_zq_r_reg
       (.C(\last_master_r_reg[2]_0 ),
        .CE(1'b1),
        .D(app_zq_r_reg_0),
        .Q(app_zq_r),
        .R(\periodic_read_request.periodic_rd_r_lcl_reg_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1202" *) 
  LUT4 #(
    .INIT(16'h3F20)) 
    cke_r_i_1
       (.I0(\maintenance_request.maint_srx_r_lcl_reg_0 ),
        .I1(\maintenance_request.maint_sre_r_lcl_reg_0 ),
        .I2(insert_maint_r1),
        .I3(cke_r),
        .O(mc_cke_ns));
  LUT6 #(
    .INIT(64'h0000000000040000)) 
    i___13_i_1
       (.I0(\refresh_timer.refresh_timer_r_reg [5]),
        .I1(maint_prescaler_tick_r),
        .I2(\refresh_timer.refresh_timer_r_reg [2]),
        .I3(\refresh_timer.refresh_timer_r_reg[1]_0 [1]),
        .I4(\refresh_timer.refresh_timer_r_reg[1]_0 [0]),
        .I5(i___13_i_2_n_0),
        .O(\refresh_timer.refresh_timer_r_reg[5]_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    i___13_i_2
       (.I0(\refresh_timer.refresh_timer_r_reg [3]),
        .I1(\refresh_timer.refresh_timer_r_reg [4]),
        .O(i___13_i_2_n_0));
  LUT5 #(
    .INIT(32'h8AAAAAAA)) 
    i___14_i_1
       (.I0(\grant_r_reg[0] ),
        .I1(\zq_cntrl.zq_timer.zq_timer_r_reg [1]),
        .I2(\zq_cntrl.zq_timer.zq_timer_r_reg [0]),
        .I3(maint_prescaler_tick_r),
        .I4(\zq_cntrl.zq_timer.zq_timer_r[0]_i_4_n_0 ),
        .O(init_calib_complete_reg_rep__26_0));
  (* SOFT_HLUTNM = "soft_lutpair1203" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \maint_prescaler.maint_prescaler_r[0]_i_1 
       (.I0(Q[0]),
        .O(\maint_prescaler.maint_prescaler_r0 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1201" *) 
  LUT3 #(
    .INIT(8'hA9)) 
    \maint_prescaler.maint_prescaler_r[2]_i_1 
       (.I0(Q[2]),
        .I1(Q[1]),
        .I2(Q[0]),
        .O(\maint_prescaler.maint_prescaler_r0 [2]));
  (* SOFT_HLUTNM = "soft_lutpair1203" *) 
  LUT4 #(
    .INIT(16'hAAA9)) 
    \maint_prescaler.maint_prescaler_r[3]_i_1 
       (.I0(Q[3]),
        .I1(Q[2]),
        .I2(Q[0]),
        .I3(Q[1]),
        .O(\maint_prescaler.maint_prescaler_r0 [3]));
  LUT5 #(
    .INIT(32'hFFFFFFFE)) 
    \maint_prescaler.maint_prescaler_r[4]_i_1 
       (.I0(Q[4]),
        .I1(Q[3]),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(Q[2]),
        .O(sel));
  (* SOFT_HLUTNM = "soft_lutpair1201" *) 
  LUT5 #(
    .INIT(32'hAAAAAAA9)) 
    \maint_prescaler.maint_prescaler_r[4]_i_2 
       (.I0(Q[4]),
        .I1(Q[3]),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(Q[2]),
        .O(\maint_prescaler.maint_prescaler_r0 [4]));
  FDRE \maint_prescaler.maint_prescaler_r_reg[0] 
       (.C(\last_master_r_reg[2]_0 ),
        .CE(sel),
        .D(\maint_prescaler.maint_prescaler_r0 [0]),
        .Q(Q[0]),
        .R(SS));
  FDRE \maint_prescaler.maint_prescaler_r_reg[1] 
       (.C(\last_master_r_reg[2]_0 ),
        .CE(sel),
        .D(\maint_prescaler.maint_prescaler_r_reg[1]_0 ),
        .Q(Q[1]),
        .R(SS));
  FDSE \maint_prescaler.maint_prescaler_r_reg[2] 
       (.C(\last_master_r_reg[2]_0 ),
        .CE(sel),
        .D(\maint_prescaler.maint_prescaler_r0 [2]),
        .Q(Q[2]),
        .S(SS));
  FDRE \maint_prescaler.maint_prescaler_r_reg[3] 
       (.C(\last_master_r_reg[2]_0 ),
        .CE(sel),
        .D(\maint_prescaler.maint_prescaler_r0 [3]),
        .Q(Q[3]),
        .R(SS));
  FDSE \maint_prescaler.maint_prescaler_r_reg[4] 
       (.C(\last_master_r_reg[2]_0 ),
        .CE(sel),
        .D(\maint_prescaler.maint_prescaler_r0 [4]),
        .Q(Q[4]),
        .S(SS));
  LUT5 #(
    .INIT(32'h00000100)) 
    \maint_prescaler.maint_prescaler_tick_r_lcl_i_1 
       (.I0(Q[4]),
        .I1(Q[3]),
        .I2(Q[1]),
        .I3(Q[0]),
        .I4(Q[2]),
        .O(\maint_prescaler.maint_prescaler_tick_ns ));
  FDRE \maint_prescaler.maint_prescaler_tick_r_lcl_reg 
       (.C(\last_master_r_reg[2]_0 ),
        .CE(1'b1),
        .D(\maint_prescaler.maint_prescaler_tick_ns ),
        .Q(maint_prescaler_tick_r),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    maint_ref_zq_wip_r_reg
       (.C(\last_master_r_reg[2]_0 ),
        .CE(1'b1),
        .D(maint_ref_zq_wip_r_reg_0),
        .Q(maint_ref_zq_wip),
        .R(\periodic_read_request.periodic_rd_r_cnt_reg_0 ));
  mig_mig_7series_v4_2_round_robin_arb \maintenance_request.maint_arb0 
       (.D(D),
        .Q(\grant_r_reg[2] ),
        .app_sr_req(app_sr_req),
        .\grant_r_reg[0]_0 (\grant_r_reg[0] ),
        .\grant_r_reg[0]_1 (\grant_r_reg[0]_0 ),
        .\grant_r_reg[0]_2 (\zq_cntrl.zq_request_logic.zq_request_r_reg_0 ),
        .\grant_r_reg[0]_3 (\sr_cntrl.sre_request_logic.sre_request_r_reg_0 ),
        .\grant_r_reg[2]_0 (\grant_r_reg[2]_0 ),
        .\last_master_r_reg[2]_0 (\last_master_r_reg[2] ),
        .\last_master_r_reg[2]_1 (\last_master_r_reg[2]_1 ),
        .\last_master_r_reg[2]_2 (\maintenance_request.upd_last_master_r_reg_0 ),
        .\last_master_r_reg[2]_3 (\maintenance_request.new_maint_rank_r_reg_0 ),
        .\last_master_r_reg[2]_4 (\last_master_r_reg[2]_0 ),
        .\maintenance_request.maint_sre_ns (\maintenance_request.maint_sre_ns ),
        .\maintenance_request.maint_sre_r_lcl_reg (\maintenance_request.maint_arb0_n_4 ),
        .\maintenance_request.maint_sre_r_lcl_reg_0 (\maintenance_request.maint_sre_r_lcl_reg_0 ),
        .\maintenance_request.maint_srx_r_lcl_reg (\maintenance_request.maint_srx_r_lcl_reg_0 ),
        .\maintenance_request.maint_zq_r_lcl_reg (\maintenance_request.maint_arb0_n_8 ),
        .\maintenance_request.maint_zq_r_lcl_reg_0 (\maintenance_request.maint_zq_r_lcl_reg_0 ),
        .\sr_cntrl.ckesr_timer.ckesr_timer_r (\sr_cntrl.ckesr_timer.ckesr_timer_r ));
  FDRE \maintenance_request.maint_req_r_lcl_reg 
       (.C(\last_master_r_reg[2]_0 ),
        .CE(1'b1),
        .D(\maintenance_request.new_maint_rank_r_reg_0 ),
        .Q(maint_req_r),
        .R(1'b0));
  FDRE \maintenance_request.maint_sre_r_lcl_reg 
       (.C(\last_master_r_reg[2]_0 ),
        .CE(1'b1),
        .D(\maintenance_request.maint_sre_ns ),
        .Q(\maintenance_request.maint_sre_r_lcl_reg_0 ),
        .R(1'b0));
  FDRE \maintenance_request.maint_srx_r_lcl_reg 
       (.C(\last_master_r_reg[2]_0 ),
        .CE(1'b1),
        .D(\maintenance_request.maint_arb0_n_4 ),
        .Q(\maintenance_request.maint_srx_r_lcl_reg_0 ),
        .R(SR));
  FDRE \maintenance_request.maint_zq_r_lcl_reg 
       (.C(\last_master_r_reg[2]_0 ),
        .CE(1'b1),
        .D(\maintenance_request.maint_arb0_n_8 ),
        .Q(\maintenance_request.maint_zq_r_lcl_reg_0 ),
        .R(SR));
  FDRE \maintenance_request.new_maint_rank_r_reg 
       (.C(\last_master_r_reg[2]_0 ),
        .CE(1'b1),
        .D(\maintenance_request.upd_last_master_r_reg_0 ),
        .Q(\maintenance_request.new_maint_rank_r_reg_0 ),
        .R(1'b0));
  FDRE \maintenance_request.upd_last_master_r_reg 
       (.C(\last_master_r_reg[2]_0 ),
        .CE(1'b1),
        .D(\maintenance_request.upd_last_master_r_reg_1 ),
        .Q(\maintenance_request.upd_last_master_r_reg_0 ),
        .R(1'b0));
  FDRE \periodic_read_request.periodic_rd_grant_r_reg[0] 
       (.C(\last_master_r_reg[2]_0 ),
        .CE(1'b1),
        .D(\periodic_read_request.periodic_rd_grant_r_reg[0]_0 ),
        .Q(\periodic_read_request.periodic_rd_grant_r ),
        .R(1'b0));
  FDRE \periodic_read_request.periodic_rd_r_cnt_reg 
       (.C(\last_master_r_reg[2]_0 ),
        .CE(1'b1),
        .D(\periodic_read_request.periodic_rd_r_cnt_reg_1 ),
        .Q(\periodic_read_request.periodic_rd_r_cnt ),
        .R(\periodic_read_request.periodic_rd_r_cnt_reg_0 ));
  FDRE \periodic_read_request.periodic_rd_r_lcl_reg 
       (.C(\last_master_r_reg[2]_0 ),
        .CE(1'b1),
        .D(\periodic_read_request.periodic_rd_r_lcl_reg_1 ),
        .Q(periodic_rd_r),
        .R(\periodic_read_request.periodic_rd_r_lcl_reg_0 ));
  LUT4 #(
    .INIT(16'h0008)) 
    \periodic_read_request.upd_last_master_r_i_1 
       (.I0(\periodic_rd_generation.periodic_rd_request_r ),
        .I1(\grant_r_reg[0] ),
        .I2(\periodic_read_request.upd_last_master_r ),
        .I3(periodic_rd_r),
        .O(\periodic_read_request.upd_last_master_ns ));
  FDRE \periodic_read_request.upd_last_master_r_reg 
       (.C(\last_master_r_reg[2]_0 ),
        .CE(1'b1),
        .D(\periodic_read_request.upd_last_master_ns ),
        .Q(\periodic_read_request.upd_last_master_r ),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h88820008)) 
    \refresh_generation.refresh_bank_r[0]_i_1 
       (.I0(\grant_r_reg[0] ),
        .I1(\grant_r_reg[0]_0 ),
        .I2(app_ref_req),
        .I3(\refresh_timer.refresh_timer_r_reg[5]_0 ),
        .I4(\refresh_generation.refresh_bank_r[0]_i_2_n_0 ),
        .O(init_calib_complete_reg_rep__26));
  (* SOFT_HLUTNM = "soft_lutpair1202" *) 
  LUT4 #(
    .INIT(16'h0100)) 
    \refresh_generation.refresh_bank_r[0]_i_2 
       (.I0(\maintenance_request.maint_sre_r_lcl_reg_0 ),
        .I1(\maintenance_request.maint_zq_r_lcl_reg_0 ),
        .I2(\maintenance_request.maint_srx_r_lcl_reg_0 ),
        .I3(insert_maint_r1),
        .O(\refresh_generation.refresh_bank_r[0]_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \refresh_timer.refresh_timer_r[0]_i_1 
       (.I0(\refresh_timer.refresh_timer_r_reg[1]_0 [0]),
        .O(\refresh_timer.refresh_timer_r0 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1204" *) 
  LUT3 #(
    .INIT(8'hA9)) 
    \refresh_timer.refresh_timer_r[2]_i_1 
       (.I0(\refresh_timer.refresh_timer_r_reg [2]),
        .I1(\refresh_timer.refresh_timer_r_reg[1]_0 [1]),
        .I2(\refresh_timer.refresh_timer_r_reg[1]_0 [0]),
        .O(\refresh_timer.refresh_timer_r0 [2]));
  (* SOFT_HLUTNM = "soft_lutpair1200" *) 
  LUT4 #(
    .INIT(16'hAAA9)) 
    \refresh_timer.refresh_timer_r[3]_i_1 
       (.I0(\refresh_timer.refresh_timer_r_reg [3]),
        .I1(\refresh_timer.refresh_timer_r_reg [2]),
        .I2(\refresh_timer.refresh_timer_r_reg[1]_0 [0]),
        .I3(\refresh_timer.refresh_timer_r_reg[1]_0 [1]),
        .O(\refresh_timer.refresh_timer_r0 [3]));
  (* SOFT_HLUTNM = "soft_lutpair1200" *) 
  LUT5 #(
    .INIT(32'hAAAAAAA9)) 
    \refresh_timer.refresh_timer_r[4]_i_1 
       (.I0(\refresh_timer.refresh_timer_r_reg [4]),
        .I1(\refresh_timer.refresh_timer_r_reg [3]),
        .I2(\refresh_timer.refresh_timer_r_reg[1]_0 [1]),
        .I3(\refresh_timer.refresh_timer_r_reg[1]_0 [0]),
        .I4(\refresh_timer.refresh_timer_r_reg [2]),
        .O(\refresh_timer.refresh_timer_r0 [4]));
  LUT5 #(
    .INIT(32'hAAAAAA8A)) 
    \refresh_timer.refresh_timer_r[5]_i_1 
       (.I0(maint_prescaler_tick_r),
        .I1(\refresh_timer.refresh_timer_r_reg [5]),
        .I2(\refresh_timer.refresh_timer_r[5]_i_3_n_0 ),
        .I3(\refresh_timer.refresh_timer_r_reg [4]),
        .I4(\refresh_timer.refresh_timer_r_reg [3]),
        .O(\refresh_timer.refresh_timer_r0_0 ));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAAAAAA9)) 
    \refresh_timer.refresh_timer_r[5]_i_2 
       (.I0(\refresh_timer.refresh_timer_r_reg [5]),
        .I1(\refresh_timer.refresh_timer_r_reg [3]),
        .I2(\refresh_timer.refresh_timer_r_reg [4]),
        .I3(\refresh_timer.refresh_timer_r_reg[1]_0 [1]),
        .I4(\refresh_timer.refresh_timer_r_reg[1]_0 [0]),
        .I5(\refresh_timer.refresh_timer_r_reg [2]),
        .O(\refresh_timer.refresh_timer_r0 [5]));
  (* SOFT_HLUTNM = "soft_lutpair1204" *) 
  LUT3 #(
    .INIT(8'h01)) 
    \refresh_timer.refresh_timer_r[5]_i_3 
       (.I0(\refresh_timer.refresh_timer_r_reg[1]_0 [1]),
        .I1(\refresh_timer.refresh_timer_r_reg[1]_0 [0]),
        .I2(\refresh_timer.refresh_timer_r_reg [2]),
        .O(\refresh_timer.refresh_timer_r[5]_i_3_n_0 ));
  FDSE \refresh_timer.refresh_timer_r_reg[0] 
       (.C(\last_master_r_reg[2]_0 ),
        .CE(\refresh_timer.refresh_timer_r0_0 ),
        .D(\refresh_timer.refresh_timer_r0 [0]),
        .Q(\refresh_timer.refresh_timer_r_reg[1]_0 [0]),
        .S(\refresh_timer.refresh_timer_r_reg[5]_1 ));
  FDRE \refresh_timer.refresh_timer_r_reg[1] 
       (.C(\last_master_r_reg[2]_0 ),
        .CE(\refresh_timer.refresh_timer_r0_0 ),
        .D(\refresh_timer.refresh_timer_r_reg[1]_1 ),
        .Q(\refresh_timer.refresh_timer_r_reg[1]_0 [1]),
        .R(\refresh_timer.refresh_timer_r_reg[5]_1 ));
  FDSE \refresh_timer.refresh_timer_r_reg[2] 
       (.C(\last_master_r_reg[2]_0 ),
        .CE(\refresh_timer.refresh_timer_r0_0 ),
        .D(\refresh_timer.refresh_timer_r0 [2]),
        .Q(\refresh_timer.refresh_timer_r_reg [2]),
        .S(\refresh_timer.refresh_timer_r_reg[5]_1 ));
  FDRE \refresh_timer.refresh_timer_r_reg[3] 
       (.C(\last_master_r_reg[2]_0 ),
        .CE(\refresh_timer.refresh_timer_r0_0 ),
        .D(\refresh_timer.refresh_timer_r0 [3]),
        .Q(\refresh_timer.refresh_timer_r_reg [3]),
        .R(\refresh_timer.refresh_timer_r_reg[5]_1 ));
  FDRE \refresh_timer.refresh_timer_r_reg[4] 
       (.C(\last_master_r_reg[2]_0 ),
        .CE(\refresh_timer.refresh_timer_r0_0 ),
        .D(\refresh_timer.refresh_timer_r0 [4]),
        .Q(\refresh_timer.refresh_timer_r_reg [4]),
        .R(\refresh_timer.refresh_timer_r_reg[5]_1 ));
  FDSE \refresh_timer.refresh_timer_r_reg[5] 
       (.C(\last_master_r_reg[2]_0 ),
        .CE(\refresh_timer.refresh_timer_r0_0 ),
        .D(\refresh_timer.refresh_timer_r0 [5]),
        .Q(\refresh_timer.refresh_timer_r_reg [5]),
        .S(\refresh_timer.refresh_timer_r_reg[5]_1 ));
  LUT6 #(
    .INIT(64'h00000101000000FF)) 
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[0]_i_1 
       (.I0(\maintenance_request.maint_srx_r_lcl_reg_0 ),
        .I1(\maintenance_request.maint_zq_r_lcl_reg_0 ),
        .I2(\maintenance_request.maint_sre_r_lcl_reg_0 ),
        .I3(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ),
        .I4(\last_master_r_reg[2]_1 ),
        .I5(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ),
        .O(\maintenance_request.maint_srx_r_lcl_reg_1 ));
  LUT5 #(
    .INIT(32'h00000100)) 
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r[3]_i_2 
       (.I0(\maintenance_request.maint_sre_r_lcl_reg_0 ),
        .I1(\maintenance_request.maint_zq_r_lcl_reg_0 ),
        .I2(\maintenance_request.maint_srx_r_lcl_reg_0 ),
        .I3(\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ),
        .I4(\last_master_r_reg[2]_1 ),
        .O(\maintenance_request.maint_sre_r_lcl_reg_1 ));
  LUT2 #(
    .INIT(4'h8)) 
    \sr_cntrl.ckesr_timer.ckesr_timer_r[0]_i_1 
       (.I0(\maintenance_request.maint_sre_r_lcl_reg_0 ),
        .I1(insert_maint_r1),
        .O(\sr_cntrl.ckesr_timer.ckesr_timer_r[0]_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \sr_cntrl.ckesr_timer.ckesr_timer_r_reg[0] 
       (.C(\last_master_r_reg[2]_0 ),
        .CE(1'b1),
        .D(\sr_cntrl.ckesr_timer.ckesr_timer_r[0]_i_1_n_0 ),
        .Q(\sr_cntrl.ckesr_timer.ckesr_timer_r ),
        .R(1'b0));
  FDRE \sr_cntrl.sre_request_logic.sre_request_r_reg 
       (.C(\last_master_r_reg[2]_0 ),
        .CE(1'b1),
        .D(\sr_cntrl.sre_request_logic.sre_request_r_reg_1 ),
        .Q(\sr_cntrl.sre_request_logic.sre_request_r_reg_0 ),
        .R(SR));
  FDRE \zq_cntrl.zq_request_logic.zq_request_r_reg 
       (.C(\last_master_r_reg[2]_0 ),
        .CE(1'b1),
        .D(\zq_cntrl.zq_request_logic.zq_request_r_reg_2 ),
        .Q(\zq_cntrl.zq_request_logic.zq_request_r_reg_0 ),
        .R(\zq_cntrl.zq_request_logic.zq_request_r_reg_1 ));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_cntrl.zq_timer.zq_timer_r[0]_i_1 
       (.I0(init_calib_complete_reg_rep__26_0),
        .O(\zq_cntrl.zq_timer.zq_timer_r0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \zq_cntrl.zq_timer.zq_timer_r[0]_i_10 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [7]),
        .I1(\zq_cntrl.zq_timer.zq_timer_r_reg [6]),
        .I2(\zq_cntrl.zq_timer.zq_timer_r_reg [5]),
        .I3(\zq_cntrl.zq_timer.zq_timer_r_reg [4]),
        .O(\zq_cntrl.zq_timer.zq_timer_r[0]_i_10_n_0 ));
  LUT4 #(
    .INIT(16'h0001)) 
    \zq_cntrl.zq_timer.zq_timer_r[0]_i_11 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [19]),
        .I1(\zq_cntrl.zq_timer.zq_timer_r_reg [17]),
        .I2(\zq_cntrl.zq_timer.zq_timer_r_reg [18]),
        .I3(\zq_cntrl.zq_timer.zq_timer_r_reg [16]),
        .O(\zq_cntrl.zq_timer.zq_timer_r[0]_i_11_n_0 ));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \zq_cntrl.zq_timer.zq_timer_r[0]_i_12 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [14]),
        .I1(\zq_cntrl.zq_timer.zq_timer_r_reg [13]),
        .I2(\zq_cntrl.zq_timer.zq_timer_r_reg [15]),
        .I3(\zq_cntrl.zq_timer.zq_timer_r_reg [12]),
        .O(\zq_cntrl.zq_timer.zq_timer_r[0]_i_12_n_0 ));
  LUT4 #(
    .INIT(16'hA8AA)) 
    \zq_cntrl.zq_timer.zq_timer_r[0]_i_2 
       (.I0(maint_prescaler_tick_r),
        .I1(\zq_cntrl.zq_timer.zq_timer_r_reg [1]),
        .I2(\zq_cntrl.zq_timer.zq_timer_r_reg [0]),
        .I3(\zq_cntrl.zq_timer.zq_timer_r[0]_i_4_n_0 ),
        .O(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000010)) 
    \zq_cntrl.zq_timer.zq_timer_r[0]_i_4 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r[0]_i_9_n_0 ),
        .I1(\zq_cntrl.zq_timer.zq_timer_r[0]_i_10_n_0 ),
        .I2(\zq_cntrl.zq_timer.zq_timer_r[0]_i_11_n_0 ),
        .I3(\zq_cntrl.zq_timer.zq_timer_r[0]_i_12_n_0 ),
        .I4(\zq_cntrl.zq_timer.zq_timer_r_reg [3]),
        .I5(\zq_cntrl.zq_timer.zq_timer_r_reg [2]),
        .O(\zq_cntrl.zq_timer.zq_timer_r[0]_i_4_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_cntrl.zq_timer.zq_timer_r[0]_i_5 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [3]),
        .O(S[3]));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_cntrl.zq_timer.zq_timer_r[0]_i_6 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [2]),
        .O(S[2]));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_cntrl.zq_timer.zq_timer_r[0]_i_7 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [1]),
        .O(S[1]));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_cntrl.zq_timer.zq_timer_r[0]_i_8 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [0]),
        .O(S[0]));
  LUT4 #(
    .INIT(16'hFFFE)) 
    \zq_cntrl.zq_timer.zq_timer_r[0]_i_9 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [10]),
        .I1(\zq_cntrl.zq_timer.zq_timer_r_reg [9]),
        .I2(\zq_cntrl.zq_timer.zq_timer_r_reg [11]),
        .I3(\zq_cntrl.zq_timer.zq_timer_r_reg [8]),
        .O(\zq_cntrl.zq_timer.zq_timer_r[0]_i_9_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_cntrl.zq_timer.zq_timer_r[12]_i_2 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [15]),
        .O(\zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 [3]));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_cntrl.zq_timer.zq_timer_r[12]_i_3 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [14]),
        .O(\zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 [2]));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_cntrl.zq_timer.zq_timer_r[12]_i_4 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [13]),
        .O(\zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 [1]));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_cntrl.zq_timer.zq_timer_r[12]_i_5 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [12]),
        .O(\zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 [0]));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_cntrl.zq_timer.zq_timer_r[16]_i_2 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [19]),
        .O(\zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 [3]));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_cntrl.zq_timer.zq_timer_r[16]_i_3 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [18]),
        .O(\zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 [2]));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_cntrl.zq_timer.zq_timer_r[16]_i_4 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [17]),
        .O(\zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 [1]));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_cntrl.zq_timer.zq_timer_r[16]_i_5 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [16]),
        .O(\zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 [0]));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_cntrl.zq_timer.zq_timer_r[4]_i_2 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [7]),
        .O(\zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 [3]));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_cntrl.zq_timer.zq_timer_r[4]_i_3 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [6]),
        .O(\zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 [2]));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_cntrl.zq_timer.zq_timer_r[4]_i_4 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [5]),
        .O(\zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 [1]));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_cntrl.zq_timer.zq_timer_r[4]_i_5 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [4]),
        .O(\zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 [0]));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_cntrl.zq_timer.zq_timer_r[8]_i_2 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [11]),
        .O(\zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 [3]));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_cntrl.zq_timer.zq_timer_r[8]_i_3 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [10]),
        .O(\zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 [2]));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_cntrl.zq_timer.zq_timer_r[8]_i_4 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [9]),
        .O(\zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 [1]));
  LUT1 #(
    .INIT(2'h1)) 
    \zq_cntrl.zq_timer.zq_timer_r[8]_i_5 
       (.I0(\zq_cntrl.zq_timer.zq_timer_r_reg [8]),
        .O(\zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 [0]));
  FDRE \zq_cntrl.zq_timer.zq_timer_r_reg[0] 
       (.C(\last_master_r_reg[2]_0 ),
        .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),
        .D(O[0]),
        .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [0]),
        .R(\zq_cntrl.zq_timer.zq_timer_r0 ));
  FDSE \zq_cntrl.zq_timer.zq_timer_r_reg[10] 
       (.C(\last_master_r_reg[2]_0 ),
        .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),
        .D(\zq_cntrl.zq_timer.zq_timer_r_reg[11]_1 [2]),
        .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [10]),
        .S(\zq_cntrl.zq_timer.zq_timer_r0 ));
  FDRE \zq_cntrl.zq_timer.zq_timer_r_reg[11] 
       (.C(\last_master_r_reg[2]_0 ),
        .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),
        .D(\zq_cntrl.zq_timer.zq_timer_r_reg[11]_1 [3]),
        .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [11]),
        .R(\zq_cntrl.zq_timer.zq_timer_r0 ));
  FDRE \zq_cntrl.zq_timer.zq_timer_r_reg[12] 
       (.C(\last_master_r_reg[2]_0 ),
        .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),
        .D(\zq_cntrl.zq_timer.zq_timer_r_reg[15]_1 [0]),
        .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [12]),
        .R(\zq_cntrl.zq_timer.zq_timer_r0 ));
  FDRE \zq_cntrl.zq_timer.zq_timer_r_reg[13] 
       (.C(\last_master_r_reg[2]_0 ),
        .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),
        .D(\zq_cntrl.zq_timer.zq_timer_r_reg[15]_1 [1]),
        .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [13]),
        .R(\zq_cntrl.zq_timer.zq_timer_r0 ));
  FDSE \zq_cntrl.zq_timer.zq_timer_r_reg[14] 
       (.C(\last_master_r_reg[2]_0 ),
        .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),
        .D(\zq_cntrl.zq_timer.zq_timer_r_reg[15]_1 [2]),
        .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [14]),
        .S(\zq_cntrl.zq_timer.zq_timer_r0 ));
  FDSE \zq_cntrl.zq_timer.zq_timer_r_reg[15] 
       (.C(\last_master_r_reg[2]_0 ),
        .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),
        .D(\zq_cntrl.zq_timer.zq_timer_r_reg[15]_1 [3]),
        .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [15]),
        .S(\zq_cntrl.zq_timer.zq_timer_r0 ));
  FDSE \zq_cntrl.zq_timer.zq_timer_r_reg[16] 
       (.C(\last_master_r_reg[2]_0 ),
        .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),
        .D(\zq_cntrl.zq_timer.zq_timer_r_reg[19]_1 [0]),
        .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [16]),
        .S(\zq_cntrl.zq_timer.zq_timer_r0 ));
  FDRE \zq_cntrl.zq_timer.zq_timer_r_reg[17] 
       (.C(\last_master_r_reg[2]_0 ),
        .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),
        .D(\zq_cntrl.zq_timer.zq_timer_r_reg[19]_1 [1]),
        .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [17]),
        .R(\zq_cntrl.zq_timer.zq_timer_r0 ));
  FDRE \zq_cntrl.zq_timer.zq_timer_r_reg[18] 
       (.C(\last_master_r_reg[2]_0 ),
        .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),
        .D(\zq_cntrl.zq_timer.zq_timer_r_reg[19]_1 [2]),
        .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [18]),
        .R(\zq_cntrl.zq_timer.zq_timer_r0 ));
  FDSE \zq_cntrl.zq_timer.zq_timer_r_reg[19] 
       (.C(\last_master_r_reg[2]_0 ),
        .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),
        .D(\zq_cntrl.zq_timer.zq_timer_r_reg[19]_1 [3]),
        .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [19]),
        .S(\zq_cntrl.zq_timer.zq_timer_r0 ));
  FDRE \zq_cntrl.zq_timer.zq_timer_r_reg[1] 
       (.C(\last_master_r_reg[2]_0 ),
        .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),
        .D(O[1]),
        .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [1]),
        .R(\zq_cntrl.zq_timer.zq_timer_r0 ));
  FDRE \zq_cntrl.zq_timer.zq_timer_r_reg[2] 
       (.C(\last_master_r_reg[2]_0 ),
        .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),
        .D(O[2]),
        .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [2]),
        .R(\zq_cntrl.zq_timer.zq_timer_r0 ));
  FDRE \zq_cntrl.zq_timer.zq_timer_r_reg[3] 
       (.C(\last_master_r_reg[2]_0 ),
        .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),
        .D(O[3]),
        .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [3]),
        .R(\zq_cntrl.zq_timer.zq_timer_r0 ));
  FDRE \zq_cntrl.zq_timer.zq_timer_r_reg[4] 
       (.C(\last_master_r_reg[2]_0 ),
        .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),
        .D(\zq_cntrl.zq_timer.zq_timer_r_reg[7]_1 [0]),
        .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [4]),
        .R(\zq_cntrl.zq_timer.zq_timer_r0 ));
  FDRE \zq_cntrl.zq_timer.zq_timer_r_reg[5] 
       (.C(\last_master_r_reg[2]_0 ),
        .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),
        .D(\zq_cntrl.zq_timer.zq_timer_r_reg[7]_1 [1]),
        .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [5]),
        .R(\zq_cntrl.zq_timer.zq_timer_r0 ));
  FDRE \zq_cntrl.zq_timer.zq_timer_r_reg[6] 
       (.C(\last_master_r_reg[2]_0 ),
        .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),
        .D(\zq_cntrl.zq_timer.zq_timer_r_reg[7]_1 [2]),
        .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [6]),
        .R(\zq_cntrl.zq_timer.zq_timer_r0 ));
  FDRE \zq_cntrl.zq_timer.zq_timer_r_reg[7] 
       (.C(\last_master_r_reg[2]_0 ),
        .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),
        .D(\zq_cntrl.zq_timer.zq_timer_r_reg[7]_1 [3]),
        .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [7]),
        .R(\zq_cntrl.zq_timer.zq_timer_r0 ));
  FDRE \zq_cntrl.zq_timer.zq_timer_r_reg[8] 
       (.C(\last_master_r_reg[2]_0 ),
        .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),
        .D(\zq_cntrl.zq_timer.zq_timer_r_reg[11]_1 [0]),
        .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [8]),
        .R(\zq_cntrl.zq_timer.zq_timer_r0 ));
  FDRE \zq_cntrl.zq_timer.zq_timer_r_reg[9] 
       (.C(\last_master_r_reg[2]_0 ),
        .CE(\zq_cntrl.zq_timer.zq_timer_r[0]_i_2_n_0 ),
        .D(\zq_cntrl.zq_timer.zq_timer_r_reg[11]_1 [1]),
        .Q(\zq_cntrl.zq_timer.zq_timer_r_reg [9]),
        .R(\zq_cntrl.zq_timer.zq_timer_r0 ));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_rank_mach" *) 
module mig_mig_7series_v4_2_rank_mach
   (\inhbt_act_faw.act_delayed ,
    maint_sre_r,
    \maintenance_request.upd_last_master_r ,
    \maintenance_request.new_maint_rank_r ,
    maint_req_r,
    \periodic_read_request.upd_last_master_r ,
    app_ref_ack,
    app_zq_ack,
    \periodic_rd_generation.read_this_rank_r ,
    inhbt_act_faw_r,
    \zq_cntrl.zq_request_logic.zq_request_r ,
    maint_srx_r,
    \sr_cntrl.sre_request_logic.sre_request_r ,
    maint_zq_r,
    \periodic_rd_generation.periodic_rd_request_r ,
    periodic_rd_r,
    app_ref_r,
    app_zq_r,
    \periodic_read_request.periodic_rd_r_cnt ,
    \periodic_read_request.periodic_rd_grant_r ,
    app_sr_active,
    maint_ref_zq_wip,
    \periodic_rd_generation.periodic_rd_cntr1_r ,
    \refresh_generation.refresh_bank_r ,
    Q,
    \refresh_timer.refresh_timer_r_reg[5] ,
    \refresh_timer.refresh_timer_r_reg[1] ,
    init_calib_complete_reg_rep__26,
    mc_cke_ns,
    \grant_r_reg[2] ,
    \last_master_r_reg[2] ,
    S,
    \zq_cntrl.zq_timer.zq_timer_r_reg[7] ,
    \zq_cntrl.zq_timer.zq_timer_r_reg[11] ,
    \zq_cntrl.zq_timer.zq_timer_r_reg[15] ,
    \zq_cntrl.zq_timer.zq_timer_r_reg[19] ,
    \wtr_timer.wtr_cnt_r_reg[1] ,
    \maintenance_request.maint_srx_r_lcl_reg ,
    \maintenance_request.maint_sre_r_lcl_reg ,
    \periodic_rd_generation.periodic_rd_timer_r_reg[2] ,
    \inhbt_act_faw.faw_cnt_r_reg[2] ,
    \rtw_timer.rtw_cnt_r_reg[1] ,
    act_this_rank,
    \last_master_r_reg[2]_0 ,
    \maintenance_request.upd_last_master_r_reg ,
    \periodic_rd_generation.read_this_rank ,
    \zq_cntrl.zq_request_logic.zq_request_r_reg ,
    \zq_cntrl.zq_request_logic.zq_request_r_reg_0 ,
    SR,
    \sr_cntrl.sre_request_logic.sre_request_r_reg ,
    \periodic_rd_generation.periodic_rd_request_r_reg ,
    \periodic_read_request.periodic_rd_r_lcl_reg ,
    \periodic_read_request.periodic_rd_r_lcl_reg_0 ,
    app_ref_r_reg,
    app_zq_r_reg,
    \periodic_read_request.periodic_rd_r_cnt_reg ,
    \periodic_read_request.periodic_rd_r_cnt_reg_0 ,
    \periodic_read_request.periodic_rd_grant_r_reg[0] ,
    app_sr_active_r_reg,
    maint_ref_zq_wip_r_reg,
    \periodic_rd_generation.periodic_rd_cntr1_r_reg ,
    \periodic_rd_generation.periodic_rd_cntr1_r_reg_0 ,
    O,
    \zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 ,
    \zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 ,
    \zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 ,
    \zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 ,
    \periodic_rd_generation.periodic_rd_timer_r_reg[2]_0 ,
    \periodic_rd_generation.periodic_rd_timer_r_reg[2]_1 ,
    \grant_r_reg[0] ,
    app_ref_req,
    insert_maint_r1,
    cke_r,
    app_sr_req,
    \last_master_r_reg[2]_1 ,
    D,
    \grant_r_reg[2]_0 ,
    \wtr_timer.wtr_cnt_r_reg[1]_0 ,
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ,
    \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ,
    \inhbt_act_faw.inhbt_act_faw_r_reg ,
    \inhbt_act_faw.inhbt_act_faw_r_reg_0 ,
    \inhbt_act_faw.faw_cnt_r_reg[2]_0 ,
    \wtr_timer.wtr_cnt_r_reg[0] ,
    \rtw_timer.rtw_cnt_r_reg[1]_0 ,
    SS,
    \maint_prescaler.maint_prescaler_r_reg[1] ,
    \refresh_timer.refresh_timer_r_reg[5]_0 ,
    \refresh_timer.refresh_timer_r_reg[1]_0 );
  output \inhbt_act_faw.act_delayed ;
  output maint_sre_r;
  output \maintenance_request.upd_last_master_r ;
  output \maintenance_request.new_maint_rank_r ;
  output maint_req_r;
  output \periodic_read_request.upd_last_master_r ;
  output app_ref_ack;
  output app_zq_ack;
  output \periodic_rd_generation.read_this_rank_r ;
  output inhbt_act_faw_r;
  output \zq_cntrl.zq_request_logic.zq_request_r ;
  output maint_srx_r;
  output \sr_cntrl.sre_request_logic.sre_request_r ;
  output maint_zq_r;
  output \periodic_rd_generation.periodic_rd_request_r ;
  output periodic_rd_r;
  output app_ref_r;
  output app_zq_r;
  output \periodic_read_request.periodic_rd_r_cnt ;
  output \periodic_read_request.periodic_rd_grant_r ;
  output app_sr_active;
  output maint_ref_zq_wip;
  output \periodic_rd_generation.periodic_rd_cntr1_r ;
  output \refresh_generation.refresh_bank_r ;
  output [4:0]Q;
  output \refresh_timer.refresh_timer_r_reg[5] ;
  output [1:0]\refresh_timer.refresh_timer_r_reg[1] ;
  output init_calib_complete_reg_rep__26;
  output [0:0]mc_cke_ns;
  output [2:0]\grant_r_reg[2] ;
  output [2:0]\last_master_r_reg[2] ;
  output [3:0]S;
  output [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[7] ;
  output [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[11] ;
  output [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[15] ;
  output [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[19] ;
  output [1:0]\wtr_timer.wtr_cnt_r_reg[1] ;
  output [0:0]\maintenance_request.maint_srx_r_lcl_reg ;
  output \maintenance_request.maint_sre_r_lcl_reg ;
  output \periodic_rd_generation.periodic_rd_timer_r_reg[2] ;
  output [2:0]\inhbt_act_faw.faw_cnt_r_reg[2] ;
  output [1:0]\rtw_timer.rtw_cnt_r_reg[1] ;
  input act_this_rank;
  input \last_master_r_reg[2]_0 ;
  input \maintenance_request.upd_last_master_r_reg ;
  input \periodic_rd_generation.read_this_rank ;
  input \zq_cntrl.zq_request_logic.zq_request_r_reg ;
  input \zq_cntrl.zq_request_logic.zq_request_r_reg_0 ;
  input [0:0]SR;
  input \sr_cntrl.sre_request_logic.sre_request_r_reg ;
  input \periodic_rd_generation.periodic_rd_request_r_reg ;
  input \periodic_read_request.periodic_rd_r_lcl_reg ;
  input \periodic_read_request.periodic_rd_r_lcl_reg_0 ;
  input app_ref_r_reg;
  input app_zq_r_reg;
  input \periodic_read_request.periodic_rd_r_cnt_reg ;
  input \periodic_read_request.periodic_rd_r_cnt_reg_0 ;
  input \periodic_read_request.periodic_rd_grant_r_reg[0] ;
  input app_sr_active_r_reg;
  input maint_ref_zq_wip_r_reg;
  input \periodic_rd_generation.periodic_rd_cntr1_r_reg ;
  input \periodic_rd_generation.periodic_rd_cntr1_r_reg_0 ;
  input [3:0]O;
  input [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 ;
  input [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 ;
  input [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 ;
  input [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 ;
  input \periodic_rd_generation.periodic_rd_timer_r_reg[2]_0 ;
  input \periodic_rd_generation.periodic_rd_timer_r_reg[2]_1 ;
  input \grant_r_reg[0] ;
  input app_ref_req;
  input insert_maint_r1;
  input cke_r;
  input app_sr_req;
  input \last_master_r_reg[2]_1 ;
  input [1:0]D;
  input \grant_r_reg[2]_0 ;
  input \wtr_timer.wtr_cnt_r_reg[1]_0 ;
  input [0:0]\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ;
  input \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ;
  input \inhbt_act_faw.inhbt_act_faw_r_reg ;
  input \inhbt_act_faw.inhbt_act_faw_r_reg_0 ;
  input [2:0]\inhbt_act_faw.faw_cnt_r_reg[2]_0 ;
  input [0:0]\wtr_timer.wtr_cnt_r_reg[0] ;
  input [1:0]\rtw_timer.rtw_cnt_r_reg[1]_0 ;
  input [0:0]SS;
  input [0:0]\maint_prescaler.maint_prescaler_r_reg[1] ;
  input [0:0]\refresh_timer.refresh_timer_r_reg[5]_0 ;
  input [0:0]\refresh_timer.refresh_timer_r_reg[1]_0 ;

  wire [1:0]D;
  wire [3:0]O;
  wire [4:0]Q;
  wire [3:0]S;
  wire [0:0]SR;
  wire [0:0]SS;
  wire act_this_rank;
  wire app_ref_ack;
  wire app_ref_r;
  wire app_ref_r_reg;
  wire app_ref_req;
  wire app_sr_active;
  wire app_sr_active_r_reg;
  wire app_sr_req;
  wire app_zq_ack;
  wire app_zq_r;
  wire app_zq_r_reg;
  wire cke_r;
  wire \grant_r_reg[0] ;
  wire [2:0]\grant_r_reg[2] ;
  wire \grant_r_reg[2]_0 ;
  wire \inhbt_act_faw.act_delayed ;
  wire [2:0]\inhbt_act_faw.faw_cnt_r_reg[2] ;
  wire [2:0]\inhbt_act_faw.faw_cnt_r_reg[2]_0 ;
  wire \inhbt_act_faw.inhbt_act_faw_r_reg ;
  wire \inhbt_act_faw.inhbt_act_faw_r_reg_0 ;
  wire inhbt_act_faw_r;
  wire init_calib_complete_reg_rep__26;
  wire insert_maint_r1;
  wire [2:0]\last_master_r_reg[2] ;
  wire \last_master_r_reg[2]_0 ;
  wire \last_master_r_reg[2]_1 ;
  wire [0:0]\maint_prescaler.maint_prescaler_r_reg[1] ;
  wire maint_prescaler_tick_r;
  wire maint_ref_zq_wip;
  wire maint_ref_zq_wip_r_reg;
  wire maint_req_r;
  wire maint_sre_r;
  wire maint_srx_r;
  wire maint_zq_r;
  wire \maintenance_request.maint_sre_r_lcl_reg ;
  wire [0:0]\maintenance_request.maint_srx_r_lcl_reg ;
  wire \maintenance_request.new_maint_rank_r ;
  wire \maintenance_request.upd_last_master_r ;
  wire \maintenance_request.upd_last_master_r_reg ;
  wire [0:0]mc_cke_ns;
  wire \periodic_rd_generation.periodic_rd_cntr1_r ;
  wire \periodic_rd_generation.periodic_rd_cntr1_r_reg ;
  wire \periodic_rd_generation.periodic_rd_cntr1_r_reg_0 ;
  wire \periodic_rd_generation.periodic_rd_request_r ;
  wire \periodic_rd_generation.periodic_rd_request_r_reg ;
  wire \periodic_rd_generation.periodic_rd_timer_r_reg[2] ;
  wire \periodic_rd_generation.periodic_rd_timer_r_reg[2]_0 ;
  wire \periodic_rd_generation.periodic_rd_timer_r_reg[2]_1 ;
  wire \periodic_rd_generation.read_this_rank ;
  wire \periodic_rd_generation.read_this_rank_r ;
  wire periodic_rd_r;
  wire \periodic_read_request.periodic_rd_grant_r ;
  wire \periodic_read_request.periodic_rd_grant_r_reg[0] ;
  wire \periodic_read_request.periodic_rd_r_cnt ;
  wire \periodic_read_request.periodic_rd_r_cnt_reg ;
  wire \periodic_read_request.periodic_rd_r_cnt_reg_0 ;
  wire \periodic_read_request.periodic_rd_r_lcl_reg ;
  wire \periodic_read_request.periodic_rd_r_lcl_reg_0 ;
  wire \periodic_read_request.upd_last_master_r ;
  wire rank_common0_n_24;
  wire \refresh_generation.refresh_bank_r ;
  wire [1:0]\refresh_timer.refresh_timer_r_reg[1] ;
  wire [0:0]\refresh_timer.refresh_timer_r_reg[1]_0 ;
  wire \refresh_timer.refresh_timer_r_reg[5] ;
  wire [0:0]\refresh_timer.refresh_timer_r_reg[5]_0 ;
  wire [0:0]\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ;
  wire \rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ;
  wire [1:0]\rtw_timer.rtw_cnt_r_reg[1] ;
  wire [1:0]\rtw_timer.rtw_cnt_r_reg[1]_0 ;
  wire \sr_cntrl.sre_request_logic.sre_request_r ;
  wire \sr_cntrl.sre_request_logic.sre_request_r_reg ;
  wire [0:0]\wtr_timer.wtr_cnt_r_reg[0] ;
  wire [1:0]\wtr_timer.wtr_cnt_r_reg[1] ;
  wire \wtr_timer.wtr_cnt_r_reg[1]_0 ;
  wire \zq_cntrl.zq_request_logic.zq_request_r ;
  wire \zq_cntrl.zq_request_logic.zq_request_r_reg ;
  wire \zq_cntrl.zq_request_logic.zq_request_r_reg_0 ;
  wire [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[11] ;
  wire [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 ;
  wire [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[15] ;
  wire [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 ;
  wire [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[19] ;
  wire [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 ;
  wire [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[7] ;
  wire [3:0]\zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 ;

  mig_mig_7series_v4_2_rank_cntrl \rank_cntrl[0].rank_cntrl0 
       (.SR(SR),
        .act_this_rank(act_this_rank),
        .\inhbt_act_faw.act_delayed (\inhbt_act_faw.act_delayed ),
        .\inhbt_act_faw.faw_cnt_r_reg[2]_0 (\inhbt_act_faw.faw_cnt_r_reg[2] ),
        .\inhbt_act_faw.faw_cnt_r_reg[2]_1 (\inhbt_act_faw.faw_cnt_r_reg[2]_0 ),
        .\inhbt_act_faw.inhbt_act_faw_r_reg_0 (\inhbt_act_faw.inhbt_act_faw_r_reg ),
        .\inhbt_act_faw.inhbt_act_faw_r_reg_1 (\inhbt_act_faw.inhbt_act_faw_r_reg_0 ),
        .inhbt_act_faw_r(inhbt_act_faw_r),
        .maint_prescaler_tick_r(maint_prescaler_tick_r),
        .\periodic_rd_generation.periodic_rd_cntr1_r (\periodic_rd_generation.periodic_rd_cntr1_r ),
        .\periodic_rd_generation.periodic_rd_cntr1_r_reg_0 (\periodic_rd_generation.periodic_rd_cntr1_r_reg ),
        .\periodic_rd_generation.periodic_rd_cntr1_r_reg_1 (\periodic_rd_generation.periodic_rd_cntr1_r_reg_0 ),
        .\periodic_rd_generation.periodic_rd_request_r (\periodic_rd_generation.periodic_rd_request_r ),
        .\periodic_rd_generation.periodic_rd_request_r_reg_0 (\last_master_r_reg[2]_0 ),
        .\periodic_rd_generation.periodic_rd_request_r_reg_1 (\periodic_rd_generation.periodic_rd_request_r_reg ),
        .\periodic_rd_generation.periodic_rd_timer_r_reg[2]_0 (\periodic_rd_generation.periodic_rd_timer_r_reg[2] ),
        .\periodic_rd_generation.periodic_rd_timer_r_reg[2]_1 (\periodic_rd_generation.periodic_rd_timer_r_reg[2]_0 ),
        .\periodic_rd_generation.periodic_rd_timer_r_reg[2]_2 (\periodic_rd_generation.periodic_rd_timer_r_reg[2]_1 ),
        .\periodic_rd_generation.read_this_rank (\periodic_rd_generation.read_this_rank ),
        .\periodic_rd_generation.read_this_rank_r (\periodic_rd_generation.read_this_rank_r ),
        .\refresh_generation.refresh_bank_r_reg[0]_0 (\refresh_generation.refresh_bank_r ),
        .\refresh_generation.refresh_bank_r_reg[0]_1 (rank_common0_n_24),
        .\rtw_timer.rtw_cnt_r_reg[1]_0 (\rtw_timer.rtw_cnt_r_reg[1] ),
        .\rtw_timer.rtw_cnt_r_reg[1]_1 (\rtw_timer.rtw_cnt_r_reg[1]_0 ),
        .\wtr_timer.wtr_cnt_r_reg[0]_0 (\wtr_timer.wtr_cnt_r_reg[0] ),
        .\wtr_timer.wtr_cnt_r_reg[1]_0 (\wtr_timer.wtr_cnt_r_reg[1] ),
        .\wtr_timer.wtr_cnt_r_reg[1]_1 (\wtr_timer.wtr_cnt_r_reg[1]_0 ),
        .\wtr_timer.wtr_cnt_r_reg[1]_2 (\last_master_r_reg[2]_1 ));
  mig_mig_7series_v4_2_rank_common rank_common0
       (.D(D),
        .O(O),
        .Q(Q),
        .S(S),
        .SR(SR),
        .SS(SS),
        .app_ref_ack(app_ref_ack),
        .app_ref_r(app_ref_r),
        .app_ref_r_reg_0(app_ref_r_reg),
        .app_ref_req(app_ref_req),
        .app_sr_active(app_sr_active),
        .app_sr_active_r_reg_0(app_sr_active_r_reg),
        .app_sr_req(app_sr_req),
        .app_zq_ack(app_zq_ack),
        .app_zq_r(app_zq_r),
        .app_zq_r_reg_0(app_zq_r_reg),
        .cke_r(cke_r),
        .\grant_r_reg[0] (\grant_r_reg[0] ),
        .\grant_r_reg[0]_0 (\refresh_generation.refresh_bank_r ),
        .\grant_r_reg[2] (\grant_r_reg[2] ),
        .\grant_r_reg[2]_0 (\grant_r_reg[2]_0 ),
        .init_calib_complete_reg_rep__26(rank_common0_n_24),
        .init_calib_complete_reg_rep__26_0(init_calib_complete_reg_rep__26),
        .insert_maint_r1(insert_maint_r1),
        .\last_master_r_reg[2] (\last_master_r_reg[2] ),
        .\last_master_r_reg[2]_0 (\last_master_r_reg[2]_0 ),
        .\last_master_r_reg[2]_1 (\last_master_r_reg[2]_1 ),
        .\maint_prescaler.maint_prescaler_r_reg[1]_0 (\maint_prescaler.maint_prescaler_r_reg[1] ),
        .maint_prescaler_tick_r(maint_prescaler_tick_r),
        .maint_ref_zq_wip(maint_ref_zq_wip),
        .maint_ref_zq_wip_r_reg_0(maint_ref_zq_wip_r_reg),
        .maint_req_r(maint_req_r),
        .\maintenance_request.maint_sre_r_lcl_reg_0 (maint_sre_r),
        .\maintenance_request.maint_sre_r_lcl_reg_1 (\maintenance_request.maint_sre_r_lcl_reg ),
        .\maintenance_request.maint_srx_r_lcl_reg_0 (maint_srx_r),
        .\maintenance_request.maint_srx_r_lcl_reg_1 (\maintenance_request.maint_srx_r_lcl_reg ),
        .\maintenance_request.maint_zq_r_lcl_reg_0 (maint_zq_r),
        .\maintenance_request.new_maint_rank_r_reg_0 (\maintenance_request.new_maint_rank_r ),
        .\maintenance_request.upd_last_master_r_reg_0 (\maintenance_request.upd_last_master_r ),
        .\maintenance_request.upd_last_master_r_reg_1 (\maintenance_request.upd_last_master_r_reg ),
        .mc_cke_ns(mc_cke_ns),
        .\periodic_rd_generation.periodic_rd_request_r (\periodic_rd_generation.periodic_rd_request_r ),
        .periodic_rd_r(periodic_rd_r),
        .\periodic_read_request.periodic_rd_grant_r (\periodic_read_request.periodic_rd_grant_r ),
        .\periodic_read_request.periodic_rd_grant_r_reg[0]_0 (\periodic_read_request.periodic_rd_grant_r_reg[0] ),
        .\periodic_read_request.periodic_rd_r_cnt (\periodic_read_request.periodic_rd_r_cnt ),
        .\periodic_read_request.periodic_rd_r_cnt_reg_0 (\periodic_read_request.periodic_rd_r_cnt_reg ),
        .\periodic_read_request.periodic_rd_r_cnt_reg_1 (\periodic_read_request.periodic_rd_r_cnt_reg_0 ),
        .\periodic_read_request.periodic_rd_r_lcl_reg_0 (\periodic_read_request.periodic_rd_r_lcl_reg ),
        .\periodic_read_request.periodic_rd_r_lcl_reg_1 (\periodic_read_request.periodic_rd_r_lcl_reg_0 ),
        .\periodic_read_request.upd_last_master_r (\periodic_read_request.upd_last_master_r ),
        .\refresh_timer.refresh_timer_r_reg[1]_0 (\refresh_timer.refresh_timer_r_reg[1] ),
        .\refresh_timer.refresh_timer_r_reg[1]_1 (\refresh_timer.refresh_timer_r_reg[1]_0 ),
        .\refresh_timer.refresh_timer_r_reg[5]_0 (\refresh_timer.refresh_timer_r_reg[5] ),
        .\refresh_timer.refresh_timer_r_reg[5]_1 (\refresh_timer.refresh_timer_r_reg[5]_0 ),
        .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] (\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0] ),
        .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 (\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[0]_0 ),
        .\sr_cntrl.sre_request_logic.sre_request_r_reg_0 (\sr_cntrl.sre_request_logic.sre_request_r ),
        .\sr_cntrl.sre_request_logic.sre_request_r_reg_1 (\sr_cntrl.sre_request_logic.sre_request_r_reg ),
        .\zq_cntrl.zq_request_logic.zq_request_r_reg_0 (\zq_cntrl.zq_request_logic.zq_request_r ),
        .\zq_cntrl.zq_request_logic.zq_request_r_reg_1 (\zq_cntrl.zq_request_logic.zq_request_r_reg ),
        .\zq_cntrl.zq_request_logic.zq_request_r_reg_2 (\zq_cntrl.zq_request_logic.zq_request_r_reg_0 ),
        .\zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 (\zq_cntrl.zq_timer.zq_timer_r_reg[11] ),
        .\zq_cntrl.zq_timer.zq_timer_r_reg[11]_1 (\zq_cntrl.zq_timer.zq_timer_r_reg[11]_0 ),
        .\zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 (\zq_cntrl.zq_timer.zq_timer_r_reg[15] ),
        .\zq_cntrl.zq_timer.zq_timer_r_reg[15]_1 (\zq_cntrl.zq_timer.zq_timer_r_reg[15]_0 ),
        .\zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 (\zq_cntrl.zq_timer.zq_timer_r_reg[19] ),
        .\zq_cntrl.zq_timer.zq_timer_r_reg[19]_1 (\zq_cntrl.zq_timer.zq_timer_r_reg[19]_0 ),
        .\zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 (\zq_cntrl.zq_timer.zq_timer_r_reg[7] ),
        .\zq_cntrl.zq_timer.zq_timer_r_reg[7]_1 (\zq_cntrl.zq_timer.zq_timer_r_reg[7]_0 ));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_round_robin_arb" *) 
module mig_mig_7series_v4_2_round_robin_arb
   (\maintenance_request.maint_sre_ns ,
    Q,
    \maintenance_request.maint_sre_r_lcl_reg ,
    \last_master_r_reg[2]_0 ,
    \maintenance_request.maint_zq_r_lcl_reg ,
    \maintenance_request.maint_sre_r_lcl_reg_0 ,
    app_sr_req,
    \sr_cntrl.ckesr_timer.ckesr_timer_r ,
    \last_master_r_reg[2]_1 ,
    \maintenance_request.maint_srx_r_lcl_reg ,
    D,
    \grant_r_reg[0]_0 ,
    \grant_r_reg[0]_1 ,
    \grant_r_reg[0]_2 ,
    \grant_r_reg[0]_3 ,
    \grant_r_reg[2]_0 ,
    \last_master_r_reg[2]_2 ,
    \last_master_r_reg[2]_3 ,
    \maintenance_request.maint_zq_r_lcl_reg_0 ,
    \last_master_r_reg[2]_4 );
  output \maintenance_request.maint_sre_ns ;
  output [2:0]Q;
  output \maintenance_request.maint_sre_r_lcl_reg ;
  output [2:0]\last_master_r_reg[2]_0 ;
  output \maintenance_request.maint_zq_r_lcl_reg ;
  input \maintenance_request.maint_sre_r_lcl_reg_0 ;
  input app_sr_req;
  input \sr_cntrl.ckesr_timer.ckesr_timer_r ;
  input \last_master_r_reg[2]_1 ;
  input \maintenance_request.maint_srx_r_lcl_reg ;
  input [1:0]D;
  input \grant_r_reg[0]_0 ;
  input \grant_r_reg[0]_1 ;
  input \grant_r_reg[0]_2 ;
  input \grant_r_reg[0]_3 ;
  input \grant_r_reg[2]_0 ;
  input \last_master_r_reg[2]_2 ;
  input \last_master_r_reg[2]_3 ;
  input \maintenance_request.maint_zq_r_lcl_reg_0 ;
  input \last_master_r_reg[2]_4 ;

  wire [1:0]D;
  wire [2:0]Q;
  wire app_sr_req;
  wire \grant_r[0]_i_1_n_0 ;
  wire \grant_r[1]_i_1_n_0 ;
  wire \grant_r[1]_i_2_n_0 ;
  wire \grant_r[1]_i_3_n_0 ;
  wire \grant_r[2]_i_1_n_0 ;
  wire \grant_r_reg[0]_0 ;
  wire \grant_r_reg[0]_1 ;
  wire \grant_r_reg[0]_2 ;
  wire \grant_r_reg[0]_3 ;
  wire \grant_r_reg[2]_0 ;
  wire \last_master_r[2]_i_1_n_0 ;
  wire [2:0]\last_master_r_reg[2]_0 ;
  wire \last_master_r_reg[2]_1 ;
  wire \last_master_r_reg[2]_2 ;
  wire \last_master_r_reg[2]_3 ;
  wire \last_master_r_reg[2]_4 ;
  wire \maintenance_request.maint_sre_ns ;
  wire \maintenance_request.maint_sre_r_lcl_i_2_n_0 ;
  wire \maintenance_request.maint_sre_r_lcl_reg ;
  wire \maintenance_request.maint_sre_r_lcl_reg_0 ;
  wire \maintenance_request.maint_srx_r_lcl_reg ;
  wire \maintenance_request.maint_zq_r_lcl_reg ;
  wire \maintenance_request.maint_zq_r_lcl_reg_0 ;
  wire \sr_cntrl.ckesr_timer.ckesr_timer_r ;

  LUT6 #(
    .INIT(64'h0000000C04040C0C)) 
    \grant_r[0]_i_1 
       (.I0(D[1]),
        .I1(\grant_r_reg[0]_0 ),
        .I2(\grant_r_reg[0]_1 ),
        .I3(\grant_r_reg[0]_2 ),
        .I4(\grant_r_reg[0]_3 ),
        .I5(D[0]),
        .O(\grant_r[0]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hAA80000080800000)) 
    \grant_r[1]_i_1 
       (.I0(\grant_r_reg[0]_2 ),
        .I1(\grant_r_reg[2]_0 ),
        .I2(\grant_r[1]_i_2_n_0 ),
        .I3(\grant_r_reg[0]_1 ),
        .I4(\grant_r_reg[0]_0 ),
        .I5(\grant_r[1]_i_3_n_0 ),
        .O(\grant_r[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1199" *) 
  LUT4 #(
    .INIT(16'h04F7)) 
    \grant_r[1]_i_2 
       (.I0(Q[1]),
        .I1(\last_master_r_reg[2]_2 ),
        .I2(\last_master_r_reg[2]_3 ),
        .I3(\last_master_r_reg[2]_0 [1]),
        .O(\grant_r[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFF7F777FFF)) 
    \grant_r[1]_i_3 
       (.I0(\grant_r_reg[0]_3 ),
        .I1(\grant_r_reg[0]_0 ),
        .I2(Q[1]),
        .I3(\maintenance_request.maint_sre_r_lcl_i_2_n_0 ),
        .I4(\last_master_r_reg[2]_0 [1]),
        .I5(\last_master_r_reg[2]_1 ),
        .O(\grant_r[1]_i_3_n_0 ));
  LUT6 #(
    .INIT(64'h7070300000000000)) 
    \grant_r[2]_i_1 
       (.I0(D[0]),
        .I1(\grant_r_reg[0]_2 ),
        .I2(\grant_r_reg[0]_0 ),
        .I3(\grant_r_reg[0]_1 ),
        .I4(\grant_r_reg[2]_0 ),
        .I5(\grant_r_reg[0]_3 ),
        .O(\grant_r[2]_i_1_n_0 ));
  FDRE \grant_r_reg[0] 
       (.C(\last_master_r_reg[2]_4 ),
        .CE(1'b1),
        .D(\grant_r[0]_i_1_n_0 ),
        .Q(Q[0]),
        .R(1'b0));
  FDRE \grant_r_reg[1] 
       (.C(\last_master_r_reg[2]_4 ),
        .CE(1'b1),
        .D(\grant_r[1]_i_1_n_0 ),
        .Q(Q[1]),
        .R(1'b0));
  FDRE \grant_r_reg[2] 
       (.C(\last_master_r_reg[2]_4 ),
        .CE(1'b1),
        .D(\grant_r[2]_i_1_n_0 ),
        .Q(Q[2]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair1198" *) 
  LUT5 #(
    .INIT(32'hFFFFFB08)) 
    \last_master_r[2]_i_1 
       (.I0(Q[2]),
        .I1(\last_master_r_reg[2]_2 ),
        .I2(\last_master_r_reg[2]_3 ),
        .I3(\last_master_r_reg[2]_0 [2]),
        .I4(\last_master_r_reg[2]_1 ),
        .O(\last_master_r[2]_i_1_n_0 ));
  FDRE \last_master_r_reg[0] 
       (.C(\last_master_r_reg[2]_4 ),
        .CE(1'b1),
        .D(D[0]),
        .Q(\last_master_r_reg[2]_0 [0]),
        .R(1'b0));
  FDRE \last_master_r_reg[1] 
       (.C(\last_master_r_reg[2]_4 ),
        .CE(1'b1),
        .D(D[1]),
        .Q(\last_master_r_reg[2]_0 [1]),
        .R(1'b0));
  FDRE \last_master_r_reg[2] 
       (.C(\last_master_r_reg[2]_4 ),
        .CE(1'b1),
        .D(\last_master_r[2]_i_1_n_0 ),
        .Q(\last_master_r_reg[2]_0 [2]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h00000000FFA800A8)) 
    \maintenance_request.maint_sre_r_lcl_i_1 
       (.I0(\maintenance_request.maint_sre_r_lcl_reg_0 ),
        .I1(app_sr_req),
        .I2(\sr_cntrl.ckesr_timer.ckesr_timer_r ),
        .I3(\maintenance_request.maint_sre_r_lcl_i_2_n_0 ),
        .I4(Q[2]),
        .I5(\last_master_r_reg[2]_1 ),
        .O(\maintenance_request.maint_sre_ns ));
  (* SOFT_HLUTNM = "soft_lutpair1198" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \maintenance_request.maint_sre_r_lcl_i_2 
       (.I0(\last_master_r_reg[2]_2 ),
        .I1(\last_master_r_reg[2]_3 ),
        .O(\maintenance_request.maint_sre_r_lcl_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h5702575702020202)) 
    \maintenance_request.maint_srx_r_lcl_i_1 
       (.I0(\maintenance_request.maint_sre_r_lcl_reg_0 ),
        .I1(app_sr_req),
        .I2(\sr_cntrl.ckesr_timer.ckesr_timer_r ),
        .I3(Q[2]),
        .I4(\maintenance_request.maint_sre_r_lcl_i_2_n_0 ),
        .I5(\maintenance_request.maint_srx_r_lcl_reg ),
        .O(\maintenance_request.maint_sre_r_lcl_reg ));
  (* SOFT_HLUTNM = "soft_lutpair1199" *) 
  LUT4 #(
    .INIT(16'hBA8A)) 
    \maintenance_request.maint_zq_r_lcl_i_1 
       (.I0(\maintenance_request.maint_zq_r_lcl_reg_0 ),
        .I1(\last_master_r_reg[2]_3 ),
        .I2(\last_master_r_reg[2]_2 ),
        .I3(Q[1]),
        .O(\maintenance_request.maint_zq_r_lcl_reg ));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_round_robin_arb" *) 
module mig_mig_7series_v4_2_round_robin_arb__parameterized1
   (granted_col_r_reg,
    \grant_r_reg[2]_0 ,
    \periodic_rd_generation.read_this_rank_r_reg ,
    Q,
    \periodic_rd_generation.read_this_rank ,
    DIC,
    mc_odt_ns,
    D,
    granted_col_r_reg_0,
    granted_col_r_reg_1,
    E,
    \rtw_timer.rtw_cnt_r_reg[1] ,
    col_rd_wr,
    \grant_r_reg[0]_0 ,
    \wr_this_rank_r_reg[0] ,
    \wr_this_rank_r_reg[0]_0 ,
    \grant_r_reg[3]_0 ,
    rnk_config_valid_r_lcl_reg,
    rnk_config_valid_r_lcl_reg_0,
    rnk_config_valid_r_lcl_reg_1,
    rnk_config_valid_r_lcl_reg_2,
    col_wr_data_buf_addr,
    granted_col_r_reg_2,
    granted_col_r_reg_3,
    req_bank_rdy_r_reg,
    \rtw_timer.rtw_cnt_r_reg[1]_0 ,
    \wtr_timer.wtr_cnt_r_reg[1] ,
    \grant_r_reg[0]_1 ,
    \cmd_pipe_plus.mc_data_offset_2_reg[0] ,
    \grant_r_reg[0]_2 ,
    \grant_r_reg[0]_3 ,
    \grant_r_reg[2]_1 ,
    \grant_r_reg[0]_4 ,
    \periodic_rd_generation.read_this_rank_r ,
    rd_this_rank_r,
    req_periodic_rd_r,
    \rtw_timer.rtw_cnt_r_reg[0] ,
    \col_mux.col_periodic_rd_r ,
    \cmd_pipe_plus.mc_odt_reg[0] ,
    O,
    \cmd_pipe_plus.mc_data_offset_1_reg[3] ,
    \cmd_pipe_plus.mc_data_offset_reg[3] ,
    \rtw_timer.rtw_cnt_r_reg[1]_1 ,
    \cmd_pipe_plus.mc_data_offset_2_reg[0]_0 ,
    \cmd_pipe_plus.mc_data_offset_2_reg[0]_1 ,
    i___22_i_1_0,
    rd_wr_r,
    col_rd_wr_r,
    wr_this_rank_r,
    \grant_r[3]_i_8 ,
    \grant_r[3]_i_8_0 ,
    \grant_r[3]_i_10 ,
    ofs_rdy_r,
    \genblk3[1].rnk_config_strobe_r_reg ,
    \genblk3[2].rnk_config_strobe_r_reg ,
    rnk_config_strobe,
    ofs_rdy_r_0,
    ofs_rdy_r_1,
    ofs_rdy_r_2,
    \last_master_r_reg[1]_0 ,
    req_data_buf_addr_r,
    \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ,
    \cmd_pipe_plus.mc_bank_reg[5] ,
    \cmd_pipe_plus.mc_bank_reg[5]_0 ,
    \cmd_pipe_plus.mc_bank_reg[5]_1 ,
    \cmd_pipe_plus.mc_bank_reg[5]_2 ,
    \cmd_pipe_plus.mc_address_reg[23] ,
    \cmd_pipe_plus.mc_address_reg[23]_0 ,
    \cmd_pipe_plus.mc_address_reg[23]_1 ,
    \cmd_pipe_plus.mc_address_reg[23]_2 ,
    \cmd_pipe_plus.mc_address_reg[24] ,
    \cmd_pipe_plus.mc_address_reg[24]_0 ,
    \cmd_pipe_plus.mc_address_reg[24]_1 ,
    \cmd_pipe_plus.mc_address_reg[24]_2 ,
    req_bank_rdy_r,
    \grant_r[2]_i_3 ,
    \grant_r[2]_i_3_0 ,
    \last_master_r_reg[3]_0 );
  output granted_col_r_reg;
  output \grant_r_reg[2]_0 ;
  output \periodic_rd_generation.read_this_rank_r_reg ;
  output [3:0]Q;
  output \periodic_rd_generation.read_this_rank ;
  output [0:0]DIC;
  output [0:0]mc_odt_ns;
  output [0:0]D;
  output [0:0]granted_col_r_reg_0;
  output [0:0]granted_col_r_reg_1;
  output [0:0]E;
  output [1:0]\rtw_timer.rtw_cnt_r_reg[1] ;
  output col_rd_wr;
  output \grant_r_reg[0]_0 ;
  output \wr_this_rank_r_reg[0] ;
  output \wr_this_rank_r_reg[0]_0 ;
  output \grant_r_reg[3]_0 ;
  output rnk_config_valid_r_lcl_reg;
  output rnk_config_valid_r_lcl_reg_0;
  output rnk_config_valid_r_lcl_reg_1;
  output rnk_config_valid_r_lcl_reg_2;
  output [3:0]col_wr_data_buf_addr;
  output [2:0]granted_col_r_reg_2;
  output [10:0]granted_col_r_reg_3;
  output req_bank_rdy_r_reg;
  output \rtw_timer.rtw_cnt_r_reg[1]_0 ;
  output \wtr_timer.wtr_cnt_r_reg[1] ;
  output \grant_r_reg[0]_1 ;
  input \cmd_pipe_plus.mc_data_offset_2_reg[0] ;
  input \grant_r_reg[0]_2 ;
  input \grant_r_reg[0]_3 ;
  input \grant_r_reg[2]_1 ;
  input \grant_r_reg[0]_4 ;
  input \periodic_rd_generation.read_this_rank_r ;
  input [3:0]rd_this_rank_r;
  input [3:0]req_periodic_rd_r;
  input \rtw_timer.rtw_cnt_r_reg[0] ;
  input \col_mux.col_periodic_rd_r ;
  input \cmd_pipe_plus.mc_odt_reg[0] ;
  input [0:0]O;
  input [0:0]\cmd_pipe_plus.mc_data_offset_1_reg[3] ;
  input [0:0]\cmd_pipe_plus.mc_data_offset_reg[3] ;
  input [1:0]\rtw_timer.rtw_cnt_r_reg[1]_1 ;
  input \cmd_pipe_plus.mc_data_offset_2_reg[0]_0 ;
  input \cmd_pipe_plus.mc_data_offset_2_reg[0]_1 ;
  input i___22_i_1_0;
  input [0:0]rd_wr_r;
  input col_rd_wr_r;
  input [3:0]wr_this_rank_r;
  input \grant_r[3]_i_8 ;
  input \grant_r[3]_i_8_0 ;
  input \grant_r[3]_i_10 ;
  input ofs_rdy_r;
  input \genblk3[1].rnk_config_strobe_r_reg ;
  input \genblk3[2].rnk_config_strobe_r_reg ;
  input rnk_config_strobe;
  input ofs_rdy_r_0;
  input ofs_rdy_r_1;
  input ofs_rdy_r_2;
  input \last_master_r_reg[1]_0 ;
  input [15:0]req_data_buf_addr_r;
  input [3:0]\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ;
  input [2:0]\cmd_pipe_plus.mc_bank_reg[5] ;
  input [2:0]\cmd_pipe_plus.mc_bank_reg[5]_0 ;
  input [2:0]\cmd_pipe_plus.mc_bank_reg[5]_1 ;
  input [2:0]\cmd_pipe_plus.mc_bank_reg[5]_2 ;
  input [9:0]\cmd_pipe_plus.mc_address_reg[23] ;
  input [9:0]\cmd_pipe_plus.mc_address_reg[23]_0 ;
  input [9:0]\cmd_pipe_plus.mc_address_reg[23]_1 ;
  input [9:0]\cmd_pipe_plus.mc_address_reg[23]_2 ;
  input \cmd_pipe_plus.mc_address_reg[24] ;
  input \cmd_pipe_plus.mc_address_reg[24]_0 ;
  input \cmd_pipe_plus.mc_address_reg[24]_1 ;
  input \cmd_pipe_plus.mc_address_reg[24]_2 ;
  input req_bank_rdy_r;
  input \grant_r[2]_i_3 ;
  input [0:0]\grant_r[2]_i_3_0 ;
  input \last_master_r_reg[3]_0 ;

  wire [0:0]D;
  wire [0:0]DIC;
  wire [0:0]E;
  wire [0:0]O;
  wire [3:0]Q;
  wire \cmd_pipe_plus.mc_address[14]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[15]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[16]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[17]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[18]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[19]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[20]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[21]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[22]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[23]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[24]_i_2_n_0 ;
  wire [9:0]\cmd_pipe_plus.mc_address_reg[23] ;
  wire [9:0]\cmd_pipe_plus.mc_address_reg[23]_0 ;
  wire [9:0]\cmd_pipe_plus.mc_address_reg[23]_1 ;
  wire [9:0]\cmd_pipe_plus.mc_address_reg[23]_2 ;
  wire \cmd_pipe_plus.mc_address_reg[24] ;
  wire \cmd_pipe_plus.mc_address_reg[24]_0 ;
  wire \cmd_pipe_plus.mc_address_reg[24]_1 ;
  wire \cmd_pipe_plus.mc_address_reg[24]_2 ;
  wire \cmd_pipe_plus.mc_bank[3]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_bank[4]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_bank[5]_i_2_n_0 ;
  wire [2:0]\cmd_pipe_plus.mc_bank_reg[5] ;
  wire [2:0]\cmd_pipe_plus.mc_bank_reg[5]_0 ;
  wire [2:0]\cmd_pipe_plus.mc_bank_reg[5]_1 ;
  wire [2:0]\cmd_pipe_plus.mc_bank_reg[5]_2 ;
  wire [0:0]\cmd_pipe_plus.mc_data_offset_1_reg[3] ;
  wire \cmd_pipe_plus.mc_data_offset_2_reg[0] ;
  wire \cmd_pipe_plus.mc_data_offset_2_reg[0]_0 ;
  wire \cmd_pipe_plus.mc_data_offset_2_reg[0]_1 ;
  wire [0:0]\cmd_pipe_plus.mc_data_offset_reg[3] ;
  wire \cmd_pipe_plus.mc_odt_reg[0] ;
  wire \col_mux.col_periodic_rd_r ;
  wire \col_mux.col_periodic_rd_r_i_2_n_0 ;
  wire col_rd_wr;
  wire col_rd_wr_r;
  wire [3:0]col_wr_data_buf_addr;
  wire \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[0]_i_2_n_0 ;
  wire \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[1]_i_2_n_0 ;
  wire \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[2]_i_2_n_0 ;
  wire \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[3]_i_2_n_0 ;
  wire [3:0]\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] ;
  wire \genblk3[1].rnk_config_strobe_r_reg ;
  wire \genblk3[2].rnk_config_strobe_r_reg ;
  wire \grant_r[0]_i_1__0_n_0 ;
  wire \grant_r[1]_i_1__1_n_0 ;
  wire \grant_r[2]_i_1__0_n_0 ;
  wire \grant_r[2]_i_2_n_0 ;
  wire \grant_r[2]_i_3 ;
  wire [0:0]\grant_r[2]_i_3_0 ;
  wire \grant_r[3]_i_10 ;
  wire \grant_r[3]_i_17_n_0 ;
  wire \grant_r[3]_i_1__0_n_0 ;
  wire \grant_r[3]_i_4_n_0 ;
  wire \grant_r[3]_i_8 ;
  wire \grant_r[3]_i_8_0 ;
  wire \grant_r_reg[0]_0 ;
  wire \grant_r_reg[0]_1 ;
  wire \grant_r_reg[0]_2 ;
  wire \grant_r_reg[0]_3 ;
  wire \grant_r_reg[0]_4 ;
  wire \grant_r_reg[2]_0 ;
  wire \grant_r_reg[2]_1 ;
  wire \grant_r_reg[3]_0 ;
  wire granted_col_r_reg;
  wire [0:0]granted_col_r_reg_0;
  wire [0:0]granted_col_r_reg_1;
  wire [2:0]granted_col_r_reg_2;
  wire [10:0]granted_col_r_reg_3;
  wire i___22_i_1_0;
  wire i___22_i_2_n_0;
  wire i___22_i_3_n_0;
  wire [3:0]last_master_r;
  wire \last_master_r[0]_i_1_n_0 ;
  wire \last_master_r[1]_i_1_n_0 ;
  wire \last_master_r[2]_i_1__0_n_0 ;
  wire \last_master_r[3]_i_1_n_0 ;
  wire \last_master_r_reg[1]_0 ;
  wire \last_master_r_reg[3]_0 ;
  wire [0:0]mc_odt_ns;
  wire ofs_rdy_r;
  wire ofs_rdy_r_0;
  wire ofs_rdy_r_1;
  wire ofs_rdy_r_2;
  wire \periodic_rd_generation.read_this_rank ;
  wire \periodic_rd_generation.read_this_rank_r ;
  wire \periodic_rd_generation.read_this_rank_r_i_2_n_0 ;
  wire \periodic_rd_generation.read_this_rank_r_reg ;
  wire [3:0]rd_this_rank_r;
  wire [0:0]rd_wr_r;
  wire req_bank_rdy_r;
  wire req_bank_rdy_r_reg;
  wire [15:0]req_data_buf_addr_r;
  wire [3:0]req_periodic_rd_r;
  wire rnk_config_strobe;
  wire rnk_config_valid_r_lcl_reg;
  wire rnk_config_valid_r_lcl_reg_0;
  wire rnk_config_valid_r_lcl_reg_1;
  wire rnk_config_valid_r_lcl_reg_2;
  wire \rtw_timer.rtw_cnt_r[1]_i_2_n_0 ;
  wire \rtw_timer.rtw_cnt_r_reg[0] ;
  wire [1:0]\rtw_timer.rtw_cnt_r_reg[1] ;
  wire \rtw_timer.rtw_cnt_r_reg[1]_0 ;
  wire [1:0]\rtw_timer.rtw_cnt_r_reg[1]_1 ;
  wire [3:0]wr_this_rank_r;
  wire \wr_this_rank_r_reg[0] ;
  wire \wr_this_rank_r_reg[0]_0 ;
  wire \wtr_timer.wtr_cnt_r_reg[1] ;

  LUT4 #(
    .INIT(16'hF737)) 
    \cmd_pipe_plus.mc_address[14]_i_1 
       (.I0(\cmd_pipe_plus.mc_address[14]_i_2_n_0 ),
        .I1(\cmd_pipe_plus.mc_data_offset_2_reg[0] ),
        .I2(Q[3]),
        .I3(\cmd_pipe_plus.mc_address_reg[23] [0]),
        .O(granted_col_r_reg_3[0]));
  LUT6 #(
    .INIT(64'h00000F77FFFF0F77)) 
    \cmd_pipe_plus.mc_address[14]_i_2 
       (.I0(\cmd_pipe_plus.mc_address_reg[23]_0 [0]),
        .I1(Q[0]),
        .I2(\cmd_pipe_plus.mc_address_reg[23]_1 [0]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(\cmd_pipe_plus.mc_address_reg[23]_2 [0]),
        .O(\cmd_pipe_plus.mc_address[14]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hF737)) 
    \cmd_pipe_plus.mc_address[15]_i_1 
       (.I0(\cmd_pipe_plus.mc_address[15]_i_2_n_0 ),
        .I1(\cmd_pipe_plus.mc_data_offset_2_reg[0] ),
        .I2(Q[3]),
        .I3(\cmd_pipe_plus.mc_address_reg[23] [1]),
        .O(granted_col_r_reg_3[1]));
  LUT6 #(
    .INIT(64'h00000F77FFFF0F77)) 
    \cmd_pipe_plus.mc_address[15]_i_2 
       (.I0(\cmd_pipe_plus.mc_address_reg[23]_0 [1]),
        .I1(Q[0]),
        .I2(\cmd_pipe_plus.mc_address_reg[23]_1 [1]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(\cmd_pipe_plus.mc_address_reg[23]_2 [1]),
        .O(\cmd_pipe_plus.mc_address[15]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hF737)) 
    \cmd_pipe_plus.mc_address[16]_i_1 
       (.I0(\cmd_pipe_plus.mc_address[16]_i_2_n_0 ),
        .I1(\cmd_pipe_plus.mc_data_offset_2_reg[0] ),
        .I2(Q[3]),
        .I3(\cmd_pipe_plus.mc_address_reg[23] [2]),
        .O(granted_col_r_reg_3[2]));
  LUT6 #(
    .INIT(64'h00000F77FFFF0F77)) 
    \cmd_pipe_plus.mc_address[16]_i_2 
       (.I0(\cmd_pipe_plus.mc_address_reg[23]_0 [2]),
        .I1(Q[0]),
        .I2(\cmd_pipe_plus.mc_address_reg[23]_1 [2]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(\cmd_pipe_plus.mc_address_reg[23]_2 [2]),
        .O(\cmd_pipe_plus.mc_address[16]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hF737)) 
    \cmd_pipe_plus.mc_address[17]_i_1 
       (.I0(\cmd_pipe_plus.mc_address[17]_i_2_n_0 ),
        .I1(\cmd_pipe_plus.mc_data_offset_2_reg[0] ),
        .I2(Q[3]),
        .I3(\cmd_pipe_plus.mc_address_reg[23] [3]),
        .O(granted_col_r_reg_3[3]));
  LUT6 #(
    .INIT(64'h00000F77FFFF0F77)) 
    \cmd_pipe_plus.mc_address[17]_i_2 
       (.I0(\cmd_pipe_plus.mc_address_reg[23]_0 [3]),
        .I1(Q[0]),
        .I2(\cmd_pipe_plus.mc_address_reg[23]_1 [3]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(\cmd_pipe_plus.mc_address_reg[23]_2 [3]),
        .O(\cmd_pipe_plus.mc_address[17]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hF737)) 
    \cmd_pipe_plus.mc_address[18]_i_1 
       (.I0(\cmd_pipe_plus.mc_address[18]_i_2_n_0 ),
        .I1(\cmd_pipe_plus.mc_data_offset_2_reg[0] ),
        .I2(Q[3]),
        .I3(\cmd_pipe_plus.mc_address_reg[23] [4]),
        .O(granted_col_r_reg_3[4]));
  LUT6 #(
    .INIT(64'h00000F77FFFF0F77)) 
    \cmd_pipe_plus.mc_address[18]_i_2 
       (.I0(\cmd_pipe_plus.mc_address_reg[23]_0 [4]),
        .I1(Q[0]),
        .I2(\cmd_pipe_plus.mc_address_reg[23]_1 [4]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(\cmd_pipe_plus.mc_address_reg[23]_2 [4]),
        .O(\cmd_pipe_plus.mc_address[18]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hF737)) 
    \cmd_pipe_plus.mc_address[19]_i_1 
       (.I0(\cmd_pipe_plus.mc_address[19]_i_2_n_0 ),
        .I1(\cmd_pipe_plus.mc_data_offset_2_reg[0] ),
        .I2(Q[3]),
        .I3(\cmd_pipe_plus.mc_address_reg[23] [5]),
        .O(granted_col_r_reg_3[5]));
  LUT6 #(
    .INIT(64'h00000F77FFFF0F77)) 
    \cmd_pipe_plus.mc_address[19]_i_2 
       (.I0(\cmd_pipe_plus.mc_address_reg[23]_0 [5]),
        .I1(Q[0]),
        .I2(\cmd_pipe_plus.mc_address_reg[23]_1 [5]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(\cmd_pipe_plus.mc_address_reg[23]_2 [5]),
        .O(\cmd_pipe_plus.mc_address[19]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hF737)) 
    \cmd_pipe_plus.mc_address[20]_i_1 
       (.I0(\cmd_pipe_plus.mc_address[20]_i_2_n_0 ),
        .I1(\cmd_pipe_plus.mc_data_offset_2_reg[0] ),
        .I2(Q[3]),
        .I3(\cmd_pipe_plus.mc_address_reg[23] [6]),
        .O(granted_col_r_reg_3[6]));
  LUT6 #(
    .INIT(64'h00000F77FFFF0F77)) 
    \cmd_pipe_plus.mc_address[20]_i_2 
       (.I0(\cmd_pipe_plus.mc_address_reg[23]_0 [6]),
        .I1(Q[0]),
        .I2(\cmd_pipe_plus.mc_address_reg[23]_1 [6]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(\cmd_pipe_plus.mc_address_reg[23]_2 [6]),
        .O(\cmd_pipe_plus.mc_address[20]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hF737)) 
    \cmd_pipe_plus.mc_address[21]_i_1 
       (.I0(\cmd_pipe_plus.mc_address[21]_i_2_n_0 ),
        .I1(\cmd_pipe_plus.mc_data_offset_2_reg[0] ),
        .I2(Q[3]),
        .I3(\cmd_pipe_plus.mc_address_reg[23] [7]),
        .O(granted_col_r_reg_3[7]));
  LUT6 #(
    .INIT(64'h00000F77FFFF0F77)) 
    \cmd_pipe_plus.mc_address[21]_i_2 
       (.I0(\cmd_pipe_plus.mc_address_reg[23]_0 [7]),
        .I1(Q[0]),
        .I2(\cmd_pipe_plus.mc_address_reg[23]_1 [7]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(\cmd_pipe_plus.mc_address_reg[23]_2 [7]),
        .O(\cmd_pipe_plus.mc_address[21]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hF737)) 
    \cmd_pipe_plus.mc_address[22]_i_1 
       (.I0(\cmd_pipe_plus.mc_address[22]_i_2_n_0 ),
        .I1(\cmd_pipe_plus.mc_data_offset_2_reg[0] ),
        .I2(Q[3]),
        .I3(\cmd_pipe_plus.mc_address_reg[23] [8]),
        .O(granted_col_r_reg_3[8]));
  LUT6 #(
    .INIT(64'h00000F77FFFF0F77)) 
    \cmd_pipe_plus.mc_address[22]_i_2 
       (.I0(\cmd_pipe_plus.mc_address_reg[23]_0 [8]),
        .I1(Q[0]),
        .I2(\cmd_pipe_plus.mc_address_reg[23]_1 [8]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(\cmd_pipe_plus.mc_address_reg[23]_2 [8]),
        .O(\cmd_pipe_plus.mc_address[22]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1144" *) 
  LUT4 #(
    .INIT(16'hF737)) 
    \cmd_pipe_plus.mc_address[23]_i_1 
       (.I0(\cmd_pipe_plus.mc_address[23]_i_2_n_0 ),
        .I1(\cmd_pipe_plus.mc_data_offset_2_reg[0] ),
        .I2(Q[3]),
        .I3(\cmd_pipe_plus.mc_address_reg[23] [9]),
        .O(granted_col_r_reg_3[9]));
  LUT6 #(
    .INIT(64'h00000F77FFFF0F77)) 
    \cmd_pipe_plus.mc_address[23]_i_2 
       (.I0(\cmd_pipe_plus.mc_address_reg[23]_0 [9]),
        .I1(Q[0]),
        .I2(\cmd_pipe_plus.mc_address_reg[23]_1 [9]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(\cmd_pipe_plus.mc_address_reg[23]_2 [9]),
        .O(\cmd_pipe_plus.mc_address[23]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hF737)) 
    \cmd_pipe_plus.mc_address[24]_i_1 
       (.I0(\cmd_pipe_plus.mc_address[24]_i_2_n_0 ),
        .I1(\cmd_pipe_plus.mc_data_offset_2_reg[0] ),
        .I2(Q[3]),
        .I3(\cmd_pipe_plus.mc_address_reg[24] ),
        .O(granted_col_r_reg_3[10]));
  LUT6 #(
    .INIT(64'h00000F77FFFF0F77)) 
    \cmd_pipe_plus.mc_address[24]_i_2 
       (.I0(\cmd_pipe_plus.mc_address_reg[24]_0 ),
        .I1(Q[0]),
        .I2(\cmd_pipe_plus.mc_address_reg[24]_1 ),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(\cmd_pipe_plus.mc_address_reg[24]_2 ),
        .O(\cmd_pipe_plus.mc_address[24]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1145" *) 
  LUT4 #(
    .INIT(16'hF737)) 
    \cmd_pipe_plus.mc_bank[3]_i_1 
       (.I0(\cmd_pipe_plus.mc_bank[3]_i_2_n_0 ),
        .I1(\cmd_pipe_plus.mc_data_offset_2_reg[0] ),
        .I2(Q[3]),
        .I3(\cmd_pipe_plus.mc_bank_reg[5] [0]),
        .O(granted_col_r_reg_2[0]));
  LUT6 #(
    .INIT(64'h00000F77FFFF0F77)) 
    \cmd_pipe_plus.mc_bank[3]_i_2 
       (.I0(\cmd_pipe_plus.mc_bank_reg[5]_0 [0]),
        .I1(Q[0]),
        .I2(\cmd_pipe_plus.mc_bank_reg[5]_1 [0]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(\cmd_pipe_plus.mc_bank_reg[5]_2 [0]),
        .O(\cmd_pipe_plus.mc_bank[3]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hF737)) 
    \cmd_pipe_plus.mc_bank[4]_i_1 
       (.I0(\cmd_pipe_plus.mc_bank[4]_i_2_n_0 ),
        .I1(\cmd_pipe_plus.mc_data_offset_2_reg[0] ),
        .I2(Q[3]),
        .I3(\cmd_pipe_plus.mc_bank_reg[5] [1]),
        .O(granted_col_r_reg_2[1]));
  LUT6 #(
    .INIT(64'h00000F77FFFF0F77)) 
    \cmd_pipe_plus.mc_bank[4]_i_2 
       (.I0(\cmd_pipe_plus.mc_bank_reg[5]_0 [1]),
        .I1(Q[0]),
        .I2(\cmd_pipe_plus.mc_bank_reg[5]_1 [1]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(\cmd_pipe_plus.mc_bank_reg[5]_2 [1]),
        .O(\cmd_pipe_plus.mc_bank[4]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hF737)) 
    \cmd_pipe_plus.mc_bank[5]_i_1 
       (.I0(\cmd_pipe_plus.mc_bank[5]_i_2_n_0 ),
        .I1(\cmd_pipe_plus.mc_data_offset_2_reg[0] ),
        .I2(Q[3]),
        .I3(\cmd_pipe_plus.mc_bank_reg[5] [2]),
        .O(granted_col_r_reg_2[2]));
  LUT6 #(
    .INIT(64'h00000F77FFFF0F77)) 
    \cmd_pipe_plus.mc_bank[5]_i_2 
       (.I0(\cmd_pipe_plus.mc_bank_reg[5]_0 [2]),
        .I1(Q[0]),
        .I2(\cmd_pipe_plus.mc_bank_reg[5]_1 [2]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(\cmd_pipe_plus.mc_bank_reg[5]_2 [2]),
        .O(\cmd_pipe_plus.mc_bank[5]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1144" *) 
  LUT2 #(
    .INIT(4'h2)) 
    \cmd_pipe_plus.mc_cmd[1]_i_1 
       (.I0(\cmd_pipe_plus.mc_data_offset_2_reg[0] ),
        .I1(\grant_r_reg[2]_0 ),
        .O(E));
  (* SOFT_HLUTNM = "soft_lutpair1148" *) 
  LUT3 #(
    .INIT(8'hA8)) 
    \cmd_pipe_plus.mc_data_offset[3]_i_1 
       (.I0(\cmd_pipe_plus.mc_data_offset_2_reg[0] ),
        .I1(\grant_r_reg[2]_0 ),
        .I2(\cmd_pipe_plus.mc_data_offset_reg[3] ),
        .O(granted_col_r_reg_1));
  (* SOFT_HLUTNM = "soft_lutpair1145" *) 
  LUT2 #(
    .INIT(4'hD)) 
    \cmd_pipe_plus.mc_data_offset[5]_i_1 
       (.I0(\cmd_pipe_plus.mc_data_offset_2_reg[0] ),
        .I1(\grant_r_reg[2]_0 ),
        .O(granted_col_r_reg));
  (* SOFT_HLUTNM = "soft_lutpair1147" *) 
  LUT3 #(
    .INIT(8'hA8)) 
    \cmd_pipe_plus.mc_data_offset_1[3]_i_1 
       (.I0(\cmd_pipe_plus.mc_data_offset_2_reg[0] ),
        .I1(\grant_r_reg[2]_0 ),
        .I2(\cmd_pipe_plus.mc_data_offset_1_reg[3] ),
        .O(granted_col_r_reg_0));
  (* SOFT_HLUTNM = "soft_lutpair1147" *) 
  LUT3 #(
    .INIT(8'hA8)) 
    \cmd_pipe_plus.mc_data_offset_2[3]_i_1 
       (.I0(\cmd_pipe_plus.mc_data_offset_2_reg[0] ),
        .I1(\grant_r_reg[2]_0 ),
        .I2(O),
        .O(D));
  (* SOFT_HLUTNM = "soft_lutpair1148" *) 
  LUT3 #(
    .INIT(8'hEA)) 
    \cmd_pipe_plus.mc_odt[0]_i_1 
       (.I0(\cmd_pipe_plus.mc_odt_reg[0] ),
        .I1(\cmd_pipe_plus.mc_data_offset_2_reg[0] ),
        .I2(\grant_r_reg[2]_0 ),
        .O(mc_odt_ns));
  LUT6 #(
    .INIT(64'h55555554FFFFFFFF)) 
    \cmd_pipe_plus.mc_we_n[1]_i_1 
       (.I0(\grant_r_reg[2]_0 ),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(Q[2]),
        .I4(Q[3]),
        .I5(\cmd_pipe_plus.mc_data_offset_2_reg[0] ),
        .O(\grant_r_reg[0]_1 ));
  LUT5 #(
    .INIT(32'hFFCA00CA)) 
    \col_mux.col_periodic_rd_r_i_1 
       (.I0(\col_mux.col_periodic_rd_r_i_2_n_0 ),
        .I1(req_periodic_rd_r[2]),
        .I2(Q[2]),
        .I3(Q[3]),
        .I4(req_periodic_rd_r[3]),
        .O(DIC));
  LUT6 #(
    .INIT(64'hAAAAFF00AAAA3030)) 
    \col_mux.col_periodic_rd_r_i_2 
       (.I0(req_periodic_rd_r[1]),
        .I1(\rtw_timer.rtw_cnt_r_reg[0] ),
        .I2(\col_mux.col_periodic_rd_r ),
        .I3(req_periodic_rd_r[0]),
        .I4(Q[1]),
        .I5(Q[0]),
        .O(\col_mux.col_periodic_rd_r_i_2_n_0 ));
  LUT1 #(
    .INIT(2'h1)) 
    \col_mux.col_rd_wr_r_i_1 
       (.I0(\grant_r_reg[2]_0 ),
        .O(col_rd_wr));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[0]_i_1 
       (.I0(req_data_buf_addr_r[12]),
        .I1(Q[3]),
        .I2(req_data_buf_addr_r[8]),
        .I3(Q[2]),
        .I4(\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[0]_i_2_n_0 ),
        .O(col_wr_data_buf_addr[0]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[0]_i_2 
       (.I0(req_data_buf_addr_r[4]),
        .I1(Q[1]),
        .I2(req_data_buf_addr_r[0]),
        .I3(Q[0]),
        .I4(\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] [0]),
        .O(\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[0]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[1]_i_1 
       (.I0(req_data_buf_addr_r[13]),
        .I1(Q[3]),
        .I2(req_data_buf_addr_r[9]),
        .I3(Q[2]),
        .I4(\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[1]_i_2_n_0 ),
        .O(col_wr_data_buf_addr[1]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[1]_i_2 
       (.I0(req_data_buf_addr_r[5]),
        .I1(Q[1]),
        .I2(req_data_buf_addr_r[1]),
        .I3(Q[0]),
        .I4(\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] [1]),
        .O(\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[1]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[2]_i_1 
       (.I0(req_data_buf_addr_r[14]),
        .I1(Q[3]),
        .I2(req_data_buf_addr_r[10]),
        .I3(Q[2]),
        .I4(\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[2]_i_2_n_0 ),
        .O(col_wr_data_buf_addr[2]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[2]_i_2 
       (.I0(req_data_buf_addr_r[6]),
        .I1(Q[1]),
        .I2(req_data_buf_addr_r[2]),
        .I3(Q[0]),
        .I4(\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] [2]),
        .O(\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[2]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[3]_i_1 
       (.I0(req_data_buf_addr_r[15]),
        .I1(Q[3]),
        .I2(req_data_buf_addr_r[11]),
        .I3(Q[2]),
        .I4(\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[3]_i_2_n_0 ),
        .O(col_wr_data_buf_addr[3]));
  LUT5 #(
    .INIT(32'hB8BBB888)) 
    \delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[3]_i_2 
       (.I0(req_data_buf_addr_r[7]),
        .I1(Q[1]),
        .I2(req_data_buf_addr_r[3]),
        .I3(Q[0]),
        .I4(\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r_reg[3] [3]),
        .O(\delay_wr_data_cntrl_eq_1.col_wr_data_buf_addr_r[3]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1146" *) 
  LUT3 #(
    .INIT(8'hDF)) 
    demand_priority_r_i_4__0
       (.I0(req_bank_rdy_r),
        .I1(Q[1]),
        .I2(\cmd_pipe_plus.mc_data_offset_2_reg[0] ),
        .O(req_bank_rdy_r_reg));
  LUT6 #(
    .INIT(64'h00000000AA020202)) 
    \grant_r[0]_i_1__0 
       (.I0(\grant_r[2]_i_2_n_0 ),
        .I1(\last_master_r[0]_i_1_n_0 ),
        .I2(\last_master_r[1]_i_1_n_0 ),
        .I3(\grant_r_reg[0]_2 ),
        .I4(\grant_r_reg[0]_4 ),
        .I5(\grant_r_reg[0]_3 ),
        .O(\grant_r[0]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h800080008000F000)) 
    \grant_r[1]_i_1__1 
       (.I0(\grant_r_reg[0]_2 ),
        .I1(\grant_r_reg[0]_3 ),
        .I2(\grant_r[3]_i_4_n_0 ),
        .I3(\grant_r_reg[2]_1 ),
        .I4(\last_master_r[2]_i_1__0_n_0 ),
        .I5(\last_master_r[1]_i_1_n_0 ),
        .O(\grant_r[1]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'h00000000080808AA)) 
    \grant_r[2]_i_1__0 
       (.I0(\grant_r[2]_i_2_n_0 ),
        .I1(\grant_r_reg[0]_3 ),
        .I2(\grant_r_reg[2]_1 ),
        .I3(\last_master_r[2]_i_1__0_n_0 ),
        .I4(\last_master_r[3]_i_1_n_0 ),
        .I5(\grant_r_reg[0]_4 ),
        .O(\grant_r[2]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h7077)) 
    \grant_r[2]_i_2 
       (.I0(\grant_r_reg[2]_1 ),
        .I1(\last_master_r[0]_i_1_n_0 ),
        .I2(\grant_r_reg[0]_2 ),
        .I3(\last_master_r[2]_i_1__0_n_0 ),
        .O(\grant_r[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFDF)) 
    \grant_r[2]_i_7 
       (.I0(\grant_r[3]_i_10 ),
        .I1(Q[0]),
        .I2(ofs_rdy_r_0),
        .I3(\genblk3[1].rnk_config_strobe_r_reg ),
        .I4(\genblk3[2].rnk_config_strobe_r_reg ),
        .I5(rnk_config_strobe),
        .O(rnk_config_valid_r_lcl_reg_0));
  LUT6 #(
    .INIT(64'h2A2AFF2AFF2AFF2A)) 
    \grant_r[3]_i_14 
       (.I0(Q[3]),
        .I1(\cmd_pipe_plus.mc_data_offset_2_reg[0]_1 ),
        .I2(\grant_r[3]_i_8 ),
        .I3(Q[2]),
        .I4(\cmd_pipe_plus.mc_data_offset_2_reg[0]_0 ),
        .I5(\grant_r[3]_i_8_0 ),
        .O(\grant_r_reg[3]_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFDF)) 
    \grant_r[3]_i_16 
       (.I0(\grant_r[3]_i_10 ),
        .I1(Q[1]),
        .I2(ofs_rdy_r_2),
        .I3(\genblk3[1].rnk_config_strobe_r_reg ),
        .I4(\genblk3[2].rnk_config_strobe_r_reg ),
        .I5(rnk_config_strobe),
        .O(rnk_config_valid_r_lcl_reg_2));
  LUT4 #(
    .INIT(16'hF808)) 
    \grant_r[3]_i_17 
       (.I0(Q[2]),
        .I1(\cmd_pipe_plus.mc_data_offset_2_reg[0]_0 ),
        .I2(Q[3]),
        .I3(\cmd_pipe_plus.mc_data_offset_2_reg[0]_1 ),
        .O(\grant_r[3]_i_17_n_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFDF)) 
    \grant_r[3]_i_18 
       (.I0(\grant_r[3]_i_10 ),
        .I1(Q[2]),
        .I2(ofs_rdy_r),
        .I3(\genblk3[1].rnk_config_strobe_r_reg ),
        .I4(\genblk3[2].rnk_config_strobe_r_reg ),
        .I5(rnk_config_strobe),
        .O(rnk_config_valid_r_lcl_reg));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFFFDF)) 
    \grant_r[3]_i_19 
       (.I0(\grant_r[3]_i_10 ),
        .I1(Q[3]),
        .I2(ofs_rdy_r_1),
        .I3(\genblk3[1].rnk_config_strobe_r_reg ),
        .I4(\genblk3[2].rnk_config_strobe_r_reg ),
        .I5(rnk_config_strobe),
        .O(rnk_config_valid_r_lcl_reg_1));
  LUT6 #(
    .INIT(64'h00000000444F0000)) 
    \grant_r[3]_i_1__0 
       (.I0(\grant_r_reg[2]_1 ),
        .I1(\grant_r_reg[0]_4 ),
        .I2(\last_master_r[0]_i_1_n_0 ),
        .I3(\last_master_r[3]_i_1_n_0 ),
        .I4(\grant_r[3]_i_4_n_0 ),
        .I5(\grant_r_reg[0]_2 ),
        .O(\grant_r[3]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'hD0DD)) 
    \grant_r[3]_i_4 
       (.I0(\last_master_r[3]_i_1_n_0 ),
        .I1(\grant_r_reg[0]_3 ),
        .I2(\grant_r_reg[0]_4 ),
        .I3(\last_master_r[1]_i_1_n_0 ),
        .O(\grant_r[3]_i_4_n_0 ));
  LUT4 #(
    .INIT(16'hFF04)) 
    \grant_r[3]_i_7 
       (.I0(\wr_this_rank_r_reg[0] ),
        .I1(\wr_this_rank_r_reg[0]_0 ),
        .I2(\grant_r[2]_i_3_0 ),
        .I3(\grant_r[2]_i_3 ),
        .O(\wtr_timer.wtr_cnt_r_reg[1] ));
  LUT5 #(
    .INIT(32'hFF00FF4F)) 
    \grant_r[3]_i_9 
       (.I0(\grant_r[3]_i_17_n_0 ),
        .I1(i___22_i_2_n_0),
        .I2(\rtw_timer.rtw_cnt_r[1]_i_2_n_0 ),
        .I3(\grant_r[2]_i_3 ),
        .I4(\rtw_timer.rtw_cnt_r_reg[1]_1 [1]),
        .O(\rtw_timer.rtw_cnt_r_reg[1]_0 ));
  FDRE \grant_r_reg[0] 
       (.C(\last_master_r_reg[3]_0 ),
        .CE(1'b1),
        .D(\grant_r[0]_i_1__0_n_0 ),
        .Q(Q[0]),
        .R(1'b0));
  FDRE \grant_r_reg[1] 
       (.C(\last_master_r_reg[3]_0 ),
        .CE(1'b1),
        .D(\grant_r[1]_i_1__1_n_0 ),
        .Q(Q[1]),
        .R(1'b0));
  FDRE \grant_r_reg[2] 
       (.C(\last_master_r_reg[3]_0 ),
        .CE(1'b1),
        .D(\grant_r[2]_i_1__0_n_0 ),
        .Q(Q[2]),
        .R(1'b0));
  FDRE \grant_r_reg[3] 
       (.C(\last_master_r_reg[3]_0 ),
        .CE(1'b1),
        .D(\grant_r[3]_i_1__0_n_0 ),
        .Q(Q[3]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hAAAAA888A888A888)) 
    i___20_i_1
       (.I0(\periodic_rd_generation.read_this_rank_r ),
        .I1(\periodic_rd_generation.read_this_rank_r_i_2_n_0 ),
        .I2(rd_this_rank_r[3]),
        .I3(Q[3]),
        .I4(rd_this_rank_r[0]),
        .I5(Q[0]),
        .O(\periodic_rd_generation.read_this_rank_r_reg ));
  LUT6 #(
    .INIT(64'h0000022222220222)) 
    i___22_i_1
       (.I0(i___22_i_2_n_0),
        .I1(i___22_i_3_n_0),
        .I2(Q[2]),
        .I3(\cmd_pipe_plus.mc_data_offset_2_reg[0]_0 ),
        .I4(Q[3]),
        .I5(\cmd_pipe_plus.mc_data_offset_2_reg[0]_1 ),
        .O(\grant_r_reg[2]_0 ));
  LUT6 #(
    .INIT(64'hEFEEEFFFEFFFEFFF)) 
    i___22_i_2
       (.I0(Q[3]),
        .I1(Q[2]),
        .I2(i___22_i_1_0),
        .I3(Q[1]),
        .I4(rd_wr_r),
        .I5(Q[0]),
        .O(i___22_i_2_n_0));
  (* SOFT_HLUTNM = "soft_lutpair1142" *) 
  LUT5 #(
    .INIT(32'h00000002)) 
    i___22_i_3
       (.I0(col_rd_wr_r),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(Q[2]),
        .I4(Q[3]),
        .O(i___22_i_3_n_0));
  (* SOFT_HLUTNM = "soft_lutpair1141" *) 
  LUT4 #(
    .INIT(16'h0777)) 
    i___24_i_1
       (.I0(wr_this_rank_r[3]),
        .I1(Q[3]),
        .I2(wr_this_rank_r[0]),
        .I3(Q[0]),
        .O(\wr_this_rank_r_reg[0]_0 ));
  LUT4 #(
    .INIT(16'hF888)) 
    i___24_i_2
       (.I0(wr_this_rank_r[1]),
        .I1(Q[1]),
        .I2(wr_this_rank_r[2]),
        .I3(Q[2]),
        .O(\wr_this_rank_r_reg[0] ));
  LUT4 #(
    .INIT(16'h00E2)) 
    \last_master_r[0]_i_1 
       (.I0(last_master_r[0]),
        .I1(\cmd_pipe_plus.mc_data_offset_2_reg[0] ),
        .I2(Q[0]),
        .I3(\last_master_r_reg[1]_0 ),
        .O(\last_master_r[0]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1146" *) 
  LUT4 #(
    .INIT(16'h00E2)) 
    \last_master_r[1]_i_1 
       (.I0(last_master_r[1]),
        .I1(\cmd_pipe_plus.mc_data_offset_2_reg[0] ),
        .I2(Q[1]),
        .I3(\last_master_r_reg[1]_0 ),
        .O(\last_master_r[1]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h00E2)) 
    \last_master_r[2]_i_1__0 
       (.I0(last_master_r[2]),
        .I1(\cmd_pipe_plus.mc_data_offset_2_reg[0] ),
        .I2(Q[2]),
        .I3(\last_master_r_reg[1]_0 ),
        .O(\last_master_r[2]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'hFEAE)) 
    \last_master_r[3]_i_1 
       (.I0(\last_master_r_reg[1]_0 ),
        .I1(last_master_r[3]),
        .I2(\cmd_pipe_plus.mc_data_offset_2_reg[0] ),
        .I3(Q[3]),
        .O(\last_master_r[3]_i_1_n_0 ));
  FDRE \last_master_r_reg[0] 
       (.C(\last_master_r_reg[3]_0 ),
        .CE(1'b1),
        .D(\last_master_r[0]_i_1_n_0 ),
        .Q(last_master_r[0]),
        .R(1'b0));
  FDRE \last_master_r_reg[1] 
       (.C(\last_master_r_reg[3]_0 ),
        .CE(1'b1),
        .D(\last_master_r[1]_i_1_n_0 ),
        .Q(last_master_r[1]),
        .R(1'b0));
  FDRE \last_master_r_reg[2] 
       (.C(\last_master_r_reg[3]_0 ),
        .CE(1'b1),
        .D(\last_master_r[2]_i_1__0_n_0 ),
        .Q(last_master_r[2]),
        .R(1'b0));
  FDRE \last_master_r_reg[3] 
       (.C(\last_master_r_reg[3]_0 ),
        .CE(1'b1),
        .D(\last_master_r[3]_i_1_n_0 ),
        .Q(last_master_r[3]),
        .R(1'b0));
  LUT5 #(
    .INIT(32'hFFEAEAEA)) 
    \periodic_rd_generation.read_this_rank_r_i_1 
       (.I0(\periodic_rd_generation.read_this_rank_r_i_2_n_0 ),
        .I1(rd_this_rank_r[3]),
        .I2(Q[3]),
        .I3(rd_this_rank_r[0]),
        .I4(Q[0]),
        .O(\periodic_rd_generation.read_this_rank ));
  LUT4 #(
    .INIT(16'hF888)) 
    \periodic_rd_generation.read_this_rank_r_i_2 
       (.I0(rd_this_rank_r[1]),
        .I1(Q[1]),
        .I2(rd_this_rank_r[2]),
        .I3(Q[2]),
        .O(\periodic_rd_generation.read_this_rank_r_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1143" *) 
  LUT5 #(
    .INIT(32'h000000D0)) 
    \rtw_timer.rtw_cnt_r[0]_i_1 
       (.I0(\rtw_timer.rtw_cnt_r[1]_i_2_n_0 ),
        .I1(\grant_r_reg[2]_0 ),
        .I2(\rtw_timer.rtw_cnt_r_reg[1]_1 [1]),
        .I3(\rtw_timer.rtw_cnt_r_reg[0] ),
        .I4(\rtw_timer.rtw_cnt_r_reg[1]_1 [0]),
        .O(\rtw_timer.rtw_cnt_r_reg[1] [0]));
  (* SOFT_HLUTNM = "soft_lutpair1143" *) 
  LUT5 #(
    .INIT(32'h00F40044)) 
    \rtw_timer.rtw_cnt_r[1]_i_1 
       (.I0(\grant_r_reg[2]_0 ),
        .I1(\rtw_timer.rtw_cnt_r[1]_i_2_n_0 ),
        .I2(\rtw_timer.rtw_cnt_r_reg[1]_1 [1]),
        .I3(\rtw_timer.rtw_cnt_r_reg[0] ),
        .I4(\rtw_timer.rtw_cnt_r_reg[1]_1 [0]),
        .O(\rtw_timer.rtw_cnt_r_reg[1] [1]));
  (* SOFT_HLUTNM = "soft_lutpair1142" *) 
  LUT4 #(
    .INIT(16'hFFFE)) 
    \rtw_timer.rtw_cnt_r[1]_i_2 
       (.I0(Q[3]),
        .I1(Q[2]),
        .I2(Q[1]),
        .I3(Q[0]),
        .O(\rtw_timer.rtw_cnt_r[1]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1141" *) 
  LUT5 #(
    .INIT(32'h00000777)) 
    \wtr_timer.wtr_cnt_r[1]_i_2 
       (.I0(Q[0]),
        .I1(wr_this_rank_r[0]),
        .I2(Q[3]),
        .I3(wr_this_rank_r[3]),
        .I4(\wr_this_rank_r_reg[0] ),
        .O(\grant_r_reg[0]_0 ));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_round_robin_arb" *) 
module mig_mig_7series_v4_2_round_robin_arb__parameterized1_3
   (Q,
    \last_master_r_reg[3]_0 ,
    \pre_4_1_1T_arb.granted_pre_r_reg ,
    \pre_4_1_1T_arb.granted_pre_r_reg_0 ,
    mc_cas_n_ns,
    mc_we_n_ns,
    \grant_r_reg[0]_0 ,
    \grant_r_reg[0]_1 ,
    \grant_r_reg[0]_2 ,
    \grant_r_reg[1]_0 ,
    \grant_r_reg[3]_0 ,
    \cmd_pipe_plus.mc_address_reg[41] ,
    \last_master_r_reg[1]_0 ,
    \cmd_pipe_plus.mc_address_reg[38] ,
    req_row_r,
    \cmd_pipe_plus.mc_we_n_reg[2] ,
    \cmd_pipe_plus.mc_we_n_reg[2]_0 ,
    \cmd_pipe_plus.mc_bank_reg[8] ,
    \cmd_pipe_plus.mc_bank_reg[8]_0 ,
    \cmd_pipe_plus.mc_bank_reg[8]_1 ,
    \cmd_pipe_plus.mc_bank_reg[8]_2 ,
    \cmd_pipe_plus.mc_we_n_reg[2]_1 ,
    \cmd_pipe_plus.mc_we_n_reg[2]_2 ,
    \cmd_pipe_plus.mc_address_reg[41]_0 ,
    \last_master_r_reg[3]_1 );
  output [3:0]Q;
  output [0:0]\last_master_r_reg[3]_0 ;
  output [13:0]\pre_4_1_1T_arb.granted_pre_r_reg ;
  output [2:0]\pre_4_1_1T_arb.granted_pre_r_reg_0 ;
  output [0:0]mc_cas_n_ns;
  output [0:0]mc_we_n_ns;
  input \grant_r_reg[0]_0 ;
  input \grant_r_reg[0]_1 ;
  input \grant_r_reg[0]_2 ;
  input \grant_r_reg[1]_0 ;
  input \grant_r_reg[3]_0 ;
  input \cmd_pipe_plus.mc_address_reg[41] ;
  input \last_master_r_reg[1]_0 ;
  input \cmd_pipe_plus.mc_address_reg[38] ;
  input [34:0]req_row_r;
  input \cmd_pipe_plus.mc_we_n_reg[2] ;
  input \cmd_pipe_plus.mc_we_n_reg[2]_0 ;
  input [2:0]\cmd_pipe_plus.mc_bank_reg[8] ;
  input [2:0]\cmd_pipe_plus.mc_bank_reg[8]_0 ;
  input [2:0]\cmd_pipe_plus.mc_bank_reg[8]_1 ;
  input [2:0]\cmd_pipe_plus.mc_bank_reg[8]_2 ;
  input \cmd_pipe_plus.mc_we_n_reg[2]_1 ;
  input \cmd_pipe_plus.mc_we_n_reg[2]_2 ;
  input [18:0]\cmd_pipe_plus.mc_address_reg[41]_0 ;
  input \last_master_r_reg[3]_1 ;

  wire [3:0]Q;
  wire \cmd_pipe_plus.mc_address[28]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[29]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[30]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[31]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[32]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[33]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[34]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[35]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[36]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[37]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[38]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[39]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[40]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[41]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address_reg[38] ;
  wire \cmd_pipe_plus.mc_address_reg[41] ;
  wire [18:0]\cmd_pipe_plus.mc_address_reg[41]_0 ;
  wire \cmd_pipe_plus.mc_bank[6]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_bank[7]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_bank[8]_i_2_n_0 ;
  wire [2:0]\cmd_pipe_plus.mc_bank_reg[8] ;
  wire [2:0]\cmd_pipe_plus.mc_bank_reg[8]_0 ;
  wire [2:0]\cmd_pipe_plus.mc_bank_reg[8]_1 ;
  wire [2:0]\cmd_pipe_plus.mc_bank_reg[8]_2 ;
  wire \cmd_pipe_plus.mc_we_n[2]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_we_n_reg[2] ;
  wire \cmd_pipe_plus.mc_we_n_reg[2]_0 ;
  wire \cmd_pipe_plus.mc_we_n_reg[2]_1 ;
  wire \cmd_pipe_plus.mc_we_n_reg[2]_2 ;
  wire \grant_r[0]_i_1__2_n_0 ;
  wire \grant_r[1]_i_1__0_n_0 ;
  wire \grant_r[2]_i_1__2_n_0 ;
  wire \grant_r[2]_i_2__1_n_0 ;
  wire \grant_r[3]_i_1_n_0 ;
  wire \grant_r[3]_i_4__0_n_0 ;
  wire \grant_r_reg[0]_0 ;
  wire \grant_r_reg[0]_1 ;
  wire \grant_r_reg[0]_2 ;
  wire \grant_r_reg[1]_0 ;
  wire \grant_r_reg[3]_0 ;
  wire [2:0]last_master_r;
  wire \last_master_r[0]_i_1__0_n_0 ;
  wire \last_master_r[1]_i_1__0_n_0 ;
  wire \last_master_r[2]_i_1__1_n_0 ;
  wire \last_master_r[3]_i_1__0_n_0 ;
  wire \last_master_r_reg[1]_0 ;
  wire [0:0]\last_master_r_reg[3]_0 ;
  wire \last_master_r_reg[3]_1 ;
  wire [0:0]mc_cas_n_ns;
  wire [0:0]mc_we_n_ns;
  wire [13:0]\pre_4_1_1T_arb.granted_pre_r_reg ;
  wire [2:0]\pre_4_1_1T_arb.granted_pre_r_reg_0 ;
  wire [34:0]req_row_r;

  LUT4 #(
    .INIT(16'hF377)) 
    \cmd_pipe_plus.mc_address[28]_i_1 
       (.I0(\cmd_pipe_plus.mc_address[28]_i_2_n_0 ),
        .I1(\cmd_pipe_plus.mc_address_reg[41] ),
        .I2(req_row_r[23]),
        .I3(Q[3]),
        .O(\pre_4_1_1T_arb.granted_pre_r_reg [0]));
  LUT6 #(
    .INIT(64'h000007F7FFFF07F7)) 
    \cmd_pipe_plus.mc_address[28]_i_2 
       (.I0(\cmd_pipe_plus.mc_address_reg[41]_0 [0]),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(req_row_r[3]),
        .I4(Q[2]),
        .I5(req_row_r[12]),
        .O(\cmd_pipe_plus.mc_address[28]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hF377)) 
    \cmd_pipe_plus.mc_address[29]_i_1 
       (.I0(\cmd_pipe_plus.mc_address[29]_i_2_n_0 ),
        .I1(\cmd_pipe_plus.mc_address_reg[41] ),
        .I2(req_row_r[24]),
        .I3(Q[3]),
        .O(\pre_4_1_1T_arb.granted_pre_r_reg [1]));
  LUT6 #(
    .INIT(64'h000007F7FFFF07F7)) 
    \cmd_pipe_plus.mc_address[29]_i_2 
       (.I0(\cmd_pipe_plus.mc_address_reg[41]_0 [1]),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(req_row_r[4]),
        .I4(Q[2]),
        .I5(req_row_r[13]),
        .O(\cmd_pipe_plus.mc_address[29]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hF377)) 
    \cmd_pipe_plus.mc_address[30]_i_1 
       (.I0(\cmd_pipe_plus.mc_address[30]_i_2_n_0 ),
        .I1(\cmd_pipe_plus.mc_address_reg[41] ),
        .I2(req_row_r[25]),
        .I3(Q[3]),
        .O(\pre_4_1_1T_arb.granted_pre_r_reg [2]));
  LUT6 #(
    .INIT(64'h000007F7FFFF07F7)) 
    \cmd_pipe_plus.mc_address[30]_i_2 
       (.I0(\cmd_pipe_plus.mc_address_reg[41]_0 [2]),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(req_row_r[5]),
        .I4(Q[2]),
        .I5(req_row_r[14]),
        .O(\cmd_pipe_plus.mc_address[30]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hF377)) 
    \cmd_pipe_plus.mc_address[31]_i_1 
       (.I0(\cmd_pipe_plus.mc_address[31]_i_2_n_0 ),
        .I1(\cmd_pipe_plus.mc_address_reg[41] ),
        .I2(req_row_r[26]),
        .I3(Q[3]),
        .O(\pre_4_1_1T_arb.granted_pre_r_reg [3]));
  LUT6 #(
    .INIT(64'h000007F7FFFF07F7)) 
    \cmd_pipe_plus.mc_address[31]_i_2 
       (.I0(\cmd_pipe_plus.mc_address_reg[41]_0 [3]),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(req_row_r[6]),
        .I4(Q[2]),
        .I5(req_row_r[15]),
        .O(\cmd_pipe_plus.mc_address[31]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hF377)) 
    \cmd_pipe_plus.mc_address[32]_i_1 
       (.I0(\cmd_pipe_plus.mc_address[32]_i_2_n_0 ),
        .I1(\cmd_pipe_plus.mc_address_reg[41] ),
        .I2(req_row_r[27]),
        .I3(Q[3]),
        .O(\pre_4_1_1T_arb.granted_pre_r_reg [4]));
  LUT6 #(
    .INIT(64'h000007F7FFFF07F7)) 
    \cmd_pipe_plus.mc_address[32]_i_2 
       (.I0(\cmd_pipe_plus.mc_address_reg[41]_0 [4]),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(req_row_r[7]),
        .I4(Q[2]),
        .I5(req_row_r[16]),
        .O(\cmd_pipe_plus.mc_address[32]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hF377)) 
    \cmd_pipe_plus.mc_address[33]_i_1 
       (.I0(\cmd_pipe_plus.mc_address[33]_i_2_n_0 ),
        .I1(\cmd_pipe_plus.mc_address_reg[41] ),
        .I2(req_row_r[28]),
        .I3(Q[3]),
        .O(\pre_4_1_1T_arb.granted_pre_r_reg [5]));
  LUT6 #(
    .INIT(64'h000007F7FFFF07F7)) 
    \cmd_pipe_plus.mc_address[33]_i_2 
       (.I0(\cmd_pipe_plus.mc_address_reg[41]_0 [5]),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(req_row_r[8]),
        .I4(Q[2]),
        .I5(req_row_r[17]),
        .O(\cmd_pipe_plus.mc_address[33]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hF377)) 
    \cmd_pipe_plus.mc_address[34]_i_1 
       (.I0(\cmd_pipe_plus.mc_address[34]_i_2_n_0 ),
        .I1(\cmd_pipe_plus.mc_address_reg[41] ),
        .I2(req_row_r[29]),
        .I3(Q[3]),
        .O(\pre_4_1_1T_arb.granted_pre_r_reg [6]));
  LUT6 #(
    .INIT(64'h000007F7FFFF07F7)) 
    \cmd_pipe_plus.mc_address[34]_i_2 
       (.I0(\cmd_pipe_plus.mc_address_reg[41]_0 [6]),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(req_row_r[9]),
        .I4(Q[2]),
        .I5(req_row_r[18]),
        .O(\cmd_pipe_plus.mc_address[34]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hF377)) 
    \cmd_pipe_plus.mc_address[35]_i_1 
       (.I0(\cmd_pipe_plus.mc_address[35]_i_2_n_0 ),
        .I1(\cmd_pipe_plus.mc_address_reg[41] ),
        .I2(req_row_r[30]),
        .I3(Q[3]),
        .O(\pre_4_1_1T_arb.granted_pre_r_reg [7]));
  LUT6 #(
    .INIT(64'h000007F7FFFF07F7)) 
    \cmd_pipe_plus.mc_address[35]_i_2 
       (.I0(\cmd_pipe_plus.mc_address_reg[41]_0 [7]),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(req_row_r[10]),
        .I4(Q[2]),
        .I5(req_row_r[19]),
        .O(\cmd_pipe_plus.mc_address[35]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hF377)) 
    \cmd_pipe_plus.mc_address[36]_i_1 
       (.I0(\cmd_pipe_plus.mc_address[36]_i_2_n_0 ),
        .I1(\cmd_pipe_plus.mc_address_reg[41] ),
        .I2(req_row_r[31]),
        .I3(Q[3]),
        .O(\pre_4_1_1T_arb.granted_pre_r_reg [8]));
  LUT6 #(
    .INIT(64'h000007F7FFFF07F7)) 
    \cmd_pipe_plus.mc_address[36]_i_2 
       (.I0(\cmd_pipe_plus.mc_address_reg[41]_0 [8]),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(req_row_r[11]),
        .I4(Q[2]),
        .I5(req_row_r[20]),
        .O(\cmd_pipe_plus.mc_address[36]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hF377)) 
    \cmd_pipe_plus.mc_address[37]_i_1 
       (.I0(\cmd_pipe_plus.mc_address[37]_i_2_n_0 ),
        .I1(\cmd_pipe_plus.mc_address_reg[41] ),
        .I2(req_row_r[32]),
        .I3(Q[3]),
        .O(\pre_4_1_1T_arb.granted_pre_r_reg [9]));
  LUT6 #(
    .INIT(64'h000007F7FFFF07F7)) 
    \cmd_pipe_plus.mc_address[37]_i_2 
       (.I0(req_row_r[0]),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(\cmd_pipe_plus.mc_address_reg[41]_0 [11]),
        .I4(Q[2]),
        .I5(req_row_r[21]),
        .O(\cmd_pipe_plus.mc_address[37]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFF0FDFDF0F0FDFDF)) 
    \cmd_pipe_plus.mc_address[38]_i_1 
       (.I0(\cmd_pipe_plus.mc_address[38]_i_2_n_0 ),
        .I1(\cmd_pipe_plus.mc_address_reg[38] ),
        .I2(\cmd_pipe_plus.mc_address_reg[41] ),
        .I3(req_row_r[33]),
        .I4(Q[3]),
        .I5(\cmd_pipe_plus.mc_we_n_reg[2] ),
        .O(\pre_4_1_1T_arb.granted_pre_r_reg [10]));
  LUT5 #(
    .INIT(32'hFFFFFF7F)) 
    \cmd_pipe_plus.mc_address[38]_i_2 
       (.I0(\cmd_pipe_plus.mc_we_n_reg[2]_0 ),
        .I1(req_row_r[1]),
        .I2(Q[0]),
        .I3(Q[1]),
        .I4(Q[2]),
        .O(\cmd_pipe_plus.mc_address[38]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hF377)) 
    \cmd_pipe_plus.mc_address[39]_i_1 
       (.I0(\cmd_pipe_plus.mc_address[39]_i_2_n_0 ),
        .I1(\cmd_pipe_plus.mc_address_reg[41] ),
        .I2(req_row_r[34]),
        .I3(Q[3]),
        .O(\pre_4_1_1T_arb.granted_pre_r_reg [11]));
  LUT6 #(
    .INIT(64'h000007F7FFFF07F7)) 
    \cmd_pipe_plus.mc_address[39]_i_2 
       (.I0(req_row_r[2]),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(\cmd_pipe_plus.mc_address_reg[41]_0 [12]),
        .I4(Q[2]),
        .I5(req_row_r[22]),
        .O(\cmd_pipe_plus.mc_address[39]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hF377)) 
    \cmd_pipe_plus.mc_address[40]_i_1 
       (.I0(\cmd_pipe_plus.mc_address[40]_i_2_n_0 ),
        .I1(\cmd_pipe_plus.mc_address_reg[41] ),
        .I2(\cmd_pipe_plus.mc_address_reg[41]_0 [17]),
        .I3(Q[3]),
        .O(\pre_4_1_1T_arb.granted_pre_r_reg [12]));
  LUT6 #(
    .INIT(64'h000007F7FFFF07F7)) 
    \cmd_pipe_plus.mc_address[40]_i_2 
       (.I0(\cmd_pipe_plus.mc_address_reg[41]_0 [9]),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(\cmd_pipe_plus.mc_address_reg[41]_0 [13]),
        .I4(Q[2]),
        .I5(\cmd_pipe_plus.mc_address_reg[41]_0 [15]),
        .O(\cmd_pipe_plus.mc_address[40]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hF377)) 
    \cmd_pipe_plus.mc_address[41]_i_1 
       (.I0(\cmd_pipe_plus.mc_address[41]_i_2_n_0 ),
        .I1(\cmd_pipe_plus.mc_address_reg[41] ),
        .I2(\cmd_pipe_plus.mc_address_reg[41]_0 [18]),
        .I3(Q[3]),
        .O(\pre_4_1_1T_arb.granted_pre_r_reg [13]));
  LUT6 #(
    .INIT(64'h000007F7FFFF07F7)) 
    \cmd_pipe_plus.mc_address[41]_i_2 
       (.I0(\cmd_pipe_plus.mc_address_reg[41]_0 [10]),
        .I1(Q[0]),
        .I2(Q[1]),
        .I3(\cmd_pipe_plus.mc_address_reg[41]_0 [14]),
        .I4(Q[2]),
        .I5(\cmd_pipe_plus.mc_address_reg[41]_0 [16]),
        .O(\cmd_pipe_plus.mc_address[41]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hF737)) 
    \cmd_pipe_plus.mc_bank[6]_i_1 
       (.I0(\cmd_pipe_plus.mc_bank[6]_i_2_n_0 ),
        .I1(\cmd_pipe_plus.mc_address_reg[41] ),
        .I2(Q[3]),
        .I3(\cmd_pipe_plus.mc_bank_reg[8] [0]),
        .O(\pre_4_1_1T_arb.granted_pre_r_reg_0 [0]));
  LUT6 #(
    .INIT(64'h00000F77FFFF0F77)) 
    \cmd_pipe_plus.mc_bank[6]_i_2 
       (.I0(\cmd_pipe_plus.mc_bank_reg[8]_0 [0]),
        .I1(Q[0]),
        .I2(\cmd_pipe_plus.mc_bank_reg[8]_1 [0]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(\cmd_pipe_plus.mc_bank_reg[8]_2 [0]),
        .O(\cmd_pipe_plus.mc_bank[6]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hF737)) 
    \cmd_pipe_plus.mc_bank[7]_i_1 
       (.I0(\cmd_pipe_plus.mc_bank[7]_i_2_n_0 ),
        .I1(\cmd_pipe_plus.mc_address_reg[41] ),
        .I2(Q[3]),
        .I3(\cmd_pipe_plus.mc_bank_reg[8] [1]),
        .O(\pre_4_1_1T_arb.granted_pre_r_reg_0 [1]));
  LUT6 #(
    .INIT(64'h00000F77FFFF0F77)) 
    \cmd_pipe_plus.mc_bank[7]_i_2 
       (.I0(\cmd_pipe_plus.mc_bank_reg[8]_0 [1]),
        .I1(Q[0]),
        .I2(\cmd_pipe_plus.mc_bank_reg[8]_1 [1]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(\cmd_pipe_plus.mc_bank_reg[8]_2 [1]),
        .O(\cmd_pipe_plus.mc_bank[7]_i_2_n_0 ));
  LUT4 #(
    .INIT(16'hF737)) 
    \cmd_pipe_plus.mc_bank[8]_i_1 
       (.I0(\cmd_pipe_plus.mc_bank[8]_i_2_n_0 ),
        .I1(\cmd_pipe_plus.mc_address_reg[41] ),
        .I2(Q[3]),
        .I3(\cmd_pipe_plus.mc_bank_reg[8] [2]),
        .O(\pre_4_1_1T_arb.granted_pre_r_reg_0 [2]));
  LUT6 #(
    .INIT(64'h00000F77FFFF0F77)) 
    \cmd_pipe_plus.mc_bank[8]_i_2 
       (.I0(\cmd_pipe_plus.mc_bank_reg[8]_0 [2]),
        .I1(Q[0]),
        .I2(\cmd_pipe_plus.mc_bank_reg[8]_1 [2]),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(\cmd_pipe_plus.mc_bank_reg[8]_2 [2]),
        .O(\cmd_pipe_plus.mc_bank[8]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFFFD)) 
    \cmd_pipe_plus.mc_cas_n[2]_i_1 
       (.I0(\cmd_pipe_plus.mc_address_reg[41] ),
        .I1(Q[3]),
        .I2(Q[1]),
        .I3(Q[2]),
        .I4(Q[0]),
        .O(mc_cas_n_ns));
  LUT4 #(
    .INIT(16'hF377)) 
    \cmd_pipe_plus.mc_we_n[2]_i_1 
       (.I0(\cmd_pipe_plus.mc_we_n[2]_i_2_n_0 ),
        .I1(\cmd_pipe_plus.mc_address_reg[41] ),
        .I2(\cmd_pipe_plus.mc_we_n_reg[2] ),
        .I3(Q[3]),
        .O(mc_we_n_ns));
  LUT6 #(
    .INIT(64'h00000F77FFFF0F77)) 
    \cmd_pipe_plus.mc_we_n[2]_i_2 
       (.I0(\cmd_pipe_plus.mc_we_n_reg[2]_0 ),
        .I1(Q[0]),
        .I2(\cmd_pipe_plus.mc_we_n_reg[2]_1 ),
        .I3(Q[1]),
        .I4(Q[2]),
        .I5(\cmd_pipe_plus.mc_we_n_reg[2]_2 ),
        .O(\cmd_pipe_plus.mc_we_n[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h020202AA00000000)) 
    \grant_r[0]_i_1__2 
       (.I0(\grant_r[2]_i_2__1_n_0 ),
        .I1(\last_master_r[0]_i_1__0_n_0 ),
        .I2(\last_master_r[1]_i_1__0_n_0 ),
        .I3(\grant_r_reg[0]_0 ),
        .I4(\grant_r_reg[0]_1 ),
        .I5(\grant_r_reg[0]_2 ),
        .O(\grant_r[0]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'h020202AA00000000)) 
    \grant_r[1]_i_1__0 
       (.I0(\grant_r[3]_i_4__0_n_0 ),
        .I1(\last_master_r[2]_i_1__1_n_0 ),
        .I2(\last_master_r[1]_i_1__0_n_0 ),
        .I3(\grant_r_reg[0]_2 ),
        .I4(\grant_r_reg[0]_0 ),
        .I5(\grant_r_reg[1]_0 ),
        .O(\grant_r[1]_i_1__0_n_0 ));
  LUT6 #(
    .INIT(64'h202020AA00000000)) 
    \grant_r[2]_i_1__2 
       (.I0(\grant_r[2]_i_2__1_n_0 ),
        .I1(\last_master_r[2]_i_1__1_n_0 ),
        .I2(\grant_r_reg[3]_0 ),
        .I3(\grant_r_reg[0]_2 ),
        .I4(\grant_r_reg[1]_0 ),
        .I5(\grant_r_reg[0]_1 ),
        .O(\grant_r[2]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'h0777)) 
    \grant_r[2]_i_2__1 
       (.I0(\grant_r_reg[1]_0 ),
        .I1(\last_master_r[0]_i_1__0_n_0 ),
        .I2(\grant_r_reg[0]_0 ),
        .I3(\last_master_r[2]_i_1__1_n_0 ),
        .O(\grant_r[2]_i_2__1_n_0 ));
  LUT6 #(
    .INIT(64'h222F000000000000)) 
    \grant_r[3]_i_1 
       (.I0(\grant_r_reg[3]_0 ),
        .I1(\last_master_r[0]_i_1__0_n_0 ),
        .I2(\grant_r_reg[0]_1 ),
        .I3(\grant_r_reg[1]_0 ),
        .I4(\grant_r[3]_i_4__0_n_0 ),
        .I5(\grant_r_reg[0]_0 ),
        .O(\grant_r[3]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h7077)) 
    \grant_r[3]_i_4__0 
       (.I0(\grant_r_reg[0]_1 ),
        .I1(\last_master_r[1]_i_1__0_n_0 ),
        .I2(\grant_r_reg[3]_0 ),
        .I3(\grant_r_reg[0]_2 ),
        .O(\grant_r[3]_i_4__0_n_0 ));
  FDRE \grant_r_reg[0] 
       (.C(\last_master_r_reg[3]_1 ),
        .CE(1'b1),
        .D(\grant_r[0]_i_1__2_n_0 ),
        .Q(Q[0]),
        .R(1'b0));
  FDRE \grant_r_reg[1] 
       (.C(\last_master_r_reg[3]_1 ),
        .CE(1'b1),
        .D(\grant_r[1]_i_1__0_n_0 ),
        .Q(Q[1]),
        .R(1'b0));
  FDRE \grant_r_reg[2] 
       (.C(\last_master_r_reg[3]_1 ),
        .CE(1'b1),
        .D(\grant_r[2]_i_1__2_n_0 ),
        .Q(Q[2]),
        .R(1'b0));
  FDRE \grant_r_reg[3] 
       (.C(\last_master_r_reg[3]_1 ),
        .CE(1'b1),
        .D(\grant_r[3]_i_1_n_0 ),
        .Q(Q[3]),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h00E2)) 
    \last_master_r[0]_i_1__0 
       (.I0(last_master_r[0]),
        .I1(\cmd_pipe_plus.mc_address_reg[41] ),
        .I2(Q[0]),
        .I3(\last_master_r_reg[1]_0 ),
        .O(\last_master_r[0]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h00E2)) 
    \last_master_r[1]_i_1__0 
       (.I0(last_master_r[1]),
        .I1(\cmd_pipe_plus.mc_address_reg[41] ),
        .I2(Q[1]),
        .I3(\last_master_r_reg[1]_0 ),
        .O(\last_master_r[1]_i_1__0_n_0 ));
  LUT4 #(
    .INIT(16'h00E2)) 
    \last_master_r[2]_i_1__1 
       (.I0(last_master_r[2]),
        .I1(\cmd_pipe_plus.mc_address_reg[41] ),
        .I2(Q[2]),
        .I3(\last_master_r_reg[1]_0 ),
        .O(\last_master_r[2]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'hFFB8)) 
    \last_master_r[3]_i_1__0 
       (.I0(Q[3]),
        .I1(\cmd_pipe_plus.mc_address_reg[41] ),
        .I2(\last_master_r_reg[3]_0 ),
        .I3(\last_master_r_reg[1]_0 ),
        .O(\last_master_r[3]_i_1__0_n_0 ));
  FDRE \last_master_r_reg[0] 
       (.C(\last_master_r_reg[3]_1 ),
        .CE(1'b1),
        .D(\last_master_r[0]_i_1__0_n_0 ),
        .Q(last_master_r[0]),
        .R(1'b0));
  FDRE \last_master_r_reg[1] 
       (.C(\last_master_r_reg[3]_1 ),
        .CE(1'b1),
        .D(\last_master_r[1]_i_1__0_n_0 ),
        .Q(last_master_r[1]),
        .R(1'b0));
  FDRE \last_master_r_reg[2] 
       (.C(\last_master_r_reg[3]_1 ),
        .CE(1'b1),
        .D(\last_master_r[2]_i_1__1_n_0 ),
        .Q(last_master_r[2]),
        .R(1'b0));
  FDRE \last_master_r_reg[3] 
       (.C(\last_master_r_reg[3]_1 ),
        .CE(1'b1),
        .D(\last_master_r[3]_i_1__0_n_0 ),
        .Q(\last_master_r_reg[3]_0 ),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_round_robin_arb" *) 
module mig_mig_7series_v4_2_round_robin_arb__parameterized1_4
   (granted_row_ns,
    mc_we_n_ns,
    Q,
    mc_cas_n_ns,
    mc_ras_n_ns,
    \grant_r_reg[0]_0 ,
    \req_row_r_lcl_reg[13] ,
    \grant_r_reg[1]_0 ,
    \grant_r_reg[0]_1 ,
    act_this_rank,
    \grant_r_reg[0]_2 ,
    \grant_r_reg[3]_0 ,
    granted_row_r_reg,
    \grant_r_reg[3]_1 ,
    \cmd_pipe_plus.mc_we_n_reg[0] ,
    \cmd_pipe_plus.mc_we_n_reg[0]_0 ,
    \cmd_pipe_plus.mc_address_reg[0] ,
    \cmd_pipe_plus.mc_cas_n_reg[0] ,
    \cmd_pipe_plus.mc_ras_n_reg[0] ,
    maint_zq_r,
    maint_srx_r,
    \last_master_r_reg[2]_0 ,
    \cmd_pipe_plus.mc_bank_reg[2] ,
    \cmd_pipe_plus.mc_address_reg[3] ,
    \cmd_pipe_plus.mc_bank_reg[2]_0 ,
    \cmd_pipe_plus.mc_address_reg[0]_0 ,
    \cmd_pipe_plus.mc_bank_reg[2]_1 ,
    \cmd_pipe_plus.mc_bank_reg[2]_2 ,
    \cmd_pipe_plus.mc_address_reg[13] ,
    req_row_r,
    \cmd_pipe_plus.mc_address_reg[10] ,
    \cmd_pipe_plus.mc_address_reg[10]_0 ,
    \cmd_pipe_plus.mc_we_n_reg[0]_1 ,
    \cmd_pipe_plus.mc_we_n_reg[0]_2 ,
    \grant_r_reg[3]_2 ,
    i___70,
    inhbt_act_faw_r,
    act_this_rank_r,
    \last_master_r_reg[3]_0 );
  output granted_row_ns;
  output [0:0]mc_we_n_ns;
  output [3:0]Q;
  output [0:0]mc_cas_n_ns;
  output [0:0]mc_ras_n_ns;
  output [2:0]\grant_r_reg[0]_0 ;
  output [13:0]\req_row_r_lcl_reg[13] ;
  output \grant_r_reg[1]_0 ;
  output \grant_r_reg[0]_1 ;
  output act_this_rank;
  output \grant_r_reg[0]_2 ;
  input \grant_r_reg[3]_0 ;
  input granted_row_r_reg;
  input \grant_r_reg[3]_1 ;
  input \cmd_pipe_plus.mc_we_n_reg[0] ;
  input \cmd_pipe_plus.mc_we_n_reg[0]_0 ;
  input \cmd_pipe_plus.mc_address_reg[0] ;
  input \cmd_pipe_plus.mc_cas_n_reg[0] ;
  input \cmd_pipe_plus.mc_ras_n_reg[0] ;
  input maint_zq_r;
  input maint_srx_r;
  input \last_master_r_reg[2]_0 ;
  input [2:0]\cmd_pipe_plus.mc_bank_reg[2] ;
  input \cmd_pipe_plus.mc_address_reg[3] ;
  input [2:0]\cmd_pipe_plus.mc_bank_reg[2]_0 ;
  input \cmd_pipe_plus.mc_address_reg[0]_0 ;
  input [2:0]\cmd_pipe_plus.mc_bank_reg[2]_1 ;
  input [2:0]\cmd_pipe_plus.mc_bank_reg[2]_2 ;
  input [19:0]\cmd_pipe_plus.mc_address_reg[13] ;
  input [33:0]req_row_r;
  input \cmd_pipe_plus.mc_address_reg[10] ;
  input \cmd_pipe_plus.mc_address_reg[10]_0 ;
  input \cmd_pipe_plus.mc_we_n_reg[0]_1 ;
  input \cmd_pipe_plus.mc_we_n_reg[0]_2 ;
  input \grant_r_reg[3]_2 ;
  input i___70;
  input inhbt_act_faw_r;
  input [3:0]act_this_rank_r;
  input \last_master_r_reg[3]_0 ;

  wire [3:0]Q;
  wire act_this_rank;
  wire [3:0]act_this_rank_r;
  wire \cmd_pipe_plus.mc_address[0]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[10]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[11]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[12]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[13]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[1]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[2]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[3]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[4]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[5]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[6]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[7]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[8]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address[9]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_address_reg[0] ;
  wire \cmd_pipe_plus.mc_address_reg[0]_0 ;
  wire \cmd_pipe_plus.mc_address_reg[10] ;
  wire \cmd_pipe_plus.mc_address_reg[10]_0 ;
  wire [19:0]\cmd_pipe_plus.mc_address_reg[13] ;
  wire \cmd_pipe_plus.mc_address_reg[3] ;
  wire \cmd_pipe_plus.mc_bank[0]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_bank[1]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_bank[2]_i_2_n_0 ;
  wire [2:0]\cmd_pipe_plus.mc_bank_reg[2] ;
  wire [2:0]\cmd_pipe_plus.mc_bank_reg[2]_0 ;
  wire [2:0]\cmd_pipe_plus.mc_bank_reg[2]_1 ;
  wire [2:0]\cmd_pipe_plus.mc_bank_reg[2]_2 ;
  wire \cmd_pipe_plus.mc_cas_n_reg[0] ;
  wire \cmd_pipe_plus.mc_ras_n[0]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_ras_n_reg[0] ;
  wire \cmd_pipe_plus.mc_we_n[0]_i_2_n_0 ;
  wire \cmd_pipe_plus.mc_we_n_reg[0] ;
  wire \cmd_pipe_plus.mc_we_n_reg[0]_0 ;
  wire \cmd_pipe_plus.mc_we_n_reg[0]_1 ;
  wire \cmd_pipe_plus.mc_we_n_reg[0]_2 ;
  wire \grant_r[0]_i_1__1_n_0 ;
  wire \grant_r[1]_i_1__2_n_0 ;
  wire \grant_r[2]_i_1__1_n_0 ;
  wire \grant_r[2]_i_2__0_n_0 ;
  wire \grant_r[3]_i_1__1_n_0 ;
  wire \grant_r[3]_i_2__0_n_0 ;
  wire \grant_r[3]_i_3__0_n_0 ;
  wire [2:0]\grant_r_reg[0]_0 ;
  wire \grant_r_reg[0]_1 ;
  wire \grant_r_reg[0]_2 ;
  wire \grant_r_reg[1]_0 ;
  wire \grant_r_reg[3]_0 ;
  wire \grant_r_reg[3]_1 ;
  wire \grant_r_reg[3]_2 ;
  wire granted_row_ns;
  wire granted_row_r_reg;
  wire i___70;
  wire i___79_i_2_n_0;
  wire inhbt_act_faw_r;
  wire [3:0]last_master_r;
  wire \last_master_r[0]_i_1__1_n_0 ;
  wire \last_master_r[1]_i_1__1_n_0 ;
  wire \last_master_r[2]_i_1__2_n_0 ;
  wire \last_master_r[3]_i_1__1_n_0 ;
  wire \last_master_r_reg[2]_0 ;
  wire \last_master_r_reg[3]_0 ;
  wire maint_srx_r;
  wire maint_zq_r;
  wire [0:0]mc_cas_n_ns;
  wire [0:0]mc_ras_n_ns;
  wire [0:0]mc_we_n_ns;
  wire [33:0]req_row_r;
  wire [13:0]\req_row_r_lcl_reg[13] ;

  LUT5 #(
    .INIT(32'hF800F8F8)) 
    \cmd_pipe_plus.mc_address[0]_i_1 
       (.I0(\cmd_pipe_plus.mc_address_reg[13] [0]),
        .I1(Q[0]),
        .I2(\cmd_pipe_plus.mc_address_reg[0] ),
        .I3(\cmd_pipe_plus.mc_address[0]_i_2_n_0 ),
        .I4(\cmd_pipe_plus.mc_address_reg[0]_0 ),
        .O(\req_row_r_lcl_reg[13] [0]));
  LUT6 #(
    .INIT(64'hFFFFF8080000F808)) 
    \cmd_pipe_plus.mc_address[0]_i_2 
       (.I0(Q[1]),
        .I1(req_row_r[3]),
        .I2(Q[2]),
        .I3(req_row_r[12]),
        .I4(Q[3]),
        .I5(req_row_r[23]),
        .O(\cmd_pipe_plus.mc_address[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFF800000FF80FF80)) 
    \cmd_pipe_plus.mc_address[10]_i_1 
       (.I0(Q[0]),
        .I1(\cmd_pipe_plus.mc_address_reg[10] ),
        .I2(req_row_r[1]),
        .I3(\cmd_pipe_plus.mc_address_reg[0] ),
        .I4(\cmd_pipe_plus.mc_address[10]_i_2_n_0 ),
        .I5(\cmd_pipe_plus.mc_address_reg[0]_0 ),
        .O(\req_row_r_lcl_reg[13] [10]));
  LUT6 #(
    .INIT(64'hAAAAAAEAAAAAAAAA)) 
    \cmd_pipe_plus.mc_address[10]_i_2 
       (.I0(\cmd_pipe_plus.mc_address_reg[10]_0 ),
        .I1(\cmd_pipe_plus.mc_we_n_reg[0]_0 ),
        .I2(Q[1]),
        .I3(Q[3]),
        .I4(Q[2]),
        .I5(\cmd_pipe_plus.mc_address_reg[13] [12]),
        .O(\cmd_pipe_plus.mc_address[10]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hF800F8F8F800F800)) 
    \cmd_pipe_plus.mc_address[11]_i_1 
       (.I0(req_row_r[2]),
        .I1(Q[0]),
        .I2(\cmd_pipe_plus.mc_address_reg[0] ),
        .I3(\cmd_pipe_plus.mc_address[11]_i_2_n_0 ),
        .I4(\cmd_pipe_plus.mc_address_reg[3] ),
        .I5(\cmd_pipe_plus.mc_address_reg[13] [13]),
        .O(\req_row_r_lcl_reg[13] [11]));
  LUT5 #(
    .INIT(32'hFFD555D5)) 
    \cmd_pipe_plus.mc_address[11]_i_2 
       (.I0(\cmd_pipe_plus.mc_address_reg[0]_0 ),
        .I1(req_row_r[22]),
        .I2(Q[2]),
        .I3(Q[3]),
        .I4(req_row_r[33]),
        .O(\cmd_pipe_plus.mc_address[11]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hF800F8F8F800F800)) 
    \cmd_pipe_plus.mc_address[12]_i_1 
       (.I0(\cmd_pipe_plus.mc_address_reg[13] [9]),
        .I1(Q[0]),
        .I2(\cmd_pipe_plus.mc_address_reg[0] ),
        .I3(\cmd_pipe_plus.mc_address[12]_i_2_n_0 ),
        .I4(\cmd_pipe_plus.mc_address_reg[3] ),
        .I5(\cmd_pipe_plus.mc_address_reg[13] [14]),
        .O(\req_row_r_lcl_reg[13] [12]));
  LUT5 #(
    .INIT(32'hFFD555D5)) 
    \cmd_pipe_plus.mc_address[12]_i_2 
       (.I0(\cmd_pipe_plus.mc_address_reg[0]_0 ),
        .I1(\cmd_pipe_plus.mc_address_reg[13] [16]),
        .I2(Q[2]),
        .I3(Q[3]),
        .I4(\cmd_pipe_plus.mc_address_reg[13] [18]),
        .O(\cmd_pipe_plus.mc_address[12]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hF800F8F8)) 
    \cmd_pipe_plus.mc_address[13]_i_1 
       (.I0(\cmd_pipe_plus.mc_address_reg[13] [10]),
        .I1(Q[0]),
        .I2(\cmd_pipe_plus.mc_address_reg[0] ),
        .I3(\cmd_pipe_plus.mc_address[13]_i_2_n_0 ),
        .I4(\cmd_pipe_plus.mc_address_reg[0]_0 ),
        .O(\req_row_r_lcl_reg[13] [13]));
  LUT6 #(
    .INIT(64'hFFFFF8080000F808)) 
    \cmd_pipe_plus.mc_address[13]_i_2 
       (.I0(Q[1]),
        .I1(\cmd_pipe_plus.mc_address_reg[13] [15]),
        .I2(Q[2]),
        .I3(\cmd_pipe_plus.mc_address_reg[13] [17]),
        .I4(Q[3]),
        .I5(\cmd_pipe_plus.mc_address_reg[13] [19]),
        .O(\cmd_pipe_plus.mc_address[13]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hF800F8F8)) 
    \cmd_pipe_plus.mc_address[1]_i_1 
       (.I0(\cmd_pipe_plus.mc_address_reg[13] [1]),
        .I1(Q[0]),
        .I2(\cmd_pipe_plus.mc_address_reg[0] ),
        .I3(\cmd_pipe_plus.mc_address[1]_i_2_n_0 ),
        .I4(\cmd_pipe_plus.mc_address_reg[0]_0 ),
        .O(\req_row_r_lcl_reg[13] [1]));
  LUT6 #(
    .INIT(64'hFFFFF8080000F808)) 
    \cmd_pipe_plus.mc_address[1]_i_2 
       (.I0(Q[1]),
        .I1(req_row_r[4]),
        .I2(Q[2]),
        .I3(req_row_r[13]),
        .I4(Q[3]),
        .I5(req_row_r[24]),
        .O(\cmd_pipe_plus.mc_address[1]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hF800F8F8)) 
    \cmd_pipe_plus.mc_address[2]_i_1 
       (.I0(\cmd_pipe_plus.mc_address_reg[13] [2]),
        .I1(Q[0]),
        .I2(\cmd_pipe_plus.mc_address_reg[0] ),
        .I3(\cmd_pipe_plus.mc_address[2]_i_2_n_0 ),
        .I4(\cmd_pipe_plus.mc_address_reg[0]_0 ),
        .O(\req_row_r_lcl_reg[13] [2]));
  LUT6 #(
    .INIT(64'hFFFFF8080000F808)) 
    \cmd_pipe_plus.mc_address[2]_i_2 
       (.I0(Q[1]),
        .I1(req_row_r[5]),
        .I2(Q[2]),
        .I3(req_row_r[14]),
        .I4(Q[3]),
        .I5(req_row_r[25]),
        .O(\cmd_pipe_plus.mc_address[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hF800F8F8F800F800)) 
    \cmd_pipe_plus.mc_address[3]_i_1 
       (.I0(\cmd_pipe_plus.mc_address_reg[13] [3]),
        .I1(Q[0]),
        .I2(\cmd_pipe_plus.mc_address_reg[0] ),
        .I3(\cmd_pipe_plus.mc_address[3]_i_2_n_0 ),
        .I4(\cmd_pipe_plus.mc_address_reg[3] ),
        .I5(req_row_r[6]),
        .O(\req_row_r_lcl_reg[13] [3]));
  LUT5 #(
    .INIT(32'hFFD555D5)) 
    \cmd_pipe_plus.mc_address[3]_i_2 
       (.I0(\cmd_pipe_plus.mc_address_reg[0]_0 ),
        .I1(req_row_r[15]),
        .I2(Q[2]),
        .I3(Q[3]),
        .I4(req_row_r[26]),
        .O(\cmd_pipe_plus.mc_address[3]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hF800F8F8)) 
    \cmd_pipe_plus.mc_address[4]_i_1 
       (.I0(\cmd_pipe_plus.mc_address_reg[13] [4]),
        .I1(Q[0]),
        .I2(\cmd_pipe_plus.mc_address_reg[0] ),
        .I3(\cmd_pipe_plus.mc_address[4]_i_2_n_0 ),
        .I4(\cmd_pipe_plus.mc_address_reg[0]_0 ),
        .O(\req_row_r_lcl_reg[13] [4]));
  LUT6 #(
    .INIT(64'hFFFFF8080000F808)) 
    \cmd_pipe_plus.mc_address[4]_i_2 
       (.I0(Q[1]),
        .I1(req_row_r[7]),
        .I2(Q[2]),
        .I3(req_row_r[16]),
        .I4(Q[3]),
        .I5(req_row_r[27]),
        .O(\cmd_pipe_plus.mc_address[4]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hF800F8F8F800F800)) 
    \cmd_pipe_plus.mc_address[5]_i_1 
       (.I0(\cmd_pipe_plus.mc_address_reg[13] [5]),
        .I1(Q[0]),
        .I2(\cmd_pipe_plus.mc_address_reg[0] ),
        .I3(\cmd_pipe_plus.mc_address[5]_i_2_n_0 ),
        .I4(\cmd_pipe_plus.mc_address_reg[3] ),
        .I5(req_row_r[8]),
        .O(\req_row_r_lcl_reg[13] [5]));
  LUT5 #(
    .INIT(32'hFFD555D5)) 
    \cmd_pipe_plus.mc_address[5]_i_2 
       (.I0(\cmd_pipe_plus.mc_address_reg[0]_0 ),
        .I1(req_row_r[17]),
        .I2(Q[2]),
        .I3(Q[3]),
        .I4(req_row_r[28]),
        .O(\cmd_pipe_plus.mc_address[5]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hF800F8F8)) 
    \cmd_pipe_plus.mc_address[6]_i_1 
       (.I0(\cmd_pipe_plus.mc_address_reg[13] [6]),
        .I1(Q[0]),
        .I2(\cmd_pipe_plus.mc_address_reg[0] ),
        .I3(\cmd_pipe_plus.mc_address[6]_i_2_n_0 ),
        .I4(\cmd_pipe_plus.mc_address_reg[0]_0 ),
        .O(\req_row_r_lcl_reg[13] [6]));
  LUT6 #(
    .INIT(64'hFFFFF8080000F808)) 
    \cmd_pipe_plus.mc_address[6]_i_2 
       (.I0(Q[1]),
        .I1(req_row_r[9]),
        .I2(Q[2]),
        .I3(req_row_r[18]),
        .I4(Q[3]),
        .I5(req_row_r[29]),
        .O(\cmd_pipe_plus.mc_address[6]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hF800F8F8)) 
    \cmd_pipe_plus.mc_address[7]_i_1 
       (.I0(\cmd_pipe_plus.mc_address_reg[13] [7]),
        .I1(Q[0]),
        .I2(\cmd_pipe_plus.mc_address_reg[0] ),
        .I3(\cmd_pipe_plus.mc_address[7]_i_2_n_0 ),
        .I4(\cmd_pipe_plus.mc_address_reg[0]_0 ),
        .O(\req_row_r_lcl_reg[13] [7]));
  LUT6 #(
    .INIT(64'hFFFFF8080000F808)) 
    \cmd_pipe_plus.mc_address[7]_i_2 
       (.I0(Q[1]),
        .I1(req_row_r[10]),
        .I2(Q[2]),
        .I3(req_row_r[19]),
        .I4(Q[3]),
        .I5(req_row_r[30]),
        .O(\cmd_pipe_plus.mc_address[7]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hF800F8F8)) 
    \cmd_pipe_plus.mc_address[8]_i_1 
       (.I0(\cmd_pipe_plus.mc_address_reg[13] [8]),
        .I1(Q[0]),
        .I2(\cmd_pipe_plus.mc_address_reg[0] ),
        .I3(\cmd_pipe_plus.mc_address[8]_i_2_n_0 ),
        .I4(\cmd_pipe_plus.mc_address_reg[0]_0 ),
        .O(\req_row_r_lcl_reg[13] [8]));
  LUT6 #(
    .INIT(64'hFFFFF8080000F808)) 
    \cmd_pipe_plus.mc_address[8]_i_2 
       (.I0(Q[1]),
        .I1(req_row_r[11]),
        .I2(Q[2]),
        .I3(req_row_r[20]),
        .I4(Q[3]),
        .I5(req_row_r[31]),
        .O(\cmd_pipe_plus.mc_address[8]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hF800F8F8)) 
    \cmd_pipe_plus.mc_address[9]_i_1 
       (.I0(req_row_r[0]),
        .I1(Q[0]),
        .I2(\cmd_pipe_plus.mc_address_reg[0] ),
        .I3(\cmd_pipe_plus.mc_address[9]_i_2_n_0 ),
        .I4(\cmd_pipe_plus.mc_address_reg[0]_0 ),
        .O(\req_row_r_lcl_reg[13] [9]));
  LUT6 #(
    .INIT(64'hFFFFF8080000F808)) 
    \cmd_pipe_plus.mc_address[9]_i_2 
       (.I0(Q[1]),
        .I1(\cmd_pipe_plus.mc_address_reg[13] [11]),
        .I2(Q[2]),
        .I3(req_row_r[21]),
        .I4(Q[3]),
        .I5(req_row_r[32]),
        .O(\cmd_pipe_plus.mc_address[9]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'hF800F8F8)) 
    \cmd_pipe_plus.mc_bank[0]_i_1 
       (.I0(Q[0]),
        .I1(\cmd_pipe_plus.mc_bank_reg[2] [0]),
        .I2(\cmd_pipe_plus.mc_address_reg[0] ),
        .I3(\cmd_pipe_plus.mc_bank[0]_i_2_n_0 ),
        .I4(\cmd_pipe_plus.mc_address_reg[0]_0 ),
        .O(\grant_r_reg[0]_0 [0]));
  LUT6 #(
    .INIT(64'hFFFFF0880000F088)) 
    \cmd_pipe_plus.mc_bank[0]_i_2 
       (.I0(Q[1]),
        .I1(\cmd_pipe_plus.mc_bank_reg[2]_0 [0]),
        .I2(\cmd_pipe_plus.mc_bank_reg[2]_1 [0]),
        .I3(Q[2]),
        .I4(Q[3]),
        .I5(\cmd_pipe_plus.mc_bank_reg[2]_2 [0]),
        .O(\cmd_pipe_plus.mc_bank[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hF800F8F8F800F800)) 
    \cmd_pipe_plus.mc_bank[1]_i_1 
       (.I0(Q[0]),
        .I1(\cmd_pipe_plus.mc_bank_reg[2] [1]),
        .I2(\cmd_pipe_plus.mc_address_reg[0] ),
        .I3(\cmd_pipe_plus.mc_bank[1]_i_2_n_0 ),
        .I4(\cmd_pipe_plus.mc_address_reg[3] ),
        .I5(\cmd_pipe_plus.mc_bank_reg[2]_0 [1]),
        .O(\grant_r_reg[0]_0 [1]));
  LUT5 #(
    .INIT(32'hFFD555D5)) 
    \cmd_pipe_plus.mc_bank[1]_i_2 
       (.I0(\cmd_pipe_plus.mc_address_reg[0]_0 ),
        .I1(\cmd_pipe_plus.mc_bank_reg[2]_1 [1]),
        .I2(Q[2]),
        .I3(Q[3]),
        .I4(\cmd_pipe_plus.mc_bank_reg[2]_2 [1]),
        .O(\cmd_pipe_plus.mc_bank[1]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hEA00EAEAEA00EA00)) 
    \cmd_pipe_plus.mc_bank[2]_i_1 
       (.I0(\cmd_pipe_plus.mc_address_reg[0] ),
        .I1(Q[0]),
        .I2(\cmd_pipe_plus.mc_bank_reg[2] [2]),
        .I3(\cmd_pipe_plus.mc_bank[2]_i_2_n_0 ),
        .I4(\cmd_pipe_plus.mc_address_reg[3] ),
        .I5(\cmd_pipe_plus.mc_bank_reg[2]_0 [2]),
        .O(\grant_r_reg[0]_0 [2]));
  LUT5 #(
    .INIT(32'hFFD555D5)) 
    \cmd_pipe_plus.mc_bank[2]_i_2 
       (.I0(\cmd_pipe_plus.mc_address_reg[0]_0 ),
        .I1(\cmd_pipe_plus.mc_bank_reg[2]_1 [2]),
        .I2(Q[2]),
        .I3(Q[3]),
        .I4(\cmd_pipe_plus.mc_bank_reg[2]_2 [2]),
        .O(\cmd_pipe_plus.mc_bank[2]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hFBFAFBFAFBFAFAFA)) 
    \cmd_pipe_plus.mc_cas_n[0]_i_1 
       (.I0(\cmd_pipe_plus.mc_address_reg[0] ),
        .I1(\cmd_pipe_plus.mc_cas_n_reg[0] ),
        .I2(Q[0]),
        .I3(\cmd_pipe_plus.mc_ras_n_reg[0] ),
        .I4(maint_zq_r),
        .I5(maint_srx_r),
        .O(mc_cas_n_ns));
  LUT6 #(
    .INIT(64'h000200020002FFFF)) 
    \cmd_pipe_plus.mc_ras_n[0]_i_1 
       (.I0(\cmd_pipe_plus.mc_ras_n[0]_i_2_n_0 ),
        .I1(Q[1]),
        .I2(Q[2]),
        .I3(Q[3]),
        .I4(\cmd_pipe_plus.mc_ras_n_reg[0] ),
        .I5(\last_master_r_reg[2]_0 ),
        .O(mc_ras_n_ns));
  LUT5 #(
    .INIT(32'h10101000)) 
    \cmd_pipe_plus.mc_ras_n[0]_i_2 
       (.I0(\cmd_pipe_plus.mc_cas_n_reg[0] ),
        .I1(Q[0]),
        .I2(\cmd_pipe_plus.mc_ras_n_reg[0] ),
        .I3(maint_zq_r),
        .I4(maint_srx_r),
        .O(\cmd_pipe_plus.mc_ras_n[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'hCCCCCCCCCCCCFCDD)) 
    \cmd_pipe_plus.mc_we_n[0]_i_1 
       (.I0(\cmd_pipe_plus.mc_we_n_reg[0] ),
        .I1(\cmd_pipe_plus.mc_we_n[0]_i_2_n_0 ),
        .I2(\cmd_pipe_plus.mc_we_n_reg[0]_0 ),
        .I3(Q[1]),
        .I4(Q[3]),
        .I5(Q[2]),
        .O(mc_we_n_ns));
  LUT6 #(
    .INIT(64'hF088F088F088FFFF)) 
    \cmd_pipe_plus.mc_we_n[0]_i_2 
       (.I0(Q[2]),
        .I1(\cmd_pipe_plus.mc_we_n_reg[0]_1 ),
        .I2(\cmd_pipe_plus.mc_we_n_reg[0]_2 ),
        .I3(Q[3]),
        .I4(\cmd_pipe_plus.mc_ras_n_reg[0] ),
        .I5(\last_master_r_reg[2]_0 ),
        .O(\cmd_pipe_plus.mc_we_n[0]_i_2_n_0 ));
  LUT6 #(
    .INIT(64'h0202AA0200000000)) 
    \grant_r[0]_i_1__1 
       (.I0(\grant_r[2]_i_2__0_n_0 ),
        .I1(\last_master_r[0]_i_1__1_n_0 ),
        .I2(\last_master_r[1]_i_1__1_n_0 ),
        .I3(\grant_r[3]_i_2__0_n_0 ),
        .I4(\grant_r_reg[3]_0 ),
        .I5(granted_row_r_reg),
        .O(\grant_r[0]_i_1__1_n_0 ));
  LUT6 #(
    .INIT(64'h100010001000F000)) 
    \grant_r[1]_i_1__2 
       (.I0(\grant_r_reg[3]_0 ),
        .I1(granted_row_r_reg),
        .I2(\grant_r[3]_i_3__0_n_0 ),
        .I3(\grant_r_reg[3]_1 ),
        .I4(\last_master_r[2]_i_1__2_n_0 ),
        .I5(\last_master_r[1]_i_1__1_n_0 ),
        .O(\grant_r[1]_i_1__2_n_0 ));
  LUT6 #(
    .INIT(64'h00000000020202AA)) 
    \grant_r[2]_i_1__1 
       (.I0(\grant_r[2]_i_2__0_n_0 ),
        .I1(granted_row_r_reg),
        .I2(\grant_r_reg[3]_1 ),
        .I3(\last_master_r[2]_i_1__2_n_0 ),
        .I4(\last_master_r[3]_i_1__1_n_0 ),
        .I5(\grant_r[3]_i_2__0_n_0 ),
        .O(\grant_r[2]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h0777)) 
    \grant_r[2]_i_2__0 
       (.I0(\grant_r_reg[3]_1 ),
        .I1(\last_master_r[0]_i_1__1_n_0 ),
        .I2(\grant_r_reg[3]_0 ),
        .I3(\last_master_r[2]_i_1__2_n_0 ),
        .O(\grant_r[2]_i_2__0_n_0 ));
  LUT6 #(
    .INIT(64'h222F000000000000)) 
    \grant_r[3]_i_1__1 
       (.I0(\grant_r[3]_i_2__0_n_0 ),
        .I1(\grant_r_reg[3]_1 ),
        .I2(\last_master_r[0]_i_1__1_n_0 ),
        .I3(\last_master_r[3]_i_1__1_n_0 ),
        .I4(\grant_r[3]_i_3__0_n_0 ),
        .I5(\grant_r_reg[3]_0 ),
        .O(\grant_r[3]_i_1__1_n_0 ));
  LUT5 #(
    .INIT(32'hFFFFFEEE)) 
    \grant_r[3]_i_2__0 
       (.I0(\grant_r_reg[3]_2 ),
        .I1(Q[2]),
        .I2(Q[0]),
        .I3(\cmd_pipe_plus.mc_address_reg[10] ),
        .I4(\grant_r_reg[1]_0 ),
        .O(\grant_r[3]_i_2__0_n_0 ));
  LUT4 #(
    .INIT(16'h0BBB)) 
    \grant_r[3]_i_3__0 
       (.I0(\grant_r[3]_i_2__0_n_0 ),
        .I1(\last_master_r[1]_i_1__1_n_0 ),
        .I2(granted_row_r_reg),
        .I3(\last_master_r[3]_i_1__1_n_0 ),
        .O(\grant_r[3]_i_3__0_n_0 ));
  FDRE \grant_r_reg[0] 
       (.C(\last_master_r_reg[3]_0 ),
        .CE(1'b1),
        .D(\grant_r[0]_i_1__1_n_0 ),
        .Q(Q[0]),
        .R(1'b0));
  FDRE \grant_r_reg[1] 
       (.C(\last_master_r_reg[3]_0 ),
        .CE(1'b1),
        .D(\grant_r[1]_i_1__2_n_0 ),
        .Q(Q[1]),
        .R(1'b0));
  FDRE \grant_r_reg[2] 
       (.C(\last_master_r_reg[3]_0 ),
        .CE(1'b1),
        .D(\grant_r[2]_i_1__1_n_0 ),
        .Q(Q[2]),
        .R(1'b0));
  FDRE \grant_r_reg[3] 
       (.C(\last_master_r_reg[3]_0 ),
        .CE(1'b1),
        .D(\grant_r[3]_i_1__1_n_0 ),
        .Q(Q[3]),
        .R(1'b0));
  LUT4 #(
    .INIT(16'hFFFD)) 
    granted_row_r_i_1
       (.I0(\grant_r[3]_i_2__0_n_0 ),
        .I1(\grant_r_reg[3]_1 ),
        .I2(\grant_r_reg[3]_0 ),
        .I3(granted_row_r_reg),
        .O(granted_row_ns));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFF888)) 
    i___70_i_1
       (.I0(Q[1]),
        .I1(\cmd_pipe_plus.mc_we_n_reg[0]_0 ),
        .I2(\cmd_pipe_plus.mc_we_n_reg[0]_2 ),
        .I3(Q[3]),
        .I4(i___70),
        .I5(inhbt_act_faw_r),
        .O(\grant_r_reg[1]_0 ));
  LUT6 #(
    .INIT(64'hFFFFFFFFFFFFF888)) 
    i___73_i_2
       (.I0(Q[0]),
        .I1(\cmd_pipe_plus.mc_address_reg[10] ),
        .I2(\cmd_pipe_plus.mc_we_n_reg[0]_1 ),
        .I3(Q[2]),
        .I4(i___70),
        .I5(inhbt_act_faw_r),
        .O(\grant_r_reg[0]_1 ));
  LUT5 #(
    .INIT(32'h00000777)) 
    i___79_i_1
       (.I0(Q[0]),
        .I1(act_this_rank_r[0]),
        .I2(Q[3]),
        .I3(act_this_rank_r[3]),
        .I4(i___79_i_2_n_0),
        .O(\grant_r_reg[0]_2 ));
  LUT4 #(
    .INIT(16'hF888)) 
    i___79_i_2
       (.I0(act_this_rank_r[2]),
        .I1(Q[2]),
        .I2(act_this_rank_r[1]),
        .I3(Q[1]),
        .O(i___79_i_2_n_0));
  LUT1 #(
    .INIT(2'h1)) 
    \inhbt_act_faw.SRLC32E0_i_1 
       (.I0(\grant_r_reg[0]_2 ),
        .O(act_this_rank));
  LUT4 #(
    .INIT(16'h00E2)) 
    \last_master_r[0]_i_1__1 
       (.I0(last_master_r[0]),
        .I1(\last_master_r_reg[2]_0 ),
        .I2(Q[0]),
        .I3(\cmd_pipe_plus.mc_cas_n_reg[0] ),
        .O(\last_master_r[0]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h00E2)) 
    \last_master_r[1]_i_1__1 
       (.I0(last_master_r[1]),
        .I1(\last_master_r_reg[2]_0 ),
        .I2(Q[1]),
        .I3(\cmd_pipe_plus.mc_cas_n_reg[0] ),
        .O(\last_master_r[1]_i_1__1_n_0 ));
  LUT4 #(
    .INIT(16'h00E2)) 
    \last_master_r[2]_i_1__2 
       (.I0(last_master_r[2]),
        .I1(\last_master_r_reg[2]_0 ),
        .I2(Q[2]),
        .I3(\cmd_pipe_plus.mc_cas_n_reg[0] ),
        .O(\last_master_r[2]_i_1__2_n_0 ));
  LUT4 #(
    .INIT(16'hFEAE)) 
    \last_master_r[3]_i_1__1 
       (.I0(\cmd_pipe_plus.mc_cas_n_reg[0] ),
        .I1(last_master_r[3]),
        .I2(\last_master_r_reg[2]_0 ),
        .I3(Q[3]),
        .O(\last_master_r[3]_i_1__1_n_0 ));
  FDRE \last_master_r_reg[0] 
       (.C(\last_master_r_reg[3]_0 ),
        .CE(1'b1),
        .D(\last_master_r[0]_i_1__1_n_0 ),
        .Q(last_master_r[0]),
        .R(1'b0));
  FDRE \last_master_r_reg[1] 
       (.C(\last_master_r_reg[3]_0 ),
        .CE(1'b1),
        .D(\last_master_r[1]_i_1__1_n_0 ),
        .Q(last_master_r[1]),
        .R(1'b0));
  FDRE \last_master_r_reg[2] 
       (.C(\last_master_r_reg[3]_0 ),
        .CE(1'b1),
        .D(\last_master_r[2]_i_1__2_n_0 ),
        .Q(last_master_r[2]),
        .R(1'b0));
  FDRE \last_master_r_reg[3] 
       (.C(\last_master_r_reg[3]_0 ),
        .CE(1'b1),
        .D(\last_master_r[3]_i_1__1_n_0 ),
        .Q(last_master_r[3]),
        .R(1'b0));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_tempmon" *) 
module mig_mig_7series_v4_2_tempmon
   (out,
    D,
    clk_ref_i,
    \xadc_supplied_temperature.rst_r1_reg_0 ,
    \sync_cntr_reg[3]_0 );
  output [11:0]out;
  output [11:0]D;
  input clk_ref_i;
  input \xadc_supplied_temperature.rst_r1_reg_0 ;
  input \sync_cntr_reg[3]_0 ;

  wire [11:0]D;
  wire \FSM_onehot_xadc_supplied_temperature.tempmon_state[3]_i_1_n_0 ;
  wire \FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[0] ;
  wire \FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[2] ;
  wire clk_ref_i;
  wire \device_temp_101[11]_i_2_n_0 ;
  wire \device_temp_101[11]_i_4_n_0 ;
  wire \device_temp_101[11]_i_5_n_0 ;
  wire [11:0]device_temp_lcl;
  (* async_reg = "true" *) wire [11:0]device_temp_r;
  wire \device_temp_r[11]_i_1_n_0 ;
  (* async_reg = "true" *) wire [11:0]device_temp_sync_r1;
  (* async_reg = "true" *) wire [11:0]device_temp_sync_r2;
  (* async_reg = "true" *) (* syn_srlstyle = "registers" *) wire [11:0]device_temp_sync_r3;
  (* async_reg = "true" *) wire [11:0]device_temp_sync_r4;
  wire device_temp_sync_r4_neq_r3;
  wire device_temp_sync_r4_neq_r3_i_2_n_0;
  wire device_temp_sync_r4_neq_r3_i_3_n_0;
  wire device_temp_sync_r4_neq_r3_i_4_n_0;
  wire device_temp_sync_r4_neq_r3_i_5_n_0;
  wire device_temp_sync_r4_neq_r3_reg_i_1_n_0;
  wire device_temp_sync_r4_neq_r3_reg_i_1_n_1;
  wire device_temp_sync_r4_neq_r3_reg_i_1_n_2;
  wire device_temp_sync_r4_neq_r3_reg_i_1_n_3;
  (* async_reg = "true" *) wire [11:0]device_temp_sync_r5;
  wire [3:0]p_0_in__0;
  wire [10:0]p_0_in__1;
  wire sync_cntr0;
  wire \sync_cntr[2]_i_1_n_0 ;
  wire \sync_cntr[3]_i_2_n_0 ;
  wire [3:0]sync_cntr_reg;
  wire \sync_cntr_reg[3]_0 ;
  wire \u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ;
  (* async_reg = "true" *) wire \xadc_supplied_temperature.rst_r1 ;
  wire \xadc_supplied_temperature.rst_r1_reg_0 ;
  (* async_reg = "true" *) wire \xadc_supplied_temperature.rst_r2 ;
  wire \xadc_supplied_temperature.sample_en ;
  wire \xadc_supplied_temperature.sample_en_i_1_n_0 ;
  wire \xadc_supplied_temperature.sample_en_i_2_n_0 ;
  wire \xadc_supplied_temperature.sample_timer0 ;
  wire \xadc_supplied_temperature.sample_timer[10]_i_3_n_0 ;
  wire \xadc_supplied_temperature.sample_timer_clr ;
  wire \xadc_supplied_temperature.sample_timer_clr_i_1_n_0 ;
  wire \xadc_supplied_temperature.sample_timer_en ;
  wire \xadc_supplied_temperature.sample_timer_en_i_1_n_0 ;
  wire [10:0]\xadc_supplied_temperature.sample_timer_reg ;
  wire \xadc_supplied_temperature.temperature ;
  wire \xadc_supplied_temperature.xadc_den ;
  wire [15:0]\xadc_supplied_temperature.xadc_do ;
  wire [15:4]\xadc_supplied_temperature.xadc_do_r ;
  wire \xadc_supplied_temperature.xadc_drdy ;
  wire \xadc_supplied_temperature.xadc_drdy_r ;
  wire [3:0]NLW_device_temp_sync_r4_neq_r3_reg_i_1_O_UNCONNECTED;
  wire \NLW_xadc_supplied_temperature.XADC_inst_BUSY_UNCONNECTED ;
  wire \NLW_xadc_supplied_temperature.XADC_inst_EOC_UNCONNECTED ;
  wire \NLW_xadc_supplied_temperature.XADC_inst_EOS_UNCONNECTED ;
  wire \NLW_xadc_supplied_temperature.XADC_inst_JTAGBUSY_UNCONNECTED ;
  wire \NLW_xadc_supplied_temperature.XADC_inst_JTAGLOCKED_UNCONNECTED ;
  wire \NLW_xadc_supplied_temperature.XADC_inst_JTAGMODIFIED_UNCONNECTED ;
  wire \NLW_xadc_supplied_temperature.XADC_inst_OT_UNCONNECTED ;
  wire [7:0]\NLW_xadc_supplied_temperature.XADC_inst_ALM_UNCONNECTED ;
  wire [4:0]\NLW_xadc_supplied_temperature.XADC_inst_CHANNEL_UNCONNECTED ;
  wire [4:0]\NLW_xadc_supplied_temperature.XADC_inst_MUXADDR_UNCONNECTED ;

  assign out[11:0] = device_temp_r;
  LUT6 #(
    .INIT(64'hFFFFFEEEFEEEFEEE)) 
    \FSM_onehot_xadc_supplied_temperature.tempmon_state[3]_i_1 
       (.I0(\xadc_supplied_temperature.temperature ),
        .I1(\xadc_supplied_temperature.sample_timer_clr ),
        .I2(\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[0] ),
        .I3(\xadc_supplied_temperature.sample_en ),
        .I4(\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[2] ),
        .I5(\xadc_supplied_temperature.xadc_drdy_r ),
        .O(\FSM_onehot_xadc_supplied_temperature.tempmon_state[3]_i_1_n_0 ));
  (* FSM_ENCODED_STATES = "INIT_IDLE:0001,REQUEST_READ_TEMP:1000,WAIT_FOR_READ:0100,READ:0010," *) 
  FDSE #(
    .INIT(1'b1)) 
    \FSM_onehot_xadc_supplied_temperature.tempmon_state_reg[0] 
       (.C(clk_ref_i),
        .CE(\FSM_onehot_xadc_supplied_temperature.tempmon_state[3]_i_1_n_0 ),
        .D(\xadc_supplied_temperature.temperature ),
        .Q(\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[0] ),
        .S(\xadc_supplied_temperature.rst_r2 ));
  (* FSM_ENCODED_STATES = "INIT_IDLE:0001,REQUEST_READ_TEMP:1000,WAIT_FOR_READ:0100,READ:0010," *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_xadc_supplied_temperature.tempmon_state_reg[1] 
       (.C(clk_ref_i),
        .CE(\FSM_onehot_xadc_supplied_temperature.tempmon_state[3]_i_1_n_0 ),
        .D(\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[2] ),
        .Q(\xadc_supplied_temperature.temperature ),
        .R(\xadc_supplied_temperature.rst_r2 ));
  (* FSM_ENCODED_STATES = "INIT_IDLE:0001,REQUEST_READ_TEMP:1000,WAIT_FOR_READ:0100,READ:0010," *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_xadc_supplied_temperature.tempmon_state_reg[2] 
       (.C(clk_ref_i),
        .CE(\FSM_onehot_xadc_supplied_temperature.tempmon_state[3]_i_1_n_0 ),
        .D(\xadc_supplied_temperature.sample_timer_clr ),
        .Q(\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[2] ),
        .R(\xadc_supplied_temperature.rst_r2 ));
  (* FSM_ENCODED_STATES = "INIT_IDLE:0001,REQUEST_READ_TEMP:1000,WAIT_FOR_READ:0100,READ:0010," *) 
  FDRE #(
    .INIT(1'b0)) 
    \FSM_onehot_xadc_supplied_temperature.tempmon_state_reg[3] 
       (.C(clk_ref_i),
        .CE(\FSM_onehot_xadc_supplied_temperature.tempmon_state[3]_i_1_n_0 ),
        .D(\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[0] ),
        .Q(\xadc_supplied_temperature.sample_timer_clr ),
        .R(\xadc_supplied_temperature.rst_r2 ));
  LUT4 #(
    .INIT(16'h0700)) 
    \device_temp_101[0]_i_1 
       (.I0(device_temp_r[10]),
        .I1(\device_temp_101[11]_i_2_n_0 ),
        .I2(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ),
        .I3(device_temp_r[0]),
        .O(D[0]));
  LUT3 #(
    .INIT(8'h8A)) 
    \device_temp_101[10]_i_1 
       (.I0(device_temp_r[10]),
        .I1(\device_temp_101[11]_i_2_n_0 ),
        .I2(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ),
        .O(D[10]));
  LUT4 #(
    .INIT(16'hFFF8)) 
    \device_temp_101[11]_i_1 
       (.I0(device_temp_r[10]),
        .I1(\device_temp_101[11]_i_2_n_0 ),
        .I2(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ),
        .I3(device_temp_r[11]),
        .O(D[11]));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAA88888)) 
    \device_temp_101[11]_i_2 
       (.I0(device_temp_r[11]),
        .I1(device_temp_r[9]),
        .I2(device_temp_r[6]),
        .I3(\device_temp_101[11]_i_4_n_0 ),
        .I4(device_temp_r[7]),
        .I5(device_temp_r[8]),
        .O(\device_temp_101[11]_i_2_n_0 ));
  LUT5 #(
    .INIT(32'h0100FFFF)) 
    \device_temp_101[11]_i_3 
       (.I0(device_temp_r[8]),
        .I1(device_temp_r[10]),
        .I2(device_temp_r[9]),
        .I3(\device_temp_101[11]_i_5_n_0 ),
        .I4(device_temp_r[11]),
        .O(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ));
  LUT6 #(
    .INIT(64'hAAAAAAAAAAA88888)) 
    \device_temp_101[11]_i_4 
       (.I0(device_temp_r[5]),
        .I1(device_temp_r[4]),
        .I2(device_temp_r[1]),
        .I3(device_temp_r[0]),
        .I4(device_temp_r[2]),
        .I5(device_temp_r[3]),
        .O(\device_temp_101[11]_i_4_n_0 ));
  LUT6 #(
    .INIT(64'h00155555FFFFFFFF)) 
    \device_temp_101[11]_i_5 
       (.I0(device_temp_r[6]),
        .I1(device_temp_r[2]),
        .I2(device_temp_r[3]),
        .I3(device_temp_r[4]),
        .I4(device_temp_r[5]),
        .I5(device_temp_r[7]),
        .O(\device_temp_101[11]_i_5_n_0 ));
  LUT4 #(
    .INIT(16'h0700)) 
    \device_temp_101[1]_i_1 
       (.I0(device_temp_r[10]),
        .I1(\device_temp_101[11]_i_2_n_0 ),
        .I2(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ),
        .I3(device_temp_r[1]),
        .O(D[1]));
  LUT4 #(
    .INIT(16'hFFF8)) 
    \device_temp_101[2]_i_1 
       (.I0(device_temp_r[10]),
        .I1(\device_temp_101[11]_i_2_n_0 ),
        .I2(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ),
        .I3(device_temp_r[2]),
        .O(D[2]));
  LUT4 #(
    .INIT(16'hF7F0)) 
    \device_temp_101[3]_i_1 
       (.I0(device_temp_r[10]),
        .I1(\device_temp_101[11]_i_2_n_0 ),
        .I2(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ),
        .I3(device_temp_r[3]),
        .O(D[3]));
  LUT4 #(
    .INIT(16'h0700)) 
    \device_temp_101[4]_i_1 
       (.I0(device_temp_r[10]),
        .I1(\device_temp_101[11]_i_2_n_0 ),
        .I2(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ),
        .I3(device_temp_r[4]),
        .O(D[4]));
  LUT4 #(
    .INIT(16'hFFF8)) 
    \device_temp_101[5]_i_1 
       (.I0(device_temp_r[10]),
        .I1(\device_temp_101[11]_i_2_n_0 ),
        .I2(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ),
        .I3(device_temp_r[5]),
        .O(D[5]));
  LUT4 #(
    .INIT(16'h0700)) 
    \device_temp_101[6]_i_1 
       (.I0(device_temp_r[10]),
        .I1(\device_temp_101[11]_i_2_n_0 ),
        .I2(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ),
        .I3(device_temp_r[6]),
        .O(D[6]));
  LUT4 #(
    .INIT(16'hFFF8)) 
    \device_temp_101[7]_i_1 
       (.I0(device_temp_r[10]),
        .I1(\device_temp_101[11]_i_2_n_0 ),
        .I2(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ),
        .I3(device_temp_r[7]),
        .O(D[7]));
  LUT4 #(
    .INIT(16'h0700)) 
    \device_temp_101[8]_i_1 
       (.I0(device_temp_r[10]),
        .I1(\device_temp_101[11]_i_2_n_0 ),
        .I2(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ),
        .I3(device_temp_r[8]),
        .O(D[8]));
  LUT4 #(
    .INIT(16'h0700)) 
    \device_temp_101[9]_i_1 
       (.I0(device_temp_r[10]),
        .I1(\device_temp_101[11]_i_2_n_0 ),
        .I2(\u_memc_ui_top_std/mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_low ),
        .I3(device_temp_r[9]),
        .O(D[9]));
  LUT4 #(
    .INIT(16'h8000)) 
    \device_temp_r[11]_i_1 
       (.I0(sync_cntr_reg[1]),
        .I1(sync_cntr_reg[0]),
        .I2(sync_cntr_reg[3]),
        .I3(sync_cntr_reg[2]),
        .O(\device_temp_r[11]_i_1_n_0 ));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_r_reg[0] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(\device_temp_r[11]_i_1_n_0 ),
        .D(device_temp_sync_r5[0]),
        .Q(device_temp_r[0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_r_reg[10] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(\device_temp_r[11]_i_1_n_0 ),
        .D(device_temp_sync_r5[10]),
        .Q(device_temp_r[10]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_r_reg[11] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(\device_temp_r[11]_i_1_n_0 ),
        .D(device_temp_sync_r5[11]),
        .Q(device_temp_r[11]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_r_reg[1] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(\device_temp_r[11]_i_1_n_0 ),
        .D(device_temp_sync_r5[1]),
        .Q(device_temp_r[1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_r_reg[2] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(\device_temp_r[11]_i_1_n_0 ),
        .D(device_temp_sync_r5[2]),
        .Q(device_temp_r[2]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_r_reg[3] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(\device_temp_r[11]_i_1_n_0 ),
        .D(device_temp_sync_r5[3]),
        .Q(device_temp_r[3]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_r_reg[4] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(\device_temp_r[11]_i_1_n_0 ),
        .D(device_temp_sync_r5[4]),
        .Q(device_temp_r[4]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_r_reg[5] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(\device_temp_r[11]_i_1_n_0 ),
        .D(device_temp_sync_r5[5]),
        .Q(device_temp_r[5]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_r_reg[6] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(\device_temp_r[11]_i_1_n_0 ),
        .D(device_temp_sync_r5[6]),
        .Q(device_temp_r[6]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_r_reg[7] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(\device_temp_r[11]_i_1_n_0 ),
        .D(device_temp_sync_r5[7]),
        .Q(device_temp_r[7]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_r_reg[8] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(\device_temp_r[11]_i_1_n_0 ),
        .D(device_temp_sync_r5[8]),
        .Q(device_temp_r[8]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_r_reg[9] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(\device_temp_r[11]_i_1_n_0 ),
        .D(device_temp_sync_r5[9]),
        .Q(device_temp_r[9]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r1_reg[0] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(1'b1),
        .D(device_temp_lcl[0]),
        .Q(device_temp_sync_r1[0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r1_reg[10] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(1'b1),
        .D(device_temp_lcl[10]),
        .Q(device_temp_sync_r1[10]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r1_reg[11] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(1'b1),
        .D(device_temp_lcl[11]),
        .Q(device_temp_sync_r1[11]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r1_reg[1] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(1'b1),
        .D(device_temp_lcl[1]),
        .Q(device_temp_sync_r1[1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r1_reg[2] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(1'b1),
        .D(device_temp_lcl[2]),
        .Q(device_temp_sync_r1[2]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r1_reg[3] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(1'b1),
        .D(device_temp_lcl[3]),
        .Q(device_temp_sync_r1[3]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r1_reg[4] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(1'b1),
        .D(device_temp_lcl[4]),
        .Q(device_temp_sync_r1[4]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r1_reg[5] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(1'b1),
        .D(device_temp_lcl[5]),
        .Q(device_temp_sync_r1[5]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r1_reg[6] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(1'b1),
        .D(device_temp_lcl[6]),
        .Q(device_temp_sync_r1[6]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r1_reg[7] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(1'b1),
        .D(device_temp_lcl[7]),
        .Q(device_temp_sync_r1[7]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r1_reg[8] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(1'b1),
        .D(device_temp_lcl[8]),
        .Q(device_temp_sync_r1[8]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r1_reg[9] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(1'b1),
        .D(device_temp_lcl[9]),
        .Q(device_temp_sync_r1[9]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r2_reg[0] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r1[0]),
        .Q(device_temp_sync_r2[0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r2_reg[10] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r1[10]),
        .Q(device_temp_sync_r2[10]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r2_reg[11] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r1[11]),
        .Q(device_temp_sync_r2[11]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r2_reg[1] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r1[1]),
        .Q(device_temp_sync_r2[1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r2_reg[2] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r1[2]),
        .Q(device_temp_sync_r2[2]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r2_reg[3] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r1[3]),
        .Q(device_temp_sync_r2[3]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r2_reg[4] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r1[4]),
        .Q(device_temp_sync_r2[4]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r2_reg[5] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r1[5]),
        .Q(device_temp_sync_r2[5]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r2_reg[6] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r1[6]),
        .Q(device_temp_sync_r2[6]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r2_reg[7] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r1[7]),
        .Q(device_temp_sync_r2[7]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r2_reg[8] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r1[8]),
        .Q(device_temp_sync_r2[8]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r2_reg[9] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r1[9]),
        .Q(device_temp_sync_r2[9]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* syn_srlstyle = "registers" *) 
  FDRE \device_temp_sync_r3_reg[0] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r2[0]),
        .Q(device_temp_sync_r3[0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* syn_srlstyle = "registers" *) 
  FDRE \device_temp_sync_r3_reg[10] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r2[10]),
        .Q(device_temp_sync_r3[10]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* syn_srlstyle = "registers" *) 
  FDRE \device_temp_sync_r3_reg[11] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r2[11]),
        .Q(device_temp_sync_r3[11]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* syn_srlstyle = "registers" *) 
  FDRE \device_temp_sync_r3_reg[1] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r2[1]),
        .Q(device_temp_sync_r3[1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* syn_srlstyle = "registers" *) 
  FDRE \device_temp_sync_r3_reg[2] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r2[2]),
        .Q(device_temp_sync_r3[2]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* syn_srlstyle = "registers" *) 
  FDRE \device_temp_sync_r3_reg[3] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r2[3]),
        .Q(device_temp_sync_r3[3]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* syn_srlstyle = "registers" *) 
  FDRE \device_temp_sync_r3_reg[4] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r2[4]),
        .Q(device_temp_sync_r3[4]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* syn_srlstyle = "registers" *) 
  FDRE \device_temp_sync_r3_reg[5] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r2[5]),
        .Q(device_temp_sync_r3[5]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* syn_srlstyle = "registers" *) 
  FDRE \device_temp_sync_r3_reg[6] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r2[6]),
        .Q(device_temp_sync_r3[6]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* syn_srlstyle = "registers" *) 
  FDRE \device_temp_sync_r3_reg[7] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r2[7]),
        .Q(device_temp_sync_r3[7]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* syn_srlstyle = "registers" *) 
  FDRE \device_temp_sync_r3_reg[8] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r2[8]),
        .Q(device_temp_sync_r3[8]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  (* syn_srlstyle = "registers" *) 
  FDRE \device_temp_sync_r3_reg[9] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r2[9]),
        .Q(device_temp_sync_r3[9]),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    device_temp_sync_r4_neq_r3_i_2
       (.I0(device_temp_sync_r4[9]),
        .I1(device_temp_sync_r3[9]),
        .I2(device_temp_sync_r3[11]),
        .I3(device_temp_sync_r4[11]),
        .I4(device_temp_sync_r3[10]),
        .I5(device_temp_sync_r4[10]),
        .O(device_temp_sync_r4_neq_r3_i_2_n_0));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    device_temp_sync_r4_neq_r3_i_3
       (.I0(device_temp_sync_r4[6]),
        .I1(device_temp_sync_r3[6]),
        .I2(device_temp_sync_r3[8]),
        .I3(device_temp_sync_r4[8]),
        .I4(device_temp_sync_r3[7]),
        .I5(device_temp_sync_r4[7]),
        .O(device_temp_sync_r4_neq_r3_i_3_n_0));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    device_temp_sync_r4_neq_r3_i_4
       (.I0(device_temp_sync_r4[3]),
        .I1(device_temp_sync_r3[3]),
        .I2(device_temp_sync_r3[5]),
        .I3(device_temp_sync_r4[5]),
        .I4(device_temp_sync_r3[4]),
        .I5(device_temp_sync_r4[4]),
        .O(device_temp_sync_r4_neq_r3_i_4_n_0));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    device_temp_sync_r4_neq_r3_i_5
       (.I0(device_temp_sync_r4[0]),
        .I1(device_temp_sync_r3[0]),
        .I2(device_temp_sync_r3[2]),
        .I3(device_temp_sync_r4[2]),
        .I4(device_temp_sync_r3[1]),
        .I5(device_temp_sync_r4[1]),
        .O(device_temp_sync_r4_neq_r3_i_5_n_0));
  FDRE device_temp_sync_r4_neq_r3_reg
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r4_neq_r3_reg_i_1_n_0),
        .Q(device_temp_sync_r4_neq_r3),
        .R(1'b0));
  CARRY4 device_temp_sync_r4_neq_r3_reg_i_1
       (.CI(1'b0),
        .CO({device_temp_sync_r4_neq_r3_reg_i_1_n_0,device_temp_sync_r4_neq_r3_reg_i_1_n_1,device_temp_sync_r4_neq_r3_reg_i_1_n_2,device_temp_sync_r4_neq_r3_reg_i_1_n_3}),
        .CYINIT(1'b0),
        .DI({1'b1,1'b1,1'b1,1'b1}),
        .O(NLW_device_temp_sync_r4_neq_r3_reg_i_1_O_UNCONNECTED[3:0]),
        .S({device_temp_sync_r4_neq_r3_i_2_n_0,device_temp_sync_r4_neq_r3_i_3_n_0,device_temp_sync_r4_neq_r3_i_4_n_0,device_temp_sync_r4_neq_r3_i_5_n_0}));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r4_reg[0] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r3[0]),
        .Q(device_temp_sync_r4[0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r4_reg[10] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r3[10]),
        .Q(device_temp_sync_r4[10]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r4_reg[11] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r3[11]),
        .Q(device_temp_sync_r4[11]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r4_reg[1] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r3[1]),
        .Q(device_temp_sync_r4[1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r4_reg[2] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r3[2]),
        .Q(device_temp_sync_r4[2]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r4_reg[3] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r3[3]),
        .Q(device_temp_sync_r4[3]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r4_reg[4] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r3[4]),
        .Q(device_temp_sync_r4[4]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r4_reg[5] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r3[5]),
        .Q(device_temp_sync_r4[5]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r4_reg[6] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r3[6]),
        .Q(device_temp_sync_r4[6]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r4_reg[7] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r3[7]),
        .Q(device_temp_sync_r4[7]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r4_reg[8] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r3[8]),
        .Q(device_temp_sync_r4[8]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r4_reg[9] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r3[9]),
        .Q(device_temp_sync_r4[9]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r5_reg[0] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r4[0]),
        .Q(device_temp_sync_r5[0]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r5_reg[10] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r4[10]),
        .Q(device_temp_sync_r5[10]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r5_reg[11] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r4[11]),
        .Q(device_temp_sync_r5[11]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r5_reg[1] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r4[1]),
        .Q(device_temp_sync_r5[1]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r5_reg[2] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r4[2]),
        .Q(device_temp_sync_r5[2]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r5_reg[3] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r4[3]),
        .Q(device_temp_sync_r5[3]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r5_reg[4] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r4[4]),
        .Q(device_temp_sync_r5[4]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r5_reg[5] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r4[5]),
        .Q(device_temp_sync_r5[5]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r5_reg[6] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r4[6]),
        .Q(device_temp_sync_r5[6]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r5_reg[7] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r4[7]),
        .Q(device_temp_sync_r5[7]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r5_reg[8] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r4[8]),
        .Q(device_temp_sync_r5[8]),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \device_temp_sync_r5_reg[9] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(1'b1),
        .D(device_temp_sync_r4[9]),
        .Q(device_temp_sync_r5[9]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair5" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \sync_cntr[0]_i_1 
       (.I0(sync_cntr_reg[0]),
        .O(p_0_in__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair5" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \sync_cntr[1]_i_1 
       (.I0(sync_cntr_reg[0]),
        .I1(sync_cntr_reg[1]),
        .O(p_0_in__0[1]));
  (* SOFT_HLUTNM = "soft_lutpair2" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \sync_cntr[2]_i_1 
       (.I0(sync_cntr_reg[1]),
        .I1(sync_cntr_reg[0]),
        .I2(sync_cntr_reg[2]),
        .O(\sync_cntr[2]_i_1_n_0 ));
  LUT2 #(
    .INIT(4'hE)) 
    \sync_cntr[3]_i_1 
       (.I0(\xadc_supplied_temperature.rst_r1_reg_0 ),
        .I1(device_temp_sync_r4_neq_r3),
        .O(sync_cntr0));
  LUT4 #(
    .INIT(16'h7FFF)) 
    \sync_cntr[3]_i_2 
       (.I0(sync_cntr_reg[2]),
        .I1(sync_cntr_reg[3]),
        .I2(sync_cntr_reg[0]),
        .I3(sync_cntr_reg[1]),
        .O(\sync_cntr[3]_i_2_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair2" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \sync_cntr[3]_i_3 
       (.I0(sync_cntr_reg[0]),
        .I1(sync_cntr_reg[1]),
        .I2(sync_cntr_reg[2]),
        .I3(sync_cntr_reg[3]),
        .O(p_0_in__0[3]));
  FDRE #(
    .INIT(1'b0)) 
    \sync_cntr_reg[0] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(\sync_cntr[3]_i_2_n_0 ),
        .D(p_0_in__0[0]),
        .Q(sync_cntr_reg[0]),
        .R(sync_cntr0));
  FDRE #(
    .INIT(1'b0)) 
    \sync_cntr_reg[1] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(\sync_cntr[3]_i_2_n_0 ),
        .D(p_0_in__0[1]),
        .Q(sync_cntr_reg[1]),
        .R(sync_cntr0));
  FDRE #(
    .INIT(1'b0)) 
    \sync_cntr_reg[2] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(\sync_cntr[3]_i_2_n_0 ),
        .D(\sync_cntr[2]_i_1_n_0 ),
        .Q(sync_cntr_reg[2]),
        .R(sync_cntr0));
  FDRE #(
    .INIT(1'b0)) 
    \sync_cntr_reg[3] 
       (.C(\sync_cntr_reg[3]_0 ),
        .CE(\sync_cntr[3]_i_2_n_0 ),
        .D(p_0_in__0[3]),
        .Q(sync_cntr_reg[3]),
        .R(sync_cntr0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  XADC #(
    .INIT_40(16'h1000),
    .INIT_41(16'h2FFF),
    .INIT_42(16'h0800),
    .INIT_43(16'h0000),
    .INIT_44(16'h0000),
    .INIT_45(16'h0000),
    .INIT_46(16'h0000),
    .INIT_47(16'h0000),
    .INIT_48(16'h0101),
    .INIT_49(16'h0000),
    .INIT_4A(16'h0100),
    .INIT_4B(16'h0000),
    .INIT_4C(16'h0000),
    .INIT_4D(16'h0000),
    .INIT_4E(16'h0000),
    .INIT_4F(16'h0000),
    .INIT_50(16'hB5ED),
    .INIT_51(16'h57E4),
    .INIT_52(16'hA147),
    .INIT_53(16'hCA33),
    .INIT_54(16'hA93A),
    .INIT_55(16'h52C6),
    .INIT_56(16'h9555),
    .INIT_57(16'hAE4E),
    .INIT_58(16'h5999),
    .INIT_59(16'h0000),
    .INIT_5A(16'h0000),
    .INIT_5B(16'h0000),
    .INIT_5C(16'h5111),
    .INIT_5D(16'h0000),
    .INIT_5E(16'h0000),
    .INIT_5F(16'h0000),
    .IS_CONVSTCLK_INVERTED(1'b0),
    .IS_DCLK_INVERTED(1'b0),
    .SIM_DEVICE("7SERIES"),
    .SIM_MONITOR_FILE("design.txt")) 
    \xadc_supplied_temperature.XADC_inst 
       (.ALM(\NLW_xadc_supplied_temperature.XADC_inst_ALM_UNCONNECTED [7:0]),
        .BUSY(\NLW_xadc_supplied_temperature.XADC_inst_BUSY_UNCONNECTED ),
        .CHANNEL(\NLW_xadc_supplied_temperature.XADC_inst_CHANNEL_UNCONNECTED [4:0]),
        .CONVST(1'b0),
        .CONVSTCLK(1'b0),
        .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .DCLK(clk_ref_i),
        .DEN(\xadc_supplied_temperature.xadc_den ),
        .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .DO(\xadc_supplied_temperature.xadc_do ),
        .DRDY(\xadc_supplied_temperature.xadc_drdy ),
        .DWE(1'b0),
        .EOC(\NLW_xadc_supplied_temperature.XADC_inst_EOC_UNCONNECTED ),
        .EOS(\NLW_xadc_supplied_temperature.XADC_inst_EOS_UNCONNECTED ),
        .JTAGBUSY(\NLW_xadc_supplied_temperature.XADC_inst_JTAGBUSY_UNCONNECTED ),
        .JTAGLOCKED(\NLW_xadc_supplied_temperature.XADC_inst_JTAGLOCKED_UNCONNECTED ),
        .JTAGMODIFIED(\NLW_xadc_supplied_temperature.XADC_inst_JTAGMODIFIED_UNCONNECTED ),
        .MUXADDR(\NLW_xadc_supplied_temperature.XADC_inst_MUXADDR_UNCONNECTED [4:0]),
        .OT(\NLW_xadc_supplied_temperature.XADC_inst_OT_UNCONNECTED ),
        .RESET(1'b0),
        .VAUXN({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .VAUXP({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
        .VN(1'b0),
        .VP(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \xadc_supplied_temperature.rst_r1_reg 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\xadc_supplied_temperature.rst_r1_reg_0 ),
        .Q(\xadc_supplied_temperature.rst_r1 ),
        .R(1'b0));
  (* ASYNC_REG *) 
  (* KEEP = "yes" *) 
  FDRE \xadc_supplied_temperature.rst_r2_reg 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\xadc_supplied_temperature.rst_r1 ),
        .Q(\xadc_supplied_temperature.rst_r2 ),
        .R(1'b0));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \xadc_supplied_temperature.sample_en_i_1 
       (.I0(\xadc_supplied_temperature.sample_timer_reg [10]),
        .I1(\xadc_supplied_temperature.sample_en_i_2_n_0 ),
        .I2(\xadc_supplied_temperature.sample_timer_reg [6]),
        .I3(\xadc_supplied_temperature.sample_timer_reg [8]),
        .I4(\xadc_supplied_temperature.sample_timer_reg [7]),
        .I5(\xadc_supplied_temperature.sample_timer_reg [9]),
        .O(\xadc_supplied_temperature.sample_en_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h0000000000000400)) 
    \xadc_supplied_temperature.sample_en_i_2 
       (.I0(\xadc_supplied_temperature.sample_timer_reg [0]),
        .I1(\xadc_supplied_temperature.sample_timer_reg [1]),
        .I2(\xadc_supplied_temperature.sample_timer_reg [2]),
        .I3(\xadc_supplied_temperature.sample_timer_reg [3]),
        .I4(\xadc_supplied_temperature.sample_timer_reg [5]),
        .I5(\xadc_supplied_temperature.sample_timer_reg [4]),
        .O(\xadc_supplied_temperature.sample_en_i_2_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.sample_en_reg 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\xadc_supplied_temperature.sample_en_i_1_n_0 ),
        .Q(\xadc_supplied_temperature.sample_en ),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \xadc_supplied_temperature.sample_timer[0]_i_1 
       (.I0(\xadc_supplied_temperature.sample_timer_reg [0]),
        .O(p_0_in__1[0]));
  LUT2 #(
    .INIT(4'hE)) 
    \xadc_supplied_temperature.sample_timer[10]_i_1 
       (.I0(\xadc_supplied_temperature.rst_r2 ),
        .I1(\xadc_supplied_temperature.xadc_den ),
        .O(\xadc_supplied_temperature.sample_timer0 ));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \xadc_supplied_temperature.sample_timer[10]_i_2 
       (.I0(\xadc_supplied_temperature.sample_timer_reg [8]),
        .I1(\xadc_supplied_temperature.sample_timer_reg [6]),
        .I2(\xadc_supplied_temperature.sample_timer[10]_i_3_n_0 ),
        .I3(\xadc_supplied_temperature.sample_timer_reg [7]),
        .I4(\xadc_supplied_temperature.sample_timer_reg [9]),
        .I5(\xadc_supplied_temperature.sample_timer_reg [10]),
        .O(p_0_in__1[10]));
  LUT6 #(
    .INIT(64'h8000000000000000)) 
    \xadc_supplied_temperature.sample_timer[10]_i_3 
       (.I0(\xadc_supplied_temperature.sample_timer_reg [5]),
        .I1(\xadc_supplied_temperature.sample_timer_reg [3]),
        .I2(\xadc_supplied_temperature.sample_timer_reg [1]),
        .I3(\xadc_supplied_temperature.sample_timer_reg [0]),
        .I4(\xadc_supplied_temperature.sample_timer_reg [2]),
        .I5(\xadc_supplied_temperature.sample_timer_reg [4]),
        .O(\xadc_supplied_temperature.sample_timer[10]_i_3_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair3" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \xadc_supplied_temperature.sample_timer[1]_i_1 
       (.I0(\xadc_supplied_temperature.sample_timer_reg [0]),
        .I1(\xadc_supplied_temperature.sample_timer_reg [1]),
        .O(p_0_in__1[1]));
  (* SOFT_HLUTNM = "soft_lutpair3" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \xadc_supplied_temperature.sample_timer[2]_i_1 
       (.I0(\xadc_supplied_temperature.sample_timer_reg [0]),
        .I1(\xadc_supplied_temperature.sample_timer_reg [1]),
        .I2(\xadc_supplied_temperature.sample_timer_reg [2]),
        .O(p_0_in__1[2]));
  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \xadc_supplied_temperature.sample_timer[3]_i_1 
       (.I0(\xadc_supplied_temperature.sample_timer_reg [1]),
        .I1(\xadc_supplied_temperature.sample_timer_reg [0]),
        .I2(\xadc_supplied_temperature.sample_timer_reg [2]),
        .I3(\xadc_supplied_temperature.sample_timer_reg [3]),
        .O(p_0_in__1[3]));
  (* SOFT_HLUTNM = "soft_lutpair0" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \xadc_supplied_temperature.sample_timer[4]_i_1 
       (.I0(\xadc_supplied_temperature.sample_timer_reg [2]),
        .I1(\xadc_supplied_temperature.sample_timer_reg [0]),
        .I2(\xadc_supplied_temperature.sample_timer_reg [1]),
        .I3(\xadc_supplied_temperature.sample_timer_reg [3]),
        .I4(\xadc_supplied_temperature.sample_timer_reg [4]),
        .O(p_0_in__1[4]));
  LUT6 #(
    .INIT(64'h7FFFFFFF80000000)) 
    \xadc_supplied_temperature.sample_timer[5]_i_1 
       (.I0(\xadc_supplied_temperature.sample_timer_reg [3]),
        .I1(\xadc_supplied_temperature.sample_timer_reg [1]),
        .I2(\xadc_supplied_temperature.sample_timer_reg [0]),
        .I3(\xadc_supplied_temperature.sample_timer_reg [2]),
        .I4(\xadc_supplied_temperature.sample_timer_reg [4]),
        .I5(\xadc_supplied_temperature.sample_timer_reg [5]),
        .O(p_0_in__1[5]));
  (* SOFT_HLUTNM = "soft_lutpair4" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \xadc_supplied_temperature.sample_timer[6]_i_1 
       (.I0(\xadc_supplied_temperature.sample_timer[10]_i_3_n_0 ),
        .I1(\xadc_supplied_temperature.sample_timer_reg [6]),
        .O(p_0_in__1[6]));
  (* SOFT_HLUTNM = "soft_lutpair4" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \xadc_supplied_temperature.sample_timer[7]_i_1 
       (.I0(\xadc_supplied_temperature.sample_timer[10]_i_3_n_0 ),
        .I1(\xadc_supplied_temperature.sample_timer_reg [6]),
        .I2(\xadc_supplied_temperature.sample_timer_reg [7]),
        .O(p_0_in__1[7]));
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \xadc_supplied_temperature.sample_timer[8]_i_1 
       (.I0(\xadc_supplied_temperature.sample_timer_reg [6]),
        .I1(\xadc_supplied_temperature.sample_timer[10]_i_3_n_0 ),
        .I2(\xadc_supplied_temperature.sample_timer_reg [7]),
        .I3(\xadc_supplied_temperature.sample_timer_reg [8]),
        .O(p_0_in__1[8]));
  (* SOFT_HLUTNM = "soft_lutpair1" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \xadc_supplied_temperature.sample_timer[9]_i_1 
       (.I0(\xadc_supplied_temperature.sample_timer_reg [7]),
        .I1(\xadc_supplied_temperature.sample_timer[10]_i_3_n_0 ),
        .I2(\xadc_supplied_temperature.sample_timer_reg [6]),
        .I3(\xadc_supplied_temperature.sample_timer_reg [8]),
        .I4(\xadc_supplied_temperature.sample_timer_reg [9]),
        .O(p_0_in__1[9]));
  LUT4 #(
    .INIT(16'h000E)) 
    \xadc_supplied_temperature.sample_timer_clr_i_1 
       (.I0(\xadc_supplied_temperature.xadc_den ),
        .I1(\xadc_supplied_temperature.sample_timer_clr ),
        .I2(\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[2] ),
        .I3(\xadc_supplied_temperature.rst_r2 ),
        .O(\xadc_supplied_temperature.sample_timer_clr_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.sample_timer_clr_reg 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\xadc_supplied_temperature.sample_timer_clr_i_1_n_0 ),
        .Q(\xadc_supplied_temperature.xadc_den ),
        .R(1'b0));
  LUT5 #(
    .INIT(32'h000000FE)) 
    \xadc_supplied_temperature.sample_timer_en_i_1 
       (.I0(\xadc_supplied_temperature.sample_timer_en ),
        .I1(\FSM_onehot_xadc_supplied_temperature.tempmon_state_reg_n_0_[0] ),
        .I2(\xadc_supplied_temperature.temperature ),
        .I3(\xadc_supplied_temperature.sample_timer_clr ),
        .I4(\xadc_supplied_temperature.rst_r2 ),
        .O(\xadc_supplied_temperature.sample_timer_en_i_1_n_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.sample_timer_en_reg 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\xadc_supplied_temperature.sample_timer_en_i_1_n_0 ),
        .Q(\xadc_supplied_temperature.sample_timer_en ),
        .R(1'b0));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.sample_timer_reg[0] 
       (.C(clk_ref_i),
        .CE(\xadc_supplied_temperature.sample_timer_en ),
        .D(p_0_in__1[0]),
        .Q(\xadc_supplied_temperature.sample_timer_reg [0]),
        .R(\xadc_supplied_temperature.sample_timer0 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.sample_timer_reg[10] 
       (.C(clk_ref_i),
        .CE(\xadc_supplied_temperature.sample_timer_en ),
        .D(p_0_in__1[10]),
        .Q(\xadc_supplied_temperature.sample_timer_reg [10]),
        .R(\xadc_supplied_temperature.sample_timer0 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.sample_timer_reg[1] 
       (.C(clk_ref_i),
        .CE(\xadc_supplied_temperature.sample_timer_en ),
        .D(p_0_in__1[1]),
        .Q(\xadc_supplied_temperature.sample_timer_reg [1]),
        .R(\xadc_supplied_temperature.sample_timer0 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.sample_timer_reg[2] 
       (.C(clk_ref_i),
        .CE(\xadc_supplied_temperature.sample_timer_en ),
        .D(p_0_in__1[2]),
        .Q(\xadc_supplied_temperature.sample_timer_reg [2]),
        .R(\xadc_supplied_temperature.sample_timer0 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.sample_timer_reg[3] 
       (.C(clk_ref_i),
        .CE(\xadc_supplied_temperature.sample_timer_en ),
        .D(p_0_in__1[3]),
        .Q(\xadc_supplied_temperature.sample_timer_reg [3]),
        .R(\xadc_supplied_temperature.sample_timer0 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.sample_timer_reg[4] 
       (.C(clk_ref_i),
        .CE(\xadc_supplied_temperature.sample_timer_en ),
        .D(p_0_in__1[4]),
        .Q(\xadc_supplied_temperature.sample_timer_reg [4]),
        .R(\xadc_supplied_temperature.sample_timer0 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.sample_timer_reg[5] 
       (.C(clk_ref_i),
        .CE(\xadc_supplied_temperature.sample_timer_en ),
        .D(p_0_in__1[5]),
        .Q(\xadc_supplied_temperature.sample_timer_reg [5]),
        .R(\xadc_supplied_temperature.sample_timer0 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.sample_timer_reg[6] 
       (.C(clk_ref_i),
        .CE(\xadc_supplied_temperature.sample_timer_en ),
        .D(p_0_in__1[6]),
        .Q(\xadc_supplied_temperature.sample_timer_reg [6]),
        .R(\xadc_supplied_temperature.sample_timer0 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.sample_timer_reg[7] 
       (.C(clk_ref_i),
        .CE(\xadc_supplied_temperature.sample_timer_en ),
        .D(p_0_in__1[7]),
        .Q(\xadc_supplied_temperature.sample_timer_reg [7]),
        .R(\xadc_supplied_temperature.sample_timer0 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.sample_timer_reg[8] 
       (.C(clk_ref_i),
        .CE(\xadc_supplied_temperature.sample_timer_en ),
        .D(p_0_in__1[8]),
        .Q(\xadc_supplied_temperature.sample_timer_reg [8]),
        .R(\xadc_supplied_temperature.sample_timer0 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.sample_timer_reg[9] 
       (.C(clk_ref_i),
        .CE(\xadc_supplied_temperature.sample_timer_en ),
        .D(p_0_in__1[9]),
        .Q(\xadc_supplied_temperature.sample_timer_reg [9]),
        .R(\xadc_supplied_temperature.sample_timer0 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.temperature_reg[0] 
       (.C(clk_ref_i),
        .CE(\xadc_supplied_temperature.temperature ),
        .D(\xadc_supplied_temperature.xadc_do_r [4]),
        .Q(device_temp_lcl[0]),
        .R(\xadc_supplied_temperature.rst_r2 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.temperature_reg[10] 
       (.C(clk_ref_i),
        .CE(\xadc_supplied_temperature.temperature ),
        .D(\xadc_supplied_temperature.xadc_do_r [14]),
        .Q(device_temp_lcl[10]),
        .R(\xadc_supplied_temperature.rst_r2 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.temperature_reg[11] 
       (.C(clk_ref_i),
        .CE(\xadc_supplied_temperature.temperature ),
        .D(\xadc_supplied_temperature.xadc_do_r [15]),
        .Q(device_temp_lcl[11]),
        .R(\xadc_supplied_temperature.rst_r2 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.temperature_reg[1] 
       (.C(clk_ref_i),
        .CE(\xadc_supplied_temperature.temperature ),
        .D(\xadc_supplied_temperature.xadc_do_r [5]),
        .Q(device_temp_lcl[1]),
        .R(\xadc_supplied_temperature.rst_r2 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.temperature_reg[2] 
       (.C(clk_ref_i),
        .CE(\xadc_supplied_temperature.temperature ),
        .D(\xadc_supplied_temperature.xadc_do_r [6]),
        .Q(device_temp_lcl[2]),
        .R(\xadc_supplied_temperature.rst_r2 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.temperature_reg[3] 
       (.C(clk_ref_i),
        .CE(\xadc_supplied_temperature.temperature ),
        .D(\xadc_supplied_temperature.xadc_do_r [7]),
        .Q(device_temp_lcl[3]),
        .R(\xadc_supplied_temperature.rst_r2 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.temperature_reg[4] 
       (.C(clk_ref_i),
        .CE(\xadc_supplied_temperature.temperature ),
        .D(\xadc_supplied_temperature.xadc_do_r [8]),
        .Q(device_temp_lcl[4]),
        .R(\xadc_supplied_temperature.rst_r2 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.temperature_reg[5] 
       (.C(clk_ref_i),
        .CE(\xadc_supplied_temperature.temperature ),
        .D(\xadc_supplied_temperature.xadc_do_r [9]),
        .Q(device_temp_lcl[5]),
        .R(\xadc_supplied_temperature.rst_r2 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.temperature_reg[6] 
       (.C(clk_ref_i),
        .CE(\xadc_supplied_temperature.temperature ),
        .D(\xadc_supplied_temperature.xadc_do_r [10]),
        .Q(device_temp_lcl[6]),
        .R(\xadc_supplied_temperature.rst_r2 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.temperature_reg[7] 
       (.C(clk_ref_i),
        .CE(\xadc_supplied_temperature.temperature ),
        .D(\xadc_supplied_temperature.xadc_do_r [11]),
        .Q(device_temp_lcl[7]),
        .R(\xadc_supplied_temperature.rst_r2 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.temperature_reg[8] 
       (.C(clk_ref_i),
        .CE(\xadc_supplied_temperature.temperature ),
        .D(\xadc_supplied_temperature.xadc_do_r [12]),
        .Q(device_temp_lcl[8]),
        .R(\xadc_supplied_temperature.rst_r2 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.temperature_reg[9] 
       (.C(clk_ref_i),
        .CE(\xadc_supplied_temperature.temperature ),
        .D(\xadc_supplied_temperature.xadc_do_r [13]),
        .Q(device_temp_lcl[9]),
        .R(\xadc_supplied_temperature.rst_r2 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.xadc_do_r_reg[10] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\xadc_supplied_temperature.xadc_do [10]),
        .Q(\xadc_supplied_temperature.xadc_do_r [10]),
        .R(\xadc_supplied_temperature.rst_r2 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.xadc_do_r_reg[11] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\xadc_supplied_temperature.xadc_do [11]),
        .Q(\xadc_supplied_temperature.xadc_do_r [11]),
        .R(\xadc_supplied_temperature.rst_r2 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.xadc_do_r_reg[12] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\xadc_supplied_temperature.xadc_do [12]),
        .Q(\xadc_supplied_temperature.xadc_do_r [12]),
        .R(\xadc_supplied_temperature.rst_r2 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.xadc_do_r_reg[13] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\xadc_supplied_temperature.xadc_do [13]),
        .Q(\xadc_supplied_temperature.xadc_do_r [13]),
        .R(\xadc_supplied_temperature.rst_r2 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.xadc_do_r_reg[14] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\xadc_supplied_temperature.xadc_do [14]),
        .Q(\xadc_supplied_temperature.xadc_do_r [14]),
        .R(\xadc_supplied_temperature.rst_r2 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.xadc_do_r_reg[15] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\xadc_supplied_temperature.xadc_do [15]),
        .Q(\xadc_supplied_temperature.xadc_do_r [15]),
        .R(\xadc_supplied_temperature.rst_r2 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.xadc_do_r_reg[4] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\xadc_supplied_temperature.xadc_do [4]),
        .Q(\xadc_supplied_temperature.xadc_do_r [4]),
        .R(\xadc_supplied_temperature.rst_r2 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.xadc_do_r_reg[5] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\xadc_supplied_temperature.xadc_do [5]),
        .Q(\xadc_supplied_temperature.xadc_do_r [5]),
        .R(\xadc_supplied_temperature.rst_r2 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.xadc_do_r_reg[6] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\xadc_supplied_temperature.xadc_do [6]),
        .Q(\xadc_supplied_temperature.xadc_do_r [6]),
        .R(\xadc_supplied_temperature.rst_r2 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.xadc_do_r_reg[7] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\xadc_supplied_temperature.xadc_do [7]),
        .Q(\xadc_supplied_temperature.xadc_do_r [7]),
        .R(\xadc_supplied_temperature.rst_r2 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.xadc_do_r_reg[8] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\xadc_supplied_temperature.xadc_do [8]),
        .Q(\xadc_supplied_temperature.xadc_do_r [8]),
        .R(\xadc_supplied_temperature.rst_r2 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.xadc_do_r_reg[9] 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\xadc_supplied_temperature.xadc_do [9]),
        .Q(\xadc_supplied_temperature.xadc_do_r [9]),
        .R(\xadc_supplied_temperature.rst_r2 ));
  FDRE #(
    .INIT(1'b0)) 
    \xadc_supplied_temperature.xadc_drdy_r_reg 
       (.C(clk_ref_i),
        .CE(1'b1),
        .D(\xadc_supplied_temperature.xadc_drdy ),
        .Q(\xadc_supplied_temperature.xadc_drdy_r ),
        .R(\xadc_supplied_temperature.rst_r2 ));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ui_cmd" *) 
module mig_mig_7series_v4_2_ui_cmd
   (E,
    \app_addr_r1_reg[23]_0 ,
    \app_addr_r1_reg[22]_0 ,
    \app_addr_r1_reg[23]_1 ,
    \app_addr_r1_reg[23]_2 ,
    \app_addr_r1_reg[23]_3 ,
    S,
    D,
    \req_row_r_lcl_reg[10] ,
    \req_bank_r_lcl_reg[0] ,
    \app_addr_r1_reg[24]_0 ,
    \app_addr_r1_reg[25]_0 ,
    \app_addr_r1_reg[26]_0 ,
    \req_bank_r_lcl_reg[0]_0 ,
    \req_bank_r_lcl_reg[2] ,
    \req_bank_r_lcl_reg[2]_0 ,
    \wr_req_counter.wr_req_cnt_r_reg[1] ,
    app_cmd_r2,
    \wr_req_counter.wr_req_cnt_r_reg[0] ,
    \read_data_indx.rd_data_upd_indx_r_reg ,
    wr_accepted,
    reset_reg,
    use_addr,
    app_en_r2_reg_0,
    \strict_mode.rd_data_buf_addr_r_lcl_reg[0] ,
    \strict_mode.rd_data_buf_addr_r_lcl_reg[1] ,
    cmd,
    \app_addr_r1_reg[9]_0 ,
    app_rdy_ns,
    \app_cmd_r2_reg[0]_0 ,
    row_hit_r_reg,
    req_bank_r,
    app_en,
    \app_addr_r1_reg[0]_0 ,
    \wr_req_counter.wr_req_cnt_r ,
    p_0_in,
    wr_data_buf_addr,
    \strict_mode.rd_data_buf_addr_r_lcl ,
    app_addr,
    app_cmd);
  output [0:0]E;
  output [0:0]\app_addr_r1_reg[23]_0 ;
  output \app_addr_r1_reg[22]_0 ;
  output [0:0]\app_addr_r1_reg[23]_1 ;
  output [0:0]\app_addr_r1_reg[23]_2 ;
  output [0:0]\app_addr_r1_reg[23]_3 ;
  output [2:0]S;
  output [12:0]D;
  output [0:0]\req_row_r_lcl_reg[10] ;
  output \req_bank_r_lcl_reg[0] ;
  output \app_addr_r1_reg[24]_0 ;
  output \app_addr_r1_reg[25]_0 ;
  output \app_addr_r1_reg[26]_0 ;
  output \req_bank_r_lcl_reg[0]_0 ;
  output \req_bank_r_lcl_reg[2] ;
  output \req_bank_r_lcl_reg[2]_0 ;
  output \wr_req_counter.wr_req_cnt_r_reg[1] ;
  output [1:0]app_cmd_r2;
  output \wr_req_counter.wr_req_cnt_r_reg[0] ;
  output \read_data_indx.rd_data_upd_indx_r_reg ;
  output wr_accepted;
  output [3:0]reset_reg;
  output use_addr;
  output app_en_r2_reg_0;
  output \strict_mode.rd_data_buf_addr_r_lcl_reg[0] ;
  output \strict_mode.rd_data_buf_addr_r_lcl_reg[1] ;
  output [1:0]cmd;
  output [9:0]\app_addr_r1_reg[9]_0 ;
  input app_rdy_ns;
  input \app_cmd_r2_reg[0]_0 ;
  input [19:0]row_hit_r_reg;
  input [11:0]req_bank_r;
  input app_en;
  input \app_addr_r1_reg[0]_0 ;
  input [1:0]\wr_req_counter.wr_req_cnt_r ;
  input [0:0]p_0_in;
  input [3:0]wr_data_buf_addr;
  input [3:0]\strict_mode.rd_data_buf_addr_r_lcl ;
  input [26:0]app_addr;
  input [1:0]app_cmd;

  wire [12:0]D;
  wire [0:0]E;
  wire [2:0]S;
  wire [26:0]app_addr;
  wire app_addr_r10;
  wire \app_addr_r1_reg[0]_0 ;
  wire \app_addr_r1_reg[22]_0 ;
  wire [0:0]\app_addr_r1_reg[23]_0 ;
  wire [0:0]\app_addr_r1_reg[23]_1 ;
  wire [0:0]\app_addr_r1_reg[23]_2 ;
  wire [0:0]\app_addr_r1_reg[23]_3 ;
  wire \app_addr_r1_reg[24]_0 ;
  wire \app_addr_r1_reg[25]_0 ;
  wire \app_addr_r1_reg[26]_0 ;
  wire [9:0]\app_addr_r1_reg[9]_0 ;
  wire \app_addr_r1_reg_n_0_[0] ;
  wire \app_addr_r1_reg_n_0_[10] ;
  wire \app_addr_r1_reg_n_0_[11] ;
  wire \app_addr_r1_reg_n_0_[12] ;
  wire \app_addr_r1_reg_n_0_[13] ;
  wire \app_addr_r1_reg_n_0_[14] ;
  wire \app_addr_r1_reg_n_0_[15] ;
  wire \app_addr_r1_reg_n_0_[16] ;
  wire \app_addr_r1_reg_n_0_[17] ;
  wire \app_addr_r1_reg_n_0_[18] ;
  wire \app_addr_r1_reg_n_0_[19] ;
  wire \app_addr_r1_reg_n_0_[1] ;
  wire \app_addr_r1_reg_n_0_[20] ;
  wire \app_addr_r1_reg_n_0_[21] ;
  wire \app_addr_r1_reg_n_0_[22] ;
  wire \app_addr_r1_reg_n_0_[23] ;
  wire \app_addr_r1_reg_n_0_[2] ;
  wire \app_addr_r1_reg_n_0_[3] ;
  wire \app_addr_r1_reg_n_0_[4] ;
  wire \app_addr_r1_reg_n_0_[5] ;
  wire \app_addr_r1_reg_n_0_[6] ;
  wire \app_addr_r1_reg_n_0_[7] ;
  wire \app_addr_r1_reg_n_0_[8] ;
  wire \app_addr_r1_reg_n_0_[9] ;
  wire \app_addr_r2_reg_n_0_[0] ;
  wire \app_addr_r2_reg_n_0_[10] ;
  wire \app_addr_r2_reg_n_0_[11] ;
  wire \app_addr_r2_reg_n_0_[12] ;
  wire \app_addr_r2_reg_n_0_[13] ;
  wire \app_addr_r2_reg_n_0_[14] ;
  wire \app_addr_r2_reg_n_0_[15] ;
  wire \app_addr_r2_reg_n_0_[16] ;
  wire \app_addr_r2_reg_n_0_[17] ;
  wire \app_addr_r2_reg_n_0_[18] ;
  wire \app_addr_r2_reg_n_0_[19] ;
  wire \app_addr_r2_reg_n_0_[1] ;
  wire \app_addr_r2_reg_n_0_[20] ;
  wire \app_addr_r2_reg_n_0_[21] ;
  wire \app_addr_r2_reg_n_0_[22] ;
  wire \app_addr_r2_reg_n_0_[23] ;
  wire \app_addr_r2_reg_n_0_[2] ;
  wire \app_addr_r2_reg_n_0_[3] ;
  wire \app_addr_r2_reg_n_0_[4] ;
  wire \app_addr_r2_reg_n_0_[5] ;
  wire \app_addr_r2_reg_n_0_[6] ;
  wire \app_addr_r2_reg_n_0_[7] ;
  wire \app_addr_r2_reg_n_0_[8] ;
  wire \app_addr_r2_reg_n_0_[9] ;
  wire [1:0]app_cmd;
  wire [1:0]app_cmd_r1;
  wire [1:0]app_cmd_r2;
  wire \app_cmd_r2_reg[0]_0 ;
  wire app_en;
  wire app_en_ns1;
  wire app_en_ns2;
  wire app_en_r1;
  wire app_en_r2;
  wire app_en_r2_reg_0;
  wire app_rdy_ns;
  wire [1:0]cmd;
  wire [0:0]p_0_in;
  wire [2:0]p_0_in_0;
  wire [2:0]p_1_in;
  wire \read_data_indx.rd_data_upd_indx_r_reg ;
  wire [11:0]req_bank_r;
  wire \req_bank_r_lcl_reg[0] ;
  wire \req_bank_r_lcl_reg[0]_0 ;
  wire \req_bank_r_lcl_reg[2] ;
  wire \req_bank_r_lcl_reg[2]_0 ;
  wire [0:0]\req_row_r_lcl_reg[10] ;
  wire [3:0]reset_reg;
  wire [19:0]row_hit_r_reg;
  wire [3:0]\strict_mode.rd_data_buf_addr_r_lcl ;
  wire \strict_mode.rd_data_buf_addr_r_lcl_reg[0] ;
  wire \strict_mode.rd_data_buf_addr_r_lcl_reg[1] ;
  wire use_addr;
  wire wr_accepted;
  wire [3:0]wr_data_buf_addr;
  wire [1:0]\wr_req_counter.wr_req_cnt_r ;
  wire \wr_req_counter.wr_req_cnt_r_reg[0] ;
  wire \wr_req_counter.wr_req_cnt_r_reg[1] ;
  wire write__0;

  LUT2 #(
    .INIT(4'h8)) 
    \app_addr_r1[26]_i_1 
       (.I0(E),
        .I1(app_en),
        .O(app_addr_r10));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[0] 
       (.C(\app_cmd_r2_reg[0]_0 ),
        .CE(app_addr_r10),
        .D(app_addr[0]),
        .Q(\app_addr_r1_reg_n_0_[0] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[10] 
       (.C(\app_cmd_r2_reg[0]_0 ),
        .CE(app_addr_r10),
        .D(app_addr[10]),
        .Q(\app_addr_r1_reg_n_0_[10] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[11] 
       (.C(\app_cmd_r2_reg[0]_0 ),
        .CE(app_addr_r10),
        .D(app_addr[11]),
        .Q(\app_addr_r1_reg_n_0_[11] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[12] 
       (.C(\app_cmd_r2_reg[0]_0 ),
        .CE(app_addr_r10),
        .D(app_addr[12]),
        .Q(\app_addr_r1_reg_n_0_[12] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[13] 
       (.C(\app_cmd_r2_reg[0]_0 ),
        .CE(app_addr_r10),
        .D(app_addr[13]),
        .Q(\app_addr_r1_reg_n_0_[13] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[14] 
       (.C(\app_cmd_r2_reg[0]_0 ),
        .CE(app_addr_r10),
        .D(app_addr[14]),
        .Q(\app_addr_r1_reg_n_0_[14] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[15] 
       (.C(\app_cmd_r2_reg[0]_0 ),
        .CE(app_addr_r10),
        .D(app_addr[15]),
        .Q(\app_addr_r1_reg_n_0_[15] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[16] 
       (.C(\app_cmd_r2_reg[0]_0 ),
        .CE(app_addr_r10),
        .D(app_addr[16]),
        .Q(\app_addr_r1_reg_n_0_[16] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[17] 
       (.C(\app_cmd_r2_reg[0]_0 ),
        .CE(app_addr_r10),
        .D(app_addr[17]),
        .Q(\app_addr_r1_reg_n_0_[17] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[18] 
       (.C(\app_cmd_r2_reg[0]_0 ),
        .CE(app_addr_r10),
        .D(app_addr[18]),
        .Q(\app_addr_r1_reg_n_0_[18] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[19] 
       (.C(\app_cmd_r2_reg[0]_0 ),
        .CE(app_addr_r10),
        .D(app_addr[19]),
        .Q(\app_addr_r1_reg_n_0_[19] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[1] 
       (.C(\app_cmd_r2_reg[0]_0 ),
        .CE(app_addr_r10),
        .D(app_addr[1]),
        .Q(\app_addr_r1_reg_n_0_[1] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[20] 
       (.C(\app_cmd_r2_reg[0]_0 ),
        .CE(app_addr_r10),
        .D(app_addr[20]),
        .Q(\app_addr_r1_reg_n_0_[20] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[21] 
       (.C(\app_cmd_r2_reg[0]_0 ),
        .CE(app_addr_r10),
        .D(app_addr[21]),
        .Q(\app_addr_r1_reg_n_0_[21] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[22] 
       (.C(\app_cmd_r2_reg[0]_0 ),
        .CE(app_addr_r10),
        .D(app_addr[22]),
        .Q(\app_addr_r1_reg_n_0_[22] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[23] 
       (.C(\app_cmd_r2_reg[0]_0 ),
        .CE(app_addr_r10),
        .D(app_addr[23]),
        .Q(\app_addr_r1_reg_n_0_[23] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[24] 
       (.C(\app_cmd_r2_reg[0]_0 ),
        .CE(app_addr_r10),
        .D(app_addr[24]),
        .Q(p_1_in[0]),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[25] 
       (.C(\app_cmd_r2_reg[0]_0 ),
        .CE(app_addr_r10),
        .D(app_addr[25]),
        .Q(p_1_in[1]),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[26] 
       (.C(\app_cmd_r2_reg[0]_0 ),
        .CE(app_addr_r10),
        .D(app_addr[26]),
        .Q(p_1_in[2]),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[2] 
       (.C(\app_cmd_r2_reg[0]_0 ),
        .CE(app_addr_r10),
        .D(app_addr[2]),
        .Q(\app_addr_r1_reg_n_0_[2] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[3] 
       (.C(\app_cmd_r2_reg[0]_0 ),
        .CE(app_addr_r10),
        .D(app_addr[3]),
        .Q(\app_addr_r1_reg_n_0_[3] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[4] 
       (.C(\app_cmd_r2_reg[0]_0 ),
        .CE(app_addr_r10),
        .D(app_addr[4]),
        .Q(\app_addr_r1_reg_n_0_[4] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[5] 
       (.C(\app_cmd_r2_reg[0]_0 ),
        .CE(app_addr_r10),
        .D(app_addr[5]),
        .Q(\app_addr_r1_reg_n_0_[5] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[6] 
       (.C(\app_cmd_r2_reg[0]_0 ),
        .CE(app_addr_r10),
        .D(app_addr[6]),
        .Q(\app_addr_r1_reg_n_0_[6] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[7] 
       (.C(\app_cmd_r2_reg[0]_0 ),
        .CE(app_addr_r10),
        .D(app_addr[7]),
        .Q(\app_addr_r1_reg_n_0_[7] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[8] 
       (.C(\app_cmd_r2_reg[0]_0 ),
        .CE(app_addr_r10),
        .D(app_addr[8]),
        .Q(\app_addr_r1_reg_n_0_[8] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r1_reg[9] 
       (.C(\app_cmd_r2_reg[0]_0 ),
        .CE(app_addr_r10),
        .D(app_addr[9]),
        .Q(\app_addr_r1_reg_n_0_[9] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[0] 
       (.C(\app_cmd_r2_reg[0]_0 ),
        .CE(E),
        .D(\app_addr_r1_reg_n_0_[0] ),
        .Q(\app_addr_r2_reg_n_0_[0] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[10] 
       (.C(\app_cmd_r2_reg[0]_0 ),
        .CE(E),
        .D(\app_addr_r1_reg_n_0_[10] ),
        .Q(\app_addr_r2_reg_n_0_[10] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[11] 
       (.C(\app_cmd_r2_reg[0]_0 ),
        .CE(E),
        .D(\app_addr_r1_reg_n_0_[11] ),
        .Q(\app_addr_r2_reg_n_0_[11] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[12] 
       (.C(\app_cmd_r2_reg[0]_0 ),
        .CE(E),
        .D(\app_addr_r1_reg_n_0_[12] ),
        .Q(\app_addr_r2_reg_n_0_[12] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[13] 
       (.C(\app_cmd_r2_reg[0]_0 ),
        .CE(E),
        .D(\app_addr_r1_reg_n_0_[13] ),
        .Q(\app_addr_r2_reg_n_0_[13] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[14] 
       (.C(\app_cmd_r2_reg[0]_0 ),
        .CE(E),
        .D(\app_addr_r1_reg_n_0_[14] ),
        .Q(\app_addr_r2_reg_n_0_[14] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[15] 
       (.C(\app_cmd_r2_reg[0]_0 ),
        .CE(E),
        .D(\app_addr_r1_reg_n_0_[15] ),
        .Q(\app_addr_r2_reg_n_0_[15] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[16] 
       (.C(\app_cmd_r2_reg[0]_0 ),
        .CE(E),
        .D(\app_addr_r1_reg_n_0_[16] ),
        .Q(\app_addr_r2_reg_n_0_[16] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[17] 
       (.C(\app_cmd_r2_reg[0]_0 ),
        .CE(E),
        .D(\app_addr_r1_reg_n_0_[17] ),
        .Q(\app_addr_r2_reg_n_0_[17] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[18] 
       (.C(\app_cmd_r2_reg[0]_0 ),
        .CE(E),
        .D(\app_addr_r1_reg_n_0_[18] ),
        .Q(\app_addr_r2_reg_n_0_[18] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[19] 
       (.C(\app_cmd_r2_reg[0]_0 ),
        .CE(E),
        .D(\app_addr_r1_reg_n_0_[19] ),
        .Q(\app_addr_r2_reg_n_0_[19] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[1] 
       (.C(\app_cmd_r2_reg[0]_0 ),
        .CE(E),
        .D(\app_addr_r1_reg_n_0_[1] ),
        .Q(\app_addr_r2_reg_n_0_[1] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[20] 
       (.C(\app_cmd_r2_reg[0]_0 ),
        .CE(E),
        .D(\app_addr_r1_reg_n_0_[20] ),
        .Q(\app_addr_r2_reg_n_0_[20] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[21] 
       (.C(\app_cmd_r2_reg[0]_0 ),
        .CE(E),
        .D(\app_addr_r1_reg_n_0_[21] ),
        .Q(\app_addr_r2_reg_n_0_[21] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[22] 
       (.C(\app_cmd_r2_reg[0]_0 ),
        .CE(E),
        .D(\app_addr_r1_reg_n_0_[22] ),
        .Q(\app_addr_r2_reg_n_0_[22] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[23] 
       (.C(\app_cmd_r2_reg[0]_0 ),
        .CE(E),
        .D(\app_addr_r1_reg_n_0_[23] ),
        .Q(\app_addr_r2_reg_n_0_[23] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[24] 
       (.C(\app_cmd_r2_reg[0]_0 ),
        .CE(E),
        .D(p_1_in[0]),
        .Q(p_0_in_0[0]),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[25] 
       (.C(\app_cmd_r2_reg[0]_0 ),
        .CE(E),
        .D(p_1_in[1]),
        .Q(p_0_in_0[1]),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[26] 
       (.C(\app_cmd_r2_reg[0]_0 ),
        .CE(E),
        .D(p_1_in[2]),
        .Q(p_0_in_0[2]),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[2] 
       (.C(\app_cmd_r2_reg[0]_0 ),
        .CE(E),
        .D(\app_addr_r1_reg_n_0_[2] ),
        .Q(\app_addr_r2_reg_n_0_[2] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[3] 
       (.C(\app_cmd_r2_reg[0]_0 ),
        .CE(E),
        .D(\app_addr_r1_reg_n_0_[3] ),
        .Q(\app_addr_r2_reg_n_0_[3] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[4] 
       (.C(\app_cmd_r2_reg[0]_0 ),
        .CE(E),
        .D(\app_addr_r1_reg_n_0_[4] ),
        .Q(\app_addr_r2_reg_n_0_[4] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[5] 
       (.C(\app_cmd_r2_reg[0]_0 ),
        .CE(E),
        .D(\app_addr_r1_reg_n_0_[5] ),
        .Q(\app_addr_r2_reg_n_0_[5] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[6] 
       (.C(\app_cmd_r2_reg[0]_0 ),
        .CE(E),
        .D(\app_addr_r1_reg_n_0_[6] ),
        .Q(\app_addr_r2_reg_n_0_[6] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[7] 
       (.C(\app_cmd_r2_reg[0]_0 ),
        .CE(E),
        .D(\app_addr_r1_reg_n_0_[7] ),
        .Q(\app_addr_r2_reg_n_0_[7] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[8] 
       (.C(\app_cmd_r2_reg[0]_0 ),
        .CE(E),
        .D(\app_addr_r1_reg_n_0_[8] ),
        .Q(\app_addr_r2_reg_n_0_[8] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE #(
    .INIT(1'b0)) 
    \app_addr_r2_reg[9] 
       (.C(\app_cmd_r2_reg[0]_0 ),
        .CE(E),
        .D(\app_addr_r1_reg_n_0_[9] ),
        .Q(\app_addr_r2_reg_n_0_[9] ),
        .R(\app_addr_r1_reg[0]_0 ));
  FDRE \app_cmd_r1_reg[0] 
       (.C(\app_cmd_r2_reg[0]_0 ),
        .CE(E),
        .D(app_cmd[0]),
        .Q(app_cmd_r1[0]),
        .R(1'b0));
  FDRE \app_cmd_r1_reg[1] 
       (.C(\app_cmd_r2_reg[0]_0 ),
        .CE(E),
        .D(app_cmd[1]),
        .Q(app_cmd_r1[1]),
        .R(1'b0));
  FDRE \app_cmd_r2_reg[0] 
       (.C(\app_cmd_r2_reg[0]_0 ),
        .CE(E),
        .D(app_cmd_r1[0]),
        .Q(app_cmd_r2[0]),
        .R(1'b0));
  FDRE \app_cmd_r2_reg[1] 
       (.C(\app_cmd_r2_reg[0]_0 ),
        .CE(E),
        .D(app_cmd_r1[1]),
        .Q(app_cmd_r2[1]),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair1216" *) 
  LUT4 #(
    .INIT(16'h2230)) 
    app_en_r1_i_1
       (.I0(app_en),
        .I1(\app_addr_r1_reg[0]_0 ),
        .I2(app_en_r1),
        .I3(E),
        .O(app_en_ns1));
  FDRE app_en_r1_reg
       (.C(\app_cmd_r2_reg[0]_0 ),
        .CE(1'b1),
        .D(app_en_ns1),
        .Q(app_en_r1),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair1216" *) 
  LUT4 #(
    .INIT(16'h2230)) 
    app_en_r2_i_1
       (.I0(app_en_r1),
        .I1(\app_addr_r1_reg[0]_0 ),
        .I2(app_en_r2),
        .I3(E),
        .O(app_en_ns2));
  FDRE app_en_r2_reg
       (.C(\app_cmd_r2_reg[0]_0 ),
        .CE(1'b1),
        .D(app_en_ns2),
        .Q(app_en_r2),
        .R(1'b0));
  LUT6 #(
    .INIT(64'hD55555D540000040)) 
    app_rdy_r_i_4
       (.I0(\wr_req_counter.wr_req_cnt_r [1]),
        .I1(E),
        .I2(app_en_r2),
        .I3(app_cmd_r2[0]),
        .I4(app_cmd_r2[1]),
        .I5(\wr_req_counter.wr_req_cnt_r [0]),
        .O(\wr_req_counter.wr_req_cnt_r_reg[1] ));
  (* syn_maxfan = "10" *) 
  FDRE #(
    .INIT(1'b0)) 
    app_rdy_r_reg
       (.C(\app_cmd_r2_reg[0]_0 ),
        .CE(1'b1),
        .D(app_rdy_ns),
        .Q(E),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair1214" *) 
  LUT4 #(
    .INIT(16'h8008)) 
    \data_buf_address_counter.data_buf_addr_cnt_r[3]_i_1 
       (.I0(E),
        .I1(app_en_r2),
        .I2(app_cmd_r2[0]),
        .I3(app_cmd_r2[1]),
        .O(wr_accepted));
  (* SOFT_HLUTNM = "soft_lutpair1215" *) 
  LUT2 #(
    .INIT(4'h8)) 
    i___42_i_1
       (.I0(app_en_r2),
        .I1(E),
        .O(use_addr));
  (* SOFT_HLUTNM = "soft_lutpair1224" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    i___59_i_1
       (.I0(app_cmd_r1[0]),
        .I1(E),
        .I2(app_cmd_r2[0]),
        .O(cmd[0]));
  LUT6 #(
    .INIT(64'h6FF6FFFFFFFF6FF6)) 
    rb_hit_busy_r_i_2
       (.I0(\app_addr_r1_reg[24]_0 ),
        .I1(req_bank_r[0]),
        .I2(req_bank_r[1]),
        .I3(\app_addr_r1_reg[25]_0 ),
        .I4(req_bank_r[2]),
        .I5(\app_addr_r1_reg[26]_0 ),
        .O(\req_bank_r_lcl_reg[0] ));
  LUT6 #(
    .INIT(64'h6FF6FFFFFFFF6FF6)) 
    rb_hit_busy_r_i_2__0
       (.I0(\app_addr_r1_reg[24]_0 ),
        .I1(req_bank_r[3]),
        .I2(req_bank_r[4]),
        .I3(\app_addr_r1_reg[25]_0 ),
        .I4(req_bank_r[5]),
        .I5(\app_addr_r1_reg[26]_0 ),
        .O(\req_bank_r_lcl_reg[0]_0 ));
  LUT6 #(
    .INIT(64'h6FF6FFFFFFFF6FF6)) 
    rb_hit_busy_r_i_2__1
       (.I0(\app_addr_r1_reg[26]_0 ),
        .I1(req_bank_r[8]),
        .I2(req_bank_r[7]),
        .I3(\app_addr_r1_reg[25]_0 ),
        .I4(req_bank_r[6]),
        .I5(\app_addr_r1_reg[24]_0 ),
        .O(\req_bank_r_lcl_reg[2] ));
  LUT6 #(
    .INIT(64'h6FF6FFFFFFFF6FF6)) 
    rb_hit_busy_r_i_2__2
       (.I0(\app_addr_r1_reg[26]_0 ),
        .I1(req_bank_r[11]),
        .I2(req_bank_r[10]),
        .I3(\app_addr_r1_reg[25]_0 ),
        .I4(req_bank_r[9]),
        .I5(\app_addr_r1_reg[24]_0 ),
        .O(\req_bank_r_lcl_reg[2]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1225" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_bank_r_lcl[0]_i_1 
       (.I0(p_1_in[0]),
        .I1(E),
        .I2(p_0_in_0[0]),
        .O(\app_addr_r1_reg[24]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1224" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_bank_r_lcl[1]_i_1 
       (.I0(p_1_in[1]),
        .I1(E),
        .I2(p_0_in_0[1]),
        .O(\app_addr_r1_reg[25]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1223" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_bank_r_lcl[2]_i_1 
       (.I0(p_1_in[2]),
        .I1(E),
        .I2(p_0_in_0[2]),
        .O(\app_addr_r1_reg[26]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1226" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_col_r[0]_i_1 
       (.I0(\app_addr_r1_reg_n_0_[0] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[0] ),
        .O(\app_addr_r1_reg[9]_0 [0]));
  (* SOFT_HLUTNM = "soft_lutpair1230" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_col_r[1]_i_1 
       (.I0(\app_addr_r1_reg_n_0_[1] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[1] ),
        .O(\app_addr_r1_reg[9]_0 [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \req_col_r[2]_i_1 
       (.I0(\app_addr_r1_reg_n_0_[2] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[2] ),
        .O(\app_addr_r1_reg[9]_0 [2]));
  (* SOFT_HLUTNM = "soft_lutpair1230" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_col_r[3]_i_1 
       (.I0(\app_addr_r1_reg_n_0_[3] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[3] ),
        .O(\app_addr_r1_reg[9]_0 [3]));
  (* SOFT_HLUTNM = "soft_lutpair1229" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_col_r[4]_i_1 
       (.I0(\app_addr_r1_reg_n_0_[4] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[4] ),
        .O(\app_addr_r1_reg[9]_0 [4]));
  (* SOFT_HLUTNM = "soft_lutpair1227" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_col_r[5]_i_1 
       (.I0(\app_addr_r1_reg_n_0_[5] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[5] ),
        .O(\app_addr_r1_reg[9]_0 [5]));
  (* SOFT_HLUTNM = "soft_lutpair1229" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_col_r[6]_i_1 
       (.I0(\app_addr_r1_reg_n_0_[6] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[6] ),
        .O(\app_addr_r1_reg[9]_0 [6]));
  (* SOFT_HLUTNM = "soft_lutpair1228" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_col_r[7]_i_1 
       (.I0(\app_addr_r1_reg_n_0_[7] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[7] ),
        .O(\app_addr_r1_reg[9]_0 [7]));
  (* SOFT_HLUTNM = "soft_lutpair1228" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_col_r[8]_i_1 
       (.I0(\app_addr_r1_reg_n_0_[8] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[8] ),
        .O(\app_addr_r1_reg[9]_0 [8]));
  (* SOFT_HLUTNM = "soft_lutpair1227" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_col_r[9]_i_1 
       (.I0(\app_addr_r1_reg_n_0_[9] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[9] ),
        .O(\app_addr_r1_reg[9]_0 [9]));
  LUT6 #(
    .INIT(64'h82B282BE828E8282)) 
    \req_data_buf_addr_r[0]_i_1 
       (.I0(wr_data_buf_addr[0]),
        .I1(app_cmd_r2[0]),
        .I2(app_cmd_r2[1]),
        .I3(\app_addr_r1_reg[0]_0 ),
        .I4(use_addr),
        .I5(\strict_mode.rd_data_buf_addr_r_lcl [0]),
        .O(reset_reg[0]));
  (* SOFT_HLUTNM = "soft_lutpair1213" *) 
  LUT5 #(
    .INIT(32'h82BE8282)) 
    \req_data_buf_addr_r[1]_i_1 
       (.I0(wr_data_buf_addr[1]),
        .I1(app_cmd_r2[0]),
        .I2(app_cmd_r2[1]),
        .I3(\app_addr_r1_reg[0]_0 ),
        .I4(\strict_mode.rd_data_buf_addr_r_lcl_reg[0] ),
        .O(reset_reg[1]));
  LUT6 #(
    .INIT(64'h828282BE82BE8282)) 
    \req_data_buf_addr_r[2]_i_1 
       (.I0(wr_data_buf_addr[2]),
        .I1(app_cmd_r2[0]),
        .I2(app_cmd_r2[1]),
        .I3(\app_addr_r1_reg[0]_0 ),
        .I4(\strict_mode.rd_data_buf_addr_r_lcl [2]),
        .I5(\strict_mode.rd_data_buf_addr_r_lcl_reg[1] ),
        .O(reset_reg[2]));
  LUT6 #(
    .INIT(64'h888B8B8B8B888888)) 
    \req_data_buf_addr_r[3]_i_1 
       (.I0(wr_data_buf_addr[3]),
        .I1(write__0),
        .I2(\app_addr_r1_reg[0]_0 ),
        .I3(\strict_mode.rd_data_buf_addr_r_lcl_reg[1] ),
        .I4(\strict_mode.rd_data_buf_addr_r_lcl [2]),
        .I5(\strict_mode.rd_data_buf_addr_r_lcl [3]),
        .O(reset_reg[3]));
  (* SOFT_HLUTNM = "soft_lutpair1213" *) 
  LUT2 #(
    .INIT(4'h9)) 
    \req_data_buf_addr_r[3]_i_2 
       (.I0(app_cmd_r2[1]),
        .I1(app_cmd_r2[0]),
        .O(write__0));
  LUT6 #(
    .INIT(64'h0800000000000000)) 
    \req_data_buf_addr_r[3]_i_3 
       (.I0(\strict_mode.rd_data_buf_addr_r_lcl [1]),
        .I1(\strict_mode.rd_data_buf_addr_r_lcl [0]),
        .I2(app_cmd_r2[1]),
        .I3(app_cmd_r2[0]),
        .I4(E),
        .I5(app_en_r2),
        .O(\strict_mode.rd_data_buf_addr_r_lcl_reg[1] ));
  (* SOFT_HLUTNM = "soft_lutpair1222" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_row_r_lcl[0]_i_1 
       (.I0(\app_addr_r1_reg_n_0_[10] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[10] ),
        .O(D[0]));
  (* SOFT_HLUTNM = "soft_lutpair1220" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_row_r_lcl[10]_i_1 
       (.I0(\app_addr_r1_reg_n_0_[20] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[20] ),
        .O(D[10]));
  (* SOFT_HLUTNM = "soft_lutpair1221" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_row_r_lcl[11]_i_1 
       (.I0(\app_addr_r1_reg_n_0_[21] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[21] ),
        .O(D[11]));
  (* SOFT_HLUTNM = "soft_lutpair1218" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_row_r_lcl[12]_i_1 
       (.I0(\app_addr_r1_reg_n_0_[22] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[22] ),
        .O(\app_addr_r1_reg[22]_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1226" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_row_r_lcl[13]_i_1 
       (.I0(\app_addr_r1_reg_n_0_[23] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[23] ),
        .O(D[12]));
  (* SOFT_HLUTNM = "soft_lutpair1221" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_row_r_lcl[1]_i_1 
       (.I0(\app_addr_r1_reg_n_0_[11] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[11] ),
        .O(D[1]));
  (* SOFT_HLUTNM = "soft_lutpair1220" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_row_r_lcl[2]_i_1 
       (.I0(\app_addr_r1_reg_n_0_[12] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[12] ),
        .O(D[2]));
  (* SOFT_HLUTNM = "soft_lutpair1219" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_row_r_lcl[3]_i_1 
       (.I0(\app_addr_r1_reg_n_0_[13] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[13] ),
        .O(D[3]));
  (* SOFT_HLUTNM = "soft_lutpair1218" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_row_r_lcl[4]_i_1 
       (.I0(\app_addr_r1_reg_n_0_[14] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[14] ),
        .O(D[4]));
  (* SOFT_HLUTNM = "soft_lutpair1217" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_row_r_lcl[5]_i_1 
       (.I0(\app_addr_r1_reg_n_0_[15] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[15] ),
        .O(D[5]));
  (* SOFT_HLUTNM = "soft_lutpair1223" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_row_r_lcl[6]_i_1 
       (.I0(\app_addr_r1_reg_n_0_[16] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[16] ),
        .O(D[6]));
  (* SOFT_HLUTNM = "soft_lutpair1222" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_row_r_lcl[7]_i_1 
       (.I0(\app_addr_r1_reg_n_0_[17] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[17] ),
        .O(D[7]));
  (* SOFT_HLUTNM = "soft_lutpair1217" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_row_r_lcl[8]_i_1 
       (.I0(\app_addr_r1_reg_n_0_[18] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[18] ),
        .O(D[8]));
  (* SOFT_HLUTNM = "soft_lutpair1219" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    \req_row_r_lcl[9]_i_1 
       (.I0(\app_addr_r1_reg_n_0_[19] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[19] ),
        .O(D[9]));
  (* SOFT_HLUTNM = "soft_lutpair1225" *) 
  LUT3 #(
    .INIT(8'hB8)) 
    req_wr_r_lcl_i_2
       (.I0(app_cmd_r1[1]),
        .I1(E),
        .I2(app_cmd_r2[1]),
        .O(cmd[1]));
  LUT6 #(
    .INIT(64'hB80000B847000047)) 
    row_hit_ns_carry__0_i_1
       (.I0(\app_addr_r1_reg_n_0_[23] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[23] ),
        .I3(\app_addr_r1_reg[22]_0 ),
        .I4(row_hit_r_reg[9]),
        .I5(row_hit_r_reg[10]),
        .O(\app_addr_r1_reg[23]_0 ));
  LUT6 #(
    .INIT(64'hB80000B847000047)) 
    row_hit_ns_carry__0_i_1__0
       (.I0(\app_addr_r1_reg_n_0_[23] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[23] ),
        .I3(\app_addr_r1_reg[22]_0 ),
        .I4(row_hit_r_reg[14]),
        .I5(row_hit_r_reg[15]),
        .O(\app_addr_r1_reg[23]_1 ));
  LUT6 #(
    .INIT(64'hB80000B847000047)) 
    row_hit_ns_carry__0_i_1__1
       (.I0(\app_addr_r1_reg_n_0_[23] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[23] ),
        .I3(\app_addr_r1_reg[22]_0 ),
        .I4(row_hit_r_reg[16]),
        .I5(row_hit_r_reg[17]),
        .O(\app_addr_r1_reg[23]_2 ));
  LUT6 #(
    .INIT(64'hB80000B847000047)) 
    row_hit_ns_carry__0_i_1__2
       (.I0(\app_addr_r1_reg_n_0_[23] ),
        .I1(E),
        .I2(\app_addr_r2_reg_n_0_[23] ),
        .I3(\app_addr_r1_reg[22]_0 ),
        .I4(row_hit_r_reg[18]),
        .I5(row_hit_r_reg[19]),
        .O(\app_addr_r1_reg[23]_3 ));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    row_hit_ns_carry_i_1__0
       (.I0(D[10]),
        .I1(row_hit_r_reg[12]),
        .I2(row_hit_r_reg[13]),
        .I3(D[11]),
        .I4(row_hit_r_reg[11]),
        .I5(D[9]),
        .O(\req_row_r_lcl_reg[10] ));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    row_hit_ns_carry_i_2
       (.I0(D[7]),
        .I1(row_hit_r_reg[7]),
        .I2(row_hit_r_reg[8]),
        .I3(D[8]),
        .I4(row_hit_r_reg[6]),
        .I5(D[6]),
        .O(S[2]));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    row_hit_ns_carry_i_3
       (.I0(D[4]),
        .I1(row_hit_r_reg[4]),
        .I2(row_hit_r_reg[5]),
        .I3(D[5]),
        .I4(row_hit_r_reg[3]),
        .I5(D[3]),
        .O(S[1]));
  LUT6 #(
    .INIT(64'h9009000000009009)) 
    row_hit_ns_carry_i_4
       (.I0(D[1]),
        .I1(row_hit_r_reg[1]),
        .I2(row_hit_r_reg[2]),
        .I3(D[2]),
        .I4(row_hit_r_reg[0]),
        .I5(D[0]),
        .O(S[0]));
  (* SOFT_HLUTNM = "soft_lutpair1215" *) 
  LUT5 #(
    .INIT(32'hFF7F0080)) 
    \strict_mode.rd_data_buf_addr_r_lcl[0]_i_1 
       (.I0(app_en_r2),
        .I1(E),
        .I2(app_cmd_r2[0]),
        .I3(app_cmd_r2[1]),
        .I4(\strict_mode.rd_data_buf_addr_r_lcl [0]),
        .O(app_en_r2_reg_0));
  LUT6 #(
    .INIT(64'hDFFFFFFF20000000)) 
    \strict_mode.rd_data_buf_addr_r_lcl[1]_i_1 
       (.I0(\strict_mode.rd_data_buf_addr_r_lcl [0]),
        .I1(app_cmd_r2[1]),
        .I2(app_cmd_r2[0]),
        .I3(E),
        .I4(app_en_r2),
        .I5(\strict_mode.rd_data_buf_addr_r_lcl [1]),
        .O(\strict_mode.rd_data_buf_addr_r_lcl_reg[0] ));
  LUT6 #(
    .INIT(64'h9669666666666666)) 
    \wr_req_counter.wr_req_cnt_r[0]_i_1 
       (.I0(\wr_req_counter.wr_req_cnt_r [0]),
        .I1(p_0_in),
        .I2(app_cmd_r2[1]),
        .I3(app_cmd_r2[0]),
        .I4(app_en_r2),
        .I5(E),
        .O(\wr_req_counter.wr_req_cnt_r_reg[0] ));
  (* SOFT_HLUTNM = "soft_lutpair1214" *) 
  LUT5 #(
    .INIT(32'h69AAAAAA)) 
    \wr_req_counter.wr_req_cnt_r[4]_i_3 
       (.I0(p_0_in),
        .I1(app_cmd_r2[1]),
        .I2(app_cmd_r2[0]),
        .I3(app_en_r2),
        .I4(E),
        .O(\read_data_indx.rd_data_upd_indx_r_reg ));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ui_rd_data" *) 
module mig_mig_7series_v4_2_ui_rd_data
   (\rd_buf_indx.ram_init_done_r_lcl_reg_0 ,
    \strict_mode.rd_data_buf_addr_r_lcl ,
    ADDRD,
    \pointer_ram.pointer_wr_data ,
    \strict_mode.rd_data_buf_addr_r_lcl_reg[0]_0 ,
    use_addr,
    app_cmd_r2,
    \strict_mode.rd_data_buf_addr_r_lcl_reg[3]_0 ,
    \strict_mode.rd_data_buf_addr_r_lcl_reg[0]_1 ,
    Q,
    wr_data_addr,
    \strict_mode.rd_data_buf_addr_r_lcl_reg[1]_0 ,
    \strict_mode.rd_data_buf_addr_r_lcl_reg[0]_2 );
  output \rd_buf_indx.ram_init_done_r_lcl_reg_0 ;
  output [3:0]\strict_mode.rd_data_buf_addr_r_lcl ;
  output [3:0]ADDRD;
  output [3:0]\pointer_ram.pointer_wr_data ;
  input \strict_mode.rd_data_buf_addr_r_lcl_reg[0]_0 ;
  input use_addr;
  input [1:0]app_cmd_r2;
  input \strict_mode.rd_data_buf_addr_r_lcl_reg[3]_0 ;
  input \strict_mode.rd_data_buf_addr_r_lcl_reg[0]_1 ;
  input [3:0]Q;
  input [3:0]wr_data_addr;
  input \strict_mode.rd_data_buf_addr_r_lcl_reg[1]_0 ;
  input \strict_mode.rd_data_buf_addr_r_lcl_reg[0]_2 ;

  wire [3:0]ADDRD;
  wire [3:0]Q;
  wire [1:0]app_cmd_r2;
  wire [4:0]p_0_in__2;
  wire [3:0]\pointer_ram.pointer_wr_data ;
  wire [3:0]ram_init_addr;
  wire \rd_buf_indx.ram_init_done_ns ;
  wire \rd_buf_indx.ram_init_done_r_lcl_i_2_n_0 ;
  wire \rd_buf_indx.ram_init_done_r_lcl_reg_0 ;
  wire \rd_buf_indx.rd_buf_indx_r[4]_i_1_n_0 ;
  wire [4:4]\rd_buf_indx.rd_buf_indx_r_reg ;
  wire [3:0]\strict_mode.rd_data_buf_addr_r_lcl ;
  wire \strict_mode.rd_data_buf_addr_r_lcl[2]_i_1_n_0 ;
  wire \strict_mode.rd_data_buf_addr_r_lcl[3]_i_1_n_0 ;
  wire \strict_mode.rd_data_buf_addr_r_lcl_reg[0]_0 ;
  wire \strict_mode.rd_data_buf_addr_r_lcl_reg[0]_1 ;
  wire \strict_mode.rd_data_buf_addr_r_lcl_reg[0]_2 ;
  wire \strict_mode.rd_data_buf_addr_r_lcl_reg[1]_0 ;
  wire \strict_mode.rd_data_buf_addr_r_lcl_reg[3]_0 ;
  wire use_addr;
  wire [3:0]wr_data_addr;

  LUT3 #(
    .INIT(8'hB8)) 
    \pointer_ram.rams[0].RAM32M0_i_2 
       (.I0(wr_data_addr[1]),
        .I1(\rd_buf_indx.ram_init_done_r_lcl_reg_0 ),
        .I2(ram_init_addr[1]),
        .O(\pointer_ram.pointer_wr_data [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \pointer_ram.rams[0].RAM32M0_i_3 
       (.I0(wr_data_addr[0]),
        .I1(\rd_buf_indx.ram_init_done_r_lcl_reg_0 ),
        .I2(ram_init_addr[0]),
        .O(\pointer_ram.pointer_wr_data [0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \pointer_ram.rams[0].RAM32M0_i_4 
       (.I0(Q[3]),
        .I1(\rd_buf_indx.ram_init_done_r_lcl_reg_0 ),
        .I2(ram_init_addr[3]),
        .O(ADDRD[3]));
  LUT3 #(
    .INIT(8'hB8)) 
    \pointer_ram.rams[0].RAM32M0_i_5 
       (.I0(Q[2]),
        .I1(\rd_buf_indx.ram_init_done_r_lcl_reg_0 ),
        .I2(ram_init_addr[2]),
        .O(ADDRD[2]));
  LUT3 #(
    .INIT(8'hB8)) 
    \pointer_ram.rams[0].RAM32M0_i_6 
       (.I0(Q[1]),
        .I1(\rd_buf_indx.ram_init_done_r_lcl_reg_0 ),
        .I2(ram_init_addr[1]),
        .O(ADDRD[1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \pointer_ram.rams[0].RAM32M0_i_7 
       (.I0(Q[0]),
        .I1(\rd_buf_indx.ram_init_done_r_lcl_reg_0 ),
        .I2(ram_init_addr[0]),
        .O(ADDRD[0]));
  LUT3 #(
    .INIT(8'hB8)) 
    \pointer_ram.rams[1].RAM32M0_i_1 
       (.I0(wr_data_addr[3]),
        .I1(\rd_buf_indx.ram_init_done_r_lcl_reg_0 ),
        .I2(ram_init_addr[3]),
        .O(\pointer_ram.pointer_wr_data [3]));
  LUT3 #(
    .INIT(8'hB8)) 
    \pointer_ram.rams[1].RAM32M0_i_2 
       (.I0(wr_data_addr[2]),
        .I1(\rd_buf_indx.ram_init_done_r_lcl_reg_0 ),
        .I2(ram_init_addr[2]),
        .O(\pointer_ram.pointer_wr_data [2]));
  LUT4 #(
    .INIT(16'h0F04)) 
    \rd_buf_indx.ram_init_done_r_lcl_i_1 
       (.I0(\rd_buf_indx.ram_init_done_r_lcl_i_2_n_0 ),
        .I1(\rd_buf_indx.rd_buf_indx_r_reg ),
        .I2(\strict_mode.rd_data_buf_addr_r_lcl_reg[0]_1 ),
        .I3(\rd_buf_indx.ram_init_done_r_lcl_reg_0 ),
        .O(\rd_buf_indx.ram_init_done_ns ));
  (* SOFT_HLUTNM = "soft_lutpair1231" *) 
  LUT4 #(
    .INIT(16'h7FFF)) 
    \rd_buf_indx.ram_init_done_r_lcl_i_2 
       (.I0(ram_init_addr[2]),
        .I1(ram_init_addr[1]),
        .I2(ram_init_addr[0]),
        .I3(ram_init_addr[3]),
        .O(\rd_buf_indx.ram_init_done_r_lcl_i_2_n_0 ));
  (* syn_maxfan = "10" *) 
  FDRE \rd_buf_indx.ram_init_done_r_lcl_reg 
       (.C(\strict_mode.rd_data_buf_addr_r_lcl_reg[0]_0 ),
        .CE(1'b1),
        .D(\rd_buf_indx.ram_init_done_ns ),
        .Q(\rd_buf_indx.ram_init_done_r_lcl_reg_0 ),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair1233" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \rd_buf_indx.rd_buf_indx_r[0]_i_1 
       (.I0(ram_init_addr[0]),
        .O(p_0_in__2[0]));
  (* SOFT_HLUTNM = "soft_lutpair1233" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \rd_buf_indx.rd_buf_indx_r[1]_i_1 
       (.I0(ram_init_addr[0]),
        .I1(ram_init_addr[1]),
        .O(p_0_in__2[1]));
  (* SOFT_HLUTNM = "soft_lutpair1232" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \rd_buf_indx.rd_buf_indx_r[2]_i_1 
       (.I0(ram_init_addr[0]),
        .I1(ram_init_addr[1]),
        .I2(ram_init_addr[2]),
        .O(p_0_in__2[2]));
  (* SOFT_HLUTNM = "soft_lutpair1232" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \rd_buf_indx.rd_buf_indx_r[3]_i_1 
       (.I0(ram_init_addr[2]),
        .I1(ram_init_addr[1]),
        .I2(ram_init_addr[0]),
        .I3(ram_init_addr[3]),
        .O(p_0_in__2[3]));
  LUT1 #(
    .INIT(2'h1)) 
    \rd_buf_indx.rd_buf_indx_r[4]_i_1 
       (.I0(\rd_buf_indx.ram_init_done_r_lcl_reg_0 ),
        .O(\rd_buf_indx.rd_buf_indx_r[4]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1231" *) 
  LUT5 #(
    .INIT(32'h7FFF8000)) 
    \rd_buf_indx.rd_buf_indx_r[4]_i_2 
       (.I0(ram_init_addr[3]),
        .I1(ram_init_addr[0]),
        .I2(ram_init_addr[1]),
        .I3(ram_init_addr[2]),
        .I4(\rd_buf_indx.rd_buf_indx_r_reg ),
        .O(p_0_in__2[4]));
  FDRE \rd_buf_indx.rd_buf_indx_r_reg[0] 
       (.C(\strict_mode.rd_data_buf_addr_r_lcl_reg[0]_0 ),
        .CE(\rd_buf_indx.rd_buf_indx_r[4]_i_1_n_0 ),
        .D(p_0_in__2[0]),
        .Q(ram_init_addr[0]),
        .R(\strict_mode.rd_data_buf_addr_r_lcl_reg[0]_1 ));
  FDRE \rd_buf_indx.rd_buf_indx_r_reg[1] 
       (.C(\strict_mode.rd_data_buf_addr_r_lcl_reg[0]_0 ),
        .CE(\rd_buf_indx.rd_buf_indx_r[4]_i_1_n_0 ),
        .D(p_0_in__2[1]),
        .Q(ram_init_addr[1]),
        .R(\strict_mode.rd_data_buf_addr_r_lcl_reg[0]_1 ));
  FDRE \rd_buf_indx.rd_buf_indx_r_reg[2] 
       (.C(\strict_mode.rd_data_buf_addr_r_lcl_reg[0]_0 ),
        .CE(\rd_buf_indx.rd_buf_indx_r[4]_i_1_n_0 ),
        .D(p_0_in__2[2]),
        .Q(ram_init_addr[2]),
        .R(\strict_mode.rd_data_buf_addr_r_lcl_reg[0]_1 ));
  FDRE \rd_buf_indx.rd_buf_indx_r_reg[3] 
       (.C(\strict_mode.rd_data_buf_addr_r_lcl_reg[0]_0 ),
        .CE(\rd_buf_indx.rd_buf_indx_r[4]_i_1_n_0 ),
        .D(p_0_in__2[3]),
        .Q(ram_init_addr[3]),
        .R(\strict_mode.rd_data_buf_addr_r_lcl_reg[0]_1 ));
  FDRE \rd_buf_indx.rd_buf_indx_r_reg[4] 
       (.C(\strict_mode.rd_data_buf_addr_r_lcl_reg[0]_0 ),
        .CE(\rd_buf_indx.rd_buf_indx_r[4]_i_1_n_0 ),
        .D(p_0_in__2[4]),
        .Q(\rd_buf_indx.rd_buf_indx_r_reg ),
        .R(\strict_mode.rd_data_buf_addr_r_lcl_reg[0]_1 ));
  LUT6 #(
    .INIT(64'hAA6AAAAAAAAAAAAA)) 
    \strict_mode.rd_data_buf_addr_r_lcl[2]_i_1 
       (.I0(\strict_mode.rd_data_buf_addr_r_lcl [2]),
        .I1(use_addr),
        .I2(app_cmd_r2[0]),
        .I3(app_cmd_r2[1]),
        .I4(\strict_mode.rd_data_buf_addr_r_lcl [0]),
        .I5(\strict_mode.rd_data_buf_addr_r_lcl [1]),
        .O(\strict_mode.rd_data_buf_addr_r_lcl[2]_i_1_n_0 ));
  LUT3 #(
    .INIT(8'h78)) 
    \strict_mode.rd_data_buf_addr_r_lcl[3]_i_1 
       (.I0(\strict_mode.rd_data_buf_addr_r_lcl_reg[3]_0 ),
        .I1(\strict_mode.rd_data_buf_addr_r_lcl [2]),
        .I2(\strict_mode.rd_data_buf_addr_r_lcl [3]),
        .O(\strict_mode.rd_data_buf_addr_r_lcl[3]_i_1_n_0 ));
  FDRE \strict_mode.rd_data_buf_addr_r_lcl_reg[0] 
       (.C(\strict_mode.rd_data_buf_addr_r_lcl_reg[0]_0 ),
        .CE(1'b1),
        .D(\strict_mode.rd_data_buf_addr_r_lcl_reg[0]_2 ),
        .Q(\strict_mode.rd_data_buf_addr_r_lcl [0]),
        .R(\strict_mode.rd_data_buf_addr_r_lcl_reg[0]_1 ));
  FDRE \strict_mode.rd_data_buf_addr_r_lcl_reg[1] 
       (.C(\strict_mode.rd_data_buf_addr_r_lcl_reg[0]_0 ),
        .CE(1'b1),
        .D(\strict_mode.rd_data_buf_addr_r_lcl_reg[1]_0 ),
        .Q(\strict_mode.rd_data_buf_addr_r_lcl [1]),
        .R(\strict_mode.rd_data_buf_addr_r_lcl_reg[0]_1 ));
  FDRE \strict_mode.rd_data_buf_addr_r_lcl_reg[2] 
       (.C(\strict_mode.rd_data_buf_addr_r_lcl_reg[0]_0 ),
        .CE(1'b1),
        .D(\strict_mode.rd_data_buf_addr_r_lcl[2]_i_1_n_0 ),
        .Q(\strict_mode.rd_data_buf_addr_r_lcl [2]),
        .R(\strict_mode.rd_data_buf_addr_r_lcl_reg[0]_1 ));
  FDRE \strict_mode.rd_data_buf_addr_r_lcl_reg[3] 
       (.C(\strict_mode.rd_data_buf_addr_r_lcl_reg[0]_0 ),
        .CE(1'b1),
        .D(\strict_mode.rd_data_buf_addr_r_lcl[3]_i_1_n_0 ),
        .Q(\strict_mode.rd_data_buf_addr_r_lcl [3]),
        .R(\strict_mode.rd_data_buf_addr_r_lcl_reg[0]_1 ));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ui_top" *) 
module mig_mig_7series_v4_2_ui_top
   (app_rdy_r_reg,
    ram_init_done_r,
    app_wdf_rdy,
    \app_addr_r1_reg[23] ,
    D,
    \app_addr_r1_reg[23]_0 ,
    \app_addr_r1_reg[23]_1 ,
    \app_addr_r1_reg[23]_2 ,
    S,
    \req_row_r_lcl_reg[10] ,
    \req_bank_r_lcl_reg[0] ,
    \app_addr_r1_reg[26] ,
    \req_bank_r_lcl_reg[0]_0 ,
    \req_bank_r_lcl_reg[2] ,
    \req_bank_r_lcl_reg[2]_0 ,
    reset_reg,
    use_addr,
    cmd,
    \app_addr_r1_reg[9] ,
    Q,
    \wr_req_counter.wr_req_cnt_r_reg[0] ,
    \pointer_ram.pointer_we ,
    wr_data_addr,
    E,
    row_hit_r_reg,
    req_bank_r,
    app_en,
    \wr_req_counter.wr_req_cnt_r_reg[0]_0 ,
    accept_ns,
    app_wdf_wren,
    app_wdf_end,
    app_wdf_mask,
    app_wdf_data,
    app_addr,
    app_cmd);
  output app_rdy_r_reg;
  output ram_init_done_r;
  output app_wdf_rdy;
  output [0:0]\app_addr_r1_reg[23] ;
  output [13:0]D;
  output [0:0]\app_addr_r1_reg[23]_0 ;
  output [0:0]\app_addr_r1_reg[23]_1 ;
  output [0:0]\app_addr_r1_reg[23]_2 ;
  output [2:0]S;
  output [0:0]\req_row_r_lcl_reg[10] ;
  output \req_bank_r_lcl_reg[0] ;
  output [2:0]\app_addr_r1_reg[26] ;
  output \req_bank_r_lcl_reg[0]_0 ;
  output \req_bank_r_lcl_reg[2] ;
  output \req_bank_r_lcl_reg[2]_0 ;
  output [3:0]reset_reg;
  output use_addr;
  output [1:0]cmd;
  output [9:0]\app_addr_r1_reg[9] ;
  output [575:0]Q;
  input \wr_req_counter.wr_req_cnt_r_reg[0] ;
  input \pointer_ram.pointer_we ;
  input [3:0]wr_data_addr;
  input [0:0]E;
  input [19:0]row_hit_r_reg;
  input [11:0]req_bank_r;
  input app_en;
  input \wr_req_counter.wr_req_cnt_r_reg[0]_0 ;
  input accept_ns;
  input app_wdf_wren;
  input app_wdf_end;
  input [63:0]app_wdf_mask;
  input [511:0]app_wdf_data;
  input [26:0]app_addr;
  input [1:0]app_cmd;

  wire [13:0]D;
  wire [0:0]E;
  wire [575:0]Q;
  wire [2:0]S;
  wire accept_ns;
  wire [26:0]app_addr;
  wire [0:0]\app_addr_r1_reg[23] ;
  wire [0:0]\app_addr_r1_reg[23]_0 ;
  wire [0:0]\app_addr_r1_reg[23]_1 ;
  wire [0:0]\app_addr_r1_reg[23]_2 ;
  wire [2:0]\app_addr_r1_reg[26] ;
  wire [9:0]\app_addr_r1_reg[9] ;
  wire [1:0]app_cmd;
  wire [1:0]app_cmd_r2;
  wire app_en;
  wire app_rdy_ns;
  wire app_rdy_r_reg;
  wire [511:0]app_wdf_data;
  wire app_wdf_end;
  wire [63:0]app_wdf_mask;
  wire app_wdf_rdy;
  wire app_wdf_wren;
  wire [1:0]cmd;
  wire [0:0]p_0_in;
  wire \pointer_ram.pointer_we ;
  wire [3:0]\pointer_ram.pointer_wr_addr ;
  wire [3:0]\pointer_ram.pointer_wr_data ;
  wire ram_init_done_r;
  wire [3:0]\read_data_indx.rd_data_indx_r_reg ;
  wire [11:0]req_bank_r;
  wire \req_bank_r_lcl_reg[0] ;
  wire \req_bank_r_lcl_reg[0]_0 ;
  wire \req_bank_r_lcl_reg[2] ;
  wire \req_bank_r_lcl_reg[2]_0 ;
  wire [0:0]\req_row_r_lcl_reg[10] ;
  wire [3:0]reset_reg;
  wire [19:0]row_hit_r_reg;
  wire [3:0]\strict_mode.rd_data_buf_addr_r_lcl ;
  wire ui_cmd0_n_30;
  wire ui_cmd0_n_33;
  wire ui_cmd0_n_34;
  wire ui_cmd0_n_41;
  wire ui_cmd0_n_42;
  wire ui_cmd0_n_43;
  wire use_addr;
  wire wr_accepted;
  wire [3:0]wr_data_addr;
  wire [3:0]wr_data_buf_addr;
  wire [1:0]\wr_req_counter.wr_req_cnt_r ;
  wire \wr_req_counter.wr_req_cnt_r_reg[0] ;
  wire \wr_req_counter.wr_req_cnt_r_reg[0]_0 ;

  mig_mig_7series_v4_2_ui_cmd ui_cmd0
       (.D({D[13],D[11:0]}),
        .E(app_rdy_r_reg),
        .S(S),
        .app_addr(app_addr),
        .\app_addr_r1_reg[0]_0 (\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .\app_addr_r1_reg[22]_0 (D[12]),
        .\app_addr_r1_reg[23]_0 (\app_addr_r1_reg[23] ),
        .\app_addr_r1_reg[23]_1 (\app_addr_r1_reg[23]_0 ),
        .\app_addr_r1_reg[23]_2 (\app_addr_r1_reg[23]_1 ),
        .\app_addr_r1_reg[23]_3 (\app_addr_r1_reg[23]_2 ),
        .\app_addr_r1_reg[24]_0 (\app_addr_r1_reg[26] [0]),
        .\app_addr_r1_reg[25]_0 (\app_addr_r1_reg[26] [1]),
        .\app_addr_r1_reg[26]_0 (\app_addr_r1_reg[26] [2]),
        .\app_addr_r1_reg[9]_0 (\app_addr_r1_reg[9] ),
        .app_cmd(app_cmd),
        .app_cmd_r2(app_cmd_r2),
        .\app_cmd_r2_reg[0]_0 (\wr_req_counter.wr_req_cnt_r_reg[0] ),
        .app_en(app_en),
        .app_en_r2_reg_0(ui_cmd0_n_41),
        .app_rdy_ns(app_rdy_ns),
        .cmd(cmd),
        .p_0_in(p_0_in),
        .\read_data_indx.rd_data_upd_indx_r_reg (ui_cmd0_n_34),
        .req_bank_r(req_bank_r),
        .\req_bank_r_lcl_reg[0] (\req_bank_r_lcl_reg[0] ),
        .\req_bank_r_lcl_reg[0]_0 (\req_bank_r_lcl_reg[0]_0 ),
        .\req_bank_r_lcl_reg[2] (\req_bank_r_lcl_reg[2] ),
        .\req_bank_r_lcl_reg[2]_0 (\req_bank_r_lcl_reg[2]_0 ),
        .\req_row_r_lcl_reg[10] (\req_row_r_lcl_reg[10] ),
        .reset_reg(reset_reg),
        .row_hit_r_reg(row_hit_r_reg),
        .\strict_mode.rd_data_buf_addr_r_lcl (\strict_mode.rd_data_buf_addr_r_lcl ),
        .\strict_mode.rd_data_buf_addr_r_lcl_reg[0] (ui_cmd0_n_42),
        .\strict_mode.rd_data_buf_addr_r_lcl_reg[1] (ui_cmd0_n_43),
        .use_addr(use_addr),
        .wr_accepted(wr_accepted),
        .wr_data_buf_addr(wr_data_buf_addr),
        .\wr_req_counter.wr_req_cnt_r (\wr_req_counter.wr_req_cnt_r ),
        .\wr_req_counter.wr_req_cnt_r_reg[0] (ui_cmd0_n_33),
        .\wr_req_counter.wr_req_cnt_r_reg[1] (ui_cmd0_n_30));
  mig_mig_7series_v4_2_ui_rd_data ui_rd_data0
       (.ADDRD(\pointer_ram.pointer_wr_addr ),
        .Q(\read_data_indx.rd_data_indx_r_reg ),
        .app_cmd_r2(app_cmd_r2),
        .\pointer_ram.pointer_wr_data (\pointer_ram.pointer_wr_data ),
        .\rd_buf_indx.ram_init_done_r_lcl_reg_0 (ram_init_done_r),
        .\strict_mode.rd_data_buf_addr_r_lcl (\strict_mode.rd_data_buf_addr_r_lcl ),
        .\strict_mode.rd_data_buf_addr_r_lcl_reg[0]_0 (\wr_req_counter.wr_req_cnt_r_reg[0] ),
        .\strict_mode.rd_data_buf_addr_r_lcl_reg[0]_1 (\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .\strict_mode.rd_data_buf_addr_r_lcl_reg[0]_2 (ui_cmd0_n_41),
        .\strict_mode.rd_data_buf_addr_r_lcl_reg[1]_0 (ui_cmd0_n_42),
        .\strict_mode.rd_data_buf_addr_r_lcl_reg[3]_0 (ui_cmd0_n_43),
        .use_addr(use_addr),
        .wr_data_addr(wr_data_addr));
  mig_mig_7series_v4_2_ui_wr_data ui_wr_data0
       (.ADDRD(\pointer_ram.pointer_wr_addr ),
        .E(E),
        .Q(\read_data_indx.rd_data_indx_r_reg ),
        .accept_ns(accept_ns),
        .app_rdy_ns(app_rdy_ns),
        .app_rdy_r_reg(ui_cmd0_n_30),
        .app_wdf_data(app_wdf_data),
        .app_wdf_end(app_wdf_end),
        .app_wdf_mask(app_wdf_mask),
        .app_wdf_rdy(app_wdf_rdy),
        .app_wdf_wren(app_wdf_wren),
        .p_0_in(p_0_in),
        .\pointer_ram.pointer_we (\pointer_ram.pointer_we ),
        .\pointer_ram.pointer_wr_data (\pointer_ram.pointer_wr_data ),
        .ram_init_done_r(ram_init_done_r),
        .wr_accepted(wr_accepted),
        .wr_data_addr(wr_data_addr),
        .wr_data_buf_addr(wr_data_buf_addr),
        .\wr_req_counter.wr_req_cnt_r_reg[0]_0 (\wr_req_counter.wr_req_cnt_r_reg[0] ),
        .\wr_req_counter.wr_req_cnt_r_reg[0]_1 (\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .\wr_req_counter.wr_req_cnt_r_reg[0]_2 (ui_cmd0_n_33),
        .\wr_req_counter.wr_req_cnt_r_reg[1]_0 (\wr_req_counter.wr_req_cnt_r ),
        .\wr_req_counter.wr_req_cnt_r_reg[4]_0 (ui_cmd0_n_34),
        .\write_buffer.wr_buf_out_data_reg[575]_0 (Q));
endmodule

(* ORIG_REF_NAME = "mig_7series_v4_2_ui_wr_data" *) 
module mig_mig_7series_v4_2_ui_wr_data
   (wr_data_buf_addr,
    p_0_in,
    app_wdf_rdy,
    app_rdy_ns,
    \wr_req_counter.wr_req_cnt_r_reg[1]_0 ,
    Q,
    \write_buffer.wr_buf_out_data_reg[575]_0 ,
    \wr_req_counter.wr_req_cnt_r_reg[0]_0 ,
    \pointer_ram.pointer_we ,
    \pointer_ram.pointer_wr_data ,
    ADDRD,
    wr_data_addr,
    E,
    accept_ns,
    \wr_req_counter.wr_req_cnt_r_reg[0]_1 ,
    wr_accepted,
    \wr_req_counter.wr_req_cnt_r_reg[4]_0 ,
    app_rdy_r_reg,
    app_wdf_wren,
    app_wdf_end,
    ram_init_done_r,
    app_wdf_mask,
    app_wdf_data,
    \wr_req_counter.wr_req_cnt_r_reg[0]_2 );
  output [3:0]wr_data_buf_addr;
  output [0:0]p_0_in;
  output app_wdf_rdy;
  output app_rdy_ns;
  output [1:0]\wr_req_counter.wr_req_cnt_r_reg[1]_0 ;
  output [3:0]Q;
  output [575:0]\write_buffer.wr_buf_out_data_reg[575]_0 ;
  input \wr_req_counter.wr_req_cnt_r_reg[0]_0 ;
  input \pointer_ram.pointer_we ;
  input [3:0]\pointer_ram.pointer_wr_data ;
  input [3:0]ADDRD;
  input [3:0]wr_data_addr;
  input [0:0]E;
  input accept_ns;
  input \wr_req_counter.wr_req_cnt_r_reg[0]_1 ;
  input wr_accepted;
  input \wr_req_counter.wr_req_cnt_r_reg[4]_0 ;
  input app_rdy_r_reg;
  input app_wdf_wren;
  input app_wdf_end;
  input ram_init_done_r;
  input [63:0]app_wdf_mask;
  input [511:0]app_wdf_data;
  input \wr_req_counter.wr_req_cnt_r_reg[0]_2 ;

  wire [3:0]ADDRD;
  wire [0:0]E;
  wire [3:0]Q;
  wire accept_ns;
  wire app_rdy_ns;
  wire app_rdy_r_i_2_n_0;
  wire app_rdy_r_i_3_n_0;
  wire app_rdy_r_reg;
  wire [511:0]app_wdf_data;
  wire [511:0]app_wdf_data_r1;
  wire app_wdf_end;
  wire app_wdf_end_ns1;
  wire app_wdf_end_r1;
  wire [63:0]app_wdf_mask;
  wire [63:0]app_wdf_mask_r1;
  wire app_wdf_rdy;
  wire app_wdf_rdy_r_copy1;
  wire app_wdf_rdy_r_copy2;
  wire app_wdf_rdy_r_copy3;
  wire app_wdf_wren;
  wire app_wdf_wren_ns1;
  wire app_wdf_wren_r1;
  wire [3:0]\data_buf_address_counter.data_buf_addr_cnt_r_reg ;
  wire \occupied_counter.occ_cnt[15]_i_1_n_0 ;
  wire \occupied_counter.occ_cnt_reg_n_0_[0] ;
  wire \occupied_counter.occ_cnt_reg_n_0_[10] ;
  wire \occupied_counter.occ_cnt_reg_n_0_[11] ;
  wire \occupied_counter.occ_cnt_reg_n_0_[12] ;
  wire \occupied_counter.occ_cnt_reg_n_0_[13] ;
  wire \occupied_counter.occ_cnt_reg_n_0_[15] ;
  wire \occupied_counter.occ_cnt_reg_n_0_[1] ;
  wire \occupied_counter.occ_cnt_reg_n_0_[2] ;
  wire \occupied_counter.occ_cnt_reg_n_0_[3] ;
  wire \occupied_counter.occ_cnt_reg_n_0_[4] ;
  wire \occupied_counter.occ_cnt_reg_n_0_[5] ;
  wire \occupied_counter.occ_cnt_reg_n_0_[6] ;
  wire \occupied_counter.occ_cnt_reg_n_0_[7] ;
  wire \occupied_counter.occ_cnt_reg_n_0_[8] ;
  wire \occupied_counter.occ_cnt_reg_n_0_[9] ;
  wire [0:0]p_0_in;
  wire [3:0]p_0_in__0;
  wire [1:1]p_0_in__0_0;
  wire [3:0]p_0_in__0__0;
  wire [3:0]p_0_in__1;
  wire [15:0]p_1_in;
  wire p_4_in;
  wire \pointer_ram.pointer_we ;
  wire [3:0]\pointer_ram.pointer_wr_data ;
  wire ram_init_done_r;
  wire [4:1]wb_wr_data_addr_w;
  wire wdf_rdy_ns;
  wire wr_accepted;
  wire [575:0]wr_buf_out_data_w;
  wire [3:0]wr_data_addr;
  wire [3:0]wr_data_buf_addr;
  wire [3:0]wr_data_pntr;
  wire [4:2]\wr_req_counter.wr_req_cnt_r ;
  wire \wr_req_counter.wr_req_cnt_r[1]_i_1_n_0 ;
  wire \wr_req_counter.wr_req_cnt_r[2]_i_1_n_0 ;
  wire \wr_req_counter.wr_req_cnt_r[3]_i_1_n_0 ;
  wire \wr_req_counter.wr_req_cnt_r[4]_i_1_n_0 ;
  wire \wr_req_counter.wr_req_cnt_r[4]_i_2_n_0 ;
  wire \wr_req_counter.wr_req_cnt_r_reg[0]_0 ;
  wire \wr_req_counter.wr_req_cnt_r_reg[0]_1 ;
  wire \wr_req_counter.wr_req_cnt_r_reg[0]_2 ;
  wire [1:0]\wr_req_counter.wr_req_cnt_r_reg[1]_0 ;
  wire \wr_req_counter.wr_req_cnt_r_reg[4]_0 ;
  wire [575:0]\write_buffer.wr_buf_in_data ;
  wire [575:0]\write_buffer.wr_buf_out_data_reg[575]_0 ;
  wire \write_data_control.wb_wr_data_addr0_ns ;
  wire \write_data_control.wb_wr_data_addr0_r ;
  wire [4:1]\write_data_control.wb_wr_data_addr_r ;
  wire \write_data_control.wr_data_addr_le ;
  wire \write_data_control.wr_data_indx_r[3]_i_3_n_0 ;
  wire [3:0]\write_data_control.wr_data_indx_r_reg ;
  wire [1:0]\NLW_pointer_ram.rams[0].RAM32M0_DOA_UNCONNECTED ;
  wire [1:0]\NLW_pointer_ram.rams[0].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_pointer_ram.rams[1].RAM32M0_DOA_UNCONNECTED ;
  wire [1:0]\NLW_pointer_ram.rams[1].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[0].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[10].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[11].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[12].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[13].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[14].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[15].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[16].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[17].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[18].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[19].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[1].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[20].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[21].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[22].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[23].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[24].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[25].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[26].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[27].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[28].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[29].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[2].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[30].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[31].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[32].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[33].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[34].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[35].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[36].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[37].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[38].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[39].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[3].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[40].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[41].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[42].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[43].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[44].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[45].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[46].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[47].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[48].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[49].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[4].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[50].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[51].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[52].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[53].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[54].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[55].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[56].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[57].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[58].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[59].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[5].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[60].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[61].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[62].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[63].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[64].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[65].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[66].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[67].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[68].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[69].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[6].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[70].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[71].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[72].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[73].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[74].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[75].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[76].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[77].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[78].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[79].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[7].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[80].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[81].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[82].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[83].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[84].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[85].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[86].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[87].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[88].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[89].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[8].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[90].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[91].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[92].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[93].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[94].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[95].RAM32M0_DOD_UNCONNECTED ;
  wire [1:0]\NLW_write_buffer.wr_buffer_ram[9].RAM32M0_DOD_UNCONNECTED ;

  LUT6 #(
    .INIT(64'hFFFFFFFFCCC8CCCC)) 
    app_rdy_r_i_1
       (.I0(\wr_req_counter.wr_req_cnt_r[3]_i_1_n_0 ),
        .I1(accept_ns),
        .I2(\wr_req_counter.wr_req_cnt_r[1]_i_1_n_0 ),
        .I3(\wr_req_counter.wr_req_cnt_r_reg[0]_1 ),
        .I4(app_rdy_r_i_2_n_0),
        .I5(app_rdy_r_i_3_n_0),
        .O(app_rdy_ns));
  LUT6 #(
    .INIT(64'h6AAAAAA9AAAAAAAA)) 
    app_rdy_r_i_2
       (.I0(\wr_req_counter.wr_req_cnt_r [4]),
        .I1(\wr_req_counter.wr_req_cnt_r [3]),
        .I2(\wr_req_counter.wr_req_cnt_r [2]),
        .I3(\wr_req_counter.wr_req_cnt_r_reg[1]_0 [1]),
        .I4(app_rdy_r_reg),
        .I5(\wr_req_counter.wr_req_cnt_r_reg[4]_0 ),
        .O(app_rdy_r_i_2_n_0));
  LUT6 #(
    .INIT(64'hAA2AAAAA88A22288)) 
    app_rdy_r_i_3
       (.I0(accept_ns),
        .I1(\wr_req_counter.wr_req_cnt_r_reg[1]_0 [0]),
        .I2(\wr_req_counter.wr_req_cnt_r_reg[1]_0 [1]),
        .I3(p_0_in),
        .I4(wr_accepted),
        .I5(\wr_req_counter.wr_req_cnt_r [2]),
        .O(app_rdy_r_i_3_n_0));
  FDRE \app_wdf_data_r1_reg[0] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[0]),
        .Q(app_wdf_data_r1[0]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[100] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[100]),
        .Q(app_wdf_data_r1[100]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[101] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[101]),
        .Q(app_wdf_data_r1[101]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[102] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[102]),
        .Q(app_wdf_data_r1[102]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[103] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[103]),
        .Q(app_wdf_data_r1[103]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[104] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[104]),
        .Q(app_wdf_data_r1[104]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[105] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[105]),
        .Q(app_wdf_data_r1[105]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[106] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[106]),
        .Q(app_wdf_data_r1[106]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[107] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[107]),
        .Q(app_wdf_data_r1[107]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[108] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[108]),
        .Q(app_wdf_data_r1[108]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[109] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[109]),
        .Q(app_wdf_data_r1[109]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[10] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[10]),
        .Q(app_wdf_data_r1[10]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[110] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[110]),
        .Q(app_wdf_data_r1[110]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[111] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[111]),
        .Q(app_wdf_data_r1[111]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[112] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[112]),
        .Q(app_wdf_data_r1[112]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[113] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[113]),
        .Q(app_wdf_data_r1[113]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[114] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[114]),
        .Q(app_wdf_data_r1[114]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[115] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[115]),
        .Q(app_wdf_data_r1[115]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[116] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[116]),
        .Q(app_wdf_data_r1[116]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[117] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[117]),
        .Q(app_wdf_data_r1[117]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[118] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[118]),
        .Q(app_wdf_data_r1[118]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[119] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[119]),
        .Q(app_wdf_data_r1[119]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[11] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[11]),
        .Q(app_wdf_data_r1[11]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[120] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[120]),
        .Q(app_wdf_data_r1[120]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[121] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[121]),
        .Q(app_wdf_data_r1[121]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[122] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[122]),
        .Q(app_wdf_data_r1[122]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[123] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[123]),
        .Q(app_wdf_data_r1[123]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[124] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[124]),
        .Q(app_wdf_data_r1[124]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[125] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[125]),
        .Q(app_wdf_data_r1[125]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[126] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[126]),
        .Q(app_wdf_data_r1[126]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[127] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[127]),
        .Q(app_wdf_data_r1[127]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[128] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[128]),
        .Q(app_wdf_data_r1[128]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[129] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[129]),
        .Q(app_wdf_data_r1[129]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[12] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[12]),
        .Q(app_wdf_data_r1[12]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[130] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[130]),
        .Q(app_wdf_data_r1[130]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[131] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[131]),
        .Q(app_wdf_data_r1[131]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[132] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[132]),
        .Q(app_wdf_data_r1[132]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[133] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[133]),
        .Q(app_wdf_data_r1[133]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[134] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[134]),
        .Q(app_wdf_data_r1[134]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[135] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[135]),
        .Q(app_wdf_data_r1[135]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[136] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[136]),
        .Q(app_wdf_data_r1[136]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[137] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[137]),
        .Q(app_wdf_data_r1[137]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[138] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[138]),
        .Q(app_wdf_data_r1[138]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[139] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[139]),
        .Q(app_wdf_data_r1[139]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[13] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[13]),
        .Q(app_wdf_data_r1[13]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[140] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[140]),
        .Q(app_wdf_data_r1[140]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[141] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[141]),
        .Q(app_wdf_data_r1[141]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[142] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[142]),
        .Q(app_wdf_data_r1[142]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[143] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[143]),
        .Q(app_wdf_data_r1[143]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[144] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[144]),
        .Q(app_wdf_data_r1[144]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[145] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[145]),
        .Q(app_wdf_data_r1[145]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[146] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[146]),
        .Q(app_wdf_data_r1[146]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[147] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[147]),
        .Q(app_wdf_data_r1[147]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[148] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[148]),
        .Q(app_wdf_data_r1[148]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[149] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[149]),
        .Q(app_wdf_data_r1[149]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[14] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[14]),
        .Q(app_wdf_data_r1[14]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[150] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[150]),
        .Q(app_wdf_data_r1[150]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[151] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[151]),
        .Q(app_wdf_data_r1[151]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[152] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[152]),
        .Q(app_wdf_data_r1[152]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[153] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[153]),
        .Q(app_wdf_data_r1[153]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[154] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[154]),
        .Q(app_wdf_data_r1[154]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[155] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[155]),
        .Q(app_wdf_data_r1[155]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[156] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[156]),
        .Q(app_wdf_data_r1[156]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[157] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[157]),
        .Q(app_wdf_data_r1[157]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[158] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[158]),
        .Q(app_wdf_data_r1[158]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[159] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[159]),
        .Q(app_wdf_data_r1[159]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[15] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[15]),
        .Q(app_wdf_data_r1[15]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[160] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[160]),
        .Q(app_wdf_data_r1[160]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[161] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[161]),
        .Q(app_wdf_data_r1[161]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[162] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[162]),
        .Q(app_wdf_data_r1[162]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[163] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[163]),
        .Q(app_wdf_data_r1[163]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[164] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[164]),
        .Q(app_wdf_data_r1[164]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[165] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[165]),
        .Q(app_wdf_data_r1[165]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[166] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[166]),
        .Q(app_wdf_data_r1[166]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[167] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[167]),
        .Q(app_wdf_data_r1[167]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[168] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[168]),
        .Q(app_wdf_data_r1[168]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[169] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[169]),
        .Q(app_wdf_data_r1[169]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[16] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[16]),
        .Q(app_wdf_data_r1[16]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[170] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[170]),
        .Q(app_wdf_data_r1[170]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[171] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[171]),
        .Q(app_wdf_data_r1[171]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[172] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[172]),
        .Q(app_wdf_data_r1[172]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[173] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[173]),
        .Q(app_wdf_data_r1[173]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[174] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[174]),
        .Q(app_wdf_data_r1[174]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[175] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[175]),
        .Q(app_wdf_data_r1[175]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[176] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[176]),
        .Q(app_wdf_data_r1[176]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[177] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[177]),
        .Q(app_wdf_data_r1[177]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[178] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[178]),
        .Q(app_wdf_data_r1[178]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[179] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[179]),
        .Q(app_wdf_data_r1[179]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[17] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[17]),
        .Q(app_wdf_data_r1[17]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[180] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[180]),
        .Q(app_wdf_data_r1[180]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[181] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[181]),
        .Q(app_wdf_data_r1[181]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[182] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[182]),
        .Q(app_wdf_data_r1[182]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[183] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[183]),
        .Q(app_wdf_data_r1[183]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[184] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[184]),
        .Q(app_wdf_data_r1[184]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[185] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[185]),
        .Q(app_wdf_data_r1[185]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[186] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[186]),
        .Q(app_wdf_data_r1[186]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[187] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[187]),
        .Q(app_wdf_data_r1[187]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[188] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[188]),
        .Q(app_wdf_data_r1[188]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[189] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[189]),
        .Q(app_wdf_data_r1[189]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[18] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[18]),
        .Q(app_wdf_data_r1[18]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[190] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[190]),
        .Q(app_wdf_data_r1[190]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[191] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[191]),
        .Q(app_wdf_data_r1[191]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[192] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[192]),
        .Q(app_wdf_data_r1[192]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[193] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[193]),
        .Q(app_wdf_data_r1[193]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[194] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[194]),
        .Q(app_wdf_data_r1[194]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[195] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[195]),
        .Q(app_wdf_data_r1[195]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[196] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[196]),
        .Q(app_wdf_data_r1[196]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[197] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[197]),
        .Q(app_wdf_data_r1[197]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[198] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[198]),
        .Q(app_wdf_data_r1[198]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[199] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[199]),
        .Q(app_wdf_data_r1[199]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[19] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[19]),
        .Q(app_wdf_data_r1[19]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[1] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[1]),
        .Q(app_wdf_data_r1[1]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[200] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[200]),
        .Q(app_wdf_data_r1[200]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[201] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[201]),
        .Q(app_wdf_data_r1[201]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[202] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[202]),
        .Q(app_wdf_data_r1[202]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[203] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[203]),
        .Q(app_wdf_data_r1[203]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[204] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[204]),
        .Q(app_wdf_data_r1[204]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[205] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[205]),
        .Q(app_wdf_data_r1[205]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[206] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[206]),
        .Q(app_wdf_data_r1[206]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[207] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[207]),
        .Q(app_wdf_data_r1[207]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[208] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[208]),
        .Q(app_wdf_data_r1[208]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[209] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[209]),
        .Q(app_wdf_data_r1[209]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[20] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[20]),
        .Q(app_wdf_data_r1[20]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[210] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[210]),
        .Q(app_wdf_data_r1[210]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[211] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[211]),
        .Q(app_wdf_data_r1[211]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[212] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[212]),
        .Q(app_wdf_data_r1[212]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[213] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[213]),
        .Q(app_wdf_data_r1[213]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[214] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[214]),
        .Q(app_wdf_data_r1[214]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[215] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[215]),
        .Q(app_wdf_data_r1[215]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[216] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[216]),
        .Q(app_wdf_data_r1[216]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[217] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[217]),
        .Q(app_wdf_data_r1[217]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[218] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[218]),
        .Q(app_wdf_data_r1[218]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[219] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[219]),
        .Q(app_wdf_data_r1[219]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[21] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[21]),
        .Q(app_wdf_data_r1[21]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[220] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[220]),
        .Q(app_wdf_data_r1[220]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[221] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[221]),
        .Q(app_wdf_data_r1[221]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[222] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[222]),
        .Q(app_wdf_data_r1[222]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[223] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[223]),
        .Q(app_wdf_data_r1[223]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[224] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[224]),
        .Q(app_wdf_data_r1[224]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[225] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[225]),
        .Q(app_wdf_data_r1[225]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[226] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[226]),
        .Q(app_wdf_data_r1[226]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[227] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[227]),
        .Q(app_wdf_data_r1[227]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[228] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[228]),
        .Q(app_wdf_data_r1[228]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[229] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[229]),
        .Q(app_wdf_data_r1[229]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[22] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[22]),
        .Q(app_wdf_data_r1[22]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[230] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[230]),
        .Q(app_wdf_data_r1[230]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[231] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[231]),
        .Q(app_wdf_data_r1[231]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[232] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[232]),
        .Q(app_wdf_data_r1[232]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[233] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[233]),
        .Q(app_wdf_data_r1[233]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[234] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[234]),
        .Q(app_wdf_data_r1[234]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[235] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[235]),
        .Q(app_wdf_data_r1[235]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[236] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[236]),
        .Q(app_wdf_data_r1[236]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[237] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[237]),
        .Q(app_wdf_data_r1[237]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[238] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[238]),
        .Q(app_wdf_data_r1[238]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[239] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[239]),
        .Q(app_wdf_data_r1[239]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[23] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[23]),
        .Q(app_wdf_data_r1[23]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[240] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[240]),
        .Q(app_wdf_data_r1[240]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[241] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[241]),
        .Q(app_wdf_data_r1[241]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[242] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[242]),
        .Q(app_wdf_data_r1[242]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[243] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[243]),
        .Q(app_wdf_data_r1[243]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[244] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[244]),
        .Q(app_wdf_data_r1[244]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[245] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[245]),
        .Q(app_wdf_data_r1[245]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[246] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[246]),
        .Q(app_wdf_data_r1[246]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[247] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[247]),
        .Q(app_wdf_data_r1[247]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[248] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[248]),
        .Q(app_wdf_data_r1[248]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[249] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[249]),
        .Q(app_wdf_data_r1[249]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[24] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[24]),
        .Q(app_wdf_data_r1[24]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[250] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[250]),
        .Q(app_wdf_data_r1[250]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[251] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[251]),
        .Q(app_wdf_data_r1[251]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[252] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[252]),
        .Q(app_wdf_data_r1[252]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[253] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[253]),
        .Q(app_wdf_data_r1[253]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[254] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[254]),
        .Q(app_wdf_data_r1[254]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[255] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[255]),
        .Q(app_wdf_data_r1[255]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[256] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[256]),
        .Q(app_wdf_data_r1[256]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[257] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[257]),
        .Q(app_wdf_data_r1[257]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[258] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[258]),
        .Q(app_wdf_data_r1[258]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[259] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[259]),
        .Q(app_wdf_data_r1[259]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[25] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[25]),
        .Q(app_wdf_data_r1[25]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[260] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[260]),
        .Q(app_wdf_data_r1[260]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[261] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[261]),
        .Q(app_wdf_data_r1[261]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[262] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[262]),
        .Q(app_wdf_data_r1[262]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[263] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[263]),
        .Q(app_wdf_data_r1[263]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[264] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[264]),
        .Q(app_wdf_data_r1[264]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[265] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[265]),
        .Q(app_wdf_data_r1[265]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[266] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[266]),
        .Q(app_wdf_data_r1[266]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[267] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[267]),
        .Q(app_wdf_data_r1[267]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[268] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[268]),
        .Q(app_wdf_data_r1[268]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[269] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[269]),
        .Q(app_wdf_data_r1[269]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[26] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[26]),
        .Q(app_wdf_data_r1[26]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[270] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[270]),
        .Q(app_wdf_data_r1[270]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[271] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[271]),
        .Q(app_wdf_data_r1[271]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[272] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[272]),
        .Q(app_wdf_data_r1[272]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[273] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[273]),
        .Q(app_wdf_data_r1[273]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[274] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[274]),
        .Q(app_wdf_data_r1[274]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[275] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[275]),
        .Q(app_wdf_data_r1[275]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[276] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[276]),
        .Q(app_wdf_data_r1[276]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[277] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[277]),
        .Q(app_wdf_data_r1[277]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[278] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[278]),
        .Q(app_wdf_data_r1[278]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[279] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[279]),
        .Q(app_wdf_data_r1[279]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[27] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[27]),
        .Q(app_wdf_data_r1[27]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[280] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[280]),
        .Q(app_wdf_data_r1[280]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[281] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[281]),
        .Q(app_wdf_data_r1[281]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[282] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[282]),
        .Q(app_wdf_data_r1[282]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[283] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[283]),
        .Q(app_wdf_data_r1[283]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[284] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[284]),
        .Q(app_wdf_data_r1[284]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[285] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[285]),
        .Q(app_wdf_data_r1[285]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[286] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[286]),
        .Q(app_wdf_data_r1[286]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[287] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[287]),
        .Q(app_wdf_data_r1[287]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[288] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[288]),
        .Q(app_wdf_data_r1[288]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[289] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[289]),
        .Q(app_wdf_data_r1[289]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[28] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[28]),
        .Q(app_wdf_data_r1[28]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[290] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[290]),
        .Q(app_wdf_data_r1[290]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[291] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[291]),
        .Q(app_wdf_data_r1[291]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[292] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[292]),
        .Q(app_wdf_data_r1[292]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[293] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[293]),
        .Q(app_wdf_data_r1[293]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[294] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[294]),
        .Q(app_wdf_data_r1[294]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[295] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[295]),
        .Q(app_wdf_data_r1[295]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[296] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[296]),
        .Q(app_wdf_data_r1[296]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[297] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[297]),
        .Q(app_wdf_data_r1[297]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[298] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[298]),
        .Q(app_wdf_data_r1[298]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[299] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[299]),
        .Q(app_wdf_data_r1[299]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[29] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[29]),
        .Q(app_wdf_data_r1[29]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[2] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[2]),
        .Q(app_wdf_data_r1[2]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[300] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[300]),
        .Q(app_wdf_data_r1[300]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[301] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[301]),
        .Q(app_wdf_data_r1[301]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[302] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[302]),
        .Q(app_wdf_data_r1[302]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[303] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[303]),
        .Q(app_wdf_data_r1[303]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[304] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[304]),
        .Q(app_wdf_data_r1[304]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[305] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[305]),
        .Q(app_wdf_data_r1[305]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[306] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[306]),
        .Q(app_wdf_data_r1[306]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[307] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[307]),
        .Q(app_wdf_data_r1[307]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[308] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[308]),
        .Q(app_wdf_data_r1[308]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[309] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[309]),
        .Q(app_wdf_data_r1[309]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[30] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[30]),
        .Q(app_wdf_data_r1[30]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[310] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[310]),
        .Q(app_wdf_data_r1[310]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[311] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[311]),
        .Q(app_wdf_data_r1[311]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[312] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[312]),
        .Q(app_wdf_data_r1[312]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[313] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[313]),
        .Q(app_wdf_data_r1[313]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[314] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[314]),
        .Q(app_wdf_data_r1[314]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[315] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[315]),
        .Q(app_wdf_data_r1[315]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[316] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[316]),
        .Q(app_wdf_data_r1[316]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[317] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[317]),
        .Q(app_wdf_data_r1[317]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[318] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[318]),
        .Q(app_wdf_data_r1[318]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[319] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[319]),
        .Q(app_wdf_data_r1[319]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[31] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[31]),
        .Q(app_wdf_data_r1[31]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[320] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[320]),
        .Q(app_wdf_data_r1[320]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[321] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[321]),
        .Q(app_wdf_data_r1[321]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[322] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[322]),
        .Q(app_wdf_data_r1[322]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[323] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[323]),
        .Q(app_wdf_data_r1[323]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[324] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[324]),
        .Q(app_wdf_data_r1[324]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[325] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[325]),
        .Q(app_wdf_data_r1[325]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[326] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[326]),
        .Q(app_wdf_data_r1[326]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[327] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[327]),
        .Q(app_wdf_data_r1[327]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[328] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[328]),
        .Q(app_wdf_data_r1[328]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[329] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[329]),
        .Q(app_wdf_data_r1[329]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[32] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[32]),
        .Q(app_wdf_data_r1[32]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[330] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[330]),
        .Q(app_wdf_data_r1[330]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[331] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[331]),
        .Q(app_wdf_data_r1[331]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[332] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[332]),
        .Q(app_wdf_data_r1[332]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[333] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[333]),
        .Q(app_wdf_data_r1[333]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[334] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[334]),
        .Q(app_wdf_data_r1[334]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[335] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[335]),
        .Q(app_wdf_data_r1[335]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[336] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[336]),
        .Q(app_wdf_data_r1[336]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[337] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[337]),
        .Q(app_wdf_data_r1[337]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[338] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[338]),
        .Q(app_wdf_data_r1[338]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[339] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[339]),
        .Q(app_wdf_data_r1[339]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[33] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[33]),
        .Q(app_wdf_data_r1[33]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[340] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[340]),
        .Q(app_wdf_data_r1[340]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[341] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[341]),
        .Q(app_wdf_data_r1[341]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[342] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[342]),
        .Q(app_wdf_data_r1[342]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[343] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[343]),
        .Q(app_wdf_data_r1[343]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[344] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[344]),
        .Q(app_wdf_data_r1[344]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[345] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[345]),
        .Q(app_wdf_data_r1[345]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[346] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[346]),
        .Q(app_wdf_data_r1[346]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[347] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[347]),
        .Q(app_wdf_data_r1[347]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[348] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[348]),
        .Q(app_wdf_data_r1[348]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[349] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[349]),
        .Q(app_wdf_data_r1[349]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[34] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[34]),
        .Q(app_wdf_data_r1[34]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[350] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[350]),
        .Q(app_wdf_data_r1[350]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[351] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[351]),
        .Q(app_wdf_data_r1[351]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[352] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[352]),
        .Q(app_wdf_data_r1[352]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[353] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[353]),
        .Q(app_wdf_data_r1[353]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[354] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[354]),
        .Q(app_wdf_data_r1[354]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[355] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[355]),
        .Q(app_wdf_data_r1[355]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[356] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[356]),
        .Q(app_wdf_data_r1[356]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[357] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[357]),
        .Q(app_wdf_data_r1[357]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[358] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[358]),
        .Q(app_wdf_data_r1[358]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[359] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[359]),
        .Q(app_wdf_data_r1[359]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[35] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[35]),
        .Q(app_wdf_data_r1[35]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[360] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[360]),
        .Q(app_wdf_data_r1[360]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[361] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[361]),
        .Q(app_wdf_data_r1[361]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[362] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[362]),
        .Q(app_wdf_data_r1[362]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[363] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[363]),
        .Q(app_wdf_data_r1[363]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[364] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[364]),
        .Q(app_wdf_data_r1[364]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[365] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[365]),
        .Q(app_wdf_data_r1[365]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[366] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[366]),
        .Q(app_wdf_data_r1[366]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[367] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[367]),
        .Q(app_wdf_data_r1[367]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[368] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[368]),
        .Q(app_wdf_data_r1[368]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[369] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[369]),
        .Q(app_wdf_data_r1[369]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[36] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[36]),
        .Q(app_wdf_data_r1[36]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[370] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[370]),
        .Q(app_wdf_data_r1[370]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[371] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[371]),
        .Q(app_wdf_data_r1[371]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[372] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[372]),
        .Q(app_wdf_data_r1[372]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[373] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[373]),
        .Q(app_wdf_data_r1[373]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[374] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[374]),
        .Q(app_wdf_data_r1[374]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[375] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[375]),
        .Q(app_wdf_data_r1[375]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[376] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[376]),
        .Q(app_wdf_data_r1[376]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[377] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[377]),
        .Q(app_wdf_data_r1[377]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[378] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[378]),
        .Q(app_wdf_data_r1[378]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[379] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[379]),
        .Q(app_wdf_data_r1[379]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[37] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[37]),
        .Q(app_wdf_data_r1[37]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[380] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[380]),
        .Q(app_wdf_data_r1[380]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[381] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[381]),
        .Q(app_wdf_data_r1[381]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[382] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[382]),
        .Q(app_wdf_data_r1[382]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[383] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[383]),
        .Q(app_wdf_data_r1[383]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[384] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[384]),
        .Q(app_wdf_data_r1[384]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[385] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[385]),
        .Q(app_wdf_data_r1[385]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[386] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[386]),
        .Q(app_wdf_data_r1[386]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[387] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[387]),
        .Q(app_wdf_data_r1[387]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[388] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[388]),
        .Q(app_wdf_data_r1[388]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[389] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[389]),
        .Q(app_wdf_data_r1[389]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[38] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[38]),
        .Q(app_wdf_data_r1[38]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[390] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[390]),
        .Q(app_wdf_data_r1[390]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[391] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[391]),
        .Q(app_wdf_data_r1[391]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[392] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[392]),
        .Q(app_wdf_data_r1[392]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[393] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[393]),
        .Q(app_wdf_data_r1[393]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[394] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[394]),
        .Q(app_wdf_data_r1[394]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[395] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[395]),
        .Q(app_wdf_data_r1[395]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[396] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[396]),
        .Q(app_wdf_data_r1[396]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[397] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[397]),
        .Q(app_wdf_data_r1[397]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[398] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[398]),
        .Q(app_wdf_data_r1[398]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[399] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[399]),
        .Q(app_wdf_data_r1[399]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[39] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[39]),
        .Q(app_wdf_data_r1[39]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[3] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[3]),
        .Q(app_wdf_data_r1[3]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[400] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[400]),
        .Q(app_wdf_data_r1[400]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[401] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[401]),
        .Q(app_wdf_data_r1[401]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[402] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[402]),
        .Q(app_wdf_data_r1[402]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[403] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[403]),
        .Q(app_wdf_data_r1[403]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[404] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[404]),
        .Q(app_wdf_data_r1[404]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[405] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[405]),
        .Q(app_wdf_data_r1[405]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[406] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[406]),
        .Q(app_wdf_data_r1[406]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[407] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[407]),
        .Q(app_wdf_data_r1[407]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[408] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[408]),
        .Q(app_wdf_data_r1[408]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[409] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[409]),
        .Q(app_wdf_data_r1[409]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[40] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[40]),
        .Q(app_wdf_data_r1[40]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[410] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[410]),
        .Q(app_wdf_data_r1[410]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[411] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[411]),
        .Q(app_wdf_data_r1[411]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[412] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[412]),
        .Q(app_wdf_data_r1[412]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[413] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[413]),
        .Q(app_wdf_data_r1[413]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[414] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[414]),
        .Q(app_wdf_data_r1[414]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[415] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[415]),
        .Q(app_wdf_data_r1[415]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[416] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[416]),
        .Q(app_wdf_data_r1[416]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[417] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[417]),
        .Q(app_wdf_data_r1[417]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[418] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[418]),
        .Q(app_wdf_data_r1[418]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[419] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[419]),
        .Q(app_wdf_data_r1[419]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[41] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[41]),
        .Q(app_wdf_data_r1[41]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[420] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[420]),
        .Q(app_wdf_data_r1[420]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[421] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[421]),
        .Q(app_wdf_data_r1[421]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[422] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[422]),
        .Q(app_wdf_data_r1[422]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[423] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[423]),
        .Q(app_wdf_data_r1[423]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[424] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[424]),
        .Q(app_wdf_data_r1[424]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[425] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[425]),
        .Q(app_wdf_data_r1[425]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[426] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[426]),
        .Q(app_wdf_data_r1[426]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[427] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[427]),
        .Q(app_wdf_data_r1[427]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[428] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[428]),
        .Q(app_wdf_data_r1[428]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[429] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[429]),
        .Q(app_wdf_data_r1[429]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[42] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[42]),
        .Q(app_wdf_data_r1[42]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[430] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[430]),
        .Q(app_wdf_data_r1[430]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[431] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[431]),
        .Q(app_wdf_data_r1[431]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[432] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[432]),
        .Q(app_wdf_data_r1[432]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[433] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[433]),
        .Q(app_wdf_data_r1[433]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[434] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[434]),
        .Q(app_wdf_data_r1[434]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[435] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[435]),
        .Q(app_wdf_data_r1[435]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[436] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[436]),
        .Q(app_wdf_data_r1[436]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[437] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[437]),
        .Q(app_wdf_data_r1[437]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[438] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[438]),
        .Q(app_wdf_data_r1[438]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[439] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[439]),
        .Q(app_wdf_data_r1[439]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[43] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[43]),
        .Q(app_wdf_data_r1[43]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[440] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[440]),
        .Q(app_wdf_data_r1[440]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[441] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[441]),
        .Q(app_wdf_data_r1[441]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[442] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[442]),
        .Q(app_wdf_data_r1[442]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[443] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[443]),
        .Q(app_wdf_data_r1[443]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[444] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[444]),
        .Q(app_wdf_data_r1[444]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[445] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[445]),
        .Q(app_wdf_data_r1[445]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[446] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[446]),
        .Q(app_wdf_data_r1[446]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[447] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[447]),
        .Q(app_wdf_data_r1[447]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[448] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[448]),
        .Q(app_wdf_data_r1[448]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[449] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[449]),
        .Q(app_wdf_data_r1[449]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[44] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[44]),
        .Q(app_wdf_data_r1[44]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[450] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[450]),
        .Q(app_wdf_data_r1[450]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[451] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[451]),
        .Q(app_wdf_data_r1[451]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[452] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[452]),
        .Q(app_wdf_data_r1[452]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[453] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[453]),
        .Q(app_wdf_data_r1[453]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[454] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[454]),
        .Q(app_wdf_data_r1[454]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[455] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[455]),
        .Q(app_wdf_data_r1[455]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[456] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[456]),
        .Q(app_wdf_data_r1[456]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[457] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[457]),
        .Q(app_wdf_data_r1[457]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[458] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[458]),
        .Q(app_wdf_data_r1[458]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[459] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[459]),
        .Q(app_wdf_data_r1[459]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[45] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[45]),
        .Q(app_wdf_data_r1[45]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[460] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[460]),
        .Q(app_wdf_data_r1[460]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[461] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[461]),
        .Q(app_wdf_data_r1[461]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[462] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[462]),
        .Q(app_wdf_data_r1[462]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[463] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[463]),
        .Q(app_wdf_data_r1[463]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[464] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[464]),
        .Q(app_wdf_data_r1[464]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[465] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[465]),
        .Q(app_wdf_data_r1[465]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[466] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[466]),
        .Q(app_wdf_data_r1[466]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[467] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[467]),
        .Q(app_wdf_data_r1[467]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[468] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[468]),
        .Q(app_wdf_data_r1[468]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[469] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[469]),
        .Q(app_wdf_data_r1[469]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[46] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[46]),
        .Q(app_wdf_data_r1[46]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[470] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[470]),
        .Q(app_wdf_data_r1[470]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[471] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[471]),
        .Q(app_wdf_data_r1[471]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[472] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[472]),
        .Q(app_wdf_data_r1[472]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[473] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[473]),
        .Q(app_wdf_data_r1[473]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[474] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[474]),
        .Q(app_wdf_data_r1[474]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[475] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[475]),
        .Q(app_wdf_data_r1[475]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[476] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[476]),
        .Q(app_wdf_data_r1[476]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[477] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[477]),
        .Q(app_wdf_data_r1[477]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[478] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[478]),
        .Q(app_wdf_data_r1[478]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[479] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[479]),
        .Q(app_wdf_data_r1[479]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[47] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[47]),
        .Q(app_wdf_data_r1[47]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[480] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[480]),
        .Q(app_wdf_data_r1[480]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[481] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[481]),
        .Q(app_wdf_data_r1[481]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[482] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[482]),
        .Q(app_wdf_data_r1[482]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[483] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[483]),
        .Q(app_wdf_data_r1[483]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[484] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[484]),
        .Q(app_wdf_data_r1[484]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[485] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[485]),
        .Q(app_wdf_data_r1[485]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[486] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[486]),
        .Q(app_wdf_data_r1[486]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[487] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[487]),
        .Q(app_wdf_data_r1[487]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[488] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[488]),
        .Q(app_wdf_data_r1[488]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[489] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[489]),
        .Q(app_wdf_data_r1[489]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[48] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[48]),
        .Q(app_wdf_data_r1[48]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[490] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[490]),
        .Q(app_wdf_data_r1[490]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[491] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[491]),
        .Q(app_wdf_data_r1[491]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[492] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[492]),
        .Q(app_wdf_data_r1[492]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[493] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[493]),
        .Q(app_wdf_data_r1[493]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[494] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[494]),
        .Q(app_wdf_data_r1[494]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[495] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[495]),
        .Q(app_wdf_data_r1[495]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[496] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[496]),
        .Q(app_wdf_data_r1[496]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[497] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[497]),
        .Q(app_wdf_data_r1[497]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[498] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[498]),
        .Q(app_wdf_data_r1[498]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[499] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[499]),
        .Q(app_wdf_data_r1[499]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[49] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[49]),
        .Q(app_wdf_data_r1[49]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[4] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[4]),
        .Q(app_wdf_data_r1[4]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[500] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[500]),
        .Q(app_wdf_data_r1[500]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[501] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[501]),
        .Q(app_wdf_data_r1[501]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[502] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[502]),
        .Q(app_wdf_data_r1[502]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[503] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[503]),
        .Q(app_wdf_data_r1[503]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[504] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[504]),
        .Q(app_wdf_data_r1[504]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[505] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[505]),
        .Q(app_wdf_data_r1[505]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[506] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[506]),
        .Q(app_wdf_data_r1[506]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[507] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[507]),
        .Q(app_wdf_data_r1[507]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[508] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[508]),
        .Q(app_wdf_data_r1[508]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[509] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[509]),
        .Q(app_wdf_data_r1[509]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[50] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[50]),
        .Q(app_wdf_data_r1[50]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[510] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[510]),
        .Q(app_wdf_data_r1[510]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[511] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[511]),
        .Q(app_wdf_data_r1[511]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[51] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[51]),
        .Q(app_wdf_data_r1[51]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[52] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[52]),
        .Q(app_wdf_data_r1[52]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[53] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[53]),
        .Q(app_wdf_data_r1[53]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[54] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[54]),
        .Q(app_wdf_data_r1[54]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[55] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[55]),
        .Q(app_wdf_data_r1[55]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[56] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[56]),
        .Q(app_wdf_data_r1[56]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[57] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[57]),
        .Q(app_wdf_data_r1[57]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[58] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[58]),
        .Q(app_wdf_data_r1[58]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[59] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[59]),
        .Q(app_wdf_data_r1[59]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[5] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[5]),
        .Q(app_wdf_data_r1[5]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[60] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[60]),
        .Q(app_wdf_data_r1[60]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[61] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[61]),
        .Q(app_wdf_data_r1[61]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[62] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[62]),
        .Q(app_wdf_data_r1[62]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[63] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[63]),
        .Q(app_wdf_data_r1[63]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[64] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[64]),
        .Q(app_wdf_data_r1[64]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[65] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[65]),
        .Q(app_wdf_data_r1[65]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[66] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[66]),
        .Q(app_wdf_data_r1[66]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[67] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[67]),
        .Q(app_wdf_data_r1[67]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[68] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[68]),
        .Q(app_wdf_data_r1[68]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[69] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[69]),
        .Q(app_wdf_data_r1[69]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[6] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[6]),
        .Q(app_wdf_data_r1[6]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[70] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[70]),
        .Q(app_wdf_data_r1[70]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[71] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[71]),
        .Q(app_wdf_data_r1[71]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[72] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[72]),
        .Q(app_wdf_data_r1[72]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[73] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[73]),
        .Q(app_wdf_data_r1[73]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[74] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[74]),
        .Q(app_wdf_data_r1[74]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[75] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[75]),
        .Q(app_wdf_data_r1[75]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[76] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[76]),
        .Q(app_wdf_data_r1[76]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[77] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[77]),
        .Q(app_wdf_data_r1[77]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[78] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[78]),
        .Q(app_wdf_data_r1[78]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[79] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[79]),
        .Q(app_wdf_data_r1[79]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[7] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[7]),
        .Q(app_wdf_data_r1[7]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[80] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[80]),
        .Q(app_wdf_data_r1[80]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[81] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[81]),
        .Q(app_wdf_data_r1[81]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[82] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[82]),
        .Q(app_wdf_data_r1[82]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[83] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[83]),
        .Q(app_wdf_data_r1[83]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[84] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[84]),
        .Q(app_wdf_data_r1[84]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[85] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[85]),
        .Q(app_wdf_data_r1[85]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[86] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[86]),
        .Q(app_wdf_data_r1[86]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[87] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[87]),
        .Q(app_wdf_data_r1[87]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[88] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[88]),
        .Q(app_wdf_data_r1[88]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[89] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[89]),
        .Q(app_wdf_data_r1[89]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[8] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[8]),
        .Q(app_wdf_data_r1[8]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[90] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[90]),
        .Q(app_wdf_data_r1[90]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[91] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[91]),
        .Q(app_wdf_data_r1[91]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[92] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[92]),
        .Q(app_wdf_data_r1[92]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[93] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[93]),
        .Q(app_wdf_data_r1[93]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[94] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[94]),
        .Q(app_wdf_data_r1[94]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[95] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[95]),
        .Q(app_wdf_data_r1[95]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[96] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[96]),
        .Q(app_wdf_data_r1[96]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[97] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[97]),
        .Q(app_wdf_data_r1[97]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[98] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[98]),
        .Q(app_wdf_data_r1[98]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[99] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[99]),
        .Q(app_wdf_data_r1[99]),
        .R(1'b0));
  FDRE \app_wdf_data_r1_reg[9] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_data[9]),
        .Q(app_wdf_data_r1[9]),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h2230)) 
    app_wdf_end_r1_i_1
       (.I0(app_wdf_end),
        .I1(\wr_req_counter.wr_req_cnt_r_reg[0]_1 ),
        .I2(app_wdf_end_r1),
        .I3(app_wdf_rdy_r_copy2),
        .O(app_wdf_end_ns1));
  FDRE app_wdf_end_r1_reg
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(app_wdf_end_ns1),
        .Q(app_wdf_end_r1),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[0] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[0]),
        .Q(app_wdf_mask_r1[0]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[10] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[10]),
        .Q(app_wdf_mask_r1[10]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[11] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[11]),
        .Q(app_wdf_mask_r1[11]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[12] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[12]),
        .Q(app_wdf_mask_r1[12]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[13] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[13]),
        .Q(app_wdf_mask_r1[13]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[14] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[14]),
        .Q(app_wdf_mask_r1[14]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[15] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[15]),
        .Q(app_wdf_mask_r1[15]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[16] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[16]),
        .Q(app_wdf_mask_r1[16]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[17] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[17]),
        .Q(app_wdf_mask_r1[17]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[18] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[18]),
        .Q(app_wdf_mask_r1[18]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[19] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[19]),
        .Q(app_wdf_mask_r1[19]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[1] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[1]),
        .Q(app_wdf_mask_r1[1]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[20] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[20]),
        .Q(app_wdf_mask_r1[20]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[21] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[21]),
        .Q(app_wdf_mask_r1[21]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[22] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[22]),
        .Q(app_wdf_mask_r1[22]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[23] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[23]),
        .Q(app_wdf_mask_r1[23]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[24] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[24]),
        .Q(app_wdf_mask_r1[24]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[25] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[25]),
        .Q(app_wdf_mask_r1[25]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[26] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[26]),
        .Q(app_wdf_mask_r1[26]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[27] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[27]),
        .Q(app_wdf_mask_r1[27]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[28] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[28]),
        .Q(app_wdf_mask_r1[28]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[29] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[29]),
        .Q(app_wdf_mask_r1[29]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[2] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[2]),
        .Q(app_wdf_mask_r1[2]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[30] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[30]),
        .Q(app_wdf_mask_r1[30]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[31] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[31]),
        .Q(app_wdf_mask_r1[31]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[32] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[32]),
        .Q(app_wdf_mask_r1[32]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[33] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[33]),
        .Q(app_wdf_mask_r1[33]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[34] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[34]),
        .Q(app_wdf_mask_r1[34]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[35] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[35]),
        .Q(app_wdf_mask_r1[35]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[36] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[36]),
        .Q(app_wdf_mask_r1[36]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[37] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[37]),
        .Q(app_wdf_mask_r1[37]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[38] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[38]),
        .Q(app_wdf_mask_r1[38]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[39] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[39]),
        .Q(app_wdf_mask_r1[39]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[3] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[3]),
        .Q(app_wdf_mask_r1[3]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[40] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[40]),
        .Q(app_wdf_mask_r1[40]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[41] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[41]),
        .Q(app_wdf_mask_r1[41]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[42] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[42]),
        .Q(app_wdf_mask_r1[42]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[43] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[43]),
        .Q(app_wdf_mask_r1[43]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[44] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[44]),
        .Q(app_wdf_mask_r1[44]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[45] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[45]),
        .Q(app_wdf_mask_r1[45]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[46] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[46]),
        .Q(app_wdf_mask_r1[46]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[47] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[47]),
        .Q(app_wdf_mask_r1[47]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[48] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[48]),
        .Q(app_wdf_mask_r1[48]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[49] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[49]),
        .Q(app_wdf_mask_r1[49]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[4] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[4]),
        .Q(app_wdf_mask_r1[4]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[50] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[50]),
        .Q(app_wdf_mask_r1[50]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[51] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[51]),
        .Q(app_wdf_mask_r1[51]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[52] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[52]),
        .Q(app_wdf_mask_r1[52]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[53] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[53]),
        .Q(app_wdf_mask_r1[53]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[54] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[54]),
        .Q(app_wdf_mask_r1[54]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[55] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[55]),
        .Q(app_wdf_mask_r1[55]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[56] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[56]),
        .Q(app_wdf_mask_r1[56]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[57] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[57]),
        .Q(app_wdf_mask_r1[57]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[58] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[58]),
        .Q(app_wdf_mask_r1[58]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[59] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[59]),
        .Q(app_wdf_mask_r1[59]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[5] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[5]),
        .Q(app_wdf_mask_r1[5]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[60] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[60]),
        .Q(app_wdf_mask_r1[60]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[61] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[61]),
        .Q(app_wdf_mask_r1[61]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[62] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[62]),
        .Q(app_wdf_mask_r1[62]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[63] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[63]),
        .Q(app_wdf_mask_r1[63]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[6] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[6]),
        .Q(app_wdf_mask_r1[6]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[7] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[7]),
        .Q(app_wdf_mask_r1[7]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[8] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[8]),
        .Q(app_wdf_mask_r1[8]),
        .R(1'b0));
  FDRE \app_wdf_mask_r1_reg[9] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(app_wdf_rdy_r_copy2),
        .D(app_wdf_mask[9]),
        .Q(app_wdf_mask_r1[9]),
        .R(1'b0));
  (* equivalent_register_removal = "no" *) 
  FDRE app_wdf_rdy_r_copy1_reg
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wdf_rdy_ns),
        .Q(app_wdf_rdy_r_copy1),
        .R(1'b0));
  (* equivalent_register_removal = "no" *) 
  FDRE app_wdf_rdy_r_copy2_reg
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wdf_rdy_ns),
        .Q(app_wdf_rdy_r_copy2),
        .R(1'b0));
  (* equivalent_register_removal = "no" *) 
  FDRE app_wdf_rdy_r_copy3_reg
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wdf_rdy_ns),
        .Q(app_wdf_rdy_r_copy3),
        .R(1'b0));
  LUT4 #(
    .INIT(16'h2230)) 
    app_wdf_wren_r1_i_1
       (.I0(app_wdf_wren),
        .I1(\wr_req_counter.wr_req_cnt_r_reg[0]_1 ),
        .I2(app_wdf_wren_r1),
        .I3(app_wdf_rdy_r_copy2),
        .O(app_wdf_wren_ns1));
  FDRE app_wdf_wren_r1_reg
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(app_wdf_wren_ns1),
        .Q(app_wdf_wren_r1),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair1241" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \data_buf_address_counter.data_buf_addr_cnt_r[0]_i_1 
       (.I0(\data_buf_address_counter.data_buf_addr_cnt_r_reg [0]),
        .O(p_0_in__0[0]));
  (* SOFT_HLUTNM = "soft_lutpair1241" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \data_buf_address_counter.data_buf_addr_cnt_r[1]_i_1 
       (.I0(\data_buf_address_counter.data_buf_addr_cnt_r_reg [0]),
        .I1(\data_buf_address_counter.data_buf_addr_cnt_r_reg [1]),
        .O(p_0_in__0[1]));
  (* SOFT_HLUTNM = "soft_lutpair1240" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \data_buf_address_counter.data_buf_addr_cnt_r[2]_i_1 
       (.I0(\data_buf_address_counter.data_buf_addr_cnt_r_reg [0]),
        .I1(\data_buf_address_counter.data_buf_addr_cnt_r_reg [1]),
        .I2(\data_buf_address_counter.data_buf_addr_cnt_r_reg [2]),
        .O(p_0_in__0[2]));
  (* SOFT_HLUTNM = "soft_lutpair1240" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \data_buf_address_counter.data_buf_addr_cnt_r[3]_i_2 
       (.I0(\data_buf_address_counter.data_buf_addr_cnt_r_reg [2]),
        .I1(\data_buf_address_counter.data_buf_addr_cnt_r_reg [1]),
        .I2(\data_buf_address_counter.data_buf_addr_cnt_r_reg [0]),
        .I3(\data_buf_address_counter.data_buf_addr_cnt_r_reg [3]),
        .O(p_0_in__0[3]));
  FDRE \data_buf_address_counter.data_buf_addr_cnt_r_reg[0] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(wr_accepted),
        .D(p_0_in__0[0]),
        .Q(\data_buf_address_counter.data_buf_addr_cnt_r_reg [0]),
        .R(\wr_req_counter.wr_req_cnt_r_reg[0]_1 ));
  FDRE \data_buf_address_counter.data_buf_addr_cnt_r_reg[1] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(wr_accepted),
        .D(p_0_in__0[1]),
        .Q(\data_buf_address_counter.data_buf_addr_cnt_r_reg [1]),
        .R(\wr_req_counter.wr_req_cnt_r_reg[0]_1 ));
  FDRE \data_buf_address_counter.data_buf_addr_cnt_r_reg[2] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(wr_accepted),
        .D(p_0_in__0[2]),
        .Q(\data_buf_address_counter.data_buf_addr_cnt_r_reg [2]),
        .R(\wr_req_counter.wr_req_cnt_r_reg[0]_1 ));
  FDRE \data_buf_address_counter.data_buf_addr_cnt_r_reg[3] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(wr_accepted),
        .D(p_0_in__0[3]),
        .Q(\data_buf_address_counter.data_buf_addr_cnt_r_reg [3]),
        .R(\wr_req_counter.wr_req_cnt_r_reg[0]_1 ));
  LUT6 #(
    .INIT(64'h5000501050105010)) 
    \occupied_counter.app_wdf_rdy_r_i_1 
       (.I0(\wr_req_counter.wr_req_cnt_r_reg[0]_1 ),
        .I1(\occupied_counter.occ_cnt_reg_n_0_[15] ),
        .I2(ram_init_done_r),
        .I3(p_0_in),
        .I4(p_4_in),
        .I5(p_0_in__0_0),
        .O(wdf_rdy_ns));
  (* SOFT_HLUTNM = "soft_lutpair1234" *) 
  LUT3 #(
    .INIT(8'h80)) 
    \occupied_counter.app_wdf_rdy_r_i_2 
       (.I0(app_wdf_wren_r1),
        .I1(app_wdf_end_r1),
        .I2(app_wdf_rdy_r_copy1),
        .O(p_0_in__0_0));
  (* equivalent_register_removal = "no" *) 
  FDRE \occupied_counter.app_wdf_rdy_r_reg 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wdf_rdy_ns),
        .Q(app_wdf_rdy),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair1236" *) 
  LUT4 #(
    .INIT(16'hFF80)) 
    \occupied_counter.occ_cnt[0]_i_1 
       (.I0(app_wdf_rdy_r_copy1),
        .I1(app_wdf_end_r1),
        .I2(app_wdf_wren_r1),
        .I3(\occupied_counter.occ_cnt_reg_n_0_[1] ),
        .O(p_1_in[0]));
  LUT5 #(
    .INIT(32'hBFFF8000)) 
    \occupied_counter.occ_cnt[10]_i_1 
       (.I0(\occupied_counter.occ_cnt_reg_n_0_[9] ),
        .I1(app_wdf_wren_r1),
        .I2(app_wdf_end_r1),
        .I3(app_wdf_rdy_r_copy1),
        .I4(\occupied_counter.occ_cnt_reg_n_0_[11] ),
        .O(p_1_in[10]));
  LUT5 #(
    .INIT(32'hBFFF8000)) 
    \occupied_counter.occ_cnt[11]_i_1 
       (.I0(\occupied_counter.occ_cnt_reg_n_0_[10] ),
        .I1(app_wdf_wren_r1),
        .I2(app_wdf_end_r1),
        .I3(app_wdf_rdy_r_copy1),
        .I4(\occupied_counter.occ_cnt_reg_n_0_[12] ),
        .O(p_1_in[11]));
  LUT5 #(
    .INIT(32'hBFFF8000)) 
    \occupied_counter.occ_cnt[12]_i_1 
       (.I0(\occupied_counter.occ_cnt_reg_n_0_[11] ),
        .I1(app_wdf_wren_r1),
        .I2(app_wdf_end_r1),
        .I3(app_wdf_rdy_r_copy1),
        .I4(\occupied_counter.occ_cnt_reg_n_0_[13] ),
        .O(p_1_in[12]));
  (* SOFT_HLUTNM = "soft_lutpair1237" *) 
  LUT5 #(
    .INIT(32'hBFFF8000)) 
    \occupied_counter.occ_cnt[13]_i_1 
       (.I0(\occupied_counter.occ_cnt_reg_n_0_[12] ),
        .I1(app_wdf_wren_r1),
        .I2(app_wdf_end_r1),
        .I3(app_wdf_rdy_r_copy1),
        .I4(p_4_in),
        .O(p_1_in[13]));
  LUT5 #(
    .INIT(32'hBFFF8000)) 
    \occupied_counter.occ_cnt[14]_i_1 
       (.I0(\occupied_counter.occ_cnt_reg_n_0_[13] ),
        .I1(app_wdf_wren_r1),
        .I2(app_wdf_end_r1),
        .I3(app_wdf_rdy_r_copy1),
        .I4(\occupied_counter.occ_cnt_reg_n_0_[15] ),
        .O(p_1_in[14]));
  LUT4 #(
    .INIT(16'h6AAA)) 
    \occupied_counter.occ_cnt[15]_i_1 
       (.I0(p_0_in),
        .I1(app_wdf_rdy_r_copy1),
        .I2(app_wdf_end_r1),
        .I3(app_wdf_wren_r1),
        .O(\occupied_counter.occ_cnt[15]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1237" *) 
  LUT4 #(
    .INIT(16'h8000)) 
    \occupied_counter.occ_cnt[15]_i_2 
       (.I0(app_wdf_rdy_r_copy1),
        .I1(app_wdf_end_r1),
        .I2(app_wdf_wren_r1),
        .I3(p_4_in),
        .O(p_1_in[15]));
  LUT5 #(
    .INIT(32'hBFFF8000)) 
    \occupied_counter.occ_cnt[1]_i_1 
       (.I0(\occupied_counter.occ_cnt_reg_n_0_[0] ),
        .I1(app_wdf_wren_r1),
        .I2(app_wdf_end_r1),
        .I3(app_wdf_rdy_r_copy1),
        .I4(\occupied_counter.occ_cnt_reg_n_0_[2] ),
        .O(p_1_in[1]));
  (* SOFT_HLUTNM = "soft_lutpair1236" *) 
  LUT5 #(
    .INIT(32'hBFFF8000)) 
    \occupied_counter.occ_cnt[2]_i_1 
       (.I0(\occupied_counter.occ_cnt_reg_n_0_[1] ),
        .I1(app_wdf_wren_r1),
        .I2(app_wdf_end_r1),
        .I3(app_wdf_rdy_r_copy1),
        .I4(\occupied_counter.occ_cnt_reg_n_0_[3] ),
        .O(p_1_in[2]));
  LUT5 #(
    .INIT(32'hBFFF8000)) 
    \occupied_counter.occ_cnt[3]_i_1 
       (.I0(\occupied_counter.occ_cnt_reg_n_0_[2] ),
        .I1(app_wdf_wren_r1),
        .I2(app_wdf_end_r1),
        .I3(app_wdf_rdy_r_copy1),
        .I4(\occupied_counter.occ_cnt_reg_n_0_[4] ),
        .O(p_1_in[3]));
  LUT5 #(
    .INIT(32'hBFFF8000)) 
    \occupied_counter.occ_cnt[4]_i_1 
       (.I0(\occupied_counter.occ_cnt_reg_n_0_[3] ),
        .I1(app_wdf_wren_r1),
        .I2(app_wdf_end_r1),
        .I3(app_wdf_rdy_r_copy1),
        .I4(\occupied_counter.occ_cnt_reg_n_0_[5] ),
        .O(p_1_in[4]));
  LUT5 #(
    .INIT(32'hBFFF8000)) 
    \occupied_counter.occ_cnt[5]_i_1 
       (.I0(\occupied_counter.occ_cnt_reg_n_0_[4] ),
        .I1(app_wdf_wren_r1),
        .I2(app_wdf_end_r1),
        .I3(app_wdf_rdy_r_copy1),
        .I4(\occupied_counter.occ_cnt_reg_n_0_[6] ),
        .O(p_1_in[5]));
  LUT5 #(
    .INIT(32'hBFFF8000)) 
    \occupied_counter.occ_cnt[6]_i_1 
       (.I0(\occupied_counter.occ_cnt_reg_n_0_[5] ),
        .I1(app_wdf_wren_r1),
        .I2(app_wdf_end_r1),
        .I3(app_wdf_rdy_r_copy1),
        .I4(\occupied_counter.occ_cnt_reg_n_0_[7] ),
        .O(p_1_in[6]));
  LUT5 #(
    .INIT(32'hBFFF8000)) 
    \occupied_counter.occ_cnt[7]_i_1 
       (.I0(\occupied_counter.occ_cnt_reg_n_0_[6] ),
        .I1(app_wdf_wren_r1),
        .I2(app_wdf_end_r1),
        .I3(app_wdf_rdy_r_copy1),
        .I4(\occupied_counter.occ_cnt_reg_n_0_[8] ),
        .O(p_1_in[7]));
  (* SOFT_HLUTNM = "soft_lutpair1234" *) 
  LUT5 #(
    .INIT(32'hBFFF8000)) 
    \occupied_counter.occ_cnt[8]_i_1 
       (.I0(\occupied_counter.occ_cnt_reg_n_0_[7] ),
        .I1(app_wdf_wren_r1),
        .I2(app_wdf_end_r1),
        .I3(app_wdf_rdy_r_copy1),
        .I4(\occupied_counter.occ_cnt_reg_n_0_[9] ),
        .O(p_1_in[8]));
  LUT5 #(
    .INIT(32'hBFFF8000)) 
    \occupied_counter.occ_cnt[9]_i_1 
       (.I0(\occupied_counter.occ_cnt_reg_n_0_[8] ),
        .I1(app_wdf_wren_r1),
        .I2(app_wdf_end_r1),
        .I3(app_wdf_rdy_r_copy1),
        .I4(\occupied_counter.occ_cnt_reg_n_0_[10] ),
        .O(p_1_in[9]));
  FDRE \occupied_counter.occ_cnt_reg[0] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ),
        .D(p_1_in[0]),
        .Q(\occupied_counter.occ_cnt_reg_n_0_[0] ),
        .R(\wr_req_counter.wr_req_cnt_r_reg[0]_1 ));
  FDRE \occupied_counter.occ_cnt_reg[10] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ),
        .D(p_1_in[10]),
        .Q(\occupied_counter.occ_cnt_reg_n_0_[10] ),
        .R(\wr_req_counter.wr_req_cnt_r_reg[0]_1 ));
  FDRE \occupied_counter.occ_cnt_reg[11] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ),
        .D(p_1_in[11]),
        .Q(\occupied_counter.occ_cnt_reg_n_0_[11] ),
        .R(\wr_req_counter.wr_req_cnt_r_reg[0]_1 ));
  FDRE \occupied_counter.occ_cnt_reg[12] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ),
        .D(p_1_in[12]),
        .Q(\occupied_counter.occ_cnt_reg_n_0_[12] ),
        .R(\wr_req_counter.wr_req_cnt_r_reg[0]_1 ));
  FDRE \occupied_counter.occ_cnt_reg[13] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ),
        .D(p_1_in[13]),
        .Q(\occupied_counter.occ_cnt_reg_n_0_[13] ),
        .R(\wr_req_counter.wr_req_cnt_r_reg[0]_1 ));
  FDRE \occupied_counter.occ_cnt_reg[14] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ),
        .D(p_1_in[14]),
        .Q(p_4_in),
        .R(\wr_req_counter.wr_req_cnt_r_reg[0]_1 ));
  FDRE \occupied_counter.occ_cnt_reg[15] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ),
        .D(p_1_in[15]),
        .Q(\occupied_counter.occ_cnt_reg_n_0_[15] ),
        .R(\wr_req_counter.wr_req_cnt_r_reg[0]_1 ));
  FDRE \occupied_counter.occ_cnt_reg[1] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ),
        .D(p_1_in[1]),
        .Q(\occupied_counter.occ_cnt_reg_n_0_[1] ),
        .R(\wr_req_counter.wr_req_cnt_r_reg[0]_1 ));
  FDRE \occupied_counter.occ_cnt_reg[2] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ),
        .D(p_1_in[2]),
        .Q(\occupied_counter.occ_cnt_reg_n_0_[2] ),
        .R(\wr_req_counter.wr_req_cnt_r_reg[0]_1 ));
  FDRE \occupied_counter.occ_cnt_reg[3] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ),
        .D(p_1_in[3]),
        .Q(\occupied_counter.occ_cnt_reg_n_0_[3] ),
        .R(\wr_req_counter.wr_req_cnt_r_reg[0]_1 ));
  FDRE \occupied_counter.occ_cnt_reg[4] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ),
        .D(p_1_in[4]),
        .Q(\occupied_counter.occ_cnt_reg_n_0_[4] ),
        .R(\wr_req_counter.wr_req_cnt_r_reg[0]_1 ));
  FDRE \occupied_counter.occ_cnt_reg[5] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ),
        .D(p_1_in[5]),
        .Q(\occupied_counter.occ_cnt_reg_n_0_[5] ),
        .R(\wr_req_counter.wr_req_cnt_r_reg[0]_1 ));
  FDRE \occupied_counter.occ_cnt_reg[6] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ),
        .D(p_1_in[6]),
        .Q(\occupied_counter.occ_cnt_reg_n_0_[6] ),
        .R(\wr_req_counter.wr_req_cnt_r_reg[0]_1 ));
  FDRE \occupied_counter.occ_cnt_reg[7] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ),
        .D(p_1_in[7]),
        .Q(\occupied_counter.occ_cnt_reg_n_0_[7] ),
        .R(\wr_req_counter.wr_req_cnt_r_reg[0]_1 ));
  FDRE \occupied_counter.occ_cnt_reg[8] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ),
        .D(p_1_in[8]),
        .Q(\occupied_counter.occ_cnt_reg_n_0_[8] ),
        .R(\wr_req_counter.wr_req_cnt_r_reg[0]_1 ));
  FDRE \occupied_counter.occ_cnt_reg[9] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(\occupied_counter.occ_cnt[15]_i_1_n_0 ),
        .D(p_1_in[9]),
        .Q(\occupied_counter.occ_cnt_reg_n_0_[9] ),
        .R(\wr_req_counter.wr_req_cnt_r_reg[0]_1 ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \pointer_ram.rams[0].RAM32M0 
       (.ADDRA({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .ADDRB({1'b0,\data_buf_address_counter.data_buf_addr_cnt_r_reg }),
        .ADDRC({1'b0,\write_data_control.wr_data_indx_r_reg }),
        .ADDRD({1'b0,ADDRD}),
        .DIA({1'b0,1'b0}),
        .DIB(\pointer_ram.pointer_wr_data [1:0]),
        .DIC(\pointer_ram.pointer_wr_data [1:0]),
        .DID({1'b0,1'b0}),
        .DOA(\NLW_pointer_ram.rams[0].RAM32M0_DOA_UNCONNECTED [1:0]),
        .DOB(wr_data_buf_addr[1:0]),
        .DOC(wr_data_pntr[1:0]),
        .DOD(\NLW_pointer_ram.rams[0].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(\pointer_ram.pointer_we ));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \pointer_ram.rams[1].RAM32M0 
       (.ADDRA({1'b0,1'b0,1'b0,1'b0,1'b0}),
        .ADDRB({1'b0,\data_buf_address_counter.data_buf_addr_cnt_r_reg }),
        .ADDRC({1'b0,\write_data_control.wr_data_indx_r_reg }),
        .ADDRD({1'b0,ADDRD}),
        .DIA({1'b0,1'b0}),
        .DIB(\pointer_ram.pointer_wr_data [3:2]),
        .DIC(\pointer_ram.pointer_wr_data [3:2]),
        .DID({1'b0,1'b0}),
        .DOA(\NLW_pointer_ram.rams[1].RAM32M0_DOA_UNCONNECTED [1:0]),
        .DOB(wr_data_buf_addr[3:2]),
        .DOC(wr_data_pntr[3:2]),
        .DOD(\NLW_pointer_ram.rams[1].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(\pointer_ram.pointer_we ));
  (* SOFT_HLUTNM = "soft_lutpair1242" *) 
  LUT1 #(
    .INIT(2'h1)) 
    \read_data_indx.rd_data_indx_r[0]_i_1 
       (.I0(Q[0]),
        .O(p_0_in__1[0]));
  (* SOFT_HLUTNM = "soft_lutpair1242" *) 
  LUT2 #(
    .INIT(4'h6)) 
    \read_data_indx.rd_data_indx_r[1]_i_1 
       (.I0(Q[0]),
        .I1(Q[1]),
        .O(p_0_in__1[1]));
  (* SOFT_HLUTNM = "soft_lutpair1239" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \read_data_indx.rd_data_indx_r[2]_i_1 
       (.I0(Q[0]),
        .I1(Q[1]),
        .I2(Q[2]),
        .O(p_0_in__1[2]));
  (* SOFT_HLUTNM = "soft_lutpair1239" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \read_data_indx.rd_data_indx_r[3]_i_1 
       (.I0(Q[2]),
        .I1(Q[1]),
        .I2(Q[0]),
        .I3(Q[3]),
        .O(p_0_in__1[3]));
  FDRE \read_data_indx.rd_data_indx_r_reg[0] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(E),
        .D(p_0_in__1[0]),
        .Q(Q[0]),
        .R(\wr_req_counter.wr_req_cnt_r_reg[0]_1 ));
  FDRE \read_data_indx.rd_data_indx_r_reg[1] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(E),
        .D(p_0_in__1[1]),
        .Q(Q[1]),
        .R(\wr_req_counter.wr_req_cnt_r_reg[0]_1 ));
  FDRE \read_data_indx.rd_data_indx_r_reg[2] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(E),
        .D(p_0_in__1[2]),
        .Q(Q[2]),
        .R(\wr_req_counter.wr_req_cnt_r_reg[0]_1 ));
  FDRE \read_data_indx.rd_data_indx_r_reg[3] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(E),
        .D(p_0_in__1[3]),
        .Q(Q[3]),
        .R(\wr_req_counter.wr_req_cnt_r_reg[0]_1 ));
  FDRE \read_data_indx.rd_data_upd_indx_r_reg 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(E),
        .Q(p_0_in),
        .R(1'b0));
  (* SOFT_HLUTNM = "soft_lutpair1235" *) 
  LUT4 #(
    .INIT(16'hDB24)) 
    \wr_req_counter.wr_req_cnt_r[1]_i_1 
       (.I0(\wr_req_counter.wr_req_cnt_r_reg[1]_0 [0]),
        .I1(p_0_in),
        .I2(wr_accepted),
        .I3(\wr_req_counter.wr_req_cnt_r_reg[1]_0 [1]),
        .O(\wr_req_counter.wr_req_cnt_r[1]_i_1_n_0 ));
  (* SOFT_HLUTNM = "soft_lutpair1235" *) 
  LUT5 #(
    .INIT(32'hF7EF0810)) 
    \wr_req_counter.wr_req_cnt_r[2]_i_1 
       (.I0(\wr_req_counter.wr_req_cnt_r_reg[1]_0 [0]),
        .I1(\wr_req_counter.wr_req_cnt_r_reg[1]_0 [1]),
        .I2(p_0_in),
        .I3(wr_accepted),
        .I4(\wr_req_counter.wr_req_cnt_r [2]),
        .O(\wr_req_counter.wr_req_cnt_r[2]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'hFF7FFEFF00800100)) 
    \wr_req_counter.wr_req_cnt_r[3]_i_1 
       (.I0(\wr_req_counter.wr_req_cnt_r [2]),
        .I1(\wr_req_counter.wr_req_cnt_r_reg[1]_0 [0]),
        .I2(\wr_req_counter.wr_req_cnt_r_reg[1]_0 [1]),
        .I3(p_0_in),
        .I4(wr_accepted),
        .I5(\wr_req_counter.wr_req_cnt_r [3]),
        .O(\wr_req_counter.wr_req_cnt_r[3]_i_1_n_0 ));
  LUT6 #(
    .INIT(64'h000000006AA9AAAA)) 
    \wr_req_counter.wr_req_cnt_r[4]_i_1 
       (.I0(\wr_req_counter.wr_req_cnt_r [4]),
        .I1(\wr_req_counter.wr_req_cnt_r [3]),
        .I2(\wr_req_counter.wr_req_cnt_r [2]),
        .I3(\wr_req_counter.wr_req_cnt_r[4]_i_2_n_0 ),
        .I4(\wr_req_counter.wr_req_cnt_r_reg[4]_0 ),
        .I5(\wr_req_counter.wr_req_cnt_r_reg[0]_1 ),
        .O(\wr_req_counter.wr_req_cnt_r[4]_i_1_n_0 ));
  LUT4 #(
    .INIT(16'h80FE)) 
    \wr_req_counter.wr_req_cnt_r[4]_i_2 
       (.I0(\wr_req_counter.wr_req_cnt_r_reg[1]_0 [1]),
        .I1(wr_accepted),
        .I2(\wr_req_counter.wr_req_cnt_r_reg[1]_0 [0]),
        .I3(\wr_req_counter.wr_req_cnt_r [2]),
        .O(\wr_req_counter.wr_req_cnt_r[4]_i_2_n_0 ));
  FDRE \wr_req_counter.wr_req_cnt_r_reg[0] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(\wr_req_counter.wr_req_cnt_r_reg[0]_2 ),
        .Q(\wr_req_counter.wr_req_cnt_r_reg[1]_0 [0]),
        .R(\wr_req_counter.wr_req_cnt_r_reg[0]_1 ));
  FDRE \wr_req_counter.wr_req_cnt_r_reg[1] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(\wr_req_counter.wr_req_cnt_r[1]_i_1_n_0 ),
        .Q(\wr_req_counter.wr_req_cnt_r_reg[1]_0 [1]),
        .R(\wr_req_counter.wr_req_cnt_r_reg[0]_1 ));
  FDRE \wr_req_counter.wr_req_cnt_r_reg[2] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(\wr_req_counter.wr_req_cnt_r[2]_i_1_n_0 ),
        .Q(\wr_req_counter.wr_req_cnt_r [2]),
        .R(\wr_req_counter.wr_req_cnt_r_reg[0]_1 ));
  FDRE \wr_req_counter.wr_req_cnt_r_reg[3] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(\wr_req_counter.wr_req_cnt_r[3]_i_1_n_0 ),
        .Q(\wr_req_counter.wr_req_cnt_r [3]),
        .R(\wr_req_counter.wr_req_cnt_r_reg[0]_1 ));
  FDRE \wr_req_counter.wr_req_cnt_r_reg[4] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(\wr_req_counter.wr_req_cnt_r[4]_i_1_n_0 ),
        .Q(\wr_req_counter.wr_req_cnt_r [4]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[0] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[0]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [0]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[100] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[100]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [100]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[101] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[101]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [101]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[102] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[102]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [102]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[103] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[103]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [103]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[104] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[104]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [104]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[105] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[105]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [105]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[106] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[106]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [106]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[107] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[107]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [107]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[108] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[108]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [108]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[109] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[109]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [109]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[10] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[10]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [10]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[110] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[110]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [110]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[111] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[111]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [111]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[112] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[112]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [112]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[113] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[113]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [113]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[114] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[114]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [114]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[115] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[115]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [115]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[116] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[116]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [116]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[117] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[117]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [117]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[118] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[118]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [118]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[119] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[119]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [119]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[11] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[11]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [11]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[120] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[120]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [120]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[121] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[121]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [121]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[122] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[122]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [122]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[123] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[123]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [123]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[124] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[124]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [124]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[125] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[125]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [125]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[126] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[126]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [126]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[127] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[127]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [127]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[128] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[128]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [128]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[129] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[129]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [129]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[12] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[12]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [12]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[130] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[130]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [130]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[131] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[131]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [131]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[132] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[132]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [132]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[133] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[133]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [133]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[134] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[134]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [134]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[135] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[135]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [135]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[136] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[136]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [136]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[137] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[137]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [137]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[138] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[138]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [138]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[139] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[139]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [139]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[13] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[13]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [13]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[140] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[140]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [140]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[141] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[141]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [141]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[142] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[142]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [142]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[143] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[143]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [143]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[144] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[144]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [144]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[145] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[145]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [145]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[146] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[146]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [146]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[147] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[147]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [147]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[148] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[148]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [148]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[149] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[149]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [149]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[14] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[14]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [14]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[150] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[150]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [150]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[151] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[151]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [151]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[152] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[152]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [152]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[153] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[153]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [153]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[154] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[154]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [154]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[155] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[155]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [155]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[156] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[156]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [156]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[157] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[157]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [157]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[158] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[158]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [158]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[159] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[159]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [159]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[15] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[15]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [15]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[160] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[160]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [160]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[161] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[161]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [161]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[162] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[162]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [162]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[163] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[163]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [163]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[164] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[164]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [164]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[165] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[165]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [165]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[166] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[166]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [166]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[167] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[167]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [167]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[168] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[168]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [168]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[169] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[169]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [169]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[16] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[16]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [16]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[170] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[170]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [170]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[171] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[171]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [171]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[172] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[172]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [172]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[173] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[173]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [173]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[174] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[174]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [174]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[175] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[175]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [175]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[176] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[176]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [176]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[177] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[177]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [177]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[178] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[178]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [178]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[179] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[179]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [179]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[17] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[17]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [17]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[180] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[180]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [180]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[181] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[181]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [181]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[182] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[182]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [182]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[183] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[183]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [183]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[184] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[184]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [184]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[185] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[185]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [185]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[186] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[186]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [186]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[187] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[187]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [187]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[188] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[188]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [188]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[189] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[189]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [189]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[18] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[18]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [18]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[190] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[190]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [190]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[191] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[191]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [191]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[192] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[192]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [192]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[193] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[193]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [193]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[194] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[194]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [194]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[195] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[195]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [195]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[196] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[196]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [196]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[197] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[197]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [197]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[198] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[198]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [198]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[199] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[199]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [199]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[19] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[19]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [19]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[1] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[1]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [1]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[200] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[200]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [200]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[201] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[201]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [201]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[202] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[202]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [202]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[203] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[203]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [203]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[204] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[204]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [204]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[205] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[205]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [205]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[206] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[206]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [206]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[207] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[207]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [207]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[208] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[208]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [208]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[209] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[209]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [209]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[20] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[20]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [20]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[210] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[210]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [210]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[211] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[211]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [211]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[212] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[212]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [212]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[213] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[213]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [213]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[214] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[214]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [214]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[215] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[215]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [215]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[216] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[216]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [216]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[217] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[217]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [217]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[218] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[218]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [218]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[219] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[219]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [219]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[21] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[21]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [21]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[220] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[220]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [220]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[221] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[221]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [221]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[222] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[222]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [222]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[223] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[223]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [223]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[224] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[224]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [224]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[225] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[225]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [225]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[226] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[226]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [226]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[227] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[227]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [227]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[228] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[228]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [228]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[229] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[229]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [229]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[22] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[22]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [22]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[230] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[230]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [230]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[231] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[231]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [231]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[232] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[232]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [232]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[233] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[233]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [233]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[234] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[234]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [234]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[235] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[235]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [235]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[236] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[236]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [236]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[237] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[237]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [237]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[238] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[238]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [238]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[239] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[239]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [239]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[23] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[23]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [23]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[240] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[240]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [240]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[241] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[241]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [241]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[242] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[242]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [242]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[243] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[243]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [243]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[244] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[244]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [244]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[245] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[245]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [245]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[246] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[246]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [246]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[247] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[247]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [247]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[248] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[248]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [248]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[249] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[249]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [249]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[24] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[24]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [24]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[250] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[250]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [250]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[251] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[251]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [251]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[252] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[252]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [252]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[253] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[253]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [253]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[254] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[254]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [254]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[255] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[255]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [255]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[256] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[256]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [256]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[257] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[257]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [257]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[258] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[258]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [258]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[259] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[259]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [259]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[25] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[25]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [25]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[260] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[260]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [260]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[261] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[261]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [261]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[262] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[262]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [262]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[263] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[263]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [263]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[264] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[264]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [264]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[265] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[265]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [265]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[266] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[266]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [266]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[267] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[267]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [267]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[268] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[268]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [268]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[269] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[269]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [269]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[26] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[26]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [26]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[270] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[270]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [270]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[271] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[271]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [271]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[272] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[272]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [272]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[273] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[273]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [273]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[274] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[274]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [274]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[275] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[275]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [275]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[276] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[276]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [276]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[277] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[277]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [277]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[278] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[278]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [278]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[279] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[279]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [279]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[27] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[27]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [27]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[280] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[280]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [280]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[281] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[281]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [281]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[282] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[282]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [282]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[283] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[283]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [283]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[284] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[284]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [284]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[285] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[285]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [285]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[286] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[286]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [286]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[287] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[287]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [287]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[288] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[288]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [288]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[289] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[289]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [289]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[28] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[28]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [28]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[290] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[290]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [290]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[291] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[291]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [291]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[292] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[292]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [292]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[293] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[293]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [293]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[294] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[294]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [294]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[295] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[295]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [295]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[296] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[296]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [296]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[297] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[297]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [297]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[298] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[298]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [298]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[299] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[299]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [299]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[29] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[29]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [29]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[2] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[2]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [2]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[300] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[300]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [300]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[301] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[301]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [301]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[302] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[302]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [302]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[303] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[303]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [303]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[304] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[304]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [304]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[305] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[305]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [305]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[306] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[306]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [306]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[307] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[307]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [307]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[308] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[308]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [308]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[309] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[309]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [309]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[30] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[30]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [30]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[310] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[310]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [310]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[311] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[311]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [311]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[312] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[312]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [312]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[313] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[313]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [313]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[314] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[314]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [314]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[315] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[315]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [315]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[316] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[316]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [316]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[317] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[317]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [317]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[318] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[318]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [318]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[319] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[319]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [319]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[31] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[31]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [31]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[320] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[320]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [320]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[321] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[321]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [321]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[322] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[322]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [322]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[323] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[323]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [323]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[324] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[324]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [324]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[325] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[325]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [325]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[326] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[326]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [326]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[327] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[327]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [327]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[328] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[328]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [328]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[329] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[329]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [329]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[32] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[32]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [32]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[330] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[330]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [330]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[331] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[331]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [331]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[332] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[332]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [332]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[333] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[333]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [333]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[334] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[334]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [334]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[335] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[335]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [335]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[336] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[336]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [336]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[337] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[337]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [337]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[338] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[338]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [338]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[339] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[339]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [339]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[33] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[33]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [33]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[340] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[340]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [340]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[341] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[341]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [341]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[342] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[342]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [342]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[343] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[343]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [343]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[344] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[344]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [344]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[345] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[345]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [345]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[346] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[346]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [346]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[347] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[347]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [347]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[348] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[348]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [348]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[349] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[349]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [349]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[34] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[34]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [34]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[350] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[350]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [350]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[351] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[351]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [351]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[352] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[352]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [352]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[353] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[353]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [353]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[354] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[354]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [354]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[355] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[355]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [355]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[356] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[356]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [356]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[357] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[357]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [357]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[358] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[358]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [358]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[359] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[359]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [359]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[35] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[35]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [35]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[360] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[360]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [360]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[361] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[361]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [361]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[362] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[362]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [362]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[363] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[363]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [363]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[364] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[364]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [364]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[365] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[365]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [365]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[366] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[366]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [366]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[367] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[367]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [367]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[368] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[368]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [368]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[369] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[369]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [369]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[36] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[36]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [36]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[370] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[370]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [370]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[371] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[371]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [371]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[372] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[372]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [372]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[373] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[373]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [373]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[374] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[374]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [374]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[375] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[375]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [375]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[376] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[376]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [376]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[377] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[377]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [377]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[378] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[378]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [378]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[379] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[379]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [379]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[37] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[37]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [37]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[380] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[380]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [380]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[381] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[381]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [381]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[382] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[382]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [382]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[383] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[383]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [383]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[384] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[384]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [384]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[385] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[385]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [385]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[386] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[386]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [386]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[387] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[387]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [387]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[388] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[388]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [388]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[389] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[389]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [389]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[38] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[38]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [38]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[390] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[390]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [390]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[391] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[391]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [391]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[392] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[392]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [392]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[393] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[393]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [393]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[394] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[394]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [394]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[395] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[395]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [395]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[396] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[396]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [396]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[397] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[397]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [397]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[398] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[398]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [398]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[399] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[399]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [399]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[39] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[39]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [39]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[3] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[3]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [3]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[400] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[400]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [400]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[401] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[401]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [401]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[402] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[402]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [402]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[403] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[403]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [403]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[404] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[404]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [404]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[405] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[405]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [405]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[406] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[406]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [406]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[407] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[407]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [407]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[408] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[408]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [408]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[409] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[409]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [409]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[40] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[40]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [40]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[410] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[410]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [410]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[411] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[411]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [411]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[412] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[412]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [412]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[413] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[413]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [413]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[414] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[414]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [414]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[415] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[415]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [415]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[416] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[416]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [416]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[417] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[417]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [417]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[418] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[418]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [418]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[419] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[419]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [419]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[41] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[41]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [41]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[420] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[420]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [420]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[421] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[421]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [421]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[422] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[422]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [422]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[423] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[423]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [423]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[424] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[424]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [424]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[425] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[425]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [425]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[426] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[426]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [426]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[427] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[427]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [427]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[428] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[428]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [428]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[429] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[429]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [429]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[42] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[42]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [42]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[430] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[430]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [430]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[431] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[431]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [431]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[432] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[432]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [432]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[433] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[433]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [433]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[434] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[434]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [434]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[435] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[435]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [435]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[436] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[436]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [436]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[437] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[437]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [437]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[438] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[438]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [438]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[439] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[439]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [439]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[43] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[43]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [43]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[440] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[440]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [440]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[441] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[441]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [441]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[442] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[442]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [442]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[443] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[443]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [443]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[444] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[444]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [444]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[445] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[445]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [445]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[446] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[446]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [446]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[447] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[447]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [447]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[448] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[448]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [448]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[449] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[449]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [449]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[44] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[44]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [44]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[450] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[450]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [450]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[451] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[451]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [451]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[452] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[452]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [452]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[453] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[453]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [453]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[454] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[454]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [454]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[455] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[455]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [455]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[456] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[456]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [456]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[457] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[457]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [457]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[458] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[458]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [458]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[459] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[459]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [459]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[45] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[45]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [45]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[460] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[460]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [460]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[461] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[461]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [461]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[462] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[462]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [462]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[463] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[463]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [463]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[464] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[464]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [464]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[465] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[465]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [465]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[466] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[466]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [466]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[467] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[467]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [467]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[468] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[468]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [468]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[469] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[469]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [469]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[46] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[46]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [46]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[470] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[470]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [470]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[471] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[471]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [471]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[472] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[472]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [472]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[473] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[473]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [473]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[474] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[474]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [474]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[475] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[475]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [475]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[476] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[476]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [476]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[477] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[477]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [477]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[478] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[478]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [478]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[479] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[479]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [479]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[47] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[47]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [47]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[480] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[480]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [480]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[481] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[481]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [481]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[482] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[482]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [482]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[483] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[483]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [483]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[484] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[484]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [484]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[485] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[485]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [485]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[486] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[486]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [486]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[487] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[487]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [487]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[488] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[488]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [488]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[489] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[489]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [489]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[48] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[48]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [48]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[490] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[490]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [490]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[491] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[491]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [491]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[492] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[492]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [492]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[493] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[493]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [493]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[494] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[494]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [494]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[495] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[495]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [495]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[496] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[496]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [496]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[497] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[497]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [497]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[498] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[498]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [498]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[499] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[499]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [499]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[49] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[49]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [49]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[4] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[4]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [4]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[500] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[500]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [500]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[501] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[501]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [501]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[502] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[502]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [502]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[503] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[503]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [503]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[504] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[504]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [504]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[505] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[505]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [505]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[506] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[506]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [506]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[507] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[507]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [507]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[508] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[508]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [508]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[509] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[509]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [509]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[50] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[50]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [50]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[510] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[510]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [510]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[511] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[511]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [511]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[512] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[512]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [512]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[513] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[513]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [513]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[514] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[514]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [514]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[515] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[515]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [515]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[516] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[516]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [516]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[517] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[517]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [517]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[518] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[518]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [518]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[519] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[519]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [519]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[51] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[51]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [51]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[520] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[520]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [520]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[521] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[521]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [521]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[522] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[522]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [522]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[523] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[523]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [523]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[524] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[524]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [524]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[525] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[525]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [525]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[526] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[526]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [526]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[527] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[527]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [527]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[528] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[528]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [528]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[529] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[529]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [529]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[52] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[52]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [52]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[530] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[530]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [530]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[531] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[531]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [531]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[532] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[532]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [532]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[533] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[533]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [533]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[534] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[534]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [534]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[535] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[535]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [535]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[536] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[536]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [536]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[537] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[537]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [537]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[538] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[538]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [538]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[539] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[539]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [539]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[53] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[53]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [53]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[540] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[540]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [540]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[541] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[541]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [541]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[542] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[542]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [542]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[543] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[543]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [543]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[544] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[544]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [544]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[545] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[545]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [545]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[546] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[546]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [546]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[547] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[547]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [547]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[548] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[548]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [548]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[549] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[549]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [549]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[54] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[54]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [54]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[550] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[550]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [550]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[551] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[551]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [551]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[552] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[552]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [552]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[553] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[553]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [553]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[554] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[554]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [554]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[555] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[555]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [555]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[556] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[556]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [556]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[557] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[557]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [557]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[558] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[558]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [558]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[559] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[559]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [559]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[55] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[55]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [55]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[560] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[560]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [560]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[561] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[561]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [561]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[562] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[562]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [562]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[563] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[563]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [563]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[564] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[564]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [564]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[565] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[565]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [565]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[566] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[566]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [566]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[567] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[567]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [567]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[568] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[568]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [568]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[569] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[569]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [569]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[56] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[56]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [56]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[570] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[570]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [570]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[571] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[571]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [571]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[572] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[572]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [572]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[573] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[573]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [573]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[574] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[574]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [574]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[575] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[575]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [575]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[57] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[57]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [57]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[58] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[58]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [58]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[59] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[59]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [59]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[5] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[5]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [5]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[60] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[60]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [60]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[61] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[61]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [61]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[62] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[62]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [62]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[63] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[63]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [63]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[64] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[64]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [64]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[65] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[65]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [65]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[66] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[66]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [66]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[67] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[67]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [67]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[68] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[68]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [68]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[69] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[69]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [69]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[6] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[6]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [6]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[70] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[70]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [70]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[71] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[71]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [71]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[72] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[72]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [72]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[73] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[73]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [73]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[74] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[74]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [74]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[75] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[75]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [75]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[76] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[76]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [76]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[77] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[77]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [77]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[78] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[78]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [78]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[79] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[79]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [79]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[7] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[7]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [7]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[80] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[80]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [80]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[81] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[81]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [81]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[82] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[82]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [82]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[83] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[83]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [83]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[84] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[84]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [84]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[85] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[85]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [85]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[86] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[86]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [86]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[87] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[87]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [87]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[88] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[88]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [88]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[89] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[89]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [89]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[8] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[8]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [8]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[90] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[90]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [90]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[91] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[91]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [91]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[92] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[92]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [92]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[93] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[93]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [93]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[94] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[94]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [94]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[95] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[95]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [95]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[96] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[96]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [96]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[97] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[97]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [97]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[98] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[98]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [98]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[99] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[99]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [99]),
        .R(1'b0));
  FDRE \write_buffer.wr_buf_out_data_reg[9] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wr_buf_out_data_w[9]),
        .Q(\write_buffer.wr_buf_out_data_reg[575]_0 [9]),
        .R(1'b0));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[0].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [5:4]),
        .DIB(\write_buffer.wr_buf_in_data [3:2]),
        .DIC(\write_buffer.wr_buf_in_data [1:0]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[5:4]),
        .DOB(wr_buf_out_data_w[3:2]),
        .DOC(wr_buf_out_data_w[1:0]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[0].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[0].RAM32M0_i_1 
       (.I0(app_wdf_data[5]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[5]),
        .O(\write_buffer.wr_buf_in_data [5]));
  LUT4 #(
    .INIT(16'h00AC)) 
    \write_buffer.wr_buffer_ram[0].RAM32M0_i_10 
       (.I0(wr_data_pntr[0]),
        .I1(\write_data_control.wb_wr_data_addr_r [1]),
        .I2(\write_data_control.wr_data_addr_le ),
        .I3(\wr_req_counter.wr_req_cnt_r_reg[0]_1 ),
        .O(wb_wr_data_addr_w[1]));
  LUT5 #(
    .INIT(32'h02020F00)) 
    \write_buffer.wr_buffer_ram[0].RAM32M0_i_11 
       (.I0(app_wdf_rdy_r_copy3),
        .I1(app_wdf_end_r1),
        .I2(\wr_req_counter.wr_req_cnt_r_reg[0]_1 ),
        .I3(\write_data_control.wb_wr_data_addr0_r ),
        .I4(app_wdf_wren_r1),
        .O(\write_data_control.wb_wr_data_addr0_ns ));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[0].RAM32M0_i_2 
       (.I0(app_wdf_data[4]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[4]),
        .O(\write_buffer.wr_buf_in_data [4]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[0].RAM32M0_i_3 
       (.I0(app_wdf_data[3]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[3]),
        .O(\write_buffer.wr_buf_in_data [3]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[0].RAM32M0_i_4 
       (.I0(app_wdf_data[2]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[2]),
        .O(\write_buffer.wr_buf_in_data [2]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[0].RAM32M0_i_5 
       (.I0(app_wdf_data[1]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[1]),
        .O(\write_buffer.wr_buf_in_data [1]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[0].RAM32M0_i_6 
       (.I0(app_wdf_data[0]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[0]),
        .O(\write_buffer.wr_buf_in_data [0]));
  LUT4 #(
    .INIT(16'h00AC)) 
    \write_buffer.wr_buffer_ram[0].RAM32M0_i_7 
       (.I0(wr_data_pntr[3]),
        .I1(\write_data_control.wb_wr_data_addr_r [4]),
        .I2(\write_data_control.wr_data_addr_le ),
        .I3(\wr_req_counter.wr_req_cnt_r_reg[0]_1 ),
        .O(wb_wr_data_addr_w[4]));
  LUT4 #(
    .INIT(16'h00AC)) 
    \write_buffer.wr_buffer_ram[0].RAM32M0_i_8 
       (.I0(wr_data_pntr[2]),
        .I1(\write_data_control.wb_wr_data_addr_r [3]),
        .I2(\write_data_control.wr_data_addr_le ),
        .I3(\wr_req_counter.wr_req_cnt_r_reg[0]_1 ),
        .O(wb_wr_data_addr_w[3]));
  LUT4 #(
    .INIT(16'h00AC)) 
    \write_buffer.wr_buffer_ram[0].RAM32M0_i_9 
       (.I0(wr_data_pntr[1]),
        .I1(\write_data_control.wb_wr_data_addr_r [2]),
        .I2(\write_data_control.wr_data_addr_le ),
        .I3(\wr_req_counter.wr_req_cnt_r_reg[0]_1 ),
        .O(wb_wr_data_addr_w[2]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[10].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [65:64]),
        .DIB(\write_buffer.wr_buf_in_data [63:62]),
        .DIC(\write_buffer.wr_buf_in_data [61:60]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[65:64]),
        .DOB(wr_buf_out_data_w[63:62]),
        .DOC(wr_buf_out_data_w[61:60]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[10].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[10].RAM32M0_i_1 
       (.I0(app_wdf_data[65]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[65]),
        .O(\write_buffer.wr_buf_in_data [65]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[10].RAM32M0_i_2 
       (.I0(app_wdf_data[64]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[64]),
        .O(\write_buffer.wr_buf_in_data [64]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[10].RAM32M0_i_3 
       (.I0(app_wdf_data[63]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[63]),
        .O(\write_buffer.wr_buf_in_data [63]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[10].RAM32M0_i_4 
       (.I0(app_wdf_data[62]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[62]),
        .O(\write_buffer.wr_buf_in_data [62]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[10].RAM32M0_i_5 
       (.I0(app_wdf_data[61]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[61]),
        .O(\write_buffer.wr_buf_in_data [61]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[10].RAM32M0_i_6 
       (.I0(app_wdf_data[60]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[60]),
        .O(\write_buffer.wr_buf_in_data [60]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[11].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [71:70]),
        .DIB(\write_buffer.wr_buf_in_data [69:68]),
        .DIC(\write_buffer.wr_buf_in_data [67:66]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[71:70]),
        .DOB(wr_buf_out_data_w[69:68]),
        .DOC(wr_buf_out_data_w[67:66]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[11].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[11].RAM32M0_i_1 
       (.I0(app_wdf_data[71]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[71]),
        .O(\write_buffer.wr_buf_in_data [71]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[11].RAM32M0_i_2 
       (.I0(app_wdf_data[70]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[70]),
        .O(\write_buffer.wr_buf_in_data [70]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[11].RAM32M0_i_3 
       (.I0(app_wdf_data[69]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[69]),
        .O(\write_buffer.wr_buf_in_data [69]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[11].RAM32M0_i_4 
       (.I0(app_wdf_data[68]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[68]),
        .O(\write_buffer.wr_buf_in_data [68]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[11].RAM32M0_i_5 
       (.I0(app_wdf_data[67]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[67]),
        .O(\write_buffer.wr_buf_in_data [67]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[11].RAM32M0_i_6 
       (.I0(app_wdf_data[66]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[66]),
        .O(\write_buffer.wr_buf_in_data [66]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[12].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [77:76]),
        .DIB(\write_buffer.wr_buf_in_data [75:74]),
        .DIC(\write_buffer.wr_buf_in_data [73:72]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[77:76]),
        .DOB(wr_buf_out_data_w[75:74]),
        .DOC(wr_buf_out_data_w[73:72]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[12].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[12].RAM32M0_i_1 
       (.I0(app_wdf_data[77]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[77]),
        .O(\write_buffer.wr_buf_in_data [77]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[12].RAM32M0_i_2 
       (.I0(app_wdf_data[76]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[76]),
        .O(\write_buffer.wr_buf_in_data [76]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[12].RAM32M0_i_3 
       (.I0(app_wdf_data[75]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[75]),
        .O(\write_buffer.wr_buf_in_data [75]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[12].RAM32M0_i_4 
       (.I0(app_wdf_data[74]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[74]),
        .O(\write_buffer.wr_buf_in_data [74]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[12].RAM32M0_i_5 
       (.I0(app_wdf_data[73]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[73]),
        .O(\write_buffer.wr_buf_in_data [73]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[12].RAM32M0_i_6 
       (.I0(app_wdf_data[72]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[72]),
        .O(\write_buffer.wr_buf_in_data [72]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[13].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [83:82]),
        .DIB(\write_buffer.wr_buf_in_data [81:80]),
        .DIC(\write_buffer.wr_buf_in_data [79:78]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[83:82]),
        .DOB(wr_buf_out_data_w[81:80]),
        .DOC(wr_buf_out_data_w[79:78]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[13].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[13].RAM32M0_i_1 
       (.I0(app_wdf_data[83]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[83]),
        .O(\write_buffer.wr_buf_in_data [83]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[13].RAM32M0_i_2 
       (.I0(app_wdf_data[82]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[82]),
        .O(\write_buffer.wr_buf_in_data [82]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[13].RAM32M0_i_3 
       (.I0(app_wdf_data[81]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[81]),
        .O(\write_buffer.wr_buf_in_data [81]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[13].RAM32M0_i_4 
       (.I0(app_wdf_data[80]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[80]),
        .O(\write_buffer.wr_buf_in_data [80]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[13].RAM32M0_i_5 
       (.I0(app_wdf_data[79]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[79]),
        .O(\write_buffer.wr_buf_in_data [79]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[13].RAM32M0_i_6 
       (.I0(app_wdf_data[78]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[78]),
        .O(\write_buffer.wr_buf_in_data [78]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[14].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [89:88]),
        .DIB(\write_buffer.wr_buf_in_data [87:86]),
        .DIC(\write_buffer.wr_buf_in_data [85:84]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[89:88]),
        .DOB(wr_buf_out_data_w[87:86]),
        .DOC(wr_buf_out_data_w[85:84]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[14].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[14].RAM32M0_i_1 
       (.I0(app_wdf_data[89]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[89]),
        .O(\write_buffer.wr_buf_in_data [89]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[14].RAM32M0_i_2 
       (.I0(app_wdf_data[88]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[88]),
        .O(\write_buffer.wr_buf_in_data [88]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[14].RAM32M0_i_3 
       (.I0(app_wdf_data[87]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[87]),
        .O(\write_buffer.wr_buf_in_data [87]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[14].RAM32M0_i_4 
       (.I0(app_wdf_data[86]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[86]),
        .O(\write_buffer.wr_buf_in_data [86]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[14].RAM32M0_i_5 
       (.I0(app_wdf_data[85]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[85]),
        .O(\write_buffer.wr_buf_in_data [85]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[14].RAM32M0_i_6 
       (.I0(app_wdf_data[84]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[84]),
        .O(\write_buffer.wr_buf_in_data [84]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[15].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [95:94]),
        .DIB(\write_buffer.wr_buf_in_data [93:92]),
        .DIC(\write_buffer.wr_buf_in_data [91:90]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[95:94]),
        .DOB(wr_buf_out_data_w[93:92]),
        .DOC(wr_buf_out_data_w[91:90]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[15].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[15].RAM32M0_i_1 
       (.I0(app_wdf_data[95]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[95]),
        .O(\write_buffer.wr_buf_in_data [95]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[15].RAM32M0_i_2 
       (.I0(app_wdf_data[94]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[94]),
        .O(\write_buffer.wr_buf_in_data [94]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[15].RAM32M0_i_3 
       (.I0(app_wdf_data[93]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[93]),
        .O(\write_buffer.wr_buf_in_data [93]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[15].RAM32M0_i_4 
       (.I0(app_wdf_data[92]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[92]),
        .O(\write_buffer.wr_buf_in_data [92]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[15].RAM32M0_i_5 
       (.I0(app_wdf_data[91]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[91]),
        .O(\write_buffer.wr_buf_in_data [91]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[15].RAM32M0_i_6 
       (.I0(app_wdf_data[90]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[90]),
        .O(\write_buffer.wr_buf_in_data [90]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[16].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [101:100]),
        .DIB(\write_buffer.wr_buf_in_data [99:98]),
        .DIC(\write_buffer.wr_buf_in_data [97:96]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[101:100]),
        .DOB(wr_buf_out_data_w[99:98]),
        .DOC(wr_buf_out_data_w[97:96]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[16].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[16].RAM32M0_i_1 
       (.I0(app_wdf_data[101]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[101]),
        .O(\write_buffer.wr_buf_in_data [101]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[16].RAM32M0_i_2 
       (.I0(app_wdf_data[100]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[100]),
        .O(\write_buffer.wr_buf_in_data [100]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[16].RAM32M0_i_3 
       (.I0(app_wdf_data[99]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[99]),
        .O(\write_buffer.wr_buf_in_data [99]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[16].RAM32M0_i_4 
       (.I0(app_wdf_data[98]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[98]),
        .O(\write_buffer.wr_buf_in_data [98]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[16].RAM32M0_i_5 
       (.I0(app_wdf_data[97]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[97]),
        .O(\write_buffer.wr_buf_in_data [97]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[16].RAM32M0_i_6 
       (.I0(app_wdf_data[96]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[96]),
        .O(\write_buffer.wr_buf_in_data [96]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[17].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [107:106]),
        .DIB(\write_buffer.wr_buf_in_data [105:104]),
        .DIC(\write_buffer.wr_buf_in_data [103:102]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[107:106]),
        .DOB(wr_buf_out_data_w[105:104]),
        .DOC(wr_buf_out_data_w[103:102]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[17].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[17].RAM32M0_i_1 
       (.I0(app_wdf_data[107]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[107]),
        .O(\write_buffer.wr_buf_in_data [107]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[17].RAM32M0_i_2 
       (.I0(app_wdf_data[106]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[106]),
        .O(\write_buffer.wr_buf_in_data [106]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[17].RAM32M0_i_3 
       (.I0(app_wdf_data[105]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[105]),
        .O(\write_buffer.wr_buf_in_data [105]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[17].RAM32M0_i_4 
       (.I0(app_wdf_data[104]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[104]),
        .O(\write_buffer.wr_buf_in_data [104]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[17].RAM32M0_i_5 
       (.I0(app_wdf_data[103]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[103]),
        .O(\write_buffer.wr_buf_in_data [103]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[17].RAM32M0_i_6 
       (.I0(app_wdf_data[102]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[102]),
        .O(\write_buffer.wr_buf_in_data [102]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[18].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [113:112]),
        .DIB(\write_buffer.wr_buf_in_data [111:110]),
        .DIC(\write_buffer.wr_buf_in_data [109:108]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[113:112]),
        .DOB(wr_buf_out_data_w[111:110]),
        .DOC(wr_buf_out_data_w[109:108]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[18].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[18].RAM32M0_i_1 
       (.I0(app_wdf_data[113]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[113]),
        .O(\write_buffer.wr_buf_in_data [113]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[18].RAM32M0_i_2 
       (.I0(app_wdf_data[112]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[112]),
        .O(\write_buffer.wr_buf_in_data [112]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[18].RAM32M0_i_3 
       (.I0(app_wdf_data[111]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[111]),
        .O(\write_buffer.wr_buf_in_data [111]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[18].RAM32M0_i_4 
       (.I0(app_wdf_data[110]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[110]),
        .O(\write_buffer.wr_buf_in_data [110]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[18].RAM32M0_i_5 
       (.I0(app_wdf_data[109]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[109]),
        .O(\write_buffer.wr_buf_in_data [109]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[18].RAM32M0_i_6 
       (.I0(app_wdf_data[108]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[108]),
        .O(\write_buffer.wr_buf_in_data [108]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[19].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [119:118]),
        .DIB(\write_buffer.wr_buf_in_data [117:116]),
        .DIC(\write_buffer.wr_buf_in_data [115:114]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[119:118]),
        .DOB(wr_buf_out_data_w[117:116]),
        .DOC(wr_buf_out_data_w[115:114]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[19].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[19].RAM32M0_i_1 
       (.I0(app_wdf_data[119]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[119]),
        .O(\write_buffer.wr_buf_in_data [119]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[19].RAM32M0_i_2 
       (.I0(app_wdf_data[118]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[118]),
        .O(\write_buffer.wr_buf_in_data [118]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[19].RAM32M0_i_3 
       (.I0(app_wdf_data[117]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[117]),
        .O(\write_buffer.wr_buf_in_data [117]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[19].RAM32M0_i_4 
       (.I0(app_wdf_data[116]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[116]),
        .O(\write_buffer.wr_buf_in_data [116]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[19].RAM32M0_i_5 
       (.I0(app_wdf_data[115]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[115]),
        .O(\write_buffer.wr_buf_in_data [115]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[19].RAM32M0_i_6 
       (.I0(app_wdf_data[114]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[114]),
        .O(\write_buffer.wr_buf_in_data [114]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[1].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [11:10]),
        .DIB(\write_buffer.wr_buf_in_data [9:8]),
        .DIC(\write_buffer.wr_buf_in_data [7:6]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[11:10]),
        .DOB(wr_buf_out_data_w[9:8]),
        .DOC(wr_buf_out_data_w[7:6]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[1].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[1].RAM32M0_i_1 
       (.I0(app_wdf_data[11]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[11]),
        .O(\write_buffer.wr_buf_in_data [11]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[1].RAM32M0_i_2 
       (.I0(app_wdf_data[10]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[10]),
        .O(\write_buffer.wr_buf_in_data [10]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[1].RAM32M0_i_3 
       (.I0(app_wdf_data[9]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[9]),
        .O(\write_buffer.wr_buf_in_data [9]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[1].RAM32M0_i_4 
       (.I0(app_wdf_data[8]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[8]),
        .O(\write_buffer.wr_buf_in_data [8]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[1].RAM32M0_i_5 
       (.I0(app_wdf_data[7]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[7]),
        .O(\write_buffer.wr_buf_in_data [7]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[1].RAM32M0_i_6 
       (.I0(app_wdf_data[6]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[6]),
        .O(\write_buffer.wr_buf_in_data [6]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[20].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [125:124]),
        .DIB(\write_buffer.wr_buf_in_data [123:122]),
        .DIC(\write_buffer.wr_buf_in_data [121:120]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[125:124]),
        .DOB(wr_buf_out_data_w[123:122]),
        .DOC(wr_buf_out_data_w[121:120]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[20].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[20].RAM32M0_i_1 
       (.I0(app_wdf_data[125]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[125]),
        .O(\write_buffer.wr_buf_in_data [125]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[20].RAM32M0_i_2 
       (.I0(app_wdf_data[124]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[124]),
        .O(\write_buffer.wr_buf_in_data [124]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[20].RAM32M0_i_3 
       (.I0(app_wdf_data[123]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[123]),
        .O(\write_buffer.wr_buf_in_data [123]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[20].RAM32M0_i_4 
       (.I0(app_wdf_data[122]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[122]),
        .O(\write_buffer.wr_buf_in_data [122]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[20].RAM32M0_i_5 
       (.I0(app_wdf_data[121]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[121]),
        .O(\write_buffer.wr_buf_in_data [121]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[20].RAM32M0_i_6 
       (.I0(app_wdf_data[120]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[120]),
        .O(\write_buffer.wr_buf_in_data [120]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[21].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [131:130]),
        .DIB(\write_buffer.wr_buf_in_data [129:128]),
        .DIC(\write_buffer.wr_buf_in_data [127:126]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[131:130]),
        .DOB(wr_buf_out_data_w[129:128]),
        .DOC(wr_buf_out_data_w[127:126]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[21].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[21].RAM32M0_i_1 
       (.I0(app_wdf_data[131]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[131]),
        .O(\write_buffer.wr_buf_in_data [131]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[21].RAM32M0_i_2 
       (.I0(app_wdf_data[130]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[130]),
        .O(\write_buffer.wr_buf_in_data [130]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[21].RAM32M0_i_3 
       (.I0(app_wdf_data[129]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[129]),
        .O(\write_buffer.wr_buf_in_data [129]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[21].RAM32M0_i_4 
       (.I0(app_wdf_data[128]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[128]),
        .O(\write_buffer.wr_buf_in_data [128]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[21].RAM32M0_i_5 
       (.I0(app_wdf_data[127]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[127]),
        .O(\write_buffer.wr_buf_in_data [127]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[21].RAM32M0_i_6 
       (.I0(app_wdf_data[126]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[126]),
        .O(\write_buffer.wr_buf_in_data [126]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[22].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [137:136]),
        .DIB(\write_buffer.wr_buf_in_data [135:134]),
        .DIC(\write_buffer.wr_buf_in_data [133:132]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[137:136]),
        .DOB(wr_buf_out_data_w[135:134]),
        .DOC(wr_buf_out_data_w[133:132]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[22].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[22].RAM32M0_i_1 
       (.I0(app_wdf_data[137]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[137]),
        .O(\write_buffer.wr_buf_in_data [137]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[22].RAM32M0_i_2 
       (.I0(app_wdf_data[136]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[136]),
        .O(\write_buffer.wr_buf_in_data [136]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[22].RAM32M0_i_3 
       (.I0(app_wdf_data[135]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[135]),
        .O(\write_buffer.wr_buf_in_data [135]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[22].RAM32M0_i_4 
       (.I0(app_wdf_data[134]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[134]),
        .O(\write_buffer.wr_buf_in_data [134]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[22].RAM32M0_i_5 
       (.I0(app_wdf_data[133]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[133]),
        .O(\write_buffer.wr_buf_in_data [133]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[22].RAM32M0_i_6 
       (.I0(app_wdf_data[132]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[132]),
        .O(\write_buffer.wr_buf_in_data [132]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[23].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [143:142]),
        .DIB(\write_buffer.wr_buf_in_data [141:140]),
        .DIC(\write_buffer.wr_buf_in_data [139:138]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[143:142]),
        .DOB(wr_buf_out_data_w[141:140]),
        .DOC(wr_buf_out_data_w[139:138]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[23].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[23].RAM32M0_i_1 
       (.I0(app_wdf_data[143]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[143]),
        .O(\write_buffer.wr_buf_in_data [143]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[23].RAM32M0_i_2 
       (.I0(app_wdf_data[142]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[142]),
        .O(\write_buffer.wr_buf_in_data [142]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[23].RAM32M0_i_3 
       (.I0(app_wdf_data[141]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[141]),
        .O(\write_buffer.wr_buf_in_data [141]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[23].RAM32M0_i_4 
       (.I0(app_wdf_data[140]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[140]),
        .O(\write_buffer.wr_buf_in_data [140]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[23].RAM32M0_i_5 
       (.I0(app_wdf_data[139]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[139]),
        .O(\write_buffer.wr_buf_in_data [139]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[23].RAM32M0_i_6 
       (.I0(app_wdf_data[138]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[138]),
        .O(\write_buffer.wr_buf_in_data [138]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[24].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [149:148]),
        .DIB(\write_buffer.wr_buf_in_data [147:146]),
        .DIC(\write_buffer.wr_buf_in_data [145:144]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[149:148]),
        .DOB(wr_buf_out_data_w[147:146]),
        .DOC(wr_buf_out_data_w[145:144]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[24].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[24].RAM32M0_i_1 
       (.I0(app_wdf_data[149]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[149]),
        .O(\write_buffer.wr_buf_in_data [149]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[24].RAM32M0_i_2 
       (.I0(app_wdf_data[148]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[148]),
        .O(\write_buffer.wr_buf_in_data [148]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[24].RAM32M0_i_3 
       (.I0(app_wdf_data[147]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[147]),
        .O(\write_buffer.wr_buf_in_data [147]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[24].RAM32M0_i_4 
       (.I0(app_wdf_data[146]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[146]),
        .O(\write_buffer.wr_buf_in_data [146]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[24].RAM32M0_i_5 
       (.I0(app_wdf_data[145]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[145]),
        .O(\write_buffer.wr_buf_in_data [145]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[24].RAM32M0_i_6 
       (.I0(app_wdf_data[144]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[144]),
        .O(\write_buffer.wr_buf_in_data [144]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[25].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [155:154]),
        .DIB(\write_buffer.wr_buf_in_data [153:152]),
        .DIC(\write_buffer.wr_buf_in_data [151:150]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[155:154]),
        .DOB(wr_buf_out_data_w[153:152]),
        .DOC(wr_buf_out_data_w[151:150]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[25].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[25].RAM32M0_i_1 
       (.I0(app_wdf_data[155]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[155]),
        .O(\write_buffer.wr_buf_in_data [155]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[25].RAM32M0_i_2 
       (.I0(app_wdf_data[154]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[154]),
        .O(\write_buffer.wr_buf_in_data [154]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[25].RAM32M0_i_3 
       (.I0(app_wdf_data[153]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[153]),
        .O(\write_buffer.wr_buf_in_data [153]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[25].RAM32M0_i_4 
       (.I0(app_wdf_data[152]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[152]),
        .O(\write_buffer.wr_buf_in_data [152]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[25].RAM32M0_i_5 
       (.I0(app_wdf_data[151]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[151]),
        .O(\write_buffer.wr_buf_in_data [151]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[25].RAM32M0_i_6 
       (.I0(app_wdf_data[150]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[150]),
        .O(\write_buffer.wr_buf_in_data [150]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[26].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [161:160]),
        .DIB(\write_buffer.wr_buf_in_data [159:158]),
        .DIC(\write_buffer.wr_buf_in_data [157:156]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[161:160]),
        .DOB(wr_buf_out_data_w[159:158]),
        .DOC(wr_buf_out_data_w[157:156]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[26].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[26].RAM32M0_i_1 
       (.I0(app_wdf_data[161]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[161]),
        .O(\write_buffer.wr_buf_in_data [161]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[26].RAM32M0_i_2 
       (.I0(app_wdf_data[160]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[160]),
        .O(\write_buffer.wr_buf_in_data [160]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[26].RAM32M0_i_3 
       (.I0(app_wdf_data[159]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[159]),
        .O(\write_buffer.wr_buf_in_data [159]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[26].RAM32M0_i_4 
       (.I0(app_wdf_data[158]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[158]),
        .O(\write_buffer.wr_buf_in_data [158]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[26].RAM32M0_i_5 
       (.I0(app_wdf_data[157]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[157]),
        .O(\write_buffer.wr_buf_in_data [157]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[26].RAM32M0_i_6 
       (.I0(app_wdf_data[156]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[156]),
        .O(\write_buffer.wr_buf_in_data [156]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[27].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [167:166]),
        .DIB(\write_buffer.wr_buf_in_data [165:164]),
        .DIC(\write_buffer.wr_buf_in_data [163:162]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[167:166]),
        .DOB(wr_buf_out_data_w[165:164]),
        .DOC(wr_buf_out_data_w[163:162]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[27].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[27].RAM32M0_i_1 
       (.I0(app_wdf_data[167]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[167]),
        .O(\write_buffer.wr_buf_in_data [167]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[27].RAM32M0_i_2 
       (.I0(app_wdf_data[166]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[166]),
        .O(\write_buffer.wr_buf_in_data [166]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[27].RAM32M0_i_3 
       (.I0(app_wdf_data[165]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[165]),
        .O(\write_buffer.wr_buf_in_data [165]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[27].RAM32M0_i_4 
       (.I0(app_wdf_data[164]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[164]),
        .O(\write_buffer.wr_buf_in_data [164]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[27].RAM32M0_i_5 
       (.I0(app_wdf_data[163]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[163]),
        .O(\write_buffer.wr_buf_in_data [163]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[27].RAM32M0_i_6 
       (.I0(app_wdf_data[162]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[162]),
        .O(\write_buffer.wr_buf_in_data [162]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[28].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [173:172]),
        .DIB(\write_buffer.wr_buf_in_data [171:170]),
        .DIC(\write_buffer.wr_buf_in_data [169:168]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[173:172]),
        .DOB(wr_buf_out_data_w[171:170]),
        .DOC(wr_buf_out_data_w[169:168]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[28].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[28].RAM32M0_i_1 
       (.I0(app_wdf_data[173]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[173]),
        .O(\write_buffer.wr_buf_in_data [173]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[28].RAM32M0_i_2 
       (.I0(app_wdf_data[172]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[172]),
        .O(\write_buffer.wr_buf_in_data [172]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[28].RAM32M0_i_3 
       (.I0(app_wdf_data[171]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[171]),
        .O(\write_buffer.wr_buf_in_data [171]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[28].RAM32M0_i_4 
       (.I0(app_wdf_data[170]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[170]),
        .O(\write_buffer.wr_buf_in_data [170]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[28].RAM32M0_i_5 
       (.I0(app_wdf_data[169]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[169]),
        .O(\write_buffer.wr_buf_in_data [169]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[28].RAM32M0_i_6 
       (.I0(app_wdf_data[168]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[168]),
        .O(\write_buffer.wr_buf_in_data [168]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[29].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [179:178]),
        .DIB(\write_buffer.wr_buf_in_data [177:176]),
        .DIC(\write_buffer.wr_buf_in_data [175:174]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[179:178]),
        .DOB(wr_buf_out_data_w[177:176]),
        .DOC(wr_buf_out_data_w[175:174]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[29].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[29].RAM32M0_i_1 
       (.I0(app_wdf_data[179]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[179]),
        .O(\write_buffer.wr_buf_in_data [179]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[29].RAM32M0_i_2 
       (.I0(app_wdf_data[178]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[178]),
        .O(\write_buffer.wr_buf_in_data [178]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[29].RAM32M0_i_3 
       (.I0(app_wdf_data[177]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[177]),
        .O(\write_buffer.wr_buf_in_data [177]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[29].RAM32M0_i_4 
       (.I0(app_wdf_data[176]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[176]),
        .O(\write_buffer.wr_buf_in_data [176]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[29].RAM32M0_i_5 
       (.I0(app_wdf_data[175]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[175]),
        .O(\write_buffer.wr_buf_in_data [175]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[29].RAM32M0_i_6 
       (.I0(app_wdf_data[174]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[174]),
        .O(\write_buffer.wr_buf_in_data [174]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[2].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [17:16]),
        .DIB(\write_buffer.wr_buf_in_data [15:14]),
        .DIC(\write_buffer.wr_buf_in_data [13:12]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[17:16]),
        .DOB(wr_buf_out_data_w[15:14]),
        .DOC(wr_buf_out_data_w[13:12]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[2].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[2].RAM32M0_i_1 
       (.I0(app_wdf_data[17]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[17]),
        .O(\write_buffer.wr_buf_in_data [17]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[2].RAM32M0_i_2 
       (.I0(app_wdf_data[16]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[16]),
        .O(\write_buffer.wr_buf_in_data [16]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[2].RAM32M0_i_3 
       (.I0(app_wdf_data[15]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[15]),
        .O(\write_buffer.wr_buf_in_data [15]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[2].RAM32M0_i_4 
       (.I0(app_wdf_data[14]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[14]),
        .O(\write_buffer.wr_buf_in_data [14]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[2].RAM32M0_i_5 
       (.I0(app_wdf_data[13]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[13]),
        .O(\write_buffer.wr_buf_in_data [13]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[2].RAM32M0_i_6 
       (.I0(app_wdf_data[12]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[12]),
        .O(\write_buffer.wr_buf_in_data [12]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[30].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [185:184]),
        .DIB(\write_buffer.wr_buf_in_data [183:182]),
        .DIC(\write_buffer.wr_buf_in_data [181:180]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[185:184]),
        .DOB(wr_buf_out_data_w[183:182]),
        .DOC(wr_buf_out_data_w[181:180]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[30].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[30].RAM32M0_i_1 
       (.I0(app_wdf_data[185]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[185]),
        .O(\write_buffer.wr_buf_in_data [185]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[30].RAM32M0_i_2 
       (.I0(app_wdf_data[184]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[184]),
        .O(\write_buffer.wr_buf_in_data [184]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[30].RAM32M0_i_3 
       (.I0(app_wdf_data[183]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[183]),
        .O(\write_buffer.wr_buf_in_data [183]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[30].RAM32M0_i_4 
       (.I0(app_wdf_data[182]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[182]),
        .O(\write_buffer.wr_buf_in_data [182]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[30].RAM32M0_i_5 
       (.I0(app_wdf_data[181]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[181]),
        .O(\write_buffer.wr_buf_in_data [181]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[30].RAM32M0_i_6 
       (.I0(app_wdf_data[180]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[180]),
        .O(\write_buffer.wr_buf_in_data [180]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[31].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [191:190]),
        .DIB(\write_buffer.wr_buf_in_data [189:188]),
        .DIC(\write_buffer.wr_buf_in_data [187:186]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[191:190]),
        .DOB(wr_buf_out_data_w[189:188]),
        .DOC(wr_buf_out_data_w[187:186]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[31].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[31].RAM32M0_i_1 
       (.I0(app_wdf_data[191]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[191]),
        .O(\write_buffer.wr_buf_in_data [191]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[31].RAM32M0_i_2 
       (.I0(app_wdf_data[190]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[190]),
        .O(\write_buffer.wr_buf_in_data [190]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[31].RAM32M0_i_3 
       (.I0(app_wdf_data[189]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[189]),
        .O(\write_buffer.wr_buf_in_data [189]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[31].RAM32M0_i_4 
       (.I0(app_wdf_data[188]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[188]),
        .O(\write_buffer.wr_buf_in_data [188]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[31].RAM32M0_i_5 
       (.I0(app_wdf_data[187]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[187]),
        .O(\write_buffer.wr_buf_in_data [187]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[31].RAM32M0_i_6 
       (.I0(app_wdf_data[186]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[186]),
        .O(\write_buffer.wr_buf_in_data [186]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[32].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [197:196]),
        .DIB(\write_buffer.wr_buf_in_data [195:194]),
        .DIC(\write_buffer.wr_buf_in_data [193:192]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[197:196]),
        .DOB(wr_buf_out_data_w[195:194]),
        .DOC(wr_buf_out_data_w[193:192]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[32].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[32].RAM32M0_i_1 
       (.I0(app_wdf_data[197]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[197]),
        .O(\write_buffer.wr_buf_in_data [197]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[32].RAM32M0_i_2 
       (.I0(app_wdf_data[196]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[196]),
        .O(\write_buffer.wr_buf_in_data [196]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[32].RAM32M0_i_3 
       (.I0(app_wdf_data[195]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[195]),
        .O(\write_buffer.wr_buf_in_data [195]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[32].RAM32M0_i_4 
       (.I0(app_wdf_data[194]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[194]),
        .O(\write_buffer.wr_buf_in_data [194]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[32].RAM32M0_i_5 
       (.I0(app_wdf_data[193]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[193]),
        .O(\write_buffer.wr_buf_in_data [193]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[32].RAM32M0_i_6 
       (.I0(app_wdf_data[192]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[192]),
        .O(\write_buffer.wr_buf_in_data [192]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[33].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [203:202]),
        .DIB(\write_buffer.wr_buf_in_data [201:200]),
        .DIC(\write_buffer.wr_buf_in_data [199:198]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[203:202]),
        .DOB(wr_buf_out_data_w[201:200]),
        .DOC(wr_buf_out_data_w[199:198]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[33].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[33].RAM32M0_i_1 
       (.I0(app_wdf_data[203]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[203]),
        .O(\write_buffer.wr_buf_in_data [203]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[33].RAM32M0_i_2 
       (.I0(app_wdf_data[202]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[202]),
        .O(\write_buffer.wr_buf_in_data [202]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[33].RAM32M0_i_3 
       (.I0(app_wdf_data[201]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[201]),
        .O(\write_buffer.wr_buf_in_data [201]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[33].RAM32M0_i_4 
       (.I0(app_wdf_data[200]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[200]),
        .O(\write_buffer.wr_buf_in_data [200]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[33].RAM32M0_i_5 
       (.I0(app_wdf_data[199]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[199]),
        .O(\write_buffer.wr_buf_in_data [199]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[33].RAM32M0_i_6 
       (.I0(app_wdf_data[198]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[198]),
        .O(\write_buffer.wr_buf_in_data [198]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[34].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [209:208]),
        .DIB(\write_buffer.wr_buf_in_data [207:206]),
        .DIC(\write_buffer.wr_buf_in_data [205:204]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[209:208]),
        .DOB(wr_buf_out_data_w[207:206]),
        .DOC(wr_buf_out_data_w[205:204]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[34].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[34].RAM32M0_i_1 
       (.I0(app_wdf_data[209]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[209]),
        .O(\write_buffer.wr_buf_in_data [209]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[34].RAM32M0_i_2 
       (.I0(app_wdf_data[208]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[208]),
        .O(\write_buffer.wr_buf_in_data [208]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[34].RAM32M0_i_3 
       (.I0(app_wdf_data[207]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[207]),
        .O(\write_buffer.wr_buf_in_data [207]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[34].RAM32M0_i_4 
       (.I0(app_wdf_data[206]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[206]),
        .O(\write_buffer.wr_buf_in_data [206]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[34].RAM32M0_i_5 
       (.I0(app_wdf_data[205]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[205]),
        .O(\write_buffer.wr_buf_in_data [205]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[34].RAM32M0_i_6 
       (.I0(app_wdf_data[204]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[204]),
        .O(\write_buffer.wr_buf_in_data [204]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[35].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [215:214]),
        .DIB(\write_buffer.wr_buf_in_data [213:212]),
        .DIC(\write_buffer.wr_buf_in_data [211:210]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[215:214]),
        .DOB(wr_buf_out_data_w[213:212]),
        .DOC(wr_buf_out_data_w[211:210]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[35].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[35].RAM32M0_i_1 
       (.I0(app_wdf_data[215]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[215]),
        .O(\write_buffer.wr_buf_in_data [215]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[35].RAM32M0_i_2 
       (.I0(app_wdf_data[214]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[214]),
        .O(\write_buffer.wr_buf_in_data [214]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[35].RAM32M0_i_3 
       (.I0(app_wdf_data[213]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[213]),
        .O(\write_buffer.wr_buf_in_data [213]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[35].RAM32M0_i_4 
       (.I0(app_wdf_data[212]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[212]),
        .O(\write_buffer.wr_buf_in_data [212]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[35].RAM32M0_i_5 
       (.I0(app_wdf_data[211]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[211]),
        .O(\write_buffer.wr_buf_in_data [211]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[35].RAM32M0_i_6 
       (.I0(app_wdf_data[210]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[210]),
        .O(\write_buffer.wr_buf_in_data [210]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[36].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [221:220]),
        .DIB(\write_buffer.wr_buf_in_data [219:218]),
        .DIC(\write_buffer.wr_buf_in_data [217:216]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[221:220]),
        .DOB(wr_buf_out_data_w[219:218]),
        .DOC(wr_buf_out_data_w[217:216]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[36].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[36].RAM32M0_i_1 
       (.I0(app_wdf_data[221]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[221]),
        .O(\write_buffer.wr_buf_in_data [221]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[36].RAM32M0_i_2 
       (.I0(app_wdf_data[220]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[220]),
        .O(\write_buffer.wr_buf_in_data [220]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[36].RAM32M0_i_3 
       (.I0(app_wdf_data[219]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[219]),
        .O(\write_buffer.wr_buf_in_data [219]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[36].RAM32M0_i_4 
       (.I0(app_wdf_data[218]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[218]),
        .O(\write_buffer.wr_buf_in_data [218]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[36].RAM32M0_i_5 
       (.I0(app_wdf_data[217]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[217]),
        .O(\write_buffer.wr_buf_in_data [217]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[36].RAM32M0_i_6 
       (.I0(app_wdf_data[216]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[216]),
        .O(\write_buffer.wr_buf_in_data [216]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[37].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [227:226]),
        .DIB(\write_buffer.wr_buf_in_data [225:224]),
        .DIC(\write_buffer.wr_buf_in_data [223:222]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[227:226]),
        .DOB(wr_buf_out_data_w[225:224]),
        .DOC(wr_buf_out_data_w[223:222]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[37].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[37].RAM32M0_i_1 
       (.I0(app_wdf_data[227]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[227]),
        .O(\write_buffer.wr_buf_in_data [227]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[37].RAM32M0_i_2 
       (.I0(app_wdf_data[226]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[226]),
        .O(\write_buffer.wr_buf_in_data [226]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[37].RAM32M0_i_3 
       (.I0(app_wdf_data[225]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[225]),
        .O(\write_buffer.wr_buf_in_data [225]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[37].RAM32M0_i_4 
       (.I0(app_wdf_data[224]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[224]),
        .O(\write_buffer.wr_buf_in_data [224]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[37].RAM32M0_i_5 
       (.I0(app_wdf_data[223]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[223]),
        .O(\write_buffer.wr_buf_in_data [223]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[37].RAM32M0_i_6 
       (.I0(app_wdf_data[222]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[222]),
        .O(\write_buffer.wr_buf_in_data [222]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[38].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [233:232]),
        .DIB(\write_buffer.wr_buf_in_data [231:230]),
        .DIC(\write_buffer.wr_buf_in_data [229:228]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[233:232]),
        .DOB(wr_buf_out_data_w[231:230]),
        .DOC(wr_buf_out_data_w[229:228]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[38].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[38].RAM32M0_i_1 
       (.I0(app_wdf_data[233]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[233]),
        .O(\write_buffer.wr_buf_in_data [233]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[38].RAM32M0_i_2 
       (.I0(app_wdf_data[232]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[232]),
        .O(\write_buffer.wr_buf_in_data [232]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[38].RAM32M0_i_3 
       (.I0(app_wdf_data[231]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[231]),
        .O(\write_buffer.wr_buf_in_data [231]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[38].RAM32M0_i_4 
       (.I0(app_wdf_data[230]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[230]),
        .O(\write_buffer.wr_buf_in_data [230]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[38].RAM32M0_i_5 
       (.I0(app_wdf_data[229]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[229]),
        .O(\write_buffer.wr_buf_in_data [229]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[38].RAM32M0_i_6 
       (.I0(app_wdf_data[228]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[228]),
        .O(\write_buffer.wr_buf_in_data [228]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[39].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [239:238]),
        .DIB(\write_buffer.wr_buf_in_data [237:236]),
        .DIC(\write_buffer.wr_buf_in_data [235:234]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[239:238]),
        .DOB(wr_buf_out_data_w[237:236]),
        .DOC(wr_buf_out_data_w[235:234]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[39].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[39].RAM32M0_i_1 
       (.I0(app_wdf_data[239]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[239]),
        .O(\write_buffer.wr_buf_in_data [239]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[39].RAM32M0_i_2 
       (.I0(app_wdf_data[238]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[238]),
        .O(\write_buffer.wr_buf_in_data [238]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[39].RAM32M0_i_3 
       (.I0(app_wdf_data[237]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[237]),
        .O(\write_buffer.wr_buf_in_data [237]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[39].RAM32M0_i_4 
       (.I0(app_wdf_data[236]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[236]),
        .O(\write_buffer.wr_buf_in_data [236]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[39].RAM32M0_i_5 
       (.I0(app_wdf_data[235]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[235]),
        .O(\write_buffer.wr_buf_in_data [235]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[39].RAM32M0_i_6 
       (.I0(app_wdf_data[234]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[234]),
        .O(\write_buffer.wr_buf_in_data [234]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[3].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [23:22]),
        .DIB(\write_buffer.wr_buf_in_data [21:20]),
        .DIC(\write_buffer.wr_buf_in_data [19:18]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[23:22]),
        .DOB(wr_buf_out_data_w[21:20]),
        .DOC(wr_buf_out_data_w[19:18]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[3].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[3].RAM32M0_i_1 
       (.I0(app_wdf_data[23]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[23]),
        .O(\write_buffer.wr_buf_in_data [23]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[3].RAM32M0_i_2 
       (.I0(app_wdf_data[22]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[22]),
        .O(\write_buffer.wr_buf_in_data [22]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[3].RAM32M0_i_3 
       (.I0(app_wdf_data[21]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[21]),
        .O(\write_buffer.wr_buf_in_data [21]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[3].RAM32M0_i_4 
       (.I0(app_wdf_data[20]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[20]),
        .O(\write_buffer.wr_buf_in_data [20]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[3].RAM32M0_i_5 
       (.I0(app_wdf_data[19]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[19]),
        .O(\write_buffer.wr_buf_in_data [19]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[3].RAM32M0_i_6 
       (.I0(app_wdf_data[18]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[18]),
        .O(\write_buffer.wr_buf_in_data [18]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[40].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [245:244]),
        .DIB(\write_buffer.wr_buf_in_data [243:242]),
        .DIC(\write_buffer.wr_buf_in_data [241:240]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[245:244]),
        .DOB(wr_buf_out_data_w[243:242]),
        .DOC(wr_buf_out_data_w[241:240]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[40].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[40].RAM32M0_i_1 
       (.I0(app_wdf_data[245]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[245]),
        .O(\write_buffer.wr_buf_in_data [245]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[40].RAM32M0_i_2 
       (.I0(app_wdf_data[244]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[244]),
        .O(\write_buffer.wr_buf_in_data [244]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[40].RAM32M0_i_3 
       (.I0(app_wdf_data[243]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[243]),
        .O(\write_buffer.wr_buf_in_data [243]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[40].RAM32M0_i_4 
       (.I0(app_wdf_data[242]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[242]),
        .O(\write_buffer.wr_buf_in_data [242]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[40].RAM32M0_i_5 
       (.I0(app_wdf_data[241]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[241]),
        .O(\write_buffer.wr_buf_in_data [241]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[40].RAM32M0_i_6 
       (.I0(app_wdf_data[240]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[240]),
        .O(\write_buffer.wr_buf_in_data [240]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[41].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [251:250]),
        .DIB(\write_buffer.wr_buf_in_data [249:248]),
        .DIC(\write_buffer.wr_buf_in_data [247:246]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[251:250]),
        .DOB(wr_buf_out_data_w[249:248]),
        .DOC(wr_buf_out_data_w[247:246]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[41].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[41].RAM32M0_i_1 
       (.I0(app_wdf_data[251]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[251]),
        .O(\write_buffer.wr_buf_in_data [251]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[41].RAM32M0_i_2 
       (.I0(app_wdf_data[250]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[250]),
        .O(\write_buffer.wr_buf_in_data [250]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[41].RAM32M0_i_3 
       (.I0(app_wdf_data[249]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[249]),
        .O(\write_buffer.wr_buf_in_data [249]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[41].RAM32M0_i_4 
       (.I0(app_wdf_data[248]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[248]),
        .O(\write_buffer.wr_buf_in_data [248]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[41].RAM32M0_i_5 
       (.I0(app_wdf_data[247]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[247]),
        .O(\write_buffer.wr_buf_in_data [247]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[41].RAM32M0_i_6 
       (.I0(app_wdf_data[246]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[246]),
        .O(\write_buffer.wr_buf_in_data [246]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[42].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [257:256]),
        .DIB(\write_buffer.wr_buf_in_data [255:254]),
        .DIC(\write_buffer.wr_buf_in_data [253:252]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[257:256]),
        .DOB(wr_buf_out_data_w[255:254]),
        .DOC(wr_buf_out_data_w[253:252]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[42].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[42].RAM32M0_i_1 
       (.I0(app_wdf_data[257]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[257]),
        .O(\write_buffer.wr_buf_in_data [257]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[42].RAM32M0_i_2 
       (.I0(app_wdf_data[256]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[256]),
        .O(\write_buffer.wr_buf_in_data [256]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[42].RAM32M0_i_3 
       (.I0(app_wdf_data[255]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[255]),
        .O(\write_buffer.wr_buf_in_data [255]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[42].RAM32M0_i_4 
       (.I0(app_wdf_data[254]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[254]),
        .O(\write_buffer.wr_buf_in_data [254]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[42].RAM32M0_i_5 
       (.I0(app_wdf_data[253]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[253]),
        .O(\write_buffer.wr_buf_in_data [253]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[42].RAM32M0_i_6 
       (.I0(app_wdf_data[252]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[252]),
        .O(\write_buffer.wr_buf_in_data [252]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[43].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [263:262]),
        .DIB(\write_buffer.wr_buf_in_data [261:260]),
        .DIC(\write_buffer.wr_buf_in_data [259:258]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[263:262]),
        .DOB(wr_buf_out_data_w[261:260]),
        .DOC(wr_buf_out_data_w[259:258]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[43].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[43].RAM32M0_i_1 
       (.I0(app_wdf_data[263]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[263]),
        .O(\write_buffer.wr_buf_in_data [263]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[43].RAM32M0_i_2 
       (.I0(app_wdf_data[262]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[262]),
        .O(\write_buffer.wr_buf_in_data [262]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[43].RAM32M0_i_3 
       (.I0(app_wdf_data[261]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[261]),
        .O(\write_buffer.wr_buf_in_data [261]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[43].RAM32M0_i_4 
       (.I0(app_wdf_data[260]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[260]),
        .O(\write_buffer.wr_buf_in_data [260]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[43].RAM32M0_i_5 
       (.I0(app_wdf_data[259]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[259]),
        .O(\write_buffer.wr_buf_in_data [259]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[43].RAM32M0_i_6 
       (.I0(app_wdf_data[258]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[258]),
        .O(\write_buffer.wr_buf_in_data [258]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[44].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [269:268]),
        .DIB(\write_buffer.wr_buf_in_data [267:266]),
        .DIC(\write_buffer.wr_buf_in_data [265:264]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[269:268]),
        .DOB(wr_buf_out_data_w[267:266]),
        .DOC(wr_buf_out_data_w[265:264]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[44].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[44].RAM32M0_i_1 
       (.I0(app_wdf_data[269]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[269]),
        .O(\write_buffer.wr_buf_in_data [269]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[44].RAM32M0_i_2 
       (.I0(app_wdf_data[268]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[268]),
        .O(\write_buffer.wr_buf_in_data [268]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[44].RAM32M0_i_3 
       (.I0(app_wdf_data[267]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[267]),
        .O(\write_buffer.wr_buf_in_data [267]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[44].RAM32M0_i_4 
       (.I0(app_wdf_data[266]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[266]),
        .O(\write_buffer.wr_buf_in_data [266]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[44].RAM32M0_i_5 
       (.I0(app_wdf_data[265]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[265]),
        .O(\write_buffer.wr_buf_in_data [265]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[44].RAM32M0_i_6 
       (.I0(app_wdf_data[264]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[264]),
        .O(\write_buffer.wr_buf_in_data [264]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[45].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [275:274]),
        .DIB(\write_buffer.wr_buf_in_data [273:272]),
        .DIC(\write_buffer.wr_buf_in_data [271:270]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[275:274]),
        .DOB(wr_buf_out_data_w[273:272]),
        .DOC(wr_buf_out_data_w[271:270]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[45].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[45].RAM32M0_i_1 
       (.I0(app_wdf_data[275]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[275]),
        .O(\write_buffer.wr_buf_in_data [275]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[45].RAM32M0_i_2 
       (.I0(app_wdf_data[274]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[274]),
        .O(\write_buffer.wr_buf_in_data [274]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[45].RAM32M0_i_3 
       (.I0(app_wdf_data[273]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[273]),
        .O(\write_buffer.wr_buf_in_data [273]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[45].RAM32M0_i_4 
       (.I0(app_wdf_data[272]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[272]),
        .O(\write_buffer.wr_buf_in_data [272]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[45].RAM32M0_i_5 
       (.I0(app_wdf_data[271]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[271]),
        .O(\write_buffer.wr_buf_in_data [271]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[45].RAM32M0_i_6 
       (.I0(app_wdf_data[270]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[270]),
        .O(\write_buffer.wr_buf_in_data [270]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[46].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [281:280]),
        .DIB(\write_buffer.wr_buf_in_data [279:278]),
        .DIC(\write_buffer.wr_buf_in_data [277:276]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[281:280]),
        .DOB(wr_buf_out_data_w[279:278]),
        .DOC(wr_buf_out_data_w[277:276]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[46].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[46].RAM32M0_i_1 
       (.I0(app_wdf_data[281]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[281]),
        .O(\write_buffer.wr_buf_in_data [281]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[46].RAM32M0_i_2 
       (.I0(app_wdf_data[280]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[280]),
        .O(\write_buffer.wr_buf_in_data [280]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[46].RAM32M0_i_3 
       (.I0(app_wdf_data[279]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[279]),
        .O(\write_buffer.wr_buf_in_data [279]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[46].RAM32M0_i_4 
       (.I0(app_wdf_data[278]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[278]),
        .O(\write_buffer.wr_buf_in_data [278]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[46].RAM32M0_i_5 
       (.I0(app_wdf_data[277]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[277]),
        .O(\write_buffer.wr_buf_in_data [277]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[46].RAM32M0_i_6 
       (.I0(app_wdf_data[276]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[276]),
        .O(\write_buffer.wr_buf_in_data [276]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[47].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [287:286]),
        .DIB(\write_buffer.wr_buf_in_data [285:284]),
        .DIC(\write_buffer.wr_buf_in_data [283:282]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[287:286]),
        .DOB(wr_buf_out_data_w[285:284]),
        .DOC(wr_buf_out_data_w[283:282]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[47].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[47].RAM32M0_i_1 
       (.I0(app_wdf_data[287]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[287]),
        .O(\write_buffer.wr_buf_in_data [287]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[47].RAM32M0_i_2 
       (.I0(app_wdf_data[286]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[286]),
        .O(\write_buffer.wr_buf_in_data [286]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[47].RAM32M0_i_3 
       (.I0(app_wdf_data[285]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[285]),
        .O(\write_buffer.wr_buf_in_data [285]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[47].RAM32M0_i_4 
       (.I0(app_wdf_data[284]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[284]),
        .O(\write_buffer.wr_buf_in_data [284]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[47].RAM32M0_i_5 
       (.I0(app_wdf_data[283]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[283]),
        .O(\write_buffer.wr_buf_in_data [283]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[47].RAM32M0_i_6 
       (.I0(app_wdf_data[282]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[282]),
        .O(\write_buffer.wr_buf_in_data [282]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[48].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [293:292]),
        .DIB(\write_buffer.wr_buf_in_data [291:290]),
        .DIC(\write_buffer.wr_buf_in_data [289:288]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[293:292]),
        .DOB(wr_buf_out_data_w[291:290]),
        .DOC(wr_buf_out_data_w[289:288]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[48].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[48].RAM32M0_i_1 
       (.I0(app_wdf_data[293]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[293]),
        .O(\write_buffer.wr_buf_in_data [293]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[48].RAM32M0_i_2 
       (.I0(app_wdf_data[292]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[292]),
        .O(\write_buffer.wr_buf_in_data [292]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[48].RAM32M0_i_3 
       (.I0(app_wdf_data[291]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[291]),
        .O(\write_buffer.wr_buf_in_data [291]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[48].RAM32M0_i_4 
       (.I0(app_wdf_data[290]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[290]),
        .O(\write_buffer.wr_buf_in_data [290]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[48].RAM32M0_i_5 
       (.I0(app_wdf_data[289]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[289]),
        .O(\write_buffer.wr_buf_in_data [289]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[48].RAM32M0_i_6 
       (.I0(app_wdf_data[288]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[288]),
        .O(\write_buffer.wr_buf_in_data [288]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[49].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [299:298]),
        .DIB(\write_buffer.wr_buf_in_data [297:296]),
        .DIC(\write_buffer.wr_buf_in_data [295:294]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[299:298]),
        .DOB(wr_buf_out_data_w[297:296]),
        .DOC(wr_buf_out_data_w[295:294]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[49].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[49].RAM32M0_i_1 
       (.I0(app_wdf_data[299]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[299]),
        .O(\write_buffer.wr_buf_in_data [299]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[49].RAM32M0_i_2 
       (.I0(app_wdf_data[298]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[298]),
        .O(\write_buffer.wr_buf_in_data [298]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[49].RAM32M0_i_3 
       (.I0(app_wdf_data[297]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[297]),
        .O(\write_buffer.wr_buf_in_data [297]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[49].RAM32M0_i_4 
       (.I0(app_wdf_data[296]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[296]),
        .O(\write_buffer.wr_buf_in_data [296]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[49].RAM32M0_i_5 
       (.I0(app_wdf_data[295]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[295]),
        .O(\write_buffer.wr_buf_in_data [295]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[49].RAM32M0_i_6 
       (.I0(app_wdf_data[294]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[294]),
        .O(\write_buffer.wr_buf_in_data [294]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[4].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [29:28]),
        .DIB(\write_buffer.wr_buf_in_data [27:26]),
        .DIC(\write_buffer.wr_buf_in_data [25:24]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[29:28]),
        .DOB(wr_buf_out_data_w[27:26]),
        .DOC(wr_buf_out_data_w[25:24]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[4].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[4].RAM32M0_i_1 
       (.I0(app_wdf_data[29]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[29]),
        .O(\write_buffer.wr_buf_in_data [29]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[4].RAM32M0_i_2 
       (.I0(app_wdf_data[28]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[28]),
        .O(\write_buffer.wr_buf_in_data [28]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[4].RAM32M0_i_3 
       (.I0(app_wdf_data[27]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[27]),
        .O(\write_buffer.wr_buf_in_data [27]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[4].RAM32M0_i_4 
       (.I0(app_wdf_data[26]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[26]),
        .O(\write_buffer.wr_buf_in_data [26]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[4].RAM32M0_i_5 
       (.I0(app_wdf_data[25]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[25]),
        .O(\write_buffer.wr_buf_in_data [25]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[4].RAM32M0_i_6 
       (.I0(app_wdf_data[24]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[24]),
        .O(\write_buffer.wr_buf_in_data [24]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[50].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [305:304]),
        .DIB(\write_buffer.wr_buf_in_data [303:302]),
        .DIC(\write_buffer.wr_buf_in_data [301:300]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[305:304]),
        .DOB(wr_buf_out_data_w[303:302]),
        .DOC(wr_buf_out_data_w[301:300]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[50].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[50].RAM32M0_i_1 
       (.I0(app_wdf_data[305]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[305]),
        .O(\write_buffer.wr_buf_in_data [305]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[50].RAM32M0_i_2 
       (.I0(app_wdf_data[304]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[304]),
        .O(\write_buffer.wr_buf_in_data [304]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[50].RAM32M0_i_3 
       (.I0(app_wdf_data[303]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[303]),
        .O(\write_buffer.wr_buf_in_data [303]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[50].RAM32M0_i_4 
       (.I0(app_wdf_data[302]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[302]),
        .O(\write_buffer.wr_buf_in_data [302]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[50].RAM32M0_i_5 
       (.I0(app_wdf_data[301]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[301]),
        .O(\write_buffer.wr_buf_in_data [301]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[50].RAM32M0_i_6 
       (.I0(app_wdf_data[300]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[300]),
        .O(\write_buffer.wr_buf_in_data [300]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[51].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [311:310]),
        .DIB(\write_buffer.wr_buf_in_data [309:308]),
        .DIC(\write_buffer.wr_buf_in_data [307:306]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[311:310]),
        .DOB(wr_buf_out_data_w[309:308]),
        .DOC(wr_buf_out_data_w[307:306]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[51].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[51].RAM32M0_i_1 
       (.I0(app_wdf_data[311]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[311]),
        .O(\write_buffer.wr_buf_in_data [311]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[51].RAM32M0_i_2 
       (.I0(app_wdf_data[310]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[310]),
        .O(\write_buffer.wr_buf_in_data [310]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[51].RAM32M0_i_3 
       (.I0(app_wdf_data[309]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[309]),
        .O(\write_buffer.wr_buf_in_data [309]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[51].RAM32M0_i_4 
       (.I0(app_wdf_data[308]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[308]),
        .O(\write_buffer.wr_buf_in_data [308]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[51].RAM32M0_i_5 
       (.I0(app_wdf_data[307]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[307]),
        .O(\write_buffer.wr_buf_in_data [307]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[51].RAM32M0_i_6 
       (.I0(app_wdf_data[306]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[306]),
        .O(\write_buffer.wr_buf_in_data [306]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[52].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [317:316]),
        .DIB(\write_buffer.wr_buf_in_data [315:314]),
        .DIC(\write_buffer.wr_buf_in_data [313:312]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[317:316]),
        .DOB(wr_buf_out_data_w[315:314]),
        .DOC(wr_buf_out_data_w[313:312]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[52].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[52].RAM32M0_i_1 
       (.I0(app_wdf_data[317]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[317]),
        .O(\write_buffer.wr_buf_in_data [317]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[52].RAM32M0_i_2 
       (.I0(app_wdf_data[316]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[316]),
        .O(\write_buffer.wr_buf_in_data [316]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[52].RAM32M0_i_3 
       (.I0(app_wdf_data[315]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[315]),
        .O(\write_buffer.wr_buf_in_data [315]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[52].RAM32M0_i_4 
       (.I0(app_wdf_data[314]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[314]),
        .O(\write_buffer.wr_buf_in_data [314]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[52].RAM32M0_i_5 
       (.I0(app_wdf_data[313]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[313]),
        .O(\write_buffer.wr_buf_in_data [313]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[52].RAM32M0_i_6 
       (.I0(app_wdf_data[312]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[312]),
        .O(\write_buffer.wr_buf_in_data [312]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[53].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [323:322]),
        .DIB(\write_buffer.wr_buf_in_data [321:320]),
        .DIC(\write_buffer.wr_buf_in_data [319:318]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[323:322]),
        .DOB(wr_buf_out_data_w[321:320]),
        .DOC(wr_buf_out_data_w[319:318]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[53].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[53].RAM32M0_i_1 
       (.I0(app_wdf_data[323]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[323]),
        .O(\write_buffer.wr_buf_in_data [323]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[53].RAM32M0_i_2 
       (.I0(app_wdf_data[322]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[322]),
        .O(\write_buffer.wr_buf_in_data [322]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[53].RAM32M0_i_3 
       (.I0(app_wdf_data[321]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[321]),
        .O(\write_buffer.wr_buf_in_data [321]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[53].RAM32M0_i_4 
       (.I0(app_wdf_data[320]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[320]),
        .O(\write_buffer.wr_buf_in_data [320]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[53].RAM32M0_i_5 
       (.I0(app_wdf_data[319]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[319]),
        .O(\write_buffer.wr_buf_in_data [319]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[53].RAM32M0_i_6 
       (.I0(app_wdf_data[318]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[318]),
        .O(\write_buffer.wr_buf_in_data [318]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[54].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [329:328]),
        .DIB(\write_buffer.wr_buf_in_data [327:326]),
        .DIC(\write_buffer.wr_buf_in_data [325:324]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[329:328]),
        .DOB(wr_buf_out_data_w[327:326]),
        .DOC(wr_buf_out_data_w[325:324]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[54].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[54].RAM32M0_i_1 
       (.I0(app_wdf_data[329]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[329]),
        .O(\write_buffer.wr_buf_in_data [329]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[54].RAM32M0_i_2 
       (.I0(app_wdf_data[328]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[328]),
        .O(\write_buffer.wr_buf_in_data [328]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[54].RAM32M0_i_3 
       (.I0(app_wdf_data[327]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[327]),
        .O(\write_buffer.wr_buf_in_data [327]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[54].RAM32M0_i_4 
       (.I0(app_wdf_data[326]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[326]),
        .O(\write_buffer.wr_buf_in_data [326]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[54].RAM32M0_i_5 
       (.I0(app_wdf_data[325]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[325]),
        .O(\write_buffer.wr_buf_in_data [325]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[54].RAM32M0_i_6 
       (.I0(app_wdf_data[324]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[324]),
        .O(\write_buffer.wr_buf_in_data [324]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[55].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [335:334]),
        .DIB(\write_buffer.wr_buf_in_data [333:332]),
        .DIC(\write_buffer.wr_buf_in_data [331:330]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[335:334]),
        .DOB(wr_buf_out_data_w[333:332]),
        .DOC(wr_buf_out_data_w[331:330]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[55].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[55].RAM32M0_i_1 
       (.I0(app_wdf_data[335]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[335]),
        .O(\write_buffer.wr_buf_in_data [335]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[55].RAM32M0_i_2 
       (.I0(app_wdf_data[334]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[334]),
        .O(\write_buffer.wr_buf_in_data [334]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[55].RAM32M0_i_3 
       (.I0(app_wdf_data[333]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[333]),
        .O(\write_buffer.wr_buf_in_data [333]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[55].RAM32M0_i_4 
       (.I0(app_wdf_data[332]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[332]),
        .O(\write_buffer.wr_buf_in_data [332]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[55].RAM32M0_i_5 
       (.I0(app_wdf_data[331]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[331]),
        .O(\write_buffer.wr_buf_in_data [331]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[55].RAM32M0_i_6 
       (.I0(app_wdf_data[330]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[330]),
        .O(\write_buffer.wr_buf_in_data [330]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[56].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [341:340]),
        .DIB(\write_buffer.wr_buf_in_data [339:338]),
        .DIC(\write_buffer.wr_buf_in_data [337:336]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[341:340]),
        .DOB(wr_buf_out_data_w[339:338]),
        .DOC(wr_buf_out_data_w[337:336]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[56].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[56].RAM32M0_i_1 
       (.I0(app_wdf_data[341]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[341]),
        .O(\write_buffer.wr_buf_in_data [341]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[56].RAM32M0_i_2 
       (.I0(app_wdf_data[340]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[340]),
        .O(\write_buffer.wr_buf_in_data [340]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[56].RAM32M0_i_3 
       (.I0(app_wdf_data[339]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[339]),
        .O(\write_buffer.wr_buf_in_data [339]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[56].RAM32M0_i_4 
       (.I0(app_wdf_data[338]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[338]),
        .O(\write_buffer.wr_buf_in_data [338]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[56].RAM32M0_i_5 
       (.I0(app_wdf_data[337]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[337]),
        .O(\write_buffer.wr_buf_in_data [337]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[56].RAM32M0_i_6 
       (.I0(app_wdf_data[336]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[336]),
        .O(\write_buffer.wr_buf_in_data [336]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[57].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [347:346]),
        .DIB(\write_buffer.wr_buf_in_data [345:344]),
        .DIC(\write_buffer.wr_buf_in_data [343:342]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[347:346]),
        .DOB(wr_buf_out_data_w[345:344]),
        .DOC(wr_buf_out_data_w[343:342]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[57].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[57].RAM32M0_i_1 
       (.I0(app_wdf_data[347]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[347]),
        .O(\write_buffer.wr_buf_in_data [347]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[57].RAM32M0_i_2 
       (.I0(app_wdf_data[346]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[346]),
        .O(\write_buffer.wr_buf_in_data [346]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[57].RAM32M0_i_3 
       (.I0(app_wdf_data[345]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[345]),
        .O(\write_buffer.wr_buf_in_data [345]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[57].RAM32M0_i_4 
       (.I0(app_wdf_data[344]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[344]),
        .O(\write_buffer.wr_buf_in_data [344]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[57].RAM32M0_i_5 
       (.I0(app_wdf_data[343]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[343]),
        .O(\write_buffer.wr_buf_in_data [343]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[57].RAM32M0_i_6 
       (.I0(app_wdf_data[342]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[342]),
        .O(\write_buffer.wr_buf_in_data [342]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[58].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [353:352]),
        .DIB(\write_buffer.wr_buf_in_data [351:350]),
        .DIC(\write_buffer.wr_buf_in_data [349:348]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[353:352]),
        .DOB(wr_buf_out_data_w[351:350]),
        .DOC(wr_buf_out_data_w[349:348]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[58].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[58].RAM32M0_i_1 
       (.I0(app_wdf_data[353]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[353]),
        .O(\write_buffer.wr_buf_in_data [353]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[58].RAM32M0_i_2 
       (.I0(app_wdf_data[352]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[352]),
        .O(\write_buffer.wr_buf_in_data [352]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[58].RAM32M0_i_3 
       (.I0(app_wdf_data[351]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[351]),
        .O(\write_buffer.wr_buf_in_data [351]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[58].RAM32M0_i_4 
       (.I0(app_wdf_data[350]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[350]),
        .O(\write_buffer.wr_buf_in_data [350]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[58].RAM32M0_i_5 
       (.I0(app_wdf_data[349]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[349]),
        .O(\write_buffer.wr_buf_in_data [349]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[58].RAM32M0_i_6 
       (.I0(app_wdf_data[348]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[348]),
        .O(\write_buffer.wr_buf_in_data [348]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[59].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [359:358]),
        .DIB(\write_buffer.wr_buf_in_data [357:356]),
        .DIC(\write_buffer.wr_buf_in_data [355:354]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[359:358]),
        .DOB(wr_buf_out_data_w[357:356]),
        .DOC(wr_buf_out_data_w[355:354]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[59].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[59].RAM32M0_i_1 
       (.I0(app_wdf_data[359]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[359]),
        .O(\write_buffer.wr_buf_in_data [359]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[59].RAM32M0_i_2 
       (.I0(app_wdf_data[358]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[358]),
        .O(\write_buffer.wr_buf_in_data [358]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[59].RAM32M0_i_3 
       (.I0(app_wdf_data[357]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[357]),
        .O(\write_buffer.wr_buf_in_data [357]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[59].RAM32M0_i_4 
       (.I0(app_wdf_data[356]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[356]),
        .O(\write_buffer.wr_buf_in_data [356]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[59].RAM32M0_i_5 
       (.I0(app_wdf_data[355]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[355]),
        .O(\write_buffer.wr_buf_in_data [355]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[59].RAM32M0_i_6 
       (.I0(app_wdf_data[354]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[354]),
        .O(\write_buffer.wr_buf_in_data [354]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[5].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [35:34]),
        .DIB(\write_buffer.wr_buf_in_data [33:32]),
        .DIC(\write_buffer.wr_buf_in_data [31:30]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[35:34]),
        .DOB(wr_buf_out_data_w[33:32]),
        .DOC(wr_buf_out_data_w[31:30]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[5].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[5].RAM32M0_i_1 
       (.I0(app_wdf_data[35]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[35]),
        .O(\write_buffer.wr_buf_in_data [35]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[5].RAM32M0_i_2 
       (.I0(app_wdf_data[34]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[34]),
        .O(\write_buffer.wr_buf_in_data [34]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[5].RAM32M0_i_3 
       (.I0(app_wdf_data[33]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[33]),
        .O(\write_buffer.wr_buf_in_data [33]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[5].RAM32M0_i_4 
       (.I0(app_wdf_data[32]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[32]),
        .O(\write_buffer.wr_buf_in_data [32]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[5].RAM32M0_i_5 
       (.I0(app_wdf_data[31]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[31]),
        .O(\write_buffer.wr_buf_in_data [31]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[5].RAM32M0_i_6 
       (.I0(app_wdf_data[30]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[30]),
        .O(\write_buffer.wr_buf_in_data [30]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[60].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [365:364]),
        .DIB(\write_buffer.wr_buf_in_data [363:362]),
        .DIC(\write_buffer.wr_buf_in_data [361:360]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[365:364]),
        .DOB(wr_buf_out_data_w[363:362]),
        .DOC(wr_buf_out_data_w[361:360]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[60].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[60].RAM32M0_i_1 
       (.I0(app_wdf_data[365]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[365]),
        .O(\write_buffer.wr_buf_in_data [365]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[60].RAM32M0_i_2 
       (.I0(app_wdf_data[364]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[364]),
        .O(\write_buffer.wr_buf_in_data [364]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[60].RAM32M0_i_3 
       (.I0(app_wdf_data[363]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[363]),
        .O(\write_buffer.wr_buf_in_data [363]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[60].RAM32M0_i_4 
       (.I0(app_wdf_data[362]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[362]),
        .O(\write_buffer.wr_buf_in_data [362]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[60].RAM32M0_i_5 
       (.I0(app_wdf_data[361]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[361]),
        .O(\write_buffer.wr_buf_in_data [361]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[60].RAM32M0_i_6 
       (.I0(app_wdf_data[360]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[360]),
        .O(\write_buffer.wr_buf_in_data [360]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[61].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [371:370]),
        .DIB(\write_buffer.wr_buf_in_data [369:368]),
        .DIC(\write_buffer.wr_buf_in_data [367:366]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[371:370]),
        .DOB(wr_buf_out_data_w[369:368]),
        .DOC(wr_buf_out_data_w[367:366]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[61].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[61].RAM32M0_i_1 
       (.I0(app_wdf_data[371]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[371]),
        .O(\write_buffer.wr_buf_in_data [371]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[61].RAM32M0_i_2 
       (.I0(app_wdf_data[370]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[370]),
        .O(\write_buffer.wr_buf_in_data [370]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[61].RAM32M0_i_3 
       (.I0(app_wdf_data[369]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[369]),
        .O(\write_buffer.wr_buf_in_data [369]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[61].RAM32M0_i_4 
       (.I0(app_wdf_data[368]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[368]),
        .O(\write_buffer.wr_buf_in_data [368]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[61].RAM32M0_i_5 
       (.I0(app_wdf_data[367]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[367]),
        .O(\write_buffer.wr_buf_in_data [367]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[61].RAM32M0_i_6 
       (.I0(app_wdf_data[366]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[366]),
        .O(\write_buffer.wr_buf_in_data [366]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[62].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [377:376]),
        .DIB(\write_buffer.wr_buf_in_data [375:374]),
        .DIC(\write_buffer.wr_buf_in_data [373:372]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[377:376]),
        .DOB(wr_buf_out_data_w[375:374]),
        .DOC(wr_buf_out_data_w[373:372]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[62].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[62].RAM32M0_i_1 
       (.I0(app_wdf_data[377]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[377]),
        .O(\write_buffer.wr_buf_in_data [377]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[62].RAM32M0_i_2 
       (.I0(app_wdf_data[376]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[376]),
        .O(\write_buffer.wr_buf_in_data [376]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[62].RAM32M0_i_3 
       (.I0(app_wdf_data[375]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[375]),
        .O(\write_buffer.wr_buf_in_data [375]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[62].RAM32M0_i_4 
       (.I0(app_wdf_data[374]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[374]),
        .O(\write_buffer.wr_buf_in_data [374]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[62].RAM32M0_i_5 
       (.I0(app_wdf_data[373]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[373]),
        .O(\write_buffer.wr_buf_in_data [373]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[62].RAM32M0_i_6 
       (.I0(app_wdf_data[372]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[372]),
        .O(\write_buffer.wr_buf_in_data [372]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[63].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [383:382]),
        .DIB(\write_buffer.wr_buf_in_data [381:380]),
        .DIC(\write_buffer.wr_buf_in_data [379:378]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[383:382]),
        .DOB(wr_buf_out_data_w[381:380]),
        .DOC(wr_buf_out_data_w[379:378]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[63].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[63].RAM32M0_i_1 
       (.I0(app_wdf_data[383]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[383]),
        .O(\write_buffer.wr_buf_in_data [383]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[63].RAM32M0_i_2 
       (.I0(app_wdf_data[382]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[382]),
        .O(\write_buffer.wr_buf_in_data [382]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[63].RAM32M0_i_3 
       (.I0(app_wdf_data[381]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[381]),
        .O(\write_buffer.wr_buf_in_data [381]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[63].RAM32M0_i_4 
       (.I0(app_wdf_data[380]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[380]),
        .O(\write_buffer.wr_buf_in_data [380]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[63].RAM32M0_i_5 
       (.I0(app_wdf_data[379]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[379]),
        .O(\write_buffer.wr_buf_in_data [379]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[63].RAM32M0_i_6 
       (.I0(app_wdf_data[378]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[378]),
        .O(\write_buffer.wr_buf_in_data [378]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[64].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [389:388]),
        .DIB(\write_buffer.wr_buf_in_data [387:386]),
        .DIC(\write_buffer.wr_buf_in_data [385:384]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[389:388]),
        .DOB(wr_buf_out_data_w[387:386]),
        .DOC(wr_buf_out_data_w[385:384]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[64].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[64].RAM32M0_i_1 
       (.I0(app_wdf_data[389]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[389]),
        .O(\write_buffer.wr_buf_in_data [389]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[64].RAM32M0_i_2 
       (.I0(app_wdf_data[388]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[388]),
        .O(\write_buffer.wr_buf_in_data [388]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[64].RAM32M0_i_3 
       (.I0(app_wdf_data[387]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[387]),
        .O(\write_buffer.wr_buf_in_data [387]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[64].RAM32M0_i_4 
       (.I0(app_wdf_data[386]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[386]),
        .O(\write_buffer.wr_buf_in_data [386]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[64].RAM32M0_i_5 
       (.I0(app_wdf_data[385]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[385]),
        .O(\write_buffer.wr_buf_in_data [385]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[64].RAM32M0_i_6 
       (.I0(app_wdf_data[384]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[384]),
        .O(\write_buffer.wr_buf_in_data [384]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[65].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [395:394]),
        .DIB(\write_buffer.wr_buf_in_data [393:392]),
        .DIC(\write_buffer.wr_buf_in_data [391:390]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[395:394]),
        .DOB(wr_buf_out_data_w[393:392]),
        .DOC(wr_buf_out_data_w[391:390]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[65].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[65].RAM32M0_i_1 
       (.I0(app_wdf_data[395]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[395]),
        .O(\write_buffer.wr_buf_in_data [395]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[65].RAM32M0_i_2 
       (.I0(app_wdf_data[394]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[394]),
        .O(\write_buffer.wr_buf_in_data [394]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[65].RAM32M0_i_3 
       (.I0(app_wdf_data[393]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[393]),
        .O(\write_buffer.wr_buf_in_data [393]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[65].RAM32M0_i_4 
       (.I0(app_wdf_data[392]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[392]),
        .O(\write_buffer.wr_buf_in_data [392]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[65].RAM32M0_i_5 
       (.I0(app_wdf_data[391]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[391]),
        .O(\write_buffer.wr_buf_in_data [391]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[65].RAM32M0_i_6 
       (.I0(app_wdf_data[390]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[390]),
        .O(\write_buffer.wr_buf_in_data [390]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[66].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [401:400]),
        .DIB(\write_buffer.wr_buf_in_data [399:398]),
        .DIC(\write_buffer.wr_buf_in_data [397:396]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[401:400]),
        .DOB(wr_buf_out_data_w[399:398]),
        .DOC(wr_buf_out_data_w[397:396]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[66].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[66].RAM32M0_i_1 
       (.I0(app_wdf_data[401]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[401]),
        .O(\write_buffer.wr_buf_in_data [401]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[66].RAM32M0_i_2 
       (.I0(app_wdf_data[400]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[400]),
        .O(\write_buffer.wr_buf_in_data [400]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[66].RAM32M0_i_3 
       (.I0(app_wdf_data[399]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[399]),
        .O(\write_buffer.wr_buf_in_data [399]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[66].RAM32M0_i_4 
       (.I0(app_wdf_data[398]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[398]),
        .O(\write_buffer.wr_buf_in_data [398]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[66].RAM32M0_i_5 
       (.I0(app_wdf_data[397]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[397]),
        .O(\write_buffer.wr_buf_in_data [397]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[66].RAM32M0_i_6 
       (.I0(app_wdf_data[396]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[396]),
        .O(\write_buffer.wr_buf_in_data [396]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[67].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [407:406]),
        .DIB(\write_buffer.wr_buf_in_data [405:404]),
        .DIC(\write_buffer.wr_buf_in_data [403:402]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[407:406]),
        .DOB(wr_buf_out_data_w[405:404]),
        .DOC(wr_buf_out_data_w[403:402]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[67].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[67].RAM32M0_i_1 
       (.I0(app_wdf_data[407]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[407]),
        .O(\write_buffer.wr_buf_in_data [407]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[67].RAM32M0_i_2 
       (.I0(app_wdf_data[406]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[406]),
        .O(\write_buffer.wr_buf_in_data [406]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[67].RAM32M0_i_3 
       (.I0(app_wdf_data[405]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[405]),
        .O(\write_buffer.wr_buf_in_data [405]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[67].RAM32M0_i_4 
       (.I0(app_wdf_data[404]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[404]),
        .O(\write_buffer.wr_buf_in_data [404]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[67].RAM32M0_i_5 
       (.I0(app_wdf_data[403]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[403]),
        .O(\write_buffer.wr_buf_in_data [403]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[67].RAM32M0_i_6 
       (.I0(app_wdf_data[402]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[402]),
        .O(\write_buffer.wr_buf_in_data [402]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[68].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [413:412]),
        .DIB(\write_buffer.wr_buf_in_data [411:410]),
        .DIC(\write_buffer.wr_buf_in_data [409:408]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[413:412]),
        .DOB(wr_buf_out_data_w[411:410]),
        .DOC(wr_buf_out_data_w[409:408]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[68].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[68].RAM32M0_i_1 
       (.I0(app_wdf_data[413]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[413]),
        .O(\write_buffer.wr_buf_in_data [413]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[68].RAM32M0_i_2 
       (.I0(app_wdf_data[412]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[412]),
        .O(\write_buffer.wr_buf_in_data [412]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[68].RAM32M0_i_3 
       (.I0(app_wdf_data[411]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[411]),
        .O(\write_buffer.wr_buf_in_data [411]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[68].RAM32M0_i_4 
       (.I0(app_wdf_data[410]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[410]),
        .O(\write_buffer.wr_buf_in_data [410]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[68].RAM32M0_i_5 
       (.I0(app_wdf_data[409]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[409]),
        .O(\write_buffer.wr_buf_in_data [409]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[68].RAM32M0_i_6 
       (.I0(app_wdf_data[408]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[408]),
        .O(\write_buffer.wr_buf_in_data [408]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[69].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [419:418]),
        .DIB(\write_buffer.wr_buf_in_data [417:416]),
        .DIC(\write_buffer.wr_buf_in_data [415:414]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[419:418]),
        .DOB(wr_buf_out_data_w[417:416]),
        .DOC(wr_buf_out_data_w[415:414]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[69].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[69].RAM32M0_i_1 
       (.I0(app_wdf_data[419]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[419]),
        .O(\write_buffer.wr_buf_in_data [419]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[69].RAM32M0_i_2 
       (.I0(app_wdf_data[418]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[418]),
        .O(\write_buffer.wr_buf_in_data [418]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[69].RAM32M0_i_3 
       (.I0(app_wdf_data[417]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[417]),
        .O(\write_buffer.wr_buf_in_data [417]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[69].RAM32M0_i_4 
       (.I0(app_wdf_data[416]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[416]),
        .O(\write_buffer.wr_buf_in_data [416]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[69].RAM32M0_i_5 
       (.I0(app_wdf_data[415]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[415]),
        .O(\write_buffer.wr_buf_in_data [415]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[69].RAM32M0_i_6 
       (.I0(app_wdf_data[414]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[414]),
        .O(\write_buffer.wr_buf_in_data [414]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[6].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [41:40]),
        .DIB(\write_buffer.wr_buf_in_data [39:38]),
        .DIC(\write_buffer.wr_buf_in_data [37:36]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[41:40]),
        .DOB(wr_buf_out_data_w[39:38]),
        .DOC(wr_buf_out_data_w[37:36]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[6].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[6].RAM32M0_i_1 
       (.I0(app_wdf_data[41]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[41]),
        .O(\write_buffer.wr_buf_in_data [41]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[6].RAM32M0_i_2 
       (.I0(app_wdf_data[40]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[40]),
        .O(\write_buffer.wr_buf_in_data [40]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[6].RAM32M0_i_3 
       (.I0(app_wdf_data[39]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[39]),
        .O(\write_buffer.wr_buf_in_data [39]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[6].RAM32M0_i_4 
       (.I0(app_wdf_data[38]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[38]),
        .O(\write_buffer.wr_buf_in_data [38]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[6].RAM32M0_i_5 
       (.I0(app_wdf_data[37]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[37]),
        .O(\write_buffer.wr_buf_in_data [37]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[6].RAM32M0_i_6 
       (.I0(app_wdf_data[36]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[36]),
        .O(\write_buffer.wr_buf_in_data [36]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[70].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [425:424]),
        .DIB(\write_buffer.wr_buf_in_data [423:422]),
        .DIC(\write_buffer.wr_buf_in_data [421:420]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[425:424]),
        .DOB(wr_buf_out_data_w[423:422]),
        .DOC(wr_buf_out_data_w[421:420]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[70].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[70].RAM32M0_i_1 
       (.I0(app_wdf_data[425]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[425]),
        .O(\write_buffer.wr_buf_in_data [425]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[70].RAM32M0_i_2 
       (.I0(app_wdf_data[424]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[424]),
        .O(\write_buffer.wr_buf_in_data [424]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[70].RAM32M0_i_3 
       (.I0(app_wdf_data[423]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[423]),
        .O(\write_buffer.wr_buf_in_data [423]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[70].RAM32M0_i_4 
       (.I0(app_wdf_data[422]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[422]),
        .O(\write_buffer.wr_buf_in_data [422]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[70].RAM32M0_i_5 
       (.I0(app_wdf_data[421]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[421]),
        .O(\write_buffer.wr_buf_in_data [421]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[70].RAM32M0_i_6 
       (.I0(app_wdf_data[420]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[420]),
        .O(\write_buffer.wr_buf_in_data [420]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[71].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [431:430]),
        .DIB(\write_buffer.wr_buf_in_data [429:428]),
        .DIC(\write_buffer.wr_buf_in_data [427:426]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[431:430]),
        .DOB(wr_buf_out_data_w[429:428]),
        .DOC(wr_buf_out_data_w[427:426]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[71].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[71].RAM32M0_i_1 
       (.I0(app_wdf_data[431]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[431]),
        .O(\write_buffer.wr_buf_in_data [431]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[71].RAM32M0_i_2 
       (.I0(app_wdf_data[430]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[430]),
        .O(\write_buffer.wr_buf_in_data [430]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[71].RAM32M0_i_3 
       (.I0(app_wdf_data[429]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[429]),
        .O(\write_buffer.wr_buf_in_data [429]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[71].RAM32M0_i_4 
       (.I0(app_wdf_data[428]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[428]),
        .O(\write_buffer.wr_buf_in_data [428]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[71].RAM32M0_i_5 
       (.I0(app_wdf_data[427]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[427]),
        .O(\write_buffer.wr_buf_in_data [427]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[71].RAM32M0_i_6 
       (.I0(app_wdf_data[426]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[426]),
        .O(\write_buffer.wr_buf_in_data [426]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[72].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [437:436]),
        .DIB(\write_buffer.wr_buf_in_data [435:434]),
        .DIC(\write_buffer.wr_buf_in_data [433:432]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[437:436]),
        .DOB(wr_buf_out_data_w[435:434]),
        .DOC(wr_buf_out_data_w[433:432]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[72].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[72].RAM32M0_i_1 
       (.I0(app_wdf_data[437]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[437]),
        .O(\write_buffer.wr_buf_in_data [437]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[72].RAM32M0_i_2 
       (.I0(app_wdf_data[436]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[436]),
        .O(\write_buffer.wr_buf_in_data [436]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[72].RAM32M0_i_3 
       (.I0(app_wdf_data[435]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[435]),
        .O(\write_buffer.wr_buf_in_data [435]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[72].RAM32M0_i_4 
       (.I0(app_wdf_data[434]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[434]),
        .O(\write_buffer.wr_buf_in_data [434]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[72].RAM32M0_i_5 
       (.I0(app_wdf_data[433]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[433]),
        .O(\write_buffer.wr_buf_in_data [433]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[72].RAM32M0_i_6 
       (.I0(app_wdf_data[432]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[432]),
        .O(\write_buffer.wr_buf_in_data [432]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[73].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [443:442]),
        .DIB(\write_buffer.wr_buf_in_data [441:440]),
        .DIC(\write_buffer.wr_buf_in_data [439:438]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[443:442]),
        .DOB(wr_buf_out_data_w[441:440]),
        .DOC(wr_buf_out_data_w[439:438]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[73].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[73].RAM32M0_i_1 
       (.I0(app_wdf_data[443]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[443]),
        .O(\write_buffer.wr_buf_in_data [443]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[73].RAM32M0_i_2 
       (.I0(app_wdf_data[442]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[442]),
        .O(\write_buffer.wr_buf_in_data [442]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[73].RAM32M0_i_3 
       (.I0(app_wdf_data[441]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[441]),
        .O(\write_buffer.wr_buf_in_data [441]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[73].RAM32M0_i_4 
       (.I0(app_wdf_data[440]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[440]),
        .O(\write_buffer.wr_buf_in_data [440]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[73].RAM32M0_i_5 
       (.I0(app_wdf_data[439]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[439]),
        .O(\write_buffer.wr_buf_in_data [439]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[73].RAM32M0_i_6 
       (.I0(app_wdf_data[438]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[438]),
        .O(\write_buffer.wr_buf_in_data [438]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[74].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [449:448]),
        .DIB(\write_buffer.wr_buf_in_data [447:446]),
        .DIC(\write_buffer.wr_buf_in_data [445:444]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[449:448]),
        .DOB(wr_buf_out_data_w[447:446]),
        .DOC(wr_buf_out_data_w[445:444]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[74].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[74].RAM32M0_i_1 
       (.I0(app_wdf_data[449]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[449]),
        .O(\write_buffer.wr_buf_in_data [449]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[74].RAM32M0_i_2 
       (.I0(app_wdf_data[448]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[448]),
        .O(\write_buffer.wr_buf_in_data [448]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[74].RAM32M0_i_3 
       (.I0(app_wdf_data[447]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[447]),
        .O(\write_buffer.wr_buf_in_data [447]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[74].RAM32M0_i_4 
       (.I0(app_wdf_data[446]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[446]),
        .O(\write_buffer.wr_buf_in_data [446]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[74].RAM32M0_i_5 
       (.I0(app_wdf_data[445]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[445]),
        .O(\write_buffer.wr_buf_in_data [445]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[74].RAM32M0_i_6 
       (.I0(app_wdf_data[444]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[444]),
        .O(\write_buffer.wr_buf_in_data [444]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[75].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [455:454]),
        .DIB(\write_buffer.wr_buf_in_data [453:452]),
        .DIC(\write_buffer.wr_buf_in_data [451:450]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[455:454]),
        .DOB(wr_buf_out_data_w[453:452]),
        .DOC(wr_buf_out_data_w[451:450]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[75].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[75].RAM32M0_i_1 
       (.I0(app_wdf_data[455]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[455]),
        .O(\write_buffer.wr_buf_in_data [455]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[75].RAM32M0_i_2 
       (.I0(app_wdf_data[454]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[454]),
        .O(\write_buffer.wr_buf_in_data [454]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[75].RAM32M0_i_3 
       (.I0(app_wdf_data[453]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[453]),
        .O(\write_buffer.wr_buf_in_data [453]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[75].RAM32M0_i_4 
       (.I0(app_wdf_data[452]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[452]),
        .O(\write_buffer.wr_buf_in_data [452]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[75].RAM32M0_i_5 
       (.I0(app_wdf_data[451]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[451]),
        .O(\write_buffer.wr_buf_in_data [451]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[75].RAM32M0_i_6 
       (.I0(app_wdf_data[450]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[450]),
        .O(\write_buffer.wr_buf_in_data [450]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[76].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [461:460]),
        .DIB(\write_buffer.wr_buf_in_data [459:458]),
        .DIC(\write_buffer.wr_buf_in_data [457:456]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[461:460]),
        .DOB(wr_buf_out_data_w[459:458]),
        .DOC(wr_buf_out_data_w[457:456]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[76].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[76].RAM32M0_i_1 
       (.I0(app_wdf_data[461]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[461]),
        .O(\write_buffer.wr_buf_in_data [461]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[76].RAM32M0_i_2 
       (.I0(app_wdf_data[460]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[460]),
        .O(\write_buffer.wr_buf_in_data [460]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[76].RAM32M0_i_3 
       (.I0(app_wdf_data[459]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[459]),
        .O(\write_buffer.wr_buf_in_data [459]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[76].RAM32M0_i_4 
       (.I0(app_wdf_data[458]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[458]),
        .O(\write_buffer.wr_buf_in_data [458]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[76].RAM32M0_i_5 
       (.I0(app_wdf_data[457]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[457]),
        .O(\write_buffer.wr_buf_in_data [457]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[76].RAM32M0_i_6 
       (.I0(app_wdf_data[456]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[456]),
        .O(\write_buffer.wr_buf_in_data [456]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[77].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [467:466]),
        .DIB(\write_buffer.wr_buf_in_data [465:464]),
        .DIC(\write_buffer.wr_buf_in_data [463:462]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[467:466]),
        .DOB(wr_buf_out_data_w[465:464]),
        .DOC(wr_buf_out_data_w[463:462]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[77].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[77].RAM32M0_i_1 
       (.I0(app_wdf_data[467]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[467]),
        .O(\write_buffer.wr_buf_in_data [467]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[77].RAM32M0_i_2 
       (.I0(app_wdf_data[466]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[466]),
        .O(\write_buffer.wr_buf_in_data [466]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[77].RAM32M0_i_3 
       (.I0(app_wdf_data[465]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[465]),
        .O(\write_buffer.wr_buf_in_data [465]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[77].RAM32M0_i_4 
       (.I0(app_wdf_data[464]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[464]),
        .O(\write_buffer.wr_buf_in_data [464]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[77].RAM32M0_i_5 
       (.I0(app_wdf_data[463]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[463]),
        .O(\write_buffer.wr_buf_in_data [463]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[77].RAM32M0_i_6 
       (.I0(app_wdf_data[462]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[462]),
        .O(\write_buffer.wr_buf_in_data [462]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[78].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [473:472]),
        .DIB(\write_buffer.wr_buf_in_data [471:470]),
        .DIC(\write_buffer.wr_buf_in_data [469:468]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[473:472]),
        .DOB(wr_buf_out_data_w[471:470]),
        .DOC(wr_buf_out_data_w[469:468]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[78].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[78].RAM32M0_i_1 
       (.I0(app_wdf_data[473]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[473]),
        .O(\write_buffer.wr_buf_in_data [473]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[78].RAM32M0_i_2 
       (.I0(app_wdf_data[472]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[472]),
        .O(\write_buffer.wr_buf_in_data [472]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[78].RAM32M0_i_3 
       (.I0(app_wdf_data[471]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[471]),
        .O(\write_buffer.wr_buf_in_data [471]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[78].RAM32M0_i_4 
       (.I0(app_wdf_data[470]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[470]),
        .O(\write_buffer.wr_buf_in_data [470]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[78].RAM32M0_i_5 
       (.I0(app_wdf_data[469]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[469]),
        .O(\write_buffer.wr_buf_in_data [469]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[78].RAM32M0_i_6 
       (.I0(app_wdf_data[468]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[468]),
        .O(\write_buffer.wr_buf_in_data [468]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[79].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [479:478]),
        .DIB(\write_buffer.wr_buf_in_data [477:476]),
        .DIC(\write_buffer.wr_buf_in_data [475:474]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[479:478]),
        .DOB(wr_buf_out_data_w[477:476]),
        .DOC(wr_buf_out_data_w[475:474]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[79].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[79].RAM32M0_i_1 
       (.I0(app_wdf_data[479]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[479]),
        .O(\write_buffer.wr_buf_in_data [479]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[79].RAM32M0_i_2 
       (.I0(app_wdf_data[478]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[478]),
        .O(\write_buffer.wr_buf_in_data [478]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[79].RAM32M0_i_3 
       (.I0(app_wdf_data[477]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[477]),
        .O(\write_buffer.wr_buf_in_data [477]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[79].RAM32M0_i_4 
       (.I0(app_wdf_data[476]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[476]),
        .O(\write_buffer.wr_buf_in_data [476]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[79].RAM32M0_i_5 
       (.I0(app_wdf_data[475]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[475]),
        .O(\write_buffer.wr_buf_in_data [475]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[79].RAM32M0_i_6 
       (.I0(app_wdf_data[474]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[474]),
        .O(\write_buffer.wr_buf_in_data [474]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[7].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [47:46]),
        .DIB(\write_buffer.wr_buf_in_data [45:44]),
        .DIC(\write_buffer.wr_buf_in_data [43:42]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[47:46]),
        .DOB(wr_buf_out_data_w[45:44]),
        .DOC(wr_buf_out_data_w[43:42]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[7].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[7].RAM32M0_i_1 
       (.I0(app_wdf_data[47]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[47]),
        .O(\write_buffer.wr_buf_in_data [47]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[7].RAM32M0_i_2 
       (.I0(app_wdf_data[46]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[46]),
        .O(\write_buffer.wr_buf_in_data [46]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[7].RAM32M0_i_3 
       (.I0(app_wdf_data[45]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[45]),
        .O(\write_buffer.wr_buf_in_data [45]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[7].RAM32M0_i_4 
       (.I0(app_wdf_data[44]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[44]),
        .O(\write_buffer.wr_buf_in_data [44]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[7].RAM32M0_i_5 
       (.I0(app_wdf_data[43]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[43]),
        .O(\write_buffer.wr_buf_in_data [43]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[7].RAM32M0_i_6 
       (.I0(app_wdf_data[42]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[42]),
        .O(\write_buffer.wr_buf_in_data [42]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[80].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [485:484]),
        .DIB(\write_buffer.wr_buf_in_data [483:482]),
        .DIC(\write_buffer.wr_buf_in_data [481:480]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[485:484]),
        .DOB(wr_buf_out_data_w[483:482]),
        .DOC(wr_buf_out_data_w[481:480]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[80].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[80].RAM32M0_i_1 
       (.I0(app_wdf_data[485]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[485]),
        .O(\write_buffer.wr_buf_in_data [485]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[80].RAM32M0_i_2 
       (.I0(app_wdf_data[484]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[484]),
        .O(\write_buffer.wr_buf_in_data [484]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[80].RAM32M0_i_3 
       (.I0(app_wdf_data[483]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[483]),
        .O(\write_buffer.wr_buf_in_data [483]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[80].RAM32M0_i_4 
       (.I0(app_wdf_data[482]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[482]),
        .O(\write_buffer.wr_buf_in_data [482]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[80].RAM32M0_i_5 
       (.I0(app_wdf_data[481]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[481]),
        .O(\write_buffer.wr_buf_in_data [481]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[80].RAM32M0_i_6 
       (.I0(app_wdf_data[480]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[480]),
        .O(\write_buffer.wr_buf_in_data [480]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[81].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [491:490]),
        .DIB(\write_buffer.wr_buf_in_data [489:488]),
        .DIC(\write_buffer.wr_buf_in_data [487:486]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[491:490]),
        .DOB(wr_buf_out_data_w[489:488]),
        .DOC(wr_buf_out_data_w[487:486]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[81].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[81].RAM32M0_i_1 
       (.I0(app_wdf_data[491]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[491]),
        .O(\write_buffer.wr_buf_in_data [491]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[81].RAM32M0_i_2 
       (.I0(app_wdf_data[490]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[490]),
        .O(\write_buffer.wr_buf_in_data [490]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[81].RAM32M0_i_3 
       (.I0(app_wdf_data[489]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[489]),
        .O(\write_buffer.wr_buf_in_data [489]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[81].RAM32M0_i_4 
       (.I0(app_wdf_data[488]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[488]),
        .O(\write_buffer.wr_buf_in_data [488]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[81].RAM32M0_i_5 
       (.I0(app_wdf_data[487]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[487]),
        .O(\write_buffer.wr_buf_in_data [487]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[81].RAM32M0_i_6 
       (.I0(app_wdf_data[486]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[486]),
        .O(\write_buffer.wr_buf_in_data [486]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[82].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [497:496]),
        .DIB(\write_buffer.wr_buf_in_data [495:494]),
        .DIC(\write_buffer.wr_buf_in_data [493:492]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[497:496]),
        .DOB(wr_buf_out_data_w[495:494]),
        .DOC(wr_buf_out_data_w[493:492]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[82].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[82].RAM32M0_i_1 
       (.I0(app_wdf_data[497]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[497]),
        .O(\write_buffer.wr_buf_in_data [497]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[82].RAM32M0_i_2 
       (.I0(app_wdf_data[496]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[496]),
        .O(\write_buffer.wr_buf_in_data [496]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[82].RAM32M0_i_3 
       (.I0(app_wdf_data[495]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[495]),
        .O(\write_buffer.wr_buf_in_data [495]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[82].RAM32M0_i_4 
       (.I0(app_wdf_data[494]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[494]),
        .O(\write_buffer.wr_buf_in_data [494]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[82].RAM32M0_i_5 
       (.I0(app_wdf_data[493]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[493]),
        .O(\write_buffer.wr_buf_in_data [493]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[82].RAM32M0_i_6 
       (.I0(app_wdf_data[492]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[492]),
        .O(\write_buffer.wr_buf_in_data [492]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[83].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [503:502]),
        .DIB(\write_buffer.wr_buf_in_data [501:500]),
        .DIC(\write_buffer.wr_buf_in_data [499:498]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[503:502]),
        .DOB(wr_buf_out_data_w[501:500]),
        .DOC(wr_buf_out_data_w[499:498]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[83].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[83].RAM32M0_i_1 
       (.I0(app_wdf_data[503]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[503]),
        .O(\write_buffer.wr_buf_in_data [503]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[83].RAM32M0_i_2 
       (.I0(app_wdf_data[502]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[502]),
        .O(\write_buffer.wr_buf_in_data [502]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[83].RAM32M0_i_3 
       (.I0(app_wdf_data[501]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[501]),
        .O(\write_buffer.wr_buf_in_data [501]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[83].RAM32M0_i_4 
       (.I0(app_wdf_data[500]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[500]),
        .O(\write_buffer.wr_buf_in_data [500]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[83].RAM32M0_i_5 
       (.I0(app_wdf_data[499]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[499]),
        .O(\write_buffer.wr_buf_in_data [499]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[83].RAM32M0_i_6 
       (.I0(app_wdf_data[498]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[498]),
        .O(\write_buffer.wr_buf_in_data [498]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[84].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [509:508]),
        .DIB(\write_buffer.wr_buf_in_data [507:506]),
        .DIC(\write_buffer.wr_buf_in_data [505:504]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[509:508]),
        .DOB(wr_buf_out_data_w[507:506]),
        .DOC(wr_buf_out_data_w[505:504]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[84].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[84].RAM32M0_i_1 
       (.I0(app_wdf_data[509]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[509]),
        .O(\write_buffer.wr_buf_in_data [509]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[84].RAM32M0_i_2 
       (.I0(app_wdf_data[508]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[508]),
        .O(\write_buffer.wr_buf_in_data [508]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[84].RAM32M0_i_3 
       (.I0(app_wdf_data[507]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[507]),
        .O(\write_buffer.wr_buf_in_data [507]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[84].RAM32M0_i_4 
       (.I0(app_wdf_data[506]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[506]),
        .O(\write_buffer.wr_buf_in_data [506]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[84].RAM32M0_i_5 
       (.I0(app_wdf_data[505]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[505]),
        .O(\write_buffer.wr_buf_in_data [505]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[84].RAM32M0_i_6 
       (.I0(app_wdf_data[504]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[504]),
        .O(\write_buffer.wr_buf_in_data [504]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[85].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [515:514]),
        .DIB(\write_buffer.wr_buf_in_data [513:512]),
        .DIC(\write_buffer.wr_buf_in_data [511:510]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[515:514]),
        .DOB(wr_buf_out_data_w[513:512]),
        .DOC(wr_buf_out_data_w[511:510]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[85].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[85].RAM32M0_i_1 
       (.I0(app_wdf_mask[3]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[3]),
        .O(\write_buffer.wr_buf_in_data [515]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[85].RAM32M0_i_2 
       (.I0(app_wdf_mask[2]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[2]),
        .O(\write_buffer.wr_buf_in_data [514]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[85].RAM32M0_i_3 
       (.I0(app_wdf_mask[1]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[1]),
        .O(\write_buffer.wr_buf_in_data [513]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[85].RAM32M0_i_4 
       (.I0(app_wdf_mask[0]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[0]),
        .O(\write_buffer.wr_buf_in_data [512]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[85].RAM32M0_i_5 
       (.I0(app_wdf_data[511]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[511]),
        .O(\write_buffer.wr_buf_in_data [511]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[85].RAM32M0_i_6 
       (.I0(app_wdf_data[510]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[510]),
        .O(\write_buffer.wr_buf_in_data [510]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[86].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [521:520]),
        .DIB(\write_buffer.wr_buf_in_data [519:518]),
        .DIC(\write_buffer.wr_buf_in_data [517:516]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[521:520]),
        .DOB(wr_buf_out_data_w[519:518]),
        .DOC(wr_buf_out_data_w[517:516]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[86].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[86].RAM32M0_i_1 
       (.I0(app_wdf_mask[9]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[9]),
        .O(\write_buffer.wr_buf_in_data [521]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[86].RAM32M0_i_2 
       (.I0(app_wdf_mask[8]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[8]),
        .O(\write_buffer.wr_buf_in_data [520]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[86].RAM32M0_i_3 
       (.I0(app_wdf_mask[7]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[7]),
        .O(\write_buffer.wr_buf_in_data [519]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[86].RAM32M0_i_4 
       (.I0(app_wdf_mask[6]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[6]),
        .O(\write_buffer.wr_buf_in_data [518]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[86].RAM32M0_i_5 
       (.I0(app_wdf_mask[5]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[5]),
        .O(\write_buffer.wr_buf_in_data [517]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[86].RAM32M0_i_6 
       (.I0(app_wdf_mask[4]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[4]),
        .O(\write_buffer.wr_buf_in_data [516]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[87].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [527:526]),
        .DIB(\write_buffer.wr_buf_in_data [525:524]),
        .DIC(\write_buffer.wr_buf_in_data [523:522]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[527:526]),
        .DOB(wr_buf_out_data_w[525:524]),
        .DOC(wr_buf_out_data_w[523:522]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[87].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[87].RAM32M0_i_1 
       (.I0(app_wdf_mask[15]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[15]),
        .O(\write_buffer.wr_buf_in_data [527]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[87].RAM32M0_i_2 
       (.I0(app_wdf_mask[14]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[14]),
        .O(\write_buffer.wr_buf_in_data [526]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[87].RAM32M0_i_3 
       (.I0(app_wdf_mask[13]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[13]),
        .O(\write_buffer.wr_buf_in_data [525]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[87].RAM32M0_i_4 
       (.I0(app_wdf_mask[12]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[12]),
        .O(\write_buffer.wr_buf_in_data [524]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[87].RAM32M0_i_5 
       (.I0(app_wdf_mask[11]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[11]),
        .O(\write_buffer.wr_buf_in_data [523]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[87].RAM32M0_i_6 
       (.I0(app_wdf_mask[10]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[10]),
        .O(\write_buffer.wr_buf_in_data [522]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[88].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [533:532]),
        .DIB(\write_buffer.wr_buf_in_data [531:530]),
        .DIC(\write_buffer.wr_buf_in_data [529:528]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[533:532]),
        .DOB(wr_buf_out_data_w[531:530]),
        .DOC(wr_buf_out_data_w[529:528]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[88].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[88].RAM32M0_i_1 
       (.I0(app_wdf_mask[21]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[21]),
        .O(\write_buffer.wr_buf_in_data [533]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[88].RAM32M0_i_2 
       (.I0(app_wdf_mask[20]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[20]),
        .O(\write_buffer.wr_buf_in_data [532]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[88].RAM32M0_i_3 
       (.I0(app_wdf_mask[19]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[19]),
        .O(\write_buffer.wr_buf_in_data [531]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[88].RAM32M0_i_4 
       (.I0(app_wdf_mask[18]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[18]),
        .O(\write_buffer.wr_buf_in_data [530]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[88].RAM32M0_i_5 
       (.I0(app_wdf_mask[17]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[17]),
        .O(\write_buffer.wr_buf_in_data [529]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[88].RAM32M0_i_6 
       (.I0(app_wdf_mask[16]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[16]),
        .O(\write_buffer.wr_buf_in_data [528]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[89].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [539:538]),
        .DIB(\write_buffer.wr_buf_in_data [537:536]),
        .DIC(\write_buffer.wr_buf_in_data [535:534]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[539:538]),
        .DOB(wr_buf_out_data_w[537:536]),
        .DOC(wr_buf_out_data_w[535:534]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[89].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[89].RAM32M0_i_1 
       (.I0(app_wdf_mask[27]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[27]),
        .O(\write_buffer.wr_buf_in_data [539]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[89].RAM32M0_i_2 
       (.I0(app_wdf_mask[26]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[26]),
        .O(\write_buffer.wr_buf_in_data [538]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[89].RAM32M0_i_3 
       (.I0(app_wdf_mask[25]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[25]),
        .O(\write_buffer.wr_buf_in_data [537]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[89].RAM32M0_i_4 
       (.I0(app_wdf_mask[24]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[24]),
        .O(\write_buffer.wr_buf_in_data [536]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[89].RAM32M0_i_5 
       (.I0(app_wdf_mask[23]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[23]),
        .O(\write_buffer.wr_buf_in_data [535]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[89].RAM32M0_i_6 
       (.I0(app_wdf_mask[22]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[22]),
        .O(\write_buffer.wr_buf_in_data [534]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[8].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [53:52]),
        .DIB(\write_buffer.wr_buf_in_data [51:50]),
        .DIC(\write_buffer.wr_buf_in_data [49:48]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[53:52]),
        .DOB(wr_buf_out_data_w[51:50]),
        .DOC(wr_buf_out_data_w[49:48]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[8].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[8].RAM32M0_i_1 
       (.I0(app_wdf_data[53]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[53]),
        .O(\write_buffer.wr_buf_in_data [53]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[8].RAM32M0_i_2 
       (.I0(app_wdf_data[52]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[52]),
        .O(\write_buffer.wr_buf_in_data [52]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[8].RAM32M0_i_3 
       (.I0(app_wdf_data[51]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[51]),
        .O(\write_buffer.wr_buf_in_data [51]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[8].RAM32M0_i_4 
       (.I0(app_wdf_data[50]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[50]),
        .O(\write_buffer.wr_buf_in_data [50]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[8].RAM32M0_i_5 
       (.I0(app_wdf_data[49]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[49]),
        .O(\write_buffer.wr_buf_in_data [49]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[8].RAM32M0_i_6 
       (.I0(app_wdf_data[48]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[48]),
        .O(\write_buffer.wr_buf_in_data [48]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[90].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [545:544]),
        .DIB(\write_buffer.wr_buf_in_data [543:542]),
        .DIC(\write_buffer.wr_buf_in_data [541:540]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[545:544]),
        .DOB(wr_buf_out_data_w[543:542]),
        .DOC(wr_buf_out_data_w[541:540]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[90].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[90].RAM32M0_i_1 
       (.I0(app_wdf_mask[33]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[33]),
        .O(\write_buffer.wr_buf_in_data [545]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[90].RAM32M0_i_2 
       (.I0(app_wdf_mask[32]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[32]),
        .O(\write_buffer.wr_buf_in_data [544]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[90].RAM32M0_i_3 
       (.I0(app_wdf_mask[31]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[31]),
        .O(\write_buffer.wr_buf_in_data [543]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[90].RAM32M0_i_4 
       (.I0(app_wdf_mask[30]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[30]),
        .O(\write_buffer.wr_buf_in_data [542]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[90].RAM32M0_i_5 
       (.I0(app_wdf_mask[29]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[29]),
        .O(\write_buffer.wr_buf_in_data [541]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[90].RAM32M0_i_6 
       (.I0(app_wdf_mask[28]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[28]),
        .O(\write_buffer.wr_buf_in_data [540]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[91].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [551:550]),
        .DIB(\write_buffer.wr_buf_in_data [549:548]),
        .DIC(\write_buffer.wr_buf_in_data [547:546]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[551:550]),
        .DOB(wr_buf_out_data_w[549:548]),
        .DOC(wr_buf_out_data_w[547:546]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[91].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[91].RAM32M0_i_1 
       (.I0(app_wdf_mask[39]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[39]),
        .O(\write_buffer.wr_buf_in_data [551]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[91].RAM32M0_i_2 
       (.I0(app_wdf_mask[38]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[38]),
        .O(\write_buffer.wr_buf_in_data [550]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[91].RAM32M0_i_3 
       (.I0(app_wdf_mask[37]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[37]),
        .O(\write_buffer.wr_buf_in_data [549]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[91].RAM32M0_i_4 
       (.I0(app_wdf_mask[36]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[36]),
        .O(\write_buffer.wr_buf_in_data [548]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[91].RAM32M0_i_5 
       (.I0(app_wdf_mask[35]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[35]),
        .O(\write_buffer.wr_buf_in_data [547]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[91].RAM32M0_i_6 
       (.I0(app_wdf_mask[34]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[34]),
        .O(\write_buffer.wr_buf_in_data [546]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[92].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [557:556]),
        .DIB(\write_buffer.wr_buf_in_data [555:554]),
        .DIC(\write_buffer.wr_buf_in_data [553:552]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[557:556]),
        .DOB(wr_buf_out_data_w[555:554]),
        .DOC(wr_buf_out_data_w[553:552]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[92].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[92].RAM32M0_i_1 
       (.I0(app_wdf_mask[45]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[45]),
        .O(\write_buffer.wr_buf_in_data [557]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[92].RAM32M0_i_2 
       (.I0(app_wdf_mask[44]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[44]),
        .O(\write_buffer.wr_buf_in_data [556]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[92].RAM32M0_i_3 
       (.I0(app_wdf_mask[43]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[43]),
        .O(\write_buffer.wr_buf_in_data [555]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[92].RAM32M0_i_4 
       (.I0(app_wdf_mask[42]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[42]),
        .O(\write_buffer.wr_buf_in_data [554]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[92].RAM32M0_i_5 
       (.I0(app_wdf_mask[41]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[41]),
        .O(\write_buffer.wr_buf_in_data [553]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[92].RAM32M0_i_6 
       (.I0(app_wdf_mask[40]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[40]),
        .O(\write_buffer.wr_buf_in_data [552]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[93].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [563:562]),
        .DIB(\write_buffer.wr_buf_in_data [561:560]),
        .DIC(\write_buffer.wr_buf_in_data [559:558]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[563:562]),
        .DOB(wr_buf_out_data_w[561:560]),
        .DOC(wr_buf_out_data_w[559:558]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[93].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[93].RAM32M0_i_1 
       (.I0(app_wdf_mask[51]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[51]),
        .O(\write_buffer.wr_buf_in_data [563]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[93].RAM32M0_i_2 
       (.I0(app_wdf_mask[50]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[50]),
        .O(\write_buffer.wr_buf_in_data [562]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[93].RAM32M0_i_3 
       (.I0(app_wdf_mask[49]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[49]),
        .O(\write_buffer.wr_buf_in_data [561]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[93].RAM32M0_i_4 
       (.I0(app_wdf_mask[48]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[48]),
        .O(\write_buffer.wr_buf_in_data [560]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[93].RAM32M0_i_5 
       (.I0(app_wdf_mask[47]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[47]),
        .O(\write_buffer.wr_buf_in_data [559]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[93].RAM32M0_i_6 
       (.I0(app_wdf_mask[46]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[46]),
        .O(\write_buffer.wr_buf_in_data [558]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[94].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [569:568]),
        .DIB(\write_buffer.wr_buf_in_data [567:566]),
        .DIC(\write_buffer.wr_buf_in_data [565:564]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[569:568]),
        .DOB(wr_buf_out_data_w[567:566]),
        .DOC(wr_buf_out_data_w[565:564]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[94].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[94].RAM32M0_i_1 
       (.I0(app_wdf_mask[57]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[57]),
        .O(\write_buffer.wr_buf_in_data [569]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[94].RAM32M0_i_2 
       (.I0(app_wdf_mask[56]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[56]),
        .O(\write_buffer.wr_buf_in_data [568]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[94].RAM32M0_i_3 
       (.I0(app_wdf_mask[55]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[55]),
        .O(\write_buffer.wr_buf_in_data [567]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[94].RAM32M0_i_4 
       (.I0(app_wdf_mask[54]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[54]),
        .O(\write_buffer.wr_buf_in_data [566]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[94].RAM32M0_i_5 
       (.I0(app_wdf_mask[53]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[53]),
        .O(\write_buffer.wr_buf_in_data [565]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[94].RAM32M0_i_6 
       (.I0(app_wdf_mask[52]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[52]),
        .O(\write_buffer.wr_buf_in_data [564]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[95].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [575:574]),
        .DIB(\write_buffer.wr_buf_in_data [573:572]),
        .DIC(\write_buffer.wr_buf_in_data [571:570]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[575:574]),
        .DOB(wr_buf_out_data_w[573:572]),
        .DOC(wr_buf_out_data_w[571:570]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[95].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[95].RAM32M0_i_1 
       (.I0(app_wdf_mask[63]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[63]),
        .O(\write_buffer.wr_buf_in_data [575]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[95].RAM32M0_i_2 
       (.I0(app_wdf_mask[62]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[62]),
        .O(\write_buffer.wr_buf_in_data [574]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[95].RAM32M0_i_3 
       (.I0(app_wdf_mask[61]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[61]),
        .O(\write_buffer.wr_buf_in_data [573]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[95].RAM32M0_i_4 
       (.I0(app_wdf_mask[60]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[60]),
        .O(\write_buffer.wr_buf_in_data [572]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[95].RAM32M0_i_5 
       (.I0(app_wdf_mask[59]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[59]),
        .O(\write_buffer.wr_buf_in_data [571]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[95].RAM32M0_i_6 
       (.I0(app_wdf_mask[58]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_mask_r1[58]),
        .O(\write_buffer.wr_buf_in_data [570]));
  (* BOX_TYPE = "PRIMITIVE" *) 
  RAM32M #(
    .INIT_A(64'h0000000000000000),
    .INIT_B(64'h0000000000000000),
    .INIT_C(64'h0000000000000000),
    .INIT_D(64'h0000000000000000),
    .IS_WCLK_INVERTED(1'b0)) 
    \write_buffer.wr_buffer_ram[9].RAM32M0 
       (.ADDRA({wr_data_addr,1'b0}),
        .ADDRB({wr_data_addr,1'b0}),
        .ADDRC({wr_data_addr,1'b0}),
        .ADDRD({wb_wr_data_addr_w,\write_data_control.wb_wr_data_addr0_ns }),
        .DIA(\write_buffer.wr_buf_in_data [59:58]),
        .DIB(\write_buffer.wr_buf_in_data [57:56]),
        .DIC(\write_buffer.wr_buf_in_data [55:54]),
        .DID({1'b0,1'b0}),
        .DOA(wr_buf_out_data_w[59:58]),
        .DOB(wr_buf_out_data_w[57:56]),
        .DOC(wr_buf_out_data_w[55:54]),
        .DOD(\NLW_write_buffer.wr_buffer_ram[9].RAM32M0_DOD_UNCONNECTED [1:0]),
        .WCLK(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .WE(wdf_rdy_ns));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[9].RAM32M0_i_1 
       (.I0(app_wdf_data[59]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[59]),
        .O(\write_buffer.wr_buf_in_data [59]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[9].RAM32M0_i_2 
       (.I0(app_wdf_data[58]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[58]),
        .O(\write_buffer.wr_buf_in_data [58]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[9].RAM32M0_i_3 
       (.I0(app_wdf_data[57]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[57]),
        .O(\write_buffer.wr_buf_in_data [57]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[9].RAM32M0_i_4 
       (.I0(app_wdf_data[56]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[56]),
        .O(\write_buffer.wr_buf_in_data [56]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[9].RAM32M0_i_5 
       (.I0(app_wdf_data[55]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[55]),
        .O(\write_buffer.wr_buf_in_data [55]));
  LUT3 #(
    .INIT(8'hB8)) 
    \write_buffer.wr_buffer_ram[9].RAM32M0_i_6 
       (.I0(app_wdf_data[54]),
        .I1(app_wdf_rdy_r_copy2),
        .I2(app_wdf_data_r1[54]),
        .O(\write_buffer.wr_buf_in_data [54]));
  FDRE \write_data_control.wb_wr_data_addr0_r_reg 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(\write_data_control.wb_wr_data_addr0_ns ),
        .Q(\write_data_control.wb_wr_data_addr0_r ),
        .R(1'b0));
  FDRE \write_data_control.wb_wr_data_addr_r_reg[1] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wb_wr_data_addr_w[1]),
        .Q(\write_data_control.wb_wr_data_addr_r [1]),
        .R(1'b0));
  FDRE \write_data_control.wb_wr_data_addr_r_reg[2] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wb_wr_data_addr_w[2]),
        .Q(\write_data_control.wb_wr_data_addr_r [2]),
        .R(1'b0));
  FDRE \write_data_control.wb_wr_data_addr_r_reg[3] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wb_wr_data_addr_w[3]),
        .Q(\write_data_control.wb_wr_data_addr_r [3]),
        .R(1'b0));
  FDRE \write_data_control.wb_wr_data_addr_r_reg[4] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(1'b1),
        .D(wb_wr_data_addr_w[4]),
        .Q(\write_data_control.wb_wr_data_addr_r [4]),
        .R(1'b0));
  LUT1 #(
    .INIT(2'h1)) 
    \write_data_control.wr_data_indx_r[0]_i_1 
       (.I0(\write_data_control.wr_data_indx_r_reg [0]),
        .O(p_0_in__0__0[0]));
  LUT2 #(
    .INIT(4'h6)) 
    \write_data_control.wr_data_indx_r[1]_i_1 
       (.I0(\write_data_control.wr_data_indx_r_reg [0]),
        .I1(\write_data_control.wr_data_indx_r_reg [1]),
        .O(p_0_in__0__0[1]));
  (* SOFT_HLUTNM = "soft_lutpair1238" *) 
  LUT3 #(
    .INIT(8'h78)) 
    \write_data_control.wr_data_indx_r[2]_i_1 
       (.I0(\write_data_control.wr_data_indx_r_reg [0]),
        .I1(\write_data_control.wr_data_indx_r_reg [1]),
        .I2(\write_data_control.wr_data_indx_r_reg [2]),
        .O(p_0_in__0__0[2]));
  LUT6 #(
    .INIT(64'h1100FFFF01000100)) 
    \write_data_control.wr_data_indx_r[3]_i_1 
       (.I0(\write_data_control.wr_data_indx_r[3]_i_3_n_0 ),
        .I1(\wr_req_counter.wr_req_cnt_r_reg[0]_1 ),
        .I2(\occupied_counter.occ_cnt_reg_n_0_[15] ),
        .I3(p_0_in__0_0),
        .I4(app_wdf_rdy_r_copy1),
        .I5(p_0_in),
        .O(\write_data_control.wr_data_addr_le ));
  (* SOFT_HLUTNM = "soft_lutpair1238" *) 
  LUT4 #(
    .INIT(16'h7F80)) 
    \write_data_control.wr_data_indx_r[3]_i_2 
       (.I0(\write_data_control.wr_data_indx_r_reg [2]),
        .I1(\write_data_control.wr_data_indx_r_reg [1]),
        .I2(\write_data_control.wr_data_indx_r_reg [0]),
        .I3(\write_data_control.wr_data_indx_r_reg [3]),
        .O(p_0_in__0__0[3]));
  LUT6 #(
    .INIT(64'h00008000FFFFFFFF)) 
    \write_data_control.wr_data_indx_r[3]_i_3 
       (.I0(app_wdf_wren_r1),
        .I1(app_wdf_end_r1),
        .I2(app_wdf_rdy_r_copy1),
        .I3(p_4_in),
        .I4(p_0_in),
        .I5(ram_init_done_r),
        .O(\write_data_control.wr_data_indx_r[3]_i_3_n_0 ));
  FDSE \write_data_control.wr_data_indx_r_reg[0] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(\write_data_control.wr_data_addr_le ),
        .D(p_0_in__0__0[0]),
        .Q(\write_data_control.wr_data_indx_r_reg [0]),
        .S(\wr_req_counter.wr_req_cnt_r_reg[0]_1 ));
  FDRE \write_data_control.wr_data_indx_r_reg[1] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(\write_data_control.wr_data_addr_le ),
        .D(p_0_in__0__0[1]),
        .Q(\write_data_control.wr_data_indx_r_reg [1]),
        .R(\wr_req_counter.wr_req_cnt_r_reg[0]_1 ));
  FDRE \write_data_control.wr_data_indx_r_reg[2] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(\write_data_control.wr_data_addr_le ),
        .D(p_0_in__0__0[2]),
        .Q(\write_data_control.wr_data_indx_r_reg [2]),
        .R(\wr_req_counter.wr_req_cnt_r_reg[0]_1 ));
  FDRE \write_data_control.wr_data_indx_r_reg[3] 
       (.C(\wr_req_counter.wr_req_cnt_r_reg[0]_0 ),
        .CE(\write_data_control.wr_data_addr_le ),
        .D(p_0_in__0__0[3]),
        .Q(\write_data_control.wr_data_indx_r_reg [3]),
        .R(\wr_req_counter.wr_req_cnt_r_reg[0]_1 ));
endmodule

(* ORIG_REF_NAME = "mig_mig" *) 
module mig_mig_mig
   (\gen_mmcm.mmcm_i ,
    app_ref_ack,
    app_zq_ack,
    app_sr_active,
    ddr3_reset_n,
    ddr3_cas_n,
    ddr3_ras_n,
    ddr3_we_n,
    ddr3_addr,
    ddr3_ba,
    ddr3_cs_n,
    ddr3_odt,
    ddr3_cke,
    ddr3_dm,
    app_rdy_r_reg,
    app_wdf_rdy,
    rstdiv0_sync_r1_reg_rep,
    out,
    iserdes_clk,
    iserdes_clk_0,
    iserdes_clk_1,
    iserdes_clk_2,
    iserdes_clk_3,
    iserdes_clk_4,
    iserdes_clk_5,
    iserdes_clk_6,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_6 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_3 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_4 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_5 ,
    \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_6 ,
    app_rd_data_end,
    init_calib_complete,
    app_rd_data_valid,
    ddr_ck_out,
    ddr3_dq,
    ddr3_dqs_p,
    ddr3_dqs_n,
    sys_clk_p,
    sys_clk_n,
    app_zq_req,
    app_sr_req,
    app_ref_req,
    clk_ref_i,
    sys_rst,
    CLKB0,
    CLKB0_7,
    CLKB0_8,
    CLKB0_9,
    CLKB0_10,
    CLKB0_11,
    CLKB0_12,
    CLKB0_13,
    app_addr,
    app_cmd,
    app_wdf_data,
    app_wdf_mask,
    app_en,
    app_wdf_wren,
    app_wdf_end);
  output \gen_mmcm.mmcm_i ;
  output app_ref_ack;
  output app_zq_ack;
  output app_sr_active;
  output ddr3_reset_n;
  output ddr3_cas_n;
  output ddr3_ras_n;
  output ddr3_we_n;
  output [13:0]ddr3_addr;
  output [2:0]ddr3_ba;
  output [0:0]ddr3_cs_n;
  output [0:0]ddr3_odt;
  output [0:0]ddr3_cke;
  output [7:0]ddr3_dm;
  output app_rdy_r_reg;
  output app_wdf_rdy;
  output rstdiv0_sync_r1_reg_rep;
  output [11:0]out;
  output iserdes_clk;
  output iserdes_clk_0;
  output iserdes_clk_1;
  output iserdes_clk_2;
  output iserdes_clk_3;
  output iserdes_clk_4;
  output iserdes_clk_5;
  output iserdes_clk_6;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_6 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_3 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_4 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_5 ;
  output \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_6 ;
  output app_rd_data_end;
  output init_calib_complete;
  output app_rd_data_valid;
  output [1:0]ddr_ck_out;
  inout [63:0]ddr3_dq;
  inout [7:0]ddr3_dqs_p;
  inout [7:0]ddr3_dqs_n;
  input sys_clk_p;
  input sys_clk_n;
  input app_zq_req;
  input app_sr_req;
  input app_ref_req;
  input clk_ref_i;
  input sys_rst;
  input CLKB0;
  input CLKB0_7;
  input CLKB0_8;
  input CLKB0_9;
  input CLKB0_10;
  input CLKB0_11;
  input CLKB0_12;
  input CLKB0_13;
  input [26:0]app_addr;
  input [1:0]app_cmd;
  input [511:0]app_wdf_data;
  input [63:0]app_wdf_mask;
  input app_en;
  input app_wdf_wren;
  input app_wdf_end;

  wire CLKB0;
  wire CLKB0_10;
  wire CLKB0_11;
  wire CLKB0_12;
  wire CLKB0_13;
  wire CLKB0_7;
  wire CLKB0_8;
  wire CLKB0_9;
  wire [26:0]app_addr;
  wire [1:0]app_cmd;
  wire app_en;
  wire app_rd_data_end;
  wire app_rd_data_valid;
  wire app_rdy_r_reg;
  wire app_ref_ack;
  wire app_ref_req;
  wire app_sr_active;
  wire app_sr_req;
  wire [511:0]app_wdf_data;
  wire app_wdf_end;
  wire [63:0]app_wdf_mask;
  wire app_wdf_rdy;
  wire app_wdf_wren;
  wire app_zq_ack;
  wire app_zq_req;
  wire clk_ref_i;
  wire [13:0]ddr3_addr;
  wire [2:0]ddr3_ba;
  wire ddr3_cas_n;
  wire [0:0]ddr3_cke;
  wire [0:0]ddr3_cs_n;
  wire [7:0]ddr3_dm;
  wire [63:0]ddr3_dq;
  wire [7:0]ddr3_dqs_n;
  wire [7:0]ddr3_dqs_p;
  wire [0:0]ddr3_odt;
  wire ddr3_ras_n;
  wire ddr3_reset_n;
  wire ddr3_we_n;
  wire [1:0]ddr_ck_out;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_3 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_4 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_5 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_6 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ;
  wire \dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ;
  wire freq_refclk;
  wire \gen_mmcm.mmcm_i ;
  wire init_calib_complete;
  wire [0:0]iodelay_ctrl_rdy;
  wire iserdes_clk;
  wire iserdes_clk_0;
  wire iserdes_clk_1;
  wire iserdes_clk_2;
  wire iserdes_clk_3;
  wire iserdes_clk_4;
  wire iserdes_clk_5;
  wire iserdes_clk_6;
  wire \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/cnt_shift_r0 ;
  wire \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/idelay_tap_limit_r0 ;
  wire \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/pi_cnt_dec ;
  wire \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/samp_edge_cnt0_en_r ;
  wire [11:0]\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_100 ;
  wire \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay/po_cnt_dec ;
  wire \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/po_cnt_dec ;
  wire \mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/prbs_rdlvl_done_pulse ;
  wire \mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/RST0 ;
  wire \mem_intfc0/mc0/bank_mach0/bank_cntrl[1].bank0/bank_state0/bm_end_r1 ;
  wire \mem_intfc0/mc0/bank_mach0/bank_cntrl[2].bank0/bank_state0/bm_end_r1 ;
  wire \mem_intfc0/mc0/bank_mach0/bank_cntrl[3].bank0/bank_state0/bm_end_r1 ;
  wire \mem_intfc0/mc0/bank_mach0/insert_maint_r ;
  wire mem_refclk;
  wire mmcm_clk;
  wire mmcm_ps_clk;
  wire [11:0]out;
  wire pll_locked;
  (* MAX_FANOUT = "10" *) (* RTL_MAX_FANOUT = "found" *) (* syn_maxfan = "10" *) wire rst_sync_r1;
  wire rst_tmp;
  wire rstdiv0_sync_r1_reg_rep;
  wire sync_pulse;
  wire sys_clk_n;
  wire sys_clk_p;
  wire sys_rst;
  wire sys_rst_act_hi;
  wire sys_rst_o;
  wire u_ddr3_infrastructure_n_0;
  wire u_ddr3_infrastructure_n_10;
  wire u_ddr3_infrastructure_n_11;
  wire u_ddr3_infrastructure_n_12;
  wire u_ddr3_infrastructure_n_13;
  wire u_ddr3_infrastructure_n_14;
  wire u_ddr3_infrastructure_n_15;
  wire u_ddr3_infrastructure_n_16;
  wire u_ddr3_infrastructure_n_17;
  wire u_ddr3_infrastructure_n_18;
  wire u_ddr3_infrastructure_n_19;
  wire u_ddr3_infrastructure_n_20;
  wire u_ddr3_infrastructure_n_21;
  wire u_ddr3_infrastructure_n_22;
  wire u_ddr3_infrastructure_n_23;
  wire u_ddr3_infrastructure_n_24;
  wire u_ddr3_infrastructure_n_25;
  wire u_ddr3_infrastructure_n_26;
  wire u_ddr3_infrastructure_n_27;
  wire u_ddr3_infrastructure_n_28;
  wire u_ddr3_infrastructure_n_29;
  wire u_ddr3_infrastructure_n_30;
  wire u_ddr3_infrastructure_n_31;
  wire u_ddr3_infrastructure_n_32;
  wire u_ddr3_infrastructure_n_33;
  wire u_ddr3_infrastructure_n_36;
  wire u_ddr3_infrastructure_n_37;
  wire u_ddr3_infrastructure_n_38;
  wire u_ddr3_infrastructure_n_39;
  wire u_ddr3_infrastructure_n_40;
  wire u_ddr3_infrastructure_n_41;
  wire u_ddr3_infrastructure_n_42;
  wire u_ddr3_infrastructure_n_45;
  wire u_ddr3_infrastructure_n_46;
  wire u_ddr3_infrastructure_n_47;
  wire u_ddr3_infrastructure_n_48;
  wire u_ddr3_infrastructure_n_49;
  wire u_ddr3_infrastructure_n_8;
  wire u_ddr3_infrastructure_n_9;
  wire u_memc_ui_top_std_n_52;
  wire u_memc_ui_top_std_n_53;
  wire u_memc_ui_top_std_n_54;
  wire u_memc_ui_top_std_n_57;
  wire u_memc_ui_top_std_n_573;

  mig_mig_7series_v4_2_tempmon \temp_mon_enabled.u_tempmon 
       (.D(\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_100 ),
        .clk_ref_i(clk_ref_i),
        .out(out),
        .\sync_cntr_reg[3]_0 (\gen_mmcm.mmcm_i ),
        .\xadc_supplied_temperature.rst_r1_reg_0 (rstdiv0_sync_r1_reg_rep));
  mig_mig_7series_v4_2_clk_ibuf u_ddr3_clk_ibuf
       (.out(mmcm_clk),
        .sys_clk_n(sys_clk_n),
        .sys_clk_p(sys_clk_p));
  mig_mig_7series_v4_2_infrastructure u_ddr3_infrastructure
       (.AS(sys_rst_act_hi),
        .RST0(\mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/RST0 ),
        .SR({u_ddr3_infrastructure_n_8,u_ddr3_infrastructure_n_9}),
        .SS(u_ddr3_infrastructure_n_40),
        .bm_end_r1(\mem_intfc0/mc0/bank_mach0/bank_cntrl[1].bank0/bank_state0/bm_end_r1 ),
        .bm_end_r1_0(\mem_intfc0/mc0/bank_mach0/bank_cntrl[2].bank0/bank_state0/bm_end_r1 ),
        .bm_end_r1_1(\mem_intfc0/mc0/bank_mach0/bank_cntrl[3].bank0/bank_state0/bm_end_r1 ),
        .bm_end_r1_reg(u_ddr3_infrastructure_n_36),
        .bm_end_r1_reg_0(u_ddr3_infrastructure_n_37),
        .bm_end_r1_reg_1(u_ddr3_infrastructure_n_38),
        .\cmp_err_4to1.compare_err_f3_reg (u_memc_ui_top_std_n_57),
        .\cnt_shift_r_reg[0] (u_memc_ui_top_std_n_54),
        .\en_cnt_div4.enable_wrlvl_cnt_reg[4] (u_memc_ui_top_std_n_573),
        .fine_adjust_reg(u_ddr3_infrastructure_n_42),
        .freq_refclk(freq_refclk),
        .\gen_mmcm.mmcm_i_0 (\gen_mmcm.mmcm_i ),
        .\gen_mmcm.mmcm_i_i_1_0 (u_ddr3_infrastructure_n_0),
        .\generate_maint_cmds.insert_maint_r_lcl_reg (u_ddr3_infrastructure_n_39),
        .insert_maint_r(\mem_intfc0/mc0/bank_mach0/insert_maint_r ),
        .mem_refclk(mem_refclk),
        .mmcm_ps_clk(mmcm_ps_clk),
        .new_cnt_cpt_r_reg(\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/idelay_tap_limit_r0 ),
        .new_cnt_dqs_r_reg(u_ddr3_infrastructure_n_47),
        .out(mmcm_clk),
        .pi_cnt_dec(\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/pi_cnt_dec ),
        .pi_cnt_dec_reg(u_ddr3_infrastructure_n_46),
        .\pi_rst_stg1_cal_r_reg[1] (u_memc_ui_top_std_n_52),
        .pll_locked(pll_locked),
        .po_cnt_dec(\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/po_cnt_dec ),
        .po_cnt_dec_2(\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay/po_cnt_dec ),
        .po_cnt_dec_reg(u_ddr3_infrastructure_n_41),
        .prbs_rdlvl_done_pulse(\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/prbs_rdlvl_done_pulse ),
        .prbs_rdlvl_done_pulse_reg(u_ddr3_infrastructure_n_49),
        .rdlvl_stg1_start_reg(\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/cnt_shift_r0 ),
        .rst_sync_r1(rst_sync_r1),
        .rst_tmp(rst_tmp),
        .rstdiv0_sync_r1_reg_rep_0(rstdiv0_sync_r1_reg_rep),
        .rstdiv0_sync_r1_reg_rep__10_0({u_ddr3_infrastructure_n_18,u_ddr3_infrastructure_n_19}),
        .rstdiv0_sync_r1_reg_rep__12_0(u_ddr3_infrastructure_n_20),
        .rstdiv0_sync_r1_reg_rep__13_0(u_ddr3_infrastructure_n_21),
        .rstdiv0_sync_r1_reg_rep__14_0(u_ddr3_infrastructure_n_22),
        .rstdiv0_sync_r1_reg_rep__15_0(u_ddr3_infrastructure_n_23),
        .rstdiv0_sync_r1_reg_rep__16_0(u_ddr3_infrastructure_n_24),
        .rstdiv0_sync_r1_reg_rep__17_0(u_ddr3_infrastructure_n_25),
        .rstdiv0_sync_r1_reg_rep__18_0(u_ddr3_infrastructure_n_26),
        .rstdiv0_sync_r1_reg_rep__19_0(u_ddr3_infrastructure_n_27),
        .rstdiv0_sync_r1_reg_rep__20_0(u_ddr3_infrastructure_n_28),
        .rstdiv0_sync_r1_reg_rep__21_0(u_ddr3_infrastructure_n_29),
        .rstdiv0_sync_r1_reg_rep__22_0(u_ddr3_infrastructure_n_30),
        .rstdiv0_sync_r1_reg_rep__23_0(u_ddr3_infrastructure_n_31),
        .rstdiv0_sync_r1_reg_rep__23_1(u_ddr3_infrastructure_n_48),
        .rstdiv0_sync_r1_reg_rep__24_0(u_ddr3_infrastructure_n_32),
        .rstdiv0_sync_r1_reg_rep__25_0(u_ddr3_infrastructure_n_33),
        .rstdiv0_sync_r1_reg_rep__2_0({u_ddr3_infrastructure_n_10,u_ddr3_infrastructure_n_11}),
        .rstdiv0_sync_r1_reg_rep__5_0({u_ddr3_infrastructure_n_12,u_ddr3_infrastructure_n_13}),
        .rstdiv0_sync_r1_reg_rep__7_0({u_ddr3_infrastructure_n_14,u_ddr3_infrastructure_n_15}),
        .rstdiv0_sync_r1_reg_rep__8_0(u_ddr3_infrastructure_n_16),
        .rstdiv0_sync_r1_reg_rep__9_0(u_ddr3_infrastructure_n_17),
        .samp_edge_cnt0_en_r(\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/samp_edge_cnt0_en_r ),
        .samp_edge_cnt0_en_r_reg(u_ddr3_infrastructure_n_45),
        .sync_pulse(sync_pulse),
        .\tap_cnt_cpt_r_reg[5] (u_memc_ui_top_std_n_53));
  mig_mig_7series_v4_2_iodelay_ctrl u_iodelay_ctrl
       (.AS(sys_rst_act_hi),
        .clk_ref_i(clk_ref_i),
        .iodelay_ctrl_rdy(iodelay_ctrl_rdy),
        .out(sys_rst_o),
        .sys_rst(sys_rst));
  (* X_CORE_INFO = "mig_7series_v4_2_ddr3_7Series, mig, 2018.3" *) 
  mig_mig_7series_v4_2_memc_ui_top_std u_memc_ui_top_std
       (.A_rst_primitives_reg(iserdes_clk),
        .A_rst_primitives_reg_0(iserdes_clk_0),
        .A_rst_primitives_reg_1(iserdes_clk_1),
        .A_rst_primitives_reg_2(iserdes_clk_2),
        .A_rst_primitives_reg_3(iserdes_clk_3),
        .A_rst_primitives_reg_4(iserdes_clk_4),
        .A_rst_primitives_reg_5(iserdes_clk_5),
        .A_rst_primitives_reg_6(iserdes_clk_6),
        .CLKB0(CLKB0),
        .CLKB0_10(CLKB0_10),
        .CLKB0_11(CLKB0_11),
        .CLKB0_12(CLKB0_12),
        .CLKB0_13(CLKB0_13),
        .CLKB0_7(CLKB0_7),
        .CLKB0_8(CLKB0_8),
        .CLKB0_9(CLKB0_9),
        .D(\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_tempmon_0/device_temp_100 ),
        .E(app_rdy_r_reg),
        .\FSM_onehot_cal1_state_r_reg[7] (u_ddr3_infrastructure_n_10),
        .RST0(\mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_1.u_ddr_phy_4lanes/RST0 ),
        .SR(u_ddr3_infrastructure_n_28),
        .SS(u_ddr3_infrastructure_n_40),
        .app_addr(app_addr),
        .app_cmd(app_cmd),
        .app_en(app_en),
        .app_rd_data_end(app_rd_data_end),
        .app_rd_data_valid(app_rd_data_valid),
        .app_ref_ack(app_ref_ack),
        .app_ref_req(app_ref_req),
        .app_sr_active(app_sr_active),
        .app_sr_req(app_sr_req),
        .app_wdf_data(app_wdf_data),
        .app_wdf_end(app_wdf_end),
        .app_wdf_mask(app_wdf_mask),
        .app_wdf_rdy(app_wdf_rdy),
        .app_wdf_wren(app_wdf_wren),
        .app_zq_ack(app_zq_ack),
        .app_zq_req(app_zq_req),
        .bm_end_r1(\mem_intfc0/mc0/bank_mach0/bank_cntrl[1].bank0/bank_state0/bm_end_r1 ),
        .bm_end_r1_0(\mem_intfc0/mc0/bank_mach0/bank_cntrl[2].bank0/bank_state0/bm_end_r1 ),
        .bm_end_r1_1(\mem_intfc0/mc0/bank_mach0/bank_cntrl[3].bank0/bank_state0/bm_end_r1 ),
        .cal2_if_reset_reg(rstdiv0_sync_r1_reg_rep),
        .\cmp_err_4to1.compare_err_f3_reg (u_ddr3_infrastructure_n_47),
        .\cnt_shift_r_reg[0] (\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/cnt_shift_r0 ),
        .\complex_num_writes_reg[1] (u_ddr3_infrastructure_n_49),
        .\corse_dec_reg[7][0] (u_ddr3_infrastructure_n_12),
        .\corse_inc_reg[6][2] ({u_ddr3_infrastructure_n_13,u_ddr3_infrastructure_n_11}),
        .ddr3_addr(ddr3_addr),
        .ddr3_ba(ddr3_ba),
        .ddr3_cas_n(ddr3_cas_n),
        .ddr3_cke(ddr3_cke),
        .ddr3_cs_n(ddr3_cs_n),
        .ddr3_dm(ddr3_dm),
        .ddr3_dq(ddr3_dq),
        .ddr3_dqs_n(ddr3_dqs_n),
        .ddr3_dqs_p(ddr3_dqs_p),
        .ddr3_odt(ddr3_odt),
        .ddr3_ras_n(ddr3_ras_n),
        .ddr3_reset_n(ddr3_reset_n),
        .ddr3_we_n(ddr3_we_n),
        .ddr_ck_out(ddr_ck_out),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[10]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[11]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[12]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[13]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[14]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[15]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[16]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[17]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[18]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[19]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[20]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[21]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[22]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[23]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[24]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[25]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[26]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[27]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[28]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[29]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[30]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[31]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[32]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[33]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[34]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[35]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[36]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[37]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[38]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[39]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[40]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[41]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[42]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[43]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[44]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[45]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[46]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[47]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[48]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[49]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[50]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[51]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[52]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[53]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[54]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[55]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[56]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[57]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[58]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[59]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[60]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[61]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[62]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[63]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[64]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[65]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[66]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[67]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[68]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[69]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[70]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[71]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[72]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[73]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[74]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[75]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[76]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[77]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[78]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_1 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_2 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_3 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_3 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_4 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_4 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_5 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_5 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_6 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[79]_6 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[8]_0 ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9] ),
        .\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 (\dq_gen_40.if_post_fifo_gen.rd_data_r_reg[9]_0 ),
        .\en_cnt_div4.enable_wrlvl_cnt_reg[2] (u_ddr3_infrastructure_n_21),
        .\en_cnt_div4.enable_wrlvl_cnt_reg[4] (u_ddr3_infrastructure_n_48),
        .fine_adjust_reg(u_memc_ui_top_std_n_52),
        .\fine_dec_cnt_reg[5] ({u_ddr3_infrastructure_n_18,u_ddr3_infrastructure_n_19}),
        .\fine_inc_reg[6][3] (u_ddr3_infrastructure_n_16),
        .first_fail_detect_reg(u_ddr3_infrastructure_n_25),
        .\four_dec_min_limit_reg[0] (u_ddr3_infrastructure_n_23),
        .freq_refclk(freq_refclk),
        .\idelay_tap_cnt_r_reg[0][0][4] (u_ddr3_infrastructure_n_30),
        .init_calib_complete(init_calib_complete),
        .\init_state_r_reg[4] (u_memc_ui_top_std_n_573),
        .insert_maint_r(\mem_intfc0/mc0/bank_mach0/insert_maint_r ),
        .iodelay_ctrl_rdy(iodelay_ctrl_rdy),
        .\last_master_r_reg[2] (u_ddr3_infrastructure_n_32),
        .mem_refclk(mem_refclk),
        .mmcm_ps_clk(mmcm_ps_clk),
        .new_cnt_cpt_r_reg(u_memc_ui_top_std_n_53),
        .new_cnt_dqs_r_reg(u_memc_ui_top_std_n_57),
        .out(sys_rst_o),
        .\periodic_rd_generation.periodic_rd_cntr1_r_reg (u_ddr3_infrastructure_n_24),
        .\periodic_read_request.periodic_rd_r_cnt_reg (u_ddr3_infrastructure_n_26),
        .pi_cnt_dec(\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/pi_cnt_dec ),
        .\pi_rst_stg1_cal_r_reg[1] (u_ddr3_infrastructure_n_42),
        .pll_locked(pll_locked),
        .po_cnt_dec(\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_wrlvl/po_cnt_dec ),
        .po_cnt_dec_2(\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/mb_wrlvl_inst.u_ddr_phy_ck_addr_cmd_delay/po_cnt_dec ),
        .prbs_rdlvl_done_pulse(\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/u_ddr_phy_init/prbs_rdlvl_done_pulse ),
        .ras_timer_zero_r_reg(u_ddr3_infrastructure_n_36),
        .ras_timer_zero_r_reg_0(u_ddr3_infrastructure_n_37),
        .ras_timer_zero_r_reg_1(u_ddr3_infrastructure_n_38),
        .\rdlvl_dqs_tap_cnt_r_reg[0][0][2] ({u_ddr3_infrastructure_n_8,u_ddr3_infrastructure_n_9}),
        .rdlvl_stg1_start_reg(u_memc_ui_top_std_n_54),
        .reset_reg_0(u_ddr3_infrastructure_n_33),
        .\rfc_zq_xsdll_timer.rfc_zq_xsdll_timer_r_reg[3] (u_ddr3_infrastructure_n_39),
        .rst_sync_r1(rst_sync_r1),
        .rst_tmp(rst_tmp),
        .\rstdiv2_sync_r_reg[11] (u_ddr3_infrastructure_n_0),
        .\rtp_timer_r_reg[0] (u_ddr3_infrastructure_n_29),
        .\rtp_timer_r_reg[1] (u_ddr3_infrastructure_n_31),
        .samp_edge_cnt0_en_r(\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/samp_edge_cnt0_en_r ),
        .\samp_edge_cnt1_r_reg[0] (u_ddr3_infrastructure_n_45),
        .\samples_cnt_r_reg[0] (u_ddr3_infrastructure_n_20),
        .sync_pulse(sync_pulse),
        .\tap_cnt_cpt_r_reg[5] (\mem_intfc0/ddr_phy_top0/u_ddr_calib_top/ddr_phy_rdlvl_gen.u_ddr_phy_rdlvl/idelay_tap_limit_r0 ),
        .\victim_sel_reg[0] (u_ddr3_infrastructure_n_22),
        .\wait_cnt_r_reg[0] (u_ddr3_infrastructure_n_41),
        .\wait_cnt_r_reg[0]_0 (u_ddr3_infrastructure_n_46),
        .\wl_dqs_tap_count_r_reg[0][5][5] (u_ddr3_infrastructure_n_17),
        .\wl_dqs_tap_count_r_reg[0][6][3] ({u_ddr3_infrastructure_n_14,u_ddr3_infrastructure_n_15}),
        .\wr_req_counter.wr_req_cnt_r_reg[0] (\gen_mmcm.mmcm_i ),
        .\zq_cntrl.zq_request_logic.zq_request_r_reg (u_ddr3_infrastructure_n_27));
endmodule
`ifndef GLBL
`define GLBL
`timescale  1 ps / 1 ps

module glbl ();

    parameter ROC_WIDTH = 100000;
    parameter TOC_WIDTH = 0;

//--------   STARTUP Globals --------------
    wire GSR;
    wire GTS;
    wire GWE;
    wire PRLD;
    tri1 p_up_tmp;
    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;

    wire PROGB_GLBL;
    wire CCLKO_GLBL;
    wire FCSBO_GLBL;
    wire [3:0] DO_GLBL;
    wire [3:0] DI_GLBL;
   
    reg GSR_int;
    reg GTS_int;
    reg PRLD_int;

//--------   JTAG Globals --------------
    wire JTAG_TDO_GLBL;
    wire JTAG_TCK_GLBL;
    wire JTAG_TDI_GLBL;
    wire JTAG_TMS_GLBL;
    wire JTAG_TRST_GLBL;

    reg JTAG_CAPTURE_GLBL;
    reg JTAG_RESET_GLBL;
    reg JTAG_SHIFT_GLBL;
    reg JTAG_UPDATE_GLBL;
    reg JTAG_RUNTEST_GLBL;

    reg JTAG_SEL1_GLBL = 0;
    reg JTAG_SEL2_GLBL = 0 ;
    reg JTAG_SEL3_GLBL = 0;
    reg JTAG_SEL4_GLBL = 0;

    reg JTAG_USER_TDO1_GLBL = 1'bz;
    reg JTAG_USER_TDO2_GLBL = 1'bz;
    reg JTAG_USER_TDO3_GLBL = 1'bz;
    reg JTAG_USER_TDO4_GLBL = 1'bz;

    assign (strong1, weak0) GSR = GSR_int;
    assign (strong1, weak0) GTS = GTS_int;
    assign (weak1, weak0) PRLD = PRLD_int;

    initial begin
	GSR_int = 1'b1;
	PRLD_int = 1'b1;
	#(ROC_WIDTH)
	GSR_int = 1'b0;
	PRLD_int = 1'b0;
    end

    initial begin
	GTS_int = 1'b1;
	#(TOC_WIDTH)
	GTS_int = 1'b0;
    end

endmodule
`endif
