//Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
//Date        : Wed Apr  8 16:29:59 2020
//Host        : LAPTOP-RJQ3H7G3 running 64-bit major release  (build 9200)
//Command     : generate_target pdm_to_pcm_wrapper.bd
//Design      : pdm_to_pcm_wrapper
//Purpose     : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

module pdm_to_pcm_wrapper
   (fifo_almost_empty,
    fifo_almost_full,
    fifo_rd_clk,
    fifo_rd_en,
    pcm_data,
    pdm_clk,
    pdm_data,
    resetn,
    start,
    sys_clock);
  output fifo_almost_empty;
  output fifo_almost_full;
  input fifo_rd_clk;
  input fifo_rd_en;
  output [31:0]pcm_data;
  output [0:0]pdm_clk;
  input [3:0]pdm_data;
  input resetn;
  input start;
  input sys_clock;

  wire fifo_almost_empty;
  wire fifo_almost_full;
  wire fifo_rd_clk;
  wire fifo_rd_en;
  wire [31:0]pcm_data;
  wire [0:0]pdm_clk;
  wire [3:0]pdm_data;
  wire resetn;
  wire start;
  wire sys_clock;

  pdm_to_pcm pdm_to_pcm_i
       (.fifo_almost_empty(fifo_almost_empty),
        .fifo_almost_full(fifo_almost_full),
        .fifo_rd_clk(fifo_rd_clk),
        .fifo_rd_en(fifo_rd_en),
        .pcm_data(pcm_data),
        .pdm_clk(pdm_clk),
        .pdm_data(pdm_data),
        .resetn(resetn),
        .start(start),
        .sys_clock(sys_clock));
endmodule
