library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity delay is
    Port ( 
                   clk: in std_logic;     
               address: out std_logic_vector(4 downto 0));
end ;

architecture Behavioral of delay is


signal address_temp: std_logic_vector(4 downto 0);


process(clk)
begin

   if(rising_edge(clk)) then
        address_temp<="10010"; --address is 18 in coe file, the 24th micro delay value of 90 degree 
   end if;
end process;
address <= address_temp;
end Behavioral;
