Library ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL; 

entity demux is
       port(
	     clk: in std_logic;
	     input_data: in std_logic;   
             output_data: out std_logic_vector(3 downto 0));
end entity demux;

architecture arch of demux is


signal clk_outQ:std_logic:='0';
signal a: natural range 0 to 3 :=0;

begin
p0: process(clk)  
       begin
 	    if(rising_edge(clk)) then
	      if (data_tvalid = '1') then
	         if a =3 then
                    a <=0;
                 else
                    a <=a + 1;
                 end if;
	       end if;   
	    end if;
	 		      
end process p0;

p1: process(a,clk,input_data)
        begin
 	    if(falling_edge(clk)) then
	       output_data(a) <= input_data;
	end if;
end process p1;
          
end arch;
