#-----------------------------------------------------------
# Vivado v2019.1 (64-bit)
# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019
# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
# Start of session at: Wed May 13 19:08:11 2020
# Process ID: 21612
# Current directory: D:/sound_location_project/vivado/dat096-master-latest_version/latest_version
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent16164 D:\sound_location_project\vivado\dat096-master-latest_version\latest_version\dat096_ref_design.xpr
# Log file: D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/vivado.log
# Journal file: D:/sound_location_project/vivado/dat096-master-latest_version/latest_version\vivado.jou
#-----------------------------------------------------------
start_gui
open_project D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.xpr
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/clean_rst.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/decoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/encoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_constants.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_regs.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_test.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/timescale.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_an.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_mdio.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_rx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_sync.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_tx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/ddr/mig_interface_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/i2c/i2c_slave_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/micron/sdram/mobile_sdr.v:]
Scanning sources...
Finished scanning sources
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/clean_rst.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/decoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/encoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_constants.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_regs.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_test.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/timescale.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_an.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_mdio.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_rx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_sync.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_tx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/ddr/mig_interface_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/i2c/i2c_slave_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/micron/sdram/mobile_sdr.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/clean_rst.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/decoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/encoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_constants.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_regs.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_test.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/timescale.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_an.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_mdio.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_rx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_sync.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_tx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/ddr/mig_interface_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/i2c/i2c_slave_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/micron/sdram/mobile_sdr.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/clean_rst.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/decoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/encoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_constants.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_regs.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_test.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/timescale.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_an.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_mdio.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_rx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_sync.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_tx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/ddr/mig_interface_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/i2c/i2c_slave_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/micron/sdram/mobile_sdr.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/clean_rst.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/decoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/encoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_constants.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_regs.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_test.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/timescale.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_an.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_mdio.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_rx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_sync.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_tx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/ddr/mig_interface_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/i2c/i2c_slave_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/micron/sdram/mobile_sdr.v:]
WARNING: [filemgmt 56-3] IP Repository Path: Could not find the directory 'D:/sound_location_project/vivado/dat096-master-latest_version/sound_location_project'.
INFO: [IP_Flow 19-234] Refreshing IP repositories
WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'd:/sound_location_project/vivado/dat096-master-latest_version/sound_location_project'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/xilinx/Vivado/2019.1/data/ip'.
open_project: Time (s): cpu = 00:00:23 ; elapsed = 00:00:12 . Memory (MB): peak = 851.699 ; gain = 210.508
open_bd_design {D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/pdm_to_pcm.bd}
Adding component instance block -- xilinx.com:ip:cic_compiler:4.0 - cic_compiler_0
Adding component instance block -- xilinx.com:ip:fir_compiler:7.2 - fir_compiler_0
Adding component instance block -- xilinx.com:ip:fir_compiler:7.2 - fir_compiler_1
Adding component instance block -- xilinx.com:ip:clk_wiz:6.0 - clk_wiz_0
Adding component instance block -- xilinx.com:ip:fifo_generator:13.2 - fifo_generator_0
INFO: [xilinx.com:ip:fifo_generator:13.2-5968] /fifo_generator_0Executing the post_config_ip from bd
Adding component instance block -- xilinx.com:ip:util_vector_logic:2.0 - util_vector_logic_0
Adding component instance block -- xilinx.com:module_ref:clk_div:1.0 - clk_div_0
Adding component instance block -- xilinx.com:ip:util_ds_buf:2.1 - util_ds_buf_0
Adding component instance block -- xilinx.com:module_ref:clk_div:1.0 - clk_div_1
Adding component instance block -- xilinx.com:module_ref:hp_filter:1.0 - hp_filter_0
Adding component instance block -- xilinx.com:ip:util_vector_logic:2.0 - util_vector_logic_1
Adding component instance block -- xilinx.com:module_ref:timemux:1.0 - timemux_0
Adding component instance block -- xilinx.com:ip:c_addsub:12.0 - c_addsub_0
Adding component instance block -- xilinx.com:ip:c_addsub:12.0 - c_addsub_1
Adding component instance block -- xilinx.com:ip:c_addsub:12.0 - c_addsub_2
Adding component instance block -- xilinx.com:module_ref:demux16_sync:1.0 - demux16_sync_0
Adding component instance block -- xilinx.com:ip:blk_mem_gen:8.4 - blk_mem_gen_0
Adding component instance block -- xilinx.com:ip:blk_mem_gen:8.4 - blk_mem_gen_1
Adding component instance block -- xilinx.com:ip:c_shift_ram:12.0 - c_shift_ram_0
Adding component instance block -- xilinx.com:ip:c_shift_ram:12.0 - c_shift_ram_1
Adding component instance block -- xilinx.com:ip:c_shift_ram:12.0 - c_shift_ram_2
Adding component instance block -- xilinx.com:ip:c_shift_ram:12.0 - c_shift_ram_3
Adding component instance block -- xilinx.com:ip:blk_mem_gen:8.4 - blk_mem_gen_2
Adding component instance block -- xilinx.com:ip:blk_mem_gen:8.4 - blk_mem_gen_3
Adding component instance block -- xilinx.com:module_ref:delay_3:1.0 - delay_3_0
Adding component instance block -- xilinx.com:module_ref:delay_2:1.0 - delay_2_0
Adding component instance block -- xilinx.com:module_ref:delay_1:1.0 - delay_1_0
Adding component instance block -- xilinx.com:module_ref:delay:1.0 - delay_3
WARNING: [BD 41-1731] Type mismatch between connected pins: /clk_wiz_0/clk_out1(clk) and /clk_div_0/clk_in(undef)
WARNING: [BD 41-1731] Type mismatch between connected pins: /clk_div_1/clk_out(undef) and /c_addsub_1/CLK(clk)
WARNING: [BD 41-1731] Type mismatch between connected pins: /clk_div_1/clk_out(undef) and /c_addsub_0/CLK(clk)
WARNING: [BD 41-1731] Type mismatch between connected pins: /clk_div_1/clk_out(undef) and /c_shift_ram_2/CLK(clk)
WARNING: [BD 41-1731] Type mismatch between connected pins: /clk_div_1/clk_out(undef) and /c_shift_ram_3/CLK(clk)
WARNING: [BD 41-1731] Type mismatch between connected pins: /clk_div_1/clk_out(undef) and /c_shift_ram_1/CLK(clk)
WARNING: [BD 41-1731] Type mismatch between connected pins: /clk_div_1/clk_out(undef) and /fifo_generator_0/wr_clk(clk)
WARNING: [BD 41-1731] Type mismatch between connected pins: /clk_div_1/clk_out(undef) and /util_ds_buf_0/BUFG_I(clk)
WARNING: [BD 41-1731] Type mismatch between connected pins: /clk_div_1/clk_out(undef) and /c_shift_ram_0/CLK(clk)
WARNING: [BD 41-1731] Type mismatch between connected pins: /clk_div_1/clk_out(undef) and /c_addsub_2/CLK(clk)
WARNING: [BD 41-1731] Type mismatch between connected pins: /clk_div_1/clk_out(undef) and /delay_3_0/clk(clk)
WARNING: [BD 41-1731] Type mismatch between connected pins: /clk_div_1/clk_out(undef) and /delay_2_0/clk(clk)
WARNING: [BD 41-1731] Type mismatch between connected pins: /clk_div_1/clk_out(undef) and /delay_1_0/clk(clk)
WARNING: [BD 41-1731] Type mismatch between connected pins: /clk_div_1/clk_out(undef) and /delay_3/clk(clk)
WARNING: [BD 41-1731] Type mismatch between connected pins: /demux16_sync_0/finish(undef) and /c_shift_ram_2/CE(ce)
WARNING: [BD 41-1731] Type mismatch between connected pins: /demux16_sync_0/finish(undef) and /c_shift_ram_3/CE(ce)
WARNING: [BD 41-1731] Type mismatch between connected pins: /demux16_sync_0/finish(undef) and /c_addsub_1/CE(ce)
WARNING: [BD 41-1731] Type mismatch between connected pins: /demux16_sync_0/finish(undef) and /c_addsub_0/CE(ce)
WARNING: [BD 41-1731] Type mismatch between connected pins: /demux16_sync_0/finish(undef) and /c_shift_ram_0/CE(ce)
WARNING: [BD 41-1731] Type mismatch between connected pins: /demux16_sync_0/finish(undef) and /c_addsub_2/CE(ce)
WARNING: [BD 41-1731] Type mismatch between connected pins: /demux16_sync_0/finish(undef) and /c_shift_ram_1/CE(ce)
Successfully read diagram <pdm_to_pcm> from BD file <D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/pdm_to_pcm.bd>
open_bd_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:24 . Memory (MB): peak = 1468.590 ; gain = 30.750
update_compile_order -fileset sources_1
close [ open D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/new/scan.vhd w ]
add_files D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/new/scan.vhd
set_property library work [get_files  D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/new/scan.vhd]
delete_bd_objs [get_bd_nets delay_3_0_address] [get_bd_cells delay_3_0]
delete_bd_objs: Time (s): cpu = 00:00:02 ; elapsed = 00:00:06 . Memory (MB): peak = 1747.758 ; gain = 0.348
delete_bd_objs [get_bd_nets delay_2_0_address] [get_bd_cells delay_2_0]
delete_bd_objs: Time (s): cpu = 00:00:06 ; elapsed = 00:00:17 . Memory (MB): peak = 1828.527 ; gain = 55.742
delete_bd_objs [get_bd_nets delay_1_0_address] [get_bd_cells delay_1_0]
delete_bd_objs [get_bd_nets delay_3_address] [get_bd_cells delay_3]
delete_bd_objs: Time (s): cpu = 00:00:01 ; elapsed = 00:00:07 . Memory (MB): peak = 1828.527 ; gain = 0.000
save_bd_design
Wrote  : <D:\sound_location_project\vivado\dat096-master-latest_version\latest_version\dat096_ref_design.srcs\sources_1\bd\pdm_to_pcm\pdm_to_pcm.bd> 
Wrote  : <D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ui/bd_8ec0abfc.ui> 
update_compile_order -fileset sources_1
create_bd_cell -type module -reference scan scan_0
INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing.
INFO: [IP_Flow 19-234] Refreshing IP repositories
WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'd:/sound_location_project/vivado/dat096-master-latest_version/sound_location_project'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
connect_bd_net [get_bd_pins scan_0/t_last] [get_bd_pins demux16_sync_0/finish]
connect_bd_net [get_bd_pins scan_0/address_0] [get_bd_pins blk_mem_gen_0/addra]
WARNING: [BD 41-1306] The connection to interface pin /blk_mem_gen_0/addra is being overridden by the user. This pin will not be connected as a part of interface connection BRAM_PORTA
connect_bd_net [get_bd_pins scan_0/address_1] [get_bd_pins blk_mem_gen_1/addra]
WARNING: [BD 41-1306] The connection to interface pin /blk_mem_gen_1/addra is being overridden by the user. This pin will not be connected as a part of interface connection BRAM_PORTA
connect_bd_net [get_bd_pins scan_0/address_2] [get_bd_pins blk_mem_gen_2/addra]
WARNING: [BD 41-1306] The connection to interface pin /blk_mem_gen_2/addra is being overridden by the user. This pin will not be connected as a part of interface connection BRAM_PORTA
connect_bd_net [get_bd_pins blk_mem_gen_3/addra] [get_bd_pins scan_0/address_3]
WARNING: [BD 41-1306] The connection to interface pin /blk_mem_gen_3/addra is being overridden by the user. This pin will not be connected as a part of interface connection BRAM_PORTA
delete_bd_objs [get_bd_nets Net1]
connect_bd_net [get_bd_pins scan_0/scan_finish] [get_bd_pins c_addsub_2/CE]
WARNING: [BD 41-1731] Type mismatch between connected pins: /scan_0/scan_finish(undef) and /c_addsub_2/CE(ce)
connect_bd_net [get_bd_pins scan_0/scan_finish] [get_bd_pins c_addsub_0/CE]
WARNING: [BD 41-1731] Type mismatch between connected pins: /scan_0/scan_finish(undef) and /c_addsub_0/CE(ce)
connect_bd_net [get_bd_pins scan_0/scan_finish] [get_bd_pins c_addsub_1/CE]
WARNING: [BD 41-1731] Type mismatch between connected pins: /scan_0/scan_finish(undef) and /c_addsub_1/CE(ce)
connect_bd_net [get_bd_pins scan_0/t_last] [get_bd_pins demux16_sync_0/finish]
connect_bd_net [get_bd_pins scan_0/clk] [get_bd_pins clk_div_1/clk_out]
WARNING: [BD 41-1731] Type mismatch between connected pins: /clk_div_1/clk_out(undef) and /scan_0/clk(clk)
connect_bd_net [get_bd_pins scan_0/start] [get_bd_pins c_shift_ram_0/CE]
connect_bd_net [get_bd_pins c_shift_ram_0/CE] [get_bd_pins c_shift_ram_1/CE]
connect_bd_net [get_bd_pins c_shift_ram_1/CE] [get_bd_pins c_shift_ram_2/CE]
delete_bd_objs [get_bd_nets scan_0_scan_finish]
connect_bd_net [get_bd_pins scan_0/fifo_wr_en] [get_bd_pins c_addsub_2/CE]
WARNING: [BD 41-1731] Type mismatch between connected pins: /scan_0/fifo_wr_en(undef) and /c_addsub_2/CE(ce)
connect_bd_net [get_bd_pins scan_0/fifo_wr_en] [get_bd_pins c_addsub_0/CE]
WARNING: [BD 41-1731] Type mismatch between connected pins: /scan_0/fifo_wr_en(undef) and /c_addsub_0/CE(ce)
connect_bd_net [get_bd_pins scan_0/fifo_wr_en] [get_bd_pins c_addsub_1/CE]
WARNING: [BD 41-1731] Type mismatch between connected pins: /scan_0/fifo_wr_en(undef) and /c_addsub_1/CE(ce)
delete_bd_objs [get_bd_nets scan_0_fifo_wr_en]
connect_bd_net [get_bd_pins scan_0/adder_enable] [get_bd_pins c_addsub_2/CE]
WARNING: [BD 41-1731] Type mismatch between connected pins: /scan_0/adder_enable(undef) and /c_addsub_2/CE(ce)
connect_bd_net [get_bd_pins scan_0/adder_enable] [get_bd_pins c_addsub_0/CE]
WARNING: [BD 41-1731] Type mismatch between connected pins: /scan_0/adder_enable(undef) and /c_addsub_0/CE(ce)
connect_bd_net [get_bd_pins scan_0/adder_enable] [get_bd_pins c_addsub_1/CE]
WARNING: [BD 41-1731] Type mismatch between connected pins: /scan_0/adder_enable(undef) and /c_addsub_1/CE(ce)
connect_bd_net [get_bd_pins fifo_generator_0/wr_en] [get_bd_pins scan_0/fifo_wr_en]
WARNING: [BD 41-1306] The connection to interface pin /fifo_generator_0/wr_en is being overridden by the user. This pin will not be connected as a part of interface connection FIFO_WRITE
delete_bd_objs [get_bd_nets Net1]
connect_bd_net [get_bd_pins c_shift_ram_1/CE] [get_bd_pins scan_0/adder_enable]
WARNING: [BD 41-1731] Type mismatch between connected pins: /scan_0/adder_enable(undef) and /c_shift_ram_1/CE(ce)
connect_bd_net [get_bd_pins c_shift_ram_0/CE] [get_bd_pins scan_0/adder_enable]
WARNING: [BD 41-1731] Type mismatch between connected pins: /scan_0/adder_enable(undef) and /c_shift_ram_0/CE(ce)
connect_bd_net [get_bd_pins c_shift_ram_3/CE] [get_bd_pins scan_0/adder_enable]
WARNING: [BD 41-1731] Type mismatch between connected pins: /scan_0/adder_enable(undef) and /c_shift_ram_3/CE(ce)
save_bd_design
Wrote  : <D:\sound_location_project\vivado\dat096-master-latest_version\latest_version\dat096_ref_design.srcs\sources_1\bd\pdm_to_pcm\pdm_to_pcm.bd> 
Wrote  : <D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ui/bd_8ec0abfc.ui> 
update_compile_order -fileset sources_1
startgroup
connect_bd_net [get_bd_ports start] [get_bd_pins scan_0/start]
endgroup
save_bd_design
Wrote  : <D:\sound_location_project\vivado\dat096-master-latest_version\latest_version\dat096_ref_design.srcs\sources_1\bd\pdm_to_pcm\pdm_to_pcm.bd> 
Wrote  : <D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ui/bd_8ec0abfc.ui> 
delete_bd_objs [get_bd_nets scan_0_adder_enable]
connect_bd_net [get_bd_pins scan_0/scan_finish] [get_bd_pins c_shift_ram_0/CE]
WARNING: [BD 41-1731] Type mismatch between connected pins: /scan_0/scan_finish(undef) and /c_shift_ram_0/CE(ce)
connect_bd_net [get_bd_pins scan_0/scan_finish] [get_bd_pins c_shift_ram_1/CE]
WARNING: [BD 41-1731] Type mismatch between connected pins: /scan_0/scan_finish(undef) and /c_shift_ram_1/CE(ce)
connect_bd_net [get_bd_pins c_shift_ram_2/CE] [get_bd_pins scan_0/scan_finish]
WARNING: [BD 41-1731] Type mismatch between connected pins: /scan_0/scan_finish(undef) and /c_shift_ram_2/CE(ce)
connect_bd_net [get_bd_pins c_shift_ram_3/CE] [get_bd_pins scan_0/scan_finish]
WARNING: [BD 41-1731] Type mismatch between connected pins: /scan_0/scan_finish(undef) and /c_shift_ram_3/CE(ce)
connect_bd_net [get_bd_pins c_addsub_1/CE] [get_bd_pins c_addsub_0/CE]
connect_bd_net [get_bd_pins c_addsub_2/CE] [get_bd_pins c_addsub_1/CE]
connect_bd_net [get_bd_pins scan_0/adder_enable] [get_bd_pins c_addsub_2/CE]
WARNING: [BD 41-1731] Type mismatch between connected pins: /c_addsub_1/CE(ce) and /scan_0/adder_enable(undef)
WARNING: [BD 41-1731] Type mismatch between connected pins: /c_addsub_0/CE(ce) and /scan_0/adder_enable(undef)
WARNING: [BD 41-1731] Type mismatch between connected pins: /c_addsub_2/CE(ce) and /scan_0/adder_enable(undef)
save_bd_design
Wrote  : <D:\sound_location_project\vivado\dat096-master-latest_version\latest_version\dat096_ref_design.srcs\sources_1\bd\pdm_to_pcm\pdm_to_pcm.bd> 
Wrote  : <D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ui/bd_8ec0abfc.ui> 
undo
INFO: [Common 17-17] undo 'connect_bd_net [get_bd_pins scan_0/adder_enable] [get_bd_pins c_addsub_2/CE]'
save_bd_design
WARNING: [BD 41-597] NET <Net1> has no source
Wrote  : <D:\sound_location_project\vivado\dat096-master-latest_version\latest_version\dat096_ref_design.srcs\sources_1\bd\pdm_to_pcm\pdm_to_pcm.bd> 
Wrote  : <D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ui/bd_8ec0abfc.ui> 
connect_bd_net [get_bd_pins scan_0/adder_enable] [get_bd_pins c_addsub_2/CE]
WARNING: [BD 41-1731] Type mismatch between connected pins: /c_addsub_1/CE(ce) and /scan_0/adder_enable(undef)
WARNING: [BD 41-1731] Type mismatch between connected pins: /c_addsub_0/CE(ce) and /scan_0/adder_enable(undef)
WARNING: [BD 41-1731] Type mismatch between connected pins: /c_addsub_2/CE(ce) and /scan_0/adder_enable(undef)
save_bd_design
Wrote  : <D:\sound_location_project\vivado\dat096-master-latest_version\latest_version\dat096_ref_design.srcs\sources_1\bd\pdm_to_pcm\pdm_to_pcm.bd> 
Wrote  : <D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ui/bd_8ec0abfc.ui> 
reset_run synth_2
launch_runs synth_2 -jobs 4
WARNING: [BD 41-2180] Resetting the memory initialization file of </blk_mem_gen_0> to default.
WARNING: [BD 41-2180] Resetting the memory initialization file of </blk_mem_gen_3> to default.
WARNING: [BD 41-2180] Resetting the memory initialization file of </blk_mem_gen_1> to default.
WARNING: [BD 41-2180] Resetting the memory initialization file of </blk_mem_gen_2> to default.
WARNING: [xilinx.com:ip:c_addsub:12.0-313] /c_addsub_0 A-DATA: Field type resolution: data = integer. /c_shift_ram_0 Q-DATA: data = null. /c_shift_ram_0 Q-DATA data field will be interpreted as integer
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_0 A_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
WARNING: [xilinx.com:ip:c_addsub:12.0-313] /c_addsub_0 B-DATA: Field type resolution: data = integer. /c_shift_ram_1 Q-DATA: data = null. /c_shift_ram_1 Q-DATA data field will be interpreted as integer
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_0 B_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:c_addsub:12.0-308] /c_addsub_0 A-DATA: Validating field: data(16:0): int16 against /c_shift_ram_0 Q-DATA: data(16:0): bit16.
WARNING: [xilinx.com:ip:c_addsub:12.0-313] /c_addsub_0 A-DATA: Field type resolution: data = integer. /c_shift_ram_0 Q-DATA: data = null. /c_shift_ram_0 Q-DATA data field will be interpreted as integer
INFO: [xilinx.com:ip:c_addsub:12.0-308] /c_addsub_0 B-DATA: Validating field: data(16:0): int16 against /c_shift_ram_1 Q-DATA: data(16:0): bit16.
WARNING: [xilinx.com:ip:c_addsub:12.0-313] /c_addsub_0 B-DATA: Field type resolution: data = integer. /c_shift_ram_1 Q-DATA: data = null. /c_shift_ram_1 Q-DATA data field will be interpreted as integer
WARNING: [xilinx.com:ip:c_addsub:12.0-313] /c_addsub_1 A-DATA: Field type resolution: data = integer. /c_shift_ram_2 Q-DATA: data = null. /c_shift_ram_2 Q-DATA data field will be interpreted as integer
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_1 A_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
WARNING: [xilinx.com:ip:c_addsub:12.0-313] /c_addsub_1 B-DATA: Field type resolution: data = integer. /c_shift_ram_3 Q-DATA: data = null. /c_shift_ram_3 Q-DATA data field will be interpreted as integer
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_1 B_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:c_addsub:12.0-308] /c_addsub_1 A-DATA: Validating field: data(16:0): int16 against /c_shift_ram_2 Q-DATA: data(16:0): bit16.
WARNING: [xilinx.com:ip:c_addsub:12.0-313] /c_addsub_1 A-DATA: Field type resolution: data = integer. /c_shift_ram_2 Q-DATA: data = null. /c_shift_ram_2 Q-DATA data field will be interpreted as integer
INFO: [xilinx.com:ip:c_addsub:12.0-308] /c_addsub_1 B-DATA: Validating field: data(16:0): int16 against /c_shift_ram_3 Q-DATA: data(16:0): bit16.
WARNING: [xilinx.com:ip:c_addsub:12.0-313] /c_addsub_1 B-DATA: Field type resolution: data = integer. /c_shift_ram_3 Q-DATA: data = null. /c_shift_ram_3 Q-DATA data field will be interpreted as integer
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_2 A_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_2 B_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:fir_compiler:7.2-913] /fir_compiler_1 Data_Sign has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:fir_compiler:7.2-913] /fir_compiler_1 Data_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:fir_compiler:7.2-913] /fir_compiler_1 Data_Fractional_Bits has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:cic_compiler:4.0-913] /cic_compiler_0 Input_Data_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:fir_compiler:7.2-913] /fir_compiler_0 Data_Sign has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:fir_compiler:7.2-913] /fir_compiler_0 Data_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:fir_compiler:7.2-913] /fir_compiler_0 Data_Fractional_Bits has been set to manual on the GUI. It will not be updated during validation with a propagated value.
WARNING: [BD 41-927] Following properties on pin /timemux_0/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
	CLK_DOMAIN=/clk_wiz_0_clk_out1 
WARNING: [BD 41-927] Following properties on pin /demux16_sync_0/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
	CLK_DOMAIN=/clk_wiz_0_clk_out1 
Wrote  : <D:\sound_location_project\vivado\dat096-master-latest_version\latest_version\dat096_ref_design.srcs\sources_1\bd\pdm_to_pcm\pdm_to_pcm.bd> 
VHDL Output written to : D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/synth/pdm_to_pcm.vhd
VHDL Output written to : D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/sim/pdm_to_pcm.vhd
VHDL Output written to : D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.vhd
INFO: [IP_Flow 19-234] Refreshing IP repositories
WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'd:/sound_location_project/vivado/dat096-master-latest_version/sound_location_project'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
INFO: [IP_Flow 19-234] Refreshing IP repositories
WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'd:/sound_location_project/vivado/dat096-master-latest_version/sound_location_project'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
INFO: [IP_Flow 19-234] Refreshing IP repositories
WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'd:/sound_location_project/vivado/dat096-master-latest_version/sound_location_project'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
INFO: [IP_Flow 19-234] Refreshing IP repositories
WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'd:/sound_location_project/vivado/dat096-master-latest_version/sound_location_project'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
INFO: [BD 41-1029] Generation completed for the IP Integrator block cic_compiler_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block fir_compiler_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block fir_compiler_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block clk_wiz_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block fifo_generator_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block util_vector_logic_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block clk_div_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block util_ds_buf_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block clk_div_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block hp_filter_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block util_vector_logic_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block timemux_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block demux16_sync_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_addsub_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_addsub_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_addsub_2 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block blk_mem_gen_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block blk_mem_gen_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_shift_ram_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_shift_ram_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_shift_ram_2 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_shift_ram_3 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block blk_mem_gen_2 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block blk_mem_gen_3 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block scan_0 .
Exporting to file D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hw_handoff/pdm_to_pcm.hwh
Generated Block Design Tcl file D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hw_handoff/pdm_to_pcm_bd.tcl
Generated Hardware Definition File D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/synth/pdm_to_pcm.hwdef
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/clean_rst.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/decoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/encoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_constants.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_regs.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_test.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/timescale.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_an.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_mdio.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_rx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_sync.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_tx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/ddr/mig_interface_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/i2c/i2c_slave_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/micron/sdram/mobile_sdr.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/clean_rst.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/decoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/encoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_constants.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_regs.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_test.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/timescale.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_an.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_mdio.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_rx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_sync.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_tx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/ddr/mig_interface_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/i2c/i2c_slave_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/micron/sdram/mobile_sdr.v:]
[Thu May 14 00:09:33 2020] Launched pdm_to_pcm_scan_0_0_synth_1...
Run output will be captured here: D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.runs/pdm_to_pcm_scan_0_0_synth_1/runme.log
[Thu May 14 00:09:33 2020] Launched synth_2...
Run output will be captured here: D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.runs/synth_2/runme.log
launch_runs: Time (s): cpu = 00:00:09 ; elapsed = 00:00:19 . Memory (MB): peak = 2032.301 ; gain = 0.000
reset_run pdm_to_pcm_scan_0_0_synth_1
reset_run synth_2
launch_runs synth_2 -jobs 4
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/clean_rst.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/decoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/encoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_constants.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_regs.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_test.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/timescale.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_an.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_mdio.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_rx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_sync.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_tx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/ddr/mig_interface_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/i2c/i2c_slave_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/micron/sdram/mobile_sdr.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/clean_rst.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/decoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/encoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_constants.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_regs.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_test.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/timescale.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_an.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_mdio.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_rx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_sync.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_tx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/ddr/mig_interface_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/i2c/i2c_slave_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/micron/sdram/mobile_sdr.v:]
[Thu May 14 00:11:17 2020] Launched pdm_to_pcm_scan_0_0_synth_1...
Run output will be captured here: D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.runs/pdm_to_pcm_scan_0_0_synth_1/runme.log
[Thu May 14 00:11:18 2020] Launched synth_2...
Run output will be captured here: D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.runs/synth_2/runme.log
update_module_reference pdm_to_pcm_scan_0_0
INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing.
INFO: [IP_Flow 19-234] Refreshing IP repositories
WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'd:/sound_location_project/vivado/dat096-master-latest_version/sound_location_project'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
Upgrading 'D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/pdm_to_pcm.bd'
INFO: [IP_Flow 19-3420] Updated pdm_to_pcm_scan_0_0 to use current project options
WARNING: [BD 41-1731] Type mismatch between connected pins: /clk_div_1/clk_out(undef) and /scan_0_upgraded_ipi/clk(clk)
WARNING: [BD 41-1731] Type mismatch between connected pins: /c_addsub_1/CE(ce) and /scan_0_upgraded_ipi/adder_enable(undef)
WARNING: [BD 41-1731] Type mismatch between connected pins: /c_addsub_0/CE(ce) and /scan_0_upgraded_ipi/adder_enable(undef)
WARNING: [BD 41-1731] Type mismatch between connected pins: /c_addsub_2/CE(ce) and /scan_0_upgraded_ipi/adder_enable(undef)
WARNING: [BD 41-1731] Type mismatch between connected pins: /c_shift_ram_0/CE(ce) and /scan_0_upgraded_ipi/scan_finish(undef)
WARNING: [BD 41-1731] Type mismatch between connected pins: /c_shift_ram_1/CE(ce) and /scan_0_upgraded_ipi/scan_finish(undef)
WARNING: [BD 41-1731] Type mismatch between connected pins: /c_shift_ram_2/CE(ce) and /scan_0_upgraded_ipi/scan_finish(undef)
WARNING: [BD 41-1731] Type mismatch between connected pins: /c_shift_ram_3/CE(ce) and /scan_0_upgraded_ipi/scan_finish(undef)
Wrote  : <D:\sound_location_project\vivado\dat096-master-latest_version\latest_version\dat096_ref_design.srcs\sources_1\bd\pdm_to_pcm\pdm_to_pcm.bd> 
update_module_reference: Time (s): cpu = 00:00:03 ; elapsed = 00:00:16 . Memory (MB): peak = 2032.301 ; gain = 0.000
reset_run synth_2
launch_runs synth_2 -jobs 4
WARNING: [BD 41-2180] Resetting the memory initialization file of </blk_mem_gen_0> to default.
WARNING: [BD 41-2180] Resetting the memory initialization file of </blk_mem_gen_3> to default.
WARNING: [BD 41-2180] Resetting the memory initialization file of </blk_mem_gen_1> to default.
WARNING: [BD 41-2180] Resetting the memory initialization file of </blk_mem_gen_2> to default.
WARNING: [xilinx.com:ip:c_addsub:12.0-313] /c_addsub_0 A-DATA: Field type resolution: data = integer. /c_shift_ram_0 Q-DATA: data = null. /c_shift_ram_0 Q-DATA data field will be interpreted as integer
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_0 A_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
WARNING: [xilinx.com:ip:c_addsub:12.0-313] /c_addsub_0 B-DATA: Field type resolution: data = integer. /c_shift_ram_1 Q-DATA: data = null. /c_shift_ram_1 Q-DATA data field will be interpreted as integer
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_0 B_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:c_addsub:12.0-308] /c_addsub_0 A-DATA: Validating field: data(16:0): int16 against /c_shift_ram_0 Q-DATA: data(16:0): bit16.
WARNING: [xilinx.com:ip:c_addsub:12.0-313] /c_addsub_0 A-DATA: Field type resolution: data = integer. /c_shift_ram_0 Q-DATA: data = null. /c_shift_ram_0 Q-DATA data field will be interpreted as integer
INFO: [xilinx.com:ip:c_addsub:12.0-308] /c_addsub_0 B-DATA: Validating field: data(16:0): int16 against /c_shift_ram_1 Q-DATA: data(16:0): bit16.
WARNING: [xilinx.com:ip:c_addsub:12.0-313] /c_addsub_0 B-DATA: Field type resolution: data = integer. /c_shift_ram_1 Q-DATA: data = null. /c_shift_ram_1 Q-DATA data field will be interpreted as integer
WARNING: [xilinx.com:ip:c_addsub:12.0-313] /c_addsub_1 A-DATA: Field type resolution: data = integer. /c_shift_ram_2 Q-DATA: data = null. /c_shift_ram_2 Q-DATA data field will be interpreted as integer
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_1 A_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
WARNING: [xilinx.com:ip:c_addsub:12.0-313] /c_addsub_1 B-DATA: Field type resolution: data = integer. /c_shift_ram_3 Q-DATA: data = null. /c_shift_ram_3 Q-DATA data field will be interpreted as integer
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_1 B_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:c_addsub:12.0-308] /c_addsub_1 A-DATA: Validating field: data(16:0): int16 against /c_shift_ram_2 Q-DATA: data(16:0): bit16.
WARNING: [xilinx.com:ip:c_addsub:12.0-313] /c_addsub_1 A-DATA: Field type resolution: data = integer. /c_shift_ram_2 Q-DATA: data = null. /c_shift_ram_2 Q-DATA data field will be interpreted as integer
INFO: [xilinx.com:ip:c_addsub:12.0-308] /c_addsub_1 B-DATA: Validating field: data(16:0): int16 against /c_shift_ram_3 Q-DATA: data(16:0): bit16.
WARNING: [xilinx.com:ip:c_addsub:12.0-313] /c_addsub_1 B-DATA: Field type resolution: data = integer. /c_shift_ram_3 Q-DATA: data = null. /c_shift_ram_3 Q-DATA data field will be interpreted as integer
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_2 A_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_2 B_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:fir_compiler:7.2-913] /fir_compiler_1 Data_Sign has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:fir_compiler:7.2-913] /fir_compiler_1 Data_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:fir_compiler:7.2-913] /fir_compiler_1 Data_Fractional_Bits has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:cic_compiler:4.0-913] /cic_compiler_0 Input_Data_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:fir_compiler:7.2-913] /fir_compiler_0 Data_Sign has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:fir_compiler:7.2-913] /fir_compiler_0 Data_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:fir_compiler:7.2-913] /fir_compiler_0 Data_Fractional_Bits has been set to manual on the GUI. It will not be updated during validation with a propagated value.
WARNING: [BD 41-927] Following properties on pin /timemux_0/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
	CLK_DOMAIN=/clk_wiz_0_clk_out1 
WARNING: [BD 41-927] Following properties on pin /demux16_sync_0/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
	CLK_DOMAIN=/clk_wiz_0_clk_out1 
Wrote  : <D:\sound_location_project\vivado\dat096-master-latest_version\latest_version\dat096_ref_design.srcs\sources_1\bd\pdm_to_pcm\pdm_to_pcm.bd> 
VHDL Output written to : D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/synth/pdm_to_pcm.vhd
VHDL Output written to : D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/sim/pdm_to_pcm.vhd
VHDL Output written to : D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.vhd
INFO: [BD 41-1029] Generation completed for the IP Integrator block cic_compiler_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block fir_compiler_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block fir_compiler_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block clk_wiz_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block fifo_generator_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block util_vector_logic_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block clk_div_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block util_ds_buf_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block clk_div_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block hp_filter_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block util_vector_logic_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block timemux_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block demux16_sync_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_addsub_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_addsub_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_addsub_2 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block blk_mem_gen_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block blk_mem_gen_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_shift_ram_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_shift_ram_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_shift_ram_2 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_shift_ram_3 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block blk_mem_gen_2 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block blk_mem_gen_3 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block scan_0 .
Exporting to file D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hw_handoff/pdm_to_pcm.hwh
Generated Block Design Tcl file D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hw_handoff/pdm_to_pcm_bd.tcl
Generated Hardware Definition File D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/synth/pdm_to_pcm.hwdef
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/clean_rst.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/decoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/encoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_constants.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_regs.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_test.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/timescale.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_an.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_mdio.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_rx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_sync.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_tx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/ddr/mig_interface_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/i2c/i2c_slave_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/micron/sdram/mobile_sdr.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/clean_rst.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/decoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/encoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_constants.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_regs.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_test.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/timescale.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_an.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_mdio.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_rx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_sync.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_tx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/ddr/mig_interface_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/i2c/i2c_slave_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/micron/sdram/mobile_sdr.v:]
[Thu May 14 00:13:11 2020] Launched pdm_to_pcm_scan_0_0_synth_1...
Run output will be captured here: D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.runs/pdm_to_pcm_scan_0_0_synth_1/runme.log
[Thu May 14 00:13:12 2020] Launched synth_2...
Run output will be captured here: D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.runs/synth_2/runme.log
launch_runs: Time (s): cpu = 00:00:03 ; elapsed = 00:00:11 . Memory (MB): peak = 2032.301 ; gain = 0.000
launch_runs impl_2 -jobs 4
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/clean_rst.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/decoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/encoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_constants.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_regs.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_test.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/timescale.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_an.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_mdio.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_rx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_sync.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_tx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/ddr/mig_interface_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/i2c/i2c_slave_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/micron/sdram/mobile_sdr.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/clean_rst.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/decoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/encoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_constants.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_regs.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_test.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/timescale.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_an.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_mdio.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_rx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_sync.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_tx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/ddr/mig_interface_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/i2c/i2c_slave_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/micron/sdram/mobile_sdr.v:]
[Thu May 14 00:24:23 2020] Launched impl_2...
Run output will be captured here: D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.runs/impl_2/runme.log
launch_runs impl_2 -to_step write_bitstream -jobs 4
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/clean_rst.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/decoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/encoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_constants.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_regs.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_test.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/timescale.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_an.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_mdio.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_rx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_sync.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_tx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/ddr/mig_interface_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/i2c/i2c_slave_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/micron/sdram/mobile_sdr.v:]
[Thu May 14 01:01:21 2020] Launched impl_2...
Run output will be captured here: D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.runs/impl_2/runme.log
open_hw
connect_hw_server
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
INFO: [Labtools 27-2222] Launching hw_server...
INFO: [Labtools 27-2221] Launch Output:

****** Xilinx hw_server v2019.1
  **** Build date : May 24 2019 at 15:13:31
    ** Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.


connect_hw_server: Time (s): cpu = 00:00:01 ; elapsed = 00:00:07 . Memory (MB): peak = 3046.414 ; gain = 0.000
open_hw_target
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210203857806A
set_property PROGRAM.FILE {D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.runs/impl_1/leon3mp.bit} [get_hw_devices xc7a200t_0]
current_hw_device [get_hw_devices xc7a200t_0]
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a200t_0] 0]
INFO: [Labtools 27-1435] Device xc7a200t (JTAG device index = 0) is not programmed (DONE status = 0).
set_property PROBES.FILE {} [get_hw_devices xc7a200t_0]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7a200t_0]
set_property PROGRAM.FILE {D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.runs/impl_1/leon3mp.bit} [get_hw_devices xc7a200t_0]
program_hw_devices [get_hw_devices xc7a200t_0]
INFO: [Labtools 27-3164] End of startup status: HIGH
program_hw_devices: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 3237.508 ; gain = 0.000
refresh_hw_device [lindex [get_hw_devices xc7a200t_0] 0]
INFO: [Labtools 27-1434] Device xc7a200t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
open_bd_design {D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/pdm_to_pcm.bd}
ERROR: [Labtoolstcl 44-513] HW Target shutdown. Closing target: localhost:3121/xilinx_tcf/Digilent/210203857806A
exit
INFO: [Common 17-206] Exiting Vivado at Thu May 14 01:48:32 2020...
