{
  "design": {
    "design_info": {
      "boundary_crc": "0x7BA6A2FF47BBB31C",
      "device": "xc7a200tfbg676-2",
      "name": "pdm_to_pcm",
      "synth_flow_mode": "Hierarchical",
      "tool_version": "2019.1"
    },
    "design_tree": {
      "cic_compiler_0": "",
      "fir_compiler_0": "",
      "fir_compiler_1": "",
      "clk_wiz_0": "",
      "fifo_generator_0": "",
      "util_vector_logic_0": "",
      "util_ds_buf_0": "",
      "clk_div_1": "",
      "util_vector_logic_1": "",
      "blk_mem_gen_0": "",
      "blk_mem_gen_1": "",
      "c_shift_ram_0": "",
      "c_shift_ram_1": "",
      "c_shift_ram_2": "",
      "c_shift_ram_3": "",
      "blk_mem_gen_2": "",
      "blk_mem_gen_3": "",
      "clk_div_0": "",
      "hp_filter_0": "",
      "timemux_0": "",
      "demux16_sync_0": "",
      "energy_compare_0": "",
      "arithm_block_0": "",
      "scan_0": ""
    },
    "ports": {
      "resetn": {
        "type": "rst",
        "direction": "I"
      },
      "pdm_clk": {
        "type": "clk",
        "direction": "O",
        "left": "0",
        "right": "0"
      },
      "sys_clock": {
        "type": "clk",
        "direction": "I",
        "parameters": {
          "FREQ_HZ": {
            "value": "100000000"
          }
        }
      },
      "start": {
        "direction": "I"
      },
      "pcm_data": {
        "type": "data",
        "direction": "O",
        "left": "31",
        "right": "0"
      },
      "fifo_almost_full": {
        "direction": "O"
      },
      "fifo_almost_empty": {
        "direction": "O"
      },
      "fifo_rd_clk": {
        "type": "clk",
        "direction": "I",
        "parameters": {
          "FREQ_HZ": {
            "value": "100000000"
          }
        }
      },
      "fifo_rd_en": {
        "direction": "I"
      },
      "pdm_data": {
        "type": "data",
        "direction": "I",
        "left": "3",
        "right": "0"
      }
    },
    "components": {
      "cic_compiler_0": {
        "vlnv": "xilinx.com:ip:cic_compiler:4.0",
        "xci_name": "pdm_to_pcm_cic_compiler_0_0",
        "parameters": {
          "Clock_Frequency": {
            "value": "12.8"
          },
          "Filter_Type": {
            "value": "Decimation"
          },
          "Fixed_Or_Initial_Rate": {
            "value": "16"
          },
          "HAS_DOUT_TREADY": {
            "value": "true"
          },
          "Input_Data_Width": {
            "value": "2"
          },
          "Input_Sample_Frequency": {
            "value": "3.2"
          },
          "Maximum_Rate": {
            "value": "16"
          },
          "Minimum_Rate": {
            "value": "16"
          },
          "Number_Of_Channels": {
            "value": "4"
          },
          "Number_Of_Stages": {
            "value": "5"
          },
          "Output_Data_Width": {
            "value": "22"
          },
          "RateSpecification": {
            "value": "Frequency_Specification"
          },
          "SamplePeriod": {
            "value": "1"
          }
        }
      },
      "fir_compiler_0": {
        "vlnv": "xilinx.com:ip:fir_compiler:7.2",
        "xci_name": "pdm_to_pcm_fir_compiler_0_0",
        "parameters": {
          "Channel_Sequence": {
            "value": "Basic"
          },
          "Clock_Frequency": {
            "value": "12.8"
          },
          "CoefficientSource": {
            "value": "COE_File"
          },
          "Coefficient_File": {
            "value": "../../../../../../../../../dat096-master-coeff files/coeff files/halfband_ultrasonic.coe"
          },
          "Coefficient_Fractional_Bits": {
            "value": "0"
          },
          "Coefficient_Sets": {
            "value": "1"
          },
          "Coefficient_Sign": {
            "value": "Signed"
          },
          "Coefficient_Structure": {
            "value": "Half_Band"
          },
          "Coefficient_Width": {
            "value": "16"
          },
          "ColumnConfig": {
            "value": "1"
          },
          "DATA_Has_TLAST": {
            "value": "Packet_Framing"
          },
          "Data_Fractional_Bits": {
            "value": "0"
          },
          "Data_Sign": {
            "value": "Signed"
          },
          "Data_Width": {
            "value": "22"
          },
          "Decimation_Rate": {
            "value": "2"
          },
          "Filter_Architecture": {
            "value": "Systolic_Multiply_Accumulate"
          },
          "Filter_Type": {
            "value": "Decimation"
          },
          "Interpolation_Rate": {
            "value": "1"
          },
          "M_DATA_Has_TREADY": {
            "value": "true"
          },
          "M_DATA_Has_TUSER": {
            "value": "Not_Required"
          },
          "Number_Channels": {
            "value": "4"
          },
          "Output_Rounding_Mode": {
            "value": "Truncate_LSBs"
          },
          "Output_Width": {
            "value": "22"
          },
          "Quantization": {
            "value": "Integer_Coefficients"
          },
          "RateSpecification": {
            "value": "Frequency_Specification"
          },
          "S_DATA_Has_FIFO": {
            "value": "true"
          },
          "S_DATA_Has_TUSER": {
            "value": "Not_Required"
          },
          "Sample_Frequency": {
            "value": "0.2"
          },
          "Select_Pattern": {
            "value": "All"
          },
          "Zero_Pack_Factor": {
            "value": "1"
          }
        }
      },
      "fir_compiler_1": {
        "vlnv": "xilinx.com:ip:fir_compiler:7.2",
        "xci_name": "pdm_to_pcm_fir_compiler_1_0",
        "parameters": {
          "Clock_Frequency": {
            "value": "12.8"
          },
          "CoefficientSource": {
            "value": "COE_File"
          },
          "Coefficient_File": {
            "value": "../../../../../../../../../dat096-master-coeff files/coeff files/lowpass_ultrasonic.coe"
          },
          "Coefficient_Fractional_Bits": {
            "value": "0"
          },
          "Coefficient_Sets": {
            "value": "1"
          },
          "Coefficient_Sign": {
            "value": "Signed"
          },
          "Coefficient_Structure": {
            "value": "Symmetric"
          },
          "Coefficient_Width": {
            "value": "20"
          },
          "ColumnConfig": {
            "value": "3"
          },
          "DATA_Has_TLAST": {
            "value": "Packet_Framing"
          },
          "Data_Fractional_Bits": {
            "value": "0"
          },
          "Data_Sign": {
            "value": "Signed"
          },
          "Data_Width": {
            "value": "22"
          },
          "Filter_Architecture": {
            "value": "Systolic_Multiply_Accumulate"
          },
          "M_DATA_Has_TREADY": {
            "value": "true"
          },
          "M_DATA_Has_TUSER": {
            "value": "Not_Required"
          },
          "Number_Channels": {
            "value": "4"
          },
          "Output_Rounding_Mode": {
            "value": "Truncate_LSBs"
          },
          "Output_Width": {
            "value": "22"
          },
          "Quantization": {
            "value": "Integer_Coefficients"
          },
          "S_DATA_Has_FIFO": {
            "value": "true"
          },
          "S_DATA_Has_TUSER": {
            "value": "Not_Required"
          },
          "Sample_Frequency": {
            "value": "0.1"
          },
          "Select_Pattern": {
            "value": "All"
          }
        }
      },
      "clk_wiz_0": {
        "vlnv": "xilinx.com:ip:clk_wiz:6.0",
        "xci_name": "pdm_to_pcm_clk_wiz_0_0",
        "parameters": {
          "CLKIN1_JITTER_PS": {
            "value": "100.0"
          },
          "CLKOUT1_JITTER": {
            "value": "199.846"
          },
          "CLKOUT1_PHASE_ERROR": {
            "value": "98.575"
          },
          "CLKOUT1_REQUESTED_OUT_FREQ": {
            "value": "12.8"
          },
          "MMCM_CLKFBOUT_MULT_F": {
            "value": "10.000"
          },
          "MMCM_CLKIN1_PERIOD": {
            "value": "10.000"
          },
          "MMCM_CLKOUT0_DIVIDE_F": {
            "value": "78.125"
          },
          "MMCM_DIVCLK_DIVIDE": {
            "value": "1"
          },
          "PRIM_IN_FREQ": {
            "value": "100.000"
          },
          "RESET_PORT": {
            "value": "resetn"
          },
          "RESET_TYPE": {
            "value": "ACTIVE_LOW"
          }
        }
      },
      "fifo_generator_0": {
        "vlnv": "xilinx.com:ip:fifo_generator:13.2",
        "xci_name": "pdm_to_pcm_fifo_generator_0_0",
        "parameters": {
          "Almost_Empty_Flag": {
            "value": "true"
          },
          "Almost_Full_Flag": {
            "value": "true"
          },
          "Enable_ECC": {
            "value": "false"
          },
          "Fifo_Implementation": {
            "value": "Independent_Clocks_Block_RAM"
          },
          "Input_Data_Width": {
            "value": "32"
          },
          "Input_Depth": {
            "value": "8192"
          },
          "Output_Data_Width": {
            "value": "32"
          },
          "Overflow_Flag": {
            "value": "true"
          },
          "Performance_Options": {
            "value": "First_Word_Fall_Through"
          },
          "Reset_Pin": {
            "value": "false"
          },
          "Underflow_Flag": {
            "value": "true"
          },
          "Use_Embedded_Registers": {
            "value": "false"
          },
          "Valid_Flag": {
            "value": "true"
          },
          "Write_Acknowledge_Flag": {
            "value": "true"
          }
        }
      },
      "util_vector_logic_0": {
        "vlnv": "xilinx.com:ip:util_vector_logic:2.0",
        "xci_name": "pdm_to_pcm_util_vector_logic_0_0",
        "parameters": {
          "C_OPERATION": {
            "value": "not"
          },
          "C_SIZE": {
            "value": "1"
          }
        }
      },
      "util_ds_buf_0": {
        "vlnv": "xilinx.com:ip:util_ds_buf:2.1",
        "xci_name": "pdm_to_pcm_util_ds_buf_0_0",
        "parameters": {
          "C_BUF_TYPE": {
            "value": "BUFG"
          }
        }
      },
      "clk_div_1": {
        "vlnv": "xilinx.com:module_ref:clk_div:1.0",
        "xci_name": "pdm_to_pcm_clk_div_1_0",
        "reference_info": {
          "ref_type": "hdl",
          "ref_name": "clk_div",
          "boundary_crc": "0x0"
        },
        "ports": {
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            "direction": "O"
          },
          "clk_in": {
            "direction": "I"
          },
          "clk_en": {
            "direction": "I"
          },
          "clr": {
            "direction": "I"
          }
        }
      },
      "util_vector_logic_1": {
        "vlnv": "xilinx.com:ip:util_vector_logic:2.0",
        "xci_name": "pdm_to_pcm_util_vector_logic_0_2",
        "parameters": {
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            "value": "not"
          },
          "C_SIZE": {
            "value": "1"
          }
        }
      },
      "blk_mem_gen_0": {
        "vlnv": "xilinx.com:ip:blk_mem_gen:8.4",
        "xci_name": "pdm_to_pcm_blk_mem_gen_0_0",
        "parameters": {
          "Coe_File": {
            "value": "../../../../../../../../../../project_vhdlcode/newvalue.coe"
          },
          "Enable_32bit_Address": {
            "value": "false"
          },
          "Enable_A": {
            "value": "Always_Enabled"
          },
          "Load_Init_File": {
            "value": "true"
          },
          "Memory_Type": {
            "value": "Single_Port_ROM"
          },
          "Port_A_Write_Rate": {
            "value": "0"
          },
          "Register_PortA_Output_of_Memory_Primitives": {
            "value": "false"
          },
          "Use_RSTA_Pin": {
            "value": "false"
          },
          "Write_Depth_A": {
            "value": "482"
          },
          "Write_Width_A": {
            "value": "10"
          },
          "use_bram_block": {
            "value": "Stand_Alone"
          }
        }
      },
      "blk_mem_gen_1": {
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        "xci_name": "pdm_to_pcm_blk_mem_gen_1_0",
        "parameters": {
          "Coe_File": {
            "value": "../../../../../../../../../../project_vhdlcode/newvalue.coe"
          },
          "Enable_32bit_Address": {
            "value": "false"
          },
          "Enable_A": {
            "value": "Always_Enabled"
          },
          "Load_Init_File": {
            "value": "true"
          },
          "Memory_Type": {
            "value": "Single_Port_ROM"
          },
          "Port_A_Write_Rate": {
            "value": "0"
          },
          "Register_PortA_Output_of_Memory_Primitives": {
            "value": "true"
          },
          "Use_RSTA_Pin": {
            "value": "false"
          },
          "Write_Depth_A": {
            "value": "482"
          },
          "Write_Width_A": {
            "value": "10"
          },
          "use_bram_block": {
            "value": "Stand_Alone"
          }
        }
      },
      "c_shift_ram_0": {
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        "xci_name": "pdm_to_pcm_c_shift_ram_0_0",
        "parameters": {
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            "value": "true"
          },
          "Depth": {
            "value": "663"
          },
          "SSET": {
            "value": "false"
          },
          "ShiftRegType": {
            "value": "Variable_Length_Lossless"
          }
        }
      },
      "c_shift_ram_1": {
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        "xci_name": "pdm_to_pcm_c_shift_ram_1_0",
        "parameters": {
          "CE": {
            "value": "true"
          },
          "Depth": {
            "value": "663"
          },
          "RegLastBit": {
            "value": "true"
          },
          "ShiftRegType": {
            "value": "Variable_Length_Lossless"
          }
        }
      },
      "c_shift_ram_2": {
        "vlnv": "xilinx.com:ip:c_shift_ram:12.0",
        "xci_name": "pdm_to_pcm_c_shift_ram_1_1",
        "parameters": {
          "CE": {
            "value": "true"
          },
          "Depth": {
            "value": "663"
          },
          "RegLastBit": {
            "value": "true"
          },
          "ShiftRegType": {
            "value": "Variable_Length_Lossless"
          }
        }
      },
      "c_shift_ram_3": {
        "vlnv": "xilinx.com:ip:c_shift_ram:12.0",
        "xci_name": "pdm_to_pcm_c_shift_ram_1_2",
        "parameters": {
          "CE": {
            "value": "true"
          },
          "Depth": {
            "value": "663"
          },
          "RegLastBit": {
            "value": "true"
          },
          "ShiftRegType": {
            "value": "Variable_Length_Lossless"
          }
        }
      },
      "blk_mem_gen_2": {
        "vlnv": "xilinx.com:ip:blk_mem_gen:8.4",
        "xci_name": "pdm_to_pcm_blk_mem_gen_1_1",
        "parameters": {
          "Coe_File": {
            "value": "../../../../../../../../../../project_vhdlcode/newvalue.coe"
          },
          "Enable_32bit_Address": {
            "value": "false"
          },
          "Enable_A": {
            "value": "Always_Enabled"
          },
          "Load_Init_File": {
            "value": "true"
          },
          "Memory_Type": {
            "value": "Single_Port_ROM"
          },
          "Port_A_Write_Rate": {
            "value": "0"
          },
          "Register_PortA_Output_of_Memory_Primitives": {
            "value": "true"
          },
          "Use_RSTA_Pin": {
            "value": "false"
          },
          "Write_Depth_A": {
            "value": "482"
          },
          "Write_Width_A": {
            "value": "10"
          },
          "use_bram_block": {
            "value": "Stand_Alone"
          }
        }
      },
      "blk_mem_gen_3": {
        "vlnv": "xilinx.com:ip:blk_mem_gen:8.4",
        "xci_name": "pdm_to_pcm_blk_mem_gen_2_0",
        "parameters": {
          "Coe_File": {
            "value": "../../../../../../../../../../project_vhdlcode/newvalue.coe"
          },
          "Enable_32bit_Address": {
            "value": "false"
          },
          "Enable_A": {
            "value": "Always_Enabled"
          },
          "Load_Init_File": {
            "value": "true"
          },
          "Memory_Type": {
            "value": "Single_Port_ROM"
          },
          "Port_A_Write_Rate": {
            "value": "0"
          },
          "Register_PortA_Output_of_Memory_Primitives": {
            "value": "true"
          },
          "Use_RSTA_Pin": {
            "value": "false"
          },
          "Write_Depth_A": {
            "value": "482"
          },
          "Write_Width_A": {
            "value": "10"
          },
          "use_bram_block": {
            "value": "Stand_Alone"
          }
        }
      },
      "clk_div_0": {
        "vlnv": "xilinx.com:module_ref:clk_div:1.0",
        "xci_name": "pdm_to_pcm_clk_div_0_0",
        "reference_info": {
          "ref_type": "hdl",
          "ref_name": "clk_div",
          "boundary_crc": "0x0"
        },
        "ports": {
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          },
          "clk_in": {
            "direction": "I"
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          "clk_en": {
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          },
          "clr": {
            "direction": "I"
          }
        }
      },
      "hp_filter_0": {
        "vlnv": "xilinx.com:module_ref:hp_filter:1.0",
        "xci_name": "pdm_to_pcm_hp_filter_0_0",
        "reference_info": {
          "ref_type": "hdl",
          "ref_name": "hp_filter",
          "boundary_crc": "0x0"
        },
        "ports": {
          "din": {
            "direction": "I",
            "left": "23",
            "right": "0"
          },
          "dout": {
            "direction": "O",
            "left": "15",
            "right": "0"
          }
        }
      },
      "timemux_0": {
        "vlnv": "xilinx.com:module_ref:timemux:1.0",
        "xci_name": "pdm_to_pcm_timemux_0_2",
        "reference_info": {
          "ref_type": "hdl",
          "ref_name": "timemux",
          "boundary_crc": "0x0"
        },
        "interface_ports": {
          "data": {
            "mode": "Master",
            "vlnv": "xilinx.com:interface:axis_rtl:1.0",
            "parameters": {
              "CLK_DOMAIN": {
                "value": "/clk_wiz_0_clk_out1",
                "value_src": "ip_prop"
              },
              "FREQ_HZ": {
                "value": "18431963",
                "value_src": "ip_prop"
              },
              "HAS_TKEEP": {
                "value": "0",
                "value_src": "constant"
              },
              "HAS_TLAST": {
                "value": "1",
                "value_src": "constant"
              },
              "HAS_TREADY": {
                "value": "0",
                "value_src": "constant"
              },
              "HAS_TSTRB": {
                "value": "0",
                "value_src": "constant"
              },
              "PHASE": {
                "value": "0.0",
                "value_src": "ip_prop"
              },
              "TDATA_NUM_BYTES": {
                "value": "0",
                "value_src": "constant"
              },
              "TDEST_WIDTH": {
                "value": "0",
                "value_src": "constant"
              },
              "TID_WIDTH": {
                "value": "0",
                "value_src": "constant"
              },
              "TUSER_WIDTH": {
                "value": "0",
                "value_src": "constant"
              }
            },
            "port_maps": {
              "TLAST": {
                "physical_name": "data_tlast",
                "direction": "O"
              },
              "TVALID": {
                "physical_name": "data_tvalid",
                "direction": "O"
              }
            }
          }
        },
        "ports": {
          "clk": {
            "type": "clk",
            "direction": "I"
          },
          "start": {
            "direction": "I"
          },
          "pdm_data": {
            "direction": "I",
            "left": "3",
            "right": "0"
          },
          "pdm_data_mux": {
            "direction": "O",
            "left": "7",
            "right": "0"
          }
        }
      },
      "demux16_sync_0": {
        "vlnv": "xilinx.com:module_ref:demux16_sync:1.0",
        "xci_name": "pdm_to_pcm_demux16_sync_0_0",
        "reference_info": {
          "ref_type": "hdl",
          "ref_name": "demux16_sync",
          "boundary_crc": "0x0"
        },
        "ports": {
          "clk": {
            "type": "clk",
            "direction": "I"
          },
          "t_valid": {
            "direction": "I"
          },
          "t_last": {
            "direction": "I"
          },
          "output_data0": {
            "direction": "O",
            "left": "15",
            "right": "0"
          },
          "output_data1": {
            "direction": "O",
            "left": "15",
            "right": "0"
          },
          "output_data2": {
            "direction": "O",
            "left": "15",
            "right": "0"
          },
          "output_data3": {
            "direction": "O",
            "left": "15",
            "right": "0"
          },
          "finish": {
            "direction": "O"
          },
          "input_data": {
            "direction": "I",
            "left": "15",
            "right": "0"
          }
        }
      },
      "energy_compare_0": {
        "vlnv": "xilinx.com:module_ref:energy_compare:1.0",
        "xci_name": "pdm_to_pcm_energy_compare_0_0",
        "reference_info": {
          "ref_type": "hdl",
          "ref_name": "energy_compare",
          "boundary_crc": "0x0"
        },
        "ports": {
          "clk": {
            "type": "clk",
            "direction": "I"
          },
          "start": {
            "direction": "I"
          },
          "val_in": {
            "direction": "I",
            "left": "31",
            "right": "0"
          },
          "max_found": {
            "direction": "O"
          },
          "start_fifo": {
            "direction": "O"
          },
          "val_out": {
            "direction": "O",
            "left": "31",
            "right": "0"
          }
        }
      },
      "arithm_block_0": {
        "vlnv": "xilinx.com:module_ref:arithm_block:1.0",
        "xci_name": "pdm_to_pcm_arithm_block_0_0",
        "reference_info": {
          "ref_type": "hdl",
          "ref_name": "arithm_block",
          "boundary_crc": "0x0"
        },
        "ports": {
          "clk": {
            "type": "clk",
            "direction": "I"
          },
          "smand0": {
            "direction": "I",
            "left": "15",
            "right": "0"
          },
          "smand1": {
            "direction": "I",
            "left": "15",
            "right": "0"
          },
          "smand2": {
            "direction": "I",
            "left": "15",
            "right": "0"
          },
          "smand3": {
            "direction": "I",
            "left": "15",
            "right": "0"
          },
          "adder_enable": {
            "direction": "I"
          },
          "en_enable": {
            "direction": "O"
          },
          "val_out": {
            "direction": "O",
            "left": "31",
            "right": "0"
          }
        }
      },
      "scan_0": {
        "vlnv": "xilinx.com:module_ref:scan:1.0",
        "xci_name": "pdm_to_pcm_scan_0_0",
        "reference_info": {
          "ref_type": "hdl",
          "ref_name": "scan",
          "boundary_crc": "0x0"
        },
        "ports": {
          "clk": {
            "type": "clk",
            "direction": "I"
          },
          "start": {
            "direction": "I"
          },
          "t_finish": {
            "direction": "I"
          },
          "max_found": {
            "direction": "I"
          },
          "adder_enable": {
            "direction": "O"
          },
          "delay_enable": {
            "direction": "O"
          },
          "scan_finish": {
            "direction": "O"
          },
          "address_0": {
            "direction": "O",
            "left": "8",
            "right": "0"
          },
          "address_1": {
            "direction": "O",
            "left": "8",
            "right": "0"
          },
          "address_2": {
            "direction": "O",
            "left": "8",
            "right": "0"
          },
          "address_3": {
            "direction": "O",
            "left": "8",
            "right": "0"
          },
          "control_ram": {
            "direction": "O"
          },
          "get_max": {
            "direction": "O"
          },
          "ram_address": {
            "direction": "O",
            "left": "9",
            "right": "0"
          }
        }
      }
    },
    "nets": {
      "sys_clock_1": {
        "ports": [
          "sys_clock",
          "clk_wiz_0/clk_in1"
        ]
      },
      "resetn_1": {
        "ports": [
          "resetn",
          "clk_wiz_0/resetn"
        ]
      },
      "util_vector_logic_0_Res": {
        "ports": [
          "util_vector_logic_0/Res",
          "clk_div_1/clr",
          "clk_div_0/clr"
        ]
      },
      "clk_wiz_0_locked": {
        "ports": [
          "clk_wiz_0/locked",
          "util_vector_logic_0/Op1",
          "clk_div_1/clk_en",
          "clk_div_0/clk_en"
        ]
      },
      "cic_compiler_0_m_axis_data_tdata": {
        "ports": [
          "cic_compiler_0/m_axis_data_tdata",
          "fir_compiler_0/s_axis_data_tdata"
        ]
      },
      "fir_compiler_0_m_axis_data_tdata": {
        "ports": [
          "fir_compiler_0/m_axis_data_tdata",
          "fir_compiler_1/s_axis_data_tdata"
        ]
      },
      "fir_compiler_1_s_axis_data_tready": {
        "ports": [
          "fir_compiler_1/s_axis_data_tready",
          "fir_compiler_0/m_axis_data_tready"
        ]
      },
      "fir_compiler_0_m_axis_data_tvalid": {
        "ports": [
          "fir_compiler_0/m_axis_data_tvalid",
          "fir_compiler_1/s_axis_data_tvalid"
        ]
      },
      "fir_compiler_0_s_axis_data_tready": {
        "ports": [
          "fir_compiler_0/s_axis_data_tready",
          "cic_compiler_0/m_axis_data_tready"
        ]
      },
      "cic_compiler_0_m_axis_data_tvalid": {
        "ports": [
          "cic_compiler_0/m_axis_data_tvalid",
          "fir_compiler_0/s_axis_data_tvalid"
        ]
      },
      "fir_compiler_1_m_axis_data_tdata": {
        "ports": [
          "fir_compiler_1/m_axis_data_tdata",
          "hp_filter_0/din"
        ]
      },
      "fifo_generator_0_dout": {
        "ports": [
          "fifo_generator_0/dout",
          "pcm_data"
        ]
      },
      "fifo_generator_0_almost_empty": {
        "ports": [
          "fifo_generator_0/almost_empty",
          "fifo_almost_empty"
        ]
      },
      "fifo_generator_0_almost_full": {
        "ports": [
          "fifo_generator_0/almost_full",
          "fifo_almost_full"
        ]
      },
      "fifo_rd_clk_1": {
        "ports": [
          "fifo_rd_clk",
          "fifo_generator_0/rd_clk"
        ]
      },
      "fifo_generator_0_full": {
        "ports": [
          "fifo_generator_0/full",
          "util_vector_logic_1/Op1"
        ]
      },
      "util_vector_logic_1_Res": {
        "ports": [
          "util_vector_logic_1/Res",
          "fir_compiler_1/m_axis_data_tready"
        ]
      },
      "util_ds_buf_0_BUFG_O": {
        "ports": [
          "util_ds_buf_0/BUFG_O",
          "pdm_clk"
        ]
      },
      "start_1": {
        "ports": [
          "start",
          "timemux_0/start",
          "scan_0/start"
        ]
      },
      "timemux_0_pdm_data_mux": {
        "ports": [
          "timemux_0/pdm_data_mux",
          "cic_compiler_0/s_axis_data_tdata"
        ]
      },
      "timemux_0_data_tvalid": {
        "ports": [
          "timemux_0/data_tvalid",
          "cic_compiler_0/s_axis_data_tvalid"
        ]
      },
      "clk_div_0_clk_out": {
        "ports": [
          "clk_div_0/clk_out",
          "clk_div_1/clk_in"
        ]
      },
      "pdm_data_1": {
        "ports": [
          "pdm_data",
          "timemux_0/pdm_data"
        ]
      },
      "hp_filter_0_dout": {
        "ports": [
          "hp_filter_0/dout",
          "demux16_sync_0/input_data"
        ]
      },
      "demux16_sync_0_output_data0": {
        "ports": [
          "demux16_sync_0/output_data0",
          "c_shift_ram_0/D"
        ]
      },
      "blk_mem_gen_0_douta": {
        "ports": [
          "blk_mem_gen_0/douta",
          "c_shift_ram_0/A"
        ]
      },
      "blk_mem_gen_1_douta": {
        "ports": [
          "blk_mem_gen_1/douta",
          "c_shift_ram_1/A"
        ]
      },
      "blk_mem_gen_2_douta": {
        "ports": [
          "blk_mem_gen_2/douta",
          "c_shift_ram_2/A"
        ]
      },
      "blk_mem_gen_3_douta": {
        "ports": [
          "blk_mem_gen_3/douta",
          "c_shift_ram_3/A"
        ]
      },
      "clk_wiz_0_clk_out1": {
        "ports": [
          "clk_wiz_0/clk_out1",
          "fir_compiler_0/aclk",
          "fir_compiler_1/aclk",
          "cic_compiler_0/aclk",
          "clk_div_0/clk_in",
          "timemux_0/clk",
          "demux16_sync_0/clk"
        ]
      },
      "Net": {
        "ports": [
          "clk_div_1/clk_out",
          "c_shift_ram_2/CLK",
          "c_shift_ram_3/CLK",
          "c_shift_ram_1/CLK",
          "fifo_generator_0/wr_clk",
          "util_ds_buf_0/BUFG_I",
          "c_shift_ram_0/CLK",
          "energy_compare_0/clk",
          "arithm_block_0/clk",
          "scan_0/clk"
        ]
      },
      "demux16_sync_0_output_data1": {
        "ports": [
          "demux16_sync_0/output_data1",
          "c_shift_ram_1/D"
        ]
      },
      "demux16_sync_0_output_data3": {
        "ports": [
          "demux16_sync_0/output_data3",
          "c_shift_ram_3/D"
        ]
      },
      "demux16_sync_0_output_data2": {
        "ports": [
          "demux16_sync_0/output_data2",
          "c_shift_ram_2/D"
        ]
      },
      "scan_0_address_0": {
        "ports": [
          "scan_0/address_0",
          "blk_mem_gen_0/addra"
        ]
      },
      "scan_0_address_1": {
        "ports": [
          "scan_0/address_1",
          "blk_mem_gen_1/addra"
        ]
      },
      "scan_0_address_2": {
        "ports": [
          "scan_0/address_2",
          "blk_mem_gen_2/addra"
        ]
      },
      "scan_0_address_3": {
        "ports": [
          "scan_0/address_3",
          "blk_mem_gen_3/addra"
        ]
      },
      "demux16_sync_0_finish": {
        "ports": [
          "demux16_sync_0/finish",
          "scan_0/t_finish"
        ]
      },
      "Net1": {
        "ports": [
          "scan_0/delay_enable",
          "c_shift_ram_0/CE",
          "c_shift_ram_1/CE",
          "c_shift_ram_2/CE",
          "c_shift_ram_3/CE"
        ]
      },
      "energy_compare_0_max_found": {
        "ports": [
          "energy_compare_0/max_found",
          "scan_0/max_found"
        ]
      },
      "energy_compare_0_val_out": {
        "ports": [
          "energy_compare_0/val_out",
          "fifo_generator_0/din"
        ]
      },
      "energy_compare_0_start_fifo": {
        "ports": [
          "energy_compare_0/start_fifo",
          "fifo_generator_0/wr_en"
        ]
      },
      "timemux_0_data_tlast": {
        "ports": [
          "timemux_0/data_tlast",
          "cic_compiler_0/s_axis_data_tlast"
        ]
      },
      "cic_compiler_0_m_axis_data_tlast": {
        "ports": [
          "cic_compiler_0/m_axis_data_tlast",
          "fir_compiler_0/s_axis_data_tlast"
        ]
      },
      "fir_compiler_0_m_axis_data_tlast": {
        "ports": [
          "fir_compiler_0/m_axis_data_tlast",
          "fir_compiler_1/s_axis_data_tlast"
        ]
      },
      "fir_compiler_1_m_axis_data_tvalid": {
        "ports": [
          "fir_compiler_1/m_axis_data_tvalid",
          "demux16_sync_0/t_valid"
        ]
      },
      "fir_compiler_1_m_axis_data_tlast": {
        "ports": [
          "fir_compiler_1/m_axis_data_tlast",
          "demux16_sync_0/t_last"
        ]
      },
      "fifo_rd_en_1": {
        "ports": [
          "fifo_rd_en",
          "fifo_generator_0/rd_en"
        ]
      },
      "arithm_block_0_val_out": {
        "ports": [
          "arithm_block_0/val_out",
          "energy_compare_0/val_in"
        ]
      },
      "c_shift_ram_0_Q": {
        "ports": [
          "c_shift_ram_0/Q",
          "arithm_block_0/smand0"
        ]
      },
      "c_shift_ram_1_Q": {
        "ports": [
          "c_shift_ram_1/Q",
          "arithm_block_0/smand1"
        ]
      },
      "c_shift_ram_2_Q": {
        "ports": [
          "c_shift_ram_2/Q",
          "arithm_block_0/smand2"
        ]
      },
      "c_shift_ram_3_Q": {
        "ports": [
          "c_shift_ram_3/Q",
          "arithm_block_0/smand3"
        ]
      },
      "arithm_block_0_en_enable": {
        "ports": [
          "arithm_block_0/en_enable",
          "energy_compare_0/start"
        ]
      },
      "scan_0_adder_enable": {
        "ports": [
          "scan_0/adder_enable",
          "arithm_block_0/adder_enable"
        ]
      }
    }
  }
}