-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
-- Date        : Tue May 12 21:39:52 2020
-- Host        : LAPTOP-RJQ3H7G3 running 64-bit major release  (build 9200)
-- Command     : write_vhdl -force -mode funcsim -rename_top pdm_to_pcm_c_shift_ram_1_2 -prefix
--               pdm_to_pcm_c_shift_ram_1_2_ pdm_to_pcm_c_shift_ram_0_0_sim_netlist.vhdl
-- Design      : pdm_to_pcm_c_shift_ram_0_0
-- Purpose     : This VHDL netlist is a functional simulation representation of the design and should not be modified or
--               synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device      : xc7a200tfbg676-2
-- --------------------------------------------------------------------------------
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity pdm_to_pcm_c_shift_ram_1_2_c_shift_ram_v12_0_13 is
  port (
    A : in STD_LOGIC_VECTOR ( 9 downto 0 );
    D : in STD_LOGIC_VECTOR ( 15 downto 0 );
    CLK : in STD_LOGIC;
    CE : in STD_LOGIC;
    SCLR : in STD_LOGIC;
    SSET : in STD_LOGIC;
    SINIT : in STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 15 downto 0 )
  );
  attribute C_ADDR_WIDTH : integer;
  attribute C_ADDR_WIDTH of pdm_to_pcm_c_shift_ram_1_2_c_shift_ram_v12_0_13 : entity is 10;
  attribute C_AINIT_VAL : string;
  attribute C_AINIT_VAL of pdm_to_pcm_c_shift_ram_1_2_c_shift_ram_v12_0_13 : entity is "0000000000000000";
  attribute C_DEFAULT_DATA : string;
  attribute C_DEFAULT_DATA of pdm_to_pcm_c_shift_ram_1_2_c_shift_ram_v12_0_13 : entity is "0000000000000000";
  attribute C_DEPTH : integer;
  attribute C_DEPTH of pdm_to_pcm_c_shift_ram_1_2_c_shift_ram_v12_0_13 : entity is 663;
  attribute C_ELABORATION_DIR : string;
  attribute C_ELABORATION_DIR of pdm_to_pcm_c_shift_ram_1_2_c_shift_ram_v12_0_13 : entity is "./";
  attribute C_HAS_A : integer;
  attribute C_HAS_A of pdm_to_pcm_c_shift_ram_1_2_c_shift_ram_v12_0_13 : entity is 1;
  attribute C_HAS_CE : integer;
  attribute C_HAS_CE of pdm_to_pcm_c_shift_ram_1_2_c_shift_ram_v12_0_13 : entity is 1;
  attribute C_HAS_SCLR : integer;
  attribute C_HAS_SCLR of pdm_to_pcm_c_shift_ram_1_2_c_shift_ram_v12_0_13 : entity is 0;
  attribute C_HAS_SINIT : integer;
  attribute C_HAS_SINIT of pdm_to_pcm_c_shift_ram_1_2_c_shift_ram_v12_0_13 : entity is 0;
  attribute C_HAS_SSET : integer;
  attribute C_HAS_SSET of pdm_to_pcm_c_shift_ram_1_2_c_shift_ram_v12_0_13 : entity is 0;
  attribute C_MEM_INIT_FILE : string;
  attribute C_MEM_INIT_FILE of pdm_to_pcm_c_shift_ram_1_2_c_shift_ram_v12_0_13 : entity is "no_coe_file_loaded";
  attribute C_OPT_GOAL : integer;
  attribute C_OPT_GOAL of pdm_to_pcm_c_shift_ram_1_2_c_shift_ram_v12_0_13 : entity is 0;
  attribute C_PARSER_TYPE : integer;
  attribute C_PARSER_TYPE of pdm_to_pcm_c_shift_ram_1_2_c_shift_ram_v12_0_13 : entity is 0;
  attribute C_READ_MIF : integer;
  attribute C_READ_MIF of pdm_to_pcm_c_shift_ram_1_2_c_shift_ram_v12_0_13 : entity is 0;
  attribute C_REG_LAST_BIT : integer;
  attribute C_REG_LAST_BIT of pdm_to_pcm_c_shift_ram_1_2_c_shift_ram_v12_0_13 : entity is 1;
  attribute C_SHIFT_TYPE : integer;
  attribute C_SHIFT_TYPE of pdm_to_pcm_c_shift_ram_1_2_c_shift_ram_v12_0_13 : entity is 1;
  attribute C_SINIT_VAL : string;
  attribute C_SINIT_VAL of pdm_to_pcm_c_shift_ram_1_2_c_shift_ram_v12_0_13 : entity is "0000000000000000";
  attribute C_SYNC_ENABLE : integer;
  attribute C_SYNC_ENABLE of pdm_to_pcm_c_shift_ram_1_2_c_shift_ram_v12_0_13 : entity is 0;
  attribute C_SYNC_PRIORITY : integer;
  attribute C_SYNC_PRIORITY of pdm_to_pcm_c_shift_ram_1_2_c_shift_ram_v12_0_13 : entity is 1;
  attribute C_VERBOSITY : integer;
  attribute C_VERBOSITY of pdm_to_pcm_c_shift_ram_1_2_c_shift_ram_v12_0_13 : entity is 0;
  attribute C_WIDTH : integer;
  attribute C_WIDTH of pdm_to_pcm_c_shift_ram_1_2_c_shift_ram_v12_0_13 : entity is 16;
  attribute C_XDEVICEFAMILY : string;
  attribute C_XDEVICEFAMILY of pdm_to_pcm_c_shift_ram_1_2_c_shift_ram_v12_0_13 : entity is "artix7";
  attribute downgradeipidentifiedwarnings : string;
  attribute downgradeipidentifiedwarnings of pdm_to_pcm_c_shift_ram_1_2_c_shift_ram_v12_0_13 : entity is "yes";
end pdm_to_pcm_c_shift_ram_1_2_c_shift_ram_v12_0_13;

architecture STRUCTURE of pdm_to_pcm_c_shift_ram_1_2_c_shift_ram_v12_0_13 is
  attribute C_AINIT_VAL of i_synth : label is "0000000000000000";
  attribute C_HAS_CE of i_synth : label is 1;
  attribute C_HAS_SCLR of i_synth : label is 0;
  attribute C_HAS_SINIT of i_synth : label is 0;
  attribute C_HAS_SSET of i_synth : label is 0;
  attribute C_SINIT_VAL of i_synth : label is "0000000000000000";
  attribute C_SYNC_ENABLE of i_synth : label is 0;
  attribute C_SYNC_PRIORITY of i_synth : label is 1;
  attribute C_WIDTH of i_synth : label is 16;
  attribute c_addr_width of i_synth : label is 10;
  attribute c_default_data of i_synth : label is "0000000000000000";
  attribute c_depth of i_synth : label is 663;
  attribute c_elaboration_dir of i_synth : label is "./";
  attribute c_has_a of i_synth : label is 1;
  attribute c_mem_init_file of i_synth : label is "no_coe_file_loaded";
  attribute c_opt_goal of i_synth : label is 0;
  attribute c_parser_type of i_synth : label is 0;
  attribute c_read_mif of i_synth : label is 0;
  attribute c_reg_last_bit of i_synth : label is 1;
  attribute c_shift_type of i_synth : label is 1;
  attribute c_verbosity of i_synth : label is 0;
  attribute c_xdevicefamily of i_synth : label is "artix7";
  attribute downgradeipidentifiedwarnings of i_synth : label is "yes";
begin
i_synth: entity work.pdm_to_pcm_c_shift_ram_1_2_c_shift_ram_v12_0_13_viv
     port map (
      A(9 downto 0) => A(9 downto 0),
      CE => CE,
      CLK => CLK,
      D(15 downto 0) => D(15 downto 0),
      Q(15 downto 0) => Q(15 downto 0),
      SCLR => '0',
      SINIT => '0',
      SSET => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity pdm_to_pcm_c_shift_ram_1_2 is
  port (
    A : in STD_LOGIC_VECTOR ( 9 downto 0 );
    D : in STD_LOGIC_VECTOR ( 15 downto 0 );
    CLK : in STD_LOGIC;
    CE : in STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 15 downto 0 )
  );
  attribute NotValidForBitStream : boolean;
  attribute NotValidForBitStream of pdm_to_pcm_c_shift_ram_1_2 : entity is true;
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of pdm_to_pcm_c_shift_ram_1_2 : entity is "pdm_to_pcm_c_shift_ram_0_0,c_shift_ram_v12_0_13,{}";
  attribute downgradeipidentifiedwarnings : string;
  attribute downgradeipidentifiedwarnings of pdm_to_pcm_c_shift_ram_1_2 : entity is "yes";
  attribute x_core_info : string;
  attribute x_core_info of pdm_to_pcm_c_shift_ram_1_2 : entity is "c_shift_ram_v12_0_13,Vivado 2019.1";
end pdm_to_pcm_c_shift_ram_1_2;

architecture STRUCTURE of pdm_to_pcm_c_shift_ram_1_2 is
  attribute C_AINIT_VAL : string;
  attribute C_AINIT_VAL of U0 : label is "0000000000000000";
  attribute C_HAS_CE : integer;
  attribute C_HAS_CE of U0 : label is 1;
  attribute C_HAS_SCLR : integer;
  attribute C_HAS_SCLR of U0 : label is 0;
  attribute C_HAS_SINIT : integer;
  attribute C_HAS_SINIT of U0 : label is 0;
  attribute C_HAS_SSET : integer;
  attribute C_HAS_SSET of U0 : label is 0;
  attribute C_SINIT_VAL : string;
  attribute C_SINIT_VAL of U0 : label is "0000000000000000";
  attribute C_SYNC_ENABLE : integer;
  attribute C_SYNC_ENABLE of U0 : label is 0;
  attribute C_SYNC_PRIORITY : integer;
  attribute C_SYNC_PRIORITY of U0 : label is 1;
  attribute C_WIDTH : integer;
  attribute C_WIDTH of U0 : label is 16;
  attribute c_addr_width : integer;
  attribute c_addr_width of U0 : label is 10;
  attribute c_default_data : string;
  attribute c_default_data of U0 : label is "0000000000000000";
  attribute c_depth : integer;
  attribute c_depth of U0 : label is 663;
  attribute c_elaboration_dir : string;
  attribute c_elaboration_dir of U0 : label is "./";
  attribute c_has_a : integer;
  attribute c_has_a of U0 : label is 1;
  attribute c_mem_init_file : string;
  attribute c_mem_init_file of U0 : label is "no_coe_file_loaded";
  attribute c_opt_goal : integer;
  attribute c_opt_goal of U0 : label is 0;
  attribute c_parser_type : integer;
  attribute c_parser_type of U0 : label is 0;
  attribute c_read_mif : integer;
  attribute c_read_mif of U0 : label is 0;
  attribute c_reg_last_bit : integer;
  attribute c_reg_last_bit of U0 : label is 1;
  attribute c_shift_type : integer;
  attribute c_shift_type of U0 : label is 1;
  attribute c_verbosity : integer;
  attribute c_verbosity of U0 : label is 0;
  attribute c_xdevicefamily : string;
  attribute c_xdevicefamily of U0 : label is "artix7";
  attribute downgradeipidentifiedwarnings of U0 : label is "yes";
  attribute x_interface_info : string;
  attribute x_interface_info of CE : signal is "xilinx.com:signal:clockenable:1.0 ce_intf CE";
  attribute x_interface_parameter : string;
  attribute x_interface_parameter of CE : signal is "XIL_INTERFACENAME ce_intf, POLARITY ACTIVE_LOW";
  attribute x_interface_info of CLK : signal is "xilinx.com:signal:clock:1.0 clk_intf CLK";
  attribute x_interface_parameter of CLK : signal is "XIL_INTERFACENAME clk_intf, ASSOCIATED_BUSIF q_intf:sinit_intf:sset_intf:d_intf:a_intf, ASSOCIATED_RESET SCLR, ASSOCIATED_CLKEN CE, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0";
  attribute x_interface_info of A : signal is "xilinx.com:signal:data:1.0 a_intf DATA";
  attribute x_interface_parameter of A : signal is "XIL_INTERFACENAME a_intf, LAYERED_METADATA undef";
  attribute x_interface_info of D : signal is "xilinx.com:signal:data:1.0 d_intf DATA";
  attribute x_interface_parameter of D : signal is "XIL_INTERFACENAME d_intf, LAYERED_METADATA undef";
  attribute x_interface_info of Q : signal is "xilinx.com:signal:data:1.0 q_intf DATA";
  attribute x_interface_parameter of Q : signal is "XIL_INTERFACENAME q_intf, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {DATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value data} bitwidth {attribs {resolve_type generated dependency data_bitwidth format long minimum {} maximum {}} value 16} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0}}} DATA_WIDTH 16}";
begin
U0: entity work.pdm_to_pcm_c_shift_ram_1_2_c_shift_ram_v12_0_13
     port map (
      A(9 downto 0) => A(9 downto 0),
      CE => CE,
      CLK => CLK,
      D(15 downto 0) => D(15 downto 0),
      Q(15 downto 0) => Q(15 downto 0),
      SCLR => '0',
      SINIT => '0',
      SSET => '0'
    );
end STRUCTURE;
