@echo off
REM ****************************************************************************
REM Vivado (TM) v2019.1 (64-bit)
REM
REM Filename    : elaborate.bat
REM Simulator   : Xilinx Vivado Simulator
REM Description : Script for elaborating the compiled design
REM
REM Generated by Vivado on Mon May 25 03:27:50 +0200 2020
REM SW Build 2552052 on Fri May 24 14:49:42 MDT 2019
REM
REM Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
REM
REM usage: elaborate.bat
REM
REM ****************************************************************************
echo "xelab -wto e28594f732a0486499082ea7bbfdcf60 --incr --debug typical --relax --mt 2 -L work -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L cic_compiler_v4_0_14 -L fir_compiler_v7_2_12 -L fifo_generator_v13_2_4 -L util_vector_logic_v2_0_1 -L c_reg_fd_v12_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_pipe_v3_0_6 -L xbip_dsp48_addsub_v3_0_6 -L xbip_addsub_v3_0_6 -L c_addsub_v12_0_13 -L blk_mem_gen_v8_4_3 -L c_mux_bit_v12_0_6 -L c_shift_ram_v12_0_13 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot test_pdm_to_pcm_behav xil_defaultlib.test_pdm_to_pcm xil_defaultlib.glbl -log elaborate.log"
call xelab  -wto e28594f732a0486499082ea7bbfdcf60 --incr --debug typical --relax --mt 2 -L work -L xil_defaultlib -L xbip_utils_v3_0_10 -L axi_utils_v2_0_6 -L cic_compiler_v4_0_14 -L fir_compiler_v7_2_12 -L fifo_generator_v13_2_4 -L util_vector_logic_v2_0_1 -L c_reg_fd_v12_0_6 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_pipe_v3_0_6 -L xbip_dsp48_addsub_v3_0_6 -L xbip_addsub_v3_0_6 -L c_addsub_v12_0_13 -L blk_mem_gen_v8_4_3 -L c_mux_bit_v12_0_6 -L c_shift_ram_v12_0_13 -L xbip_bram18k_v3_0_6 -L mult_gen_v12_0_15 -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot test_pdm_to_pcm_behav xil_defaultlib.test_pdm_to_pcm xil_defaultlib.glbl -log elaborate.log
if "%errorlevel%"=="0" goto SUCCESS
if "%errorlevel%"=="1" goto END
:END
exit 1
:SUCCESS
exit 0
