-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
-- Date        : Tue May 26 01:40:24 2020
-- Host        : LAPTOP-RJQ3H7G3 running 64-bit major release  (build 9200)
-- Command     : write_vhdl -force -mode funcsim
--               D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_demux16_sync_0_0/pdm_to_pcm_demux16_sync_0_0_sim_netlist.vhdl
-- Design      : pdm_to_pcm_demux16_sync_0_0
-- Purpose     : This VHDL netlist is a functional simulation representation of the design and should not be modified or
--               synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device      : xc7a200tfbg676-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity pdm_to_pcm_demux16_sync_0_0_demux16_sync is
  port (
    output_data0 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    output_data1 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    output_data2 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    output_data3 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    t_last : in STD_LOGIC;
    t_valid : in STD_LOGIC;
    clk : in STD_LOGIC;
    input_data : in STD_LOGIC_VECTOR ( 15 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of pdm_to_pcm_demux16_sync_0_0_demux16_sync : entity is "demux16_sync";
end pdm_to_pcm_demux16_sync_0_0_demux16_sync;

architecture STRUCTURE of pdm_to_pcm_demux16_sync_0_0_demux16_sync is
  signal \FSM_onehot_a[0]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_a[1]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_a[2]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_a_reg_n_0_[1]\ : STD_LOGIC;
  signal \FSM_onehot_a_reg_n_0_[2]\ : STD_LOGIC;
  signal demux16_data0 : STD_LOGIC;
  signal \demux16_data0[15]_i_1_n_0\ : STD_LOGIC;
  signal \demux16_data0_reg_n_0_[0]\ : STD_LOGIC;
  signal \demux16_data0_reg_n_0_[10]\ : STD_LOGIC;
  signal \demux16_data0_reg_n_0_[11]\ : STD_LOGIC;
  signal \demux16_data0_reg_n_0_[12]\ : STD_LOGIC;
  signal \demux16_data0_reg_n_0_[13]\ : STD_LOGIC;
  signal \demux16_data0_reg_n_0_[14]\ : STD_LOGIC;
  signal \demux16_data0_reg_n_0_[15]\ : STD_LOGIC;
  signal \demux16_data0_reg_n_0_[1]\ : STD_LOGIC;
  signal \demux16_data0_reg_n_0_[2]\ : STD_LOGIC;
  signal \demux16_data0_reg_n_0_[3]\ : STD_LOGIC;
  signal \demux16_data0_reg_n_0_[4]\ : STD_LOGIC;
  signal \demux16_data0_reg_n_0_[5]\ : STD_LOGIC;
  signal \demux16_data0_reg_n_0_[6]\ : STD_LOGIC;
  signal \demux16_data0_reg_n_0_[7]\ : STD_LOGIC;
  signal \demux16_data0_reg_n_0_[8]\ : STD_LOGIC;
  signal \demux16_data0_reg_n_0_[9]\ : STD_LOGIC;
  signal demux16_data1 : STD_LOGIC;
  signal \demux16_data1_reg_n_0_[0]\ : STD_LOGIC;
  signal \demux16_data1_reg_n_0_[10]\ : STD_LOGIC;
  signal \demux16_data1_reg_n_0_[11]\ : STD_LOGIC;
  signal \demux16_data1_reg_n_0_[12]\ : STD_LOGIC;
  signal \demux16_data1_reg_n_0_[13]\ : STD_LOGIC;
  signal \demux16_data1_reg_n_0_[14]\ : STD_LOGIC;
  signal \demux16_data1_reg_n_0_[15]\ : STD_LOGIC;
  signal \demux16_data1_reg_n_0_[1]\ : STD_LOGIC;
  signal \demux16_data1_reg_n_0_[2]\ : STD_LOGIC;
  signal \demux16_data1_reg_n_0_[3]\ : STD_LOGIC;
  signal \demux16_data1_reg_n_0_[4]\ : STD_LOGIC;
  signal \demux16_data1_reg_n_0_[5]\ : STD_LOGIC;
  signal \demux16_data1_reg_n_0_[6]\ : STD_LOGIC;
  signal \demux16_data1_reg_n_0_[7]\ : STD_LOGIC;
  signal \demux16_data1_reg_n_0_[8]\ : STD_LOGIC;
  signal \demux16_data1_reg_n_0_[9]\ : STD_LOGIC;
  signal demux16_data2 : STD_LOGIC;
  signal \demux16_data2_reg_n_0_[0]\ : STD_LOGIC;
  signal \demux16_data2_reg_n_0_[10]\ : STD_LOGIC;
  signal \demux16_data2_reg_n_0_[11]\ : STD_LOGIC;
  signal \demux16_data2_reg_n_0_[12]\ : STD_LOGIC;
  signal \demux16_data2_reg_n_0_[13]\ : STD_LOGIC;
  signal \demux16_data2_reg_n_0_[14]\ : STD_LOGIC;
  signal \demux16_data2_reg_n_0_[15]\ : STD_LOGIC;
  signal \demux16_data2_reg_n_0_[1]\ : STD_LOGIC;
  signal \demux16_data2_reg_n_0_[2]\ : STD_LOGIC;
  signal \demux16_data2_reg_n_0_[3]\ : STD_LOGIC;
  signal \demux16_data2_reg_n_0_[4]\ : STD_LOGIC;
  signal \demux16_data2_reg_n_0_[5]\ : STD_LOGIC;
  signal \demux16_data2_reg_n_0_[6]\ : STD_LOGIC;
  signal \demux16_data2_reg_n_0_[7]\ : STD_LOGIC;
  signal \demux16_data2_reg_n_0_[8]\ : STD_LOGIC;
  signal \demux16_data2_reg_n_0_[9]\ : STD_LOGIC;
  signal demux16_data3 : STD_LOGIC;
  signal \demux16_data3_reg_n_0_[0]\ : STD_LOGIC;
  signal \demux16_data3_reg_n_0_[10]\ : STD_LOGIC;
  signal \demux16_data3_reg_n_0_[11]\ : STD_LOGIC;
  signal \demux16_data3_reg_n_0_[12]\ : STD_LOGIC;
  signal \demux16_data3_reg_n_0_[13]\ : STD_LOGIC;
  signal \demux16_data3_reg_n_0_[14]\ : STD_LOGIC;
  signal \demux16_data3_reg_n_0_[15]\ : STD_LOGIC;
  signal \demux16_data3_reg_n_0_[1]\ : STD_LOGIC;
  signal \demux16_data3_reg_n_0_[2]\ : STD_LOGIC;
  signal \demux16_data3_reg_n_0_[3]\ : STD_LOGIC;
  signal \demux16_data3_reg_n_0_[4]\ : STD_LOGIC;
  signal \demux16_data3_reg_n_0_[5]\ : STD_LOGIC;
  signal \demux16_data3_reg_n_0_[6]\ : STD_LOGIC;
  signal \demux16_data3_reg_n_0_[7]\ : STD_LOGIC;
  signal \demux16_data3_reg_n_0_[8]\ : STD_LOGIC;
  signal \demux16_data3_reg_n_0_[9]\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_onehot_a[0]_i_1\ : label is "soft_lutpair0";
  attribute SOFT_HLUTNM of \FSM_onehot_a[2]_i_1\ : label is "soft_lutpair0";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_onehot_a_reg[0]\ : label is "iSTATE:1000,iSTATE0:0001,iSTATE1:0010,iSTATE2:0100,";
  attribute FSM_ENCODED_STATES of \FSM_onehot_a_reg[1]\ : label is "iSTATE:1000,iSTATE0:0001,iSTATE1:0010,iSTATE2:0100,";
  attribute FSM_ENCODED_STATES of \FSM_onehot_a_reg[2]\ : label is "iSTATE:1000,iSTATE0:0001,iSTATE1:0010,iSTATE2:0100,";
  attribute XILINX_LEGACY_PRIM : string;
  attribute XILINX_LEGACY_PRIM of \output_data0_reg[0]\ : label is "LD";
  attribute XILINX_LEGACY_PRIM of \output_data0_reg[10]\ : label is "LD";
  attribute XILINX_LEGACY_PRIM of \output_data0_reg[11]\ : label is "LD";
  attribute XILINX_LEGACY_PRIM of \output_data0_reg[12]\ : label is "LD";
  attribute XILINX_LEGACY_PRIM of \output_data0_reg[13]\ : label is "LD";
  attribute XILINX_LEGACY_PRIM of \output_data0_reg[14]\ : label is "LD";
  attribute XILINX_LEGACY_PRIM of \output_data0_reg[15]\ : label is "LD";
  attribute XILINX_LEGACY_PRIM of \output_data0_reg[1]\ : label is "LD";
  attribute XILINX_LEGACY_PRIM of \output_data0_reg[2]\ : label is "LD";
  attribute XILINX_LEGACY_PRIM of \output_data0_reg[3]\ : label is "LD";
  attribute XILINX_LEGACY_PRIM of \output_data0_reg[4]\ : label is "LD";
  attribute XILINX_LEGACY_PRIM of \output_data0_reg[5]\ : label is "LD";
  attribute XILINX_LEGACY_PRIM of \output_data0_reg[6]\ : label is "LD";
  attribute XILINX_LEGACY_PRIM of \output_data0_reg[7]\ : label is "LD";
  attribute XILINX_LEGACY_PRIM of \output_data0_reg[8]\ : label is "LD";
  attribute XILINX_LEGACY_PRIM of \output_data0_reg[9]\ : label is "LD";
  attribute XILINX_LEGACY_PRIM of \output_data1_reg[0]\ : label is "LD";
  attribute XILINX_LEGACY_PRIM of \output_data1_reg[10]\ : label is "LD";
  attribute XILINX_LEGACY_PRIM of \output_data1_reg[11]\ : label is "LD";
  attribute XILINX_LEGACY_PRIM of \output_data1_reg[12]\ : label is "LD";
  attribute XILINX_LEGACY_PRIM of \output_data1_reg[13]\ : label is "LD";
  attribute XILINX_LEGACY_PRIM of \output_data1_reg[14]\ : label is "LD";
  attribute XILINX_LEGACY_PRIM of \output_data1_reg[15]\ : label is "LD";
  attribute XILINX_LEGACY_PRIM of \output_data1_reg[1]\ : label is "LD";
  attribute XILINX_LEGACY_PRIM of \output_data1_reg[2]\ : label is "LD";
  attribute XILINX_LEGACY_PRIM of \output_data1_reg[3]\ : label is "LD";
  attribute XILINX_LEGACY_PRIM of \output_data1_reg[4]\ : label is "LD";
  attribute XILINX_LEGACY_PRIM of \output_data1_reg[5]\ : label is "LD";
  attribute XILINX_LEGACY_PRIM of \output_data1_reg[6]\ : label is "LD";
  attribute XILINX_LEGACY_PRIM of \output_data1_reg[7]\ : label is "LD";
  attribute XILINX_LEGACY_PRIM of \output_data1_reg[8]\ : label is "LD";
  attribute XILINX_LEGACY_PRIM of \output_data1_reg[9]\ : label is "LD";
  attribute XILINX_LEGACY_PRIM of \output_data2_reg[0]\ : label is "LD";
  attribute XILINX_LEGACY_PRIM of \output_data2_reg[10]\ : label is "LD";
  attribute XILINX_LEGACY_PRIM of \output_data2_reg[11]\ : label is "LD";
  attribute XILINX_LEGACY_PRIM of \output_data2_reg[12]\ : label is "LD";
  attribute XILINX_LEGACY_PRIM of \output_data2_reg[13]\ : label is "LD";
  attribute XILINX_LEGACY_PRIM of \output_data2_reg[14]\ : label is "LD";
  attribute XILINX_LEGACY_PRIM of \output_data2_reg[15]\ : label is "LD";
  attribute XILINX_LEGACY_PRIM of \output_data2_reg[1]\ : label is "LD";
  attribute XILINX_LEGACY_PRIM of \output_data2_reg[2]\ : label is "LD";
  attribute XILINX_LEGACY_PRIM of \output_data2_reg[3]\ : label is "LD";
  attribute XILINX_LEGACY_PRIM of \output_data2_reg[4]\ : label is "LD";
  attribute XILINX_LEGACY_PRIM of \output_data2_reg[5]\ : label is "LD";
  attribute XILINX_LEGACY_PRIM of \output_data2_reg[6]\ : label is "LD";
  attribute XILINX_LEGACY_PRIM of \output_data2_reg[7]\ : label is "LD";
  attribute XILINX_LEGACY_PRIM of \output_data2_reg[8]\ : label is "LD";
  attribute XILINX_LEGACY_PRIM of \output_data2_reg[9]\ : label is "LD";
  attribute XILINX_LEGACY_PRIM of \output_data3_reg[0]\ : label is "LD";
  attribute XILINX_LEGACY_PRIM of \output_data3_reg[10]\ : label is "LD";
  attribute XILINX_LEGACY_PRIM of \output_data3_reg[11]\ : label is "LD";
  attribute XILINX_LEGACY_PRIM of \output_data3_reg[12]\ : label is "LD";
  attribute XILINX_LEGACY_PRIM of \output_data3_reg[13]\ : label is "LD";
  attribute XILINX_LEGACY_PRIM of \output_data3_reg[14]\ : label is "LD";
  attribute XILINX_LEGACY_PRIM of \output_data3_reg[15]\ : label is "LD";
  attribute XILINX_LEGACY_PRIM of \output_data3_reg[1]\ : label is "LD";
  attribute XILINX_LEGACY_PRIM of \output_data3_reg[2]\ : label is "LD";
  attribute XILINX_LEGACY_PRIM of \output_data3_reg[3]\ : label is "LD";
  attribute XILINX_LEGACY_PRIM of \output_data3_reg[4]\ : label is "LD";
  attribute XILINX_LEGACY_PRIM of \output_data3_reg[5]\ : label is "LD";
  attribute XILINX_LEGACY_PRIM of \output_data3_reg[6]\ : label is "LD";
  attribute XILINX_LEGACY_PRIM of \output_data3_reg[7]\ : label is "LD";
  attribute XILINX_LEGACY_PRIM of \output_data3_reg[8]\ : label is "LD";
  attribute XILINX_LEGACY_PRIM of \output_data3_reg[9]\ : label is "LD";
begin
\FSM_onehot_a[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0F10"
    )
        port map (
      I0 => \FSM_onehot_a_reg_n_0_[1]\,
      I1 => \FSM_onehot_a_reg_n_0_[2]\,
      I2 => t_valid,
      I3 => demux16_data0,
      O => \FSM_onehot_a[0]_i_1_n_0\
    );
\FSM_onehot_a[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => demux16_data0,
      I1 => t_valid,
      I2 => \FSM_onehot_a_reg_n_0_[1]\,
      O => \FSM_onehot_a[1]_i_1_n_0\
    );
\FSM_onehot_a[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \FSM_onehot_a_reg_n_0_[1]\,
      I1 => t_valid,
      I2 => \FSM_onehot_a_reg_n_0_[2]\,
      O => \FSM_onehot_a[2]_i_1_n_0\
    );
\FSM_onehot_a_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => clk,
      CE => '1',
      D => \FSM_onehot_a[0]_i_1_n_0\,
      Q => demux16_data0,
      R => '0'
    );
\FSM_onehot_a_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \FSM_onehot_a[1]_i_1_n_0\,
      Q => \FSM_onehot_a_reg_n_0_[1]\,
      R => '0'
    );
\FSM_onehot_a_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \FSM_onehot_a[2]_i_1_n_0\,
      Q => \FSM_onehot_a_reg_n_0_[2]\,
      R => '0'
    );
\demux16_data0[15]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => t_valid,
      I1 => demux16_data0,
      O => \demux16_data0[15]_i_1_n_0\
    );
\demux16_data0_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \demux16_data0[15]_i_1_n_0\,
      D => input_data(0),
      Q => \demux16_data0_reg_n_0_[0]\,
      R => '0'
    );
\demux16_data0_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \demux16_data0[15]_i_1_n_0\,
      D => input_data(10),
      Q => \demux16_data0_reg_n_0_[10]\,
      R => '0'
    );
\demux16_data0_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \demux16_data0[15]_i_1_n_0\,
      D => input_data(11),
      Q => \demux16_data0_reg_n_0_[11]\,
      R => '0'
    );
\demux16_data0_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \demux16_data0[15]_i_1_n_0\,
      D => input_data(12),
      Q => \demux16_data0_reg_n_0_[12]\,
      R => '0'
    );
\demux16_data0_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \demux16_data0[15]_i_1_n_0\,
      D => input_data(13),
      Q => \demux16_data0_reg_n_0_[13]\,
      R => '0'
    );
\demux16_data0_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \demux16_data0[15]_i_1_n_0\,
      D => input_data(14),
      Q => \demux16_data0_reg_n_0_[14]\,
      R => '0'
    );
\demux16_data0_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \demux16_data0[15]_i_1_n_0\,
      D => input_data(15),
      Q => \demux16_data0_reg_n_0_[15]\,
      R => '0'
    );
\demux16_data0_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \demux16_data0[15]_i_1_n_0\,
      D => input_data(1),
      Q => \demux16_data0_reg_n_0_[1]\,
      R => '0'
    );
\demux16_data0_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \demux16_data0[15]_i_1_n_0\,
      D => input_data(2),
      Q => \demux16_data0_reg_n_0_[2]\,
      R => '0'
    );
\demux16_data0_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \demux16_data0[15]_i_1_n_0\,
      D => input_data(3),
      Q => \demux16_data0_reg_n_0_[3]\,
      R => '0'
    );
\demux16_data0_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \demux16_data0[15]_i_1_n_0\,
      D => input_data(4),
      Q => \demux16_data0_reg_n_0_[4]\,
      R => '0'
    );
\demux16_data0_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \demux16_data0[15]_i_1_n_0\,
      D => input_data(5),
      Q => \demux16_data0_reg_n_0_[5]\,
      R => '0'
    );
\demux16_data0_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \demux16_data0[15]_i_1_n_0\,
      D => input_data(6),
      Q => \demux16_data0_reg_n_0_[6]\,
      R => '0'
    );
\demux16_data0_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \demux16_data0[15]_i_1_n_0\,
      D => input_data(7),
      Q => \demux16_data0_reg_n_0_[7]\,
      R => '0'
    );
\demux16_data0_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \demux16_data0[15]_i_1_n_0\,
      D => input_data(8),
      Q => \demux16_data0_reg_n_0_[8]\,
      R => '0'
    );
\demux16_data0_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \demux16_data0[15]_i_1_n_0\,
      D => input_data(9),
      Q => \demux16_data0_reg_n_0_[9]\,
      R => '0'
    );
\demux16_data1[15]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => t_valid,
      I1 => \FSM_onehot_a_reg_n_0_[1]\,
      O => demux16_data1
    );
\demux16_data1_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => demux16_data1,
      D => input_data(0),
      Q => \demux16_data1_reg_n_0_[0]\,
      R => '0'
    );
\demux16_data1_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => demux16_data1,
      D => input_data(10),
      Q => \demux16_data1_reg_n_0_[10]\,
      R => '0'
    );
\demux16_data1_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => demux16_data1,
      D => input_data(11),
      Q => \demux16_data1_reg_n_0_[11]\,
      R => '0'
    );
\demux16_data1_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => demux16_data1,
      D => input_data(12),
      Q => \demux16_data1_reg_n_0_[12]\,
      R => '0'
    );
\demux16_data1_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => demux16_data1,
      D => input_data(13),
      Q => \demux16_data1_reg_n_0_[13]\,
      R => '0'
    );
\demux16_data1_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => demux16_data1,
      D => input_data(14),
      Q => \demux16_data1_reg_n_0_[14]\,
      R => '0'
    );
\demux16_data1_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => demux16_data1,
      D => input_data(15),
      Q => \demux16_data1_reg_n_0_[15]\,
      R => '0'
    );
\demux16_data1_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => demux16_data1,
      D => input_data(1),
      Q => \demux16_data1_reg_n_0_[1]\,
      R => '0'
    );
\demux16_data1_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => demux16_data1,
      D => input_data(2),
      Q => \demux16_data1_reg_n_0_[2]\,
      R => '0'
    );
\demux16_data1_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => demux16_data1,
      D => input_data(3),
      Q => \demux16_data1_reg_n_0_[3]\,
      R => '0'
    );
\demux16_data1_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => demux16_data1,
      D => input_data(4),
      Q => \demux16_data1_reg_n_0_[4]\,
      R => '0'
    );
\demux16_data1_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => demux16_data1,
      D => input_data(5),
      Q => \demux16_data1_reg_n_0_[5]\,
      R => '0'
    );
\demux16_data1_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => demux16_data1,
      D => input_data(6),
      Q => \demux16_data1_reg_n_0_[6]\,
      R => '0'
    );
\demux16_data1_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => demux16_data1,
      D => input_data(7),
      Q => \demux16_data1_reg_n_0_[7]\,
      R => '0'
    );
\demux16_data1_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => demux16_data1,
      D => input_data(8),
      Q => \demux16_data1_reg_n_0_[8]\,
      R => '0'
    );
\demux16_data1_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => demux16_data1,
      D => input_data(9),
      Q => \demux16_data1_reg_n_0_[9]\,
      R => '0'
    );
\demux16_data2[15]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => t_valid,
      I1 => \FSM_onehot_a_reg_n_0_[2]\,
      O => demux16_data2
    );
\demux16_data2_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => demux16_data2,
      D => input_data(0),
      Q => \demux16_data2_reg_n_0_[0]\,
      R => '0'
    );
\demux16_data2_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => demux16_data2,
      D => input_data(10),
      Q => \demux16_data2_reg_n_0_[10]\,
      R => '0'
    );
\demux16_data2_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => demux16_data2,
      D => input_data(11),
      Q => \demux16_data2_reg_n_0_[11]\,
      R => '0'
    );
\demux16_data2_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => demux16_data2,
      D => input_data(12),
      Q => \demux16_data2_reg_n_0_[12]\,
      R => '0'
    );
\demux16_data2_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => demux16_data2,
      D => input_data(13),
      Q => \demux16_data2_reg_n_0_[13]\,
      R => '0'
    );
\demux16_data2_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => demux16_data2,
      D => input_data(14),
      Q => \demux16_data2_reg_n_0_[14]\,
      R => '0'
    );
\demux16_data2_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => demux16_data2,
      D => input_data(15),
      Q => \demux16_data2_reg_n_0_[15]\,
      R => '0'
    );
\demux16_data2_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => demux16_data2,
      D => input_data(1),
      Q => \demux16_data2_reg_n_0_[1]\,
      R => '0'
    );
\demux16_data2_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => demux16_data2,
      D => input_data(2),
      Q => \demux16_data2_reg_n_0_[2]\,
      R => '0'
    );
\demux16_data2_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => demux16_data2,
      D => input_data(3),
      Q => \demux16_data2_reg_n_0_[3]\,
      R => '0'
    );
\demux16_data2_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => demux16_data2,
      D => input_data(4),
      Q => \demux16_data2_reg_n_0_[4]\,
      R => '0'
    );
\demux16_data2_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => demux16_data2,
      D => input_data(5),
      Q => \demux16_data2_reg_n_0_[5]\,
      R => '0'
    );
\demux16_data2_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => demux16_data2,
      D => input_data(6),
      Q => \demux16_data2_reg_n_0_[6]\,
      R => '0'
    );
\demux16_data2_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => demux16_data2,
      D => input_data(7),
      Q => \demux16_data2_reg_n_0_[7]\,
      R => '0'
    );
\demux16_data2_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => demux16_data2,
      D => input_data(8),
      Q => \demux16_data2_reg_n_0_[8]\,
      R => '0'
    );
\demux16_data2_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => demux16_data2,
      D => input_data(9),
      Q => \demux16_data2_reg_n_0_[9]\,
      R => '0'
    );
\demux16_data3[15]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0002"
    )
        port map (
      I0 => t_valid,
      I1 => \FSM_onehot_a_reg_n_0_[2]\,
      I2 => demux16_data0,
      I3 => \FSM_onehot_a_reg_n_0_[1]\,
      O => demux16_data3
    );
\demux16_data3_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => demux16_data3,
      D => input_data(0),
      Q => \demux16_data3_reg_n_0_[0]\,
      R => '0'
    );
\demux16_data3_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => demux16_data3,
      D => input_data(10),
      Q => \demux16_data3_reg_n_0_[10]\,
      R => '0'
    );
\demux16_data3_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => demux16_data3,
      D => input_data(11),
      Q => \demux16_data3_reg_n_0_[11]\,
      R => '0'
    );
\demux16_data3_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => demux16_data3,
      D => input_data(12),
      Q => \demux16_data3_reg_n_0_[12]\,
      R => '0'
    );
\demux16_data3_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => demux16_data3,
      D => input_data(13),
      Q => \demux16_data3_reg_n_0_[13]\,
      R => '0'
    );
\demux16_data3_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => demux16_data3,
      D => input_data(14),
      Q => \demux16_data3_reg_n_0_[14]\,
      R => '0'
    );
\demux16_data3_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => demux16_data3,
      D => input_data(15),
      Q => \demux16_data3_reg_n_0_[15]\,
      R => '0'
    );
\demux16_data3_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => demux16_data3,
      D => input_data(1),
      Q => \demux16_data3_reg_n_0_[1]\,
      R => '0'
    );
\demux16_data3_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => demux16_data3,
      D => input_data(2),
      Q => \demux16_data3_reg_n_0_[2]\,
      R => '0'
    );
\demux16_data3_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => demux16_data3,
      D => input_data(3),
      Q => \demux16_data3_reg_n_0_[3]\,
      R => '0'
    );
\demux16_data3_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => demux16_data3,
      D => input_data(4),
      Q => \demux16_data3_reg_n_0_[4]\,
      R => '0'
    );
\demux16_data3_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => demux16_data3,
      D => input_data(5),
      Q => \demux16_data3_reg_n_0_[5]\,
      R => '0'
    );
\demux16_data3_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => demux16_data3,
      D => input_data(6),
      Q => \demux16_data3_reg_n_0_[6]\,
      R => '0'
    );
\demux16_data3_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => demux16_data3,
      D => input_data(7),
      Q => \demux16_data3_reg_n_0_[7]\,
      R => '0'
    );
\demux16_data3_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => demux16_data3,
      D => input_data(8),
      Q => \demux16_data3_reg_n_0_[8]\,
      R => '0'
    );
\demux16_data3_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => demux16_data3,
      D => input_data(9),
      Q => \demux16_data3_reg_n_0_[9]\,
      R => '0'
    );
\output_data0_reg[0]\: unisim.vcomponents.LDCE
    generic map(
      INIT => '0'
    )
        port map (
      CLR => '0',
      D => \demux16_data0_reg_n_0_[0]\,
      G => t_last,
      GE => '1',
      Q => output_data0(0)
    );
\output_data0_reg[10]\: unisim.vcomponents.LDCE
    generic map(
      INIT => '0'
    )
        port map (
      CLR => '0',
      D => \demux16_data0_reg_n_0_[10]\,
      G => t_last,
      GE => '1',
      Q => output_data0(10)
    );
\output_data0_reg[11]\: unisim.vcomponents.LDCE
    generic map(
      INIT => '0'
    )
        port map (
      CLR => '0',
      D => \demux16_data0_reg_n_0_[11]\,
      G => t_last,
      GE => '1',
      Q => output_data0(11)
    );
\output_data0_reg[12]\: unisim.vcomponents.LDCE
    generic map(
      INIT => '0'
    )
        port map (
      CLR => '0',
      D => \demux16_data0_reg_n_0_[12]\,
      G => t_last,
      GE => '1',
      Q => output_data0(12)
    );
\output_data0_reg[13]\: unisim.vcomponents.LDCE
    generic map(
      INIT => '0'
    )
        port map (
      CLR => '0',
      D => \demux16_data0_reg_n_0_[13]\,
      G => t_last,
      GE => '1',
      Q => output_data0(13)
    );
\output_data0_reg[14]\: unisim.vcomponents.LDCE
    generic map(
      INIT => '0'
    )
        port map (
      CLR => '0',
      D => \demux16_data0_reg_n_0_[14]\,
      G => t_last,
      GE => '1',
      Q => output_data0(14)
    );
\output_data0_reg[15]\: unisim.vcomponents.LDCE
    generic map(
      INIT => '0'
    )
        port map (
      CLR => '0',
      D => \demux16_data0_reg_n_0_[15]\,
      G => t_last,
      GE => '1',
      Q => output_data0(15)
    );
\output_data0_reg[1]\: unisim.vcomponents.LDCE
    generic map(
      INIT => '0'
    )
        port map (
      CLR => '0',
      D => \demux16_data0_reg_n_0_[1]\,
      G => t_last,
      GE => '1',
      Q => output_data0(1)
    );
\output_data0_reg[2]\: unisim.vcomponents.LDCE
    generic map(
      INIT => '0'
    )
        port map (
      CLR => '0',
      D => \demux16_data0_reg_n_0_[2]\,
      G => t_last,
      GE => '1',
      Q => output_data0(2)
    );
\output_data0_reg[3]\: unisim.vcomponents.LDCE
    generic map(
      INIT => '0'
    )
        port map (
      CLR => '0',
      D => \demux16_data0_reg_n_0_[3]\,
      G => t_last,
      GE => '1',
      Q => output_data0(3)
    );
\output_data0_reg[4]\: unisim.vcomponents.LDCE
    generic map(
      INIT => '0'
    )
        port map (
      CLR => '0',
      D => \demux16_data0_reg_n_0_[4]\,
      G => t_last,
      GE => '1',
      Q => output_data0(4)
    );
\output_data0_reg[5]\: unisim.vcomponents.LDCE
    generic map(
      INIT => '0'
    )
        port map (
      CLR => '0',
      D => \demux16_data0_reg_n_0_[5]\,
      G => t_last,
      GE => '1',
      Q => output_data0(5)
    );
\output_data0_reg[6]\: unisim.vcomponents.LDCE
    generic map(
      INIT => '0'
    )
        port map (
      CLR => '0',
      D => \demux16_data0_reg_n_0_[6]\,
      G => t_last,
      GE => '1',
      Q => output_data0(6)
    );
\output_data0_reg[7]\: unisim.vcomponents.LDCE
    generic map(
      INIT => '0'
    )
        port map (
      CLR => '0',
      D => \demux16_data0_reg_n_0_[7]\,
      G => t_last,
      GE => '1',
      Q => output_data0(7)
    );
\output_data0_reg[8]\: unisim.vcomponents.LDCE
    generic map(
      INIT => '0'
    )
        port map (
      CLR => '0',
      D => \demux16_data0_reg_n_0_[8]\,
      G => t_last,
      GE => '1',
      Q => output_data0(8)
    );
\output_data0_reg[9]\: unisim.vcomponents.LDCE
    generic map(
      INIT => '0'
    )
        port map (
      CLR => '0',
      D => \demux16_data0_reg_n_0_[9]\,
      G => t_last,
      GE => '1',
      Q => output_data0(9)
    );
\output_data1_reg[0]\: unisim.vcomponents.LDCE
    generic map(
      INIT => '0'
    )
        port map (
      CLR => '0',
      D => \demux16_data1_reg_n_0_[0]\,
      G => t_last,
      GE => '1',
      Q => output_data1(0)
    );
\output_data1_reg[10]\: unisim.vcomponents.LDCE
    generic map(
      INIT => '0'
    )
        port map (
      CLR => '0',
      D => \demux16_data1_reg_n_0_[10]\,
      G => t_last,
      GE => '1',
      Q => output_data1(10)
    );
\output_data1_reg[11]\: unisim.vcomponents.LDCE
    generic map(
      INIT => '0'
    )
        port map (
      CLR => '0',
      D => \demux16_data1_reg_n_0_[11]\,
      G => t_last,
      GE => '1',
      Q => output_data1(11)
    );
\output_data1_reg[12]\: unisim.vcomponents.LDCE
    generic map(
      INIT => '0'
    )
        port map (
      CLR => '0',
      D => \demux16_data1_reg_n_0_[12]\,
      G => t_last,
      GE => '1',
      Q => output_data1(12)
    );
\output_data1_reg[13]\: unisim.vcomponents.LDCE
    generic map(
      INIT => '0'
    )
        port map (
      CLR => '0',
      D => \demux16_data1_reg_n_0_[13]\,
      G => t_last,
      GE => '1',
      Q => output_data1(13)
    );
\output_data1_reg[14]\: unisim.vcomponents.LDCE
    generic map(
      INIT => '0'
    )
        port map (
      CLR => '0',
      D => \demux16_data1_reg_n_0_[14]\,
      G => t_last,
      GE => '1',
      Q => output_data1(14)
    );
\output_data1_reg[15]\: unisim.vcomponents.LDCE
    generic map(
      INIT => '0'
    )
        port map (
      CLR => '0',
      D => \demux16_data1_reg_n_0_[15]\,
      G => t_last,
      GE => '1',
      Q => output_data1(15)
    );
\output_data1_reg[1]\: unisim.vcomponents.LDCE
    generic map(
      INIT => '0'
    )
        port map (
      CLR => '0',
      D => \demux16_data1_reg_n_0_[1]\,
      G => t_last,
      GE => '1',
      Q => output_data1(1)
    );
\output_data1_reg[2]\: unisim.vcomponents.LDCE
    generic map(
      INIT => '0'
    )
        port map (
      CLR => '0',
      D => \demux16_data1_reg_n_0_[2]\,
      G => t_last,
      GE => '1',
      Q => output_data1(2)
    );
\output_data1_reg[3]\: unisim.vcomponents.LDCE
    generic map(
      INIT => '0'
    )
        port map (
      CLR => '0',
      D => \demux16_data1_reg_n_0_[3]\,
      G => t_last,
      GE => '1',
      Q => output_data1(3)
    );
\output_data1_reg[4]\: unisim.vcomponents.LDCE
    generic map(
      INIT => '0'
    )
        port map (
      CLR => '0',
      D => \demux16_data1_reg_n_0_[4]\,
      G => t_last,
      GE => '1',
      Q => output_data1(4)
    );
\output_data1_reg[5]\: unisim.vcomponents.LDCE
    generic map(
      INIT => '0'
    )
        port map (
      CLR => '0',
      D => \demux16_data1_reg_n_0_[5]\,
      G => t_last,
      GE => '1',
      Q => output_data1(5)
    );
\output_data1_reg[6]\: unisim.vcomponents.LDCE
    generic map(
      INIT => '0'
    )
        port map (
      CLR => '0',
      D => \demux16_data1_reg_n_0_[6]\,
      G => t_last,
      GE => '1',
      Q => output_data1(6)
    );
\output_data1_reg[7]\: unisim.vcomponents.LDCE
    generic map(
      INIT => '0'
    )
        port map (
      CLR => '0',
      D => \demux16_data1_reg_n_0_[7]\,
      G => t_last,
      GE => '1',
      Q => output_data1(7)
    );
\output_data1_reg[8]\: unisim.vcomponents.LDCE
    generic map(
      INIT => '0'
    )
        port map (
      CLR => '0',
      D => \demux16_data1_reg_n_0_[8]\,
      G => t_last,
      GE => '1',
      Q => output_data1(8)
    );
\output_data1_reg[9]\: unisim.vcomponents.LDCE
    generic map(
      INIT => '0'
    )
        port map (
      CLR => '0',
      D => \demux16_data1_reg_n_0_[9]\,
      G => t_last,
      GE => '1',
      Q => output_data1(9)
    );
\output_data2_reg[0]\: unisim.vcomponents.LDCE
    generic map(
      INIT => '0'
    )
        port map (
      CLR => '0',
      D => \demux16_data2_reg_n_0_[0]\,
      G => t_last,
      GE => '1',
      Q => output_data2(0)
    );
\output_data2_reg[10]\: unisim.vcomponents.LDCE
    generic map(
      INIT => '0'
    )
        port map (
      CLR => '0',
      D => \demux16_data2_reg_n_0_[10]\,
      G => t_last,
      GE => '1',
      Q => output_data2(10)
    );
\output_data2_reg[11]\: unisim.vcomponents.LDCE
    generic map(
      INIT => '0'
    )
        port map (
      CLR => '0',
      D => \demux16_data2_reg_n_0_[11]\,
      G => t_last,
      GE => '1',
      Q => output_data2(11)
    );
\output_data2_reg[12]\: unisim.vcomponents.LDCE
    generic map(
      INIT => '0'
    )
        port map (
      CLR => '0',
      D => \demux16_data2_reg_n_0_[12]\,
      G => t_last,
      GE => '1',
      Q => output_data2(12)
    );
\output_data2_reg[13]\: unisim.vcomponents.LDCE
    generic map(
      INIT => '0'
    )
        port map (
      CLR => '0',
      D => \demux16_data2_reg_n_0_[13]\,
      G => t_last,
      GE => '1',
      Q => output_data2(13)
    );
\output_data2_reg[14]\: unisim.vcomponents.LDCE
    generic map(
      INIT => '0'
    )
        port map (
      CLR => '0',
      D => \demux16_data2_reg_n_0_[14]\,
      G => t_last,
      GE => '1',
      Q => output_data2(14)
    );
\output_data2_reg[15]\: unisim.vcomponents.LDCE
    generic map(
      INIT => '0'
    )
        port map (
      CLR => '0',
      D => \demux16_data2_reg_n_0_[15]\,
      G => t_last,
      GE => '1',
      Q => output_data2(15)
    );
\output_data2_reg[1]\: unisim.vcomponents.LDCE
    generic map(
      INIT => '0'
    )
        port map (
      CLR => '0',
      D => \demux16_data2_reg_n_0_[1]\,
      G => t_last,
      GE => '1',
      Q => output_data2(1)
    );
\output_data2_reg[2]\: unisim.vcomponents.LDCE
    generic map(
      INIT => '0'
    )
        port map (
      CLR => '0',
      D => \demux16_data2_reg_n_0_[2]\,
      G => t_last,
      GE => '1',
      Q => output_data2(2)
    );
\output_data2_reg[3]\: unisim.vcomponents.LDCE
    generic map(
      INIT => '0'
    )
        port map (
      CLR => '0',
      D => \demux16_data2_reg_n_0_[3]\,
      G => t_last,
      GE => '1',
      Q => output_data2(3)
    );
\output_data2_reg[4]\: unisim.vcomponents.LDCE
    generic map(
      INIT => '0'
    )
        port map (
      CLR => '0',
      D => \demux16_data2_reg_n_0_[4]\,
      G => t_last,
      GE => '1',
      Q => output_data2(4)
    );
\output_data2_reg[5]\: unisim.vcomponents.LDCE
    generic map(
      INIT => '0'
    )
        port map (
      CLR => '0',
      D => \demux16_data2_reg_n_0_[5]\,
      G => t_last,
      GE => '1',
      Q => output_data2(5)
    );
\output_data2_reg[6]\: unisim.vcomponents.LDCE
    generic map(
      INIT => '0'
    )
        port map (
      CLR => '0',
      D => \demux16_data2_reg_n_0_[6]\,
      G => t_last,
      GE => '1',
      Q => output_data2(6)
    );
\output_data2_reg[7]\: unisim.vcomponents.LDCE
    generic map(
      INIT => '0'
    )
        port map (
      CLR => '0',
      D => \demux16_data2_reg_n_0_[7]\,
      G => t_last,
      GE => '1',
      Q => output_data2(7)
    );
\output_data2_reg[8]\: unisim.vcomponents.LDCE
    generic map(
      INIT => '0'
    )
        port map (
      CLR => '0',
      D => \demux16_data2_reg_n_0_[8]\,
      G => t_last,
      GE => '1',
      Q => output_data2(8)
    );
\output_data2_reg[9]\: unisim.vcomponents.LDCE
    generic map(
      INIT => '0'
    )
        port map (
      CLR => '0',
      D => \demux16_data2_reg_n_0_[9]\,
      G => t_last,
      GE => '1',
      Q => output_data2(9)
    );
\output_data3_reg[0]\: unisim.vcomponents.LDCE
    generic map(
      INIT => '0'
    )
        port map (
      CLR => '0',
      D => \demux16_data3_reg_n_0_[0]\,
      G => t_last,
      GE => '1',
      Q => output_data3(0)
    );
\output_data3_reg[10]\: unisim.vcomponents.LDCE
    generic map(
      INIT => '0'
    )
        port map (
      CLR => '0',
      D => \demux16_data3_reg_n_0_[10]\,
      G => t_last,
      GE => '1',
      Q => output_data3(10)
    );
\output_data3_reg[11]\: unisim.vcomponents.LDCE
    generic map(
      INIT => '0'
    )
        port map (
      CLR => '0',
      D => \demux16_data3_reg_n_0_[11]\,
      G => t_last,
      GE => '1',
      Q => output_data3(11)
    );
\output_data3_reg[12]\: unisim.vcomponents.LDCE
    generic map(
      INIT => '0'
    )
        port map (
      CLR => '0',
      D => \demux16_data3_reg_n_0_[12]\,
      G => t_last,
      GE => '1',
      Q => output_data3(12)
    );
\output_data3_reg[13]\: unisim.vcomponents.LDCE
    generic map(
      INIT => '0'
    )
        port map (
      CLR => '0',
      D => \demux16_data3_reg_n_0_[13]\,
      G => t_last,
      GE => '1',
      Q => output_data3(13)
    );
\output_data3_reg[14]\: unisim.vcomponents.LDCE
    generic map(
      INIT => '0'
    )
        port map (
      CLR => '0',
      D => \demux16_data3_reg_n_0_[14]\,
      G => t_last,
      GE => '1',
      Q => output_data3(14)
    );
\output_data3_reg[15]\: unisim.vcomponents.LDCE
    generic map(
      INIT => '0'
    )
        port map (
      CLR => '0',
      D => \demux16_data3_reg_n_0_[15]\,
      G => t_last,
      GE => '1',
      Q => output_data3(15)
    );
\output_data3_reg[1]\: unisim.vcomponents.LDCE
    generic map(
      INIT => '0'
    )
        port map (
      CLR => '0',
      D => \demux16_data3_reg_n_0_[1]\,
      G => t_last,
      GE => '1',
      Q => output_data3(1)
    );
\output_data3_reg[2]\: unisim.vcomponents.LDCE
    generic map(
      INIT => '0'
    )
        port map (
      CLR => '0',
      D => \demux16_data3_reg_n_0_[2]\,
      G => t_last,
      GE => '1',
      Q => output_data3(2)
    );
\output_data3_reg[3]\: unisim.vcomponents.LDCE
    generic map(
      INIT => '0'
    )
        port map (
      CLR => '0',
      D => \demux16_data3_reg_n_0_[3]\,
      G => t_last,
      GE => '1',
      Q => output_data3(3)
    );
\output_data3_reg[4]\: unisim.vcomponents.LDCE
    generic map(
      INIT => '0'
    )
        port map (
      CLR => '0',
      D => \demux16_data3_reg_n_0_[4]\,
      G => t_last,
      GE => '1',
      Q => output_data3(4)
    );
\output_data3_reg[5]\: unisim.vcomponents.LDCE
    generic map(
      INIT => '0'
    )
        port map (
      CLR => '0',
      D => \demux16_data3_reg_n_0_[5]\,
      G => t_last,
      GE => '1',
      Q => output_data3(5)
    );
\output_data3_reg[6]\: unisim.vcomponents.LDCE
    generic map(
      INIT => '0'
    )
        port map (
      CLR => '0',
      D => \demux16_data3_reg_n_0_[6]\,
      G => t_last,
      GE => '1',
      Q => output_data3(6)
    );
\output_data3_reg[7]\: unisim.vcomponents.LDCE
    generic map(
      INIT => '0'
    )
        port map (
      CLR => '0',
      D => \demux16_data3_reg_n_0_[7]\,
      G => t_last,
      GE => '1',
      Q => output_data3(7)
    );
\output_data3_reg[8]\: unisim.vcomponents.LDCE
    generic map(
      INIT => '0'
    )
        port map (
      CLR => '0',
      D => \demux16_data3_reg_n_0_[8]\,
      G => t_last,
      GE => '1',
      Q => output_data3(8)
    );
\output_data3_reg[9]\: unisim.vcomponents.LDCE
    generic map(
      INIT => '0'
    )
        port map (
      CLR => '0',
      D => \demux16_data3_reg_n_0_[9]\,
      G => t_last,
      GE => '1',
      Q => output_data3(9)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity pdm_to_pcm_demux16_sync_0_0 is
  port (
    clk : in STD_LOGIC;
    t_valid : in STD_LOGIC;
    t_last : in STD_LOGIC;
    output_data0 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    output_data1 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    output_data2 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    output_data3 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    finish : out STD_LOGIC;
    input_data : in STD_LOGIC_VECTOR ( 15 downto 0 )
  );
  attribute NotValidForBitStream : boolean;
  attribute NotValidForBitStream of pdm_to_pcm_demux16_sync_0_0 : entity is true;
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of pdm_to_pcm_demux16_sync_0_0 : entity is "pdm_to_pcm_demux16_sync_0_0,demux16_sync,{}";
  attribute downgradeipidentifiedwarnings : string;
  attribute downgradeipidentifiedwarnings of pdm_to_pcm_demux16_sync_0_0 : entity is "yes";
  attribute ip_definition_source : string;
  attribute ip_definition_source of pdm_to_pcm_demux16_sync_0_0 : entity is "module_ref";
  attribute x_core_info : string;
  attribute x_core_info of pdm_to_pcm_demux16_sync_0_0 : entity is "demux16_sync,Vivado 2019.1";
end pdm_to_pcm_demux16_sync_0_0;

architecture STRUCTURE of pdm_to_pcm_demux16_sync_0_0 is
  signal \^t_last\ : STD_LOGIC;
  attribute x_interface_info : string;
  attribute x_interface_info of clk : signal is "xilinx.com:signal:clock:1.0 clk CLK";
  attribute x_interface_parameter : string;
  attribute x_interface_parameter of clk : signal is "XIL_INTERFACENAME clk, FREQ_HZ 18431963, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, INSERT_VIP 0";
begin
  \^t_last\ <= t_last;
  finish <= \^t_last\;
U0: entity work.pdm_to_pcm_demux16_sync_0_0_demux16_sync
     port map (
      clk => clk,
      input_data(15 downto 0) => input_data(15 downto 0),
      output_data0(15 downto 0) => output_data0(15 downto 0),
      output_data1(15 downto 0) => output_data1(15 downto 0),
      output_data2(15 downto 0) => output_data2(15 downto 0),
      output_data3(15 downto 0) => output_data3(15 downto 0),
      t_last => \^t_last\,
      t_valid => t_valid
    );
end STRUCTURE;
