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-- IP VLNV: xilinx.com:module_ref:energy_compare:1.0
-- IP Revision: 1

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY pdm_to_pcm_energy_compare_0_0 IS
  PORT (
    clk : IN STD_LOGIC;
    start : IN STD_LOGIC;
    val_in : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
    max_found : OUT STD_LOGIC;
    start_fifo : OUT STD_LOGIC;
    val_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
  );
END pdm_to_pcm_energy_compare_0_0;

ARCHITECTURE pdm_to_pcm_energy_compare_0_0_arch OF pdm_to_pcm_energy_compare_0_0 IS
  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
  ATTRIBUTE DowngradeIPIdentifiedWarnings OF pdm_to_pcm_energy_compare_0_0_arch: ARCHITECTURE IS "yes";
  COMPONENT energy_compare IS
    PORT (
      clk : IN STD_LOGIC;
      start : IN STD_LOGIC;
      val_in : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
      max_found : OUT STD_LOGIC;
      start_fifo : OUT STD_LOGIC;
      val_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
    );
  END COMPONENT energy_compare;
  ATTRIBUTE X_CORE_INFO : STRING;
  ATTRIBUTE X_CORE_INFO OF pdm_to_pcm_energy_compare_0_0_arch: ARCHITECTURE IS "energy_compare,Vivado 2019.1";
  ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
  ATTRIBUTE CHECK_LICENSE_TYPE OF pdm_to_pcm_energy_compare_0_0_arch : ARCHITECTURE IS "pdm_to_pcm_energy_compare_0_0,energy_compare,{}";
  ATTRIBUTE CORE_GENERATION_INFO : STRING;
  ATTRIBUTE CORE_GENERATION_INFO OF pdm_to_pcm_energy_compare_0_0_arch: ARCHITECTURE IS "pdm_to_pcm_energy_compare_0_0,energy_compare,{x_ipProduct=Vivado 2019.1,x_ipVendor=xilinx.com,x_ipLibrary=module_ref,x_ipName=energy_compare,x_ipVersion=1.0,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
  ATTRIBUTE IP_DEFINITION_SOURCE : STRING;
  ATTRIBUTE IP_DEFINITION_SOURCE OF pdm_to_pcm_energy_compare_0_0_arch: ARCHITECTURE IS "module_ref";
  ATTRIBUTE X_INTERFACE_INFO : STRING;
  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
  ATTRIBUTE X_INTERFACE_PARAMETER OF clk: SIGNAL IS "XIL_INTERFACENAME clk, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0";
  ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
BEGIN
  U0 : energy_compare
    PORT MAP (
      clk => clk,
      start => start,
      val_in => val_in,
      max_found => max_found,
      start_fifo => start_fifo,
      val_out => val_out
    );
END pdm_to_pcm_energy_compare_0_0_arch;
