#-----------------------------------------------------------
# Vivado v2019.1 (64-bit)
# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019
# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
# Start of session at: Mon May 25 19:57:08 2020
# Process ID: 18696
# Current directory: D:/sound_location_project/energy/dat096-master-latest_version/latest_version
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent28284 D:\sound_location_project\energy\dat096-master-latest_version\latest_version\dat096_ref_design.xpr
# Log file: D:/sound_location_project/energy/dat096-master-latest_version/latest_version/vivado.log
# Journal file: D:/sound_location_project/energy/dat096-master-latest_version/latest_version\vivado.jou
#-----------------------------------------------------------
start_gui
open_project D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.xpr
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/clean_rst.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/decoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/encoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_constants.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_regs.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_test.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/timescale.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_an.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_mdio.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_rx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_sync.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_tx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/ddr/mig_interface_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/i2c/i2c_slave_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/micron/sdram/mobile_sdr.v:]
Scanning sources...
Finished scanning sources
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/clean_rst.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/decoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/encoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_constants.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_regs.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_test.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/timescale.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_an.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_mdio.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_rx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_sync.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_tx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/ddr/mig_interface_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/i2c/i2c_slave_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/micron/sdram/mobile_sdr.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/clean_rst.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/decoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/encoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_constants.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_regs.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_test.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/timescale.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_an.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_mdio.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_rx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_sync.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_tx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/ddr/mig_interface_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/i2c/i2c_slave_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/micron/sdram/mobile_sdr.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/clean_rst.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/decoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/encoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_constants.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_regs.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_test.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/timescale.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_an.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_mdio.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_rx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_sync.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_tx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/ddr/mig_interface_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/i2c/i2c_slave_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/micron/sdram/mobile_sdr.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/clean_rst.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/decoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/encoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_constants.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_regs.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_test.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/timescale.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_an.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_mdio.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_rx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_sync.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_tx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/ddr/mig_interface_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/i2c/i2c_slave_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/micron/sdram/mobile_sdr.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/clean_rst.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/decoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/encoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_constants.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_regs.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_test.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/timescale.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_an.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_mdio.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_rx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_sync.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_tx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/ddr/mig_interface_model.v:]
INFO: [Common 17-14] Message 'filemgmt 56-99' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
WARNING: [filemgmt 56-3] IP Repository Path: Could not find the directory 'D:/sound_location_project/energy/dat096-master-latest_version/sound_location_project'.
INFO: [IP_Flow 19-234] Refreshing IP repositories
WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'd:/sound_location_project/energy/dat096-master-latest_version/sound_location_project'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/xilinx/Vivado/2019.1/data/ip'.
open_project: Time (s): cpu = 00:00:24 ; elapsed = 00:00:13 . Memory (MB): peak = 833.215 ; gain = 190.766
update_compile_order -fileset sources_1
open_run impl_2
INFO: [Device 21-403] Loading part xc7a200tfbg676-2
INFO: [Netlist 29-17] Analyzing 3499 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2019.1
INFO: [Project 1-570] Preparing netlist for logic optimization
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'masterrdwrgen.filter/pdm_to_pcm_i/clk_wiz_0/clk_in1' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
INFO: [Timing 38-478] Restoring timing data from binary archive.
INFO: [Timing 38-479] Binary timing data restore complete.
INFO: [Project 1-856] Restoring constraints from binary archive.
INFO: [Project 1-853] Binary constraint restore complete.
Reading XDEF placement.
Reading placer database...
Reading XDEF routing.
Read XDEF File: Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 2334.063 ; gain = 50.996
Restored from archive | CPU: 6.000000 secs | Memory: 0.000000 MB |
Finished XDEF File Restore: Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 2334.063 ; gain = 50.996
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.016 . Memory (MB): peak = 2334.063 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 492 instances were transformed.
  IOBUF => IOBUF (IBUF, OBUFT): 8 instances
  IOBUFDS_DIFF_OUT_INTERMDISABLE => IOBUFDS_DIFF_OUT_INTERMDISABLE (IBUFDS_INTERMDISABLE_INT, IBUFDS_INTERMDISABLE_INT, INV, OBUFTDS, OBUFTDS): 8 instances
  IOBUF_INTERMDISABLE => IOBUF_INTERMDISABLE (IBUF_INTERMDISABLE, OBUFT): 64 instances
  OBUFDS => OBUFDS_DUAL_BUF (INV, OBUFDS, OBUFDS): 1 instances
  RAM16X1D => RAM32X1D (RAMD32, RAMD32): 45 instances
  RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 343 instances
  RAM32X1D => RAM32X1D (RAMD32, RAMD32): 22 instances
  SRLC32E => SRL16E: 1 instances

open_run: Time (s): cpu = 00:00:47 ; elapsed = 00:00:39 . Memory (MB): peak = 2450.355 ; gain = 1019.227
open_report: Time (s): cpu = 00:00:33 ; elapsed = 00:00:17 . Memory (MB): peak = 2628.863 ; gain = 158.145
CRITICAL WARNING: [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.
WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met.
open_bd_design {D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/pdm_to_pcm.bd}
Adding component instance block -- xilinx.com:ip:cic_compiler:4.0 - cic_compiler_0
Adding component instance block -- xilinx.com:ip:fir_compiler:7.2 - fir_compiler_0
Adding component instance block -- xilinx.com:ip:fir_compiler:7.2 - fir_compiler_1
Adding component instance block -- xilinx.com:ip:clk_wiz:6.0 - clk_wiz_0
Adding component instance block -- xilinx.com:ip:fifo_generator:13.2 - fifo_generator_0
INFO: [xilinx.com:ip:fifo_generator:13.2-5968] /fifo_generator_0Executing the post_config_ip from bd
Adding component instance block -- xilinx.com:ip:util_vector_logic:2.0 - util_vector_logic_0
Adding component instance block -- xilinx.com:ip:util_ds_buf:2.1 - util_ds_buf_0
Adding component instance block -- xilinx.com:module_ref:clk_div:1.0 - clk_div_1
Adding component instance block -- xilinx.com:ip:util_vector_logic:2.0 - util_vector_logic_1
Adding component instance block -- xilinx.com:ip:c_addsub:12.0 - c_addsub_0
Adding component instance block -- xilinx.com:ip:c_addsub:12.0 - c_addsub_1
Adding component instance block -- xilinx.com:ip:c_addsub:12.0 - c_addsub_2
Adding component instance block -- xilinx.com:ip:blk_mem_gen:8.4 - blk_mem_gen_0
Adding component instance block -- xilinx.com:ip:blk_mem_gen:8.4 - blk_mem_gen_1
Adding component instance block -- xilinx.com:ip:c_shift_ram:12.0 - c_shift_ram_0
Adding component instance block -- xilinx.com:ip:c_shift_ram:12.0 - c_shift_ram_1
Adding component instance block -- xilinx.com:ip:c_shift_ram:12.0 - c_shift_ram_2
Adding component instance block -- xilinx.com:ip:c_shift_ram:12.0 - c_shift_ram_3
Adding component instance block -- xilinx.com:ip:blk_mem_gen:8.4 - blk_mem_gen_2
Adding component instance block -- xilinx.com:ip:blk_mem_gen:8.4 - blk_mem_gen_3
Adding component instance block -- xilinx.com:ip:mult_gen:12.0 - mult_gen_0
Adding component instance block -- xilinx.com:module_ref:clk_div:1.0 - clk_div_0
Adding component instance block -- xilinx.com:module_ref:hp_filter:1.0 - hp_filter_0
Adding component instance block -- xilinx.com:module_ref:timemux:1.0 - timemux_0
Adding component instance block -- xilinx.com:module_ref:demux16_sync:1.0 - demux16_sync_0
Adding component instance block -- xilinx.com:module_ref:scan:1.0 - scan_0
Adding component instance block -- xilinx.com:module_ref:energy_compare:1.0 - energy_compare_0
WARNING: [BD 41-1731] Type mismatch between connected pins: /clk_wiz_0/clk_out1(clk) and /clk_div_0/clk_in(undef)
WARNING: [BD 41-1731] Type mismatch between connected pins: /clk_div_1/clk_out(undef) and /c_addsub_1/CLK(clk)
WARNING: [BD 41-1731] Type mismatch between connected pins: /clk_div_1/clk_out(undef) and /c_addsub_0/CLK(clk)
WARNING: [BD 41-1731] Type mismatch between connected pins: /clk_div_1/clk_out(undef) and /c_shift_ram_2/CLK(clk)
WARNING: [BD 41-1731] Type mismatch between connected pins: /clk_div_1/clk_out(undef) and /c_shift_ram_3/CLK(clk)
WARNING: [BD 41-1731] Type mismatch between connected pins: /clk_div_1/clk_out(undef) and /c_shift_ram_1/CLK(clk)
WARNING: [BD 41-1731] Type mismatch between connected pins: /clk_div_1/clk_out(undef) and /fifo_generator_0/wr_clk(clk)
WARNING: [BD 41-1731] Type mismatch between connected pins: /clk_div_1/clk_out(undef) and /util_ds_buf_0/BUFG_I(clk)
WARNING: [BD 41-1731] Type mismatch between connected pins: /clk_div_1/clk_out(undef) and /c_shift_ram_0/CLK(clk)
WARNING: [BD 41-1731] Type mismatch between connected pins: /clk_div_1/clk_out(undef) and /c_addsub_2/CLK(clk)
WARNING: [BD 41-1731] Type mismatch between connected pins: /clk_div_1/clk_out(undef) and /mult_gen_0/CLK(clk)
WARNING: [BD 41-1731] Type mismatch between connected pins: /clk_div_1/clk_out(undef) and /scan_0/clk(clk)
WARNING: [BD 41-1731] Type mismatch between connected pins: /clk_div_1/clk_out(undef) and /energy_compare_0/clk(clk)
WARNING: [BD 41-1731] Type mismatch between connected pins: /scan_0/adder_enable(undef) and /c_addsub_1/CE(ce)
WARNING: [BD 41-1731] Type mismatch between connected pins: /scan_0/adder_enable(undef) and /c_addsub_0/CE(ce)
WARNING: [BD 41-1731] Type mismatch between connected pins: /scan_0/adder_enable(undef) and /c_addsub_2/CE(ce)
WARNING: [BD 41-1731] Type mismatch between connected pins: /scan_0/adder_enable(undef) and /c_shift_ram_0/CE(ce)
WARNING: [BD 41-1731] Type mismatch between connected pins: /scan_0/adder_enable(undef) and /c_shift_ram_1/CE(ce)
WARNING: [BD 41-1731] Type mismatch between connected pins: /scan_0/adder_enable(undef) and /c_shift_ram_2/CE(ce)
WARNING: [BD 41-1731] Type mismatch between connected pins: /scan_0/adder_enable(undef) and /c_shift_ram_3/CE(ce)
Successfully read diagram <pdm_to_pcm> from BD file <D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/pdm_to_pcm.bd>
open_bd_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2833.215 ; gain = 13.813
report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -routable_nets -name timing_1
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met.
report_timing_summary: Time (s): cpu = 00:00:37 ; elapsed = 00:00:17 . Memory (MB): peak = 3010.008 ; gain = 155.992
open_bd_design {D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/pdm_to_pcm.bd}
open_bd_design {D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/pdm_to_pcm.bd}
open_bd_design {D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/pdm_to_pcm.bd}
update_module_reference pdm_to_pcm_demux16_sync_0_0
INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing.
INFO: [IP_Flow 19-234] Refreshing IP repositories
WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'd:/sound_location_project/energy/dat096-master-latest_version/sound_location_project'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
Upgrading 'D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/pdm_to_pcm.bd'
INFO: [IP_Flow 19-3420] Updated pdm_to_pcm_demux16_sync_0_0 to use current project options
Wrote  : <D:\sound_location_project\energy\dat096-master-latest_version\latest_version\dat096_ref_design.srcs\sources_1\bd\pdm_to_pcm\pdm_to_pcm.bd> 
Wrote  : <D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ui/bd_8ec0abfc.ui> 
reset_run impl_2
reset_run synth_2
launch_runs impl_2 -jobs 4
WARNING: [BD 41-2180] Resetting the memory initialization file of </blk_mem_gen_0> to default.
WARNING: [BD 41-2180] Resetting the memory initialization file of </blk_mem_gen_3> to default.
WARNING: [BD 41-2180] Resetting the memory initialization file of </blk_mem_gen_1> to default.
WARNING: [BD 41-2180] Resetting the memory initialization file of </blk_mem_gen_2> to default.
INFO: [xilinx.com:ip:fir_compiler:7.2-913] /fir_compiler_1 Data_Sign has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:fir_compiler:7.2-913] /fir_compiler_1 Data_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:fir_compiler:7.2-913] /fir_compiler_1 Data_Fractional_Bits has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:cic_compiler:4.0-913] /cic_compiler_0 Input_Data_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:fir_compiler:7.2-913] /fir_compiler_0 Data_Sign has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:fir_compiler:7.2-913] /fir_compiler_0 Data_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:fir_compiler:7.2-913] /fir_compiler_0 Data_Fractional_Bits has been set to manual on the GUI. It will not be updated during validation with a propagated value.
WARNING: [xilinx.com:ip:c_addsub:12.0-313] /c_addsub_0 A-DATA: Field type resolution: data = integer. /c_shift_ram_0 Q-DATA: data = null. /c_shift_ram_0 Q-DATA data field will be interpreted as integer
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_0 A_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_0 A_Type has been set to manual on the GUI. It will not be updated during validation with a propagated value.
WARNING: [xilinx.com:ip:c_addsub:12.0-313] /c_addsub_0 B-DATA: Field type resolution: data = integer. /c_shift_ram_1 Q-DATA: data = null. /c_shift_ram_1 Q-DATA data field will be interpreted as integer
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_0 B_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_0 B_Type has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:c_addsub:12.0-308] /c_addsub_0 A-DATA: Validating field: data(16:0): int16 against /c_shift_ram_0 Q-DATA: data(16:0): bit16.
WARNING: [xilinx.com:ip:c_addsub:12.0-313] /c_addsub_0 A-DATA: Field type resolution: data = integer. /c_shift_ram_0 Q-DATA: data = null. /c_shift_ram_0 Q-DATA data field will be interpreted as integer
INFO: [xilinx.com:ip:c_addsub:12.0-308] /c_addsub_0 B-DATA: Validating field: data(16:0): int16 against /c_shift_ram_1 Q-DATA: data(16:0): bit16.
WARNING: [xilinx.com:ip:c_addsub:12.0-313] /c_addsub_0 B-DATA: Field type resolution: data = integer. /c_shift_ram_1 Q-DATA: data = null. /c_shift_ram_1 Q-DATA data field will be interpreted as integer
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_2 A_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_2 A_Type has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_2 B_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_2 B_Type has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:mult_gen:12.0-913] /mult_gen_0 PortAType has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:mult_gen:12.0-913] /mult_gen_0 PortBType has been set to manual on the GUI. It will not be updated during validation with a propagated value.
WARNING: [xilinx.com:ip:c_addsub:12.0-313] /c_addsub_1 A-DATA: Field type resolution: data = integer. /c_shift_ram_2 Q-DATA: data = null. /c_shift_ram_2 Q-DATA data field will be interpreted as integer
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_1 A_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_1 A_Type has been set to manual on the GUI. It will not be updated during validation with a propagated value.
WARNING: [xilinx.com:ip:c_addsub:12.0-313] /c_addsub_1 B-DATA: Field type resolution: data = integer. /c_shift_ram_3 Q-DATA: data = null. /c_shift_ram_3 Q-DATA data field will be interpreted as integer
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_1 B_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_1 B_Type has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:c_addsub:12.0-308] /c_addsub_1 A-DATA: Validating field: data(16:0): int16 against /c_shift_ram_2 Q-DATA: data(16:0): bit16.
WARNING: [xilinx.com:ip:c_addsub:12.0-313] /c_addsub_1 A-DATA: Field type resolution: data = integer. /c_shift_ram_2 Q-DATA: data = null. /c_shift_ram_2 Q-DATA data field will be interpreted as integer
INFO: [xilinx.com:ip:c_addsub:12.0-308] /c_addsub_1 B-DATA: Validating field: data(16:0): int16 against /c_shift_ram_3 Q-DATA: data(16:0): bit16.
WARNING: [xilinx.com:ip:c_addsub:12.0-313] /c_addsub_1 B-DATA: Field type resolution: data = integer. /c_shift_ram_3 Q-DATA: data = null. /c_shift_ram_3 Q-DATA data field will be interpreted as integer
WARNING: [BD 41-927] Following properties on pin /timemux_0/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
	CLK_DOMAIN=/clk_wiz_0_clk_out1 
WARNING: [BD 41-927] Following properties on pin /demux16_sync_0/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
	CLK_DOMAIN=/clk_wiz_0_clk_out1 
CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow.
Please check your design and connect them as needed: 
/energy_compare_0/t_finish

Wrote  : <D:\sound_location_project\energy\dat096-master-latest_version\latest_version\dat096_ref_design.srcs\sources_1\bd\pdm_to_pcm\pdm_to_pcm.bd> 
VHDL Output written to : D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/synth/pdm_to_pcm.vhd
VHDL Output written to : D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/sim/pdm_to_pcm.vhd
VHDL Output written to : D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.vhd
INFO: [BD 41-1029] Generation completed for the IP Integrator block cic_compiler_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block fir_compiler_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block fir_compiler_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block clk_wiz_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block fifo_generator_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block util_vector_logic_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block clk_div_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block util_ds_buf_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block clk_div_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block hp_filter_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block util_vector_logic_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block timemux_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block demux16_sync_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_addsub_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_addsub_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_addsub_2 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block blk_mem_gen_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block blk_mem_gen_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_shift_ram_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_shift_ram_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_shift_ram_2 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_shift_ram_3 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block blk_mem_gen_2 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block blk_mem_gen_3 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block scan_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block energy_compare_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block mult_gen_0 .
Exporting to file D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hw_handoff/pdm_to_pcm.hwh
Generated Block Design Tcl file D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hw_handoff/pdm_to_pcm_bd.tcl
Generated Hardware Definition File D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/synth/pdm_to_pcm.hwdef
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/clean_rst.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/decoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/encoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_constants.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_regs.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_test.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/timescale.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_an.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_mdio.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_rx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_sync.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_tx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/ddr/mig_interface_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/i2c/i2c_slave_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/micron/sdram/mobile_sdr.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/clean_rst.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/decoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/encoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_constants.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_regs.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_test.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/timescale.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_an.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_mdio.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_rx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_sync.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_tx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/ddr/mig_interface_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/i2c/i2c_slave_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/micron/sdram/mobile_sdr.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/clean_rst.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/decoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/encoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_constants.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_regs.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_test.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/timescale.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_an.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_mdio.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_rx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_sync.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_tx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/ddr/mig_interface_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/i2c/i2c_slave_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/micron/sdram/mobile_sdr.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/clean_rst.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/decoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/encoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_constants.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_regs.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_test.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/timescale.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_an.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_mdio.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_rx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_sync.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_tx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/ddr/mig_interface_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/i2c/i2c_slave_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/micron/sdram/mobile_sdr.v:]
[Mon May 25 20:42:50 2020] Launched pdm_to_pcm_demux16_sync_0_0_synth_1, synth_2...
Run output will be captured here:
pdm_to_pcm_demux16_sync_0_0_synth_1: D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.runs/pdm_to_pcm_demux16_sync_0_0_synth_1/runme.log
synth_2: D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.runs/synth_2/runme.log
[Mon May 25 20:42:51 2020] Launched impl_2...
Run output will be captured here: D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.runs/impl_2/runme.log
launch_runs: Time (s): cpu = 00:00:08 ; elapsed = 00:00:15 . Memory (MB): peak = 3406.266 ; gain = 50.824
report_clock_interaction -delay_type min_max -significant_digits 3 -name timing_2
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
WARNING: [Timing 38-164] This design has multiple clocks. Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
open_bd_design {D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/pdm_to_pcm.bd}
create_ip_run [get_files -of_objects [get_fileset sources_1] D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/pdm_to_pcm.bd]
refresh_design
INFO: [Netlist 29-17] Analyzing 3499 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2019.1
INFO: [Project 1-570] Preparing netlist for logic optimization
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'masterrdwrgen.filter/pdm_to_pcm_i/clk_wiz_0/clk_in1' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
INFO: [Timing 38-478] Restoring timing data from binary archive.
INFO: [Timing 38-479] Binary timing data restore complete.
INFO: [Project 1-856] Restoring constraints from binary archive.
INFO: [Project 1-853] Binary constraint restore complete.
Reading XDEF placement.
Reading placer database...
Reading XDEF routing.
Read XDEF File: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 3514.355 ; gain = 0.000
Restored from archive | CPU: 6.000000 secs | Memory: 0.000000 MB |
Finished XDEF File Restore: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 3514.355 ; gain = 0.000
refresh_design: Time (s): cpu = 00:00:32 ; elapsed = 00:00:27 . Memory (MB): peak = 3514.355 ; gain = 63.125
open_report: Time (s): cpu = 00:00:25 ; elapsed = 00:00:16 . Memory (MB): peak = 3829.449 ; gain = 44.496
CRITICAL WARNING: [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.
WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met.
open_bd_design {D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/pdm_to_pcm.bd}
startgroup
set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {18.432} CONFIG.MMCM_DIVCLK_DIVIDE {7} CONFIG.MMCM_CLKFBOUT_MULT_F {61.125} CONFIG.MMCM_CLKOUT0_DIVIDE_F {47.375} CONFIG.CLKOUT1_JITTER {437.060} CONFIG.CLKOUT1_PHASE_ERROR {514.970}] [get_bd_cells clk_wiz_0]
endgroup
startgroup
set_property -dict [list CONFIG.Input_Sample_Frequency {4.608} CONFIG.Clock_Frequency {18.432} CONFIG.Clock_Frequency {18.432}] [get_bd_cells cic_compiler_0]
endgroup
startgroup
set_property -dict [list CONFIG.Sample_Frequency {3.2} CONFIG.Clock_Frequency {12.8} CONFIG.Coefficient_Width {16} CONFIG.Coefficient_Structure {Half_Band} CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} CONFIG.ColumnConfig {2}] [get_bd_cells fir_compiler_0]
endgroup
startgroup
set_property -dict [list CONFIG.Input_Sample_Frequency {3.2} CONFIG.Clock_Frequency {12.8}] [get_bd_cells cic_compiler_0]
endgroup
startgroup
set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.8} CONFIG.MMCM_DIVCLK_DIVIDE {1} CONFIG.MMCM_CLKFBOUT_MULT_F {10.000} CONFIG.MMCM_CLKOUT0_DIVIDE_F {78.125} CONFIG.CLKOUT1_JITTER {199.846} CONFIG.CLKOUT1_PHASE_ERROR {98.575}] [get_bd_cells clk_wiz_0]
endgroup
startgroup
set_property -dict [list CONFIG.Sample_Frequency {0.2} CONFIG.Clock_Frequency {12.8} CONFIG.Coefficient_Width {16} CONFIG.Coefficient_Structure {Half_Band} CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} CONFIG.ColumnConfig {1}] [get_bd_cells fir_compiler_0]
endgroup
startgroup
set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {18.432} CONFIG.MMCM_DIVCLK_DIVIDE {7} CONFIG.MMCM_CLKFBOUT_MULT_F {61.125} CONFIG.MMCM_CLKOUT0_DIVIDE_F {47.375} CONFIG.CLKOUT1_JITTER {437.060} CONFIG.CLKOUT1_PHASE_ERROR {514.970}] [get_bd_cells clk_wiz_0]
endgroup
startgroup
set_property -dict [list CONFIG.Input_Sample_Frequency {4.608} CONFIG.Clock_Frequency {18.4320000}] [get_bd_cells cic_compiler_0]
endgroup
startgroup
set_property -dict [list CONFIG.Sample_Frequency {0.288} CONFIG.Clock_Frequency {18.432} CONFIG.Clock_Frequency {18.432} CONFIG.Coefficient_Width {16} CONFIG.Coefficient_Structure {Half_Band} CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate}] [get_bd_cells fir_compiler_0]
endgroup
startgroup
set_property -dict [list CONFIG.Sample_Frequency {0.144} CONFIG.Clock_Frequency {18.432} CONFIG.Clock_Frequency {18.432} CONFIG.Coefficient_Width {20} CONFIG.Coefficient_Structure {Symmetric} CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} CONFIG.ColumnConfig {3}] [get_bd_cells fir_compiler_1]
endgroup
reset_run pdm_to_pcm_cic_compiler_0_0_synth_1
reset_run pdm_to_pcm_clk_wiz_0_0_synth_1
reset_run pdm_to_pcm_fir_compiler_0_0_synth_1
reset_run pdm_to_pcm_fir_compiler_1_0_synth_1
reset_run synth_2
close_design
save_bd_design
Wrote  : <D:\sound_location_project\energy\dat096-master-latest_version\latest_version\dat096_ref_design.srcs\sources_1\bd\pdm_to_pcm\pdm_to_pcm.bd> 
launch_runs impl_2 -jobs 4
WARNING: [BD 41-2180] Resetting the memory initialization file of </blk_mem_gen_0> to default.
WARNING: [BD 41-2180] Resetting the memory initialization file of </blk_mem_gen_3> to default.
WARNING: [BD 41-2180] Resetting the memory initialization file of </blk_mem_gen_1> to default.
WARNING: [BD 41-2180] Resetting the memory initialization file of </blk_mem_gen_2> to default.
INFO: [xilinx.com:ip:fir_compiler:7.2-913] /fir_compiler_1 Data_Sign has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:fir_compiler:7.2-913] /fir_compiler_1 Data_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:fir_compiler:7.2-913] /fir_compiler_1 Data_Fractional_Bits has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:cic_compiler:4.0-913] /cic_compiler_0 Input_Data_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:fir_compiler:7.2-913] /fir_compiler_0 Data_Sign has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:fir_compiler:7.2-913] /fir_compiler_0 Data_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:fir_compiler:7.2-913] /fir_compiler_0 Data_Fractional_Bits has been set to manual on the GUI. It will not be updated during validation with a propagated value.
WARNING: [xilinx.com:ip:c_addsub:12.0-313] /c_addsub_0 A-DATA: Field type resolution: data = integer. /c_shift_ram_0 Q-DATA: data = null. /c_shift_ram_0 Q-DATA data field will be interpreted as integer
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_0 A_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_0 A_Type has been set to manual on the GUI. It will not be updated during validation with a propagated value.
WARNING: [xilinx.com:ip:c_addsub:12.0-313] /c_addsub_0 B-DATA: Field type resolution: data = integer. /c_shift_ram_1 Q-DATA: data = null. /c_shift_ram_1 Q-DATA data field will be interpreted as integer
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_0 B_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_0 B_Type has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:c_addsub:12.0-308] /c_addsub_0 A-DATA: Validating field: data(16:0): int16 against /c_shift_ram_0 Q-DATA: data(16:0): bit16.
WARNING: [xilinx.com:ip:c_addsub:12.0-313] /c_addsub_0 A-DATA: Field type resolution: data = integer. /c_shift_ram_0 Q-DATA: data = null. /c_shift_ram_0 Q-DATA data field will be interpreted as integer
INFO: [xilinx.com:ip:c_addsub:12.0-308] /c_addsub_0 B-DATA: Validating field: data(16:0): int16 against /c_shift_ram_1 Q-DATA: data(16:0): bit16.
WARNING: [xilinx.com:ip:c_addsub:12.0-313] /c_addsub_0 B-DATA: Field type resolution: data = integer. /c_shift_ram_1 Q-DATA: data = null. /c_shift_ram_1 Q-DATA data field will be interpreted as integer
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_2 A_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_2 A_Type has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_2 B_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_2 B_Type has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:mult_gen:12.0-913] /mult_gen_0 PortAType has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:mult_gen:12.0-913] /mult_gen_0 PortBType has been set to manual on the GUI. It will not be updated during validation with a propagated value.
WARNING: [xilinx.com:ip:c_addsub:12.0-313] /c_addsub_1 A-DATA: Field type resolution: data = integer. /c_shift_ram_2 Q-DATA: data = null. /c_shift_ram_2 Q-DATA data field will be interpreted as integer
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_1 A_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_1 A_Type has been set to manual on the GUI. It will not be updated during validation with a propagated value.
WARNING: [xilinx.com:ip:c_addsub:12.0-313] /c_addsub_1 B-DATA: Field type resolution: data = integer. /c_shift_ram_3 Q-DATA: data = null. /c_shift_ram_3 Q-DATA data field will be interpreted as integer
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_1 B_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_1 B_Type has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:c_addsub:12.0-308] /c_addsub_1 A-DATA: Validating field: data(16:0): int16 against /c_shift_ram_2 Q-DATA: data(16:0): bit16.
WARNING: [xilinx.com:ip:c_addsub:12.0-313] /c_addsub_1 A-DATA: Field type resolution: data = integer. /c_shift_ram_2 Q-DATA: data = null. /c_shift_ram_2 Q-DATA data field will be interpreted as integer
INFO: [xilinx.com:ip:c_addsub:12.0-308] /c_addsub_1 B-DATA: Validating field: data(16:0): int16 against /c_shift_ram_3 Q-DATA: data(16:0): bit16.
WARNING: [xilinx.com:ip:c_addsub:12.0-313] /c_addsub_1 B-DATA: Field type resolution: data = integer. /c_shift_ram_3 Q-DATA: data = null. /c_shift_ram_3 Q-DATA data field will be interpreted as integer
WARNING: [BD 41-927] Following properties on pin /timemux_0/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
	CLK_DOMAIN=/clk_wiz_0_clk_out1 
WARNING: [BD 41-927] Following properties on pin /demux16_sync_0/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
	CLK_DOMAIN=/clk_wiz_0_clk_out1 
CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow.
Please check your design and connect them as needed: 
/energy_compare_0/t_finish

Wrote  : <D:\sound_location_project\energy\dat096-master-latest_version\latest_version\dat096_ref_design.srcs\sources_1\bd\pdm_to_pcm\pdm_to_pcm.bd> 
VHDL Output written to : D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/synth/pdm_to_pcm.vhd
VHDL Output written to : D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/sim/pdm_to_pcm.vhd
VHDL Output written to : D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.vhd
INFO: [BD 41-1029] Generation completed for the IP Integrator block cic_compiler_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block fir_compiler_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block fir_compiler_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block clk_wiz_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block fifo_generator_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block util_vector_logic_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block clk_div_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block util_ds_buf_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block clk_div_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block hp_filter_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block util_vector_logic_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block timemux_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block demux16_sync_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_addsub_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_addsub_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_addsub_2 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block blk_mem_gen_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block blk_mem_gen_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_shift_ram_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_shift_ram_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_shift_ram_2 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_shift_ram_3 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block blk_mem_gen_2 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block blk_mem_gen_3 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block scan_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block energy_compare_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block mult_gen_0 .
Exporting to file D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hw_handoff/pdm_to_pcm.hwh
Generated Block Design Tcl file D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hw_handoff/pdm_to_pcm_bd.tcl
Generated Hardware Definition File D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/synth/pdm_to_pcm.hwdef
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP pdm_to_pcm_clk_wiz_0_0, cache-ID = a1bc551b142cbeb2; cache size = 88.671 MB.
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/clean_rst.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/decoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/encoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_constants.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_regs.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_test.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/timescale.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_an.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_mdio.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_rx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_sync.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_tx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/ddr/mig_interface_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/i2c/i2c_slave_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/micron/sdram/mobile_sdr.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/clean_rst.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/decoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/encoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_constants.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_regs.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_test.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/timescale.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_an.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_mdio.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_rx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_sync.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_tx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/ddr/mig_interface_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/i2c/i2c_slave_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/micron/sdram/mobile_sdr.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/clean_rst.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/decoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/encoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_constants.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_regs.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_test.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/timescale.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_an.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_mdio.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_rx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_sync.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_tx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/ddr/mig_interface_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/i2c/i2c_slave_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/micron/sdram/mobile_sdr.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/clean_rst.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/decoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/encoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_constants.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_regs.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_test.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/timescale.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_an.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_mdio.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_rx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_sync.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_tx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/ddr/mig_interface_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/i2c/i2c_slave_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/micron/sdram/mobile_sdr.v:]
[Mon May 25 21:22:06 2020] Launched pdm_to_pcm_cic_compiler_0_0_synth_1, pdm_to_pcm_fir_compiler_0_0_synth_1, pdm_to_pcm_fir_compiler_1_0_synth_1, synth_2...
Run output will be captured here:
pdm_to_pcm_cic_compiler_0_0_synth_1: D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.runs/pdm_to_pcm_cic_compiler_0_0_synth_1/runme.log
pdm_to_pcm_fir_compiler_0_0_synth_1: D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.runs/pdm_to_pcm_fir_compiler_0_0_synth_1/runme.log
pdm_to_pcm_fir_compiler_1_0_synth_1: D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.runs/pdm_to_pcm_fir_compiler_1_0_synth_1/runme.log
synth_2: D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.runs/synth_2/runme.log
[Mon May 25 21:22:07 2020] Launched impl_2...
Run output will be captured here: D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.runs/impl_2/runme.log
launch_runs: Time (s): cpu = 00:00:10 ; elapsed = 00:00:20 . Memory (MB): peak = 4591.953 ; gain = 54.039
open_run impl_2
INFO: [Netlist 29-17] Analyzing 3499 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2019.1
INFO: [Project 1-570] Preparing netlist for logic optimization
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'masterrdwrgen.filter/pdm_to_pcm_i/clk_wiz_0/clk_in1' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
INFO: [Timing 38-478] Restoring timing data from binary archive.
INFO: [Timing 38-479] Binary timing data restore complete.
INFO: [Project 1-856] Restoring constraints from binary archive.
INFO: [Project 1-853] Binary constraint restore complete.
Reading XDEF placement.
Reading placer database...
Reading XDEF routing.
Read XDEF File: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 4744.703 ; gain = 7.250
Restored from archive | CPU: 5.000000 secs | Memory: 0.000000 MB |
Finished XDEF File Restore: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 4744.703 ; gain = 7.250
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 4744.703 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 492 instances were transformed.
  IOBUF => IOBUF (IBUF, OBUFT): 8 instances
  IOBUFDS_DIFF_OUT_INTERMDISABLE => IOBUFDS_DIFF_OUT_INTERMDISABLE (IBUFDS_INTERMDISABLE_INT, IBUFDS_INTERMDISABLE_INT, INV, OBUFTDS, OBUFTDS): 8 instances
  IOBUF_INTERMDISABLE => IOBUF_INTERMDISABLE (IBUF_INTERMDISABLE, OBUFT): 64 instances
  OBUFDS => OBUFDS_DUAL_BUF (INV, OBUFDS, OBUFDS): 1 instances
  RAM16X1D => RAM32X1D (RAMD32, RAMD32): 45 instances
  RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 343 instances
  RAM32X1D => RAM32X1D (RAMD32, RAMD32): 22 instances
  SRLC32E => SRL16E: 1 instances

open_run: Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 4744.703 ; gain = 152.750
open_report: Time (s): cpu = 00:00:30 ; elapsed = 00:00:16 . Memory (MB): peak = 4744.703 ; gain = 0.000
CRITICAL WARNING: [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.
WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met.
open_bd_design {D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/pdm_to_pcm.bd}
reset_run impl_2
update_module_reference pdm_to_pcm_demux16_sync_0_0
INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing.
INFO: [IP_Flow 19-234] Refreshing IP repositories
WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'd:/sound_location_project/energy/dat096-master-latest_version/sound_location_project'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
Upgrading 'D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/pdm_to_pcm.bd'
INFO: [IP_Flow 19-3420] Updated pdm_to_pcm_demux16_sync_0_0 to use current project options
Wrote  : <D:\sound_location_project\energy\dat096-master-latest_version\latest_version\dat096_ref_design.srcs\sources_1\bd\pdm_to_pcm\pdm_to_pcm.bd> 
update_module_reference: Time (s): cpu = 00:00:04 ; elapsed = 00:00:15 . Memory (MB): peak = 4744.703 ; gain = 0.000
reset_run synth_2
launch_runs impl_2 -jobs 4
WARNING: [BD 41-2180] Resetting the memory initialization file of </blk_mem_gen_0> to default.
WARNING: [BD 41-2180] Resetting the memory initialization file of </blk_mem_gen_3> to default.
WARNING: [BD 41-2180] Resetting the memory initialization file of </blk_mem_gen_1> to default.
WARNING: [BD 41-2180] Resetting the memory initialization file of </blk_mem_gen_2> to default.
INFO: [xilinx.com:ip:fir_compiler:7.2-913] /fir_compiler_1 Data_Sign has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:fir_compiler:7.2-913] /fir_compiler_1 Data_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:fir_compiler:7.2-913] /fir_compiler_1 Data_Fractional_Bits has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:cic_compiler:4.0-913] /cic_compiler_0 Input_Data_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:fir_compiler:7.2-913] /fir_compiler_0 Data_Sign has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:fir_compiler:7.2-913] /fir_compiler_0 Data_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:fir_compiler:7.2-913] /fir_compiler_0 Data_Fractional_Bits has been set to manual on the GUI. It will not be updated during validation with a propagated value.
WARNING: [xilinx.com:ip:c_addsub:12.0-313] /c_addsub_0 A-DATA: Field type resolution: data = integer. /c_shift_ram_0 Q-DATA: data = null. /c_shift_ram_0 Q-DATA data field will be interpreted as integer
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_0 A_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_0 A_Type has been set to manual on the GUI. It will not be updated during validation with a propagated value.
WARNING: [xilinx.com:ip:c_addsub:12.0-313] /c_addsub_0 B-DATA: Field type resolution: data = integer. /c_shift_ram_1 Q-DATA: data = null. /c_shift_ram_1 Q-DATA data field will be interpreted as integer
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_0 B_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_0 B_Type has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:c_addsub:12.0-308] /c_addsub_0 A-DATA: Validating field: data(16:0): int16 against /c_shift_ram_0 Q-DATA: data(16:0): bit16.
WARNING: [xilinx.com:ip:c_addsub:12.0-313] /c_addsub_0 A-DATA: Field type resolution: data = integer. /c_shift_ram_0 Q-DATA: data = null. /c_shift_ram_0 Q-DATA data field will be interpreted as integer
INFO: [xilinx.com:ip:c_addsub:12.0-308] /c_addsub_0 B-DATA: Validating field: data(16:0): int16 against /c_shift_ram_1 Q-DATA: data(16:0): bit16.
WARNING: [xilinx.com:ip:c_addsub:12.0-313] /c_addsub_0 B-DATA: Field type resolution: data = integer. /c_shift_ram_1 Q-DATA: data = null. /c_shift_ram_1 Q-DATA data field will be interpreted as integer
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_2 A_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_2 A_Type has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_2 B_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_2 B_Type has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:mult_gen:12.0-913] /mult_gen_0 PortAType has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:mult_gen:12.0-913] /mult_gen_0 PortBType has been set to manual on the GUI. It will not be updated during validation with a propagated value.
WARNING: [xilinx.com:ip:c_addsub:12.0-313] /c_addsub_1 A-DATA: Field type resolution: data = integer. /c_shift_ram_2 Q-DATA: data = null. /c_shift_ram_2 Q-DATA data field will be interpreted as integer
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_1 A_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_1 A_Type has been set to manual on the GUI. It will not be updated during validation with a propagated value.
WARNING: [xilinx.com:ip:c_addsub:12.0-313] /c_addsub_1 B-DATA: Field type resolution: data = integer. /c_shift_ram_3 Q-DATA: data = null. /c_shift_ram_3 Q-DATA data field will be interpreted as integer
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_1 B_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_1 B_Type has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:c_addsub:12.0-308] /c_addsub_1 A-DATA: Validating field: data(16:0): int16 against /c_shift_ram_2 Q-DATA: data(16:0): bit16.
WARNING: [xilinx.com:ip:c_addsub:12.0-313] /c_addsub_1 A-DATA: Field type resolution: data = integer. /c_shift_ram_2 Q-DATA: data = null. /c_shift_ram_2 Q-DATA data field will be interpreted as integer
INFO: [xilinx.com:ip:c_addsub:12.0-308] /c_addsub_1 B-DATA: Validating field: data(16:0): int16 against /c_shift_ram_3 Q-DATA: data(16:0): bit16.
WARNING: [xilinx.com:ip:c_addsub:12.0-313] /c_addsub_1 B-DATA: Field type resolution: data = integer. /c_shift_ram_3 Q-DATA: data = null. /c_shift_ram_3 Q-DATA data field will be interpreted as integer
WARNING: [BD 41-927] Following properties on pin /timemux_0/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
	CLK_DOMAIN=/clk_wiz_0_clk_out1 
WARNING: [BD 41-927] Following properties on pin /demux16_sync_0/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
	CLK_DOMAIN=/clk_wiz_0_clk_out1 
CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow.
Please check your design and connect them as needed: 
/energy_compare_0/t_finish

Wrote  : <D:\sound_location_project\energy\dat096-master-latest_version\latest_version\dat096_ref_design.srcs\sources_1\bd\pdm_to_pcm\pdm_to_pcm.bd> 
VHDL Output written to : D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/synth/pdm_to_pcm.vhd
VHDL Output written to : D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/sim/pdm_to_pcm.vhd
VHDL Output written to : D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.vhd
INFO: [BD 41-1029] Generation completed for the IP Integrator block cic_compiler_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block fir_compiler_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block fir_compiler_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block clk_wiz_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block fifo_generator_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block util_vector_logic_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block clk_div_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block util_ds_buf_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block clk_div_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block hp_filter_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block util_vector_logic_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block timemux_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block demux16_sync_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_addsub_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_addsub_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_addsub_2 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block blk_mem_gen_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block blk_mem_gen_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_shift_ram_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_shift_ram_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_shift_ram_2 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_shift_ram_3 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block blk_mem_gen_2 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block blk_mem_gen_3 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block scan_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block energy_compare_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block mult_gen_0 .
Exporting to file D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hw_handoff/pdm_to_pcm.hwh
Generated Block Design Tcl file D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hw_handoff/pdm_to_pcm_bd.tcl
Generated Hardware Definition File D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/synth/pdm_to_pcm.hwdef
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/clean_rst.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/decoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/encoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_constants.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_regs.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_test.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/timescale.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_an.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_mdio.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_rx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_sync.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_tx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/ddr/mig_interface_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/i2c/i2c_slave_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/micron/sdram/mobile_sdr.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/clean_rst.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/decoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/encoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_constants.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_regs.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_test.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/timescale.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_an.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_mdio.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_rx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_sync.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_tx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/ddr/mig_interface_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/i2c/i2c_slave_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/micron/sdram/mobile_sdr.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/clean_rst.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/decoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/encoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_constants.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_regs.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_test.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/timescale.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_an.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_mdio.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_rx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_sync.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_tx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/ddr/mig_interface_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/i2c/i2c_slave_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/micron/sdram/mobile_sdr.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/clean_rst.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/decoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/encoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_constants.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_regs.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_test.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/timescale.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_an.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_mdio.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_rx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_sync.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_tx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/ddr/mig_interface_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/i2c/i2c_slave_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/micron/sdram/mobile_sdr.v:]
[Mon May 25 21:56:34 2020] Launched pdm_to_pcm_demux16_sync_0_0_synth_1, synth_2...
Run output will be captured here:
pdm_to_pcm_demux16_sync_0_0_synth_1: D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.runs/pdm_to_pcm_demux16_sync_0_0_synth_1/runme.log
synth_2: D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.runs/synth_2/runme.log
[Mon May 25 21:56:35 2020] Launched impl_2...
Run output will be captured here: D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.runs/impl_2/runme.log
launch_runs: Time (s): cpu = 00:00:04 ; elapsed = 00:00:14 . Memory (MB): peak = 4744.703 ; gain = 0.000
create_ip_run [get_files -of_objects [get_fileset sources_1] D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/pdm_to_pcm.bd]
refresh_design
INFO: [Netlist 29-17] Analyzing 3499 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2019.1
INFO: [Project 1-570] Preparing netlist for logic optimization
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'masterrdwrgen.filter/pdm_to_pcm_i/clk_wiz_0/clk_in1' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
INFO: [Timing 38-478] Restoring timing data from binary archive.
INFO: [Timing 38-479] Binary timing data restore complete.
INFO: [Project 1-856] Restoring constraints from binary archive.
INFO: [Project 1-853] Binary constraint restore complete.
Reading XDEF placement.
Reading placer database...
Reading XDEF routing.
Read XDEF File: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 4744.703 ; gain = 0.000
Restored from archive | CPU: 6.000000 secs | Memory: 0.000000 MB |
Finished XDEF File Restore: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 4744.703 ; gain = 0.000
refresh_design: Time (s): cpu = 00:00:29 ; elapsed = 00:00:26 . Memory (MB): peak = 4744.703 ; gain = 0.000
open_report: Time (s): cpu = 00:00:26 ; elapsed = 00:00:15 . Memory (MB): peak = 4744.703 ; gain = 0.000
CRITICAL WARNING: [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.
WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met.
open_bd_design {D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/pdm_to_pcm.bd}
open_bd_design {D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/pdm_to_pcm.bd}
report_timing -from [get_clocks -of_objects [get_pins masterrdwrgen.filter/pdm_to_pcm_i/clk_div_1/U0/BUFR_inst/O]] -to [get_clocks -of_objects [get_pins mig_gen.gen_mig.ddrc/gen_mig.MCB_inst/u_mig_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT]] -delay_type min_max -max_paths 10 -sort_by group -input_pins -routable_nets -name timing_1
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
INFO: [Timing 38-78] ReportTimingParams: -from_pins  -to_pins  -max_paths 10 -nworst 1 -delay_type min_max -sort_by group.
WARNING: [Timing 38-164] This design has multiple clocks. Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
WARNING: [Timing 38-127] No common period was found between clocks Net {rise@0ns fall@108.507ns period=217.014ns} and clk_pll_i {rise@0ns fall@5ns period=10ns} in 1000 cycles.
report_timing: Time (s): cpu = 00:00:18 ; elapsed = 00:00:09 . Memory (MB): peak = 4744.703 ; gain = 0.000
open_bd_design {D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/pdm_to_pcm.bd}
report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -routable_nets -name timing_2
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met.
report_timing_summary: Time (s): cpu = 00:00:13 ; elapsed = 00:00:08 . Memory (MB): peak = 4744.703 ; gain = 0.000
open_bd_design {D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/pdm_to_pcm.bd}
update_module_reference pdm_to_pcm_energy_compare_0_0
INFO: [IP_Flow 19-5107] Inferred bus interface 'rst' of definition 'xilinx.com:signal:reset:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-4728] Bus Interface 'clk': Added interface parameter 'ASSOCIATED_RESET' with value 'rst'.
WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing.
INFO: [IP_Flow 19-234] Refreshing IP repositories
WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'd:/sound_location_project/energy/dat096-master-latest_version/sound_location_project'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
Upgrading 'D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/pdm_to_pcm.bd'
INFO: [IP_Flow 19-3420] Updated pdm_to_pcm_energy_compare_0_0 to use current project options
WARNING: [BD 41-1731] Type mismatch between connected pins: /clk_div_1/clk_out(undef) and /energy_compare_0_upgraded_ipi/clk(clk)
Wrote  : <D:\sound_location_project\energy\dat096-master-latest_version\latest_version\dat096_ref_design.srcs\sources_1\bd\pdm_to_pcm\pdm_to_pcm.bd> 
Wrote  : <D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ui/bd_8ec0abfc.ui> 
update_module_reference: Time (s): cpu = 00:00:03 ; elapsed = 00:00:08 . Memory (MB): peak = 4744.703 ; gain = 0.000
startgroup
set_property -dict [list CONFIG.Input_Depth {8192} CONFIG.Output_Depth {8192} CONFIG.Data_Count_Width {13} CONFIG.Write_Data_Count_Width {13} CONFIG.Read_Data_Count_Width {13} CONFIG.Full_Threshold_Assert_Value {8191} CONFIG.Full_Threshold_Negate_Value {8190}] [get_bd_cells fifo_generator_0]
INFO: [xilinx.com:ip:fifo_generator:13.2-5968] /fifo_generator_0Executing the post_config_ip from bd
endgroup
update_module_reference pdm_to_pcm_demux16_sync_0_0
INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing.
INFO: [IP_Flow 19-234] Refreshing IP repositories
WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'd:/sound_location_project/energy/dat096-master-latest_version/sound_location_project'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
Upgrading 'D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/pdm_to_pcm.bd'
INFO: [IP_Flow 19-3420] Updated pdm_to_pcm_demux16_sync_0_0 to use current project options
Wrote  : <D:\sound_location_project\energy\dat096-master-latest_version\latest_version\dat096_ref_design.srcs\sources_1\bd\pdm_to_pcm\pdm_to_pcm.bd> 
Wrote  : <D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ui/bd_8ec0abfc.ui> 
update_module_reference: Time (s): cpu = 00:00:05 ; elapsed = 00:00:16 . Memory (MB): peak = 4744.703 ; gain = 0.000
update_module_reference pdm_to_pcm_demux16_sync_0_0
INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing.
INFO: [IP_Flow 19-234] Refreshing IP repositories
WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'd:/sound_location_project/energy/dat096-master-latest_version/sound_location_project'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
Upgrading 'D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/pdm_to_pcm.bd'
INFO: [IP_Flow 19-3420] Updated pdm_to_pcm_demux16_sync_0_0 to use current project options
Wrote  : <D:\sound_location_project\energy\dat096-master-latest_version\latest_version\dat096_ref_design.srcs\sources_1\bd\pdm_to_pcm\pdm_to_pcm.bd> 
reset_run pdm_to_pcm_fifo_generator_0_0_synth_1
reset_run synth_2
launch_runs impl_2 -jobs 4
WARNING: [BD 41-2180] Resetting the memory initialization file of </blk_mem_gen_0> to default.
WARNING: [BD 41-2180] Resetting the memory initialization file of </blk_mem_gen_3> to default.
WARNING: [BD 41-2180] Resetting the memory initialization file of </blk_mem_gen_1> to default.
WARNING: [BD 41-2180] Resetting the memory initialization file of </blk_mem_gen_2> to default.
INFO: [xilinx.com:ip:fir_compiler:7.2-913] /fir_compiler_1 Data_Sign has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:fir_compiler:7.2-913] /fir_compiler_1 Data_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:fir_compiler:7.2-913] /fir_compiler_1 Data_Fractional_Bits has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:cic_compiler:4.0-913] /cic_compiler_0 Input_Data_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:fir_compiler:7.2-913] /fir_compiler_0 Data_Sign has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:fir_compiler:7.2-913] /fir_compiler_0 Data_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:fir_compiler:7.2-913] /fir_compiler_0 Data_Fractional_Bits has been set to manual on the GUI. It will not be updated during validation with a propagated value.
WARNING: [xilinx.com:ip:c_addsub:12.0-313] /c_addsub_0 A-DATA: Field type resolution: data = integer. /c_shift_ram_0 Q-DATA: data = null. /c_shift_ram_0 Q-DATA data field will be interpreted as integer
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_0 A_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_0 A_Type has been set to manual on the GUI. It will not be updated during validation with a propagated value.
WARNING: [xilinx.com:ip:c_addsub:12.0-313] /c_addsub_0 B-DATA: Field type resolution: data = integer. /c_shift_ram_1 Q-DATA: data = null. /c_shift_ram_1 Q-DATA data field will be interpreted as integer
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_0 B_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_0 B_Type has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:c_addsub:12.0-308] /c_addsub_0 A-DATA: Validating field: data(16:0): int16 against /c_shift_ram_0 Q-DATA: data(16:0): bit16.
WARNING: [xilinx.com:ip:c_addsub:12.0-313] /c_addsub_0 A-DATA: Field type resolution: data = integer. /c_shift_ram_0 Q-DATA: data = null. /c_shift_ram_0 Q-DATA data field will be interpreted as integer
INFO: [xilinx.com:ip:c_addsub:12.0-308] /c_addsub_0 B-DATA: Validating field: data(16:0): int16 against /c_shift_ram_1 Q-DATA: data(16:0): bit16.
WARNING: [xilinx.com:ip:c_addsub:12.0-313] /c_addsub_0 B-DATA: Field type resolution: data = integer. /c_shift_ram_1 Q-DATA: data = null. /c_shift_ram_1 Q-DATA data field will be interpreted as integer
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_2 A_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_2 A_Type has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_2 B_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_2 B_Type has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:mult_gen:12.0-913] /mult_gen_0 PortAType has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:mult_gen:12.0-913] /mult_gen_0 PortBType has been set to manual on the GUI. It will not be updated during validation with a propagated value.
WARNING: [xilinx.com:ip:c_addsub:12.0-313] /c_addsub_1 A-DATA: Field type resolution: data = integer. /c_shift_ram_2 Q-DATA: data = null. /c_shift_ram_2 Q-DATA data field will be interpreted as integer
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_1 A_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_1 A_Type has been set to manual on the GUI. It will not be updated during validation with a propagated value.
WARNING: [xilinx.com:ip:c_addsub:12.0-313] /c_addsub_1 B-DATA: Field type resolution: data = integer. /c_shift_ram_3 Q-DATA: data = null. /c_shift_ram_3 Q-DATA data field will be interpreted as integer
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_1 B_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_1 B_Type has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:c_addsub:12.0-308] /c_addsub_1 A-DATA: Validating field: data(16:0): int16 against /c_shift_ram_2 Q-DATA: data(16:0): bit16.
WARNING: [xilinx.com:ip:c_addsub:12.0-313] /c_addsub_1 A-DATA: Field type resolution: data = integer. /c_shift_ram_2 Q-DATA: data = null. /c_shift_ram_2 Q-DATA data field will be interpreted as integer
INFO: [xilinx.com:ip:c_addsub:12.0-308] /c_addsub_1 B-DATA: Validating field: data(16:0): int16 against /c_shift_ram_3 Q-DATA: data(16:0): bit16.
WARNING: [xilinx.com:ip:c_addsub:12.0-313] /c_addsub_1 B-DATA: Field type resolution: data = integer. /c_shift_ram_3 Q-DATA: data = null. /c_shift_ram_3 Q-DATA data field will be interpreted as integer
WARNING: [BD 41-927] Following properties on pin /timemux_0/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
	CLK_DOMAIN=/clk_wiz_0_clk_out1 
WARNING: [BD 41-927] Following properties on pin /demux16_sync_0/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
	CLK_DOMAIN=/clk_wiz_0_clk_out1 
CRITICAL WARNING: [BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified. These pins are tied-off to all 0's to avoid error in Implementation flow.
Please check your design and connect them as needed: 
/energy_compare_0/t_finish

Wrote  : <D:\sound_location_project\energy\dat096-master-latest_version\latest_version\dat096_ref_design.srcs\sources_1\bd\pdm_to_pcm\pdm_to_pcm.bd> 
VHDL Output written to : D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/synth/pdm_to_pcm.vhd
VHDL Output written to : D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/sim/pdm_to_pcm.vhd
VHDL Output written to : D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.vhd
INFO: [BD 41-1029] Generation completed for the IP Integrator block cic_compiler_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block fir_compiler_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block fir_compiler_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block clk_wiz_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block fifo_generator_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block util_vector_logic_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block clk_div_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block util_ds_buf_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block clk_div_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block hp_filter_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block util_vector_logic_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block timemux_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block demux16_sync_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_addsub_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_addsub_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_addsub_2 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block blk_mem_gen_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block blk_mem_gen_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_shift_ram_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_shift_ram_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_shift_ram_2 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_shift_ram_3 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block blk_mem_gen_2 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block blk_mem_gen_3 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block scan_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block energy_compare_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block mult_gen_0 .
Exporting to file D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hw_handoff/pdm_to_pcm.hwh
Generated Block Design Tcl file D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hw_handoff/pdm_to_pcm_bd.tcl
Generated Hardware Definition File D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/synth/pdm_to_pcm.hwdef
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/clean_rst.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/decoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/encoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_constants.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_regs.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_test.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/timescale.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_an.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_mdio.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_rx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_sync.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_tx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/ddr/mig_interface_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/i2c/i2c_slave_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/micron/sdram/mobile_sdr.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/clean_rst.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/decoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/encoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_constants.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_regs.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_test.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/timescale.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_an.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_mdio.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_rx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_sync.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_tx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/ddr/mig_interface_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/i2c/i2c_slave_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/micron/sdram/mobile_sdr.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/clean_rst.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/decoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/encoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_constants.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_regs.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_test.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/timescale.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_an.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_mdio.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_rx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_sync.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_tx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/ddr/mig_interface_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/i2c/i2c_slave_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/micron/sdram/mobile_sdr.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/clean_rst.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/decoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/encoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_constants.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_regs.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_test.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/timescale.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_an.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_mdio.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_rx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_sync.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_tx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/ddr/mig_interface_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/i2c/i2c_slave_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/micron/sdram/mobile_sdr.v:]
[Mon May 25 23:38:30 2020] Launched pdm_to_pcm_fifo_generator_0_0_synth_1, pdm_to_pcm_demux16_sync_0_0_synth_1, pdm_to_pcm_energy_compare_0_0_synth_1, synth_2...
Run output will be captured here:
pdm_to_pcm_fifo_generator_0_0_synth_1: D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.runs/pdm_to_pcm_fifo_generator_0_0_synth_1/runme.log
pdm_to_pcm_demux16_sync_0_0_synth_1: D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.runs/pdm_to_pcm_demux16_sync_0_0_synth_1/runme.log
pdm_to_pcm_energy_compare_0_0_synth_1: D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.runs/pdm_to_pcm_energy_compare_0_0_synth_1/runme.log
synth_2: D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.runs/synth_2/runme.log
[Mon May 25 23:38:31 2020] Launched impl_2...
Run output will be captured here: D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.runs/impl_2/runme.log
launch_runs: Time (s): cpu = 00:00:07 ; elapsed = 00:00:26 . Memory (MB): peak = 4744.703 ; gain = 0.000
create_ip_run [get_files -of_objects [get_fileset sources_1] D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/pdm_to_pcm.bd]
refresh_design
INFO: [Netlist 29-17] Analyzing 3484 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2019.1
INFO: [Project 1-570] Preparing netlist for logic optimization
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'masterrdwrgen.filter/pdm_to_pcm_i/clk_wiz_0/clk_in1' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
INFO: [Timing 38-478] Restoring timing data from binary archive.
INFO: [Timing 38-479] Binary timing data restore complete.
INFO: [Project 1-856] Restoring constraints from binary archive.
INFO: [Project 1-853] Binary constraint restore complete.
Reading XDEF placement.
Reading placer database...
Reading XDEF routing.
Read XDEF File: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 4805.980 ; gain = 0.000
Restored from archive | CPU: 5.000000 secs | Memory: 0.000000 MB |
Finished XDEF File Restore: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 4805.980 ; gain = 0.000
refresh_design: Time (s): cpu = 00:00:36 ; elapsed = 00:00:37 . Memory (MB): peak = 4805.980 ; gain = 61.277
open_report: Time (s): cpu = 00:00:25 ; elapsed = 00:00:16 . Memory (MB): peak = 4805.980 ; gain = 0.000
CRITICAL WARNING: [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.
WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met.
open_run synth_2 -name synth_2
Design is defaulting to impl run constrset: constrs_1
Design is defaulting to synth run part: xc7a200tfbg676-2
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_blk_mem_gen_0_0/pdm_to_pcm_blk_mem_gen_0_0.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/blk_mem_gen_0'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_blk_mem_gen_1_0/pdm_to_pcm_blk_mem_gen_1_0.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/blk_mem_gen_1'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_blk_mem_gen_1_1/pdm_to_pcm_blk_mem_gen_1_1.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/blk_mem_gen_2'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_blk_mem_gen_2_0/pdm_to_pcm_blk_mem_gen_2_0.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/blk_mem_gen_3'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_c_addsub_0_0/pdm_to_pcm_c_addsub_0_0.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/c_addsub_0'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_c_addsub_0_1/pdm_to_pcm_c_addsub_0_1.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/c_addsub_1'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_c_addsub_1_0/pdm_to_pcm_c_addsub_1_0.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/c_addsub_2'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_c_shift_ram_0_0/pdm_to_pcm_c_shift_ram_0_0.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/c_shift_ram_0'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_c_shift_ram_1_0/pdm_to_pcm_c_shift_ram_1_0.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/c_shift_ram_1'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_c_shift_ram_1_1/pdm_to_pcm_c_shift_ram_1_1.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/c_shift_ram_2'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_c_shift_ram_1_2/pdm_to_pcm_c_shift_ram_1_2.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/c_shift_ram_3'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_cic_compiler_0_0/pdm_to_pcm_cic_compiler_0_0.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/cic_compiler_0'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_clk_div_0_0/pdm_to_pcm_clk_div_0_0.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/clk_div_0'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_clk_div_1_0/pdm_to_pcm_clk_div_1_0.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/clk_div_1'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_clk_wiz_0_0/pdm_to_pcm_clk_wiz_0_0.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/clk_wiz_0'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_demux16_sync_0_0/pdm_to_pcm_demux16_sync_0_0.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/demux16_sync_0'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_energy_compare_0_0/pdm_to_pcm_energy_compare_0_0.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/energy_compare_0'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_fifo_generator_0_0/pdm_to_pcm_fifo_generator_0_0.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/fifo_generator_0'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_fir_compiler_0_0/pdm_to_pcm_fir_compiler_0_0.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/fir_compiler_0'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_fir_compiler_1_0/pdm_to_pcm_fir_compiler_1_0.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/fir_compiler_1'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_hp_filter_0_0/pdm_to_pcm_hp_filter_0_0.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/hp_filter_0'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_mult_gen_0_0/pdm_to_pcm_mult_gen_0_0.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/mult_gen_0'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_scan_0_0/pdm_to_pcm_scan_0_0.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/scan_0'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_timemux_0_2/pdm_to_pcm_timemux_0_2.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/timemux_0'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_util_ds_buf_0_0/pdm_to_pcm_util_ds_buf_0_0.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/util_ds_buf_0'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_util_vector_logic_0_0/pdm_to_pcm_util_vector_logic_0_0.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/util_vector_logic_0'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_util_vector_logic_0_2/pdm_to_pcm_util_vector_logic_0_2.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/util_vector_logic_1'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/ip/mig/mig.dcp' for cell 'mig_gen.gen_mig.ddrc/gen_mig.MCB_inst'
INFO: [Netlist 29-17] Analyzing 3493 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2019.1
INFO: [Project 1-570] Preparing netlist for logic optimization
WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. masterrdwrgen.filter/pdm_to_pcm_i/clk_wiz_0/inst/clkin1_ibufg 
Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'masterrdwrgen.filter/pdm_to_pcm_i/clk_wiz_0/clk_in1' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_fir_compiler_0_0/constraints/fir_compiler_v7_2.xdc] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/fir_compiler_0/U0'
Finished Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_fir_compiler_0_0/constraints/fir_compiler_v7_2.xdc] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/fir_compiler_0/U0'
Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_fir_compiler_1_0/constraints/fir_compiler_v7_2.xdc] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/fir_compiler_1/U0'
Finished Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_fir_compiler_1_0/constraints/fir_compiler_v7_2.xdc] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/fir_compiler_1/U0'
Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_clk_wiz_0_0/pdm_to_pcm_clk_wiz_0_0_board.xdc] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/clk_wiz_0/inst'
Finished Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_clk_wiz_0_0/pdm_to_pcm_clk_wiz_0_0_board.xdc] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/clk_wiz_0/inst'
Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_clk_wiz_0_0/pdm_to_pcm_clk_wiz_0_0.xdc] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/clk_wiz_0/inst'
INFO: [Timing 38-35] Done setting XDC timing constraints. [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_clk_wiz_0_0/pdm_to_pcm_clk_wiz_0_0.xdc:57]
INFO: [Timing 38-2] Deriving generated clocks [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_clk_wiz_0_0/pdm_to_pcm_clk_wiz_0_0.xdc:57]
Finished Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_clk_wiz_0_0/pdm_to_pcm_clk_wiz_0_0.xdc] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/clk_wiz_0/inst'
Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_fifo_generator_0_0/pdm_to_pcm_fifo_generator_0_0.xdc] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/fifo_generator_0/U0'
Finished Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_fifo_generator_0_0/pdm_to_pcm_fifo_generator_0_0.xdc] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/fifo_generator_0/U0'
Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_util_ds_buf_0_0/pdm_to_pcm_util_ds_buf_0_0_board.xdc] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/util_ds_buf_0/U0'
Finished Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_util_ds_buf_0_0/pdm_to_pcm_util_ds_buf_0_0_board.xdc] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/util_ds_buf_0/U0'
Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/constraints/mig.xdc] for cell 'mig_gen.gen_mig.ddrc/gen_mig.MCB_inst'
Finished Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/constraints/mig.xdc] for cell 'mig_gen.gen_mig.ddrc/gen_mig.MCB_inst'
Parsing XDC File [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc]
CRITICAL WARNING: [Constraints 18-1056] Clock 'clk200' completely overrides clock 'clk200p'.
New: create_clock -period 5.000 -name clk200 [get_ports clk200p], [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:2]
Previous: create_clock -period 5.000 [get_ports clk200p], [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/constraints/mig.xdc:30]
Resolution: Review the constraint files and remove the redundant clock definition(s). If the clock constraints are not saved in a file, you can first save the constraints to an XDC file and reload the design once the constraints have been corrected.
INFO: [Timing 38-2] Deriving generated clocks [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:12]
WARNING: [Vivado 12-627] No clocks matched 'clk_div_1_clk_out'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:12]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:12]
CRITICAL WARNING: [Vivado 12-4739] set_false_path:No valid object(s) found for '-from [get_clocks clk_div_1_clk_out]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:12]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:15]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:15]
CRITICAL WARNING: [Vivado 12-4739] set_input_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:15]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:17]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:17]
CRITICAL WARNING: [Vivado 12-4739] set_input_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:17]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:18]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:18]
CRITICAL WARNING: [Vivado 12-4739] set_output_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:18]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:21]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:21]
CRITICAL WARNING: [Vivado 12-4739] set_input_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:21]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:22]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:22]
CRITICAL WARNING: [Vivado 12-4739] set_output_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:22]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:23]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:23]
CRITICAL WARNING: [Vivado 12-4739] set_input_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:23]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:24]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:24]
CRITICAL WARNING: [Vivado 12-4739] set_output_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:24]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:28]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:28]
CRITICAL WARNING: [Vivado 12-4739] set_input_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:28]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:29]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:29]
CRITICAL WARNING: [Vivado 12-4739] set_input_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:29]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:30]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:30]
CRITICAL WARNING: [Vivado 12-4739] set_input_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:30]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:31]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:31]
CRITICAL WARNING: [Vivado 12-4739] set_input_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:31]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:34]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:34]
CRITICAL WARNING: [Vivado 12-4739] set_output_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:34]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:35]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:35]
CRITICAL WARNING: [Vivado 12-4739] set_output_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:35]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:36]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:36]
CRITICAL WARNING: [Vivado 12-4739] set_output_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:36]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:37]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:37]
CRITICAL WARNING: [Vivado 12-4739] set_output_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:37]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:44]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:44]
CRITICAL WARNING: [Vivado 12-4739] set_input_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:44]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:45]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:45]
CRITICAL WARNING: [Vivado 12-4739] set_input_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:45]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:46]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:46]
CRITICAL WARNING: [Vivado 12-4739] set_output_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:46]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:47]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:47]
CRITICAL WARNING: [Vivado 12-4739] set_output_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:47]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:48]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:48]
CRITICAL WARNING: [Vivado 12-4739] set_input_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:48]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:49]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:49]
CRITICAL WARNING: [Vivado 12-4739] set_input_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:49]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:50]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:50]
CRITICAL WARNING: [Vivado 12-4739] set_output_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:50]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:51]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:51]
CRITICAL WARNING: [Vivado 12-4739] set_output_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:51]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
INFO: [Timing 38-2] Deriving generated clocks [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:113]
WARNING: [Vivado 12-627] No clocks matched 'rgmii_tx_clk'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:140]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:140]
CRITICAL WARNING: [Vivado 12-4739] set_output_delay:No valid object(s) found for '-clock [get_clocks rgmii_tx_clk]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:140]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'rgmii_tx_clk'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:141]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:141]
CRITICAL WARNING: [Vivado 12-4739] set_output_delay:No valid object(s) found for '-clock [get_clocks rgmii_tx_clk]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:141]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'rgmii_tx_clk'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:142]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:142]
CRITICAL WARNING: [Vivado 12-4739] set_output_delay:No valid object(s) found for '-clock [get_clocks rgmii_tx_clk]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:142]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'rgmii_tx_clk'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:143]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:143]
CRITICAL WARNING: [Vivado 12-4739] set_output_delay:No valid object(s) found for '-clock [get_clocks rgmii_tx_clk]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:143]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:156]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:156]
CRITICAL WARNING: [Vivado 12-4739] set_input_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:156]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:157]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:157]
CRITICAL WARNING: [Vivado 12-4739] set_input_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:157]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:158]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:158]
CRITICAL WARNING: [Vivado 12-4739] set_output_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:158]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:159]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:159]
CRITICAL WARNING: [Vivado 12-4739] set_output_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:159]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:162]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:162]
CRITICAL WARNING: [Vivado 12-4739] set_output_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:162]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:163]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:163]
CRITICAL WARNING: [Vivado 12-4739] set_output_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:163]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-180] No cells matched 'eth1.*delay_rgmii*'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:181]
WARNING: [Vivado 12-180] No cells matched 'eth1.*.*delay_rgmii*'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:181]
WARNING: [Vivado 12-180] No cells matched 'eth1.*.*.*delay_rgmii*'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:181]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:181]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-627] No clocks matched 'clk50*'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:200]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:200]
CRITICAL WARNING: [Vivado 12-4739] set_false_path:No valid object(s) found for '-to [get_clocks clk50*]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:200]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'clk50*'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:201]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:201]
CRITICAL WARNING: [Vivado 12-4739] set_false_path:No valid object(s) found for '-from [get_clocks clk50*]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:201]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
Finished Parsing XDC File [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc]
Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_fifo_generator_0_0/pdm_to_pcm_fifo_generator_0_0_clocks.xdc] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/fifo_generator_0/U0'
Finished Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_fifo_generator_0_0/pdm_to_pcm_fifo_generator_0_0_clocks.xdc] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/fifo_generator_0/U0'
Sourcing Tcl File [C:/xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/fifo_generator_0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Finished Sourcing Tcl File [C:/xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/fifo_generator_0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Sourcing Tcl File [C:/xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/fifo_generator_0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Finished Sourcing Tcl File [C:/xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/fifo_generator_0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.019 . Memory (MB): peak = 5125.813 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 491 instances were transformed.
  IOBUF => IOBUF (IBUF, OBUFT): 8 instances
  IOBUFDS_DIFF_OUT_INTERMDISABLE => IOBUFDS_DIFF_OUT_INTERMDISABLE (IBUFDS_INTERMDISABLE_INT, IBUFDS_INTERMDISABLE_INT, INV, OBUFTDS, OBUFTDS): 8 instances
  IOBUF_INTERMDISABLE => IOBUF_INTERMDISABLE (IBUF_INTERMDISABLE, OBUFT): 64 instances
  OBUFDS => OBUFDS_DUAL_BUF (INV, OBUFDS, OBUFDS): 1 instances
  RAM16X1D => RAM32X1D (RAMD32, RAMD32): 45 instances
  RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 343 instances
  RAM32X1D => RAM32X1D (RAMD32, RAMD32): 22 instances

open_run: Time (s): cpu = 00:00:44 ; elapsed = 00:00:38 . Memory (MB): peak = 5125.813 ; gain = 319.832
file mkdir D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/new
close [ open D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/new/constr_synth.xdc w ]
add_files -fileset constrs_1 D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/new/constr_synth.xdc
set_property target_constrs_file D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/new/constr_synth.xdc [current_fileset -constrset]
create_ip_run [get_files -of_objects [get_fileset sources_1] D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/pdm_to_pcm.bd]
refresh_design
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_fir_compiler_0_0/constraints/fir_compiler_v7_2.xdc] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/fir_compiler_0/U0'
Finished Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_fir_compiler_0_0/constraints/fir_compiler_v7_2.xdc] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/fir_compiler_0/U0'
Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_fir_compiler_1_0/constraints/fir_compiler_v7_2.xdc] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/fir_compiler_1/U0'
Finished Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_fir_compiler_1_0/constraints/fir_compiler_v7_2.xdc] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/fir_compiler_1/U0'
Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_clk_wiz_0_0/pdm_to_pcm_clk_wiz_0_0_board.xdc] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/clk_wiz_0/inst'
Finished Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_clk_wiz_0_0/pdm_to_pcm_clk_wiz_0_0_board.xdc] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/clk_wiz_0/inst'
Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_clk_wiz_0_0/pdm_to_pcm_clk_wiz_0_0.xdc] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/clk_wiz_0/inst'
INFO: [Timing 38-35] Done setting XDC timing constraints. [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_clk_wiz_0_0/pdm_to_pcm_clk_wiz_0_0.xdc:57]
INFO: [Timing 38-2] Deriving generated clocks [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_clk_wiz_0_0/pdm_to_pcm_clk_wiz_0_0.xdc:57]
Finished Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_clk_wiz_0_0/pdm_to_pcm_clk_wiz_0_0.xdc] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/clk_wiz_0/inst'
Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_fifo_generator_0_0/pdm_to_pcm_fifo_generator_0_0.xdc] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/fifo_generator_0/U0'
Finished Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_fifo_generator_0_0/pdm_to_pcm_fifo_generator_0_0.xdc] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/fifo_generator_0/U0'
Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_util_ds_buf_0_0/pdm_to_pcm_util_ds_buf_0_0_board.xdc] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/util_ds_buf_0/U0'
Finished Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_util_ds_buf_0_0/pdm_to_pcm_util_ds_buf_0_0_board.xdc] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/util_ds_buf_0/U0'
Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/constraints/mig.xdc] for cell 'mig_gen.gen_mig.ddrc/gen_mig.MCB_inst'
Finished Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/constraints/mig.xdc] for cell 'mig_gen.gen_mig.ddrc/gen_mig.MCB_inst'
Parsing XDC File [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc]
CRITICAL WARNING: [Constraints 18-1056] Clock 'clk200' completely overrides clock 'clk200p'.
New: create_clock -period 5.000 -name clk200 [get_ports clk200p], [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:2]
Previous: create_clock -period 5.000 [get_ports clk200p], [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/constraints/mig.xdc:30]
Resolution: Review the constraint files and remove the redundant clock definition(s). If the clock constraints are not saved in a file, you can first save the constraints to an XDC file and reload the design once the constraints have been corrected.
INFO: [Timing 38-2] Deriving generated clocks [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:12]
WARNING: [Vivado 12-627] No clocks matched 'clk_div_1_clk_out'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:12]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:12]
CRITICAL WARNING: [Vivado 12-4739] set_false_path:No valid object(s) found for '-from [get_clocks clk_div_1_clk_out]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:12]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:15]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:15]
CRITICAL WARNING: [Vivado 12-4739] set_input_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:15]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:17]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:17]
CRITICAL WARNING: [Vivado 12-4739] set_input_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:17]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:18]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:18]
CRITICAL WARNING: [Vivado 12-4739] set_output_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:18]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:21]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:21]
CRITICAL WARNING: [Vivado 12-4739] set_input_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:21]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:22]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:22]
CRITICAL WARNING: [Vivado 12-4739] set_output_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:22]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:23]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:23]
CRITICAL WARNING: [Vivado 12-4739] set_input_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:23]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:24]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:24]
CRITICAL WARNING: [Vivado 12-4739] set_output_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:24]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:28]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:28]
CRITICAL WARNING: [Vivado 12-4739] set_input_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:28]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:29]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:29]
CRITICAL WARNING: [Vivado 12-4739] set_input_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:29]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:30]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:30]
CRITICAL WARNING: [Vivado 12-4739] set_input_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:30]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:31]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:31]
CRITICAL WARNING: [Vivado 12-4739] set_input_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:31]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:34]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:34]
CRITICAL WARNING: [Vivado 12-4739] set_output_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:34]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:35]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:35]
CRITICAL WARNING: [Vivado 12-4739] set_output_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:35]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:36]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:36]
CRITICAL WARNING: [Vivado 12-4739] set_output_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:36]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:37]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:37]
CRITICAL WARNING: [Vivado 12-4739] set_output_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:37]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:44]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:44]
CRITICAL WARNING: [Vivado 12-4739] set_input_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:44]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:45]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:45]
CRITICAL WARNING: [Vivado 12-4739] set_input_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:45]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:46]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:46]
CRITICAL WARNING: [Vivado 12-4739] set_output_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:46]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:47]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:47]
CRITICAL WARNING: [Vivado 12-4739] set_output_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:47]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:48]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:48]
CRITICAL WARNING: [Vivado 12-4739] set_input_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:48]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:49]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:49]
CRITICAL WARNING: [Vivado 12-4739] set_input_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:49]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:50]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:50]
CRITICAL WARNING: [Vivado 12-4739] set_output_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:50]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:51]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:51]
CRITICAL WARNING: [Vivado 12-4739] set_output_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:51]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
INFO: [Timing 38-2] Deriving generated clocks [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:113]
WARNING: [Vivado 12-627] No clocks matched 'rgmii_tx_clk'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:140]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:140]
CRITICAL WARNING: [Vivado 12-4739] set_output_delay:No valid object(s) found for '-clock [get_clocks rgmii_tx_clk]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:140]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'rgmii_tx_clk'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:141]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:141]
CRITICAL WARNING: [Vivado 12-4739] set_output_delay:No valid object(s) found for '-clock [get_clocks rgmii_tx_clk]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:141]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'rgmii_tx_clk'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:142]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:142]
CRITICAL WARNING: [Vivado 12-4739] set_output_delay:No valid object(s) found for '-clock [get_clocks rgmii_tx_clk]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:142]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'rgmii_tx_clk'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:143]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:143]
CRITICAL WARNING: [Vivado 12-4739] set_output_delay:No valid object(s) found for '-clock [get_clocks rgmii_tx_clk]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:143]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:156]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:156]
CRITICAL WARNING: [Vivado 12-4739] set_input_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:156]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:157]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:157]
CRITICAL WARNING: [Vivado 12-4739] set_input_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:157]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:158]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:158]
CRITICAL WARNING: [Vivado 12-4739] set_output_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:158]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:159]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:159]
CRITICAL WARNING: [Vivado 12-4739] set_output_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:159]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:162]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:162]
CRITICAL WARNING: [Vivado 12-4739] set_output_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:162]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:163]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:163]
CRITICAL WARNING: [Vivado 12-4739] set_output_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:163]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-180] No cells matched 'eth1.*delay_rgmii*'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:181]
WARNING: [Vivado 12-180] No cells matched 'eth1.*.*delay_rgmii*'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:181]
WARNING: [Vivado 12-180] No cells matched 'eth1.*.*.*delay_rgmii*'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:181]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:181]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-627] No clocks matched 'clk50*'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:200]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:200]
CRITICAL WARNING: [Vivado 12-4739] set_false_path:No valid object(s) found for '-to [get_clocks clk50*]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:200]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'clk50*'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:201]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:201]
CRITICAL WARNING: [Vivado 12-4739] set_false_path:No valid object(s) found for '-from [get_clocks clk50*]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:201]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
Finished Parsing XDC File [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc]
Parsing XDC File [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/new/constr_synth.xdc]
Finished Parsing XDC File [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/new/constr_synth.xdc]
Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_fifo_generator_0_0/pdm_to_pcm_fifo_generator_0_0_clocks.xdc] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/fifo_generator_0/U0'
Finished Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_fifo_generator_0_0/pdm_to_pcm_fifo_generator_0_0_clocks.xdc] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/fifo_generator_0/U0'
Sourcing Tcl File [C:/xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/fifo_generator_0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Finished Sourcing Tcl File [C:/xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/fifo_generator_0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Sourcing Tcl File [C:/xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/fifo_generator_0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Finished Sourcing Tcl File [C:/xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/fifo_generator_0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
refresh_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:25 . Memory (MB): peak = 5217.047 ; gain = 91.234
INFO: [Timing 38-35] Done setting XDC timing constraints.
report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -routable_nets -name timing_1
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met.
report_timing_summary: Time (s): cpu = 00:00:22 ; elapsed = 00:00:14 . Memory (MB): peak = 5617.930 ; gain = 58.559
current_design impl_2
report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -routable_nets -name timing_1
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met.
report_timing_summary: Time (s): cpu = 00:00:27 ; elapsed = 00:00:18 . Memory (MB): peak = 5704.277 ; gain = 73.066
report_clock_interaction -delay_type min_max -significant_digits 3 -name timing_2
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
WARNING: [Timing 38-164] This design has multiple clocks. Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
WARNING: [Timing 38-127] No common period was found between clocks Net {rise@0ns fall@108.507ns period=217.014ns} and clk_pll_i {rise@0ns fall@5ns period=10ns} in 1000 cycles.
open_bd_design {D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/pdm_to_pcm.bd}
current_design synth_2
export_ip_user_files -of_objects  [get_files D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/new/demux_16.vhd] -no_script -reset -force -quiet
remove_files  D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/new/demux_16.vhd
file delete -force D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/new/demux_16.vhd
open_bd_design {D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/pdm_to_pcm.bd}
update_module_reference pdm_to_pcm_demux16_sync_0_0
INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing.
INFO: [IP_Flow 19-234] Refreshing IP repositories
WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'd:/sound_location_project/energy/dat096-master-latest_version/sound_location_project'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
Upgrading 'D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/pdm_to_pcm.bd'
INFO: [IP_Flow 19-3420] Updated pdm_to_pcm_demux16_sync_0_0 to use current project options
Wrote  : <D:\sound_location_project\energy\dat096-master-latest_version\latest_version\dat096_ref_design.srcs\sources_1\bd\pdm_to_pcm\pdm_to_pcm.bd> 
update_module_reference pdm_to_pcm_energy_compare_0_0
INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing.
INFO: [IP_Flow 19-234] Refreshing IP repositories
WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'd:/sound_location_project/energy/dat096-master-latest_version/sound_location_project'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
Upgrading 'D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/pdm_to_pcm.bd'
INFO: [IP_Flow 19-3420] Updated pdm_to_pcm_energy_compare_0_0 to use current project options
WARNING: [IP_Flow 19-4699] Upgrade has removed interface 'rst'
WARNING: [IP_Flow 19-3670] Detected external interface differences while upgrading 'pdm_to_pcm_energy_compare_0_0'.
WARNING: [IP_Flow 19-4700] Upgrade has removed port 'rst'
WARNING: [IP_Flow 19-4700] Upgrade has removed port 't_finish'
WARNING: [IP_Flow 19-3298] Detected external port differences while upgrading 'pdm_to_pcm_energy_compare_0_0'. These changes may impact your design.
WARNING: [BD 41-1731] Type mismatch between connected pins: /clk_div_1/clk_out(undef) and /energy_compare_0_upgraded_ipi/clk(clk)
CRITICAL WARNING: [Coretcl 2-1280] The upgrade of 'pdm_to_pcm_energy_compare_0_0' has identified issues that may require user intervention. Please verify that the instance is correctly configured, and review any upgrade messages.
Wrote  : <D:\sound_location_project\energy\dat096-master-latest_version\latest_version\dat096_ref_design.srcs\sources_1\bd\pdm_to_pcm\pdm_to_pcm.bd> 
Wrote  : <D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ui/bd_8ec0abfc.ui> 
update_module_reference: Time (s): cpu = 00:00:03 ; elapsed = 00:00:08 . Memory (MB): peak = 5804.164 ; gain = 9.938
reset_run synth_2
launch_runs impl_2 -jobs 6
WARNING: [BD 41-2180] Resetting the memory initialization file of </blk_mem_gen_0> to default.
WARNING: [BD 41-2180] Resetting the memory initialization file of </blk_mem_gen_3> to default.
WARNING: [BD 41-2180] Resetting the memory initialization file of </blk_mem_gen_1> to default.
WARNING: [BD 41-2180] Resetting the memory initialization file of </blk_mem_gen_2> to default.
INFO: [xilinx.com:ip:fir_compiler:7.2-913] /fir_compiler_1 Data_Sign has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:fir_compiler:7.2-913] /fir_compiler_1 Data_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:fir_compiler:7.2-913] /fir_compiler_1 Data_Fractional_Bits has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:cic_compiler:4.0-913] /cic_compiler_0 Input_Data_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:fir_compiler:7.2-913] /fir_compiler_0 Data_Sign has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:fir_compiler:7.2-913] /fir_compiler_0 Data_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:fir_compiler:7.2-913] /fir_compiler_0 Data_Fractional_Bits has been set to manual on the GUI. It will not be updated during validation with a propagated value.
WARNING: [xilinx.com:ip:c_addsub:12.0-313] /c_addsub_0 A-DATA: Field type resolution: data = integer. /c_shift_ram_0 Q-DATA: data = null. /c_shift_ram_0 Q-DATA data field will be interpreted as integer
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_0 A_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_0 A_Type has been set to manual on the GUI. It will not be updated during validation with a propagated value.
WARNING: [xilinx.com:ip:c_addsub:12.0-313] /c_addsub_0 B-DATA: Field type resolution: data = integer. /c_shift_ram_1 Q-DATA: data = null. /c_shift_ram_1 Q-DATA data field will be interpreted as integer
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_0 B_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_0 B_Type has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:c_addsub:12.0-308] /c_addsub_0 A-DATA: Validating field: data(16:0): int16 against /c_shift_ram_0 Q-DATA: data(16:0): bit16.
WARNING: [xilinx.com:ip:c_addsub:12.0-313] /c_addsub_0 A-DATA: Field type resolution: data = integer. /c_shift_ram_0 Q-DATA: data = null. /c_shift_ram_0 Q-DATA data field will be interpreted as integer
INFO: [xilinx.com:ip:c_addsub:12.0-308] /c_addsub_0 B-DATA: Validating field: data(16:0): int16 against /c_shift_ram_1 Q-DATA: data(16:0): bit16.
WARNING: [xilinx.com:ip:c_addsub:12.0-313] /c_addsub_0 B-DATA: Field type resolution: data = integer. /c_shift_ram_1 Q-DATA: data = null. /c_shift_ram_1 Q-DATA data field will be interpreted as integer
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_2 A_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_2 A_Type has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_2 B_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_2 B_Type has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:mult_gen:12.0-913] /mult_gen_0 PortAType has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:mult_gen:12.0-913] /mult_gen_0 PortBType has been set to manual on the GUI. It will not be updated during validation with a propagated value.
WARNING: [xilinx.com:ip:c_addsub:12.0-313] /c_addsub_1 A-DATA: Field type resolution: data = integer. /c_shift_ram_2 Q-DATA: data = null. /c_shift_ram_2 Q-DATA data field will be interpreted as integer
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_1 A_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_1 A_Type has been set to manual on the GUI. It will not be updated during validation with a propagated value.
WARNING: [xilinx.com:ip:c_addsub:12.0-313] /c_addsub_1 B-DATA: Field type resolution: data = integer. /c_shift_ram_3 Q-DATA: data = null. /c_shift_ram_3 Q-DATA data field will be interpreted as integer
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_1 B_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_1 B_Type has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:c_addsub:12.0-308] /c_addsub_1 A-DATA: Validating field: data(16:0): int16 against /c_shift_ram_2 Q-DATA: data(16:0): bit16.
WARNING: [xilinx.com:ip:c_addsub:12.0-313] /c_addsub_1 A-DATA: Field type resolution: data = integer. /c_shift_ram_2 Q-DATA: data = null. /c_shift_ram_2 Q-DATA data field will be interpreted as integer
INFO: [xilinx.com:ip:c_addsub:12.0-308] /c_addsub_1 B-DATA: Validating field: data(16:0): int16 against /c_shift_ram_3 Q-DATA: data(16:0): bit16.
WARNING: [xilinx.com:ip:c_addsub:12.0-313] /c_addsub_1 B-DATA: Field type resolution: data = integer. /c_shift_ram_3 Q-DATA: data = null. /c_shift_ram_3 Q-DATA data field will be interpreted as integer
WARNING: [BD 41-927] Following properties on pin /timemux_0/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
	CLK_DOMAIN=/clk_wiz_0_clk_out1 
WARNING: [BD 41-927] Following properties on pin /demux16_sync_0/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
	CLK_DOMAIN=/clk_wiz_0_clk_out1 
Wrote  : <D:\sound_location_project\energy\dat096-master-latest_version\latest_version\dat096_ref_design.srcs\sources_1\bd\pdm_to_pcm\pdm_to_pcm.bd> 
Wrote  : <D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ui/bd_8ec0abfc.ui> 
VHDL Output written to : D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/synth/pdm_to_pcm.vhd
VHDL Output written to : D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/sim/pdm_to_pcm.vhd
VHDL Output written to : D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.vhd
INFO: [BD 41-1029] Generation completed for the IP Integrator block cic_compiler_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block fir_compiler_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block fir_compiler_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block clk_wiz_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block fifo_generator_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block util_vector_logic_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block clk_div_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block util_ds_buf_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block clk_div_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block hp_filter_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block util_vector_logic_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block timemux_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block demux16_sync_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_addsub_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_addsub_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_addsub_2 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block blk_mem_gen_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block blk_mem_gen_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_shift_ram_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_shift_ram_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_shift_ram_2 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_shift_ram_3 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block blk_mem_gen_2 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block blk_mem_gen_3 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block scan_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block energy_compare_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block mult_gen_0 .
Exporting to file D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hw_handoff/pdm_to_pcm.hwh
Generated Block Design Tcl file D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hw_handoff/pdm_to_pcm_bd.tcl
Generated Hardware Definition File D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/synth/pdm_to_pcm.hwdef
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/clean_rst.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/decoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/encoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_constants.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_regs.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_test.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/timescale.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_an.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_mdio.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_rx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_sync.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_tx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/ddr/mig_interface_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/i2c/i2c_slave_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/micron/sdram/mobile_sdr.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/clean_rst.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/decoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/encoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_constants.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_regs.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_test.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/timescale.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_an.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_mdio.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_rx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_sync.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_tx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/ddr/mig_interface_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/i2c/i2c_slave_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/micron/sdram/mobile_sdr.v:]
WARNING: [Project 1-478] Design 'synth_2' is stale and will not be used when launching 'impl_2'
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/clean_rst.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/decoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/encoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_constants.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_regs.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_test.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/timescale.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_an.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_mdio.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_rx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_sync.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_tx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/ddr/mig_interface_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/i2c/i2c_slave_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/micron/sdram/mobile_sdr.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/clean_rst.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/decoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/encoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_constants.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_regs.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_test.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/timescale.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_an.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_mdio.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_rx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_sync.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_tx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/ddr/mig_interface_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/i2c/i2c_slave_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/micron/sdram/mobile_sdr.v:]
[Tue May 26 01:39:33 2020] Launched pdm_to_pcm_demux16_sync_0_0_synth_1, pdm_to_pcm_energy_compare_0_0_synth_1, synth_2...
Run output will be captured here:
pdm_to_pcm_demux16_sync_0_0_synth_1: D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.runs/pdm_to_pcm_demux16_sync_0_0_synth_1/runme.log
pdm_to_pcm_energy_compare_0_0_synth_1: D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.runs/pdm_to_pcm_energy_compare_0_0_synth_1/runme.log
synth_2: D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.runs/synth_2/runme.log
[Tue May 26 01:39:34 2020] Launched impl_2...
Run output will be captured here: D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.runs/impl_2/runme.log
launch_runs: Time (s): cpu = 00:00:05 ; elapsed = 00:00:21 . Memory (MB): peak = 5866.305 ; gain = 38.855
update_module_reference pdm_to_pcm_energy_compare_0_0
INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing.
INFO: [IP_Flow 19-234] Refreshing IP repositories
WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'd:/sound_location_project/energy/dat096-master-latest_version/sound_location_project'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
Upgrading 'D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/pdm_to_pcm.bd'
INFO: [IP_Flow 19-3420] Updated pdm_to_pcm_energy_compare_0_0 to use current project options
WARNING: [BD 41-1731] Type mismatch between connected pins: /clk_div_1/clk_out(undef) and /energy_compare_0_upgraded_ipi/clk(clk)
Wrote  : <D:\sound_location_project\energy\dat096-master-latest_version\latest_version\dat096_ref_design.srcs\sources_1\bd\pdm_to_pcm\pdm_to_pcm.bd> 
Wrote  : <D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ui/bd_8ec0abfc.ui> 
update_module_reference: Time (s): cpu = 00:00:03 ; elapsed = 00:00:17 . Memory (MB): peak = 5914.359 ; gain = 29.594
reset_run impl_2
launch_runs impl_2 -jobs 6
WARNING: [BD 41-2180] Resetting the memory initialization file of </blk_mem_gen_0> to default.
WARNING: [BD 41-2180] Resetting the memory initialization file of </blk_mem_gen_3> to default.
WARNING: [BD 41-2180] Resetting the memory initialization file of </blk_mem_gen_1> to default.
WARNING: [BD 41-2180] Resetting the memory initialization file of </blk_mem_gen_2> to default.
INFO: [xilinx.com:ip:fir_compiler:7.2-913] /fir_compiler_1 Data_Sign has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:fir_compiler:7.2-913] /fir_compiler_1 Data_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:fir_compiler:7.2-913] /fir_compiler_1 Data_Fractional_Bits has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:cic_compiler:4.0-913] /cic_compiler_0 Input_Data_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:fir_compiler:7.2-913] /fir_compiler_0 Data_Sign has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:fir_compiler:7.2-913] /fir_compiler_0 Data_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:fir_compiler:7.2-913] /fir_compiler_0 Data_Fractional_Bits has been set to manual on the GUI. It will not be updated during validation with a propagated value.
WARNING: [xilinx.com:ip:c_addsub:12.0-313] /c_addsub_0 A-DATA: Field type resolution: data = integer. /c_shift_ram_0 Q-DATA: data = null. /c_shift_ram_0 Q-DATA data field will be interpreted as integer
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_0 A_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_0 A_Type has been set to manual on the GUI. It will not be updated during validation with a propagated value.
WARNING: [xilinx.com:ip:c_addsub:12.0-313] /c_addsub_0 B-DATA: Field type resolution: data = integer. /c_shift_ram_1 Q-DATA: data = null. /c_shift_ram_1 Q-DATA data field will be interpreted as integer
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_0 B_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_0 B_Type has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:c_addsub:12.0-308] /c_addsub_0 A-DATA: Validating field: data(16:0): int16 against /c_shift_ram_0 Q-DATA: data(16:0): bit16.
WARNING: [xilinx.com:ip:c_addsub:12.0-313] /c_addsub_0 A-DATA: Field type resolution: data = integer. /c_shift_ram_0 Q-DATA: data = null. /c_shift_ram_0 Q-DATA data field will be interpreted as integer
INFO: [xilinx.com:ip:c_addsub:12.0-308] /c_addsub_0 B-DATA: Validating field: data(16:0): int16 against /c_shift_ram_1 Q-DATA: data(16:0): bit16.
WARNING: [xilinx.com:ip:c_addsub:12.0-313] /c_addsub_0 B-DATA: Field type resolution: data = integer. /c_shift_ram_1 Q-DATA: data = null. /c_shift_ram_1 Q-DATA data field will be interpreted as integer
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_2 A_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_2 A_Type has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_2 B_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_2 B_Type has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:mult_gen:12.0-913] /mult_gen_0 PortAType has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:mult_gen:12.0-913] /mult_gen_0 PortBType has been set to manual on the GUI. It will not be updated during validation with a propagated value.
WARNING: [xilinx.com:ip:c_addsub:12.0-313] /c_addsub_1 A-DATA: Field type resolution: data = integer. /c_shift_ram_2 Q-DATA: data = null. /c_shift_ram_2 Q-DATA data field will be interpreted as integer
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_1 A_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_1 A_Type has been set to manual on the GUI. It will not be updated during validation with a propagated value.
WARNING: [xilinx.com:ip:c_addsub:12.0-313] /c_addsub_1 B-DATA: Field type resolution: data = integer. /c_shift_ram_3 Q-DATA: data = null. /c_shift_ram_3 Q-DATA data field will be interpreted as integer
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_1 B_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_1 B_Type has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:c_addsub:12.0-308] /c_addsub_1 A-DATA: Validating field: data(16:0): int16 against /c_shift_ram_2 Q-DATA: data(16:0): bit16.
WARNING: [xilinx.com:ip:c_addsub:12.0-313] /c_addsub_1 A-DATA: Field type resolution: data = integer. /c_shift_ram_2 Q-DATA: data = null. /c_shift_ram_2 Q-DATA data field will be interpreted as integer
INFO: [xilinx.com:ip:c_addsub:12.0-308] /c_addsub_1 B-DATA: Validating field: data(16:0): int16 against /c_shift_ram_3 Q-DATA: data(16:0): bit16.
WARNING: [xilinx.com:ip:c_addsub:12.0-313] /c_addsub_1 B-DATA: Field type resolution: data = integer. /c_shift_ram_3 Q-DATA: data = null. /c_shift_ram_3 Q-DATA data field will be interpreted as integer
WARNING: [BD 41-927] Following properties on pin /timemux_0/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
	CLK_DOMAIN=/clk_wiz_0_clk_out1 
WARNING: [BD 41-927] Following properties on pin /demux16_sync_0/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
	CLK_DOMAIN=/clk_wiz_0_clk_out1 
Wrote  : <D:\sound_location_project\energy\dat096-master-latest_version\latest_version\dat096_ref_design.srcs\sources_1\bd\pdm_to_pcm\pdm_to_pcm.bd> 
VHDL Output written to : D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/synth/pdm_to_pcm.vhd
VHDL Output written to : D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/sim/pdm_to_pcm.vhd
VHDL Output written to : D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.vhd
INFO: [BD 41-1029] Generation completed for the IP Integrator block cic_compiler_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block fir_compiler_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block fir_compiler_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block clk_wiz_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block fifo_generator_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block util_vector_logic_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block clk_div_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block util_ds_buf_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block clk_div_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block hp_filter_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block util_vector_logic_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block timemux_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block demux16_sync_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_addsub_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_addsub_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_addsub_2 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block blk_mem_gen_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block blk_mem_gen_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_shift_ram_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_shift_ram_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_shift_ram_2 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_shift_ram_3 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block blk_mem_gen_2 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block blk_mem_gen_3 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block scan_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block energy_compare_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block mult_gen_0 .
Exporting to file D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hw_handoff/pdm_to_pcm.hwh
Generated Block Design Tcl file D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hw_handoff/pdm_to_pcm_bd.tcl
Generated Hardware Definition File D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/synth/pdm_to_pcm.hwdef
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/clean_rst.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/decoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/encoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_constants.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_regs.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_test.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/timescale.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_an.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_mdio.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_rx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_sync.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_tx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/ddr/mig_interface_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/i2c/i2c_slave_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/micron/sdram/mobile_sdr.v:]
WARNING: [Project 1-478] Design 'synth_2' is stale and will not be used when launching 'impl_2'
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/clean_rst.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/decoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/encoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_constants.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_regs.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_test.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/timescale.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_an.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_mdio.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_rx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_sync.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_tx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/ddr/mig_interface_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/i2c/i2c_slave_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/micron/sdram/mobile_sdr.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/clean_rst.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/decoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/encoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_constants.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_regs.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_test.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/timescale.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_an.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_mdio.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_rx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_sync.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_tx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/ddr/mig_interface_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/i2c/i2c_slave_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/micron/sdram/mobile_sdr.v:]
[Tue May 26 01:41:54 2020] Launched pdm_to_pcm_energy_compare_0_0_synth_1, synth_2...
Run output will be captured here:
pdm_to_pcm_energy_compare_0_0_synth_1: D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.runs/pdm_to_pcm_energy_compare_0_0_synth_1/runme.log
synth_2: D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.runs/synth_2/runme.log
[Tue May 26 01:41:54 2020] Launched impl_2...
Run output will be captured here: D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.runs/impl_2/runme.log
launch_runs: Time (s): cpu = 00:00:06 ; elapsed = 00:00:18 . Memory (MB): peak = 5976.301 ; gain = 61.941
regenerate_bd_layout
current_design impl_2
report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -routable_nets -name timing_3
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met.
report_timing_summary: Time (s): cpu = 00:00:11 ; elapsed = 00:00:09 . Memory (MB): peak = 6028.137 ; gain = 2.031
create_ip_run [get_files -of_objects [get_fileset sources_1] D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/pdm_to_pcm.bd]
refresh_design
INFO: [Netlist 29-17] Analyzing 3484 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2019.1
INFO: [Project 1-570] Preparing netlist for logic optimization
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'masterrdwrgen.filter/pdm_to_pcm_i/clk_wiz_0/clk_in1' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
INFO: [Timing 38-478] Restoring timing data from binary archive.
INFO: [Timing 38-479] Binary timing data restore complete.
INFO: [Project 1-856] Restoring constraints from binary archive.
INFO: [Project 1-853] Binary constraint restore complete.
Reading XDEF placement.
Reading placer database...
Reading XDEF routing.
Read XDEF File: Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 6123.742 ; gain = 0.000
Restored from archive | CPU: 4.000000 secs | Memory: 0.000000 MB |
Finished XDEF File Restore: Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 6123.742 ; gain = 0.000
refresh_design: Time (s): cpu = 00:00:34 ; elapsed = 00:00:32 . Memory (MB): peak = 6123.742 ; gain = 95.254
open_report: Time (s): cpu = 00:00:37 ; elapsed = 00:00:27 . Memory (MB): peak = 6126.086 ; gain = 2.344
CRITICAL WARNING: [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.
WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met.
open_bd_design {D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/pdm_to_pcm.bd}
close [ open D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/new/arithm_block.vhd w ]
add_files D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/new/arithm_block.vhd
set_property library work [get_files  D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/new/arithm_block.vhd]
update_compile_order -fileset sources_1
open_bd_design {D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/pdm_to_pcm.bd}
delete_bd_objs [get_bd_nets c_addsub_2_S] [get_bd_nets mult_gen_0_P] [get_bd_nets c_addsub_1_S] [get_bd_nets c_shift_ram_2_Q] [get_bd_nets c_shift_ram_3_Q] [get_bd_nets c_addsub_0_S] [get_bd_nets c_shift_ram_0_Q] [get_bd_nets c_shift_ram_1_Q] [get_bd_cells mult_gen_0] [get_bd_cells c_addsub_1] [get_bd_cells c_addsub_2] [get_bd_cells c_addsub_0]
create_bd_cell -type module -reference arithm_block arithm_block_0
INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing.
INFO: [IP_Flow 19-234] Refreshing IP repositories
WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'd:/sound_location_project/energy/dat096-master-latest_version/sound_location_project'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
connect_bd_net [get_bd_pins arithm_block_0/val_out] [get_bd_pins energy_compare_0/val_in]
connect_bd_net [get_bd_pins c_shift_ram_0/Q] [get_bd_pins arithm_block_0/smand0]
connect_bd_net [get_bd_pins c_shift_ram_1/Q] [get_bd_pins arithm_block_0/smand1]
connect_bd_net [get_bd_pins c_shift_ram_2/Q] [get_bd_pins arithm_block_0/smand2]
connect_bd_net [get_bd_pins c_shift_ram_3/Q] [get_bd_pins arithm_block_0/smand3]
connect_bd_net [get_bd_pins arithm_block_0/adder_enable] [get_bd_pins scan_0/adder_enable]
connect_bd_net [get_bd_pins arithm_block_0/clk] [get_bd_pins clk_div_1/clk_out]
WARNING: [BD 41-1731] Type mismatch between connected pins: /clk_div_1/clk_out(undef) and /arithm_block_0/clk(clk)
save_bd_design
Wrote  : <D:\sound_location_project\energy\dat096-master-latest_version\latest_version\dat096_ref_design.srcs\sources_1\bd\pdm_to_pcm\pdm_to_pcm.bd> 
Wrote  : <D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ui/bd_8ec0abfc.ui> 
update_compile_order -fileset sources_1
regenerate_bd_layout
update_module_reference pdm_to_pcm_arithm_block_0_0
CRITICAL WARNING: [HDL 9-806] Syntax error near "en_enable". [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/new/arithm_block.vhd:23]
ERROR: [IP_Flow 19-259] [HDL Parser] Failed analyze operation while parsing HDL.
ERROR: [IP_Flow 19-258] [HDL Parser] Error parsing HDL file '../../../new/arithm_block.vhd'.
WARNING: [IP_Flow 19-378] There are no ports found from top-level file 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/new/arithm_block.vhd'.
ERROR: [IP_Flow 19-4668] Failed to infer definition from module 'arithm_block'.
update_module_reference: Time (s): cpu = 00:00:01 ; elapsed = 00:00:13 . Memory (MB): peak = 6182.379 ; gain = 2.707
ERROR: [Common 17-39] 'update_module_reference' failed due to earlier errors.
CRITICAL WARNING: [HDL 9-806] Syntax error near "en_enable". [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/new/arithm_block.vhd:23]
CRITICAL WARNING: [HDL 9-806] Syntax error near "en_enable". [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/new/arithm_block.vhd:23]
save_bd_design
Wrote  : <D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ui/bd_8ec0abfc.ui> 
update_module_reference pdm_to_pcm_arithm_block_0_0
INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing.
INFO: [IP_Flow 19-234] Refreshing IP repositories
WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'd:/sound_location_project/energy/dat096-master-latest_version/sound_location_project'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
Upgrading 'D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/pdm_to_pcm.bd'
INFO: [IP_Flow 19-3420] Updated pdm_to_pcm_arithm_block_0_0 to use current project options
WARNING: [IP_Flow 19-4698] Upgrade has added port 'en_enable'
WARNING: [IP_Flow 19-3298] Detected external port differences while upgrading 'pdm_to_pcm_arithm_block_0_0'. These changes may impact your design.
WARNING: [BD 41-1731] Type mismatch between connected pins: /clk_div_1/clk_out(undef) and /arithm_block_0_upgraded_ipi/clk(clk)
CRITICAL WARNING: [Coretcl 2-1280] The upgrade of 'pdm_to_pcm_arithm_block_0_0' has identified issues that may require user intervention. Please verify that the instance is correctly configured, and review any upgrade messages.
Wrote  : <D:\sound_location_project\energy\dat096-master-latest_version\latest_version\dat096_ref_design.srcs\sources_1\bd\pdm_to_pcm\pdm_to_pcm.bd> 
Wrote  : <D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ui/bd_8ec0abfc.ui> 
update_module_reference: Time (s): cpu = 00:00:03 ; elapsed = 00:00:14 . Memory (MB): peak = 6225.238 ; gain = 18.836
disconnect_bd_net /Net1 [get_bd_pins energy_compare_0/start]
connect_bd_net [get_bd_pins energy_compare_0/start] [get_bd_pins arithm_block_0/en_enable]
startgroup
set_property -dict [list CONFIG.SSET {false}] [get_bd_cells c_shift_ram_0]
endgroup
save_bd_design
Wrote  : <D:\sound_location_project\energy\dat096-master-latest_version\latest_version\dat096_ref_design.srcs\sources_1\bd\pdm_to_pcm\pdm_to_pcm.bd> 
Wrote  : <D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ui/bd_8ec0abfc.ui> 
update_module_reference pdm_to_pcm_scan_0_0
INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing.
INFO: [IP_Flow 19-234] Refreshing IP repositories
WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'd:/sound_location_project/energy/dat096-master-latest_version/sound_location_project'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
Upgrading 'D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/pdm_to_pcm.bd'
INFO: [IP_Flow 19-3420] Updated pdm_to_pcm_scan_0_0 to use current project options
WARNING: [IP_Flow 19-4700] Upgrade has removed port 'fifo_wr_en'
WARNING: [IP_Flow 19-4698] Upgrade has added port 'delay_enable'
WARNING: [IP_Flow 19-3298] Detected external port differences while upgrading 'pdm_to_pcm_scan_0_0'. These changes may impact your design.
WARNING: [BD 41-1731] Type mismatch between connected pins: /clk_div_1/clk_out(undef) and /scan_0_upgraded_ipi/clk(clk)
WARNING: [BD 41-1731] Type mismatch between connected pins: /c_shift_ram_0/CE(ce) and /scan_0_upgraded_ipi/adder_enable(undef)
WARNING: [BD 41-1731] Type mismatch between connected pins: /c_shift_ram_1/CE(ce) and /scan_0_upgraded_ipi/adder_enable(undef)
WARNING: [BD 41-1731] Type mismatch between connected pins: /c_shift_ram_2/CE(ce) and /scan_0_upgraded_ipi/adder_enable(undef)
WARNING: [BD 41-1731] Type mismatch between connected pins: /c_shift_ram_3/CE(ce) and /scan_0_upgraded_ipi/adder_enable(undef)
CRITICAL WARNING: [Coretcl 2-1280] The upgrade of 'pdm_to_pcm_scan_0_0' has identified issues that may require user intervention. Please verify that the instance is correctly configured, and review any upgrade messages.
Wrote  : <D:\sound_location_project\energy\dat096-master-latest_version\latest_version\dat096_ref_design.srcs\sources_1\bd\pdm_to_pcm\pdm_to_pcm.bd> 
Wrote  : <D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ui/bd_8ec0abfc.ui> 
update_module_reference: Time (s): cpu = 00:00:03 ; elapsed = 00:00:12 . Memory (MB): peak = 6283.582 ; gain = 11.914
disconnect_bd_net /Net1 [get_bd_pins scan_0/adder_enable]
disconnect_bd_net /Net1 [get_bd_pins arithm_block_0/adder_enable]
connect_bd_net [get_bd_pins arithm_block_0/adder_enable] [get_bd_pins scan_0/adder_enable]
connect_bd_net [get_bd_pins scan_0/delay_enable] [get_bd_pins c_shift_ram_0/CE]
WARNING: [BD 41-1731] Type mismatch between connected pins: /c_shift_ram_0/CE(ce) and /scan_0/delay_enable(undef)
WARNING: [BD 41-1731] Type mismatch between connected pins: /c_shift_ram_1/CE(ce) and /scan_0/delay_enable(undef)
WARNING: [BD 41-1731] Type mismatch between connected pins: /c_shift_ram_2/CE(ce) and /scan_0/delay_enable(undef)
WARNING: [BD 41-1731] Type mismatch between connected pins: /c_shift_ram_3/CE(ce) and /scan_0/delay_enable(undef)
save_bd_design
Wrote  : <D:\sound_location_project\energy\dat096-master-latest_version\latest_version\dat096_ref_design.srcs\sources_1\bd\pdm_to_pcm\pdm_to_pcm.bd> 
Wrote  : <D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ui/bd_8ec0abfc.ui> 
reset_run synth_2
launch_runs impl_2 -jobs 6
WARNING: [BD 41-2180] Resetting the memory initialization file of </blk_mem_gen_0> to default.
WARNING: [BD 41-2180] Resetting the memory initialization file of </blk_mem_gen_3> to default.
WARNING: [BD 41-2180] Resetting the memory initialization file of </blk_mem_gen_1> to default.
WARNING: [BD 41-2180] Resetting the memory initialization file of </blk_mem_gen_2> to default.
INFO: [xilinx.com:ip:fir_compiler:7.2-913] /fir_compiler_1 Data_Sign has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:fir_compiler:7.2-913] /fir_compiler_1 Data_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:fir_compiler:7.2-913] /fir_compiler_1 Data_Fractional_Bits has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:cic_compiler:4.0-913] /cic_compiler_0 Input_Data_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:fir_compiler:7.2-913] /fir_compiler_0 Data_Sign has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:fir_compiler:7.2-913] /fir_compiler_0 Data_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:fir_compiler:7.2-913] /fir_compiler_0 Data_Fractional_Bits has been set to manual on the GUI. It will not be updated during validation with a propagated value.
WARNING: [BD 41-927] Following properties on pin /timemux_0/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
	CLK_DOMAIN=/clk_wiz_0_clk_out1 
WARNING: [BD 41-927] Following properties on pin /demux16_sync_0/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
	CLK_DOMAIN=/clk_wiz_0_clk_out1 
Wrote  : <D:\sound_location_project\energy\dat096-master-latest_version\latest_version\dat096_ref_design.srcs\sources_1\bd\pdm_to_pcm\pdm_to_pcm.bd> 
VHDL Output written to : D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/synth/pdm_to_pcm.vhd
VHDL Output written to : D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/sim/pdm_to_pcm.vhd
VHDL Output written to : D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.vhd
INFO: [BD 41-1029] Generation completed for the IP Integrator block cic_compiler_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block fir_compiler_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block fir_compiler_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block clk_wiz_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block fifo_generator_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block util_vector_logic_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block clk_div_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block util_ds_buf_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block clk_div_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block hp_filter_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block util_vector_logic_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block timemux_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block demux16_sync_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block blk_mem_gen_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block blk_mem_gen_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_shift_ram_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_shift_ram_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_shift_ram_2 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_shift_ram_3 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block blk_mem_gen_2 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block blk_mem_gen_3 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block scan_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block energy_compare_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block arithm_block_0 .
Exporting to file D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hw_handoff/pdm_to_pcm.hwh
Generated Block Design Tcl file D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hw_handoff/pdm_to_pcm_bd.tcl
Generated Hardware Definition File D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/synth/pdm_to_pcm.hwdef
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/clean_rst.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/decoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/encoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_constants.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_regs.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_test.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/timescale.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_an.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_mdio.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_rx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_sync.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_tx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/ddr/mig_interface_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/i2c/i2c_slave_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/micron/sdram/mobile_sdr.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/clean_rst.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/decoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/encoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_constants.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_regs.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_test.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/timescale.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_an.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_mdio.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_rx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_sync.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_tx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/ddr/mig_interface_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/i2c/i2c_slave_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/micron/sdram/mobile_sdr.v:]
WARNING: [Project 1-478] Design 'synth_2' is stale and will not be used when launching 'impl_2'
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/clean_rst.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/decoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/encoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_constants.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_regs.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_test.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/timescale.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_an.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_mdio.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_rx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_sync.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_tx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/ddr/mig_interface_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/i2c/i2c_slave_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/micron/sdram/mobile_sdr.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/clean_rst.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/decoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/encoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_constants.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_regs.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_test.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/timescale.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_an.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_mdio.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_rx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_sync.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_tx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/ddr/mig_interface_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/i2c/i2c_slave_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/micron/sdram/mobile_sdr.v:]
[Tue May 26 02:35:58 2020] Launched pdm_to_pcm_scan_0_0_synth_1, pdm_to_pcm_arithm_block_0_0_synth_1, synth_2...
Run output will be captured here:
pdm_to_pcm_scan_0_0_synth_1: D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.runs/pdm_to_pcm_scan_0_0_synth_1/runme.log
pdm_to_pcm_arithm_block_0_0_synth_1: D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.runs/pdm_to_pcm_arithm_block_0_0_synth_1/runme.log
synth_2: D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.runs/synth_2/runme.log
[Tue May 26 02:35:59 2020] Launched impl_2...
Run output will be captured here: D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.runs/impl_2/runme.log
launch_runs: Time (s): cpu = 00:00:06 ; elapsed = 00:00:16 . Memory (MB): peak = 6333.949 ; gain = 46.336
update_module_reference pdm_to_pcm_arithm_block_0_0
INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing.
INFO: [IP_Flow 19-234] Refreshing IP repositories
WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'd:/sound_location_project/energy/dat096-master-latest_version/sound_location_project'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
Upgrading 'D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/pdm_to_pcm.bd'
INFO: [IP_Flow 19-3420] Updated pdm_to_pcm_arithm_block_0_0 to use current project options
WARNING: [BD 41-1731] Type mismatch between connected pins: /clk_div_1/clk_out(undef) and /arithm_block_0_upgraded_ipi/clk(clk)
Wrote  : <D:\sound_location_project\energy\dat096-master-latest_version\latest_version\dat096_ref_design.srcs\sources_1\bd\pdm_to_pcm\pdm_to_pcm.bd> 
Wrote  : <D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ui/bd_8ec0abfc.ui> 
update_module_reference: Time (s): cpu = 00:00:04 ; elapsed = 00:00:16 . Memory (MB): peak = 6390.602 ; gain = 35.934
reset_run impl_2
launch_runs impl_2 -jobs 6
WARNING: [BD 41-2180] Resetting the memory initialization file of </blk_mem_gen_0> to default.
WARNING: [BD 41-2180] Resetting the memory initialization file of </blk_mem_gen_3> to default.
WARNING: [BD 41-2180] Resetting the memory initialization file of </blk_mem_gen_1> to default.
WARNING: [BD 41-2180] Resetting the memory initialization file of </blk_mem_gen_2> to default.
INFO: [xilinx.com:ip:fir_compiler:7.2-913] /fir_compiler_1 Data_Sign has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:fir_compiler:7.2-913] /fir_compiler_1 Data_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:fir_compiler:7.2-913] /fir_compiler_1 Data_Fractional_Bits has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:cic_compiler:4.0-913] /cic_compiler_0 Input_Data_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:fir_compiler:7.2-913] /fir_compiler_0 Data_Sign has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:fir_compiler:7.2-913] /fir_compiler_0 Data_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:fir_compiler:7.2-913] /fir_compiler_0 Data_Fractional_Bits has been set to manual on the GUI. It will not be updated during validation with a propagated value.
WARNING: [BD 41-927] Following properties on pin /timemux_0/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
	CLK_DOMAIN=/clk_wiz_0_clk_out1 
WARNING: [BD 41-927] Following properties on pin /demux16_sync_0/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
	CLK_DOMAIN=/clk_wiz_0_clk_out1 
Wrote  : <D:\sound_location_project\energy\dat096-master-latest_version\latest_version\dat096_ref_design.srcs\sources_1\bd\pdm_to_pcm\pdm_to_pcm.bd> 
VHDL Output written to : D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/synth/pdm_to_pcm.vhd
VHDL Output written to : D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/sim/pdm_to_pcm.vhd
VHDL Output written to : D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.vhd
INFO: [BD 41-1029] Generation completed for the IP Integrator block cic_compiler_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block fir_compiler_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block fir_compiler_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block clk_wiz_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block fifo_generator_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block util_vector_logic_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block clk_div_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block util_ds_buf_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block clk_div_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block hp_filter_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block util_vector_logic_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block timemux_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block demux16_sync_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block blk_mem_gen_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block blk_mem_gen_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_shift_ram_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_shift_ram_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_shift_ram_2 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_shift_ram_3 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block blk_mem_gen_2 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block blk_mem_gen_3 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block scan_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block energy_compare_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block arithm_block_0 .
Exporting to file D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hw_handoff/pdm_to_pcm.hwh
Generated Block Design Tcl file D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hw_handoff/pdm_to_pcm_bd.tcl
Generated Hardware Definition File D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/synth/pdm_to_pcm.hwdef
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/clean_rst.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/decoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/encoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_constants.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_regs.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_test.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/timescale.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_an.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_mdio.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_rx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_sync.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_tx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/ddr/mig_interface_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/i2c/i2c_slave_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/micron/sdram/mobile_sdr.v:]
WARNING: [Project 1-478] Design 'synth_2' is stale and will not be used when launching 'impl_2'
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/clean_rst.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/decoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/encoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_constants.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_regs.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_test.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/timescale.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_an.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_mdio.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_rx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_sync.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_tx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/ddr/mig_interface_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/i2c/i2c_slave_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/micron/sdram/mobile_sdr.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/clean_rst.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/decoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/encoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_constants.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_regs.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_test.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/timescale.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_an.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_mdio.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_rx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_sync.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_tx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/ddr/mig_interface_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/i2c/i2c_slave_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/micron/sdram/mobile_sdr.v:]
[Tue May 26 02:40:37 2020] Launched pdm_to_pcm_arithm_block_0_0_synth_1, synth_2...
Run output will be captured here:
pdm_to_pcm_arithm_block_0_0_synth_1: D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.runs/pdm_to_pcm_arithm_block_0_0_synth_1/runme.log
synth_2: D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.runs/synth_2/runme.log
[Tue May 26 02:40:38 2020] Launched impl_2...
Run output will be captured here: D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.runs/impl_2/runme.log
launch_runs: Time (s): cpu = 00:00:04 ; elapsed = 00:00:14 . Memory (MB): peak = 6445.008 ; gain = 54.406
create_ip_run [get_files -of_objects [get_fileset sources_1] D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/pdm_to_pcm.bd]
refresh_design
INFO: [Netlist 29-17] Analyzing 3409 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2019.1
INFO: [Project 1-570] Preparing netlist for logic optimization
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'masterrdwrgen.filter/pdm_to_pcm_i/clk_wiz_0/clk_in1' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
INFO: [Timing 38-478] Restoring timing data from binary archive.
INFO: [Timing 38-479] Binary timing data restore complete.
INFO: [Project 1-856] Restoring constraints from binary archive.
INFO: [Project 1-853] Binary constraint restore complete.
Reading XDEF placement.
Reading placer database...
Reading XDEF routing.
Read XDEF File: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 6588.598 ; gain = 0.000
Restored from archive | CPU: 5.000000 secs | Memory: 0.000000 MB |
Finished XDEF File Restore: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 6588.598 ; gain = 0.000
refresh_design: Time (s): cpu = 00:00:34 ; elapsed = 00:00:31 . Memory (MB): peak = 6714.637 ; gain = 229.664
open_report: Time (s): cpu = 00:00:38 ; elapsed = 00:00:28 . Memory (MB): peak = 6737.234 ; gain = 19.453
CRITICAL WARNING: [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.
WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met.
open_bd_design {D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/pdm_to_pcm.bd}
reset_run synth_2
launch_runs impl_2 -jobs 6
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/clean_rst.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/decoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/encoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_constants.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_regs.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_test.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/timescale.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_an.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_mdio.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_rx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_sync.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_tx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/ddr/mig_interface_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/i2c/i2c_slave_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/micron/sdram/mobile_sdr.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/clean_rst.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/decoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/encoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_constants.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_regs.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_test.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/timescale.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_an.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_mdio.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_rx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_sync.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_tx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/ddr/mig_interface_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/i2c/i2c_slave_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/micron/sdram/mobile_sdr.v:]
WARNING: [Project 1-478] Design 'synth_2' is stale and will not be used when launching 'impl_2'
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/clean_rst.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/decoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/encoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_constants.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_regs.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_test.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/timescale.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_an.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_mdio.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_rx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_sync.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_tx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/ddr/mig_interface_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/i2c/i2c_slave_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/micron/sdram/mobile_sdr.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/clean_rst.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/decoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/encoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_constants.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_regs.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_test.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/timescale.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_an.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_mdio.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_rx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_sync.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_tx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/ddr/mig_interface_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/i2c/i2c_slave_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/micron/sdram/mobile_sdr.v:]
[Tue May 26 03:06:52 2020] Launched synth_2...
Run output will be captured here: D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.runs/synth_2/runme.log
[Tue May 26 03:06:52 2020] Launched impl_2...
Run output will be captured here: D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.runs/impl_2/runme.log
open_bd_design {D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/pdm_to_pcm.bd}
open_bd_design {D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/pdm_to_pcm.bd}
current_design synth_2
create_ip_run [get_files -of_objects [get_fileset sources_1] D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/pdm_to_pcm.bd]
refresh_design
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_arithm_block_0_0/pdm_to_pcm_arithm_block_0_0.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/arithm_block_0'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_blk_mem_gen_0_0/pdm_to_pcm_blk_mem_gen_0_0.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/blk_mem_gen_0'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_blk_mem_gen_1_0/pdm_to_pcm_blk_mem_gen_1_0.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/blk_mem_gen_1'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_blk_mem_gen_1_1/pdm_to_pcm_blk_mem_gen_1_1.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/blk_mem_gen_2'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_blk_mem_gen_2_0/pdm_to_pcm_blk_mem_gen_2_0.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/blk_mem_gen_3'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_c_shift_ram_0_0/pdm_to_pcm_c_shift_ram_0_0.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/c_shift_ram_0'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_c_shift_ram_1_0/pdm_to_pcm_c_shift_ram_1_0.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/c_shift_ram_1'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_c_shift_ram_1_1/pdm_to_pcm_c_shift_ram_1_1.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/c_shift_ram_2'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_c_shift_ram_1_2/pdm_to_pcm_c_shift_ram_1_2.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/c_shift_ram_3'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_cic_compiler_0_0/pdm_to_pcm_cic_compiler_0_0.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/cic_compiler_0'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_clk_div_0_0/pdm_to_pcm_clk_div_0_0.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/clk_div_0'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_clk_div_1_0/pdm_to_pcm_clk_div_1_0.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/clk_div_1'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_clk_wiz_0_0/pdm_to_pcm_clk_wiz_0_0.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/clk_wiz_0'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_demux16_sync_0_0/pdm_to_pcm_demux16_sync_0_0.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/demux16_sync_0'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_energy_compare_0_0/pdm_to_pcm_energy_compare_0_0.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/energy_compare_0'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_fifo_generator_0_0/pdm_to_pcm_fifo_generator_0_0.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/fifo_generator_0'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_fir_compiler_0_0/pdm_to_pcm_fir_compiler_0_0.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/fir_compiler_0'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_fir_compiler_1_0/pdm_to_pcm_fir_compiler_1_0.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/fir_compiler_1'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_hp_filter_0_0/pdm_to_pcm_hp_filter_0_0.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/hp_filter_0'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_scan_0_0/pdm_to_pcm_scan_0_0.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/scan_0'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_timemux_0_2/pdm_to_pcm_timemux_0_2.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/timemux_0'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_util_ds_buf_0_0/pdm_to_pcm_util_ds_buf_0_0.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/util_ds_buf_0'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_util_vector_logic_0_0/pdm_to_pcm_util_vector_logic_0_0.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/util_vector_logic_0'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_util_vector_logic_0_2/pdm_to_pcm_util_vector_logic_0_2.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/util_vector_logic_1'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/ip/mig/mig.dcp' for cell 'mig_gen.gen_mig.ddrc/gen_mig.MCB_inst'
INFO: [Netlist 29-17] Analyzing 3418 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2019.1
INFO: [Project 1-570] Preparing netlist for logic optimization
WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. masterrdwrgen.filter/pdm_to_pcm_i/clk_wiz_0/inst/clkin1_ibufg 
Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'masterrdwrgen.filter/pdm_to_pcm_i/clk_wiz_0/clk_in1' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_fir_compiler_0_0/constraints/fir_compiler_v7_2.xdc] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/fir_compiler_0/U0'
Finished Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_fir_compiler_0_0/constraints/fir_compiler_v7_2.xdc] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/fir_compiler_0/U0'
Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_fir_compiler_1_0/constraints/fir_compiler_v7_2.xdc] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/fir_compiler_1/U0'
Finished Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_fir_compiler_1_0/constraints/fir_compiler_v7_2.xdc] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/fir_compiler_1/U0'
Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_clk_wiz_0_0/pdm_to_pcm_clk_wiz_0_0_board.xdc] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/clk_wiz_0/inst'
Finished Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_clk_wiz_0_0/pdm_to_pcm_clk_wiz_0_0_board.xdc] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/clk_wiz_0/inst'
Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_clk_wiz_0_0/pdm_to_pcm_clk_wiz_0_0.xdc] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/clk_wiz_0/inst'
INFO: [Timing 38-35] Done setting XDC timing constraints. [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_clk_wiz_0_0/pdm_to_pcm_clk_wiz_0_0.xdc:57]
INFO: [Timing 38-2] Deriving generated clocks [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_clk_wiz_0_0/pdm_to_pcm_clk_wiz_0_0.xdc:57]
Finished Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_clk_wiz_0_0/pdm_to_pcm_clk_wiz_0_0.xdc] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/clk_wiz_0/inst'
Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_fifo_generator_0_0/pdm_to_pcm_fifo_generator_0_0.xdc] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/fifo_generator_0/U0'
Finished Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_fifo_generator_0_0/pdm_to_pcm_fifo_generator_0_0.xdc] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/fifo_generator_0/U0'
Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_util_ds_buf_0_0/pdm_to_pcm_util_ds_buf_0_0_board.xdc] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/util_ds_buf_0/U0'
Finished Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_util_ds_buf_0_0/pdm_to_pcm_util_ds_buf_0_0_board.xdc] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/util_ds_buf_0/U0'
Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/constraints/mig.xdc] for cell 'mig_gen.gen_mig.ddrc/gen_mig.MCB_inst'
Finished Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/constraints/mig.xdc] for cell 'mig_gen.gen_mig.ddrc/gen_mig.MCB_inst'
Parsing XDC File [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc]
CRITICAL WARNING: [Constraints 18-1056] Clock 'clk200' completely overrides clock 'clk200p'.
New: create_clock -period 5.000 -name clk200 [get_ports clk200p], [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:2]
Previous: create_clock -period 5.000 [get_ports clk200p], [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/constraints/mig.xdc:30]
Resolution: Review the constraint files and remove the redundant clock definition(s). If the clock constraints are not saved in a file, you can first save the constraints to an XDC file and reload the design once the constraints have been corrected.
INFO: [Timing 38-2] Deriving generated clocks [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:12]
CRITICAL WARNING: [Common 17-165] Too many positional options when parsing 'block', please type 'set_false_path -help' for usage info. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:12]
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:15]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:15]
CRITICAL WARNING: [Vivado 12-4739] set_input_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:15]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:17]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:17]
CRITICAL WARNING: [Vivado 12-4739] set_input_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:17]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:18]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:18]
CRITICAL WARNING: [Vivado 12-4739] set_output_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:18]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:21]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:21]
CRITICAL WARNING: [Vivado 12-4739] set_input_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:21]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:22]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:22]
CRITICAL WARNING: [Vivado 12-4739] set_output_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:22]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:23]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:23]
CRITICAL WARNING: [Vivado 12-4739] set_input_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:23]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:24]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:24]
CRITICAL WARNING: [Vivado 12-4739] set_output_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:24]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:28]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:28]
CRITICAL WARNING: [Vivado 12-4739] set_input_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:28]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:29]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:29]
CRITICAL WARNING: [Vivado 12-4739] set_input_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:29]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:30]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:30]
CRITICAL WARNING: [Vivado 12-4739] set_input_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:30]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:31]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:31]
CRITICAL WARNING: [Vivado 12-4739] set_input_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:31]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:34]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:34]
CRITICAL WARNING: [Vivado 12-4739] set_output_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:34]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:35]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:35]
CRITICAL WARNING: [Vivado 12-4739] set_output_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:35]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:36]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:36]
CRITICAL WARNING: [Vivado 12-4739] set_output_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:36]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:37]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:37]
CRITICAL WARNING: [Vivado 12-4739] set_output_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:37]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:44]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:44]
CRITICAL WARNING: [Vivado 12-4739] set_input_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:44]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:45]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:45]
CRITICAL WARNING: [Vivado 12-4739] set_input_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:45]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:46]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:46]
CRITICAL WARNING: [Vivado 12-4739] set_output_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:46]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:47]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:47]
CRITICAL WARNING: [Vivado 12-4739] set_output_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:47]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:48]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:48]
CRITICAL WARNING: [Vivado 12-4739] set_input_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:48]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:49]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:49]
CRITICAL WARNING: [Vivado 12-4739] set_input_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:49]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:50]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:50]
CRITICAL WARNING: [Vivado 12-4739] set_output_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:50]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:51]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:51]
CRITICAL WARNING: [Vivado 12-4739] set_output_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:51]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
INFO: [Timing 38-2] Deriving generated clocks [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:113]
WARNING: [Vivado 12-627] No clocks matched 'rgmii_tx_clk'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:140]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:140]
CRITICAL WARNING: [Vivado 12-4739] set_output_delay:No valid object(s) found for '-clock [get_clocks rgmii_tx_clk]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:140]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'rgmii_tx_clk'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:141]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:141]
CRITICAL WARNING: [Vivado 12-4739] set_output_delay:No valid object(s) found for '-clock [get_clocks rgmii_tx_clk]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:141]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'rgmii_tx_clk'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:142]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:142]
CRITICAL WARNING: [Vivado 12-4739] set_output_delay:No valid object(s) found for '-clock [get_clocks rgmii_tx_clk]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:142]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'rgmii_tx_clk'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:143]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:143]
CRITICAL WARNING: [Vivado 12-4739] set_output_delay:No valid object(s) found for '-clock [get_clocks rgmii_tx_clk]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:143]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:156]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:156]
CRITICAL WARNING: [Vivado 12-4739] set_input_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:156]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:157]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:157]
CRITICAL WARNING: [Vivado 12-4739] set_input_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:157]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:158]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:158]
CRITICAL WARNING: [Vivado 12-4739] set_output_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:158]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:159]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:159]
CRITICAL WARNING: [Vivado 12-4739] set_output_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:159]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:162]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:162]
CRITICAL WARNING: [Vivado 12-4739] set_output_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:162]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'CLKFBOUT'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:163]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:163]
CRITICAL WARNING: [Vivado 12-4739] set_output_delay:No valid object(s) found for '-clock [get_clocks -include_generated_clocks CLKFBOUT]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:163]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-180] No cells matched 'eth1.*delay_rgmii*'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:181]
WARNING: [Vivado 12-180] No cells matched 'eth1.*.*delay_rgmii*'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:181]
WARNING: [Vivado 12-180] No cells matched 'eth1.*.*.*delay_rgmii*'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:181]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:181]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
WARNING: [Vivado 12-627] No clocks matched 'clk50*'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:200]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:200]
CRITICAL WARNING: [Vivado 12-4739] set_false_path:No valid object(s) found for '-to [get_clocks clk50*]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:200]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
WARNING: [Vivado 12-627] No clocks matched 'clk50*'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:201]
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:201]
CRITICAL WARNING: [Vivado 12-4739] set_false_path:No valid object(s) found for '-from [get_clocks clk50*]'. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:201]
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced.
Finished Parsing XDC File [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc]
Parsing XDC File [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/new/constr_synth.xdc]
Finished Parsing XDC File [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/new/constr_synth.xdc]
Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_fifo_generator_0_0/pdm_to_pcm_fifo_generator_0_0_clocks.xdc] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/fifo_generator_0/U0'
Finished Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_fifo_generator_0_0/pdm_to_pcm_fifo_generator_0_0_clocks.xdc] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/fifo_generator_0/U0'
Sourcing Tcl File [C:/xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/fifo_generator_0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Finished Sourcing Tcl File [C:/xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/fifo_generator_0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Sourcing Tcl File [C:/xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/fifo_generator_0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Finished Sourcing Tcl File [C:/xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/fifo_generator_0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
refresh_design: Time (s): cpu = 00:00:54 ; elapsed = 00:00:50 . Memory (MB): peak = 7149.324 ; gain = 388.441
current_design impl_2
create_ip_run [get_files -of_objects [get_fileset sources_1] D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/pdm_to_pcm.bd]
refresh_design
INFO: [Netlist 29-17] Analyzing 3409 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2019.1
INFO: [Project 1-570] Preparing netlist for logic optimization
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'masterrdwrgen.filter/pdm_to_pcm_i/clk_wiz_0/clk_in1' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
INFO: [Timing 38-478] Restoring timing data from binary archive.
INFO: [Timing 38-479] Binary timing data restore complete.
INFO: [Project 1-856] Restoring constraints from binary archive.
INFO: [Project 1-853] Binary constraint restore complete.
Reading XDEF placement.
Reading placer database...
Reading XDEF routing.
Read XDEF File: Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 7149.324 ; gain = 0.000
Restored from archive | CPU: 5.000000 secs | Memory: 0.000000 MB |
Finished XDEF File Restore: Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak = 7149.324 ; gain = 0.000
refresh_design: Time (s): cpu = 00:00:34 ; elapsed = 00:00:33 . Memory (MB): peak = 7149.324 ; gain = 0.000
open_report: Time (s): cpu = 00:00:38 ; elapsed = 00:00:28 . Memory (MB): peak = 7149.324 ; gain = 0.000
CRITICAL WARNING: [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.
WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met.
current_design synth_2
INFO: [Timing 38-35] Done setting XDC timing constraints.
WARNING: [Vivado 12-508] No pins matched '*clk_pII*'.
set_false_path -from [get_clocks  -filter { NAME =~  "Net" && NAME =~  "*" }] -to [get_clocks -of_objects [get_pins mig_gen.gen_mig.ddrc/gen_mig.MCB_inst/u_mig_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT]]
current_design impl_2
ERROR: [Constraints 18-358] set_false_path: at least one of -from, -through or -to required.
current_design synth_2
current_design impl_2
WARNING: [Vivado 12-508] No pins matched '*net*'.
WARNING: [Vivado 12-627] No clocks matched '*net*'.
INFO: [Vivado 12-626] No clocks found. Please use 'create_clock' or 'create_generated_clock' command to create clocks.
set_false_path -from [get_clocks  "*Net*"] -to [get_clocks -of_objects [get_pins mig_gen.gen_mig.ddrc/gen_mig.MCB_inst/u_mig_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT]]
save_constraints -force
current_design synth_2
create_ip_run [get_files -of_objects [get_fileset sources_1] D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/pdm_to_pcm.bd]
refresh_design
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_fir_compiler_0_0/constraints/fir_compiler_v7_2.xdc] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/fir_compiler_0/U0'
Finished Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_fir_compiler_0_0/constraints/fir_compiler_v7_2.xdc] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/fir_compiler_0/U0'
Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_fir_compiler_1_0/constraints/fir_compiler_v7_2.xdc] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/fir_compiler_1/U0'
Finished Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_fir_compiler_1_0/constraints/fir_compiler_v7_2.xdc] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/fir_compiler_1/U0'
Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_clk_wiz_0_0/pdm_to_pcm_clk_wiz_0_0_board.xdc] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/clk_wiz_0/inst'
Finished Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_clk_wiz_0_0/pdm_to_pcm_clk_wiz_0_0_board.xdc] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/clk_wiz_0/inst'
Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_clk_wiz_0_0/pdm_to_pcm_clk_wiz_0_0.xdc] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/clk_wiz_0/inst'
INFO: [Timing 38-35] Done setting XDC timing constraints. [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_clk_wiz_0_0/pdm_to_pcm_clk_wiz_0_0.xdc:57]
INFO: [Timing 38-2] Deriving generated clocks [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_clk_wiz_0_0/pdm_to_pcm_clk_wiz_0_0.xdc:57]
Finished Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_clk_wiz_0_0/pdm_to_pcm_clk_wiz_0_0.xdc] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/clk_wiz_0/inst'
Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_fifo_generator_0_0/pdm_to_pcm_fifo_generator_0_0.xdc] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/fifo_generator_0/U0'
Finished Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_fifo_generator_0_0/pdm_to_pcm_fifo_generator_0_0.xdc] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/fifo_generator_0/U0'
Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_util_ds_buf_0_0/pdm_to_pcm_util_ds_buf_0_0_board.xdc] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/util_ds_buf_0/U0'
Finished Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_util_ds_buf_0_0/pdm_to_pcm_util_ds_buf_0_0_board.xdc] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/util_ds_buf_0/U0'
Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/constraints/mig.xdc] for cell 'mig_gen.gen_mig.ddrc/gen_mig.MCB_inst'
Finished Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/constraints/mig.xdc] for cell 'mig_gen.gen_mig.ddrc/gen_mig.MCB_inst'
Parsing XDC File [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc]
CRITICAL WARNING: [Constraints 18-1056] Clock 'clk200' completely overrides clock 'clk200p'.
New: create_clock -period 5.000 -name clk200 [get_ports clk200p], [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:74161]
Previous: create_clock -period 5.000 [get_ports clk200p], [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/constraints/mig.xdc:30]
Resolution: Review the constraint files and remove the redundant clock definition(s). If the clock constraints are not saved in a file, you can first save the constraints to an XDC file and reload the design once the constraints have been corrected.
INFO: [Timing 38-2] Deriving generated clocks [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:74248]
Finished Parsing XDC File [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc]
Parsing XDC File [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/new/constr_synth.xdc]
Finished Parsing XDC File [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/new/constr_synth.xdc]
Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_fifo_generator_0_0/pdm_to_pcm_fifo_generator_0_0_clocks.xdc] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/fifo_generator_0/U0'
Finished Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_fifo_generator_0_0/pdm_to_pcm_fifo_generator_0_0_clocks.xdc] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/fifo_generator_0/U0'
Sourcing Tcl File [C:/xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/fifo_generator_0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Finished Sourcing Tcl File [C:/xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/fifo_generator_0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Sourcing Tcl File [C:/xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/fifo_generator_0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Finished Sourcing Tcl File [C:/xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/fifo_generator_0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
refresh_design: Time (s): cpu = 00:07:06 ; elapsed = 00:02:40 . Memory (MB): peak = 8370.523 ; gain = 1221.199
reset_run synth_2
launch_runs impl_2 -jobs 6
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/clean_rst.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/decoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/encoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_constants.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_regs.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_test.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/timescale.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_an.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_mdio.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_rx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_sync.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_tx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/ddr/mig_interface_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/i2c/i2c_slave_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/micron/sdram/mobile_sdr.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/clean_rst.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/decoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/encoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_constants.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_regs.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_test.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/timescale.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_an.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_mdio.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_rx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_sync.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_tx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/ddr/mig_interface_model.v:]
INFO: [Common 17-14] Message 'filemgmt 56-99' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
WARNING: [Project 1-478] Design 'synth_2' is stale and will not be used when launching 'impl_2'
[Tue May 26 03:40:15 2020] Launched synth_2...
Run output will be captured here: D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.runs/synth_2/runme.log
[Tue May 26 03:40:15 2020] Launched impl_2...
Run output will be captured here: D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.runs/impl_2/runme.log
launch_runs: Time (s): cpu = 00:07:05 ; elapsed = 00:02:25 . Memory (MB): peak = 8386.309 ; gain = 13.660
create_ip_run [get_files -of_objects [get_fileset sources_1] D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/pdm_to_pcm.bd]
refresh_design
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_arithm_block_0_0/pdm_to_pcm_arithm_block_0_0.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/arithm_block_0'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_blk_mem_gen_0_0/pdm_to_pcm_blk_mem_gen_0_0.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/blk_mem_gen_0'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_blk_mem_gen_1_0/pdm_to_pcm_blk_mem_gen_1_0.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/blk_mem_gen_1'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_blk_mem_gen_1_1/pdm_to_pcm_blk_mem_gen_1_1.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/blk_mem_gen_2'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_blk_mem_gen_2_0/pdm_to_pcm_blk_mem_gen_2_0.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/blk_mem_gen_3'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_c_shift_ram_0_0/pdm_to_pcm_c_shift_ram_0_0.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/c_shift_ram_0'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_c_shift_ram_1_0/pdm_to_pcm_c_shift_ram_1_0.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/c_shift_ram_1'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_c_shift_ram_1_1/pdm_to_pcm_c_shift_ram_1_1.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/c_shift_ram_2'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_c_shift_ram_1_2/pdm_to_pcm_c_shift_ram_1_2.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/c_shift_ram_3'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_cic_compiler_0_0/pdm_to_pcm_cic_compiler_0_0.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/cic_compiler_0'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_clk_div_0_0/pdm_to_pcm_clk_div_0_0.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/clk_div_0'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_clk_div_1_0/pdm_to_pcm_clk_div_1_0.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/clk_div_1'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_clk_wiz_0_0/pdm_to_pcm_clk_wiz_0_0.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/clk_wiz_0'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_demux16_sync_0_0/pdm_to_pcm_demux16_sync_0_0.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/demux16_sync_0'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_energy_compare_0_0/pdm_to_pcm_energy_compare_0_0.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/energy_compare_0'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_fifo_generator_0_0/pdm_to_pcm_fifo_generator_0_0.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/fifo_generator_0'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_fir_compiler_0_0/pdm_to_pcm_fir_compiler_0_0.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/fir_compiler_0'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_fir_compiler_1_0/pdm_to_pcm_fir_compiler_1_0.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/fir_compiler_1'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_hp_filter_0_0/pdm_to_pcm_hp_filter_0_0.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/hp_filter_0'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_scan_0_0/pdm_to_pcm_scan_0_0.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/scan_0'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_timemux_0_2/pdm_to_pcm_timemux_0_2.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/timemux_0'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_util_ds_buf_0_0/pdm_to_pcm_util_ds_buf_0_0.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/util_ds_buf_0'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_util_vector_logic_0_0/pdm_to_pcm_util_vector_logic_0_0.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/util_vector_logic_0'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_util_vector_logic_0_2/pdm_to_pcm_util_vector_logic_0_2.dcp' for cell 'masterrdwrgen.filter/pdm_to_pcm_i/util_vector_logic_1'
INFO: [Project 1-454] Reading design checkpoint 'd:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/ip/mig/mig.dcp' for cell 'mig_gen.gen_mig.ddrc/gen_mig.MCB_inst'
INFO: [Netlist 29-17] Analyzing 3418 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2019.1
INFO: [Project 1-570] Preparing netlist for logic optimization
WARNING: [Opt 31-32] Removing redundant IBUF since it is not being driven by a top-level port. masterrdwrgen.filter/pdm_to_pcm_i/clk_wiz_0/inst/clkin1_ibufg 
Resolution: The tool has removed redundant IBUF. To resolve this warning, check for redundant IBUF in the input design.
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'masterrdwrgen.filter/pdm_to_pcm_i/clk_wiz_0/clk_in1' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_fir_compiler_0_0/constraints/fir_compiler_v7_2.xdc] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/fir_compiler_0/U0'
Finished Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_fir_compiler_0_0/constraints/fir_compiler_v7_2.xdc] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/fir_compiler_0/U0'
Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_fir_compiler_1_0/constraints/fir_compiler_v7_2.xdc] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/fir_compiler_1/U0'
Finished Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_fir_compiler_1_0/constraints/fir_compiler_v7_2.xdc] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/fir_compiler_1/U0'
Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_clk_wiz_0_0/pdm_to_pcm_clk_wiz_0_0_board.xdc] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/clk_wiz_0/inst'
Finished Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_clk_wiz_0_0/pdm_to_pcm_clk_wiz_0_0_board.xdc] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/clk_wiz_0/inst'
Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_clk_wiz_0_0/pdm_to_pcm_clk_wiz_0_0.xdc] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/clk_wiz_0/inst'
INFO: [Timing 38-35] Done setting XDC timing constraints. [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_clk_wiz_0_0/pdm_to_pcm_clk_wiz_0_0.xdc:57]
INFO: [Timing 38-2] Deriving generated clocks [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_clk_wiz_0_0/pdm_to_pcm_clk_wiz_0_0.xdc:57]
Finished Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_clk_wiz_0_0/pdm_to_pcm_clk_wiz_0_0.xdc] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/clk_wiz_0/inst'
Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_fifo_generator_0_0/pdm_to_pcm_fifo_generator_0_0.xdc] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/fifo_generator_0/U0'
Finished Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_fifo_generator_0_0/pdm_to_pcm_fifo_generator_0_0.xdc] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/fifo_generator_0/U0'
Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_util_ds_buf_0_0/pdm_to_pcm_util_ds_buf_0_0_board.xdc] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/util_ds_buf_0/U0'
Finished Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_util_ds_buf_0_0/pdm_to_pcm_util_ds_buf_0_0_board.xdc] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/util_ds_buf_0/U0'
Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/constraints/mig.xdc] for cell 'mig_gen.gen_mig.ddrc/gen_mig.MCB_inst'
Finished Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/constraints/mig.xdc] for cell 'mig_gen.gen_mig.ddrc/gen_mig.MCB_inst'
Parsing XDC File [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc]
CRITICAL WARNING: [Constraints 18-1056] Clock 'clk200' completely overrides clock 'clk200p'.
New: create_clock -period 5.000 -name clk200 [get_ports clk200p], [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:74161]
Previous: create_clock -period 5.000 [get_ports clk200p], [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/ip/mig/mig/user_design/constraints/mig.xdc:30]
Resolution: Review the constraint files and remove the redundant clock definition(s). If the clock constraints are not saved in a file, you can first save the constraints to an XDC file and reload the design once the constraints have been corrected.
INFO: [Timing 38-2] Deriving generated clocks [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc:74248]
Finished Parsing XDC File [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/imports/xilinx-ac701-xc7a200t/xilinx-ac701-xc7a200t.xdc]
Parsing XDC File [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/new/constr_synth.xdc]
Finished Parsing XDC File [D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/constrs_1/new/constr_synth.xdc]
Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_fifo_generator_0_0/pdm_to_pcm_fifo_generator_0_0_clocks.xdc] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/fifo_generator_0/U0'
Finished Parsing XDC File [d:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_fifo_generator_0_0/pdm_to_pcm_fifo_generator_0_0_clocks.xdc] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/fifo_generator_0/U0'
Sourcing Tcl File [C:/xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/fifo_generator_0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Finished Sourcing Tcl File [C:/xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/fifo_generator_0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst'
Sourcing Tcl File [C:/xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/fifo_generator_0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
Finished Sourcing Tcl File [C:/xilinx/Vivado/2019.1/data/ip/xpm/xpm_cdc/tcl/xpm_cdc_gray.tcl] for cell 'masterrdwrgen.filter/pdm_to_pcm_i/fifo_generator_0/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst'
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
refresh_design: Time (s): cpu = 00:07:40 ; elapsed = 00:03:07 . Memory (MB): peak = 8408.848 ; gain = 22.535
current_design impl_2
create_ip_run [get_files -of_objects [get_fileset sources_1] D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/pdm_to_pcm.bd]
refresh_design
INFO: [Netlist 29-17] Analyzing 3409 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2019.1
INFO: [Project 1-570] Preparing netlist for logic optimization
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'masterrdwrgen.filter/pdm_to_pcm_i/clk_wiz_0/clk_in1' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
INFO: [Timing 38-478] Restoring timing data from binary archive.
INFO: [Timing 38-479] Binary timing data restore complete.
INFO: [Project 1-856] Restoring constraints from binary archive.
INFO: [Project 1-853] Binary constraint restore complete.
Reading XDEF placement.
Reading placer database...
Reading XDEF routing.
Read XDEF File: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 8425.254 ; gain = 0.000
Restored from archive | CPU: 5.000000 secs | Memory: 0.000000 MB |
Finished XDEF File Restore: Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 8425.254 ; gain = 0.000
refresh_design: Time (s): cpu = 00:06:46 ; elapsed = 00:02:37 . Memory (MB): peak = 8441.934 ; gain = 33.086
open_report: Time (s): cpu = 00:00:37 ; elapsed = 00:00:30 . Memory (MB): peak = 8441.934 ; gain = 0.000
CRITICAL WARNING: [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.
WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met.
startgroup
create_pblock pblock_1
resize_pblock pblock_1 -add {SLICE_X104Y67:SLICE_X159Y134 DSP48_X7Y28:DSP48_X8Y53 RAMB18_X7Y28:RAMB18_X8Y53 RAMB36_X7Y14:RAMB36_X8Y26}
resize_pblock: Time (s): cpu = 06:17:15 ; elapsed = 02:07:51 . Memory (MB): peak = 8486.344 ; gain = 36.715
add_cells_to_pblock pblock_1 [get_cells [list {leon/l3.leon3blk.cpu[0].leon3/vhdl.p0/c0mmu/a0/i___262_i_1} {ahb0/sn2.rs[addr][19]_i_1} {ahb0/tb0.tpf.tfr[shsel][1]_i_4} {mig_gen.gen_mig.ddrc/rnxt[nxt]_i_3} {mig_gen.gen_mig.ddrc/r[wdf_data_buffer][511]_i_6} mig_gen.gen_mig.ddrc/gen_mig.MCB_inst/u_mig_mig/u_ddr3_clk_ibuf/diff_input_clk.u_ibufg_sys_clk {mig_gen.gen_mig.ddrc/r_reg[int_buffer][673]} {mig_gen.gen_mig.ddrc/r_reg[int_buffer][769]} {leon/l3.leon3blk.cpu[0].leon3/i___356} {leon/l3.leon3blk.cpu[0].leon3/vhdl.p0/c0mmu/a0/i___260_i_1} {ahb0/tb0.tpf.tfr[shsel][1]_i_10} {ahb0/rnxt[haddr_start][7]_i_1} mig_gen.gen_mig.ddrc/gen_mig.MCB_inst/u_mig_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i mig_gen.gen_mig.ddrc/gen_mig.MCB_inst/u_mig_mig/u_ddr3_infrastructure/u_bufg_clkdiv0 {mig_gen.gen_mig.ddrc/r_reg[int_buffer][182]} {mig_gen.gen_mig.ddrc/r_reg[int_buffer][843]} {ahb0/tb0.tpf.tfr[shsel][4]_i_1} {mig_gen.gen_mig.ddrc/r[int_buffer][1022]_i_9} {mig_gen.gen_mig.ddrc/r[int_buffer][1022]_i_1} {mig_gen.gen_mig.ddrc/r[int_buffer][511]_i_1} {mig_gen.gen_mig.ddrc/r_reg[int_buffer][592]} {mig_gen.gen_mig.ddrc/r_reg[int_buffer][752]} {mig_gen.gen_mig.ddrc/r_reg[int_buffer][799]} {mig_gen.gen_mig.ddrc/r_reg[int_buffer][804]} {leon/l3.leon3blk.cpu[0].leon3/i___261} {leon/l3.leon3blk.cpu[0].leon3/vhdl.p0/c0mmu/a0/r_reg[ba]} mig_gen.gen_mig.ddrc/gen_mig.MCB_inst/u_mig_mig/u_ddr3_infrastructure/plle2_i mig_gen.gen_mig.ddrc/gen_mig.MCB_inst/u_mig_mig/u_ddr3_infrastructure/u_bufh_pll_clk3 {mig_gen.gen_mig.ddrc/r[int_buffer][1022]_i_3} {mig_gen.gen_mig.ddrc/r_reg[int_buffer][628]} {mig_gen.gen_mig.ddrc/r_reg[int_buffer][650]}]] -clear_locs
INFO: [Vivado 12-3520] Assignment of 'diff_input_clk.u_ibufg_sys_clk, gen_mmcm.mmcm_i, plle2_i, u_bufh_pll_clk3, u_bufg_clkdiv0, rnxt[haddr_start][7]_i_1, sn2.rs[addr][19]_i_1, tb0.tpf.tfr[shsel][4]_i_1, tb0.tpf.tfr[shsel][1]_i_4, tb0.tpf.tfr[shsel][1]_i_10, r_reg[int_buffer][182], r_reg[int_buffer][592], r_reg[int_buffer][628], r_reg[int_buffer][650], r_reg[int_buffer][673], r_reg[int_buffer][752], r_reg[int_buffer][804], r_reg[int_buffer][799], r_reg[int_buffer][769], r_reg[int_buffer][843], r[int_buffer][1022]_i_3, r[int_buffer][1022]_i_9, r[int_buffer][1022]_i_1, r[int_buffer][511]_i_1, rnxt[nxt]_i_3, r[wdf_data_buffer][511]_i_6, i___260_i_1, i___262_i_1, r_reg[ba], i___356, and i___261' to a pblock 'pblock_1' means that all children of 'u_ddr3_clk_ibuf' are in the pblock. Changing the pblock assignment to 'u_ddr3_clk_ibuf'.
endgroup
save_constraints
