# compile verilog/system verilog design source files
verilog xil_defaultlib  --include "../../../../dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ipshared/c923" \
"../../../../dat096_ref_design.ip_user_files/bd/pdm_to_pcm/ip/pdm_to_pcm_clk_wiz_0_0/pdm_to_pcm_clk_wiz_0_0_clk_wiz.v" \
"../../../../dat096_ref_design.ip_user_files/bd/pdm_to_pcm/ip/pdm_to_pcm_clk_wiz_0_0/pdm_to_pcm_clk_wiz_0_0.v" \
"../../../../dat096_ref_design.ip_user_files/bd/pdm_to_pcm/ip/pdm_to_pcm_fifo_generator_0_0/sim/pdm_to_pcm_fifo_generator_0_0.v" \
"../../../../dat096_ref_design.ip_user_files/bd/pdm_to_pcm/ip/pdm_to_pcm_util_vector_logic_0_0/sim/pdm_to_pcm_util_vector_logic_0_0.v" \
"../../../../dat096_ref_design.ip_user_files/bd/pdm_to_pcm/ip/pdm_to_pcm_util_vector_logic_0_2/sim/pdm_to_pcm_util_vector_logic_0_2.v" \
"../../../../dat096_ref_design.ip_user_files/bd/pdm_to_pcm/ip/pdm_to_pcm_blk_mem_gen_0_0/sim/pdm_to_pcm_blk_mem_gen_0_0.v" \
"../../../../dat096_ref_design.ip_user_files/bd/pdm_to_pcm/ip/pdm_to_pcm_blk_mem_gen_1_0/sim/pdm_to_pcm_blk_mem_gen_1_0.v" \
"../../../../dat096_ref_design.ip_user_files/bd/pdm_to_pcm/ip/pdm_to_pcm_blk_mem_gen_1_1/sim/pdm_to_pcm_blk_mem_gen_1_1.v" \
"../../../../dat096_ref_design.ip_user_files/bd/pdm_to_pcm/ip/pdm_to_pcm_blk_mem_gen_2_0/sim/pdm_to_pcm_blk_mem_gen_2_0.v" \

# compile glbl module
verilog xil_defaultlib "glbl.v"

# Do not sort compile order
nosort
