-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
-- Date        : Mon May 25 21:23:24 2020
-- Host        : LAPTOP-RJQ3H7G3 running 64-bit major release  (build 9200)
-- Command     : write_vhdl -force -mode funcsim
--               D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_cic_compiler_0_0/pdm_to_pcm_cic_compiler_0_0_sim_netlist.vhdl
-- Design      : pdm_to_pcm_cic_compiler_0_0
-- Purpose     : This VHDL netlist is a functional simulation representation of the design and should not be modified or
--               synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device      : xc7a200tfbg676-2
-- --------------------------------------------------------------------------------
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity pdm_to_pcm_cic_compiler_0_0_cic_compiler_v4_0_14 is
  port (
    aclk : in STD_LOGIC;
    aclken : in STD_LOGIC;
    aresetn : in STD_LOGIC;
    s_axis_config_tdata : in STD_LOGIC_VECTOR ( 0 to 0 );
    s_axis_config_tvalid : in STD_LOGIC;
    s_axis_config_tready : out STD_LOGIC;
    s_axis_data_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
    s_axis_data_tvalid : in STD_LOGIC;
    s_axis_data_tready : out STD_LOGIC;
    s_axis_data_tlast : in STD_LOGIC;
    m_axis_data_tdata : out STD_LOGIC_VECTOR ( 23 downto 0 );
    m_axis_data_tuser : out STD_LOGIC_VECTOR ( 15 downto 0 );
    m_axis_data_tvalid : out STD_LOGIC;
    m_axis_data_tready : in STD_LOGIC;
    m_axis_data_tlast : out STD_LOGIC;
    event_tlast_unexpected : out STD_LOGIC;
    event_tlast_missing : out STD_LOGIC;
    event_halted : out STD_LOGIC
  );
  attribute C_C1 : integer;
  attribute C_C1 of pdm_to_pcm_cic_compiler_0_0_cic_compiler_v4_0_14 : entity is 22;
  attribute C_C2 : integer;
  attribute C_C2 of pdm_to_pcm_cic_compiler_0_0_cic_compiler_v4_0_14 : entity is 22;
  attribute C_C3 : integer;
  attribute C_C3 of pdm_to_pcm_cic_compiler_0_0_cic_compiler_v4_0_14 : entity is 22;
  attribute C_C4 : integer;
  attribute C_C4 of pdm_to_pcm_cic_compiler_0_0_cic_compiler_v4_0_14 : entity is 22;
  attribute C_C5 : integer;
  attribute C_C5 of pdm_to_pcm_cic_compiler_0_0_cic_compiler_v4_0_14 : entity is 22;
  attribute C_C6 : integer;
  attribute C_C6 of pdm_to_pcm_cic_compiler_0_0_cic_compiler_v4_0_14 : entity is 0;
  attribute C_CLK_FREQ : integer;
  attribute C_CLK_FREQ of pdm_to_pcm_cic_compiler_0_0_cic_compiler_v4_0_14 : entity is 4;
  attribute C_COMPONENT_NAME : string;
  attribute C_COMPONENT_NAME of pdm_to_pcm_cic_compiler_0_0_cic_compiler_v4_0_14 : entity is "pdm_to_pcm_cic_compiler_0_0";
  attribute C_DIFF_DELAY : integer;
  attribute C_DIFF_DELAY of pdm_to_pcm_cic_compiler_0_0_cic_compiler_v4_0_14 : entity is 1;
  attribute C_FAMILY : string;
  attribute C_FAMILY of pdm_to_pcm_cic_compiler_0_0_cic_compiler_v4_0_14 : entity is "artix7";
  attribute C_FILTER_TYPE : integer;
  attribute C_FILTER_TYPE of pdm_to_pcm_cic_compiler_0_0_cic_compiler_v4_0_14 : entity is 1;
  attribute C_HAS_ACLKEN : integer;
  attribute C_HAS_ACLKEN of pdm_to_pcm_cic_compiler_0_0_cic_compiler_v4_0_14 : entity is 0;
  attribute C_HAS_ARESETN : integer;
  attribute C_HAS_ARESETN of pdm_to_pcm_cic_compiler_0_0_cic_compiler_v4_0_14 : entity is 0;
  attribute C_HAS_DOUT_TREADY : integer;
  attribute C_HAS_DOUT_TREADY of pdm_to_pcm_cic_compiler_0_0_cic_compiler_v4_0_14 : entity is 1;
  attribute C_HAS_ROUNDING : integer;
  attribute C_HAS_ROUNDING of pdm_to_pcm_cic_compiler_0_0_cic_compiler_v4_0_14 : entity is 0;
  attribute C_I1 : integer;
  attribute C_I1 of pdm_to_pcm_cic_compiler_0_0_cic_compiler_v4_0_14 : entity is 22;
  attribute C_I2 : integer;
  attribute C_I2 of pdm_to_pcm_cic_compiler_0_0_cic_compiler_v4_0_14 : entity is 22;
  attribute C_I3 : integer;
  attribute C_I3 of pdm_to_pcm_cic_compiler_0_0_cic_compiler_v4_0_14 : entity is 22;
  attribute C_I4 : integer;
  attribute C_I4 of pdm_to_pcm_cic_compiler_0_0_cic_compiler_v4_0_14 : entity is 22;
  attribute C_I5 : integer;
  attribute C_I5 of pdm_to_pcm_cic_compiler_0_0_cic_compiler_v4_0_14 : entity is 22;
  attribute C_I6 : integer;
  attribute C_I6 of pdm_to_pcm_cic_compiler_0_0_cic_compiler_v4_0_14 : entity is 0;
  attribute C_INPUT_WIDTH : integer;
  attribute C_INPUT_WIDTH of pdm_to_pcm_cic_compiler_0_0_cic_compiler_v4_0_14 : entity is 2;
  attribute C_MAX_RATE : integer;
  attribute C_MAX_RATE of pdm_to_pcm_cic_compiler_0_0_cic_compiler_v4_0_14 : entity is 16;
  attribute C_MIN_RATE : integer;
  attribute C_MIN_RATE of pdm_to_pcm_cic_compiler_0_0_cic_compiler_v4_0_14 : entity is 16;
  attribute C_M_AXIS_DATA_TDATA_WIDTH : integer;
  attribute C_M_AXIS_DATA_TDATA_WIDTH of pdm_to_pcm_cic_compiler_0_0_cic_compiler_v4_0_14 : entity is 24;
  attribute C_M_AXIS_DATA_TUSER_WIDTH : integer;
  attribute C_M_AXIS_DATA_TUSER_WIDTH of pdm_to_pcm_cic_compiler_0_0_cic_compiler_v4_0_14 : entity is 16;
  attribute C_NUM_CHANNELS : integer;
  attribute C_NUM_CHANNELS of pdm_to_pcm_cic_compiler_0_0_cic_compiler_v4_0_14 : entity is 4;
  attribute C_NUM_STAGES : integer;
  attribute C_NUM_STAGES of pdm_to_pcm_cic_compiler_0_0_cic_compiler_v4_0_14 : entity is 5;
  attribute C_OUTPUT_WIDTH : integer;
  attribute C_OUTPUT_WIDTH of pdm_to_pcm_cic_compiler_0_0_cic_compiler_v4_0_14 : entity is 22;
  attribute C_RATE : integer;
  attribute C_RATE of pdm_to_pcm_cic_compiler_0_0_cic_compiler_v4_0_14 : entity is 16;
  attribute C_RATE_TYPE : integer;
  attribute C_RATE_TYPE of pdm_to_pcm_cic_compiler_0_0_cic_compiler_v4_0_14 : entity is 0;
  attribute C_SAMPLE_FREQ : integer;
  attribute C_SAMPLE_FREQ of pdm_to_pcm_cic_compiler_0_0_cic_compiler_v4_0_14 : entity is 1;
  attribute C_S_AXIS_CONFIG_TDATA_WIDTH : integer;
  attribute C_S_AXIS_CONFIG_TDATA_WIDTH of pdm_to_pcm_cic_compiler_0_0_cic_compiler_v4_0_14 : entity is 1;
  attribute C_S_AXIS_DATA_TDATA_WIDTH : integer;
  attribute C_S_AXIS_DATA_TDATA_WIDTH of pdm_to_pcm_cic_compiler_0_0_cic_compiler_v4_0_14 : entity is 8;
  attribute C_USE_DSP : integer;
  attribute C_USE_DSP of pdm_to_pcm_cic_compiler_0_0_cic_compiler_v4_0_14 : entity is 1;
  attribute C_USE_STREAMING_INTERFACE : integer;
  attribute C_USE_STREAMING_INTERFACE of pdm_to_pcm_cic_compiler_0_0_cic_compiler_v4_0_14 : entity is 1;
  attribute C_XDEVICEFAMILY : string;
  attribute C_XDEVICEFAMILY of pdm_to_pcm_cic_compiler_0_0_cic_compiler_v4_0_14 : entity is "artix7";
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of pdm_to_pcm_cic_compiler_0_0_cic_compiler_v4_0_14 : entity is "cic_compiler_v4_0_14";
  attribute downgradeipidentifiedwarnings : string;
  attribute downgradeipidentifiedwarnings of pdm_to_pcm_cic_compiler_0_0_cic_compiler_v4_0_14 : entity is "yes";
end pdm_to_pcm_cic_compiler_0_0_cic_compiler_v4_0_14;

architecture STRUCTURE of pdm_to_pcm_cic_compiler_0_0_cic_compiler_v4_0_14 is
  signal \<const0>\ : STD_LOGIC;
  signal \^m_axis_data_tdata\ : STD_LOGIC_VECTOR ( 21 downto 0 );
  signal \^m_axis_data_tuser\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal NLW_i_synth_s_axis_config_tready_UNCONNECTED : STD_LOGIC;
  signal NLW_i_synth_m_axis_data_tdata_UNCONNECTED : STD_LOGIC_VECTOR ( 22 downto 21 );
  signal NLW_i_synth_m_axis_data_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 2 );
  attribute C_C1 of i_synth : label is 22;
  attribute C_C2 of i_synth : label is 22;
  attribute C_C3 of i_synth : label is 22;
  attribute C_C4 of i_synth : label is 22;
  attribute C_C5 of i_synth : label is 22;
  attribute C_C6 of i_synth : label is 0;
  attribute C_CLK_FREQ of i_synth : label is 4;
  attribute C_COMPONENT_NAME of i_synth : label is "pdm_to_pcm_cic_compiler_0_0";
  attribute C_DIFF_DELAY of i_synth : label is 1;
  attribute C_FAMILY of i_synth : label is "artix7";
  attribute C_FILTER_TYPE of i_synth : label is 1;
  attribute C_HAS_ACLKEN of i_synth : label is 0;
  attribute C_HAS_ARESETN of i_synth : label is 0;
  attribute C_HAS_DOUT_TREADY of i_synth : label is 1;
  attribute C_HAS_ROUNDING of i_synth : label is 0;
  attribute C_I1 of i_synth : label is 22;
  attribute C_I2 of i_synth : label is 22;
  attribute C_I3 of i_synth : label is 22;
  attribute C_I4 of i_synth : label is 22;
  attribute C_I5 of i_synth : label is 22;
  attribute C_I6 of i_synth : label is 0;
  attribute C_INPUT_WIDTH of i_synth : label is 2;
  attribute C_MAX_RATE of i_synth : label is 16;
  attribute C_MIN_RATE of i_synth : label is 16;
  attribute C_M_AXIS_DATA_TDATA_WIDTH of i_synth : label is 24;
  attribute C_M_AXIS_DATA_TUSER_WIDTH of i_synth : label is 16;
  attribute C_NUM_CHANNELS of i_synth : label is 4;
  attribute C_NUM_STAGES of i_synth : label is 5;
  attribute C_OUTPUT_WIDTH of i_synth : label is 22;
  attribute C_RATE of i_synth : label is 16;
  attribute C_RATE_TYPE of i_synth : label is 0;
  attribute C_SAMPLE_FREQ of i_synth : label is 1;
  attribute C_S_AXIS_CONFIG_TDATA_WIDTH of i_synth : label is 1;
  attribute C_S_AXIS_DATA_TDATA_WIDTH of i_synth : label is 8;
  attribute C_USE_DSP of i_synth : label is 1;
  attribute C_USE_STREAMING_INTERFACE of i_synth : label is 1;
  attribute C_XDEVICEFAMILY of i_synth : label is "artix7";
  attribute downgradeipidentifiedwarnings of i_synth : label is "yes";
begin
  m_axis_data_tdata(23) <= \^m_axis_data_tdata\(21);
  m_axis_data_tdata(22) <= \^m_axis_data_tdata\(21);
  m_axis_data_tdata(21 downto 0) <= \^m_axis_data_tdata\(21 downto 0);
  m_axis_data_tuser(15) <= \<const0>\;
  m_axis_data_tuser(14) <= \<const0>\;
  m_axis_data_tuser(13) <= \<const0>\;
  m_axis_data_tuser(12) <= \<const0>\;
  m_axis_data_tuser(11) <= \<const0>\;
  m_axis_data_tuser(10) <= \<const0>\;
  m_axis_data_tuser(9) <= \<const0>\;
  m_axis_data_tuser(8) <= \^m_axis_data_tuser\(8);
  m_axis_data_tuser(7) <= \<const0>\;
  m_axis_data_tuser(6) <= \<const0>\;
  m_axis_data_tuser(5) <= \<const0>\;
  m_axis_data_tuser(4) <= \<const0>\;
  m_axis_data_tuser(3) <= \<const0>\;
  m_axis_data_tuser(2) <= \<const0>\;
  m_axis_data_tuser(1 downto 0) <= \^m_axis_data_tuser\(1 downto 0);
  s_axis_config_tready <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
i_synth: entity work.pdm_to_pcm_cic_compiler_0_0_cic_compiler_v4_0_14_viv
     port map (
      aclk => aclk,
      aclken => '0',
      aresetn => '0',
      event_halted => event_halted,
      event_tlast_missing => event_tlast_missing,
      event_tlast_unexpected => event_tlast_unexpected,
      m_axis_data_tdata(23) => \^m_axis_data_tdata\(21),
      m_axis_data_tdata(22 downto 21) => NLW_i_synth_m_axis_data_tdata_UNCONNECTED(22 downto 21),
      m_axis_data_tdata(20 downto 0) => \^m_axis_data_tdata\(20 downto 0),
      m_axis_data_tlast => m_axis_data_tlast,
      m_axis_data_tready => m_axis_data_tready,
      m_axis_data_tuser(15 downto 9) => NLW_i_synth_m_axis_data_tuser_UNCONNECTED(15 downto 9),
      m_axis_data_tuser(8) => \^m_axis_data_tuser\(8),
      m_axis_data_tuser(7 downto 2) => NLW_i_synth_m_axis_data_tuser_UNCONNECTED(7 downto 2),
      m_axis_data_tuser(1 downto 0) => \^m_axis_data_tuser\(1 downto 0),
      m_axis_data_tvalid => m_axis_data_tvalid,
      s_axis_config_tdata(0) => '0',
      s_axis_config_tready => NLW_i_synth_s_axis_config_tready_UNCONNECTED,
      s_axis_config_tvalid => '0',
      s_axis_data_tdata(7 downto 2) => B"000000",
      s_axis_data_tdata(1 downto 0) => s_axis_data_tdata(1 downto 0),
      s_axis_data_tlast => s_axis_data_tlast,
      s_axis_data_tready => s_axis_data_tready,
      s_axis_data_tvalid => s_axis_data_tvalid
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity pdm_to_pcm_cic_compiler_0_0 is
  port (
    aclk : in STD_LOGIC;
    s_axis_data_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
    s_axis_data_tvalid : in STD_LOGIC;
    s_axis_data_tready : out STD_LOGIC;
    s_axis_data_tlast : in STD_LOGIC;
    m_axis_data_tdata : out STD_LOGIC_VECTOR ( 23 downto 0 );
    m_axis_data_tuser : out STD_LOGIC_VECTOR ( 15 downto 0 );
    m_axis_data_tvalid : out STD_LOGIC;
    m_axis_data_tready : in STD_LOGIC;
    m_axis_data_tlast : out STD_LOGIC;
    event_tlast_unexpected : out STD_LOGIC;
    event_tlast_missing : out STD_LOGIC;
    event_halted : out STD_LOGIC
  );
  attribute NotValidForBitStream : boolean;
  attribute NotValidForBitStream of pdm_to_pcm_cic_compiler_0_0 : entity is true;
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of pdm_to_pcm_cic_compiler_0_0 : entity is "pdm_to_pcm_cic_compiler_0_0,cic_compiler_v4_0_14,{}";
  attribute downgradeipidentifiedwarnings : string;
  attribute downgradeipidentifiedwarnings of pdm_to_pcm_cic_compiler_0_0 : entity is "yes";
  attribute x_core_info : string;
  attribute x_core_info of pdm_to_pcm_cic_compiler_0_0 : entity is "cic_compiler_v4_0_14,Vivado 2019.1";
end pdm_to_pcm_cic_compiler_0_0;

architecture STRUCTURE of pdm_to_pcm_cic_compiler_0_0 is
  signal NLW_U0_s_axis_config_tready_UNCONNECTED : STD_LOGIC;
  attribute C_C1 : integer;
  attribute C_C1 of U0 : label is 22;
  attribute C_C2 : integer;
  attribute C_C2 of U0 : label is 22;
  attribute C_C3 : integer;
  attribute C_C3 of U0 : label is 22;
  attribute C_C4 : integer;
  attribute C_C4 of U0 : label is 22;
  attribute C_C5 : integer;
  attribute C_C5 of U0 : label is 22;
  attribute C_C6 : integer;
  attribute C_C6 of U0 : label is 0;
  attribute C_CLK_FREQ : integer;
  attribute C_CLK_FREQ of U0 : label is 4;
  attribute C_COMPONENT_NAME : string;
  attribute C_COMPONENT_NAME of U0 : label is "pdm_to_pcm_cic_compiler_0_0";
  attribute C_DIFF_DELAY : integer;
  attribute C_DIFF_DELAY of U0 : label is 1;
  attribute C_FAMILY : string;
  attribute C_FAMILY of U0 : label is "artix7";
  attribute C_FILTER_TYPE : integer;
  attribute C_FILTER_TYPE of U0 : label is 1;
  attribute C_HAS_ACLKEN : integer;
  attribute C_HAS_ACLKEN of U0 : label is 0;
  attribute C_HAS_ARESETN : integer;
  attribute C_HAS_ARESETN of U0 : label is 0;
  attribute C_HAS_DOUT_TREADY : integer;
  attribute C_HAS_DOUT_TREADY of U0 : label is 1;
  attribute C_HAS_ROUNDING : integer;
  attribute C_HAS_ROUNDING of U0 : label is 0;
  attribute C_I1 : integer;
  attribute C_I1 of U0 : label is 22;
  attribute C_I2 : integer;
  attribute C_I2 of U0 : label is 22;
  attribute C_I3 : integer;
  attribute C_I3 of U0 : label is 22;
  attribute C_I4 : integer;
  attribute C_I4 of U0 : label is 22;
  attribute C_I5 : integer;
  attribute C_I5 of U0 : label is 22;
  attribute C_I6 : integer;
  attribute C_I6 of U0 : label is 0;
  attribute C_INPUT_WIDTH : integer;
  attribute C_INPUT_WIDTH of U0 : label is 2;
  attribute C_MAX_RATE : integer;
  attribute C_MAX_RATE of U0 : label is 16;
  attribute C_MIN_RATE : integer;
  attribute C_MIN_RATE of U0 : label is 16;
  attribute C_M_AXIS_DATA_TDATA_WIDTH : integer;
  attribute C_M_AXIS_DATA_TDATA_WIDTH of U0 : label is 24;
  attribute C_M_AXIS_DATA_TUSER_WIDTH : integer;
  attribute C_M_AXIS_DATA_TUSER_WIDTH of U0 : label is 16;
  attribute C_NUM_CHANNELS : integer;
  attribute C_NUM_CHANNELS of U0 : label is 4;
  attribute C_NUM_STAGES : integer;
  attribute C_NUM_STAGES of U0 : label is 5;
  attribute C_OUTPUT_WIDTH : integer;
  attribute C_OUTPUT_WIDTH of U0 : label is 22;
  attribute C_RATE : integer;
  attribute C_RATE of U0 : label is 16;
  attribute C_RATE_TYPE : integer;
  attribute C_RATE_TYPE of U0 : label is 0;
  attribute C_SAMPLE_FREQ : integer;
  attribute C_SAMPLE_FREQ of U0 : label is 1;
  attribute C_S_AXIS_CONFIG_TDATA_WIDTH : integer;
  attribute C_S_AXIS_CONFIG_TDATA_WIDTH of U0 : label is 1;
  attribute C_S_AXIS_DATA_TDATA_WIDTH : integer;
  attribute C_S_AXIS_DATA_TDATA_WIDTH of U0 : label is 8;
  attribute C_USE_DSP : integer;
  attribute C_USE_DSP of U0 : label is 1;
  attribute C_USE_STREAMING_INTERFACE : integer;
  attribute C_USE_STREAMING_INTERFACE of U0 : label is 1;
  attribute C_XDEVICEFAMILY : string;
  attribute C_XDEVICEFAMILY of U0 : label is "artix7";
  attribute downgradeipidentifiedwarnings of U0 : label is "yes";
  attribute x_interface_info : string;
  attribute x_interface_info of aclk : signal is "xilinx.com:signal:clock:1.0 aclk_intf CLK";
  attribute x_interface_parameter : string;
  attribute x_interface_parameter of aclk : signal is "XIL_INTERFACENAME aclk_intf, ASSOCIATED_BUSIF S_AXIS_CONFIG:M_AXIS_DATA:S_AXIS_DATA, ASSOCIATED_RESET aresetn, ASSOCIATED_CLKEN aclken, FREQ_HZ 18431963, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, INSERT_VIP 0";
  attribute x_interface_info of event_halted : signal is "xilinx.com:signal:interrupt:1.0 event_halted_intf INTERRUPT";
  attribute x_interface_parameter of event_halted : signal is "XIL_INTERFACENAME event_halted_intf, SENSITIVITY EDGE_RISING, PortWidth 1";
  attribute x_interface_info of event_tlast_missing : signal is "xilinx.com:signal:interrupt:1.0 event_tlast_missing_intf INTERRUPT";
  attribute x_interface_parameter of event_tlast_missing : signal is "XIL_INTERFACENAME event_tlast_missing_intf, SENSITIVITY EDGE_RISING, PortWidth 1";
  attribute x_interface_info of event_tlast_unexpected : signal is "xilinx.com:signal:interrupt:1.0 event_tlast_unexpected_intf INTERRUPT";
  attribute x_interface_parameter of event_tlast_unexpected : signal is "XIL_INTERFACENAME event_tlast_unexpected_intf, SENSITIVITY EDGE_RISING, PortWidth 1";
  attribute x_interface_info of m_axis_data_tlast : signal is "xilinx.com:interface:axis:1.0 M_AXIS_DATA TLAST";
  attribute x_interface_info of m_axis_data_tready : signal is "xilinx.com:interface:axis:1.0 M_AXIS_DATA TREADY";
  attribute x_interface_info of m_axis_data_tvalid : signal is "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
  attribute x_interface_info of s_axis_data_tlast : signal is "xilinx.com:interface:axis:1.0 S_AXIS_DATA TLAST";
  attribute x_interface_info of s_axis_data_tready : signal is "xilinx.com:interface:axis:1.0 S_AXIS_DATA TREADY";
  attribute x_interface_info of s_axis_data_tvalid : signal is "xilinx.com:interface:axis:1.0 S_AXIS_DATA TVALID";
  attribute x_interface_info of m_axis_data_tdata : signal is "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
  attribute x_interface_parameter of m_axis_data_tdata : signal is "XIL_INTERFACENAME M_AXIS_DATA, TDATA_NUM_BYTES 3, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 16, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 18431963, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {TDATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type automatic dependency {} format long minimum {} maximum {}} value 94} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} array_type {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value chan} size {attribs {resolve_type generated dependency chan_size format long minimum {} maximum {}} value 4} stride {attribs {resolve_type generated dependency chan_stride format long minimum {} maximum {}} value 24} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency data_width format long minimum {} maximum {}} value 22} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type generated dependency data_fractwidth format long minimum {} maximum {}} value 0} signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value true}}}}}}} TDATA_WIDTH 24 TUSER {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type automatic dependency {} format long minimum {} maximum {}} value 9} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} struct {field_chan_out {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value chan_out} enabled {attribs {resolve_type generated dependency enabled format bool minimum {} maximum {}} value true} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency chan_out_width format long minimum {} maximum {}} value 2} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} integer {signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value false}}}} field_chan_sync {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value chan_sync} enabled {attribs {resolve_type generated dependency enabled format bool minimum {} maximum {}} value true} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency chan_sync_width format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type generated dependency chan_sync_offset format long minimum {} maximum {}} value 8}}}}}} TUSER_WIDTH 16}, INSERT_VIP 0";
  attribute x_interface_info of m_axis_data_tuser : signal is "xilinx.com:interface:axis:1.0 M_AXIS_DATA TUSER";
  attribute x_interface_info of s_axis_data_tdata : signal is "xilinx.com:interface:axis:1.0 S_AXIS_DATA TDATA";
  attribute x_interface_parameter of s_axis_data_tdata : signal is "XIL_INTERFACENAME S_AXIS_DATA, TDATA_NUM_BYTES 1, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 18431963, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, LAYERED_METADATA undef, INSERT_VIP 0";
begin
U0: entity work.pdm_to_pcm_cic_compiler_0_0_cic_compiler_v4_0_14
     port map (
      aclk => aclk,
      aclken => '1',
      aresetn => '1',
      event_halted => event_halted,
      event_tlast_missing => event_tlast_missing,
      event_tlast_unexpected => event_tlast_unexpected,
      m_axis_data_tdata(23 downto 0) => m_axis_data_tdata(23 downto 0),
      m_axis_data_tlast => m_axis_data_tlast,
      m_axis_data_tready => m_axis_data_tready,
      m_axis_data_tuser(15 downto 0) => m_axis_data_tuser(15 downto 0),
      m_axis_data_tvalid => m_axis_data_tvalid,
      s_axis_config_tdata(0) => '0',
      s_axis_config_tready => NLW_U0_s_axis_config_tready_UNCONNECTED,
      s_axis_config_tvalid => '0',
      s_axis_data_tdata(7 downto 0) => s_axis_data_tdata(7 downto 0),
      s_axis_data_tlast => s_axis_data_tlast,
      s_axis_data_tready => s_axis_data_tready,
      s_axis_data_tvalid => s_axis_data_tvalid
    );
end STRUCTURE;
