-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
-- Date        : Mon May 25 02:55:18 2020
-- Host        : LAPTOP-RJQ3H7G3 running 64-bit major release  (build 9200)
-- Command     : write_vhdl -force -mode funcsim
--               D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_energy_compare_0_0/pdm_to_pcm_energy_compare_0_0_sim_netlist.vhdl
-- Design      : pdm_to_pcm_energy_compare_0_0
-- Purpose     : This VHDL netlist is a functional simulation representation of the design and should not be modified or
--               synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device      : xc7a200tfbg676-2
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity pdm_to_pcm_energy_compare_0_0_energy_compare is
  port (
    max_found : out STD_LOGIC;
    start_fifo : out STD_LOGIC;
    rst : out STD_LOGIC;
    start : in STD_LOGIC;
    clk : in STD_LOGIC;
    val_in : in STD_LOGIC_VECTOR ( 31 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of pdm_to_pcm_energy_compare_0_0_energy_compare : entity is "energy_compare";
end pdm_to_pcm_energy_compare_0_0_energy_compare;

architecture STRUCTURE of pdm_to_pcm_energy_compare_0_0_energy_compare is
  signal \FSM_onehot_state[0]_i_1_n_1\ : STD_LOGIC;
  signal \FSM_onehot_state[0]_i_2_n_1\ : STD_LOGIC;
  signal \FSM_onehot_state[1]_i_1_n_1\ : STD_LOGIC;
  signal \FSM_onehot_state[1]_i_2_n_1\ : STD_LOGIC;
  signal \FSM_onehot_state[1]_i_3_n_1\ : STD_LOGIC;
  signal \FSM_onehot_state[2]_i_1_n_1\ : STD_LOGIC;
  signal \FSM_onehot_state_reg_n_1_[1]\ : STD_LOGIC;
  signal \FSM_onehot_state_reg_n_1_[2]\ : STD_LOGIC;
  signal data1 : STD_LOGIC_VECTOR ( 31 downto 1 );
  signal fifo_reset : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \fifo_reset[0]_i_1_n_1\ : STD_LOGIC;
  signal i : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal \i0_carry__0_n_1\ : STD_LOGIC;
  signal \i0_carry__0_n_2\ : STD_LOGIC;
  signal \i0_carry__0_n_3\ : STD_LOGIC;
  signal \i0_carry__0_n_4\ : STD_LOGIC;
  signal \i0_carry__1_n_1\ : STD_LOGIC;
  signal \i0_carry__1_n_2\ : STD_LOGIC;
  signal \i0_carry__1_n_3\ : STD_LOGIC;
  signal \i0_carry__1_n_4\ : STD_LOGIC;
  signal \i0_carry__2_n_1\ : STD_LOGIC;
  signal \i0_carry__2_n_2\ : STD_LOGIC;
  signal \i0_carry__2_n_3\ : STD_LOGIC;
  signal \i0_carry__2_n_4\ : STD_LOGIC;
  signal \i0_carry__3_n_1\ : STD_LOGIC;
  signal \i0_carry__3_n_2\ : STD_LOGIC;
  signal \i0_carry__3_n_3\ : STD_LOGIC;
  signal \i0_carry__3_n_4\ : STD_LOGIC;
  signal \i0_carry__4_n_1\ : STD_LOGIC;
  signal \i0_carry__4_n_2\ : STD_LOGIC;
  signal \i0_carry__4_n_3\ : STD_LOGIC;
  signal \i0_carry__4_n_4\ : STD_LOGIC;
  signal \i0_carry__5_n_1\ : STD_LOGIC;
  signal \i0_carry__5_n_2\ : STD_LOGIC;
  signal \i0_carry__5_n_3\ : STD_LOGIC;
  signal \i0_carry__5_n_4\ : STD_LOGIC;
  signal \i0_carry__6_n_3\ : STD_LOGIC;
  signal \i0_carry__6_n_4\ : STD_LOGIC;
  signal i0_carry_n_1 : STD_LOGIC;
  signal i0_carry_n_2 : STD_LOGIC;
  signal i0_carry_n_3 : STD_LOGIC;
  signal i0_carry_n_4 : STD_LOGIC;
  signal \i[0]_i_1_n_1\ : STD_LOGIC;
  signal \i[10]_i_1_n_1\ : STD_LOGIC;
  signal \i[11]_i_1_n_1\ : STD_LOGIC;
  signal \i[12]_i_1_n_1\ : STD_LOGIC;
  signal \i[13]_i_1_n_1\ : STD_LOGIC;
  signal \i[14]_i_1_n_1\ : STD_LOGIC;
  signal \i[15]_i_1_n_1\ : STD_LOGIC;
  signal \i[16]_i_1_n_1\ : STD_LOGIC;
  signal \i[17]_i_1_n_1\ : STD_LOGIC;
  signal \i[18]_i_1_n_1\ : STD_LOGIC;
  signal \i[19]_i_1_n_1\ : STD_LOGIC;
  signal \i[1]_i_1_n_1\ : STD_LOGIC;
  signal \i[20]_i_1_n_1\ : STD_LOGIC;
  signal \i[21]_i_1_n_1\ : STD_LOGIC;
  signal \i[22]_i_1_n_1\ : STD_LOGIC;
  signal \i[23]_i_1_n_1\ : STD_LOGIC;
  signal \i[24]_i_1_n_1\ : STD_LOGIC;
  signal \i[25]_i_1_n_1\ : STD_LOGIC;
  signal \i[26]_i_1_n_1\ : STD_LOGIC;
  signal \i[27]_i_1_n_1\ : STD_LOGIC;
  signal \i[28]_i_1_n_1\ : STD_LOGIC;
  signal \i[29]_i_1_n_1\ : STD_LOGIC;
  signal \i[2]_i_1_n_1\ : STD_LOGIC;
  signal \i[30]_i_1_n_1\ : STD_LOGIC;
  signal \i[31]_i_2_n_1\ : STD_LOGIC;
  signal \i[3]_i_1_n_1\ : STD_LOGIC;
  signal \i[4]_i_1_n_1\ : STD_LOGIC;
  signal \i[5]_i_1_n_1\ : STD_LOGIC;
  signal \i[6]_i_1_n_1\ : STD_LOGIC;
  signal \i[7]_i_1_n_1\ : STD_LOGIC;
  signal \i[8]_i_1_n_1\ : STD_LOGIC;
  signal \i[9]_i_1_n_1\ : STD_LOGIC;
  signal i_0 : STD_LOGIC;
  signal \i__carry__0_i_1_n_1\ : STD_LOGIC;
  signal \i__carry__0_i_2_n_1\ : STD_LOGIC;
  signal \i__carry__0_i_3_n_1\ : STD_LOGIC;
  signal \i__carry__0_i_4_n_1\ : STD_LOGIC;
  signal \i__carry__0_i_5_n_1\ : STD_LOGIC;
  signal \i__carry__0_i_6_n_1\ : STD_LOGIC;
  signal \i__carry__0_i_7_n_1\ : STD_LOGIC;
  signal \i__carry__0_i_8_n_1\ : STD_LOGIC;
  signal \i__carry__1_i_1_n_1\ : STD_LOGIC;
  signal \i__carry__1_i_2_n_1\ : STD_LOGIC;
  signal \i__carry__1_i_3_n_1\ : STD_LOGIC;
  signal \i__carry__1_i_4_n_1\ : STD_LOGIC;
  signal \i__carry__1_i_5_n_1\ : STD_LOGIC;
  signal \i__carry__1_i_6_n_1\ : STD_LOGIC;
  signal \i__carry__1_i_7_n_1\ : STD_LOGIC;
  signal \i__carry__1_i_8_n_1\ : STD_LOGIC;
  signal \i__carry__2_i_1_n_1\ : STD_LOGIC;
  signal \i__carry__2_i_2_n_1\ : STD_LOGIC;
  signal \i__carry__2_i_3_n_1\ : STD_LOGIC;
  signal \i__carry__2_i_4_n_1\ : STD_LOGIC;
  signal \i__carry__2_i_5_n_1\ : STD_LOGIC;
  signal \i__carry__2_i_6_n_1\ : STD_LOGIC;
  signal \i__carry__2_i_7_n_1\ : STD_LOGIC;
  signal \i__carry__2_i_8_n_1\ : STD_LOGIC;
  signal \i__carry_i_1_n_1\ : STD_LOGIC;
  signal \i__carry_i_2_n_1\ : STD_LOGIC;
  signal \i__carry_i_3_n_1\ : STD_LOGIC;
  signal \i__carry_i_4_n_1\ : STD_LOGIC;
  signal \i__carry_i_5_n_1\ : STD_LOGIC;
  signal \i__carry_i_6_n_1\ : STD_LOGIC;
  signal \i__carry_i_7_n_1\ : STD_LOGIC;
  signal \i__carry_i_8_n_1\ : STD_LOGIC;
  signal in3 : STD_LOGIC_VECTOR ( 31 downto 1 );
  signal \in3__0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal j : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal \j0_carry__0_n_1\ : STD_LOGIC;
  signal \j0_carry__0_n_2\ : STD_LOGIC;
  signal \j0_carry__0_n_3\ : STD_LOGIC;
  signal \j0_carry__0_n_4\ : STD_LOGIC;
  signal \j0_carry__1_n_1\ : STD_LOGIC;
  signal \j0_carry__1_n_2\ : STD_LOGIC;
  signal \j0_carry__1_n_3\ : STD_LOGIC;
  signal \j0_carry__1_n_4\ : STD_LOGIC;
  signal \j0_carry__2_n_1\ : STD_LOGIC;
  signal \j0_carry__2_n_2\ : STD_LOGIC;
  signal \j0_carry__2_n_3\ : STD_LOGIC;
  signal \j0_carry__2_n_4\ : STD_LOGIC;
  signal \j0_carry__3_n_1\ : STD_LOGIC;
  signal \j0_carry__3_n_2\ : STD_LOGIC;
  signal \j0_carry__3_n_3\ : STD_LOGIC;
  signal \j0_carry__3_n_4\ : STD_LOGIC;
  signal \j0_carry__4_n_1\ : STD_LOGIC;
  signal \j0_carry__4_n_2\ : STD_LOGIC;
  signal \j0_carry__4_n_3\ : STD_LOGIC;
  signal \j0_carry__4_n_4\ : STD_LOGIC;
  signal \j0_carry__5_n_1\ : STD_LOGIC;
  signal \j0_carry__5_n_2\ : STD_LOGIC;
  signal \j0_carry__5_n_3\ : STD_LOGIC;
  signal \j0_carry__5_n_4\ : STD_LOGIC;
  signal \j0_carry__6_n_3\ : STD_LOGIC;
  signal \j0_carry__6_n_4\ : STD_LOGIC;
  signal j0_carry_n_1 : STD_LOGIC;
  signal j0_carry_n_2 : STD_LOGIC;
  signal j0_carry_n_3 : STD_LOGIC;
  signal j0_carry_n_4 : STD_LOGIC;
  signal \j1_carry__0_i_1_n_1\ : STD_LOGIC;
  signal \j1_carry__0_i_2_n_1\ : STD_LOGIC;
  signal \j1_carry__0_i_3_n_1\ : STD_LOGIC;
  signal \j1_carry__0_i_4_n_1\ : STD_LOGIC;
  signal \j1_carry__0_n_1\ : STD_LOGIC;
  signal \j1_carry__0_n_2\ : STD_LOGIC;
  signal \j1_carry__0_n_3\ : STD_LOGIC;
  signal \j1_carry__0_n_4\ : STD_LOGIC;
  signal \j1_carry__1_i_1_n_1\ : STD_LOGIC;
  signal \j1_carry__1_i_2_n_1\ : STD_LOGIC;
  signal \j1_carry__1_i_3_n_1\ : STD_LOGIC;
  signal \j1_carry__1_n_3\ : STD_LOGIC;
  signal \j1_carry__1_n_4\ : STD_LOGIC;
  signal j1_carry_i_1_n_1 : STD_LOGIC;
  signal j1_carry_i_2_n_1 : STD_LOGIC;
  signal j1_carry_i_3_n_1 : STD_LOGIC;
  signal j1_carry_i_4_n_1 : STD_LOGIC;
  signal j1_carry_n_1 : STD_LOGIC;
  signal j1_carry_n_2 : STD_LOGIC;
  signal j1_carry_n_3 : STD_LOGIC;
  signal j1_carry_n_4 : STD_LOGIC;
  signal \j[31]_i_1_n_1\ : STD_LOGIC;
  signal \j[31]_i_2_n_1\ : STD_LOGIC;
  signal \^max_found\ : STD_LOGIC;
  signal max_found1 : STD_LOGIC;
  signal max_found12_in : STD_LOGIC;
  signal \max_found1_carry__0_i_1_n_1\ : STD_LOGIC;
  signal \max_found1_carry__0_i_2_n_1\ : STD_LOGIC;
  signal \max_found1_carry__0_i_3_n_1\ : STD_LOGIC;
  signal \max_found1_carry__0_i_4_n_1\ : STD_LOGIC;
  signal \max_found1_carry__0_i_5_n_1\ : STD_LOGIC;
  signal \max_found1_carry__0_i_6_n_1\ : STD_LOGIC;
  signal \max_found1_carry__0_i_7_n_1\ : STD_LOGIC;
  signal \max_found1_carry__0_i_8_n_1\ : STD_LOGIC;
  signal \max_found1_carry__0_n_1\ : STD_LOGIC;
  signal \max_found1_carry__0_n_2\ : STD_LOGIC;
  signal \max_found1_carry__0_n_3\ : STD_LOGIC;
  signal \max_found1_carry__0_n_4\ : STD_LOGIC;
  signal \max_found1_carry__1_i_1_n_1\ : STD_LOGIC;
  signal \max_found1_carry__1_i_2_n_1\ : STD_LOGIC;
  signal \max_found1_carry__1_i_3_n_1\ : STD_LOGIC;
  signal \max_found1_carry__1_i_4_n_1\ : STD_LOGIC;
  signal \max_found1_carry__1_i_5_n_1\ : STD_LOGIC;
  signal \max_found1_carry__1_i_6_n_1\ : STD_LOGIC;
  signal \max_found1_carry__1_i_7_n_1\ : STD_LOGIC;
  signal \max_found1_carry__1_i_8_n_1\ : STD_LOGIC;
  signal \max_found1_carry__1_n_1\ : STD_LOGIC;
  signal \max_found1_carry__1_n_2\ : STD_LOGIC;
  signal \max_found1_carry__1_n_3\ : STD_LOGIC;
  signal \max_found1_carry__1_n_4\ : STD_LOGIC;
  signal \max_found1_carry__2_i_1_n_1\ : STD_LOGIC;
  signal \max_found1_carry__2_i_2_n_1\ : STD_LOGIC;
  signal \max_found1_carry__2_i_3_n_1\ : STD_LOGIC;
  signal \max_found1_carry__2_i_4_n_1\ : STD_LOGIC;
  signal \max_found1_carry__2_i_5_n_1\ : STD_LOGIC;
  signal \max_found1_carry__2_i_6_n_1\ : STD_LOGIC;
  signal \max_found1_carry__2_i_7_n_1\ : STD_LOGIC;
  signal \max_found1_carry__2_i_8_n_1\ : STD_LOGIC;
  signal \max_found1_carry__2_n_2\ : STD_LOGIC;
  signal \max_found1_carry__2_n_3\ : STD_LOGIC;
  signal \max_found1_carry__2_n_4\ : STD_LOGIC;
  signal max_found1_carry_i_1_n_1 : STD_LOGIC;
  signal max_found1_carry_i_2_n_1 : STD_LOGIC;
  signal max_found1_carry_i_3_n_1 : STD_LOGIC;
  signal max_found1_carry_i_4_n_1 : STD_LOGIC;
  signal max_found1_carry_i_5_n_1 : STD_LOGIC;
  signal max_found1_carry_i_6_n_1 : STD_LOGIC;
  signal max_found1_carry_i_7_n_1 : STD_LOGIC;
  signal max_found1_carry_i_8_n_1 : STD_LOGIC;
  signal max_found1_carry_n_1 : STD_LOGIC;
  signal max_found1_carry_n_2 : STD_LOGIC;
  signal max_found1_carry_n_3 : STD_LOGIC;
  signal max_found1_carry_n_4 : STD_LOGIC;
  signal \max_found1_inferred__0/i__carry__0_n_1\ : STD_LOGIC;
  signal \max_found1_inferred__0/i__carry__0_n_2\ : STD_LOGIC;
  signal \max_found1_inferred__0/i__carry__0_n_3\ : STD_LOGIC;
  signal \max_found1_inferred__0/i__carry__0_n_4\ : STD_LOGIC;
  signal \max_found1_inferred__0/i__carry__1_n_1\ : STD_LOGIC;
  signal \max_found1_inferred__0/i__carry__1_n_2\ : STD_LOGIC;
  signal \max_found1_inferred__0/i__carry__1_n_3\ : STD_LOGIC;
  signal \max_found1_inferred__0/i__carry__1_n_4\ : STD_LOGIC;
  signal \max_found1_inferred__0/i__carry__2_n_2\ : STD_LOGIC;
  signal \max_found1_inferred__0/i__carry__2_n_3\ : STD_LOGIC;
  signal \max_found1_inferred__0/i__carry__2_n_4\ : STD_LOGIC;
  signal \max_found1_inferred__0/i__carry_n_1\ : STD_LOGIC;
  signal \max_found1_inferred__0/i__carry_n_2\ : STD_LOGIC;
  signal \max_found1_inferred__0/i__carry_n_3\ : STD_LOGIC;
  signal \max_found1_inferred__0/i__carry_n_4\ : STD_LOGIC;
  signal max_found_i_1_n_1 : STD_LOGIC;
  signal p_0_in : STD_LOGIC;
  signal resig : STD_LOGIC;
  signal resig_i_1_n_1 : STD_LOGIC;
  signal resig_reg_n_1 : STD_LOGIC;
  signal \^rst\ : STD_LOGIC;
  signal rst_i_1_n_1 : STD_LOGIC;
  signal \^start_fifo\ : STD_LOGIC;
  signal start_fifo_i_1_n_1 : STD_LOGIC;
  signal \state0_carry__0_i_1_n_1\ : STD_LOGIC;
  signal \state0_carry__0_i_2_n_1\ : STD_LOGIC;
  signal \state0_carry__0_i_3_n_1\ : STD_LOGIC;
  signal \state0_carry__0_i_4_n_1\ : STD_LOGIC;
  signal \state0_carry__0_i_5_n_1\ : STD_LOGIC;
  signal \state0_carry__0_i_6_n_1\ : STD_LOGIC;
  signal \state0_carry__0_i_7_n_1\ : STD_LOGIC;
  signal \state0_carry__0_i_8_n_1\ : STD_LOGIC;
  signal \state0_carry__0_n_1\ : STD_LOGIC;
  signal \state0_carry__0_n_2\ : STD_LOGIC;
  signal \state0_carry__0_n_3\ : STD_LOGIC;
  signal \state0_carry__0_n_4\ : STD_LOGIC;
  signal \state0_carry__1_i_1_n_1\ : STD_LOGIC;
  signal \state0_carry__1_i_2_n_1\ : STD_LOGIC;
  signal \state0_carry__1_i_3_n_1\ : STD_LOGIC;
  signal \state0_carry__1_i_4_n_1\ : STD_LOGIC;
  signal \state0_carry__1_i_5_n_1\ : STD_LOGIC;
  signal \state0_carry__1_i_6_n_1\ : STD_LOGIC;
  signal \state0_carry__1_i_7_n_1\ : STD_LOGIC;
  signal \state0_carry__1_i_8_n_1\ : STD_LOGIC;
  signal \state0_carry__1_n_1\ : STD_LOGIC;
  signal \state0_carry__1_n_2\ : STD_LOGIC;
  signal \state0_carry__1_n_3\ : STD_LOGIC;
  signal \state0_carry__1_n_4\ : STD_LOGIC;
  signal \state0_carry__2_i_1_n_1\ : STD_LOGIC;
  signal \state0_carry__2_i_2_n_1\ : STD_LOGIC;
  signal \state0_carry__2_i_3_n_1\ : STD_LOGIC;
  signal \state0_carry__2_i_4_n_1\ : STD_LOGIC;
  signal \state0_carry__2_i_5_n_1\ : STD_LOGIC;
  signal \state0_carry__2_i_6_n_1\ : STD_LOGIC;
  signal \state0_carry__2_n_2\ : STD_LOGIC;
  signal \state0_carry__2_n_3\ : STD_LOGIC;
  signal \state0_carry__2_n_4\ : STD_LOGIC;
  signal state0_carry_i_1_n_1 : STD_LOGIC;
  signal state0_carry_i_2_n_1 : STD_LOGIC;
  signal state0_carry_i_3_n_1 : STD_LOGIC;
  signal state0_carry_i_4_n_1 : STD_LOGIC;
  signal state0_carry_i_5_n_1 : STD_LOGIC;
  signal state0_carry_i_6_n_1 : STD_LOGIC;
  signal state0_carry_i_7_n_1 : STD_LOGIC;
  signal state0_carry_i_8_n_1 : STD_LOGIC;
  signal state0_carry_n_1 : STD_LOGIC;
  signal state0_carry_n_2 : STD_LOGIC;
  signal state0_carry_n_3 : STD_LOGIC;
  signal state0_carry_n_4 : STD_LOGIC;
  signal val0 : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal val1 : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal val2 : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal \val2[31]_i_1_n_1\ : STD_LOGIC;
  signal \val2[31]_i_2_n_1\ : STD_LOGIC;
  signal val_last : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal \val_last[31]_i_2_n_1\ : STD_LOGIC;
  signal \val_last[31]_i_3_n_1\ : STD_LOGIC;
  signal \val_last[31]_i_4_n_1\ : STD_LOGIC;
  signal \val_last[31]_i_5_n_1\ : STD_LOGIC;
  signal \val_last[31]_i_6_n_1\ : STD_LOGIC;
  signal \val_last[31]_i_7_n_1\ : STD_LOGIC;
  signal \val_last[31]_i_8_n_1\ : STD_LOGIC;
  signal \val_last[31]_i_9_n_1\ : STD_LOGIC;
  signal val_last_1 : STD_LOGIC;
  signal \NLW_i0_carry__6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_i0_carry__6_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \NLW_j0_carry__6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_j0_carry__6_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal NLW_j1_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_j1_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_j1_carry__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \NLW_j1_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_max_found1_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_max_found1_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_max_found1_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_max_found1_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_max_found1_inferred__0/i__carry_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_max_found1_inferred__0/i__carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_max_found1_inferred__0/i__carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_max_found1_inferred__0/i__carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal NLW_state0_carry_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_state0_carry__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_state0_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_state0_carry__2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
  signal \NLW_state0_carry__2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_onehot_state[0]_i_2\ : label is "soft_lutpair0";
  attribute SOFT_HLUTNM of \FSM_onehot_state[1]_i_2\ : label is "soft_lutpair0";
  attribute SOFT_HLUTNM of \FSM_onehot_state[1]_i_3\ : label is "soft_lutpair1";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_onehot_state_reg[0]\ : label is "compare:100,idle:001,store:010";
  attribute FSM_ENCODED_STATES of \FSM_onehot_state_reg[1]\ : label is "compare:100,idle:001,store:010";
  attribute FSM_ENCODED_STATES of \FSM_onehot_state_reg[2]\ : label is "compare:100,idle:001,store:010";
  attribute SOFT_HLUTNM of \fifo_reset[0]_i_1\ : label is "soft_lutpair2";
  attribute SOFT_HLUTNM of resig_i_1 : label is "soft_lutpair1";
  attribute SOFT_HLUTNM of rst_i_1 : label is "soft_lutpair2";
begin
  max_found <= \^max_found\;
  rst <= \^rst\;
  start_fifo <= \^start_fifo\;
\FSM_onehot_state[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAA8B8A8B8A8B8"
    )
        port map (
      I0 => \FSM_onehot_state[0]_i_2_n_1\,
      I1 => \FSM_onehot_state_reg_n_1_[2]\,
      I2 => resig,
      I3 => start,
      I4 => \state0_carry__2_n_2\,
      I5 => val_last_1,
      O => \FSM_onehot_state[0]_i_1_n_1\
    );
\FSM_onehot_state[0]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"D500"
    )
        port map (
      I0 => start,
      I1 => max_found12_in,
      I2 => max_found1,
      I3 => \FSM_onehot_state_reg_n_1_[2]\,
      O => \FSM_onehot_state[0]_i_2_n_1\
    );
\FSM_onehot_state[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ABBBA888"
    )
        port map (
      I0 => \FSM_onehot_state[1]_i_2_n_1\,
      I1 => \FSM_onehot_state[1]_i_3_n_1\,
      I2 => \state0_carry__2_n_2\,
      I3 => val_last_1,
      I4 => \FSM_onehot_state_reg_n_1_[1]\,
      O => \FSM_onehot_state[1]_i_1_n_1\
    );
\FSM_onehot_state[1]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF7000"
    )
        port map (
      I0 => max_found12_in,
      I1 => max_found1,
      I2 => \FSM_onehot_state_reg_n_1_[2]\,
      I3 => start,
      I4 => resig,
      O => \FSM_onehot_state[1]_i_2_n_1\
    );
\FSM_onehot_state[1]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => start,
      I1 => resig,
      I2 => \FSM_onehot_state_reg_n_1_[2]\,
      O => \FSM_onehot_state[1]_i_3_n_1\
    );
\FSM_onehot_state[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAA888A888A888"
    )
        port map (
      I0 => \FSM_onehot_state_reg_n_1_[1]\,
      I1 => \FSM_onehot_state_reg_n_1_[2]\,
      I2 => resig,
      I3 => start,
      I4 => \state0_carry__2_n_2\,
      I5 => val_last_1,
      O => \FSM_onehot_state[2]_i_1_n_1\
    );
\FSM_onehot_state_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => clk,
      CE => '1',
      D => \FSM_onehot_state[0]_i_1_n_1\,
      Q => resig,
      R => '0'
    );
\FSM_onehot_state_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \FSM_onehot_state[1]_i_1_n_1\,
      Q => \FSM_onehot_state_reg_n_1_[1]\,
      R => '0'
    );
\FSM_onehot_state_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \FSM_onehot_state[2]_i_1_n_1\,
      Q => \FSM_onehot_state_reg_n_1_[2]\,
      R => '0'
    );
\fifo_reset[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F2"
    )
        port map (
      I0 => resig,
      I1 => resig_reg_n_1,
      I2 => fifo_reset(0),
      O => \fifo_reset[0]_i_1_n_1\
    );
\fifo_reset_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \fifo_reset[0]_i_1_n_1\,
      Q => fifo_reset(0),
      R => '0'
    );
i0_carry: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => i0_carry_n_1,
      CO(2) => i0_carry_n_2,
      CO(1) => i0_carry_n_3,
      CO(0) => i0_carry_n_4,
      CYINIT => i(0),
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => data1(4 downto 1),
      S(3 downto 0) => i(4 downto 1)
    );
\i0_carry__0\: unisim.vcomponents.CARRY4
     port map (
      CI => i0_carry_n_1,
      CO(3) => \i0_carry__0_n_1\,
      CO(2) => \i0_carry__0_n_2\,
      CO(1) => \i0_carry__0_n_3\,
      CO(0) => \i0_carry__0_n_4\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => data1(8 downto 5),
      S(3 downto 0) => i(8 downto 5)
    );
\i0_carry__1\: unisim.vcomponents.CARRY4
     port map (
      CI => \i0_carry__0_n_1\,
      CO(3) => \i0_carry__1_n_1\,
      CO(2) => \i0_carry__1_n_2\,
      CO(1) => \i0_carry__1_n_3\,
      CO(0) => \i0_carry__1_n_4\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => data1(12 downto 9),
      S(3 downto 0) => i(12 downto 9)
    );
\i0_carry__2\: unisim.vcomponents.CARRY4
     port map (
      CI => \i0_carry__1_n_1\,
      CO(3) => \i0_carry__2_n_1\,
      CO(2) => \i0_carry__2_n_2\,
      CO(1) => \i0_carry__2_n_3\,
      CO(0) => \i0_carry__2_n_4\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => data1(16 downto 13),
      S(3 downto 0) => i(16 downto 13)
    );
\i0_carry__3\: unisim.vcomponents.CARRY4
     port map (
      CI => \i0_carry__2_n_1\,
      CO(3) => \i0_carry__3_n_1\,
      CO(2) => \i0_carry__3_n_2\,
      CO(1) => \i0_carry__3_n_3\,
      CO(0) => \i0_carry__3_n_4\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => data1(20 downto 17),
      S(3 downto 0) => i(20 downto 17)
    );
\i0_carry__4\: unisim.vcomponents.CARRY4
     port map (
      CI => \i0_carry__3_n_1\,
      CO(3) => \i0_carry__4_n_1\,
      CO(2) => \i0_carry__4_n_2\,
      CO(1) => \i0_carry__4_n_3\,
      CO(0) => \i0_carry__4_n_4\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => data1(24 downto 21),
      S(3 downto 0) => i(24 downto 21)
    );
\i0_carry__5\: unisim.vcomponents.CARRY4
     port map (
      CI => \i0_carry__4_n_1\,
      CO(3) => \i0_carry__5_n_1\,
      CO(2) => \i0_carry__5_n_2\,
      CO(1) => \i0_carry__5_n_3\,
      CO(0) => \i0_carry__5_n_4\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => data1(28 downto 25),
      S(3 downto 0) => i(28 downto 25)
    );
\i0_carry__6\: unisim.vcomponents.CARRY4
     port map (
      CI => \i0_carry__5_n_1\,
      CO(3 downto 2) => \NLW_i0_carry__6_CO_UNCONNECTED\(3 downto 2),
      CO(1) => \i0_carry__6_n_3\,
      CO(0) => \i0_carry__6_n_4\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \NLW_i0_carry__6_O_UNCONNECTED\(3),
      O(2 downto 0) => data1(31 downto 29),
      S(3) => '0',
      S(2 downto 0) => i(31 downto 29)
    );
\i[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00FEFF00"
    )
        port map (
      I0 => \val_last[31]_i_2_n_1\,
      I1 => \val_last[31]_i_3_n_1\,
      I2 => \val_last[31]_i_4_n_1\,
      I3 => i(0),
      I4 => \FSM_onehot_state_reg_n_1_[1]\,
      O => \i[0]_i_1_n_1\
    );
\i[10]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0000"
    )
        port map (
      I0 => \val_last[31]_i_4_n_1\,
      I1 => \val_last[31]_i_3_n_1\,
      I2 => \val_last[31]_i_2_n_1\,
      I3 => i(0),
      I4 => data1(10),
      O => \i[10]_i_1_n_1\
    );
\i[11]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0000"
    )
        port map (
      I0 => \val_last[31]_i_4_n_1\,
      I1 => \val_last[31]_i_3_n_1\,
      I2 => \val_last[31]_i_2_n_1\,
      I3 => i(0),
      I4 => data1(11),
      O => \i[11]_i_1_n_1\
    );
\i[12]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0000"
    )
        port map (
      I0 => \val_last[31]_i_4_n_1\,
      I1 => \val_last[31]_i_3_n_1\,
      I2 => \val_last[31]_i_2_n_1\,
      I3 => i(0),
      I4 => data1(12),
      O => \i[12]_i_1_n_1\
    );
\i[13]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0000"
    )
        port map (
      I0 => \val_last[31]_i_4_n_1\,
      I1 => \val_last[31]_i_3_n_1\,
      I2 => \val_last[31]_i_2_n_1\,
      I3 => i(0),
      I4 => data1(13),
      O => \i[13]_i_1_n_1\
    );
\i[14]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0000"
    )
        port map (
      I0 => \val_last[31]_i_4_n_1\,
      I1 => \val_last[31]_i_3_n_1\,
      I2 => \val_last[31]_i_2_n_1\,
      I3 => i(0),
      I4 => data1(14),
      O => \i[14]_i_1_n_1\
    );
\i[15]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0000"
    )
        port map (
      I0 => \val_last[31]_i_4_n_1\,
      I1 => \val_last[31]_i_3_n_1\,
      I2 => \val_last[31]_i_2_n_1\,
      I3 => i(0),
      I4 => data1(15),
      O => \i[15]_i_1_n_1\
    );
\i[16]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0000"
    )
        port map (
      I0 => \val_last[31]_i_4_n_1\,
      I1 => \val_last[31]_i_3_n_1\,
      I2 => \val_last[31]_i_2_n_1\,
      I3 => i(0),
      I4 => data1(16),
      O => \i[16]_i_1_n_1\
    );
\i[17]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0000"
    )
        port map (
      I0 => \val_last[31]_i_4_n_1\,
      I1 => \val_last[31]_i_3_n_1\,
      I2 => \val_last[31]_i_2_n_1\,
      I3 => i(0),
      I4 => data1(17),
      O => \i[17]_i_1_n_1\
    );
\i[18]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0000"
    )
        port map (
      I0 => \val_last[31]_i_4_n_1\,
      I1 => \val_last[31]_i_3_n_1\,
      I2 => \val_last[31]_i_2_n_1\,
      I3 => i(0),
      I4 => data1(18),
      O => \i[18]_i_1_n_1\
    );
\i[19]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0000"
    )
        port map (
      I0 => \val_last[31]_i_4_n_1\,
      I1 => \val_last[31]_i_3_n_1\,
      I2 => \val_last[31]_i_2_n_1\,
      I3 => i(0),
      I4 => data1(19),
      O => \i[19]_i_1_n_1\
    );
\i[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0000"
    )
        port map (
      I0 => \val_last[31]_i_4_n_1\,
      I1 => \val_last[31]_i_3_n_1\,
      I2 => \val_last[31]_i_2_n_1\,
      I3 => i(0),
      I4 => data1(1),
      O => \i[1]_i_1_n_1\
    );
\i[20]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0000"
    )
        port map (
      I0 => \val_last[31]_i_4_n_1\,
      I1 => \val_last[31]_i_3_n_1\,
      I2 => \val_last[31]_i_2_n_1\,
      I3 => i(0),
      I4 => data1(20),
      O => \i[20]_i_1_n_1\
    );
\i[21]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0000"
    )
        port map (
      I0 => \val_last[31]_i_4_n_1\,
      I1 => \val_last[31]_i_3_n_1\,
      I2 => \val_last[31]_i_2_n_1\,
      I3 => i(0),
      I4 => data1(21),
      O => \i[21]_i_1_n_1\
    );
\i[22]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0000"
    )
        port map (
      I0 => \val_last[31]_i_4_n_1\,
      I1 => \val_last[31]_i_3_n_1\,
      I2 => \val_last[31]_i_2_n_1\,
      I3 => i(0),
      I4 => data1(22),
      O => \i[22]_i_1_n_1\
    );
\i[23]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0000"
    )
        port map (
      I0 => \val_last[31]_i_4_n_1\,
      I1 => \val_last[31]_i_3_n_1\,
      I2 => \val_last[31]_i_2_n_1\,
      I3 => i(0),
      I4 => data1(23),
      O => \i[23]_i_1_n_1\
    );
\i[24]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0000"
    )
        port map (
      I0 => \val_last[31]_i_4_n_1\,
      I1 => \val_last[31]_i_3_n_1\,
      I2 => \val_last[31]_i_2_n_1\,
      I3 => i(0),
      I4 => data1(24),
      O => \i[24]_i_1_n_1\
    );
\i[25]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0000"
    )
        port map (
      I0 => \val_last[31]_i_4_n_1\,
      I1 => \val_last[31]_i_3_n_1\,
      I2 => \val_last[31]_i_2_n_1\,
      I3 => i(0),
      I4 => data1(25),
      O => \i[25]_i_1_n_1\
    );
\i[26]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0000"
    )
        port map (
      I0 => \val_last[31]_i_4_n_1\,
      I1 => \val_last[31]_i_3_n_1\,
      I2 => \val_last[31]_i_2_n_1\,
      I3 => i(0),
      I4 => data1(26),
      O => \i[26]_i_1_n_1\
    );
\i[27]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0000"
    )
        port map (
      I0 => \val_last[31]_i_4_n_1\,
      I1 => \val_last[31]_i_3_n_1\,
      I2 => \val_last[31]_i_2_n_1\,
      I3 => i(0),
      I4 => data1(27),
      O => \i[27]_i_1_n_1\
    );
\i[28]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0000"
    )
        port map (
      I0 => \val_last[31]_i_4_n_1\,
      I1 => \val_last[31]_i_3_n_1\,
      I2 => \val_last[31]_i_2_n_1\,
      I3 => i(0),
      I4 => data1(28),
      O => \i[28]_i_1_n_1\
    );
\i[29]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0000"
    )
        port map (
      I0 => \val_last[31]_i_4_n_1\,
      I1 => \val_last[31]_i_3_n_1\,
      I2 => \val_last[31]_i_2_n_1\,
      I3 => i(0),
      I4 => data1(29),
      O => \i[29]_i_1_n_1\
    );
\i[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0000"
    )
        port map (
      I0 => \val_last[31]_i_4_n_1\,
      I1 => \val_last[31]_i_3_n_1\,
      I2 => \val_last[31]_i_2_n_1\,
      I3 => i(0),
      I4 => data1(2),
      O => \i[2]_i_1_n_1\
    );
\i[30]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0000"
    )
        port map (
      I0 => \val_last[31]_i_4_n_1\,
      I1 => \val_last[31]_i_3_n_1\,
      I2 => \val_last[31]_i_2_n_1\,
      I3 => i(0),
      I4 => data1(30),
      O => \i[30]_i_1_n_1\
    );
\i[31]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFEFFFF00000000"
    )
        port map (
      I0 => \val_last[31]_i_4_n_1\,
      I1 => \val_last[31]_i_3_n_1\,
      I2 => \val_last[31]_i_2_n_1\,
      I3 => i(0),
      I4 => p_0_in,
      I5 => \FSM_onehot_state_reg_n_1_[1]\,
      O => i_0
    );
\i[31]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0000"
    )
        port map (
      I0 => \val_last[31]_i_4_n_1\,
      I1 => \val_last[31]_i_3_n_1\,
      I2 => \val_last[31]_i_2_n_1\,
      I3 => i(0),
      I4 => data1(31),
      O => \i[31]_i_2_n_1\
    );
\i[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0000"
    )
        port map (
      I0 => \val_last[31]_i_4_n_1\,
      I1 => \val_last[31]_i_3_n_1\,
      I2 => \val_last[31]_i_2_n_1\,
      I3 => i(0),
      I4 => data1(3),
      O => \i[3]_i_1_n_1\
    );
\i[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0000"
    )
        port map (
      I0 => \val_last[31]_i_4_n_1\,
      I1 => \val_last[31]_i_3_n_1\,
      I2 => \val_last[31]_i_2_n_1\,
      I3 => i(0),
      I4 => data1(4),
      O => \i[4]_i_1_n_1\
    );
\i[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0000"
    )
        port map (
      I0 => \val_last[31]_i_4_n_1\,
      I1 => \val_last[31]_i_3_n_1\,
      I2 => \val_last[31]_i_2_n_1\,
      I3 => i(0),
      I4 => data1(5),
      O => \i[5]_i_1_n_1\
    );
\i[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0000"
    )
        port map (
      I0 => \val_last[31]_i_4_n_1\,
      I1 => \val_last[31]_i_3_n_1\,
      I2 => \val_last[31]_i_2_n_1\,
      I3 => i(0),
      I4 => data1(6),
      O => \i[6]_i_1_n_1\
    );
\i[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0000"
    )
        port map (
      I0 => \val_last[31]_i_4_n_1\,
      I1 => \val_last[31]_i_3_n_1\,
      I2 => \val_last[31]_i_2_n_1\,
      I3 => i(0),
      I4 => data1(7),
      O => \i[7]_i_1_n_1\
    );
\i[8]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0000"
    )
        port map (
      I0 => \val_last[31]_i_4_n_1\,
      I1 => \val_last[31]_i_3_n_1\,
      I2 => \val_last[31]_i_2_n_1\,
      I3 => i(0),
      I4 => data1(8),
      O => \i[8]_i_1_n_1\
    );
\i[9]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0000"
    )
        port map (
      I0 => \val_last[31]_i_4_n_1\,
      I1 => \val_last[31]_i_3_n_1\,
      I2 => \val_last[31]_i_2_n_1\,
      I3 => i(0),
      I4 => data1(9),
      O => \i[9]_i_1_n_1\
    );
\i__carry__0_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => val1(15),
      I1 => val0(15),
      I2 => val1(14),
      I3 => val0(14),
      O => \i__carry__0_i_1_n_1\
    );
\i__carry__0_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => val1(13),
      I1 => val0(13),
      I2 => val1(12),
      I3 => val0(12),
      O => \i__carry__0_i_2_n_1\
    );
\i__carry__0_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => val1(11),
      I1 => val0(11),
      I2 => val1(10),
      I3 => val0(10),
      O => \i__carry__0_i_3_n_1\
    );
\i__carry__0_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => val1(9),
      I1 => val0(9),
      I2 => val1(8),
      I3 => val0(8),
      O => \i__carry__0_i_4_n_1\
    );
\i__carry__0_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => val0(15),
      I1 => val1(15),
      I2 => val0(14),
      I3 => val1(14),
      O => \i__carry__0_i_5_n_1\
    );
\i__carry__0_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => val0(13),
      I1 => val1(13),
      I2 => val0(12),
      I3 => val1(12),
      O => \i__carry__0_i_6_n_1\
    );
\i__carry__0_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => val0(11),
      I1 => val1(11),
      I2 => val0(10),
      I3 => val1(10),
      O => \i__carry__0_i_7_n_1\
    );
\i__carry__0_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => val0(9),
      I1 => val1(9),
      I2 => val0(8),
      I3 => val1(8),
      O => \i__carry__0_i_8_n_1\
    );
\i__carry__1_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => val1(23),
      I1 => val0(23),
      I2 => val1(22),
      I3 => val0(22),
      O => \i__carry__1_i_1_n_1\
    );
\i__carry__1_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => val1(21),
      I1 => val0(21),
      I2 => val1(20),
      I3 => val0(20),
      O => \i__carry__1_i_2_n_1\
    );
\i__carry__1_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => val1(19),
      I1 => val0(19),
      I2 => val1(18),
      I3 => val0(18),
      O => \i__carry__1_i_3_n_1\
    );
\i__carry__1_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => val1(17),
      I1 => val0(17),
      I2 => val1(16),
      I3 => val0(16),
      O => \i__carry__1_i_4_n_1\
    );
\i__carry__1_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => val0(23),
      I1 => val1(23),
      I2 => val0(22),
      I3 => val1(22),
      O => \i__carry__1_i_5_n_1\
    );
\i__carry__1_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => val0(21),
      I1 => val1(21),
      I2 => val0(20),
      I3 => val1(20),
      O => \i__carry__1_i_6_n_1\
    );
\i__carry__1_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => val0(19),
      I1 => val1(19),
      I2 => val0(18),
      I3 => val1(18),
      O => \i__carry__1_i_7_n_1\
    );
\i__carry__1_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => val0(17),
      I1 => val1(17),
      I2 => val0(16),
      I3 => val1(16),
      O => \i__carry__1_i_8_n_1\
    );
\i__carry__2_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => val0(31),
      I1 => val1(31),
      I2 => val1(30),
      I3 => val0(30),
      O => \i__carry__2_i_1_n_1\
    );
\i__carry__2_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => val1(29),
      I1 => val0(29),
      I2 => val1(28),
      I3 => val0(28),
      O => \i__carry__2_i_2_n_1\
    );
\i__carry__2_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => val1(27),
      I1 => val0(27),
      I2 => val1(26),
      I3 => val0(26),
      O => \i__carry__2_i_3_n_1\
    );
\i__carry__2_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => val1(25),
      I1 => val0(25),
      I2 => val1(24),
      I3 => val0(24),
      O => \i__carry__2_i_4_n_1\
    );
\i__carry__2_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => val0(31),
      I1 => val1(31),
      I2 => val0(30),
      I3 => val1(30),
      O => \i__carry__2_i_5_n_1\
    );
\i__carry__2_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => val0(29),
      I1 => val1(29),
      I2 => val0(28),
      I3 => val1(28),
      O => \i__carry__2_i_6_n_1\
    );
\i__carry__2_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => val0(27),
      I1 => val1(27),
      I2 => val0(26),
      I3 => val1(26),
      O => \i__carry__2_i_7_n_1\
    );
\i__carry__2_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => val0(25),
      I1 => val1(25),
      I2 => val0(24),
      I3 => val1(24),
      O => \i__carry__2_i_8_n_1\
    );
\i__carry_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => val1(7),
      I1 => val0(7),
      I2 => val1(6),
      I3 => val0(6),
      O => \i__carry_i_1_n_1\
    );
\i__carry_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => val1(5),
      I1 => val0(5),
      I2 => val1(4),
      I3 => val0(4),
      O => \i__carry_i_2_n_1\
    );
\i__carry_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => val1(3),
      I1 => val0(3),
      I2 => val1(2),
      I3 => val0(2),
      O => \i__carry_i_3_n_1\
    );
\i__carry_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => val1(1),
      I1 => val0(1),
      I2 => val1(0),
      I3 => val0(0),
      O => \i__carry_i_4_n_1\
    );
\i__carry_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => val0(7),
      I1 => val1(7),
      I2 => val0(6),
      I3 => val1(6),
      O => \i__carry_i_5_n_1\
    );
\i__carry_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => val0(5),
      I1 => val1(5),
      I2 => val0(4),
      I3 => val1(4),
      O => \i__carry_i_6_n_1\
    );
\i__carry_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => val0(3),
      I1 => val1(3),
      I2 => val0(2),
      I3 => val1(2),
      O => \i__carry_i_7_n_1\
    );
\i__carry_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => val0(1),
      I1 => val1(1),
      I2 => val0(0),
      I3 => val1(0),
      O => \i__carry_i_8_n_1\
    );
\i_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => '1',
      D => \i[0]_i_1_n_1\,
      Q => i(0),
      R => '0'
    );
\i_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => i_0,
      D => \i[10]_i_1_n_1\,
      Q => i(10),
      R => '0'
    );
\i_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => i_0,
      D => \i[11]_i_1_n_1\,
      Q => i(11),
      R => '0'
    );
\i_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => i_0,
      D => \i[12]_i_1_n_1\,
      Q => i(12),
      R => '0'
    );
\i_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => i_0,
      D => \i[13]_i_1_n_1\,
      Q => i(13),
      R => '0'
    );
\i_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => i_0,
      D => \i[14]_i_1_n_1\,
      Q => i(14),
      R => '0'
    );
\i_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => i_0,
      D => \i[15]_i_1_n_1\,
      Q => i(15),
      R => '0'
    );
\i_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => i_0,
      D => \i[16]_i_1_n_1\,
      Q => i(16),
      R => '0'
    );
\i_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => i_0,
      D => \i[17]_i_1_n_1\,
      Q => i(17),
      R => '0'
    );
\i_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => i_0,
      D => \i[18]_i_1_n_1\,
      Q => i(18),
      R => '0'
    );
\i_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => i_0,
      D => \i[19]_i_1_n_1\,
      Q => i(19),
      R => '0'
    );
\i_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => i_0,
      D => \i[1]_i_1_n_1\,
      Q => i(1),
      R => '0'
    );
\i_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => i_0,
      D => \i[20]_i_1_n_1\,
      Q => i(20),
      R => '0'
    );
\i_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => i_0,
      D => \i[21]_i_1_n_1\,
      Q => i(21),
      R => '0'
    );
\i_reg[22]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => i_0,
      D => \i[22]_i_1_n_1\,
      Q => i(22),
      R => '0'
    );
\i_reg[23]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => i_0,
      D => \i[23]_i_1_n_1\,
      Q => i(23),
      R => '0'
    );
\i_reg[24]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => i_0,
      D => \i[24]_i_1_n_1\,
      Q => i(24),
      R => '0'
    );
\i_reg[25]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => i_0,
      D => \i[25]_i_1_n_1\,
      Q => i(25),
      R => '0'
    );
\i_reg[26]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => i_0,
      D => \i[26]_i_1_n_1\,
      Q => i(26),
      R => '0'
    );
\i_reg[27]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => i_0,
      D => \i[27]_i_1_n_1\,
      Q => i(27),
      R => '0'
    );
\i_reg[28]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => i_0,
      D => \i[28]_i_1_n_1\,
      Q => i(28),
      R => '0'
    );
\i_reg[29]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => i_0,
      D => \i[29]_i_1_n_1\,
      Q => i(29),
      R => '0'
    );
\i_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => i_0,
      D => \i[2]_i_1_n_1\,
      Q => i(2),
      R => '0'
    );
\i_reg[30]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => i_0,
      D => \i[30]_i_1_n_1\,
      Q => i(30),
      R => '0'
    );
\i_reg[31]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => i_0,
      D => \i[31]_i_2_n_1\,
      Q => i(31),
      R => '0'
    );
\i_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => i_0,
      D => \i[3]_i_1_n_1\,
      Q => i(3),
      R => '0'
    );
\i_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => i_0,
      D => \i[4]_i_1_n_1\,
      Q => i(4),
      R => '0'
    );
\i_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => i_0,
      D => \i[5]_i_1_n_1\,
      Q => i(5),
      R => '0'
    );
\i_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => i_0,
      D => \i[6]_i_1_n_1\,
      Q => i(6),
      R => '0'
    );
\i_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => i_0,
      D => \i[7]_i_1_n_1\,
      Q => i(7),
      R => '0'
    );
\i_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => i_0,
      D => \i[8]_i_1_n_1\,
      Q => i(8),
      R => '0'
    );
\i_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => i_0,
      D => \i[9]_i_1_n_1\,
      Q => i(9),
      R => '0'
    );
j0_carry: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => j0_carry_n_1,
      CO(2) => j0_carry_n_2,
      CO(1) => j0_carry_n_3,
      CO(0) => j0_carry_n_4,
      CYINIT => j(0),
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => in3(4 downto 1),
      S(3 downto 0) => j(4 downto 1)
    );
\j0_carry__0\: unisim.vcomponents.CARRY4
     port map (
      CI => j0_carry_n_1,
      CO(3) => \j0_carry__0_n_1\,
      CO(2) => \j0_carry__0_n_2\,
      CO(1) => \j0_carry__0_n_3\,
      CO(0) => \j0_carry__0_n_4\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => in3(8 downto 5),
      S(3 downto 0) => j(8 downto 5)
    );
\j0_carry__1\: unisim.vcomponents.CARRY4
     port map (
      CI => \j0_carry__0_n_1\,
      CO(3) => \j0_carry__1_n_1\,
      CO(2) => \j0_carry__1_n_2\,
      CO(1) => \j0_carry__1_n_3\,
      CO(0) => \j0_carry__1_n_4\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => in3(12 downto 9),
      S(3 downto 0) => j(12 downto 9)
    );
\j0_carry__2\: unisim.vcomponents.CARRY4
     port map (
      CI => \j0_carry__1_n_1\,
      CO(3) => \j0_carry__2_n_1\,
      CO(2) => \j0_carry__2_n_2\,
      CO(1) => \j0_carry__2_n_3\,
      CO(0) => \j0_carry__2_n_4\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => in3(16 downto 13),
      S(3 downto 0) => j(16 downto 13)
    );
\j0_carry__3\: unisim.vcomponents.CARRY4
     port map (
      CI => \j0_carry__2_n_1\,
      CO(3) => \j0_carry__3_n_1\,
      CO(2) => \j0_carry__3_n_2\,
      CO(1) => \j0_carry__3_n_3\,
      CO(0) => \j0_carry__3_n_4\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => in3(20 downto 17),
      S(3 downto 0) => j(20 downto 17)
    );
\j0_carry__4\: unisim.vcomponents.CARRY4
     port map (
      CI => \j0_carry__3_n_1\,
      CO(3) => \j0_carry__4_n_1\,
      CO(2) => \j0_carry__4_n_2\,
      CO(1) => \j0_carry__4_n_3\,
      CO(0) => \j0_carry__4_n_4\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => in3(24 downto 21),
      S(3 downto 0) => j(24 downto 21)
    );
\j0_carry__5\: unisim.vcomponents.CARRY4
     port map (
      CI => \j0_carry__4_n_1\,
      CO(3) => \j0_carry__5_n_1\,
      CO(2) => \j0_carry__5_n_2\,
      CO(1) => \j0_carry__5_n_3\,
      CO(0) => \j0_carry__5_n_4\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => in3(28 downto 25),
      S(3 downto 0) => j(28 downto 25)
    );
\j0_carry__6\: unisim.vcomponents.CARRY4
     port map (
      CI => \j0_carry__5_n_1\,
      CO(3 downto 2) => \NLW_j0_carry__6_CO_UNCONNECTED\(3 downto 2),
      CO(1) => \j0_carry__6_n_3\,
      CO(0) => \j0_carry__6_n_4\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \NLW_j0_carry__6_O_UNCONNECTED\(3),
      O(2 downto 0) => in3(31 downto 29),
      S(3) => '0',
      S(2 downto 0) => j(31 downto 29)
    );
j1_carry: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => j1_carry_n_1,
      CO(2) => j1_carry_n_2,
      CO(1) => j1_carry_n_3,
      CO(0) => j1_carry_n_4,
      CYINIT => '1',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => NLW_j1_carry_O_UNCONNECTED(3 downto 0),
      S(3) => j1_carry_i_1_n_1,
      S(2) => j1_carry_i_2_n_1,
      S(1) => j1_carry_i_3_n_1,
      S(0) => j1_carry_i_4_n_1
    );
\j1_carry__0\: unisim.vcomponents.CARRY4
     port map (
      CI => j1_carry_n_1,
      CO(3) => \j1_carry__0_n_1\,
      CO(2) => \j1_carry__0_n_2\,
      CO(1) => \j1_carry__0_n_3\,
      CO(0) => \j1_carry__0_n_4\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \NLW_j1_carry__0_O_UNCONNECTED\(3 downto 0),
      S(3) => \j1_carry__0_i_1_n_1\,
      S(2) => \j1_carry__0_i_2_n_1\,
      S(1) => \j1_carry__0_i_3_n_1\,
      S(0) => \j1_carry__0_i_4_n_1\
    );
\j1_carry__0_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => val_in(23),
      I1 => val_last(23),
      I2 => val_in(22),
      I3 => val_last(22),
      I4 => val_last(21),
      I5 => val_in(21),
      O => \j1_carry__0_i_1_n_1\
    );
\j1_carry__0_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => val_in(20),
      I1 => val_last(20),
      I2 => val_in(19),
      I3 => val_last(19),
      I4 => val_last(18),
      I5 => val_in(18),
      O => \j1_carry__0_i_2_n_1\
    );
\j1_carry__0_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => val_in(17),
      I1 => val_last(17),
      I2 => val_in(16),
      I3 => val_last(16),
      I4 => val_last(15),
      I5 => val_in(15),
      O => \j1_carry__0_i_3_n_1\
    );
\j1_carry__0_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => val_in(14),
      I1 => val_last(14),
      I2 => val_in(13),
      I3 => val_last(13),
      I4 => val_last(12),
      I5 => val_in(12),
      O => \j1_carry__0_i_4_n_1\
    );
\j1_carry__1\: unisim.vcomponents.CARRY4
     port map (
      CI => \j1_carry__0_n_1\,
      CO(3) => \NLW_j1_carry__1_CO_UNCONNECTED\(3),
      CO(2) => p_0_in,
      CO(1) => \j1_carry__1_n_3\,
      CO(0) => \j1_carry__1_n_4\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => \NLW_j1_carry__1_O_UNCONNECTED\(3 downto 0),
      S(3) => '0',
      S(2) => \j1_carry__1_i_1_n_1\,
      S(1) => \j1_carry__1_i_2_n_1\,
      S(0) => \j1_carry__1_i_3_n_1\
    );
\j1_carry__1_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => val_in(31),
      I1 => val_last(31),
      I2 => val_in(30),
      I3 => val_last(30),
      O => \j1_carry__1_i_1_n_1\
    );
\j1_carry__1_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => val_in(29),
      I1 => val_last(29),
      I2 => val_in(28),
      I3 => val_last(28),
      I4 => val_last(27),
      I5 => val_in(27),
      O => \j1_carry__1_i_2_n_1\
    );
\j1_carry__1_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => val_in(26),
      I1 => val_last(26),
      I2 => val_in(25),
      I3 => val_last(25),
      I4 => val_last(24),
      I5 => val_in(24),
      O => \j1_carry__1_i_3_n_1\
    );
j1_carry_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => val_in(11),
      I1 => val_last(11),
      I2 => val_in(10),
      I3 => val_last(10),
      I4 => val_last(9),
      I5 => val_in(9),
      O => j1_carry_i_1_n_1
    );
j1_carry_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => val_in(8),
      I1 => val_last(8),
      I2 => val_in(7),
      I3 => val_last(7),
      I4 => val_last(6),
      I5 => val_in(6),
      O => j1_carry_i_2_n_1
    );
j1_carry_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => val_in(5),
      I1 => val_last(5),
      I2 => val_in(4),
      I3 => val_last(4),
      I4 => val_last(3),
      I5 => val_in(3),
      O => j1_carry_i_3_n_1
    );
j1_carry_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"9009000000009009"
    )
        port map (
      I0 => val_in(2),
      I1 => val_last(2),
      I2 => val_in(1),
      I3 => val_last(1),
      I4 => val_last(0),
      I5 => val_in(0),
      O => j1_carry_i_4_n_1
    );
\j[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => j(0),
      O => \in3__0\(0)
    );
\j[31]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0E"
    )
        port map (
      I0 => resig,
      I1 => val_last_1,
      I2 => \FSM_onehot_state_reg_n_1_[1]\,
      O => \j[31]_i_1_n_1\
    );
\j[31]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => val_last_1,
      I1 => resig,
      O => \j[31]_i_2_n_1\
    );
\j_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \j[31]_i_2_n_1\,
      D => \in3__0\(0),
      Q => j(0),
      R => \j[31]_i_1_n_1\
    );
\j_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \j[31]_i_2_n_1\,
      D => in3(10),
      Q => j(10),
      R => \j[31]_i_1_n_1\
    );
\j_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \j[31]_i_2_n_1\,
      D => in3(11),
      Q => j(11),
      R => \j[31]_i_1_n_1\
    );
\j_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \j[31]_i_2_n_1\,
      D => in3(12),
      Q => j(12),
      R => \j[31]_i_1_n_1\
    );
\j_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \j[31]_i_2_n_1\,
      D => in3(13),
      Q => j(13),
      R => \j[31]_i_1_n_1\
    );
\j_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \j[31]_i_2_n_1\,
      D => in3(14),
      Q => j(14),
      R => \j[31]_i_1_n_1\
    );
\j_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \j[31]_i_2_n_1\,
      D => in3(15),
      Q => j(15),
      R => \j[31]_i_1_n_1\
    );
\j_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \j[31]_i_2_n_1\,
      D => in3(16),
      Q => j(16),
      R => \j[31]_i_1_n_1\
    );
\j_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \j[31]_i_2_n_1\,
      D => in3(17),
      Q => j(17),
      R => \j[31]_i_1_n_1\
    );
\j_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \j[31]_i_2_n_1\,
      D => in3(18),
      Q => j(18),
      R => \j[31]_i_1_n_1\
    );
\j_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \j[31]_i_2_n_1\,
      D => in3(19),
      Q => j(19),
      R => \j[31]_i_1_n_1\
    );
\j_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \j[31]_i_2_n_1\,
      D => in3(1),
      Q => j(1),
      R => \j[31]_i_1_n_1\
    );
\j_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \j[31]_i_2_n_1\,
      D => in3(20),
      Q => j(20),
      R => \j[31]_i_1_n_1\
    );
\j_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \j[31]_i_2_n_1\,
      D => in3(21),
      Q => j(21),
      R => \j[31]_i_1_n_1\
    );
\j_reg[22]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \j[31]_i_2_n_1\,
      D => in3(22),
      Q => j(22),
      R => \j[31]_i_1_n_1\
    );
\j_reg[23]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \j[31]_i_2_n_1\,
      D => in3(23),
      Q => j(23),
      R => \j[31]_i_1_n_1\
    );
\j_reg[24]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \j[31]_i_2_n_1\,
      D => in3(24),
      Q => j(24),
      R => \j[31]_i_1_n_1\
    );
\j_reg[25]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \j[31]_i_2_n_1\,
      D => in3(25),
      Q => j(25),
      R => \j[31]_i_1_n_1\
    );
\j_reg[26]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \j[31]_i_2_n_1\,
      D => in3(26),
      Q => j(26),
      R => \j[31]_i_1_n_1\
    );
\j_reg[27]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \j[31]_i_2_n_1\,
      D => in3(27),
      Q => j(27),
      R => \j[31]_i_1_n_1\
    );
\j_reg[28]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \j[31]_i_2_n_1\,
      D => in3(28),
      Q => j(28),
      R => \j[31]_i_1_n_1\
    );
\j_reg[29]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \j[31]_i_2_n_1\,
      D => in3(29),
      Q => j(29),
      R => \j[31]_i_1_n_1\
    );
\j_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \j[31]_i_2_n_1\,
      D => in3(2),
      Q => j(2),
      R => \j[31]_i_1_n_1\
    );
\j_reg[30]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \j[31]_i_2_n_1\,
      D => in3(30),
      Q => j(30),
      R => \j[31]_i_1_n_1\
    );
\j_reg[31]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \j[31]_i_2_n_1\,
      D => in3(31),
      Q => j(31),
      R => \j[31]_i_1_n_1\
    );
\j_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \j[31]_i_2_n_1\,
      D => in3(3),
      Q => j(3),
      R => \j[31]_i_1_n_1\
    );
\j_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \j[31]_i_2_n_1\,
      D => in3(4),
      Q => j(4),
      R => \j[31]_i_1_n_1\
    );
\j_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \j[31]_i_2_n_1\,
      D => in3(5),
      Q => j(5),
      R => \j[31]_i_1_n_1\
    );
\j_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \j[31]_i_2_n_1\,
      D => in3(6),
      Q => j(6),
      R => \j[31]_i_1_n_1\
    );
\j_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \j[31]_i_2_n_1\,
      D => in3(7),
      Q => j(7),
      R => \j[31]_i_1_n_1\
    );
\j_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \j[31]_i_2_n_1\,
      D => in3(8),
      Q => j(8),
      R => \j[31]_i_1_n_1\
    );
\j_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => clk,
      CE => \j[31]_i_2_n_1\,
      D => in3(9),
      Q => j(9),
      R => \j[31]_i_1_n_1\
    );
max_found1_carry: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => max_found1_carry_n_1,
      CO(2) => max_found1_carry_n_2,
      CO(1) => max_found1_carry_n_3,
      CO(0) => max_found1_carry_n_4,
      CYINIT => '0',
      DI(3) => max_found1_carry_i_1_n_1,
      DI(2) => max_found1_carry_i_2_n_1,
      DI(1) => max_found1_carry_i_3_n_1,
      DI(0) => max_found1_carry_i_4_n_1,
      O(3 downto 0) => NLW_max_found1_carry_O_UNCONNECTED(3 downto 0),
      S(3) => max_found1_carry_i_5_n_1,
      S(2) => max_found1_carry_i_6_n_1,
      S(1) => max_found1_carry_i_7_n_1,
      S(0) => max_found1_carry_i_8_n_1
    );
\max_found1_carry__0\: unisim.vcomponents.CARRY4
     port map (
      CI => max_found1_carry_n_1,
      CO(3) => \max_found1_carry__0_n_1\,
      CO(2) => \max_found1_carry__0_n_2\,
      CO(1) => \max_found1_carry__0_n_3\,
      CO(0) => \max_found1_carry__0_n_4\,
      CYINIT => '0',
      DI(3) => \max_found1_carry__0_i_1_n_1\,
      DI(2) => \max_found1_carry__0_i_2_n_1\,
      DI(1) => \max_found1_carry__0_i_3_n_1\,
      DI(0) => \max_found1_carry__0_i_4_n_1\,
      O(3 downto 0) => \NLW_max_found1_carry__0_O_UNCONNECTED\(3 downto 0),
      S(3) => \max_found1_carry__0_i_5_n_1\,
      S(2) => \max_found1_carry__0_i_6_n_1\,
      S(1) => \max_found1_carry__0_i_7_n_1\,
      S(0) => \max_found1_carry__0_i_8_n_1\
    );
\max_found1_carry__0_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => val1(15),
      I1 => val2(15),
      I2 => val1(14),
      I3 => val2(14),
      O => \max_found1_carry__0_i_1_n_1\
    );
\max_found1_carry__0_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => val1(13),
      I1 => val2(13),
      I2 => val1(12),
      I3 => val2(12),
      O => \max_found1_carry__0_i_2_n_1\
    );
\max_found1_carry__0_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => val1(11),
      I1 => val2(11),
      I2 => val1(10),
      I3 => val2(10),
      O => \max_found1_carry__0_i_3_n_1\
    );
\max_found1_carry__0_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => val1(9),
      I1 => val2(9),
      I2 => val1(8),
      I3 => val2(8),
      O => \max_found1_carry__0_i_4_n_1\
    );
\max_found1_carry__0_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => val2(15),
      I1 => val1(15),
      I2 => val2(14),
      I3 => val1(14),
      O => \max_found1_carry__0_i_5_n_1\
    );
\max_found1_carry__0_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => val2(13),
      I1 => val1(13),
      I2 => val2(12),
      I3 => val1(12),
      O => \max_found1_carry__0_i_6_n_1\
    );
\max_found1_carry__0_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => val2(11),
      I1 => val1(11),
      I2 => val2(10),
      I3 => val1(10),
      O => \max_found1_carry__0_i_7_n_1\
    );
\max_found1_carry__0_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => val2(9),
      I1 => val1(9),
      I2 => val2(8),
      I3 => val1(8),
      O => \max_found1_carry__0_i_8_n_1\
    );
\max_found1_carry__1\: unisim.vcomponents.CARRY4
     port map (
      CI => \max_found1_carry__0_n_1\,
      CO(3) => \max_found1_carry__1_n_1\,
      CO(2) => \max_found1_carry__1_n_2\,
      CO(1) => \max_found1_carry__1_n_3\,
      CO(0) => \max_found1_carry__1_n_4\,
      CYINIT => '0',
      DI(3) => \max_found1_carry__1_i_1_n_1\,
      DI(2) => \max_found1_carry__1_i_2_n_1\,
      DI(1) => \max_found1_carry__1_i_3_n_1\,
      DI(0) => \max_found1_carry__1_i_4_n_1\,
      O(3 downto 0) => \NLW_max_found1_carry__1_O_UNCONNECTED\(3 downto 0),
      S(3) => \max_found1_carry__1_i_5_n_1\,
      S(2) => \max_found1_carry__1_i_6_n_1\,
      S(1) => \max_found1_carry__1_i_7_n_1\,
      S(0) => \max_found1_carry__1_i_8_n_1\
    );
\max_found1_carry__1_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => val1(23),
      I1 => val2(23),
      I2 => val1(22),
      I3 => val2(22),
      O => \max_found1_carry__1_i_1_n_1\
    );
\max_found1_carry__1_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => val1(21),
      I1 => val2(21),
      I2 => val1(20),
      I3 => val2(20),
      O => \max_found1_carry__1_i_2_n_1\
    );
\max_found1_carry__1_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => val1(19),
      I1 => val2(19),
      I2 => val1(18),
      I3 => val2(18),
      O => \max_found1_carry__1_i_3_n_1\
    );
\max_found1_carry__1_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => val1(17),
      I1 => val2(17),
      I2 => val1(16),
      I3 => val2(16),
      O => \max_found1_carry__1_i_4_n_1\
    );
\max_found1_carry__1_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => val2(23),
      I1 => val1(23),
      I2 => val2(22),
      I3 => val1(22),
      O => \max_found1_carry__1_i_5_n_1\
    );
\max_found1_carry__1_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => val2(21),
      I1 => val1(21),
      I2 => val2(20),
      I3 => val1(20),
      O => \max_found1_carry__1_i_6_n_1\
    );
\max_found1_carry__1_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => val2(19),
      I1 => val1(19),
      I2 => val2(18),
      I3 => val1(18),
      O => \max_found1_carry__1_i_7_n_1\
    );
\max_found1_carry__1_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => val2(17),
      I1 => val1(17),
      I2 => val2(16),
      I3 => val1(16),
      O => \max_found1_carry__1_i_8_n_1\
    );
\max_found1_carry__2\: unisim.vcomponents.CARRY4
     port map (
      CI => \max_found1_carry__1_n_1\,
      CO(3) => max_found1,
      CO(2) => \max_found1_carry__2_n_2\,
      CO(1) => \max_found1_carry__2_n_3\,
      CO(0) => \max_found1_carry__2_n_4\,
      CYINIT => '0',
      DI(3) => \max_found1_carry__2_i_1_n_1\,
      DI(2) => \max_found1_carry__2_i_2_n_1\,
      DI(1) => \max_found1_carry__2_i_3_n_1\,
      DI(0) => \max_found1_carry__2_i_4_n_1\,
      O(3 downto 0) => \NLW_max_found1_carry__2_O_UNCONNECTED\(3 downto 0),
      S(3) => \max_found1_carry__2_i_5_n_1\,
      S(2) => \max_found1_carry__2_i_6_n_1\,
      S(1) => \max_found1_carry__2_i_7_n_1\,
      S(0) => \max_found1_carry__2_i_8_n_1\
    );
\max_found1_carry__2_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => val2(31),
      I1 => val1(31),
      I2 => val1(30),
      I3 => val2(30),
      O => \max_found1_carry__2_i_1_n_1\
    );
\max_found1_carry__2_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => val1(29),
      I1 => val2(29),
      I2 => val1(28),
      I3 => val2(28),
      O => \max_found1_carry__2_i_2_n_1\
    );
\max_found1_carry__2_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => val1(27),
      I1 => val2(27),
      I2 => val1(26),
      I3 => val2(26),
      O => \max_found1_carry__2_i_3_n_1\
    );
\max_found1_carry__2_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => val1(25),
      I1 => val2(25),
      I2 => val1(24),
      I3 => val2(24),
      O => \max_found1_carry__2_i_4_n_1\
    );
\max_found1_carry__2_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => val2(31),
      I1 => val1(31),
      I2 => val2(30),
      I3 => val1(30),
      O => \max_found1_carry__2_i_5_n_1\
    );
\max_found1_carry__2_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => val2(29),
      I1 => val1(29),
      I2 => val2(28),
      I3 => val1(28),
      O => \max_found1_carry__2_i_6_n_1\
    );
\max_found1_carry__2_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => val2(27),
      I1 => val1(27),
      I2 => val2(26),
      I3 => val1(26),
      O => \max_found1_carry__2_i_7_n_1\
    );
\max_found1_carry__2_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => val2(25),
      I1 => val1(25),
      I2 => val2(24),
      I3 => val1(24),
      O => \max_found1_carry__2_i_8_n_1\
    );
max_found1_carry_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => val1(7),
      I1 => val2(7),
      I2 => val1(6),
      I3 => val2(6),
      O => max_found1_carry_i_1_n_1
    );
max_found1_carry_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => val1(5),
      I1 => val2(5),
      I2 => val1(4),
      I3 => val2(4),
      O => max_found1_carry_i_2_n_1
    );
max_found1_carry_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => val1(3),
      I1 => val2(3),
      I2 => val1(2),
      I3 => val2(2),
      O => max_found1_carry_i_3_n_1
    );
max_found1_carry_i_4: unisim.vcomponents.LUT4
    generic map(
      INIT => X"22B2"
    )
        port map (
      I0 => val1(1),
      I1 => val2(1),
      I2 => val1(0),
      I3 => val2(0),
      O => max_found1_carry_i_4_n_1
    );
max_found1_carry_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => val2(7),
      I1 => val1(7),
      I2 => val2(6),
      I3 => val1(6),
      O => max_found1_carry_i_5_n_1
    );
max_found1_carry_i_6: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => val2(5),
      I1 => val1(5),
      I2 => val2(4),
      I3 => val1(4),
      O => max_found1_carry_i_6_n_1
    );
max_found1_carry_i_7: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => val2(3),
      I1 => val1(3),
      I2 => val2(2),
      I3 => val1(2),
      O => max_found1_carry_i_7_n_1
    );
max_found1_carry_i_8: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => val2(1),
      I1 => val1(1),
      I2 => val2(0),
      I3 => val1(0),
      O => max_found1_carry_i_8_n_1
    );
\max_found1_inferred__0/i__carry\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \max_found1_inferred__0/i__carry_n_1\,
      CO(2) => \max_found1_inferred__0/i__carry_n_2\,
      CO(1) => \max_found1_inferred__0/i__carry_n_3\,
      CO(0) => \max_found1_inferred__0/i__carry_n_4\,
      CYINIT => '0',
      DI(3) => \i__carry_i_1_n_1\,
      DI(2) => \i__carry_i_2_n_1\,
      DI(1) => \i__carry_i_3_n_1\,
      DI(0) => \i__carry_i_4_n_1\,
      O(3 downto 0) => \NLW_max_found1_inferred__0/i__carry_O_UNCONNECTED\(3 downto 0),
      S(3) => \i__carry_i_5_n_1\,
      S(2) => \i__carry_i_6_n_1\,
      S(1) => \i__carry_i_7_n_1\,
      S(0) => \i__carry_i_8_n_1\
    );
\max_found1_inferred__0/i__carry__0\: unisim.vcomponents.CARRY4
     port map (
      CI => \max_found1_inferred__0/i__carry_n_1\,
      CO(3) => \max_found1_inferred__0/i__carry__0_n_1\,
      CO(2) => \max_found1_inferred__0/i__carry__0_n_2\,
      CO(1) => \max_found1_inferred__0/i__carry__0_n_3\,
      CO(0) => \max_found1_inferred__0/i__carry__0_n_4\,
      CYINIT => '0',
      DI(3) => \i__carry__0_i_1_n_1\,
      DI(2) => \i__carry__0_i_2_n_1\,
      DI(1) => \i__carry__0_i_3_n_1\,
      DI(0) => \i__carry__0_i_4_n_1\,
      O(3 downto 0) => \NLW_max_found1_inferred__0/i__carry__0_O_UNCONNECTED\(3 downto 0),
      S(3) => \i__carry__0_i_5_n_1\,
      S(2) => \i__carry__0_i_6_n_1\,
      S(1) => \i__carry__0_i_7_n_1\,
      S(0) => \i__carry__0_i_8_n_1\
    );
\max_found1_inferred__0/i__carry__1\: unisim.vcomponents.CARRY4
     port map (
      CI => \max_found1_inferred__0/i__carry__0_n_1\,
      CO(3) => \max_found1_inferred__0/i__carry__1_n_1\,
      CO(2) => \max_found1_inferred__0/i__carry__1_n_2\,
      CO(1) => \max_found1_inferred__0/i__carry__1_n_3\,
      CO(0) => \max_found1_inferred__0/i__carry__1_n_4\,
      CYINIT => '0',
      DI(3) => \i__carry__1_i_1_n_1\,
      DI(2) => \i__carry__1_i_2_n_1\,
      DI(1) => \i__carry__1_i_3_n_1\,
      DI(0) => \i__carry__1_i_4_n_1\,
      O(3 downto 0) => \NLW_max_found1_inferred__0/i__carry__1_O_UNCONNECTED\(3 downto 0),
      S(3) => \i__carry__1_i_5_n_1\,
      S(2) => \i__carry__1_i_6_n_1\,
      S(1) => \i__carry__1_i_7_n_1\,
      S(0) => \i__carry__1_i_8_n_1\
    );
\max_found1_inferred__0/i__carry__2\: unisim.vcomponents.CARRY4
     port map (
      CI => \max_found1_inferred__0/i__carry__1_n_1\,
      CO(3) => max_found12_in,
      CO(2) => \max_found1_inferred__0/i__carry__2_n_2\,
      CO(1) => \max_found1_inferred__0/i__carry__2_n_3\,
      CO(0) => \max_found1_inferred__0/i__carry__2_n_4\,
      CYINIT => '0',
      DI(3) => \i__carry__2_i_1_n_1\,
      DI(2) => \i__carry__2_i_2_n_1\,
      DI(1) => \i__carry__2_i_3_n_1\,
      DI(0) => \i__carry__2_i_4_n_1\,
      O(3 downto 0) => \NLW_max_found1_inferred__0/i__carry__2_O_UNCONNECTED\(3 downto 0),
      S(3) => \i__carry__2_i_5_n_1\,
      S(2) => \i__carry__2_i_6_n_1\,
      S(1) => \i__carry__2_i_7_n_1\,
      S(0) => \i__carry__2_i_8_n_1\
    );
max_found_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8080FFFF80808000"
    )
        port map (
      I0 => max_found12_in,
      I1 => max_found1,
      I2 => \FSM_onehot_state_reg_n_1_[2]\,
      I3 => start,
      I4 => resig,
      I5 => \^max_found\,
      O => max_found_i_1_n_1
    );
max_found_reg: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => max_found_i_1_n_1,
      Q => \^max_found\,
      R => '0'
    );
resig_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"34"
    )
        port map (
      I0 => fifo_reset(0),
      I1 => resig,
      I2 => resig_reg_n_1,
      O => resig_i_1_n_1
    );
resig_reg: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => resig_i_1_n_1,
      Q => resig_reg_n_1,
      R => '0'
    );
rst_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => resig_reg_n_1,
      I1 => resig,
      I2 => \^rst\,
      O => rst_i_1_n_1
    );
rst_reg: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => rst_i_1_n_1,
      Q => \^rst\,
      R => '0'
    );
start_fifo_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"80AAFFFF80AA80AA"
    )
        port map (
      I0 => \FSM_onehot_state_reg_n_1_[2]\,
      I1 => max_found1,
      I2 => max_found12_in,
      I3 => start,
      I4 => resig,
      I5 => \^start_fifo\,
      O => start_fifo_i_1_n_1
    );
start_fifo_reg: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => '1',
      D => start_fifo_i_1_n_1,
      Q => \^start_fifo\,
      R => '0'
    );
state0_carry: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => state0_carry_n_1,
      CO(2) => state0_carry_n_2,
      CO(1) => state0_carry_n_3,
      CO(0) => state0_carry_n_4,
      CYINIT => '0',
      DI(3) => state0_carry_i_1_n_1,
      DI(2) => state0_carry_i_2_n_1,
      DI(1) => state0_carry_i_3_n_1,
      DI(0) => state0_carry_i_4_n_1,
      O(3 downto 0) => NLW_state0_carry_O_UNCONNECTED(3 downto 0),
      S(3) => state0_carry_i_5_n_1,
      S(2) => state0_carry_i_6_n_1,
      S(1) => state0_carry_i_7_n_1,
      S(0) => state0_carry_i_8_n_1
    );
\state0_carry__0\: unisim.vcomponents.CARRY4
     port map (
      CI => state0_carry_n_1,
      CO(3) => \state0_carry__0_n_1\,
      CO(2) => \state0_carry__0_n_2\,
      CO(1) => \state0_carry__0_n_3\,
      CO(0) => \state0_carry__0_n_4\,
      CYINIT => '0',
      DI(3) => \state0_carry__0_i_1_n_1\,
      DI(2) => \state0_carry__0_i_2_n_1\,
      DI(1) => \state0_carry__0_i_3_n_1\,
      DI(0) => \state0_carry__0_i_4_n_1\,
      O(3 downto 0) => \NLW_state0_carry__0_O_UNCONNECTED\(3 downto 0),
      S(3) => \state0_carry__0_i_5_n_1\,
      S(2) => \state0_carry__0_i_6_n_1\,
      S(1) => \state0_carry__0_i_7_n_1\,
      S(0) => \state0_carry__0_i_8_n_1\
    );
\state0_carry__0_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => in3(16),
      I1 => in3(17),
      O => \state0_carry__0_i_1_n_1\
    );
\state0_carry__0_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => in3(14),
      I1 => in3(15),
      O => \state0_carry__0_i_2_n_1\
    );
\state0_carry__0_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => in3(12),
      I1 => in3(13),
      O => \state0_carry__0_i_3_n_1\
    );
\state0_carry__0_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => in3(10),
      I1 => in3(11),
      O => \state0_carry__0_i_4_n_1\
    );
\state0_carry__0_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => in3(16),
      I1 => in3(17),
      O => \state0_carry__0_i_5_n_1\
    );
\state0_carry__0_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => in3(14),
      I1 => in3(15),
      O => \state0_carry__0_i_6_n_1\
    );
\state0_carry__0_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => in3(12),
      I1 => in3(13),
      O => \state0_carry__0_i_7_n_1\
    );
\state0_carry__0_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => in3(10),
      I1 => in3(11),
      O => \state0_carry__0_i_8_n_1\
    );
\state0_carry__1\: unisim.vcomponents.CARRY4
     port map (
      CI => \state0_carry__0_n_1\,
      CO(3) => \state0_carry__1_n_1\,
      CO(2) => \state0_carry__1_n_2\,
      CO(1) => \state0_carry__1_n_3\,
      CO(0) => \state0_carry__1_n_4\,
      CYINIT => '0',
      DI(3) => \state0_carry__1_i_1_n_1\,
      DI(2) => \state0_carry__1_i_2_n_1\,
      DI(1) => \state0_carry__1_i_3_n_1\,
      DI(0) => \state0_carry__1_i_4_n_1\,
      O(3 downto 0) => \NLW_state0_carry__1_O_UNCONNECTED\(3 downto 0),
      S(3) => \state0_carry__1_i_5_n_1\,
      S(2) => \state0_carry__1_i_6_n_1\,
      S(1) => \state0_carry__1_i_7_n_1\,
      S(0) => \state0_carry__1_i_8_n_1\
    );
\state0_carry__1_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => in3(24),
      I1 => in3(25),
      O => \state0_carry__1_i_1_n_1\
    );
\state0_carry__1_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => in3(22),
      I1 => in3(23),
      O => \state0_carry__1_i_2_n_1\
    );
\state0_carry__1_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => in3(20),
      I1 => in3(21),
      O => \state0_carry__1_i_3_n_1\
    );
\state0_carry__1_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => in3(18),
      I1 => in3(19),
      O => \state0_carry__1_i_4_n_1\
    );
\state0_carry__1_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => in3(24),
      I1 => in3(25),
      O => \state0_carry__1_i_5_n_1\
    );
\state0_carry__1_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => in3(22),
      I1 => in3(23),
      O => \state0_carry__1_i_6_n_1\
    );
\state0_carry__1_i_7\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => in3(20),
      I1 => in3(21),
      O => \state0_carry__1_i_7_n_1\
    );
\state0_carry__1_i_8\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => in3(18),
      I1 => in3(19),
      O => \state0_carry__1_i_8_n_1\
    );
\state0_carry__2\: unisim.vcomponents.CARRY4
     port map (
      CI => \state0_carry__1_n_1\,
      CO(3) => \NLW_state0_carry__2_CO_UNCONNECTED\(3),
      CO(2) => \state0_carry__2_n_2\,
      CO(1) => \state0_carry__2_n_3\,
      CO(0) => \state0_carry__2_n_4\,
      CYINIT => '0',
      DI(3) => '0',
      DI(2) => \state0_carry__2_i_1_n_1\,
      DI(1) => \state0_carry__2_i_2_n_1\,
      DI(0) => \state0_carry__2_i_3_n_1\,
      O(3 downto 0) => \NLW_state0_carry__2_O_UNCONNECTED\(3 downto 0),
      S(3) => '0',
      S(2) => \state0_carry__2_i_4_n_1\,
      S(1) => \state0_carry__2_i_5_n_1\,
      S(0) => \state0_carry__2_i_6_n_1\
    );
\state0_carry__2_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => in3(30),
      I1 => in3(31),
      O => \state0_carry__2_i_1_n_1\
    );
\state0_carry__2_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => in3(28),
      I1 => in3(29),
      O => \state0_carry__2_i_2_n_1\
    );
\state0_carry__2_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => in3(26),
      I1 => in3(27),
      O => \state0_carry__2_i_3_n_1\
    );
\state0_carry__2_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => in3(30),
      I1 => in3(31),
      O => \state0_carry__2_i_4_n_1\
    );
\state0_carry__2_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => in3(28),
      I1 => in3(29),
      O => \state0_carry__2_i_5_n_1\
    );
\state0_carry__2_i_6\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => in3(26),
      I1 => in3(27),
      O => \state0_carry__2_i_6_n_1\
    );
state0_carry_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => in3(8),
      I1 => in3(9),
      O => state0_carry_i_1_n_1
    );
state0_carry_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => in3(6),
      I1 => in3(7),
      O => state0_carry_i_2_n_1
    );
state0_carry_i_3: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => in3(4),
      I1 => in3(5),
      O => state0_carry_i_3_n_1
    );
state0_carry_i_4: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => in3(2),
      I1 => in3(3),
      O => state0_carry_i_4_n_1
    );
state0_carry_i_5: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => in3(8),
      I1 => in3(9),
      O => state0_carry_i_5_n_1
    );
state0_carry_i_6: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => in3(6),
      I1 => in3(7),
      O => state0_carry_i_6_n_1
    );
state0_carry_i_7: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => in3(4),
      I1 => in3(5),
      O => state0_carry_i_7_n_1
    );
state0_carry_i_8: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => in3(2),
      I1 => in3(3),
      O => state0_carry_i_8_n_1
    );
\val0_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val1(0),
      Q => val0(0),
      R => \val2[31]_i_1_n_1\
    );
\val0_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val1(10),
      Q => val0(10),
      R => \val2[31]_i_1_n_1\
    );
\val0_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val1(11),
      Q => val0(11),
      R => \val2[31]_i_1_n_1\
    );
\val0_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val1(12),
      Q => val0(12),
      R => \val2[31]_i_1_n_1\
    );
\val0_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val1(13),
      Q => val0(13),
      R => \val2[31]_i_1_n_1\
    );
\val0_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val1(14),
      Q => val0(14),
      R => \val2[31]_i_1_n_1\
    );
\val0_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val1(15),
      Q => val0(15),
      R => \val2[31]_i_1_n_1\
    );
\val0_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val1(16),
      Q => val0(16),
      R => \val2[31]_i_1_n_1\
    );
\val0_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val1(17),
      Q => val0(17),
      R => \val2[31]_i_1_n_1\
    );
\val0_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val1(18),
      Q => val0(18),
      R => \val2[31]_i_1_n_1\
    );
\val0_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val1(19),
      Q => val0(19),
      R => \val2[31]_i_1_n_1\
    );
\val0_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val1(1),
      Q => val0(1),
      R => \val2[31]_i_1_n_1\
    );
\val0_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val1(20),
      Q => val0(20),
      R => \val2[31]_i_1_n_1\
    );
\val0_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val1(21),
      Q => val0(21),
      R => \val2[31]_i_1_n_1\
    );
\val0_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val1(22),
      Q => val0(22),
      R => \val2[31]_i_1_n_1\
    );
\val0_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val1(23),
      Q => val0(23),
      R => \val2[31]_i_1_n_1\
    );
\val0_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val1(24),
      Q => val0(24),
      R => \val2[31]_i_1_n_1\
    );
\val0_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val1(25),
      Q => val0(25),
      R => \val2[31]_i_1_n_1\
    );
\val0_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val1(26),
      Q => val0(26),
      R => \val2[31]_i_1_n_1\
    );
\val0_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val1(27),
      Q => val0(27),
      R => \val2[31]_i_1_n_1\
    );
\val0_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val1(28),
      Q => val0(28),
      R => \val2[31]_i_1_n_1\
    );
\val0_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val1(29),
      Q => val0(29),
      R => \val2[31]_i_1_n_1\
    );
\val0_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val1(2),
      Q => val0(2),
      R => \val2[31]_i_1_n_1\
    );
\val0_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val1(30),
      Q => val0(30),
      R => \val2[31]_i_1_n_1\
    );
\val0_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val1(31),
      Q => val0(31),
      R => \val2[31]_i_1_n_1\
    );
\val0_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val1(3),
      Q => val0(3),
      R => \val2[31]_i_1_n_1\
    );
\val0_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val1(4),
      Q => val0(4),
      R => \val2[31]_i_1_n_1\
    );
\val0_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val1(5),
      Q => val0(5),
      R => \val2[31]_i_1_n_1\
    );
\val0_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val1(6),
      Q => val0(6),
      R => \val2[31]_i_1_n_1\
    );
\val0_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val1(7),
      Q => val0(7),
      R => \val2[31]_i_1_n_1\
    );
\val0_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val1(8),
      Q => val0(8),
      R => \val2[31]_i_1_n_1\
    );
\val0_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val1(9),
      Q => val0(9),
      R => \val2[31]_i_1_n_1\
    );
\val1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val2(0),
      Q => val1(0),
      R => \val2[31]_i_1_n_1\
    );
\val1_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val2(10),
      Q => val1(10),
      R => \val2[31]_i_1_n_1\
    );
\val1_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val2(11),
      Q => val1(11),
      R => \val2[31]_i_1_n_1\
    );
\val1_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val2(12),
      Q => val1(12),
      R => \val2[31]_i_1_n_1\
    );
\val1_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val2(13),
      Q => val1(13),
      R => \val2[31]_i_1_n_1\
    );
\val1_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val2(14),
      Q => val1(14),
      R => \val2[31]_i_1_n_1\
    );
\val1_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val2(15),
      Q => val1(15),
      R => \val2[31]_i_1_n_1\
    );
\val1_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val2(16),
      Q => val1(16),
      R => \val2[31]_i_1_n_1\
    );
\val1_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val2(17),
      Q => val1(17),
      R => \val2[31]_i_1_n_1\
    );
\val1_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val2(18),
      Q => val1(18),
      R => \val2[31]_i_1_n_1\
    );
\val1_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val2(19),
      Q => val1(19),
      R => \val2[31]_i_1_n_1\
    );
\val1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val2(1),
      Q => val1(1),
      R => \val2[31]_i_1_n_1\
    );
\val1_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val2(20),
      Q => val1(20),
      R => \val2[31]_i_1_n_1\
    );
\val1_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val2(21),
      Q => val1(21),
      R => \val2[31]_i_1_n_1\
    );
\val1_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val2(22),
      Q => val1(22),
      R => \val2[31]_i_1_n_1\
    );
\val1_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val2(23),
      Q => val1(23),
      R => \val2[31]_i_1_n_1\
    );
\val1_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val2(24),
      Q => val1(24),
      R => \val2[31]_i_1_n_1\
    );
\val1_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val2(25),
      Q => val1(25),
      R => \val2[31]_i_1_n_1\
    );
\val1_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val2(26),
      Q => val1(26),
      R => \val2[31]_i_1_n_1\
    );
\val1_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val2(27),
      Q => val1(27),
      R => \val2[31]_i_1_n_1\
    );
\val1_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val2(28),
      Q => val1(28),
      R => \val2[31]_i_1_n_1\
    );
\val1_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val2(29),
      Q => val1(29),
      R => \val2[31]_i_1_n_1\
    );
\val1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val2(2),
      Q => val1(2),
      R => \val2[31]_i_1_n_1\
    );
\val1_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val2(30),
      Q => val1(30),
      R => \val2[31]_i_1_n_1\
    );
\val1_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val2(31),
      Q => val1(31),
      R => \val2[31]_i_1_n_1\
    );
\val1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val2(3),
      Q => val1(3),
      R => \val2[31]_i_1_n_1\
    );
\val1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val2(4),
      Q => val1(4),
      R => \val2[31]_i_1_n_1\
    );
\val1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val2(5),
      Q => val1(5),
      R => \val2[31]_i_1_n_1\
    );
\val1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val2(6),
      Q => val1(6),
      R => \val2[31]_i_1_n_1\
    );
\val1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val2(7),
      Q => val1(7),
      R => \val2[31]_i_1_n_1\
    );
\val1_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val2(8),
      Q => val1(8),
      R => \val2[31]_i_1_n_1\
    );
\val1_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val2(9),
      Q => val1(9),
      R => \val2[31]_i_1_n_1\
    );
\val2[31]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFFFD500"
    )
        port map (
      I0 => start,
      I1 => max_found12_in,
      I2 => max_found1,
      I3 => \FSM_onehot_state_reg_n_1_[2]\,
      I4 => val_last_1,
      I5 => \FSM_onehot_state_reg_n_1_[1]\,
      O => \val2[31]_i_1_n_1\
    );
\val2[31]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EAAAEEEE"
    )
        port map (
      I0 => val_last_1,
      I1 => \FSM_onehot_state_reg_n_1_[2]\,
      I2 => max_found1,
      I3 => max_found12_in,
      I4 => start,
      O => \val2[31]_i_2_n_1\
    );
\val2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val_in(0),
      Q => val2(0),
      R => \val2[31]_i_1_n_1\
    );
\val2_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val_in(10),
      Q => val2(10),
      R => \val2[31]_i_1_n_1\
    );
\val2_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val_in(11),
      Q => val2(11),
      R => \val2[31]_i_1_n_1\
    );
\val2_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val_in(12),
      Q => val2(12),
      R => \val2[31]_i_1_n_1\
    );
\val2_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val_in(13),
      Q => val2(13),
      R => \val2[31]_i_1_n_1\
    );
\val2_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val_in(14),
      Q => val2(14),
      R => \val2[31]_i_1_n_1\
    );
\val2_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val_in(15),
      Q => val2(15),
      R => \val2[31]_i_1_n_1\
    );
\val2_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val_in(16),
      Q => val2(16),
      R => \val2[31]_i_1_n_1\
    );
\val2_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val_in(17),
      Q => val2(17),
      R => \val2[31]_i_1_n_1\
    );
\val2_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val_in(18),
      Q => val2(18),
      R => \val2[31]_i_1_n_1\
    );
\val2_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val_in(19),
      Q => val2(19),
      R => \val2[31]_i_1_n_1\
    );
\val2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val_in(1),
      Q => val2(1),
      R => \val2[31]_i_1_n_1\
    );
\val2_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val_in(20),
      Q => val2(20),
      R => \val2[31]_i_1_n_1\
    );
\val2_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val_in(21),
      Q => val2(21),
      R => \val2[31]_i_1_n_1\
    );
\val2_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val_in(22),
      Q => val2(22),
      R => \val2[31]_i_1_n_1\
    );
\val2_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val_in(23),
      Q => val2(23),
      R => \val2[31]_i_1_n_1\
    );
\val2_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val_in(24),
      Q => val2(24),
      R => \val2[31]_i_1_n_1\
    );
\val2_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val_in(25),
      Q => val2(25),
      R => \val2[31]_i_1_n_1\
    );
\val2_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val_in(26),
      Q => val2(26),
      R => \val2[31]_i_1_n_1\
    );
\val2_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val_in(27),
      Q => val2(27),
      R => \val2[31]_i_1_n_1\
    );
\val2_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val_in(28),
      Q => val2(28),
      R => \val2[31]_i_1_n_1\
    );
\val2_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val_in(29),
      Q => val2(29),
      R => \val2[31]_i_1_n_1\
    );
\val2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val_in(2),
      Q => val2(2),
      R => \val2[31]_i_1_n_1\
    );
\val2_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val_in(30),
      Q => val2(30),
      R => \val2[31]_i_1_n_1\
    );
\val2_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val_in(31),
      Q => val2(31),
      R => \val2[31]_i_1_n_1\
    );
\val2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val_in(3),
      Q => val2(3),
      R => \val2[31]_i_1_n_1\
    );
\val2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val_in(4),
      Q => val2(4),
      R => \val2[31]_i_1_n_1\
    );
\val2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val_in(5),
      Q => val2(5),
      R => \val2[31]_i_1_n_1\
    );
\val2_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val_in(6),
      Q => val2(6),
      R => \val2[31]_i_1_n_1\
    );
\val2_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val_in(7),
      Q => val2(7),
      R => \val2[31]_i_1_n_1\
    );
\val2_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val_in(8),
      Q => val2(8),
      R => \val2[31]_i_1_n_1\
    );
\val2_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => \val2[31]_i_2_n_1\,
      D => val_in(9),
      Q => val2(9),
      R => \val2[31]_i_1_n_1\
    );
\val_last[31]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000004"
    )
        port map (
      I0 => p_0_in,
      I1 => \FSM_onehot_state_reg_n_1_[1]\,
      I2 => i(0),
      I3 => \val_last[31]_i_2_n_1\,
      I4 => \val_last[31]_i_3_n_1\,
      I5 => \val_last[31]_i_4_n_1\,
      O => val_last_1
    );
\val_last[31]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => i(12),
      I1 => i(13),
      I2 => i(10),
      I3 => i(11),
      I4 => \val_last[31]_i_5_n_1\,
      O => \val_last[31]_i_2_n_1\
    );
\val_last[31]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFBFF"
    )
        port map (
      I0 => i(5),
      I1 => i(4),
      I2 => i(2),
      I3 => i(3),
      I4 => \val_last[31]_i_6_n_1\,
      O => \val_last[31]_i_3_n_1\
    );
\val_last[31]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \val_last[31]_i_7_n_1\,
      I1 => \val_last[31]_i_8_n_1\,
      I2 => i(31),
      I3 => i(30),
      I4 => i(1),
      I5 => \val_last[31]_i_9_n_1\,
      O => \val_last[31]_i_4_n_1\
    );
\val_last[31]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => i(15),
      I1 => i(14),
      I2 => i(17),
      I3 => i(16),
      O => \val_last[31]_i_5_n_1\
    );
\val_last[31]_i_6\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => i(7),
      I1 => i(6),
      I2 => i(9),
      I3 => i(8),
      O => \val_last[31]_i_6_n_1\
    );
\val_last[31]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => i(23),
      I1 => i(22),
      I2 => i(25),
      I3 => i(24),
      O => \val_last[31]_i_7_n_1\
    );
\val_last[31]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => i(19),
      I1 => i(18),
      I2 => i(21),
      I3 => i(20),
      O => \val_last[31]_i_8_n_1\
    );
\val_last[31]_i_9\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => i(27),
      I1 => i(26),
      I2 => i(29),
      I3 => i(28),
      O => \val_last[31]_i_9_n_1\
    );
\val_last_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => val_last_1,
      D => val_in(0),
      Q => val_last(0),
      R => '0'
    );
\val_last_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => val_last_1,
      D => val_in(10),
      Q => val_last(10),
      R => '0'
    );
\val_last_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => val_last_1,
      D => val_in(11),
      Q => val_last(11),
      R => '0'
    );
\val_last_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => val_last_1,
      D => val_in(12),
      Q => val_last(12),
      R => '0'
    );
\val_last_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => val_last_1,
      D => val_in(13),
      Q => val_last(13),
      R => '0'
    );
\val_last_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => val_last_1,
      D => val_in(14),
      Q => val_last(14),
      R => '0'
    );
\val_last_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => val_last_1,
      D => val_in(15),
      Q => val_last(15),
      R => '0'
    );
\val_last_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => val_last_1,
      D => val_in(16),
      Q => val_last(16),
      R => '0'
    );
\val_last_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => val_last_1,
      D => val_in(17),
      Q => val_last(17),
      R => '0'
    );
\val_last_reg[18]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => val_last_1,
      D => val_in(18),
      Q => val_last(18),
      R => '0'
    );
\val_last_reg[19]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => val_last_1,
      D => val_in(19),
      Q => val_last(19),
      R => '0'
    );
\val_last_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => val_last_1,
      D => val_in(1),
      Q => val_last(1),
      R => '0'
    );
\val_last_reg[20]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => val_last_1,
      D => val_in(20),
      Q => val_last(20),
      R => '0'
    );
\val_last_reg[21]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => val_last_1,
      D => val_in(21),
      Q => val_last(21),
      R => '0'
    );
\val_last_reg[22]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => val_last_1,
      D => val_in(22),
      Q => val_last(22),
      R => '0'
    );
\val_last_reg[23]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => val_last_1,
      D => val_in(23),
      Q => val_last(23),
      R => '0'
    );
\val_last_reg[24]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => val_last_1,
      D => val_in(24),
      Q => val_last(24),
      R => '0'
    );
\val_last_reg[25]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => val_last_1,
      D => val_in(25),
      Q => val_last(25),
      R => '0'
    );
\val_last_reg[26]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => val_last_1,
      D => val_in(26),
      Q => val_last(26),
      R => '0'
    );
\val_last_reg[27]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => val_last_1,
      D => val_in(27),
      Q => val_last(27),
      R => '0'
    );
\val_last_reg[28]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => val_last_1,
      D => val_in(28),
      Q => val_last(28),
      R => '0'
    );
\val_last_reg[29]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => val_last_1,
      D => val_in(29),
      Q => val_last(29),
      R => '0'
    );
\val_last_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => val_last_1,
      D => val_in(2),
      Q => val_last(2),
      R => '0'
    );
\val_last_reg[30]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => val_last_1,
      D => val_in(30),
      Q => val_last(30),
      R => '0'
    );
\val_last_reg[31]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => val_last_1,
      D => val_in(31),
      Q => val_last(31),
      R => '0'
    );
\val_last_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => val_last_1,
      D => val_in(3),
      Q => val_last(3),
      R => '0'
    );
\val_last_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => val_last_1,
      D => val_in(4),
      Q => val_last(4),
      R => '0'
    );
\val_last_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => val_last_1,
      D => val_in(5),
      Q => val_last(5),
      R => '0'
    );
\val_last_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => val_last_1,
      D => val_in(6),
      Q => val_last(6),
      R => '0'
    );
\val_last_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => val_last_1,
      D => val_in(7),
      Q => val_last(7),
      R => '0'
    );
\val_last_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => val_last_1,
      D => val_in(8),
      Q => val_last(8),
      R => '0'
    );
\val_last_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => clk,
      CE => val_last_1,
      D => val_in(9),
      Q => val_last(9),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity pdm_to_pcm_energy_compare_0_0 is
  port (
    clk : in STD_LOGIC;
    start : in STD_LOGIC;
    t_finish : in STD_LOGIC;
    val_in : in STD_LOGIC_VECTOR ( 31 downto 0 );
    max_found : out STD_LOGIC;
    start_fifo : out STD_LOGIC;
    rst : out STD_LOGIC;
    val_out : out STD_LOGIC_VECTOR ( 31 downto 0 )
  );
  attribute NotValidForBitStream : boolean;
  attribute NotValidForBitStream of pdm_to_pcm_energy_compare_0_0 : entity is true;
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of pdm_to_pcm_energy_compare_0_0 : entity is "pdm_to_pcm_energy_compare_0_0,energy_compare,{}";
  attribute downgradeipidentifiedwarnings : string;
  attribute downgradeipidentifiedwarnings of pdm_to_pcm_energy_compare_0_0 : entity is "yes";
  attribute ip_definition_source : string;
  attribute ip_definition_source of pdm_to_pcm_energy_compare_0_0 : entity is "module_ref";
  attribute x_core_info : string;
  attribute x_core_info of pdm_to_pcm_energy_compare_0_0 : entity is "energy_compare,Vivado 2019.1";
end pdm_to_pcm_energy_compare_0_0;

architecture STRUCTURE of pdm_to_pcm_energy_compare_0_0 is
  signal \<const0>\ : STD_LOGIC;
  attribute x_interface_info : string;
  attribute x_interface_info of clk : signal is "xilinx.com:signal:clock:1.0 clk CLK";
  attribute x_interface_parameter : string;
  attribute x_interface_parameter of clk : signal is "XIL_INTERFACENAME clk, ASSOCIATED_RESET rst, FREQ_HZ 100000000, PHASE 0.000, INSERT_VIP 0";
  attribute x_interface_info of rst : signal is "xilinx.com:signal:reset:1.0 rst RST";
  attribute x_interface_parameter of rst : signal is "XIL_INTERFACENAME rst, POLARITY ACTIVE_LOW, INSERT_VIP 0";
begin
  val_out(31) <= \<const0>\;
  val_out(30) <= \<const0>\;
  val_out(29) <= \<const0>\;
  val_out(28) <= \<const0>\;
  val_out(27) <= \<const0>\;
  val_out(26) <= \<const0>\;
  val_out(25) <= \<const0>\;
  val_out(24) <= \<const0>\;
  val_out(23) <= \<const0>\;
  val_out(22) <= \<const0>\;
  val_out(21) <= \<const0>\;
  val_out(20) <= \<const0>\;
  val_out(19) <= \<const0>\;
  val_out(18) <= \<const0>\;
  val_out(17) <= \<const0>\;
  val_out(16) <= \<const0>\;
  val_out(15) <= \<const0>\;
  val_out(14) <= \<const0>\;
  val_out(13) <= \<const0>\;
  val_out(12) <= \<const0>\;
  val_out(11) <= \<const0>\;
  val_out(10) <= \<const0>\;
  val_out(9) <= \<const0>\;
  val_out(8) <= \<const0>\;
  val_out(7) <= \<const0>\;
  val_out(6) <= \<const0>\;
  val_out(5) <= \<const0>\;
  val_out(4) <= \<const0>\;
  val_out(3) <= \<const0>\;
  val_out(2) <= \<const0>\;
  val_out(1) <= \<const0>\;
  val_out(0) <= \<const0>\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
U0: entity work.pdm_to_pcm_energy_compare_0_0_energy_compare
     port map (
      clk => clk,
      max_found => max_found,
      rst => rst,
      start => start,
      start_fifo => start_fifo,
      val_in(31 downto 0) => val_in(31 downto 0)
    );
end STRUCTURE;
