{
   "ExpandedHierarchyInLayout":"",
   "guistr":"# # String gsaved with Nlview 7.0.19  2019-03-26 bk=1.5019 VDI=41 GEI=35 GUI=JA:9.0 non-TLS
#  -string -flagsOSRD
preplace port resetn -pg 1 -lvl 0 -x -10 -y 1030 -defaultsOSRD
preplace port sys_clock -pg 1 -lvl 0 -x -10 -y 1050 -defaultsOSRD
preplace port start -pg 1 -lvl 0 -x -10 -y 1110 -defaultsOSRD
preplace port fifo_almost_full -pg 1 -lvl 11 -x 3490 -y 790 -defaultsOSRD
preplace port fifo_almost_empty -pg 1 -lvl 11 -x 3490 -y 1130 -defaultsOSRD
preplace port fifo_rd_clk -pg 1 -lvl 0 -x -10 -y 940 -defaultsOSRD
preplace port fifo_rd_en -pg 1 -lvl 0 -x -10 -y 960 -defaultsOSRD
preplace portBus pdm_clk -pg 1 -lvl 11 -x 3490 -y 1310 -defaultsOSRD
preplace portBus pcm_data -pg 1 -lvl 11 -x 3490 -y 1250 -defaultsOSRD
preplace portBus pdm_data -pg 1 -lvl 0 -x -10 -y 1270 -defaultsOSRD
preplace inst cic_compiler_0 -pg 1 -lvl 3 -x 760 -y 1240 -defaultsOSRD
preplace inst fir_compiler_0 -pg 1 -lvl 4 -x 1180 -y 1220 -defaultsOSRD
preplace inst fir_compiler_1 -pg 1 -lvl 5 -x 1620 -y 1230 -defaultsOSRD
preplace inst clk_wiz_0 -pg 1 -lvl 1 -x 110 -y 1040 -defaultsOSRD
preplace inst fifo_generator_0 -pg 1 -lvl 10 -x 3290 -y 960 -defaultsOSRD
preplace inst util_vector_logic_0 -pg 1 -lvl 4 -x 1180 -y 1050 -defaultsOSRD
preplace inst util_ds_buf_0 -pg 1 -lvl 10 -x 3290 -y 1310 -defaultsOSRD
preplace inst clk_div_1 -pg 1 -lvl 6 -x 1980 -y 860 -defaultsOSRD
preplace inst util_vector_logic_1 -pg 1 -lvl 10 -x 3290 -y 1190 -defaultsOSRD
preplace inst blk_mem_gen_0 -pg 1 -lvl 10 -x 3290 -y 220 -defaultsOSRD
preplace inst blk_mem_gen_1 -pg 1 -lvl 10 -x 3290 -y 80 -defaultsOSRD
preplace inst c_shift_ram_0 -pg 1 -lvl 9 -x 2950 -y 330 -defaultsOSRD
preplace inst c_shift_ram_1 -pg 1 -lvl 9 -x 2950 -y 130 -defaultsOSRD
preplace inst c_shift_ram_2 -pg 1 -lvl 9 -x 2950 -y 530 -defaultsOSRD
preplace inst c_shift_ram_3 -pg 1 -lvl 9 -x 2950 -y 720 -defaultsOSRD
preplace inst blk_mem_gen_2 -pg 1 -lvl 10 -x 3290 -y 360 -defaultsOSRD
preplace inst blk_mem_gen_3 -pg 1 -lvl 10 -x 3290 -y 500 -defaultsOSRD
preplace inst clk_div_0 -pg 1 -lvl 5 -x 1620 -y 1030 -defaultsOSRD
preplace inst hp_filter_0 -pg 1 -lvl 6 -x 1980 -y 720 -defaultsOSRD
preplace inst timemux_0 -pg 1 -lvl 2 -x 380 -y 1250 -defaultsOSRD
preplace inst demux16_sync_0 -pg 1 -lvl 7 -x 2290 -y 690 -defaultsOSRD
preplace inst energy_compare_0 -pg 1 -lvl 7 -x 2290 -y 880 -defaultsOSRD
preplace inst arithm_block_0 -pg 1 -lvl 10 -x 3290 -y 670 -defaultsOSRD
preplace inst scan_0 -pg 1 -lvl 8 -x 2640 -y 470 -defaultsOSRD
preplace netloc sys_clock_1 1 0 1 NJ 1050
preplace netloc resetn_1 1 0 1 NJ 1030
preplace netloc util_vector_logic_0_Res 1 4 2 1400 880 NJ
preplace netloc clk_wiz_0_locked 1 1 5 NJ 1050 NJ 1050 960 990 1390 860 NJ
preplace netloc cic_compiler_0_m_axis_data_tdata 1 3 1 N 1190
preplace netloc fir_compiler_0_m_axis_data_tdata 1 4 1 N 1200
preplace netloc fir_compiler_1_s_axis_data_tready 1 4 1 N 1240
preplace netloc fir_compiler_0_m_axis_data_tvalid 1 4 1 N 1260
preplace netloc fir_compiler_0_s_axis_data_tready 1 3 1 N 1230
preplace netloc cic_compiler_0_m_axis_data_tvalid 1 3 1 N 1250
preplace netloc fir_compiler_1_m_axis_data_tdata 1 5 1 1820 720n
preplace netloc fifo_generator_0_dout 1 9 2 3110 1370 3470J
preplace netloc fifo_generator_0_almost_empty 1 9 2 3120 1130 NJ
preplace netloc fifo_generator_0_almost_full 1 9 2 3120 790 NJ
preplace netloc fifo_rd_clk_1 1 0 10 NJ 940 NJ 940 NJ 940 NJ 940 NJ 940 NJ 940 2120J 1030 NJ 1030 NJ 1030 3050J
preplace netloc fifo_generator_0_full 1 9 1 3090 900n
preplace netloc util_vector_logic_1_Res 1 5 6 NJ 1250 NJ 1250 NJ 1250 NJ 1250 NJ 1250 3460
preplace netloc util_ds_buf_0_BUFG_O 1 10 1 NJ 1310
preplace netloc start_1 1 0 8 NJ 1110 210 460 NJ 460 NJ 460 NJ 460 NJ 460 NJ 460 N
preplace netloc timemux_0_pdm_data_mux 1 2 1 540 1220n
preplace netloc timemux_0_data_tvalid 1 2 1 N 1260
preplace netloc clk_div_0_clk_out 1 5 1 1840 840n
preplace netloc pdm_data_1 1 0 2 NJ 1270 NJ
preplace netloc hp_filter_0_dout 1 6 1 NJ 720
preplace netloc demux16_sync_0_output_data0 1 7 2 2460 320 NJ
preplace netloc blk_mem_gen_0_douta 1 8 2 2850 240 NJ
preplace netloc blk_mem_gen_1_douta 1 8 2 2790 30 3090J
preplace netloc blk_mem_gen_2_douta 1 8 2 2850 420 3060J
preplace netloc blk_mem_gen_3_douta 1 8 2 2850 630 3060J
preplace netloc clk_wiz_0_clk_out1 1 1 6 200 1340 550 1370 960 1330 1380 650 NJ 650 2120
preplace netloc Net 1 6 4 2100 590 2490 620 2820 620 3070
preplace netloc demux16_sync_0_output_data1 1 7 2 2450 120 NJ
preplace netloc demux16_sync_0_output_data3 1 7 2 NJ 710 N
preplace netloc demux16_sync_0_output_data2 1 7 2 NJ 690 2840
preplace netloc scan_0_address_0 1 8 2 2790 220 NJ
preplace netloc scan_0_address_1 1 8 2 2780 40 3080J
preplace netloc scan_0_address_2 1 8 2 2810 430 3050J
preplace netloc scan_0_address_3 1 8 2 2840 440 3060J
preplace netloc demux16_sync_0_finish 1 7 1 2470 480n
preplace netloc Net1 1 8 1 2830 160n
preplace netloc energy_compare_0_max_found 1 7 1 2480 500n
preplace netloc energy_compare_0_val_out 1 7 3 NJ 900 NJ 900 3050
preplace netloc energy_compare_0_start_fifo 1 7 3 NJ 880 NJ 880 3060
preplace netloc timemux_0_data_tlast 1 2 1 N 1240
preplace netloc cic_compiler_0_m_axis_data_tlast 1 3 1 N 1210
preplace netloc fir_compiler_0_m_axis_data_tlast 1 4 1 N 1220
preplace netloc fir_compiler_1_m_axis_data_tvalid 1 5 2 1830 660 2110J
preplace netloc fir_compiler_1_m_axis_data_tlast 1 5 2 1850 780 2120J
preplace netloc fifo_rd_en_1 1 0 10 10J 950 NJ 950 NJ 950 NJ 950 NJ 950 NJ 950 2110J 1020 NJ 1020 NJ 1020 NJ
preplace netloc arithm_block_0_val_out 1 6 5 2120 800 2450J 810 NJ 810 3100J 800 3460
preplace netloc c_shift_ram_0_Q 1 9 1 3080 330n
preplace netloc c_shift_ram_1_Q 1 9 1 3090 130n
preplace netloc c_shift_ram_2_Q 1 9 1 3050 530n
preplace netloc c_shift_ram_3_Q 1 9 1 3080 700n
preplace netloc arithm_block_0_en_enable 1 6 5 2110 790 2460J 830 NJ 830 3110J 780 3470
preplace netloc scan_0_adder_enable 1 8 2 2800J 820 3090
levelinfo -pg 1 -10 110 380 760 1180 1620 1980 2290 2640 2950 3290 3490
pagesize -pg 1 -db -bbox -sgen -150 0 3660 1390
"
}
0
