--Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
--Date        : Mon May 25 03:27:12 2020
--Host        : LAPTOP-RJQ3H7G3 running 64-bit major release  (build 9200)
--Command     : generate_target pdm_to_pcm.bd
--Design      : pdm_to_pcm
--Purpose     : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity pdm_to_pcm is
  port (
    fifo_almost_empty : out STD_LOGIC;
    fifo_almost_full : out STD_LOGIC;
    fifo_rd_clk : in STD_LOGIC;
    fifo_rd_en : in STD_LOGIC;
    pcm_data : out STD_LOGIC_VECTOR ( 31 downto 0 );
    pdm_clk : out STD_LOGIC_VECTOR ( 0 to 0 );
    pdm_data : in STD_LOGIC_VECTOR ( 3 downto 0 );
    resetn : in STD_LOGIC;
    start : in STD_LOGIC;
    sys_clock : in STD_LOGIC
  );
  attribute CORE_GENERATION_INFO : string;
  attribute CORE_GENERATION_INFO of pdm_to_pcm : entity is "pdm_to_pcm,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=pdm_to_pcm,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=27,numReposBlks=27,numNonXlnxBlks=0,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=7,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}";
  attribute HW_HANDOFF : string;
  attribute HW_HANDOFF of pdm_to_pcm : entity is "pdm_to_pcm.hwdef";
end pdm_to_pcm;

architecture STRUCTURE of pdm_to_pcm is
  component pdm_to_pcm_cic_compiler_0_0 is
  port (
    aclk : in STD_LOGIC;
    s_axis_data_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
    s_axis_data_tvalid : in STD_LOGIC;
    s_axis_data_tready : out STD_LOGIC;
    s_axis_data_tlast : in STD_LOGIC;
    m_axis_data_tdata : out STD_LOGIC_VECTOR ( 23 downto 0 );
    m_axis_data_tuser : out STD_LOGIC_VECTOR ( 15 downto 0 );
    m_axis_data_tvalid : out STD_LOGIC;
    m_axis_data_tready : in STD_LOGIC;
    m_axis_data_tlast : out STD_LOGIC;
    event_tlast_unexpected : out STD_LOGIC;
    event_tlast_missing : out STD_LOGIC;
    event_halted : out STD_LOGIC
  );
  end component pdm_to_pcm_cic_compiler_0_0;
  component pdm_to_pcm_fir_compiler_0_0 is
  port (
    aclk : in STD_LOGIC;
    s_axis_data_tvalid : in STD_LOGIC;
    s_axis_data_tready : out STD_LOGIC;
    s_axis_data_tlast : in STD_LOGIC;
    s_axis_data_tdata : in STD_LOGIC_VECTOR ( 23 downto 0 );
    m_axis_data_tvalid : out STD_LOGIC;
    m_axis_data_tready : in STD_LOGIC;
    m_axis_data_tlast : out STD_LOGIC;
    m_axis_data_tdata : out STD_LOGIC_VECTOR ( 23 downto 0 )
  );
  end component pdm_to_pcm_fir_compiler_0_0;
  component pdm_to_pcm_fir_compiler_1_0 is
  port (
    aclk : in STD_LOGIC;
    s_axis_data_tvalid : in STD_LOGIC;
    s_axis_data_tready : out STD_LOGIC;
    s_axis_data_tlast : in STD_LOGIC;
    s_axis_data_tdata : in STD_LOGIC_VECTOR ( 23 downto 0 );
    m_axis_data_tvalid : out STD_LOGIC;
    m_axis_data_tready : in STD_LOGIC;
    m_axis_data_tlast : out STD_LOGIC;
    m_axis_data_tdata : out STD_LOGIC_VECTOR ( 23 downto 0 )
  );
  end component pdm_to_pcm_fir_compiler_1_0;
  component pdm_to_pcm_clk_wiz_0_0 is
  port (
    resetn : in STD_LOGIC;
    clk_in1 : in STD_LOGIC;
    clk_out1 : out STD_LOGIC;
    locked : out STD_LOGIC
  );
  end component pdm_to_pcm_clk_wiz_0_0;
  component pdm_to_pcm_fifo_generator_0_0 is
  port (
    wr_clk : in STD_LOGIC;
    rd_clk : in STD_LOGIC;
    din : in STD_LOGIC_VECTOR ( 31 downto 0 );
    wr_en : in STD_LOGIC;
    rd_en : in STD_LOGIC;
    dout : out STD_LOGIC_VECTOR ( 31 downto 0 );
    full : out STD_LOGIC;
    almost_full : out STD_LOGIC;
    wr_ack : out STD_LOGIC;
    overflow : out STD_LOGIC;
    empty : out STD_LOGIC;
    almost_empty : out STD_LOGIC;
    valid : out STD_LOGIC;
    underflow : out STD_LOGIC
  );
  end component pdm_to_pcm_fifo_generator_0_0;
  component pdm_to_pcm_util_vector_logic_0_0 is
  port (
    Op1 : in STD_LOGIC_VECTOR ( 0 to 0 );
    Res : out STD_LOGIC_VECTOR ( 0 to 0 )
  );
  end component pdm_to_pcm_util_vector_logic_0_0;
  component pdm_to_pcm_util_ds_buf_0_0 is
  port (
    BUFG_I : in STD_LOGIC_VECTOR ( 0 to 0 );
    BUFG_O : out STD_LOGIC_VECTOR ( 0 to 0 )
  );
  end component pdm_to_pcm_util_ds_buf_0_0;
  component pdm_to_pcm_clk_div_1_0 is
  port (
    clk_out : out STD_LOGIC;
    clk_in : in STD_LOGIC;
    clk_en : in STD_LOGIC;
    clr : in STD_LOGIC
  );
  end component pdm_to_pcm_clk_div_1_0;
  component pdm_to_pcm_util_vector_logic_0_2 is
  port (
    Op1 : in STD_LOGIC_VECTOR ( 0 to 0 );
    Res : out STD_LOGIC_VECTOR ( 0 to 0 )
  );
  end component pdm_to_pcm_util_vector_logic_0_2;
  component pdm_to_pcm_c_addsub_0_0 is
  port (
    A : in STD_LOGIC_VECTOR ( 15 downto 0 );
    B : in STD_LOGIC_VECTOR ( 15 downto 0 );
    CLK : in STD_LOGIC;
    CE : in STD_LOGIC;
    S : out STD_LOGIC_VECTOR ( 15 downto 0 )
  );
  end component pdm_to_pcm_c_addsub_0_0;
  component pdm_to_pcm_c_addsub_0_1 is
  port (
    A : in STD_LOGIC_VECTOR ( 15 downto 0 );
    B : in STD_LOGIC_VECTOR ( 15 downto 0 );
    CLK : in STD_LOGIC;
    CE : in STD_LOGIC;
    S : out STD_LOGIC_VECTOR ( 15 downto 0 )
  );
  end component pdm_to_pcm_c_addsub_0_1;
  component pdm_to_pcm_c_addsub_1_0 is
  port (
    A : in STD_LOGIC_VECTOR ( 15 downto 0 );
    B : in STD_LOGIC_VECTOR ( 15 downto 0 );
    CLK : in STD_LOGIC;
    CE : in STD_LOGIC;
    S : out STD_LOGIC_VECTOR ( 15 downto 0 )
  );
  end component pdm_to_pcm_c_addsub_1_0;
  component pdm_to_pcm_blk_mem_gen_0_0 is
  port (
    clka : in STD_LOGIC;
    addra : in STD_LOGIC_VECTOR ( 8 downto 0 );
    douta : out STD_LOGIC_VECTOR ( 9 downto 0 )
  );
  end component pdm_to_pcm_blk_mem_gen_0_0;
  component pdm_to_pcm_blk_mem_gen_1_0 is
  port (
    clka : in STD_LOGIC;
    addra : in STD_LOGIC_VECTOR ( 8 downto 0 );
    douta : out STD_LOGIC_VECTOR ( 9 downto 0 )
  );
  end component pdm_to_pcm_blk_mem_gen_1_0;
  component pdm_to_pcm_c_shift_ram_0_0 is
  port (
    A : in STD_LOGIC_VECTOR ( 9 downto 0 );
    D : in STD_LOGIC_VECTOR ( 15 downto 0 );
    CLK : in STD_LOGIC;
    CE : in STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 15 downto 0 )
  );
  end component pdm_to_pcm_c_shift_ram_0_0;
  component pdm_to_pcm_c_shift_ram_1_0 is
  port (
    A : in STD_LOGIC_VECTOR ( 9 downto 0 );
    D : in STD_LOGIC_VECTOR ( 15 downto 0 );
    CLK : in STD_LOGIC;
    CE : in STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 15 downto 0 )
  );
  end component pdm_to_pcm_c_shift_ram_1_0;
  component pdm_to_pcm_c_shift_ram_1_1 is
  port (
    A : in STD_LOGIC_VECTOR ( 9 downto 0 );
    D : in STD_LOGIC_VECTOR ( 15 downto 0 );
    CLK : in STD_LOGIC;
    CE : in STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 15 downto 0 )
  );
  end component pdm_to_pcm_c_shift_ram_1_1;
  component pdm_to_pcm_c_shift_ram_1_2 is
  port (
    A : in STD_LOGIC_VECTOR ( 9 downto 0 );
    D : in STD_LOGIC_VECTOR ( 15 downto 0 );
    CLK : in STD_LOGIC;
    CE : in STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 15 downto 0 )
  );
  end component pdm_to_pcm_c_shift_ram_1_2;
  component pdm_to_pcm_blk_mem_gen_1_1 is
  port (
    clka : in STD_LOGIC;
    addra : in STD_LOGIC_VECTOR ( 8 downto 0 );
    douta : out STD_LOGIC_VECTOR ( 9 downto 0 )
  );
  end component pdm_to_pcm_blk_mem_gen_1_1;
  component pdm_to_pcm_blk_mem_gen_2_0 is
  port (
    clka : in STD_LOGIC;
    addra : in STD_LOGIC_VECTOR ( 8 downto 0 );
    douta : out STD_LOGIC_VECTOR ( 9 downto 0 )
  );
  end component pdm_to_pcm_blk_mem_gen_2_0;
  component pdm_to_pcm_mult_gen_0_0 is
  port (
    CLK : in STD_LOGIC;
    A : in STD_LOGIC_VECTOR ( 15 downto 0 );
    B : in STD_LOGIC_VECTOR ( 15 downto 0 );
    P : out STD_LOGIC_VECTOR ( 31 downto 0 )
  );
  end component pdm_to_pcm_mult_gen_0_0;
  component pdm_to_pcm_clk_div_0_0 is
  port (
    clk_out : out STD_LOGIC;
    clk_in : in STD_LOGIC;
    clk_en : in STD_LOGIC;
    clr : in STD_LOGIC
  );
  end component pdm_to_pcm_clk_div_0_0;
  component pdm_to_pcm_hp_filter_0_0 is
  port (
    din : in STD_LOGIC_VECTOR ( 23 downto 0 );
    dout : out STD_LOGIC_VECTOR ( 15 downto 0 )
  );
  end component pdm_to_pcm_hp_filter_0_0;
  component pdm_to_pcm_timemux_0_2 is
  port (
    clk : in STD_LOGIC;
    start : in STD_LOGIC;
    pdm_data : in STD_LOGIC_VECTOR ( 3 downto 0 );
    pdm_data_mux : out STD_LOGIC_VECTOR ( 7 downto 0 );
    data_tvalid : out STD_LOGIC;
    data_tlast : out STD_LOGIC
  );
  end component pdm_to_pcm_timemux_0_2;
  component pdm_to_pcm_demux16_sync_0_0 is
  port (
    clk : in STD_LOGIC;
    t_valid : in STD_LOGIC;
    t_last : in STD_LOGIC;
    output_data0 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    output_data1 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    output_data2 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    output_data3 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    finish : out STD_LOGIC;
    input_data : in STD_LOGIC_VECTOR ( 15 downto 0 )
  );
  end component pdm_to_pcm_demux16_sync_0_0;
  component pdm_to_pcm_scan_0_0 is
  port (
    clk : in STD_LOGIC;
    start : in STD_LOGIC;
    t_finish : in STD_LOGIC;
    max_found : in STD_LOGIC;
    adder_enable : out STD_LOGIC;
    fifo_wr_en : out STD_LOGIC;
    scan_finish : out STD_LOGIC;
    address_0 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    address_1 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    address_2 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    address_3 : out STD_LOGIC_VECTOR ( 8 downto 0 );
    control_ram : out STD_LOGIC;
    get_max : out STD_LOGIC;
    ram_address : out STD_LOGIC_VECTOR ( 9 downto 0 )
  );
  end component pdm_to_pcm_scan_0_0;
  component pdm_to_pcm_energy_compare_0_0 is
  port (
    clk : in STD_LOGIC;
    start : in STD_LOGIC;
    t_finish : in STD_LOGIC;
    val_in : in STD_LOGIC_VECTOR ( 31 downto 0 );
    max_found : out STD_LOGIC;
    start_fifo : out STD_LOGIC;
    rst : out STD_LOGIC;
    val_out : out STD_LOGIC_VECTOR ( 31 downto 0 )
  );
  end component pdm_to_pcm_energy_compare_0_0;
  signal Net : STD_LOGIC;
  signal Net1 : STD_LOGIC;
  signal blk_mem_gen_0_douta : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal blk_mem_gen_1_douta : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal blk_mem_gen_2_douta : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal blk_mem_gen_3_douta : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal c_addsub_0_S : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal c_addsub_1_S : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal c_addsub_2_S : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal c_shift_ram_0_Q : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal c_shift_ram_1_Q : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal c_shift_ram_2_Q : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal c_shift_ram_3_Q : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal cic_compiler_0_m_axis_data_tdata : STD_LOGIC_VECTOR ( 23 downto 0 );
  signal cic_compiler_0_m_axis_data_tlast : STD_LOGIC;
  signal cic_compiler_0_m_axis_data_tvalid : STD_LOGIC;
  signal clk_div_0_clk_out : STD_LOGIC;
  signal clk_wiz_0_clk_out1 : STD_LOGIC;
  signal clk_wiz_0_locked : STD_LOGIC;
  signal demux16_sync_0_finish : STD_LOGIC;
  signal demux16_sync_0_output_data0 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal demux16_sync_0_output_data1 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal demux16_sync_0_output_data2 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal demux16_sync_0_output_data3 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal energy_compare_0_max_found : STD_LOGIC;
  signal energy_compare_0_start_fifo : STD_LOGIC;
  signal energy_compare_0_val_out : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal fifo_generator_0_almost_empty : STD_LOGIC;
  signal fifo_generator_0_almost_full : STD_LOGIC;
  signal fifo_generator_0_dout : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal fifo_generator_0_full : STD_LOGIC;
  signal fifo_rd_clk_1 : STD_LOGIC;
  signal fifo_rd_en_1 : STD_LOGIC;
  signal fir_compiler_0_m_axis_data_tdata : STD_LOGIC_VECTOR ( 23 downto 0 );
  signal fir_compiler_0_m_axis_data_tlast : STD_LOGIC;
  signal fir_compiler_0_m_axis_data_tvalid : STD_LOGIC;
  signal fir_compiler_0_s_axis_data_tready : STD_LOGIC;
  signal fir_compiler_1_m_axis_data_tdata : STD_LOGIC_VECTOR ( 23 downto 0 );
  signal fir_compiler_1_m_axis_data_tlast : STD_LOGIC;
  signal fir_compiler_1_m_axis_data_tvalid : STD_LOGIC;
  signal fir_compiler_1_s_axis_data_tready : STD_LOGIC;
  signal hp_filter_0_dout : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal mult_gen_0_P : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal pdm_data_1 : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal resetn_1 : STD_LOGIC;
  signal scan_0_address_0 : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal scan_0_address_1 : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal scan_0_address_2 : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal scan_0_address_3 : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal start_1 : STD_LOGIC;
  signal sys_clock_1 : STD_LOGIC;
  signal timemux_0_data_tlast : STD_LOGIC;
  signal timemux_0_data_tvalid : STD_LOGIC;
  signal timemux_0_pdm_data_mux : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal util_ds_buf_0_BUFG_O : STD_LOGIC_VECTOR ( 0 to 0 );
  signal util_vector_logic_0_Res : STD_LOGIC_VECTOR ( 0 to 0 );
  signal util_vector_logic_1_Res : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_cic_compiler_0_event_halted_UNCONNECTED : STD_LOGIC;
  signal NLW_cic_compiler_0_event_tlast_missing_UNCONNECTED : STD_LOGIC;
  signal NLW_cic_compiler_0_event_tlast_unexpected_UNCONNECTED : STD_LOGIC;
  signal NLW_cic_compiler_0_s_axis_data_tready_UNCONNECTED : STD_LOGIC;
  signal NLW_cic_compiler_0_m_axis_data_tuser_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_energy_compare_0_rst_UNCONNECTED : STD_LOGIC;
  signal NLW_fifo_generator_0_empty_UNCONNECTED : STD_LOGIC;
  signal NLW_fifo_generator_0_overflow_UNCONNECTED : STD_LOGIC;
  signal NLW_fifo_generator_0_underflow_UNCONNECTED : STD_LOGIC;
  signal NLW_fifo_generator_0_valid_UNCONNECTED : STD_LOGIC;
  signal NLW_fifo_generator_0_wr_ack_UNCONNECTED : STD_LOGIC;
  signal NLW_scan_0_control_ram_UNCONNECTED : STD_LOGIC;
  signal NLW_scan_0_fifo_wr_en_UNCONNECTED : STD_LOGIC;
  signal NLW_scan_0_get_max_UNCONNECTED : STD_LOGIC;
  signal NLW_scan_0_scan_finish_UNCONNECTED : STD_LOGIC;
  signal NLW_scan_0_ram_address_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
  attribute X_INTERFACE_INFO : string;
  attribute X_INTERFACE_INFO of fifo_rd_clk : signal is "xilinx.com:signal:clock:1.0 CLK.FIFO_RD_CLK CLK";
  attribute X_INTERFACE_PARAMETER : string;
  attribute X_INTERFACE_PARAMETER of fifo_rd_clk : signal is "XIL_INTERFACENAME CLK.FIFO_RD_CLK, CLK_DOMAIN pdm_to_pcm_fifo_rd_clk, FREQ_HZ 100000000, INSERT_VIP 0, PHASE 0.000";
  attribute X_INTERFACE_INFO of resetn : signal is "xilinx.com:signal:reset:1.0 RST.RESETN RST";
  attribute X_INTERFACE_PARAMETER of resetn : signal is "XIL_INTERFACENAME RST.RESETN, INSERT_VIP 0, POLARITY ACTIVE_LOW";
  attribute X_INTERFACE_INFO of sys_clock : signal is "xilinx.com:signal:clock:1.0 CLK.SYS_CLOCK CLK";
  attribute X_INTERFACE_PARAMETER of sys_clock : signal is "XIL_INTERFACENAME CLK.SYS_CLOCK, CLK_DOMAIN pdm_to_pcm_sys_clock, FREQ_HZ 100000000, INSERT_VIP 0, PHASE 0.000";
  attribute X_INTERFACE_INFO of pcm_data : signal is "xilinx.com:signal:data:1.0 DATA.PCM_DATA DATA";
  attribute X_INTERFACE_PARAMETER of pcm_data : signal is "XIL_INTERFACENAME DATA.PCM_DATA, LAYERED_METADATA undef";
  attribute X_INTERFACE_INFO of pdm_clk : signal is "xilinx.com:signal:clock:1.0 CLK.PDM_CLK CLK";
  attribute X_INTERFACE_PARAMETER of pdm_clk : signal is "XIL_INTERFACENAME CLK.PDM_CLK, CLK_DOMAIN pdm_to_pcm_util_ds_buf_0_0_BUFG_O, FREQ_HZ 100000000, INSERT_VIP 0, PHASE 0.000";
  attribute X_INTERFACE_INFO of pdm_data : signal is "xilinx.com:signal:data:1.0 DATA.PDM_DATA DATA";
  attribute X_INTERFACE_PARAMETER of pdm_data : signal is "XIL_INTERFACENAME DATA.PDM_DATA, LAYERED_METADATA undef";
begin
  fifo_almost_empty <= fifo_generator_0_almost_empty;
  fifo_almost_full <= fifo_generator_0_almost_full;
  fifo_rd_clk_1 <= fifo_rd_clk;
  fifo_rd_en_1 <= fifo_rd_en;
  pcm_data(31 downto 0) <= fifo_generator_0_dout(31 downto 0);
  pdm_clk(0) <= util_ds_buf_0_BUFG_O(0);
  pdm_data_1(3 downto 0) <= pdm_data(3 downto 0);
  resetn_1 <= resetn;
  start_1 <= start;
  sys_clock_1 <= sys_clock;
blk_mem_gen_0: component pdm_to_pcm_blk_mem_gen_0_0
     port map (
      addra(8 downto 0) => scan_0_address_0(8 downto 0),
      clka => '0',
      douta(9 downto 0) => blk_mem_gen_0_douta(9 downto 0)
    );
blk_mem_gen_1: component pdm_to_pcm_blk_mem_gen_1_0
     port map (
      addra(8 downto 0) => scan_0_address_1(8 downto 0),
      clka => '0',
      douta(9 downto 0) => blk_mem_gen_1_douta(9 downto 0)
    );
blk_mem_gen_2: component pdm_to_pcm_blk_mem_gen_1_1
     port map (
      addra(8 downto 0) => scan_0_address_2(8 downto 0),
      clka => '0',
      douta(9 downto 0) => blk_mem_gen_2_douta(9 downto 0)
    );
blk_mem_gen_3: component pdm_to_pcm_blk_mem_gen_2_0
     port map (
      addra(8 downto 0) => scan_0_address_3(8 downto 0),
      clka => '0',
      douta(9 downto 0) => blk_mem_gen_3_douta(9 downto 0)
    );
c_addsub_0: component pdm_to_pcm_c_addsub_0_0
     port map (
      A(15 downto 0) => c_shift_ram_0_Q(15 downto 0),
      B(15 downto 0) => c_shift_ram_1_Q(15 downto 0),
      CE => Net1,
      CLK => Net,
      S(15 downto 0) => c_addsub_0_S(15 downto 0)
    );
c_addsub_1: component pdm_to_pcm_c_addsub_0_1
     port map (
      A(15 downto 0) => c_shift_ram_2_Q(15 downto 0),
      B(15 downto 0) => c_shift_ram_3_Q(15 downto 0),
      CE => Net1,
      CLK => Net,
      S(15 downto 0) => c_addsub_1_S(15 downto 0)
    );
c_addsub_2: component pdm_to_pcm_c_addsub_1_0
     port map (
      A(15 downto 0) => c_addsub_0_S(15 downto 0),
      B(15 downto 0) => c_addsub_1_S(15 downto 0),
      CE => Net1,
      CLK => Net,
      S(15 downto 0) => c_addsub_2_S(15 downto 0)
    );
c_shift_ram_0: component pdm_to_pcm_c_shift_ram_0_0
     port map (
      A(9 downto 0) => blk_mem_gen_0_douta(9 downto 0),
      CE => Net1,
      CLK => Net,
      D(15 downto 0) => demux16_sync_0_output_data0(15 downto 0),
      Q(15 downto 0) => c_shift_ram_0_Q(15 downto 0)
    );
c_shift_ram_1: component pdm_to_pcm_c_shift_ram_1_0
     port map (
      A(9 downto 0) => blk_mem_gen_1_douta(9 downto 0),
      CE => Net1,
      CLK => Net,
      D(15 downto 0) => demux16_sync_0_output_data1(15 downto 0),
      Q(15 downto 0) => c_shift_ram_1_Q(15 downto 0)
    );
c_shift_ram_2: component pdm_to_pcm_c_shift_ram_1_1
     port map (
      A(9 downto 0) => blk_mem_gen_2_douta(9 downto 0),
      CE => Net1,
      CLK => Net,
      D(15 downto 0) => demux16_sync_0_output_data2(15 downto 0),
      Q(15 downto 0) => c_shift_ram_2_Q(15 downto 0)
    );
c_shift_ram_3: component pdm_to_pcm_c_shift_ram_1_2
     port map (
      A(9 downto 0) => blk_mem_gen_3_douta(9 downto 0),
      CE => Net1,
      CLK => Net,
      D(15 downto 0) => demux16_sync_0_output_data3(15 downto 0),
      Q(15 downto 0) => c_shift_ram_3_Q(15 downto 0)
    );
cic_compiler_0: component pdm_to_pcm_cic_compiler_0_0
     port map (
      aclk => clk_wiz_0_clk_out1,
      event_halted => NLW_cic_compiler_0_event_halted_UNCONNECTED,
      event_tlast_missing => NLW_cic_compiler_0_event_tlast_missing_UNCONNECTED,
      event_tlast_unexpected => NLW_cic_compiler_0_event_tlast_unexpected_UNCONNECTED,
      m_axis_data_tdata(23 downto 0) => cic_compiler_0_m_axis_data_tdata(23 downto 0),
      m_axis_data_tlast => cic_compiler_0_m_axis_data_tlast,
      m_axis_data_tready => fir_compiler_0_s_axis_data_tready,
      m_axis_data_tuser(15 downto 0) => NLW_cic_compiler_0_m_axis_data_tuser_UNCONNECTED(15 downto 0),
      m_axis_data_tvalid => cic_compiler_0_m_axis_data_tvalid,
      s_axis_data_tdata(7 downto 0) => timemux_0_pdm_data_mux(7 downto 0),
      s_axis_data_tlast => timemux_0_data_tlast,
      s_axis_data_tready => NLW_cic_compiler_0_s_axis_data_tready_UNCONNECTED,
      s_axis_data_tvalid => timemux_0_data_tvalid
    );
clk_div_0: component pdm_to_pcm_clk_div_0_0
     port map (
      clk_en => clk_wiz_0_locked,
      clk_in => clk_wiz_0_clk_out1,
      clk_out => clk_div_0_clk_out,
      clr => util_vector_logic_0_Res(0)
    );
clk_div_1: component pdm_to_pcm_clk_div_1_0
     port map (
      clk_en => clk_wiz_0_locked,
      clk_in => clk_div_0_clk_out,
      clk_out => Net,
      clr => util_vector_logic_0_Res(0)
    );
clk_wiz_0: component pdm_to_pcm_clk_wiz_0_0
     port map (
      clk_in1 => sys_clock_1,
      clk_out1 => clk_wiz_0_clk_out1,
      locked => clk_wiz_0_locked,
      resetn => resetn_1
    );
demux16_sync_0: component pdm_to_pcm_demux16_sync_0_0
     port map (
      clk => clk_wiz_0_clk_out1,
      finish => demux16_sync_0_finish,
      input_data(15 downto 0) => hp_filter_0_dout(15 downto 0),
      output_data0(15 downto 0) => demux16_sync_0_output_data0(15 downto 0),
      output_data1(15 downto 0) => demux16_sync_0_output_data1(15 downto 0),
      output_data2(15 downto 0) => demux16_sync_0_output_data2(15 downto 0),
      output_data3(15 downto 0) => demux16_sync_0_output_data3(15 downto 0),
      t_last => fir_compiler_1_m_axis_data_tlast,
      t_valid => fir_compiler_1_m_axis_data_tvalid
    );
energy_compare_0: component pdm_to_pcm_energy_compare_0_0
     port map (
      clk => Net,
      max_found => energy_compare_0_max_found,
      rst => NLW_energy_compare_0_rst_UNCONNECTED,
      start => Net1,
      start_fifo => energy_compare_0_start_fifo,
      t_finish => '0',
      val_in(31 downto 0) => mult_gen_0_P(31 downto 0),
      val_out(31 downto 0) => energy_compare_0_val_out(31 downto 0)
    );
fifo_generator_0: component pdm_to_pcm_fifo_generator_0_0
     port map (
      almost_empty => fifo_generator_0_almost_empty,
      almost_full => fifo_generator_0_almost_full,
      din(31 downto 0) => energy_compare_0_val_out(31 downto 0),
      dout(31 downto 0) => fifo_generator_0_dout(31 downto 0),
      empty => NLW_fifo_generator_0_empty_UNCONNECTED,
      full => fifo_generator_0_full,
      overflow => NLW_fifo_generator_0_overflow_UNCONNECTED,
      rd_clk => fifo_rd_clk_1,
      rd_en => fifo_rd_en_1,
      underflow => NLW_fifo_generator_0_underflow_UNCONNECTED,
      valid => NLW_fifo_generator_0_valid_UNCONNECTED,
      wr_ack => NLW_fifo_generator_0_wr_ack_UNCONNECTED,
      wr_clk => Net,
      wr_en => energy_compare_0_start_fifo
    );
fir_compiler_0: component pdm_to_pcm_fir_compiler_0_0
     port map (
      aclk => clk_wiz_0_clk_out1,
      m_axis_data_tdata(23 downto 0) => fir_compiler_0_m_axis_data_tdata(23 downto 0),
      m_axis_data_tlast => fir_compiler_0_m_axis_data_tlast,
      m_axis_data_tready => fir_compiler_1_s_axis_data_tready,
      m_axis_data_tvalid => fir_compiler_0_m_axis_data_tvalid,
      s_axis_data_tdata(23 downto 0) => cic_compiler_0_m_axis_data_tdata(23 downto 0),
      s_axis_data_tlast => cic_compiler_0_m_axis_data_tlast,
      s_axis_data_tready => fir_compiler_0_s_axis_data_tready,
      s_axis_data_tvalid => cic_compiler_0_m_axis_data_tvalid
    );
fir_compiler_1: component pdm_to_pcm_fir_compiler_1_0
     port map (
      aclk => clk_wiz_0_clk_out1,
      m_axis_data_tdata(23 downto 0) => fir_compiler_1_m_axis_data_tdata(23 downto 0),
      m_axis_data_tlast => fir_compiler_1_m_axis_data_tlast,
      m_axis_data_tready => util_vector_logic_1_Res(0),
      m_axis_data_tvalid => fir_compiler_1_m_axis_data_tvalid,
      s_axis_data_tdata(23 downto 0) => fir_compiler_0_m_axis_data_tdata(23 downto 0),
      s_axis_data_tlast => fir_compiler_0_m_axis_data_tlast,
      s_axis_data_tready => fir_compiler_1_s_axis_data_tready,
      s_axis_data_tvalid => fir_compiler_0_m_axis_data_tvalid
    );
hp_filter_0: component pdm_to_pcm_hp_filter_0_0
     port map (
      din(23 downto 0) => fir_compiler_1_m_axis_data_tdata(23 downto 0),
      dout(15 downto 0) => hp_filter_0_dout(15 downto 0)
    );
mult_gen_0: component pdm_to_pcm_mult_gen_0_0
     port map (
      A(15 downto 0) => c_addsub_2_S(15 downto 0),
      B(15 downto 0) => c_addsub_2_S(15 downto 0),
      CLK => Net,
      P(31 downto 0) => mult_gen_0_P(31 downto 0)
    );
scan_0: component pdm_to_pcm_scan_0_0
     port map (
      adder_enable => Net1,
      address_0(8 downto 0) => scan_0_address_0(8 downto 0),
      address_1(8 downto 0) => scan_0_address_1(8 downto 0),
      address_2(8 downto 0) => scan_0_address_2(8 downto 0),
      address_3(8 downto 0) => scan_0_address_3(8 downto 0),
      clk => Net,
      control_ram => NLW_scan_0_control_ram_UNCONNECTED,
      fifo_wr_en => NLW_scan_0_fifo_wr_en_UNCONNECTED,
      get_max => NLW_scan_0_get_max_UNCONNECTED,
      max_found => energy_compare_0_max_found,
      ram_address(9 downto 0) => NLW_scan_0_ram_address_UNCONNECTED(9 downto 0),
      scan_finish => NLW_scan_0_scan_finish_UNCONNECTED,
      start => start_1,
      t_finish => demux16_sync_0_finish
    );
timemux_0: component pdm_to_pcm_timemux_0_2
     port map (
      clk => clk_wiz_0_clk_out1,
      data_tlast => timemux_0_data_tlast,
      data_tvalid => timemux_0_data_tvalid,
      pdm_data(3 downto 0) => pdm_data_1(3 downto 0),
      pdm_data_mux(7 downto 0) => timemux_0_pdm_data_mux(7 downto 0),
      start => start_1
    );
util_ds_buf_0: component pdm_to_pcm_util_ds_buf_0_0
     port map (
      BUFG_I(0) => Net,
      BUFG_O(0) => util_ds_buf_0_BUFG_O(0)
    );
util_vector_logic_0: component pdm_to_pcm_util_vector_logic_0_0
     port map (
      Op1(0) => clk_wiz_0_locked,
      Res(0) => util_vector_logic_0_Res(0)
    );
util_vector_logic_1: component pdm_to_pcm_util_vector_logic_0_2
     port map (
      Op1(0) => fifo_generator_0_full,
      Res(0) => util_vector_logic_1_Res(0)
    );
end STRUCTURE;
