Library ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL; 

entity demux_16 is
       generic(n:integer := 16);
       port(
	     clk: in std_logic;
             t_valid:in std_logic;
             t_last:in std_logic;
             input_data: in std_logic_vector(n-1 downto 0);
	     output_data0: out std_logic_vector(n-1 downto 0);   
             output_data1: out std_logic_vector(n-1 downto 0);
             output_data2: out std_logic_vector(n-1 downto 0);
             output_data3: out std_logic_vector(n-1 downto 0)
	     );
end entity demux_16;

architecture arch of demux_16 is

signal a: natural range 0 to 3 :=0;



begin
p1: process(a,clk)
        begin
if (rising_edge(clk)) then
         if (t_valid = '1') then
         
	       if (a=0) then 
	       output_data0 <= input_data; 
	       a<=1; 
                            
                                      
               elsif (a=1) then
                output_data1 <= input_data;
                 a<=2; 
                           
               elsif (a=2) then
                output_data2 <= input_data;
                 a<=3; 
               else
                output_data3 <= input_data;
                 a<=0; 
               end if;
         end if;
end if;
end process p1;
      
end arch;

