// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
// Date        : Mon May 25 21:23:23 2020
// Host        : LAPTOP-RJQ3H7G3 running 64-bit major release  (build 9200)
// Command     : write_verilog -force -mode funcsim
//               D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_cic_compiler_0_0/pdm_to_pcm_cic_compiler_0_0_sim_netlist.v
// Design      : pdm_to_pcm_cic_compiler_0_0
// Purpose     : This verilog netlist is a functional simulation representation of the design and should not be modified
//               or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device      : xc7a200tfbg676-2
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps

(* CHECK_LICENSE_TYPE = "pdm_to_pcm_cic_compiler_0_0,cic_compiler_v4_0_14,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "cic_compiler_v4_0_14,Vivado 2019.1" *) 
(* NotValidForBitStream *)
module pdm_to_pcm_cic_compiler_0_0
   (aclk,
    s_axis_data_tdata,
    s_axis_data_tvalid,
    s_axis_data_tready,
    s_axis_data_tlast,
    m_axis_data_tdata,
    m_axis_data_tuser,
    m_axis_data_tvalid,
    m_axis_data_tready,
    m_axis_data_tlast,
    event_tlast_unexpected,
    event_tlast_missing,
    event_halted);
  (* x_interface_info = "xilinx.com:signal:clock:1.0 aclk_intf CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME aclk_intf, ASSOCIATED_BUSIF S_AXIS_CONFIG:M_AXIS_DATA:S_AXIS_DATA, ASSOCIATED_RESET aresetn, ASSOCIATED_CLKEN aclken, FREQ_HZ 18431963, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, INSERT_VIP 0" *) input aclk;
  (* x_interface_info = "xilinx.com:interface:axis:1.0 S_AXIS_DATA TDATA" *) (* x_interface_parameter = "XIL_INTERFACENAME S_AXIS_DATA, TDATA_NUM_BYTES 1, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 18431963, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, LAYERED_METADATA undef, INSERT_VIP 0" *) input [7:0]s_axis_data_tdata;
  (* x_interface_info = "xilinx.com:interface:axis:1.0 S_AXIS_DATA TVALID" *) input s_axis_data_tvalid;
  (* x_interface_info = "xilinx.com:interface:axis:1.0 S_AXIS_DATA TREADY" *) output s_axis_data_tready;
  (* x_interface_info = "xilinx.com:interface:axis:1.0 S_AXIS_DATA TLAST" *) input s_axis_data_tlast;
  (* x_interface_info = "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA" *) (* x_interface_parameter = "XIL_INTERFACENAME M_AXIS_DATA, TDATA_NUM_BYTES 3, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 16, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 18431963, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, LAYERED_METADATA xilinx.com:interface:datatypes:1.0 {TDATA {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type automatic dependency {} format long minimum {} maximum {}} value 94} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} array_type {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value chan} size {attribs {resolve_type generated dependency chan_size format long minimum {} maximum {}} value 4} stride {attribs {resolve_type generated dependency chan_stride format long minimum {} maximum {}} value 24} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency data_width format long minimum {} maximum {}} value 22} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} real {fixed {fractwidth {attribs {resolve_type generated dependency data_fractwidth format long minimum {} maximum {}} value 0} signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value true}}}}}}} TDATA_WIDTH 24 TUSER {datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type automatic dependency {} format long minimum {} maximum {}} value 9} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} struct {field_chan_out {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value chan_out} enabled {attribs {resolve_type generated dependency enabled format bool minimum {} maximum {}} value true} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency chan_out_width format long minimum {} maximum {}} value 2} bitoffset {attribs {resolve_type immediate dependency {} format long minimum {} maximum {}} value 0} integer {signed {attribs {resolve_type immediate dependency {} format bool minimum {} maximum {}} value false}}}} field_chan_sync {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value chan_sync} enabled {attribs {resolve_type generated dependency enabled format bool minimum {} maximum {}} value true} datatype {name {attribs {resolve_type immediate dependency {} format string minimum {} maximum {}} value {}} bitwidth {attribs {resolve_type generated dependency chan_sync_width format long minimum {} maximum {}} value 1} bitoffset {attribs {resolve_type generated dependency chan_sync_offset format long minimum {} maximum {}} value 8}}}}}} TUSER_WIDTH 16}, INSERT_VIP 0" *) output [23:0]m_axis_data_tdata;
  (* x_interface_info = "xilinx.com:interface:axis:1.0 M_AXIS_DATA TUSER" *) output [15:0]m_axis_data_tuser;
  (* x_interface_info = "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID" *) output m_axis_data_tvalid;
  (* x_interface_info = "xilinx.com:interface:axis:1.0 M_AXIS_DATA TREADY" *) input m_axis_data_tready;
  (* x_interface_info = "xilinx.com:interface:axis:1.0 M_AXIS_DATA TLAST" *) output m_axis_data_tlast;
  (* x_interface_info = "xilinx.com:signal:interrupt:1.0 event_tlast_unexpected_intf INTERRUPT" *) (* x_interface_parameter = "XIL_INTERFACENAME event_tlast_unexpected_intf, SENSITIVITY EDGE_RISING, PortWidth 1" *) output event_tlast_unexpected;
  (* x_interface_info = "xilinx.com:signal:interrupt:1.0 event_tlast_missing_intf INTERRUPT" *) (* x_interface_parameter = "XIL_INTERFACENAME event_tlast_missing_intf, SENSITIVITY EDGE_RISING, PortWidth 1" *) output event_tlast_missing;
  (* x_interface_info = "xilinx.com:signal:interrupt:1.0 event_halted_intf INTERRUPT" *) (* x_interface_parameter = "XIL_INTERFACENAME event_halted_intf, SENSITIVITY EDGE_RISING, PortWidth 1" *) output event_halted;

  wire aclk;
  wire event_halted;
  wire event_tlast_missing;
  wire event_tlast_unexpected;
  wire [23:0]m_axis_data_tdata;
  wire m_axis_data_tlast;
  wire m_axis_data_tready;
  wire [15:0]m_axis_data_tuser;
  wire m_axis_data_tvalid;
  wire [7:0]s_axis_data_tdata;
  wire s_axis_data_tlast;
  wire s_axis_data_tready;
  wire s_axis_data_tvalid;
  wire NLW_U0_s_axis_config_tready_UNCONNECTED;

  (* C_C1 = "22" *) 
  (* C_C2 = "22" *) 
  (* C_C3 = "22" *) 
  (* C_C4 = "22" *) 
  (* C_C5 = "22" *) 
  (* C_C6 = "0" *) 
  (* C_CLK_FREQ = "4" *) 
  (* C_COMPONENT_NAME = "pdm_to_pcm_cic_compiler_0_0" *) 
  (* C_DIFF_DELAY = "1" *) 
  (* C_FAMILY = "artix7" *) 
  (* C_FILTER_TYPE = "1" *) 
  (* C_HAS_ACLKEN = "0" *) 
  (* C_HAS_ARESETN = "0" *) 
  (* C_HAS_DOUT_TREADY = "1" *) 
  (* C_HAS_ROUNDING = "0" *) 
  (* C_I1 = "22" *) 
  (* C_I2 = "22" *) 
  (* C_I3 = "22" *) 
  (* C_I4 = "22" *) 
  (* C_I5 = "22" *) 
  (* C_I6 = "0" *) 
  (* C_INPUT_WIDTH = "2" *) 
  (* C_MAX_RATE = "16" *) 
  (* C_MIN_RATE = "16" *) 
  (* C_M_AXIS_DATA_TDATA_WIDTH = "24" *) 
  (* C_M_AXIS_DATA_TUSER_WIDTH = "16" *) 
  (* C_NUM_CHANNELS = "4" *) 
  (* C_NUM_STAGES = "5" *) 
  (* C_OUTPUT_WIDTH = "22" *) 
  (* C_RATE = "16" *) 
  (* C_RATE_TYPE = "0" *) 
  (* C_SAMPLE_FREQ = "1" *) 
  (* C_S_AXIS_CONFIG_TDATA_WIDTH = "1" *) 
  (* C_S_AXIS_DATA_TDATA_WIDTH = "8" *) 
  (* C_USE_DSP = "1" *) 
  (* C_USE_STREAMING_INTERFACE = "1" *) 
  (* C_XDEVICEFAMILY = "artix7" *) 
  (* downgradeipidentifiedwarnings = "yes" *) 
  pdm_to_pcm_cic_compiler_0_0_cic_compiler_v4_0_14 U0
       (.aclk(aclk),
        .aclken(1'b1),
        .aresetn(1'b1),
        .event_halted(event_halted),
        .event_tlast_missing(event_tlast_missing),
        .event_tlast_unexpected(event_tlast_unexpected),
        .m_axis_data_tdata(m_axis_data_tdata),
        .m_axis_data_tlast(m_axis_data_tlast),
        .m_axis_data_tready(m_axis_data_tready),
        .m_axis_data_tuser(m_axis_data_tuser),
        .m_axis_data_tvalid(m_axis_data_tvalid),
        .s_axis_config_tdata(1'b0),
        .s_axis_config_tready(NLW_U0_s_axis_config_tready_UNCONNECTED),
        .s_axis_config_tvalid(1'b0),
        .s_axis_data_tdata(s_axis_data_tdata),
        .s_axis_data_tlast(s_axis_data_tlast),
        .s_axis_data_tready(s_axis_data_tready),
        .s_axis_data_tvalid(s_axis_data_tvalid));
endmodule

(* C_C1 = "22" *) (* C_C2 = "22" *) (* C_C3 = "22" *) 
(* C_C4 = "22" *) (* C_C5 = "22" *) (* C_C6 = "0" *) 
(* C_CLK_FREQ = "4" *) (* C_COMPONENT_NAME = "pdm_to_pcm_cic_compiler_0_0" *) (* C_DIFF_DELAY = "1" *) 
(* C_FAMILY = "artix7" *) (* C_FILTER_TYPE = "1" *) (* C_HAS_ACLKEN = "0" *) 
(* C_HAS_ARESETN = "0" *) (* C_HAS_DOUT_TREADY = "1" *) (* C_HAS_ROUNDING = "0" *) 
(* C_I1 = "22" *) (* C_I2 = "22" *) (* C_I3 = "22" *) 
(* C_I4 = "22" *) (* C_I5 = "22" *) (* C_I6 = "0" *) 
(* C_INPUT_WIDTH = "2" *) (* C_MAX_RATE = "16" *) (* C_MIN_RATE = "16" *) 
(* C_M_AXIS_DATA_TDATA_WIDTH = "24" *) (* C_M_AXIS_DATA_TUSER_WIDTH = "16" *) (* C_NUM_CHANNELS = "4" *) 
(* C_NUM_STAGES = "5" *) (* C_OUTPUT_WIDTH = "22" *) (* C_RATE = "16" *) 
(* C_RATE_TYPE = "0" *) (* C_SAMPLE_FREQ = "1" *) (* C_S_AXIS_CONFIG_TDATA_WIDTH = "1" *) 
(* C_S_AXIS_DATA_TDATA_WIDTH = "8" *) (* C_USE_DSP = "1" *) (* C_USE_STREAMING_INTERFACE = "1" *) 
(* C_XDEVICEFAMILY = "artix7" *) (* ORIG_REF_NAME = "cic_compiler_v4_0_14" *) (* downgradeipidentifiedwarnings = "yes" *) 
module pdm_to_pcm_cic_compiler_0_0_cic_compiler_v4_0_14
   (aclk,
    aclken,
    aresetn,
    s_axis_config_tdata,
    s_axis_config_tvalid,
    s_axis_config_tready,
    s_axis_data_tdata,
    s_axis_data_tvalid,
    s_axis_data_tready,
    s_axis_data_tlast,
    m_axis_data_tdata,
    m_axis_data_tuser,
    m_axis_data_tvalid,
    m_axis_data_tready,
    m_axis_data_tlast,
    event_tlast_unexpected,
    event_tlast_missing,
    event_halted);
  input aclk;
  input aclken;
  input aresetn;
  input [0:0]s_axis_config_tdata;
  input s_axis_config_tvalid;
  output s_axis_config_tready;
  input [7:0]s_axis_data_tdata;
  input s_axis_data_tvalid;
  output s_axis_data_tready;
  input s_axis_data_tlast;
  output [23:0]m_axis_data_tdata;
  output [15:0]m_axis_data_tuser;
  output m_axis_data_tvalid;
  input m_axis_data_tready;
  output m_axis_data_tlast;
  output event_tlast_unexpected;
  output event_tlast_missing;
  output event_halted;

  wire \<const0> ;
  wire aclk;
  wire event_halted;
  wire event_tlast_missing;
  wire event_tlast_unexpected;
  wire [21:0]\^m_axis_data_tdata ;
  wire m_axis_data_tlast;
  wire m_axis_data_tready;
  wire [8:0]\^m_axis_data_tuser ;
  wire m_axis_data_tvalid;
  wire [7:0]s_axis_data_tdata;
  wire s_axis_data_tlast;
  wire s_axis_data_tready;
  wire s_axis_data_tvalid;
  wire NLW_i_synth_s_axis_config_tready_UNCONNECTED;
  wire [22:21]NLW_i_synth_m_axis_data_tdata_UNCONNECTED;
  wire [15:2]NLW_i_synth_m_axis_data_tuser_UNCONNECTED;

  assign m_axis_data_tdata[23] = \^m_axis_data_tdata [21];
  assign m_axis_data_tdata[22] = \^m_axis_data_tdata [21];
  assign m_axis_data_tdata[21:0] = \^m_axis_data_tdata [21:0];
  assign m_axis_data_tuser[15] = \<const0> ;
  assign m_axis_data_tuser[14] = \<const0> ;
  assign m_axis_data_tuser[13] = \<const0> ;
  assign m_axis_data_tuser[12] = \<const0> ;
  assign m_axis_data_tuser[11] = \<const0> ;
  assign m_axis_data_tuser[10] = \<const0> ;
  assign m_axis_data_tuser[9] = \<const0> ;
  assign m_axis_data_tuser[8] = \^m_axis_data_tuser [8];
  assign m_axis_data_tuser[7] = \<const0> ;
  assign m_axis_data_tuser[6] = \<const0> ;
  assign m_axis_data_tuser[5] = \<const0> ;
  assign m_axis_data_tuser[4] = \<const0> ;
  assign m_axis_data_tuser[3] = \<const0> ;
  assign m_axis_data_tuser[2] = \<const0> ;
  assign m_axis_data_tuser[1:0] = \^m_axis_data_tuser [1:0];
  assign s_axis_config_tready = \<const0> ;
  GND GND
       (.G(\<const0> ));
  (* C_C1 = "22" *) 
  (* C_C2 = "22" *) 
  (* C_C3 = "22" *) 
  (* C_C4 = "22" *) 
  (* C_C5 = "22" *) 
  (* C_C6 = "0" *) 
  (* C_CLK_FREQ = "4" *) 
  (* C_COMPONENT_NAME = "pdm_to_pcm_cic_compiler_0_0" *) 
  (* C_DIFF_DELAY = "1" *) 
  (* C_FAMILY = "artix7" *) 
  (* C_FILTER_TYPE = "1" *) 
  (* C_HAS_ACLKEN = "0" *) 
  (* C_HAS_ARESETN = "0" *) 
  (* C_HAS_DOUT_TREADY = "1" *) 
  (* C_HAS_ROUNDING = "0" *) 
  (* C_I1 = "22" *) 
  (* C_I2 = "22" *) 
  (* C_I3 = "22" *) 
  (* C_I4 = "22" *) 
  (* C_I5 = "22" *) 
  (* C_I6 = "0" *) 
  (* C_INPUT_WIDTH = "2" *) 
  (* C_MAX_RATE = "16" *) 
  (* C_MIN_RATE = "16" *) 
  (* C_M_AXIS_DATA_TDATA_WIDTH = "24" *) 
  (* C_M_AXIS_DATA_TUSER_WIDTH = "16" *) 
  (* C_NUM_CHANNELS = "4" *) 
  (* C_NUM_STAGES = "5" *) 
  (* C_OUTPUT_WIDTH = "22" *) 
  (* C_RATE = "16" *) 
  (* C_RATE_TYPE = "0" *) 
  (* C_SAMPLE_FREQ = "1" *) 
  (* C_S_AXIS_CONFIG_TDATA_WIDTH = "1" *) 
  (* C_S_AXIS_DATA_TDATA_WIDTH = "8" *) 
  (* C_USE_DSP = "1" *) 
  (* C_USE_STREAMING_INTERFACE = "1" *) 
  (* C_XDEVICEFAMILY = "artix7" *) 
  (* downgradeipidentifiedwarnings = "yes" *) 
  pdm_to_pcm_cic_compiler_0_0_cic_compiler_v4_0_14_viv i_synth
       (.aclk(aclk),
        .aclken(1'b0),
        .aresetn(1'b0),
        .event_halted(event_halted),
        .event_tlast_missing(event_tlast_missing),
        .event_tlast_unexpected(event_tlast_unexpected),
        .m_axis_data_tdata({\^m_axis_data_tdata [21],NLW_i_synth_m_axis_data_tdata_UNCONNECTED[22:21],\^m_axis_data_tdata [20:0]}),
        .m_axis_data_tlast(m_axis_data_tlast),
        .m_axis_data_tready(m_axis_data_tready),
        .m_axis_data_tuser({NLW_i_synth_m_axis_data_tuser_UNCONNECTED[15:9],\^m_axis_data_tuser }),
        .m_axis_data_tvalid(m_axis_data_tvalid),
        .s_axis_config_tdata(1'b0),
        .s_axis_config_tready(NLW_i_synth_s_axis_config_tready_UNCONNECTED),
        .s_axis_config_tvalid(1'b0),
        .s_axis_data_tdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,s_axis_data_tdata[1:0]}),
        .s_axis_data_tlast(s_axis_data_tlast),
        .s_axis_data_tready(s_axis_data_tready),
        .s_axis_data_tvalid(s_axis_data_tvalid));
endmodule
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`pragma protect key_keyowner="Mentor Graphics Corporation", key_keyname="MGC-PREC-RSA", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
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`pragma protect key_keyowner="Synplicity", key_keyname="SYNP15_1", key_method="rsa"
`pragma protect encoding = (enctype="BASE64", line_length=76, bytes=256)
`pragma protect key_block
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N84ya6ZShaeSOkRvXjEvQJOa6Vvj1tI4ySXObQ==

`pragma protect data_method = "AES128-CBC"
`pragma protect encoding = (enctype = "BASE64", line_length = 76, bytes = 465744)
`pragma protect data_block
[encoded data, 620992 characters]
`pragma protect end_protected
`ifndef GLBL
`define GLBL
`timescale  1 ps / 1 ps

module glbl ();

    parameter ROC_WIDTH = 100000;
    parameter TOC_WIDTH = 0;

//--------   STARTUP Globals --------------
    wire GSR;
    wire GTS;
    wire GWE;
    wire PRLD;
    tri1 p_up_tmp;
    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;

    wire PROGB_GLBL;
    wire CCLKO_GLBL;
    wire FCSBO_GLBL;
    wire [3:0] DO_GLBL;
    wire [3:0] DI_GLBL;
   
    reg GSR_int;
    reg GTS_int;
    reg PRLD_int;

//--------   JTAG Globals --------------
    wire JTAG_TDO_GLBL;
    wire JTAG_TCK_GLBL;
    wire JTAG_TDI_GLBL;
    wire JTAG_TMS_GLBL;
    wire JTAG_TRST_GLBL;

    reg JTAG_CAPTURE_GLBL;
    reg JTAG_RESET_GLBL;
    reg JTAG_SHIFT_GLBL;
    reg JTAG_UPDATE_GLBL;
    reg JTAG_RUNTEST_GLBL;

    reg JTAG_SEL1_GLBL = 0;
    reg JTAG_SEL2_GLBL = 0 ;
    reg JTAG_SEL3_GLBL = 0;
    reg JTAG_SEL4_GLBL = 0;

    reg JTAG_USER_TDO1_GLBL = 1'bz;
    reg JTAG_USER_TDO2_GLBL = 1'bz;
    reg JTAG_USER_TDO3_GLBL = 1'bz;
    reg JTAG_USER_TDO4_GLBL = 1'bz;

    assign (strong1, weak0) GSR = GSR_int;
    assign (strong1, weak0) GTS = GTS_int;
    assign (weak1, weak0) PRLD = PRLD_int;

    initial begin
	GSR_int = 1'b1;
	PRLD_int = 1'b1;
	#(ROC_WIDTH)
	GSR_int = 1'b0;
	PRLD_int = 1'b0;
    end

    initial begin
	GTS_int = 1'b1;
	#(TOC_WIDTH)
	GTS_int = 1'b0;
    end

endmodule
`endif
