library ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL; 

entity timemux is 
	port( 
		clk:in std_logic;
      		cicdata1: in std_logic;
	  	cicdata2:in std_logic;
		pdm_data_mux:out std_logic);
end entity timemux;
architecture arch of timemux is
 	
signal flag:natural :=1;
		begin
--signal count:std_logic;
	
   	process(clk)
		begin 
   			 if(rising_edge(clk)) then
			      
	 			flag<=flag+1;
	 			if(flag=2) then 
	   			flag<=1;
				end if;
			end if;
	 		      
   	end process;
    
	pdm_data_mux<=cicdata1 when flag=1 else
			cicdata2 when flag=2 else
			'0';
	--if(flag==1)
	 --pdm_data_mux<=cicdata1;
	--else {
		--if(flag==2)
		--pdm_data_mux<=cicdata2;
		--end if;
	 --}
	--end if;
	 
end arch;

  
	 