// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.1 (win64) Build 2552052 Fri May 24 14:49:42 MDT 2019
// Date        : Mon May 25 01:04:53 2020
// Host        : LAPTOP-RJQ3H7G3 running 64-bit major release  (build 9200)
// Command     : write_verilog -force -mode synth_stub
//               D:/sound_location_project/energy/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ip/pdm_to_pcm_timemux_0_2/pdm_to_pcm_timemux_0_2_stub.v
// Design      : pdm_to_pcm_timemux_0_2
// Purpose     : Stub declaration of top-level module interface
// Device      : xc7a200tfbg676-2
// --------------------------------------------------------------------------------

// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "timemux,Vivado 2019.1" *)
module pdm_to_pcm_timemux_0_2(clk, start, pdm_data, pdm_data_mux, data_tvalid, 
  data_tlast)
/* synthesis syn_black_box black_box_pad_pin="clk,start,pdm_data[3:0],pdm_data_mux[7:0],data_tvalid,data_tlast" */;
  input clk;
  input start;
  input [3:0]pdm_data;
  output [7:0]pdm_data_mux;
  output data_tvalid;
  output data_tlast;
endmodule
