#-----------------------------------------------------------
# Vivado v2019.1 (64-bit)
# SW Build 2552052 on Fri May 24 14:49:42 MDT 2019
# IP Build 2548770 on Fri May 24 18:01:18 MDT 2019
# Start of session at: Wed May 20 15:11:01 2020
# Process ID: 15116
# Current directory: D:/sound_location_project/vivado/dat096-master-latest_version/latest_version
# Command line: vivado.exe -gui_launcher_event rodinguilauncherevent19076 D:\sound_location_project\vivado\dat096-master-latest_version\latest_version\dat096_ref_design.xpr
# Log file: D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/vivado.log
# Journal file: D:/sound_location_project/vivado/dat096-master-latest_version/latest_version\vivado.jou
#-----------------------------------------------------------
start_gui
open_project D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.xpr
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/clean_rst.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/decoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/encoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_constants.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_regs.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_test.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/timescale.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_an.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_mdio.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_rx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_sync.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_tx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/ddr/mig_interface_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/i2c/i2c_slave_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/micron/sdram/mobile_sdr.v:]
Scanning sources...
Finished scanning sources
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/clean_rst.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/decoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/encoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_constants.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_regs.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_test.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/timescale.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_an.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_mdio.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_rx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_sync.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_tx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/ddr/mig_interface_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/i2c/i2c_slave_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/micron/sdram/mobile_sdr.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/clean_rst.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/decoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/encoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_constants.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_regs.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_test.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/timescale.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_an.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_mdio.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_rx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_sync.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_tx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/ddr/mig_interface_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/i2c/i2c_slave_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/micron/sdram/mobile_sdr.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/clean_rst.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/decoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/encoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_constants.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_regs.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_test.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/timescale.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_an.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_mdio.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_rx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_sync.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_tx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/ddr/mig_interface_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/i2c/i2c_slave_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/micron/sdram/mobile_sdr.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/clean_rst.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/decoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/encoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_constants.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_regs.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_test.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/timescale.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_an.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_mdio.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_rx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_sync.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_tx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/ddr/mig_interface_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/i2c/i2c_slave_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/micron/sdram/mobile_sdr.v:]
WARNING: [filemgmt 56-3] IP Repository Path: Could not find the directory 'D:/sound_location_project/vivado/dat096-master-latest_version/sound_location_project'.
INFO: [IP_Flow 19-234] Refreshing IP repositories
WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'd:/sound_location_project/vivado/dat096-master-latest_version/sound_location_project'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'C:/xilinx/Vivado/2019.1/data/ip'.
open_project: Time (s): cpu = 00:00:23 ; elapsed = 00:00:13 . Memory (MB): peak = 881.035 ; gain = 238.477
open_bd_design {D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/pdm_to_pcm.bd}
Adding component instance block -- xilinx.com:ip:cic_compiler:4.0 - cic_compiler_0
Adding component instance block -- xilinx.com:ip:fir_compiler:7.2 - fir_compiler_0
Adding component instance block -- xilinx.com:ip:fir_compiler:7.2 - fir_compiler_1
Adding component instance block -- xilinx.com:ip:clk_wiz:6.0 - clk_wiz_0
Adding component instance block -- xilinx.com:ip:fifo_generator:13.2 - fifo_generator_0
INFO: [xilinx.com:ip:fifo_generator:13.2-5968] /fifo_generator_0Executing the post_config_ip from bd
Adding component instance block -- xilinx.com:ip:util_vector_logic:2.0 - util_vector_logic_0
Adding component instance block -- xilinx.com:module_ref:clk_div:1.0 - clk_div_0
Adding component instance block -- xilinx.com:ip:util_ds_buf:2.1 - util_ds_buf_0
Adding component instance block -- xilinx.com:module_ref:clk_div:1.0 - clk_div_1
Adding component instance block -- xilinx.com:module_ref:hp_filter:1.0 - hp_filter_0
Adding component instance block -- xilinx.com:ip:util_vector_logic:2.0 - util_vector_logic_1
Adding component instance block -- xilinx.com:module_ref:timemux:1.0 - timemux_0
Adding component instance block -- xilinx.com:ip:c_addsub:12.0 - c_addsub_0
Adding component instance block -- xilinx.com:ip:c_addsub:12.0 - c_addsub_1
Adding component instance block -- xilinx.com:ip:c_addsub:12.0 - c_addsub_2
Adding component instance block -- xilinx.com:module_ref:demux16_sync:1.0 - demux16_sync_0
Adding component instance block -- xilinx.com:ip:blk_mem_gen:8.4 - blk_mem_gen_0
Adding component instance block -- xilinx.com:ip:blk_mem_gen:8.4 - blk_mem_gen_1
Adding component instance block -- xilinx.com:ip:c_shift_ram:12.0 - c_shift_ram_0
Adding component instance block -- xilinx.com:ip:c_shift_ram:12.0 - c_shift_ram_1
Adding component instance block -- xilinx.com:ip:c_shift_ram:12.0 - c_shift_ram_2
Adding component instance block -- xilinx.com:ip:c_shift_ram:12.0 - c_shift_ram_3
Adding component instance block -- xilinx.com:ip:blk_mem_gen:8.4 - blk_mem_gen_2
Adding component instance block -- xilinx.com:ip:blk_mem_gen:8.4 - blk_mem_gen_3
Adding component instance block -- xilinx.com:module_ref:scan:1.0 - scan_0
WARNING: [BD 41-1731] Type mismatch between connected pins: /clk_wiz_0/clk_out1(clk) and /clk_div_0/clk_in(undef)
WARNING: [BD 41-1731] Type mismatch between connected pins: /clk_div_1/clk_out(undef) and /c_addsub_1/CLK(clk)
WARNING: [BD 41-1731] Type mismatch between connected pins: /clk_div_1/clk_out(undef) and /c_addsub_0/CLK(clk)
WARNING: [BD 41-1731] Type mismatch between connected pins: /clk_div_1/clk_out(undef) and /c_shift_ram_2/CLK(clk)
WARNING: [BD 41-1731] Type mismatch between connected pins: /clk_div_1/clk_out(undef) and /c_shift_ram_3/CLK(clk)
WARNING: [BD 41-1731] Type mismatch between connected pins: /clk_div_1/clk_out(undef) and /c_shift_ram_1/CLK(clk)
WARNING: [BD 41-1731] Type mismatch between connected pins: /clk_div_1/clk_out(undef) and /fifo_generator_0/wr_clk(clk)
WARNING: [BD 41-1731] Type mismatch between connected pins: /clk_div_1/clk_out(undef) and /util_ds_buf_0/BUFG_I(clk)
WARNING: [BD 41-1731] Type mismatch between connected pins: /clk_div_1/clk_out(undef) and /c_shift_ram_0/CLK(clk)
WARNING: [BD 41-1731] Type mismatch between connected pins: /clk_div_1/clk_out(undef) and /c_addsub_2/CLK(clk)
WARNING: [BD 41-1731] Type mismatch between connected pins: /clk_div_1/clk_out(undef) and /scan_0/clk(clk)
WARNING: [BD 41-1731] Type mismatch between connected pins: /scan_0/scan_finish(undef) and /c_shift_ram_0/CE(ce)
WARNING: [BD 41-1731] Type mismatch between connected pins: /scan_0/scan_finish(undef) and /c_shift_ram_1/CE(ce)
WARNING: [BD 41-1731] Type mismatch between connected pins: /scan_0/scan_finish(undef) and /c_shift_ram_2/CE(ce)
WARNING: [BD 41-1731] Type mismatch between connected pins: /scan_0/scan_finish(undef) and /c_shift_ram_3/CE(ce)
WARNING: [BD 41-1731] Type mismatch between connected pins: /scan_0/adder_enable(undef) and /c_addsub_1/CE(ce)
WARNING: [BD 41-1731] Type mismatch between connected pins: /scan_0/adder_enable(undef) and /c_addsub_0/CE(ce)
WARNING: [BD 41-1731] Type mismatch between connected pins: /scan_0/adder_enable(undef) and /c_addsub_2/CE(ce)
Successfully read diagram <pdm_to_pcm> from BD file <D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/pdm_to_pcm.bd>
open_bd_design: Time (s): cpu = 00:00:15 ; elapsed = 00:00:25 . Memory (MB): peak = 1561.656 ; gain = 45.820
update_compile_order -fileset sources_1
startgroup
set_property -dict [list CONFIG.Coefficient_File {D:/sound_location_project/dat096-master-coeff files/coeff files/halfband_ultrasonic.coe} CONFIG.Coefficient_Sets {1} CONFIG.Coefficient_Sign {Signed} CONFIG.Quantization {Integer_Coefficients} CONFIG.Coefficient_Width {16} CONFIG.Coefficient_Fractional_Bits {0} CONFIG.Coefficient_Structure {Half_Band} CONFIG.Data_Width {22} CONFIG.Output_Rounding_Mode {Truncate_LSBs} CONFIG.Output_Width {22}] [get_bd_cells fir_compiler_0]
INFO: [IP_Flow 19-3484] Absolute path of file 'd:/sound_location_project/dat096-master-coeff files/coeff files/halfband_ultrasonic.coe' provided. It will be converted relative to IP Instance files '../../../../../../../../../dat096-master-coeff files/coeff files/halfband_ultrasonic.coe'
endgroup
startgroup
set_property -dict [list CONFIG.Coefficient_File {D:/sound_location_project/dat096-master-coeff files/coeff files/lowpass_ultrasonic.coe} CONFIG.Coefficient_Sets {1} CONFIG.Coefficient_Sign {Signed} CONFIG.Quantization {Integer_Coefficients} CONFIG.Coefficient_Width {20} CONFIG.Coefficient_Fractional_Bits {0} CONFIG.Coefficient_Structure {Symmetric} CONFIG.Data_Width {22} CONFIG.Output_Width {22}] [get_bd_cells fir_compiler_1]
INFO: [IP_Flow 19-3484] Absolute path of file 'd:/sound_location_project/dat096-master-coeff files/coeff files/lowpass_ultrasonic.coe' provided. It will be converted relative to IP Instance files '../../../../../../../../../dat096-master-coeff files/coeff files/lowpass_ultrasonic.coe'
endgroup
startgroup
set_property -dict [list CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {12.8} CONFIG.MMCM_DIVCLK_DIVIDE {1} CONFIG.MMCM_CLKFBOUT_MULT_F {10.000} CONFIG.MMCM_CLKOUT0_DIVIDE_F {78.125} CONFIG.CLKOUT1_JITTER {199.846} CONFIG.CLKOUT1_PHASE_ERROR {98.575}] [get_bd_cells clk_wiz_0]
endgroup
startgroup
set_property -dict [list CONFIG.Input_Sample_Frequency {3.2} CONFIG.Clock_Frequency {12.8} CONFIG.Clock_Frequency {12.8}] [get_bd_cells cic_compiler_0]
endgroup
startgroup
set_property -dict [list CONFIG.Sample_Frequency {0.2} CONFIG.Clock_Frequency {12.8} CONFIG.Clock_Frequency {12.8} CONFIG.Coefficient_Width {16} CONFIG.Coefficient_Structure {Half_Band} CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate}] [get_bd_cells fir_compiler_0]
endgroup
startgroup
set_property -dict [list CONFIG.Sample_Frequency {0.1} CONFIG.Clock_Frequency {12.8} CONFIG.Clock_Frequency {12.8} CONFIG.Coefficient_Width {20} CONFIG.Coefficient_Structure {Symmetric} CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} CONFIG.ColumnConfig {3}] [get_bd_cells fir_compiler_1]
endgroup
WARNING: [IP_Flow 19-4067] Ignoring invalid widget type specified checkbox.Providing a default widget
WARNING: [IP_Flow 19-4067] Ignoring invalid widget type specified checkbox.Providing a default widget
INFO: [IP_Flow 19-3484] Absolute path of file 'd:/project_vhdlcode/previousdelayvalue.coe' provided. It will be converted relative to IP Instance files '../../../../../../../../project_vhdlcode/previousdelayvalue.coe'
startgroup
set_property -dict [list CONFIG.Coe_File {d:/project_vhdlcode/previousdelayvalue.coe}] [get_bd_cells blk_mem_gen_3]
INFO: [IP_Flow 19-3484] Absolute path of file 'd:/project_vhdlcode/previousdelayvalue.coe' provided. It will be converted relative to IP Instance files '../../../../../../../../../../project_vhdlcode/previousdelayvalue.coe'
endgroup
reset_run pdm_to_pcm_cic_compiler_0_0_synth_1
WARNING: [Vivado 12-1017] Problems encountered:
1. Failed to delete one or more files in run directory D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.runs/pdm_to_pcm_cic_compiler_0_0_synth_1

reset_run pdm_to_pcm_clk_wiz_0_0_synth_1
WARNING: [Vivado 12-1017] Problems encountered:
1. Failed to delete one or more files in run directory D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.runs/pdm_to_pcm_clk_wiz_0_0_synth_1

reset_run pdm_to_pcm_fir_compiler_1_0_synth_1
WARNING: [Vivado 12-1017] Problems encountered:
1. Failed to delete one or more files in run directory D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.runs/pdm_to_pcm_fir_compiler_1_0_synth_1

reset_run pdm_to_pcm_fir_compiler_0_0_synth_1
WARNING: [Vivado 12-1017] Problems encountered:
1. Failed to delete one or more files in run directory D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.runs/pdm_to_pcm_fir_compiler_0_0_synth_1

reset_run pdm_to_pcm_blk_mem_gen_2_0_synth_1
WARNING: [Vivado 12-1017] Problems encountered:
1. Failed to delete one or more files in run directory D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.runs/pdm_to_pcm_blk_mem_gen_2_0_synth_1

reset_run pdm_to_pcm_blk_mem_gen_1_1_synth_1
WARNING: [Vivado 12-1017] Problems encountered:
1. Failed to delete one or more files in run directory D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.runs/pdm_to_pcm_blk_mem_gen_1_1_synth_1

reset_run pdm_to_pcm_blk_mem_gen_1_0_synth_1
WARNING: [Vivado 12-1017] Problems encountered:
1. Failed to delete one or more files in run directory D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.runs/pdm_to_pcm_blk_mem_gen_1_0_synth_1

reset_run pdm_to_pcm_blk_mem_gen_0_0_synth_1
WARNING: [Vivado 12-1017] Problems encountered:
1. Failed to delete one or more files in run directory D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.runs/pdm_to_pcm_blk_mem_gen_0_0_synth_1

save_bd_design
Wrote  : <D:\sound_location_project\vivado\dat096-master-latest_version\latest_version\dat096_ref_design.srcs\sources_1\bd\pdm_to_pcm\pdm_to_pcm.bd> 
reset_run synth_2
WARNING: [Vivado 12-1017] Problems encountered:
1. Failed to delete one or more files in run directory D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.runs/synth_2

launch_runs synth_2 -jobs 4
WARNING: [BD 41-2180] Resetting the memory initialization file of </blk_mem_gen_3> to default.
WARNING: [BD 41-2180] Resetting the memory initialization file of </blk_mem_gen_2> to default.
WARNING: [BD 41-2180] Resetting the memory initialization file of </blk_mem_gen_1> to default.
WARNING: [BD 41-2180] Resetting the memory initialization file of </blk_mem_gen_0> to default.
INFO: [xilinx.com:ip:cic_compiler:4.0-913] /cic_compiler_0 Input_Data_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_2 A_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_2 B_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
WARNING: [xilinx.com:ip:c_addsub:12.0-313] /c_addsub_0 A-DATA: Field type resolution: data = integer. /c_shift_ram_0 Q-DATA: data = null. /c_shift_ram_0 Q-DATA data field will be interpreted as integer
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_0 A_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
WARNING: [xilinx.com:ip:c_addsub:12.0-313] /c_addsub_0 B-DATA: Field type resolution: data = integer. /c_shift_ram_1 Q-DATA: data = null. /c_shift_ram_1 Q-DATA data field will be interpreted as integer
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_0 B_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:c_addsub:12.0-308] /c_addsub_0 A-DATA: Validating field: data(16:0): int16 against /c_shift_ram_0 Q-DATA: data(16:0): bit16.
WARNING: [xilinx.com:ip:c_addsub:12.0-313] /c_addsub_0 A-DATA: Field type resolution: data = integer. /c_shift_ram_0 Q-DATA: data = null. /c_shift_ram_0 Q-DATA data field will be interpreted as integer
INFO: [xilinx.com:ip:c_addsub:12.0-308] /c_addsub_0 B-DATA: Validating field: data(16:0): int16 against /c_shift_ram_1 Q-DATA: data(16:0): bit16.
WARNING: [xilinx.com:ip:c_addsub:12.0-313] /c_addsub_0 B-DATA: Field type resolution: data = integer. /c_shift_ram_1 Q-DATA: data = null. /c_shift_ram_1 Q-DATA data field will be interpreted as integer
WARNING: [xilinx.com:ip:c_addsub:12.0-313] /c_addsub_1 A-DATA: Field type resolution: data = integer. /c_shift_ram_2 Q-DATA: data = null. /c_shift_ram_2 Q-DATA data field will be interpreted as integer
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_1 A_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
WARNING: [xilinx.com:ip:c_addsub:12.0-313] /c_addsub_1 B-DATA: Field type resolution: data = integer. /c_shift_ram_3 Q-DATA: data = null. /c_shift_ram_3 Q-DATA data field will be interpreted as integer
INFO: [xilinx.com:ip:c_addsub:12.0-913] /c_addsub_1 B_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:c_addsub:12.0-308] /c_addsub_1 A-DATA: Validating field: data(16:0): int16 against /c_shift_ram_2 Q-DATA: data(16:0): bit16.
WARNING: [xilinx.com:ip:c_addsub:12.0-313] /c_addsub_1 A-DATA: Field type resolution: data = integer. /c_shift_ram_2 Q-DATA: data = null. /c_shift_ram_2 Q-DATA data field will be interpreted as integer
INFO: [xilinx.com:ip:c_addsub:12.0-308] /c_addsub_1 B-DATA: Validating field: data(16:0): int16 against /c_shift_ram_3 Q-DATA: data(16:0): bit16.
WARNING: [xilinx.com:ip:c_addsub:12.0-313] /c_addsub_1 B-DATA: Field type resolution: data = integer. /c_shift_ram_3 Q-DATA: data = null. /c_shift_ram_3 Q-DATA data field will be interpreted as integer
INFO: [xilinx.com:ip:fir_compiler:7.2-913] /fir_compiler_1 Data_Sign has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:fir_compiler:7.2-913] /fir_compiler_1 Data_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:fir_compiler:7.2-913] /fir_compiler_1 Data_Fractional_Bits has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:fir_compiler:7.2-913] /fir_compiler_0 Data_Sign has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:fir_compiler:7.2-913] /fir_compiler_0 Data_Width has been set to manual on the GUI. It will not be updated during validation with a propagated value.
INFO: [xilinx.com:ip:fir_compiler:7.2-913] /fir_compiler_0 Data_Fractional_Bits has been set to manual on the GUI. It will not be updated during validation with a propagated value.
WARNING: [BD 41-927] Following properties on pin /timemux_0/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
	CLK_DOMAIN=/clk_wiz_0_clk_out1 
WARNING: [BD 41-927] Following properties on pin /demux16_sync_0/clk have been updated from connected ip. They may not be synchronized with cell properties. You can set property on pin directly to confirm the value and resolve the warning.
	CLK_DOMAIN=/clk_wiz_0_clk_out1 
Wrote  : <D:\sound_location_project\vivado\dat096-master-latest_version\latest_version\dat096_ref_design.srcs\sources_1\bd\pdm_to_pcm\pdm_to_pcm.bd> 
VHDL Output written to : D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/synth/pdm_to_pcm.vhd
VHDL Output written to : D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/sim/pdm_to_pcm.vhd
VHDL Output written to : D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.vhd
INFO: [BD 41-1029] Generation completed for the IP Integrator block cic_compiler_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block fir_compiler_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block fir_compiler_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block clk_wiz_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block fifo_generator_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block util_vector_logic_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block clk_div_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block util_ds_buf_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block clk_div_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block hp_filter_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block util_vector_logic_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block timemux_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block demux16_sync_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_addsub_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_addsub_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_addsub_2 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block blk_mem_gen_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block blk_mem_gen_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_shift_ram_0 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_shift_ram_1 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_shift_ram_2 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block c_shift_ram_3 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block blk_mem_gen_2 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block blk_mem_gen_3 .
INFO: [BD 41-1029] Generation completed for the IP Integrator block scan_0 .
Exporting to file D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hw_handoff/pdm_to_pcm.hwh
Generated Block Design Tcl file D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hw_handoff/pdm_to_pcm_bd.tcl
Generated Hardware Definition File D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/synth/pdm_to_pcm.hwdef
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP pdm_to_pcm_blk_mem_gen_0_0, cache-ID = c0dd38e449b973fe; cache size = 66.438 MB.
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP pdm_to_pcm_blk_mem_gen_1_0, cache-ID = 16412065237b5812; cache size = 66.438 MB.
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP pdm_to_pcm_blk_mem_gen_1_1, cache-ID = 16412065237b5812; cache size = 66.438 MB.
INFO: [IP_Flow 19-4993] Using cached IP synthesis design for IP pdm_to_pcm_blk_mem_gen_2_0, cache-ID = 16412065237b5812; cache size = 66.438 MB.
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/clean_rst.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/decoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/encoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_constants.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_regs.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_test.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/timescale.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_an.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_mdio.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_rx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_sync.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_tx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/ddr/mig_interface_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/i2c/i2c_slave_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/micron/sdram/mobile_sdr.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/clean_rst.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/decoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/encoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_constants.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_regs.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_test.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/timescale.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_an.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_mdio.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_rx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_sync.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_tx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/ddr/mig_interface_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/i2c/i2c_slave_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/micron/sdram/mobile_sdr.v:]
[Wed May 20 15:16:41 2020] Launched pdm_to_pcm_cic_compiler_0_0_synth_1, pdm_to_pcm_clk_wiz_0_0_synth_1, pdm_to_pcm_fir_compiler_1_0_synth_1, pdm_to_pcm_fir_compiler_0_0_synth_1...
Run output will be captured here:
pdm_to_pcm_cic_compiler_0_0_synth_1: D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.runs/pdm_to_pcm_cic_compiler_0_0_synth_1/runme.log
pdm_to_pcm_clk_wiz_0_0_synth_1: D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.runs/pdm_to_pcm_clk_wiz_0_0_synth_1/runme.log
pdm_to_pcm_fir_compiler_1_0_synth_1: D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.runs/pdm_to_pcm_fir_compiler_1_0_synth_1/runme.log
pdm_to_pcm_fir_compiler_0_0_synth_1: D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.runs/pdm_to_pcm_fir_compiler_0_0_synth_1/runme.log
[Wed May 20 15:16:42 2020] Launched synth_2...
Run output will be captured here: D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.runs/synth_2/runme.log
launch_runs: Time (s): cpu = 00:00:15 ; elapsed = 00:00:20 . Memory (MB): peak = 1561.656 ; gain = 0.000
launch_runs impl_2 -jobs 4
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/clean_rst.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/decoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/encoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_constants.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_regs.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_test.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/timescale.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_an.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_mdio.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_rx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_sync.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_tx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/ddr/mig_interface_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/i2c/i2c_slave_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/micron/sdram/mobile_sdr.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/clean_rst.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/decoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/encoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_constants.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_regs.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_test.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/timescale.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_an.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_mdio.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_rx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_sync.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_tx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/ddr/mig_interface_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/i2c/i2c_slave_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/micron/sdram/mobile_sdr.v:]
[Wed May 20 15:24:18 2020] Launched impl_2...
Run output will be captured here: D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.runs/impl_2/runme.log
launch_runs impl_2 -to_step write_bitstream -jobs 4
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/hdl/pdm_to_pcm_wrapper.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/clean_rst.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/decoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/encoder_8b10b.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_constants.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_regs.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_test.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/timescale.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_an.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_mdio.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_rx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_sync.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/opencores/ge_1000baseX/ge_1000baseX_tx.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/ddr/mig_interface_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/gaisler/i2c/i2c_slave_model.v:]
WARNING: [filemgmt 56-99] Vivado Synthesis ignores library specification for Verilog or SystemVerilog files. [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/imports/grlib-gpl-2019.4-b4246/lib/micron/sdram/mobile_sdr.v:]
[Wed May 20 15:35:50 2020] Launched impl_2...
Run output will be captured here: D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.runs/impl_2/runme.log
open_run impl_2
INFO: [Device 21-403] Loading part xc7a200tfbg676-2
INFO: [Netlist 29-17] Analyzing 3354 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2019.1
INFO: [Project 1-570] Preparing netlist for logic optimization
WARNING: [Constraints 18-550] Could not create 'IBUF_LOW_PWR' constraint because net 'masterrdwrgen.filter/pdm_to_pcm_i/clk_wiz_0/clk_in1' is not directly connected to top level port. Synthesis is ignored for IBUF_LOW_PWR but preserved for implementation.
INFO: [Timing 38-478] Restoring timing data from binary archive.
INFO: [Timing 38-479] Binary timing data restore complete.
INFO: [Project 1-856] Restoring constraints from binary archive.
INFO: [Project 1-853] Binary constraint restore complete.
Reading XDEF placement.
Reading placer database...
Reading XDEF routing.
Read XDEF File: Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 2608.621 ; gain = 48.699
Restored from archive | CPU: 5.000000 secs | Memory: 0.000000 MB |
Finished XDEF File Restore: Time (s): cpu = 00:00:05 ; elapsed = 00:00:04 . Memory (MB): peak = 2608.621 ; gain = 48.699
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.017 . Memory (MB): peak = 2608.621 ; gain = 0.000
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 491 instances were transformed.
  IOBUF => IOBUF (IBUF, OBUFT): 8 instances
  IOBUFDS_DIFF_OUT_INTERMDISABLE => IOBUFDS_DIFF_OUT_INTERMDISABLE (IBUFDS_INTERMDISABLE_INT, IBUFDS_INTERMDISABLE_INT, INV, OBUFTDS, OBUFTDS): 8 instances
  IOBUF_INTERMDISABLE => IOBUF_INTERMDISABLE (IBUF_INTERMDISABLE, OBUFT): 64 instances
  OBUFDS => OBUFDS_DUAL_BUF (INV, OBUFDS, OBUFDS): 1 instances
  RAM16X1D => RAM32X1D (RAMD32, RAMD32): 44 instances
  RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 343 instances
  RAM32X1D => RAM32X1D (RAMD32, RAMD32): 22 instances
  SRLC32E => SRL16E: 1 instances

open_run: Time (s): cpu = 00:00:40 ; elapsed = 00:00:36 . Memory (MB): peak = 2722.559 ; gain = 1118.289
open_report: Time (s): cpu = 00:00:32 ; elapsed = 00:00:17 . Memory (MB): peak = 2874.129 ; gain = 132.512
CRITICAL WARNING: [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.
WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Please run report_bus_skew to ensure that bus skew requirements are met.
open_bd_design {D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/pdm_to_pcm.bd}
open_hw
connect_hw_server
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
open_hw_target
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210203857806A
set_property PROGRAM.FILE {D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.runs/impl_1/leon3mp.bit} [get_hw_devices xc7a200t_0]
current_hw_device [get_hw_devices xc7a200t_0]
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a200t_0] 0]
INFO: [Labtools 27-1435] Device xc7a200t (JTAG device index = 0) is not programmed (DONE status = 0).
set_property PROBES.FILE {} [get_hw_devices xc7a200t_0]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7a200t_0]
set_property PROGRAM.FILE {D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.runs/impl_1/leon3mp.bit} [get_hw_devices xc7a200t_0]
program_hw_devices [get_hw_devices xc7a200t_0]
INFO: [Labtools 27-3164] End of startup status: HIGH
program_hw_devices: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 4194.609 ; gain = 0.000
refresh_hw_device [lindex [get_hw_devices xc7a200t_0] 0]
INFO: [Labtools 27-1434] Device xc7a200t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
ERROR: [Labtoolstcl 44-513] HW Target shutdown. Closing target: localhost:3121/xilinx_tcf/Digilent/210203857806A
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210203857806A
INFO: [Labtools 27-1435] Device xc7a200t (JTAG device index = 0) is not programmed (DONE status = 0).
WARNING: [Labtoolstcl 44-129] No matching hw_ila_data was found.
ERROR: [Labtoolstcl 44-513] HW Target shutdown. Closing target: localhost:3121/xilinx_tcf/Digilent/210203857806A
close_hw
open_hw
connect_hw_server
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
open_hw_target
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210203857806A
set_property PROGRAM.FILE {D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.runs/impl_1/leon3mp.bit} [get_hw_devices xc7a200t_0]
current_hw_device [get_hw_devices xc7a200t_0]
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a200t_0] 0]
INFO: [Labtools 27-1435] Device xc7a200t (JTAG device index = 0) is not programmed (DONE status = 0).
set_property PROBES.FILE {} [get_hw_devices xc7a200t_0]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7a200t_0]
set_property PROGRAM.FILE {D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.runs/impl_1/leon3mp.bit} [get_hw_devices xc7a200t_0]
program_hw_devices [get_hw_devices xc7a200t_0]
INFO: [Labtools 27-3164] End of startup status: HIGH
program_hw_devices: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 4239.438 ; gain = 0.000
refresh_hw_device [lindex [get_hw_devices xc7a200t_0] 0]
INFO: [Labtools 27-1434] Device xc7a200t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
ERROR: [Labtoolstcl 44-513] HW Target shutdown. Closing target: localhost:3121/xilinx_tcf/Digilent/210203857806A
close_hw
open_hw
connect_hw_server
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
ERROR: [Labtoolstcl 44-494] There is no active target available for server at localhost.
 Targets(s) ", jsn-JTAG-SMT1-210203857806A" may be locked by another hw_server.
disconnect_hw_server localhost:3121
connect_hw_server
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
open_hw_target
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210203857806A
set_property PROGRAM.FILE {D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.runs/impl_1/leon3mp.bit} [get_hw_devices xc7a200t_0]
current_hw_device [get_hw_devices xc7a200t_0]
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a200t_0] 0]
INFO: [Labtools 27-1435] Device xc7a200t (JTAG device index = 0) is not programmed (DONE status = 0).
set_property PROBES.FILE {} [get_hw_devices xc7a200t_0]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7a200t_0]
set_property PROGRAM.FILE {D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.runs/impl_1/leon3mp.bit} [get_hw_devices xc7a200t_0]
program_hw_devices [get_hw_devices xc7a200t_0]
INFO: [Labtools 27-3164] End of startup status: HIGH
program_hw_devices: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 4239.898 ; gain = 0.000
refresh_hw_device [lindex [get_hw_devices xc7a200t_0] 0]
INFO: [Labtools 27-1434] Device xc7a200t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
ERROR: [Labtoolstcl 44-513] HW Target shutdown. Closing target: localhost:3121/xilinx_tcf/Digilent/210203857806A
close_hw
open_hw
connect_hw_server
INFO: [Labtools 27-2285] Connecting to hw_server url TCP:localhost:3121
open_hw_target
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210203857806A
set_property PROGRAM.FILE {D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.runs/impl_1/leon3mp.bit} [get_hw_devices xc7a200t_0]
current_hw_device [get_hw_devices xc7a200t_0]
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a200t_0] 0]
INFO: [Labtools 27-1435] Device xc7a200t (JTAG device index = 0) is not programmed (DONE status = 0).
set_property PROBES.FILE {} [get_hw_devices xc7a200t_0]
set_property FULL_PROBES.FILE {} [get_hw_devices xc7a200t_0]
set_property PROGRAM.FILE {D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.runs/impl_1/leon3mp.bit} [get_hw_devices xc7a200t_0]
program_hw_devices [get_hw_devices xc7a200t_0]
INFO: [Labtools 27-3164] End of startup status: HIGH
program_hw_devices: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 4240.316 ; gain = 0.000
refresh_hw_device [lindex [get_hw_devices xc7a200t_0] 0]
INFO: [Labtools 27-1434] Device xc7a200t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it.
ERROR: [Labtoolstcl 44-513] HW Target shutdown. Closing target: localhost:3121/xilinx_tcf/Digilent/210203857806A
open_bd_design {D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/pdm_to_pcm.bd}
set_property location {11 3305 592} [get_bd_cells c_addsub_2]
startgroup
create_bd_cell -type ip -vlnv xilinx.com:ip:mult_gen:12.0 mult_gen_0
endgroup
set_property location {11 3279 766} [get_bd_cells mult_gen_0]
set_property location {12 3662 743} [get_bd_cells mult_gen_0]
connect_bd_net [get_bd_pins mult_gen_0/CLK] [get_bd_pins clk_div_1/clk_out]
WARNING: [BD 41-1731] Type mismatch between connected pins: /clk_div_1/clk_out(undef) and /mult_gen_0/CLK(clk)
connect_bd_net [get_bd_pins mult_gen_0/A] [get_bd_pins c_addsub_2/S]
connect_bd_net [get_bd_pins mult_gen_0/B] [get_bd_pins c_addsub_2/S]
set_property location {12 3666 740} [get_bd_cells mult_gen_0]
set_property location {11 3346 760} [get_bd_cells mult_gen_0]
set_property location {12 3692 528} [get_bd_cells blk_mem_gen_2]
copy_bd_objs /  [get_bd_cells {c_shift_ram_0}]
set_property -dict [list CONFIG.Width.VALUE_SRC USER] [get_bd_cells c_shift_ram_4]
set_property -dict [list CONFIG.OptGoal {Resources} CONFIG.Width {36} CONFIG.Depth {10} CONFIG.DefaultData {000000000000000000000000000000000000} CONFIG.AsyncInitVal {000000000000000000000000000000000000} CONFIG.SyncInitVal {000000000000000000000000000000000000}] [get_bd_cells c_shift_ram_4]
connect_bd_net [get_bd_pins mult_gen_0/P] [get_bd_pins c_shift_ram_4/D]
startgroup
set_property -dict [list CONFIG.Depth {16}] [get_bd_cells c_shift_ram_4]
endgroup
connect_bd_net [get_bd_pins c_shift_ram_4/CLK] [get_bd_pins clk_div_1/clk_out]
WARNING: [BD 41-1731] Type mismatch between connected pins: /clk_div_1/clk_out(undef) and /c_shift_ram_4/CLK(clk)
connect_bd_net [get_bd_pins c_shift_ram_4/CE] [get_bd_pins scan_0/adder_enable]
WARNING: [BD 41-1731] Type mismatch between connected pins: /scan_0/adder_enable(undef) and /c_shift_ram_4/CE(ce)
set_property location {12 3610 660} [get_bd_cells c_shift_ram_4]
set_property location {12.5 3947 520} [get_bd_cells c_shift_ram_4]
copy_bd_objs /  [get_bd_cells {blk_mem_gen_0}]
WARNING: [IP_Flow 19-4067] Ignoring invalid widget type specified checkbox.Providing a default widget
WARNING: [IP_Flow 19-4067] Ignoring invalid widget type specified checkbox.Providing a default widget
set_property -dict [list CONFIG.Memory_Type {Single_Port_RAM} CONFIG.Use_Byte_Write_Enable {false} CONFIG.Write_Width_A {36} CONFIG.Write_Depth_A {7} CONFIG.Read_Width_A {36} CONFIG.Operating_Mode_A {NO_CHANGE} CONFIG.Enable_A {Use_ENA_Pin} CONFIG.Write_Width_B {36} CONFIG.Read_Width_B {36} CONFIG.Register_PortA_Output_of_Memory_Primitives {true} CONFIG.Load_Init_File {false} CONFIG.Coe_File {no_coe_file_loaded} CONFIG.Fill_Remaining_Memory_Locations {true} CONFIG.Port_A_Write_Rate {50}] [get_bd_cells blk_mem_gen_4]
WARNING: [IP_Flow 19-3374] An attempt to modify the value of disabled parameter 'Coe_File' from 'no_coe_file_loaded' to 'no_coe_file_loaded' has been ignored for IP 'blk_mem_gen_4'
close [ open D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/new/energy_compare.vhd w ]
add_files D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/new/energy_compare.vhd
set_property library work [get_files  D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/new/energy_compare.vhd]
update_compile_order -fileset sources_1
open_bd_design {D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/pdm_to_pcm.bd}
create_bd_cell -type module -reference energy_compare energy_compare_0
INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing.
INFO: [IP_Flow 19-234] Refreshing IP repositories
WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'd:/sound_location_project/vivado/dat096-master-latest_version/sound_location_project'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
set_property location {12 3525 424} [get_bd_cells energy_compare_0]
connect_bd_net [get_bd_pins energy_compare_0/clk] [get_bd_pins clk_div_1/clk_out]
WARNING: [BD 41-1731] Type mismatch between connected pins: /clk_div_1/clk_out(undef) and /energy_compare_0/clk(clk)
connect_bd_net [get_bd_pins energy_compare_0/val_in] [get_bd_pins mult_gen_0/P]
connect_bd_net [get_bd_pins energy_compare_0/adder_enable] [get_bd_pins scan_0/adder_enable]
connect_bd_net [get_bd_pins energy_compare_0/start] [get_bd_pins scan_0/adder_enable]
update_module_reference pdm_to_pcm_energy_compare_0_0
INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing.
INFO: [IP_Flow 19-234] Refreshing IP repositories
WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'd:/sound_location_project/vivado/dat096-master-latest_version/sound_location_project'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
Upgrading 'D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/pdm_to_pcm.bd'
INFO: [IP_Flow 19-3420] Updated pdm_to_pcm_energy_compare_0_0 to use current project options
WARNING: [IP_Flow 19-4700] Upgrade has removed port 'adder_enable'
WARNING: [IP_Flow 19-4700] Upgrade has removed port 't_finish'
WARNING: [IP_Flow 19-3298] Detected external port differences while upgrading 'pdm_to_pcm_energy_compare_0_0'. These changes may impact your design.
WARNING: [BD 41-1731] Type mismatch between connected pins: /clk_div_1/clk_out(undef) and /energy_compare_0_upgraded_ipi/clk(clk)
CRITICAL WARNING: [BD 41-1167] The pin 'adder_enable' is not found on the upgraded version of the cell '/energy_compare_0'. Its connection to the net 'Net1' has been removed.
CRITICAL WARNING: [Coretcl 2-1280] The upgrade of 'pdm_to_pcm_energy_compare_0_0' has identified issues that may require user intervention. Please verify that the instance is correctly configured, and review any upgrade messages.
Wrote  : <D:\sound_location_project\vivado\dat096-master-latest_version\latest_version\dat096_ref_design.srcs\sources_1\bd\pdm_to_pcm\pdm_to_pcm.bd> 
Wrote  : <D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ui/bd_8ec0abfc.ui> 
update_module_reference: Time (s): cpu = 00:00:01 ; elapsed = 00:00:14 . Memory (MB): peak = 4477.453 ; gain = 15.512
update_compile_order -fileset sources_1
connect_bd_net [get_bd_pins energy_compare_0/val_out] [get_bd_pins blk_mem_gen_4/dina]
WARNING: [BD 41-1306] The connection to interface pin /blk_mem_gen_4/dina is being overridden by the user. This pin will not be connected as a part of interface connection BRAM_PORTA
WARNING: [IP_Flow 19-4067] Ignoring invalid widget type specified checkbox.Providing a default widget
WARNING: [IP_Flow 19-4067] Ignoring invalid widget type specified checkbox.Providing a default widget
connect_bd_net [get_bd_pins blk_mem_gen_4/clka] [get_bd_pins clk_div_1/clk_out]
WARNING: [BD 41-1306] The connection to interface pin /blk_mem_gen_4/clka is being overridden by the user. This pin will not be connected as a part of interface connection BRAM_PORTA
WARNING: [BD 41-1731] Type mismatch between connected pins: /clk_div_1/clk_out(undef) and /blk_mem_gen_4/clka(clk)
WARNING: [IP_Flow 19-4067] Ignoring invalid widget type specified checkbox.Providing a default widget
WARNING: [IP_Flow 19-4067] Ignoring invalid widget type specified checkbox.Providing a default widget
CRITICAL WARNING: [HDL 9-806] Syntax error near "=". [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/new/scan.vhd:111]
CRITICAL WARNING: [HDL 9-806] Syntax error near "=". [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/new/scan.vhd:111]
CRITICAL WARNING: [HDL 9-806] Syntax error near "=". [D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/new/scan.vhd:111]
update_module_reference pdm_to_pcm_energy_compare_0_0
INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing.
INFO: [IP_Flow 19-234] Refreshing IP repositories
WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'd:/sound_location_project/vivado/dat096-master-latest_version/sound_location_project'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
Upgrading 'D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/pdm_to_pcm.bd'
INFO: [IP_Flow 19-3420] Updated pdm_to_pcm_energy_compare_0_0 to use current project options
WARNING: [BD 41-1731] Type mismatch between connected pins: /clk_div_1/clk_out(undef) and /energy_compare_0_upgraded_ipi/clk(clk)
Wrote  : <D:\sound_location_project\vivado\dat096-master-latest_version\latest_version\dat096_ref_design.srcs\sources_1\bd\pdm_to_pcm\pdm_to_pcm.bd> 
Wrote  : <D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ui/bd_8ec0abfc.ui> 
update_module_reference pdm_to_pcm_scan_0_0
INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing.
INFO: [IP_Flow 19-234] Refreshing IP repositories
WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'd:/sound_location_project/vivado/dat096-master-latest_version/sound_location_project'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
Upgrading 'D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/pdm_to_pcm.bd'
INFO: [IP_Flow 19-3420] Updated pdm_to_pcm_scan_0_0 to use current project options
WARNING: [IP_Flow 19-4698] Upgrade has added port 'control_ram'
WARNING: [IP_Flow 19-4698] Upgrade has added port 'max_found'
WARNING: [IP_Flow 19-4698] Upgrade has added port 'ram_address'
WARNING: [IP_Flow 19-3298] Detected external port differences while upgrading 'pdm_to_pcm_scan_0_0'. These changes may impact your design.
WARNING: [BD 41-1731] Type mismatch between connected pins: /clk_div_1/clk_out(undef) and /scan_0_upgraded_ipi/clk(clk)
WARNING: [BD 41-1731] Type mismatch between connected pins: /c_addsub_1/CE(ce) and /scan_0_upgraded_ipi/adder_enable(undef)
WARNING: [BD 41-1731] Type mismatch between connected pins: /c_addsub_0/CE(ce) and /scan_0_upgraded_ipi/adder_enable(undef)
WARNING: [BD 41-1731] Type mismatch between connected pins: /c_addsub_2/CE(ce) and /scan_0_upgraded_ipi/adder_enable(undef)
WARNING: [BD 41-1731] Type mismatch between connected pins: /c_shift_ram_4/CE(ce) and /scan_0_upgraded_ipi/adder_enable(undef)
WARNING: [BD 41-1731] Type mismatch between connected pins: /c_shift_ram_0/CE(ce) and /scan_0_upgraded_ipi/scan_finish(undef)
WARNING: [BD 41-1731] Type mismatch between connected pins: /c_shift_ram_1/CE(ce) and /scan_0_upgraded_ipi/scan_finish(undef)
WARNING: [BD 41-1731] Type mismatch between connected pins: /c_shift_ram_2/CE(ce) and /scan_0_upgraded_ipi/scan_finish(undef)
WARNING: [BD 41-1731] Type mismatch between connected pins: /c_shift_ram_3/CE(ce) and /scan_0_upgraded_ipi/scan_finish(undef)
CRITICAL WARNING: [Coretcl 2-1280] The upgrade of 'pdm_to_pcm_scan_0_0' has identified issues that may require user intervention. Please verify that the instance is correctly configured, and review any upgrade messages.
Wrote  : <D:\sound_location_project\vivado\dat096-master-latest_version\latest_version\dat096_ref_design.srcs\sources_1\bd\pdm_to_pcm\pdm_to_pcm.bd> 
Wrote  : <D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ui/bd_8ec0abfc.ui> 
update_module_reference: Time (s): cpu = 00:00:02 ; elapsed = 00:00:07 . Memory (MB): peak = 4640.941 ; gain = 7.648
connect_bd_net [get_bd_pins scan_0/max_found] [get_bd_pins energy_compare_0/max_found]
connect_bd_net [get_bd_pins blk_mem_gen_4/ena] [get_bd_pins scan_0/control_ram]
WARNING: [BD 41-1306] The connection to interface pin /blk_mem_gen_4/ena is being overridden by the user. This pin will not be connected as a part of interface connection BRAM_PORTA
connect_bd_net [get_bd_pins blk_mem_gen_4/addra] [get_bd_pins scan_0/ram_address]
WARNING: [BD 41-1306] The connection to interface pin /blk_mem_gen_4/addra is being overridden by the user. This pin will not be connected as a part of interface connection BRAM_PORTA
update_module_reference pdm_to_pcm_scan_0_0
INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing.
INFO: [IP_Flow 19-234] Refreshing IP repositories
WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'd:/sound_location_project/vivado/dat096-master-latest_version/sound_location_project'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
Upgrading 'D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/pdm_to_pcm.bd'
INFO: [IP_Flow 19-3420] Updated pdm_to_pcm_scan_0_0 to use current project options
WARNING: [IP_Flow 19-4706] Upgraded port 'ram_address' width 3 differs from original width 4
WARNING: [IP_Flow 19-3298] Detected external port differences while upgrading 'pdm_to_pcm_scan_0_0'. These changes may impact your design.
WARNING: [BD 41-1731] Type mismatch between connected pins: /clk_div_1/clk_out(undef) and /scan_0_upgraded_ipi/clk(clk)
WARNING: [BD 41-1731] Type mismatch between connected pins: /c_addsub_1/CE(ce) and /scan_0_upgraded_ipi/adder_enable(undef)
WARNING: [BD 41-1731] Type mismatch between connected pins: /c_addsub_0/CE(ce) and /scan_0_upgraded_ipi/adder_enable(undef)
WARNING: [BD 41-1731] Type mismatch between connected pins: /c_addsub_2/CE(ce) and /scan_0_upgraded_ipi/adder_enable(undef)
WARNING: [BD 41-1731] Type mismatch between connected pins: /c_shift_ram_4/CE(ce) and /scan_0_upgraded_ipi/adder_enable(undef)
WARNING: [BD 41-1731] Type mismatch between connected pins: /c_shift_ram_0/CE(ce) and /scan_0_upgraded_ipi/scan_finish(undef)
WARNING: [BD 41-1731] Type mismatch between connected pins: /c_shift_ram_1/CE(ce) and /scan_0_upgraded_ipi/scan_finish(undef)
WARNING: [BD 41-1731] Type mismatch between connected pins: /c_shift_ram_2/CE(ce) and /scan_0_upgraded_ipi/scan_finish(undef)
WARNING: [BD 41-1731] Type mismatch between connected pins: /c_shift_ram_3/CE(ce) and /scan_0_upgraded_ipi/scan_finish(undef)
CRITICAL WARNING: [Coretcl 2-1280] The upgrade of 'pdm_to_pcm_scan_0_0' has identified issues that may require user intervention. Please verify that the instance is correctly configured, and review any upgrade messages.
Wrote  : <D:\sound_location_project\vivado\dat096-master-latest_version\latest_version\dat096_ref_design.srcs\sources_1\bd\pdm_to_pcm\pdm_to_pcm.bd> 
Wrote  : <D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ui/bd_8ec0abfc.ui> 
update_module_reference: Time (s): cpu = 00:00:02 ; elapsed = 00:00:14 . Memory (MB): peak = 5370.945 ; gain = 17.867
update_module_reference pdm_to_pcm_scan_0_0
INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing.
INFO: [IP_Flow 19-234] Refreshing IP repositories
WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'd:/sound_location_project/vivado/dat096-master-latest_version/sound_location_project'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
Upgrading 'D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/pdm_to_pcm.bd'
INFO: [IP_Flow 19-3420] Updated pdm_to_pcm_scan_0_0 to use current project options
WARNING: [BD 41-1731] Type mismatch between connected pins: /clk_div_1/clk_out(undef) and /scan_0_upgraded_ipi/clk(clk)
WARNING: [BD 41-1731] Type mismatch between connected pins: /c_addsub_1/CE(ce) and /scan_0_upgraded_ipi/adder_enable(undef)
WARNING: [BD 41-1731] Type mismatch between connected pins: /c_addsub_0/CE(ce) and /scan_0_upgraded_ipi/adder_enable(undef)
WARNING: [BD 41-1731] Type mismatch between connected pins: /c_addsub_2/CE(ce) and /scan_0_upgraded_ipi/adder_enable(undef)
WARNING: [BD 41-1731] Type mismatch between connected pins: /c_shift_ram_4/CE(ce) and /scan_0_upgraded_ipi/adder_enable(undef)
WARNING: [BD 41-1731] Type mismatch between connected pins: /c_shift_ram_0/CE(ce) and /scan_0_upgraded_ipi/scan_finish(undef)
WARNING: [BD 41-1731] Type mismatch between connected pins: /c_shift_ram_1/CE(ce) and /scan_0_upgraded_ipi/scan_finish(undef)
WARNING: [BD 41-1731] Type mismatch between connected pins: /c_shift_ram_2/CE(ce) and /scan_0_upgraded_ipi/scan_finish(undef)
WARNING: [BD 41-1731] Type mismatch between connected pins: /c_shift_ram_3/CE(ce) and /scan_0_upgraded_ipi/scan_finish(undef)
Wrote  : <D:\sound_location_project\vivado\dat096-master-latest_version\latest_version\dat096_ref_design.srcs\sources_1\bd\pdm_to_pcm\pdm_to_pcm.bd> 
close [ open D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/new/find_max.vhd w ]
add_files D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/new/find_max.vhd
set_property library work [get_files  D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/new/find_max.vhd]
update_compile_order -fileset sources_1
update_compile_order -fileset sources_1
update_module_reference pdm_to_pcm_scan_0_0
INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing.
INFO: [IP_Flow 19-234] Refreshing IP repositories
WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'd:/sound_location_project/vivado/dat096-master-latest_version/sound_location_project'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
Upgrading 'D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/pdm_to_pcm.bd'
INFO: [IP_Flow 19-3420] Updated pdm_to_pcm_scan_0_0 to use current project options
WARNING: [IP_Flow 19-4698] Upgrade has added port 'get_max'
WARNING: [IP_Flow 19-3298] Detected external port differences while upgrading 'pdm_to_pcm_scan_0_0'. These changes may impact your design.
WARNING: [BD 41-1731] Type mismatch between connected pins: /clk_div_1/clk_out(undef) and /scan_0_upgraded_ipi/clk(clk)
WARNING: [BD 41-1731] Type mismatch between connected pins: /c_addsub_1/CE(ce) and /scan_0_upgraded_ipi/adder_enable(undef)
WARNING: [BD 41-1731] Type mismatch between connected pins: /c_addsub_0/CE(ce) and /scan_0_upgraded_ipi/adder_enable(undef)
WARNING: [BD 41-1731] Type mismatch between connected pins: /c_addsub_2/CE(ce) and /scan_0_upgraded_ipi/adder_enable(undef)
WARNING: [BD 41-1731] Type mismatch between connected pins: /c_shift_ram_4/CE(ce) and /scan_0_upgraded_ipi/adder_enable(undef)
WARNING: [BD 41-1731] Type mismatch between connected pins: /c_shift_ram_0/CE(ce) and /scan_0_upgraded_ipi/scan_finish(undef)
WARNING: [BD 41-1731] Type mismatch between connected pins: /c_shift_ram_1/CE(ce) and /scan_0_upgraded_ipi/scan_finish(undef)
WARNING: [BD 41-1731] Type mismatch between connected pins: /c_shift_ram_2/CE(ce) and /scan_0_upgraded_ipi/scan_finish(undef)
WARNING: [BD 41-1731] Type mismatch between connected pins: /c_shift_ram_3/CE(ce) and /scan_0_upgraded_ipi/scan_finish(undef)
CRITICAL WARNING: [Coretcl 2-1280] The upgrade of 'pdm_to_pcm_scan_0_0' has identified issues that may require user intervention. Please verify that the instance is correctly configured, and review any upgrade messages.
Wrote  : <D:\sound_location_project\vivado\dat096-master-latest_version\latest_version\dat096_ref_design.srcs\sources_1\bd\pdm_to_pcm\pdm_to_pcm.bd> 
Wrote  : <D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ui/bd_8ec0abfc.ui> 
update_module_reference: Time (s): cpu = 00:00:01 ; elapsed = 00:00:10 . Memory (MB): peak = 5496.809 ; gain = 0.000
create_bd_cell -type module -reference find_max find_max_0
INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing.
INFO: [IP_Flow 19-234] Refreshing IP repositories
WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'd:/sound_location_project/vivado/dat096-master-latest_version/sound_location_project'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
set_property location {12 3517 902} [get_bd_cells find_max_0]
connect_bd_net [get_bd_pins find_max_0/clk] [get_bd_pins clk_div_1/clk_out]
WARNING: [BD 41-1731] Type mismatch between connected pins: /clk_div_1/clk_out(undef) and /find_max_0/clk(clk)
connect_bd_net [get_bd_pins find_max_0/val_in] [get_bd_pins blk_mem_gen_4/douta]
WARNING: [BD 41-1306] The connection to interface pin /blk_mem_gen_4/douta is being overridden by the user. This pin will not be connected as a part of interface connection BRAM_PORTA
connect_bd_net [get_bd_pins find_max_0/start] [get_bd_pins scan_0/get_max]
set_property location {12 3596 901} [get_bd_cells find_max_0]
disconnect_bd_net /c_addsub_2_S [get_bd_pins fifo_generator_0/din]
connect_bd_net [get_bd_pins fifo_generator_0/din] [get_bd_pins blk_mem_gen_4/douta]
WARNING: [BD 41-1306] The connection to interface pin /fifo_generator_0/din is being overridden by the user. This pin will not be connected as a part of interface connection FIFO_WRITE
startgroup
set_property -dict [list CONFIG.PortBWidth.VALUE_SRC USER CONFIG.PortAWidth.VALUE_SRC USER] [get_bd_cells mult_gen_0]
set_property -dict [list CONFIG.PortAWidth {16} CONFIG.PortBWidth {16} CONFIG.OutputWidthHigh {31}] [get_bd_cells mult_gen_0]
endgroup
delete_bd_objs [get_bd_cells c_shift_ram_4]
startgroup
set_property -dict [list CONFIG.Input_Data_Width {32} CONFIG.Output_Depth {1024} CONFIG.Read_Data_Count_Width {10}] [get_bd_cells fifo_generator_0]
INFO: [xilinx.com:ip:fifo_generator:13.2-5968] /fifo_generator_0Executing the post_config_ip from bd
endgroup
update_module_reference pdm_to_pcm_energy_compare_0_0
INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing.
INFO: [IP_Flow 19-234] Refreshing IP repositories
WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'd:/sound_location_project/vivado/dat096-master-latest_version/sound_location_project'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
Upgrading 'D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/pdm_to_pcm.bd'
INFO: [IP_Flow 19-3420] Updated pdm_to_pcm_energy_compare_0_0 to use current project options
WARNING: [IP_Flow 19-4706] Upgraded port 'val_in' width 32 differs from original width 36
WARNING: [IP_Flow 19-4706] Upgraded port 'val_out' width 32 differs from original width 36
WARNING: [IP_Flow 19-3298] Detected external port differences while upgrading 'pdm_to_pcm_energy_compare_0_0'. These changes may impact your design.
WARNING: [BD 41-1731] Type mismatch between connected pins: /clk_div_1/clk_out(undef) and /energy_compare_0_upgraded_ipi/clk(clk)
CRITICAL WARNING: [Coretcl 2-1280] The upgrade of 'pdm_to_pcm_energy_compare_0_0' has identified issues that may require user intervention. Please verify that the instance is correctly configured, and review any upgrade messages.
Wrote  : <D:\sound_location_project\vivado\dat096-master-latest_version\latest_version\dat096_ref_design.srcs\sources_1\bd\pdm_to_pcm\pdm_to_pcm.bd> 
Wrote  : <D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ui/bd_8ec0abfc.ui> 
update_module_reference pdm_to_pcm_find_max_0_0
INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing.
INFO: [IP_Flow 19-234] Refreshing IP repositories
WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'd:/sound_location_project/vivado/dat096-master-latest_version/sound_location_project'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
Upgrading 'D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/pdm_to_pcm.bd'
INFO: [IP_Flow 19-3420] Updated pdm_to_pcm_find_max_0_0 to use current project options
WARNING: [IP_Flow 19-4706] Upgraded port 'val_in' width 32 differs from original width 36
WARNING: [IP_Flow 19-4706] Upgraded port 'val_out' width 32 differs from original width 36
WARNING: [IP_Flow 19-3298] Detected external port differences while upgrading 'pdm_to_pcm_find_max_0_0'. These changes may impact your design.
WARNING: [BD 41-1731] Type mismatch between connected pins: /clk_div_1/clk_out(undef) and /find_max_0_upgraded_ipi/clk(clk)
CRITICAL WARNING: [Coretcl 2-1280] The upgrade of 'pdm_to_pcm_find_max_0_0' has identified issues that may require user intervention. Please verify that the instance is correctly configured, and review any upgrade messages.
Wrote  : <D:\sound_location_project\vivado\dat096-master-latest_version\latest_version\dat096_ref_design.srcs\sources_1\bd\pdm_to_pcm\pdm_to_pcm.bd> 
Wrote  : <D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ui/bd_8ec0abfc.ui> 
update_module_reference: Time (s): cpu = 00:00:00 ; elapsed = 00:00:06 . Memory (MB): peak = 5496.809 ; gain = 0.000
update_compile_order -fileset sources_1
update_module_reference pdm_to_pcm_scan_0_0
INFO: [IP_Flow 19-5107] Inferred bus interface 'clk' of definition 'xilinx.com:signal:clock:1.0' (from Xilinx Repository).
WARNING: [IP_Flow 19-3153] Bus Interface 'clk': ASSOCIATED_BUSIF bus parameter is missing.
INFO: [IP_Flow 19-234] Refreshing IP repositories
WARNING: [IP_Flow 19-2248] Failed to load user IP repository 'd:/sound_location_project/vivado/dat096-master-latest_version/sound_location_project'; Can't find the specified path.
If this directory should no longer be in your list of user repositories, go to the IP Settings dialog and remove it.
Upgrading 'D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/pdm_to_pcm.bd'
INFO: [IP_Flow 19-3420] Updated pdm_to_pcm_scan_0_0 to use current project options
WARNING: [BD 41-1731] Type mismatch between connected pins: /clk_div_1/clk_out(undef) and /scan_0_upgraded_ipi/clk(clk)
WARNING: [BD 41-1731] Type mismatch between connected pins: /c_addsub_1/CE(ce) and /scan_0_upgraded_ipi/adder_enable(undef)
WARNING: [BD 41-1731] Type mismatch between connected pins: /c_addsub_0/CE(ce) and /scan_0_upgraded_ipi/adder_enable(undef)
WARNING: [BD 41-1731] Type mismatch between connected pins: /c_addsub_2/CE(ce) and /scan_0_upgraded_ipi/adder_enable(undef)
WARNING: [BD 41-1731] Type mismatch between connected pins: /c_shift_ram_0/CE(ce) and /scan_0_upgraded_ipi/scan_finish(undef)
WARNING: [BD 41-1731] Type mismatch between connected pins: /c_shift_ram_1/CE(ce) and /scan_0_upgraded_ipi/scan_finish(undef)
WARNING: [BD 41-1731] Type mismatch between connected pins: /c_shift_ram_2/CE(ce) and /scan_0_upgraded_ipi/scan_finish(undef)
WARNING: [BD 41-1731] Type mismatch between connected pins: /c_shift_ram_3/CE(ce) and /scan_0_upgraded_ipi/scan_finish(undef)
Wrote  : <D:\sound_location_project\vivado\dat096-master-latest_version\latest_version\dat096_ref_design.srcs\sources_1\bd\pdm_to_pcm\pdm_to_pcm.bd> 
Wrote  : <D:/sound_location_project/vivado/dat096-master-latest_version/latest_version/dat096_ref_design.srcs/sources_1/bd/pdm_to_pcm/ui/bd_8ec0abfc.ui> 
update_module_reference: Time (s): cpu = 00:00:01 ; elapsed = 00:00:14 . Memory (MB): peak = 5527.012 ; gain = 15.480
exit
INFO: [Common 17-206] Exiting Vivado at Thu May 21 02:22:31 2020...
