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-- Company: 
-- Engineer: 
-- 
-- Create Date: 07/24/2017 12:42:44 PM
-- Design Name: 
-- Module Name: pdm1tocic8 - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity pdm1tocic8 is
    Port ( pdm_data : in STD_LOGIC;
           cic_data : out STD_LOGIC_VECTOR (7 downto 0));
end pdm1tocic8;

architecture Behavioral of pdm1tocic8 is


begin
cic_data(7) <= '0';
cic_data(6) <= '0';
cic_data(5) <= '0';
cic_data(4) <= '0';
cic_data(3) <= '0';
cic_data(2) <= '0';
cic_data(1) <= pdm_data;
cic_data(0) <= '1';


end Behavioral;
