sim: command line: ./bin/sim-outorder -config ./configs/l2t1-perfect/base2.txt -redir:sim ./configs/l2t1-perfect/Stats_base2_qsort.txt ./apps/qsort/qsort_small ./apps/qsort/input_small.dat 

sim: simulation started @ Wed Sep 25 15:49:33 2019

sim: ** starting performance simulation **

sim: ** simulation statistics **

# Statistics on Performance:

sim_IPC                      0.4433 # instructions per cycle
sim_CPI                      2.2556 # cycles per instruction
sim_cycle                  94506186 # total simulation time in cycles
sim_elapsed_time                 17 # total simulation time in seconds
sim_inst_rate          2464626.1176 # simulation speed (in insts/sec)
sim_exec_BW                  0.4433 # total instructions (mis-spec + committed) per cycle
sim_IPB                      6.2317 # instruction per branch

# Statistics on  Commited and Executed instructions:

sim_num_insn               41898644 # total number of instructions committed
sim_total_insn             41898643 # total number of instructions executed
sim_num_icmp               13253882 # total number of integer insts committed
sim_total_icmp             13253893 # total number of integer insts executed
sim_num_fcmp                      0 # total number of FP insts committed
sim_total_fcmp                    0 # total number of FP insts executed
sim_num_refs               21921253 # total number of loads and stores committed
sim_total_refs             21921253 # total number of loads and stores executed
sim_num_branches            6723479 # total number of branches committed
sim_total_branches          6723479 # total number of branches executed
freq_icmp_exe          31.63 # Freqeuncy (%) of executed integer instructions
freq_fcmp_exe           0.00 # Freqeuncy (%) of executed FP instructions
freq_refs_exe          52.32 # Freqeuncy (%) of executed loads and stores
freq_branches_exe      16.05 # Freqeuncy (%) of executed branch instructions

# Statistics on Processor Core :

busy_int_alu               18406090 # Cyles integer ALU(s) is busy
busy_int_mul                  73759 # Cyles integer MULT/DIV(s) is busy
busy_fp_alu                       0 # Cyles FP ALU(s) is busy
busy_fp_mul                       0 # Cyles FP MULT/DIV(s) is busy
IFQ_count                 319179249 # cumulative IFQ occupancy
IFQ_fcount                 68206333 # cumulative IFQ full count
ifq_occupancy                3.3773 # avg IFQ occupancy (insn's)
ifq_rate                     0.4433 # avg IFQ dispatch rate (insn/cycle)
ifq_latency                  7.6179 # avg IFQ occupant latency (cycle's)
ifq_full                     0.7217 # fraction of time (cycle's) IFQ was full
RUU_count                 351066943 # cumulative RUU occupancy
RUU_fcount                    13651 # cumulative RUU full count
ruu_occupancy                3.7148 # avg RUU occupancy (insn's)
ruu_rate                     0.4433 # avg RUU dispatch rate (insn/cycle)
ruu_latency                  8.3790 # avg RUU occupant latency (cycle's)
ruu_full                     0.0001 # fraction of time (cycle's) RUU was full
LSQ_count                 232685156 # cumulative LSQ occupancy
LSQ_fcount                    76971 # cumulative LSQ full count
lsq_occupancy                2.4621 # avg LSQ occupancy (insn's)
lsq_rate                     0.4433 # avg LSQ dispatch rate (insn/cycle)
lsq_latency                  5.5535 # avg LSQ occupant latency (cycle's)
lsq_full                     0.0008 # fraction of time (cycle's) LSQ was full

# Statistics on Branch Predictors :


# Statistics on Level-1 and Level-2 Caches :

il1.accesses               49914171 # total number of accesses
il1.hits                   49913900 # total number of hits
il1.misses                      271 # total number of misses
il1.miss_rate           0.00 # miss rate (i.e., misses/ref)
dl1.accesses               21911252 # total number of accesses
dl1.hits                   21617885 # total number of hits
dl1.misses                   293367 # total number of misses
dl1.miss_rate           0.01 # miss rate (i.e., misses/ref)

