DATA cache dl1 =============== stringsearch ------------ Hit latency: 1, assoc: 1, cache_size: 4096 sim_CPI 17.6056 # cycles per instruction Hit latency: 1, assoc: 1, cache_size: 8192 sim_CPI 17.4600 # cycles per instruction Hit latency: 2, assoc: 1, cache_size: 16384 sim_CPI 17.4266 # cycles per instruction Hit latency: 2, assoc: 1, cache_size: 32768 sim_CPI 17.4215 # cycles per instruction --------------------------------------------------------------- Hit latency: 1, assoc: 2, cache_size: 4096 sim_CPI 17.4704 # cycles per instruction Hit latency: 2, assoc: 2, cache_size: 8192 sim_CPI 17.4426 # cycles per instruction Hit latency: 2, assoc: 2, cache_size: 16384 sim_CPI 17.4286 # cycles per instruction Hit latency: 3, assoc: 2, cache_size: 32768 sim_CPI 17.4839 # cycles per instruction --------------------------------------------------------------- Hit latency: 2, assoc: 4, cache_size: 4096 sim_CPI 17.4357 # cycles per instruction Hit latency: 2, assoc: 4, cache_size: 8192 sim_CPI 17.4320 # cycles per instruction Hit latency: 3, assoc: 4, cache_size: 16384 sim_CPI 17.4891 # cycles per instruction Hit latency: 3, assoc: 4, cache_size: 32768 sim_CPI 17.4839 # cycles per instruction --------------------------------------------------------------- Hit latency: 2, assoc: 8, cache_size: 4096 sim_CPI 17.4327 # cycles per instruction Hit latency: 3, assoc: 8, cache_size: 8192 sim_CPI 17.4937 # cycles per instruction Hit latency: 3, assoc: 8, cache_size: 16384 sim_CPI 17.4864 # cycles per instruction Hit latency: 4, assoc: 8, cache_size: 32768 sim_CPI 17.5656 # cycles per instruction --------------------------------------------------------------- jpeg ------------ Hit latency: 1, assoc: 1, cache_size: 4096 sim_CPI 6.1088 # cycles per instruction Hit latency: 1, assoc: 1, cache_size: 8192 sim_CPI 5.2230 # cycles per instruction Hit latency: 2, assoc: 1, cache_size: 16384 sim_CPI 4.9712 # cycles per instruction Hit latency: 2, assoc: 1, cache_size: 32768 sim_CPI 4.8157 # cycles per instruction --------------------------------------------------------------- Hit latency: 1, assoc: 2, cache_size: 4096 sim_CPI 5.8863 # cycles per instruction Hit latency: 2, assoc: 2, cache_size: 8192 sim_CPI 5.0090 # cycles per instruction Hit latency: 2, assoc: 2, cache_size: 16384 sim_CPI 4.8080 # cycles per instruction Hit latency: 3, assoc: 2, cache_size: 32768 sim_CPI 4.8646 # cycles per instruction --------------------------------------------------------------- Hit latency: 2, assoc: 4, cache_size: 4096 sim_CPI 5.7906 # cycles per instruction Hit latency: 2, assoc: 4, cache_size: 8192 sim_CPI 5.0028 # cycles per instruction Hit latency: 3, assoc: 4, cache_size: 16384 sim_CPI 4.9205 # cycles per instruction Hit latency: 3, assoc: 4, cache_size: 32768 sim_CPI 4.8692 # cycles per instruction --------------------------------------------------------------- Hit latency: 2, assoc: 8, cache_size: 4096 sim_CPI 5.2097 # cycles per instruction Hit latency: 3, assoc: 8, cache_size: 8192 sim_CPI 5.1402 # cycles per instruction Hit latency: 3, assoc: 8, cache_size: 16384 sim_CPI 4.9161 # cycles per instruction Hit latency: 4, assoc: 8, cache_size: 32768 sim_CPI 5.0087 # cycles per instruction --------------------------------------------------------------- gsm ------------ Hit latency: 1, assoc: 1, cache_size: 4096 sim_CPI 3.3812 # cycles per instruction Hit latency: 1, assoc: 1, cache_size: 8192 sim_CPI 3.3444 # cycles per instruction Hit latency: 2, assoc: 1, cache_size: 16384 sim_CPI 3.3365 # cycles per instruction Hit latency: 2, assoc: 1, cache_size: 32768 sim_CPI 3.3033 # cycles per instruction --------------------------------------------------------------- Hit latency: 1, assoc: 2, cache_size: 4096 sim_CPI 3.3478 # cycles per instruction Hit latency: 2, assoc: 2, cache_size: 8192 sim_CPI 3.2938 # cycles per instruction Hit latency: 2, assoc: 2, cache_size: 16384 sim_CPI 3.2799 # cycles per instruction Hit latency: 3, assoc: 2, cache_size: 32768 sim_CPI 3.2853 # cycles per instruction --------------------------------------------------------------- Hit latency: 2, assoc: 4, cache_size: 4096 sim_CPI 3.3527 # cycles per instruction Hit latency: 2, assoc: 4, cache_size: 8192 sim_CPI 3.2859 # cycles per instruction Hit latency: 3, assoc: 4, cache_size: 16384 sim_CPI 3.2856 # cycles per instruction Hit latency: 3, assoc: 4, cache_size: 32768 sim_CPI 3.2845 # cycles per instruction --------------------------------------------------------------- Hit latency: 2, assoc: 8, cache_size: 4096 sim_CPI 3.3537 # cycles per instruction Hit latency: 3, assoc: 8, cache_size: 8192 sim_CPI 3.2934 # cycles per instruction Hit latency: 3, assoc: 8, cache_size: 16384 sim_CPI 3.2852 # cycles per instruction Hit latency: 4, assoc: 8, cache_size: 32768 sim_CPI 3.3209 # cycles per instruction --------------------------------------------------------------- qsort ------------ Hit latency: 1, assoc: 1, cache_size: 4096 sim_CPI 15.4579 # cycles per instruction Hit latency: 1, assoc: 1, cache_size: 8192 sim_CPI 15.0354 # cycles per instruction Hit latency: 2, assoc: 1, cache_size: 16384 sim_CPI 14.6812 # cycles per instruction Hit latency: 2, assoc: 1, cache_size: 32768 sim_CPI 14.1801 # cycles per instruction --------------------------------------------------------------- Hit latency: 1, assoc: 2, cache_size: 4096 sim_CPI 14.9852 # cycles per instruction Hit latency: 2, assoc: 2, cache_size: 8192 sim_CPI 14.6457 # cycles per instruction Hit latency: 2, assoc: 2, cache_size: 16384 sim_CPI 14.3278 # cycles per instruction Hit latency: 3, assoc: 2, cache_size: 32768 sim_CPI 14.0459 # cycles per instruction --------------------------------------------------------------- Hit latency: 2, assoc: 4, cache_size: 4096 sim_CPI 14.9897 # cycles per instruction Hit latency: 2, assoc: 4, cache_size: 8192 sim_CPI 14.6635 # cycles per instruction Hit latency: 3, assoc: 4, cache_size: 16384 sim_CPI 14.3760 # cycles per instruction Hit latency: 3, assoc: 4, cache_size: 32768 sim_CPI 14.0692 # cycles per instruction --------------------------------------------------------------- Hit latency: 2, assoc: 8, cache_size: 4096 sim_CPI 15.0218 # cycles per instruction Hit latency: 3, assoc: 8, cache_size: 8192 sim_CPI 14.7272 # cycles per instruction Hit latency: 3, assoc: 8, cache_size: 16384 sim_CPI 14.4157 # cycles per instruction Hit latency: 4, assoc: 8, cache_size: 32768 sim_CPI 14.1375 # cycles per instruction --------------------------------------------------------------- dijkstra ------------ Hit latency: 1, assoc: 1, cache_size: 4096 sim_CPI 9.2295 # cycles per instruction Hit latency: 1, assoc: 1, cache_size: 8192 sim_CPI 8.4527 # cycles per instruction Hit latency: 2, assoc: 1, cache_size: 16384 sim_CPI 8.2608 # cycles per instruction Hit latency: 2, assoc: 1, cache_size: 32768 sim_CPI 7.8878 # cycles per instruction --------------------------------------------------------------- Hit latency: 1, assoc: 2, cache_size: 4096 sim_CPI 8.7625 # cycles per instruction Hit latency: 2, assoc: 2, cache_size: 8192 sim_CPI 7.7133 # cycles per instruction Hit latency: 2, assoc: 2, cache_size: 16384 sim_CPI 7.4261 # cycles per instruction Hit latency: 3, assoc: 2, cache_size: 32768 sim_CPI 7.2952 # cycles per instruction --------------------------------------------------------------- Hit latency: 2, assoc: 4, cache_size: 4096 sim_CPI 8.9029 # cycles per instruction Hit latency: 2, assoc: 4, cache_size: 8192 sim_CPI 7.5945 # cycles per instruction Hit latency: 3, assoc: 4, cache_size: 16384 sim_CPI 7.5697 # cycles per instruction Hit latency: 3, assoc: 4, cache_size: 32768 sim_CPI 7.2856 # cycles per instruction --------------------------------------------------------------- Hit latency: 2, assoc: 8, cache_size: 4096 sim_CPI 9.0054 # cycles per instruction Hit latency: 3, assoc: 8, cache_size: 8192 sim_CPI 7.7688 # cycles per instruction Hit latency: 3, assoc: 8, cache_size: 16384 sim_CPI 7.5677 # cycles per instruction Hit latency: 4, assoc: 8, cache_size: 32768 sim_CPI 7.4932 # cycles per instruction ---------------------------------------------------------------