---------- Begin Simulation Statistics ---------- final_tick 27385000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) host_inst_rate 43864 # Simulator instruction rate (inst/s) host_mem_usage 798792 # Number of bytes of host memory used host_op_rate 50104 # Simulator op (including micro ops) rate (op/s) host_seconds 0.13 # Real time elapsed on the host host_tick_rate 205401464 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5839 # Number of instructions simulated sim_ops 6679 # Number of ops (including micro ops) simulated sim_seconds 0.000027 # Number of seconds simulated sim_ticks 27385000 # Number of ticks simulated system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 39.296382 # BTB Hit Percentage system.cpu.branchPred.BTBHits 1184 # Number of BTB hits system.cpu.branchPred.BTBLookups 3013 # Number of BTB lookups system.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions. system.cpu.branchPred.condIncorrect 525 # Number of conditional branches incorrect system.cpu.branchPred.condPredicted 2540 # Number of conditional branches predicted system.cpu.branchPred.indirectHits 14 # Number of indirect target hits. system.cpu.branchPred.indirectLookups 248 # Number of indirect predictor lookups. system.cpu.branchPred.indirectMisses 234 # Number of indirect misses. system.cpu.branchPred.lookups 3798 # Number of BP lookups system.cpu.branchPred.usedRAS 362 # Number of times the RAS was used to get a target. system.cpu.branchPredindirectMispredicted 60 # Number of mispredicted indirect branches. system.cpu.cc_regfile_reads 35754 # number of cc regfile reads system.cpu.cc_regfile_writes 4626 # number of cc regfile writes system.cpu.commit.amos 0 # Number of atomic instructions committed system.cpu.commit.branchMispredicts 373 # The number of times a branch was mispredicted system.cpu.commit.branches 1296 # Number of branches committed system.cpu.commit.bw_lim_events 141 # number cycles where commit BW limit reached system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.commitSquashedInsts 6516 # The number of squashed insts skipped by commit system.cpu.commit.committedInsts 5839 # Number of instructions committed system.cpu.commit.committedOps 6679 # Number of ops (including micro ops) committed system.cpu.commit.committed_per_cycle::samples 12773 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 0.522900 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 1.403280 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::0 10301 80.65% 80.65% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 1015 7.95% 88.59% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 525 4.11% 92.70% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 261 2.04% 94.75% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 117 0.92% 95.66% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 287 2.25% 97.91% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 82 0.64% 98.55% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 44 0.34% 98.90% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 141 1.10% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 12773 # Number of insts commited each cycle system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.function_calls 100 # Number of function calls committed. system.cpu.commit.int_insts 5673 # Number of committed integer instructions. system.cpu.commit.loads 1203 # Number of loads committed system.cpu.commit.membars 12 # Number of memory barriers committed system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction system.cpu.commit.op_class_0::IntAlu 4495 67.30% 67.30% # Class of committed instruction system.cpu.commit.op_class_0::IntMult 4 0.06% 67.36% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 67.36% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 67.36% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 67.36% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 67.36% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 0 0.00% 67.36% # Class of committed instruction system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 67.36% # Class of committed instruction system.cpu.commit.op_class_0::FloatDiv 0 0.00% 67.36% # Class of committed instruction system.cpu.commit.op_class_0::FloatMisc 0 0.00% 67.36% # Class of committed instruction system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 67.36% # Class of committed instruction system.cpu.commit.op_class_0::SimdAdd 0 0.00% 67.36% # Class of committed instruction system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 67.36% # Class of committed instruction system.cpu.commit.op_class_0::SimdAlu 0 0.00% 67.36% # Class of committed instruction system.cpu.commit.op_class_0::SimdCmp 0 0.00% 67.36% # Class of committed instruction system.cpu.commit.op_class_0::SimdCvt 0 0.00% 67.36% # Class of committed instruction system.cpu.commit.op_class_0::SimdMisc 0 0.00% 67.36% # Class of committed instruction system.cpu.commit.op_class_0::SimdMult 0 0.00% 67.36% # Class of committed instruction system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 67.36% # Class of committed instruction system.cpu.commit.op_class_0::SimdShift 0 0.00% 67.36% # Class of committed instruction system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 67.36% # Class of committed instruction system.cpu.commit.op_class_0::SimdDiv 0 0.00% 67.36% # Class of committed instruction system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 67.36% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 67.36% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 67.36% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 67.36% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 67.36% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 67.36% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMisc 3 0.04% 67.41% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 67.41% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.41% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.41% # Class of committed instruction system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 67.41% # Class of committed instruction system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 67.41% # Class of committed instruction system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 67.41% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatReduceAdd 0 0.00% 67.41% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 67.41% # Class of committed instruction system.cpu.commit.op_class_0::SimdAes 0 0.00% 67.41% # Class of committed instruction system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 67.41% # Class of committed instruction system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 67.41% # Class of committed instruction system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 67.41% # Class of committed instruction system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 67.41% # Class of committed instruction system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 67.41% # Class of committed instruction system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 67.41% # Class of committed instruction system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 67.41% # Class of committed instruction system.cpu.commit.op_class_0::SimdPredAlu 0 0.00% 67.41% # Class of committed instruction system.cpu.commit.op_class_0::MemRead 1203 18.01% 85.42% # Class of committed instruction system.cpu.commit.op_class_0::MemWrite 974 14.58% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 6679 # Class of committed instruction system.cpu.commit.refs 2177 # Number of memory references committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.vec_insts 0 # Number of committed Vector instructions. system.cpu.committedInsts 5839 # Number of Instructions Simulated system.cpu.committedOps 6679 # Number of Ops (including micro ops) Simulated system.cpu.cpi 4.690187 # CPI: Cycles Per Instruction system.cpu.cpi_total 4.690187 # CPI: Total CPI of All Threads system.cpu.decode.BlockedCycles 3841 # Number of cycles decode is blocked system.cpu.decode.BranchMispred 165 # Number of times decode detected a branch misprediction system.cpu.decode.BranchResolved 1235 # Number of times decode resolved a branch system.cpu.decode.DecodedInsts 15763 # Number of instructions handled by decode system.cpu.decode.IdleCycles 6710 # Number of cycles decode is idle system.cpu.decode.RunCycles 2758 # Number of cycles decode is running system.cpu.decode.SquashCycles 398 # Number of cycles decode is squashing system.cpu.decode.SquashedInsts 489 # Number of squashed instructions handled by decode system.cpu.decode.UnblockCycles 168 # Number of cycles decode is unblocking system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.inst_accesses 0 # ITB inst accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.dtb.read_accesses 0 # DTB read accesses system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses system.cpu.fetch.Branches 3798 # Number of branches that fetch encountered system.cpu.fetch.CacheLines 2400 # Number of cache lines fetched system.cpu.fetch.Cycles 4886 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.IcacheSquashes 316 # Number of outstanding Icache misses that were squashed system.cpu.fetch.Insts 16020 # Number of instructions fetch has processed system.cpu.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 237 # Number of stall cycles due to pending traps system.cpu.fetch.SquashCycles 1110 # Number of cycles fetch has spent squashing system.cpu.fetch.branchRate 0.138684 # Number of branch fetches per cycle system.cpu.fetch.icacheStallCycles 8192 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.predictedBranches 1560 # Number of branches that fetch has predicted taken system.cpu.fetch.rate 0.584970 # Number of inst fetches per cycle system.cpu.fetch.rateDist::samples 13875 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 1.343207 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 2.668802 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::0 10464 75.42% 75.42% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 339 2.44% 77.86% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 271 1.95% 79.81% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 312 2.25% 82.06% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 328 2.36% 84.43% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::5 402 2.90% 87.32% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::6 178 1.28% 88.61% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::7 218 1.57% 90.18% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::8 1363 9.82% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 13875 # Number of instructions fetched each cycle (Total) system.cpu.idleCycles 13511 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.iew.branchMispredicts 432 # Number of branch mispredicts detected at execute system.cpu.iew.exec_branches 2044 # Number of branches executed system.cpu.iew.exec_nop 0 # number of nop insts executed system.cpu.iew.exec_rate 0.369714 # Inst execution rate system.cpu.iew.exec_refs 3378 # number of memory reference insts executed system.cpu.iew.exec_stores 1192 # Number of stores executed system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.iewBlockCycles 999 # Number of cycles IEW is blocking system.cpu.iew.iewDispLoadInsts 2693 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 32 # Number of dispatched non-speculative instructions system.cpu.iew.iewDispSquashedInsts 193 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispStoreInsts 1631 # Number of dispatched store instructions system.cpu.iew.iewDispatchedInsts 13196 # Number of instructions dispatched to IQ system.cpu.iew.iewExecLoadInsts 2186 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 433 # Number of squashed instructions skipped in execute system.cpu.iew.iewExecutedInsts 10125 # Number of executed instructions system.cpu.iew.iewIQFullEvents 13 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewSquashCycles 398 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 15 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.cacheBlocked 1 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.lsq.thread0.forwLoads 24 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.memOrderViolation 20 # Number of memory ordering violations system.cpu.iew.lsq.thread0.rescheduledLoads 33 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.squashedLoads 1490 # Number of loads squashed system.cpu.iew.lsq.thread0.squashedStores 657 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 20 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 317 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 115 # Number of branches that were predicted taken incorrectly system.cpu.iew.wb_consumers 8892 # num instructions consuming a value system.cpu.iew.wb_count 9644 # cumulative count of insts written-back system.cpu.iew.wb_fanout 0.533063 # average fanout of values written-back system.cpu.iew.wb_producers 4740 # num instructions producing a value system.cpu.iew.wb_rate 0.352151 # insts written-back per cycle system.cpu.iew.wb_sent 9782 # cumulative count of insts sent to commit system.cpu.int_regfile_reads 9927 # number of integer regfile reads system.cpu.int_regfile_writes 5482 # number of integer regfile writes system.cpu.ipc 0.213211 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.213211 # IPC: Total IPC of All Threads system.cpu.iq.FU_type_0::No_OpClass 9 0.09% 0.09% # Type of FU issued system.cpu.iq.FU_type_0::IntAlu 6953 65.86% 65.94% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 7 0.07% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.01% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 66.04% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.04% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.04% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.04% # Type of FU issued system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 66.04% # Type of FU issued system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 66.04% # Type of FU issued system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 66.04% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatReduceAdd 0 0.00% 66.04% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 66.04% # Type of FU issued system.cpu.iq.FU_type_0::SimdAes 0 0.00% 66.04% # Type of FU issued system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 66.04% # Type of FU issued system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 66.04% # Type of FU issued system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 66.04% # Type of FU issued system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 66.04% # Type of FU issued system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 66.04% # Type of FU issued system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 66.04% # Type of FU issued system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 66.04% # Type of FU issued system.cpu.iq.FU_type_0::SimdPredAlu 0 0.00% 66.04% # Type of FU issued system.cpu.iq.FU_type_0::MemRead 2343 22.19% 88.23% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 1243 11.77% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 10558 # Type of FU issued system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu.iq.fu_busy_cnt 245 # FU busy when requested system.cpu.iq.fu_busy_rate 0.023205 # FU busy rate (busy events/executed inst) system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 87 35.51% 35.51% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 35.51% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 35.51% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 35.51% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 35.51% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCvt 0 0.00% 35.51% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMult 0 0.00% 35.51% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 35.51% # attempts to use FU when none available system.cpu.iq.fu_full::FloatDiv 0 0.00% 35.51% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMisc 0 0.00% 35.51% # attempts to use FU when none available system.cpu.iq.fu_full::FloatSqrt 0 0.00% 35.51% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAdd 0 0.00% 35.51% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 35.51% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAlu 0 0.00% 35.51% # attempts to use FU when none available system.cpu.iq.fu_full::SimdCmp 0 0.00% 35.51% # attempts to use FU when none available system.cpu.iq.fu_full::SimdCvt 0 0.00% 35.51% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMisc 0 0.00% 35.51% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMult 0 0.00% 35.51% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 35.51% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShift 0 0.00% 35.51% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 35.51% # attempts to use FU when none available system.cpu.iq.fu_full::SimdDiv 0 0.00% 35.51% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 35.51% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 35.51% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 35.51% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 35.51% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 35.51% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 35.51% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 35.51% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 35.51% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 35.51% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 35.51% # attempts to use FU when none available system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 35.51% # attempts to use FU when none available system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 35.51% # attempts to use FU when none available system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 35.51% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 35.51% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 35.51% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAes 0 0.00% 35.51% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAesMix 0 0.00% 35.51% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 35.51% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 35.51% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 35.51% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 35.51% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 35.51% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 35.51% # attempts to use FU when none available system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 35.51% # attempts to use FU when none available system.cpu.iq.fu_full::MemRead 84 34.29% 69.80% # attempts to use FU when none available system.cpu.iq.fu_full::MemWrite 74 30.20% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.int_alu_accesses 10794 # Number of integer alu accesses system.cpu.iq.int_inst_queue_reads 35298 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_wakeup_accesses 9644 # Number of integer instruction queue wakeup accesses system.cpu.iq.int_inst_queue_writes 19732 # Number of integer instruction queue writes system.cpu.iq.iqInstsAdded 13152 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 10558 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 44 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqSquashedInstsExamined 6516 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedInstsIssued 62 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 7 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedOperandsExamined 15312 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.issued_per_cycle::samples 13875 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 0.760937 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 1.545943 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::0 10069 72.57% 72.57% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::1 1226 8.84% 81.41% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 841 6.06% 87.47% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 582 4.19% 91.66% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 394 2.84% 94.50% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 400 2.88% 97.38% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 234 1.69% 99.07% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 108 0.78% 99.85% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 21 0.15% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::total 13875 # Number of insts issued each cycle system.cpu.iq.rate 0.385525 # Inst issue rate system.cpu.iq.vec_alu_accesses 0 # Number of vector alu accesses system.cpu.iq.vec_inst_queue_reads 0 # Number of vector instruction queue reads system.cpu.iq.vec_inst_queue_wakeup_accesses 0 # Number of vector instruction queue wakeup accesses system.cpu.iq.vec_inst_queue_writes 0 # Number of vector instruction queue writes system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.hits 0 # DTB hits system.cpu.itb.inst_accesses 0 # ITB inst accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.misses 0 # DTB misses system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.write_accesses 0 # DTB write accesses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.memDep0.conflictingLoads 32 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 22 # Number of conflicting stores. system.cpu.memDep0.insertedLoads 2693 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 1631 # Number of stores inserted to the mem dependence unit. system.cpu.misc_regfile_reads 9079 # number of misc regfile reads system.cpu.misc_regfile_writes 46 # number of misc regfile writes system.cpu.numCycles 27386 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.rename.BlockCycles 1058 # Number of cycles rename is blocking system.cpu.rename.CommittedMaps 6929 # Number of HB maps that are committed system.cpu.rename.IQFullEvents 25 # Number of times rename has blocked due to IQ full system.cpu.rename.IdleCycles 6964 # Number of cycles rename is idle system.cpu.rename.LQFullEvents 75 # Number of times rename has blocked due to LQ full system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full system.cpu.rename.RenameLookups 66861 # Number of register rename lookups that rename has made system.cpu.rename.RenamedInsts 14912 # Number of instructions processed by rename system.cpu.rename.RenamedOperands 15541 # Number of destination operands rename has renamed system.cpu.rename.RunCycles 2654 # Number of cycles rename is running system.cpu.rename.SQFullEvents 503 # Number of times rename has blocked due to SQ full system.cpu.rename.SquashCycles 398 # Number of cycles rename is squashing system.cpu.rename.UnblockCycles 637 # Number of cycles rename is unblocking system.cpu.rename.UndoneMaps 8611 # Number of HB maps that are undone due to squashing system.cpu.rename.int_rename_lookups 15938 # Number of integer rename lookups system.cpu.rename.serializeStallCycles 2164 # count of cycles rename stalled for serializing inst system.cpu.rename.serializingInsts 38 # count of serializing insts renamed system.cpu.rename.skidInsts 379 # count of insts added to the skid buffer system.cpu.rename.tempSerializingInsts 33 # count of temporary serializing insts renamed system.cpu.rename.vec_rename_lookups 184 # Number of vector rename lookups system.cpu.rob.rob_reads 25670 # The number of ROB reads system.cpu.rob.rob_writes 27502 # The number of ROB writes system.cpu.timesIdled 201 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.vec_regfile_reads 32 # number of vector regfile reads system.cpu.workload.numSyscalls 13 # Number of system calls system.l2bus.snoop_filter.hit_multi_requests 21 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.l2bus.snoop_filter.hit_single_requests 149 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.tot_requests 586 # Total number of requests made to the snoop filter. system.l2bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.tot_requests 398 # Total number of requests made to the snoop filter. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.pwrStateResidencyTicks::UNDEFINED 27385000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 355 # Transaction distribution system.membus.trans_dist::ReadExReq 42 # Transaction distribution system.membus.trans_dist::ReadExResp 42 # Transaction distribution system.membus.trans_dist::ReadSharedReq 356 # Transaction distribution system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 795 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 795 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 25408 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 25408 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 398 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 398 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 398 # Request fanout histogram system.membus.reqLayer0.occupancy 398000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.5 # Layer utilization (%) system.membus.respLayer0.occupancy 1987000 # Layer occupancy (ticks) system.membus.respLayer0.utilization 7.3 # Layer utilization (%) system.l2bus.pwrStateResidencyTicks::UNDEFINED 27385000 # Cumulative time (in ticks) in various power states system.l2bus.trans_dist::ReadResp 420 # Transaction distribution system.l2bus.trans_dist::CleanEvict 123 # Transaction distribution system.l2bus.trans_dist::ReadExReq 42 # Transaction distribution system.l2bus.trans_dist::ReadExResp 42 # Transaction distribution system.l2bus.trans_dist::ReadSharedReq 421 # Transaction distribution system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 751 # Packet count per connected master and slave (bytes) system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 297 # Packet count per connected master and slave (bytes) system.l2bus.pkt_count::total 1048 # Packet count per connected master and slave (bytes) system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side 20096 # Cumulative packet size per connected master and slave (bytes) system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side 9472 # Cumulative packet size per connected master and slave (bytes) system.l2bus.pkt_size::total 29568 # Cumulative packet size per connected master and slave (bytes) system.l2bus.snoops 0 # Total snoops (count) system.l2bus.snoopTraffic 0 # Total snoop traffic (bytes) system.l2bus.snoop_fanout::samples 463 # Request fanout histogram system.l2bus.snoop_fanout::mean 0.101512 # Request fanout histogram system.l2bus.snoop_fanout::stdev 0.302332 # Request fanout histogram system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.l2bus.snoop_fanout::0 416 89.85% 89.85% # Request fanout histogram system.l2bus.snoop_fanout::1 47 10.15% 100.00% # Request fanout histogram system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram system.l2bus.snoop_fanout::total 463 # Request fanout histogram system.l2bus.respLayer1.occupancy 448995 # Layer occupancy (ticks) system.l2bus.respLayer1.utilization 1.6 # Layer utilization (%) system.l2bus.reqLayer0.occupancy 586000 # Layer occupancy (ticks) system.l2bus.reqLayer0.utilization 2.1 # Layer utilization (%) system.l2bus.respLayer0.occupancy 942000 # Layer occupancy (ticks) system.l2bus.respLayer0.utilization 3.4 # Layer utilization (%) system.clk_domain.clock 1000 # Clock period in ticks system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.cpu.pwrStateResidencyTicks::ON 27385000 # Cumulative time (in ticks) in various power states system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 27385000 # Cumulative time (in ticks) in various power states system.cpu.icache.demand_hits::.cpu.inst 1994 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 1994 # number of demand (read+write) hits system.cpu.icache.overall_hits::.cpu.inst 1994 # number of overall hits system.cpu.icache.overall_hits::total 1994 # number of overall hits system.cpu.icache.demand_misses::.cpu.inst 406 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 406 # number of demand (read+write) misses system.cpu.icache.overall_misses::.cpu.inst 406 # number of overall misses system.cpu.icache.overall_misses::total 406 # number of overall misses system.cpu.icache.demand_miss_latency::.cpu.inst 36750000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 36750000 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::.cpu.inst 36750000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 36750000 # number of overall miss cycles system.cpu.icache.demand_accesses::.cpu.inst 2400 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 2400 # number of demand (read+write) accesses system.cpu.icache.overall_accesses::.cpu.inst 2400 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 2400 # number of overall (read+write) accesses system.cpu.icache.demand_miss_rate::.cpu.inst 0.169167 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.169167 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::.cpu.inst 0.169167 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.169167 # miss rate for overall accesses system.cpu.icache.demand_avg_miss_latency::.cpu.inst 90517.241379 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 90517.241379 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::.cpu.inst 90517.241379 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 90517.241379 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 190 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs 47.500000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.demand_mshr_hits::.cpu.inst 92 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits::total 92 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits::.cpu.inst 92 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 92 # number of overall MSHR hits system.cpu.icache.demand_mshr_misses::.cpu.inst 314 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 314 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::.cpu.inst 314 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 314 # number of overall MSHR misses system.cpu.icache.demand_mshr_miss_latency::.cpu.inst 30708000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 30708000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::.cpu.inst 30708000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 30708000 # number of overall MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate::.cpu.inst 0.130833 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.130833 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::.cpu.inst 0.130833 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.130833 # mshr miss rate for overall accesses system.cpu.icache.demand_avg_mshr_miss_latency::.cpu.inst 97796.178344 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 97796.178344 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::.cpu.inst 97796.178344 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 97796.178344 # average overall mshr miss latency system.cpu.icache.replacements 123 # number of replacements system.cpu.icache.ReadReq_hits::.cpu.inst 1994 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1994 # number of ReadReq hits system.cpu.icache.ReadReq_misses::.cpu.inst 406 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 406 # number of ReadReq misses system.cpu.icache.ReadReq_miss_latency::.cpu.inst 36750000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 36750000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_accesses::.cpu.inst 2400 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 2400 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_miss_rate::.cpu.inst 0.169167 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.169167 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_avg_miss_latency::.cpu.inst 90517.241379 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 90517.241379 # average ReadReq miss latency system.cpu.icache.ReadReq_mshr_hits::.cpu.inst 92 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits::total 92 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_misses::.cpu.inst 314 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 314 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_miss_latency::.cpu.inst 30708000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 30708000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::.cpu.inst 0.130833 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.130833 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::.cpu.inst 97796.178344 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 97796.178344 # average ReadReq mshr miss latency system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 27385000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.tagsinuse 112.602961 # Cycle average of tags in use system.cpu.icache.tags.total_refs 2308 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 314 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 7.350318 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 108000 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::.cpu.inst 112.602961 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::.cpu.inst 0.439855 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.439855 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 191 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 114 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 77 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.746094 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 5114 # Number of tag accesses system.cpu.icache.tags.data_accesses 5114 # Number of data accesses system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 27385000 # Cumulative time (in ticks) in various power states system.cpu.dtb.stage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 27385000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 27385000 # Cumulative time (in ticks) in various power states system.cpu.itb.stage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 27385000 # Cumulative time (in ticks) in various power states system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 27385000 # Cumulative time (in ticks) in various power states system.cpu.dcache.demand_hits::.cpu.data 2525 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 2525 # number of demand (read+write) hits system.cpu.dcache.overall_hits::.cpu.data 2525 # number of overall hits system.cpu.dcache.overall_hits::total 2525 # number of overall hits system.cpu.dcache.demand_misses::.cpu.data 490 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 490 # number of demand (read+write) misses system.cpu.dcache.overall_misses::.cpu.data 490 # number of overall misses system.cpu.dcache.overall_misses::total 490 # number of overall misses system.cpu.dcache.demand_miss_latency::.cpu.data 45762000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 45762000 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::.cpu.data 45762000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 45762000 # number of overall miss cycles system.cpu.dcache.demand_accesses::.cpu.data 3015 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 3015 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::.cpu.data 3015 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 3015 # number of overall (read+write) accesses system.cpu.dcache.demand_miss_rate::.cpu.data 0.162521 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.162521 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::.cpu.data 0.162521 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.162521 # miss rate for overall accesses system.cpu.dcache.demand_avg_miss_latency::.cpu.data 93391.836735 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 93391.836735 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::.cpu.data 93391.836735 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 93391.836735 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 146 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 36.500000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.demand_mshr_hits::.cpu.data 341 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 341 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::.cpu.data 341 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 341 # number of overall MSHR hits system.cpu.dcache.demand_mshr_misses::.cpu.data 149 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 149 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::.cpu.data 149 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 149 # number of overall MSHR misses system.cpu.dcache.demand_mshr_miss_latency::.cpu.data 15131000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 15131000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::.cpu.data 15131000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 15131000 # number of overall MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate::.cpu.data 0.049420 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.049420 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::.cpu.data 0.049420 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.049420 # mshr miss rate for overall accesses system.cpu.dcache.demand_avg_mshr_miss_latency::.cpu.data 101550.335570 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 101550.335570 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::.cpu.data 101550.335570 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 101550.335570 # average overall mshr miss latency system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.ReadReq_hits::.cpu.data 1845 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1845 # number of ReadReq hits system.cpu.dcache.ReadReq_misses::.cpu.data 221 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 221 # number of ReadReq misses system.cpu.dcache.ReadReq_miss_latency::.cpu.data 18479000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 18479000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_accesses::.cpu.data 2066 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 2066 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_miss_rate::.cpu.data 0.106970 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.106970 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_avg_miss_latency::.cpu.data 83615.384615 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 83615.384615 # average ReadReq miss latency system.cpu.dcache.ReadReq_mshr_hits::.cpu.data 114 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 114 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_misses::.cpu.data 107 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 107 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::.cpu.data 10083000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 10083000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data 0.051791 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.051791 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 94233.644860 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 94233.644860 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_hits::.cpu.data 680 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 680 # number of WriteReq hits system.cpu.dcache.WriteReq_misses::.cpu.data 269 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 269 # number of WriteReq misses system.cpu.dcache.WriteReq_miss_latency::.cpu.data 27283000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 27283000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_accesses::.cpu.data 949 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 949 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.283456 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.283456 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 101423.791822 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 101423.791822 # average WriteReq miss latency system.cpu.dcache.WriteReq_mshr_hits::.cpu.data 227 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 227 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_misses::.cpu.data 42 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 5048000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 5048000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.044257 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044257 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 120190.476190 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 120190.476190 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_hits::.cpu.data 10 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_misses::.cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_miss_latency::.cpu.data 219000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 219000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 12 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 12 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_miss_rate::.cpu.data 0.166667 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_avg_miss_latency::.cpu.data 109500 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 109500 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_mshr_hits::.cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.StoreCondReq_hits::.cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_accesses::.cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 27385000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.tagsinuse 89.149391 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 2694 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 148 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 18.202703 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 142000 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::.cpu.data 89.149391 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::.cpu.data 0.087060 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.087060 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 148 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 110 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.144531 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 6224 # Number of tag accesses system.cpu.dcache.tags.data_accesses 6224 # Number of data accesses system.l2cache.pwrStateResidencyTicks::UNDEFINED 27385000 # Cumulative time (in ticks) in various power states system.l2cache.demand_hits::.cpu.inst 40 # number of demand (read+write) hits system.l2cache.demand_hits::.cpu.data 20 # number of demand (read+write) hits system.l2cache.demand_hits::total 60 # number of demand (read+write) hits system.l2cache.overall_hits::.cpu.inst 40 # number of overall hits system.l2cache.overall_hits::.cpu.data 20 # number of overall hits system.l2cache.overall_hits::total 60 # number of overall hits system.l2cache.demand_misses::.cpu.inst 274 # number of demand (read+write) misses system.l2cache.demand_misses::.cpu.data 129 # number of demand (read+write) misses system.l2cache.demand_misses::total 403 # number of demand (read+write) misses system.l2cache.overall_misses::.cpu.inst 274 # number of overall misses system.l2cache.overall_misses::.cpu.data 129 # number of overall misses system.l2cache.overall_misses::total 403 # number of overall misses system.l2cache.demand_miss_latency::.cpu.inst 28870000 # number of demand (read+write) miss cycles system.l2cache.demand_miss_latency::.cpu.data 14218000 # number of demand (read+write) miss cycles system.l2cache.demand_miss_latency::total 43088000 # number of demand (read+write) miss cycles system.l2cache.overall_miss_latency::.cpu.inst 28870000 # number of overall miss cycles system.l2cache.overall_miss_latency::.cpu.data 14218000 # number of overall miss cycles system.l2cache.overall_miss_latency::total 43088000 # number of overall miss cycles system.l2cache.demand_accesses::.cpu.inst 314 # number of demand (read+write) accesses system.l2cache.demand_accesses::.cpu.data 149 # number of demand (read+write) accesses system.l2cache.demand_accesses::total 463 # number of demand (read+write) accesses system.l2cache.overall_accesses::.cpu.inst 314 # number of overall (read+write) accesses system.l2cache.overall_accesses::.cpu.data 149 # number of overall (read+write) accesses system.l2cache.overall_accesses::total 463 # number of overall (read+write) accesses system.l2cache.demand_miss_rate::.cpu.inst 0.872611 # miss rate for demand accesses system.l2cache.demand_miss_rate::.cpu.data 0.865772 # miss rate for demand accesses system.l2cache.demand_miss_rate::total 0.870410 # miss rate for demand accesses system.l2cache.overall_miss_rate::.cpu.inst 0.872611 # miss rate for overall accesses system.l2cache.overall_miss_rate::.cpu.data 0.865772 # miss rate for overall accesses system.l2cache.overall_miss_rate::total 0.870410 # miss rate for overall accesses system.l2cache.demand_avg_miss_latency::.cpu.inst 105364.963504 # average overall miss latency system.l2cache.demand_avg_miss_latency::.cpu.data 110217.054264 # average overall miss latency system.l2cache.demand_avg_miss_latency::total 106918.114144 # average overall miss latency system.l2cache.overall_avg_miss_latency::.cpu.inst 105364.963504 # average overall miss latency system.l2cache.overall_avg_miss_latency::.cpu.data 110217.054264 # average overall miss latency system.l2cache.overall_avg_miss_latency::total 106918.114144 # average overall miss latency system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2cache.demand_mshr_hits::.cpu.data 5 # number of demand (read+write) MSHR hits system.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits system.l2cache.overall_mshr_hits::.cpu.data 5 # number of overall MSHR hits system.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits system.l2cache.demand_mshr_misses::.cpu.inst 274 # number of demand (read+write) MSHR misses system.l2cache.demand_mshr_misses::.cpu.data 124 # number of demand (read+write) MSHR misses system.l2cache.demand_mshr_misses::total 398 # number of demand (read+write) MSHR misses system.l2cache.overall_mshr_misses::.cpu.inst 274 # number of overall MSHR misses system.l2cache.overall_mshr_misses::.cpu.data 124 # number of overall MSHR misses system.l2cache.overall_mshr_misses::total 398 # number of overall MSHR misses system.l2cache.demand_mshr_miss_latency::.cpu.inst 23390000 # number of demand (read+write) MSHR miss cycles system.l2cache.demand_mshr_miss_latency::.cpu.data 11303000 # number of demand (read+write) MSHR miss cycles system.l2cache.demand_mshr_miss_latency::total 34693000 # number of demand (read+write) MSHR miss cycles system.l2cache.overall_mshr_miss_latency::.cpu.inst 23390000 # number of overall MSHR miss cycles system.l2cache.overall_mshr_miss_latency::.cpu.data 11303000 # number of overall MSHR miss cycles system.l2cache.overall_mshr_miss_latency::total 34693000 # number of overall MSHR miss cycles system.l2cache.demand_mshr_miss_rate::.cpu.inst 0.872611 # mshr miss rate for demand accesses system.l2cache.demand_mshr_miss_rate::.cpu.data 0.832215 # mshr miss rate for demand accesses system.l2cache.demand_mshr_miss_rate::total 0.859611 # mshr miss rate for demand accesses system.l2cache.overall_mshr_miss_rate::.cpu.inst 0.872611 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::.cpu.data 0.832215 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::total 0.859611 # mshr miss rate for overall accesses system.l2cache.demand_avg_mshr_miss_latency::.cpu.inst 85364.963504 # average overall mshr miss latency system.l2cache.demand_avg_mshr_miss_latency::.cpu.data 91153.225806 # average overall mshr miss latency system.l2cache.demand_avg_mshr_miss_latency::total 87168.341709 # average overall mshr miss latency system.l2cache.overall_avg_mshr_miss_latency::.cpu.inst 85364.963504 # average overall mshr miss latency system.l2cache.overall_avg_mshr_miss_latency::.cpu.data 91153.225806 # average overall mshr miss latency system.l2cache.overall_avg_mshr_miss_latency::total 87168.341709 # average overall mshr miss latency system.l2cache.replacements 0 # number of replacements system.l2cache.ReadExReq_misses::.cpu.data 42 # number of ReadExReq misses system.l2cache.ReadExReq_misses::total 42 # number of ReadExReq misses system.l2cache.ReadExReq_miss_latency::.cpu.data 4920000 # number of ReadExReq miss cycles system.l2cache.ReadExReq_miss_latency::total 4920000 # number of ReadExReq miss cycles system.l2cache.ReadExReq_accesses::.cpu.data 42 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadExReq_accesses::total 42 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadExReq_miss_rate::.cpu.data 1 # miss rate for ReadExReq accesses system.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.l2cache.ReadExReq_avg_miss_latency::.cpu.data 117142.857143 # average ReadExReq miss latency system.l2cache.ReadExReq_avg_miss_latency::total 117142.857143 # average ReadExReq miss latency system.l2cache.ReadExReq_mshr_misses::.cpu.data 42 # number of ReadExReq MSHR misses system.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses system.l2cache.ReadExReq_mshr_miss_latency::.cpu.data 4080000 # number of ReadExReq MSHR miss cycles system.l2cache.ReadExReq_mshr_miss_latency::total 4080000 # number of ReadExReq MSHR miss cycles system.l2cache.ReadExReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.l2cache.ReadExReq_avg_mshr_miss_latency::.cpu.data 97142.857143 # average ReadExReq mshr miss latency system.l2cache.ReadExReq_avg_mshr_miss_latency::total 97142.857143 # average ReadExReq mshr miss latency system.l2cache.ReadSharedReq_hits::.cpu.inst 40 # number of ReadSharedReq hits system.l2cache.ReadSharedReq_hits::.cpu.data 20 # number of ReadSharedReq hits system.l2cache.ReadSharedReq_hits::total 60 # number of ReadSharedReq hits system.l2cache.ReadSharedReq_misses::.cpu.inst 274 # number of ReadSharedReq misses system.l2cache.ReadSharedReq_misses::.cpu.data 87 # number of ReadSharedReq misses system.l2cache.ReadSharedReq_misses::total 361 # number of ReadSharedReq misses system.l2cache.ReadSharedReq_miss_latency::.cpu.inst 28870000 # number of ReadSharedReq miss cycles system.l2cache.ReadSharedReq_miss_latency::.cpu.data 9298000 # number of ReadSharedReq miss cycles system.l2cache.ReadSharedReq_miss_latency::total 38168000 # number of ReadSharedReq miss cycles system.l2cache.ReadSharedReq_accesses::.cpu.inst 314 # number of ReadSharedReq accesses(hits+misses) system.l2cache.ReadSharedReq_accesses::.cpu.data 107 # number of ReadSharedReq accesses(hits+misses) system.l2cache.ReadSharedReq_accesses::total 421 # number of ReadSharedReq accesses(hits+misses) system.l2cache.ReadSharedReq_miss_rate::.cpu.inst 0.872611 # miss rate for ReadSharedReq accesses system.l2cache.ReadSharedReq_miss_rate::.cpu.data 0.813084 # miss rate for ReadSharedReq accesses system.l2cache.ReadSharedReq_miss_rate::total 0.857482 # miss rate for ReadSharedReq accesses system.l2cache.ReadSharedReq_avg_miss_latency::.cpu.inst 105364.963504 # average ReadSharedReq miss latency system.l2cache.ReadSharedReq_avg_miss_latency::.cpu.data 106873.563218 # average ReadSharedReq miss latency system.l2cache.ReadSharedReq_avg_miss_latency::total 105728.531856 # average ReadSharedReq miss latency system.l2cache.ReadSharedReq_mshr_hits::.cpu.data 5 # number of ReadSharedReq MSHR hits system.l2cache.ReadSharedReq_mshr_hits::total 5 # number of ReadSharedReq MSHR hits system.l2cache.ReadSharedReq_mshr_misses::.cpu.inst 274 # number of ReadSharedReq MSHR misses system.l2cache.ReadSharedReq_mshr_misses::.cpu.data 82 # number of ReadSharedReq MSHR misses system.l2cache.ReadSharedReq_mshr_misses::total 356 # number of ReadSharedReq MSHR misses system.l2cache.ReadSharedReq_mshr_miss_latency::.cpu.inst 23390000 # number of ReadSharedReq MSHR miss cycles system.l2cache.ReadSharedReq_mshr_miss_latency::.cpu.data 7223000 # number of ReadSharedReq MSHR miss cycles system.l2cache.ReadSharedReq_mshr_miss_latency::total 30613000 # number of ReadSharedReq MSHR miss cycles system.l2cache.ReadSharedReq_mshr_miss_rate::.cpu.inst 0.872611 # mshr miss rate for ReadSharedReq accesses system.l2cache.ReadSharedReq_mshr_miss_rate::.cpu.data 0.766355 # mshr miss rate for ReadSharedReq accesses system.l2cache.ReadSharedReq_mshr_miss_rate::total 0.845606 # mshr miss rate for ReadSharedReq accesses system.l2cache.ReadSharedReq_avg_mshr_miss_latency::.cpu.inst 85364.963504 # average ReadSharedReq mshr miss latency system.l2cache.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 88085.365854 # average ReadSharedReq mshr miss latency system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 85991.573034 # average ReadSharedReq mshr miss latency system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 27385000 # Cumulative time (in ticks) in various power states system.l2cache.tags.tagsinuse 216.095789 # Cycle average of tags in use system.l2cache.tags.total_refs 559 # Total number of references to valid blocks. system.l2cache.tags.sampled_refs 397 # Sample count of references to valid blocks. system.l2cache.tags.avg_refs 1.408060 # Average number of references to valid blocks. system.l2cache.tags.warmup_cycle 87000 # Cycle when the warmup percentage was hit. system.l2cache.tags.occ_blocks::.cpu.inst 139.234842 # Average occupied blocks per requestor system.l2cache.tags.occ_blocks::.cpu.data 76.860947 # Average occupied blocks per requestor system.l2cache.tags.occ_percent::.cpu.inst 0.033993 # Average percentage of cache occupancy system.l2cache.tags.occ_percent::.cpu.data 0.018765 # Average percentage of cache occupancy system.l2cache.tags.occ_percent::total 0.052758 # Average percentage of cache occupancy system.l2cache.tags.occ_task_id_blocks::1024 397 # Occupied blocks per task id system.l2cache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id system.l2cache.tags.age_task_id_blocks_1024::1 267 # Occupied blocks per task id system.l2cache.tags.occ_task_id_percent::1024 0.096924 # Percentage of cache occupancy per task id system.l2cache.tags.tag_accesses 4917 # Number of tag accesses system.l2cache.tags.data_accesses 4917 # Number of data accesses system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 27385000 # Cumulative time (in ticks) in various power states system.mem_ctrl.bytes_read::.cpu.inst 17536 # Number of bytes read from this memory system.mem_ctrl.bytes_read::.cpu.data 7872 # Number of bytes read from this memory system.mem_ctrl.bytes_read::total 25408 # Number of bytes read from this memory system.mem_ctrl.bytes_inst_read::.cpu.inst 17536 # Number of instructions bytes read from this memory system.mem_ctrl.bytes_inst_read::total 17536 # Number of instructions bytes read from this memory system.mem_ctrl.num_reads::.cpu.inst 274 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::.cpu.data 123 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::total 397 # Number of read requests responded to by this memory system.mem_ctrl.bw_read::.cpu.inst 640350557 # Total read bandwidth from this memory (bytes/s) system.mem_ctrl.bw_read::.cpu.data 287456637 # Total read bandwidth from this memory (bytes/s) system.mem_ctrl.bw_read::total 927807194 # Total read bandwidth from this memory (bytes/s) system.mem_ctrl.bw_inst_read::.cpu.inst 640350557 # Instruction read bandwidth from this memory (bytes/s) system.mem_ctrl.bw_inst_read::total 640350557 # Instruction read bandwidth from this memory (bytes/s) system.mem_ctrl.bw_total::.cpu.inst 640350557 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.bw_total::.cpu.data 287456637 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.bw_total::total 927807194 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.avgPriority_.cpu.inst::samples 274.00 # Average QoS priority value for accepted requests system.mem_ctrl.avgPriority_.cpu.data::samples 124.00 # Average QoS priority value for accepted requests system.mem_ctrl.priorityMinLatency 0.000000019000 # per QoS priority minimum request to response latency (s) system.mem_ctrl.priorityMaxLatency 0.000000370000 # per QoS priority maximum request to response latency (s) system.mem_ctrl.numReadWriteTurnArounds 0 # Number of turnarounds from READ to WRITE system.mem_ctrl.numWriteReadTurnArounds 0 # Number of turnarounds from WRITE to READ system.mem_ctrl.numStayReadState 782 # Number of times bus staying in READ state system.mem_ctrl.numStayWriteState 0 # Number of times bus staying in WRITE state system.mem_ctrl.readReqs 398 # Number of read requests accepted system.mem_ctrl.writeReqs 0 # Number of write requests accepted system.mem_ctrl.readBursts 398 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrl.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue system.mem_ctrl.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.mem_ctrl.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.mem_ctrl.perBankRdBursts::0 64 # Per bank write bursts system.mem_ctrl.perBankRdBursts::1 57 # Per bank write bursts system.mem_ctrl.perBankRdBursts::2 47 # Per bank write bursts system.mem_ctrl.perBankRdBursts::3 36 # Per bank write bursts system.mem_ctrl.perBankRdBursts::4 73 # Per bank write bursts system.mem_ctrl.perBankRdBursts::5 73 # Per bank write bursts system.mem_ctrl.perBankRdBursts::6 21 # Per bank write bursts system.mem_ctrl.perBankRdBursts::7 27 # Per bank write bursts system.mem_ctrl.perBankWrBursts::0 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::4 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::5 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts system.mem_ctrl.perBankWrBursts::7 0 # Per bank write bursts system.mem_ctrl.avgRdQLen 1.68 # Average read queue length when enqueuing system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing system.mem_ctrl.totQLat 6945500 # Total ticks spent queuing system.mem_ctrl.totBusLat 1592000 # Total ticks spent in databus transfers system.mem_ctrl.totMemAccLat 14507500 # Total ticks spent from burst creation until serviced by the DRAM system.mem_ctrl.avgQLat 17451.01 # Average queueing delay per DRAM burst system.mem_ctrl.avgBusLat 4000.00 # Average bus latency per DRAM burst system.mem_ctrl.avgMemAccLat 36451.01 # Average memory access latency per DRAM burst system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry system.mem_ctrl.readRowHits 251 # Number of row buffer hits during reads system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes system.mem_ctrl.readRowHitRate 63.07 # Row buffer hit rate for reads system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::3 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::6 398 # Read request sizes (log2) system.mem_ctrl.writePktSize::0 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::1 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::2 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::3 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) system.mem_ctrl.rdQLenPdf::0 229 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::1 113 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::2 41 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::3 12 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::4 2 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::5 1 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::6 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::7 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::8 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::9 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::10 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::11 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::12 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::13 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::14 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::15 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::16 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::17 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::18 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::19 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::20 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::21 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::22 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::23 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::24 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::25 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::26 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::27 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::28 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::29 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::30 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::31 0 # What read queue length does an incoming req see system.mem_ctrl.wrQLenPdf::0 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::1 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::2 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::3 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::4 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::5 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::6 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::7 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::8 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::9 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::10 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::11 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::12 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::13 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::14 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::15 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::16 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::17 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::18 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::19 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::20 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::21 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::22 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::23 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::24 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::25 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::26 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::27 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::28 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::29 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::30 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::31 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::32 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::33 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::34 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::36 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::37 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::38 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::39 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::40 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::41 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::42 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::43 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::44 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::45 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::46 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::47 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::48 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::49 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::50 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::51 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::52 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::53 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::54 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::55 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see system.mem_ctrl.bytesPerActivate::samples 146 # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::mean 174.027397 # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::gmean 123.589833 # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::stdev 176.074120 # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::0-127 73 50.00% 50.00% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::128-255 38 26.03% 76.03% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::256-383 17 11.64% 87.67% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::384-511 9 6.16% 93.84% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::512-639 3 2.05% 95.89% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::640-767 2 1.37% 97.26% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::768-895 2 1.37% 98.63% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::896-1023 1 0.68% 99.32% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::1024-1151 1 0.68% 100.00% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::total 146 # Bytes accessed per row activation system.mem_ctrl.bytesReadDRAM 25472 # Total number of bytes read from DRAM system.mem_ctrl.bytesReadWrQ 0 # Total number of bytes read from write queue system.mem_ctrl.bytesWritten 0 # Total number of bytes written to DRAM system.mem_ctrl.bytesReadSys 25472 # Total read bytes from the system interface side system.mem_ctrl.bytesWrittenSys 0 # Total written bytes from the system interface side system.mem_ctrl.avgRdBW 930.14 # Average DRAM read bandwidth in MiByte/s system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s system.mem_ctrl.avgRdBWSys 930.14 # Average system read bandwidth in MiByte/s system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.mem_ctrl.peakBW 16000.00 # Theoretical peak bandwidth in MiByte/s system.mem_ctrl.busUtil 5.81 # Data bus utilization in percentage system.mem_ctrl.busUtilRead 5.81 # Data bus utilization in percentage for reads system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.mem_ctrl.totGap 27214000 # Total gap between requests system.mem_ctrl.avgGap 68376.88 # Average gap between requests system.mem_ctrl.masterReadBytes::.cpu.inst 17536 # Per-master bytes read from memory system.mem_ctrl.masterReadBytes::.cpu.data 7936 # Per-master bytes read from memory system.mem_ctrl.masterReadRate::.cpu.inst 640350556.874201178551 # Per-master bytes read from memory rate (Bytes/sec) system.mem_ctrl.masterReadRate::.cpu.data 289793682.672996163368 # Per-master bytes read from memory rate (Bytes/sec) system.mem_ctrl.masterReadAccesses::.cpu.inst 274 # Per-master read serviced memory accesses system.mem_ctrl.masterReadAccesses::.cpu.data 124 # Per-master read serviced memory accesses system.mem_ctrl.masterReadTotalLat::.cpu.inst 9384500 # Per-master read total memory access latency system.mem_ctrl.masterReadTotalLat::.cpu.data 5123000 # Per-master read total memory access latency system.mem_ctrl.masterReadAvgLat::.cpu.inst 34250.00 # Per-master read average memory access latency system.mem_ctrl.masterReadAvgLat::.cpu.data 41314.52 # Per-master read average memory access latency system.mem_ctrl.pageHitRate 63.07 # Row buffer hit rate, read and write combined system.mem_ctrl.rank0.actEnergy 0 # Energy for activate commands per rank (pJ) system.mem_ctrl.rank0.preEnergy 0 # Energy for precharge commands per rank (pJ) system.mem_ctrl.rank0.readEnergy 0 # Energy for read commands per rank (pJ) system.mem_ctrl.rank0.writeEnergy 0 # Energy for write commands per rank (pJ) system.mem_ctrl.rank0.refreshEnergy 0 # Energy for refresh commands per rank (pJ) system.mem_ctrl.rank0.actBackEnergy 0 # Energy for active background per rank (pJ) system.mem_ctrl.rank0.preBackEnergy 0 # Energy for precharge background per rank (pJ) system.mem_ctrl.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) system.mem_ctrl.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) system.mem_ctrl.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) system.mem_ctrl.rank0.totalEnergy 0 # Total energy per rank (pJ) system.mem_ctrl.rank0.averagePower 0 # Core power per rank (mW) system.mem_ctrl.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank system.mem_ctrl.rank0.memoryStateTime::IDLE 463000 # Time in different power states system.mem_ctrl.rank0.memoryStateTime::REF 1120000 # Time in different power states system.mem_ctrl.rank0.memoryStateTime::SREF 0 # Time in different power states system.mem_ctrl.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrl.rank0.memoryStateTime::ACT 25802000 # Time in different power states system.mem_ctrl.rank0.memoryStateTime::ACT_PDN 0 # Time in different power states ---------- End Simulation Statistics ----------