---------- Begin Simulation Statistics ---------- final_tick 53378704000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) host_inst_rate 1081100 # Simulator instruction rate (inst/s) host_mem_usage 803604 # Number of bytes of host memory used host_op_rate 1083927 # Simulator op (including micro ops) rate (op/s) host_seconds 15.09 # Real time elapsed on the host host_tick_rate 3537202549 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 16314370 # Number of instructions simulated sim_ops 16357154 # Number of ops (including micro ops) simulated sim_seconds 0.053379 # Number of seconds simulated sim_ticks 53378704000 # Number of ticks simulated system.cpu.Branches 2258110 # Number of branches fetched system.cpu.committedInsts 16314370 # Number of instructions committed system.cpu.committedOps 16357154 # Number of ops (including micro ops) committed system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.inst_accesses 0 # ITB inst accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.dtb.read_accesses 0 # DTB read accesses system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses system.cpu.idle_fraction 0.000000 # Percentage of idle cycles system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.hits 0 # DTB hits system.cpu.itb.inst_accesses 0 # ITB inst accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.misses 0 # DTB misses system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.write_accesses 0 # DTB write accesses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.numCycles 53378704 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.num_busy_cycles 53378703.999000 # Number of busy cycles system.cpu.num_cc_register_reads 6755100 # number of times the CC registers were read system.cpu.num_cc_register_writes 6787058 # number of times the CC registers were written system.cpu.num_conditional_control_insts 2254498 # number of instructions that are conditional controls system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses system.cpu.num_fp_insts 0 # number of float instructions system.cpu.num_fp_register_reads 0 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written system.cpu.num_func_calls 3056 # number of times a function call or return occured system.cpu.num_idle_cycles 0.001000 # Number of idle cycles system.cpu.num_int_alu_accesses 11779415 # Number of integer alu accesses system.cpu.num_int_insts 11779415 # number of integer instructions system.cpu.num_int_register_reads 38764913 # number of times the integer registers were read system.cpu.num_int_register_writes 7538917 # number of times the integer registers were written system.cpu.num_load_insts 4354133 # Number of load instructions system.cpu.num_mem_refs 6575954 # number of memory refs system.cpu.num_store_insts 2221821 # Number of store instructions system.cpu.num_vec_alu_accesses 8798345 # Number of vector alu accesses system.cpu.num_vec_insts 8798345 # number of vector instructions system.cpu.num_vec_register_reads 8814729 # number of times the vector registers were read system.cpu.num_vec_register_writes 6635550 # number of times the vector registers were written system.cpu.op_class::No_OpClass 1 0.00% 0.00% # Class of executed instruction system.cpu.op_class::IntAlu 7258038 44.37% 44.37% # Class of executed instruction system.cpu.op_class::IntMult 131097 0.80% 45.17% # Class of executed instruction system.cpu.op_class::IntDiv 3 0.00% 45.17% # Class of executed instruction system.cpu.op_class::FloatAdd 32768 0.20% 45.37% # Class of executed instruction system.cpu.op_class::FloatCmp 32768 0.20% 45.57% # Class of executed instruction system.cpu.op_class::FloatCvt 65536 0.40% 45.97% # Class of executed instruction system.cpu.op_class::FloatMult 0 0.00% 45.97% # Class of executed instruction system.cpu.op_class::FloatMultAcc 2162688 13.22% 59.20% # Class of executed instruction system.cpu.op_class::FloatDiv 32768 0.20% 59.40% # Class of executed instruction system.cpu.op_class::FloatMisc 32772 0.20% 59.60% # Class of executed instruction system.cpu.op_class::FloatSqrt 0 0.00% 59.60% # Class of executed instruction system.cpu.op_class::SimdAdd 5 0.00% 59.60% # Class of executed instruction system.cpu.op_class::SimdAddAcc 0 0.00% 59.60% # Class of executed instruction system.cpu.op_class::SimdAlu 4 0.00% 59.60% # Class of executed instruction system.cpu.op_class::SimdCmp 4 0.00% 59.60% # Class of executed instruction system.cpu.op_class::SimdCvt 0 0.00% 59.60% # Class of executed instruction system.cpu.op_class::SimdMisc 32775 0.20% 59.80% # Class of executed instruction system.cpu.op_class::SimdMult 0 0.00% 59.80% # Class of executed instruction system.cpu.op_class::SimdMultAcc 0 0.00% 59.80% # Class of executed instruction system.cpu.op_class::SimdShift 0 0.00% 59.80% # Class of executed instruction system.cpu.op_class::SimdShiftAcc 0 0.00% 59.80% # Class of executed instruction system.cpu.op_class::SimdDiv 0 0.00% 59.80% # Class of executed instruction system.cpu.op_class::SimdSqrt 0 0.00% 59.80% # Class of executed instruction system.cpu.op_class::SimdFloatAdd 0 0.00% 59.80% # Class of executed instruction system.cpu.op_class::SimdFloatAlu 0 0.00% 59.80% # Class of executed instruction system.cpu.op_class::SimdFloatCmp 0 0.00% 59.80% # Class of executed instruction system.cpu.op_class::SimdFloatCvt 0 0.00% 59.80% # Class of executed instruction system.cpu.op_class::SimdFloatDiv 0 0.00% 59.80% # Class of executed instruction system.cpu.op_class::SimdFloatMisc 0 0.00% 59.80% # Class of executed instruction system.cpu.op_class::SimdFloatMult 0 0.00% 59.80% # Class of executed instruction system.cpu.op_class::SimdFloatMultAcc 0 0.00% 59.80% # Class of executed instruction system.cpu.op_class::SimdFloatSqrt 0 0.00% 59.80% # Class of executed instruction system.cpu.op_class::SimdReduceAdd 0 0.00% 59.80% # Class of executed instruction system.cpu.op_class::SimdReduceAlu 0 0.00% 59.80% # Class of executed instruction system.cpu.op_class::SimdReduceCmp 0 0.00% 59.80% # Class of executed instruction system.cpu.op_class::SimdFloatReduceAdd 0 0.00% 59.80% # Class of executed instruction system.cpu.op_class::SimdFloatReduceCmp 0 0.00% 59.80% # Class of executed instruction system.cpu.op_class::SimdAes 0 0.00% 59.80% # Class of executed instruction system.cpu.op_class::SimdAesMix 0 0.00% 59.80% # Class of executed instruction system.cpu.op_class::SimdSha1Hash 0 0.00% 59.80% # Class of executed instruction system.cpu.op_class::SimdSha1Hash2 0 0.00% 59.80% # Class of executed instruction system.cpu.op_class::SimdSha256Hash 0 0.00% 59.80% # Class of executed instruction system.cpu.op_class::SimdSha256Hash2 0 0.00% 59.80% # Class of executed instruction system.cpu.op_class::SimdShaSigma2 0 0.00% 59.80% # Class of executed instruction system.cpu.op_class::SimdShaSigma3 0 0.00% 59.80% # Class of executed instruction system.cpu.op_class::SimdPredAlu 0 0.00% 59.80% # Class of executed instruction system.cpu.op_class::MemRead 4354133 26.62% 86.42% # Class of executed instruction system.cpu.op_class::MemWrite 2221821 13.58% 100.00% # Class of executed instruction system.cpu.op_class::FloatMemRead 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::total 16357181 # Class of executed instruction system.cpu.workload.numSyscalls 26 # Number of system calls system.l2bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.l2bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.l2bus.snoop_filter.hit_single_requests 277120 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.hit_single_snoops 295 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.l2bus.snoop_filter.tot_requests 555519 # Total number of requests made to the snoop filter. system.l2bus.snoop_filter.tot_snoops 295 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.hit_single_requests 7591 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.tot_requests 19462 # Total number of requests made to the snoop filter. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.pwrStateResidencyTicks::UNDEFINED 53378704000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 5451 # Transaction distribution system.membus.trans_dist::WritebackDirty 5660 # Transaction distribution system.membus.trans_dist::CleanEvict 1931 # Transaction distribution system.membus.trans_dist::ReadExReq 6412 # Transaction distribution system.membus.trans_dist::ReadExResp 6412 # Transaction distribution system.membus.trans_dist::ReadSharedReq 5451 # Transaction distribution system.membus.trans_dist::InvalidateReq 8 # Transaction distribution system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 31325 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 31325 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 1121472 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 1121472 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 11871 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 11871 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 11871 # Request fanout histogram system.membus.reqLayer0.occupancy 42102000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.respLayer0.occupancy 63013750 # Layer occupancy (ticks) system.membus.respLayer0.utilization 0.1 # Layer utilization (%) system.l2bus.pwrStateResidencyTicks::UNDEFINED 53378704000 # Cumulative time (in ticks) in various power states system.l2bus.trans_dist::ReadResp 267862 # Transaction distribution system.l2bus.trans_dist::WritebackDirty 215969 # Transaction distribution system.l2bus.trans_dist::CleanEvict 68927 # Transaction distribution system.l2bus.trans_dist::ReadExReq 10529 # Transaction distribution system.l2bus.trans_dist::ReadExResp 10529 # Transaction distribution system.l2bus.trans_dist::ReadSharedReq 267862 # Transaction distribution system.l2bus.trans_dist::InvalidateReq 8 # Transaction distribution system.l2bus.trans_dist::InvalidateResp 8 # Transaction distribution system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 2952 # Packet count per connected master and slave (bytes) system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 830966 # Packet count per connected master and slave (bytes) system.l2bus.pkt_count::total 833918 # Packet count per connected master and slave (bytes) system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side 68416 # Cumulative packet size per connected master and slave (bytes) system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side 31208384 # Cumulative packet size per connected master and slave (bytes) system.l2bus.pkt_size::total 31276800 # Cumulative packet size per connected master and slave (bytes) system.l2bus.snoops 7776 # Total snoops (count) system.l2bus.snoopTraffic 362240 # Total snoop traffic (bytes) system.l2bus.snoop_fanout::samples 286175 # Request fanout histogram system.l2bus.snoop_fanout::mean 0.001034 # Request fanout histogram system.l2bus.snoop_fanout::stdev 0.032144 # Request fanout histogram system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.l2bus.snoop_fanout::0 285879 99.90% 99.90% # Request fanout histogram system.l2bus.snoop_fanout::1 296 0.10% 100.00% # Request fanout histogram system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.l2bus.snoop_fanout::min_value 0 # Request fanout histogram system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram system.l2bus.snoop_fanout::total 286175 # Request fanout histogram system.l2bus.respLayer1.occupancy 831974000 # Layer occupancy (ticks) system.l2bus.respLayer1.utilization 1.6 # Layer utilization (%) system.l2bus.reqLayer0.occupancy 976137000 # Layer occupancy (ticks) system.l2bus.reqLayer0.utilization 1.8 # Layer utilization (%) system.l2bus.respLayer0.occupancy 3207000 # Layer occupancy (ticks) system.l2bus.respLayer0.utilization 0.0 # Layer utilization (%) system.clk_domain.clock 1000 # Clock period in ticks system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts system.cpu.numPwrStateTransitions 1 # Number of power state transitions system.cpu.pwrStateResidencyTicks::ON 53378704000 # Cumulative time (in ticks) in various power states system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 53378704000 # Cumulative time (in ticks) in various power states system.cpu.icache.demand_hits::.cpu.inst 16313328 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 16313328 # number of demand (read+write) hits system.cpu.icache.overall_hits::.cpu.inst 16313328 # number of overall hits system.cpu.icache.overall_hits::total 16313328 # number of overall hits system.cpu.icache.demand_misses::.cpu.inst 1069 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 1069 # number of demand (read+write) misses system.cpu.icache.overall_misses::.cpu.inst 1069 # number of overall misses system.cpu.icache.overall_misses::total 1069 # number of overall misses system.cpu.icache.demand_miss_latency::.cpu.inst 97754000 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 97754000 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::.cpu.inst 97754000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 97754000 # number of overall miss cycles system.cpu.icache.demand_accesses::.cpu.inst 16314397 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 16314397 # number of demand (read+write) accesses system.cpu.icache.overall_accesses::.cpu.inst 16314397 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 16314397 # number of overall (read+write) accesses system.cpu.icache.demand_miss_rate::.cpu.inst 0.000066 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000066 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::.cpu.inst 0.000066 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000066 # miss rate for overall accesses system.cpu.icache.demand_avg_miss_latency::.cpu.inst 91444.340505 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 91444.340505 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::.cpu.inst 91444.340505 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 91444.340505 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.demand_mshr_misses::.cpu.inst 1069 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 1069 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::.cpu.inst 1069 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 1069 # number of overall MSHR misses system.cpu.icache.demand_mshr_miss_latency::.cpu.inst 95616000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 95616000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::.cpu.inst 95616000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 95616000 # number of overall MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate::.cpu.inst 0.000066 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000066 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::.cpu.inst 0.000066 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000066 # mshr miss rate for overall accesses system.cpu.icache.demand_avg_mshr_miss_latency::.cpu.inst 89444.340505 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 89444.340505 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::.cpu.inst 89444.340505 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 89444.340505 # average overall mshr miss latency system.cpu.icache.replacements 814 # number of replacements system.cpu.icache.ReadReq_hits::.cpu.inst 16313328 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 16313328 # number of ReadReq hits system.cpu.icache.ReadReq_misses::.cpu.inst 1069 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 1069 # number of ReadReq misses system.cpu.icache.ReadReq_miss_latency::.cpu.inst 97754000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 97754000 # number of ReadReq miss cycles system.cpu.icache.ReadReq_accesses::.cpu.inst 16314397 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 16314397 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_miss_rate::.cpu.inst 0.000066 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000066 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_avg_miss_latency::.cpu.inst 91444.340505 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 91444.340505 # average ReadReq miss latency system.cpu.icache.ReadReq_mshr_misses::.cpu.inst 1069 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 1069 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_miss_latency::.cpu.inst 95616000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 95616000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::.cpu.inst 0.000066 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000066 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::.cpu.inst 89444.340505 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 89444.340505 # average ReadReq mshr miss latency system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 53378704000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.tagsinuse 254.749981 # Cycle average of tags in use system.cpu.icache.tags.total_refs 16314397 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 1069 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 15261.362956 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 107000 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::.cpu.inst 254.749981 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::.cpu.inst 0.995117 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.995117 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 255 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 47 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 183 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.996094 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 32629863 # Number of tag accesses system.cpu.icache.tags.data_accesses 32629863 # Number of data accesses system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 53378704000 # Cumulative time (in ticks) in various power states system.cpu.dtb.stage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 53378704000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 53378704000 # Cumulative time (in ticks) in various power states system.cpu.itb.stage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 53378704000 # Cumulative time (in ticks) in various power states system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 53378704000 # Cumulative time (in ticks) in various power states system.cpu.dcache.demand_hits::.cpu.data 6298502 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 6298502 # number of demand (read+write) hits system.cpu.dcache.overall_hits::.cpu.data 6298509 # number of overall hits system.cpu.dcache.overall_hits::total 6298509 # number of overall hits system.cpu.dcache.demand_misses::.cpu.data 277327 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 277327 # number of demand (read+write) misses system.cpu.dcache.overall_misses::.cpu.data 277333 # number of overall misses system.cpu.dcache.overall_misses::total 277333 # number of overall misses system.cpu.dcache.demand_miss_latency::.cpu.data 8056971000 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 8056971000 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::.cpu.data 8056971000 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 8056971000 # number of overall miss cycles system.cpu.dcache.demand_accesses::.cpu.data 6575829 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 6575829 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::.cpu.data 6575842 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 6575842 # number of overall (read+write) accesses system.cpu.dcache.demand_miss_rate::.cpu.data 0.042174 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.042174 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::.cpu.data 0.042175 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.042175 # miss rate for overall accesses system.cpu.dcache.demand_avg_miss_latency::.cpu.data 29052.241578 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 29052.241578 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::.cpu.data 29051.613043 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 29051.613043 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.writebacks::.writebacks 210309 # number of writebacks system.cpu.dcache.writebacks::total 210309 # number of writebacks system.cpu.dcache.demand_mshr_hits::.cpu.data 4 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 4 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::.cpu.data 4 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 4 # number of overall MSHR hits system.cpu.dcache.demand_mshr_misses::.cpu.data 277323 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 277323 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::.cpu.data 277329 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 277329 # number of overall MSHR misses system.cpu.dcache.demand_mshr_miss_latency::.cpu.data 7501947000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 7501947000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::.cpu.data 7502617000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 7502617000 # number of overall MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate::.cpu.data 0.042173 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.042173 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::.cpu.data 0.042174 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.042174 # mshr miss rate for overall accesses system.cpu.dcache.demand_avg_mshr_miss_latency::.cpu.data 27051.297584 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 27051.297584 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::.cpu.data 27053.128234 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 27053.128234 # average overall mshr miss latency system.cpu.dcache.replacements 276306 # number of replacements system.cpu.dcache.ReadReq_hits::.cpu.data 4087315 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 4087315 # number of ReadReq hits system.cpu.dcache.ReadReq_misses::.cpu.data 266790 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 266790 # number of ReadReq misses system.cpu.dcache.ReadReq_miss_latency::.cpu.data 7303238000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 7303238000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_accesses::.cpu.data 4354105 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 4354105 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_miss_rate::.cpu.data 0.061273 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.061273 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_avg_miss_latency::.cpu.data 27374.481802 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 27374.481802 # average ReadReq miss latency system.cpu.dcache.ReadReq_mshr_hits::.cpu.data 4 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_misses::.cpu.data 266786 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 266786 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::.cpu.data 6769288000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 6769288000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data 0.061272 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.061272 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 25373.475370 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 25373.475370 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_hits::.cpu.data 2211187 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 2211187 # number of WriteReq hits system.cpu.dcache.WriteReq_misses::.cpu.data 10529 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 10529 # number of WriteReq misses system.cpu.dcache.WriteReq_miss_latency::.cpu.data 753301000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 753301000 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_accesses::.cpu.data 2221716 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 2221716 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.004739 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.004739 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 71545.350936 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 71545.350936 # average WriteReq miss latency system.cpu.dcache.WriteReq_mshr_misses::.cpu.data 10529 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 10529 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 732243000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 732243000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.004739 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.004739 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 69545.350936 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 69545.350936 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_hits::.cpu.data 7 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 7 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_misses::.cpu.data 6 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 6 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_accesses::.cpu.data 13 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::total 13 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.461538 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.461538 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 6 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 6 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 670000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 670000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.461538 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.461538 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 111666.666667 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 111666.666667 # average SoftPFReq mshr miss latency system.cpu.dcache.WriteLineReq_misses::.cpu.data 8 # number of WriteLineReq misses system.cpu.dcache.WriteLineReq_misses::total 8 # number of WriteLineReq misses system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 432000 # number of WriteLineReq miss cycles system.cpu.dcache.WriteLineReq_miss_latency::total 432000 # number of WriteLineReq miss cycles system.cpu.dcache.WriteLineReq_accesses::.cpu.data 8 # number of WriteLineReq accesses(hits+misses) system.cpu.dcache.WriteLineReq_accesses::total 8 # number of WriteLineReq accesses(hits+misses) system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 1 # miss rate for WriteLineReq accesses system.cpu.dcache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 54000 # average WriteLineReq miss latency system.cpu.dcache.WriteLineReq_avg_miss_latency::total 54000 # average WriteLineReq miss latency system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 8 # number of WriteLineReq MSHR misses system.cpu.dcache.WriteLineReq_mshr_misses::total 8 # number of WriteLineReq MSHR misses system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 416000 # number of WriteLineReq MSHR miss cycles system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 416000 # number of WriteLineReq MSHR miss cycles system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for WriteLineReq accesses system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 52000 # average WriteLineReq mshr miss latency system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 52000 # average WriteLineReq mshr miss latency system.cpu.dcache.LoadLockedReq_hits::.cpu.data 101 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 101 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_misses::.cpu.data 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_miss_latency::.cpu.data 95000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 95000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 102 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 102 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_miss_rate::.cpu.data 0.009804 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.009804 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_avg_miss_latency::.cpu.data 95000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 95000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_mshr_misses::.cpu.data 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_miss_latency::.cpu.data 93000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 93000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_rate::.cpu.data 0.009804 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.009804 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::.cpu.data 93000 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 93000 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_hits::.cpu.data 102 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 102 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_accesses::.cpu.data 102 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 102 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 53378704000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.tagsinuse 1019.499482 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 6576042 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 277330 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 23.711975 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 236000 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::.cpu.data 1019.499482 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::.cpu.data 0.995605 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.995605 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 1024 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 27 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 465 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 531 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 13429422 # Number of tag accesses system.cpu.dcache.tags.data_accesses 13429422 # Number of data accesses system.l2cache.pwrStateResidencyTicks::UNDEFINED 53378704000 # Cumulative time (in ticks) in various power states system.l2cache.demand_hits::.cpu.inst 152 # number of demand (read+write) hits system.l2cache.demand_hits::.cpu.data 266376 # number of demand (read+write) hits system.l2cache.demand_hits::total 266528 # number of demand (read+write) hits system.l2cache.overall_hits::.cpu.inst 152 # number of overall hits system.l2cache.overall_hits::.cpu.data 266376 # number of overall hits system.l2cache.overall_hits::total 266528 # number of overall hits system.l2cache.demand_misses::.cpu.inst 917 # number of demand (read+write) misses system.l2cache.demand_misses::.cpu.data 10946 # number of demand (read+write) misses system.l2cache.demand_misses::total 11863 # number of demand (read+write) misses system.l2cache.overall_misses::.cpu.inst 917 # number of overall misses system.l2cache.overall_misses::.cpu.data 10946 # number of overall misses system.l2cache.overall_misses::total 11863 # number of overall misses system.l2cache.demand_miss_latency::.cpu.inst 89211000 # number of demand (read+write) miss cycles system.l2cache.demand_miss_latency::.cpu.data 1076430000 # number of demand (read+write) miss cycles system.l2cache.demand_miss_latency::total 1165641000 # number of demand (read+write) miss cycles system.l2cache.overall_miss_latency::.cpu.inst 89211000 # number of overall miss cycles system.l2cache.overall_miss_latency::.cpu.data 1076430000 # number of overall miss cycles system.l2cache.overall_miss_latency::total 1165641000 # number of overall miss cycles system.l2cache.demand_accesses::.cpu.inst 1069 # number of demand (read+write) accesses system.l2cache.demand_accesses::.cpu.data 277322 # number of demand (read+write) accesses system.l2cache.demand_accesses::total 278391 # number of demand (read+write) accesses system.l2cache.overall_accesses::.cpu.inst 1069 # number of overall (read+write) accesses system.l2cache.overall_accesses::.cpu.data 277322 # number of overall (read+write) accesses system.l2cache.overall_accesses::total 278391 # number of overall (read+write) accesses system.l2cache.demand_miss_rate::.cpu.inst 0.857811 # miss rate for demand accesses system.l2cache.demand_miss_rate::.cpu.data 0.039470 # miss rate for demand accesses system.l2cache.demand_miss_rate::total 0.042613 # miss rate for demand accesses system.l2cache.overall_miss_rate::.cpu.inst 0.857811 # miss rate for overall accesses system.l2cache.overall_miss_rate::.cpu.data 0.039470 # miss rate for overall accesses system.l2cache.overall_miss_rate::total 0.042613 # miss rate for overall accesses system.l2cache.demand_avg_miss_latency::.cpu.inst 97285.714286 # average overall miss latency system.l2cache.demand_avg_miss_latency::.cpu.data 98340.032889 # average overall miss latency system.l2cache.demand_avg_miss_latency::total 98258.534941 # average overall miss latency system.l2cache.overall_avg_miss_latency::.cpu.inst 97285.714286 # average overall miss latency system.l2cache.overall_avg_miss_latency::.cpu.data 98340.032889 # average overall miss latency system.l2cache.overall_avg_miss_latency::total 98258.534941 # average overall miss latency system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2cache.writebacks::.writebacks 5660 # number of writebacks system.l2cache.writebacks::total 5660 # number of writebacks system.l2cache.demand_mshr_misses::.cpu.inst 917 # number of demand (read+write) MSHR misses system.l2cache.demand_mshr_misses::.cpu.data 10946 # number of demand (read+write) MSHR misses system.l2cache.demand_mshr_misses::total 11863 # number of demand (read+write) MSHR misses system.l2cache.overall_mshr_misses::.cpu.inst 917 # number of overall MSHR misses system.l2cache.overall_mshr_misses::.cpu.data 10946 # number of overall MSHR misses system.l2cache.overall_mshr_misses::total 11863 # number of overall MSHR misses system.l2cache.demand_mshr_miss_latency::.cpu.inst 70871000 # number of demand (read+write) MSHR miss cycles system.l2cache.demand_mshr_miss_latency::.cpu.data 857510000 # number of demand (read+write) MSHR miss cycles system.l2cache.demand_mshr_miss_latency::total 928381000 # number of demand (read+write) MSHR miss cycles system.l2cache.overall_mshr_miss_latency::.cpu.inst 70871000 # number of overall MSHR miss cycles system.l2cache.overall_mshr_miss_latency::.cpu.data 857510000 # number of overall MSHR miss cycles system.l2cache.overall_mshr_miss_latency::total 928381000 # number of overall MSHR miss cycles system.l2cache.demand_mshr_miss_rate::.cpu.inst 0.857811 # mshr miss rate for demand accesses system.l2cache.demand_mshr_miss_rate::.cpu.data 0.039470 # mshr miss rate for demand accesses system.l2cache.demand_mshr_miss_rate::total 0.042613 # mshr miss rate for demand accesses system.l2cache.overall_mshr_miss_rate::.cpu.inst 0.857811 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::.cpu.data 0.039470 # mshr miss rate for overall accesses system.l2cache.overall_mshr_miss_rate::total 0.042613 # mshr miss rate for overall accesses system.l2cache.demand_avg_mshr_miss_latency::.cpu.inst 77285.714286 # average overall mshr miss latency system.l2cache.demand_avg_mshr_miss_latency::.cpu.data 78340.032889 # average overall mshr miss latency system.l2cache.demand_avg_mshr_miss_latency::total 78258.534941 # average overall mshr miss latency system.l2cache.overall_avg_mshr_miss_latency::.cpu.inst 77285.714286 # average overall mshr miss latency system.l2cache.overall_avg_mshr_miss_latency::.cpu.data 78340.032889 # average overall mshr miss latency system.l2cache.overall_avg_mshr_miss_latency::total 78258.534941 # average overall mshr miss latency system.l2cache.replacements 7776 # number of replacements system.l2cache.WritebackDirty_hits::.writebacks 210309 # number of WritebackDirty hits system.l2cache.WritebackDirty_hits::total 210309 # number of WritebackDirty hits system.l2cache.WritebackDirty_accesses::.writebacks 210309 # number of WritebackDirty accesses(hits+misses) system.l2cache.WritebackDirty_accesses::total 210309 # number of WritebackDirty accesses(hits+misses) system.l2cache.CleanEvict_mshr_misses::.writebacks 111 # number of CleanEvict MSHR misses system.l2cache.CleanEvict_mshr_misses::total 111 # number of CleanEvict MSHR misses system.l2cache.CleanEvict_mshr_miss_rate::.writebacks inf # mshr miss rate for CleanEvict accesses system.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.l2cache.ReadExReq_hits::.cpu.data 4117 # number of ReadExReq hits system.l2cache.ReadExReq_hits::total 4117 # number of ReadExReq hits system.l2cache.ReadExReq_misses::.cpu.data 6412 # number of ReadExReq misses system.l2cache.ReadExReq_misses::total 6412 # number of ReadExReq misses system.l2cache.ReadExReq_miss_latency::.cpu.data 614198000 # number of ReadExReq miss cycles system.l2cache.ReadExReq_miss_latency::total 614198000 # number of ReadExReq miss cycles system.l2cache.ReadExReq_accesses::.cpu.data 10529 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadExReq_accesses::total 10529 # number of ReadExReq accesses(hits+misses) system.l2cache.ReadExReq_miss_rate::.cpu.data 0.608985 # miss rate for ReadExReq accesses system.l2cache.ReadExReq_miss_rate::total 0.608985 # miss rate for ReadExReq accesses system.l2cache.ReadExReq_avg_miss_latency::.cpu.data 95788.833437 # average ReadExReq miss latency system.l2cache.ReadExReq_avg_miss_latency::total 95788.833437 # average ReadExReq miss latency system.l2cache.ReadExReq_mshr_misses::.cpu.data 6412 # number of ReadExReq MSHR misses system.l2cache.ReadExReq_mshr_misses::total 6412 # number of ReadExReq MSHR misses system.l2cache.ReadExReq_mshr_miss_latency::.cpu.data 485958000 # number of ReadExReq MSHR miss cycles system.l2cache.ReadExReq_mshr_miss_latency::total 485958000 # number of ReadExReq MSHR miss cycles system.l2cache.ReadExReq_mshr_miss_rate::.cpu.data 0.608985 # mshr miss rate for ReadExReq accesses system.l2cache.ReadExReq_mshr_miss_rate::total 0.608985 # mshr miss rate for ReadExReq accesses system.l2cache.ReadExReq_avg_mshr_miss_latency::.cpu.data 75788.833437 # average ReadExReq mshr miss latency system.l2cache.ReadExReq_avg_mshr_miss_latency::total 75788.833437 # average ReadExReq mshr miss latency system.l2cache.ReadSharedReq_hits::.cpu.inst 152 # number of ReadSharedReq hits system.l2cache.ReadSharedReq_hits::.cpu.data 262259 # number of ReadSharedReq hits system.l2cache.ReadSharedReq_hits::total 262411 # number of ReadSharedReq hits system.l2cache.ReadSharedReq_misses::.cpu.inst 917 # number of ReadSharedReq misses system.l2cache.ReadSharedReq_misses::.cpu.data 4534 # number of ReadSharedReq misses system.l2cache.ReadSharedReq_misses::total 5451 # number of ReadSharedReq misses system.l2cache.ReadSharedReq_miss_latency::.cpu.inst 89211000 # number of ReadSharedReq miss cycles system.l2cache.ReadSharedReq_miss_latency::.cpu.data 462232000 # number of ReadSharedReq miss cycles system.l2cache.ReadSharedReq_miss_latency::total 551443000 # number of ReadSharedReq miss cycles system.l2cache.ReadSharedReq_accesses::.cpu.inst 1069 # number of ReadSharedReq accesses(hits+misses) system.l2cache.ReadSharedReq_accesses::.cpu.data 266793 # number of ReadSharedReq accesses(hits+misses) system.l2cache.ReadSharedReq_accesses::total 267862 # number of ReadSharedReq accesses(hits+misses) system.l2cache.ReadSharedReq_miss_rate::.cpu.inst 0.857811 # miss rate for ReadSharedReq accesses system.l2cache.ReadSharedReq_miss_rate::.cpu.data 0.016994 # miss rate for ReadSharedReq accesses system.l2cache.ReadSharedReq_miss_rate::total 0.020350 # miss rate for ReadSharedReq accesses system.l2cache.ReadSharedReq_avg_miss_latency::.cpu.inst 97285.714286 # average ReadSharedReq miss latency system.l2cache.ReadSharedReq_avg_miss_latency::.cpu.data 101947.948831 # average ReadSharedReq miss latency system.l2cache.ReadSharedReq_avg_miss_latency::total 101163.639699 # average ReadSharedReq miss latency system.l2cache.ReadSharedReq_mshr_misses::.cpu.inst 917 # number of ReadSharedReq MSHR misses system.l2cache.ReadSharedReq_mshr_misses::.cpu.data 4534 # number of ReadSharedReq MSHR misses system.l2cache.ReadSharedReq_mshr_misses::total 5451 # number of ReadSharedReq MSHR misses system.l2cache.ReadSharedReq_mshr_miss_latency::.cpu.inst 70871000 # number of ReadSharedReq MSHR miss cycles system.l2cache.ReadSharedReq_mshr_miss_latency::.cpu.data 371552000 # number of ReadSharedReq MSHR miss cycles system.l2cache.ReadSharedReq_mshr_miss_latency::total 442423000 # number of ReadSharedReq MSHR miss cycles system.l2cache.ReadSharedReq_mshr_miss_rate::.cpu.inst 0.857811 # mshr miss rate for ReadSharedReq accesses system.l2cache.ReadSharedReq_mshr_miss_rate::.cpu.data 0.016994 # mshr miss rate for ReadSharedReq accesses system.l2cache.ReadSharedReq_mshr_miss_rate::total 0.020350 # mshr miss rate for ReadSharedReq accesses system.l2cache.ReadSharedReq_avg_mshr_miss_latency::.cpu.inst 77285.714286 # average ReadSharedReq mshr miss latency system.l2cache.ReadSharedReq_avg_mshr_miss_latency::.cpu.data 81947.948831 # average ReadSharedReq mshr miss latency system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 81163.639699 # average ReadSharedReq mshr miss latency system.l2cache.InvalidateReq_misses::.cpu.data 8 # number of InvalidateReq misses system.l2cache.InvalidateReq_misses::total 8 # number of InvalidateReq misses system.l2cache.InvalidateReq_accesses::.cpu.data 8 # number of InvalidateReq accesses(hits+misses) system.l2cache.InvalidateReq_accesses::total 8 # number of InvalidateReq accesses(hits+misses) system.l2cache.InvalidateReq_miss_rate::.cpu.data 1 # miss rate for InvalidateReq accesses system.l2cache.InvalidateReq_miss_rate::total 1 # miss rate for InvalidateReq accesses system.l2cache.InvalidateReq_mshr_misses::.cpu.data 8 # number of InvalidateReq MSHR misses system.l2cache.InvalidateReq_mshr_misses::total 8 # number of InvalidateReq MSHR misses system.l2cache.InvalidateReq_mshr_miss_latency::.cpu.data 232000 # number of InvalidateReq MSHR miss cycles system.l2cache.InvalidateReq_mshr_miss_latency::total 232000 # number of InvalidateReq MSHR miss cycles system.l2cache.InvalidateReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for InvalidateReq accesses system.l2cache.InvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for InvalidateReq accesses system.l2cache.InvalidateReq_avg_mshr_miss_latency::.cpu.data 29000 # average InvalidateReq mshr miss latency system.l2cache.InvalidateReq_avg_mshr_miss_latency::total 29000 # average InvalidateReq mshr miss latency system.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 53378704000 # Cumulative time (in ticks) in various power states system.l2cache.tags.tagsinuse 4041.428770 # Cycle average of tags in use system.l2cache.tags.total_refs 555399 # Total number of references to valid blocks. system.l2cache.tags.sampled_refs 11872 # Sample count of references to valid blocks. system.l2cache.tags.avg_refs 46.782261 # Average number of references to valid blocks. system.l2cache.tags.warmup_cycle 86000 # Cycle when the warmup percentage was hit. system.l2cache.tags.occ_blocks::.writebacks 0.361595 # Average occupied blocks per requestor system.l2cache.tags.occ_blocks::.cpu.inst 31.628679 # Average occupied blocks per requestor system.l2cache.tags.occ_blocks::.cpu.data 4009.438497 # Average occupied blocks per requestor system.l2cache.tags.occ_percent::.writebacks 0.000088 # Average percentage of cache occupancy system.l2cache.tags.occ_percent::.cpu.inst 0.007722 # Average percentage of cache occupancy system.l2cache.tags.occ_percent::.cpu.data 0.978867 # Average percentage of cache occupancy system.l2cache.tags.occ_percent::total 0.986677 # Average percentage of cache occupancy system.l2cache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id system.l2cache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id system.l2cache.tags.age_task_id_blocks_1024::1 93 # Occupied blocks per task id system.l2cache.tags.age_task_id_blocks_1024::2 70 # Occupied blocks per task id system.l2cache.tags.age_task_id_blocks_1024::3 740 # Occupied blocks per task id system.l2cache.tags.age_task_id_blocks_1024::4 3120 # Occupied blocks per task id system.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.l2cache.tags.tag_accesses 4456016 # Number of tag accesses system.l2cache.tags.data_accesses 4456016 # Number of data accesses system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 53378704000 # Cumulative time (in ticks) in various power states system.mem_ctrl.bytes_read::.cpu.inst 58688 # Number of bytes read from this memory system.mem_ctrl.bytes_read::.cpu.data 700544 # Number of bytes read from this memory system.mem_ctrl.bytes_read::total 759232 # Number of bytes read from this memory system.mem_ctrl.bytes_inst_read::.cpu.inst 58688 # Number of instructions bytes read from this memory system.mem_ctrl.bytes_inst_read::total 58688 # Number of instructions bytes read from this memory system.mem_ctrl.bytes_written::.writebacks 362240 # Number of bytes written to this memory system.mem_ctrl.bytes_written::total 362240 # Number of bytes written to this memory system.mem_ctrl.num_reads::.cpu.inst 917 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::.cpu.data 10946 # Number of read requests responded to by this memory system.mem_ctrl.num_reads::total 11863 # Number of read requests responded to by this memory system.mem_ctrl.num_writes::.writebacks 5660 # Number of write requests responded to by this memory system.mem_ctrl.num_writes::total 5660 # Number of write requests responded to by this memory system.mem_ctrl.bw_read::.cpu.inst 1099465 # Total read bandwidth from this memory (bytes/s) system.mem_ctrl.bw_read::.cpu.data 13124035 # Total read bandwidth from this memory (bytes/s) system.mem_ctrl.bw_read::total 14223500 # Total read bandwidth from this memory (bytes/s) system.mem_ctrl.bw_inst_read::.cpu.inst 1099465 # Instruction read bandwidth from this memory (bytes/s) system.mem_ctrl.bw_inst_read::total 1099465 # Instruction read bandwidth from this memory (bytes/s) system.mem_ctrl.bw_write::.writebacks 6786227 # Write bandwidth from this memory (bytes/s) system.mem_ctrl.bw_write::total 6786227 # Write bandwidth from this memory (bytes/s) system.mem_ctrl.bw_total::.writebacks 6786227 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.bw_total::.cpu.inst 1099465 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.bw_total::.cpu.data 13124035 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.bw_total::total 21009727 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrl.avgPriority_.writebacks::samples 5660.00 # Average QoS priority value for accepted requests system.mem_ctrl.avgPriority_.cpu.inst::samples 917.00 # Average QoS priority value for accepted requests system.mem_ctrl.avgPriority_.cpu.data::samples 10946.00 # Average QoS priority value for accepted requests system.mem_ctrl.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) system.mem_ctrl.priorityMaxLatency 0.003225031750 # per QoS priority maximum request to response latency (s) system.mem_ctrl.numReadWriteTurnArounds 314 # Number of turnarounds from READ to WRITE system.mem_ctrl.numWriteReadTurnArounds 314 # Number of turnarounds from WRITE to READ system.mem_ctrl.numStayReadState 43065 # Number of times bus staying in READ state system.mem_ctrl.numStayWriteState 5330 # Number of times bus staying in WRITE state system.mem_ctrl.readReqs 11863 # Number of read requests accepted system.mem_ctrl.writeReqs 5660 # Number of write requests accepted system.mem_ctrl.readBursts 11863 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrl.writeBursts 5660 # Number of DRAM write bursts, including those merged in the write queue system.mem_ctrl.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.mem_ctrl.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.mem_ctrl.perBankRdBursts::0 851 # Per bank write bursts system.mem_ctrl.perBankRdBursts::1 807 # Per bank write bursts system.mem_ctrl.perBankRdBursts::2 746 # Per bank write bursts system.mem_ctrl.perBankRdBursts::3 638 # Per bank write bursts system.mem_ctrl.perBankRdBursts::4 571 # Per bank write bursts system.mem_ctrl.perBankRdBursts::5 590 # Per bank write bursts system.mem_ctrl.perBankRdBursts::6 679 # Per bank write bursts system.mem_ctrl.perBankRdBursts::7 736 # Per bank write bursts system.mem_ctrl.perBankRdBursts::8 729 # Per bank write bursts system.mem_ctrl.perBankRdBursts::9 762 # Per bank write bursts system.mem_ctrl.perBankRdBursts::10 773 # Per bank write bursts system.mem_ctrl.perBankRdBursts::11 817 # Per bank write bursts system.mem_ctrl.perBankRdBursts::12 836 # Per bank write bursts system.mem_ctrl.perBankRdBursts::13 839 # Per bank write bursts system.mem_ctrl.perBankRdBursts::14 743 # Per bank write bursts system.mem_ctrl.perBankRdBursts::15 746 # Per bank write bursts system.mem_ctrl.perBankWrBursts::0 331 # Per bank write bursts system.mem_ctrl.perBankWrBursts::1 297 # Per bank write bursts system.mem_ctrl.perBankWrBursts::2 300 # Per bank write bursts system.mem_ctrl.perBankWrBursts::3 291 # Per bank write bursts system.mem_ctrl.perBankWrBursts::4 303 # Per bank write bursts system.mem_ctrl.perBankWrBursts::5 290 # Per bank write bursts system.mem_ctrl.perBankWrBursts::6 363 # Per bank write bursts system.mem_ctrl.perBankWrBursts::7 417 # Per bank write bursts system.mem_ctrl.perBankWrBursts::8 427 # Per bank write bursts system.mem_ctrl.perBankWrBursts::9 418 # Per bank write bursts system.mem_ctrl.perBankWrBursts::10 431 # Per bank write bursts system.mem_ctrl.perBankWrBursts::11 403 # Per bank write bursts system.mem_ctrl.perBankWrBursts::12 403 # Per bank write bursts system.mem_ctrl.perBankWrBursts::13 391 # Per bank write bursts system.mem_ctrl.perBankWrBursts::14 284 # Per bank write bursts system.mem_ctrl.perBankWrBursts::15 283 # Per bank write bursts system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing system.mem_ctrl.avgWrQLen 23.41 # Average write queue length when enqueuing system.mem_ctrl.totQLat 97237000 # Total ticks spent queuing system.mem_ctrl.totBusLat 59315000 # Total ticks spent in databus transfers system.mem_ctrl.totMemAccLat 319668250 # Total ticks spent from burst creation until serviced by the DRAM system.mem_ctrl.avgQLat 8196.66 # Average queueing delay per DRAM burst system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst system.mem_ctrl.avgMemAccLat 26946.66 # Average memory access latency per DRAM burst system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry system.mem_ctrl.readRowHits 8907 # Number of row buffer hits during reads system.mem_ctrl.writeRowHits 4907 # Number of row buffer hits during writes system.mem_ctrl.readRowHitRate 75.08 # Row buffer hit rate for reads system.mem_ctrl.writeRowHitRate 86.70 # Row buffer hit rate for writes system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::3 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) system.mem_ctrl.readPktSize::6 11863 # Read request sizes (log2) system.mem_ctrl.writePktSize::0 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::1 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::2 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::3 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrl.writePktSize::6 5660 # Write request sizes (log2) system.mem_ctrl.rdQLenPdf::0 11860 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::1 3 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::4 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::5 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::6 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::7 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::8 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::9 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::10 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::11 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::12 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::13 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::14 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::15 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::16 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::17 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::18 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::19 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::20 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::21 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::22 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::23 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::24 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::25 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::26 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::27 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::28 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::29 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::30 0 # What read queue length does an incoming req see system.mem_ctrl.rdQLenPdf::31 0 # What read queue length does an incoming req see system.mem_ctrl.wrQLenPdf::0 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::1 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::2 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::3 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::4 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::5 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::6 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::7 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::8 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::9 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::10 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::11 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::12 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::14 1 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::15 305 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::16 305 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::17 315 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::18 315 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::19 315 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::20 315 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::21 315 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::22 315 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::23 315 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::24 315 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::25 315 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::26 315 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::27 315 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::28 314 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::29 314 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::30 314 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::31 314 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::32 314 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::33 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::34 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::36 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::37 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::38 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::39 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::40 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::41 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::42 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::43 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::44 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::45 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::46 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::47 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::48 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::49 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::50 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::51 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::52 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::53 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::54 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::55 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see system.mem_ctrl.bytesPerActivate::samples 3675 # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::mean 304.448435 # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::gmean 156.117057 # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::stdev 357.897847 # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::0-127 1988 54.10% 54.10% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::128-255 461 12.54% 66.64% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::256-383 152 4.14% 70.78% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::384-511 122 3.32% 74.10% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::512-639 135 3.67% 77.77% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::640-767 98 2.67% 80.44% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::768-895 128 3.48% 83.92% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::896-1023 106 2.88% 86.80% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::1024-1151 485 13.20% 100.00% # Bytes accessed per row activation system.mem_ctrl.bytesPerActivate::total 3675 # Bytes accessed per row activation system.mem_ctrl.rdPerTurnAround::samples 314 # Reads before turning the bus around for writes system.mem_ctrl.rdPerTurnAround::mean 37.659236 # Reads before turning the bus around for writes system.mem_ctrl.rdPerTurnAround::gmean 22.224786 # Reads before turning the bus around for writes system.mem_ctrl.rdPerTurnAround::stdev 251.383015 # Reads before turning the bus around for writes system.mem_ctrl.rdPerTurnAround::0-255 313 99.68% 99.68% # Reads before turning the bus around for writes system.mem_ctrl.rdPerTurnAround::4352-4607 1 0.32% 100.00% # Reads before turning the bus around for writes system.mem_ctrl.rdPerTurnAround::total 314 # Reads before turning the bus around for writes system.mem_ctrl.wrPerTurnAround::samples 314 # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::mean 17.936306 # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::gmean 17.932608 # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::stdev 0.351747 # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::16 10 3.18% 3.18% # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::18 304 96.82% 100.00% # Writes before turning the bus around for reads system.mem_ctrl.wrPerTurnAround::total 314 # Writes before turning the bus around for reads system.mem_ctrl.bytesReadDRAM 759232 # Total number of bytes read from DRAM system.mem_ctrl.bytesReadWrQ 0 # Total number of bytes read from write queue system.mem_ctrl.bytesWritten 360448 # Total number of bytes written to DRAM system.mem_ctrl.bytesReadSys 759232 # Total read bytes from the system interface side system.mem_ctrl.bytesWrittenSys 362240 # Total written bytes from the system interface side system.mem_ctrl.avgRdBW 14.22 # Average DRAM read bandwidth in MiByte/s system.mem_ctrl.avgWrBW 6.75 # Average achieved write bandwidth in MiByte/s system.mem_ctrl.avgRdBWSys 14.22 # Average system read bandwidth in MiByte/s system.mem_ctrl.avgWrBWSys 6.79 # Average system write bandwidth in MiByte/s system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.mem_ctrl.busUtil 0.16 # Data bus utilization in percentage system.mem_ctrl.busUtilRead 0.11 # Data bus utilization in percentage for reads system.mem_ctrl.busUtilWrite 0.05 # Data bus utilization in percentage for writes system.mem_ctrl.totGap 53378609000 # Total gap between requests system.mem_ctrl.avgGap 3046202.65 # Average gap between requests system.mem_ctrl.masterReadBytes::.cpu.inst 58688 # Per-master bytes read from memory system.mem_ctrl.masterReadBytes::.cpu.data 700544 # Per-master bytes read from memory system.mem_ctrl.masterWriteBytes::.writebacks 360448 # Per-master bytes write to memory system.mem_ctrl.masterReadRate::.cpu.inst 1099464.685392136918 # Per-master bytes read from memory rate (Bytes/sec) system.mem_ctrl.masterReadRate::.cpu.data 13124035.383099596947 # Per-master bytes read from memory rate (Bytes/sec) system.mem_ctrl.masterWriteRate::.writebacks 6752655.515952579677 # Per-master bytes write to memory rate (Bytes/sec) system.mem_ctrl.masterReadAccesses::.cpu.inst 917 # Per-master read serviced memory accesses system.mem_ctrl.masterReadAccesses::.cpu.data 10946 # Per-master read serviced memory accesses system.mem_ctrl.masterWriteAccesses::.writebacks 5660 # Per-master write serviced memory accesses system.mem_ctrl.masterReadTotalLat::.cpu.inst 23795750 # Per-master read total memory access latency system.mem_ctrl.masterReadTotalLat::.cpu.data 295872500 # Per-master read total memory access latency system.mem_ctrl.masterWriteTotalLat::.writebacks 1194932694500 # Per-master write total memory access latency system.mem_ctrl.masterReadAvgLat::.cpu.inst 25949.56 # Per-master read average memory access latency system.mem_ctrl.masterReadAvgLat::.cpu.data 27030.19 # Per-master read average memory access latency system.mem_ctrl.masterWriteAvgLat::.writebacks 211118850.62 # Per-master write average memory access latency system.mem_ctrl.pageHitRate 78.83 # Row buffer hit rate, read and write combined system.mem_ctrl.rank1.actEnergy 14822640 # Energy for activate commands per rank (pJ) system.mem_ctrl.rank1.preEnergy 7867035 # Energy for precharge commands per rank (pJ) system.mem_ctrl.rank1.readEnergy 44589300 # Energy for read commands per rank (pJ) system.mem_ctrl.rank1.writeEnergy 15868800 # Energy for write commands per rank (pJ) system.mem_ctrl.rank1.refreshEnergy 4213357200.000000 # Energy for refresh commands per rank (pJ) system.mem_ctrl.rank1.actBackEnergy 3463477890 # Energy for active background per rank (pJ) system.mem_ctrl.rank1.preBackEnergy 17580809760 # Energy for precharge background per rank (pJ) system.mem_ctrl.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) system.mem_ctrl.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) system.mem_ctrl.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) system.mem_ctrl.rank1.totalEnergy 25340792625 # Total energy per rank (pJ) system.mem_ctrl.rank1.averagePower 474.736004 # Core power per rank (mW) system.mem_ctrl.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank system.mem_ctrl.rank1.memoryStateTime::IDLE 45667870500 # Time in different power states system.mem_ctrl.rank1.memoryStateTime::REF 1782300000 # Time in different power states system.mem_ctrl.rank1.memoryStateTime::SREF 0 # Time in different power states system.mem_ctrl.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrl.rank1.memoryStateTime::ACT 5928533500 # Time in different power states system.mem_ctrl.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states system.mem_ctrl.rank0.actEnergy 11459700 # Energy for activate commands per rank (pJ) system.mem_ctrl.rank0.preEnergy 6079590 # Energy for precharge commands per rank (pJ) system.mem_ctrl.rank0.readEnergy 40112520 # Energy for read commands per rank (pJ) system.mem_ctrl.rank0.writeEnergy 13530240 # Energy for write commands per rank (pJ) system.mem_ctrl.rank0.refreshEnergy 4213357200.000000 # Energy for refresh commands per rank (pJ) system.mem_ctrl.rank0.actBackEnergy 2708508330 # Energy for active background per rank (pJ) system.mem_ctrl.rank0.preBackEnergy 18216573600 # Energy for precharge background per rank (pJ) system.mem_ctrl.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) system.mem_ctrl.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) system.mem_ctrl.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) system.mem_ctrl.rank0.totalEnergy 25209621180 # Total energy per rank (pJ) system.mem_ctrl.rank0.averagePower 472.278630 # Core power per rank (mW) system.mem_ctrl.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank system.mem_ctrl.rank0.memoryStateTime::IDLE 47329122750 # Time in different power states system.mem_ctrl.rank0.memoryStateTime::REF 1782300000 # Time in different power states system.mem_ctrl.rank0.memoryStateTime::SREF 0 # Time in different power states system.mem_ctrl.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrl.rank0.memoryStateTime::ACT 4267281250 # Time in different power states system.mem_ctrl.rank0.memoryStateTime::ACT_PDN 0 # Time in different power states ---------- End Simulation Statistics ----------