---------- Begin Simulation Statistics ---------- final_tick 3464305000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) host_inst_rate 34369 # Simulator instruction rate (inst/s) host_mem_usage 818308 # Number of bytes of host memory used host_op_rate 179011 # Simulator op (including micro ops) rate (op/s) host_seconds 14.51 # Real time elapsed on the host host_tick_rate 238802817 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 498582 # Number of instructions simulated sim_ops 2596898 # Number of ops (including micro ops) simulated sim_seconds 0.003464 # Number of seconds simulated sim_ticks 3464305000 # Number of ticks simulated system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.branchPred.BTBHitPct 98.962835 # BTB Hit Percentage system.cpu.branchPred.BTBHits 33205 # Number of BTB hits system.cpu.branchPred.BTBLookups 33553 # Number of BTB lookups system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions. system.cpu.branchPred.condIncorrect 743 # Number of conditional branches incorrect system.cpu.branchPred.condPredicted 67669 # Number of conditional branches predicted system.cpu.branchPred.indirectHits 0 # Number of indirect target hits. system.cpu.branchPred.indirectLookups 76 # Number of indirect predictor lookups. system.cpu.branchPred.indirectMisses 76 # Number of indirect misses. system.cpu.branchPred.lookups 68471 # Number of BP lookups system.cpu.branchPred.usedRAS 266 # Number of times the RAS was used to get a target. system.cpu.branchPredindirectMispredicted 35 # Number of mispredicted indirect branches. system.cpu.cc_regfile_reads 199698 # number of cc regfile reads system.cpu.cc_regfile_writes 199689 # number of cc regfile writes system.cpu.commit.amos 0 # Number of atomic instructions committed system.cpu.commit.branchMispredicts 593 # The number of times a branch was mispredicted system.cpu.commit.branches 67001 # Number of branches committed system.cpu.commit.bw_lim_events 117688 # number cycles where commit BW limit reached system.cpu.commit.commitNonSpecStalls 23 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.commitSquashedInsts 3134 # The number of squashed insts skipped by commit system.cpu.commit.committedInsts 515112 # Number of instructions committed system.cpu.commit.committedOps 2613428 # Number of ops (including micro ops) committed system.cpu.commit.committed_per_cycle::samples 6907179 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::mean 0.378364 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::stdev 1.150374 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::0 5368477 77.72% 77.72% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 1281560 18.55% 96.28% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::2 78434 1.14% 97.41% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 41401 0.60% 98.01% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 2954 0.04% 98.05% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 7518 0.11% 98.16% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::6 4142 0.06% 98.22% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::7 5005 0.07% 98.30% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::8 117688 1.70% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::total 6907179 # Number of insts commited each cycle system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.function_calls 117 # Number of function calls committed. system.cpu.commit.int_insts 2383051 # Number of committed integer instructions. system.cpu.commit.loads 2147169 # Number of loads committed system.cpu.commit.membars 14 # Number of memory barriers committed system.cpu.commit.op_class_0::No_OpClass 2 0.00% 0.00% # Class of committed instruction system.cpu.commit.op_class_0::IntAlu 235659 9.02% 9.02% # Class of committed instruction system.cpu.commit.op_class_0::IntMult 5 0.00% 9.02% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 2 0.00% 9.02% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 9.02% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 9.02% # Class of committed instruction system.cpu.commit.op_class_0::FloatCvt 0 0.00% 9.02% # Class of committed instruction system.cpu.commit.op_class_0::FloatMult 0 0.00% 9.02% # Class of committed instruction system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 9.02% # Class of committed instruction system.cpu.commit.op_class_0::FloatDiv 0 0.00% 9.02% # Class of committed instruction system.cpu.commit.op_class_0::FloatMisc 0 0.00% 9.02% # Class of committed instruction system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 9.02% # Class of committed instruction system.cpu.commit.op_class_0::SimdAdd 11 0.00% 9.02% # Class of committed instruction system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 9.02% # Class of committed instruction system.cpu.commit.op_class_0::SimdAlu 65546 2.51% 11.53% # Class of committed instruction system.cpu.commit.op_class_0::SimdCmp 32777 1.25% 12.78% # Class of committed instruction system.cpu.commit.op_class_0::SimdCvt 0 0.00% 12.78% # Class of committed instruction system.cpu.commit.op_class_0::SimdMisc 32776 1.25% 14.03% # Class of committed instruction system.cpu.commit.op_class_0::SimdMult 0 0.00% 14.03% # Class of committed instruction system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 14.03% # Class of committed instruction system.cpu.commit.op_class_0::SimdShift 0 0.00% 14.03% # Class of committed instruction system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 14.03% # Class of committed instruction system.cpu.commit.op_class_0::SimdDiv 0 0.00% 14.03% # Class of committed instruction system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 14.03% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 14.03% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 14.03% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 14.03% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 14.03% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 14.03% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 14.03% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMult 32768 1.25% 15.29% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 15.29% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 15.29% # Class of committed instruction system.cpu.commit.op_class_0::SimdReduceAdd 0 0.00% 15.29% # Class of committed instruction system.cpu.commit.op_class_0::SimdReduceAlu 0 0.00% 15.29% # Class of committed instruction system.cpu.commit.op_class_0::SimdReduceCmp 0 0.00% 15.29% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatReduceAdd 32768 1.25% 16.54% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatReduceCmp 0 0.00% 16.54% # Class of committed instruction system.cpu.commit.op_class_0::SimdAes 0 0.00% 16.54% # Class of committed instruction system.cpu.commit.op_class_0::SimdAesMix 0 0.00% 16.54% # Class of committed instruction system.cpu.commit.op_class_0::SimdSha1Hash 0 0.00% 16.54% # Class of committed instruction system.cpu.commit.op_class_0::SimdSha1Hash2 0 0.00% 16.54% # Class of committed instruction system.cpu.commit.op_class_0::SimdSha256Hash 0 0.00% 16.54% # Class of committed instruction system.cpu.commit.op_class_0::SimdSha256Hash2 0 0.00% 16.54% # Class of committed instruction system.cpu.commit.op_class_0::SimdShaSigma2 0 0.00% 16.54% # Class of committed instruction system.cpu.commit.op_class_0::SimdShaSigma3 0 0.00% 16.54% # Class of committed instruction system.cpu.commit.op_class_0::SimdPredAlu 16385 0.63% 17.17% # Class of committed instruction system.cpu.commit.op_class_0::MemRead 2147169 82.16% 99.33% # Class of committed instruction system.cpu.commit.op_class_0::MemWrite 17560 0.67% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::total 2613428 # Class of committed instruction system.cpu.commit.refs 2164729 # Number of memory references committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.vec_insts 2293842 # Number of committed Vector instructions. system.cpu.committedInsts 498582 # Number of Instructions Simulated system.cpu.committedOps 2596898 # Number of Ops (including micro ops) Simulated system.cpu.cpi 13.896633 # CPI: Cycles Per Instruction system.cpu.cpi_total 13.896633 # CPI: Total CPI of All Threads system.cpu.decode.BlockedCycles 5763588 # Number of cycles decode is blocked system.cpu.decode.BranchMispred 158 # Number of times decode detected a branch misprediction system.cpu.decode.BranchResolved 33313 # Number of times decode resolved a branch system.cpu.decode.DecodedInsts 2619803 # Number of instructions handled by decode system.cpu.decode.IdleCycles 267942 # Number of cycles decode is idle system.cpu.decode.RunCycles 484389 # Number of cycles decode is running system.cpu.decode.SquashCycles 604 # Number of cycles decode is squashing system.cpu.decode.SquashedInsts 2144 # Number of squashed instructions handled by decode system.cpu.decode.UnblockCycles 391378 # Number of cycles decode is unblocking system.cpu.dtb.accesses 0 # DTB accesses system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.hits 0 # DTB hits system.cpu.dtb.inst_accesses 0 # ITB inst accesses system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.misses 0 # DTB misses system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.dtb.read_accesses 0 # DTB read accesses system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.dtb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.stage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dtb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu.dtb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dtb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dtb.stage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dtb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.dtb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.dtb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu.dtb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu.dtb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dtb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu.dtb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu.dtb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walks 0 # Table walker walks requested system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses system.cpu.fetch.Branches 68471 # Number of branches that fetch encountered system.cpu.fetch.CacheLines 152201 # Number of cache lines fetched system.cpu.fetch.Cycles 6746294 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.IcacheSquashes 336 # Number of outstanding Icache misses that were squashed system.cpu.fetch.Insts 522771 # Number of instructions fetch has processed system.cpu.fetch.SquashCycles 1508 # Number of cycles fetch has spent squashing system.cpu.fetch.branchRate 0.009882 # Number of branch fetches per cycle system.cpu.fetch.icacheStallCycles 160853 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.predictedBranches 33471 # Number of branches that fetch has predicted taken system.cpu.fetch.rate 0.075451 # Number of inst fetches per cycle system.cpu.fetch.rateDist::samples 6907901 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 0.380381 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 0.975144 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::0 5945838 86.07% 86.07% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::1 101234 1.47% 87.54% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 56086 0.81% 88.35% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 804743 11.65% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::total 6907901 # Number of instructions fetched each cycle (Total) system.cpu.idleCycles 20710 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.iew.branchMispredicts 612 # Number of branch mispredicts detected at execute system.cpu.iew.exec_branches 67370 # Number of branches executed system.cpu.iew.exec_nop 16637 # number of nop insts executed system.cpu.iew.exec_rate 0.378104 # Inst execution rate system.cpu.iew.exec_refs 2185816 # number of memory reference insts executed system.cpu.iew.exec_stores 17665 # Number of stores executed system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.iewBlockCycles 118 # Number of cycles IEW is blocking system.cpu.iew.iewDispLoadInsts 2147923 # Number of dispatched load instructions system.cpu.iew.iewDispNonSpecInsts 29 # Number of dispatched non-speculative instructions system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispStoreInsts 17826 # Number of dispatched store instructions system.cpu.iew.iewDispatchedInsts 2617307 # Number of instructions dispatched to IQ system.cpu.iew.iewExecLoadInsts 2168151 # Number of load instructions executed system.cpu.iew.iewExecSquashedInsts 763 # Number of squashed instructions skipped in execute system.cpu.iew.iewExecutedInsts 2619736 # Number of executed instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle system.cpu.iew.iewLSQFullEvents 893711 # Number of times the LSQ has become full, causing a stall system.cpu.iew.iewSquashCycles 604 # Number of cycles IEW is squashing system.cpu.iew.iewUnblockCycles 893710 # Number of cycles IEW is unblocking system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.cacheBlocked 1969 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.lsq.thread0.forwLoads 12 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.memOrderViolation 3 # Number of memory ordering violations system.cpu.iew.lsq.thread0.rescheduledLoads 4 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.squashedLoads 754 # Number of loads squashed system.cpu.iew.lsq.thread0.squashedStores 266 # Number of stores squashed system.cpu.iew.memOrderViolationEvents 3 # Number of memory order violations system.cpu.iew.predictedNotTakenIncorrect 480 # Number of branches that were predicted not taken incorrectly system.cpu.iew.predictedTakenIncorrect 132 # Number of branches that were predicted taken incorrectly system.cpu.iew.wb_consumers 872212 # num instructions consuming a value system.cpu.iew.wb_count 2598826 # cumulative count of insts written-back system.cpu.iew.wb_fanout 0.357932 # average fanout of values written-back system.cpu.iew.wb_producers 312193 # num instructions producing a value system.cpu.iew.wb_rate 0.375086 # insts written-back per cycle system.cpu.iew.wb_sent 2598903 # cumulative count of insts sent to commit system.cpu.int_regfile_reads 2556076 # number of integer regfile reads system.cpu.int_regfile_writes 187505 # number of integer regfile writes system.cpu.ipc 0.071960 # IPC: Instructions Per Cycle system.cpu.ipc_total 0.071960 # IPC: Total IPC of All Threads system.cpu.iq.FU_type_0::No_OpClass 2 0.00% 0.00% # Type of FU issued system.cpu.iq.FU_type_0::IntAlu 221277 8.44% 8.44% # Type of FU issued system.cpu.iq.FU_type_0::IntMult 5 0.00% 8.44% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 2 0.00% 8.44% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 8.44% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 8.44% # Type of FU issued system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 8.44% # Type of FU issued system.cpu.iq.FU_type_0::FloatMult 0 0.00% 8.44% # Type of FU issued system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 8.44% # Type of FU issued system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 8.44% # Type of FU issued system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 8.44% # Type of FU issued system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 8.44% # Type of FU issued system.cpu.iq.FU_type_0::SimdAdd 11 0.00% 8.44% # Type of FU issued system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 8.44% # Type of FU issued system.cpu.iq.FU_type_0::SimdAlu 65548 2.50% 10.95% # Type of FU issued system.cpu.iq.FU_type_0::SimdCmp 32777 1.25% 12.20% # Type of FU issued system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 12.20% # Type of FU issued system.cpu.iq.FU_type_0::SimdMisc 32776 1.25% 13.45% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 13.45% # Type of FU issued system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 13.45% # Type of FU issued system.cpu.iq.FU_type_0::SimdShift 0 0.00% 13.45% # Type of FU issued system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 13.45% # Type of FU issued system.cpu.iq.FU_type_0::SimdDiv 0 0.00% 13.45% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 13.45% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 13.45% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 13.45% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 13.45% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 13.45% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 13.45% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 13.45% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 32768 1.25% 14.70% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 14.70% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 14.70% # Type of FU issued system.cpu.iq.FU_type_0::SimdReduceAdd 0 0.00% 14.70% # Type of FU issued system.cpu.iq.FU_type_0::SimdReduceAlu 0 0.00% 14.70% # Type of FU issued system.cpu.iq.FU_type_0::SimdReduceCmp 0 0.00% 14.70% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatReduceAdd 32768 1.25% 15.95% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatReduceCmp 0 0.00% 15.95% # Type of FU issued system.cpu.iq.FU_type_0::SimdAes 0 0.00% 15.95% # Type of FU issued system.cpu.iq.FU_type_0::SimdAesMix 0 0.00% 15.95% # Type of FU issued system.cpu.iq.FU_type_0::SimdSha1Hash 0 0.00% 15.95% # Type of FU issued system.cpu.iq.FU_type_0::SimdSha1Hash2 0 0.00% 15.95% # Type of FU issued system.cpu.iq.FU_type_0::SimdSha256Hash 0 0.00% 15.95% # Type of FU issued system.cpu.iq.FU_type_0::SimdSha256Hash2 0 0.00% 15.95% # Type of FU issued system.cpu.iq.FU_type_0::SimdShaSigma2 0 0.00% 15.95% # Type of FU issued system.cpu.iq.FU_type_0::SimdShaSigma3 0 0.00% 15.95% # Type of FU issued system.cpu.iq.FU_type_0::SimdPredAlu 16501 0.63% 16.58% # Type of FU issued system.cpu.iq.FU_type_0::MemRead 2168355 82.75% 99.32% # Type of FU issued system.cpu.iq.FU_type_0::MemWrite 17709 0.68% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 2620499 # Type of FU issued system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu.iq.fu_busy_cnt 2051709 # FU busy when requested system.cpu.iq.fu_busy_rate 0.782946 # FU busy rate (busy events/executed inst) system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 39254 1.91% 1.91% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 1.91% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 1.91% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.91% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.91% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.91% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMult 0 0.00% 1.91% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 1.91% # attempts to use FU when none available system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.91% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMisc 0 0.00% 1.91% # attempts to use FU when none available system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.91% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.91% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.91% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAlu 2 0.00% 1.91% # attempts to use FU when none available system.cpu.iq.fu_full::SimdCmp 2 0.00% 1.91% # attempts to use FU when none available system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.91% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.91% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMult 0 0.00% 1.91% # attempts to use FU when none available system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.91% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShift 0 0.00% 1.91% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.91% # attempts to use FU when none available system.cpu.iq.fu_full::SimdDiv 0 0.00% 1.91% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.91% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.91% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.91% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.91% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.91% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.91% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.91% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.91% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.91% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.91% # attempts to use FU when none available system.cpu.iq.fu_full::SimdReduceAdd 0 0.00% 1.91% # attempts to use FU when none available system.cpu.iq.fu_full::SimdReduceAlu 0 0.00% 1.91% # attempts to use FU when none available system.cpu.iq.fu_full::SimdReduceCmp 0 0.00% 1.91% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatReduceAdd 0 0.00% 1.91% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatReduceCmp 0 0.00% 1.91% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAes 0 0.00% 1.91% # attempts to use FU when none available system.cpu.iq.fu_full::SimdAesMix 0 0.00% 1.91% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSha1Hash 0 0.00% 1.91% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSha1Hash2 0 0.00% 1.91% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSha256Hash 0 0.00% 1.91% # attempts to use FU when none available system.cpu.iq.fu_full::SimdSha256Hash2 0 0.00% 1.91% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShaSigma2 0 0.00% 1.91% # attempts to use FU when none available system.cpu.iq.fu_full::SimdShaSigma3 0 0.00% 1.91% # attempts to use FU when none available system.cpu.iq.fu_full::SimdPredAlu 0 0.00% 1.91% # attempts to use FU when none available system.cpu.iq.fu_full::MemRead 2011902 98.06% 99.97% # attempts to use FU when none available system.cpu.iq.fu_full::MemWrite 549 0.03% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.int_alu_accesses 345977 # Number of integer alu accesses system.cpu.iq.int_inst_queue_reads 7559977 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_wakeup_accesses 304984 # Number of integer instruction queue wakeup accesses system.cpu.iq.int_inst_queue_writes 310196 # Number of integer instruction queue writes system.cpu.iq.iqInstsAdded 2600641 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqInstsIssued 2620499 # Number of instructions issued system.cpu.iq.iqNonSpecInstsAdded 29 # Number of non-speculative instructions added to the IQ system.cpu.iq.iqSquashedInstsExamined 3771 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedInstsIssued 172 # Number of squashed instructions issued system.cpu.iq.iqSquashedNonSpecRemoved 6 # Number of squashed non-spec instructions that were removed system.cpu.iq.iqSquashedOperandsExamined 2396 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.issued_per_cycle::samples 6907901 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 0.379348 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::stdev 0.605250 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::0 4647177 67.27% 67.27% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::1 1980377 28.67% 95.94% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::2 213786 3.09% 99.04% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 53694 0.78% 99.81% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 12867 0.19% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 4 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::total 6907901 # Number of insts issued each cycle system.cpu.iq.rate 0.378214 # Inst issue rate system.cpu.iq.vec_alu_accesses 4326229 # Number of vector alu accesses system.cpu.iq.vec_inst_queue_reads 6640803 # Number of vector instruction queue reads system.cpu.iq.vec_inst_queue_wakeup_accesses 2293842 # Number of vector instruction queue wakeup accesses system.cpu.iq.vec_inst_queue_writes 2294248 # Number of vector instruction queue writes system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.hits 0 # DTB hits system.cpu.itb.inst_accesses 0 # ITB inst accesses system.cpu.itb.inst_hits 0 # ITB inst hits system.cpu.itb.inst_misses 0 # ITB inst misses system.cpu.itb.misses 0 # DTB misses system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.stage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu.itb.stage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.stage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.itb.stage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.stage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.stage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.itb.stage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses system.cpu.itb.stage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.itb.stage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.itb.stage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.itb.stage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.stage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.stage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses system.cpu.itb.stage2_mmu.stage2_tlb.read_hits 0 # DTB read hits system.cpu.itb.stage2_mmu.stage2_tlb.read_misses 0 # DTB read misses system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.stage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.itb.stage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses system.cpu.itb.stage2_mmu.stage2_tlb.write_hits 0 # DTB write hits system.cpu.itb.stage2_mmu.stage2_tlb.write_misses 0 # DTB write misses system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walks 0 # Table walker walks requested system.cpu.itb.write_accesses 0 # DTB write accesses system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.memDep0.conflictingLoads 0 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. system.cpu.memDep0.insertedLoads 2147923 # Number of loads inserted to the mem dependence unit. system.cpu.memDep0.insertedStores 17826 # Number of stores inserted to the mem dependence unit. system.cpu.misc_regfile_reads 7512110 # number of misc regfile reads system.cpu.misc_regfile_writes 65593 # number of misc regfile writes system.cpu.numCycles 6928611 # number of cpu cycles simulated system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.pred_regfile_reads 2331083 # number of predicate regfile reads system.cpu.pred_regfile_writes 2166518 # number of predicate regfile writes system.cpu.rename.BlockCycles 894063 # Number of cycles rename is blocking system.cpu.rename.CommittedMaps 4874340 # Number of HB maps that are committed system.cpu.rename.IdleCycles 492159 # Number of cycles rename is idle system.cpu.rename.LQFullEvents 4742483 # Number of times rename has blocked due to LQ full system.cpu.rename.ROBFullEvents 178 # Number of times rename has blocked due to ROB full system.cpu.rename.RenameLookups 12144667 # Number of register rename lookups that rename has made system.cpu.rename.RenamedInsts 2618118 # Number of instructions processed by rename system.cpu.rename.RenamedOperands 4879401 # Number of destination operands rename has renamed system.cpu.rename.RunCycles 648012 # Number of cycles rename is running system.cpu.rename.SQFullEvents 1532 # Number of times rename has blocked due to SQ full system.cpu.rename.SquashCycles 604 # Number of cycles rename is squashing system.cpu.rename.SquashedInsts 864 # Number of squashed instructions processed by rename system.cpu.rename.UnblockCycles 4870396 # Number of cycles rename is unblocking system.cpu.rename.UndoneMaps 5061 # Number of HB maps that are undone due to squashing system.cpu.rename.int_rename_lookups 2537456 # Number of integer rename lookups system.cpu.rename.serializeStallCycles 2667 # count of cycles rename stalled for serializing inst system.cpu.rename.serializingInsts 62 # count of serializing insts renamed system.cpu.rename.skidInsts 940824 # count of insts added to the skid buffer system.cpu.rename.tempSerializingInsts 30 # count of temporary serializing insts renamed system.cpu.rename.vec_pred_rename_lookups 2277986 # Number of vector predicate rename lookups system.cpu.rename.vec_rename_lookups 2310542 # Number of vector rename lookups system.cpu.rob.rob_reads 9405949 # The number of ROB reads system.cpu.rob.rob_writes 5233847 # The number of ROB writes system.cpu.timesIdled 249 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.vec_regfile_reads 2330341 # number of vector regfile reads system.cpu.vec_regfile_writes 2277415 # number of vector regfile writes system.cpu.workload.numSyscalls 8 # Number of system calls system.membus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.hit_single_requests 67655 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.tot_requests 136598 # Total number of requests made to the snoop filter. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.pwrStateResidencyTicks::UNDEFINED 3464305000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadResp 66885 # Transaction distribution system.membus.trans_dist::WritebackDirty 13391 # Transaction distribution system.membus.trans_dist::WritebackClean 40 # Transaction distribution system.membus.trans_dist::CleanEvict 54223 # Transaction distribution system.membus.trans_dist::ReadExReq 2051 # Transaction distribution system.membus.trans_dist::ReadExResp 2051 # Transaction distribution system.membus.trans_dist::ReadCleanReq 306 # Transaction distribution system.membus.trans_dist::ReadSharedReq 66580 # Transaction distribution system.membus.trans_dist::InvalidateReq 7 # Transaction distribution system.membus.pkt_count_system.cpu.icache.mem_side::system.mem_ctrls.port 651 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.dcache.mem_side::system.mem_ctrls.port 204883 # Packet count per connected master and slave (bytes) system.membus.pkt_count::total 205534 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.icache.mem_side::system.mem_ctrls.port 22080 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.dcache.mem_side::system.mem_ctrls.port 5249408 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size::total 5271488 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) system.membus.snoopTraffic 0 # Total snoop traffic (bytes) system.membus.snoop_fanout::samples 68944 # Request fanout histogram system.membus.snoop_fanout::mean 0.000029 # Request fanout histogram system.membus.snoop_fanout::stdev 0.005386 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 68942 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 2 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram system.membus.snoop_fanout::total 68944 # Request fanout histogram system.membus.reqLayer0.occupancy 204937000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 5.9 # Layer utilization (%) system.membus.respLayer1.occupancy 1622750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.0 # Layer utilization (%) system.membus.respLayer2.occupancy 358324500 # Layer occupancy (ticks) system.membus.respLayer2.utilization 10.3 # Layer utilization (%) system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.cpu_voltage_domain.voltage 1 # Voltage in Volts system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 3464305000 # Cumulative time (in ticks) in various power states system.mem_ctrls.bytes_read::.cpu.inst 19520 # Number of bytes read from this memory system.mem_ctrls.bytes_read::.cpu.data 4392384 # Number of bytes read from this memory system.mem_ctrls.bytes_read::total 4411904 # Number of bytes read from this memory system.mem_ctrls.bytes_inst_read::.cpu.inst 19520 # Number of instructions bytes read from this memory system.mem_ctrls.bytes_inst_read::total 19520 # Number of instructions bytes read from this memory system.mem_ctrls.bytes_written::.writebacks 857024 # Number of bytes written to this memory system.mem_ctrls.bytes_written::total 857024 # Number of bytes written to this memory system.mem_ctrls.num_reads::.cpu.inst 305 # Number of read requests responded to by this memory system.mem_ctrls.num_reads::.cpu.data 68631 # Number of read requests responded to by this memory system.mem_ctrls.num_reads::total 68936 # Number of read requests responded to by this memory system.mem_ctrls.num_writes::.writebacks 13391 # Number of write requests responded to by this memory system.mem_ctrls.num_writes::total 13391 # Number of write requests responded to by this memory system.mem_ctrls.bw_read::.cpu.inst 5634608 # Total read bandwidth from this memory (bytes/s) system.mem_ctrls.bw_read::.cpu.data 1267897601 # Total read bandwidth from this memory (bytes/s) system.mem_ctrls.bw_read::total 1273532209 # Total read bandwidth from this memory (bytes/s) system.mem_ctrls.bw_inst_read::.cpu.inst 5634608 # Instruction read bandwidth from this memory (bytes/s) system.mem_ctrls.bw_inst_read::total 5634608 # Instruction read bandwidth from this memory (bytes/s) system.mem_ctrls.bw_write::.writebacks 247386994 # Write bandwidth from this memory (bytes/s) system.mem_ctrls.bw_write::total 247386994 # Write bandwidth from this memory (bytes/s) system.mem_ctrls.bw_total::.writebacks 247386994 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.bw_total::.cpu.inst 5634608 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.bw_total::.cpu.data 1267897601 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.bw_total::total 1520919203 # Total bandwidth to/from this memory (bytes/s) system.mem_ctrls.avgPriority_.writebacks::samples 1177.00 # Average QoS priority value for accepted requests system.mem_ctrls.avgPriority_.cpu.inst::samples 304.00 # Average QoS priority value for accepted requests system.mem_ctrls.avgPriority_.cpu.data::samples 56374.00 # Average QoS priority value for accepted requests system.mem_ctrls.priorityMinLatency 0.000000018750 # per QoS priority minimum request to response latency (s) system.mem_ctrls.priorityMaxLatency 0.000249764250 # per QoS priority maximum request to response latency (s) system.mem_ctrls.numReadWriteTurnArounds 72 # Number of turnarounds from READ to WRITE system.mem_ctrls.numWriteReadTurnArounds 72 # Number of turnarounds from WRITE to READ system.mem_ctrls.numStayReadState 126564 # Number of times bus staying in READ state system.mem_ctrls.numStayWriteState 1089 # Number of times bus staying in WRITE state system.mem_ctrls.readReqs 68937 # Number of read requests accepted system.mem_ctrls.writeReqs 13431 # Number of write requests accepted system.mem_ctrls.readBursts 68937 # Number of DRAM read bursts, including those serviced by the write queue system.mem_ctrls.writeBursts 13431 # Number of DRAM write bursts, including those merged in the write queue system.mem_ctrls.servicedByWrQ 12259 # Number of DRAM read bursts serviced by the write queue system.mem_ctrls.mergedWrBursts 12254 # Number of DRAM write bursts merged with an existing one system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.mem_ctrls.perBankRdBursts::0 2532 # Per bank write bursts system.mem_ctrls.perBankRdBursts::1 2167 # Per bank write bursts system.mem_ctrls.perBankRdBursts::2 1954 # Per bank write bursts system.mem_ctrls.perBankRdBursts::3 2438 # Per bank write bursts system.mem_ctrls.perBankRdBursts::4 2487 # Per bank write bursts system.mem_ctrls.perBankRdBursts::5 2163 # Per bank write bursts system.mem_ctrls.perBankRdBursts::6 3858 # Per bank write bursts system.mem_ctrls.perBankRdBursts::7 4881 # Per bank write bursts system.mem_ctrls.perBankRdBursts::8 4981 # Per bank write bursts system.mem_ctrls.perBankRdBursts::9 4838 # Per bank write bursts system.mem_ctrls.perBankRdBursts::10 4867 # Per bank write bursts system.mem_ctrls.perBankRdBursts::11 5020 # Per bank write bursts system.mem_ctrls.perBankRdBursts::12 5042 # Per bank write bursts system.mem_ctrls.perBankRdBursts::13 4667 # Per bank write bursts system.mem_ctrls.perBankRdBursts::14 2346 # Per bank write bursts system.mem_ctrls.perBankRdBursts::15 2437 # Per bank write bursts system.mem_ctrls.perBankWrBursts::0 134 # Per bank write bursts system.mem_ctrls.perBankWrBursts::1 128 # Per bank write bursts system.mem_ctrls.perBankWrBursts::2 128 # Per bank write bursts system.mem_ctrls.perBankWrBursts::3 128 # Per bank write bursts system.mem_ctrls.perBankWrBursts::4 129 # Per bank write bursts system.mem_ctrls.perBankWrBursts::5 128 # Per bank write bursts system.mem_ctrls.perBankWrBursts::6 10 # Per bank write bursts system.mem_ctrls.perBankWrBursts::7 1 # Per bank write bursts system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts system.mem_ctrls.perBankWrBursts::9 2 # Per bank write bursts system.mem_ctrls.perBankWrBursts::10 9 # Per bank write bursts system.mem_ctrls.perBankWrBursts::11 50 # Per bank write bursts system.mem_ctrls.perBankWrBursts::12 34 # Per bank write bursts system.mem_ctrls.perBankWrBursts::13 13 # Per bank write bursts system.mem_ctrls.perBankWrBursts::14 132 # Per bank write bursts system.mem_ctrls.perBankWrBursts::15 128 # Per bank write bursts system.mem_ctrls.avgRdQLen 1.33 # Average read queue length when enqueuing system.mem_ctrls.avgWrQLen 25.35 # Average write queue length when enqueuing system.mem_ctrls.totQLat 367187750 # Total ticks spent queuing system.mem_ctrls.totBusLat 283390000 # Total ticks spent in databus transfers system.mem_ctrls.totMemAccLat 1429900250 # Total ticks spent from burst creation until serviced by the DRAM system.mem_ctrls.avgQLat 6478.49 # Average queueing delay per DRAM burst system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst system.mem_ctrls.avgMemAccLat 25228.49 # Average memory access latency per DRAM burst system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry system.mem_ctrls.readRowHits 50573 # Number of row buffer hits during reads system.mem_ctrls.writeRowHits 1053 # Number of row buffer hits during writes system.mem_ctrls.readRowHitRate 89.23 # Row buffer hit rate for reads system.mem_ctrls.writeRowHitRate 89.46 # Row buffer hit rate for writes system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) system.mem_ctrls.readPktSize::6 68937 # Read request sizes (log2) system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) system.mem_ctrls.writePktSize::6 13431 # Write request sizes (log2) system.mem_ctrls.rdQLenPdf::0 43134 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::1 11236 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::2 1836 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::3 464 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::4 7 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::5 1 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::15 2 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::16 2 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::17 69 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::18 71 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::19 73 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::20 73 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::21 73 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::22 74 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::23 73 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::24 73 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::25 73 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::26 72 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::27 72 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::28 73 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::29 73 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::30 72 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::31 72 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::32 72 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see system.mem_ctrls.bytesPerActivate::samples 6194 # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::mean 596.840814 # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::gmean 370.952000 # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::stdev 414.110055 # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::0-127 1576 25.44% 25.44% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::128-255 442 7.14% 32.58% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::256-383 391 6.31% 38.89% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::384-511 224 3.62% 42.51% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::512-639 239 3.86% 46.37% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::640-767 326 5.26% 51.63% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::768-895 285 4.60% 56.23% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::896-1023 344 5.55% 61.79% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::1024-1151 2367 38.21% 100.00% # Bytes accessed per row activation system.mem_ctrls.bytesPerActivate::total 6194 # Bytes accessed per row activation system.mem_ctrls.rdPerTurnAround::samples 72 # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::mean 787.055556 # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::gmean 726.488414 # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::stdev 220.733342 # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::128-159 2 2.78% 2.78% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::160-191 3 4.17% 6.94% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::192-223 1 1.39% 8.33% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::288-319 1 1.39% 9.72% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::320-351 1 1.39% 11.11% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::512-543 1 1.39% 12.50% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::736-767 1 1.39% 13.89% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::768-799 12 16.67% 30.56% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::800-831 3 4.17% 34.72% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::832-863 13 18.06% 52.78% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::864-895 4 5.56% 58.33% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::896-927 29 40.28% 98.61% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::992-1023 1 1.39% 100.00% # Reads before turning the bus around for writes system.mem_ctrls.rdPerTurnAround::total 72 # Reads before turning the bus around for writes system.mem_ctrls.wrPerTurnAround::samples 72 # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::mean 16.027778 # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::gmean 16.026195 # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::stdev 0.235702 # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::16 71 98.61% 98.61% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::18 1 1.39% 100.00% # Writes before turning the bus around for reads system.mem_ctrls.wrPerTurnAround::total 72 # Writes before turning the bus around for reads system.mem_ctrls.bytesReadDRAM 3627392 # Total number of bytes read from DRAM system.mem_ctrls.bytesReadWrQ 784576 # Total number of bytes read from write queue system.mem_ctrls.bytesWritten 73856 # Total number of bytes written to DRAM system.mem_ctrls.bytesReadSys 4411968 # Total read bytes from the system interface side system.mem_ctrls.bytesWrittenSys 859584 # Total written bytes from the system interface side system.mem_ctrls.avgRdBW 1047.08 # Average DRAM read bandwidth in MiByte/s system.mem_ctrls.avgWrBW 21.32 # Average achieved write bandwidth in MiByte/s system.mem_ctrls.avgRdBWSys 1273.55 # Average system read bandwidth in MiByte/s system.mem_ctrls.avgWrBWSys 248.13 # Average system write bandwidth in MiByte/s system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.mem_ctrls.busUtil 8.35 # Data bus utilization in percentage system.mem_ctrls.busUtilRead 8.18 # Data bus utilization in percentage for reads system.mem_ctrls.busUtilWrite 0.17 # Data bus utilization in percentage for writes system.mem_ctrls.totGap 3464301500 # Total gap between requests system.mem_ctrls.avgGap 42058.83 # Average gap between requests system.mem_ctrls.masterReadBytes::.cpu.inst 19456 # Per-master bytes read from memory system.mem_ctrls.masterReadBytes::.cpu.data 3607936 # Per-master bytes read from memory system.mem_ctrls.masterWriteBytes::.writebacks 73856 # Per-master bytes write to memory system.mem_ctrls.masterReadRate::.cpu.inst 5616133.683379494585 # Per-master bytes read from memory rate (Bytes/sec) system.mem_ctrls.masterReadRate::.cpu.data 1041460264.035643458366 # Per-master bytes read from memory rate (Bytes/sec) system.mem_ctrls.masterWriteRate::.writebacks 21319139.048091895878 # Per-master bytes write to memory rate (Bytes/sec) system.mem_ctrls.masterReadAccesses::.cpu.inst 306 # Per-master read serviced memory accesses system.mem_ctrls.masterReadAccesses::.cpu.data 68631 # Per-master read serviced memory accesses system.mem_ctrls.masterWriteAccesses::.writebacks 13431 # Per-master write serviced memory accesses system.mem_ctrls.masterReadTotalLat::.cpu.inst 8525500 # Per-master read total memory access latency system.mem_ctrls.masterReadTotalLat::.cpu.data 1421374750 # Per-master read total memory access latency system.mem_ctrls.masterWriteTotalLat::.writebacks 84264726000 # Per-master write total memory access latency system.mem_ctrls.masterReadAvgLat::.cpu.inst 27861.11 # Per-master read average memory access latency system.mem_ctrls.masterReadAvgLat::.cpu.data 20710.39 # Per-master read average memory access latency system.mem_ctrls.masterWriteAvgLat::.writebacks 6273898.15 # Per-master write average memory access latency system.mem_ctrls.pageHitRate 89.23 # Row buffer hit rate, read and write combined system.mem_ctrls.rank1.actEnergy 23333520 # Energy for activate commands per rank (pJ) system.mem_ctrls.rank1.preEnergy 12383085 # Energy for precharge commands per rank (pJ) system.mem_ctrls.rank1.readEnergy 244173720 # Energy for read commands per rank (pJ) system.mem_ctrls.rank1.writeEnergy 1920960 # Energy for write commands per rank (pJ) system.mem_ctrls.rank1.refreshEnergy 272900160.000000 # Energy for refresh commands per rank (pJ) system.mem_ctrls.rank1.actBackEnergy 1545381720 # Energy for active background per rank (pJ) system.mem_ctrls.rank1.preBackEnergy 28919040 # Energy for precharge background per rank (pJ) system.mem_ctrls.rank1.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) system.mem_ctrls.rank1.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) system.mem_ctrls.rank1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) system.mem_ctrls.rank1.totalEnergy 2129012205 # Total energy per rank (pJ) system.mem_ctrls.rank1.averagePower 614.556803 # Core power per rank (mW) system.mem_ctrls.rank1.totalIdleTime 0 # Total Idle time Per DRAM Rank system.mem_ctrls.rank1.memoryStateTime::IDLE 57870250 # Time in different power states system.mem_ctrls.rank1.memoryStateTime::REF 115440000 # Time in different power states system.mem_ctrls.rank1.memoryStateTime::SREF 0 # Time in different power states system.mem_ctrls.rank1.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrls.rank1.memoryStateTime::ACT 3290994750 # Time in different power states system.mem_ctrls.rank1.memoryStateTime::ACT_PDN 0 # Time in different power states system.mem_ctrls.rank0.actEnergy 20977320 # Energy for activate commands per rank (pJ) system.mem_ctrls.rank0.preEnergy 11123145 # Energy for precharge commands per rank (pJ) system.mem_ctrls.rank0.readEnergy 160507200 # Energy for read commands per rank (pJ) system.mem_ctrls.rank0.writeEnergy 4102920 # Energy for write commands per rank (pJ) system.mem_ctrls.rank0.refreshEnergy 272900160.000000 # Energy for refresh commands per rank (pJ) system.mem_ctrls.rank0.actBackEnergy 1527701460 # Energy for active background per rank (pJ) system.mem_ctrls.rank0.preBackEnergy 43807680 # Energy for precharge background per rank (pJ) system.mem_ctrls.rank0.actPowerDownEnergy 0 # Energy for active power-down per rank (pJ) system.mem_ctrls.rank0.prePowerDownEnergy 0 # Energy for precharge power-down per rank (pJ) system.mem_ctrls.rank0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) system.mem_ctrls.rank0.totalEnergy 2041119885 # Total energy per rank (pJ) system.mem_ctrls.rank0.averagePower 589.185965 # Core power per rank (mW) system.mem_ctrls.rank0.totalIdleTime 0 # Total Idle time Per DRAM Rank system.mem_ctrls.rank0.memoryStateTime::IDLE 84318000 # Time in different power states system.mem_ctrls.rank0.memoryStateTime::REF 115440000 # Time in different power states system.mem_ctrls.rank0.memoryStateTime::SREF 0 # Time in different power states system.mem_ctrls.rank0.memoryStateTime::PRE_PDN 0 # Time in different power states system.mem_ctrls.rank0.memoryStateTime::ACT 3264547000 # Time in different power states system.mem_ctrls.rank0.memoryStateTime::ACT_PDN 0 # Time in different power states system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.pwrStateResidencyTicks::ON 3464305000 # Cumulative time (in ticks) in various power states system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 3464305000 # Cumulative time (in ticks) in various power states system.cpu.icache.demand_hits::.cpu.inst 151795 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 151795 # number of demand (read+write) hits system.cpu.icache.overall_hits::.cpu.inst 151795 # number of overall hits system.cpu.icache.overall_hits::total 151795 # number of overall hits system.cpu.icache.demand_misses::.cpu.inst 406 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 406 # number of demand (read+write) misses system.cpu.icache.overall_misses::.cpu.inst 406 # number of overall misses system.cpu.icache.overall_misses::total 406 # number of overall misses system.cpu.icache.demand_miss_latency::.cpu.inst 22170500 # number of demand (read+write) miss cycles system.cpu.icache.demand_miss_latency::total 22170500 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::.cpu.inst 22170500 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 22170500 # number of overall miss cycles system.cpu.icache.demand_accesses::.cpu.inst 152201 # number of demand (read+write) accesses system.cpu.icache.demand_accesses::total 152201 # number of demand (read+write) accesses system.cpu.icache.overall_accesses::.cpu.inst 152201 # number of overall (read+write) accesses system.cpu.icache.overall_accesses::total 152201 # number of overall (read+write) accesses system.cpu.icache.demand_miss_rate::.cpu.inst 0.002668 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.002668 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::.cpu.inst 0.002668 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.002668 # miss rate for overall accesses system.cpu.icache.demand_avg_miss_latency::.cpu.inst 54607.142857 # average overall miss latency system.cpu.icache.demand_avg_miss_latency::total 54607.142857 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::.cpu.inst 54607.142857 # average overall miss latency system.cpu.icache.overall_avg_miss_latency::total 54607.142857 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.writebacks::.writebacks 40 # number of writebacks system.cpu.icache.writebacks::total 40 # number of writebacks system.cpu.icache.demand_mshr_hits::.cpu.inst 100 # number of demand (read+write) MSHR hits system.cpu.icache.demand_mshr_hits::total 100 # number of demand (read+write) MSHR hits system.cpu.icache.overall_mshr_hits::.cpu.inst 100 # number of overall MSHR hits system.cpu.icache.overall_mshr_hits::total 100 # number of overall MSHR hits system.cpu.icache.demand_mshr_misses::.cpu.inst 306 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 306 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::.cpu.inst 306 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 306 # number of overall MSHR misses system.cpu.icache.demand_mshr_miss_latency::.cpu.inst 18157000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.demand_mshr_miss_latency::total 18157000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::.cpu.inst 18157000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 18157000 # number of overall MSHR miss cycles system.cpu.icache.demand_mshr_miss_rate::.cpu.inst 0.002010 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.002010 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::.cpu.inst 0.002010 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.002010 # mshr miss rate for overall accesses system.cpu.icache.demand_avg_mshr_miss_latency::.cpu.inst 59336.601307 # average overall mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::total 59336.601307 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::.cpu.inst 59336.601307 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 59336.601307 # average overall mshr miss latency system.cpu.icache.replacements 40 # number of replacements system.cpu.icache.ReadReq_hits::.cpu.inst 151795 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 151795 # number of ReadReq hits system.cpu.icache.ReadReq_misses::.cpu.inst 406 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 406 # number of ReadReq misses system.cpu.icache.ReadReq_miss_latency::.cpu.inst 22170500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_miss_latency::total 22170500 # number of ReadReq miss cycles system.cpu.icache.ReadReq_accesses::.cpu.inst 152201 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 152201 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_miss_rate::.cpu.inst 0.002668 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.002668 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_avg_miss_latency::.cpu.inst 54607.142857 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 54607.142857 # average ReadReq miss latency system.cpu.icache.ReadReq_mshr_hits::.cpu.inst 100 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_hits::total 100 # number of ReadReq MSHR hits system.cpu.icache.ReadReq_mshr_misses::.cpu.inst 306 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 306 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_miss_latency::.cpu.inst 18157000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_latency::total 18157000 # number of ReadReq MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::.cpu.inst 0.002010 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.002010 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::.cpu.inst 59336.601307 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 59336.601307 # average ReadReq mshr miss latency system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 3464305000 # Cumulative time (in ticks) in various power states system.cpu.icache.tags.tagsinuse 241.413430 # Cycle average of tags in use system.cpu.icache.tags.total_refs 152100 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 305 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 498.688525 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 77000 # Cycle when the warmup percentage was hit. system.cpu.icache.tags.occ_blocks::.cpu.inst 241.413430 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::.cpu.inst 0.471511 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.471511 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 265 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 221 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.517578 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 304707 # Number of tag accesses system.cpu.icache.tags.data_accesses 304707 # Number of data accesses system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 3464305000 # Cumulative time (in ticks) in various power states system.cpu.dtb.stage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 3464305000 # Cumulative time (in ticks) in various power states system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 3464305000 # Cumulative time (in ticks) in various power states system.cpu.itb.stage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 3464305000 # Cumulative time (in ticks) in various power states system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 3464305000 # Cumulative time (in ticks) in various power states system.cpu.dcache.demand_hits::.cpu.data 2218662 # number of demand (read+write) hits system.cpu.dcache.demand_hits::total 2218662 # number of demand (read+write) hits system.cpu.dcache.overall_hits::.cpu.data 2218666 # number of overall hits system.cpu.dcache.overall_hits::total 2218666 # number of overall hits system.cpu.dcache.demand_misses::.cpu.data 77380 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 77380 # number of demand (read+write) misses system.cpu.dcache.overall_misses::.cpu.data 77382 # number of overall misses system.cpu.dcache.overall_misses::total 77382 # number of overall misses system.cpu.dcache.demand_miss_latency::.cpu.data 3726861966 # number of demand (read+write) miss cycles system.cpu.dcache.demand_miss_latency::total 3726861966 # number of demand (read+write) miss cycles system.cpu.dcache.overall_miss_latency::.cpu.data 3726861966 # number of overall miss cycles system.cpu.dcache.overall_miss_latency::total 3726861966 # number of overall miss cycles system.cpu.dcache.demand_accesses::.cpu.data 2296042 # number of demand (read+write) accesses system.cpu.dcache.demand_accesses::total 2296042 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::.cpu.data 2296048 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 2296048 # number of overall (read+write) accesses system.cpu.dcache.demand_miss_rate::.cpu.data 0.033701 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.033701 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::.cpu.data 0.033702 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.033702 # miss rate for overall accesses system.cpu.dcache.demand_avg_miss_latency::.cpu.data 48163.116645 # average overall miss latency system.cpu.dcache.demand_avg_miss_latency::total 48163.116645 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::.cpu.data 48161.871831 # average overall miss latency system.cpu.dcache.overall_avg_miss_latency::total 48161.871831 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 78450 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 1984 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.dcache.avg_blocked_cycles::no_mshrs 39.541331 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.writebacks::.writebacks 13391 # number of writebacks system.cpu.dcache.writebacks::total 13391 # number of writebacks system.cpu.dcache.demand_mshr_hits::.cpu.data 8746 # number of demand (read+write) MSHR hits system.cpu.dcache.demand_mshr_hits::total 8746 # number of demand (read+write) MSHR hits system.cpu.dcache.overall_mshr_hits::.cpu.data 8746 # number of overall MSHR hits system.cpu.dcache.overall_mshr_hits::total 8746 # number of overall MSHR hits system.cpu.dcache.demand_mshr_misses::.cpu.data 68634 # number of demand (read+write) MSHR misses system.cpu.dcache.demand_mshr_misses::total 68634 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::.cpu.data 68636 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 68636 # number of overall MSHR misses system.cpu.dcache.demand_mshr_miss_latency::.cpu.data 3472241967 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_latency::total 3472241967 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::.cpu.data 3472383967 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_latency::total 3472383967 # number of overall MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate::.cpu.data 0.029892 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.029892 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::.cpu.data 0.029893 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.029893 # mshr miss rate for overall accesses system.cpu.dcache.demand_avg_mshr_miss_latency::.cpu.data 50590.698007 # average overall mshr miss latency system.cpu.dcache.demand_avg_mshr_miss_latency::total 50590.698007 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::.cpu.data 50591.292718 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_miss_latency::total 50591.292718 # average overall mshr miss latency system.cpu.dcache.replacements 67614 # number of replacements system.cpu.dcache.ReadReq_hits::.cpu.data 2211855 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 2211855 # number of ReadReq hits system.cpu.dcache.ReadReq_misses::.cpu.data 66641 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 66641 # number of ReadReq misses system.cpu.dcache.ReadReq_miss_latency::.cpu.data 3490482000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_miss_latency::total 3490482000 # number of ReadReq miss cycles system.cpu.dcache.ReadReq_accesses::.cpu.data 2278496 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 2278496 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_miss_rate::.cpu.data 0.029248 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.029248 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_avg_miss_latency::.cpu.data 52377.395297 # average ReadReq miss latency system.cpu.dcache.ReadReq_avg_miss_latency::total 52377.395297 # average ReadReq miss latency system.cpu.dcache.ReadReq_mshr_hits::.cpu.data 65 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 65 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_misses::.cpu.data 66576 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 66576 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_miss_latency::.cpu.data 3420383000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_latency::total 3420383000 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::.cpu.data 0.029219 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.029219 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_avg_mshr_miss_latency::.cpu.data 51375.615838 # average ReadReq mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51375.615838 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_hits::.cpu.data 6807 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 6807 # number of WriteReq hits system.cpu.dcache.WriteReq_misses::.cpu.data 10732 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 10732 # number of WriteReq misses system.cpu.dcache.WriteReq_miss_latency::.cpu.data 236306966 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 236306966 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_accesses::.cpu.data 17539 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 17539 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_miss_rate::.cpu.data 0.611893 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.611893 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_avg_miss_latency::.cpu.data 22018.912225 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 22018.912225 # average WriteReq miss latency system.cpu.dcache.WriteReq_mshr_hits::.cpu.data 8681 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 8681 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_misses::.cpu.data 2051 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 2051 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_miss_latency::.cpu.data 51792967 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 51792967 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate::.cpu.data 0.116939 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.116939 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_avg_mshr_miss_latency::.cpu.data 25252.543637 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 25252.543637 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_hits::.cpu.data 4 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_hits::total 4 # number of SoftPFReq hits system.cpu.dcache.SoftPFReq_misses::.cpu.data 2 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_misses::total 2 # number of SoftPFReq misses system.cpu.dcache.SoftPFReq_accesses::.cpu.data 6 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_accesses::total 6 # number of SoftPFReq accesses(hits+misses) system.cpu.dcache.SoftPFReq_miss_rate::.cpu.data 0.333333 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_miss_rate::total 0.333333 # miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_misses::.cpu.data 2 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_misses::total 2 # number of SoftPFReq MSHR misses system.cpu.dcache.SoftPFReq_mshr_miss_latency::.cpu.data 142000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 142000 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_rate::.cpu.data 0.333333 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.333333 # mshr miss rate for SoftPFReq accesses system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::.cpu.data 71000 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 71000 # average SoftPFReq mshr miss latency system.cpu.dcache.WriteLineReq_misses::.cpu.data 7 # number of WriteLineReq misses system.cpu.dcache.WriteLineReq_misses::total 7 # number of WriteLineReq misses system.cpu.dcache.WriteLineReq_miss_latency::.cpu.data 73000 # number of WriteLineReq miss cycles system.cpu.dcache.WriteLineReq_miss_latency::total 73000 # number of WriteLineReq miss cycles system.cpu.dcache.WriteLineReq_accesses::.cpu.data 7 # number of WriteLineReq accesses(hits+misses) system.cpu.dcache.WriteLineReq_accesses::total 7 # number of WriteLineReq accesses(hits+misses) system.cpu.dcache.WriteLineReq_miss_rate::.cpu.data 1 # miss rate for WriteLineReq accesses system.cpu.dcache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.cpu.dcache.WriteLineReq_avg_miss_latency::.cpu.data 10428.571429 # average WriteLineReq miss latency system.cpu.dcache.WriteLineReq_avg_miss_latency::total 10428.571429 # average WriteLineReq miss latency system.cpu.dcache.WriteLineReq_mshr_misses::.cpu.data 7 # number of WriteLineReq MSHR misses system.cpu.dcache.WriteLineReq_mshr_misses::total 7 # number of WriteLineReq MSHR misses system.cpu.dcache.WriteLineReq_mshr_miss_latency::.cpu.data 66000 # number of WriteLineReq MSHR miss cycles system.cpu.dcache.WriteLineReq_mshr_miss_latency::total 66000 # number of WriteLineReq MSHR miss cycles system.cpu.dcache.WriteLineReq_mshr_miss_rate::.cpu.data 1 # mshr miss rate for WriteLineReq accesses system.cpu.dcache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::.cpu.data 9428.571429 # average WriteLineReq mshr miss latency system.cpu.dcache.WriteLineReq_avg_mshr_miss_latency::total 9428.571429 # average WriteLineReq mshr miss latency system.cpu.dcache.LoadLockedReq_hits::.cpu.data 15 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 15 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_misses::.cpu.data 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 3 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_miss_latency::.cpu.data 189000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 189000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_accesses::.cpu.data 18 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 18 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_miss_rate::.cpu.data 0.166667 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_avg_miss_latency::.cpu.data 63000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 63000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_mshr_hits::.cpu.data 1 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_misses::.cpu.data 2 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 2 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_miss_latency::.cpu.data 134500 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 134500 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_rate::.cpu.data 0.111111 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.111111 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::.cpu.data 67250 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 67250 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_hits::.cpu.data 14 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 14 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_accesses::.cpu.data 14 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 14 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 3464305000 # Cumulative time (in ticks) in various power states system.cpu.dcache.tags.tagsinuse 1015.405115 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 2287333 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 68638 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 33.324587 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 152000 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::.cpu.data 1015.405115 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::.cpu.data 0.991607 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.991607 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 1024 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 49 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 72 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 499 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::3 404 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu.dcache.tags.tag_accesses 4660798 # Number of tag accesses system.cpu.dcache.tags.data_accesses 4660798 # Number of data accesses ---------- End Simulation Statistics ----------